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-rw-r--r--arch/arm/mach-mx5/Kconfig1
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c14
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c3
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h4
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c12
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h10
6 files changed, 39 insertions, 5 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 23b0e3f5cad7..777740b9ffdd 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -126,6 +126,7 @@ config MACH_MX53_EVK
126 select IMX_HAVE_PLATFORM_IMX_UART 126 select IMX_HAVE_PLATFORM_IMX_UART
127 select IMX_HAVE_PLATFORM_IMX_I2C 127 select IMX_HAVE_PLATFORM_IMX_I2C
128 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 128 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
129 select IMX_HAVE_PLATFORM_SPI_IMX
129 help 130 help
130 Include support for MX53 EVK platform. This includes specific 131 Include support for MX53 EVK platform. This includes specific
131 configurations for the board and its peripherals. 132 configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 4043451798db..8017d680f112 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -33,6 +33,8 @@
33#include <mach/iomux-mx53.h> 33#include <mach/iomux-mx53.h>
34 34
35#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) 35#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
36#define EVK_ECSPI1_CS0 IMX_GPIO_NR(3, 19)
37#define EVK_ECSPI1_CS1 IMX_GPIO_NR(2, 30)
36 38
37#include "crm_regs.h" 39#include "crm_regs.h"
38#include "devices-imx53.h" 40#include "devices-imx53.h"
@@ -89,6 +91,16 @@ static struct fec_platform_data mx53_evk_fec_pdata = {
89 .phy = PHY_INTERFACE_MODE_RMII, 91 .phy = PHY_INTERFACE_MODE_RMII,
90}; 92};
91 93
94static int mx53_evk_spi_cs[] = {
95 EVK_ECSPI1_CS0,
96 EVK_ECSPI1_CS1,
97};
98
99static const struct spi_imx_master mx53_evk_spi_data __initconst = {
100 .chipselect = mx53_evk_spi_cs,
101 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
102};
103
92static void __init mx53_evk_board_init(void) 104static void __init mx53_evk_board_init(void)
93{ 105{
94 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, 106 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
@@ -102,6 +114,8 @@ static void __init mx53_evk_board_init(void)
102 114
103 imx53_add_sdhci_esdhc_imx(0, NULL); 115 imx53_add_sdhci_esdhc_imx(0, NULL);
104 imx53_add_sdhci_esdhc_imx(1, NULL); 116 imx53_add_sdhci_esdhc_imx(1, NULL);
117
118 imx53_add_ecspi(0, &mx53_evk_spi_data);
105} 119}
106 120
107static void __init mx53_evk_timer_init(void) 121static void __init mx53_evk_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 15fa89ed5d0c..64fe24900a4d 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1330,6 +1330,9 @@ static struct clk_lookup mx53_lookups[] = {
1330 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) 1330 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1331 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 1331 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1332 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) 1332 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1333 _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
1334 _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
1335 _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
1333}; 1336};
1334 1337
1335static void clk_tree_init(void) 1338static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index f7c89ef2f667..8639735a117b 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -25,3 +25,7 @@ extern const struct imx_sdhci_esdhc_imx_data
25imx53_sdhci_esdhc_imx_data[] __initconst; 25imx53_sdhci_esdhc_imx_data[] __initconst;
26#define imx53_add_sdhci_esdhc_imx(id, pdata) \ 26#define imx53_add_sdhci_esdhc_imx(id, pdata) \
27 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata) 27 imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
28
29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
30#define imx53_add_ecspi(id, pdata) \
31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 8ea49adcdfc1..013c85f20b58 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -81,6 +81,18 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
81}; 81};
82#endif /* ifdef CONFIG_SOC_IMX51 */ 82#endif /* ifdef CONFIG_SOC_IMX51 */
83 83
84#ifdef CONFIG_SOC_IMX53
85const struct imx_spi_imx_data imx53_cspi_data __initconst =
86 imx_spi_imx_data_entry_single(MX53, CSPI, "imx53-cspi", 0, , SZ_4K);
87
88const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
89#define imx53_ecspi_data_entry(_id, _hwid) \
90 imx_spi_imx_data_entry(MX53, ECSPI, "imx53-ecspi", _id, _hwid, SZ_4K)
91 imx53_ecspi_data_entry(0, 1),
92 imx53_ecspi_data_entry(1, 2),
93};
94#endif /* ifdef CONFIG_SOC_IMX53 */
95
84struct platform_device *__init imx_add_spi_imx( 96struct platform_device *__init imx_add_spi_imx(
85 const struct imx_spi_imx_data *data, 97 const struct imx_spi_imx_data *data,
86 const struct spi_imx_master *pdata) 98 const struct spi_imx_master *pdata)
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 340937f94e6f..d7a8e52181ea 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -56,7 +56,7 @@
56#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) 56#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
57#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) 57#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
58#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) 58#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
59#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) 59#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
60#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) 60#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
61#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) 61#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
62#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) 62#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
@@ -117,12 +117,12 @@
117#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) 117#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
118#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) 118#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
119#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) 119#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
120#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) 120#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
121#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) 121#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
122#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) 122#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
123#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) 123#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
124#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) 124#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
125#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) 125#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
126#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) 126#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
127#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) 127#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
128#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) 128#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
@@ -264,8 +264,8 @@
264#define MX53_INT_UART3 33 264#define MX53_INT_UART3 33
265#define MX53_INT_RESV34 34 265#define MX53_INT_RESV34 34
266#define MX53_INT_RESV35 35 266#define MX53_INT_RESV35 35
267#define MX53_INT_CSPI1 36 267#define MX53_INT_ECSPI1 36
268#define MX53_INT_CSPI2 37 268#define MX53_INT_ECSPI2 37
269#define MX53_INT_CSPI 38 269#define MX53_INT_CSPI 38
270#define MX53_INT_GPT 39 270#define MX53_INT_GPT 39
271#define MX53_INT_EPIT1 40 271#define MX53_INT_EPIT1 40