diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx53.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx53.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 340937f94e6f..d7a8e52181ea 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h | |||
| @@ -56,7 +56,7 @@ | |||
| 56 | #define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) | 56 | #define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) |
| 57 | #define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) | 57 | #define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) |
| 58 | #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) | 58 | #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) |
| 59 | #define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) | 59 | #define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) |
| 60 | #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) | 60 | #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) |
| 61 | #define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) | 61 | #define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) |
| 62 | #define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) | 62 | #define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) |
| @@ -117,12 +117,12 @@ | |||
| 117 | #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) | 117 | #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) |
| 118 | #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) | 118 | #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) |
| 119 | #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) | 119 | #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) |
| 120 | #define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) | 120 | #define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) |
| 121 | #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) | 121 | #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) |
| 122 | #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) | 122 | #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) |
| 123 | #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) | 123 | #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) |
| 124 | #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) | 124 | #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) |
| 125 | #define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) | 125 | #define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) |
| 126 | #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) | 126 | #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) |
| 127 | #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) | 127 | #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) |
| 128 | #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) | 128 | #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) |
| @@ -264,8 +264,8 @@ | |||
| 264 | #define MX53_INT_UART3 33 | 264 | #define MX53_INT_UART3 33 |
| 265 | #define MX53_INT_RESV34 34 | 265 | #define MX53_INT_RESV34 34 |
| 266 | #define MX53_INT_RESV35 35 | 266 | #define MX53_INT_RESV35 35 |
| 267 | #define MX53_INT_CSPI1 36 | 267 | #define MX53_INT_ECSPI1 36 |
| 268 | #define MX53_INT_CSPI2 37 | 268 | #define MX53_INT_ECSPI2 37 |
| 269 | #define MX53_INT_CSPI 38 | 269 | #define MX53_INT_CSPI 38 |
| 270 | #define MX53_INT_GPT 39 | 270 | #define MX53_INT_GPT 39 |
| 271 | #define MX53_INT_EPIT1 40 | 271 | #define MX53_INT_EPIT1 40 |