172 files changed, 3147 insertions, 7799 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 62079d434581..1e31dac36a5f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -689,12 +689,15 @@ config ARCH_SA1100
 config ARCH_S3C24XX
         bool "Samsung S3C24XX SoCs"
         select ARCH_HAS_CPUFREQ
-        select ARCH_USES_GETTIMEOFFSET
+        select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
+        select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         help
@@ -707,10 +710,11 @@ config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
-        select ARCH_USES_GETTIMEOFFSET
         select ARM_VIC
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V6
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -744,9 +748,11 @@ config ARCH_S5P64X0
 
 config ARCH_S5PC100
         bool "Samsung S5PC100"
-        select ARCH_USES_GETTIMEOFFSET
+        select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V7
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -779,6 +785,7 @@ config ARCH_EXYNOS
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_SPARSEMEM_ENABLE
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
@@ -1552,7 +1559,8 @@ config ARCH_NR_GPIO
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 512 if SOC_OMAP5
         default 392 if ARCH_U8500
-        default 288 if ARCH_VT8500 || ARCH_SUNXI
+        default 352 if ARCH_VT8500
+        default 288 if ARCH_SUNXI
         default 264 if MACH_H4700
         default 0
         help
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 20358fb43450..55196639211d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -49,7 +49,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
+        exynos4412-odroidx.dtb \
         exynos4412-smdk4412.dtb \
+        exynos4412-origen.dtb \
+        exynos5250-arndale.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
         exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 46c098017036..62eceb4f0d3f 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -24,6 +24,144 @@
                 samsung,i2c-max-bus-freq = <378000>;
                 gpios = <&gpb3 0 2 3 0>,
                         <&gpb3 1 2 3 0>;
+
+                max77686@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "P1.0V_LDO_OUT1";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "P1.8V_LDO_OUT2";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "P1.8V_LDO_OUT3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "P1.1V_LDO_OUT7";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "P1.0V_LDO_OUT8";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "P1.8V_LDO_OUT10";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "P3.0V_LDO_OUT12";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "P1.8V_LDO_OUT14";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "P1.0V_LDO_OUT15";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "P1.8V_LDO_OUT16";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "P1.8V_BUCK_OUT5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "P1.35V_BUCK_OUT6";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "P2.0V_BUCK_OUT7";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "P2.85V_BUCK_OUT8";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
         };
 
         i2c@12C70000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1a62bcf18aa3..9ac47d51c407 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -86,6 +86,8 @@
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 43 0>;
+                clocks = <&clock 345>;
+                clock-names = "watchdog";
                 status = "disabled";
         };
 
@@ -93,6 +95,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x10070000 0x100>;
                 interrupts = <0 44 0>, <0 45 0>;
+                clocks = <&clock 346>;
+                clock-names = "rtc";
                 status = "disabled";
         };
 
@@ -100,6 +104,8 @@
                 compatible = "samsung,s5pv210-keypad";
                 reg = <0x100A0000 0x100>;
                 interrupts = <0 109 0>;
+                clocks = <&clock 347>;
+                clock-names = "keypad";
                 status = "disabled";
         };
 
@@ -107,6 +113,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12510000 0x100>;
                 interrupts = <0 73 0>;
+                clocks = <&clock 297>, <&clock 145>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -114,6 +122,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12520000 0x100>;
                 interrupts = <0 74 0>;
+                clocks = <&clock 298>, <&clock 146>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -121,6 +131,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12530000 0x100>;
                 interrupts = <0 75 0>;
+                clocks = <&clock 299>, <&clock 147>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -128,6 +140,16 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12540000 0x100>;
                 interrupts = <0 76 0>;
+                clocks = <&clock 300>, <&clock 148>;
+                clock-names = "hsmmc", "mmc_busclk.2";
+                status = "disabled";
+        };
+
+        mfc: codec@13400000 {
+                compatible = "samsung,mfc-v5";
+                reg = <0x13400000 0x10000>;
+                interrupts = <0 94 0>;
+                samsung,power-domain = <&pd_mfc>;
                 status = "disabled";
         };
 
@@ -135,6 +157,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13800000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 312>, <&clock 151>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -142,6 +166,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13810000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 313>, <&clock 152>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -149,6 +175,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13820000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -156,6 +184,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13830000 0x100>;
                 interrupts = <0 55 0>;
+                clocks = <&clock 315>, <&clock 154>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -165,6 +195,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13860000 0x100>;
                 interrupts = <0 58 0>;
+                clocks = <&clock 317>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -174,6 +206,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13870000 0x100>;
                 interrupts = <0 59 0>;
+                clocks = <&clock 318>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -183,6 +217,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13880000 0x100>;
                 interrupts = <0 60 0>;
+                clocks = <&clock 319>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -192,6 +228,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13890000 0x100>;
                 interrupts = <0 61 0>;
+                clocks = <&clock 320>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -201,6 +239,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138A0000 0x100>;
                 interrupts = <0 62 0>;
+                clocks = <&clock 321>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -210,6 +250,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138B0000 0x100>;
                 interrupts = <0 63 0>;
+                clocks = <&clock 322>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -219,6 +261,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138C0000 0x100>;
                 interrupts = <0 64 0>;
+                clocks = <&clock 323>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -228,6 +272,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138D0000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 324>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -239,6 +285,8 @@
                 rx-dma-channel = <&pdma0 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 327>, <&clock 159>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -250,6 +298,8 @@
                 rx-dma-channel = <&pdma1 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 328>, <&clock 160>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -261,6 +311,8 @@
                 rx-dma-channel = <&pdma0 8>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 329>, <&clock 161>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -275,6 +327,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12680000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 292>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -284,6 +338,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12690000 0x1000>;
                         interrupts = <0 36 0>;
+                        clocks = <&clock 293>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -293,6 +349,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12850000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 279>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f2710018e84e..1b30bc8e2654 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -121,4 +127,16 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f63490707f3a..f52c86e2d424 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -189,4 +195,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <12000000>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index c346b64dff55..9a14484c7bb1 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,4 +289,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2feffc70814c..15143bdbafb8 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,42 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &gic 0 69 0>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 0 42 0>,
+                                        <0x5 0 &gic 0 48 0>;
+                };
+        };
+
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4210-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <2 2>, <3 2>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4210-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae2005961f..36d4299789ef 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,26 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 000000000000..53bc8bf77984
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,111 @@
+/*
+ * Hardkernel's Exynos4412 based ODROID-X board device tree source
+ *
+ * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
+ *
+ * Device tree source file for Hardkernel's ODROID-X board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Hardkernel ODROID-X board based on Exynos4412";
+        compatible = "hardkernel,odroid-x", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        label = "led1:heart";
+                        gpios = <&gpc1 0 1>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led2 {
+                        label = "led2:mmc0";
+                        gpios = <&gpc1 2 1>;
+                        default-state = "on";
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        regulator_p3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "p3v3_en";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpa1 1 1>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        rtc@10070000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
new file mode 100644
index 000000000000..1fecf7666dc0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -0,0 +1,432 @@
+/*
+ * Insignal's Exynos4412 based Origen board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Insignal Origen evaluation board based on Exynos4412";
+        compatible = "insignal,origen4412", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs ="console=ttySAC2,115200";
+        };
+
+        mmc_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpx1 1 0>;
+                enable-active-high;
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                vmmc-supply = <&mmc_reg>;
+                status = "okay";
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                s5m8767_pmic@66 {
+                        compatible = "samsung,s5m8767-pmic";
+                        reg = <0x66>;
+
+                        s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+                        s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
+                                                         <&gpx2 4 0>,
+                                                         <&gpx2 5 0>;
+
+                        s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
+                                                        <&gpm3 6 0>,
+                                                        <&gpm3 7 0>;
+
+                        s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>;
+
+                        s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDIOAP_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_PRE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDD18_2M";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VDD10_MIPI";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VDD33_LCD";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD18_MIPI";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_UOTG";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDIOPERI_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB02";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_USH";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDDIOAP_MMC012_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo18_reg: LDO18 {
+                                        regulator-name = "VDDIOPERI_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo19_reg: LDO19 {
+                                        regulator-name = "DVDD25";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "VDD28_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD28_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo22_reg: LDO22 {
+                                        regulator-name = "VDDA28_2M";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo23_reg: LDO23 {
+                                        regulator-name = "VDD28_TF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo24_reg: LDO24 {
+                                        regulator-name = "VDD33_A31";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDD18_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo26_reg: LDO26 {
+                                        regulator-name = "VDD18_A31";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo27_reg: LDO27 {
+                                        regulator-name = "GPS_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo28_reg: LDO28 {
+                                        regulator-name = "DVDD12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <925000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "vdd_m12";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "vdd12_5m";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "vddf28_emmc";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+                        };
+                };
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf575cc45..874beeaef99d 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,6 +27,19 @@
                 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
         };
 
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -42,4 +55,16 @@
         serial@13830000 {
                 status = "okay";
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe312772a..d75c047e80a9 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,30 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>, <6 0>, <7 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>,
+                                        <0x6 0 &gic 1 12 0>,
+                                        <0x7 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 9a8780694909..7496b8d633ea 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
                              <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
         };
 
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4412-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4x12-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
new file mode 100644
index 000000000000..5de019cb0e58
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -0,0 +1,129 @@
+/*
+ * Samsung's Exynos5250 based Arndale board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+        model = "Insignal Arndale evaluation board based on EXYNOS5250";
+        compatible = "insignal,arndale", "samsung,exynos5250";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200";
+        };
+
+        i2c@12C60000 {
+                status = "disabled";
+        };
+
+        i2c@12C70000 {
+                status = "disabled";
+        };
+
+        i2c@12C80000 {
+                status = "disabled";
+        };
+
+        i2c@12C90000 {
+                status = "disabled";
+        };
+
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+
+        i2c@12CB0000 {
+                status = "disabled";
+        };
+
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+
+        i2c@12CD0000 {
+                status = "disabled";
+        };
+
+        i2c@121D0000 {
+                status = "disabled";
+        };
+
+        dwmmc_0: dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
+                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
+                };
+        };
+
+        dwmmc_1: dwmmc1@12210000 {
+                status = "disabled";
+        };
+
+        dwmmc_2: dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
+                };
+        };
+
+        dwmmc_3: dwmmc3@12230000 {
+                status = "disabled";
+        };
+
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1b8d4106d338..872ae1f93c75 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -231,4 +231,24 @@
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&wm8994>;
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+        };
+
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 17dd951c1cd2..babd9f9b1bf9 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -40,4 +40,15 @@
                                 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
                 };
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx1 1 1 3 3>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b1ac73e21c80..28758e5dd15c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,22 @@
                 i2c8 = &i2c_8;
         };
 
+        pd_gsc: gsc-power-domain@0x10044000 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044000 0x20>;
+        };
+
+        pd_mfc: mfc-power-domain@0x10044040 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044040 0x20>;
+        };
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5250-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -69,58 +85,106 @@
                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 1>, <&clock 335>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x1 0 &combiner 23 4>,
+                                        <0x2 0 &combiner 25 2>,
+                                        <0x3 0 &combiner 25 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <1 2>, <22 4>;
+        };
+
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
                 interrupts = <0 42 0>;
+                clocks = <&clock 336>;
+                clock-names = "watchdog";
         };
 
         codec@11000000 {
                 compatible = "samsung,mfc-v6";
                 reg = <0x11000000 0x10000>;
                 interrupts = <0 96 0>;
+                samsung,power-domain = <&pd_mfc>;
         };
 
         rtc {
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x101E0000 0x100>;
                 interrupts = <0 43 0>, <0 44 0>;
+                clocks = <&clock 337>;
+                clock-names = "rtc";
+                status = "disabled";
         };
 
         tmu@10060000 {
                 compatible = "samsung,exynos5250-tmu";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 338>;
+                clock-names = "tmu_apbif";
         };
 
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
                 interrupts = <0 51 0>;
+                clocks = <&clock 289>, <&clock 146>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C10000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C10000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 290>, <&clock 147>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C20000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C20000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 291>, <&clock 148>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C30000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C30000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 292>, <&clock 149>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         sata@122F0000 {
                 compatible = "samsung,exynos5-sata-ahci";
                 reg = <0x122F0000 0x1ff>;
                 interrupts = <0 115 0>;
+                clocks = <&clock 277>, <&clock 143>;
+                clock-names = "sata", "sclk_sata";
         };
 
         sata-phy@12170000 {
@@ -134,6 +198,8 @@
                 interrupts = <0 56 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 294>;
+                clock-names = "i2c";
         };
 
         i2c_1: i2c@12C70000 {
@@ -142,6 +208,8 @@
                 interrupts = <0 57 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 295>;
+                clock-names = "i2c";
         };
 
         i2c_2: i2c@12C80000 {
@@ -150,6 +218,8 @@
                 interrupts = <0 58 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 296>;
+                clock-names = "i2c";
         };
 
         i2c_3: i2c@12C90000 {
@@ -158,6 +228,8 @@
                 interrupts = <0 59 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 297>;
+                clock-names = "i2c";
         };
 
         i2c_4: i2c@12CA0000 {
@@ -166,6 +238,8 @@
                 interrupts = <0 60 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 298>;
+                clock-names = "i2c";
         };
 
         i2c_5: i2c@12CB0000 {
@@ -174,6 +248,8 @@
                 interrupts = <0 61 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 299>;
+                clock-names = "i2c";
         };
 
         i2c_6: i2c@12CC0000 {
@@ -182,6 +258,8 @@
                 interrupts = <0 62 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 300>;
+                clock-names = "i2c";
         };
 
         i2c_7: i2c@12CD0000 {
@@ -190,6 +268,8 @@
                 interrupts = <0 63 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 301>;
+                clock-names = "i2c";
         };
 
         i2c_8: i2c@12CE0000 {
@@ -198,6 +278,8 @@
                 interrupts = <0 64 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 302>;
+                clock-names = "i2c";
         };
 
         i2c@121D0000 {
@@ -205,6 +287,8 @@
                 reg = <0x121D0000 0x100>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 288>;
+                clock-names = "i2c";
         };
 
         spi_0: spi@12d20000 {
@@ -216,6 +300,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 304>, <&clock 154>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_1: spi@12d30000 {
@@ -227,6 +313,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 305>, <&clock 155>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_2: spi@12d40000 {
@@ -238,6 +326,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 306>, <&clock 156>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         dwmmc_0: dwmmc0@12200000 {
@@ -246,6 +336,8 @@
                 interrupts = <0 75 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 280>, <&clock 139>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_1: dwmmc1@12210000 {
@@ -254,6 +346,8 @@
                 interrupts = <0 76 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 281>, <&clock 140>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_2: dwmmc2@12220000 {
@@ -262,6 +356,8 @@
                 interrupts = <0 77 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 282>, <&clock 141>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_3: dwmmc3@12230000 {
@@ -270,6 +366,8 @@
                 interrupts = <0 78 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 283>, <&clock 142>;
+                clock-names = "biu", "ciu";
         };
 
         i2s0: i2s@03830000 {
@@ -301,6 +399,18 @@
                 dma-names = "tx", "rx";
         };
 
+        usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
+        usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -312,6 +422,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121A0000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 275>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -321,6 +433,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121B0000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 276>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -330,6 +444,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -339,6 +455,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -592,34 +710,51 @@
                 };
         };
 
+
         gsc_0:  gsc@0x13e00000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e00000 0x1000>;
                 interrupts = <0 85 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 256>;
+                clock-names = "gscl";
         };
 
         gsc_1:  gsc@0x13e10000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e10000 0x1000>;
                 interrupts = <0 86 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 257>;
+                clock-names = "gscl";
         };
 
         gsc_2:  gsc@0x13e20000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e20000 0x1000>;
                 interrupts = <0 87 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 258>;
+                clock-names = "gscl";
         };
 
         gsc_3:  gsc@0x13e30000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e30000 0x1000>;
                 interrupts = <0 88 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 259>;
+                clock-names = "gscl";
         };
 
         hdmi {
                 compatible = "samsung,exynos5-hdmi";
                 reg = <0x14530000 0x70000>;
                 interrupts = <0 95 0>;
+                clocks = <&clock 333>, <&clock 136>, <&clock 137>,
+                                <&clock 333>, <&clock 333>;
+                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                "sclk_hdmiphy", "hdmiphy";
         };
 
         mixer {
@@ -627,4 +762,18 @@
                 reg = <0x14450000 0x10000>;
                 interrupts = <0 94 0>;
         };
+
+        dp-controller {
+                compatible = "samsung,exynos5-dp";
+                reg = <0x145b0000 0x1000>;
+                interrupts = <10 3>;
+                interrupt-parent = <&combiner>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                dptx-phy {
+                        reg = <0x10040720>;
+                        samsung,enable-mask = <1>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 81e2c964a900..a21eb4cbe893 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -28,19 +28,10 @@
                 status = "disabled";
         };
 
-        i2c@F0000 {
-                status = "disabled";
-        };
-
-        i2c@100000 {
-                status = "disabled";
-        };
-
-        watchdog {
-                status = "disabled";
-        };
-
-        rtc {
-                status = "disabled";
+        fixed-rate-clocks {
+                xtal {
+                        compatible = "samsung,clock-xtal";
+                        clock-frequency = <50000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9a99755920c0..48cc96aa0b5f 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,12 @@
 
         interrupt-parent = <&gic>;
 
+        clock: clock-controller@0x160000 {
+                compatible = "samsung,exynos5440-clock";
+                reg = <0x160000 0x1000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@2E0000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
@@ -24,55 +30,51 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 13 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <0>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <1>;
                 };
                 cpu@2 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <2>;
                 };
                 cpu@3 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <3>;
                 };
         };
 
-        common {
-                compatible = "samsung,exynos5440";
-
+        timer {
+                compatible = "arm,cortex-a15-timer",
+                             "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+                clock-frequency = <50000000>;
         };
 
         serial@B0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xB0000 0x1000>;
                 interrupts = <0 2 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@C0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xC0000 0x1000>;
                 interrupts = <0 3 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         spi {
@@ -83,6 +85,8 @@
                 rx-dma-channel = <&pdma0 4>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>, <&clock 16>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         pinctrl {
@@ -110,25 +114,31 @@
         };
 
         i2c@F0000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0xF0000 0x1000>;
                 interrupts = <0 5 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         i2c@100000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0x100000 0x1000>;
                 interrupts = <0 6 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x110000 0x1000>;
                 interrupts = <0 1 0>;
+                clocks = <&clock 21>;
+                clock-names = "watchdog";
         };
 
         amba {
@@ -142,6 +152,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x120000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -151,6 +163,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -161,5 +175,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x130000 0x1000>;
                 interrupts = <0 17 0>, <0 16 0>;
+                clocks = <&clock 21>;
+                clock-names = "rtc";
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index f624dc85d441..02d23f15fd86 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -38,6 +38,57 @@
                 };
         };
 
+        /* HS USB Port 2 RESET */
+        hsusb2_reset: hsusb2_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 19 0>;   /* gpio_147 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Port 2 Power */
+        hsusb2_power: hsusb2_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 18 0>;        /* GPIO LEDA */
+                startup-delay-us = <70000>;
+        };
+
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb2_reset>;
+                vcc-supply = <&hsusb2_power>;
+        };
+};
+
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusbb2_pins
+        >;
+
+        hsusbb2_pins: pinmux_hsusbb2_pins {
+                pinctrl-single,pins = <
+                        0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
+                        0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
+                        0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
+                        0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
+                        0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
+                        0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
+                        0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
+                        0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
+                        0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
+                        0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
+                        0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
+                        0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+                >;
+        };
 };
 
 &i2c1 {
@@ -65,3 +116,23 @@
 &mmc3 {
         status = "disabled";
 };
+
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1acc26148ffc..a14f74bbce7c 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -397,5 +397,36 @@
                         ti,timer-alwon;
                         ti,timer-secure;
                 };
+
+                usbhstll: usbhstll@48062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x48062000 0x1000>;
+                        interrupts = <78>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@48064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x48064000 0x400>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@48064400 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x48064400 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <76>;
+                        };
+
+                        usbhsehci: ehci@48064800 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x48064800 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <77>;
+                        };
+                };
+
         };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 739bb79e410e..b7db1a2b6ca7 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -529,5 +529,35 @@
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
+
+                usbhstll: usbhstll@4a062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x4a062000 0x1000>;
+                        interrupts = <0 78 0x4>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@4a064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x4a064000 0x800>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@4a064800 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x4a064800 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 76 0x4>;
+                        };
+
+                        usbhsehci: ehci@4a064c00 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x4a064c00 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 77 0x4>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 6ebc1b704190..616990dc92db 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,7 +12,6 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 5deb8692b350..6bbc8efae9c0 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,7 +12,6 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c0b527d15fda..c1110a9b2a91 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -24,10 +24,11 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
-                compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+                compatible = "nvidia,tegra114-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
         };
@@ -66,6 +67,7 @@
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 6>;
         };
 
         serial@70006040 {
@@ -74,6 +76,7 @@
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 192>;
         };
 
         serial@70006200 {
@@ -82,6 +85,7 @@
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 55>;
         };
 
         serial@70006300 {
@@ -90,12 +94,14 @@
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 65>;
         };
 
         rtc {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         pmc {
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index 68c8dc644383..4a4b96f6827e 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -25,11 +25,13 @@
                         #interrupt-cells = <1>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "via,vt8500-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "via,vt8500-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index 398b8bca791e..b2bf359e852f 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -40,11 +40,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8505-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8505-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index 9313407bbc30..dd8464eeb40d 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -34,11 +34,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8650-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index 7149cd13e3b9..fc790d0aee66 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -41,11 +41,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8850-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 9e1c339c4491..748fc347ed18 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -118,56 +118,23 @@
                 };
 
                 ttc0: ttc0@f8001000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8001000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc0_0: ttc0.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 10 4>;
-                        };
-                        ttc0_1: ttc0.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 11 4>;
-                        };
-                        ttc0_2: ttc0.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 12 4>;
-                        };
                 };
 
                 ttc1: ttc1@f8002000 {
-                        #interrupt-parent = <&intc>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8002000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc1_0: ttc1.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 37 4>;
-                        };
-                        ttc1_1: ttc1.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 38 4>;
-                        };
-                        ttc1_2: ttc1.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 39 4>;
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index c772942a399a..86f44d5b0265 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -32,13 +32,3 @@
 &ps_clk {
         clock-frequency = <33333330>;
 };
-
-&ttc0_0 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clocksource";
-};
-
-&ttc0_1 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clockevent";
-};
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index ac7a341bd0ff..25efb5ac30f1 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -169,6 +169,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 92e0f861084a..629ea5fc95cf 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -488,7 +488,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -505,6 +504,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
                 return;
         }
 
+        if (cpu_is_at91sam9g10())
+                at91_lcdc_device.name = "at91sam9g10-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9261-lcdfb";
+
 #if defined(CONFIG_FB_ATMEL_STN)
         at91_set_A_periph(AT91_PIN_PB0, 0);     /* LCDVSYNC */
         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 8e2d9f4a9a45..f44ffd2105a7 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index ed666f5cb01d..858c8aac2daf 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9263-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index a6c224fc9542..8b7fce067652 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -228,6 +228,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_ID("hclk", &macb_clk),
         /* One additional fake clock for ohci */
         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index f0bf68268ca2..acb703e13331 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -981,7 +981,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -997,6 +996,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
         if (!data)
                 return;
 
+        if (cpu_is_at91sam9g45es())
+                at91_lcdc_device.name = "at91sam9g45es-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9g45-lcdfb";
+
         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 
         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index c39600764236..f77fae5591bc 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -179,6 +179,7 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index ddf223ff35c4..352468f265a9 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9rl-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f22f69e2d081..d19edff0ea6e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select S5P_DEV_MFC
@@ -83,12 +84,6 @@ config SOC_EXYNOS5440
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS4_MCT
-        bool
-        default y
-        help
-          Use MCT (Multi Core Timer) as kernel timers
-
 config EXYNOS_ATAGS
         bool "ATAGS based boot for EXYNOS (deprecated)"
         depends on !ARCH_MULTIPLATFORM
@@ -285,8 +280,8 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_ONENAND
         select S5P_DEV_TV
         select S5P_GPIO_INT
-        select S5P_HRT
         select S5P_SETUP_MIPIPHY
+        select SAMSUNG_HRT
         help
           Machine support for Samsung Mobile Universal S5PC210 Reference
           Board.
@@ -414,10 +409,12 @@ config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
         depends on ARCH_EXYNOS4
         select ARM_AMBA
+        select CLKSRC_OF
         select CPU_EXYNOS4210
         select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
         select PINCTRL
         select PINCTRL_EXYNOS
+        select S5P_DEV_MFC
         select USE_OF
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
@@ -430,6 +427,7 @@ config MACH_EXYNOS5_DT
         default y
         depends on ARCH_EXYNOS5
         select ARM_AMBA
+        select CLKSRC_OF
         select USE_OF
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 435757e57bb4..d2f6b362b6dd 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,10 +13,6 @@ obj-				:=
 # Core
 
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
-obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
-obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
-obj-$(CONFIG_SOC_EXYNOS5250)    += clock-exynos5.o
 
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
@@ -26,8 +22,6 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
-obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
-
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
 # machine support
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
deleted file mode 100644
index 8a8468d83c8c..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ /dev/null
@@ -1,1601 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
-        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
-        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
-        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
-};
-#endif
-
-static struct clk exynos4_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos4_clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
-}
-
-int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
-}
-
-int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos4_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos4_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk exynos4_clk_mout_mpll = {
-        .clk    = {
-                .name           = "mout_mpll",
-        },
-        .sources = &clk_src_mpll,
-
-        /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *exynos4_clkset_moutcore_list[] = {
-        [0] = &exynos4_clk_mout_apll.clk,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_moutcore = {
-        .sources        = exynos4_clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
-};
-
-static struct clksrc_clk exynos4_clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources = &exynos4_clkset_moutcore,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &exynos4_clk_moutcore.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-static struct clk *exynos4_clkset_corebus_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_corebus = {
-        .sources        = exynos4_clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources = &exynos4_clkset_mout_corebus,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &exynos4_clk_sclk_dmc.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &exynos4_clk_aclk_cored.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos4_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *exynos4_clkset_aclk_top_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_aclk = {
-        .sources        = exynos4_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos4_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk exynos4_clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *exynos4_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos4_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos4_clkset_vpllsrc = {
-        .sources        = exynos4_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos4_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_vpll_list[] = {
-        [0] = &exynos4_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_vpll = {
-        .sources        = exynos4_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos4_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk exynos4_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "jpeg",
-                .id             = 0,
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "tsi",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "biu",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "onenand",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "tmu_apbif",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "slimbus",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }
-};
-
-static struct clk exynos4_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos4_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk exynos4_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos4_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos4_clk_ip_image_ctrl,
-        .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
-};
-
-static struct clk exynos4_clk_fimd0 = {
-        .name           = "fimd",
-        .devname        = "exynos4-fb.0",
-        .enable         = exynos4_clk_ip_lcd0_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-struct clk *exynos4_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &exynos4_clk_sclk_hdmi27m,
-        [3] = &exynos4_clk_sclk_usbphy0,
-        [4] = &exynos4_clk_sclk_usbphy1,
-        [5] = &exynos4_clk_sclk_hdmiphy,
-        [6] = &exynos4_clk_mout_mpll.clk,
-        [7] = &exynos4_clk_mout_epll.clk,
-        [8] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_group = {
-        .sources        = exynos4_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d0 = {
-        .sources        = exynos4_clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d1 = {
-        .sources        = exynos4_clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
-};
-
-static struct clk *exynos4_clkset_mout_mfc0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
-        .sources        = exynos4_clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources = &exynos4_clkset_mout_mfc0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
-        .sources        = exynos4_clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources = &exynos4_clkset_mout_mfc1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc_list[] = {
-        [0] = &exynos4_clk_mout_mfc0.clk,
-        [1] = &exynos4_clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc = {
-        .sources        = exynos4_clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
-};
-
-static struct clk *exynos4_clkset_sclk_dac_list[] = {
-        [0] = &exynos4_clk_sclk_vpll.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_dac = {
-        .sources        = exynos4_clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_sclk_dac,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos4_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos4_clk_sclk_pixel.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
-        .sources        = exynos4_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_mixer_list[] = {
-        [0] = &exynos4_clk_sclk_dac.clk,
-        [1] = &exynos4_clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_mixer = {
-        .sources        = exynos4_clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mixer = {
-        .clk    = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_sclk_mixer,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *exynos4_sclk_tv[] = {
-        &exynos4_clk_sclk_dac,
-        &exynos4_clk_sclk_pixel,
-        &exynos4_clk_sclk_hdmi,
-        &exynos4_clk_sclk_mixer,
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc0 = {
-        .clk    = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc1 = {
-        .clk    = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc2 = {
-        .clk    = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc3 = {
-        .clk    = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &exynos4_clkset_mout_mfc,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "ciu",
-                        .parent         = &exynos4_clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos4_clk_mdout_spi0.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos4_clk_mdout_spi1.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos4_clk_mdout_spi2.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos4_sysclks[] = {
-        &exynos4_clk_mout_apll,
-        &exynos4_clk_sclk_apll,
-        &exynos4_clk_mout_epll,
-        &exynos4_clk_mout_mpll,
-        &exynos4_clk_moutcore,
-        &exynos4_clk_coreclk,
-        &exynos4_clk_armclk,
-        &exynos4_clk_aclk_corem0,
-        &exynos4_clk_aclk_cores,
-        &exynos4_clk_aclk_corem1,
-        &exynos4_clk_periphclk,
-        &exynos4_clk_mout_corebus,
-        &exynos4_clk_sclk_dmc,
-        &exynos4_clk_aclk_cored,
-        &exynos4_clk_aclk_corep,
-        &exynos4_clk_aclk_acp,
-        &exynos4_clk_pclk_acp,
-        &exynos4_clk_vpllsrc,
-        &exynos4_clk_sclk_vpll,
-        &exynos4_clk_aclk_200,
-        &exynos4_clk_aclk_100,
-        &exynos4_clk_aclk_160,
-        &exynos4_clk_aclk_133,
-        &exynos4_clk_dout_mmc0,
-        &exynos4_clk_dout_mmc1,
-        &exynos4_clk_dout_mmc2,
-        &exynos4_clk_dout_mmc3,
-        &exynos4_clk_dout_mmc4,
-        &exynos4_clk_mout_mfc0,
-        &exynos4_clk_mout_mfc1,
-};
-
-static struct clk *exynos4_clk_cdev[] = {
-        &exynos4_clk_pdma0,
-        &exynos4_clk_pdma1,
-        &exynos4_clk_mdma1,
-        &exynos4_clk_fimd0,
-};
-
-static struct clksrc_clk *exynos4_clksrc_cdev[] = {
-        &exynos4_clk_sclk_uart0,
-        &exynos4_clk_sclk_uart1,
-        &exynos4_clk_sclk_uart2,
-        &exynos4_clk_sclk_uart3,
-        &exynos4_clk_sclk_mmc0,
-        &exynos4_clk_sclk_mmc1,
-        &exynos4_clk_sclk_mmc2,
-        &exynos4_clk_sclk_mmc3,
-        &exynos4_clk_sclk_spi0,
-        &exynos4_clk_sclk_spi1,
-        &exynos4_clk_sclk_spi2,
-        &exynos4_clk_mdout_spi0,
-        &exynos4_clk_mdout_spi1,
-        &exynos4_clk_mdout_spi2,
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
-        else
-                return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 exynos4_vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
-                if (exynos4_vpll_div[i][0] == rate) {
-                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
-        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1));
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
-
-        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
-
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
-}
-
-static struct clk *exynos4_clks[] __initdata = {
-        &exynos4_clk_sclk_hdmi27m,
-        &exynos4_clk_sclk_hdmiphy,
-        &exynos4_clk_sclk_usbphy0,
-        &exynos4_clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
-                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
-        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
deleted file mode 100644
index bd12d5f8b63d..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clksrc_clk exynos4_clk_aclk_133;
-extern struct clksrc_clk exynos4_clk_mout_mpll;
-
-extern struct clksrc_sources exynos4_clkset_mout_corebus;
-extern struct clksrc_sources exynos4_clkset_group;
-
-extern struct clk *exynos4_clkset_aclk_top_list[];
-extern struct clk *exynos4_clkset_group_list[];
-
-extern struct clksrc_sources exynos4_clkset_mout_g2d0;
-extern struct clksrc_sources exynos4_clkset_mout_g2d1;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
deleted file mode 100644
index 19af9f783c56..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4210 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
-};
-#endif
-
-static struct clksrc_clk *sysclks[] = {
-        /* nothing here yet */
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4210_clkset_mout_g2d_list[] = {
-        [0] = &exynos4210_clk_mout_g2d0.clk,
-        [1] = &exynos4210_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4210_clkset_mout_g2d = {
-        .sources        = exynos4210_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
-};
-
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .id             = -1,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_mout_corebus,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4210_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sataphy",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sata",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4210_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-
-        return 0;
-}
-
-static void exynos4210_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-}
-
-#else
-#define exynos4210_clock_suspend NULL
-#define exynos4210_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4210_clock_syscore_ops = {
-        .suspend        = exynos4210_clock_suspend,
-        .resume         = exynos4210_clock_resume,
-};
-
-void __init exynos4210_register_clocks(void)
-{
-        int ptr;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
-        exynos4_clk_mout_mpll.reg_src.shift = 8;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4210_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
deleted file mode 100644
index 529476f8ec71..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4212 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
-};
-#endif
-
-static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static struct clk *clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_mpll_user = {
-        .sources        = clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk clk_mout_mpll_user = {
-        .clk = {
-                .name           = "mout_mpll_user",
-        },
-        .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
-        [0] = &exynos4x12_clk_mout_g2d0.clk,
-        [1] = &exynos4x12_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
-        .sources        = exynos4x12_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
-};
-
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_mpll_user,
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4x12_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (7 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = exynos4212_clk_ip_isp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.15",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.0",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.1",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 23),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4212_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-
-        return 0;
-}
-
-static void exynos4212_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-}
-
-#else
-#define exynos4212_clock_suspend NULL
-#define exynos4212_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4212_clock_syscore_ops = {
-        .suspend        = exynos4212_clock_suspend,
-        .resume         = exynos4212_clock_resume,
-};
-
-void __init exynos4212_register_clocks(void)
-{
-        int ptr;
-
-        /* usbphy1 is removed */
-        exynos4_clkset_group_list[4] = NULL;
-
-        /* mout_mpll_user is used */
-        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
-        exynos4_clk_mout_mpll.reg_src.shift = 12;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4212_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Clock support for EXYNOS5 SoCs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos5_clock_save[] = {
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
-        SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
-        SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
-        SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
-        SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
-        SAVE_ITEM(EXYNOS5_EPLL_CON0),
-        SAVE_ITEM(EXYNOS5_EPLL_CON1),
-        SAVE_ITEM(EXYNOS5_EPLL_CON2),
-        SAVE_ITEM(EXYNOS5_VPLL_CON0),
-        SAVE_ITEM(EXYNOS5_VPLL_CON1),
-        SAVE_ITEM(EXYNOS5_VPLL_CON2),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL1),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL2),
-};
-#endif
-
-static struct clk exynos5_clk_sclk_dptxphy = {
-        .name           = "sclk_dptx",
-};
-
-static struct clk exynos5_clk_sclk_hdmi24m = {
-        .name           = "sclk_hdmi24m",
-        .rate           = 24000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos5_clk_sclk_usbphy = {
-        .name           = "sclk_usbphy",
-        .rate           = 48000000,
-};
-
-static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
-}
-
-static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
-}
-
-static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
-}
-
-static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
-}
-
-static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
-}
-
-static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
-}
-
-static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
-}
-
-static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
-}
-
-static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
-}
-
-static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos5_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos5_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
-        .clk    = {
-                .name           = "mout_bpll_fout",
-        },
-        .sources = &clk_src_bpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_list[] = {
-        [0] = &clk_fin_bpll,
-        [1] = &exynos5_clk_mout_bpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll = {
-        .sources        = exynos5_clk_src_bpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll = {
-        .clk    = {
-                .name           = "mout_bpll",
-        },
-        .sources = &exynos5_clk_src_bpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll_user = {
-        .sources        = exynos5_clk_src_bpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_user = {
-        .clk    = {
-                .name           = "mout_bpll_user",
-        },
-        .sources = &exynos5_clk_src_bpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpll = {
-        .clk    = {
-                .name           = "mout_cpll",
-        },
-        .sources = &clk_src_cpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
-        .clk    = {
-                .name           = "mout_mpll_fout",
-        },
-        .sources = &clk_src_mpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll = {
-        .sources        = exynos5_clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources = &exynos5_clk_src_mpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
-};
-
-static struct clk *exynos_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos5_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos5_clkset_vpllsrc = {
-        .sources        = exynos_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos5_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos5_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_sclk_vpll_list[] = {
-        [0] = &exynos5_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_vpll = {
-        .sources        = exynos5_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos5_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_pixel = {
-        .clk    = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos5_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
-};
-
-static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos5_clk_sclk_pixel.clk,
-        [1] = &exynos5_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
-        .sources        = exynos5_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_hdmi = {
-        .clk    = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .sources = &exynos5_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk *exynos5_sclk_tv[] = {
-        &exynos5_clk_sclk_pixel,
-        &exynos5_clk_sclk_hdmi,
-};
-
-static struct clk *exynos5_clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll_user = {
-        .sources        = exynos5_clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_user = {
-        .clk    = {
-                .name           = "mout_mpll_user",
-        },
-        .sources = &exynos5_clk_src_mpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_mout_cpu_list[] = {
-        [0] = &exynos5_clk_mout_apll.clk,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_mout_cpu = {
-        .sources        = exynos5_clkset_mout_cpu_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpu = {
-        .clk    = {
-                .name           = "mout_cpu",
-        },
-        .sources = &exynos5_clkset_mout_cpu,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_armclk = {
-        .clk    = {
-                .name           = "dout_armclk",
-                .parent         = &exynos5_clk_mout_cpu.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_arm2clk = {
-        .clk    = {
-                .name           = "dout_arm2clk",
-                .parent         = &exynos5_clk_dout_armclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
-};
-
-static struct clk exynos5_clk_armclk = {
-        .name           = "armclk",
-        .parent         = &exynos5_clk_dout_arm2clk.clk,
-};
-
-/* Core list of CMU_CDREX side */
-
-static struct clk *exynos5_clkset_cdrex_list[] = {
-        [0] = &exynos5_clk_mout_mpll.clk,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_cdrex = {
-        .sources        = exynos5_clkset_cdrex_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
-};
-
-static struct clksrc_clk exynos5_clk_cdrex = {
-        .clk    = {
-                .name           = "clk_cdrex",
-        },
-        .sources = &exynos5_clkset_cdrex,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos5_clk_mout_mpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos5_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-static struct clk *exynos5_clkset_aclk_top_list[] = {
-        [0] = &exynos5_clk_mout_mpll_user.clk,
-        [1] = &exynos5_clk_mout_bpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk = {
-        .sources        = exynos5_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_400 = {
-        .clk    = {
-                .name           = "aclk_400",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-};
-
-static struct clk *exynos5_clkset_aclk_333_166_list[] = {
-        [0] = &exynos5_clk_mout_cpll.clk,
-        [1] = &exynos5_clk_mout_mpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
-        .sources        = exynos5_clkset_aclk_333_166_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_333 = {
-        .clk    = {
-                .name           = "aclk_333",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_166 = {
-        .clk    = {
-                .name           = "aclk_166",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_266 = {
-        .clk    = {
-                .name           = "aclk_266",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66_pre = {
-        .clk    = {
-                .name           = "aclk_66_pre",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66 = {
-        .clk    = {
-                .name           = "aclk_66",
-                .parent         = &exynos5_clk_aclk_66_pre.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
-        [0] = &exynos5_clk_sclk_vpll.clk,
-        [1] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
-        .sources        = exynos5_clkset_aclk_300_mid1_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid1",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl_mid1,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
-        [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
-        [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
-        .sources        = exynos5_clkset_aclk_300_gscl_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_gscl_300_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_gscl_300 = {
-        .sources        = exynos5_clk_src_gscl_300_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
-        .clk    = {
-                .name           = "aclk_300_gscl",
-        },
-        .sources = &exynos5_clk_src_gscl_300,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
-};
-
-static struct clk exynos5_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "tmu_apbif",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "rtc",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "biu",        /* bus interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "sata",
-                .devname        = "exynos5-sata",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "sata-phy",
-                .devname        = "exynos5-sata-phy",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "i2c",
-                .devname        = "exynos5-sata-phy-i2c",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc-v6",
-                .enable         = exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mixer",
-                .devname        = "exynos5-mixer",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "dp",
-                .devname        = "exynos-dp",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "jpeg",
-                .enable         = exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "dsim0",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos5_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "usbotg",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
-        }, {
-                .name           = "core_iop",
-                .enable         = exynos5_clk_ip_core_ctrl,
-                .ctrlbit        = ((1 << 21) | (1 << 3)),
-        }, {
-                .name           = "mcu_iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.0",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.1",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.2",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.3",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 9)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 6)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = &exynos5_clk_ip_isp0_ctrl,
-                .ctrlbit        = (0x3F << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = &exynos5_clk_ip_isp1_ctrl,
-                .ctrlbit        = (0xF << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 8)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = &exynos5_clk_ip_acp_ctrl,
-                .ctrlbit        = (1 << 7)
-        }
-};
-
-static struct clk exynos5_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos5_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 2),
-};
-
-static struct clk exynos5_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos5_clk_ip_gen_ctrl,
-        .ctrlbit        = (1 << 4),
-};
-
-static struct clk exynos5_clk_fimd1 = {
-        .name           = "fimd",
-        .devname        = "exynos5-fb.1",
-        .enable         = exynos5_clk_ip_disp1_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk *exynos5_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = NULL,
-        [2] = &exynos5_clk_sclk_hdmi24m,
-        [3] = &exynos5_clk_sclk_dptxphy,
-        [4] = &exynos5_clk_sclk_usbphy,
-        [5] = &exynos5_clk_sclk_hdmiphy,
-        [6] = &exynos5_clk_mout_mpll_user.clk,
-        [7] = &exynos5_clk_mout_epll.clk,
-        [8] = &exynos5_clk_sclk_vpll.clk,
-        [9] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_group = {
-        .sources        = exynos5_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
-};
-
-/* Possible clock sources for aclk_266_gscl_sub Mux */
-static struct clk *clk_src_gscl_266_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_aclk_266.clk,
-};
-
-static struct clksrc_sources clk_src_gscl_266 = {
-        .sources        = clk_src_gscl_266_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "ciu",        /* card interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_dout_mmc0.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_dout_mmc1.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_dout_mmc2.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_dout_mmc3.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_mdout_spi0.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_mdout_spi1.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_mdout_spi2.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
-        .clk    = {
-                .name           = "sclk_fimd",
-                .devname        = "exynos5-fb.1",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "aclk_266_gscl",
-                },
-                .sources = &clk_src_gscl_266,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_g3d",
-                        .devname        = "mali-t604.0",
-                        .enable         = exynos5_clk_block_ctrl,
-                        .ctrlbit        = (1 << 1),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_sata",
-                        .devname        = "exynos5-sata",
-                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_jpeg",
-                        .parent         = &exynos5_clk_mout_cpll.clk,
-                },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
-        },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos5_sysclks[] = {
-        &exynos5_clk_mout_apll,
-        &exynos5_clk_sclk_apll,
-        &exynos5_clk_mout_bpll,
-        &exynos5_clk_mout_bpll_fout,
-        &exynos5_clk_mout_bpll_user,
-        &exynos5_clk_mout_cpll,
-        &exynos5_clk_mout_epll,
-        &exynos5_clk_mout_mpll,
-        &exynos5_clk_mout_mpll_fout,
-        &exynos5_clk_mout_mpll_user,
-        &exynos5_clk_vpllsrc,
-        &exynos5_clk_sclk_vpll,
-        &exynos5_clk_mout_cpu,
-        &exynos5_clk_dout_armclk,
-        &exynos5_clk_dout_arm2clk,
-        &exynos5_clk_cdrex,
-        &exynos5_clk_aclk_400,
-        &exynos5_clk_aclk_333,
-        &exynos5_clk_aclk_266,
-        &exynos5_clk_aclk_200,
-        &exynos5_clk_aclk_166,
-        &exynos5_clk_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl_mid,
-        &exynos5_clk_mout_aclk_300_gscl_mid1,
-        &exynos5_clk_aclk_66_pre,
-        &exynos5_clk_aclk_66,
-        &exynos5_clk_dout_mmc0,
-        &exynos5_clk_dout_mmc1,
-        &exynos5_clk_dout_mmc2,
-        &exynos5_clk_dout_mmc3,
-        &exynos5_clk_dout_mmc4,
-        &exynos5_clk_aclk_acp,
-        &exynos5_clk_pclk_acp,
-        &exynos5_clk_sclk_spi0,
-        &exynos5_clk_sclk_spi1,
-        &exynos5_clk_sclk_spi2,
-        &exynos5_clk_mdout_spi0,
-        &exynos5_clk_mdout_spi1,
-        &exynos5_clk_mdout_spi2,
-        &exynos5_clk_sclk_fimd1,
-};
-
-static struct clk *exynos5_clk_cdev[] = {
-        &exynos5_clk_pdma0,
-        &exynos5_clk_pdma1,
-        &exynos5_clk_mdma1,
-        &exynos5_clk_fimd1,
-};
-
-static struct clksrc_clk *exynos5_clksrc_cdev[] = {
-        &exynos5_clk_sclk_uart0,
-        &exynos5_clk_sclk_uart1,
-        &exynos5_clk_sclk_uart2,
-        &exynos5_clk_sclk_uart3,
-        &exynos5_clk_sclk_mmc0,
-        &exynos5_clk_sclk_mmc1,
-        &exynos5_clk_sclk_mmc2,
-        &exynos5_clk_sclk_mmc3,
-};
-
-static struct clk_lookup exynos5_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
-        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
-};
-
-static unsigned long exynos5_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static struct clk *exynos5_clks[] __initdata = {
-        &exynos5_clk_sclk_hdmi27m,
-        &exynos5_clk_sclk_hdmiphy,
-        &clk_fout_bpll,
-        &clk_fout_bpll_div2,
-        &clk_fout_cpll,
-        &clk_fout_mpll_div2,
-        &exynos5_clk_armclk,
-};
-
-static u32 epll_div[][6] = {
-        { 192000000, 0, 48, 3, 1, 0 },
-        { 180000000, 0, 45, 3, 1, 0 },
-        {  73728000, 1, 73, 3, 3, 47710 },
-        {  67737600, 1, 90, 4, 3, 20762 },
-        {  49152000, 0, 49, 3, 3, 9961 },
-        {  45158400, 0, 45, 3, 3, 10381 },
-        { 180633600, 0, 45, 3, 1, 10381 },
-};
-
-static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-        unsigned int tmp;
-        unsigned int epll_rate;
-        unsigned int locktime;
-        unsigned int lockcnt;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        if (clk->parent)
-                epll_rate = clk_get_rate(clk->parent);
-        else
-                epll_rate = clk_ext_xtal_mux.rate;
-
-        if (epll_rate != 24000000) {
-                pr_err("Invalid Clock : recommended clock is 24MHz.\n");
-                return -EINVAL;
-        }
-
-        epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
-        epll_con &= ~(0x1 << 27 | \
-                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
-                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
-                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                if (epll_div[i][0] == rate) {
-                        epll_con_k = epll_div[i][5] << 0;
-                        epll_con |= epll_div[i][1] << 27;
-                        epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
-                        epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        epll_rate /= 1000000;
-
-        /* 3000 max_cycls : specification data */
-        locktime = 3000 / epll_rate * epll_div[i][3];
-        lockcnt = locktime * 10000 / (10000 / epll_rate);
-
-        __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
-
-        __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
-        __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
-
-        do {
-                tmp = __raw_readl(EXYNOS5_EPLL_CON0);
-        } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops exynos5_epll_ops = {
-        .get_rate = exynos5_epll_get_rate,
-        .set_rate = exynos5_epll_set_rate,
-};
-
-static int xtal_rate;
-
-static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
-{
-        return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
-}
-
-static struct clk_ops exynos5_fout_apll_ops = {
-        .get_rate = exynos5_fout_apll_get_rate,
-};
-
-#ifdef CONFIG_PM
-static int exynos5_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-
-        return 0;
-}
-
-static void exynos5_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-}
-#else
-#define exynos5_clock_suspend NULL
-#define exynos5_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos5_clock_syscore_ops = {
-        .suspend        = exynos5_clock_suspend,
-        .resume         = exynos5_clock_resume,
-};
-
-void __init_or_cpufreq exynos5_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll;
-        unsigned long bpll;
-        unsigned long cpll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long mout_cdrex;
-        unsigned long aclk_400;
-        unsigned long aclk_333;
-        unsigned long aclk_266;
-        unsigned long aclk_200;
-        unsigned long aclk_166;
-        unsigned long aclk_66;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
-        bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
-        cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
-        mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
-        epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
-                        __raw_readl(EXYNOS5_EPLL_CON1));
-
-        vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
-        vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
-                        __raw_readl(EXYNOS5_VPLL_CON1));
-
-        clk_fout_apll.ops = &exynos5_fout_apll_ops;
-        clk_fout_bpll.rate = bpll;
-        clk_fout_bpll_div2.rate = bpll >> 1;
-        clk_fout_cpll.rate = cpll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_mpll_div2.rate = mpll >> 1;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
-                        "M=%ld, E=%ld V=%ld",
-                        apll, bpll, cpll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos5_clk_armclk);
-        mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
-
-        aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
-        aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
-        aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
-        aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
-        aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
-        aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
-
-        printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
-                        "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
-                        "ACLK166=%ld, ACLK66=%ld\n",
-                        armclk, mout_cdrex, aclk_400,
-                        aclk_333, aclk_266, aclk_200,
-                        aclk_166, aclk_66);
-
-
-        clk_fout_epll.ops = &exynos5_epll_ops;
-
-        if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
-                printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
-                                clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
-
-        clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
-        clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
-
-        clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
-        clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
-}
-
-void __init exynos5_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
-                s3c_register_clksrc(exynos5_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
-        s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
-
-        register_syscore_ops(&exynos5_clock_syscore_ops);
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 15718da30c45..b35c60059bb8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -24,6 +24,8 @@
 #include <linux/export.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/irqchip/chained_irq.h>
 
@@ -37,9 +39,9 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
+#include <mach/irqs.h>
 
 #include <plat/cpu.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/sdhci.h>
@@ -65,17 +67,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
-static void exynos4_init_clocks(int xtal);
-static void exynos5_init_clocks(int xtal);
 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = EXYNOS4210_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
@@ -83,7 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4212_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
@@ -91,7 +91,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4412_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
@@ -99,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS5250_SOC_ID,
                 .idmask         = EXYNOS5_SOC_MASK,
                 .map_io         = exynos5_map_io,
-                .init_clocks    = exynos5_init_clocks,
                 .init           = exynos_init,
                 .name           = name_exynos5250,
         }, {
@@ -257,11 +255,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
                 .length         = SZ_4K,
@@ -402,43 +395,26 @@ static void __init exynos5_map_io(void)
         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 }
 
-static void __init exynos4_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        if (soc_is_exynos4210())
-                exynos4210_register_clocks();
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                exynos4212_register_clocks();
-
-        exynos4_register_clocks();
-        exynos4_setup_clocks();
-}
-
 static void __init exynos5440_map_io(void)
 {
         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 }
 
-static void __init exynos5_init_clocks(int xtal)
+void __init exynos_init_time(void)
 {
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        /* EXYNOS5440 can support only common clock framework */
-
-        if (soc_is_exynos5440())
-                return;
-
-#ifdef CONFIG_SOC_EXYNOS5250
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        exynos5_register_clocks();
-        exynos5_setup_clocks();
+        if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
+                of_clk_init(NULL);
+                clocksource_of_init();
+#endif
+        } else {
+                /* todo: remove after migrating legacy E4 platforms to dt */
+#ifdef CONFIG_ARCH_EXYNOS4
+                exynos4_clk_init(NULL);
+                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 #endif
+                mct_init();
+        }
 }
 
 void __init exynos4_init_irq(void)
@@ -824,6 +800,7 @@ static int __init exynos_init_irq_eint(void)
         static const struct of_device_id exynos_pinctrl_ids[] = {
                 { .compatible = "samsung,exynos4210-pinctrl", },
                 { .compatible = "samsung,exynos4x12-pinctrl", },
+                { .compatible = "samsung,exynos5250-pinctrl", },
         };
         struct device_node *pctrl_np, *wkup_np;
         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
@@ -877,3 +854,30 @@ static int __init exynos_init_irq_eint(void)
         return 0;
 }
 arch_initcall(exynos_init_irq_eint);
+
+static struct resource exynos4_pmu_resource[] = {
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+#if defined(CONFIG_SOC_EXYNOS4412)
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+#endif
+};
+
+static struct platform_device exynos4_device_pmu = {
+        .name           = "arm-pmu",
+        .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
+        .resource       = exynos4_pmu_resource,
+};
+
+static int __init exynos_armpmu_init(void)
+{
+        if (!of_have_populated_dt()) {
+                if (soc_is_exynos4210() || soc_is_exynos4212())
+                        exynos4_device_pmu.num_resources = 2;
+                platform_device_register(&exynos4_device_pmu);
+        }
+
+        return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9339bb8954be..cb89ab886950 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,11 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
-extern void exynos4_timer_init(void);
+#include <linux/of.h>
+
+extern void mct_init(void);
+void exynos_init_time(void);
+extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
+/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
+void exynos4_clk_init(struct device_node *np);
+void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 8bd5dde5fc78..c72f59d91fce 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
 
 /* For EXYNOS4 and EXYNOS5 */
 
-#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
-
 #define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
 
 /* For EXYNOS4 SoCs */
@@ -128,7 +126,7 @@
 #define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
 #define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
 #define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU                 IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU           IRQ_SPI(110)
 #define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
 #define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
 #define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
@@ -136,6 +134,11 @@
 #define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
 
+#define EXYNOS4_IRQ_PMU                 COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1            COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2            COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3            COMBINER_IRQ(19, 2)
+
 #define EXYNOS4_IRQ_TMU_TRIG0           COMBINER_IRQ(2, 4)
 #define EXYNOS4_IRQ_TMU_TRIG1           COMBINER_IRQ(3, 4)
 
@@ -168,7 +171,10 @@
 #define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
 
-#define EXYNOS4_MAX_COMBINER_NR         16
+#define EXYNOS4210_MAX_COMBINER_NR      16
+#define EXYNOS4212_MAX_COMBINER_NR      18
+#define EXYNOS4412_MAX_COMBINER_NR      20
+#define EXYNOS4_MAX_COMBINER_NR         EXYNOS4412_MAX_COMBINER_NR
 
 #define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
@@ -233,7 +239,6 @@
 #define IRQ_TC                          EXYNOS4_IRQ_PEN0
 
 #define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU                         EXYNOS4_IRQ_PMU
 
 #define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
@@ -323,8 +328,6 @@
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
 
-#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -419,8 +422,6 @@
 #define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
 
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 1df6abbf53b8..7f99b7b187d6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -65,7 +65,6 @@
 #define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
-#define EXYNOS5_PA_SYSTIMER             0x101C0000
 
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
deleted file mode 100644
index 80dd02ad6d61..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-mct.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x)               (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK              (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET              (0x00)
-#define MCT_L_ICNTB_OFFSET              (0x08)
-#define MCT_L_TCON_OFFSET               (0x20)
-#define MCT_L_INT_CSTAT_OFFSET          (0x30)
-#define MCT_L_INT_ENB_OFFSET            (0x34)
-#define MCT_L_WSTAT_OFFSET              (0x40)
-
-#define MCT_G_TCON_START                (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
-#define MCT_L_TCON_INT_START            (1 << 1)
-#define MCT_L_TCON_TIMER_START          (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 2126f3503a3f..5f0f55701374 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -178,7 +178,6 @@ static void __init armlex4210_smsc911x_init(void)
 static void __init armlex4210_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(armlex4210_uartcfgs,
                            ARRAY_SIZE(armlex4210_uartcfgs));
 }
@@ -203,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 3358088c822a..ac27f3cd121f 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,121 +11,26 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 #include <linux/serial_core.h>
+#include <linux/memblock.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-serial.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
-                                "exynos4-sdhci.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
-                                "exynos4-sdhci.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
-                                "exynos4-sdhci.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
-                                "exynos4-sdhci.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
-                        "exynos-sysmmu.0", NULL), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
-                        "exynos-sysmmu.1", NULL), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
-                        "exynos-sysmmu.3", NULL), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
-                        "exynos-sysmmu.5", NULL), /* FIMC0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
-                        "exynos-sysmmu.6", NULL), /* FIMC1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
-                        "exynos-sysmmu.7", NULL), /* FIMC2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
-                        "exynos-sysmmu.8", NULL), /* FIMC3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
-                        "exynos-sysmmu.10", NULL), /* FIMD0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
-                        "exynos-sysmmu.12", NULL), /* IS0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
-                        "exynos-sysmmu.13", NULL), /* IS1(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
-                        "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
-                        "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
-        {},
-};
-
 static void __init exynos4_dt_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos4_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos4_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos4_dt_compat[] __initdata = {
@@ -135,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
         NULL
 };
 
+static void __init exynos4_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+        struct s5p_mfc_dt_meminfo mfc_mem;
+
+        /* Reserve memory for MFC only if it's available */
+        mfc_mem.compatible = "samsung,mfc-v5";
+        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+                                mfc_mem.lsize);
+#endif
+}
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .smp            = smp_ops(exynos_smp_ops),
@@ -142,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         .map_io         = exynos4_dt_map_io,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
+        .reserve        = exynos4_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index acaeb14db54b..753b94f3fca7 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,151 +11,21 @@
 
 #include <linux/of_platform.h>
 #include <linux/of_fdt.h>
-#include <linux/serial_core.h>
 #include <linux/memblock.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
 #include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the EXYNOS5 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
-                                "s3c2440-hdmiphy-i2c", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
-                                "dw_mmc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
-                                "dw_mmc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
-                                "dw_mmc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
-                                "dw_mmc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
-                                "exynos5-sata", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
-                                "exynos5-sata-phy", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
-                                "exynos5-sata-phy-i2c", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
-                                "exynos-gsc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
-                                "exynos-gsc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
-                                "exynos-gsc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
-                                "exynos-gsc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
-                                "exynos5-hdmi", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
-                                "exynos5-mixer", NULL),
-        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
-                                "samsung-i2s.0", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
-                                "samsung-i2s.1", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
-                                "samsung-i2s.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
-                        "exynos-sysmmu.0", "mfc"), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
-                        "exynos-sysmmu.1", "mfc"), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
-                        "exynos-sysmmu.3", "jpeg"), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
-                        "exynos-sysmmu.5", "gscl"), /* GSCL0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
-                        "exynos-sysmmu.6", "gscl"), /* GSCL1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
-                        "exynos-sysmmu.7", "gscl"), /* GSCL2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
-                        "exynos-sysmmu.8", "gscl"), /* GSCL3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
-                        "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
-                        "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
-                        "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
-                        "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
-                        "exynos-sysmmu.14", NULL), /* G2D */
-        {},
-};
-
-static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        {},
-};
-
 static void __init exynos5_dt_map_io(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
         exynos_init_io(NULL, 0);
-
-        if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
-                s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos5_dt_machine_init(void)
@@ -182,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
                 }
         }
 
-        if (of_machine_is_compatible("samsung,exynos5250"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5250_auxdata_lookup, NULL);
-        else if (of_machine_is_compatible("samsung,exynos5440"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5440_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos5_dt_compat[] __initdata = {
@@ -216,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         .map_io         = exynos5_dt_map_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
         .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 2517406e7f56..5c8b2878dbbd 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1331,8 +1331,9 @@ static struct platform_device *nuri_devices[] __initdata = {
 static void __init nuri_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init nuri_reserve(void)
@@ -1381,7 +1382,7 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &nuri_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index ec42024dd13f..27f03ed5d067 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -755,8 +755,9 @@ static void s5p_tv_setup(void)
 static void __init origen_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init origen_power_init(void)
@@ -816,7 +817,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
         .map_io         = origen_map_io,
         .init_machine   = origen_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &origen_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 5df91236dbb4..2c8af9617920 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -323,7 +323,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
 static void __init smdk4x12_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
 }
 
@@ -377,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -391,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 9680e1291065..d95b8cf85253 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -372,8 +372,9 @@ static void s5p_tv_setup(void)
 static void __init smdkv310_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+        xxti_f = 12000000;
+        xusbxti_f = 24000000;
 }
 
 static void __init smdkv310_reserve(void)
@@ -424,7 +425,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
@@ -437,7 +438,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index d28c7fbaba2d..327d50d4681d 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -41,7 +41,7 @@
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/fimc-core.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/camport.h>
 
 #include <mach/map.h>
@@ -1093,9 +1093,10 @@ static struct platform_device *universal_devices[] __initdata = {
 static void __init universal_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void s5p_tv_setup(void)
@@ -1153,7 +1154,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         .map_io         = universal_map_io,
         .init_machine   = universal_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &universal_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
deleted file mode 100644
index c9d6650f9b5d..000000000000
--- a/arch/arm/mach-exynos/mct.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mct.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT(Multi-Core Timer) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/percpu.h>
-#include <linux/of.h>
-
-#include <asm/arch_timer.h>
-#include <asm/localtimer.h>
-
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/regs-mct.h>
-#include <asm/mach/time.h>
-
-#define TICK_BASE_CNT   1
-
-enum {
-        MCT_INT_SPI,
-        MCT_INT_PPI
-};
-
-static unsigned long clk_rate;
-static unsigned int mct_int_type;
-
-struct mct_clock_event_device {
-        struct clock_event_device *evt;
-        void __iomem *base;
-        char name[10];
-};
-
-static void exynos4_mct_write(unsigned int value, void *addr)
-{
-        void __iomem *stat_addr;
-        u32 mask;
-        u32 i;
-
-        __raw_writel(value, addr);
-
-        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-                case (u32) MCT_L_TCON_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 3;          /* L_TCON write status */
-                        break;
-                case (u32) MCT_L_ICNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 1;          /* L_ICNTB write status */
-                        break;
-                case (u32) MCT_L_TCNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 0;          /* L_TCNTB write status */
-                        break;
-                default:
-                        return;
-                }
-        } else {
-                switch ((u32) addr) {
-                case (u32) EXYNOS4_MCT_G_TCON:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 16;         /* G_TCON write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_L:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 0;          /* G_COMP0_L write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_U:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 1;          /* G_COMP0_U write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_CNT_L:
-                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                        mask = 1 << 0;          /* G_CNT_L write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_CNT_U:
-                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                        mask = 1 << 1;          /* G_CNT_U write status */
-                        break;
-                default:
-                        return;
-                }
-        }
-
-        /* Wait maximum 1 ms until written values are applied */
-        for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-                if (__raw_readl(stat_addr) & mask) {
-                        __raw_writel(mask, stat_addr);
-                        return;
-                }
-
-        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
-}
-
-/* Clocksource handling */
-static void exynos4_mct_frc_start(u32 hi, u32 lo)
-{
-        u32 reg;
-
-        exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
-        exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
-
-        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
-        reg |= MCT_G_TCON_START;
-        exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
-}
-
-static cycle_t exynos4_frc_read(struct clocksource *cs)
-{
-        unsigned int lo, hi;
-        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-
-        do {
-                hi = hi2;
-                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
-                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-        } while (hi != hi2);
-
-        return ((cycle_t)hi << 32) | lo;
-}
-
-static void exynos4_frc_resume(struct clocksource *cs)
-{
-        exynos4_mct_frc_start(0, 0);
-}
-
-struct clocksource mct_frc = {
-        .name           = "mct-frc",
-        .rating         = 400,
-        .read           = exynos4_frc_read,
-        .mask           = CLOCKSOURCE_MASK(64),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-        .resume         = exynos4_frc_resume,
-};
-
-static void __init exynos4_clocksource_init(void)
-{
-        exynos4_mct_frc_start(0, 0);
-
-        if (clocksource_register_hz(&mct_frc, clk_rate))
-                panic("%s: can't register clocksource\n", mct_frc.name);
-}
-
-static void exynos4_mct_comp0_stop(void)
-{
-        unsigned int tcon;
-
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-        tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
-
-        exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
-        exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
-}
-
-static void exynos4_mct_comp0_start(enum clock_event_mode mode,
-                                    unsigned long cycles)
-{
-        unsigned int tcon;
-        cycle_t comp_cycle;
-
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-
-        if (mode == CLOCK_EVT_MODE_PERIODIC) {
-                tcon |= MCT_G_TCON_COMP0_AUTO_INC;
-                exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
-        }
-
-        comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
-        exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
-        exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
-
-        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
-
-        tcon |= MCT_G_TCON_COMP0_ENABLE;
-        exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
-}
-
-static int exynos4_comp_set_next_event(unsigned long cycles,
-                                       struct clock_event_device *evt)
-{
-        exynos4_mct_comp0_start(evt->mode, cycles);
-
-        return 0;
-}
-
-static void exynos4_comp_set_mode(enum clock_event_mode mode,
-                                  struct clock_event_device *evt)
-{
-        unsigned long cycles_per_jiffy;
-        exynos4_mct_comp0_stop();
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                cycles_per_jiffy =
-                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
-                exynos4_mct_comp0_start(mode, cycles_per_jiffy);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static struct clock_event_device mct_comp_device = {
-        .name           = "mct-comp",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 250,
-        .set_next_event = exynos4_comp_set_next_event,
-        .set_mode       = exynos4_comp_set_mode,
-};
-
-static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-
-        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mct_comp_event_irq = {
-        .name           = "mct_comp_irq",
-        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = exynos4_mct_comp_isr,
-        .dev_id         = &mct_comp_device,
-};
-
-static void exynos4_clockevent_init(void)
-{
-        mct_comp_device.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&mct_comp_device, clk_rate,
-                                        0xf, 0xffffffff);
-
-        if (soc_is_exynos5250())
-                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
-        else
-                setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
-}
-
-#ifdef CONFIG_LOCAL_TIMERS
-
-static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
-
-/* Clock event handling */
-static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
-{
-        unsigned long tmp;
-        unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
-        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
-
-        tmp = __raw_readl(addr);
-        if (tmp & mask) {
-                tmp &= ~mask;
-                exynos4_mct_write(tmp, addr);
-        }
-}
-
-static void exynos4_mct_tick_start(unsigned long cycles,
-                                   struct mct_clock_event_device *mevt)
-{
-        unsigned long tmp;
-
-        exynos4_mct_tick_stop(mevt);
-
-        tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
-
-        /* update interrupt count buffer */
-        exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
-
-        /* enable MCT tick interrupt */
-        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
-
-        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
-        tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
-               MCT_L_TCON_INTERVAL_MODE;
-        exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
-}
-
-static int exynos4_tick_set_next_event(unsigned long cycles,
-                                       struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-
-        exynos4_mct_tick_start(cycles, mevt);
-
-        return 0;
-}
-
-static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
-                                         struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-        unsigned long cycles_per_jiffy;
-
-        exynos4_mct_tick_stop(mevt);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                cycles_per_jiffy =
-                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
-                exynos4_mct_tick_start(cycles_per_jiffy, mevt);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
-{
-        struct clock_event_device *evt = mevt->evt;
-
-        /*
-         * This is for supporting oneshot mode.
-         * Mct would generate interrupt periodically
-         * without explicit stopping.
-         */
-        if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
-                exynos4_mct_tick_stop(mevt);
-
-        /* Clear the MCT tick interrupt */
-        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
-                exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
-                return 1;
-        } else {
-                return 0;
-        }
-}
-
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
-{
-        struct mct_clock_event_device *mevt = dev_id;
-        struct clock_event_device *evt = mevt->evt;
-
-        exynos4_mct_tick_clear(mevt);
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mct_tick0_event_irq = {
-        .name           = "mct_tick0_irq",
-        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler        = exynos4_mct_tick_isr,
-};
-
-static struct irqaction mct_tick1_event_irq = {
-        .name           = "mct_tick1_irq",
-        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler        = exynos4_mct_tick_isr,
-};
-
-static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt;
-        unsigned int cpu = smp_processor_id();
-        int mct_lx_irq;
-
-        mevt = this_cpu_ptr(&percpu_mct_tick);
-        mevt->evt = evt;
-
-        mevt->base = EXYNOS4_MCT_L_BASE(cpu);
-        sprintf(mevt->name, "mct_tick%d", cpu);
-
-        evt->name = mevt->name;
-        evt->cpumask = cpumask_of(cpu);
-        evt->set_next_event = exynos4_tick_set_next_event;
-        evt->set_mode = exynos4_tick_set_mode;
-        evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        evt->rating = 450;
-        clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
-                                        0xf, 0x7fffffff);
-
-        exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
-
-        if (mct_int_type == MCT_INT_SPI) {
-                if (cpu == 0) {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
-                                                EXYNOS5_IRQ_MCT_L0;
-                        mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
-                } else {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
-                                                EXYNOS5_IRQ_MCT_L1;
-                        mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
-                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
-                }
-        } else {
-                enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
-        }
-
-        return 0;
-}
-
-static void exynos4_local_timer_stop(struct clock_event_device *evt)
-{
-        unsigned int cpu = smp_processor_id();
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-        if (mct_int_type == MCT_INT_SPI)
-                if (cpu == 0)
-                        remove_irq(evt->irq, &mct_tick0_event_irq);
-                else
-                        remove_irq(evt->irq, &mct_tick1_event_irq);
-        else
-                disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
-}
-
-static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
-        .setup  = exynos4_local_timer_setup,
-        .stop   = exynos4_local_timer_stop,
-};
-#endif /* CONFIG_LOCAL_TIMERS */
-
-static void __init exynos4_timer_resources(void)
-{
-        struct clk *mct_clk;
-        mct_clk = clk_get(NULL, "xtal");
-
-        clk_rate = clk_get_rate(mct_clk);
-
-#ifdef CONFIG_LOCAL_TIMERS
-        if (mct_int_type == MCT_INT_PPI) {
-                int err;
-
-                err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
-                                         exynos4_mct_tick_isr, "MCT",
-                                         &percpu_mct_tick);
-                WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                     EXYNOS_IRQ_MCT_LOCALTIMER, err);
-        }
-
-        local_timer_register(&exynos4_mct_tick_ops);
-#endif /* CONFIG_LOCAL_TIMERS */
-}
-
-void __init exynos4_timer_init(void)
-{
-        if (soc_is_exynos5440()) {
-                arch_timer_of_register();
-                return;
-        }
-
-        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
-                mct_int_type = MCT_INT_SPI;
-        else
-                mct_int_type = MCT_INT_PPI;
-
-        exynos4_timer_resources();
-        exynos4_clocksource_init();
-        exynos4_clockevent_init();
-}
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 2612eeaa5889..a4d4664894e1 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -445,16 +445,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -606,6 +613,8 @@ static void __init omap_3430sdp_init(void)
         board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 67447bd4564f..20d6d8189240 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -53,16 +53,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 126,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 126,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -199,6 +206,8 @@ static void __init omap_sdp_init(void)
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 7d3358b2e593..fc53911d0d13 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -47,15 +47,17 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_USB_NRESET,
+                .vcc_gpio = GPIO_USB_POWER,
+                .vcc_polarity = 1,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = GPIO_USB_NRESET,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static struct mtd_partition crane_nand_partitions[] = {
@@ -131,13 +133,7 @@ static void __init am3517_crane_init(void)
                 return;
         }
 
-        ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
-                               "usb_ehci_enable");
-        if (ret < 0) {
-                pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
-                return;
-        }
-
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 1d6c28872505..c29d2e743688 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -273,6 +273,14 @@ static __init void am3517_evm_mcbsp1_init(void)
         omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -281,12 +289,6 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 #else
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
 #endif
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -348,7 +350,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-
 static void __init am3517_evm_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -360,6 +361,8 @@ static void __init am3517_evm_init(void)
 
         /* Configure GPIO for EHCI port */
         omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
         /* DSS */
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index bccd3e51fecb..e0ed8c07fc54 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -418,15 +418,22 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 6,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 7,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = OMAP_MAX_GPIO_LINES + 6,
-        .reset_gpio_port[1]  = OMAP_MAX_GPIO_LINES + 7,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void  __init cm_t35_init_usbh(void)
@@ -443,6 +450,7 @@ static void  __init cm_t35_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a66da808cc4a..4eb5e6f2f7f5 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -188,15 +188,22 @@ static inline void cm_t3517_init_rtc(void) {}
 #define HSUSB2_RESET_GPIO       (147)
 #define USB_HUB_RESET_GPIO      (152)
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = HSUSB1_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = HSUSB2_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = HSUSB1_RESET_GPIO,
-        .reset_gpio_port[1]  = HSUSB2_RESET_GPIO,
-        .reset_gpio_port[2]  = -EINVAL,
 };
 
 static int __init cm_t3517_init_usbh(void)
@@ -213,6 +220,7 @@ static int __init cm_t3517_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&cm_t3517_ehci_pdata);
 
         return 0;
@@ -324,6 +332,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = cm_t3517_init,
         .init_late      = am35xx_init_late,
-        .init_time      = omap3_gp_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 12d2126a2382..e44b804f75ae 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -436,15 +436,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index e54a48060198..78813b397209 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -140,7 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
         .init_irq       = omap_intc_of_init,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
-        .init_time      = omap3_am33xx_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .dt_compat      = am33xx_boards_compat,
         .restart        = am33xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index e979d48270c9..b54562d1235e 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -527,26 +527,28 @@ static void __init igep_i2c_init(void)
         omap3_pmic_init("twl4030", &igep_twldata);
 }
 
+static struct usbhs_phy_data igep2_phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = IGEP2_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
+static struct usbhs_phy_data igep3_phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = IGEP3_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
-        .reset_gpio_port[1] = -EINVAL,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -642,8 +644,10 @@ static void __init igep_init(void)
         if (machine_is_igep0020()) {
                 omap_display_init(&igep2_dss_data);
                 igep2_init_smsc911x();
+                usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
                 usbhs_init(&igep2_usbhs_bdata);
         } else {
+                usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
                 usbhs_init(&igep3_usbhs_bdata);
         }
 }
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index fff141330a63..6de78605c0af 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,6 +33,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -277,6 +278,21 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = {
 
 static struct gpio_led gpio_leds[];
 
+/* PHY's VCC regulator might be added later, so flag that we need it */
+static struct nop_usb_xceiv_platform_data hsusb2_phy_data = {
+        .needs_vcc = true,
+};
+
+static struct usbhs_phy_data phy_data[] = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -1,         /* updated in beagle_twl_gpio_setup */
+                .vcc_polarity = 1,      /* updated in beagle_twl_gpio_setup */
+                .platform_data = &hsusb2_phy_data,
+        },
+};
+
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -318,9 +334,11 @@ static int beagle_twl_gpio_setup(struct device *dev,
         }
         dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
 
-        gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
-                        "nEN_USB_PWR");
+        /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
+        phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
+        phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         return 0;
 }
 
@@ -453,15 +471,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -543,7 +553,9 @@ static void __init omap3_beagle_init(void)
 
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
         usbhs_init(&usbhs_bdata);
+
         board_nand_init(omap3beagle_nand_partitions,
                         ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
                         NAND_BUSWIDTH_16, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 233a0d528fcf..4f1bbc3cc29b 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -496,7 +496,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
 static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
         REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"),    /* OMAP ISP */
         REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"),    /* OMAP ISP */
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
         REGULATOR_SUPPLY("vaux2", NULL),
 };
 
@@ -539,17 +539,16 @@ static int __init omap3_evm_i2c_init(void)
         return 0;
 }
 
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = -1,       /* set at runtime */
+                .vcc_gpio = -EINVAL,
+        },
+};
 
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        /* PHY reset GPIO will be runtime programmed based on EVM version */
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -725,7 +724,7 @@ static void __init omap3_evm_init(void)
 
                 /* setup EHCI phy reset config */
                 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
-                usbhs_bdata.reset_gpio_port[1] = 21;
+                phy_data[0].reset_gpio = 21;
 
                 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
                 musb_board_data.power = 500;
@@ -733,10 +732,12 @@ static void __init omap3_evm_init(void)
         } else {
                 /* setup EHCI phy reset on MDC */
                 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
-                usbhs_bdata.reset_gpio_port[1] = 135;
+                phy_data[0].reset_gpio = 135;
         }
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(&musb_board_data);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3evm_nand_partitions,
                         ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 2bba362148a0..1004d2aaa68f 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -346,7 +346,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
 };
 
 static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
 };
 
 /* ads7846 on SPI and 2 nub controllers on I2C */
@@ -561,6 +561,14 @@ fail:
         printk(KERN_ERR "wl1251 board initialisation failed\n");
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 16,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
@@ -569,15 +577,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 16,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -601,7 +601,10 @@ static void __init omap3pandora_init(void)
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
         omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
+
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
         gpmc_nand_init(&pandora_nand_data, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 495b989f9040..8afbba0923d6 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -357,19 +357,20 @@ static int __init omap3_stalker_i2c_init(void)
 
 #define OMAP3_STALKER_TS_GPIO   175
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 21,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_stalker_devices[] __initdata = {
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = 21,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -406,6 +407,8 @@ static void __init omap3_stalker_init(void)
         omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
 
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index bcd44fbcd877..7da48bc42bbf 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -305,21 +305,22 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
         &leds_gpio,
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void omap3_touchbook_poweroff(void)
@@ -368,6 +369,8 @@ static void __init omap3_touchbook_init(void)
         omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3touchbook_nand_partitions,
                         ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b02c2f00609b..a71ad345f20d 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -31,6 +31,7 @@
 #include <linux/ti_wilink_st.h>
 #include <linux/usb/musb.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include <linux/wl12xx.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
@@ -132,6 +133,22 @@ static struct platform_device btwilink_device = {
         .id     = -1,
 };
 
+/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
+static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
+        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
+        .clk_rate = 19200000,
+};
+
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_HUB_NRESET,
+                .vcc_gpio = GPIO_HUB_POWER,
+                .vcc_polarity = 1,
+                .platform_data = &hsusb1_phy_data,
+        },
+};
+
 static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
         &wl1271_device,
@@ -142,49 +159,19 @@ static struct platform_device *panda_devices[] __initdata = {
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = false,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
-};
-
-static struct gpio panda_ehci_gpios[] __initdata = {
-        { GPIO_HUB_POWER,       GPIOF_OUT_INIT_LOW,  "hub_power"  },
-        { GPIO_HUB_NRESET,      GPIOF_OUT_INIT_LOW,  "hub_nreset" },
 };
 
 static void __init omap4_ehci_init(void)
 {
         int ret;
-        struct clk *phy_ref_clk;
 
         /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        phy_ref_clk = clk_get(NULL, "auxclk3_ck");
-        if (IS_ERR(phy_ref_clk)) {
-                pr_err("Cannot request auxclk3\n");
-                return;
-        }
-        clk_set_rate(phy_ref_clk, 19200000);
-        clk_prepare_enable(phy_ref_clk);
-
-        /* disable the power to the usb hub prior to init and reset phy+hub */
-        ret = gpio_request_array(panda_ehci_gpios,
-                                 ARRAY_SIZE(panda_ehci_gpios));
-        if (ret) {
-                pr_err("Unable to initialize EHCI power/reset\n");
-                return;
-        }
-
-        gpio_export(GPIO_HUB_POWER, 0);
-        gpio_export(GPIO_HUB_NRESET, 0);
-        gpio_set_value(GPIO_HUB_NRESET, 1);
+        ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
+        if (ret)
+                pr_err("Failed to add main_clk alias to auxclk3_ck\n");
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
-
-        /* enable power to hub */
-        gpio_set_value(GPIO_HUB_POWER, 1);
 }
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 630833235cbc..f9101407cd56 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -457,14 +457,16 @@ static int __init overo_spi_init(void)
         return 0;
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = OVERO_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = OVERO_GPIO_USBH_NRESET,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -501,6 +503,8 @@ static void __init overo_init(void)
                         ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         overo_spi_init();
         overo_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 5e4d4c9fe61a..1a3dd865d8eb 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -92,14 +92,16 @@ static struct mtd_partition zoom_nand_partitions[] = {
         },
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = ZOOM3_EHCI_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0]           = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1]           = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2]           = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset              = true,
-        .reset_gpio_port[0]     = -EINVAL,
-        .reset_gpio_port[1]     = ZOOM3_EHCI_RESET_GPIO,
-        .reset_gpio_port[2]     = -EINVAL,
 };
 
 static void __init omap_zoom_init(void)
@@ -109,6 +111,8 @@ static void __init omap_zoom_init(void)
         } else if (machine_is_omap_zoom3()) {
                 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
                 omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
+
+                usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
                 usbhs_init(&usbhs_bdata);
         }
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index df00e7580aa7..d555cf2459e1 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -82,8 +82,7 @@ extern void omap2_init_common_infrastructure(void);
 extern void omap2_sync32k_timer_init(void);
 extern void omap3_sync32k_timer_init(void);
 extern void omap3_secure_sync32k_timer_init(void);
-extern void omap3_gp_gptimer_timer_init(void);
-extern void omap3_am33xx_gptimer_timer_init(void);
+extern void omap3_gptimer_timer_init(void);
 extern void omap4_local_timer_init(void);
 extern void omap5_realtime_timer_init(void);
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index afc1e8c32d6c..d9c27195caf0 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime(
         t.cs_wr_off = gpmc_t->cs_wr_off;
         t.wr_cycle = gpmc_t->wr_cycle;
 
-        /* Configure GPMC */
-        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
-        else
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                        GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
-        gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
         if (err)
                 return err;
@@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                    struct gpmc_timings *gpmc_t)
 {
         int err = 0;
+        struct gpmc_settings s;
         struct device *dev = &gpmc_nand_device.dev;
 
+        memset(&s, 0, sizeof(struct gpmc_settings));
+
         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
                                 (unsigned long *)&gpmc_nand_resource[0].start);
         if (err < 0) {
-                dev_err(dev, "Cannot request GPMC CS\n");
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_nand_data->cs, err);
                 return err;
         }
 
@@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                         return err;
                 }
-        }
 
-        /* Enable RD PIN Monitoring Reg */
-        if (gpmc_nand_data->dev_ready) {
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
+                if (gpmc_nand_data->of_node) {
+                        gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
+                } else {
+                        s.device_nand = true;
+
+                        /* Enable RD PIN Monitoring Reg */
+                        if (gpmc_nand_data->dev_ready) {
+                                s.wait_on_read = true;
+                                s.wait_on_write = true;
+                        }
+                }
+
+                if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                        s.device_width = GPMC_DEVWIDTH_16BIT;
+                else
+                        s.device_width = GPMC_DEVWIDTH_8BIT;
+
+                err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
+                if (err < 0)
+                        goto out_free_cs;
+
+                err = gpmc_configure(GPMC_CONFIG_WP, 0);
+                if (err < 0)
+                        goto out_free_cs;
         }
 
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 0d75889c0a6f..64b5a8346982 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = {
         .resource       = &gpmc_onenand_resource,
 };
 
-static struct gpmc_timings omap2_onenand_calc_async_timings(void)
+static struct gpmc_settings onenand_async = {
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings onenand_sync = {
+        .burst_read     = true,
+        .burst_wrap     = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+        .wait_pin       = 0,
+};
+
+static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
-
         const int t_cer = 15;
         const int t_avdp = 12;
         const int t_aavdh = 7;
@@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
         dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
         dev_t.t_avdp_w = dev_t.t_avdp_r;
         dev_t.t_aavdh = t_aavdh * 1000;
@@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
         dev_t.t_wpl = t_wpl * 1000;
         dev_t.t_wph = t_wph * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
-{
-        /* Configure GPMC for asynchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_async, &dev_t);
 }
 
 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
@@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
         return freq;
 }
 
-static struct gpmc_timings
-omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
-                                int freq)
+static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
+                                            unsigned int flags,
+                                            int freq)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
         const int t_cer  = 15;
         const int t_avdp = 12;
         const int t_cez  = 20; /* max of t_cez, t_oez */
@@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int div, gpmc_clk_ns;
 
-        if (cfg->flags & ONENAND_SYNC_READ)
+        if (flags & ONENAND_SYNC_READ)
                 onenand_flags = ONENAND_FLAG_SYNCREAD;
-        else if (cfg->flags & ONENAND_SYNC_READWRITE)
+        else if (flags & ONENAND_SYNC_READWRITE)
                 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 
         switch (freq) {
@@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         /* Set synchronous read timings */
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
+        if (onenand_flags & ONENAND_FLAG_SYNCREAD)
+                onenand_sync.sync_read = true;
         if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-                dev_t.sync_write = true;
+                onenand_sync.sync_write = true;
+                onenand_sync.burst_write = true;
         } else {
                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
                 dev_t.t_wpl = t_wpl * 1000;
@@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         dev_t.cyc_aavdh_oe = 1;
         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
-{
-        unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
-        unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
-
-        /* Configure GPMC for synchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_WRAPBURST_SUPP |
-                          GPMC_CONFIG1_READMULTIPLE_SUPP |
-                          (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
-                          GPMC_CONFIG1_PAGE_LEN(2) |
-                          (cpu_is_omap34xx() ? 0 :
-                                (GPMC_CONFIG1_WAIT_READ_MON |
-                                 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_DEVICETYPE_NOR |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_sync, &dev_t);
 }
 
 static int omap2_onenand_setup_async(void __iomem *onenand_base)
@@ -298,11 +272,19 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
         struct gpmc_timings t;
         int ret;
 
+        if (gpmc_onenand_data->of_node)
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_async);
+
         omap2_onenand_set_async_mode(onenand_base);
 
-        t = omap2_onenand_calc_async_timings();
+        omap2_onenand_calc_async_timings(&t);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
+        if (ret < 0)
+                return ret;
 
-        ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
         if (ret < 0)
                 return ret;
 
@@ -322,9 +304,25 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
                 set_onenand_cfg(onenand_base);
         }
 
-        t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
+        if (gpmc_onenand_data->of_node) {
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_sync);
+        } else {
+                /*
+                 * FIXME: Appears to be legacy code from initial ONENAND commit.
+                 * Unclear what boards this is for and if this can be removed.
+                 */
+                if (!cpu_is_omap34xx())
+                        onenand_sync.wait_on_read = true;
+        }
 
-        ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
+        omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
+        if (ret < 0)
+                return ret;
+
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
         if (ret < 0)
                 return ret;
 
@@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
         int err;
+        struct device *dev = &gpmc_onenand_device.dev;
 
         gpmc_onenand_data = _onenand_data;
         gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
@@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 
         if (cpu_is_omap24xx() &&
                         (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
-                printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
+                dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
                 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
         }
@@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
         err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
                                 (unsigned long *)&gpmc_onenand_resource.start);
         if (err < 0) {
-                pr_err("%s: Cannot request GPMC CS\n", __func__);
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_onenand_data->cs, err);
                 return;
         }
 
@@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                                                         ONENAND_IO_SIZE - 1;
 
         if (platform_device_register(&gpmc_onenand_device) < 0) {
-                pr_err("%s: Unable to register OneNAND device\n", __func__);
+                dev_err(dev, "Unable to register OneNAND device\n");
                 gpmc_cs_free(gpmc_onenand_data->cs);
                 return;
         }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 11d0b756f098..61a063595e66 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = {
         .resource       = gpmc_smc91x_resources,
 };
 
+static struct gpmc_settings smc91x_settings = {
+        .device_width = GPMC_DEVWIDTH_16BIT,
+};
+
 /*
  * Set the gpmc timings for smc91c96. The timings are taken
  * from the data sheet available at:
@@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void)
         const int t7 = 5;       /* Figure 12.4 write */
         const int t8 = 5;       /* Figure 12.4 write */
         const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
-        u32 l;
-
-        l = GPMC_CONFIG1_DEVICESIZE_16;
-        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
-                l |= GPMC_CONFIG1_MUXADDDATA;
-        if (gpmc_cfg->flags & GPMC_READ_MON)
-                l |= GPMC_CONFIG1_WAIT_READ_MON;
-        if (gpmc_cfg->flags & GPMC_WRITE_MON)
-                l |= GPMC_CONFIG1_WAIT_WRITE_MON;
-        if (gpmc_cfg->wait_pin)
-                l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
-        gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
 
         /*
          * FIXME: Calculate the address and data bus muxed timings.
@@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void)
         dev_t.t_cez_w = t4_w * 1000;
         dev_t.t_wr_cycle = (t20 - t3) * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
 
         return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
 }
@@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
         gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
         gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
 
+        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
+                smc91x_settings.mux_add_data = GPMC_MUX_AD;
+        if (gpmc_cfg->flags & GPMC_READ_MON)
+                smc91x_settings.wait_on_read = true;
+        if (gpmc_cfg->flags & GPMC_WRITE_MON)
+                smc91x_settings.wait_on_write = true;
+        if (gpmc_cfg->wait_pin)
+                smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
+        ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
+        if (ret < 0)
+                goto free1;
+
         if (gpmc_cfg->retime) {
                 ret = gpmc_cfg->retime();
                 if (ret != 0)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6de31739b45c..ed946df5ad8a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_mtd.h>
 #include <linux/of_device.h>
 #include <linux/mtd/nand.h>
@@ -91,9 +92,7 @@
 #define GPMC_CS_SIZE            0x30
 #define GPMC_BCH_SIZE           0x10
 
-#define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
-#define BOOT_ROM_SPACE          0x100000        /* 1MB */
 
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
@@ -107,6 +106,9 @@
 
 #define GPMC_HAS_WR_ACCESS              0x1
 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+#define GPMC_HAS_MUX_AAD                0x4
+
+#define GPMC_NR_WAITPINS                4
 
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
@@ -153,6 +155,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
         __raw_writel(val, reg_addr);
 }
 
-u32 gpmc_cs_read_reg(int cs, int idx)
+static u32 gpmc_cs_read_reg(int cs, int idx)
 {
         void __iomem *reg_addr;
 
@@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
-unsigned long gpmc_get_fclk_period(void)
+static unsigned long gpmc_get_fclk_period(void)
 {
         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 
@@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void)
         return rate;
 }
 
-unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 {
         unsigned long tick_ps;
 
@@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
-unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 {
         unsigned long tick_ps;
 
@@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
         return ticks * gpmc_get_fclk_period() / 1000;
 }
 
-unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
-{
-        unsigned long ticks = gpmc_ns_to_ticks(time_ns);
-
-        return ticks * gpmc_get_fclk_period() / 1000;
-}
-
 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 {
         return ticks * gpmc_get_fclk_period();
@@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
         return 0;
 }
 
-static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
+static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 {
         u32 l;
         u32 mask;
 
+        /*
+         * Ensure that base address is aligned on a
+         * boundary equal to or greater than size.
+         */
+        if (base & (size - 1))
+                return -EINVAL;
+
         mask = (1 << GPMC_SECTION_SHIFT) - size;
         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
         l &= ~0x3f;
@@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
         l |= GPMC_CONFIG7_CSVALID;
         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
+
+        return 0;
 }
 
 static void gpmc_cs_disable_mem(int cs)
@@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs)
         return l & GPMC_CONFIG7_CSVALID;
 }
 
-int gpmc_cs_set_reserved(int cs, int reserved)
+static void gpmc_cs_set_reserved(int cs, int reserved)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         gpmc_cs_map &= ~(1 << cs);
         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-
-        return 0;
 }
 
-int gpmc_cs_reserved(int cs)
+static bool gpmc_cs_reserved(int cs)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         return gpmc_cs_map & (1 << cs);
 }
 
@@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs)
         return r;
 }
 
+/**
+ * gpmc_cs_remap - remaps a chip-select physical base address
+ * @cs:         chip-select to remap
+ * @base:       physical base address to re-map chip-select to
+ *
+ * Re-maps a chip-select to a new physical base address specified by
+ * "base". Returns 0 on success and appropriate negative error code
+ * on failure.
+ */
+static int gpmc_cs_remap(int cs, u32 base)
+{
+        int ret;
+        u32 old_base, size;
+
+        if (cs > GPMC_CS_NUM)
+                return -ENODEV;
+        gpmc_cs_get_memconf(cs, &old_base, &size);
+        if (base == old_base)
+                return 0;
+        gpmc_cs_disable_mem(cs);
+        ret = gpmc_cs_delete_mem(cs);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_insert_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_enable_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
         if (r < 0)
                 goto out;
 
-        gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        if (r < 0) {
+                release_resource(res);
+                goto out;
+        }
+
         *base = res->start;
         gpmc_cs_set_reserved(cs, 1);
 out:
@@ -561,16 +596,14 @@ void gpmc_cs_free(int cs)
 EXPORT_SYMBOL(gpmc_cs_free);
 
 /**
- * gpmc_cs_configure - write request to configure gpmc
- * @cs: chip select number
+ * gpmc_configure - write request to configure gpmc
  * @cmd: command type
  * @wval: value to write
  * @return status of the operation
  */
-int gpmc_cs_configure(int cs, int cmd, int wval)
+int gpmc_configure(int cmd, int wval)
 {
-        int err = 0;
-        u32 regval = 0;
+        u32 regval;
 
         switch (cmd) {
         case GPMC_ENABLE_IRQ:
@@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
                 gpmc_write_reg(GPMC_CONFIG, regval);
                 break;
 
-        case GPMC_CONFIG_RDY_BSY:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                if (wval)
-                        regval |= WR_RD_PIN_MONITORING;
-                else
-                        regval &= ~WR_RD_PIN_MONITORING;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_SIZE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                /* clear 2 target bits */
-                regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
-
-                /* set the proper value */
-                regval |= GPMC_CONFIG1_DEVICESIZE(wval);
-
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_TYPE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                regval |= GPMC_CONFIG1_DEVICETYPE(wval);
-                if (wval == GPMC_DEVICETYPE_NOR)
-                        regval |= GPMC_CONFIG1_MUXADDDATA;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
         default:
-                printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
-                err = -EINVAL;
+                pr_err("%s: command not supported\n", __func__);
+                return -EINVAL;
         }
 
-        return err;
+        return 0;
 }
-EXPORT_SYMBOL(gpmc_cs_configure);
+EXPORT_SYMBOL(gpmc_configure);
 
 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 {
@@ -781,16 +785,16 @@ static void gpmc_mem_exit(void)
 
 }
 
-static int gpmc_mem_init(void)
+static void gpmc_mem_init(void)
 {
-        int cs, rc;
-        unsigned long boot_rom_space = 0;
+        int cs;
 
-        /* never allocate the first page, to facilitate bug detection;
-         * even if we didn't boot from ROM.
+        /*
+         * The first 1MB of GPMC address space is typically mapped to
+         * the internal ROM. Never allocate the first page, to
+         * facilitate bug detection; even if we didn't boot from ROM.
          */
-        boot_rom_space = BOOT_ROM_SPACE;
-        gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
+        gpmc_mem_root.start = SZ_1M;
         gpmc_mem_root.end = GPMC_MEM_END;
 
         /* Reserve all regions that has been set up by bootloader */
@@ -800,16 +804,12 @@ static int gpmc_mem_init(void)
                 if (!gpmc_cs_mem_enabled(cs))
                         continue;
                 gpmc_cs_get_memconf(cs, &base, &size);
-                rc = gpmc_cs_insert_mem(cs, base, size);
-                if (rc < 0) {
-                        while (--cs >= 0)
-                                if (gpmc_cs_mem_enabled(cs))
-                                        gpmc_cs_delete_mem(cs);
-                        return rc;
+                if (gpmc_cs_insert_mem(cs, base, size)) {
+                        pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
+                                __func__, cs, base, base + size);
+                        gpmc_cs_disable_mem(cs);
                 }
         }
-
-        return 0;
 }
 
 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
@@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
 
 /* XXX: can the cycles be avoided ? */
 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                       struct gpmc_device_timings *dev_t,
+                                       bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                         struct gpmc_device_timings *dev_t,
+                                         bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                                    struct gpmc_device_timings *dev_t,
+                                    bool sync)
 {
         u32 temp;
 
@@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
                                 gpmc_t->cs_on + dev_t->t_ce_avd);
         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
 
-        if (dev_t->sync_write || dev_t->sync_read)
+        if (sync)
                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
 
         return 0;
@@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
 }
 
 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                      struct gpmc_settings *gpmc_s,
+                      struct gpmc_device_timings *dev_t)
 {
+        bool mux = false, sync = false;
+
+        if (gpmc_s) {
+                mux = gpmc_s->mux_add_data ? true : false;
+                sync = (gpmc_s->sync_read || gpmc_s->sync_write);
+        }
+
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
-        gpmc_calc_common_timings(gpmc_t, dev_t);
+        gpmc_calc_common_timings(gpmc_t, dev_t, sync);
 
-        if (dev_t->sync_read)
-                gpmc_calc_sync_read_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_read)
+                gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_read_timings(gpmc_t, dev_t);
+                gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
 
-        if (dev_t->sync_write)
-                gpmc_calc_sync_write_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_write)
+                gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_write_timings(gpmc_t, dev_t);
+                gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
 
         /* TODO: remove, see function definition */
         gpmc_convert_ps_to_ns(gpmc_t);
@@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
         return 0;
 }
 
+/**
+ * gpmc_cs_program_settings - programs non-timing related settings
+ * @cs:         GPMC chip-select to program
+ * @p:          pointer to GPMC settings structure
+ *
+ * Programs non-timing related settings for a GPMC chip-select, such as
+ * bus-width, burst configuration, etc. Function should be called once
+ * for each chip-select that is being used and must be called before
+ * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
+ * register will be initialised to zero by this function. Returns 0 on
+ * success and appropriate negative error code on failure.
+ */
+int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
+{
+        u32 config1;
+
+        if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
+                pr_err("%s: invalid width %d!", __func__, p->device_width);
+                return -EINVAL;
+        }
+
+        /* Address-data multiplexing not supported for NAND devices */
+        if (p->device_nand && p->mux_add_data) {
+                pr_err("%s: invalid configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        if ((p->mux_add_data > GPMC_MUX_AD) ||
+            ((p->mux_add_data == GPMC_MUX_AAD) &&
+             !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
+                pr_err("%s: invalid multiplex configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
+        if (p->burst_read || p->burst_write) {
+                switch (p->burst_len) {
+                case GPMC_BURST_4:
+                case GPMC_BURST_8:
+                case GPMC_BURST_16:
+                        break;
+                default:
+                        pr_err("%s: invalid page/burst-length (%d)\n",
+                               __func__, p->burst_len);
+                        return -EINVAL;
+                }
+        }
+
+        if ((p->wait_on_read || p->wait_on_write) &&
+            (p->wait_pin > gpmc_nr_waitpins)) {
+                pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
+                return -EINVAL;
+        }
+
+        config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
+
+        if (p->sync_read)
+                config1 |= GPMC_CONFIG1_READTYPE_SYNC;
+        if (p->sync_write)
+                config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
+        if (p->wait_on_read)
+                config1 |= GPMC_CONFIG1_WAIT_READ_MON;
+        if (p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
+        if (p->wait_on_read || p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
+        if (p->device_nand)
+                config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
+        if (p->mux_add_data)
+                config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
+        if (p->burst_read)
+                config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
+        if (p->burst_write)
+                config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
+        if (p->burst_read || p->burst_write) {
+                config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
+                config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
+        }
+
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
+
+        return 0;
+}
+
 #ifdef CONFIG_OF
 static struct of_device_id gpmc_dt_ids[] = {
         { .compatible = "ti,omap2420-gpmc" },
@@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
 
+/**
+ * gpmc_read_settings_dt - read gpmc settings from device-tree
+ * @np:         pointer to device-tree node for a gpmc child device
+ * @p:          pointer to gpmc settings structure
+ *
+ * Reads the GPMC settings for a GPMC child device from device-tree and
+ * stores them in the GPMC settings structure passed. The GPMC settings
+ * structure is initialised to zero by this function and so any
+ * previously stored settings will be cleared.
+ */
+void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
+{
+        memset(p, 0, sizeof(struct gpmc_settings));
+
+        p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
+        p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
+        p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
+        of_property_read_u32(np, "gpmc,device-width", &p->device_width);
+        of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
+
+        if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
+                p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
+                p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
+                p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
+                if (!p->burst_read && !p->burst_write)
+                        pr_warn("%s: page/burst-length set but not used!\n",
+                                __func__);
+        }
+
+        if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
+                p->wait_on_read = of_property_read_bool(np,
+                                                        "gpmc,wait-on-read");
+                p->wait_on_write = of_property_read_bool(np,
+                                                         "gpmc,wait-on-write");
+                if (!p->wait_on_read && !p->wait_on_write)
+                        pr_warn("%s: read/write wait monitoring not enabled!\n",
+                                __func__);
+        }
+}
+
 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
                                                 struct gpmc_timings *gpmc_t)
 {
-        u32 val;
+        struct gpmc_bool_timings *p;
+
+        if (!np || !gpmc_t)
+                return;
 
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
         /* minimum clock period for syncronous mode */
-        if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
-                gpmc_t->sync_clk = val;
+        of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
 
         /* chip select timtings */
-        if (!of_property_read_u32(np, "gpmc,cs-on", &val))
-                gpmc_t->cs_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
-                gpmc_t->cs_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
-                gpmc_t->cs_wr_off = val;
+        of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
+        of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
+        of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
 
         /* ADV signal timings */
-        if (!of_property_read_u32(np, "gpmc,adv-on", &val))
-                gpmc_t->adv_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
-                gpmc_t->adv_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
-                gpmc_t->adv_wr_off = val;
+        of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
+        of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
+        of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
 
         /* WE signal timings */
-        if (!of_property_read_u32(np, "gpmc,we-on", &val))
-                gpmc_t->we_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,we-off", &val))
-                gpmc_t->we_off = val;
+        of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
+        of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
 
         /* OE signal timings */
-        if (!of_property_read_u32(np, "gpmc,oe-on", &val))
-                gpmc_t->oe_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,oe-off", &val))
-                gpmc_t->oe_off = val;
+        of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
+        of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
 
         /* access and cycle timings */
-        if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
-                gpmc_t->page_burst_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,access", &val))
-                gpmc_t->access = val;
-
-        if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
-                gpmc_t->rd_cycle = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
-                gpmc_t->wr_cycle = val;
-
-        /* only for OMAP3430 */
-        if (!of_property_read_u32(np, "gpmc,wr-access", &val))
-                gpmc_t->wr_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
-                gpmc_t->wr_data_mux_bus = val;
+        of_property_read_u32(np, "gpmc,page-burst-access-ns",
+                             &gpmc_t->page_burst_access);
+        of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
+        of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
+        of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
+        of_property_read_u32(np, "gpmc,bus-turnaround-ns",
+                             &gpmc_t->bus_turnaround);
+        of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
+                             &gpmc_t->cycle2cycle_delay);
+        of_property_read_u32(np, "gpmc,wait-monitoring-ns",
+                             &gpmc_t->wait_monitoring);
+        of_property_read_u32(np, "gpmc,clk-activation-ns",
+                             &gpmc_t->clk_activation);
+
+        /* only applicable to OMAP3+ */
+        of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
+        of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
+                             &gpmc_t->wr_data_mux_bus);
+
+        /* bool timing parameters */
+        p = &gpmc_t->bool_timings;
+
+        p->cycle2cyclediffcsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
+        p->cycle2cyclesamecsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
+        p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
+        p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
+        p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
+        p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
+        p->time_para_granularity =
+                of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
 #ifdef CONFIG_MTD_NAND
@@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
 }
 #endif
 
+/**
+ * gpmc_probe_generic_child - configures the gpmc for a child device
+ * @pdev:       pointer to gpmc platform device
+ * @child:      pointer to device-tree node for child device
+ *
+ * Allocates and configures a GPMC chip-select for a child device.
+ * Returns 0 on success and appropriate negative error code on failure.
+ */
+static int gpmc_probe_generic_child(struct platform_device *pdev,
+                                struct device_node *child)
+{
+        struct gpmc_settings gpmc_s;
+        struct gpmc_timings gpmc_t;
+        struct resource res;
+        unsigned long base;
+        int ret, cs;
+
+        if (of_property_read_u32(child, "reg", &cs) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        if (of_address_to_resource(child, 0, &res) < 0) {
+                dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        ret = gpmc_cs_request(cs, resource_size(&res), &base);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
+                return ret;
+        }
+
+        /*
+         * FIXME: gpmc_cs_request() will map the CS to an arbitary
+         * location in the gpmc address space. When booting with
+         * device-tree we want the NOR flash to be mapped to the
+         * location specified in the device-tree blob. So remap the
+         * CS to this location. Once DT migration is complete should
+         * just make gpmc_cs_request() map a specific address.
+         */
+        ret = gpmc_cs_remap(cs, res.start);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
+                        cs, res.start);
+                goto err;
+        }
+
+        gpmc_read_settings_dt(child, &gpmc_s);
+
+        ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
+        if (ret < 0)
+                goto err;
+
+        ret = gpmc_cs_program_settings(cs, &gpmc_s);
+        if (ret < 0)
+                goto err;
+
+        gpmc_read_timings_dt(child, &gpmc_t);
+        gpmc_cs_set_timings(cs, &gpmc_t);
+
+        if (of_platform_device_create(child, NULL, &pdev->dev))
+                return 0;
+
+        dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
+        ret = -ENODEV;
+
+err:
+        gpmc_cs_free(cs);
+
+        return ret;
+}
+
 static int gpmc_probe_dt(struct platform_device *pdev)
 {
         int ret;
@@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
         if (!of_id)
                 return 0;
 
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
+                                   &gpmc_nr_waitpins);
+        if (ret < 0) {
+                pr_err("%s: number of wait pins not found!\n", __func__);
+                return ret;
+        }
+
         for_each_node_by_name(child, "nand") {
                 ret = gpmc_probe_nand_child(pdev, child);
                 if (ret < 0) {
@@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev)
                         return ret;
                 }
         }
+
+        for_each_node_by_name(child, "nor") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
+        for_each_node_by_name(child, "ethernet") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
         return 0;
 }
 #else
@@ -1364,18 +1596,27 @@ static int gpmc_probe(struct platform_device *pdev)
         gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
+
+        /*
+         * FIXME: Once device-tree migration is complete the below flags
+         * should be populated based upon the device-tree compatible
+         * string. For now just use the IP revision. OMAP3+ devices have
+         * the wr_access and wr_data_mux_bus register fields. OMAP4+
+         * devices support the addr-addr-data multiplex protocol.
+         *
+         * GPMC IP revisions:
+         * - OMAP24xx                   = 2.0
+         * - OMAP3xxx                   = 5.0
+         * - OMAP44xx/54xx/AM335x       = 6.0
+         */
         if (GPMC_REVISION_MAJOR(l) > 0x4)
                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        if (GPMC_REVISION_MAJOR(l) > 0x5)
+                gpmc_capability |= GPMC_HAS_MUX_AAD;
         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
                  GPMC_REVISION_MINOR(l));
 
-        rc = gpmc_mem_init();
-        if (rc < 0) {
-                clk_disable_unprepare(gpmc_l3_clk);
-                clk_put(gpmc_l3_clk);
-                dev_err(gpmc_dev, "failed to reserve memory\n");
-                return rc;
-        }
+        gpmc_mem_init();
 
         if (gpmc_setup_irq() < 0)
                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
@@ -1383,6 +1624,9 @@ static int gpmc_probe(struct platform_device *pdev)
         /* Now the GPMC is initialised, unreserve the chip-selects */
         gpmc_cs_map = 0;
 
+        if (!pdev->dev.of_node)
+                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+
         rc = gpmc_probe_dt(pdev);
         if (rc < 0) {
                 clk_disable_unprepare(gpmc_l3_clk);
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index fe0a844d5007..707f6d58edd5 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -58,7 +58,7 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
@@ -73,6 +73,13 @@
 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
 #define GPMC_IRQ_COUNT_EVENT            0x02
 
+#define GPMC_BURST_4                    4       /* 4 word burst */
+#define GPMC_BURST_8                    8       /* 8 word burst */
+#define GPMC_BURST_16                   16      /* 16 word burst */
+#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
+#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
+#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
+#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
 
 /* bool type time settings */
 struct gpmc_bool_timings {
@@ -178,10 +185,6 @@ struct gpmc_device_timings {
         u8 cyc_wpl;     /* write deassertion time in cycles */
         u32 cyc_iaa;    /* initial access time in cycles */
 
-        bool mux;       /* address & data muxed */
-        bool sync_write;/* synchronous write */
-        bool sync_read; /* synchronous read */
-
         /* extra delays */
         bool ce_xdelay;
         bool avd_xdelay;
@@ -189,28 +192,40 @@ struct gpmc_device_timings {
         bool we_xdelay;
 };
 
+struct gpmc_settings {
+        bool burst_wrap;        /* enables wrap bursting */
+        bool burst_read;        /* enables read page/burst mode */
+        bool burst_write;       /* enables write page/burst mode */
+        bool device_nand;       /* device is NAND */
+        bool sync_read;         /* enables synchronous reads */
+        bool sync_write;        /* enables synchronous writes */
+        bool wait_on_read;      /* monitor wait on reads */
+        bool wait_on_write;     /* monitor wait on writes */
+        u32 burst_len;          /* page/burst length */
+        u32 device_width;       /* device bus width (8 or 16 bit) */
+        u32 mux_add_data;       /* multiplex address & data */
+        u32 wait_pin;           /* wait-pin to be used */
+};
+
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t);
+                             struct gpmc_settings *gpmc_s,
+                             struct gpmc_device_timings *dev_t);
 
 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
 
-extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
-extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
-extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
-extern unsigned long gpmc_get_fclk_period(void);
 
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
-extern u32 gpmc_cs_read_reg(int cs, int idx);
 extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-extern int gpmc_cs_set_reserved(int cs, int reserved);
-extern int gpmc_cs_reserved(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern int gpmc_cs_configure(int cs, int cmd, int wval);
+extern int gpmc_configure(int cmd, int wval);
+extern void gpmc_read_settings_dt(struct device_node *np,
+                                  struct gpmc_settings *p);
 
 #endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 63e6384fa72e..f12aa6c15da4 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -57,16 +57,6 @@
 #include "common.h"
 #include "powerdomain.h"
 
-/* Parent clocks, eventually these will come from the clock framework */
-
-#define OMAP2_MPU_SOURCE        "sys_ck"
-#define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
-#define OMAP4_MPU_SOURCE        "sys_clkin_ck"
-#define OMAP5_MPU_SOURCE        "sys_clkin"
-#define OMAP2_32K_SOURCE        "func_32k_ck"
-#define OMAP3_32K_SOURCE        "omap_32k_fck"
-#define OMAP4_32K_SOURCE        "sys_32k_ck"
-
 #define REALTIME_COUNTER_BASE                           0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
@@ -130,7 +120,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 }
 
 static struct clock_event_device clockevent_gpt = {
-        .name           = "gp_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 300,
         .set_next_event = omap2_gp_timer_set_next_event,
@@ -171,6 +160,12 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
                 if (property && !of_get_property(np, property, NULL))
                         continue;
 
+                if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
+                                  of_get_property(np, "ti,timer-dsp", NULL) ||
+                                  of_get_property(np, "ti,timer-pwm", NULL) ||
+                                  of_get_property(np, "ti,timer-secure", NULL)))
+                        continue;
+
                 of_add_property(np, &device_disabled);
                 return np;
         }
@@ -215,16 +210,17 @@ static u32 __init omap_dm_timer_get_errata(void)
 }
 
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
-                                                int gptimer_id,
-                                                const char *fck_source,
-                                                const char *property,
-                                                int posted)
+                                         const char *fck_source,
+                                         const char *property,
+                                         const char **timer_name,
+                                         int posted)
 {
         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
         const char *oh_name;
         struct device_node *np;
         struct omap_hwmod *oh;
         struct resource irq, mem;
+        struct clk *src;
         int r = 0;
 
         if (of_have_populated_dt()) {
@@ -244,10 +240,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
                 of_node_put(np);
         } else {
-                if (omap_dm_timer_reserve_systimer(gptimer_id))
+                if (omap_dm_timer_reserve_systimer(timer->id))
                         return -ENODEV;
 
-                sprintf(name, "timer%d", gptimer_id);
+                sprintf(name, "timer%d", timer->id);
                 oh_name = name;
         }
 
@@ -255,6 +251,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (!oh)
                 return -ENODEV;
 
+        *timer_name = oh->name;
+
         if (!of_have_populated_dt()) {
                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
                                                    &irq);
@@ -277,24 +275,24 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         /* After the dmtimer is using hwmod these clocks won't be needed */
         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
         if (IS_ERR(timer->fclk))
-                return -ENODEV;
+                return PTR_ERR(timer->fclk);
 
-        /* FIXME: Need to remove hard-coded test on timer ID */
-        if (gptimer_id != 12) {
-                struct clk *src;
-
-                src = clk_get(NULL, fck_source);
-                if (IS_ERR(src)) {
-                        r = -EINVAL;
-                } else {
-                        r = clk_set_parent(timer->fclk, src);
-                        if (r < 0)
-                                pr_warn("%s: %s cannot set source\n",
-                                        __func__, oh->name);
+        src = clk_get(NULL, fck_source);
+        if (IS_ERR(src))
+                return PTR_ERR(src);
+
+        if (clk_get_parent(timer->fclk) != src) {
+                r = clk_set_parent(timer->fclk, src);
+                if (r < 0) {
+                        pr_warn("%s: %s cannot set source\n", __func__,
+                                oh->name);
                         clk_put(src);
+                        return r;
                 }
         }
 
+        clk_put(src);
+
         omap_hwmod_setup_one(oh_name);
         omap_hwmod_enable(oh);
         __omap_dm_timer_init_regs(timer);
@@ -318,6 +316,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 {
         int res;
 
+        clkev.id = gptimer_id;
         clkev.errata = omap_dm_timer_get_errata();
 
         /*
@@ -327,8 +326,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
          */
         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 
-        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
-                                     OMAP_TIMER_POSTED);
+        res = omap_dm_timer_init_one(&clkev, fck_source, property,
+                                     &clockevent_gpt.name, OMAP_TIMER_POSTED);
         BUG_ON(res);
 
         omap2_gp_timer_irq.dev_id = &clkev;
@@ -342,8 +341,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
                                         3, /* Timer internal resynch latency */
                                         0xffffffff);
 
-        pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
-                gptimer_id, clkev.rate);
+        pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
+                clkev.rate);
 }
 
 /* Clocksource code */
@@ -360,7 +359,6 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs)
 }
 
 static struct clocksource clocksource_gpt = {
-        .name           = "gp_timer",
         .rating         = 300,
         .read           = clocksource_read_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
@@ -443,13 +441,16 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 }
 
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
-                                                const char *fck_source)
+                                                  const char *fck_source,
+                                                  const char *property)
 {
         int res;
 
+        clksrc.id = gptimer_id;
         clksrc.errata = omap_dm_timer_get_errata();
 
-        res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
+        res = omap_dm_timer_init_one(&clksrc, fck_source, property,
+                                     &clocksource_gpt.name,
                                      OMAP_TIMER_NONPOSTED);
         BUG_ON(res);
 
@@ -462,8 +463,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                 pr_err("Could not register clocksource %s\n",
                         clocksource_gpt.name);
         else
-                pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
-                        gptimer_id, clksrc.rate);
+                pr_info("OMAP clocksource: %s at %lu Hz\n",
+                        clocksource_gpt.name, clksrc.rate);
 }
 
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
@@ -488,7 +489,7 @@ static void __init realtime_counter_init(void)
                 pr_err("%s: ioremap failed\n", __func__);
                 return;
         }
-        sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
+        sys_clk = clk_get(NULL, "sys_clkin");
         if (IS_ERR(sys_clk)) {
                 pr_err("%s: failed to get system clock handle\n", __func__);
                 iounmap(base);
@@ -545,53 +546,52 @@ static inline void __init realtime_counter_init(void)
 #endif
 
 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
-                               clksrc_nr, clksrc_src)                   \
+                               clksrc_nr, clksrc_src, clksrc_prop)      \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
-        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
+        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
+                                        clksrc_prop);                   \
 }
 
 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
-                                clksrc_nr, clksrc_src)                  \
+                                clksrc_nr, clksrc_src, clksrc_prop)     \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
         if (use_gptimer_clksrc)                                         \
-                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
+                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
+                                                clksrc_prop);           \
         else                                                            \
                 omap2_sync32k_clocksource_init();                       \
 }
 
 #ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP2_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 
 #ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP3_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
+OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP3 */
 
-#ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP4_MPU_SOURCE);
-#endif /* CONFIG_SOC_AM33XX */
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
+OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
+                       1, "timer_sys_ck", "ti,timer-alwon");
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
+                               2, "sys_clkin_ck", NULL);
+#endif
 
 #ifdef CONFIG_ARCH_OMAP4
-OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 void __init omap4_local_timer_init(void)
@@ -620,13 +620,11 @@ void __init omap4_local_timer_init(void)
 #endif /* CONFIG_ARCH_OMAP4 */
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP5_MPU_SOURCE);
 void __init omap5_realtime_timer_init(void)
 {
         int err;
 
-        omap5_sync32k_timer_init();
+        omap4_sync32k_timer_init();
         realtime_counter_init();
 
         err = arch_timer_of_register();
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 5706bdccf45e..aa27d7f5cbb7 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -22,8 +22,12 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/dma-mapping.h>
-
-#include <asm/io.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/usb/phy.h>
 
 #include "soc.h"
 #include "omap_device.h"
@@ -526,3 +530,155 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 }
 
 #endif
+
+/* Template for PHY regulators */
+static struct fixed_voltage_config hsusb_reg_config = {
+        /* .supply_name filled later */
+        .microvolts = 3300000,
+        .gpio = -1,             /* updated later */
+        .startup_delay = 70000, /* 70msec */
+        .enable_high = 1,       /* updated later */
+        .enabled_at_boot = 0,   /* keep in RESET */
+        /* .init_data filled later */
+};
+
+static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */
+static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
+
+/**
+ * usbhs_add_regulator - Add a gpio based fixed voltage regulator device
+ * @name: name for the regulator
+ * @dev_id: device id of the device this regulator supplies power to
+ * @dev_supply: supply name that the device expects
+ * @gpio: GPIO number
+ * @polarity: 1 - Active high, 0 - Active low
+ */
+static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
+                                                int gpio, int polarity)
+{
+        struct regulator_consumer_supply *supplies;
+        struct regulator_init_data *reg_data;
+        struct fixed_voltage_config *config;
+        struct platform_device *pdev;
+        int ret;
+
+        supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
+        if (!supplies)
+                return -ENOMEM;
+
+        supplies->supply = dev_supply;
+        supplies->dev_name = dev_id;
+
+        reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
+        if (!reg_data)
+                return -ENOMEM;
+
+        reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
+        reg_data->consumer_supplies = supplies;
+        reg_data->num_consumer_supplies = 1;
+
+        config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
+                        GFP_KERNEL);
+        if (!config)
+                return -ENOMEM;
+
+        config->supply_name = name;
+        config->gpio = gpio;
+        config->enable_high = polarity;
+        config->init_data = reg_data;
+
+        /* create a regulator device */
+        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+        if (!pdev)
+                return -ENOMEM;
+
+        pdev->id = PLATFORM_DEVID_AUTO;
+        pdev->name = reg_name;
+        pdev->dev.platform_data = config;
+
+        ret = platform_device_register(pdev);
+        if (ret)
+                pr_err("%s: Failed registering regulator %s for %s\n",
+                                __func__, name, dev_id);
+
+        return ret;
+}
+
+int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
+{
+        char *rail_name;
+        int i, len;
+        struct platform_device *pdev;
+        char *phy_id;
+
+        /* the phy_id will be something like "nop_usb_xceiv.1" */
+        len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
+
+        for (i = 0; i < num_phys; i++) {
+
+                if (!phy->port) {
+                        pr_err("%s: Invalid port 0. Must start from 1\n",
+                                                __func__);
+                        continue;
+                }
+
+                /* do we need a NOP PHY device ? */
+                if (!gpio_is_valid(phy->reset_gpio) &&
+                        !gpio_is_valid(phy->vcc_gpio))
+                        continue;
+
+                /* create a NOP PHY device */
+                pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+                if (!pdev)
+                        return -ENOMEM;
+
+                pdev->id = phy->port;
+                pdev->name = nop_name;
+                pdev->dev.platform_data = phy->platform_data;
+
+                phy_id = kmalloc(len, GFP_KERNEL);
+                if (!phy_id)
+                        return -ENOMEM;
+
+                scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
+                                        pdev->id);
+
+                if (platform_device_register(pdev)) {
+                        pr_err("%s: Failed to register device %s\n",
+                                __func__,  phy_id);
+                        continue;
+                }
+
+                usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
+
+                /* Do we need RESET regulator ? */
+                if (gpio_is_valid(phy->reset_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "reset",
+                                                phy->reset_gpio, 1);
+                }
+
+                /* Do we need VCC regulator ? */
+                if (gpio_is_valid(phy->vcc_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "vcc",
+                                        phy->vcc_gpio, phy->vcc_polarity);
+                }
+
+                phy++;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index c5a3c6f9504e..e832bc7b8e2d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/err.h>
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/errno.h>
@@ -26,6 +27,24 @@
 static u8               async_cs, sync_cs;
 static unsigned         refclk_psec;
 
+static struct gpmc_settings tusb_async = {
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings tusb_sync = {
+        .burst_read     = true,
+        .burst_write    = true,
+        .sync_read      = true,
+        .sync_write     = true,
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
 
 /* NOTE:  timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
 
@@ -37,8 +56,6 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-
         dev_t.t_ceasu = 8 * 1000;
         dev_t.t_avdasu = t_acsnh_advnh - 7000;
         dev_t.t_ce_avd = 1000;
@@ -52,7 +69,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
         dev_t.t_wpl = 300;
         dev_t.cyc_aavdh_we = 1;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_async, &dev_t);
 
         return gpmc_cs_set_timings(async_cs, &t);
 }
@@ -65,10 +82,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
-        dev_t.sync_write = true;
-
         dev_t.clk = 11100;
         dev_t.t_bacc = 1000;
         dev_t.t_ces = 1000;
@@ -84,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
         dev_t.cyc_wpl = 6;
         dev_t.t_ce_rdyz = 7000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_sync, &dev_t);
 
         return gpmc_cs_set_timings(sync_cs, &t);
 }
@@ -165,18 +178,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
+        tusb_async.wait_pin = waitpin;
         async_cs = async;
-        gpmc_cs_write_reg(async, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_READTYPE_ASYNC
-                        | GPMC_CONFIG1_WRITETYPE_ASYNC
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA);
 
+        status = gpmc_cs_program_settings(async_cs, &tusb_async);
+        if (status < 0)
+                return status;
 
         /* SYNC region, primarily for DMA */
         status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
@@ -186,21 +193,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
+        tusb_sync.wait_pin = waitpin;
         sync_cs = sync;
-        gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_READMULTIPLE_SUPP
-                        | GPMC_CONFIG1_READTYPE_SYNC
-                        | GPMC_CONFIG1_WRITEMULTIPLE_SUPP
-                        | GPMC_CONFIG1_WRITETYPE_SYNC
-                        | GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA
-                        /* fclk divider gets set later */
-                        );
+
+        status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
+        if (status < 0)
+                return status;
 
         /* IRQ */
         status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
index 3319f5cf47a3..e7261ebcf7b0 100644
--- a/arch/arm/mach-omap2/usb.h
+++ b/arch/arm/mach-omap2/usb.h
@@ -53,8 +53,17 @@
 #define USBPHY_OTGSESSEND_EN    (1 << 20)
 #define USBPHY_DATA_POLARITY    (1 << 23)
 
+struct usbhs_phy_data {
+        int port;               /* 1 indexed port number */
+        int reset_gpio;
+        int vcc_gpio;
+        bool vcc_polarity;      /* 1 active high, 0 active low */
+        void *platform_data;
+};
+
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
+extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys);
 
 extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 8d5fa6ece014..f2f7088bfd22 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,6 +30,7 @@ config CPU_S3C2410
         select S3C2410_CLOCK
         select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
@@ -40,6 +41,7 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_DMA if S3C24XX_DMA
         select S3C2412_PM if PM
+        select SAMSUNG_HRT
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
@@ -51,6 +53,7 @@ config CPU_S3C2416
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2416 SoC from the S3C24XX line
 
@@ -61,6 +64,7 @@ config CPU_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2440_DMA if S3C24XX_DMA
+        select SAMSUNG_HRT
         help
           Support for S3C2440 Samsung Mobile CPU based systems.
 
@@ -70,6 +74,7 @@ config CPU_S3C2442
         select CPU_LLSERIAL_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2442 Samsung Mobile CPU based systems.
 
@@ -84,6 +89,7 @@ config CPU_S3C2443
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
@@ -395,6 +401,7 @@ config S3C2412_DMA
 config S3C2412_PM
         bool
         select S3C2412_PM_SLEEP
+        select SAMSUNG_WAKEMASK
         help
           Internal config node to apply S3C2412 power management
 
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index af53d27d5c36..6f46ecfc8396 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 # core
 
-obj-y                           += common.o irq.o
+obj-y                           += common.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
@@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA)	+= dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
@@ -31,9 +31,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP)	+= sleep-s3c2412.o
 obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
 obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 8a2b4137ddb6..307c3714be55 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -21,6 +21,7 @@ extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
 extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
 #define s3c2410_init_uarts NULL
@@ -36,6 +37,7 @@ extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
 extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
 #define s3c2412_init_uarts NULL
@@ -73,6 +75,7 @@ extern void s3c244x_restart(char mode, const char *cmd);
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
 extern void s3c2440_map_io(void);
+extern void s3c2440_init_irq(void);
 #else
 #define s3c2440_init NULL
 #define s3c2440_map_io NULL
@@ -81,6 +84,7 @@ extern void s3c2440_map_io(void);
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
 extern void s3c2442_map_io(void);
+extern void s3c2442_init_irq(void);
 #else
 #define s3c2442_init NULL
 #define s3c2442_map_io NULL
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
deleted file mode 100644
index 6a21beeba1da..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-s3c2410/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for S3C2410-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* We have a problem that the INTOFFSET register does not always
- * show one interrupt. Occasionally we get two interrupts through
- * the prioritiser, and this causes the INTOFFSET register to show
- * what looks like the logical-or of the two interrupt numbers.
- *
- * Thanks to Klaus, Shannon, et al for helping to debug this problem
-*/
-
-#define INTPND          (0x10)
-#define INTOFFSET       (0x14)
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                mov     \base, #S3C24XX_VA_IRQ
-
-                @@ try the interrupt offset register, since it is there
-
-                ldr     \irqstat, [\base, #INTPND ]
-                teq     \irqstat, #0
-                beq     1002f
-                ldr     \irqnr, [\base, #INTOFFSET ]
-                mov     \tmp, #1
-                tst     \irqstat, \tmp, lsl \irqnr
-                bne     1001f
-
-                @@ the number specified is not a valid irq, so try
-                @@ and work it out for ourselves
-
-                mov     \irqnr, #0              @@ start here
-
-                @@ work out which irq (if any) we got
-
-                movs    \tmp, \irqstat, lsl#16
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr#16
-                tst     \irqstat, #0xff
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr#8
-                tst     \irqstat, #0xf
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr#4
-                tst     \irqstat, #0x3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr#2
-                tst     \irqstat, #0x1
-                addeq   \irqnr, \irqnr, #1
-
-                @@ we have the value
-1001:
-                adds    \irqnr, \irqnr, #IRQ_EINT0
-1002:
-                @@ exit here, Z flag unset if IRQ
-
-        .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index 1e73f5fa8659..b6dd4cb5a2ec 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -59,49 +59,53 @@
 #define IRQ_ADCPARENT  S3C2410_IRQ(31)
 
 /* interrupts generated from the external interrupts sources */
-#define IRQ_EINT4      S3C2410_IRQ(32)     /* 48 */
-#define IRQ_EINT5      S3C2410_IRQ(33)
-#define IRQ_EINT6      S3C2410_IRQ(34)
-#define IRQ_EINT7      S3C2410_IRQ(35)
-#define IRQ_EINT8      S3C2410_IRQ(36)
-#define IRQ_EINT9      S3C2410_IRQ(37)
-#define IRQ_EINT10     S3C2410_IRQ(38)
-#define IRQ_EINT11     S3C2410_IRQ(39)
-#define IRQ_EINT12     S3C2410_IRQ(40)
-#define IRQ_EINT13     S3C2410_IRQ(41)
-#define IRQ_EINT14     S3C2410_IRQ(42)
-#define IRQ_EINT15     S3C2410_IRQ(43)
-#define IRQ_EINT16     S3C2410_IRQ(44)
-#define IRQ_EINT17     S3C2410_IRQ(45)
-#define IRQ_EINT18     S3C2410_IRQ(46)
-#define IRQ_EINT19     S3C2410_IRQ(47)
-#define IRQ_EINT20     S3C2410_IRQ(48)     /* 64 */
-#define IRQ_EINT21     S3C2410_IRQ(49)
-#define IRQ_EINT22     S3C2410_IRQ(50)
-#define IRQ_EINT23     S3C2410_IRQ(51)
+#define IRQ_EINT0_2412 S3C2410_IRQ(32)
+#define IRQ_EINT1_2412 S3C2410_IRQ(33)
+#define IRQ_EINT2_2412 S3C2410_IRQ(34)
+#define IRQ_EINT3_2412 S3C2410_IRQ(35)
+#define IRQ_EINT4      S3C2410_IRQ(36)     /* 52 */
+#define IRQ_EINT5      S3C2410_IRQ(37)
+#define IRQ_EINT6      S3C2410_IRQ(38)
+#define IRQ_EINT7      S3C2410_IRQ(39)
+#define IRQ_EINT8      S3C2410_IRQ(40)
+#define IRQ_EINT9      S3C2410_IRQ(41)
+#define IRQ_EINT10     S3C2410_IRQ(42)
+#define IRQ_EINT11     S3C2410_IRQ(43)
+#define IRQ_EINT12     S3C2410_IRQ(44)
+#define IRQ_EINT13     S3C2410_IRQ(45)
+#define IRQ_EINT14     S3C2410_IRQ(46)
+#define IRQ_EINT15     S3C2410_IRQ(47)
+#define IRQ_EINT16     S3C2410_IRQ(48)
+#define IRQ_EINT17     S3C2410_IRQ(49)
+#define IRQ_EINT18     S3C2410_IRQ(50)
+#define IRQ_EINT19     S3C2410_IRQ(51)
+#define IRQ_EINT20     S3C2410_IRQ(52)     /* 68 */
+#define IRQ_EINT21     S3C2410_IRQ(53)
+#define IRQ_EINT22     S3C2410_IRQ(54)
+#define IRQ_EINT23     S3C2410_IRQ(55)
 
 #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
 #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
 
-#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
-#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
+#define IRQ_LCD_FIFO   S3C2410_IRQ(56)
+#define IRQ_LCD_FRAME  S3C2410_IRQ(57)
 
 /* IRQs for the interal UARTs, and ADC
  * these need to be ordered in number of appearance in the
  * SUBSRC mask register
 */
 
-#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+54)
+#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+58)
 
-#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 70 */
+#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 74 */
 #define IRQ_S3CUART_TX0         S3C2410_IRQSUB(1)
 #define IRQ_S3CUART_ERR0        S3C2410_IRQSUB(2)
 
-#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 73 */
+#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 77 */
 #define IRQ_S3CUART_TX1         S3C2410_IRQSUB(4)
 #define IRQ_S3CUART_ERR1        S3C2410_IRQSUB(5)
 
-#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 76 */
+#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 80 */
 #define IRQ_S3CUART_TX2         S3C2410_IRQSUB(7)
 #define IRQ_S3CUART_ERR2        S3C2410_IRQSUB(8)
 
@@ -136,7 +140,7 @@
 
 /* second interrupt-register of s3c2416/s3c2450 */
 
-#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 54 + 29)
+#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 58 + 29)
 #define IRQ_S3C2416_2D          S3C2416_IRQ(0)
 #define IRQ_S3C2416_IIC1        S3C2416_IRQ(1)
 #define IRQ_S3C2416_RESERVED2   S3C2416_IRQ(2)
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
deleted file mode 100644
index 67d763178d3f..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/irq.c
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/irq.h>
-#include <plat/pm.h>
-
-#include "s3c2412-power.h"
-
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
-
-/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
- * having them turn up in both the INT* and the EINT* registers. Whilst
- * both show the status, they both now need to be acked when the IRQs
- * go off.
-*/
-
-static void
-s3c2412_irq_mask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask | bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-}
-
-static inline void
-s3c2412_irq_ack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static inline void
-s3c2412_irq_maskack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask|bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static void
-s3c2412_irq_unmask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask & ~bitval, S3C2410_INTMSK);
-}
-
-static struct irq_chip s3c2412_irq_eint0t4 = {
-        .irq_ack        = s3c2412_irq_ack,
-        .irq_mask       = s3c2412_irq_mask,
-        .irq_unmask     = s3c2412_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext_type,
-};
-
-#define INTBIT(x)       (1 << ((x) - S3C2410_IRQSUB(0)))
-
-/* CF and SDI sub interrupts */
-
-static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc  &= ~submsk;
-
-        if (subsrc & INTBIT(IRQ_S3C2412_SDI))
-                generic_handle_irq(IRQ_S3C2412_SDI);
-
-        if (subsrc & INTBIT(IRQ_S3C2412_CF))
-                generic_handle_irq(IRQ_S3C2412_CF);
-}
-
-#define INTMSK_CFSDI    (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
-#define SUBMSK_CFSDI    INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
-
-static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static struct irq_chip s3c2412_irq_cfsdi = {
-        .name           = "s3c2412-cfsdi",
-        .irq_ack        = s3c2412_irq_cfsdi_ack,
-        .irq_mask       = s3c2412_irq_cfsdi_mask,
-        .irq_unmask     = s3c2412_irq_cfsdi_unmask,
-};
-
-static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
-{
-        unsigned long pwrcfg;
-
-        pwrcfg = __raw_readl(S3C2412_PWRCFG);
-        if (state)
-                pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
-        else
-                pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
-        __raw_writel(pwrcfg, S3C2412_PWRCFG);
-
-        return s3c_irq_chip.irq_set_wake(data, state);
-}
-
-static struct irq_chip s3c2412_irq_rtc_chip;
-
-static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* add demux support for CF/SDI */
-
-        irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
-
-        for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* change RTC IRQ's set wake method */
-
-        s3c2412_irq_rtc_chip = s3c_irq_chip;
-        s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
-
-        irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
-
-        return 0;
-}
-
-static struct subsys_interface s3c2412_irq_interface = {
-        .name           = "s3c2412_irq",
-        .subsys         = &s3c2412_subsys,
-        .add_dev        = s3c2412_irq_add,
-};
-
-static int s3c2412_irq_init(void)
-{
-        return subsys_interface_register(&s3c2412_irq_interface);
-}
-
-arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2440.c b/arch/arm/mach-s3c24xx/irq-s3c2440.c
deleted file mode 100644
index 4a18cde439cc..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2440.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* WDT/AC97 */
-
-static void s3c_irq_demux_wdtac97(unsigned int irq,
-                                  struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 13;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_WDT);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_AC97);
-                }
-        }
-}
-
-
-#define INTMSK_WDT       (1UL << (IRQ_WDT - IRQ_EINT0))
-
-static void
-s3c_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static void
-s3c_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDT);
-}
-
-static void
-s3c_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static struct irq_chip s3c_irq_wdtac97 = {
-        .irq_mask       = s3c_irq_wdtac97_mask,
-        .irq_unmask     = s3c_irq_wdtac97_unmask,
-        .irq_ack        = s3c_irq_wdtac97_ack,
-};
-
-static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        printk("S3C2440: IRQ Support\n");
-
-        /* add new chained handler for wdt, ac7 */
-
-        irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
-
-        for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
diff --git a/arch/arm/mach-s3c24xx/irq-s3c244x.c b/arch/arm/mach-s3c24xx/irq-s3c244x.c
deleted file mode 100644
index 5fe8e58d3afd..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c244x.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* camera irq */
-
-static void s3c_irq_demux_cam(unsigned int irq,
-                              struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 11;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_C);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_P);
-                }
-        }
-}
-
-#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
-
-static void
-s3c_irq_cam_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static void
-s3c_irq_cam_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
-}
-
-static void
-s3c_irq_cam_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static struct irq_chip s3c_irq_cam = {
-        .irq_mask       = s3c_irq_cam_mask,
-        .irq_unmask     = s3c_irq_cam_unmask,
-        .irq_ack        = s3c_irq_cam_ack,
-};
-
-static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        set_irq_flags(IRQ_NFCON, IRQF_VALID);
-
-        /* add chained handler for camera */
-
-        irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
-
-        for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_cam,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
-static struct subsys_interface s3c2442_irq_interface = {
-        .name           = "s3c2442_irq",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-
-static int s3c2442_irq_init(void)
-{
-        return subsys_interface_register(&s3c2442_irq_interface);
-}
-
-arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
deleted file mode 100644
index b41c2cb7af4a..000000000000
--- a/arch/arm/mach-s3c24xx/irq.c
+++ /dev/null
@@ -1,821 +0,0 @@
-/*
- * S3C24XX IRQ handling
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip/chained_irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-irqtype.h>
-#include <plat/pm.h>
-
-#define S3C_IRQTYPE_NONE        0
-#define S3C_IRQTYPE_EINT        1
-#define S3C_IRQTYPE_EDGE        2
-#define S3C_IRQTYPE_LEVEL       3
-
-struct s3c_irq_data {
-        unsigned int type;
-        unsigned long parent_irq;
-
-        /* data gets filled during init */
-        struct s3c_irq_intc *intc;
-        unsigned long sub_bits;
-        struct s3c_irq_intc *sub_intc;
-};
-
-/*
- * Sructure holding the controller data
- * @reg_pending         register holding pending irqs
- * @reg_intpnd          special register intpnd in main intc
- * @reg_mask            mask register
- * @domain              irq_domain of the controller
- * @parent              parent controller for ext and sub irqs
- * @irqs                irq-data, always s3c_irq_data[32]
- */
-struct s3c_irq_intc {
-        void __iomem            *reg_pending;
-        void __iomem            *reg_intpnd;
-        void __iomem            *reg_mask;
-        struct irq_domain       *domain;
-        struct s3c_irq_intc     *parent;
-        struct s3c_irq_data     *irqs;
-};
-
-static void s3c_irq_mask(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
-        struct s3c_irq_data *parent_data;
-        unsigned long mask;
-        unsigned int irqno;
-
-        mask = __raw_readl(intc->reg_mask);
-        mask |= (1UL << data->hwirq);
-        __raw_writel(mask, intc->reg_mask);
-
-        if (parent_intc && irq_data->parent_irq) {
-                parent_data = &parent_intc->irqs[irq_data->parent_irq];
-
-                /* check to see if we need to mask the parent IRQ */
-                if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
-                        irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                        s3c_irq_mask(irq_get_irq_data(irqno));
-                }
-        }
-}
-
-static void s3c_irq_unmask(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
-        unsigned long mask;
-        unsigned int irqno;
-
-        mask = __raw_readl(intc->reg_mask);
-        mask &= ~(1UL << data->hwirq);
-        __raw_writel(mask, intc->reg_mask);
-
-        if (parent_intc && irq_data->parent_irq) {
-                irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                s3c_irq_unmask(irq_get_irq_data(irqno));
-        }
-}
-
-static inline void s3c_irq_ack(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        unsigned long bitval = 1UL << data->hwirq;
-
-        __raw_writel(bitval, intc->reg_pending);
-        if (intc->reg_intpnd)
-                __raw_writel(bitval, intc->reg_intpnd);
-}
-
-static int s3c_irqext_type_set(void __iomem *gpcon_reg,
-                               void __iomem *extint_reg,
-                               unsigned long gpcon_offset,
-                               unsigned long extint_offset,
-                               unsigned int type)
-{
-        unsigned long newvalue = 0, value;
-
-        /* Set the GPIO to external interrupt mode */
-        value = __raw_readl(gpcon_reg);
-        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
-        __raw_writel(value, gpcon_reg);
-
-        /* Set the external interrupt to pointed trigger type */
-        switch (type)
-        {
-                case IRQ_TYPE_NONE:
-                        pr_warn("No edge setting!\n");
-                        break;
-
-                case IRQ_TYPE_EDGE_RISING:
-                        newvalue = S3C2410_EXTINT_RISEEDGE;
-                        break;
-
-                case IRQ_TYPE_EDGE_FALLING:
-                        newvalue = S3C2410_EXTINT_FALLEDGE;
-                        break;
-
-                case IRQ_TYPE_EDGE_BOTH:
-                        newvalue = S3C2410_EXTINT_BOTHEDGE;
-                        break;
-
-                case IRQ_TYPE_LEVEL_LOW:
-                        newvalue = S3C2410_EXTINT_LOWLEV;
-                        break;
-
-                case IRQ_TYPE_LEVEL_HIGH:
-                        newvalue = S3C2410_EXTINT_HILEV;
-                        break;
-
-                default:
-                        pr_err("No such irq type %d", type);
-                        return -EINVAL;
-        }
-
-        value = __raw_readl(extint_reg);
-        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
-        __raw_writel(value, extint_reg);
-
-        return 0;
-}
-
-static int s3c_irqext_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-
-        if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->hwirq) * 2;
-                extint_offset = (data->hwirq) * 4;
-        } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT1;
-                gpcon_offset = (data->hwirq - 8) * 2;
-                extint_offset = (data->hwirq - 8) * 4;
-        } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT2;
-                gpcon_offset = (data->hwirq - 8) * 2;
-                extint_offset = (data->hwirq - 16) * 4;
-        } else {
-                return -EINVAL;
-        }
-
-        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
-                                   extint_offset, type);
-}
-
-static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-
-        if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->hwirq) * 2;
-                extint_offset = (data->hwirq) * 4;
-        } else {
-                return -EINVAL;
-        }
-
-        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
-                                   extint_offset, type);
-}
-
-static struct irq_chip s3c_irq_chip = {
-        .name           = "s3c",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake
-};
-
-static struct irq_chip s3c_irq_level_chip = {
-        .name           = "s3c-level",
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_ack        = s3c_irq_ack,
-};
-
-static struct irq_chip s3c_irqext_chip = {
-        .name           = "s3c-ext",
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_ack        = s3c_irq_ack,
-        .irq_set_type   = s3c_irqext_type,
-        .irq_set_wake   = s3c_irqext_wake
-};
-
-static struct irq_chip s3c_irq_eint0t4 = {
-        .name           = "s3c-ext0",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext0_type,
-};
-
-static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
-        struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
-        unsigned long src;
-        unsigned long msk;
-        unsigned int n;
-
-        chained_irq_enter(chip, desc);
-
-        src = __raw_readl(sub_intc->reg_pending);
-        msk = __raw_readl(sub_intc->reg_mask);
-
-        src &= ~msk;
-        src &= irq_data->sub_bits;
-
-        while (src) {
-                n = __ffs(src);
-                src &= ~(1 << n);
-                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
-        }
-
-        chained_irq_exit(chip, desc);
-}
-
-#ifdef CONFIG_FIQ
-/**
- * s3c24xx_set_fiq - set the FIQ routing
- * @irq: IRQ number to route to FIQ on processor.
- * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
- *
- * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
- * @on is true, the @irq is checked to see if it can be routed and the
- * interrupt controller updated to route the IRQ. If @on is false, the FIQ
- * routing is cleared, regardless of which @irq is specified.
- */
-int s3c24xx_set_fiq(unsigned int irq, bool on)
-{
-        u32 intmod;
-        unsigned offs;
-
-        if (on) {
-                offs = irq - FIQ_START;
-                if (offs > 31)
-                        return -EINVAL;
-
-                intmod = 1 << offs;
-        } else {
-                intmod = 0;
-        }
-
-        __raw_writel(intmod, S3C2410_INTMOD);
-        return 0;
-}
-
-EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
-#endif
-
-static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
-                                                        irq_hw_number_t hw)
-{
-        struct s3c_irq_intc *intc = h->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[hw];
-        struct s3c_irq_intc *parent_intc;
-        struct s3c_irq_data *parent_irq_data;
-        unsigned int irqno;
-
-        if (!intc) {
-                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        if (!irq_data) {
-                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        /* attach controller pointer to irq_data */
-        irq_data->intc = intc;
-
-        /* set handler and flags */
-        switch (irq_data->type) {
-        case S3C_IRQTYPE_NONE:
-                return 0;
-        case S3C_IRQTYPE_EINT:
-                if (irq_data->parent_irq)
-                        irq_set_chip_and_handler(virq, &s3c_irqext_chip,
-                                                 handle_edge_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
-                                                 handle_edge_irq);
-                break;
-        case S3C_IRQTYPE_EDGE:
-                if (irq_data->parent_irq ||
-                    intc->reg_pending == S3C2416_SRCPND2)
-                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
-                                                 handle_edge_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
-                                                 handle_edge_irq);
-                break;
-        case S3C_IRQTYPE_LEVEL:
-                if (irq_data->parent_irq)
-                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
-                                                 handle_level_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
-                                                 handle_level_irq);
-                break;
-        default:
-                pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
-                return -EINVAL;
-        }
-        set_irq_flags(virq, IRQF_VALID);
-
-        if (irq_data->parent_irq) {
-                parent_intc = intc->parent;
-                if (!parent_intc) {
-                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
-                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
-                if (!irq_data) {
-                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
-                parent_irq_data->sub_intc = intc;
-                parent_irq_data->sub_bits |= (1UL << hw);
-
-                /* attach the demuxer to the parent irq */
-                irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                if (!irqno) {
-                        pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
-                               irq_data->parent_irq);
-                        goto err;
-                }
-                irq_set_chained_handler(irqno, s3c_irq_demux);
-        }
-
-        return 0;
-
-err:
-        set_irq_flags(virq, 0);
-
-        /* the only error can result from bad mapping data*/
-        return -EINVAL;
-}
-
-static struct irq_domain_ops s3c24xx_irq_ops = {
-        .map = s3c24xx_irq_map,
-        .xlate = irq_domain_xlate_twocell,
-};
-
-static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
-{
-        void __iomem *reg_source;
-        unsigned long pend;
-        unsigned long last;
-        int i;
-
-        /* if intpnd is set, read the next pending irq from there */
-        reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
-
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(reg_source);
-
-                if (pend == 0 || pend == last)
-                        break;
-
-                __raw_writel(pend, intc->reg_pending);
-                if (intc->reg_intpnd)
-                        __raw_writel(pend, intc->reg_intpnd);
-
-                pr_info("irq: clearing pending status %08x\n", (int)pend);
-                last = pend;
-        }
-}
-
-struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
-                                       struct s3c_irq_data *irq_data,
-                                       struct s3c_irq_intc *parent,
-                                       unsigned long address)
-{
-        struct s3c_irq_intc *intc;
-        void __iomem *base = (void *)0xf6000000; /* static mapping */
-        int irq_num;
-        int irq_start;
-        int irq_offset;
-        int ret;
-
-        intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
-        if (!intc)
-                return ERR_PTR(-ENOMEM);
-
-        intc->irqs = irq_data;
-
-        if (parent)
-                intc->parent = parent;
-
-        /* select the correct data for the controller.
-         * Need to hard code the irq num start and offset
-         * to preserve the static mapping for now
-         */
-        switch (address) {
-        case 0x4a000000:
-                pr_debug("irq: found main intc\n");
-                intc->reg_pending = base;
-                intc->reg_mask = base + 0x08;
-                intc->reg_intpnd = base + 0x10;
-                irq_num = 32;
-                irq_start = S3C2410_IRQ(0);
-                irq_offset = 0;
-                break;
-        case 0x4a000018:
-                pr_debug("irq: found subintc\n");
-                intc->reg_pending = base + 0x18;
-                intc->reg_mask = base + 0x1c;
-                irq_num = 29;
-                irq_start = S3C2410_IRQSUB(0);
-                irq_offset = 0;
-                break;
-        case 0x4a000040:
-                pr_debug("irq: found intc2\n");
-                intc->reg_pending = base + 0x40;
-                intc->reg_mask = base + 0x48;
-                intc->reg_intpnd = base + 0x50;
-                irq_num = 8;
-                irq_start = S3C2416_IRQ(0);
-                irq_offset = 0;
-                break;
-        case 0x560000a4:
-                pr_debug("irq: found eintc\n");
-                base = (void *)0xfd000000;
-
-                intc->reg_mask = base + 0xa4;
-                intc->reg_pending = base + 0xa8;
-                irq_num = 20;
-                irq_start = S3C2410_IRQ(32);
-                irq_offset = 4;
-                break;
-        default:
-                pr_err("irq: unsupported controller address\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        /* now that all the data is complete, init the irq-domain */
-        s3c24xx_clear_intc(intc);
-        intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
-                                             irq_offset, &s3c24xx_irq_ops,
-                                             intc);
-        if (!intc->domain) {
-                pr_err("irq: could not create irq-domain\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        return intc;
-
-err:
-        kfree(intc);
-        return ERR_PTR(ret);
-}
-
-/* s3c24xx_init_irq
- *
- * Initialise S3C2410 IRQ system
-*/
-
-static struct s3c_irq_data init_base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_eint[32] = {
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
-};
-
-static struct s3c_irq_data init_subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-};
-
-void __init s3c24xx_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-}
-
-#ifdef CONFIG_CPU_S3C2416
-static struct s3c_irq_data init_s3c2416base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_NONE, },
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2416subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-static struct s3c_irq_data init_s3c2416_second[32] = {
-        { .type = S3C_IRQTYPE_EDGE }, /* 2D */
-        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
-};
-
-void __init s3c2416_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-        pr_info("S3C2416: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
-
-        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
-}
-
-#endif
-
-#ifdef CONFIG_CPU_S3C2443
-static struct s3c_irq_data init_s3c2443base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-
-static struct s3c_irq_data init_s3c2443subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-void __init s3c2443_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-        pr_info("S3C2443: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
-}
-#endif
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 0e0279e79150..e27b5c91b3db 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -63,6 +63,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
 
+#include <plat/samsung-time.h>
+
 #include "common.h"
 
 static struct resource amlm5900_nor_resource =
@@ -160,6 +162,7 @@ static void __init amlm5900_map_io(void)
         s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 #ifdef CONFIG_FB_S3C2410
@@ -235,8 +238,8 @@ static void __init amlm5900_init(void)
 MACHINE_START(AML_M5900, "AML_M5900")
         .atag_offset    = 0x100,
         .map_io         = amlm5900_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = amlm5900_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index bb595f15ce36..c1fb6c37867f 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/samsung-time.h>
 
 #include "anubis.h"
 #include "common.h"
@@ -410,6 +411,7 @@ static void __init anubis_map_io(void)
         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -443,7 +445,7 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .atag_offset    = 0x100,
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index b4bc60c78ebb..6dfeeb7ef469 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -48,6 +48,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mmc-s3cmci.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -192,6 +193,7 @@ static void __init at2440evb_map_io(void)
         s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init at2440evb_init(void)
@@ -209,7 +211,7 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .atag_offset    = 0x100,
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index ca6618081041..22d6ae926d91 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -55,6 +55,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -576,6 +577,7 @@ static void __init bast_map_io(void)
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init bast_init(void)
@@ -603,8 +605,8 @@ MACHINE_START(BAST, "Simtec-BAST")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = bast_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = bast_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index a25e8c5a7b4c..13d8d073675a 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -81,6 +81,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "gta02.h"
@@ -501,6 +502,7 @@ static void __init gta02_map_io(void)
         s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 
@@ -587,8 +589,8 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
         .atag_offset    = 0x100,
         .map_io         = gta02_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine   = gta02_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 79bc0830d740..af4334d6b4d5 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -62,7 +62,7 @@
 #include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
-
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -646,6 +646,7 @@ static void __init h1940_map_io(void)
         s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -666,11 +667,6 @@ static void __init h1940_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init h1940_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init h1940_init(void)
 {
         u32 tmp;
@@ -739,8 +735,8 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .atag_offset    = 0x100,
         .map_io         = h1940_map_io,
         .reserve        = h1940_reserve,
-        .init_irq       = h1940_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = h1940_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ca08d7df07f7..a45fcd8ccf79 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -52,6 +52,7 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "s3c2412-power.h"
@@ -506,6 +507,7 @@ static void __init jive_map_io(void)
         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void jive_power_off(void)
@@ -658,9 +660,9 @@ MACHINE_START(JIVE, "JIVE")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2865e5919f2c..a83db46320bc 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -56,6 +56,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include <sound/s3c24xx_uda134x.h>
 
@@ -525,6 +526,7 @@ static void __init mini2440_map_io(void)
         s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /*
@@ -686,7 +688,7 @@ MACHINE_START(MINI2440, "MINI2440")
         .atag_offset    = 0x100,
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 8017c0fc1729..2cb46c37c920 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -535,6 +536,7 @@ static void __init n30_map_io(void)
         n30_hwinit();
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
@@ -588,9 +590,9 @@ MACHINE_START(N30, "Acer-N30")
                                 Ben Dooks <ben-linux@fluff.org>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
@@ -599,9 +601,9 @@ MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 144b9f80c4a5..01f4354206f9 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -44,6 +44,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -135,6 +136,7 @@ static void __init nexcoder_map_io(void)
         s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         nexcoder_sensorboard_init();
 }
@@ -150,7 +152,7 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .atag_offset    = 0x100,
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ae2cbdf3e3ca..58d6fbe5bf1f 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -45,6 +45,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
@@ -384,6 +385,7 @@ static void __init osiris_map_io(void)
         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -424,8 +426,8 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = osiris_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = osiris_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index deb0ace585b0..7e16b0740ec1 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -33,6 +33,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "otom.h"
@@ -101,6 +102,7 @@ static void __init otom11_map_io(void)
         s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init otom11_init(void)
@@ -114,7 +116,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .atag_offset    = 0x100,
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 84c541602661..f8feaeadb55a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -59,6 +59,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -304,6 +305,7 @@ static void __init qt2410_map_io(void)
         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
         s3c24xx_init_clocks(12*1000*1000);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init qt2410_machine_init(void)
@@ -341,8 +343,8 @@ static void __init qt2410_machine_init(void)
 MACHINE_START(QT2410, "QT2410")
         .atag_offset    = 0x100,
         .map_io         = qt2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = qt2410_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 43f3ac5a1c7a..44ca018e1f96 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -57,6 +57,7 @@
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -740,6 +741,7 @@ static void __init rx1950_map_io(void)
         s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -810,8 +812,8 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .atag_offset = 0x100,
         .map_io = rx1950_map_io,
         .reserve        = rx1950_reserve,
-        .init_irq = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine = rx1950_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index f20418a2fb1b..3bc6231d0a1f 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -179,6 +180,7 @@ static void __init rx3715_map_io(void)
         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* H1940 and RX3715 need to reserve this for suspend */
@@ -188,11 +190,6 @@ static void __init rx3715_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init rx3715_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init rx3715_init_machine(void)
 {
 #ifdef CONFIG_PM_H1940
@@ -210,8 +207,8 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .atag_offset    = 0x100,
         .map_io         = rx3715_map_io,
         .reserve        = rx3715_reserve,
-        .init_irq       = rx3715_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = rx3715_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index cd0b1635c47e..a773789e4f38 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -51,6 +51,7 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -100,6 +101,7 @@ static void __init smdk2410_map_io(void)
         s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2410_init(void)
@@ -114,8 +116,8 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         /* Maintainer: Jonas Dietsche */
         .atag_offset    = 0x100,
         .map_io         = smdk2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = smdk2410_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 79485907950f..8146e920f10d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -44,6 +44,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -105,6 +106,7 @@ static void __init smdk2413_map_io(void)
         s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2413_machine_init(void)
@@ -128,10 +130,10 @@ MACHINE_START(S3C2413, "S3C2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -140,10 +142,10 @@ MACHINE_START(SMDK2412, "SMDK2412")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -152,9 +154,9 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 037a5da343bd..cb46847c66b4 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -50,6 +50,7 @@
 #include <plat/sdhci.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
+#include <plat/samsung-time.h>
 
 #include <plat/fb.h>
 
@@ -221,6 +222,7 @@ static void __init smdk2416_map_io(void)
         s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2416_machine_init(void)
@@ -253,6 +255,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
         .init_irq       = s3c2416_init_irq,
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 29d31314e23c..de2e5d39a847 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -160,6 +161,7 @@ static void __init smdk2440_map_io(void)
         s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2440_machine_init(void)
@@ -175,9 +177,9 @@ MACHINE_START(S3C2440, "SMDK2440")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index b3be4c4dc7bc..9435c3bef18a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -121,6 +122,7 @@ static void __init smdk2443_map_io(void)
         s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2443_machine_init(void)
@@ -142,6 +144,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
         .init_irq       = s3c2443_init_irq,
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 24b3d79e7b2c..7fad8f055cab 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -53,6 +53,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -136,6 +137,7 @@ static void __init tct_hammer_map_io(void)
         s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init tct_hammer_init(void)
@@ -147,8 +149,8 @@ static void __init tct_hammer_init(void)
 MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .atag_offset    = 0x100,
         .map_io         = tct_hammer_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = tct_hammer_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index ec42d1e4e465..42e7187fed60 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -45,6 +45,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -332,6 +333,7 @@ static void __init vr1000_map_io(void)
         s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vr1000_init(void)
@@ -353,7 +355,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .atag_offset    = 0x100,
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 239129c2d8bc..b66588428ec9 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -44,6 +44,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -142,6 +143,7 @@ static void __init vstms_map_io(void)
         s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vstms_init(void)
@@ -156,9 +158,9 @@ MACHINE_START(VSTMS, "VSTMS")
         .atag_offset    = 0x100,
 
         .fixup          = vstms_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 4c4bc1c83b77..d75f95e487ee 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -29,6 +29,7 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/wakeup-mask.h>
 
 #include "regs-dsc.h"
 #include "s3c2412-power.h"
@@ -51,8 +52,15 @@ static int s3c2412_cpu_suspend(unsigned long arg)
         return 1; /* Aborting suspend */
 }
 
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask wake_irqs[] = {
+        { .irq = IRQ_RTC,       .bit = S3C2412_PWRCFG_RTC_MASKIRQ, },
+};
+
 static void s3c2412_pm_prepare(void)
 {
+        samsung_sync_wakemask(S3C2412_PWRCFG,
+                              wake_irqs, ARRAY_SIZE(wake_irqs));
 }
 
 static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 131c86284711..283cb77d4721 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,11 +17,13 @@ config PLAT_S3C64XX
 # Configuration options for the S3C6410 CPU
 
 config CPU_S3C6400
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6400 CPU support
 
 config CPU_S3C6410
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6410 CPU support
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 728eef3296b2..35e3f54574ef 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -208,6 +209,7 @@ static void __init anw6410_map_io(void)
         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         anw6410_lcd_mode_set();
 }
@@ -232,6 +234,6 @@ MACHINE_START(ANW6410, "A&W6410")
         .map_io         = anw6410_map_io,
         .init_machine   = anw6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 1acf02bace57..8ad88ace795a 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -64,6 +64,7 @@
 #include <plat/adc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "crag6410.h"
@@ -744,6 +745,7 @@ static void __init crag6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* LCD type and Bypass set by bootloader */
 }
@@ -868,6 +870,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
         .map_io         = crag6410_map_io,
         .init_machine   = crag6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 7212eb9cfeb9..5b7f357d8c22 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -248,6 +249,7 @@ static void __init hmt_map_io(void)
         s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init hmt_machine_init(void)
@@ -275,6 +277,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
         .map_io         = hmt_map_io,
         .init_machine   = hmt_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 4b41fcdaa7b6..fc043e3ecdf8 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,6 +41,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -232,6 +233,7 @@ static void __init mini6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -354,6 +356,6 @@ MACHINE_START(MINI6410, "MINI6410")
         .map_io         = mini6410_map_io,
         .init_machine   = mini6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 8d3cedd995ff..7e2c3908f1f8 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -87,6 +88,7 @@ static void __init ncp_map_io(void)
         s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init ncp_machine_init(void)
@@ -103,6 +105,6 @@ MACHINE_START(NCP, "NCP")
         .map_io         = ncp_map_io,
         .init_machine   = ncp_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index fa12bd21ad82..8bed37b3d5ac 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,6 +42,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -211,6 +212,7 @@ static void __init real6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -333,6 +335,6 @@ MACHINE_START(REAL6410, "REAL6410")
         .map_io         = real6410_map_io,
         .init_machine   = real6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index fc3e9b32e26f..58ac99041274 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -38,6 +38,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <video/platform_lcd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -378,6 +379,7 @@ void __init smartq_map_io(void)
         s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         smartq_lcd_mode_set();
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index ca2afcfce573..8aca5daf3d05 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -155,6 +156,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
         .map_io         = smartq_map_io,
         .init_machine   = smartq5_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 37bb0c632a5e..a052e107c0b4 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -171,6 +172,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
         .map_io         = smartq_map_io,
         .init_machine   = smartq7_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index a392869c8342..d70c0843aea2 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,6 +35,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -66,6 +67,7 @@ static void __init smdk6400_map_io(void)
         s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static struct platform_device *smdk6400_devices[] __initdata = {
@@ -92,6 +94,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
         .map_io         = smdk6400_map_io,
         .init_machine   = smdk6400_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ba7544e2d04d..bd3295a19ad7 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -69,6 +69,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -634,6 +635,7 @@ static void __init smdk6410_map_io(void)
         s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
 
@@ -702,6 +704,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
         .map_io         = smdk6410_map_io,
         .init_machine   = smdk6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index e8742cb7ddd9..5a707bdb9ea0 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,16 +9,16 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
-        select S5P_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select S5P_HRT
+        select SAMSUNG_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index e23723a5a214..73f71a698a34 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -229,7 +229,7 @@ static void __init smdk6440_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6440_set_lcd_interface(void)
@@ -273,6 +273,6 @@ MACHINE_START(SMDK6440, "SMDK6440")
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
         .init_machine   = smdk6440_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index ca10963a959e..18303e12019f 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -248,7 +248,7 @@ static void __init smdk6450_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(19200000);
         s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6450_set_lcd_interface(void)
@@ -292,6 +292,6 @@ MACHINE_START(SMDK6450, "SMDK6450")
         .init_irq       = s5p6450_init_irq,
         .map_io         = smdk6450_map_io,
         .init_machine   = smdk6450_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 15170be97a74..2f456a4533ba 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,6 +11,7 @@ config CPU_S5PC100
         bool
         select S5P_EXT_INT
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 185a19583898..8c880f76f274 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -51,6 +51,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <linux/platform_data/asoc-s3c.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -221,6 +222,7 @@ static void __init smdkc100_map_io(void)
         s5pc100_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc100_machine_init(void)
@@ -255,6 +257,6 @@ MACHINE_START(SMDKC100, "SMDKC100")
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pc100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 92ad72f0ef98..0963283a7c5d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -12,10 +12,10 @@ if ARCH_S5PV210
 config CPU_S5PV210
         bool
         select S5P_EXT_INT
-        select S5P_HRT
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 11900a8e88a3..ed2b85485b9d 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,7 +38,7 @@
 #include <plat/fb.h>
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -651,7 +651,7 @@ static void __init aquila_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init aquila_machine_init(void)
@@ -686,6 +686,6 @@ MACHINE_START(AQUILA, "Aquila")
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
         .init_machine   = aquila_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e373de44a8b6..30b24ad84f49 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -47,7 +47,7 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 #include <plat/camport.h>
 
@@ -908,7 +908,7 @@ static void __init goni_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init goni_reserve(void)
@@ -973,7 +973,7 @@ MACHINE_START(GONI, "GONI")
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &goni_reserve,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 28bd0248a3e2..7c0ed07a78a3 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -29,7 +29,7 @@
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 
 #include "common.h"
@@ -120,7 +120,7 @@ static void __init smdkc110_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc110_reserve(void)
@@ -153,7 +153,7 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
         .init_machine   = smdkc110_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 3c73f36869bb..d50b6f124465 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -44,7 +44,7 @@
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
@@ -285,7 +285,7 @@ static void __init smdkv210_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
 }
 
 static void __init smdkv210_reserve(void)
@@ -329,7 +329,7 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
         .init_machine   = smdkv210_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 2d4c5531819c..579afe89842a 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -26,7 +26,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -106,7 +106,7 @@ static void __init torbreck_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init torbreck_machine_init(void)
@@ -130,6 +130,6 @@ MACHINE_START(TORBRECK, "TORBRECK")
         .init_irq       = s5pv210_init_irq,
         .map_io         = torbreck_map_io,
         .init_machine   = torbreck_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9255546e7bf6..75d413c004b6 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -16,6 +16,7 @@ config ARCH_SH73A0
         select CPU_V7
         select I2C
         select SH_CLK_CPG
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
@@ -31,6 +32,7 @@ config ARCH_R8A7779
         select SH_CLK_CPG
         select USB_ARCH_HAS_EHCI
         select USB_ARCH_HAS_OHCI
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index a385f570bbfc..95fe396f9604 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -81,7 +81,7 @@ static struct resource smsc9221_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x260), /* IRQ3 */
+                .start  = irq_pin(3), /* IRQ3 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -115,7 +115,7 @@ static struct resource usb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x220), /* IRQ1 */
+                .start  = irq_pin(1), /* IRQ1 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -138,7 +138,7 @@ struct usbhs_private {
         struct renesas_usbhs_platform_info info;
 };
 
-#define IRQ15                   intcs_evt2irq(0x03e0)
+#define IRQ15                   irq_pin(15)
 #define USB_PHY_MODE            (1 << 4)
 #define USB_PHY_INT_EN          ((1 << 3) | (1 << 2))
 #define USB_PHY_ON              (1 << 1)
@@ -567,25 +567,25 @@ static struct i2c_board_info i2c0_devices[] = {
         },
         {
                 I2C_BOARD_INFO("ak8975", 0x0c),
-                .irq = intcs_evt2irq(0x3380), /* IRQ28 */
+                .irq = irq_pin(28), /* IRQ28 */
         },
         {
                 I2C_BOARD_INFO("adxl34x", 0x1d),
-                .irq = intcs_evt2irq(0x3340), /* IRQ26 */
+                .irq = irq_pin(26), /* IRQ26 */
         },
 };
 
 static struct i2c_board_info i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("st1232-ts", 0x55),
-                .irq = intcs_evt2irq(0x300), /* IRQ8 */
+                .irq = irq_pin(8), /* IRQ8 */
         },
 };
 
 static struct i2c_board_info i2c3_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8575", 0x20),
-                .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
+                .irq = irq_pin(19), /* IRQ19 */
                 .platform_data = &pcf8575_pdata,
         },
 };
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 62c04c252418..1fef737a4c1a 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -58,6 +58,7 @@ extern void r8a7740_pm_init(void);
 
 extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq(void);
+extern void r8a7779_init_irq_extpin(int irlm);
 extern void r8a7779_init_irq_dt(void);
 extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 992ed213cec1..b2074e2acb15 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -12,4 +12,8 @@
 #define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
 #define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
 
+/* External IRQ pins */
+#define IRQPIN_BASE             2000
+#define irq_pin(nr)             ((nr) + IRQPIN_BASE)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index f9cc4bc9c798..b86dc8908724 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -19,13 +19,16 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
-#include <mach/common.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/irqchip.h>
+#include <mach/common.h>
 #include <mach/intc.h>
+#include <mach/irqs.h>
 #include <mach/r8a7779.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,6 +42,54 @@
 #define INT2NTSR0 IOMEM(0xfe700060)
 #define INT2NTSR1 IOMEM(0xfe700064)
 
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
+        .sense_bitfield_width = 2,
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
+        DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
+        DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
+        DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
+        DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+void __init r8a7779_init_irq_extpin(int irlm)
+{
+        void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
+        unsigned long tmp;
+
+        if (icr0) {
+                tmp = ioread32(icr0);
+                if (irlm)
+                        tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
+                else
+                        tmp &= ~(1 << 23); /* IRL mode - not supported */
+                tmp |= (1 << 21); /* LVLMODE = 1 */
+                iowrite32(tmp, icr0);
+                iounmap(icr0);
+
+                if (irlm)
+                        platform_device_register(&irqpin0_device);
+        } else
+                pr_warn("r8a7779: unable to setup external irq pin mode\n");
+}
+
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
         return 0; /* always allow wakeup */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index a81a1d804e2e..19a26f4579b3 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
         return 0; /* always allow wakeup */
 }
 
-#define RELOC_BASE 0x1200
-
-/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
-#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
-
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
-                 INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
-
-static int to_gic_irq(struct irq_data *data)
-{
-        unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
-
-        if (vect >= 0x3200)
-                vect -= 0x3000;
-        else
-                vect -= 0x0200;
-
-        return gic_spi((vect >> 5) + 1);
-}
-
-static int to_intca_reloc_irq(struct irq_data *data)
-{
-        return data->irq + (RELOC_BASE >> 5);
-}
-
-#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
-#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
-
-static void intca_gic_enable(struct irq_data *data)
-{
-        irq_cb(irq_unmask, to_intca_reloc_irq(data));
-        irq_cb(irq_unmask, to_gic_irq(data));
-}
-
-static void intca_gic_disable(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_mask_ack(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_eoi(struct irq_data *data)
-{
-        irq_cb(irq_eoi, to_gic_irq(data));
-}
-
-static int intca_gic_set_type(struct irq_data *data, unsigned int type)
-{
-        return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
-}
-
-#ifdef CONFIG_SMP
-static int intca_gic_set_affinity(struct irq_data *data,
-                                  const struct cpumask *cpumask,
-                                  bool force)
-{
-        return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
-}
-#endif
-
-struct irq_chip intca_gic_irq_chip = {
-        .name                   = "INTCA-GIC",
-        .irq_mask               = intca_gic_disable,
-        .irq_unmask             = intca_gic_enable,
-        .irq_mask_ack           = intca_gic_mask_ack,
-        .irq_eoi                = intca_gic_eoi,
-        .irq_enable             = intca_gic_enable,
-        .irq_disable            = intca_gic_disable,
-        .irq_shutdown           = intca_gic_disable,
-        .irq_set_type           = intca_gic_set_type,
-        .irq_set_wake           = sh73a0_set_wake,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = intca_gic_set_affinity,
-#endif
-};
-
-static int to_intc_vect(int irq)
-{
-        unsigned int irq_pin = irq - gic_spi(1);
-        unsigned int offs;
-
-        if (irq_pin < 16)
-                offs = 0x0200;
-        else
-                offs = 0x3000;
-
-        return offs + (irq_pin << 5);
-}
-
-static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
-{
-        generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
-        return IRQ_HANDLED;
-}
-
-static struct irqaction sh73a0_irq_pin_cascade[32];
-
 #define PINTER0_PHYS 0xe69000a0
 #define PINTER1_PHYS 0xe69000a4
 #define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void)
         void __iomem *gic_dist_base = IOMEM(0xf0001000);
         void __iomem *gic_cpu_base = IOMEM(0xf0000100);
         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
-        int k, n;
 
         gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 
         register_intc_controller(&intcs_desc);
-        register_intc_controller(&intca_irq_pins_desc);
         register_intc_controller(&intc_pint0_desc);
         register_intc_controller(&intc_pint1_desc);
 
@@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void)
         sh73a0_intcs_cascade.dev_id = intevtsa;
         setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
 
-        /* IRQ pins require special handling through INTCA and GIC */
-        for (k = 0; k < 32; k++) {
-                sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
-                sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
-                setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
-
-                n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
-                WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
-                irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
-                                              handle_level_irq, "level");
-                set_irq_flags(n, IRQF_VALID); /* yuck */
-        }
-
         /* PINT pins are sanely tied to the GIC as SPI */
         sh73a0_pint0_cascade.name = "PINT0 cascade";
         sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 2257a915746d..e8cd93a5c550 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -33,6 +33,7 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -811,6 +812,127 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
+        DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
+        DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
+        DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
+        DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
+        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
+        DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
+        DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
+        DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
+        DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin1_platform_data = {
+        .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
+        .control_parent = true, /* Disable spurious IRQ10 */
+};
+
+static struct resource irqpin1_resources[] = {
+        DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
+        DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
+        DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
+        DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
+        DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
+        DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
+        DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
+        DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
+        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
+        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
+        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
+        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
+        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
+};
+
+static struct platform_device irqpin1_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 1,
+        .resource       = irqpin1_resources,
+        .num_resources  = ARRAY_SIZE(irqpin1_resources),
+        .dev            = {
+                .platform_data  = &irqpin1_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin2_platform_data = {
+        .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
+};
+
+static struct resource irqpin2_resources[] = {
+        DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
+        DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
+        DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
+        DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
+        DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
+        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
+        DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
+        DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
+        DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
+        DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
+        DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
+        DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
+        DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
+};
+
+static struct platform_device irqpin2_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 2,
+        .resource       = irqpin2_resources,
+        .num_resources  = ARRAY_SIZE(irqpin2_resources),
+        .dev            = {
+                .platform_data  = &irqpin2_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin3_platform_data = {
+        .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
+};
+
+static struct resource irqpin3_resources[] = {
+        DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
+        DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
+        DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
+        DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
+        DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
+        DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
+        DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
+        DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
+        DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
+};
+
+static struct platform_device irqpin3_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 3,
+        .resource       = irqpin3_resources,
+        .num_resources  = ARRAY_SIZE(irqpin3_resources),
+        .dev            = {
+                .platform_data  = &irqpin3_platform_data,
+        },
+};
+
 static struct platform_device *sh73a0_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -839,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &dma0_device,
         &mpdma0_device,
         &pmu_device,
+        &irqpin0_device,
+        &irqpin1_device,
+        &irqpin2_device,
+        &irqpin3_device,
 };
 
 #define SRCR2          IOMEM(0xe61580b0)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 9cf1ab17afeb..0d1e4128d460 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -85,6 +86,8 @@ static void __init tegra_dt_init(void)
         struct soc_device *soc_dev;
         struct device *parent = NULL;
 
+        tegra_clocks_apply_init_table();
+
         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
         if (!soc_dev_attr)
                 goto out;
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f3976f9c404a..947bd9eca079 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -46,8 +46,12 @@ BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
@@ -76,9 +80,6 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
 #define DB8500_PIN_HOG(pin,conf) \
         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
-                            pin, conf)
 
 /* These are default states associated with device and changed runtime */
 #define DB8500_MUX(group,func,dev) \
@@ -307,8 +308,23 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 
         /* Mux in USB pins, drive STP high */
-        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
-        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
+        /* USB default state */
+        DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
+        DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
+        /* USB sleep state */
+        DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
+        DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
+        DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
+        DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
+        DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
+        DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
+        DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
+        DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
+        DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
+        DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
+
         /* Mux in SPI2 pins on the "other C1" altfunction */
         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
@@ -316,9 +332,9 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
         /* SPI2 idle state */
-        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
+        DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
         /* SPI2 sleep state */
         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
@@ -745,6 +761,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = {
         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
         DB8500_MUX_HOG("sm_b_1", "sm"),
+        /* User LED */
+        DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
         /* Drive RSTn_LAN high */
         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
         /*  Accelerometer/Magnetometer */
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index e3e94b2fa145..9b252934b206 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -7,6 +7,7 @@ config ARCH_VT8500
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select VT8500_TIMER
+        select PINCTRL
         help
           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 92ceb2436b60..4c8a84637594 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_ARCH_VT8500) += irq.o vt8500.o
+obj-$(CONFIG_ARCH_VT8500) += vt8500.o
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
index 77611a6968d6..087787af62f1 100644
--- a/arch/arm/mach-vt8500/common.h
+++ b/arch/arm/mach-vt8500/common.h
@@ -18,13 +18,7 @@
 
 #include <linux/of.h>
 
-int __init vt8500_irq_init(struct device_node *node,
-                                struct device_node *parent);
-
 /* defined in drivers/clk/clk-vt8500.c */
 void __init vtwm_clk_init(void __iomem *pmc_base);
 
-/* defined in irq.c */
-asmlinkage void vt8500_handle_irq(struct pt_regs *regs);
-
 #endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
deleted file mode 100644
index b9cf5ce9efbb..000000000000
--- a/arch/arm/mach-vt8500/irq.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/irq.c
- *
- *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * This file is copied and modified from the original irq.c provided by
- * Alexey Charkov. Minor changes have been made for Device Tree Support.
- */
-
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-
-#include <asm/irq.h>
-#include <asm/exception.h>
-
-#define VT8500_ICPC_IRQ         0x20
-#define VT8500_ICPC_FIQ         0x24
-#define VT8500_ICDC             0x40            /* Destination Control 64*u32 */
-#define VT8500_ICIS             0x80            /* Interrupt status, 16*u32 */
-
-/* ICPC */
-#define ICPC_MASK               0x3F
-#define ICPC_ROTATE             BIT(6)
-
-/* IC_DCTR */
-#define ICDC_IRQ                0x00
-#define ICDC_FIQ                0x01
-#define ICDC_DSS0               0x02
-#define ICDC_DSS1               0x03
-#define ICDC_DSS2               0x04
-#define ICDC_DSS3               0x05
-#define ICDC_DSS4               0x06
-#define ICDC_DSS5               0x07
-
-#define VT8500_INT_DISABLE      0
-#define VT8500_INT_ENABLE       BIT(3)
-
-#define VT8500_TRIGGER_HIGH     0
-#define VT8500_TRIGGER_RISING   BIT(5)
-#define VT8500_TRIGGER_FALLING  BIT(6)
-#define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
-                                | VT8500_TRIGGER_FALLING)
-
-/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
-#define VT8500_INTC_MAX         2
-
-struct vt8500_irq_data {
-        void __iomem            *base;          /* IO Memory base address */
-        struct irq_domain       *domain;        /* Domain for this controller */
-};
-
-/* Global variable for accessing io-mem addresses */
-static struct vt8500_irq_data intc[VT8500_INTC_MAX];
-static u32 active_cnt = 0;
-
-static void vt8500_irq_mask(struct irq_data *d)
-{
-        struct vt8500_irq_data *priv = d->domain->host_data;
-        void __iomem *base = priv->base;
-        void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
-        u8 edge, dctr;
-        u32 status;
-
-        edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
-        if (edge) {
-                status = readl(stat_reg);
-
-                status |= (1 << (d->hwirq & 0x1f));
-                writel(status, stat_reg);
-        } else {
-                dctr = readb(base + VT8500_ICDC + d->hwirq);
-                dctr &= ~VT8500_INT_ENABLE;
-                writeb(dctr, base + VT8500_ICDC + d->hwirq);
-        }
-}
-
-static void vt8500_irq_unmask(struct irq_data *d)
-{
-        struct vt8500_irq_data *priv = d->domain->host_data;
-        void __iomem *base = priv->base;
-        u8 dctr;
-
-        dctr = readb(base + VT8500_ICDC + d->hwirq);
-        dctr |= VT8500_INT_ENABLE;
-        writeb(dctr, base + VT8500_ICDC + d->hwirq);
-}
-
-static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
-        struct vt8500_irq_data *priv = d->domain->host_data;
-        void __iomem *base = priv->base;
-        u8 dctr;
-
-        dctr = readb(base + VT8500_ICDC + d->hwirq);
-        dctr &= ~VT8500_EDGE;
-
-        switch (flow_type) {
-        case IRQF_TRIGGER_LOW:
-                return -EINVAL;
-        case IRQF_TRIGGER_HIGH:
-                dctr |= VT8500_TRIGGER_HIGH;
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-                break;
-        case IRQF_TRIGGER_FALLING:
-                dctr |= VT8500_TRIGGER_FALLING;
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-                break;
-        case IRQF_TRIGGER_RISING:
-                dctr |= VT8500_TRIGGER_RISING;
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-                break;
-        }
-        writeb(dctr, base + VT8500_ICDC + d->hwirq);
-
-        return 0;
-}
-
-static struct irq_chip vt8500_irq_chip = {
-        .name = "vt8500",
-        .irq_ack = vt8500_irq_mask,
-        .irq_mask = vt8500_irq_mask,
-        .irq_unmask = vt8500_irq_unmask,
-        .irq_set_type = vt8500_irq_set_type,
-};
-
-static void __init vt8500_init_irq_hw(void __iomem *base)
-{
-        u32 i;
-
-        /* Enable rotating priority for IRQ */
-        writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
-        writel(0x00, base + VT8500_ICPC_FIQ);
-
-        /* Disable all interrupts and route them to IRQ */
-        for (i = 0; i < 64; i++)
-                writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
-}
-
-static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
-                                                        irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
-        set_irq_flags(virq, IRQF_VALID);
-
-        return 0;
-}
-
-static struct irq_domain_ops vt8500_irq_domain_ops = {
-        .map = vt8500_irq_map,
-        .xlate = irq_domain_xlate_onecell,
-};
-
-asmlinkage void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
-{
-        u32 stat, i;
-        int irqnr, virq;
-        void __iomem *base;
-
-        /* Loop through each active controller */
-        for (i=0; i<active_cnt; i++) {
-                base = intc[i].base;
-                irqnr = readl_relaxed(base) & 0x3F;
-                /*
-                  Highest Priority register default = 63, so check that this
-                  is a real interrupt by checking the status register
-                */
-                if (irqnr == 63) {
-                        stat = readl_relaxed(base + VT8500_ICIS + 4);
-                        if (!(stat & BIT(31)))
-                                continue;
-                }
-
-                virq = irq_find_mapping(intc[i].domain, irqnr);
-                handle_IRQ(virq, regs);
-        }
-}
-
-int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
-{
-        int irq, i;
-        struct device_node *np = node;
-
-        if (active_cnt == VT8500_INTC_MAX) {
-                pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
-                                                                __func__);
-                goto out;
-        }
-
-        intc[active_cnt].base = of_iomap(np, 0);
-        intc[active_cnt].domain = irq_domain_add_linear(node, 64,
-                        &vt8500_irq_domain_ops, &intc[active_cnt]);
-
-        if (!intc[active_cnt].base) {
-                pr_err("%s: Unable to map IO memory\n", __func__);
-                goto out;
-        }
-
-        if (!intc[active_cnt].domain) {
-                pr_err("%s: Unable to add irq domain!\n", __func__);
-                goto out;
-        }
-
-        vt8500_init_irq_hw(intc[active_cnt].base);
-
-        pr_info("vt8500-irq: Added interrupt controller\n");
-
-        active_cnt++;
-
-        /* check if this is a slaved controller */
-        if (of_irq_count(np) != 0) {
-                /* check that we have the correct number of interrupts */
-                if (of_irq_count(np) != 8) {
-                        pr_err("%s: Incorrect IRQ map for slaved controller\n",
-                                        __func__);
-                        return -EINVAL;
-                }
-
-                for (i = 0; i < 8; i++) {
-                        irq = irq_of_parse_and_map(np, i);
-                        enable_irq(irq);
-                }
-
-                pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
-        }
-out:
-        return 0;
-}
-
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 49e80053d828..1dd281efc020 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -20,6 +20,7 @@
 
 #include <linux/clocksource.h>
 #include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/pm.h>
 
 #include <asm/mach-types.h>
@@ -166,16 +167,6 @@ void __init vt8500_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const struct of_device_id vt8500_irq_match[] __initconst = {
-        { .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
-        { /* sentinel */ },
-};
-
-static void __init vt8500_init_irq(void)
-{
-        of_irq_init(vt8500_irq_match);
-};
-
 static const char * const vt8500_dt_compat[] = {
         "via,vt8500",
         "wm,wm8650",
@@ -187,10 +178,9 @@ static const char * const vt8500_dt_compat[] = {
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
         .dt_compat      = vt8500_dt_compat,
         .map_io         = vt8500_map_io,
-        .init_irq       = vt8500_init_irq,
+        .init_irq       = irqchip_init,
         .init_machine   = vt8500_init,
         .init_time      = clocksource_of_init,
         .restart        = vt8500_restart,
-        .handle_irq     = vt8500_handle_irq,
 MACHINE_END
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 138b5891f4ef..cf3226b041f5 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -11,5 +11,6 @@ config ARCH_ZYNQ
         select MIGHT_HAVE_CACHE_L2X0
         select USE_OF
         select SPARSE_IRQ
+        select CADENCE_TTC_TIMER
         help
           Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 397268c1b250..320faedeb484 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -3,4 +3,4 @@
 #
 
 # Common support
-obj-y                           := common.o timer.o
+obj-y                           := common.o
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5c8983218183..68e0907de5d0 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -20,6 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/clk/zynq.h>
+#include <linux/clocksource.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -77,7 +78,7 @@ static void __init xilinx_zynq_timer_init(void)
 
         xilinx_zynq_clocks_init(slcr);
 
-        xttcps_timer_init();
+        clocksource_of_init();
 }
 
 /**
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 8b4dbbaa01cf..5050bb10bb12 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,6 +17,4 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
 
-void __init xttcps_timer_init(void);
-
 #endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
deleted file mode 100644
index f9fbc9c1e7a6..000000000000
--- a/arch/arm/mach-zynq/timer.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * This file contains driver for the Xilinx PS Timer Counter IP.
- *
- *  Copyright (C) 2011 Xilinx
- *
- * based on arch/mips/kernel/time.c timer driver
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/interrupt.h>
-#include <linux/clockchips.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/slab.h>
-#include <linux/clk-provider.h>
-#include "common.h"
-
-/*
- * Timer Register Offset Definitions of Timer 1, Increment base address by 4
- * and use same offsets for Timer 2
- */
-#define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
-#define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
-#define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
-#define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
-
-#define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
-
-/*
- * Setup the timers to use pre-scaling, using a fixed value for now that will
- * work across most input frequency, but it may need to be more dynamic
- */
-#define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
-#define PRESCALE                2048    /* The exponent must match this */
-#define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
-#define CLK_CNTRL_PRESCALE_EN   1
-#define CNT_CNTRL_RESET         (1<<4)
-
-/**
- * struct xttcps_timer - This definition defines local timer structure
- *
- * @base_addr:  Base address of timer
- **/
-struct xttcps_timer {
-        void __iomem    *base_addr;
-};
-
-struct xttcps_timer_clocksource {
-        struct xttcps_timer     xttc;
-        struct clocksource      cs;
-};
-
-#define to_xttcps_timer_clksrc(x) \
-                container_of(x, struct xttcps_timer_clocksource, cs)
-
-struct xttcps_timer_clockevent {
-        struct xttcps_timer             xttc;
-        struct clock_event_device       ce;
-        struct clk                      *clk;
-};
-
-#define to_xttcps_timer_clkevent(x) \
-                container_of(x, struct xttcps_timer_clockevent, ce)
-
-/**
- * xttcps_set_interval - Set the timer interval value
- *
- * @timer:      Pointer to the timer instance
- * @cycles:     Timer interval ticks
- **/
-static void xttcps_set_interval(struct xttcps_timer *timer,
-                                        unsigned long cycles)
-{
-        u32 ctrl_reg;
-
-        /* Disable the counter, set the counter value  and re-enable counter */
-        ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
-
-        /*
-         * Reset the counter (0x10) so that it starts from 0, one-shot
-         * mode makes this needed for timing to be right.
-         */
-        ctrl_reg |= CNT_CNTRL_RESET;
-        ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-}
-
-/**
- * xttcps_clock_event_interrupt - Clock event timer interrupt handler
- *
- * @irq:        IRQ number of the Timer
- * @dev_id:     void pointer to the xttcps_timer instance
- *
- * returns: Always IRQ_HANDLED - success
- **/
-static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
-{
-        struct xttcps_timer_clockevent *xttce = dev_id;
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        /* Acknowledge the interrupt and call event handler */
-        __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
-
-        xttce->ce.event_handler(&xttce->ce);
-
-        return IRQ_HANDLED;
-}
-
-/**
- * __xttc_clocksource_read - Reads the timer counter register
- *
- * returns: Current timer counter register value
- **/
-static cycle_t __xttc_clocksource_read(struct clocksource *cs)
-{
-        struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
-
-        return (cycle_t)__raw_readl(timer->base_addr +
-                                XTTCPS_COUNT_VAL_OFFSET);
-}
-
-/**
- * xttcps_set_next_event - Sets the time interval for next event
- *
- * @cycles:     Timer interval ticks
- * @evt:        Address of clock event instance
- *
- * returns: Always 0 - success
- **/
-static int xttcps_set_next_event(unsigned long cycles,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        xttcps_set_interval(timer, cycles);
-        return 0;
-}
-
-/**
- * xttcps_set_mode - Sets the mode of timer
- *
- * @mode:       Mode to be set
- * @evt:        Address of clock event instance
- **/
-static void xttcps_set_mode(enum clock_event_mode mode,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-        u32 ctrl_reg;
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                xttcps_set_interval(timer,
-                                     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
-                                                       PRESCALE * HZ));
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        case CLOCK_EVT_MODE_RESUME:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        }
-}
-
-static void __init zynq_ttc_setup_clocksource(struct device_node *np,
-                                             void __iomem *base)
-{
-        struct xttcps_timer_clocksource *ttccs;
-        struct clk *clk;
-        int err;
-        u32 reg;
-
-        ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
-        if (WARN_ON(!ttccs))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = clk_prepare_enable(clk);
-        if (WARN_ON(err))
-                return;
-
-        ttccs->xttc.base_addr = base + reg * 4;
-
-        ttccs->cs.name = np->name;
-        ttccs->cs.rating = 200;
-        ttccs->cs.read = __xttc_clocksource_read;
-        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
-        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
-
-        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(CNT_CNTRL_RESET,
-                     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
-        if (WARN_ON(err))
-                return;
-}
-
-static void __init zynq_ttc_setup_clockevent(struct device_node *np,
-                                            void __iomem *base)
-{
-        struct xttcps_timer_clockevent *ttcce;
-        int err, irq;
-        u32 reg;
-
-        ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
-        if (WARN_ON(!ttcce))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        ttcce->xttc.base_addr = base + reg * 4;
-
-        ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(ttcce->clk)))
-                return;
-
-        err = clk_prepare_enable(ttcce->clk);
-        if (WARN_ON(err))
-                return;
-
-        irq = irq_of_parse_and_map(np, 0);
-        if (WARN_ON(!irq))
-                return;
-
-        ttcce->ce.name = np->name;
-        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        ttcce->ce.set_next_event = xttcps_set_next_event;
-        ttcce->ce.set_mode = xttcps_set_mode;
-        ttcce->ce.rating = 200;
-        ttcce->ce.irq = irq;
-        ttcce->ce.cpumask = cpu_possible_mask;
-
-        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
-
-        err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
-                          np->name, ttcce);
-        if (WARN_ON(err))
-                return;
-
-        clockevents_config_and_register(&ttcce->ce,
-                                        clk_get_rate(ttcce->clk) / PRESCALE,
-                                        1, 0xfffe);
-}
-
-static const __initconst struct of_device_id zynq_ttc_match[] = {
-        { .compatible = "xlnx,ttc-counter-clocksource",
-                .data = zynq_ttc_setup_clocksource, },
-        { .compatible = "xlnx,ttc-counter-clockevent",
-                .data = zynq_ttc_setup_clockevent, },
-        {}
-};
-
-/**
- * xttcps_timer_init - Initialize the timer
- *
- * Initializes the timer hardware and register the clock source and clock event
- * timers with Linux kernal timer framework
- **/
-void __init xttcps_timer_init(void)
-{
-        struct device_node *np;
-
-        for_each_compatible_node(np, NULL, "xlnx,ttc") {
-                struct device_node *np_chld;
-                void __iomem *base;
-
-                base = of_iomap(np, 0);
-                if (WARN_ON(!base))
-                        return;
-
-                for_each_available_child_of_node(np, np_chld) {
-                        int (*cb)(struct device_node *np, void __iomem *base);
-                        const struct of_device_id *match;
-
-                        match = of_match_node(zynq_ttc_match, np_chld);
-                        if (match) {
-                                cb = match->data;
-                                cb(np_chld, base);
-                        }
-                }
-        }
-}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 91c2d72e689b..54d186106f9f 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,7 @@ config PLAT_S5P
         select PLAT_SAMSUNG
         select S3C_GPIO_TRACK
         select S5P_GPIO_DRVSTR
-        select SAMSUNG_CLKSRC
+        select SAMSUNG_CLKSRC if !COMMON_CLK
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_IRQ_VIC_TIMER
         help
@@ -62,7 +62,7 @@ config S3C_LOWLEVEL_UART_PORT
 
 # timer options
 
-config S5P_HRT
+config SAMSUNG_HRT
         bool
         select SAMSUNG_DEV_PWM
         help
@@ -81,7 +81,7 @@ config SAMSUNG_CLKSRC
           used by newer systems such as the S3C64XX.
 
 config S5P_CLOCK
-        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         help
           Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
 
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 3a7c64d1814a..a23c460299a1 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,8 +12,7 @@ obj-				:=
 # Objects we always build independent of SoC choice
 
 obj-y                           += init.o cpu.o
-obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
-obj-$(CONFIG_S5P_HRT)           += s5p-time.o
+obj-$(CONFIG_SAMSUNG_HRT)       += samsung-time.o
 
 obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
 obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 33ad3f32c2b9..30c2fe243f76 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1074,7 +1074,7 @@ struct platform_device s5p_device_onenand = {
 
 /* PMU */
 
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
 static struct resource s5p_pmu_resource[] = {
         DEFINE_RES_IRQ(IRQ_PMU)
 };
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 37703ef6dfc7..989fefe18be6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -23,6 +23,9 @@ extern unsigned long samsung_cpu_id;
 #define S3C24XX_CPU_ID          0x32400000
 #define S3C24XX_CPU_MASK        0xFFF00000
 
+#define S3C2412_CPU_ID          0x32412000
+#define S3C2412_CPU_MASK        0xFFFFF000
+
 #define S3C6400_CPU_ID          0x36400000
 #define S3C6410_CPU_ID          0x36410000
 #define S3C64XX_CPU_MASK        0xFFFFF000
@@ -53,6 +56,7 @@ static inline int is_samsung_##name(void)	\
 }
 
 IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
+IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
@@ -74,6 +78,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s3c24xx()       0
 #endif
 
+#if defined(CONFIG_CPU_S3C2412)
+# define soc_is_s3c2412()       is_samsung_s3c2412()
+#else
+# define soc_is_s3c2412()       0
+#endif
+
 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
 # define soc_is_s3c64xx()       (is_samsung_s3c6400() || is_samsung_s3c6410())
 #else
@@ -173,7 +183,6 @@ extern void s3c_init_cpu(unsigned long idcode,
 
 /* core initialisation functions */
 
-extern void s3c24xx_init_irq(void);
 extern void s5p_init_irq(u32 *vic, u32 num_vic);
 
 extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
@@ -192,10 +201,6 @@ extern void s3c24xx_init_uartdevs(char *name,
                                   struct s3c24xx_uart_resources *res,
                                   struct s3c2410_uartcfg *cfg, int no);
 
-/* timer for 2410/2440 */
-
-extern void s3c24xx_timer_init(void);
-
 extern struct syscore_ops s3c2410_pm_syscore_ops;
 extern struct syscore_ops s3c2412_pm_syscore_ops;
 extern struct syscore_ops s3c2416_pm_syscore_ops;
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
deleted file mode 100644
index 9c96f3586ce0..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-time.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
- *
- * Copyright 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Header file for s5p time support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S5P_TIME_H
-#define __ASM_PLAT_S5P_TIME_H __FILE__
-
-/* S5P HR-Timer Clock mode */
-enum s5p_timer_mode {
-        S5P_PWM0,
-        S5P_PWM1,
-        S5P_PWM2,
-        S5P_PWM3,
-        S5P_PWM4,
-};
-
-struct s5p_timer_source {
-        unsigned int event_id;
-        unsigned int source_id;
-};
-
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define S5PTIMER_MIN_RANGE      4
-
-#define TCNT_MAX                0xffffffff
-#define NON_PERIODIC            0
-#define PERIODIC                1
-
-extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                        enum s5p_timer_mode source);
-extern  void s5p_timer_init(void);
-#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
new file mode 100644
index 000000000000..4cc99bb1f176
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/samsung-time.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-samsung/include/plat/samsung-time.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for samsung s3c and s5p time support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_SAMSUNG_TIME_H
+#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__
+
+/* SAMSUNG HR-Timer Clock mode */
+enum samsung_timer_mode {
+        SAMSUNG_PWM0,
+        SAMSUNG_PWM1,
+        SAMSUNG_PWM2,
+        SAMSUNG_PWM3,
+        SAMSUNG_PWM4,
+};
+
+struct samsung_timer_source {
+        unsigned int event_id;
+        unsigned int source_id;
+};
+
+/* Be able to sleep for atleast 4 seconds (usually more) */
+#define SAMSUNG_TIMER_MIN_RANGE 4
+
+#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100)
+#define TCNT_MAX                0xffff
+#define TSCALER_DIV             25
+#define TDIV                    50
+#define TSIZE                   16
+#else
+#define TCNT_MAX                0xffffffff
+#define TSCALER_DIV             2
+#define TDIV                    2
+#define TSIZE                   32
+#endif
+
+#define NON_PERIODIC            0
+#define PERIODIC                1
+
+extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                        enum samsung_timer_mode source);
+
+extern void __init samsung_timer_init(void);
+
+#endif /* __ASM_PLAT_SAMSUNG_TIME_H */
diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/samsung-time.c
index e92510cf82ee..f899cbc9b288 100644
--- a/arch/arm/plat-samsung/s5p-time.c
+++ b/arch/arm/plat-samsung/samsung-time.c
@@ -2,7 +2,7 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
- * S5P - Common hr-timer support
+ * samsung - Common hr-timer support (s3c and s5p)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,41 +25,41 @@
 #include <mach/map.h>
 #include <plat/devs.h>
 #include <plat/regs-timer.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 static struct clk *tin_event;
 static struct clk *tin_source;
 static struct clk *tdiv_event;
 static struct clk *tdiv_source;
 static struct clk *timerclk;
-static struct s5p_timer_source timer_source;
+static struct samsung_timer_source timer_source;
 static unsigned long clock_count_per_tick;
-static void s5p_timer_resume(void);
+static void samsung_timer_resume(void);
 
-static void s5p_time_stop(enum s5p_timer_mode mode)
+static void samsung_time_stop(enum samsung_timer_mode mode)
 {
         unsigned long tcon;
 
         tcon = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~S3C2410_TCON_T0START;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~S3C2410_TCON_T1START;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~S3C2410_TCON_T2START;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~S3C2410_TCON_T3START;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~S3C2410_TCON_T4START;
                 break;
 
@@ -70,7 +70,7 @@ static void s5p_time_stop(enum s5p_timer_mode mode)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
+static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt)
 {
         unsigned long tcon;
 
@@ -79,27 +79,27 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         tcnt--;
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~(0x0f << 0);
                 tcon |= S3C2410_TCON_T0MANUALUPD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~(0x0f << 8);
                 tcon |= S3C2410_TCON_T1MANUALUPD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~(0x0f << 12);
                 tcon |= S3C2410_TCON_T2MANUALUPD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~(0x0f << 16);
                 tcon |= S3C2410_TCON_T3MANUALUPD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~(0x07 << 20);
                 tcon |= S3C2410_TCON_T4MANUALUPD;
                 break;
@@ -114,14 +114,14 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
+static void samsung_time_start(enum samsung_timer_mode mode, bool periodic)
 {
         unsigned long tcon;
 
         tcon  = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon |= S3C2410_TCON_T0START;
                 tcon &= ~S3C2410_TCON_T0MANUALUPD;
 
@@ -131,7 +131,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T0RELOAD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon |= S3C2410_TCON_T1START;
                 tcon &= ~S3C2410_TCON_T1MANUALUPD;
 
@@ -141,7 +141,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T1RELOAD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon |= S3C2410_TCON_T2START;
                 tcon &= ~S3C2410_TCON_T2MANUALUPD;
 
@@ -151,7 +151,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T2RELOAD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon |= S3C2410_TCON_T3START;
                 tcon &= ~S3C2410_TCON_T3MANUALUPD;
 
@@ -161,7 +161,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T3RELOAD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon |= S3C2410_TCON_T4START;
                 tcon &= ~S3C2410_TCON_T4MANUALUPD;
 
@@ -178,24 +178,24 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static int s5p_set_next_event(unsigned long cycles,
+static int samsung_set_next_event(unsigned long cycles,
                                 struct clock_event_device *evt)
 {
-        s5p_time_setup(timer_source.event_id, cycles);
-        s5p_time_start(timer_source.event_id, NON_PERIODIC);
+        samsung_time_setup(timer_source.event_id, cycles);
+        samsung_time_start(timer_source.event_id, NON_PERIODIC);
 
         return 0;
 }
 
-static void s5p_set_mode(enum clock_event_mode mode,
+static void samsung_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *evt)
 {
-        s5p_time_stop(timer_source.event_id);
+        samsung_time_stop(timer_source.event_id);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-                s5p_time_start(timer_source.event_id, PERIODIC);
+                samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+                samsung_time_start(timer_source.event_id, PERIODIC);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -206,24 +206,24 @@ static void s5p_set_mode(enum clock_event_mode mode,
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
-                s5p_timer_resume();
+                samsung_timer_resume();
                 break;
         }
 }
 
-static void s5p_timer_resume(void)
+static void samsung_timer_resume(void)
 {
         /* event timer restart */
-        s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-        s5p_time_start(timer_source.event_id, PERIODIC);
+        samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+        samsung_time_start(timer_source.event_id, PERIODIC);
 
         /* source timer restart */
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 }
 
-void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                 enum s5p_timer_mode source)
+void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                 enum samsung_timer_mode source)
 {
         s3c_device_timer[event].dev.bus = &platform_bus_type;
         s3c_device_timer[source].dev.bus = &platform_bus_type;
@@ -233,14 +233,14 @@ void __init s5p_set_timer_source(enum s5p_timer_mode event,
 }
 
 static struct clock_event_device time_event_device = {
-        .name           = "s5p_event_timer",
+        .name           = "samsung_event_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
-        .set_next_event = s5p_set_next_event,
-        .set_mode       = s5p_set_mode,
+        .set_next_event = samsung_set_next_event,
+        .set_mode       = samsung_set_mode,
 };
 
-static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
+static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
 {
         struct clock_event_device *evt = dev_id;
 
@@ -249,14 +249,14 @@ static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction s5p_clock_event_irq = {
-        .name           = "s5p_time_irq",
+static struct irqaction samsung_clock_event_irq = {
+        .name           = "samsung_time_irq",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s5p_clock_event_isr,
+        .handler        = samsung_clock_event_isr,
         .dev_id         = &time_event_device,
 };
 
-static void __init s5p_clockevent_init(void)
+static void __init samsung_clockevent_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
@@ -267,8 +267,8 @@ static void __init s5p_clockevent_init(void)
 
         tscaler = clk_get_parent(tdiv_event);
 
-        clk_set_rate(tscaler, pclk / 2);
-        clk_set_rate(tdiv_event, pclk / 2);
+        clk_set_rate(tscaler, pclk / TSCALER_DIV);
+        clk_set_rate(tdiv_event, pclk / TDIV);
         clk_set_parent(tin_event, tdiv_event);
 
         clock_rate = clk_get_rate(tin_event);
@@ -278,22 +278,22 @@ static void __init s5p_clockevent_init(void)
         clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
 
         irq_number = timer_source.event_id + IRQ_TIMER0;
-        setup_irq(irq_number, &s5p_clock_event_irq);
+        setup_irq(irq_number, &samsung_clock_event_irq);
 }
 
-static void __iomem *s5p_timer_reg(void)
+static void __iomem *samsung_timer_reg(void)
 {
         unsigned long offset = 0;
 
         switch (timer_source.source_id) {
-        case S5P_PWM0:
-        case S5P_PWM1:
-        case S5P_PWM2:
-        case S5P_PWM3:
+        case SAMSUNG_PWM0:
+        case SAMSUNG_PWM1:
+        case SAMSUNG_PWM2:
+        case SAMSUNG_PWM3:
                 offset = (timer_source.source_id * 0x0c) + 0x14;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 offset = 0x40;
                 break;
 
@@ -312,9 +312,9 @@ static void __iomem *s5p_timer_reg(void)
  * this wraps around for now, since it is just a relative time
  * stamp. (Inspired by U300 implementation.)
  */
-static u32 notrace s5p_read_sched_clock(void)
+static u32 notrace samsung_read_sched_clock(void)
 {
-        void __iomem *reg = s5p_timer_reg();
+        void __iomem *reg = samsung_timer_reg();
 
         if (!reg)
                 return 0;
@@ -322,29 +322,29 @@ static u32 notrace s5p_read_sched_clock(void)
         return ~__raw_readl(reg);
 }
 
-static void __init s5p_clocksource_init(void)
+static void __init samsung_clocksource_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
 
         pclk = clk_get_rate(timerclk);
 
-        clk_set_rate(tdiv_source, pclk / 2);
+        clk_set_rate(tdiv_source, pclk / TDIV);
         clk_set_parent(tin_source, tdiv_source);
 
         clock_rate = clk_get_rate(tin_source);
 
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 
-        setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
+        setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate);
 
-        if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
-                        clock_rate, 250, 32, clocksource_mmio_readl_down))
-                panic("s5p_clocksource_timer: can't register clocksource\n");
+        if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer",
+                        clock_rate, 250, TSIZE, clocksource_mmio_readl_down))
+                panic("samsung_clocksource_timer: can't register clocksource\n");
 }
 
-static void __init s5p_timer_resources(void)
+static void __init samsung_timer_resources(void)
 {
 
         unsigned long event_id = timer_source.event_id;
@@ -386,9 +386,9 @@ static void __init s5p_timer_resources(void)
         clk_enable(tin_source);
 }
 
-void __init s5p_timer_init(void)
+void __init samsung_timer_init(void)
 {
-        s5p_timer_resources();
-        s5p_clockevent_init();
-        s5p_clocksource_init();
+        samsung_timer_resources();
+        samsung_clockevent_init();
+        samsung_clocksource_init();
 }
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
deleted file mode 100644
index 73defd00c3e4..000000000000
--- a/arch/arm/plat-samsung/time.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* linux/arch/arm/plat-samsung/time.c
- *
- * Copyright (C) 2003-2005 Simtec Electronics
- *      Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/mach-types.h>
-
-#include <asm/irq.h>
-#include <mach/map.h>
-#include <plat/regs-timer.h>
-#include <mach/regs-irq.h>
-#include <asm/mach/time.h>
-#include <mach/tick.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-static unsigned long timer_startval;
-static unsigned long timer_usec_ticks;
-
-#ifndef TICK_MAX
-#define TICK_MAX (0xffff)
-#endif
-
-#define TIMER_USEC_SHIFT 16
-
-/* we use the shifted arithmetic to work out the ratio of timer ticks
- * to usecs, as often the peripheral clock is not a nice even multiple
- * of 1MHz.
- *
- * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
- * for the current HZ value of 200 without producing overflows.
- *
- * Original patch by Dimitry Andric, updated by Ben Dooks
-*/
-
-
-/* timer_mask_usec_ticks
- *
- * given a clock and divisor, make the value to pass into timer_ticks_to_usec
- * to scale the ticks into usecs
-*/
-
-static inline unsigned long
-timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
-{
-        unsigned long den = pclk / 1000;
-
-        return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
-}
-
-/* timer_ticks_to_usec
- *
- * convert timer ticks to usec.
-*/
-
-static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
-{
-        unsigned long res;
-
-        res = ticks * timer_usec_ticks;
-        res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
-
-        return res >> TIMER_USEC_SHIFT;
-}
-
-/***
- * Returns microsecond  since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- * IRQs are disabled before entering here from do_gettimeofday()
- */
-
-static u32 s3c2410_gettimeoffset(void)
-{
-        unsigned long tdone;
-        unsigned long tval;
-
-        /* work out how many ticks have gone since last timer interrupt */
-
-        tval =  __raw_readl(S3C2410_TCNTO(4));
-        tdone = timer_startval - tval;
-
-        /* check to see if there is an interrupt pending */
-
-        if (s3c24xx_ostimer_pending()) {
-                /* re-read the timer, and try and fix up for the missed
-                 * interrupt. Note, the interrupt may go off before the
-                 * timer has re-loaded from wrapping.
-                 */
-
-                tval =  __raw_readl(S3C2410_TCNTO(4));
-                tdone = timer_startval - tval;
-
-                if (tval != 0)
-                        tdone += timer_startval;
-        }
-
-        return timer_ticks_to_usec(tdone) * 1000;
-}
-
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-s3c2410_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        return IRQ_HANDLED;
-}
-
-static struct irqaction s3c2410_timer_irq = {
-        .name           = "S3C2410 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s3c2410_timer_interrupt,
-};
-
-#define use_tclk1_12() ( \
-        machine_is_bast()       || \
-        machine_is_vr1000()     || \
-        machine_is_anubis()     || \
-        machine_is_osiris())
-
-static struct clk *tin;
-static struct clk *tdiv;
-static struct clk *timerclk;
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- *
- * Currently we only use timer4, as it is the only timer which has no
- * other function that can be exploited externally
- */
-static void s3c2410_timer_setup (void)
-{
-        unsigned long tcon;
-        unsigned long tcnt;
-        unsigned long tcfg1;
-        unsigned long tcfg0;
-
-        tcnt = TICK_MAX;  /* default value for tcnt */
-
-        /* configure the system for whichever machine is in use */
-
-        if (use_tclk1_12()) {
-                /* timer is at 12MHz, scaler is 1 */
-                timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
-                tcnt = 12000000 / HZ;
-
-                tcfg1 = __raw_readl(S3C2410_TCFG1);
-                tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
-                tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
-                __raw_writel(tcfg1, S3C2410_TCFG1);
-        } else {
-                unsigned long pclk;
-                struct clk *tscaler;
-
-                /* for the h1940 (and others), we use the pclk from the core
-                 * to generate the timer values. since values around 50 to
-                 * 70MHz are not values we can directly generate the timer
-                 * value from, we need to pre-scale and divide before using it.
-                 *
-                 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
-                 * (8.45 ticks per usec)
-                 */
-
-                pclk = clk_get_rate(timerclk);
-
-                /* configure clock tick */
-
-                timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
-
-                tscaler = clk_get_parent(tdiv);
-
-                clk_set_rate(tscaler, pclk / 3);
-                clk_set_rate(tdiv, pclk / 6);
-                clk_set_parent(tin, tdiv);
-
-                tcnt = clk_get_rate(tin) / HZ;
-        }
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcfg0 = __raw_readl(S3C2410_TCFG0);
-        tcfg1 = __raw_readl(S3C2410_TCFG1);
-
-        /* timers reload after counting zero, so reduce the count by 1 */
-
-        tcnt--;
-
-        printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
-               tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
-
-        /* check to see if timer is within 16bit range... */
-        if (tcnt > TICK_MAX) {
-                panic("setup_timer: HZ is too small, cannot configure timer!");
-                return;
-        }
-
-        __raw_writel(tcfg1, S3C2410_TCFG1);
-        __raw_writel(tcfg0, S3C2410_TCFG0);
-
-        timer_startval = tcnt;
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-
-        /* ensure timer is stopped... */
-
-        tcon &= ~(7<<20);
-        tcon |= S3C2410_TCON_T4RELOAD;
-        tcon |= S3C2410_TCON_T4MANUALUPD;
-
-        __raw_writel(tcon, S3C2410_TCON);
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-        __raw_writel(tcnt, S3C2410_TCMPB(4));
-
-        /* start the timer running */
-        tcon |= S3C2410_TCON_T4START;
-        tcon &= ~S3C2410_TCON_T4MANUALUPD;
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void __init s3c2410_timer_resources(void)
-{
-        struct platform_device tmpdev;
-
-        tmpdev.dev.bus = &platform_bus_type;
-        tmpdev.id = 4;
-
-        timerclk = clk_get(NULL, "timers");
-        if (IS_ERR(timerclk))
-                panic("failed to get clock for system timer");
-
-        clk_enable(timerclk);
-
-        if (!use_tclk1_12()) {
-                tmpdev.id = 4;
-                tmpdev.dev.init_name = "s3c24xx-pwm.4";
-                tin = clk_get(&tmpdev.dev, "pwm-tin");
-                if (IS_ERR(tin))
-                        panic("failed to get pwm-tin clock for system timer");
-
-                tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
-                if (IS_ERR(tdiv))
-                        panic("failed to get pwm-tdiv clock for system timer");
-        }
-
-        clk_enable(tin);
-}
-
-static struct syscore_ops s3c24xx_syscore_ops = {
-        .resume         = s3c2410_timer_setup,
-};
-
-void __init s3c24xx_timer_init(void)
-{
-        arch_gettimeoffset = s3c2410_gettimeoffset;
-
-        s3c2410_timer_resources();
-        s3c2410_timer_setup();
-        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
-        register_syscore_ops(&s3c24xx_syscore_ops);
-}
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index b323d8d3185b..7c2f6685bf43 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1453,7 +1453,7 @@ static struct resource atmel_lcdfb0_resource[] = {
         },
 };
 DEFINE_DEV_DATA(atmel_lcdfb, 0);
-DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
+DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
 static struct clk atmel_lcdfb0_pixclk = {
         .name           = "lcdc_clk",
         .dev            = &atmel_lcdfb0_device.dev,
@@ -1530,6 +1530,8 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
         info->default_monspecs = monspecs;
 
+        pdev->name = "at32ap-lcdfb";
+
         platform_device_register(pdev);
         return pdev;
 
@@ -2246,7 +2248,7 @@ static __initdata struct clk *init_clocks[] = {
         &atmel_twi0_pclk,
         &atmel_mci0_pclk,
 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
-        &atmel_lcdfb0_hck1,
+        &atmel_lcdfb0_hclk,
         &atmel_lcdfb0_pixclk,
 #endif
         &ssc0_pclk,