diff options
Diffstat (limited to 'arch/arm/mach-s3c24xx/include/mach/irqs.h')
-rw-r--r-- | arch/arm/mach-s3c24xx/include/mach/irqs.h | 58 |
1 files changed, 31 insertions, 27 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h index 1e73f5fa8659..b6dd4cb5a2ec 100644 --- a/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h | |||
@@ -59,49 +59,53 @@ | |||
59 | #define IRQ_ADCPARENT S3C2410_IRQ(31) | 59 | #define IRQ_ADCPARENT S3C2410_IRQ(31) |
60 | 60 | ||
61 | /* interrupts generated from the external interrupts sources */ | 61 | /* interrupts generated from the external interrupts sources */ |
62 | #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ | 62 | #define IRQ_EINT0_2412 S3C2410_IRQ(32) |
63 | #define IRQ_EINT5 S3C2410_IRQ(33) | 63 | #define IRQ_EINT1_2412 S3C2410_IRQ(33) |
64 | #define IRQ_EINT6 S3C2410_IRQ(34) | 64 | #define IRQ_EINT2_2412 S3C2410_IRQ(34) |
65 | #define IRQ_EINT7 S3C2410_IRQ(35) | 65 | #define IRQ_EINT3_2412 S3C2410_IRQ(35) |
66 | #define IRQ_EINT8 S3C2410_IRQ(36) | 66 | #define IRQ_EINT4 S3C2410_IRQ(36) /* 52 */ |
67 | #define IRQ_EINT9 S3C2410_IRQ(37) | 67 | #define IRQ_EINT5 S3C2410_IRQ(37) |
68 | #define IRQ_EINT10 S3C2410_IRQ(38) | 68 | #define IRQ_EINT6 S3C2410_IRQ(38) |
69 | #define IRQ_EINT11 S3C2410_IRQ(39) | 69 | #define IRQ_EINT7 S3C2410_IRQ(39) |
70 | #define IRQ_EINT12 S3C2410_IRQ(40) | 70 | #define IRQ_EINT8 S3C2410_IRQ(40) |
71 | #define IRQ_EINT13 S3C2410_IRQ(41) | 71 | #define IRQ_EINT9 S3C2410_IRQ(41) |
72 | #define IRQ_EINT14 S3C2410_IRQ(42) | 72 | #define IRQ_EINT10 S3C2410_IRQ(42) |
73 | #define IRQ_EINT15 S3C2410_IRQ(43) | 73 | #define IRQ_EINT11 S3C2410_IRQ(43) |
74 | #define IRQ_EINT16 S3C2410_IRQ(44) | 74 | #define IRQ_EINT12 S3C2410_IRQ(44) |
75 | #define IRQ_EINT17 S3C2410_IRQ(45) | 75 | #define IRQ_EINT13 S3C2410_IRQ(45) |
76 | #define IRQ_EINT18 S3C2410_IRQ(46) | 76 | #define IRQ_EINT14 S3C2410_IRQ(46) |
77 | #define IRQ_EINT19 S3C2410_IRQ(47) | 77 | #define IRQ_EINT15 S3C2410_IRQ(47) |
78 | #define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ | 78 | #define IRQ_EINT16 S3C2410_IRQ(48) |
79 | #define IRQ_EINT21 S3C2410_IRQ(49) | 79 | #define IRQ_EINT17 S3C2410_IRQ(49) |
80 | #define IRQ_EINT22 S3C2410_IRQ(50) | 80 | #define IRQ_EINT18 S3C2410_IRQ(50) |
81 | #define IRQ_EINT23 S3C2410_IRQ(51) | 81 | #define IRQ_EINT19 S3C2410_IRQ(51) |
82 | #define IRQ_EINT20 S3C2410_IRQ(52) /* 68 */ | ||
83 | #define IRQ_EINT21 S3C2410_IRQ(53) | ||
84 | #define IRQ_EINT22 S3C2410_IRQ(54) | ||
85 | #define IRQ_EINT23 S3C2410_IRQ(55) | ||
82 | 86 | ||
83 | #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) | 87 | #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) |
84 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) | 88 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) |
85 | 89 | ||
86 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) | 90 | #define IRQ_LCD_FIFO S3C2410_IRQ(56) |
87 | #define IRQ_LCD_FRAME S3C2410_IRQ(53) | 91 | #define IRQ_LCD_FRAME S3C2410_IRQ(57) |
88 | 92 | ||
89 | /* IRQs for the interal UARTs, and ADC | 93 | /* IRQs for the interal UARTs, and ADC |
90 | * these need to be ordered in number of appearance in the | 94 | * these need to be ordered in number of appearance in the |
91 | * SUBSRC mask register | 95 | * SUBSRC mask register |
92 | */ | 96 | */ |
93 | 97 | ||
94 | #define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54) | 98 | #define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+58) |
95 | 99 | ||
96 | #define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */ | 100 | #define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 74 */ |
97 | #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) | 101 | #define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1) |
98 | #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) | 102 | #define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2) |
99 | 103 | ||
100 | #define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */ | 104 | #define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 77 */ |
101 | #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) | 105 | #define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4) |
102 | #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) | 106 | #define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5) |
103 | 107 | ||
104 | #define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */ | 108 | #define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 80 */ |
105 | #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) | 109 | #define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7) |
106 | #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) | 110 | #define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8) |
107 | 111 | ||
@@ -136,7 +140,7 @@ | |||
136 | 140 | ||
137 | /* second interrupt-register of s3c2416/s3c2450 */ | 141 | /* second interrupt-register of s3c2416/s3c2450 */ |
138 | 142 | ||
139 | #define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29) | 143 | #define S3C2416_IRQ(x) S3C2410_IRQ((x) + 58 + 29) |
140 | #define IRQ_S3C2416_2D S3C2416_IRQ(0) | 144 | #define IRQ_S3C2416_2D S3C2416_IRQ(0) |
141 | #define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) | 145 | #define IRQ_S3C2416_IIC1 S3C2416_IRQ(1) |
142 | #define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) | 146 | #define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2) |