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-rw-r--r--arch/xtensa/mm/mmu.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
index 0f77f9d3bb8b..a1077570e383 100644
--- a/arch/xtensa/mm/mmu.c
+++ b/arch/xtensa/mm/mmu.c
@@ -24,15 +24,19 @@ void __init paging_init(void)
24 */ 24 */
25void __init init_mmu(void) 25void __init init_mmu(void)
26{ 26{
27 /* Writing zeros to the <t>TLBCFG special registers ensure 27#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
28 * that valid values exist in the register. For existing 28 /*
29 * PGSZID<w> fields, zero selects the first element of the 29 * Writing zeros to the instruction and data TLBCFG special
30 * page-size array. For nonexistent PGSZID<w> fields, zero is 30 * registers ensure that valid values exist in the register.
31 * the best value to write. Also, when changing PGSZID<w> 31 *
32 * For existing PGSZID<w> fields, zero selects the first element
33 * of the page-size array. For nonexistent PGSZID<w> fields,
34 * zero is the best value to write. Also, when changing PGSZID<w>
32 * fields, the corresponding TLB must be flushed. 35 * fields, the corresponding TLB must be flushed.
33 */ 36 */
34 set_itlbcfg_register(0); 37 set_itlbcfg_register(0);
35 set_dtlbcfg_register(0); 38 set_dtlbcfg_register(0);
39#endif
36 flush_tlb_all(); 40 flush_tlb_all();
37 41
38 /* Set rasid register to a known value. */ 42 /* Set rasid register to a known value. */