diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-09 17:38:16 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-05-09 17:38:16 -0400 |
commit | c61c48dfe00907007df3b87e4ed271a5c143bdda (patch) | |
tree | 6d26bd3a8b4aa3cf35cad35fa27d1e0afe715db3 /arch/xtensa/mm | |
parent | e30f4192456971623b40c97a027346b69457ef69 (diff) | |
parent | b341d84c8ac5ecbf7aa0b3ccd0745d87e881953c (diff) |
Merge tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux
Pull xtensa updates from Chris Zankel:
"Support for the latest MMU architecture that allows for a larger
accessible memory region, and various bug-fixes"
* tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux:
xtensa: Switch to asm-generic/linkage.h
xtensa: fix redboot load address
xtensa: ISS: fix timer_lock usage in rs_open
xtensa: disable IRQs while IRQ handler is running
xtensa: enable lockdep support
xtensa: fix arch_irqs_disabled_flags implementation
xtensa: add irq flags trace support
xtensa: provide custom CALLER_ADDR* implementations
xtensa: add stacktrace support
xtensa: clean up stpill_registers
xtensa: don't use a7 in simcalls
xtensa: don't attempt to use unconfigured timers
xtensa: provide default platform_pcibios_init implementation
xtensa: remove KCORE_ELF again
xtensa: document MMUv3 setup sequence
xtensa: add MMU v3 support
xtensa: fix ibreakenable register update
xtensa: fix oprofile building as module
Diffstat (limited to 'arch/xtensa/mm')
-rw-r--r-- | arch/xtensa/mm/mmu.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c index 0f77f9d3bb8b..a1077570e383 100644 --- a/arch/xtensa/mm/mmu.c +++ b/arch/xtensa/mm/mmu.c | |||
@@ -24,15 +24,19 @@ void __init paging_init(void) | |||
24 | */ | 24 | */ |
25 | void __init init_mmu(void) | 25 | void __init init_mmu(void) |
26 | { | 26 | { |
27 | /* Writing zeros to the <t>TLBCFG special registers ensure | 27 | #if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY) |
28 | * that valid values exist in the register. For existing | 28 | /* |
29 | * PGSZID<w> fields, zero selects the first element of the | 29 | * Writing zeros to the instruction and data TLBCFG special |
30 | * page-size array. For nonexistent PGSZID<w> fields, zero is | 30 | * registers ensure that valid values exist in the register. |
31 | * the best value to write. Also, when changing PGSZID<w> | 31 | * |
32 | * For existing PGSZID<w> fields, zero selects the first element | ||
33 | * of the page-size array. For nonexistent PGSZID<w> fields, | ||
34 | * zero is the best value to write. Also, when changing PGSZID<w> | ||
32 | * fields, the corresponding TLB must be flushed. | 35 | * fields, the corresponding TLB must be flushed. |
33 | */ | 36 | */ |
34 | set_itlbcfg_register(0); | 37 | set_itlbcfg_register(0); |
35 | set_dtlbcfg_register(0); | 38 | set_dtlbcfg_register(0); |
39 | #endif | ||
36 | flush_tlb_all(); | 40 | flush_tlb_all(); |
37 | 41 | ||
38 | /* Set rasid register to a known value. */ | 42 | /* Set rasid register to a known value. */ |