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-rw-r--r--arch/x86/include/uapi/asm/Kbuild58
-rw-r--r--arch/x86/include/uapi/asm/a.out.h20
-rw-r--r--arch/x86/include/uapi/asm/auxvec.h19
-rw-r--r--arch/x86/include/uapi/asm/bitsperlong.h13
-rw-r--r--arch/x86/include/uapi/asm/boot.h10
-rw-r--r--arch/x86/include/uapi/asm/bootparam.h139
-rw-r--r--arch/x86/include/uapi/asm/byteorder.h6
-rw-r--r--arch/x86/include/uapi/asm/debugreg.h80
-rw-r--r--arch/x86/include/uapi/asm/e820.h75
-rw-r--r--arch/x86/include/uapi/asm/errno.h1
-rw-r--r--arch/x86/include/uapi/asm/fcntl.h1
-rw-r--r--arch/x86/include/uapi/asm/hw_breakpoint.h0
-rw-r--r--arch/x86/include/uapi/asm/hyperv.h194
-rw-r--r--arch/x86/include/uapi/asm/ioctl.h1
-rw-r--r--arch/x86/include/uapi/asm/ioctls.h1
-rw-r--r--arch/x86/include/uapi/asm/ipcbuf.h1
-rw-r--r--arch/x86/include/uapi/asm/ist.h29
-rw-r--r--arch/x86/include/uapi/asm/kvm.h346
-rw-r--r--arch/x86/include/uapi/asm/kvm_para.h100
-rw-r--r--arch/x86/include/uapi/asm/ldt.h40
-rw-r--r--arch/x86/include/uapi/asm/mce.h121
-rw-r--r--arch/x86/include/uapi/asm/mman.h11
-rw-r--r--arch/x86/include/uapi/asm/msgbuf.h1
-rw-r--r--arch/x86/include/uapi/asm/msr-index.h488
-rw-r--r--arch/x86/include/uapi/asm/msr.h15
-rw-r--r--arch/x86/include/uapi/asm/mtrr.h117
-rw-r--r--arch/x86/include/uapi/asm/param.h1
-rw-r--r--arch/x86/include/uapi/asm/perf_regs.h33
-rw-r--r--arch/x86/include/uapi/asm/poll.h1
-rw-r--r--arch/x86/include/uapi/asm/posix_types.h9
-rw-r--r--arch/x86/include/uapi/asm/posix_types_32.h25
-rw-r--r--arch/x86/include/uapi/asm/posix_types_64.h19
-rw-r--r--arch/x86/include/uapi/asm/posix_types_x32.h19
-rw-r--r--arch/x86/include/uapi/asm/prctl.h9
-rw-r--r--arch/x86/include/uapi/asm/processor-flags.h99
-rw-r--r--arch/x86/include/uapi/asm/ptrace-abi.h87
-rw-r--r--arch/x86/include/uapi/asm/ptrace.h78
-rw-r--r--arch/x86/include/uapi/asm/resource.h1
-rw-r--r--arch/x86/include/uapi/asm/sembuf.h24
-rw-r--r--arch/x86/include/uapi/asm/setup.h0
-rw-r--r--arch/x86/include/uapi/asm/shmbuf.h1
-rw-r--r--arch/x86/include/uapi/asm/sigcontext.h221
-rw-r--r--arch/x86/include/uapi/asm/sigcontext32.h77
-rw-r--r--arch/x86/include/uapi/asm/siginfo.h16
-rw-r--r--arch/x86/include/uapi/asm/signal.h145
-rw-r--r--arch/x86/include/uapi/asm/socket.h1
-rw-r--r--arch/x86/include/uapi/asm/sockios.h1
-rw-r--r--arch/x86/include/uapi/asm/stat.h135
-rw-r--r--arch/x86/include/uapi/asm/statfs.h12
-rw-r--r--arch/x86/include/uapi/asm/svm.h132
-rw-r--r--arch/x86/include/uapi/asm/swab.h36
-rw-r--r--arch/x86/include/uapi/asm/termbits.h1
-rw-r--r--arch/x86/include/uapi/asm/termios.h1
-rw-r--r--arch/x86/include/uapi/asm/types.h6
-rw-r--r--arch/x86/include/uapi/asm/ucontext.h12
-rw-r--r--arch/x86/include/uapi/asm/unistd.h17
-rw-r--r--arch/x86/include/uapi/asm/vm86.h129
-rw-r--r--arch/x86/include/uapi/asm/vmx.h109
-rw-r--r--arch/x86/include/uapi/asm/vsyscall.h17
59 files changed, 3361 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/Kbuild b/arch/x86/include/uapi/asm/Kbuild
index 83b6e9a0dce4..09409c44f9a5 100644
--- a/arch/x86/include/uapi/asm/Kbuild
+++ b/arch/x86/include/uapi/asm/Kbuild
@@ -4,3 +4,61 @@ include include/uapi/asm-generic/Kbuild.asm
4genhdr-y += unistd_32.h 4genhdr-y += unistd_32.h
5genhdr-y += unistd_64.h 5genhdr-y += unistd_64.h
6genhdr-y += unistd_x32.h 6genhdr-y += unistd_x32.h
7header-y += a.out.h
8header-y += auxvec.h
9header-y += bitsperlong.h
10header-y += boot.h
11header-y += bootparam.h
12header-y += byteorder.h
13header-y += debugreg.h
14header-y += e820.h
15header-y += errno.h
16header-y += fcntl.h
17header-y += hw_breakpoint.h
18header-y += hyperv.h
19header-y += ioctl.h
20header-y += ioctls.h
21header-y += ipcbuf.h
22header-y += ist.h
23header-y += kvm.h
24header-y += kvm_para.h
25header-y += ldt.h
26header-y += mce.h
27header-y += mman.h
28header-y += msgbuf.h
29header-y += msr-index.h
30header-y += msr.h
31header-y += mtrr.h
32header-y += param.h
33header-y += perf_regs.h
34header-y += poll.h
35header-y += posix_types.h
36header-y += posix_types_32.h
37header-y += posix_types_64.h
38header-y += posix_types_x32.h
39header-y += prctl.h
40header-y += processor-flags.h
41header-y += ptrace-abi.h
42header-y += ptrace.h
43header-y += resource.h
44header-y += sembuf.h
45header-y += setup.h
46header-y += shmbuf.h
47header-y += sigcontext.h
48header-y += sigcontext32.h
49header-y += siginfo.h
50header-y += signal.h
51header-y += socket.h
52header-y += sockios.h
53header-y += stat.h
54header-y += statfs.h
55header-y += svm.h
56header-y += swab.h
57header-y += termbits.h
58header-y += termios.h
59header-y += types.h
60header-y += ucontext.h
61header-y += unistd.h
62header-y += vm86.h
63header-y += vmx.h
64header-y += vsyscall.h
diff --git a/arch/x86/include/uapi/asm/a.out.h b/arch/x86/include/uapi/asm/a.out.h
new file mode 100644
index 000000000000..4684f97a5bbd
--- /dev/null
+++ b/arch/x86/include/uapi/asm/a.out.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_X86_A_OUT_H
2#define _ASM_X86_A_OUT_H
3
4struct exec
5{
6 unsigned int a_info; /* Use macros N_MAGIC, etc for access */
7 unsigned a_text; /* length of text, in bytes */
8 unsigned a_data; /* length of data, in bytes */
9 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
10 unsigned a_syms; /* length of symbol table data in file, in bytes */
11 unsigned a_entry; /* start address */
12 unsigned a_trsize; /* length of relocation info for text, in bytes */
13 unsigned a_drsize; /* length of relocation info for data, in bytes */
14};
15
16#define N_TRSIZE(a) ((a).a_trsize)
17#define N_DRSIZE(a) ((a).a_drsize)
18#define N_SYMSIZE(a) ((a).a_syms)
19
20#endif /* _ASM_X86_A_OUT_H */
diff --git a/arch/x86/include/uapi/asm/auxvec.h b/arch/x86/include/uapi/asm/auxvec.h
new file mode 100644
index 000000000000..77203ac352de
--- /dev/null
+++ b/arch/x86/include/uapi/asm/auxvec.h
@@ -0,0 +1,19 @@
1#ifndef _ASM_X86_AUXVEC_H
2#define _ASM_X86_AUXVEC_H
3/*
4 * Architecture-neutral AT_ values in 0-17, leave some room
5 * for more of them, start the x86-specific ones at 32.
6 */
7#ifdef __i386__
8#define AT_SYSINFO 32
9#endif
10#define AT_SYSINFO_EHDR 33
11
12/* entries in ARCH_DLINFO: */
13#if defined(CONFIG_IA32_EMULATION) || !defined(CONFIG_X86_64)
14# define AT_VECTOR_SIZE_ARCH 2
15#else /* else it's non-compat x86-64 */
16# define AT_VECTOR_SIZE_ARCH 1
17#endif
18
19#endif /* _ASM_X86_AUXVEC_H */
diff --git a/arch/x86/include/uapi/asm/bitsperlong.h b/arch/x86/include/uapi/asm/bitsperlong.h
new file mode 100644
index 000000000000..b0ae1c4dc791
--- /dev/null
+++ b/arch/x86/include/uapi/asm/bitsperlong.h
@@ -0,0 +1,13 @@
1#ifndef __ASM_X86_BITSPERLONG_H
2#define __ASM_X86_BITSPERLONG_H
3
4#ifdef __x86_64__
5# define __BITS_PER_LONG 64
6#else
7# define __BITS_PER_LONG 32
8#endif
9
10#include <asm-generic/bitsperlong.h>
11
12#endif /* __ASM_X86_BITSPERLONG_H */
13
diff --git a/arch/x86/include/uapi/asm/boot.h b/arch/x86/include/uapi/asm/boot.h
new file mode 100644
index 000000000000..94292c4c8122
--- /dev/null
+++ b/arch/x86/include/uapi/asm/boot.h
@@ -0,0 +1,10 @@
1#ifndef _UAPI_ASM_X86_BOOT_H
2#define _UAPI_ASM_X86_BOOT_H
3
4/* Internal svga startup constants */
5#define NORMAL_VGA 0xffff /* 80x25 mode */
6#define EXTENDED_VGA 0xfffe /* 80x50 mode */
7#define ASK_VGA 0xfffd /* ask for it at bootup */
8
9
10#endif /* _UAPI_ASM_X86_BOOT_H */
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
new file mode 100644
index 000000000000..92862cd90201
--- /dev/null
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -0,0 +1,139 @@
1#ifndef _ASM_X86_BOOTPARAM_H
2#define _ASM_X86_BOOTPARAM_H
3
4#include <linux/types.h>
5#include <linux/screen_info.h>
6#include <linux/apm_bios.h>
7#include <linux/edd.h>
8#include <asm/e820.h>
9#include <asm/ist.h>
10#include <video/edid.h>
11
12/* setup data types */
13#define SETUP_NONE 0
14#define SETUP_E820_EXT 1
15#define SETUP_DTB 2
16#define SETUP_PCI 3
17
18/* extensible setup data list node */
19struct setup_data {
20 __u64 next;
21 __u32 type;
22 __u32 len;
23 __u8 data[0];
24};
25
26struct setup_header {
27 __u8 setup_sects;
28 __u16 root_flags;
29 __u32 syssize;
30 __u16 ram_size;
31#define RAMDISK_IMAGE_START_MASK 0x07FF
32#define RAMDISK_PROMPT_FLAG 0x8000
33#define RAMDISK_LOAD_FLAG 0x4000
34 __u16 vid_mode;
35 __u16 root_dev;
36 __u16 boot_flag;
37 __u16 jump;
38 __u32 header;
39 __u16 version;
40 __u32 realmode_swtch;
41 __u16 start_sys;
42 __u16 kernel_version;
43 __u8 type_of_loader;
44 __u8 loadflags;
45#define LOADED_HIGH (1<<0)
46#define QUIET_FLAG (1<<5)
47#define KEEP_SEGMENTS (1<<6)
48#define CAN_USE_HEAP (1<<7)
49 __u16 setup_move_size;
50 __u32 code32_start;
51 __u32 ramdisk_image;
52 __u32 ramdisk_size;
53 __u32 bootsect_kludge;
54 __u16 heap_end_ptr;
55 __u8 ext_loader_ver;
56 __u8 ext_loader_type;
57 __u32 cmd_line_ptr;
58 __u32 initrd_addr_max;
59 __u32 kernel_alignment;
60 __u8 relocatable_kernel;
61 __u8 _pad2[3];
62 __u32 cmdline_size;
63 __u32 hardware_subarch;
64 __u64 hardware_subarch_data;
65 __u32 payload_offset;
66 __u32 payload_length;
67 __u64 setup_data;
68 __u64 pref_address;
69 __u32 init_size;
70 __u32 handover_offset;
71} __attribute__((packed));
72
73struct sys_desc_table {
74 __u16 length;
75 __u8 table[14];
76};
77
78/* Gleaned from OFW's set-parameters in cpu/x86/pc/linux.fth */
79struct olpc_ofw_header {
80 __u32 ofw_magic; /* OFW signature */
81 __u32 ofw_version;
82 __u32 cif_handler; /* callback into OFW */
83 __u32 irq_desc_table;
84} __attribute__((packed));
85
86struct efi_info {
87 __u32 efi_loader_signature;
88 __u32 efi_systab;
89 __u32 efi_memdesc_size;
90 __u32 efi_memdesc_version;
91 __u32 efi_memmap;
92 __u32 efi_memmap_size;
93 __u32 efi_systab_hi;
94 __u32 efi_memmap_hi;
95};
96
97/* The so-called "zeropage" */
98struct boot_params {
99 struct screen_info screen_info; /* 0x000 */
100 struct apm_bios_info apm_bios_info; /* 0x040 */
101 __u8 _pad2[4]; /* 0x054 */
102 __u64 tboot_addr; /* 0x058 */
103 struct ist_info ist_info; /* 0x060 */
104 __u8 _pad3[16]; /* 0x070 */
105 __u8 hd0_info[16]; /* obsolete! */ /* 0x080 */
106 __u8 hd1_info[16]; /* obsolete! */ /* 0x090 */
107 struct sys_desc_table sys_desc_table; /* 0x0a0 */
108 struct olpc_ofw_header olpc_ofw_header; /* 0x0b0 */
109 __u8 _pad4[128]; /* 0x0c0 */
110 struct edid_info edid_info; /* 0x140 */
111 struct efi_info efi_info; /* 0x1c0 */
112 __u32 alt_mem_k; /* 0x1e0 */
113 __u32 scratch; /* Scratch field! */ /* 0x1e4 */
114 __u8 e820_entries; /* 0x1e8 */
115 __u8 eddbuf_entries; /* 0x1e9 */
116 __u8 edd_mbr_sig_buf_entries; /* 0x1ea */
117 __u8 kbd_status; /* 0x1eb */
118 __u8 _pad6[5]; /* 0x1ec */
119 struct setup_header hdr; /* setup header */ /* 0x1f1 */
120 __u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)];
121 __u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */
122 struct e820entry e820_map[E820MAX]; /* 0x2d0 */
123 __u8 _pad8[48]; /* 0xcd0 */
124 struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */
125 __u8 _pad9[276]; /* 0xeec */
126} __attribute__((packed));
127
128enum {
129 X86_SUBARCH_PC = 0,
130 X86_SUBARCH_LGUEST,
131 X86_SUBARCH_XEN,
132 X86_SUBARCH_MRST,
133 X86_SUBARCH_CE4100,
134 X86_NR_SUBARCHS,
135};
136
137
138
139#endif /* _ASM_X86_BOOTPARAM_H */
diff --git a/arch/x86/include/uapi/asm/byteorder.h b/arch/x86/include/uapi/asm/byteorder.h
new file mode 100644
index 000000000000..b13a7a88f3eb
--- /dev/null
+++ b/arch/x86/include/uapi/asm/byteorder.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_X86_BYTEORDER_H
2#define _ASM_X86_BYTEORDER_H
3
4#include <linux/byteorder/little_endian.h>
5
6#endif /* _ASM_X86_BYTEORDER_H */
diff --git a/arch/x86/include/uapi/asm/debugreg.h b/arch/x86/include/uapi/asm/debugreg.h
new file mode 100644
index 000000000000..3c0874dd9861
--- /dev/null
+++ b/arch/x86/include/uapi/asm/debugreg.h
@@ -0,0 +1,80 @@
1#ifndef _UAPI_ASM_X86_DEBUGREG_H
2#define _UAPI_ASM_X86_DEBUGREG_H
3
4
5/* Indicate the register numbers for a number of the specific
6 debug registers. Registers 0-3 contain the addresses we wish to trap on */
7#define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
8#define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
9
10#define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
11#define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
12
13/* Define a few things for the status register. We can use this to determine
14 which debugging register was responsible for the trap. The other bits
15 are either reserved or not of interest to us. */
16
17/* Define reserved bits in DR6 which are always set to 1 */
18#define DR6_RESERVED (0xFFFF0FF0)
19
20#define DR_TRAP0 (0x1) /* db0 */
21#define DR_TRAP1 (0x2) /* db1 */
22#define DR_TRAP2 (0x4) /* db2 */
23#define DR_TRAP3 (0x8) /* db3 */
24#define DR_TRAP_BITS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)
25
26#define DR_STEP (0x4000) /* single-step */
27#define DR_SWITCH (0x8000) /* task switch */
28
29/* Now define a bunch of things for manipulating the control register.
30 The top two bytes of the control register consist of 4 fields of 4
31 bits - each field corresponds to one of the four debug registers,
32 and indicates what types of access we trap on, and how large the data
33 field is that we are looking at */
34
35#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
36#define DR_CONTROL_SIZE 4 /* 4 control bits per register */
37
38#define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
39#define DR_RW_WRITE (0x1)
40#define DR_RW_READ (0x3)
41
42#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
43#define DR_LEN_2 (0x4)
44#define DR_LEN_4 (0xC)
45#define DR_LEN_8 (0x8)
46
47/* The low byte to the control register determine which registers are
48 enabled. There are 4 fields of two bits. One bit is "local", meaning
49 that the processor will reset the bit after a task switch and the other
50 is global meaning that we have to explicitly reset the bit. With linux,
51 you can use either one, since we explicitly zero the register when we enter
52 kernel mode. */
53
54#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
55#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
56#define DR_LOCAL_ENABLE (0x1) /* Local enable for reg 0 */
57#define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
58#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
59
60#define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
61#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
62
63/* The second byte to the control register has a few special things.
64 We can slow the instruction pipeline for instructions coming via the
65 gdt or the ldt if we want to. I am not sure why this is an advantage */
66
67#ifdef __i386__
68#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
69#else
70#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
71#endif
72
73#define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
74#define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
75
76/*
77 * HW breakpoint additions
78 */
79
80#endif /* _UAPI_ASM_X86_DEBUGREG_H */
diff --git a/arch/x86/include/uapi/asm/e820.h b/arch/x86/include/uapi/asm/e820.h
new file mode 100644
index 000000000000..bbae02470701
--- /dev/null
+++ b/arch/x86/include/uapi/asm/e820.h
@@ -0,0 +1,75 @@
1#ifndef _UAPI_ASM_X86_E820_H
2#define _UAPI_ASM_X86_E820_H
3#define E820MAP 0x2d0 /* our map */
4#define E820MAX 128 /* number of entries in E820MAP */
5
6/*
7 * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
8 * constrained space in the zeropage. If we have more nodes than
9 * that, and if we've booted off EFI firmware, then the EFI tables
10 * passed us from the EFI firmware can list more nodes. Size our
11 * internal memory map tables to have room for these additional
12 * nodes, based on up to three entries per node for which the
13 * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
14 * plus E820MAX, allowing space for the possible duplicate E820
15 * entries that might need room in the same arrays, prior to the
16 * call to sanitize_e820_map() to remove duplicates. The allowance
17 * of three memory map entries per node is "enough" entries for
18 * the initial hardware platform motivating this mechanism to make
19 * use of additional EFI map entries. Future platforms may want
20 * to allow more than three entries per node or otherwise refine
21 * this size.
22 */
23
24/*
25 * Odd: 'make headers_check' complains about numa.h if I try
26 * to collapse the next two #ifdef lines to a single line:
27 * #if defined(__KERNEL__) && defined(CONFIG_EFI)
28 */
29#ifndef __KERNEL__
30#define E820_X_MAX E820MAX
31#endif
32
33#define E820NR 0x1e8 /* # entries in E820MAP */
34
35#define E820_RAM 1
36#define E820_RESERVED 2
37#define E820_ACPI 3
38#define E820_NVS 4
39#define E820_UNUSABLE 5
40
41
42/*
43 * reserved RAM used by kernel itself
44 * if CONFIG_INTEL_TXT is enabled, memory of this type will be
45 * included in the S3 integrity calculation and so should not include
46 * any memory that BIOS might alter over the S3 transition
47 */
48#define E820_RESERVED_KERN 128
49
50#ifndef __ASSEMBLY__
51#include <linux/types.h>
52struct e820entry {
53 __u64 addr; /* start of memory segment */
54 __u64 size; /* size of memory segment */
55 __u32 type; /* type of memory segment */
56} __attribute__((packed));
57
58struct e820map {
59 __u32 nr_map;
60 struct e820entry map[E820_X_MAX];
61};
62
63#define ISA_START_ADDRESS 0xa0000
64#define ISA_END_ADDRESS 0x100000
65
66#define BIOS_BEGIN 0x000a0000
67#define BIOS_END 0x00100000
68
69#define BIOS_ROM_BASE 0xffe00000
70#define BIOS_ROM_END 0xffffffff
71
72#endif /* __ASSEMBLY__ */
73
74
75#endif /* _UAPI_ASM_X86_E820_H */
diff --git a/arch/x86/include/uapi/asm/errno.h b/arch/x86/include/uapi/asm/errno.h
new file mode 100644
index 000000000000..4c82b503d92f
--- /dev/null
+++ b/arch/x86/include/uapi/asm/errno.h
@@ -0,0 +1 @@
#include <asm-generic/errno.h>
diff --git a/arch/x86/include/uapi/asm/fcntl.h b/arch/x86/include/uapi/asm/fcntl.h
new file mode 100644
index 000000000000..46ab12db5739
--- /dev/null
+++ b/arch/x86/include/uapi/asm/fcntl.h
@@ -0,0 +1 @@
#include <asm-generic/fcntl.h>
diff --git a/arch/x86/include/uapi/asm/hw_breakpoint.h b/arch/x86/include/uapi/asm/hw_breakpoint.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/x86/include/uapi/asm/hw_breakpoint.h
diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h
new file mode 100644
index 000000000000..b80420bcd09d
--- /dev/null
+++ b/arch/x86/include/uapi/asm/hyperv.h
@@ -0,0 +1,194 @@
1#ifndef _ASM_X86_HYPERV_H
2#define _ASM_X86_HYPERV_H
3
4#include <linux/types.h>
5
6/*
7 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
8 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
9 */
10#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
11#define HYPERV_CPUID_INTERFACE 0x40000001
12#define HYPERV_CPUID_VERSION 0x40000002
13#define HYPERV_CPUID_FEATURES 0x40000003
14#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
15#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
16
17#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
18#define HYPERV_CPUID_MIN 0x40000005
19#define HYPERV_CPUID_MAX 0x4000ffff
20
21/*
22 * Feature identification. EAX indicates which features are available
23 * to the partition based upon the current partition privileges.
24 */
25
26/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
27#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
28/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
29#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
30/*
31 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
32 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
33 */
34#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
35/*
36 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
37 * HV_X64_MSR_STIMER3_COUNT) available
38 */
39#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3)
40/*
41 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
42 * are available
43 */
44#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
45/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
46#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
47/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
48#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
49/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
50#define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
51 /*
52 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
53 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
54 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
55 */
56#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
57
58/*
59 * Feature identification: EBX indicates which flags were specified at
60 * partition creation. The format is the same as the partition creation
61 * flag structure defined in section Partition Creation Flags.
62 */
63#define HV_X64_CREATE_PARTITIONS (1 << 0)
64#define HV_X64_ACCESS_PARTITION_ID (1 << 1)
65#define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
66#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
67#define HV_X64_POST_MESSAGES (1 << 4)
68#define HV_X64_SIGNAL_EVENTS (1 << 5)
69#define HV_X64_CREATE_PORT (1 << 6)
70#define HV_X64_CONNECT_PORT (1 << 7)
71#define HV_X64_ACCESS_STATS (1 << 8)
72#define HV_X64_DEBUGGING (1 << 11)
73#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
74#define HV_X64_CONFIGURE_PROFILER (1 << 13)
75
76/*
77 * Feature identification. EDX indicates which miscellaneous features
78 * are available to the partition.
79 */
80/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
81#define HV_X64_MWAIT_AVAILABLE (1 << 0)
82/* Guest debugging support is available */
83#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
84/* Performance Monitor support is available*/
85#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
86/* Support for physical CPU dynamic partitioning events is available*/
87#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
88/*
89 * Support for passing hypercall input parameter block via XMM
90 * registers is available
91 */
92#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
93/* Support for a virtual guest idle state is available */
94#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
95
96/*
97 * Implementation recommendations. Indicates which behaviors the hypervisor
98 * recommends the OS implement for optimal performance.
99 */
100 /*
101 * Recommend using hypercall for address space switches rather
102 * than MOV to CR3 instruction
103 */
104#define HV_X64_MWAIT_RECOMMENDED (1 << 0)
105/* Recommend using hypercall for local TLB flushes rather
106 * than INVLPG or MOV to CR3 instructions */
107#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
108/*
109 * Recommend using hypercall for remote TLB flushes rather
110 * than inter-processor interrupts
111 */
112#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
113/*
114 * Recommend using MSRs for accessing APIC registers
115 * EOI, ICR and TPR rather than their memory-mapped counterparts
116 */
117#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
118/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
119#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
120/*
121 * Recommend using relaxed timing for this partition. If used,
122 * the VM should disable any watchdog timeouts that rely on the
123 * timely delivery of external interrupts
124 */
125#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
126
127/* MSR used to identify the guest OS. */
128#define HV_X64_MSR_GUEST_OS_ID 0x40000000
129
130/* MSR used to setup pages used to communicate with the hypervisor. */
131#define HV_X64_MSR_HYPERCALL 0x40000001
132
133/* MSR used to provide vcpu index */
134#define HV_X64_MSR_VP_INDEX 0x40000002
135
136/* MSR used to read the per-partition time reference counter */
137#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
138
139/* Define the virtual APIC registers */
140#define HV_X64_MSR_EOI 0x40000070
141#define HV_X64_MSR_ICR 0x40000071
142#define HV_X64_MSR_TPR 0x40000072
143#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
144
145/* Define synthetic interrupt controller model specific registers. */
146#define HV_X64_MSR_SCONTROL 0x40000080
147#define HV_X64_MSR_SVERSION 0x40000081
148#define HV_X64_MSR_SIEFP 0x40000082
149#define HV_X64_MSR_SIMP 0x40000083
150#define HV_X64_MSR_EOM 0x40000084
151#define HV_X64_MSR_SINT0 0x40000090
152#define HV_X64_MSR_SINT1 0x40000091
153#define HV_X64_MSR_SINT2 0x40000092
154#define HV_X64_MSR_SINT3 0x40000093
155#define HV_X64_MSR_SINT4 0x40000094
156#define HV_X64_MSR_SINT5 0x40000095
157#define HV_X64_MSR_SINT6 0x40000096
158#define HV_X64_MSR_SINT7 0x40000097
159#define HV_X64_MSR_SINT8 0x40000098
160#define HV_X64_MSR_SINT9 0x40000099
161#define HV_X64_MSR_SINT10 0x4000009A
162#define HV_X64_MSR_SINT11 0x4000009B
163#define HV_X64_MSR_SINT12 0x4000009C
164#define HV_X64_MSR_SINT13 0x4000009D
165#define HV_X64_MSR_SINT14 0x4000009E
166#define HV_X64_MSR_SINT15 0x4000009F
167
168
169#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
170#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
171#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
172 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
173
174/* Declare the various hypercall operations. */
175#define HV_X64_HV_NOTIFY_LONG_SPIN_WAIT 0x0008
176
177#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001
178#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12
179#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
180 (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
181
182#define HV_PROCESSOR_POWER_STATE_C0 0
183#define HV_PROCESSOR_POWER_STATE_C1 1
184#define HV_PROCESSOR_POWER_STATE_C2 2
185#define HV_PROCESSOR_POWER_STATE_C3 3
186
187/* hypercall status code */
188#define HV_STATUS_SUCCESS 0
189#define HV_STATUS_INVALID_HYPERCALL_CODE 2
190#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
191#define HV_STATUS_INVALID_ALIGNMENT 4
192#define HV_STATUS_INSUFFICIENT_BUFFERS 19
193
194#endif
diff --git a/arch/x86/include/uapi/asm/ioctl.h b/arch/x86/include/uapi/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ioctl.h
@@ -0,0 +1 @@
#include <asm-generic/ioctl.h>
diff --git a/arch/x86/include/uapi/asm/ioctls.h b/arch/x86/include/uapi/asm/ioctls.h
new file mode 100644
index 000000000000..ec34c760665e
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ioctls.h
@@ -0,0 +1 @@
#include <asm-generic/ioctls.h>
diff --git a/arch/x86/include/uapi/asm/ipcbuf.h b/arch/x86/include/uapi/asm/ipcbuf.h
new file mode 100644
index 000000000000..84c7e51cb6d0
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ipcbuf.h
@@ -0,0 +1 @@
#include <asm-generic/ipcbuf.h>
diff --git a/arch/x86/include/uapi/asm/ist.h b/arch/x86/include/uapi/asm/ist.h
new file mode 100644
index 000000000000..bad9f5ea4070
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ist.h
@@ -0,0 +1,29 @@
1/*
2 * Include file for the interface to IST BIOS
3 * Copyright 2002 Andy Grover <andrew.grover@intel.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 */
15#ifndef _UAPI_ASM_X86_IST_H
16#define _UAPI_ASM_X86_IST_H
17
18
19
20#include <linux/types.h>
21
22struct ist_info {
23 __u32 signature;
24 __u32 command;
25 __u32 event;
26 __u32 perf_level;
27};
28
29#endif /* _UAPI_ASM_X86_IST_H */
diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h
new file mode 100644
index 000000000000..a65ec29e6ffb
--- /dev/null
+++ b/arch/x86/include/uapi/asm/kvm.h
@@ -0,0 +1,346 @@
1#ifndef _ASM_X86_KVM_H
2#define _ASM_X86_KVM_H
3
4/*
5 * KVM x86 specific structures and definitions
6 *
7 */
8
9#include <linux/types.h>
10#include <linux/ioctl.h>
11
12#define DE_VECTOR 0
13#define DB_VECTOR 1
14#define BP_VECTOR 3
15#define OF_VECTOR 4
16#define BR_VECTOR 5
17#define UD_VECTOR 6
18#define NM_VECTOR 7
19#define DF_VECTOR 8
20#define TS_VECTOR 10
21#define NP_VECTOR 11
22#define SS_VECTOR 12
23#define GP_VECTOR 13
24#define PF_VECTOR 14
25#define MF_VECTOR 16
26#define MC_VECTOR 18
27
28/* Select x86 specific features in <linux/kvm.h> */
29#define __KVM_HAVE_PIT
30#define __KVM_HAVE_IOAPIC
31#define __KVM_HAVE_IRQ_LINE
32#define __KVM_HAVE_DEVICE_ASSIGNMENT
33#define __KVM_HAVE_MSI
34#define __KVM_HAVE_USER_NMI
35#define __KVM_HAVE_GUEST_DEBUG
36#define __KVM_HAVE_MSIX
37#define __KVM_HAVE_MCE
38#define __KVM_HAVE_PIT_STATE2
39#define __KVM_HAVE_XEN_HVM
40#define __KVM_HAVE_VCPU_EVENTS
41#define __KVM_HAVE_DEBUGREGS
42#define __KVM_HAVE_XSAVE
43#define __KVM_HAVE_XCRS
44#define __KVM_HAVE_READONLY_MEM
45
46/* Architectural interrupt line count. */
47#define KVM_NR_INTERRUPTS 256
48
49struct kvm_memory_alias {
50 __u32 slot; /* this has a different namespace than memory slots */
51 __u32 flags;
52 __u64 guest_phys_addr;
53 __u64 memory_size;
54 __u64 target_phys_addr;
55};
56
57/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
58struct kvm_pic_state {
59 __u8 last_irr; /* edge detection */
60 __u8 irr; /* interrupt request register */
61 __u8 imr; /* interrupt mask register */
62 __u8 isr; /* interrupt service register */
63 __u8 priority_add; /* highest irq priority */
64 __u8 irq_base;
65 __u8 read_reg_select;
66 __u8 poll;
67 __u8 special_mask;
68 __u8 init_state;
69 __u8 auto_eoi;
70 __u8 rotate_on_auto_eoi;
71 __u8 special_fully_nested_mode;
72 __u8 init4; /* true if 4 byte init */
73 __u8 elcr; /* PIIX edge/trigger selection */
74 __u8 elcr_mask;
75};
76
77#define KVM_IOAPIC_NUM_PINS 24
78struct kvm_ioapic_state {
79 __u64 base_address;
80 __u32 ioregsel;
81 __u32 id;
82 __u32 irr;
83 __u32 pad;
84 union {
85 __u64 bits;
86 struct {
87 __u8 vector;
88 __u8 delivery_mode:3;
89 __u8 dest_mode:1;
90 __u8 delivery_status:1;
91 __u8 polarity:1;
92 __u8 remote_irr:1;
93 __u8 trig_mode:1;
94 __u8 mask:1;
95 __u8 reserve:7;
96 __u8 reserved[4];
97 __u8 dest_id;
98 } fields;
99 } redirtbl[KVM_IOAPIC_NUM_PINS];
100};
101
102#define KVM_IRQCHIP_PIC_MASTER 0
103#define KVM_IRQCHIP_PIC_SLAVE 1
104#define KVM_IRQCHIP_IOAPIC 2
105#define KVM_NR_IRQCHIPS 3
106
107/* for KVM_GET_REGS and KVM_SET_REGS */
108struct kvm_regs {
109 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
110 __u64 rax, rbx, rcx, rdx;
111 __u64 rsi, rdi, rsp, rbp;
112 __u64 r8, r9, r10, r11;
113 __u64 r12, r13, r14, r15;
114 __u64 rip, rflags;
115};
116
117/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
118#define KVM_APIC_REG_SIZE 0x400
119struct kvm_lapic_state {
120 char regs[KVM_APIC_REG_SIZE];
121};
122
123struct kvm_segment {
124 __u64 base;
125 __u32 limit;
126 __u16 selector;
127 __u8 type;
128 __u8 present, dpl, db, s, l, g, avl;
129 __u8 unusable;
130 __u8 padding;
131};
132
133struct kvm_dtable {
134 __u64 base;
135 __u16 limit;
136 __u16 padding[3];
137};
138
139
140/* for KVM_GET_SREGS and KVM_SET_SREGS */
141struct kvm_sregs {
142 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
143 struct kvm_segment cs, ds, es, fs, gs, ss;
144 struct kvm_segment tr, ldt;
145 struct kvm_dtable gdt, idt;
146 __u64 cr0, cr2, cr3, cr4, cr8;
147 __u64 efer;
148 __u64 apic_base;
149 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
150};
151
152/* for KVM_GET_FPU and KVM_SET_FPU */
153struct kvm_fpu {
154 __u8 fpr[8][16];
155 __u16 fcw;
156 __u16 fsw;
157 __u8 ftwx; /* in fxsave format */
158 __u8 pad1;
159 __u16 last_opcode;
160 __u64 last_ip;
161 __u64 last_dp;
162 __u8 xmm[16][16];
163 __u32 mxcsr;
164 __u32 pad2;
165};
166
167struct kvm_msr_entry {
168 __u32 index;
169 __u32 reserved;
170 __u64 data;
171};
172
173/* for KVM_GET_MSRS and KVM_SET_MSRS */
174struct kvm_msrs {
175 __u32 nmsrs; /* number of msrs in entries */
176 __u32 pad;
177
178 struct kvm_msr_entry entries[0];
179};
180
181/* for KVM_GET_MSR_INDEX_LIST */
182struct kvm_msr_list {
183 __u32 nmsrs; /* number of msrs in entries */
184 __u32 indices[0];
185};
186
187
188struct kvm_cpuid_entry {
189 __u32 function;
190 __u32 eax;
191 __u32 ebx;
192 __u32 ecx;
193 __u32 edx;
194 __u32 padding;
195};
196
197/* for KVM_SET_CPUID */
198struct kvm_cpuid {
199 __u32 nent;
200 __u32 padding;
201 struct kvm_cpuid_entry entries[0];
202};
203
204struct kvm_cpuid_entry2 {
205 __u32 function;
206 __u32 index;
207 __u32 flags;
208 __u32 eax;
209 __u32 ebx;
210 __u32 ecx;
211 __u32 edx;
212 __u32 padding[3];
213};
214
215#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
216#define KVM_CPUID_FLAG_STATEFUL_FUNC 2
217#define KVM_CPUID_FLAG_STATE_READ_NEXT 4
218
219/* for KVM_SET_CPUID2 */
220struct kvm_cpuid2 {
221 __u32 nent;
222 __u32 padding;
223 struct kvm_cpuid_entry2 entries[0];
224};
225
226/* for KVM_GET_PIT and KVM_SET_PIT */
227struct kvm_pit_channel_state {
228 __u32 count; /* can be 65536 */
229 __u16 latched_count;
230 __u8 count_latched;
231 __u8 status_latched;
232 __u8 status;
233 __u8 read_state;
234 __u8 write_state;
235 __u8 write_latch;
236 __u8 rw_mode;
237 __u8 mode;
238 __u8 bcd;
239 __u8 gate;
240 __s64 count_load_time;
241};
242
243struct kvm_debug_exit_arch {
244 __u32 exception;
245 __u32 pad;
246 __u64 pc;
247 __u64 dr6;
248 __u64 dr7;
249};
250
251#define KVM_GUESTDBG_USE_SW_BP 0x00010000
252#define KVM_GUESTDBG_USE_HW_BP 0x00020000
253#define KVM_GUESTDBG_INJECT_DB 0x00040000
254#define KVM_GUESTDBG_INJECT_BP 0x00080000
255
256/* for KVM_SET_GUEST_DEBUG */
257struct kvm_guest_debug_arch {
258 __u64 debugreg[8];
259};
260
261struct kvm_pit_state {
262 struct kvm_pit_channel_state channels[3];
263};
264
265#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
266
267struct kvm_pit_state2 {
268 struct kvm_pit_channel_state channels[3];
269 __u32 flags;
270 __u32 reserved[9];
271};
272
273struct kvm_reinject_control {
274 __u8 pit_reinject;
275 __u8 reserved[31];
276};
277
278/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
279#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
280#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
281#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
282
283/* Interrupt shadow states */
284#define KVM_X86_SHADOW_INT_MOV_SS 0x01
285#define KVM_X86_SHADOW_INT_STI 0x02
286
287/* for KVM_GET/SET_VCPU_EVENTS */
288struct kvm_vcpu_events {
289 struct {
290 __u8 injected;
291 __u8 nr;
292 __u8 has_error_code;
293 __u8 pad;
294 __u32 error_code;
295 } exception;
296 struct {
297 __u8 injected;
298 __u8 nr;
299 __u8 soft;
300 __u8 shadow;
301 } interrupt;
302 struct {
303 __u8 injected;
304 __u8 pending;
305 __u8 masked;
306 __u8 pad;
307 } nmi;
308 __u32 sipi_vector;
309 __u32 flags;
310 __u32 reserved[10];
311};
312
313/* for KVM_GET/SET_DEBUGREGS */
314struct kvm_debugregs {
315 __u64 db[4];
316 __u64 dr6;
317 __u64 dr7;
318 __u64 flags;
319 __u64 reserved[9];
320};
321
322/* for KVM_CAP_XSAVE */
323struct kvm_xsave {
324 __u32 region[1024];
325};
326
327#define KVM_MAX_XCRS 16
328
329struct kvm_xcr {
330 __u32 xcr;
331 __u32 reserved;
332 __u64 value;
333};
334
335struct kvm_xcrs {
336 __u32 nr_xcrs;
337 __u32 flags;
338 struct kvm_xcr xcrs[KVM_MAX_XCRS];
339 __u64 padding[16];
340};
341
342/* definition of registers in kvm_run */
343struct kvm_sync_regs {
344};
345
346#endif /* _ASM_X86_KVM_H */
diff --git a/arch/x86/include/uapi/asm/kvm_para.h b/arch/x86/include/uapi/asm/kvm_para.h
new file mode 100644
index 000000000000..06fdbd987e97
--- /dev/null
+++ b/arch/x86/include/uapi/asm/kvm_para.h
@@ -0,0 +1,100 @@
1#ifndef _UAPI_ASM_X86_KVM_PARA_H
2#define _UAPI_ASM_X86_KVM_PARA_H
3
4#include <linux/types.h>
5#include <asm/hyperv.h>
6
7/* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx. It
8 * should be used to determine that a VM is running under KVM.
9 */
10#define KVM_CPUID_SIGNATURE 0x40000000
11
12/* This CPUID returns a feature bitmap in eax. Before enabling a particular
13 * paravirtualization, the appropriate feature bit should be checked.
14 */
15#define KVM_CPUID_FEATURES 0x40000001
16#define KVM_FEATURE_CLOCKSOURCE 0
17#define KVM_FEATURE_NOP_IO_DELAY 1
18#define KVM_FEATURE_MMU_OP 2
19/* This indicates that the new set of kvmclock msrs
20 * are available. The use of 0x11 and 0x12 is deprecated
21 */
22#define KVM_FEATURE_CLOCKSOURCE2 3
23#define KVM_FEATURE_ASYNC_PF 4
24#define KVM_FEATURE_STEAL_TIME 5
25#define KVM_FEATURE_PV_EOI 6
26
27/* The last 8 bits are used to indicate how to interpret the flags field
28 * in pvclock structure. If no bits are set, all flags are ignored.
29 */
30#define KVM_FEATURE_CLOCKSOURCE_STABLE_BIT 24
31
32#define MSR_KVM_WALL_CLOCK 0x11
33#define MSR_KVM_SYSTEM_TIME 0x12
34
35#define KVM_MSR_ENABLED 1
36/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */
37#define MSR_KVM_WALL_CLOCK_NEW 0x4b564d00
38#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01
39#define MSR_KVM_ASYNC_PF_EN 0x4b564d02
40#define MSR_KVM_STEAL_TIME 0x4b564d03
41#define MSR_KVM_PV_EOI_EN 0x4b564d04
42
43struct kvm_steal_time {
44 __u64 steal;
45 __u32 version;
46 __u32 flags;
47 __u32 pad[12];
48};
49
50#define KVM_STEAL_ALIGNMENT_BITS 5
51#define KVM_STEAL_VALID_BITS ((-1ULL << (KVM_STEAL_ALIGNMENT_BITS + 1)))
52#define KVM_STEAL_RESERVED_MASK (((1 << KVM_STEAL_ALIGNMENT_BITS) - 1 ) << 1)
53
54#define KVM_MAX_MMU_OP_BATCH 32
55
56#define KVM_ASYNC_PF_ENABLED (1 << 0)
57#define KVM_ASYNC_PF_SEND_ALWAYS (1 << 1)
58
59/* Operations for KVM_HC_MMU_OP */
60#define KVM_MMU_OP_WRITE_PTE 1
61#define KVM_MMU_OP_FLUSH_TLB 2
62#define KVM_MMU_OP_RELEASE_PT 3
63
64/* Payload for KVM_HC_MMU_OP */
65struct kvm_mmu_op_header {
66 __u32 op;
67 __u32 pad;
68};
69
70struct kvm_mmu_op_write_pte {
71 struct kvm_mmu_op_header header;
72 __u64 pte_phys;
73 __u64 pte_val;
74};
75
76struct kvm_mmu_op_flush_tlb {
77 struct kvm_mmu_op_header header;
78};
79
80struct kvm_mmu_op_release_pt {
81 struct kvm_mmu_op_header header;
82 __u64 pt_phys;
83};
84
85#define KVM_PV_REASON_PAGE_NOT_PRESENT 1
86#define KVM_PV_REASON_PAGE_READY 2
87
88struct kvm_vcpu_pv_apf_data {
89 __u32 reason;
90 __u8 pad[60];
91 __u32 enabled;
92};
93
94#define KVM_PV_EOI_BIT 0
95#define KVM_PV_EOI_MASK (0x1 << KVM_PV_EOI_BIT)
96#define KVM_PV_EOI_ENABLED KVM_PV_EOI_MASK
97#define KVM_PV_EOI_DISABLED 0x0
98
99
100#endif /* _UAPI_ASM_X86_KVM_PARA_H */
diff --git a/arch/x86/include/uapi/asm/ldt.h b/arch/x86/include/uapi/asm/ldt.h
new file mode 100644
index 000000000000..46727eb37bfe
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ldt.h
@@ -0,0 +1,40 @@
1/*
2 * ldt.h
3 *
4 * Definitions of structures used with the modify_ldt system call.
5 */
6#ifndef _ASM_X86_LDT_H
7#define _ASM_X86_LDT_H
8
9/* Maximum number of LDT entries supported. */
10#define LDT_ENTRIES 8192
11/* The size of each LDT entry. */
12#define LDT_ENTRY_SIZE 8
13
14#ifndef __ASSEMBLY__
15/*
16 * Note on 64bit base and limit is ignored and you cannot set DS/ES/CS
17 * not to the default values if you still want to do syscalls. This
18 * call is more for 32bit mode therefore.
19 */
20struct user_desc {
21 unsigned int entry_number;
22 unsigned int base_addr;
23 unsigned int limit;
24 unsigned int seg_32bit:1;
25 unsigned int contents:2;
26 unsigned int read_exec_only:1;
27 unsigned int limit_in_pages:1;
28 unsigned int seg_not_present:1;
29 unsigned int useable:1;
30#ifdef __x86_64__
31 unsigned int lm:1;
32#endif
33};
34
35#define MODIFY_LDT_CONTENTS_DATA 0
36#define MODIFY_LDT_CONTENTS_STACK 1
37#define MODIFY_LDT_CONTENTS_CODE 2
38
39#endif /* !__ASSEMBLY__ */
40#endif /* _ASM_X86_LDT_H */
diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mce.h
new file mode 100644
index 000000000000..58c829871c31
--- /dev/null
+++ b/arch/x86/include/uapi/asm/mce.h
@@ -0,0 +1,121 @@
1#ifndef _UAPI_ASM_X86_MCE_H
2#define _UAPI_ASM_X86_MCE_H
3
4#include <linux/types.h>
5#include <asm/ioctls.h>
6
7/*
8 * Machine Check support for x86
9 */
10
11/* MCG_CAP register defines */
12#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
13#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
14#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
15#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
16#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
17#define MCG_EXT_CNT_SHIFT 16
18#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
19#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
20
21/* MCG_STATUS register defines */
22#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
23#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
24#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
25
26/* MCi_STATUS register defines */
27#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
28#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
29#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
30#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
31#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
32#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
33#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
34#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
35#define MCI_STATUS_AR (1ULL<<55) /* Action required */
36#define MCACOD 0xffff /* MCA Error Code */
37
38/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
39#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
40#define MCACOD_SCRUBMSK 0xfff0
41#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
42#define MCACOD_DATA 0x0134 /* Data Load */
43#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
44
45/* MCi_MISC register defines */
46#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
47#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
48#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
49#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
50#define MCI_MISC_ADDR_PHYS 2 /* physical address */
51#define MCI_MISC_ADDR_MEM 3 /* memory address */
52#define MCI_MISC_ADDR_GENERIC 7 /* generic */
53
54/* CTL2 register defines */
55#define MCI_CTL2_CMCI_EN (1ULL << 30)
56#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
57
58#define MCJ_CTX_MASK 3
59#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
60#define MCJ_CTX_RANDOM 0 /* inject context: random */
61#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
62#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
63#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
64#define MCJ_EXCEPTION 0x8 /* raise as exception */
65#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
66
67/* Fields are zero when not available */
68struct mce {
69 __u64 status;
70 __u64 misc;
71 __u64 addr;
72 __u64 mcgstatus;
73 __u64 ip;
74 __u64 tsc; /* cpu time stamp counter */
75 __u64 time; /* wall time_t when error was detected */
76 __u8 cpuvendor; /* cpu vendor as encoded in system.h */
77 __u8 inject_flags; /* software inject flags */
78 __u16 pad;
79 __u32 cpuid; /* CPUID 1 EAX */
80 __u8 cs; /* code segment */
81 __u8 bank; /* machine check bank */
82 __u8 cpu; /* cpu number; obsolete; use extcpu now */
83 __u8 finished; /* entry is valid */
84 __u32 extcpu; /* linux cpu number that detected the error */
85 __u32 socketid; /* CPU socket ID */
86 __u32 apicid; /* CPU initial apic ID */
87 __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
88};
89
90/*
91 * This structure contains all data related to the MCE log. Also
92 * carries a signature to make it easier to find from external
93 * debugging tools. Each entry is only valid when its finished flag
94 * is set.
95 */
96
97#define MCE_LOG_LEN 32
98
99struct mce_log {
100 char signature[12]; /* "MACHINECHECK" */
101 unsigned len; /* = MCE_LOG_LEN */
102 unsigned next;
103 unsigned flags;
104 unsigned recordlen; /* length of struct mce */
105 struct mce entry[MCE_LOG_LEN];
106};
107
108#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
109
110#define MCE_LOG_SIGNATURE "MACHINECHECK"
111
112#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
113#define MCE_GET_LOG_LEN _IOR('M', 2, int)
114#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
115
116/* Software defined banks */
117#define MCE_EXTENDED_BANK 128
118#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
119#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
120
121#endif /* _UAPI_ASM_X86_MCE_H */
diff --git a/arch/x86/include/uapi/asm/mman.h b/arch/x86/include/uapi/asm/mman.h
new file mode 100644
index 000000000000..513b05f15bb4
--- /dev/null
+++ b/arch/x86/include/uapi/asm/mman.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_X86_MMAN_H
2#define _ASM_X86_MMAN_H
3
4#define MAP_32BIT 0x40 /* only give out 32bit addresses */
5
6#define MAP_HUGE_2MB (21 << MAP_HUGE_SHIFT)
7#define MAP_HUGE_1GB (30 << MAP_HUGE_SHIFT)
8
9#include <asm-generic/mman.h>
10
11#endif /* _ASM_X86_MMAN_H */
diff --git a/arch/x86/include/uapi/asm/msgbuf.h b/arch/x86/include/uapi/asm/msgbuf.h
new file mode 100644
index 000000000000..809134c644a6
--- /dev/null
+++ b/arch/x86/include/uapi/asm/msgbuf.h
@@ -0,0 +1 @@
#include <asm-generic/msgbuf.h>
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
new file mode 100644
index 000000000000..6e930b218724
--- /dev/null
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -0,0 +1,488 @@
1#ifndef _ASM_X86_MSR_INDEX_H
2#define _ASM_X86_MSR_INDEX_H
3
4/* CPU model specific register (MSR) numbers */
5
6/* x86-64 specific MSRs */
7#define MSR_EFER 0xc0000080 /* extended feature register */
8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
16
17/* EFER bits: */
18#define _EFER_SCE 0 /* SYSCALL/SYSRET */
19#define _EFER_LME 8 /* Long mode enable */
20#define _EFER_LMA 10 /* Long mode active (read-only) */
21#define _EFER_NX 11 /* No execute enable */
22#define _EFER_SVME 12 /* Enable virtualization */
23#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
24#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
25
26#define EFER_SCE (1<<_EFER_SCE)
27#define EFER_LME (1<<_EFER_LME)
28#define EFER_LMA (1<<_EFER_LMA)
29#define EFER_NX (1<<_EFER_NX)
30#define EFER_SVME (1<<_EFER_SVME)
31#define EFER_LMSLE (1<<_EFER_LMSLE)
32#define EFER_FFXSR (1<<_EFER_FFXSR)
33
34/* Intel MSRs. Some also available on other CPUs */
35#define MSR_IA32_PERFCTR0 0x000000c1
36#define MSR_IA32_PERFCTR1 0x000000c2
37#define MSR_FSB_FREQ 0x000000cd
38
39#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
40#define NHM_C3_AUTO_DEMOTE (1UL << 25)
41#define NHM_C1_AUTO_DEMOTE (1UL << 26)
42#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
43
44#define MSR_MTRRcap 0x000000fe
45#define MSR_IA32_BBL_CR_CTL 0x00000119
46#define MSR_IA32_BBL_CR_CTL3 0x0000011e
47
48#define MSR_IA32_SYSENTER_CS 0x00000174
49#define MSR_IA32_SYSENTER_ESP 0x00000175
50#define MSR_IA32_SYSENTER_EIP 0x00000176
51
52#define MSR_IA32_MCG_CAP 0x00000179
53#define MSR_IA32_MCG_STATUS 0x0000017a
54#define MSR_IA32_MCG_CTL 0x0000017b
55
56#define MSR_OFFCORE_RSP_0 0x000001a6
57#define MSR_OFFCORE_RSP_1 0x000001a7
58
59#define MSR_LBR_SELECT 0x000001c8
60#define MSR_LBR_TOS 0x000001c9
61#define MSR_LBR_NHM_FROM 0x00000680
62#define MSR_LBR_NHM_TO 0x000006c0
63#define MSR_LBR_CORE_FROM 0x00000040
64#define MSR_LBR_CORE_TO 0x00000060
65
66#define MSR_IA32_PEBS_ENABLE 0x000003f1
67#define MSR_IA32_DS_AREA 0x00000600
68#define MSR_IA32_PERF_CAPABILITIES 0x00000345
69
70#define MSR_MTRRfix64K_00000 0x00000250
71#define MSR_MTRRfix16K_80000 0x00000258
72#define MSR_MTRRfix16K_A0000 0x00000259
73#define MSR_MTRRfix4K_C0000 0x00000268
74#define MSR_MTRRfix4K_C8000 0x00000269
75#define MSR_MTRRfix4K_D0000 0x0000026a
76#define MSR_MTRRfix4K_D8000 0x0000026b
77#define MSR_MTRRfix4K_E0000 0x0000026c
78#define MSR_MTRRfix4K_E8000 0x0000026d
79#define MSR_MTRRfix4K_F0000 0x0000026e
80#define MSR_MTRRfix4K_F8000 0x0000026f
81#define MSR_MTRRdefType 0x000002ff
82
83#define MSR_IA32_CR_PAT 0x00000277
84
85#define MSR_IA32_DEBUGCTLMSR 0x000001d9
86#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
87#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
88#define MSR_IA32_LASTINTFROMIP 0x000001dd
89#define MSR_IA32_LASTINTTOIP 0x000001de
90
91/* DEBUGCTLMSR bits (others vary by model): */
92#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
93#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
94#define DEBUGCTLMSR_TR (1UL << 6)
95#define DEBUGCTLMSR_BTS (1UL << 7)
96#define DEBUGCTLMSR_BTINT (1UL << 8)
97#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
98#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
99#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
100
101#define MSR_IA32_MC0_CTL 0x00000400
102#define MSR_IA32_MC0_STATUS 0x00000401
103#define MSR_IA32_MC0_ADDR 0x00000402
104#define MSR_IA32_MC0_MISC 0x00000403
105
106#define MSR_AMD64_MC0_MASK 0xc0010044
107
108#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
109#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
110#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
111#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
112
113#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
114
115/* These are consecutive and not in the normal 4er MCE bank block */
116#define MSR_IA32_MC0_CTL2 0x00000280
117#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
118
119#define MSR_P6_PERFCTR0 0x000000c1
120#define MSR_P6_PERFCTR1 0x000000c2
121#define MSR_P6_EVNTSEL0 0x00000186
122#define MSR_P6_EVNTSEL1 0x00000187
123
124#define MSR_KNC_PERFCTR0 0x00000020
125#define MSR_KNC_PERFCTR1 0x00000021
126#define MSR_KNC_EVNTSEL0 0x00000028
127#define MSR_KNC_EVNTSEL1 0x00000029
128
129/* AMD64 MSRs. Not complete. See the architecture manual for a more
130 complete list. */
131
132#define MSR_AMD64_PATCH_LEVEL 0x0000008b
133#define MSR_AMD64_TSC_RATIO 0xc0000104
134#define MSR_AMD64_NB_CFG 0xc001001f
135#define MSR_AMD64_PATCH_LOADER 0xc0010020
136#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
137#define MSR_AMD64_OSVW_STATUS 0xc0010141
138#define MSR_AMD64_DC_CFG 0xc0011022
139#define MSR_AMD64_IBSFETCHCTL 0xc0011030
140#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
141#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
142#define MSR_AMD64_IBSFETCH_REG_COUNT 3
143#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
144#define MSR_AMD64_IBSOPCTL 0xc0011033
145#define MSR_AMD64_IBSOPRIP 0xc0011034
146#define MSR_AMD64_IBSOPDATA 0xc0011035
147#define MSR_AMD64_IBSOPDATA2 0xc0011036
148#define MSR_AMD64_IBSOPDATA3 0xc0011037
149#define MSR_AMD64_IBSDCLINAD 0xc0011038
150#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
151#define MSR_AMD64_IBSOP_REG_COUNT 7
152#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
153#define MSR_AMD64_IBSCTL 0xc001103a
154#define MSR_AMD64_IBSBRTARGET 0xc001103b
155#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
156
157/* Fam 15h MSRs */
158#define MSR_F15H_PERF_CTL 0xc0010200
159#define MSR_F15H_PERF_CTR 0xc0010201
160
161/* Fam 10h MSRs */
162#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
163#define FAM10H_MMIO_CONF_ENABLE (1<<0)
164#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
165#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
166#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
167#define FAM10H_MMIO_CONF_BASE_SHIFT 20
168#define MSR_FAM10H_NODE_ID 0xc001100c
169
170/* K8 MSRs */
171#define MSR_K8_TOP_MEM1 0xc001001a
172#define MSR_K8_TOP_MEM2 0xc001001d
173#define MSR_K8_SYSCFG 0xc0010010
174#define MSR_K8_INT_PENDING_MSG 0xc0010055
175/* C1E active bits in int pending message */
176#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
177#define MSR_K8_TSEG_ADDR 0xc0010112
178#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
179#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
180#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
181
182/* K7 MSRs */
183#define MSR_K7_EVNTSEL0 0xc0010000
184#define MSR_K7_PERFCTR0 0xc0010004
185#define MSR_K7_EVNTSEL1 0xc0010001
186#define MSR_K7_PERFCTR1 0xc0010005
187#define MSR_K7_EVNTSEL2 0xc0010002
188#define MSR_K7_PERFCTR2 0xc0010006
189#define MSR_K7_EVNTSEL3 0xc0010003
190#define MSR_K7_PERFCTR3 0xc0010007
191#define MSR_K7_CLK_CTL 0xc001001b
192#define MSR_K7_HWCR 0xc0010015
193#define MSR_K7_FID_VID_CTL 0xc0010041
194#define MSR_K7_FID_VID_STATUS 0xc0010042
195
196/* K6 MSRs */
197#define MSR_K6_WHCR 0xc0000082
198#define MSR_K6_UWCCR 0xc0000085
199#define MSR_K6_EPMR 0xc0000086
200#define MSR_K6_PSOR 0xc0000087
201#define MSR_K6_PFIR 0xc0000088
202
203/* Centaur-Hauls/IDT defined MSRs. */
204#define MSR_IDT_FCR1 0x00000107
205#define MSR_IDT_FCR2 0x00000108
206#define MSR_IDT_FCR3 0x00000109
207#define MSR_IDT_FCR4 0x0000010a
208
209#define MSR_IDT_MCR0 0x00000110
210#define MSR_IDT_MCR1 0x00000111
211#define MSR_IDT_MCR2 0x00000112
212#define MSR_IDT_MCR3 0x00000113
213#define MSR_IDT_MCR4 0x00000114
214#define MSR_IDT_MCR5 0x00000115
215#define MSR_IDT_MCR6 0x00000116
216#define MSR_IDT_MCR7 0x00000117
217#define MSR_IDT_MCR_CTRL 0x00000120
218
219/* VIA Cyrix defined MSRs*/
220#define MSR_VIA_FCR 0x00001107
221#define MSR_VIA_LONGHAUL 0x0000110a
222#define MSR_VIA_RNG 0x0000110b
223#define MSR_VIA_BCR2 0x00001147
224
225/* Transmeta defined MSRs */
226#define MSR_TMTA_LONGRUN_CTRL 0x80868010
227#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
228#define MSR_TMTA_LRTI_READOUT 0x80868018
229#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
230
231/* Intel defined MSRs. */
232#define MSR_IA32_P5_MC_ADDR 0x00000000
233#define MSR_IA32_P5_MC_TYPE 0x00000001
234#define MSR_IA32_TSC 0x00000010
235#define MSR_IA32_PLATFORM_ID 0x00000017
236#define MSR_IA32_EBL_CR_POWERON 0x0000002a
237#define MSR_EBC_FREQUENCY_ID 0x0000002c
238#define MSR_IA32_FEATURE_CONTROL 0x0000003a
239#define MSR_IA32_TSC_ADJUST 0x0000003b
240
241#define FEATURE_CONTROL_LOCKED (1<<0)
242#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
243#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
244
245#define MSR_IA32_APICBASE 0x0000001b
246#define MSR_IA32_APICBASE_BSP (1<<8)
247#define MSR_IA32_APICBASE_ENABLE (1<<11)
248#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
249
250#define MSR_IA32_TSCDEADLINE 0x000006e0
251
252#define MSR_IA32_UCODE_WRITE 0x00000079
253#define MSR_IA32_UCODE_REV 0x0000008b
254
255#define MSR_IA32_PERF_STATUS 0x00000198
256#define MSR_IA32_PERF_CTL 0x00000199
257#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
258#define MSR_AMD_PERF_STATUS 0xc0010063
259#define MSR_AMD_PERF_CTL 0xc0010062
260
261#define MSR_IA32_MPERF 0x000000e7
262#define MSR_IA32_APERF 0x000000e8
263
264#define MSR_IA32_THERM_CONTROL 0x0000019a
265#define MSR_IA32_THERM_INTERRUPT 0x0000019b
266
267#define THERM_INT_HIGH_ENABLE (1 << 0)
268#define THERM_INT_LOW_ENABLE (1 << 1)
269#define THERM_INT_PLN_ENABLE (1 << 24)
270
271#define MSR_IA32_THERM_STATUS 0x0000019c
272
273#define THERM_STATUS_PROCHOT (1 << 0)
274#define THERM_STATUS_POWER_LIMIT (1 << 10)
275
276#define MSR_THERM2_CTL 0x0000019d
277
278#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
279
280#define MSR_IA32_MISC_ENABLE 0x000001a0
281
282#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
283
284#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
285#define ENERGY_PERF_BIAS_PERFORMANCE 0
286#define ENERGY_PERF_BIAS_NORMAL 6
287#define ENERGY_PERF_BIAS_POWERSAVE 15
288
289#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
290
291#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
292#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
293
294#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
295
296#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
297#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
298#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
299
300/* Thermal Thresholds Support */
301#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
302#define THERM_SHIFT_THRESHOLD0 8
303#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
304#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
305#define THERM_SHIFT_THRESHOLD1 16
306#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
307#define THERM_STATUS_THRESHOLD0 (1 << 6)
308#define THERM_LOG_THRESHOLD0 (1 << 7)
309#define THERM_STATUS_THRESHOLD1 (1 << 8)
310#define THERM_LOG_THRESHOLD1 (1 << 9)
311
312/* MISC_ENABLE bits: architectural */
313#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
314#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
315#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
316#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
317#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
318#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
319#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
320#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
321#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
322#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
323
324/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
325#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
326#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
327#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
328#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
329#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
330#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
331#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
332#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
333#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
334#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
335#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
336#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
337#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
338#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
339#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
340
341#define MSR_IA32_TSC_DEADLINE 0x000006E0
342
343/* P4/Xeon+ specific */
344#define MSR_IA32_MCG_EAX 0x00000180
345#define MSR_IA32_MCG_EBX 0x00000181
346#define MSR_IA32_MCG_ECX 0x00000182
347#define MSR_IA32_MCG_EDX 0x00000183
348#define MSR_IA32_MCG_ESI 0x00000184
349#define MSR_IA32_MCG_EDI 0x00000185
350#define MSR_IA32_MCG_EBP 0x00000186
351#define MSR_IA32_MCG_ESP 0x00000187
352#define MSR_IA32_MCG_EFLAGS 0x00000188
353#define MSR_IA32_MCG_EIP 0x00000189
354#define MSR_IA32_MCG_RESERVED 0x0000018a
355
356/* Pentium IV performance counter MSRs */
357#define MSR_P4_BPU_PERFCTR0 0x00000300
358#define MSR_P4_BPU_PERFCTR1 0x00000301
359#define MSR_P4_BPU_PERFCTR2 0x00000302
360#define MSR_P4_BPU_PERFCTR3 0x00000303
361#define MSR_P4_MS_PERFCTR0 0x00000304
362#define MSR_P4_MS_PERFCTR1 0x00000305
363#define MSR_P4_MS_PERFCTR2 0x00000306
364#define MSR_P4_MS_PERFCTR3 0x00000307
365#define MSR_P4_FLAME_PERFCTR0 0x00000308
366#define MSR_P4_FLAME_PERFCTR1 0x00000309
367#define MSR_P4_FLAME_PERFCTR2 0x0000030a
368#define MSR_P4_FLAME_PERFCTR3 0x0000030b
369#define MSR_P4_IQ_PERFCTR0 0x0000030c
370#define MSR_P4_IQ_PERFCTR1 0x0000030d
371#define MSR_P4_IQ_PERFCTR2 0x0000030e
372#define MSR_P4_IQ_PERFCTR3 0x0000030f
373#define MSR_P4_IQ_PERFCTR4 0x00000310
374#define MSR_P4_IQ_PERFCTR5 0x00000311
375#define MSR_P4_BPU_CCCR0 0x00000360
376#define MSR_P4_BPU_CCCR1 0x00000361
377#define MSR_P4_BPU_CCCR2 0x00000362
378#define MSR_P4_BPU_CCCR3 0x00000363
379#define MSR_P4_MS_CCCR0 0x00000364
380#define MSR_P4_MS_CCCR1 0x00000365
381#define MSR_P4_MS_CCCR2 0x00000366
382#define MSR_P4_MS_CCCR3 0x00000367
383#define MSR_P4_FLAME_CCCR0 0x00000368
384#define MSR_P4_FLAME_CCCR1 0x00000369
385#define MSR_P4_FLAME_CCCR2 0x0000036a
386#define MSR_P4_FLAME_CCCR3 0x0000036b
387#define MSR_P4_IQ_CCCR0 0x0000036c
388#define MSR_P4_IQ_CCCR1 0x0000036d
389#define MSR_P4_IQ_CCCR2 0x0000036e
390#define MSR_P4_IQ_CCCR3 0x0000036f
391#define MSR_P4_IQ_CCCR4 0x00000370
392#define MSR_P4_IQ_CCCR5 0x00000371
393#define MSR_P4_ALF_ESCR0 0x000003ca
394#define MSR_P4_ALF_ESCR1 0x000003cb
395#define MSR_P4_BPU_ESCR0 0x000003b2
396#define MSR_P4_BPU_ESCR1 0x000003b3
397#define MSR_P4_BSU_ESCR0 0x000003a0
398#define MSR_P4_BSU_ESCR1 0x000003a1
399#define MSR_P4_CRU_ESCR0 0x000003b8
400#define MSR_P4_CRU_ESCR1 0x000003b9
401#define MSR_P4_CRU_ESCR2 0x000003cc
402#define MSR_P4_CRU_ESCR3 0x000003cd
403#define MSR_P4_CRU_ESCR4 0x000003e0
404#define MSR_P4_CRU_ESCR5 0x000003e1
405#define MSR_P4_DAC_ESCR0 0x000003a8
406#define MSR_P4_DAC_ESCR1 0x000003a9
407#define MSR_P4_FIRM_ESCR0 0x000003a4
408#define MSR_P4_FIRM_ESCR1 0x000003a5
409#define MSR_P4_FLAME_ESCR0 0x000003a6
410#define MSR_P4_FLAME_ESCR1 0x000003a7
411#define MSR_P4_FSB_ESCR0 0x000003a2
412#define MSR_P4_FSB_ESCR1 0x000003a3
413#define MSR_P4_IQ_ESCR0 0x000003ba
414#define MSR_P4_IQ_ESCR1 0x000003bb
415#define MSR_P4_IS_ESCR0 0x000003b4
416#define MSR_P4_IS_ESCR1 0x000003b5
417#define MSR_P4_ITLB_ESCR0 0x000003b6
418#define MSR_P4_ITLB_ESCR1 0x000003b7
419#define MSR_P4_IX_ESCR0 0x000003c8
420#define MSR_P4_IX_ESCR1 0x000003c9
421#define MSR_P4_MOB_ESCR0 0x000003aa
422#define MSR_P4_MOB_ESCR1 0x000003ab
423#define MSR_P4_MS_ESCR0 0x000003c0
424#define MSR_P4_MS_ESCR1 0x000003c1
425#define MSR_P4_PMH_ESCR0 0x000003ac
426#define MSR_P4_PMH_ESCR1 0x000003ad
427#define MSR_P4_RAT_ESCR0 0x000003bc
428#define MSR_P4_RAT_ESCR1 0x000003bd
429#define MSR_P4_SAAT_ESCR0 0x000003ae
430#define MSR_P4_SAAT_ESCR1 0x000003af
431#define MSR_P4_SSU_ESCR0 0x000003be
432#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
433
434#define MSR_P4_TBPU_ESCR0 0x000003c2
435#define MSR_P4_TBPU_ESCR1 0x000003c3
436#define MSR_P4_TC_ESCR0 0x000003c4
437#define MSR_P4_TC_ESCR1 0x000003c5
438#define MSR_P4_U2L_ESCR0 0x000003b0
439#define MSR_P4_U2L_ESCR1 0x000003b1
440
441#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
442
443/* Intel Core-based CPU performance counters */
444#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
445#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
446#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
447#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
448#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
449#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
450#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
451
452/* Geode defined MSRs */
453#define MSR_GEODE_BUSCONT_CONF0 0x00001900
454
455/* Intel VT MSRs */
456#define MSR_IA32_VMX_BASIC 0x00000480
457#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
458#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
459#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
460#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
461#define MSR_IA32_VMX_MISC 0x00000485
462#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
463#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
464#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
465#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
466#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
467#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
468#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
469#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
470#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
471#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
472#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
473
474/* VMX_BASIC bits and bitmasks */
475#define VMX_BASIC_VMCS_SIZE_SHIFT 32
476#define VMX_BASIC_64 0x0001000000000000LLU
477#define VMX_BASIC_MEM_TYPE_SHIFT 50
478#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
479#define VMX_BASIC_MEM_TYPE_WB 6LLU
480#define VMX_BASIC_INOUT 0x0040000000000000LLU
481
482/* AMD-V MSRs */
483
484#define MSR_VM_CR 0xc0010114
485#define MSR_VM_IGNNE 0xc0010115
486#define MSR_VM_HSAVE_PA 0xc0010117
487
488#endif /* _ASM_X86_MSR_INDEX_H */
diff --git a/arch/x86/include/uapi/asm/msr.h b/arch/x86/include/uapi/asm/msr.h
new file mode 100644
index 000000000000..155e51048fa4
--- /dev/null
+++ b/arch/x86/include/uapi/asm/msr.h
@@ -0,0 +1,15 @@
1#ifndef _UAPI_ASM_X86_MSR_H
2#define _UAPI_ASM_X86_MSR_H
3
4#include <asm/msr-index.h>
5
6#ifndef __ASSEMBLY__
7
8#include <linux/types.h>
9#include <linux/ioctl.h>
10
11#define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8])
12#define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8])
13
14#endif /* __ASSEMBLY__ */
15#endif /* _UAPI_ASM_X86_MSR_H */
diff --git a/arch/x86/include/uapi/asm/mtrr.h b/arch/x86/include/uapi/asm/mtrr.h
new file mode 100644
index 000000000000..d0acb658c8f4
--- /dev/null
+++ b/arch/x86/include/uapi/asm/mtrr.h
@@ -0,0 +1,117 @@
1/* Generic MTRR (Memory Type Range Register) ioctls.
2
3 Copyright (C) 1997-1999 Richard Gooch
4
5 This library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Library General Public
7 License as published by the Free Software Foundation; either
8 version 2 of the License, or (at your option) any later version.
9
10 This library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Library General Public License for more details.
14
15 You should have received a copy of the GNU Library General Public
16 License along with this library; if not, write to the Free
17 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
20 The postal address is:
21 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
22*/
23#ifndef _UAPI_ASM_X86_MTRR_H
24#define _UAPI_ASM_X86_MTRR_H
25
26#include <linux/types.h>
27#include <linux/ioctl.h>
28#include <linux/errno.h>
29
30#define MTRR_IOCTL_BASE 'M'
31
32/* Warning: this structure has a different order from i386
33 on x86-64. The 32bit emulation code takes care of that.
34 But you need to use this for 64bit, otherwise your X server
35 will break. */
36
37#ifdef __i386__
38struct mtrr_sentry {
39 unsigned long base; /* Base address */
40 unsigned int size; /* Size of region */
41 unsigned int type; /* Type of region */
42};
43
44struct mtrr_gentry {
45 unsigned int regnum; /* Register number */
46 unsigned long base; /* Base address */
47 unsigned int size; /* Size of region */
48 unsigned int type; /* Type of region */
49};
50
51#else /* __i386__ */
52
53struct mtrr_sentry {
54 __u64 base; /* Base address */
55 __u32 size; /* Size of region */
56 __u32 type; /* Type of region */
57};
58
59struct mtrr_gentry {
60 __u64 base; /* Base address */
61 __u32 size; /* Size of region */
62 __u32 regnum; /* Register number */
63 __u32 type; /* Type of region */
64 __u32 _pad; /* Unused */
65};
66
67#endif /* !__i386__ */
68
69struct mtrr_var_range {
70 __u32 base_lo;
71 __u32 base_hi;
72 __u32 mask_lo;
73 __u32 mask_hi;
74};
75
76/* In the Intel processor's MTRR interface, the MTRR type is always held in
77 an 8 bit field: */
78typedef __u8 mtrr_type;
79
80#define MTRR_NUM_FIXED_RANGES 88
81#define MTRR_MAX_VAR_RANGES 256
82
83struct mtrr_state_type {
84 struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES];
85 mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES];
86 unsigned char enabled;
87 unsigned char have_fixed;
88 mtrr_type def_type;
89};
90
91#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
92#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
93
94/* These are the various ioctls */
95#define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry)
96#define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry)
97#define MTRRIOC_DEL_ENTRY _IOW(MTRR_IOCTL_BASE, 2, struct mtrr_sentry)
98#define MTRRIOC_GET_ENTRY _IOWR(MTRR_IOCTL_BASE, 3, struct mtrr_gentry)
99#define MTRRIOC_KILL_ENTRY _IOW(MTRR_IOCTL_BASE, 4, struct mtrr_sentry)
100#define MTRRIOC_ADD_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 5, struct mtrr_sentry)
101#define MTRRIOC_SET_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 6, struct mtrr_sentry)
102#define MTRRIOC_DEL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 7, struct mtrr_sentry)
103#define MTRRIOC_GET_PAGE_ENTRY _IOWR(MTRR_IOCTL_BASE, 8, struct mtrr_gentry)
104#define MTRRIOC_KILL_PAGE_ENTRY _IOW(MTRR_IOCTL_BASE, 9, struct mtrr_sentry)
105
106/* These are the region types */
107#define MTRR_TYPE_UNCACHABLE 0
108#define MTRR_TYPE_WRCOMB 1
109/*#define MTRR_TYPE_ 2*/
110/*#define MTRR_TYPE_ 3*/
111#define MTRR_TYPE_WRTHROUGH 4
112#define MTRR_TYPE_WRPROT 5
113#define MTRR_TYPE_WRBACK 6
114#define MTRR_NUM_TYPES 7
115
116
117#endif /* _UAPI_ASM_X86_MTRR_H */
diff --git a/arch/x86/include/uapi/asm/param.h b/arch/x86/include/uapi/asm/param.h
new file mode 100644
index 000000000000..965d45427975
--- /dev/null
+++ b/arch/x86/include/uapi/asm/param.h
@@ -0,0 +1 @@
#include <asm-generic/param.h>
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
new file mode 100644
index 000000000000..3f2207bfd17b
--- /dev/null
+++ b/arch/x86/include/uapi/asm/perf_regs.h
@@ -0,0 +1,33 @@
1#ifndef _ASM_X86_PERF_REGS_H
2#define _ASM_X86_PERF_REGS_H
3
4enum perf_event_x86_regs {
5 PERF_REG_X86_AX,
6 PERF_REG_X86_BX,
7 PERF_REG_X86_CX,
8 PERF_REG_X86_DX,
9 PERF_REG_X86_SI,
10 PERF_REG_X86_DI,
11 PERF_REG_X86_BP,
12 PERF_REG_X86_SP,
13 PERF_REG_X86_IP,
14 PERF_REG_X86_FLAGS,
15 PERF_REG_X86_CS,
16 PERF_REG_X86_SS,
17 PERF_REG_X86_DS,
18 PERF_REG_X86_ES,
19 PERF_REG_X86_FS,
20 PERF_REG_X86_GS,
21 PERF_REG_X86_R8,
22 PERF_REG_X86_R9,
23 PERF_REG_X86_R10,
24 PERF_REG_X86_R11,
25 PERF_REG_X86_R12,
26 PERF_REG_X86_R13,
27 PERF_REG_X86_R14,
28 PERF_REG_X86_R15,
29
30 PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
31 PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
32};
33#endif /* _ASM_X86_PERF_REGS_H */
diff --git a/arch/x86/include/uapi/asm/poll.h b/arch/x86/include/uapi/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/x86/include/uapi/asm/poll.h
@@ -0,0 +1 @@
#include <asm-generic/poll.h>
diff --git a/arch/x86/include/uapi/asm/posix_types.h b/arch/x86/include/uapi/asm/posix_types.h
new file mode 100644
index 000000000000..85506b383627
--- /dev/null
+++ b/arch/x86/include/uapi/asm/posix_types.h
@@ -0,0 +1,9 @@
1#ifndef __KERNEL__
2# ifdef __i386__
3# include <asm/posix_types_32.h>
4# elif defined(__ILP32__)
5# include <asm/posix_types_x32.h>
6# else
7# include <asm/posix_types_64.h>
8# endif
9#endif
diff --git a/arch/x86/include/uapi/asm/posix_types_32.h b/arch/x86/include/uapi/asm/posix_types_32.h
new file mode 100644
index 000000000000..8e525059e7d8
--- /dev/null
+++ b/arch/x86/include/uapi/asm/posix_types_32.h
@@ -0,0 +1,25 @@
1#ifndef _ASM_X86_POSIX_TYPES_32_H
2#define _ASM_X86_POSIX_TYPES_32_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned short __kernel_mode_t;
11#define __kernel_mode_t __kernel_mode_t
12
13typedef unsigned short __kernel_ipc_pid_t;
14#define __kernel_ipc_pid_t __kernel_ipc_pid_t
15
16typedef unsigned short __kernel_uid_t;
17typedef unsigned short __kernel_gid_t;
18#define __kernel_uid_t __kernel_uid_t
19
20typedef unsigned short __kernel_old_dev_t;
21#define __kernel_old_dev_t __kernel_old_dev_t
22
23#include <asm-generic/posix_types.h>
24
25#endif /* _ASM_X86_POSIX_TYPES_32_H */
diff --git a/arch/x86/include/uapi/asm/posix_types_64.h b/arch/x86/include/uapi/asm/posix_types_64.h
new file mode 100644
index 000000000000..cba0c1ead162
--- /dev/null
+++ b/arch/x86/include/uapi/asm/posix_types_64.h
@@ -0,0 +1,19 @@
1#ifndef _ASM_X86_POSIX_TYPES_64_H
2#define _ASM_X86_POSIX_TYPES_64_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned short __kernel_old_uid_t;
11typedef unsigned short __kernel_old_gid_t;
12#define __kernel_old_uid_t __kernel_old_uid_t
13
14typedef unsigned long __kernel_old_dev_t;
15#define __kernel_old_dev_t __kernel_old_dev_t
16
17#include <asm-generic/posix_types.h>
18
19#endif /* _ASM_X86_POSIX_TYPES_64_H */
diff --git a/arch/x86/include/uapi/asm/posix_types_x32.h b/arch/x86/include/uapi/asm/posix_types_x32.h
new file mode 100644
index 000000000000..85f9bdafa93c
--- /dev/null
+++ b/arch/x86/include/uapi/asm/posix_types_x32.h
@@ -0,0 +1,19 @@
1#ifndef _ASM_X86_POSIX_TYPES_X32_H
2#define _ASM_X86_POSIX_TYPES_X32_H
3
4/*
5 * This file is only used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 *
9 * These types should generally match the ones used by the 64-bit kernel,
10 *
11 */
12
13typedef long long __kernel_long_t;
14typedef unsigned long long __kernel_ulong_t;
15#define __kernel_long_t __kernel_long_t
16
17#include <asm/posix_types_64.h>
18
19#endif /* _ASM_X86_POSIX_TYPES_X32_H */
diff --git a/arch/x86/include/uapi/asm/prctl.h b/arch/x86/include/uapi/asm/prctl.h
new file mode 100644
index 000000000000..3ac5032fae09
--- /dev/null
+++ b/arch/x86/include/uapi/asm/prctl.h
@@ -0,0 +1,9 @@
1#ifndef _ASM_X86_PRCTL_H
2#define _ASM_X86_PRCTL_H
3
4#define ARCH_SET_GS 0x1001
5#define ARCH_SET_FS 0x1002
6#define ARCH_GET_FS 0x1003
7#define ARCH_GET_GS 0x1004
8
9#endif /* _ASM_X86_PRCTL_H */
diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h
new file mode 100644
index 000000000000..54991a746043
--- /dev/null
+++ b/arch/x86/include/uapi/asm/processor-flags.h
@@ -0,0 +1,99 @@
1#ifndef _UAPI_ASM_X86_PROCESSOR_FLAGS_H
2#define _UAPI_ASM_X86_PROCESSOR_FLAGS_H
3/* Various flags defined: can be included from assembler. */
4
5/*
6 * EFLAGS bits
7 */
8#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
9#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */
10#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
11#define X86_EFLAGS_AF 0x00000010 /* Auxiliary carry Flag */
12#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
13#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
14#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
15#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
16#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
17#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
18#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
19#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
20#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
21#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
22#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
23#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
24#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
25#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
26
27/*
28 * Basic CPU control in CR0
29 */
30#define X86_CR0_PE 0x00000001 /* Protection Enable */
31#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
32#define X86_CR0_EM 0x00000004 /* Emulation */
33#define X86_CR0_TS 0x00000008 /* Task Switched */
34#define X86_CR0_ET 0x00000010 /* Extension Type */
35#define X86_CR0_NE 0x00000020 /* Numeric Error */
36#define X86_CR0_WP 0x00010000 /* Write Protect */
37#define X86_CR0_AM 0x00040000 /* Alignment Mask */
38#define X86_CR0_NW 0x20000000 /* Not Write-through */
39#define X86_CR0_CD 0x40000000 /* Cache Disable */
40#define X86_CR0_PG 0x80000000 /* Paging */
41
42/*
43 * Paging options in CR3
44 */
45#define X86_CR3_PWT 0x00000008 /* Page Write Through */
46#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */
47#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */
48
49/*
50 * Intel CPU features in CR4
51 */
52#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */
53#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */
54#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */
55#define X86_CR4_DE 0x00000008 /* enable debugging extensions */
56#define X86_CR4_PSE 0x00000010 /* enable page size extensions */
57#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
58#define X86_CR4_MCE 0x00000040 /* Machine check enable */
59#define X86_CR4_PGE 0x00000080 /* enable global pages */
60#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */
61#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
62#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
63#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
64#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
65#define X86_CR4_PCIDE 0x00020000 /* enable PCID support */
66#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
67#define X86_CR4_SMEP 0x00100000 /* enable SMEP support */
68#define X86_CR4_SMAP 0x00200000 /* enable SMAP support */
69
70/*
71 * x86-64 Task Priority Register, CR8
72 */
73#define X86_CR8_TPR 0x0000000F /* task priority register */
74
75/*
76 * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
77 */
78
79/*
80 * NSC/Cyrix CPU configuration register indexes
81 */
82#define CX86_PCR0 0x20
83#define CX86_GCR 0xb8
84#define CX86_CCR0 0xc0
85#define CX86_CCR1 0xc1
86#define CX86_CCR2 0xc2
87#define CX86_CCR3 0xc3
88#define CX86_CCR4 0xe8
89#define CX86_CCR5 0xe9
90#define CX86_CCR6 0xea
91#define CX86_CCR7 0xeb
92#define CX86_PCR1 0xf0
93#define CX86_DIR0 0xfe
94#define CX86_DIR1 0xff
95#define CX86_ARR_BASE 0xc4
96#define CX86_RCR_BASE 0xdc
97
98
99#endif /* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */
diff --git a/arch/x86/include/uapi/asm/ptrace-abi.h b/arch/x86/include/uapi/asm/ptrace-abi.h
new file mode 100644
index 000000000000..7b0a55a88851
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ptrace-abi.h
@@ -0,0 +1,87 @@
1#ifndef _ASM_X86_PTRACE_ABI_H
2#define _ASM_X86_PTRACE_ABI_H
3
4#ifdef __i386__
5
6#define EBX 0
7#define ECX 1
8#define EDX 2
9#define ESI 3
10#define EDI 4
11#define EBP 5
12#define EAX 6
13#define DS 7
14#define ES 8
15#define FS 9
16#define GS 10
17#define ORIG_EAX 11
18#define EIP 12
19#define CS 13
20#define EFL 14
21#define UESP 15
22#define SS 16
23#define FRAME_SIZE 17
24
25#else /* __i386__ */
26
27#if defined(__ASSEMBLY__) || defined(__FRAME_OFFSETS)
28#define R15 0
29#define R14 8
30#define R13 16
31#define R12 24
32#define RBP 32
33#define RBX 40
34/* arguments: interrupts/non tracing syscalls only save up to here*/
35#define R11 48
36#define R10 56
37#define R9 64
38#define R8 72
39#define RAX 80
40#define RCX 88
41#define RDX 96
42#define RSI 104
43#define RDI 112
44#define ORIG_RAX 120 /* = ERROR */
45/* end of arguments */
46/* cpu exception frame or undefined in case of fast syscall. */
47#define RIP 128
48#define CS 136
49#define EFLAGS 144
50#define RSP 152
51#define SS 160
52#define ARGOFFSET R11
53#endif /* __ASSEMBLY__ */
54
55/* top of stack page */
56#define FRAME_SIZE 168
57
58#endif /* !__i386__ */
59
60/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
61#define PTRACE_GETREGS 12
62#define PTRACE_SETREGS 13
63#define PTRACE_GETFPREGS 14
64#define PTRACE_SETFPREGS 15
65#define PTRACE_GETFPXREGS 18
66#define PTRACE_SETFPXREGS 19
67
68#define PTRACE_OLDSETOPTIONS 21
69
70/* only useful for access 32bit programs / kernels */
71#define PTRACE_GET_THREAD_AREA 25
72#define PTRACE_SET_THREAD_AREA 26
73
74#ifdef __x86_64__
75# define PTRACE_ARCH_PRCTL 30
76#endif
77
78#define PTRACE_SYSEMU 31
79#define PTRACE_SYSEMU_SINGLESTEP 32
80
81#define PTRACE_SINGLEBLOCK 33 /* resume execution until next branch */
82
83#ifndef __ASSEMBLY__
84#include <linux/types.h>
85#endif
86
87#endif /* _ASM_X86_PTRACE_ABI_H */
diff --git a/arch/x86/include/uapi/asm/ptrace.h b/arch/x86/include/uapi/asm/ptrace.h
new file mode 100644
index 000000000000..ac4b9aa4d999
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ptrace.h
@@ -0,0 +1,78 @@
1#ifndef _UAPI_ASM_X86_PTRACE_H
2#define _UAPI_ASM_X86_PTRACE_H
3
4#include <linux/compiler.h> /* For __user */
5#include <asm/ptrace-abi.h>
6#include <asm/processor-flags.h>
7
8
9#ifndef __ASSEMBLY__
10
11#ifdef __i386__
12/* this struct defines the way the registers are stored on the
13 stack during a system call. */
14
15#ifndef __KERNEL__
16
17struct pt_regs {
18 long ebx;
19 long ecx;
20 long edx;
21 long esi;
22 long edi;
23 long ebp;
24 long eax;
25 int xds;
26 int xes;
27 int xfs;
28 int xgs;
29 long orig_eax;
30 long eip;
31 int xcs;
32 long eflags;
33 long esp;
34 int xss;
35};
36
37#endif /* __KERNEL__ */
38
39#else /* __i386__ */
40
41#ifndef __KERNEL__
42
43struct pt_regs {
44 unsigned long r15;
45 unsigned long r14;
46 unsigned long r13;
47 unsigned long r12;
48 unsigned long rbp;
49 unsigned long rbx;
50/* arguments: non interrupts/non tracing syscalls only save up to here*/
51 unsigned long r11;
52 unsigned long r10;
53 unsigned long r9;
54 unsigned long r8;
55 unsigned long rax;
56 unsigned long rcx;
57 unsigned long rdx;
58 unsigned long rsi;
59 unsigned long rdi;
60 unsigned long orig_rax;
61/* end of arguments */
62/* cpu exception frame or undefined */
63 unsigned long rip;
64 unsigned long cs;
65 unsigned long eflags;
66 unsigned long rsp;
67 unsigned long ss;
68/* top of stack page */
69};
70
71#endif /* __KERNEL__ */
72#endif /* !__i386__ */
73
74
75
76#endif /* !__ASSEMBLY__ */
77
78#endif /* _UAPI_ASM_X86_PTRACE_H */
diff --git a/arch/x86/include/uapi/asm/resource.h b/arch/x86/include/uapi/asm/resource.h
new file mode 100644
index 000000000000..04bc4db8921b
--- /dev/null
+++ b/arch/x86/include/uapi/asm/resource.h
@@ -0,0 +1 @@
#include <asm-generic/resource.h>
diff --git a/arch/x86/include/uapi/asm/sembuf.h b/arch/x86/include/uapi/asm/sembuf.h
new file mode 100644
index 000000000000..ee50c801f7b7
--- /dev/null
+++ b/arch/x86/include/uapi/asm/sembuf.h
@@ -0,0 +1,24 @@
1#ifndef _ASM_X86_SEMBUF_H
2#define _ASM_X86_SEMBUF_H
3
4/*
5 * The semid64_ds structure for x86 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 64-bit time_t to solve y2038 problem
11 * - 2 miscellaneous 32-bit values
12 */
13struct semid64_ds {
14 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
15 __kernel_time_t sem_otime; /* last semop time */
16 unsigned long __unused1;
17 __kernel_time_t sem_ctime; /* last change time */
18 unsigned long __unused2;
19 unsigned long sem_nsems; /* no. of semaphores in array */
20 unsigned long __unused3;
21 unsigned long __unused4;
22};
23
24#endif /* _ASM_X86_SEMBUF_H */
diff --git a/arch/x86/include/uapi/asm/setup.h b/arch/x86/include/uapi/asm/setup.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/x86/include/uapi/asm/setup.h
diff --git a/arch/x86/include/uapi/asm/shmbuf.h b/arch/x86/include/uapi/asm/shmbuf.h
new file mode 100644
index 000000000000..83c05fc2de38
--- /dev/null
+++ b/arch/x86/include/uapi/asm/shmbuf.h
@@ -0,0 +1 @@
#include <asm-generic/shmbuf.h>
diff --git a/arch/x86/include/uapi/asm/sigcontext.h b/arch/x86/include/uapi/asm/sigcontext.h
new file mode 100644
index 000000000000..d8b9f9081e86
--- /dev/null
+++ b/arch/x86/include/uapi/asm/sigcontext.h
@@ -0,0 +1,221 @@
1#ifndef _UAPI_ASM_X86_SIGCONTEXT_H
2#define _UAPI_ASM_X86_SIGCONTEXT_H
3
4#include <linux/compiler.h>
5#include <linux/types.h>
6
7#define FP_XSTATE_MAGIC1 0x46505853U
8#define FP_XSTATE_MAGIC2 0x46505845U
9#define FP_XSTATE_MAGIC2_SIZE sizeof(FP_XSTATE_MAGIC2)
10
11/*
12 * bytes 464..511 in the current 512byte layout of fxsave/fxrstor frame
13 * are reserved for SW usage. On cpu's supporting xsave/xrstor, these bytes
14 * are used to extended the fpstate pointer in the sigcontext, which now
15 * includes the extended state information along with fpstate information.
16 *
17 * Presence of FP_XSTATE_MAGIC1 at the beginning of this SW reserved
18 * area and FP_XSTATE_MAGIC2 at the end of memory layout
19 * (extended_size - FP_XSTATE_MAGIC2_SIZE) indicates the presence of the
20 * extended state information in the memory layout pointed by the fpstate
21 * pointer in sigcontext.
22 */
23struct _fpx_sw_bytes {
24 __u32 magic1; /* FP_XSTATE_MAGIC1 */
25 __u32 extended_size; /* total size of the layout referred by
26 * fpstate pointer in the sigcontext.
27 */
28 __u64 xstate_bv;
29 /* feature bit mask (including fp/sse/extended
30 * state) that is present in the memory
31 * layout.
32 */
33 __u32 xstate_size; /* actual xsave state size, based on the
34 * features saved in the layout.
35 * 'extended_size' will be greater than
36 * 'xstate_size'.
37 */
38 __u32 padding[7]; /* for future use. */
39};
40
41#ifdef __i386__
42/*
43 * As documented in the iBCS2 standard..
44 *
45 * The first part of "struct _fpstate" is just the normal i387
46 * hardware setup, the extra "status" word is used to save the
47 * coprocessor status word before entering the handler.
48 *
49 * Pentium III FXSR, SSE support
50 * Gareth Hughes <gareth@valinux.com>, May 2000
51 *
52 * The FPU state data structure has had to grow to accommodate the
53 * extended FPU state required by the Streaming SIMD Extensions.
54 * There is no documented standard to accomplish this at the moment.
55 */
56struct _fpreg {
57 unsigned short significand[4];
58 unsigned short exponent;
59};
60
61struct _fpxreg {
62 unsigned short significand[4];
63 unsigned short exponent;
64 unsigned short padding[3];
65};
66
67struct _xmmreg {
68 unsigned long element[4];
69};
70
71struct _fpstate {
72 /* Regular FPU environment */
73 unsigned long cw;
74 unsigned long sw;
75 unsigned long tag;
76 unsigned long ipoff;
77 unsigned long cssel;
78 unsigned long dataoff;
79 unsigned long datasel;
80 struct _fpreg _st[8];
81 unsigned short status;
82 unsigned short magic; /* 0xffff = regular FPU data only */
83
84 /* FXSR FPU environment */
85 unsigned long _fxsr_env[6]; /* FXSR FPU env is ignored */
86 unsigned long mxcsr;
87 unsigned long reserved;
88 struct _fpxreg _fxsr_st[8]; /* FXSR FPU reg data is ignored */
89 struct _xmmreg _xmm[8];
90 unsigned long padding1[44];
91
92 union {
93 unsigned long padding2[12];
94 struct _fpx_sw_bytes sw_reserved; /* represents the extended
95 * state info */
96 };
97};
98
99#define X86_FXSR_MAGIC 0x0000
100
101#ifndef __KERNEL__
102/*
103 * User-space might still rely on the old definition:
104 */
105struct sigcontext {
106 unsigned short gs, __gsh;
107 unsigned short fs, __fsh;
108 unsigned short es, __esh;
109 unsigned short ds, __dsh;
110 unsigned long edi;
111 unsigned long esi;
112 unsigned long ebp;
113 unsigned long esp;
114 unsigned long ebx;
115 unsigned long edx;
116 unsigned long ecx;
117 unsigned long eax;
118 unsigned long trapno;
119 unsigned long err;
120 unsigned long eip;
121 unsigned short cs, __csh;
122 unsigned long eflags;
123 unsigned long esp_at_signal;
124 unsigned short ss, __ssh;
125 struct _fpstate __user *fpstate;
126 unsigned long oldmask;
127 unsigned long cr2;
128};
129#endif /* !__KERNEL__ */
130
131#else /* __i386__ */
132
133/* FXSAVE frame */
134/* Note: reserved1/2 may someday contain valuable data. Always save/restore
135 them when you change signal frames. */
136struct _fpstate {
137 __u16 cwd;
138 __u16 swd;
139 __u16 twd; /* Note this is not the same as the
140 32bit/x87/FSAVE twd */
141 __u16 fop;
142 __u64 rip;
143 __u64 rdp;
144 __u32 mxcsr;
145 __u32 mxcsr_mask;
146 __u32 st_space[32]; /* 8*16 bytes for each FP-reg */
147 __u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg */
148 __u32 reserved2[12];
149 union {
150 __u32 reserved3[12];
151 struct _fpx_sw_bytes sw_reserved; /* represents the extended
152 * state information */
153 };
154};
155
156#ifndef __KERNEL__
157/*
158 * User-space might still rely on the old definition:
159 */
160struct sigcontext {
161 __u64 r8;
162 __u64 r9;
163 __u64 r10;
164 __u64 r11;
165 __u64 r12;
166 __u64 r13;
167 __u64 r14;
168 __u64 r15;
169 __u64 rdi;
170 __u64 rsi;
171 __u64 rbp;
172 __u64 rbx;
173 __u64 rdx;
174 __u64 rax;
175 __u64 rcx;
176 __u64 rsp;
177 __u64 rip;
178 __u64 eflags; /* RFLAGS */
179 __u16 cs;
180 __u16 gs;
181 __u16 fs;
182 __u16 __pad0;
183 __u64 err;
184 __u64 trapno;
185 __u64 oldmask;
186 __u64 cr2;
187 struct _fpstate __user *fpstate; /* zero when no FPU context */
188#ifdef __ILP32__
189 __u32 __fpstate_pad;
190#endif
191 __u64 reserved1[8];
192};
193#endif /* !__KERNEL__ */
194
195#endif /* !__i386__ */
196
197struct _xsave_hdr {
198 __u64 xstate_bv;
199 __u64 reserved1[2];
200 __u64 reserved2[5];
201};
202
203struct _ymmh_state {
204 /* 16 * 16 bytes for each YMMH-reg */
205 __u32 ymmh_space[64];
206};
207
208/*
209 * Extended state pointed by the fpstate pointer in the sigcontext.
210 * In addition to the fpstate, information encoded in the xstate_hdr
211 * indicates the presence of other extended state information
212 * supported by the processor and OS.
213 */
214struct _xstate {
215 struct _fpstate fpstate;
216 struct _xsave_hdr xstate_hdr;
217 struct _ymmh_state ymmh;
218 /* new processor state extensions go here */
219};
220
221#endif /* _UAPI_ASM_X86_SIGCONTEXT_H */
diff --git a/arch/x86/include/uapi/asm/sigcontext32.h b/arch/x86/include/uapi/asm/sigcontext32.h
new file mode 100644
index 000000000000..ad1478c4ae12
--- /dev/null
+++ b/arch/x86/include/uapi/asm/sigcontext32.h
@@ -0,0 +1,77 @@
1#ifndef _ASM_X86_SIGCONTEXT32_H
2#define _ASM_X86_SIGCONTEXT32_H
3
4#include <linux/types.h>
5
6/* signal context for 32bit programs. */
7
8#define X86_FXSR_MAGIC 0x0000
9
10struct _fpreg {
11 unsigned short significand[4];
12 unsigned short exponent;
13};
14
15struct _fpxreg {
16 unsigned short significand[4];
17 unsigned short exponent;
18 unsigned short padding[3];
19};
20
21struct _xmmreg {
22 __u32 element[4];
23};
24
25/* FSAVE frame with extensions */
26struct _fpstate_ia32 {
27 /* Regular FPU environment */
28 __u32 cw;
29 __u32 sw;
30 __u32 tag; /* not compatible to 64bit twd */
31 __u32 ipoff;
32 __u32 cssel;
33 __u32 dataoff;
34 __u32 datasel;
35 struct _fpreg _st[8];
36 unsigned short status;
37 unsigned short magic; /* 0xffff = regular FPU data only */
38
39 /* FXSR FPU environment */
40 __u32 _fxsr_env[6];
41 __u32 mxcsr;
42 __u32 reserved;
43 struct _fpxreg _fxsr_st[8];
44 struct _xmmreg _xmm[8]; /* It's actually 16 */
45 __u32 padding[44];
46 union {
47 __u32 padding2[12];
48 struct _fpx_sw_bytes sw_reserved;
49 };
50};
51
52struct sigcontext_ia32 {
53 unsigned short gs, __gsh;
54 unsigned short fs, __fsh;
55 unsigned short es, __esh;
56 unsigned short ds, __dsh;
57 unsigned int di;
58 unsigned int si;
59 unsigned int bp;
60 unsigned int sp;
61 unsigned int bx;
62 unsigned int dx;
63 unsigned int cx;
64 unsigned int ax;
65 unsigned int trapno;
66 unsigned int err;
67 unsigned int ip;
68 unsigned short cs, __csh;
69 unsigned int flags;
70 unsigned int sp_at_signal;
71 unsigned short ss, __ssh;
72 unsigned int fpstate; /* really (struct _fpstate_ia32 *) */
73 unsigned int oldmask;
74 unsigned int cr2;
75};
76
77#endif /* _ASM_X86_SIGCONTEXT32_H */
diff --git a/arch/x86/include/uapi/asm/siginfo.h b/arch/x86/include/uapi/asm/siginfo.h
new file mode 100644
index 000000000000..34c47b3341c0
--- /dev/null
+++ b/arch/x86/include/uapi/asm/siginfo.h
@@ -0,0 +1,16 @@
1#ifndef _ASM_X86_SIGINFO_H
2#define _ASM_X86_SIGINFO_H
3
4#ifdef __x86_64__
5# ifdef __ILP32__ /* x32 */
6typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
7# define __ARCH_SI_CLOCK_T __kernel_si_clock_t
8# define __ARCH_SI_ATTRIBUTES __attribute__((aligned(8)))
9# else /* x86-64 */
10# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
11# endif
12#endif
13
14#include <asm-generic/siginfo.h>
15
16#endif /* _ASM_X86_SIGINFO_H */
diff --git a/arch/x86/include/uapi/asm/signal.h b/arch/x86/include/uapi/asm/signal.h
new file mode 100644
index 000000000000..0818f9a8e889
--- /dev/null
+++ b/arch/x86/include/uapi/asm/signal.h
@@ -0,0 +1,145 @@
1#ifndef _UAPI_ASM_X86_SIGNAL_H
2#define _UAPI_ASM_X86_SIGNAL_H
3
4#ifndef __ASSEMBLY__
5#include <linux/types.h>
6#include <linux/time.h>
7#include <linux/compiler.h>
8
9/* Avoid too many header ordering problems. */
10struct siginfo;
11
12#ifndef __KERNEL__
13/* Here we must cater to libcs that poke about in kernel headers. */
14
15#define NSIG 32
16typedef unsigned long sigset_t;
17
18#endif /* __KERNEL__ */
19#endif /* __ASSEMBLY__ */
20
21
22#define SIGHUP 1
23#define SIGINT 2
24#define SIGQUIT 3
25#define SIGILL 4
26#define SIGTRAP 5
27#define SIGABRT 6
28#define SIGIOT 6
29#define SIGBUS 7
30#define SIGFPE 8
31#define SIGKILL 9
32#define SIGUSR1 10
33#define SIGSEGV 11
34#define SIGUSR2 12
35#define SIGPIPE 13
36#define SIGALRM 14
37#define SIGTERM 15
38#define SIGSTKFLT 16
39#define SIGCHLD 17
40#define SIGCONT 18
41#define SIGSTOP 19
42#define SIGTSTP 20
43#define SIGTTIN 21
44#define SIGTTOU 22
45#define SIGURG 23
46#define SIGXCPU 24
47#define SIGXFSZ 25
48#define SIGVTALRM 26
49#define SIGPROF 27
50#define SIGWINCH 28
51#define SIGIO 29
52#define SIGPOLL SIGIO
53/*
54#define SIGLOST 29
55*/
56#define SIGPWR 30
57#define SIGSYS 31
58#define SIGUNUSED 31
59
60/* These should not be considered constants from userland. */
61#define SIGRTMIN 32
62#define SIGRTMAX _NSIG
63
64/*
65 * SA_FLAGS values:
66 *
67 * SA_ONSTACK indicates that a registered stack_t will be used.
68 * SA_RESTART flag to get restarting signals (which were the default long ago)
69 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
70 * SA_RESETHAND clears the handler when the signal is delivered.
71 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
72 * SA_NODEFER prevents the current signal from being masked in the handler.
73 *
74 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
75 * Unix names RESETHAND and NODEFER respectively.
76 */
77#define SA_NOCLDSTOP 0x00000001u
78#define SA_NOCLDWAIT 0x00000002u
79#define SA_SIGINFO 0x00000004u
80#define SA_ONSTACK 0x08000000u
81#define SA_RESTART 0x10000000u
82#define SA_NODEFER 0x40000000u
83#define SA_RESETHAND 0x80000000u
84
85#define SA_NOMASK SA_NODEFER
86#define SA_ONESHOT SA_RESETHAND
87
88#define SA_RESTORER 0x04000000
89
90/*
91 * sigaltstack controls
92 */
93#define SS_ONSTACK 1
94#define SS_DISABLE 2
95
96#define MINSIGSTKSZ 2048
97#define SIGSTKSZ 8192
98
99#include <asm-generic/signal-defs.h>
100
101#ifndef __ASSEMBLY__
102
103
104#ifdef __i386__
105# ifndef __KERNEL__
106/* Here we must cater to libcs that poke about in kernel headers. */
107
108struct sigaction {
109 union {
110 __sighandler_t _sa_handler;
111 void (*_sa_sigaction)(int, struct siginfo *, void *);
112 } _u;
113 sigset_t sa_mask;
114 unsigned long sa_flags;
115 void (*sa_restorer)(void);
116};
117
118#define sa_handler _u._sa_handler
119#define sa_sigaction _u._sa_sigaction
120
121# endif /* ! __KERNEL__ */
122#else /* __i386__ */
123
124struct sigaction {
125 __sighandler_t sa_handler;
126 unsigned long sa_flags;
127 __sigrestore_t sa_restorer;
128 sigset_t sa_mask; /* mask last for extensibility */
129};
130
131struct k_sigaction {
132 struct sigaction sa;
133};
134
135#endif /* !__i386__ */
136
137typedef struct sigaltstack {
138 void __user *ss_sp;
139 int ss_flags;
140 size_t ss_size;
141} stack_t;
142
143#endif /* __ASSEMBLY__ */
144
145#endif /* _UAPI_ASM_X86_SIGNAL_H */
diff --git a/arch/x86/include/uapi/asm/socket.h b/arch/x86/include/uapi/asm/socket.h
new file mode 100644
index 000000000000..6b71384b9d8b
--- /dev/null
+++ b/arch/x86/include/uapi/asm/socket.h
@@ -0,0 +1 @@
#include <asm-generic/socket.h>
diff --git a/arch/x86/include/uapi/asm/sockios.h b/arch/x86/include/uapi/asm/sockios.h
new file mode 100644
index 000000000000..def6d4746ee7
--- /dev/null
+++ b/arch/x86/include/uapi/asm/sockios.h
@@ -0,0 +1 @@
#include <asm-generic/sockios.h>
diff --git a/arch/x86/include/uapi/asm/stat.h b/arch/x86/include/uapi/asm/stat.h
new file mode 100644
index 000000000000..7b3ddc348585
--- /dev/null
+++ b/arch/x86/include/uapi/asm/stat.h
@@ -0,0 +1,135 @@
1#ifndef _ASM_X86_STAT_H
2#define _ASM_X86_STAT_H
3
4#define STAT_HAVE_NSEC 1
5
6#ifdef __i386__
7struct stat {
8 unsigned long st_dev;
9 unsigned long st_ino;
10 unsigned short st_mode;
11 unsigned short st_nlink;
12 unsigned short st_uid;
13 unsigned short st_gid;
14 unsigned long st_rdev;
15 unsigned long st_size;
16 unsigned long st_blksize;
17 unsigned long st_blocks;
18 unsigned long st_atime;
19 unsigned long st_atime_nsec;
20 unsigned long st_mtime;
21 unsigned long st_mtime_nsec;
22 unsigned long st_ctime;
23 unsigned long st_ctime_nsec;
24 unsigned long __unused4;
25 unsigned long __unused5;
26};
27
28/* We don't need to memset the whole thing just to initialize the padding */
29#define INIT_STRUCT_STAT_PADDING(st) do { \
30 st.__unused4 = 0; \
31 st.__unused5 = 0; \
32} while (0)
33
34#define STAT64_HAS_BROKEN_ST_INO 1
35
36/* This matches struct stat64 in glibc2.1, hence the absolutely
37 * insane amounts of padding around dev_t's.
38 */
39struct stat64 {
40 unsigned long long st_dev;
41 unsigned char __pad0[4];
42
43 unsigned long __st_ino;
44
45 unsigned int st_mode;
46 unsigned int st_nlink;
47
48 unsigned long st_uid;
49 unsigned long st_gid;
50
51 unsigned long long st_rdev;
52 unsigned char __pad3[4];
53
54 long long st_size;
55 unsigned long st_blksize;
56
57 /* Number 512-byte blocks allocated. */
58 unsigned long long st_blocks;
59
60 unsigned long st_atime;
61 unsigned long st_atime_nsec;
62
63 unsigned long st_mtime;
64 unsigned int st_mtime_nsec;
65
66 unsigned long st_ctime;
67 unsigned long st_ctime_nsec;
68
69 unsigned long long st_ino;
70};
71
72/* We don't need to memset the whole thing just to initialize the padding */
73#define INIT_STRUCT_STAT64_PADDING(st) do { \
74 memset(&st.__pad0, 0, sizeof(st.__pad0)); \
75 memset(&st.__pad3, 0, sizeof(st.__pad3)); \
76} while (0)
77
78#else /* __i386__ */
79
80struct stat {
81 unsigned long st_dev;
82 unsigned long st_ino;
83 unsigned long st_nlink;
84
85 unsigned int st_mode;
86 unsigned int st_uid;
87 unsigned int st_gid;
88 unsigned int __pad0;
89 unsigned long st_rdev;
90 long st_size;
91 long st_blksize;
92 long st_blocks; /* Number 512-byte blocks allocated. */
93
94 unsigned long st_atime;
95 unsigned long st_atime_nsec;
96 unsigned long st_mtime;
97 unsigned long st_mtime_nsec;
98 unsigned long st_ctime;
99 unsigned long st_ctime_nsec;
100 long __unused[3];
101};
102
103/* We don't need to memset the whole thing just to initialize the padding */
104#define INIT_STRUCT_STAT_PADDING(st) do { \
105 st.__pad0 = 0; \
106 st.__unused[0] = 0; \
107 st.__unused[1] = 0; \
108 st.__unused[2] = 0; \
109} while (0)
110
111#endif
112
113/* for 32bit emulation and 32 bit kernels */
114struct __old_kernel_stat {
115 unsigned short st_dev;
116 unsigned short st_ino;
117 unsigned short st_mode;
118 unsigned short st_nlink;
119 unsigned short st_uid;
120 unsigned short st_gid;
121 unsigned short st_rdev;
122#ifdef __i386__
123 unsigned long st_size;
124 unsigned long st_atime;
125 unsigned long st_mtime;
126 unsigned long st_ctime;
127#else
128 unsigned int st_size;
129 unsigned int st_atime;
130 unsigned int st_mtime;
131 unsigned int st_ctime;
132#endif
133};
134
135#endif /* _ASM_X86_STAT_H */
diff --git a/arch/x86/include/uapi/asm/statfs.h b/arch/x86/include/uapi/asm/statfs.h
new file mode 100644
index 000000000000..2d0adbf99a8e
--- /dev/null
+++ b/arch/x86/include/uapi/asm/statfs.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_X86_STATFS_H
2#define _ASM_X86_STATFS_H
3
4/*
5 * We need compat_statfs64 to be packed, because the i386 ABI won't
6 * add padding at the end to bring it to a multiple of 8 bytes, but
7 * the x86_64 ABI will.
8 */
9#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
10
11#include <asm-generic/statfs.h>
12#endif /* _ASM_X86_STATFS_H */
diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h
new file mode 100644
index 000000000000..b5d7640abc5d
--- /dev/null
+++ b/arch/x86/include/uapi/asm/svm.h
@@ -0,0 +1,132 @@
1#ifndef _UAPI__SVM_H
2#define _UAPI__SVM_H
3
4#define SVM_EXIT_READ_CR0 0x000
5#define SVM_EXIT_READ_CR3 0x003
6#define SVM_EXIT_READ_CR4 0x004
7#define SVM_EXIT_READ_CR8 0x008
8#define SVM_EXIT_WRITE_CR0 0x010
9#define SVM_EXIT_WRITE_CR3 0x013
10#define SVM_EXIT_WRITE_CR4 0x014
11#define SVM_EXIT_WRITE_CR8 0x018
12#define SVM_EXIT_READ_DR0 0x020
13#define SVM_EXIT_READ_DR1 0x021
14#define SVM_EXIT_READ_DR2 0x022
15#define SVM_EXIT_READ_DR3 0x023
16#define SVM_EXIT_READ_DR4 0x024
17#define SVM_EXIT_READ_DR5 0x025
18#define SVM_EXIT_READ_DR6 0x026
19#define SVM_EXIT_READ_DR7 0x027
20#define SVM_EXIT_WRITE_DR0 0x030
21#define SVM_EXIT_WRITE_DR1 0x031
22#define SVM_EXIT_WRITE_DR2 0x032
23#define SVM_EXIT_WRITE_DR3 0x033
24#define SVM_EXIT_WRITE_DR4 0x034
25#define SVM_EXIT_WRITE_DR5 0x035
26#define SVM_EXIT_WRITE_DR6 0x036
27#define SVM_EXIT_WRITE_DR7 0x037
28#define SVM_EXIT_EXCP_BASE 0x040
29#define SVM_EXIT_INTR 0x060
30#define SVM_EXIT_NMI 0x061
31#define SVM_EXIT_SMI 0x062
32#define SVM_EXIT_INIT 0x063
33#define SVM_EXIT_VINTR 0x064
34#define SVM_EXIT_CR0_SEL_WRITE 0x065
35#define SVM_EXIT_IDTR_READ 0x066
36#define SVM_EXIT_GDTR_READ 0x067
37#define SVM_EXIT_LDTR_READ 0x068
38#define SVM_EXIT_TR_READ 0x069
39#define SVM_EXIT_IDTR_WRITE 0x06a
40#define SVM_EXIT_GDTR_WRITE 0x06b
41#define SVM_EXIT_LDTR_WRITE 0x06c
42#define SVM_EXIT_TR_WRITE 0x06d
43#define SVM_EXIT_RDTSC 0x06e
44#define SVM_EXIT_RDPMC 0x06f
45#define SVM_EXIT_PUSHF 0x070
46#define SVM_EXIT_POPF 0x071
47#define SVM_EXIT_CPUID 0x072
48#define SVM_EXIT_RSM 0x073
49#define SVM_EXIT_IRET 0x074
50#define SVM_EXIT_SWINT 0x075
51#define SVM_EXIT_INVD 0x076
52#define SVM_EXIT_PAUSE 0x077
53#define SVM_EXIT_HLT 0x078
54#define SVM_EXIT_INVLPG 0x079
55#define SVM_EXIT_INVLPGA 0x07a
56#define SVM_EXIT_IOIO 0x07b
57#define SVM_EXIT_MSR 0x07c
58#define SVM_EXIT_TASK_SWITCH 0x07d
59#define SVM_EXIT_FERR_FREEZE 0x07e
60#define SVM_EXIT_SHUTDOWN 0x07f
61#define SVM_EXIT_VMRUN 0x080
62#define SVM_EXIT_VMMCALL 0x081
63#define SVM_EXIT_VMLOAD 0x082
64#define SVM_EXIT_VMSAVE 0x083
65#define SVM_EXIT_STGI 0x084
66#define SVM_EXIT_CLGI 0x085
67#define SVM_EXIT_SKINIT 0x086
68#define SVM_EXIT_RDTSCP 0x087
69#define SVM_EXIT_ICEBP 0x088
70#define SVM_EXIT_WBINVD 0x089
71#define SVM_EXIT_MONITOR 0x08a
72#define SVM_EXIT_MWAIT 0x08b
73#define SVM_EXIT_MWAIT_COND 0x08c
74#define SVM_EXIT_XSETBV 0x08d
75#define SVM_EXIT_NPF 0x400
76
77#define SVM_EXIT_ERR -1
78
79#define SVM_EXIT_REASONS \
80 { SVM_EXIT_READ_CR0, "read_cr0" }, \
81 { SVM_EXIT_READ_CR3, "read_cr3" }, \
82 { SVM_EXIT_READ_CR4, "read_cr4" }, \
83 { SVM_EXIT_READ_CR8, "read_cr8" }, \
84 { SVM_EXIT_WRITE_CR0, "write_cr0" }, \
85 { SVM_EXIT_WRITE_CR3, "write_cr3" }, \
86 { SVM_EXIT_WRITE_CR4, "write_cr4" }, \
87 { SVM_EXIT_WRITE_CR8, "write_cr8" }, \
88 { SVM_EXIT_READ_DR0, "read_dr0" }, \
89 { SVM_EXIT_READ_DR1, "read_dr1" }, \
90 { SVM_EXIT_READ_DR2, "read_dr2" }, \
91 { SVM_EXIT_READ_DR3, "read_dr3" }, \
92 { SVM_EXIT_WRITE_DR0, "write_dr0" }, \
93 { SVM_EXIT_WRITE_DR1, "write_dr1" }, \
94 { SVM_EXIT_WRITE_DR2, "write_dr2" }, \
95 { SVM_EXIT_WRITE_DR3, "write_dr3" }, \
96 { SVM_EXIT_WRITE_DR5, "write_dr5" }, \
97 { SVM_EXIT_WRITE_DR7, "write_dr7" }, \
98 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, \
99 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, \
100 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, \
101 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, \
102 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, \
103 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, \
104 { SVM_EXIT_INTR, "interrupt" }, \
105 { SVM_EXIT_NMI, "nmi" }, \
106 { SVM_EXIT_SMI, "smi" }, \
107 { SVM_EXIT_INIT, "init" }, \
108 { SVM_EXIT_VINTR, "vintr" }, \
109 { SVM_EXIT_CPUID, "cpuid" }, \
110 { SVM_EXIT_INVD, "invd" }, \
111 { SVM_EXIT_HLT, "hlt" }, \
112 { SVM_EXIT_INVLPG, "invlpg" }, \
113 { SVM_EXIT_INVLPGA, "invlpga" }, \
114 { SVM_EXIT_IOIO, "io" }, \
115 { SVM_EXIT_MSR, "msr" }, \
116 { SVM_EXIT_TASK_SWITCH, "task_switch" }, \
117 { SVM_EXIT_SHUTDOWN, "shutdown" }, \
118 { SVM_EXIT_VMRUN, "vmrun" }, \
119 { SVM_EXIT_VMMCALL, "hypercall" }, \
120 { SVM_EXIT_VMLOAD, "vmload" }, \
121 { SVM_EXIT_VMSAVE, "vmsave" }, \
122 { SVM_EXIT_STGI, "stgi" }, \
123 { SVM_EXIT_CLGI, "clgi" }, \
124 { SVM_EXIT_SKINIT, "skinit" }, \
125 { SVM_EXIT_WBINVD, "wbinvd" }, \
126 { SVM_EXIT_MONITOR, "monitor" }, \
127 { SVM_EXIT_MWAIT, "mwait" }, \
128 { SVM_EXIT_XSETBV, "xsetbv" }, \
129 { SVM_EXIT_NPF, "npf" }
130
131
132#endif /* _UAPI__SVM_H */
diff --git a/arch/x86/include/uapi/asm/swab.h b/arch/x86/include/uapi/asm/swab.h
new file mode 100644
index 000000000000..7f235c7105c1
--- /dev/null
+++ b/arch/x86/include/uapi/asm/swab.h
@@ -0,0 +1,36 @@
1#ifndef _ASM_X86_SWAB_H
2#define _ASM_X86_SWAB_H
3
4#include <linux/types.h>
5#include <linux/compiler.h>
6
7static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
8{
9 asm("bswapl %0" : "=r" (val) : "0" (val));
10 return val;
11}
12#define __arch_swab32 __arch_swab32
13
14static inline __attribute_const__ __u64 __arch_swab64(__u64 val)
15{
16#ifdef __i386__
17 union {
18 struct {
19 __u32 a;
20 __u32 b;
21 } s;
22 __u64 u;
23 } v;
24 v.u = val;
25 asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1"
26 : "=r" (v.s.a), "=r" (v.s.b)
27 : "0" (v.s.a), "1" (v.s.b));
28 return v.u;
29#else /* __i386__ */
30 asm("bswapq %0" : "=r" (val) : "0" (val));
31 return val;
32#endif
33}
34#define __arch_swab64 __arch_swab64
35
36#endif /* _ASM_X86_SWAB_H */
diff --git a/arch/x86/include/uapi/asm/termbits.h b/arch/x86/include/uapi/asm/termbits.h
new file mode 100644
index 000000000000..3935b106de79
--- /dev/null
+++ b/arch/x86/include/uapi/asm/termbits.h
@@ -0,0 +1 @@
#include <asm-generic/termbits.h>
diff --git a/arch/x86/include/uapi/asm/termios.h b/arch/x86/include/uapi/asm/termios.h
new file mode 100644
index 000000000000..280d78a9d966
--- /dev/null
+++ b/arch/x86/include/uapi/asm/termios.h
@@ -0,0 +1 @@
#include <asm-generic/termios.h>
diff --git a/arch/x86/include/uapi/asm/types.h b/arch/x86/include/uapi/asm/types.h
new file mode 100644
index 000000000000..8e8c23fef08c
--- /dev/null
+++ b/arch/x86/include/uapi/asm/types.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_X86_TYPES_H
2#define _ASM_X86_TYPES_H
3
4#include <asm-generic/types.h>
5
6#endif /* _ASM_X86_TYPES_H */
diff --git a/arch/x86/include/uapi/asm/ucontext.h b/arch/x86/include/uapi/asm/ucontext.h
new file mode 100644
index 000000000000..b7c29c8017f2
--- /dev/null
+++ b/arch/x86/include/uapi/asm/ucontext.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_X86_UCONTEXT_H
2#define _ASM_X86_UCONTEXT_H
3
4#define UC_FP_XSTATE 0x1 /* indicates the presence of extended state
5 * information in the memory layout pointed
6 * by the fpstate pointer in the ucontext's
7 * sigcontext struct (uc_mcontext).
8 */
9
10#include <asm-generic/ucontext.h>
11
12#endif /* _ASM_X86_UCONTEXT_H */
diff --git a/arch/x86/include/uapi/asm/unistd.h b/arch/x86/include/uapi/asm/unistd.h
new file mode 100644
index 000000000000..a26df0d75cd0
--- /dev/null
+++ b/arch/x86/include/uapi/asm/unistd.h
@@ -0,0 +1,17 @@
1#ifndef _UAPI_ASM_X86_UNISTD_H
2#define _UAPI_ASM_X86_UNISTD_H
3
4/* x32 syscall flag bit */
5#define __X32_SYSCALL_BIT 0x40000000
6
7#ifndef __KERNEL__
8# ifdef __i386__
9# include <asm/unistd_32.h>
10# elif defined(__ILP32__)
11# include <asm/unistd_x32.h>
12# else
13# include <asm/unistd_64.h>
14# endif
15#endif
16
17#endif /* _UAPI_ASM_X86_UNISTD_H */
diff --git a/arch/x86/include/uapi/asm/vm86.h b/arch/x86/include/uapi/asm/vm86.h
new file mode 100644
index 000000000000..e0b243e9d859
--- /dev/null
+++ b/arch/x86/include/uapi/asm/vm86.h
@@ -0,0 +1,129 @@
1#ifndef _UAPI_ASM_X86_VM86_H
2#define _UAPI_ASM_X86_VM86_H
3
4/*
5 * I'm guessing at the VIF/VIP flag usage, but hope that this is how
6 * the Pentium uses them. Linux will return from vm86 mode when both
7 * VIF and VIP is set.
8 *
9 * On a Pentium, we could probably optimize the virtual flags directly
10 * in the eflags register instead of doing it "by hand" in vflags...
11 *
12 * Linus
13 */
14
15#include <asm/processor-flags.h>
16
17#define BIOSSEG 0x0f000
18
19#define CPU_086 0
20#define CPU_186 1
21#define CPU_286 2
22#define CPU_386 3
23#define CPU_486 4
24#define CPU_586 5
25
26/*
27 * Return values for the 'vm86()' system call
28 */
29#define VM86_TYPE(retval) ((retval) & 0xff)
30#define VM86_ARG(retval) ((retval) >> 8)
31
32#define VM86_SIGNAL 0 /* return due to signal */
33#define VM86_UNKNOWN 1 /* unhandled GP fault
34 - IO-instruction or similar */
35#define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
36#define VM86_STI 3 /* sti/popf/iret instruction enabled
37 virtual interrupts */
38
39/*
40 * Additional return values when invoking new vm86()
41 */
42#define VM86_PICRETURN 4 /* return due to pending PIC request */
43#define VM86_TRAP 6 /* return due to DOS-debugger request */
44
45/*
46 * function codes when invoking new vm86()
47 */
48#define VM86_PLUS_INSTALL_CHECK 0
49#define VM86_ENTER 1
50#define VM86_ENTER_NO_BYPASS 2
51#define VM86_REQUEST_IRQ 3
52#define VM86_FREE_IRQ 4
53#define VM86_GET_IRQ_BITS 5
54#define VM86_GET_AND_RESET_IRQ 6
55
56/*
57 * This is the stack-layout seen by the user space program when we have
58 * done a translation of "SAVE_ALL" from vm86 mode. The real kernel layout
59 * is 'kernel_vm86_regs' (see below).
60 */
61
62struct vm86_regs {
63/*
64 * normal regs, with special meaning for the segment descriptors..
65 */
66 long ebx;
67 long ecx;
68 long edx;
69 long esi;
70 long edi;
71 long ebp;
72 long eax;
73 long __null_ds;
74 long __null_es;
75 long __null_fs;
76 long __null_gs;
77 long orig_eax;
78 long eip;
79 unsigned short cs, __csh;
80 long eflags;
81 long esp;
82 unsigned short ss, __ssh;
83/*
84 * these are specific to v86 mode:
85 */
86 unsigned short es, __esh;
87 unsigned short ds, __dsh;
88 unsigned short fs, __fsh;
89 unsigned short gs, __gsh;
90};
91
92struct revectored_struct {
93 unsigned long __map[8]; /* 256 bits */
94};
95
96struct vm86_struct {
97 struct vm86_regs regs;
98 unsigned long flags;
99 unsigned long screen_bitmap;
100 unsigned long cpu_type;
101 struct revectored_struct int_revectored;
102 struct revectored_struct int21_revectored;
103};
104
105/*
106 * flags masks
107 */
108#define VM86_SCREEN_BITMAP 0x0001
109
110struct vm86plus_info_struct {
111 unsigned long force_return_for_pic:1;
112 unsigned long vm86dbg_active:1; /* for debugger */
113 unsigned long vm86dbg_TFpendig:1; /* for debugger */
114 unsigned long unused:28;
115 unsigned long is_vm86pus:1; /* for vm86 internal use */
116 unsigned char vm86dbg_intxxtab[32]; /* for debugger */
117};
118struct vm86plus_struct {
119 struct vm86_regs regs;
120 unsigned long flags;
121 unsigned long screen_bitmap;
122 unsigned long cpu_type;
123 struct revectored_struct int_revectored;
124 struct revectored_struct int21_revectored;
125 struct vm86plus_info_struct vm86plus;
126};
127
128
129#endif /* _UAPI_ASM_X86_VM86_H */
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/include/uapi/asm/vmx.h
new file mode 100644
index 000000000000..979d03bce135
--- /dev/null
+++ b/arch/x86/include/uapi/asm/vmx.h
@@ -0,0 +1,109 @@
1/*
2 * vmx.h: VMX Architecture related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 * A few random additions are:
19 * Copyright (C) 2006 Qumranet
20 * Avi Kivity <avi@qumranet.com>
21 * Yaniv Kamay <yaniv@qumranet.com>
22 *
23 */
24#ifndef _UAPIVMX_H
25#define _UAPIVMX_H
26
27
28#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
29
30#define EXIT_REASON_EXCEPTION_NMI 0
31#define EXIT_REASON_EXTERNAL_INTERRUPT 1
32#define EXIT_REASON_TRIPLE_FAULT 2
33
34#define EXIT_REASON_PENDING_INTERRUPT 7
35#define EXIT_REASON_NMI_WINDOW 8
36#define EXIT_REASON_TASK_SWITCH 9
37#define EXIT_REASON_CPUID 10
38#define EXIT_REASON_HLT 12
39#define EXIT_REASON_INVD 13
40#define EXIT_REASON_INVLPG 14
41#define EXIT_REASON_RDPMC 15
42#define EXIT_REASON_RDTSC 16
43#define EXIT_REASON_VMCALL 18
44#define EXIT_REASON_VMCLEAR 19
45#define EXIT_REASON_VMLAUNCH 20
46#define EXIT_REASON_VMPTRLD 21
47#define EXIT_REASON_VMPTRST 22
48#define EXIT_REASON_VMREAD 23
49#define EXIT_REASON_VMRESUME 24
50#define EXIT_REASON_VMWRITE 25
51#define EXIT_REASON_VMOFF 26
52#define EXIT_REASON_VMON 27
53#define EXIT_REASON_CR_ACCESS 28
54#define EXIT_REASON_DR_ACCESS 29
55#define EXIT_REASON_IO_INSTRUCTION 30
56#define EXIT_REASON_MSR_READ 31
57#define EXIT_REASON_MSR_WRITE 32
58#define EXIT_REASON_INVALID_STATE 33
59#define EXIT_REASON_MWAIT_INSTRUCTION 36
60#define EXIT_REASON_MONITOR_INSTRUCTION 39
61#define EXIT_REASON_PAUSE_INSTRUCTION 40
62#define EXIT_REASON_MCE_DURING_VMENTRY 41
63#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
64#define EXIT_REASON_APIC_ACCESS 44
65#define EXIT_REASON_EPT_VIOLATION 48
66#define EXIT_REASON_EPT_MISCONFIG 49
67#define EXIT_REASON_WBINVD 54
68#define EXIT_REASON_XSETBV 55
69#define EXIT_REASON_INVPCID 58
70
71#define VMX_EXIT_REASONS \
72 { EXIT_REASON_EXCEPTION_NMI, "EXCEPTION_NMI" }, \
73 { EXIT_REASON_EXTERNAL_INTERRUPT, "EXTERNAL_INTERRUPT" }, \
74 { EXIT_REASON_TRIPLE_FAULT, "TRIPLE_FAULT" }, \
75 { EXIT_REASON_PENDING_INTERRUPT, "PENDING_INTERRUPT" }, \
76 { EXIT_REASON_NMI_WINDOW, "NMI_WINDOW" }, \
77 { EXIT_REASON_TASK_SWITCH, "TASK_SWITCH" }, \
78 { EXIT_REASON_CPUID, "CPUID" }, \
79 { EXIT_REASON_HLT, "HLT" }, \
80 { EXIT_REASON_INVLPG, "INVLPG" }, \
81 { EXIT_REASON_RDPMC, "RDPMC" }, \
82 { EXIT_REASON_RDTSC, "RDTSC" }, \
83 { EXIT_REASON_VMCALL, "VMCALL" }, \
84 { EXIT_REASON_VMCLEAR, "VMCLEAR" }, \
85 { EXIT_REASON_VMLAUNCH, "VMLAUNCH" }, \
86 { EXIT_REASON_VMPTRLD, "VMPTRLD" }, \
87 { EXIT_REASON_VMPTRST, "VMPTRST" }, \
88 { EXIT_REASON_VMREAD, "VMREAD" }, \
89 { EXIT_REASON_VMRESUME, "VMRESUME" }, \
90 { EXIT_REASON_VMWRITE, "VMWRITE" }, \
91 { EXIT_REASON_VMOFF, "VMOFF" }, \
92 { EXIT_REASON_VMON, "VMON" }, \
93 { EXIT_REASON_CR_ACCESS, "CR_ACCESS" }, \
94 { EXIT_REASON_DR_ACCESS, "DR_ACCESS" }, \
95 { EXIT_REASON_IO_INSTRUCTION, "IO_INSTRUCTION" }, \
96 { EXIT_REASON_MSR_READ, "MSR_READ" }, \
97 { EXIT_REASON_MSR_WRITE, "MSR_WRITE" }, \
98 { EXIT_REASON_MWAIT_INSTRUCTION, "MWAIT_INSTRUCTION" }, \
99 { EXIT_REASON_MONITOR_INSTRUCTION, "MONITOR_INSTRUCTION" }, \
100 { EXIT_REASON_PAUSE_INSTRUCTION, "PAUSE_INSTRUCTION" }, \
101 { EXIT_REASON_MCE_DURING_VMENTRY, "MCE_DURING_VMENTRY" }, \
102 { EXIT_REASON_TPR_BELOW_THRESHOLD, "TPR_BELOW_THRESHOLD" }, \
103 { EXIT_REASON_APIC_ACCESS, "APIC_ACCESS" }, \
104 { EXIT_REASON_EPT_VIOLATION, "EPT_VIOLATION" }, \
105 { EXIT_REASON_EPT_MISCONFIG, "EPT_MISCONFIG" }, \
106 { EXIT_REASON_WBINVD, "WBINVD" }
107
108
109#endif /* _UAPIVMX_H */
diff --git a/arch/x86/include/uapi/asm/vsyscall.h b/arch/x86/include/uapi/asm/vsyscall.h
new file mode 100644
index 000000000000..85dc1b3825ab
--- /dev/null
+++ b/arch/x86/include/uapi/asm/vsyscall.h
@@ -0,0 +1,17 @@
1#ifndef _UAPI_ASM_X86_VSYSCALL_H
2#define _UAPI_ASM_X86_VSYSCALL_H
3
4enum vsyscall_num {
5 __NR_vgettimeofday,
6 __NR_vtime,
7 __NR_vgetcpu,
8};
9
10#define VSYSCALL_START (-10UL << 20)
11#define VSYSCALL_SIZE 1024
12#define VSYSCALL_END (-2UL << 20)
13#define VSYSCALL_MAPPED_PAGES 1
14#define VSYSCALL_ADDR(vsyscall_nr) (VSYSCALL_START+VSYSCALL_SIZE*(vsyscall_nr))
15
16
17#endif /* _UAPI_ASM_X86_VSYSCALL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 11:20:21 -0400