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-rw-r--r--arch/tile/Kconfig123
-rw-r--r--arch/tile/Kconfig.debug11
-rw-r--r--arch/tile/Makefile19
-rw-r--r--arch/tile/configs/tile_defconfig71
-rw-r--r--arch/tile/configs/tilegx_defconfig1833
-rw-r--r--arch/tile/configs/tilepro_defconfig1163
-rw-r--r--arch/tile/include/arch/chip_tilegx.h258
-rw-r--r--arch/tile/include/arch/icache.h11
-rw-r--r--arch/tile/include/arch/interrupts_32.h9
-rw-r--r--arch/tile/include/arch/interrupts_64.h276
-rw-r--r--arch/tile/include/arch/sim.h643
-rw-r--r--arch/tile/include/arch/sim_def.h551
-rw-r--r--arch/tile/include/arch/spr_def.h94
-rw-r--r--arch/tile/include/arch/spr_def_32.h39
-rw-r--r--arch/tile/include/arch/spr_def_64.h173
-rw-r--r--arch/tile/include/asm/Kbuild1
-rw-r--r--arch/tile/include/asm/atomic.h51
-rw-r--r--arch/tile/include/asm/atomic_32.h10
-rw-r--r--arch/tile/include/asm/atomic_64.h156
-rw-r--r--arch/tile/include/asm/backtrace.h81
-rw-r--r--arch/tile/include/asm/bitops.h5
-rw-r--r--arch/tile/include/asm/bitops_32.h3
-rw-r--r--arch/tile/include/asm/bitops_64.h105
-rw-r--r--arch/tile/include/asm/cache.h2
-rw-r--r--arch/tile/include/asm/cacheflush.h27
-rw-r--r--arch/tile/include/asm/compat.h17
-rw-r--r--arch/tile/include/asm/dma-mapping.h3
-rw-r--r--arch/tile/include/asm/edac.h29
-rw-r--r--arch/tile/include/asm/fb.h1
-rw-r--r--arch/tile/include/asm/futex.h27
-rw-r--r--arch/tile/include/asm/hardwall.h15
-rw-r--r--arch/tile/include/asm/highmem.h11
-rw-r--r--arch/tile/include/asm/hugetlb.h2
-rw-r--r--arch/tile/include/asm/io.h33
-rw-r--r--arch/tile/include/asm/irq.h2
-rw-r--r--arch/tile/include/asm/irqflags.h118
-rw-r--r--arch/tile/include/asm/kmap_types.h34
-rw-r--r--arch/tile/include/asm/mman.h1
-rw-r--r--arch/tile/include/asm/mmu_context.h4
-rw-r--r--arch/tile/include/asm/mmzone.h11
-rw-r--r--arch/tile/include/asm/opcode-tile_32.h7
-rw-r--r--arch/tile/include/asm/opcode-tile_64.h1500
-rw-r--r--arch/tile/include/asm/opcode_constants_64.h1043
-rw-r--r--arch/tile/include/asm/page.h71
-rw-r--r--arch/tile/include/asm/parport.h1
-rw-r--r--arch/tile/include/asm/pci-bridge.h117
-rw-r--r--arch/tile/include/asm/pci.h110
-rw-r--r--arch/tile/include/asm/pgalloc.h7
-rw-r--r--arch/tile/include/asm/pgtable.h42
-rw-r--r--arch/tile/include/asm/pgtable_32.h8
-rw-r--r--arch/tile/include/asm/pgtable_64.h175
-rw-r--r--arch/tile/include/asm/processor.h31
-rw-r--r--arch/tile/include/asm/ptrace.h7
-rw-r--r--arch/tile/include/asm/serial.h1
-rw-r--r--arch/tile/include/asm/signal.h6
-rw-r--r--arch/tile/include/asm/spinlock_32.h83
-rw-r--r--arch/tile/include/asm/spinlock_64.h161
-rw-r--r--arch/tile/include/asm/stack.h3
-rw-r--r--arch/tile/include/asm/stat.h3
-rw-r--r--arch/tile/include/asm/swab.h6
-rw-r--r--arch/tile/include/asm/syscalls.h73
-rw-r--r--arch/tile/include/asm/system.h31
-rw-r--r--arch/tile/include/asm/thread_info.h8
-rw-r--r--arch/tile/include/asm/timex.h3
-rw-r--r--arch/tile/include/asm/topology.h75
-rw-r--r--arch/tile/include/asm/traps.h8
-rw-r--r--arch/tile/include/asm/unistd.h3
-rw-r--r--arch/tile/include/asm/vga.h (renamed from arch/tile/lib/mb_incoherent.S)35
-rw-r--r--arch/tile/include/hv/drv_mshim_intf.h50
-rw-r--r--arch/tile/include/hv/drv_xgbe_impl.h300
-rw-r--r--arch/tile/include/hv/drv_xgbe_intf.h615
-rw-r--r--arch/tile/include/hv/hypervisor.h90
-rw-r--r--arch/tile/include/hv/netio_errors.h122
-rw-r--r--arch/tile/include/hv/netio_intf.h2975
-rw-r--r--arch/tile/include/hv/pagesize.h32
-rw-r--r--arch/tile/kernel/Makefile3
-rw-r--r--arch/tile/kernel/backtrace.c99
-rw-r--r--arch/tile/kernel/compat.c18
-rw-r--r--arch/tile/kernel/compat_signal.c21
-rw-r--r--arch/tile/kernel/early_printk.c2
-rw-r--r--arch/tile/kernel/entry.S50
-rw-r--r--arch/tile/kernel/futex_64.S55
-rw-r--r--arch/tile/kernel/hardwall.c101
-rw-r--r--arch/tile/kernel/head_32.S20
-rw-r--r--arch/tile/kernel/head_64.S269
-rw-r--r--arch/tile/kernel/intvec_32.S360
-rw-r--r--arch/tile/kernel/intvec_64.S1231
-rw-r--r--arch/tile/kernel/irq.c91
-rw-r--r--arch/tile/kernel/machine_kexec.c13
-rw-r--r--arch/tile/kernel/messaging.c2
-rw-r--r--arch/tile/kernel/module.c8
-rw-r--r--arch/tile/kernel/pci-dma.c40
-rw-r--r--arch/tile/kernel/pci.c647
-rw-r--r--arch/tile/kernel/proc.c73
-rw-r--r--arch/tile/kernel/process.c110
-rw-r--r--arch/tile/kernel/ptrace.c108
-rw-r--r--arch/tile/kernel/reboot.c6
-rw-r--r--arch/tile/kernel/regs_32.S2
-rw-r--r--arch/tile/kernel/regs_64.S145
-rw-r--r--arch/tile/kernel/setup.c70
-rw-r--r--arch/tile/kernel/signal.c154
-rw-r--r--arch/tile/kernel/single_step.c106
-rw-r--r--arch/tile/kernel/smp.c43
-rw-r--r--arch/tile/kernel/smpboot.c1
-rw-r--r--arch/tile/kernel/stack.c75
-rw-r--r--arch/tile/kernel/sys.c19
-rw-r--r--arch/tile/kernel/sysfs.c185
-rw-r--r--arch/tile/kernel/tile-desc_32.c11
-rw-r--r--arch/tile/kernel/tile-desc_64.c2200
-rw-r--r--arch/tile/kernel/time.c20
-rw-r--r--arch/tile/kernel/tlb.c12
-rw-r--r--arch/tile/kernel/traps.c5
-rw-r--r--arch/tile/kernel/vmlinux.lds.S7
-rw-r--r--arch/tile/kvm/Kconfig38
-rw-r--r--arch/tile/lib/Makefile5
-rw-r--r--arch/tile/lib/atomic_32.c25
-rw-r--r--arch/tile/lib/atomic_asm_32.S4
-rw-r--r--arch/tile/lib/cacheflush.c120
-rw-r--r--arch/tile/lib/delay.c21
-rw-r--r--arch/tile/lib/exports.c7
-rw-r--r--arch/tile/lib/memchr_32.c35
-rw-r--r--arch/tile/lib/memchr_64.c71
-rw-r--r--arch/tile/lib/memcpy_32.S206
-rw-r--r--arch/tile/lib/memcpy_64.c220
-rw-r--r--arch/tile/lib/memcpy_tile64.c15
-rw-r--r--arch/tile/lib/memcpy_user_64.c86
-rw-r--r--arch/tile/lib/memmove.c (renamed from arch/tile/lib/memmove_32.c)0
-rw-r--r--arch/tile/lib/memset_32.c1
-rw-r--r--arch/tile/lib/memset_64.c145
-rw-r--r--arch/tile/lib/spinlock_32.c190
-rw-r--r--arch/tile/lib/spinlock_64.c104
-rw-r--r--arch/tile/lib/strchr_64.c67
-rw-r--r--arch/tile/lib/strlen_32.c2
-rw-r--r--arch/tile/lib/strlen_64.c38
-rw-r--r--arch/tile/lib/usercopy_64.S196
-rw-r--r--arch/tile/mm/fault.c53
-rw-r--r--arch/tile/mm/highmem.c88
-rw-r--r--arch/tile/mm/homecache.c49
-rw-r--r--arch/tile/mm/hugetlbpage.c3
-rw-r--r--arch/tile/mm/init.c44
-rw-r--r--arch/tile/mm/migrate_32.S1
-rw-r--r--arch/tile/mm/migrate_64.S187
-rw-r--r--arch/tile/mm/pgtable.c187
143 files changed, 18879 insertions, 3536 deletions
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 1eb308cb711a..0249b8b4db54 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -1,24 +1,34 @@
1# For a description of the syntax of this configuration file, 1# For a description of the syntax of this configuration file,
2# see Documentation/kbuild/config-language.txt. 2# see Documentation/kbuild/kconfig-language.txt.
3 3
4config MMU 4config TILE
5 def_bool y
6
7config GENERIC_CSUM
8 def_bool y
9
10config GENERIC_HARDIRQS
11 def_bool y 5 def_bool y
6 select HAVE_KVM if !TILEGX
7 select GENERIC_FIND_FIRST_BIT
8 select USE_GENERIC_SMP_HELPERS
9 select CC_OPTIMIZE_FOR_SIZE
10 select HAVE_GENERIC_HARDIRQS
11 select GENERIC_IRQ_PROBE
12 select GENERIC_PENDING_IRQ if SMP
13 select GENERIC_IRQ_SHOW
14 select SYS_HYPERVISOR
12 15
13config GENERIC_HARDIRQS_NO__DO_IRQ 16# FIXME: investigate whether we need/want these options.
14 def_bool y 17# select HAVE_IOREMAP_PROT
18# select HAVE_OPTPROBES
19# select HAVE_REGS_AND_STACK_ACCESS_API
20# select HAVE_HW_BREAKPOINT
21# select PERF_EVENTS
22# select HAVE_USER_RETURN_NOTIFIER
23# config NO_BOOTMEM
24# config ARCH_SUPPORTS_DEBUG_PAGEALLOC
25# config HUGETLB_PAGE_SIZE_VARIABLE
15 26
16config GENERIC_IRQ_PROBE 27config MMU
17 def_bool y 28 def_bool y
18 29
19config GENERIC_PENDING_IRQ 30config GENERIC_CSUM
20 def_bool y 31 def_bool y
21 depends on GENERIC_HARDIRQS && SMP
22 32
23config SEMAPHORE_SLEEPERS 33config SEMAPHORE_SLEEPERS
24 def_bool y 34 def_bool y
@@ -30,7 +40,7 @@ config HAVE_SETUP_PER_CPU_AREA
30 def_bool y 40 def_bool y
31 41
32config NEED_PER_CPU_PAGE_FIRST_CHUNK 42config NEED_PER_CPU_PAGE_FIRST_CHUNK
33 def_bool y 43 def_bool y
34 44
35config SYS_SUPPORTS_HUGETLBFS 45config SYS_SUPPORTS_HUGETLBFS
36 def_bool y 46 def_bool y
@@ -41,7 +51,7 @@ config GENERIC_TIME
41config GENERIC_CLOCKEVENTS 51config GENERIC_CLOCKEVENTS
42 def_bool y 52 def_bool y
43 53
44# FIXME: tilegx can implement a more efficent rwsem. 54# FIXME: tilegx can implement a more efficient rwsem.
45config RWSEM_GENERIC_SPINLOCK 55config RWSEM_GENERIC_SPINLOCK
46 def_bool y 56 def_bool y
47 57
@@ -58,6 +68,9 @@ config ARCH_SUPPORTS_OPTIMIZED_INLINING
58config ARCH_PHYS_ADDR_T_64BIT 68config ARCH_PHYS_ADDR_T_64BIT
59 def_bool y 69 def_bool y
60 70
71config ARCH_DMA_ADDR_T_64BIT
72 def_bool y
73
61config LOCKDEP_SUPPORT 74config LOCKDEP_SUPPORT
62 def_bool y 75 def_bool y
63 76
@@ -94,27 +107,6 @@ config HVC_TILE
94 select HVC_DRIVER 107 select HVC_DRIVER
95 def_bool y 108 def_bool y
96 109
97config TILE
98 def_bool y
99 select GENERIC_FIND_FIRST_BIT
100 select GENERIC_FIND_NEXT_BIT
101 select USE_GENERIC_SMP_HELPERS
102 select CC_OPTIMIZE_FOR_SIZE
103
104# FIXME: investigate whether we need/want these options.
105# select HAVE_IOREMAP_PROT
106# select HAVE_OPTPROBES
107# select HAVE_REGS_AND_STACK_ACCESS_API
108# select HAVE_HW_BREAKPOINT
109# select PERF_EVENTS
110# select HAVE_USER_RETURN_NOTIFIER
111# config NO_BOOTMEM
112# config ARCH_SUPPORTS_DEBUG_PAGEALLOC
113# config HUGETLB_PAGE_SIZE_VARIABLE
114
115
116mainmenu "Linux/TILE Kernel Configuration"
117
118# Please note: TILE-Gx support is not yet finalized; this is 110# Please note: TILE-Gx support is not yet finalized; this is
119# the preliminary support. TILE-Gx drivers are only provided 111# the preliminary support. TILE-Gx drivers are only provided
120# with the alpha or beta test versions for Tilera customers. 112# with the alpha or beta test versions for Tilera customers.
@@ -210,15 +202,9 @@ config NODES_SHIFT
210 By default, 2, i.e. 2^2 == 4 DDR2 controllers. 202 By default, 2, i.e. 2^2 == 4 DDR2 controllers.
211 In a system with more controllers, this value should be raised. 203 In a system with more controllers, this value should be raised.
212 204
213# Need 16MB areas to enable hugetlb
214# See build-time check in arch/tile/mm/init.c.
215config FORCE_MAX_ZONEORDER
216 int
217 default 9
218
219choice 205choice
220 depends on !TILEGX 206 depends on !TILEGX
221 prompt "Memory split" if EMBEDDED 207 prompt "Memory split" if EXPERT
222 default VMSPLIT_3G 208 default VMSPLIT_3G
223 ---help--- 209 ---help---
224 Select the desired split between kernel and user memory. 210 Select the desired split between kernel and user memory.
@@ -236,14 +222,18 @@ choice
236 If you are not absolutely sure what you are doing, leave this 222 If you are not absolutely sure what you are doing, leave this
237 option alone! 223 option alone!
238 224
239 config VMSPLIT_375G 225 config VMSPLIT_3_75G
240 bool "3.75G/0.25G user/kernel split (no kernel networking)" 226 bool "3.75G/0.25G user/kernel split (no kernel networking)"
241 config VMSPLIT_35G 227 config VMSPLIT_3_5G
242 bool "3.5G/0.5G user/kernel split" 228 bool "3.5G/0.5G user/kernel split"
243 config VMSPLIT_3G 229 config VMSPLIT_3G
244 bool "3G/1G user/kernel split" 230 bool "3G/1G user/kernel split"
245 config VMSPLIT_3G_OPT 231 config VMSPLIT_2_75G
246 bool "3G/1G user/kernel split (for full 1G low memory)" 232 bool "2.75G/1.25G user/kernel split (for full 1G low memory)"
233 config VMSPLIT_2_5G
234 bool "2.5G/1.5G user/kernel split"
235 config VMSPLIT_2_25G
236 bool "2.25G/1.75G user/kernel split"
247 config VMSPLIT_2G 237 config VMSPLIT_2G
248 bool "2G/2G user/kernel split" 238 bool "2G/2G user/kernel split"
249 config VMSPLIT_1G 239 config VMSPLIT_1G
@@ -252,9 +242,11 @@ endchoice
252 242
253config PAGE_OFFSET 243config PAGE_OFFSET
254 hex 244 hex
255 default 0xF0000000 if VMSPLIT_375G 245 default 0xF0000000 if VMSPLIT_3_75G
256 default 0xE0000000 if VMSPLIT_35G 246 default 0xE0000000 if VMSPLIT_3_5G
257 default 0xB0000000 if VMSPLIT_3G_OPT 247 default 0xB0000000 if VMSPLIT_2_75G
248 default 0xA0000000 if VMSPLIT_2_5G
249 default 0x90000000 if VMSPLIT_2_25G
258 default 0x80000000 if VMSPLIT_2G 250 default 0x80000000 if VMSPLIT_2G
259 default 0x40000000 if VMSPLIT_1G 251 default 0x40000000 if VMSPLIT_1G
260 default 0xC0000000 252 default 0xC0000000
@@ -314,10 +306,31 @@ config HARDWALL
314 bool "Hardwall support to allow access to user dynamic network" 306 bool "Hardwall support to allow access to user dynamic network"
315 default y 307 default y
316 308
309config KERNEL_PL
310 int "Processor protection level for kernel"
311 range 1 2
312 default "1"
313 ---help---
314 This setting determines the processor protection level the
315 kernel will be built to run at. Generally you should use
316 the default value here.
317
317endmenu # Tilera-specific configuration 318endmenu # Tilera-specific configuration
318 319
319menu "Bus options" 320menu "Bus options"
320 321
322config PCI
323 bool "PCI support"
324 default y
325 select PCI_DOMAINS
326 ---help---
327 Enable PCI root complex support, so PCIe endpoint devices can
328 be attached to the Tile chip. Many, but not all, PCI devices
329 are supported under Tilera's root complex driver.
330
331config PCI_DOMAINS
332 bool
333
321config NO_IOMEM 334config NO_IOMEM
322 def_bool !PCI 335 def_bool !PCI
323 336
@@ -326,6 +339,14 @@ config NO_IOPORT
326 339
327source "drivers/pci/Kconfig" 340source "drivers/pci/Kconfig"
328 341
342config HOTPLUG
343 bool "Support for hot-pluggable devices"
344 ---help---
345 Say Y here if you want to plug devices into your computer while
346 the system is running, and be able to use them quickly. In many
347 cases, the devices can likewise be unplugged at any time too.
348 One well-known example of this is USB.
349
329source "drivers/pci/hotplug/Kconfig" 350source "drivers/pci/hotplug/Kconfig"
330 351
331endmenu 352endmenu
@@ -354,3 +375,5 @@ source "security/Kconfig"
354source "crypto/Kconfig" 375source "crypto/Kconfig"
355 376
356source "lib/Kconfig" 377source "lib/Kconfig"
378
379source "arch/tile/kvm/Kconfig"
diff --git a/arch/tile/Kconfig.debug b/arch/tile/Kconfig.debug
index a81f0fbf7e60..ddbfc3322d7f 100644
--- a/arch/tile/Kconfig.debug
+++ b/arch/tile/Kconfig.debug
@@ -3,7 +3,7 @@ menu "Kernel hacking"
3source "lib/Kconfig.debug" 3source "lib/Kconfig.debug"
4 4
5config EARLY_PRINTK 5config EARLY_PRINTK
6 bool "Early printk" if EMBEDDED && DEBUG_KERNEL 6 bool "Early printk" if EXPERT && DEBUG_KERNEL
7 default y 7 default y
8 help 8 help
9 Write kernel log output directly via the hypervisor console. 9 Write kernel log output directly via the hypervisor console.
@@ -21,15 +21,6 @@ config DEBUG_STACKOVERFLOW
21 This option will cause messages to be printed if free stack space 21 This option will cause messages to be printed if free stack space
22 drops below a certain limit. 22 drops below a certain limit.
23 23
24config DEBUG_STACK_USAGE
25 bool "Stack utilization instrumentation"
26 depends on DEBUG_KERNEL
27 help
28 Enables the display of the minimum amount of free stack which each
29 task has ever had available in the sysrq-T and sysrq-P debug output.
30
31 This option will slow down process creation somewhat.
32
33config DEBUG_EXTRA_FLAGS 24config DEBUG_EXTRA_FLAGS
34 string "Additional compiler arguments when building with '-g'" 25 string "Additional compiler arguments when building with '-g'"
35 depends on DEBUG_INFO 26 depends on DEBUG_INFO
diff --git a/arch/tile/Makefile b/arch/tile/Makefile
index fd8f6bb5face..17acce70569b 100644
--- a/arch/tile/Makefile
+++ b/arch/tile/Makefile
@@ -26,8 +26,9 @@ $(error Set TILERA_ROOT or CROSS_COMPILE when building $(ARCH) on $(HOST_ARCH))
26 endif 26 endif
27endif 27endif
28 28
29 29ifneq ($(CONFIG_DEBUG_EXTRA_FLAGS),"")
30KBUILD_CFLAGS += $(CONFIG_DEBUG_EXTRA_FLAGS) 30KBUILD_CFLAGS += $(CONFIG_DEBUG_EXTRA_FLAGS)
31endif
31 32
32LIBGCC_PATH := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) 33LIBGCC_PATH := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
33 34
@@ -49,6 +50,20 @@ head-y := arch/tile/kernel/head_$(BITS).o
49libs-y += arch/tile/lib/ 50libs-y += arch/tile/lib/
50libs-y += $(LIBGCC_PATH) 51libs-y += $(LIBGCC_PATH)
51 52
52
53# See arch/tile/Kbuild for content of core part of the kernel 53# See arch/tile/Kbuild for content of core part of the kernel
54core-y += arch/tile/ 54core-y += arch/tile/
55
56core-$(CONFIG_KVM) += arch/tile/kvm/
57
58ifdef TILERA_ROOT
59INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot
60endif
61
62install:
63 install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
64 install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
65 install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
66
67define archhelp
68 echo ' install - install kernel into $(INSTALL_PATH)'
69endef
diff --git a/arch/tile/configs/tile_defconfig b/arch/tile/configs/tile_defconfig
deleted file mode 100644
index 919c54afd981..000000000000
--- a/arch/tile/configs/tile_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
6CONFIG_EMBEDDED=y
7# CONFIG_COMPAT_BRK is not set
8CONFIG_PROFILING=y
9CONFIG_MODULES=y
10CONFIG_MODULE_UNLOAD=y
11# CONFIG_BLK_DEV_BSG is not set
12# CONFIG_IOSCHED_DEADLINE is not set
13# CONFIG_IOSCHED_CFQ is not set
14CONFIG_NO_HZ=y
15CONFIG_HIGH_RES_TIMERS=y
16CONFIG_HZ_100=y
17CONFIG_NET=y
18CONFIG_PACKET=y
19CONFIG_UNIX=y
20CONFIG_INET=y
21CONFIG_IP_MULTICAST=y
22# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
23# CONFIG_INET_XFRM_MODE_TUNNEL is not set
24# CONFIG_INET_LRO is not set
25# CONFIG_INET_DIAG is not set
26CONFIG_IPV6=y
27# CONFIG_WIRELESS is not set
28CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
29CONFIG_SCSI=y
30CONFIG_BLK_DEV_SD=y
31CONFIG_SCSI_CONSTANTS=y
32CONFIG_SCSI_LOGGING=y
33CONFIG_NETDEVICES=y
34CONFIG_TUN=y
35# CONFIG_NETDEV_10000 is not set
36# CONFIG_WLAN is not set
37# CONFIG_INPUT_MOUSEDEV is not set
38# CONFIG_INPUT_KEYBOARD is not set
39# CONFIG_INPUT_MOUSE is not set
40# CONFIG_SERIO is not set
41# CONFIG_VT is not set
42# CONFIG_LEGACY_PTYS is not set
43# CONFIG_HW_RANDOM is not set
44CONFIG_WATCHDOG=y
45CONFIG_WATCHDOG_NOWAYOUT=y
46# CONFIG_HID_SUPPORT is not set
47CONFIG_RTC_CLASS=y
48# CONFIG_RTC_INTF_SYSFS is not set
49# CONFIG_RTC_INTF_PROC is not set
50CONFIG_EXT2_FS=y
51CONFIG_EXT3_FS=y
52# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
53CONFIG_FUSE_FS=y
54CONFIG_MSDOS_FS=y
55CONFIG_VFAT_FS=m
56CONFIG_TMPFS=y
57CONFIG_HUGETLBFS=y
58CONFIG_NFS_FS=m
59CONFIG_NFS_V3=y
60CONFIG_NLS_CODEPAGE_437=y
61CONFIG_NLS_ISO8859_1=y
62CONFIG_FRAME_WARN=2048
63CONFIG_MAGIC_SYSRQ=y
64CONFIG_DEBUG_KERNEL=y
65CONFIG_DETECT_HUNG_TASK=y
66CONFIG_DEBUG_SPINLOCK_SLEEP=y
67CONFIG_DEBUG_INFO=y
68CONFIG_DEBUG_VM=y
69# CONFIG_RCU_CPU_STALL_DETECTOR is not set
70CONFIG_DEBUG_STACKOVERFLOW=y
71CONFIG_DEBUG_EXTRA_FLAGS="-femit-struct-debug-baseonly"
diff --git a/arch/tile/configs/tilegx_defconfig b/arch/tile/configs/tilegx_defconfig
new file mode 100644
index 000000000000..09f1c7fad8bf
--- /dev/null
+++ b/arch/tile/configs/tilegx_defconfig
@@ -0,0 +1,1833 @@
1#
2# Automatically generated make config: don't edit
3# Linux/tilegx 2.6.39-rc5 Kernel Configuration
4# Wed May 4 11:08:04 2011
5#
6CONFIG_TILE=y
7CONFIG_MMU=y
8CONFIG_GENERIC_CSUM=y
9CONFIG_SEMAPHORE_SLEEPERS=y
10CONFIG_HAVE_ARCH_ALLOC_REMAP=y
11CONFIG_HAVE_SETUP_PER_CPU_AREA=y
12CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
13CONFIG_SYS_SUPPORTS_HUGETLBFS=y
14CONFIG_GENERIC_TIME=y
15CONFIG_GENERIC_CLOCKEVENTS=y
16CONFIG_RWSEM_GENERIC_SPINLOCK=y
17CONFIG_DEFAULT_MIGRATION_COST=10000000
18CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
19CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
20CONFIG_ARCH_DMA_ADDR_T_64BIT=y
21CONFIG_LOCKDEP_SUPPORT=y
22CONFIG_STACKTRACE_SUPPORT=y
23CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
24CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
25CONFIG_TRACE_IRQFLAGS_SUPPORT=y
26CONFIG_STRICT_DEVMEM=y
27CONFIG_SMP=y
28# CONFIG_DEBUG_COPY_FROM_USER is not set
29CONFIG_HVC_TILE=y
30CONFIG_TILEGX=y
31CONFIG_64BIT=y
32CONFIG_ARCH_DEFCONFIG="arch/tile/configs/tilegx_defconfig"
33CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
34CONFIG_CONSTRUCTORS=y
35
36#
37# General setup
38#
39CONFIG_EXPERIMENTAL=y
40CONFIG_INIT_ENV_ARG_LIMIT=32
41CONFIG_CROSS_COMPILE=""
42CONFIG_LOCALVERSION=""
43# CONFIG_LOCALVERSION_AUTO is not set
44CONFIG_SWAP=y
45CONFIG_SYSVIPC=y
46CONFIG_SYSVIPC_SYSCTL=y
47CONFIG_POSIX_MQUEUE=y
48CONFIG_POSIX_MQUEUE_SYSCTL=y
49CONFIG_BSD_PROCESS_ACCT=y
50CONFIG_BSD_PROCESS_ACCT_V3=y
51# CONFIG_FHANDLE is not set
52CONFIG_TASKSTATS=y
53CONFIG_TASK_DELAY_ACCT=y
54CONFIG_TASK_XACCT=y
55CONFIG_TASK_IO_ACCOUNTING=y
56CONFIG_AUDIT=y
57CONFIG_HAVE_GENERIC_HARDIRQS=y
58
59#
60# IRQ subsystem
61#
62CONFIG_GENERIC_HARDIRQS=y
63CONFIG_GENERIC_IRQ_PROBE=y
64CONFIG_GENERIC_IRQ_SHOW=y
65CONFIG_GENERIC_PENDING_IRQ=y
66
67#
68# RCU Subsystem
69#
70CONFIG_TREE_RCU=y
71# CONFIG_PREEMPT_RCU is not set
72# CONFIG_RCU_TRACE is not set
73CONFIG_RCU_FANOUT=64
74# CONFIG_RCU_FANOUT_EXACT is not set
75# CONFIG_RCU_FAST_NO_HZ is not set
76# CONFIG_TREE_RCU_TRACE is not set
77# CONFIG_IKCONFIG is not set
78CONFIG_LOG_BUF_SHIFT=19
79CONFIG_CGROUPS=y
80CONFIG_CGROUP_DEBUG=y
81CONFIG_CGROUP_NS=y
82# CONFIG_CGROUP_FREEZER is not set
83CONFIG_CGROUP_DEVICE=y
84CONFIG_CPUSETS=y
85CONFIG_PROC_PID_CPUSET=y
86CONFIG_CGROUP_CPUACCT=y
87CONFIG_RESOURCE_COUNTERS=y
88CONFIG_CGROUP_MEM_RES_CTLR=y
89CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
90CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED=y
91CONFIG_CGROUP_SCHED=y
92CONFIG_FAIR_GROUP_SCHED=y
93CONFIG_RT_GROUP_SCHED=y
94CONFIG_BLK_CGROUP=y
95# CONFIG_DEBUG_BLK_CGROUP is not set
96CONFIG_NAMESPACES=y
97CONFIG_UTS_NS=y
98CONFIG_IPC_NS=y
99CONFIG_USER_NS=y
100CONFIG_PID_NS=y
101CONFIG_NET_NS=y
102# CONFIG_SCHED_AUTOGROUP is not set
103CONFIG_MM_OWNER=y
104# CONFIG_SYSFS_DEPRECATED is not set
105CONFIG_RELAY=y
106CONFIG_BLK_DEV_INITRD=y
107CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
108CONFIG_INITRAMFS_ROOT_UID=0
109CONFIG_INITRAMFS_ROOT_GID=0
110CONFIG_RD_GZIP=y
111# CONFIG_RD_BZIP2 is not set
112# CONFIG_RD_LZMA is not set
113# CONFIG_RD_XZ is not set
114# CONFIG_RD_LZO is not set
115CONFIG_INITRAMFS_COMPRESSION_NONE=y
116# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
117CONFIG_CC_OPTIMIZE_FOR_SIZE=y
118CONFIG_SYSCTL=y
119CONFIG_ANON_INODES=y
120CONFIG_EXPERT=y
121CONFIG_SYSCTL_SYSCALL=y
122CONFIG_KALLSYMS=y
123# CONFIG_KALLSYMS_ALL is not set
124# CONFIG_KALLSYMS_EXTRA_PASS is not set
125CONFIG_HOTPLUG=y
126CONFIG_PRINTK=y
127CONFIG_BUG=y
128CONFIG_ELF_CORE=y
129CONFIG_BASE_FULL=y
130CONFIG_FUTEX=y
131CONFIG_EPOLL=y
132CONFIG_SIGNALFD=y
133CONFIG_TIMERFD=y
134CONFIG_EVENTFD=y
135CONFIG_SHMEM=y
136CONFIG_AIO=y
137CONFIG_EMBEDDED=y
138
139#
140# Kernel Performance Events And Counters
141#
142CONFIG_VM_EVENT_COUNTERS=y
143CONFIG_PCI_QUIRKS=y
144CONFIG_SLUB_DEBUG=y
145# CONFIG_COMPAT_BRK is not set
146# CONFIG_SLAB is not set
147CONFIG_SLUB=y
148# CONFIG_SLOB is not set
149CONFIG_PROFILING=y
150CONFIG_USE_GENERIC_SMP_HELPERS=y
151
152#
153# GCOV-based kernel profiling
154#
155# CONFIG_GCOV_KERNEL is not set
156# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
157CONFIG_SLABINFO=y
158CONFIG_RT_MUTEXES=y
159CONFIG_BASE_SMALL=0
160CONFIG_MODULES=y
161CONFIG_MODULE_FORCE_LOAD=y
162CONFIG_MODULE_UNLOAD=y
163# CONFIG_MODULE_FORCE_UNLOAD is not set
164# CONFIG_MODVERSIONS is not set
165# CONFIG_MODULE_SRCVERSION_ALL is not set
166CONFIG_STOP_MACHINE=y
167CONFIG_BLOCK=y
168CONFIG_BLK_DEV_BSG=y
169CONFIG_BLK_DEV_INTEGRITY=y
170# CONFIG_BLK_DEV_THROTTLING is not set
171CONFIG_BLOCK_COMPAT=y
172
173#
174# IO Schedulers
175#
176CONFIG_IOSCHED_NOOP=y
177CONFIG_IOSCHED_DEADLINE=y
178CONFIG_IOSCHED_CFQ=y
179CONFIG_CFQ_GROUP_IOSCHED=y
180# CONFIG_DEFAULT_DEADLINE is not set
181CONFIG_DEFAULT_CFQ=y
182# CONFIG_DEFAULT_NOOP is not set
183CONFIG_DEFAULT_IOSCHED="cfq"
184CONFIG_PADATA=y
185# CONFIG_INLINE_SPIN_TRYLOCK is not set
186# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
187# CONFIG_INLINE_SPIN_LOCK is not set
188# CONFIG_INLINE_SPIN_LOCK_BH is not set
189# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
190# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
191CONFIG_INLINE_SPIN_UNLOCK=y
192# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
193CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
194# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
195# CONFIG_INLINE_READ_TRYLOCK is not set
196# CONFIG_INLINE_READ_LOCK is not set
197# CONFIG_INLINE_READ_LOCK_BH is not set
198# CONFIG_INLINE_READ_LOCK_IRQ is not set
199# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
200CONFIG_INLINE_READ_UNLOCK=y
201# CONFIG_INLINE_READ_UNLOCK_BH is not set
202CONFIG_INLINE_READ_UNLOCK_IRQ=y
203# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
204# CONFIG_INLINE_WRITE_TRYLOCK is not set
205# CONFIG_INLINE_WRITE_LOCK is not set
206# CONFIG_INLINE_WRITE_LOCK_BH is not set
207# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
208# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
209CONFIG_INLINE_WRITE_UNLOCK=y
210# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
211CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
212# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
213CONFIG_MUTEX_SPIN_ON_OWNER=y
214
215#
216# Tilera-specific configuration
217#
218CONFIG_NR_CPUS=100
219CONFIG_TICK_ONESHOT=y
220CONFIG_NO_HZ=y
221CONFIG_HIGH_RES_TIMERS=y
222CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
223CONFIG_HZ_100=y
224# CONFIG_HZ_250 is not set
225# CONFIG_HZ_300 is not set
226# CONFIG_HZ_1000 is not set
227CONFIG_HZ=100
228CONFIG_SCHED_HRTICK=y
229# CONFIG_KEXEC is not set
230CONFIG_COMPAT=y
231CONFIG_SYSVIPC_COMPAT=y
232# CONFIG_HIGHMEM is not set
233CONFIG_NUMA=y
234CONFIG_NODES_SHIFT=2
235CONFIG_PAGE_OFFSET=0xC0000000
236CONFIG_SELECT_MEMORY_MODEL=y
237CONFIG_DISCONTIGMEM_MANUAL=y
238CONFIG_DISCONTIGMEM=y
239CONFIG_FLAT_NODE_MEM_MAP=y
240CONFIG_NEED_MULTIPLE_NODES=y
241CONFIG_PAGEFLAGS_EXTENDED=y
242CONFIG_SPLIT_PTLOCK_CPUS=4
243# CONFIG_COMPACTION is not set
244CONFIG_MIGRATION=y
245CONFIG_PHYS_ADDR_T_64BIT=y
246CONFIG_ZONE_DMA_FLAG=0
247CONFIG_VIRT_TO_BUS=y
248# CONFIG_KSM is not set
249CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
250# CONFIG_CMDLINE_BOOL is not set
251CONFIG_VMALLOC_RESERVE=0x1000000
252CONFIG_HARDWALL=y
253CONFIG_KERNEL_PL=1
254
255#
256# Bus options
257#
258CONFIG_PCI=y
259CONFIG_PCI_DOMAINS=y
260# CONFIG_NO_IOMEM is not set
261# CONFIG_NO_IOPORT is not set
262# CONFIG_ARCH_SUPPORTS_MSI is not set
263CONFIG_PCI_DEBUG=y
264# CONFIG_PCI_STUB is not set
265# CONFIG_PCI_IOV is not set
266# CONFIG_HOTPLUG_PCI is not set
267
268#
269# Executable file formats
270#
271CONFIG_KCORE_ELF=y
272CONFIG_BINFMT_ELF=y
273CONFIG_COMPAT_BINFMT_ELF=y
274# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
275# CONFIG_HAVE_AOUT is not set
276CONFIG_BINFMT_MISC=y
277CONFIG_NET=y
278
279#
280# Networking options
281#
282CONFIG_PACKET=y
283CONFIG_UNIX=y
284CONFIG_XFRM=y
285CONFIG_XFRM_USER=y
286CONFIG_XFRM_SUB_POLICY=y
287CONFIG_XFRM_MIGRATE=y
288CONFIG_XFRM_STATISTICS=y
289CONFIG_XFRM_IPCOMP=m
290CONFIG_NET_KEY=m
291CONFIG_NET_KEY_MIGRATE=y
292CONFIG_INET=y
293CONFIG_IP_MULTICAST=y
294CONFIG_IP_ADVANCED_ROUTER=y
295# CONFIG_IP_FIB_TRIE_STATS is not set
296CONFIG_IP_MULTIPLE_TABLES=y
297CONFIG_IP_ROUTE_MULTIPATH=y
298CONFIG_IP_ROUTE_VERBOSE=y
299CONFIG_IP_ROUTE_CLASSID=y
300# CONFIG_IP_PNP is not set
301CONFIG_NET_IPIP=m
302# CONFIG_NET_IPGRE_DEMUX is not set
303CONFIG_IP_MROUTE=y
304# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
305CONFIG_IP_PIMSM_V1=y
306CONFIG_IP_PIMSM_V2=y
307# CONFIG_ARPD is not set
308CONFIG_SYN_COOKIES=y
309CONFIG_INET_AH=m
310CONFIG_INET_ESP=m
311CONFIG_INET_IPCOMP=m
312CONFIG_INET_XFRM_TUNNEL=m
313CONFIG_INET_TUNNEL=m
314CONFIG_INET_XFRM_MODE_TRANSPORT=m
315CONFIG_INET_XFRM_MODE_TUNNEL=m
316CONFIG_INET_XFRM_MODE_BEET=m
317CONFIG_INET_LRO=y
318CONFIG_INET_DIAG=m
319CONFIG_INET_TCP_DIAG=m
320CONFIG_TCP_CONG_ADVANCED=y
321CONFIG_TCP_CONG_BIC=m
322CONFIG_TCP_CONG_CUBIC=y
323CONFIG_TCP_CONG_WESTWOOD=m
324CONFIG_TCP_CONG_HTCP=m
325CONFIG_TCP_CONG_HSTCP=m
326CONFIG_TCP_CONG_HYBLA=m
327CONFIG_TCP_CONG_VEGAS=m
328CONFIG_TCP_CONG_SCALABLE=m
329CONFIG_TCP_CONG_LP=m
330CONFIG_TCP_CONG_VENO=m
331CONFIG_TCP_CONG_YEAH=m
332CONFIG_TCP_CONG_ILLINOIS=m
333CONFIG_DEFAULT_CUBIC=y
334# CONFIG_DEFAULT_RENO is not set
335CONFIG_DEFAULT_TCP_CONG="cubic"
336CONFIG_TCP_MD5SIG=y
337CONFIG_IPV6=y
338CONFIG_IPV6_PRIVACY=y
339CONFIG_IPV6_ROUTER_PREF=y
340CONFIG_IPV6_ROUTE_INFO=y
341CONFIG_IPV6_OPTIMISTIC_DAD=y
342CONFIG_INET6_AH=m
343CONFIG_INET6_ESP=m
344CONFIG_INET6_IPCOMP=m
345CONFIG_IPV6_MIP6=m
346CONFIG_INET6_XFRM_TUNNEL=m
347CONFIG_INET6_TUNNEL=m
348CONFIG_INET6_XFRM_MODE_TRANSPORT=m
349CONFIG_INET6_XFRM_MODE_TUNNEL=m
350CONFIG_INET6_XFRM_MODE_BEET=m
351CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
352CONFIG_IPV6_SIT=m
353# CONFIG_IPV6_SIT_6RD is not set
354CONFIG_IPV6_NDISC_NODETYPE=y
355CONFIG_IPV6_TUNNEL=m
356CONFIG_IPV6_MULTIPLE_TABLES=y
357# CONFIG_IPV6_SUBTREES is not set
358CONFIG_IPV6_MROUTE=y
359# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
360CONFIG_IPV6_PIMSM_V2=y
361CONFIG_NETLABEL=y
362CONFIG_NETWORK_SECMARK=y
363# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
364CONFIG_NETFILTER=y
365# CONFIG_NETFILTER_DEBUG is not set
366CONFIG_NETFILTER_ADVANCED=y
367CONFIG_BRIDGE_NETFILTER=y
368
369#
370# Core Netfilter Configuration
371#
372CONFIG_NETFILTER_NETLINK=m
373CONFIG_NETFILTER_NETLINK_QUEUE=m
374CONFIG_NETFILTER_NETLINK_LOG=m
375CONFIG_NF_CONNTRACK=y
376CONFIG_NF_CONNTRACK_MARK=y
377CONFIG_NF_CONNTRACK_SECMARK=y
378CONFIG_NF_CONNTRACK_ZONES=y
379CONFIG_NF_CONNTRACK_EVENTS=y
380# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
381CONFIG_NF_CT_PROTO_DCCP=m
382CONFIG_NF_CT_PROTO_GRE=m
383CONFIG_NF_CT_PROTO_SCTP=m
384CONFIG_NF_CT_PROTO_UDPLITE=m
385CONFIG_NF_CONNTRACK_AMANDA=m
386CONFIG_NF_CONNTRACK_FTP=m
387CONFIG_NF_CONNTRACK_H323=m
388CONFIG_NF_CONNTRACK_IRC=m
389CONFIG_NF_CONNTRACK_BROADCAST=m
390CONFIG_NF_CONNTRACK_NETBIOS_NS=m
391# CONFIG_NF_CONNTRACK_SNMP is not set
392CONFIG_NF_CONNTRACK_PPTP=m
393CONFIG_NF_CONNTRACK_SANE=m
394CONFIG_NF_CONNTRACK_SIP=m
395CONFIG_NF_CONNTRACK_TFTP=m
396# CONFIG_NF_CT_NETLINK is not set
397CONFIG_NETFILTER_TPROXY=m
398CONFIG_NETFILTER_XTABLES=y
399
400#
401# Xtables combined modules
402#
403CONFIG_NETFILTER_XT_MARK=m
404CONFIG_NETFILTER_XT_CONNMARK=m
405
406#
407# Xtables targets
408#
409# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
410# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
411CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
412CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
413CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
414CONFIG_NETFILTER_XT_TARGET_CT=m
415CONFIG_NETFILTER_XT_TARGET_DSCP=m
416CONFIG_NETFILTER_XT_TARGET_HL=m
417CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
418CONFIG_NETFILTER_XT_TARGET_MARK=m
419CONFIG_NETFILTER_XT_TARGET_NFLOG=m
420CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
421CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
422CONFIG_NETFILTER_XT_TARGET_RATEEST=m
423CONFIG_NETFILTER_XT_TARGET_TEE=m
424CONFIG_NETFILTER_XT_TARGET_TPROXY=m
425CONFIG_NETFILTER_XT_TARGET_TRACE=m
426CONFIG_NETFILTER_XT_TARGET_SECMARK=m
427CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
428CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
429
430#
431# Xtables matches
432#
433# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
434CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
435CONFIG_NETFILTER_XT_MATCH_COMMENT=m
436CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
437CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
438CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
439CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
440# CONFIG_NETFILTER_XT_MATCH_CPU is not set
441CONFIG_NETFILTER_XT_MATCH_DCCP=m
442# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
443CONFIG_NETFILTER_XT_MATCH_DSCP=m
444CONFIG_NETFILTER_XT_MATCH_ESP=m
445CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
446CONFIG_NETFILTER_XT_MATCH_HELPER=m
447CONFIG_NETFILTER_XT_MATCH_HL=m
448CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
449CONFIG_NETFILTER_XT_MATCH_IPVS=m
450CONFIG_NETFILTER_XT_MATCH_LENGTH=m
451CONFIG_NETFILTER_XT_MATCH_LIMIT=m
452CONFIG_NETFILTER_XT_MATCH_MAC=m
453CONFIG_NETFILTER_XT_MATCH_MARK=m
454CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
455CONFIG_NETFILTER_XT_MATCH_OSF=m
456CONFIG_NETFILTER_XT_MATCH_OWNER=m
457CONFIG_NETFILTER_XT_MATCH_POLICY=m
458CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
459CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
460CONFIG_NETFILTER_XT_MATCH_QUOTA=m
461CONFIG_NETFILTER_XT_MATCH_RATEEST=m
462CONFIG_NETFILTER_XT_MATCH_REALM=m
463CONFIG_NETFILTER_XT_MATCH_RECENT=m
464CONFIG_NETFILTER_XT_MATCH_SCTP=m
465CONFIG_NETFILTER_XT_MATCH_SOCKET=m
466CONFIG_NETFILTER_XT_MATCH_STATE=y
467CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
468CONFIG_NETFILTER_XT_MATCH_STRING=m
469CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
470CONFIG_NETFILTER_XT_MATCH_TIME=m
471CONFIG_NETFILTER_XT_MATCH_U32=m
472# CONFIG_IP_SET is not set
473CONFIG_IP_VS=m
474CONFIG_IP_VS_IPV6=y
475# CONFIG_IP_VS_DEBUG is not set
476CONFIG_IP_VS_TAB_BITS=12
477
478#
479# IPVS transport protocol load balancing support
480#
481CONFIG_IP_VS_PROTO_TCP=y
482CONFIG_IP_VS_PROTO_UDP=y
483CONFIG_IP_VS_PROTO_AH_ESP=y
484CONFIG_IP_VS_PROTO_ESP=y
485CONFIG_IP_VS_PROTO_AH=y
486CONFIG_IP_VS_PROTO_SCTP=y
487
488#
489# IPVS scheduler
490#
491CONFIG_IP_VS_RR=m
492CONFIG_IP_VS_WRR=m
493CONFIG_IP_VS_LC=m
494CONFIG_IP_VS_WLC=m
495CONFIG_IP_VS_LBLC=m
496CONFIG_IP_VS_LBLCR=m
497# CONFIG_IP_VS_DH is not set
498# CONFIG_IP_VS_SH is not set
499CONFIG_IP_VS_SED=m
500CONFIG_IP_VS_NQ=m
501
502#
503# IPVS application helper
504#
505# CONFIG_IP_VS_NFCT is not set
506# CONFIG_IP_VS_PE_SIP is not set
507
508#
509# IP: Netfilter Configuration
510#
511CONFIG_NF_DEFRAG_IPV4=y
512CONFIG_NF_CONNTRACK_IPV4=y
513# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
514CONFIG_IP_NF_QUEUE=m
515CONFIG_IP_NF_IPTABLES=y
516CONFIG_IP_NF_MATCH_AH=m
517CONFIG_IP_NF_MATCH_ECN=m
518CONFIG_IP_NF_MATCH_TTL=m
519CONFIG_IP_NF_FILTER=y
520CONFIG_IP_NF_TARGET_REJECT=y
521CONFIG_IP_NF_TARGET_LOG=m
522CONFIG_IP_NF_TARGET_ULOG=m
523# CONFIG_NF_NAT is not set
524CONFIG_IP_NF_MANGLE=m
525# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
526CONFIG_IP_NF_TARGET_ECN=m
527CONFIG_IP_NF_TARGET_TTL=m
528CONFIG_IP_NF_RAW=m
529CONFIG_IP_NF_SECURITY=m
530CONFIG_IP_NF_ARPTABLES=m
531CONFIG_IP_NF_ARPFILTER=m
532CONFIG_IP_NF_ARP_MANGLE=m
533
534#
535# IPv6: Netfilter Configuration
536#
537CONFIG_NF_DEFRAG_IPV6=m
538CONFIG_NF_CONNTRACK_IPV6=m
539CONFIG_IP6_NF_QUEUE=m
540CONFIG_IP6_NF_IPTABLES=m
541CONFIG_IP6_NF_MATCH_AH=m
542CONFIG_IP6_NF_MATCH_EUI64=m
543CONFIG_IP6_NF_MATCH_FRAG=m
544CONFIG_IP6_NF_MATCH_OPTS=m
545CONFIG_IP6_NF_MATCH_HL=m
546CONFIG_IP6_NF_MATCH_IPV6HEADER=m
547CONFIG_IP6_NF_MATCH_MH=m
548CONFIG_IP6_NF_MATCH_RT=m
549CONFIG_IP6_NF_TARGET_HL=m
550CONFIG_IP6_NF_TARGET_LOG=m
551CONFIG_IP6_NF_FILTER=m
552CONFIG_IP6_NF_TARGET_REJECT=m
553CONFIG_IP6_NF_MANGLE=m
554CONFIG_IP6_NF_RAW=m
555CONFIG_IP6_NF_SECURITY=m
556CONFIG_BRIDGE_NF_EBTABLES=m
557CONFIG_BRIDGE_EBT_BROUTE=m
558CONFIG_BRIDGE_EBT_T_FILTER=m
559CONFIG_BRIDGE_EBT_T_NAT=m
560CONFIG_BRIDGE_EBT_802_3=m
561CONFIG_BRIDGE_EBT_AMONG=m
562CONFIG_BRIDGE_EBT_ARP=m
563CONFIG_BRIDGE_EBT_IP=m
564CONFIG_BRIDGE_EBT_IP6=m
565CONFIG_BRIDGE_EBT_LIMIT=m
566CONFIG_BRIDGE_EBT_MARK=m
567CONFIG_BRIDGE_EBT_PKTTYPE=m
568CONFIG_BRIDGE_EBT_STP=m
569CONFIG_BRIDGE_EBT_VLAN=m
570CONFIG_BRIDGE_EBT_ARPREPLY=m
571CONFIG_BRIDGE_EBT_DNAT=m
572CONFIG_BRIDGE_EBT_MARK_T=m
573CONFIG_BRIDGE_EBT_REDIRECT=m
574CONFIG_BRIDGE_EBT_SNAT=m
575CONFIG_BRIDGE_EBT_LOG=m
576CONFIG_BRIDGE_EBT_ULOG=m
577CONFIG_BRIDGE_EBT_NFLOG=m
578# CONFIG_IP_DCCP is not set
579CONFIG_IP_SCTP=m
580# CONFIG_SCTP_DBG_MSG is not set
581# CONFIG_SCTP_DBG_OBJCNT is not set
582# CONFIG_SCTP_HMAC_NONE is not set
583# CONFIG_SCTP_HMAC_SHA1 is not set
584CONFIG_SCTP_HMAC_MD5=y
585CONFIG_RDS=m
586CONFIG_RDS_TCP=m
587# CONFIG_RDS_DEBUG is not set
588# CONFIG_TIPC is not set
589# CONFIG_ATM is not set
590# CONFIG_L2TP is not set
591CONFIG_STP=m
592CONFIG_GARP=m
593CONFIG_BRIDGE=m
594CONFIG_BRIDGE_IGMP_SNOOPING=y
595CONFIG_NET_DSA=y
596CONFIG_NET_DSA_TAG_DSA=y
597CONFIG_NET_DSA_TAG_EDSA=y
598CONFIG_NET_DSA_TAG_TRAILER=y
599CONFIG_NET_DSA_MV88E6XXX=y
600CONFIG_NET_DSA_MV88E6060=y
601CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y
602CONFIG_NET_DSA_MV88E6131=y
603CONFIG_NET_DSA_MV88E6123_61_65=y
604CONFIG_VLAN_8021Q=m
605CONFIG_VLAN_8021Q_GVRP=y
606# CONFIG_DECNET is not set
607CONFIG_LLC=m
608# CONFIG_LLC2 is not set
609# CONFIG_IPX is not set
610# CONFIG_ATALK is not set
611# CONFIG_X25 is not set
612# CONFIG_LAPB is not set
613# CONFIG_ECONET is not set
614# CONFIG_WAN_ROUTER is not set
615CONFIG_PHONET=m
616# CONFIG_IEEE802154 is not set
617CONFIG_NET_SCHED=y
618
619#
620# Queueing/Scheduling
621#
622CONFIG_NET_SCH_CBQ=m
623CONFIG_NET_SCH_HTB=m
624CONFIG_NET_SCH_HFSC=m
625CONFIG_NET_SCH_PRIO=m
626CONFIG_NET_SCH_MULTIQ=m
627CONFIG_NET_SCH_RED=m
628# CONFIG_NET_SCH_SFB is not set
629CONFIG_NET_SCH_SFQ=m
630CONFIG_NET_SCH_TEQL=m
631CONFIG_NET_SCH_TBF=m
632CONFIG_NET_SCH_GRED=m
633CONFIG_NET_SCH_DSMARK=m
634CONFIG_NET_SCH_NETEM=m
635CONFIG_NET_SCH_DRR=m
636# CONFIG_NET_SCH_MQPRIO is not set
637# CONFIG_NET_SCH_CHOKE is not set
638CONFIG_NET_SCH_INGRESS=m
639
640#
641# Classification
642#
643CONFIG_NET_CLS=y
644CONFIG_NET_CLS_BASIC=m
645CONFIG_NET_CLS_TCINDEX=m
646CONFIG_NET_CLS_ROUTE4=m
647CONFIG_NET_CLS_FW=m
648CONFIG_NET_CLS_U32=m
649CONFIG_CLS_U32_PERF=y
650CONFIG_CLS_U32_MARK=y
651CONFIG_NET_CLS_RSVP=m
652CONFIG_NET_CLS_RSVP6=m
653CONFIG_NET_CLS_FLOW=m
654CONFIG_NET_CLS_CGROUP=y
655CONFIG_NET_EMATCH=y
656CONFIG_NET_EMATCH_STACK=32
657CONFIG_NET_EMATCH_CMP=m
658CONFIG_NET_EMATCH_NBYTE=m
659CONFIG_NET_EMATCH_U32=m
660CONFIG_NET_EMATCH_META=m
661CONFIG_NET_EMATCH_TEXT=m
662CONFIG_NET_CLS_ACT=y
663CONFIG_NET_ACT_POLICE=m
664CONFIG_NET_ACT_GACT=m
665CONFIG_GACT_PROB=y
666CONFIG_NET_ACT_MIRRED=m
667CONFIG_NET_ACT_IPT=m
668CONFIG_NET_ACT_NAT=m
669CONFIG_NET_ACT_PEDIT=m
670CONFIG_NET_ACT_SIMP=m
671CONFIG_NET_ACT_SKBEDIT=m
672# CONFIG_NET_ACT_CSUM is not set
673CONFIG_NET_CLS_IND=y
674CONFIG_NET_SCH_FIFO=y
675CONFIG_DCB=y
676CONFIG_DNS_RESOLVER=y
677# CONFIG_BATMAN_ADV is not set
678CONFIG_RPS=y
679CONFIG_RFS_ACCEL=y
680CONFIG_XPS=y
681
682#
683# Network testing
684#
685# CONFIG_NET_PKTGEN is not set
686# CONFIG_HAMRADIO is not set
687# CONFIG_CAN is not set
688# CONFIG_IRDA is not set
689# CONFIG_BT is not set
690# CONFIG_AF_RXRPC is not set
691CONFIG_FIB_RULES=y
692# CONFIG_WIRELESS is not set
693# CONFIG_WIMAX is not set
694# CONFIG_RFKILL is not set
695# CONFIG_NET_9P is not set
696# CONFIG_CAIF is not set
697# CONFIG_CEPH_LIB is not set
698
699#
700# Device Drivers
701#
702
703#
704# Generic Driver Options
705#
706CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
707CONFIG_DEVTMPFS=y
708CONFIG_DEVTMPFS_MOUNT=y
709CONFIG_STANDALONE=y
710CONFIG_PREVENT_FIRMWARE_BUILD=y
711CONFIG_FW_LOADER=y
712# CONFIG_FIRMWARE_IN_KERNEL is not set
713CONFIG_EXTRA_FIRMWARE=""
714# CONFIG_DEBUG_DRIVER is not set
715# CONFIG_DEBUG_DEVRES is not set
716# CONFIG_SYS_HYPERVISOR is not set
717CONFIG_CONNECTOR=y
718CONFIG_PROC_EVENTS=y
719# CONFIG_MTD is not set
720# CONFIG_PARPORT is not set
721CONFIG_BLK_DEV=y
722# CONFIG_BLK_CPQ_DA is not set
723# CONFIG_BLK_CPQ_CISS_DA is not set
724# CONFIG_BLK_DEV_DAC960 is not set
725# CONFIG_BLK_DEV_UMEM is not set
726# CONFIG_BLK_DEV_COW_COMMON is not set
727CONFIG_BLK_DEV_LOOP=y
728CONFIG_BLK_DEV_CRYPTOLOOP=m
729# CONFIG_BLK_DEV_DRBD is not set
730# CONFIG_BLK_DEV_NBD is not set
731CONFIG_BLK_DEV_SX8=m
732CONFIG_BLK_DEV_RAM=y
733CONFIG_BLK_DEV_RAM_COUNT=16
734CONFIG_BLK_DEV_RAM_SIZE=16384
735# CONFIG_BLK_DEV_XIP is not set
736# CONFIG_CDROM_PKTCDVD is not set
737CONFIG_ATA_OVER_ETH=y
738# CONFIG_BLK_DEV_RBD is not set
739# CONFIG_SENSORS_LIS3LV02D is not set
740CONFIG_MISC_DEVICES=y
741# CONFIG_AD525X_DPOT is not set
742# CONFIG_PHANTOM is not set
743# CONFIG_SGI_IOC4 is not set
744# CONFIG_TIFM_CORE is not set
745# CONFIG_ICS932S401 is not set
746# CONFIG_ENCLOSURE_SERVICES is not set
747# CONFIG_HP_ILO is not set
748# CONFIG_APDS9802ALS is not set
749# CONFIG_ISL29003 is not set
750# CONFIG_ISL29020 is not set
751# CONFIG_SENSORS_TSL2550 is not set
752# CONFIG_SENSORS_BH1780 is not set
753# CONFIG_SENSORS_BH1770 is not set
754# CONFIG_SENSORS_APDS990X is not set
755# CONFIG_HMC6352 is not set
756# CONFIG_DS1682 is not set
757# CONFIG_BMP085 is not set
758# CONFIG_PCH_PHUB is not set
759# CONFIG_C2PORT is not set
760
761#
762# EEPROM support
763#
764# CONFIG_EEPROM_AT24 is not set
765# CONFIG_EEPROM_LEGACY is not set
766# CONFIG_EEPROM_MAX6875 is not set
767# CONFIG_EEPROM_93CX6 is not set
768# CONFIG_CB710_CORE is not set
769
770#
771# Texas Instruments shared transport line discipline
772#
773# CONFIG_SENSORS_LIS3_I2C is not set
774
775#
776# SCSI device support
777#
778CONFIG_SCSI_MOD=m
779CONFIG_RAID_ATTRS=m
780CONFIG_SCSI=m
781CONFIG_SCSI_DMA=y
782CONFIG_SCSI_TGT=m
783# CONFIG_SCSI_NETLINK is not set
784CONFIG_SCSI_PROC_FS=y
785
786#
787# SCSI support type (disk, tape, CD-ROM)
788#
789CONFIG_BLK_DEV_SD=m
790# CONFIG_CHR_DEV_ST is not set
791# CONFIG_CHR_DEV_OSST is not set
792# CONFIG_BLK_DEV_SR is not set
793# CONFIG_CHR_DEV_SG is not set
794# CONFIG_CHR_DEV_SCH is not set
795# CONFIG_SCSI_MULTI_LUN is not set
796CONFIG_SCSI_CONSTANTS=y
797CONFIG_SCSI_LOGGING=y
798# CONFIG_SCSI_SCAN_ASYNC is not set
799CONFIG_SCSI_WAIT_SCAN=m
800
801#
802# SCSI Transports
803#
804# CONFIG_SCSI_SPI_ATTRS is not set
805# CONFIG_SCSI_FC_ATTRS is not set
806# CONFIG_SCSI_ISCSI_ATTRS is not set
807CONFIG_SCSI_SAS_ATTRS=m
808# CONFIG_SCSI_SAS_LIBSAS is not set
809# CONFIG_SCSI_SRP_ATTRS is not set
810CONFIG_SCSI_LOWLEVEL=y
811# CONFIG_ISCSI_TCP is not set
812# CONFIG_ISCSI_BOOT_SYSFS is not set
813# CONFIG_SCSI_CXGB3_ISCSI is not set
814# CONFIG_SCSI_CXGB4_ISCSI is not set
815# CONFIG_SCSI_BNX2_ISCSI is not set
816# CONFIG_SCSI_BNX2X_FCOE is not set
817# CONFIG_BE2ISCSI is not set
818# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
819# CONFIG_SCSI_HPSA is not set
820# CONFIG_SCSI_3W_9XXX is not set
821# CONFIG_SCSI_3W_SAS is not set
822# CONFIG_SCSI_ACARD is not set
823# CONFIG_SCSI_AACRAID is not set
824# CONFIG_SCSI_AIC7XXX is not set
825# CONFIG_SCSI_AIC7XXX_OLD is not set
826# CONFIG_SCSI_AIC79XX is not set
827# CONFIG_SCSI_AIC94XX is not set
828# CONFIG_SCSI_MVSAS is not set
829# CONFIG_SCSI_DPT_I2O is not set
830# CONFIG_SCSI_ADVANSYS is not set
831# CONFIG_SCSI_ARCMSR is not set
832# CONFIG_MEGARAID_NEWGEN is not set
833# CONFIG_MEGARAID_LEGACY is not set
834# CONFIG_MEGARAID_SAS is not set
835# CONFIG_SCSI_MPT2SAS is not set
836# CONFIG_SCSI_HPTIOP is not set
837# CONFIG_LIBFC is not set
838# CONFIG_LIBFCOE is not set
839# CONFIG_FCOE is not set
840# CONFIG_SCSI_DMX3191D is not set
841# CONFIG_SCSI_FUTURE_DOMAIN is not set
842# CONFIG_SCSI_IPS is not set
843# CONFIG_SCSI_INITIO is not set
844# CONFIG_SCSI_INIA100 is not set
845# CONFIG_SCSI_STEX is not set
846# CONFIG_SCSI_SYM53C8XX_2 is not set
847# CONFIG_SCSI_IPR is not set
848# CONFIG_SCSI_QLOGIC_1280 is not set
849# CONFIG_SCSI_QLA_FC is not set
850# CONFIG_SCSI_QLA_ISCSI is not set
851# CONFIG_SCSI_LPFC is not set
852# CONFIG_SCSI_DC395x is not set
853# CONFIG_SCSI_DC390T is not set
854# CONFIG_SCSI_DEBUG is not set
855# CONFIG_SCSI_PMCRAID is not set
856# CONFIG_SCSI_PM8001 is not set
857# CONFIG_SCSI_SRP is not set
858# CONFIG_SCSI_BFA_FC is not set
859# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
860# CONFIG_SCSI_DH is not set
861# CONFIG_SCSI_OSD_INITIATOR is not set
862CONFIG_ATA=m
863# CONFIG_ATA_NONSTANDARD is not set
864CONFIG_ATA_VERBOSE_ERROR=y
865CONFIG_SATA_PMP=y
866
867#
868# Controllers with non-SFF native interface
869#
870# CONFIG_SATA_AHCI is not set
871# CONFIG_SATA_AHCI_PLATFORM is not set
872# CONFIG_SATA_INIC162X is not set
873# CONFIG_SATA_ACARD_AHCI is not set
874CONFIG_SATA_SIL24=m
875CONFIG_ATA_SFF=y
876
877#
878# SFF controllers with custom DMA interface
879#
880# CONFIG_PDC_ADMA is not set
881# CONFIG_SATA_QSTOR is not set
882# CONFIG_SATA_SX4 is not set
883CONFIG_ATA_BMDMA=y
884
885#
886# SATA SFF controllers with BMDMA
887#
888# CONFIG_ATA_PIIX is not set
889# CONFIG_SATA_MV is not set
890# CONFIG_SATA_NV is not set
891# CONFIG_SATA_PROMISE is not set
892# CONFIG_SATA_SIL is not set
893# CONFIG_SATA_SIS is not set
894# CONFIG_SATA_SVW is not set
895# CONFIG_SATA_ULI is not set
896# CONFIG_SATA_VIA is not set
897# CONFIG_SATA_VITESSE is not set
898
899#
900# PATA SFF controllers with BMDMA
901#
902# CONFIG_PATA_ALI is not set
903# CONFIG_PATA_AMD is not set
904# CONFIG_PATA_ARASAN_CF is not set
905# CONFIG_PATA_ARTOP is not set
906# CONFIG_PATA_ATIIXP is not set
907# CONFIG_PATA_ATP867X is not set
908# CONFIG_PATA_CMD64X is not set
909# CONFIG_PATA_CS5520 is not set
910# CONFIG_PATA_CS5530 is not set
911# CONFIG_PATA_CS5536 is not set
912# CONFIG_PATA_CYPRESS is not set
913# CONFIG_PATA_EFAR is not set
914# CONFIG_PATA_HPT366 is not set
915# CONFIG_PATA_HPT37X is not set
916# CONFIG_PATA_HPT3X2N is not set
917# CONFIG_PATA_HPT3X3 is not set
918# CONFIG_PATA_IT8213 is not set
919# CONFIG_PATA_IT821X is not set
920# CONFIG_PATA_JMICRON is not set
921# CONFIG_PATA_MARVELL is not set
922# CONFIG_PATA_NETCELL is not set
923# CONFIG_PATA_NINJA32 is not set
924# CONFIG_PATA_NS87415 is not set
925# CONFIG_PATA_OLDPIIX is not set
926# CONFIG_PATA_OPTIDMA is not set
927# CONFIG_PATA_PDC2027X is not set
928# CONFIG_PATA_PDC_OLD is not set
929# CONFIG_PATA_RADISYS is not set
930# CONFIG_PATA_RDC is not set
931# CONFIG_PATA_SC1200 is not set
932# CONFIG_PATA_SCH is not set
933# CONFIG_PATA_SERVERWORKS is not set
934# CONFIG_PATA_SIL680 is not set
935# CONFIG_PATA_SIS is not set
936# CONFIG_PATA_TOSHIBA is not set
937# CONFIG_PATA_TRIFLEX is not set
938# CONFIG_PATA_VIA is not set
939# CONFIG_PATA_WINBOND is not set
940
941#
942# PIO-only SFF controllers
943#
944# CONFIG_PATA_CMD640_PCI is not set
945# CONFIG_PATA_MPIIX is not set
946# CONFIG_PATA_NS87410 is not set
947# CONFIG_PATA_OPTI is not set
948# CONFIG_PATA_PLATFORM is not set
949# CONFIG_PATA_RZ1000 is not set
950
951#
952# Generic fallback / legacy drivers
953#
954# CONFIG_ATA_GENERIC is not set
955# CONFIG_PATA_LEGACY is not set
956CONFIG_MD=y
957CONFIG_BLK_DEV_MD=y
958CONFIG_MD_AUTODETECT=y
959CONFIG_MD_LINEAR=m
960CONFIG_MD_RAID0=m
961CONFIG_MD_RAID1=m
962CONFIG_MD_RAID10=m
963CONFIG_MD_RAID456=m
964CONFIG_MULTICORE_RAID456=y
965# CONFIG_MD_MULTIPATH is not set
966CONFIG_MD_FAULTY=m
967CONFIG_BLK_DEV_DM=m
968CONFIG_DM_DEBUG=y
969CONFIG_DM_CRYPT=m
970CONFIG_DM_SNAPSHOT=m
971CONFIG_DM_MIRROR=m
972# CONFIG_DM_RAID is not set
973CONFIG_DM_LOG_USERSPACE=m
974CONFIG_DM_ZERO=m
975CONFIG_DM_MULTIPATH=m
976CONFIG_DM_MULTIPATH_QL=m
977CONFIG_DM_MULTIPATH_ST=m
978CONFIG_DM_DELAY=m
979CONFIG_DM_UEVENT=y
980# CONFIG_DM_FLAKEY is not set
981# CONFIG_TARGET_CORE is not set
982# CONFIG_FUSION is not set
983
984#
985# IEEE 1394 (FireWire) support
986#
987# CONFIG_FIREWIRE is not set
988# CONFIG_FIREWIRE_NOSY is not set
989# CONFIG_I2O is not set
990CONFIG_NETDEVICES=y
991CONFIG_IFB=m
992CONFIG_DUMMY=m
993CONFIG_BONDING=m
994CONFIG_MACVLAN=m
995CONFIG_MACVTAP=m
996# CONFIG_EQUALIZER is not set
997CONFIG_TUN=y
998CONFIG_VETH=m
999# CONFIG_ARCNET is not set
1000# CONFIG_MII is not set
1001CONFIG_PHYLIB=y
1002
1003#
1004# MII PHY device drivers
1005#
1006# CONFIG_MARVELL_PHY is not set
1007# CONFIG_DAVICOM_PHY is not set
1008# CONFIG_QSEMI_PHY is not set
1009# CONFIG_LXT_PHY is not set
1010# CONFIG_CICADA_PHY is not set
1011# CONFIG_VITESSE_PHY is not set
1012# CONFIG_SMSC_PHY is not set
1013# CONFIG_BROADCOM_PHY is not set
1014# CONFIG_BCM63XX_PHY is not set
1015# CONFIG_ICPLUS_PHY is not set
1016# CONFIG_REALTEK_PHY is not set
1017# CONFIG_NATIONAL_PHY is not set
1018# CONFIG_STE10XP is not set
1019# CONFIG_LSI_ET1011C_PHY is not set
1020# CONFIG_MICREL_PHY is not set
1021# CONFIG_FIXED_PHY is not set
1022# CONFIG_MDIO_BITBANG is not set
1023# CONFIG_NET_ETHERNET is not set
1024CONFIG_NETDEV_1000=y
1025# CONFIG_ACENIC is not set
1026# CONFIG_DL2K is not set
1027# CONFIG_E1000 is not set
1028CONFIG_E1000E=m
1029# CONFIG_IP1000 is not set
1030# CONFIG_IGB is not set
1031# CONFIG_IGBVF is not set
1032# CONFIG_NS83820 is not set
1033# CONFIG_HAMACHI is not set
1034# CONFIG_YELLOWFIN is not set
1035# CONFIG_R8169 is not set
1036# CONFIG_SIS190 is not set
1037# CONFIG_SKGE is not set
1038# CONFIG_SKY2 is not set
1039# CONFIG_VIA_VELOCITY is not set
1040# CONFIG_TIGON3 is not set
1041# CONFIG_BNX2 is not set
1042# CONFIG_CNIC is not set
1043# CONFIG_QLA3XXX is not set
1044# CONFIG_ATL1 is not set
1045# CONFIG_ATL1E is not set
1046# CONFIG_ATL1C is not set
1047# CONFIG_JME is not set
1048# CONFIG_STMMAC_ETH is not set
1049# CONFIG_PCH_GBE is not set
1050# CONFIG_NETDEV_10000 is not set
1051# CONFIG_TR is not set
1052# CONFIG_WLAN is not set
1053
1054#
1055# Enable WiMAX (Networking options) to see the WiMAX drivers
1056#
1057# CONFIG_WAN is not set
1058
1059#
1060# CAIF transport drivers
1061#
1062# CONFIG_TILE_NET is not set
1063# CONFIG_FDDI is not set
1064# CONFIG_HIPPI is not set
1065# CONFIG_PPP is not set
1066# CONFIG_SLIP is not set
1067# CONFIG_NET_FC is not set
1068# CONFIG_NETCONSOLE is not set
1069# CONFIG_NETPOLL is not set
1070# CONFIG_NET_POLL_CONTROLLER is not set
1071# CONFIG_VMXNET3 is not set
1072# CONFIG_ISDN is not set
1073# CONFIG_PHONE is not set
1074
1075#
1076# Input device support
1077#
1078CONFIG_INPUT=y
1079# CONFIG_INPUT_FF_MEMLESS is not set
1080# CONFIG_INPUT_POLLDEV is not set
1081# CONFIG_INPUT_SPARSEKMAP is not set
1082
1083#
1084# Userland interfaces
1085#
1086# CONFIG_INPUT_MOUSEDEV is not set
1087# CONFIG_INPUT_JOYDEV is not set
1088# CONFIG_INPUT_EVDEV is not set
1089# CONFIG_INPUT_EVBUG is not set
1090
1091#
1092# Input Device Drivers
1093#
1094# CONFIG_INPUT_KEYBOARD is not set
1095# CONFIG_INPUT_MOUSE is not set
1096# CONFIG_INPUT_JOYSTICK is not set
1097# CONFIG_INPUT_TABLET is not set
1098# CONFIG_INPUT_TOUCHSCREEN is not set
1099# CONFIG_INPUT_MISC is not set
1100
1101#
1102# Hardware I/O ports
1103#
1104# CONFIG_SERIO is not set
1105# CONFIG_GAMEPORT is not set
1106
1107#
1108# Character devices
1109#
1110# CONFIG_VT is not set
1111CONFIG_UNIX98_PTYS=y
1112# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1113# CONFIG_LEGACY_PTYS is not set
1114# CONFIG_SERIAL_NONSTANDARD is not set
1115# CONFIG_NOZOMI is not set
1116# CONFIG_N_GSM is not set
1117CONFIG_DEVKMEM=y
1118
1119#
1120# Serial drivers
1121#
1122# CONFIG_SERIAL_8250 is not set
1123
1124#
1125# Non-8250 serial port support
1126#
1127# CONFIG_SERIAL_MFD_HSU is not set
1128# CONFIG_SERIAL_JSM is not set
1129# CONFIG_SERIAL_TIMBERDALE is not set
1130# CONFIG_SERIAL_ALTERA_JTAGUART is not set
1131# CONFIG_SERIAL_ALTERA_UART is not set
1132# CONFIG_SERIAL_PCH_UART is not set
1133# CONFIG_TTY_PRINTK is not set
1134CONFIG_HVC_DRIVER=y
1135# CONFIG_IPMI_HANDLER is not set
1136CONFIG_HW_RANDOM=y
1137CONFIG_HW_RANDOM_TIMERIOMEM=m
1138# CONFIG_R3964 is not set
1139# CONFIG_APPLICOM is not set
1140
1141#
1142# PCMCIA character devices
1143#
1144# CONFIG_RAW_DRIVER is not set
1145# CONFIG_TCG_TPM is not set
1146CONFIG_DEVPORT=y
1147# CONFIG_RAMOOPS is not set
1148CONFIG_I2C=y
1149CONFIG_I2C_BOARDINFO=y
1150CONFIG_I2C_COMPAT=y
1151CONFIG_I2C_CHARDEV=y
1152# CONFIG_I2C_MUX is not set
1153CONFIG_I2C_HELPER_AUTO=y
1154
1155#
1156# I2C Hardware Bus support
1157#
1158
1159#
1160# PC SMBus host controller drivers
1161#
1162# CONFIG_I2C_ALI1535 is not set
1163# CONFIG_I2C_ALI1563 is not set
1164# CONFIG_I2C_ALI15X3 is not set
1165# CONFIG_I2C_AMD756 is not set
1166# CONFIG_I2C_AMD8111 is not set
1167# CONFIG_I2C_I801 is not set
1168# CONFIG_I2C_ISCH is not set
1169# CONFIG_I2C_PIIX4 is not set
1170# CONFIG_I2C_NFORCE2 is not set
1171# CONFIG_I2C_SIS5595 is not set
1172# CONFIG_I2C_SIS630 is not set
1173# CONFIG_I2C_SIS96X is not set
1174# CONFIG_I2C_VIA is not set
1175# CONFIG_I2C_VIAPRO is not set
1176
1177#
1178# I2C system bus drivers (mostly embedded / system-on-chip)
1179#
1180# CONFIG_I2C_INTEL_MID is not set
1181# CONFIG_I2C_OCORES is not set
1182# CONFIG_I2C_PCA_PLATFORM is not set
1183# CONFIG_I2C_PXA_PCI is not set
1184# CONFIG_I2C_SIMTEC is not set
1185# CONFIG_I2C_XILINX is not set
1186# CONFIG_I2C_EG20T is not set
1187
1188#
1189# External I2C/SMBus adapter drivers
1190#
1191# CONFIG_I2C_PARPORT_LIGHT is not set
1192# CONFIG_I2C_TAOS_EVM is not set
1193
1194#
1195# Other I2C/SMBus bus drivers
1196#
1197# CONFIG_I2C_STUB is not set
1198# CONFIG_I2C_DEBUG_CORE is not set
1199# CONFIG_I2C_DEBUG_ALGO is not set
1200# CONFIG_I2C_DEBUG_BUS is not set
1201# CONFIG_SPI is not set
1202
1203#
1204# PPS support
1205#
1206# CONFIG_PPS is not set
1207
1208#
1209# PPS generators support
1210#
1211# CONFIG_W1 is not set
1212# CONFIG_POWER_SUPPLY is not set
1213# CONFIG_HWMON is not set
1214# CONFIG_THERMAL is not set
1215# CONFIG_WATCHDOG is not set
1216CONFIG_SSB_POSSIBLE=y
1217
1218#
1219# Sonics Silicon Backplane
1220#
1221# CONFIG_SSB is not set
1222CONFIG_MFD_SUPPORT=y
1223# CONFIG_MFD_CORE is not set
1224# CONFIG_MFD_88PM860X is not set
1225# CONFIG_MFD_SM501 is not set
1226# CONFIG_HTC_PASIC3 is not set
1227# CONFIG_TPS6105X is not set
1228# CONFIG_TPS6507X is not set
1229# CONFIG_TWL4030_CORE is not set
1230# CONFIG_MFD_STMPE is not set
1231# CONFIG_MFD_TC3589X is not set
1232# CONFIG_MFD_TMIO is not set
1233# CONFIG_PMIC_DA903X is not set
1234# CONFIG_PMIC_ADP5520 is not set
1235# CONFIG_MFD_MAX8925 is not set
1236# CONFIG_MFD_MAX8997 is not set
1237# CONFIG_MFD_MAX8998 is not set
1238# CONFIG_MFD_WM8400 is not set
1239# CONFIG_MFD_WM831X_I2C is not set
1240# CONFIG_MFD_WM8350_I2C is not set
1241# CONFIG_MFD_WM8994 is not set
1242# CONFIG_MFD_PCF50633 is not set
1243# CONFIG_ABX500_CORE is not set
1244# CONFIG_LPC_SCH is not set
1245# CONFIG_MFD_RDC321X is not set
1246# CONFIG_MFD_JANZ_CMODIO is not set
1247# CONFIG_MFD_VX855 is not set
1248# CONFIG_MFD_WL1273_CORE is not set
1249# CONFIG_REGULATOR is not set
1250# CONFIG_MEDIA_SUPPORT is not set
1251
1252#
1253# Graphics support
1254#
1255# CONFIG_VGA_ARB is not set
1256# CONFIG_DRM is not set
1257# CONFIG_STUB_POULSBO is not set
1258# CONFIG_VGASTATE is not set
1259# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1260# CONFIG_FB is not set
1261# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1262
1263#
1264# Display device support
1265#
1266# CONFIG_DISPLAY_SUPPORT is not set
1267# CONFIG_SOUND is not set
1268# CONFIG_HID_SUPPORT is not set
1269# CONFIG_USB_SUPPORT is not set
1270# CONFIG_UWB is not set
1271# CONFIG_MMC is not set
1272# CONFIG_MEMSTICK is not set
1273# CONFIG_NEW_LEDS is not set
1274# CONFIG_NFC_DEVICES is not set
1275# CONFIG_ACCESSIBILITY is not set
1276# CONFIG_INFINIBAND is not set
1277# CONFIG_EDAC is not set
1278CONFIG_RTC_LIB=y
1279CONFIG_RTC_CLASS=y
1280CONFIG_RTC_HCTOSYS=y
1281CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1282# CONFIG_RTC_DEBUG is not set
1283
1284#
1285# RTC interfaces
1286#
1287CONFIG_RTC_INTF_SYSFS=y
1288CONFIG_RTC_INTF_PROC=y
1289CONFIG_RTC_INTF_DEV=y
1290# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1291# CONFIG_RTC_DRV_TEST is not set
1292
1293#
1294# I2C RTC drivers
1295#
1296# CONFIG_RTC_DRV_DS1307 is not set
1297# CONFIG_RTC_DRV_DS1374 is not set
1298# CONFIG_RTC_DRV_DS1672 is not set
1299# CONFIG_RTC_DRV_DS3232 is not set
1300# CONFIG_RTC_DRV_MAX6900 is not set
1301# CONFIG_RTC_DRV_RS5C372 is not set
1302# CONFIG_RTC_DRV_ISL1208 is not set
1303# CONFIG_RTC_DRV_ISL12022 is not set
1304# CONFIG_RTC_DRV_X1205 is not set
1305# CONFIG_RTC_DRV_PCF8563 is not set
1306# CONFIG_RTC_DRV_PCF8583 is not set
1307# CONFIG_RTC_DRV_M41T80 is not set
1308# CONFIG_RTC_DRV_BQ32K is not set
1309# CONFIG_RTC_DRV_S35390A is not set
1310# CONFIG_RTC_DRV_FM3130 is not set
1311# CONFIG_RTC_DRV_RX8581 is not set
1312# CONFIG_RTC_DRV_RX8025 is not set
1313
1314#
1315# SPI RTC drivers
1316#
1317
1318#
1319# Platform RTC drivers
1320#
1321# CONFIG_RTC_DRV_DS1286 is not set
1322# CONFIG_RTC_DRV_DS1511 is not set
1323# CONFIG_RTC_DRV_DS1553 is not set
1324# CONFIG_RTC_DRV_DS1742 is not set
1325# CONFIG_RTC_DRV_STK17TA8 is not set
1326# CONFIG_RTC_DRV_M48T86 is not set
1327# CONFIG_RTC_DRV_M48T35 is not set
1328# CONFIG_RTC_DRV_M48T59 is not set
1329# CONFIG_RTC_DRV_MSM6242 is not set
1330# CONFIG_RTC_DRV_BQ4802 is not set
1331# CONFIG_RTC_DRV_RP5C01 is not set
1332# CONFIG_RTC_DRV_V3020 is not set
1333
1334#
1335# on-CPU RTC drivers
1336#
1337CONFIG_RTC_DRV_TILE=y
1338# CONFIG_DMADEVICES is not set
1339# CONFIG_AUXDISPLAY is not set
1340# CONFIG_UIO is not set
1341# CONFIG_STAGING is not set
1342
1343#
1344# File systems
1345#
1346CONFIG_EXT2_FS=y
1347CONFIG_EXT2_FS_XATTR=y
1348CONFIG_EXT2_FS_POSIX_ACL=y
1349CONFIG_EXT2_FS_SECURITY=y
1350CONFIG_EXT2_FS_XIP=y
1351CONFIG_EXT3_FS=y
1352CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
1353CONFIG_EXT3_FS_XATTR=y
1354CONFIG_EXT3_FS_POSIX_ACL=y
1355CONFIG_EXT3_FS_SECURITY=y
1356CONFIG_EXT4_FS=y
1357CONFIG_EXT4_FS_XATTR=y
1358CONFIG_EXT4_FS_POSIX_ACL=y
1359CONFIG_EXT4_FS_SECURITY=y
1360# CONFIG_EXT4_DEBUG is not set
1361CONFIG_FS_XIP=y
1362CONFIG_JBD=y
1363# CONFIG_JBD_DEBUG is not set
1364CONFIG_JBD2=y
1365CONFIG_JBD2_DEBUG=y
1366CONFIG_FS_MBCACHE=y
1367# CONFIG_REISERFS_FS is not set
1368# CONFIG_JFS_FS is not set
1369CONFIG_XFS_FS=m
1370CONFIG_XFS_QUOTA=y
1371CONFIG_XFS_POSIX_ACL=y
1372# CONFIG_XFS_RT is not set
1373# CONFIG_XFS_DEBUG is not set
1374CONFIG_GFS2_FS=m
1375CONFIG_GFS2_FS_LOCKING_DLM=y
1376# CONFIG_OCFS2_FS is not set
1377CONFIG_BTRFS_FS=m
1378CONFIG_BTRFS_FS_POSIX_ACL=y
1379# CONFIG_NILFS2_FS is not set
1380CONFIG_FS_POSIX_ACL=y
1381CONFIG_EXPORTFS=y
1382CONFIG_FILE_LOCKING=y
1383CONFIG_FSNOTIFY=y
1384CONFIG_DNOTIFY=y
1385CONFIG_INOTIFY_USER=y
1386# CONFIG_FANOTIFY is not set
1387CONFIG_QUOTA=y
1388CONFIG_QUOTA_NETLINK_INTERFACE=y
1389# CONFIG_PRINT_QUOTA_WARNING is not set
1390# CONFIG_QUOTA_DEBUG is not set
1391CONFIG_QUOTA_TREE=y
1392# CONFIG_QFMT_V1 is not set
1393CONFIG_QFMT_V2=y
1394CONFIG_QUOTACTL=y
1395# CONFIG_AUTOFS4_FS is not set
1396CONFIG_FUSE_FS=y
1397CONFIG_CUSE=m
1398CONFIG_GENERIC_ACL=y
1399
1400#
1401# Caches
1402#
1403CONFIG_FSCACHE=m
1404CONFIG_FSCACHE_STATS=y
1405# CONFIG_FSCACHE_HISTOGRAM is not set
1406# CONFIG_FSCACHE_DEBUG is not set
1407# CONFIG_FSCACHE_OBJECT_LIST is not set
1408CONFIG_CACHEFILES=m
1409# CONFIG_CACHEFILES_DEBUG is not set
1410# CONFIG_CACHEFILES_HISTOGRAM is not set
1411
1412#
1413# CD-ROM/DVD Filesystems
1414#
1415CONFIG_ISO9660_FS=m
1416CONFIG_JOLIET=y
1417CONFIG_ZISOFS=y
1418CONFIG_UDF_FS=m
1419CONFIG_UDF_NLS=y
1420
1421#
1422# DOS/FAT/NT Filesystems
1423#
1424CONFIG_FAT_FS=m
1425CONFIG_MSDOS_FS=m
1426CONFIG_VFAT_FS=m
1427CONFIG_FAT_DEFAULT_CODEPAGE=437
1428CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1429# CONFIG_NTFS_FS is not set
1430
1431#
1432# Pseudo filesystems
1433#
1434CONFIG_PROC_FS=y
1435CONFIG_PROC_KCORE=y
1436CONFIG_PROC_SYSCTL=y
1437CONFIG_PROC_PAGE_MONITOR=y
1438CONFIG_SYSFS=y
1439CONFIG_TMPFS=y
1440CONFIG_TMPFS_POSIX_ACL=y
1441CONFIG_HUGETLBFS=y
1442CONFIG_HUGETLB_PAGE=y
1443CONFIG_CONFIGFS_FS=m
1444CONFIG_MISC_FILESYSTEMS=y
1445# CONFIG_ADFS_FS is not set
1446# CONFIG_AFFS_FS is not set
1447CONFIG_ECRYPT_FS=m
1448# CONFIG_HFS_FS is not set
1449# CONFIG_HFSPLUS_FS is not set
1450# CONFIG_BEFS_FS is not set
1451# CONFIG_BFS_FS is not set
1452# CONFIG_EFS_FS is not set
1453# CONFIG_LOGFS is not set
1454CONFIG_CRAMFS=m
1455CONFIG_SQUASHFS=m
1456# CONFIG_SQUASHFS_XATTR is not set
1457# CONFIG_SQUASHFS_LZO is not set
1458# CONFIG_SQUASHFS_XZ is not set
1459# CONFIG_SQUASHFS_EMBEDDED is not set
1460CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
1461# CONFIG_VXFS_FS is not set
1462# CONFIG_MINIX_FS is not set
1463# CONFIG_OMFS_FS is not set
1464# CONFIG_HPFS_FS is not set
1465# CONFIG_QNX4FS_FS is not set
1466# CONFIG_ROMFS_FS is not set
1467# CONFIG_PSTORE is not set
1468# CONFIG_SYSV_FS is not set
1469# CONFIG_UFS_FS is not set
1470CONFIG_NETWORK_FILESYSTEMS=y
1471CONFIG_NFS_FS=m
1472CONFIG_NFS_V3=y
1473CONFIG_NFS_V3_ACL=y
1474CONFIG_NFS_V4=y
1475CONFIG_NFS_V4_1=y
1476CONFIG_PNFS_FILE_LAYOUT=m
1477CONFIG_NFS_FSCACHE=y
1478# CONFIG_NFS_USE_LEGACY_DNS is not set
1479CONFIG_NFS_USE_KERNEL_DNS=y
1480# CONFIG_NFS_USE_NEW_IDMAPPER is not set
1481CONFIG_NFSD=m
1482CONFIG_NFSD_DEPRECATED=y
1483CONFIG_NFSD_V2_ACL=y
1484CONFIG_NFSD_V3=y
1485CONFIG_NFSD_V3_ACL=y
1486CONFIG_NFSD_V4=y
1487CONFIG_LOCKD=m
1488CONFIG_LOCKD_V4=y
1489CONFIG_NFS_ACL_SUPPORT=m
1490CONFIG_NFS_COMMON=y
1491CONFIG_SUNRPC=m
1492CONFIG_SUNRPC_GSS=m
1493CONFIG_RPCSEC_GSS_KRB5=m
1494# CONFIG_CEPH_FS is not set
1495CONFIG_CIFS=m
1496CONFIG_CIFS_STATS=y
1497# CONFIG_CIFS_STATS2 is not set
1498CONFIG_CIFS_WEAK_PW_HASH=y
1499CONFIG_CIFS_UPCALL=y
1500CONFIG_CIFS_XATTR=y
1501CONFIG_CIFS_POSIX=y
1502# CONFIG_CIFS_DEBUG2 is not set
1503CONFIG_CIFS_DFS_UPCALL=y
1504CONFIG_CIFS_FSCACHE=y
1505# CONFIG_CIFS_ACL is not set
1506CONFIG_CIFS_EXPERIMENTAL=y
1507# CONFIG_NCP_FS is not set
1508# CONFIG_CODA_FS is not set
1509# CONFIG_AFS_FS is not set
1510
1511#
1512# Partition Types
1513#
1514CONFIG_PARTITION_ADVANCED=y
1515# CONFIG_ACORN_PARTITION is not set
1516CONFIG_OSF_PARTITION=y
1517CONFIG_AMIGA_PARTITION=y
1518# CONFIG_ATARI_PARTITION is not set
1519CONFIG_MAC_PARTITION=y
1520CONFIG_MSDOS_PARTITION=y
1521CONFIG_BSD_DISKLABEL=y
1522CONFIG_MINIX_SUBPARTITION=y
1523CONFIG_SOLARIS_X86_PARTITION=y
1524CONFIG_UNIXWARE_DISKLABEL=y
1525# CONFIG_LDM_PARTITION is not set
1526CONFIG_SGI_PARTITION=y
1527# CONFIG_ULTRIX_PARTITION is not set
1528CONFIG_SUN_PARTITION=y
1529CONFIG_KARMA_PARTITION=y
1530CONFIG_EFI_PARTITION=y
1531# CONFIG_SYSV68_PARTITION is not set
1532CONFIG_NLS=y
1533CONFIG_NLS_DEFAULT="utf8"
1534CONFIG_NLS_CODEPAGE_437=y
1535CONFIG_NLS_CODEPAGE_737=m
1536CONFIG_NLS_CODEPAGE_775=m
1537CONFIG_NLS_CODEPAGE_850=m
1538CONFIG_NLS_CODEPAGE_852=m
1539CONFIG_NLS_CODEPAGE_855=m
1540CONFIG_NLS_CODEPAGE_857=m
1541CONFIG_NLS_CODEPAGE_860=m
1542CONFIG_NLS_CODEPAGE_861=m
1543CONFIG_NLS_CODEPAGE_862=m
1544CONFIG_NLS_CODEPAGE_863=m
1545CONFIG_NLS_CODEPAGE_864=m
1546CONFIG_NLS_CODEPAGE_865=m
1547CONFIG_NLS_CODEPAGE_866=m
1548CONFIG_NLS_CODEPAGE_869=m
1549CONFIG_NLS_CODEPAGE_936=m
1550CONFIG_NLS_CODEPAGE_950=m
1551CONFIG_NLS_CODEPAGE_932=m
1552CONFIG_NLS_CODEPAGE_949=m
1553CONFIG_NLS_CODEPAGE_874=m
1554CONFIG_NLS_ISO8859_8=m
1555CONFIG_NLS_CODEPAGE_1250=m
1556CONFIG_NLS_CODEPAGE_1251=m
1557CONFIG_NLS_ASCII=y
1558CONFIG_NLS_ISO8859_1=m
1559CONFIG_NLS_ISO8859_2=m
1560CONFIG_NLS_ISO8859_3=m
1561CONFIG_NLS_ISO8859_4=m
1562CONFIG_NLS_ISO8859_5=m
1563CONFIG_NLS_ISO8859_6=m
1564CONFIG_NLS_ISO8859_7=m
1565CONFIG_NLS_ISO8859_9=m
1566CONFIG_NLS_ISO8859_13=m
1567CONFIG_NLS_ISO8859_14=m
1568CONFIG_NLS_ISO8859_15=m
1569CONFIG_NLS_KOI8_R=m
1570CONFIG_NLS_KOI8_U=m
1571CONFIG_NLS_UTF8=m
1572CONFIG_DLM=m
1573CONFIG_DLM_DEBUG=y
1574
1575#
1576# Kernel hacking
1577#
1578# CONFIG_PRINTK_TIME is not set
1579CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
1580# CONFIG_ENABLE_WARN_DEPRECATED is not set
1581CONFIG_ENABLE_MUST_CHECK=y
1582CONFIG_FRAME_WARN=2048
1583CONFIG_MAGIC_SYSRQ=y
1584CONFIG_STRIP_ASM_SYMS=y
1585# CONFIG_UNUSED_SYMBOLS is not set
1586CONFIG_DEBUG_FS=y
1587CONFIG_HEADERS_CHECK=y
1588# CONFIG_DEBUG_SECTION_MISMATCH is not set
1589CONFIG_DEBUG_KERNEL=y
1590CONFIG_DEBUG_SHIRQ=y
1591CONFIG_LOCKUP_DETECTOR=y
1592# CONFIG_HARDLOCKUP_DETECTOR is not set
1593# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
1594CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
1595# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1596CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1597CONFIG_DETECT_HUNG_TASK=y
1598# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1599CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1600CONFIG_SCHED_DEBUG=y
1601CONFIG_SCHEDSTATS=y
1602CONFIG_TIMER_STATS=y
1603# CONFIG_DEBUG_OBJECTS is not set
1604# CONFIG_SLUB_DEBUG_ON is not set
1605# CONFIG_SLUB_STATS is not set
1606# CONFIG_DEBUG_KMEMLEAK is not set
1607# CONFIG_DEBUG_RT_MUTEXES is not set
1608# CONFIG_RT_MUTEX_TESTER is not set
1609# CONFIG_DEBUG_SPINLOCK is not set
1610# CONFIG_DEBUG_MUTEXES is not set
1611# CONFIG_DEBUG_LOCK_ALLOC is not set
1612# CONFIG_PROVE_LOCKING is not set
1613# CONFIG_SPARSE_RCU_POINTER is not set
1614# CONFIG_LOCK_STAT is not set
1615CONFIG_DEBUG_SPINLOCK_SLEEP=y
1616# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1617CONFIG_STACKTRACE=y
1618# CONFIG_DEBUG_KOBJECT is not set
1619CONFIG_DEBUG_INFO=y
1620CONFIG_DEBUG_INFO_REDUCED=y
1621CONFIG_DEBUG_VM=y
1622# CONFIG_DEBUG_WRITECOUNT is not set
1623CONFIG_DEBUG_MEMORY_INIT=y
1624CONFIG_DEBUG_LIST=y
1625# CONFIG_TEST_LIST_SORT is not set
1626# CONFIG_DEBUG_SG is not set
1627# CONFIG_DEBUG_NOTIFIERS is not set
1628CONFIG_DEBUG_CREDENTIALS=y
1629# CONFIG_RCU_TORTURE_TEST is not set
1630# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1631# CONFIG_BACKTRACE_SELF_TEST is not set
1632# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1633CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
1634# CONFIG_LKDTM is not set
1635# CONFIG_FAULT_INJECTION is not set
1636# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1637# CONFIG_DEBUG_PAGEALLOC is not set
1638CONFIG_TRACING_SUPPORT=y
1639CONFIG_FTRACE=y
1640# CONFIG_IRQSOFF_TRACER is not set
1641# CONFIG_SCHED_TRACER is not set
1642# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1643CONFIG_BRANCH_PROFILE_NONE=y
1644# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1645# CONFIG_PROFILE_ALL_BRANCHES is not set
1646# CONFIG_BLK_DEV_IO_TRACE is not set
1647# CONFIG_BUILD_DOCSRC is not set
1648CONFIG_DYNAMIC_DEBUG=y
1649# CONFIG_ATOMIC64_SELFTEST is not set
1650CONFIG_ASYNC_RAID6_TEST=m
1651# CONFIG_SAMPLES is not set
1652# CONFIG_TEST_KSTRTOX is not set
1653CONFIG_EARLY_PRINTK=y
1654CONFIG_DEBUG_STACKOVERFLOW=y
1655# CONFIG_DEBUG_STACK_USAGE is not set
1656CONFIG_DEBUG_EXTRA_FLAGS=""
1657
1658#
1659# Security options
1660#
1661CONFIG_KEYS=y
1662CONFIG_KEYS_DEBUG_PROC_KEYS=y
1663# CONFIG_SECURITY_DMESG_RESTRICT is not set
1664CONFIG_SECURITY=y
1665CONFIG_SECURITYFS=y
1666CONFIG_SECURITY_NETWORK=y
1667CONFIG_SECURITY_NETWORK_XFRM=y
1668# CONFIG_SECURITY_PATH is not set
1669CONFIG_LSM_MMAP_MIN_ADDR=65536
1670CONFIG_SECURITY_SELINUX=y
1671CONFIG_SECURITY_SELINUX_BOOTPARAM=y
1672CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
1673CONFIG_SECURITY_SELINUX_DISABLE=y
1674CONFIG_SECURITY_SELINUX_DEVELOP=y
1675CONFIG_SECURITY_SELINUX_AVC_STATS=y
1676CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
1677# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
1678# CONFIG_SECURITY_SMACK is not set
1679# CONFIG_SECURITY_TOMOYO is not set
1680# CONFIG_SECURITY_APPARMOR is not set
1681# CONFIG_IMA is not set
1682CONFIG_DEFAULT_SECURITY_SELINUX=y
1683# CONFIG_DEFAULT_SECURITY_DAC is not set
1684CONFIG_DEFAULT_SECURITY="selinux"
1685CONFIG_XOR_BLOCKS=m
1686CONFIG_ASYNC_CORE=m
1687CONFIG_ASYNC_MEMCPY=m
1688CONFIG_ASYNC_XOR=m
1689CONFIG_ASYNC_PQ=m
1690CONFIG_ASYNC_RAID6_RECOV=m
1691CONFIG_CRYPTO=y
1692
1693#
1694# Crypto core or helper
1695#
1696CONFIG_CRYPTO_ALGAPI=y
1697CONFIG_CRYPTO_ALGAPI2=y
1698CONFIG_CRYPTO_AEAD=m
1699CONFIG_CRYPTO_AEAD2=y
1700CONFIG_CRYPTO_BLKCIPHER=m
1701CONFIG_CRYPTO_BLKCIPHER2=y
1702CONFIG_CRYPTO_HASH=y
1703CONFIG_CRYPTO_HASH2=y
1704CONFIG_CRYPTO_RNG=m
1705CONFIG_CRYPTO_RNG2=y
1706CONFIG_CRYPTO_PCOMP=m
1707CONFIG_CRYPTO_PCOMP2=y
1708CONFIG_CRYPTO_MANAGER=y
1709CONFIG_CRYPTO_MANAGER2=y
1710CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
1711CONFIG_CRYPTO_GF128MUL=m
1712CONFIG_CRYPTO_NULL=m
1713CONFIG_CRYPTO_PCRYPT=m
1714CONFIG_CRYPTO_WORKQUEUE=y
1715CONFIG_CRYPTO_CRYPTD=m
1716CONFIG_CRYPTO_AUTHENC=m
1717CONFIG_CRYPTO_TEST=m
1718
1719#
1720# Authenticated Encryption with Associated Data
1721#
1722CONFIG_CRYPTO_CCM=m
1723CONFIG_CRYPTO_GCM=m
1724CONFIG_CRYPTO_SEQIV=m
1725
1726#
1727# Block modes
1728#
1729CONFIG_CRYPTO_CBC=m
1730CONFIG_CRYPTO_CTR=m
1731CONFIG_CRYPTO_CTS=m
1732CONFIG_CRYPTO_ECB=m
1733CONFIG_CRYPTO_LRW=m
1734CONFIG_CRYPTO_PCBC=m
1735CONFIG_CRYPTO_XTS=m
1736
1737#
1738# Hash modes
1739#
1740CONFIG_CRYPTO_HMAC=y
1741CONFIG_CRYPTO_XCBC=m
1742CONFIG_CRYPTO_VMAC=m
1743
1744#
1745# Digest
1746#
1747CONFIG_CRYPTO_CRC32C=y
1748CONFIG_CRYPTO_GHASH=m
1749CONFIG_CRYPTO_MD4=m
1750CONFIG_CRYPTO_MD5=y
1751CONFIG_CRYPTO_MICHAEL_MIC=m
1752CONFIG_CRYPTO_RMD128=m
1753CONFIG_CRYPTO_RMD160=m
1754CONFIG_CRYPTO_RMD256=m
1755CONFIG_CRYPTO_RMD320=m
1756CONFIG_CRYPTO_SHA1=y
1757CONFIG_CRYPTO_SHA256=m
1758CONFIG_CRYPTO_SHA512=m
1759CONFIG_CRYPTO_TGR192=m
1760CONFIG_CRYPTO_WP512=m
1761
1762#
1763# Ciphers
1764#
1765CONFIG_CRYPTO_AES=m
1766CONFIG_CRYPTO_ANUBIS=m
1767CONFIG_CRYPTO_ARC4=m
1768CONFIG_CRYPTO_BLOWFISH=m
1769CONFIG_CRYPTO_CAMELLIA=m
1770CONFIG_CRYPTO_CAST5=m
1771CONFIG_CRYPTO_CAST6=m
1772CONFIG_CRYPTO_DES=m
1773CONFIG_CRYPTO_FCRYPT=m
1774CONFIG_CRYPTO_KHAZAD=m
1775# CONFIG_CRYPTO_SALSA20 is not set
1776CONFIG_CRYPTO_SEED=m
1777CONFIG_CRYPTO_SERPENT=m
1778CONFIG_CRYPTO_TEA=m
1779CONFIG_CRYPTO_TWOFISH=m
1780CONFIG_CRYPTO_TWOFISH_COMMON=m
1781
1782#
1783# Compression
1784#
1785CONFIG_CRYPTO_DEFLATE=m
1786CONFIG_CRYPTO_ZLIB=m
1787CONFIG_CRYPTO_LZO=m
1788
1789#
1790# Random Number Generation
1791#
1792CONFIG_CRYPTO_ANSI_CPRNG=m
1793# CONFIG_CRYPTO_USER_API_HASH is not set
1794# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
1795CONFIG_CRYPTO_HW=y
1796CONFIG_CRYPTO_DEV_HIFN_795X=m
1797CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
1798# CONFIG_BINARY_PRINTF is not set
1799
1800#
1801# Library routines
1802#
1803CONFIG_RAID6_PQ=m
1804CONFIG_BITREVERSE=y
1805CONFIG_GENERIC_FIND_FIRST_BIT=y
1806CONFIG_GENERIC_FIND_NEXT_BIT=y
1807CONFIG_GENERIC_FIND_LAST_BIT=y
1808# CONFIG_CRC_CCITT is not set
1809CONFIG_CRC16=y
1810CONFIG_CRC_T10DIF=y
1811CONFIG_CRC_ITU_T=m
1812CONFIG_CRC32=y
1813# CONFIG_CRC7 is not set
1814CONFIG_LIBCRC32C=m
1815CONFIG_AUDIT_GENERIC=y
1816CONFIG_ZLIB_INFLATE=y
1817CONFIG_ZLIB_DEFLATE=m
1818CONFIG_LZO_COMPRESS=m
1819CONFIG_LZO_DECOMPRESS=m
1820# CONFIG_XZ_DEC is not set
1821# CONFIG_XZ_DEC_BCJ is not set
1822CONFIG_DECOMPRESS_GZIP=y
1823CONFIG_TEXTSEARCH=y
1824CONFIG_TEXTSEARCH_KMP=m
1825CONFIG_TEXTSEARCH_BM=m
1826CONFIG_TEXTSEARCH_FSM=m
1827CONFIG_HAS_IOMEM=y
1828CONFIG_HAS_IOPORT=y
1829CONFIG_HAS_DMA=y
1830CONFIG_CPU_RMAP=y
1831CONFIG_NLATTR=y
1832# CONFIG_AVERAGE is not set
1833# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/tile/configs/tilepro_defconfig b/arch/tile/configs/tilepro_defconfig
new file mode 100644
index 000000000000..f58dc362b944
--- /dev/null
+++ b/arch/tile/configs/tilepro_defconfig
@@ -0,0 +1,1163 @@
1#
2# Automatically generated make config: don't edit
3# Linux/tile 2.6.39-rc5 Kernel Configuration
4# Tue May 3 09:15:02 2011
5#
6CONFIG_TILE=y
7CONFIG_MMU=y
8CONFIG_GENERIC_CSUM=y
9CONFIG_SEMAPHORE_SLEEPERS=y
10CONFIG_HAVE_ARCH_ALLOC_REMAP=y
11CONFIG_HAVE_SETUP_PER_CPU_AREA=y
12CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
13CONFIG_SYS_SUPPORTS_HUGETLBFS=y
14CONFIG_GENERIC_TIME=y
15CONFIG_GENERIC_CLOCKEVENTS=y
16CONFIG_RWSEM_GENERIC_SPINLOCK=y
17CONFIG_DEFAULT_MIGRATION_COST=10000000
18CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
19CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
20CONFIG_ARCH_DMA_ADDR_T_64BIT=y
21CONFIG_LOCKDEP_SUPPORT=y
22CONFIG_STACKTRACE_SUPPORT=y
23CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
24CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
25CONFIG_TRACE_IRQFLAGS_SUPPORT=y
26CONFIG_STRICT_DEVMEM=y
27CONFIG_SMP=y
28# CONFIG_DEBUG_COPY_FROM_USER is not set
29CONFIG_HVC_TILE=y
30# CONFIG_TILEGX is not set
31CONFIG_ARCH_DEFCONFIG="arch/tile/configs/tile_defconfig"
32CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
33CONFIG_CONSTRUCTORS=y
34
35#
36# General setup
37#
38CONFIG_EXPERIMENTAL=y
39CONFIG_INIT_ENV_ARG_LIMIT=32
40CONFIG_CROSS_COMPILE=""
41CONFIG_LOCALVERSION=""
42CONFIG_LOCALVERSION_AUTO=y
43# CONFIG_SWAP is not set
44CONFIG_SYSVIPC=y
45CONFIG_SYSVIPC_SYSCTL=y
46# CONFIG_POSIX_MQUEUE is not set
47# CONFIG_BSD_PROCESS_ACCT is not set
48CONFIG_FHANDLE=y
49# CONFIG_TASKSTATS is not set
50# CONFIG_AUDIT is not set
51CONFIG_HAVE_GENERIC_HARDIRQS=y
52
53#
54# IRQ subsystem
55#
56CONFIG_GENERIC_HARDIRQS=y
57CONFIG_GENERIC_IRQ_PROBE=y
58CONFIG_GENERIC_IRQ_SHOW=y
59CONFIG_GENERIC_PENDING_IRQ=y
60
61#
62# RCU Subsystem
63#
64CONFIG_TREE_RCU=y
65# CONFIG_PREEMPT_RCU is not set
66# CONFIG_RCU_TRACE is not set
67CONFIG_RCU_FANOUT=32
68# CONFIG_RCU_FANOUT_EXACT is not set
69# CONFIG_RCU_FAST_NO_HZ is not set
70# CONFIG_TREE_RCU_TRACE is not set
71# CONFIG_IKCONFIG is not set
72CONFIG_LOG_BUF_SHIFT=17
73# CONFIG_CGROUPS is not set
74# CONFIG_NAMESPACES is not set
75# CONFIG_SCHED_AUTOGROUP is not set
76# CONFIG_SYSFS_DEPRECATED is not set
77# CONFIG_RELAY is not set
78CONFIG_BLK_DEV_INITRD=y
79CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
80CONFIG_INITRAMFS_ROOT_UID=0
81CONFIG_INITRAMFS_ROOT_GID=0
82CONFIG_RD_GZIP=y
83# CONFIG_RD_BZIP2 is not set
84# CONFIG_RD_LZMA is not set
85# CONFIG_RD_XZ is not set
86# CONFIG_RD_LZO is not set
87CONFIG_INITRAMFS_COMPRESSION_NONE=y
88# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
89CONFIG_CC_OPTIMIZE_FOR_SIZE=y
90CONFIG_SYSCTL=y
91CONFIG_ANON_INODES=y
92CONFIG_EXPERT=y
93CONFIG_SYSCTL_SYSCALL=y
94CONFIG_KALLSYMS=y
95# CONFIG_KALLSYMS_ALL is not set
96# CONFIG_KALLSYMS_EXTRA_PASS is not set
97CONFIG_HOTPLUG=y
98CONFIG_PRINTK=y
99CONFIG_BUG=y
100CONFIG_ELF_CORE=y
101CONFIG_BASE_FULL=y
102CONFIG_FUTEX=y
103CONFIG_EPOLL=y
104CONFIG_SIGNALFD=y
105CONFIG_TIMERFD=y
106CONFIG_EVENTFD=y
107CONFIG_SHMEM=y
108CONFIG_AIO=y
109CONFIG_EMBEDDED=y
110
111#
112# Kernel Performance Events And Counters
113#
114CONFIG_VM_EVENT_COUNTERS=y
115CONFIG_PCI_QUIRKS=y
116CONFIG_SLUB_DEBUG=y
117# CONFIG_COMPAT_BRK is not set
118# CONFIG_SLAB is not set
119CONFIG_SLUB=y
120# CONFIG_SLOB is not set
121CONFIG_PROFILING=y
122CONFIG_USE_GENERIC_SMP_HELPERS=y
123
124#
125# GCOV-based kernel profiling
126#
127# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
128CONFIG_SLABINFO=y
129CONFIG_RT_MUTEXES=y
130CONFIG_BASE_SMALL=0
131CONFIG_MODULES=y
132# CONFIG_MODULE_FORCE_LOAD is not set
133CONFIG_MODULE_UNLOAD=y
134# CONFIG_MODULE_FORCE_UNLOAD is not set
135# CONFIG_MODVERSIONS is not set
136# CONFIG_MODULE_SRCVERSION_ALL is not set
137CONFIG_STOP_MACHINE=y
138CONFIG_BLOCK=y
139CONFIG_LBDAF=y
140# CONFIG_BLK_DEV_BSG is not set
141# CONFIG_BLK_DEV_INTEGRITY is not set
142
143#
144# IO Schedulers
145#
146CONFIG_IOSCHED_NOOP=y
147# CONFIG_IOSCHED_DEADLINE is not set
148# CONFIG_IOSCHED_CFQ is not set
149CONFIG_DEFAULT_NOOP=y
150CONFIG_DEFAULT_IOSCHED="noop"
151# CONFIG_INLINE_SPIN_TRYLOCK is not set
152# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
153# CONFIG_INLINE_SPIN_LOCK is not set
154# CONFIG_INLINE_SPIN_LOCK_BH is not set
155# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
156# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
157CONFIG_INLINE_SPIN_UNLOCK=y
158# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
159CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
160# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
161# CONFIG_INLINE_READ_TRYLOCK is not set
162# CONFIG_INLINE_READ_LOCK is not set
163# CONFIG_INLINE_READ_LOCK_BH is not set
164# CONFIG_INLINE_READ_LOCK_IRQ is not set
165# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
166CONFIG_INLINE_READ_UNLOCK=y
167# CONFIG_INLINE_READ_UNLOCK_BH is not set
168CONFIG_INLINE_READ_UNLOCK_IRQ=y
169# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
170# CONFIG_INLINE_WRITE_TRYLOCK is not set
171# CONFIG_INLINE_WRITE_LOCK is not set
172# CONFIG_INLINE_WRITE_LOCK_BH is not set
173# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
174# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
175CONFIG_INLINE_WRITE_UNLOCK=y
176# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
177CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
178# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
179CONFIG_MUTEX_SPIN_ON_OWNER=y
180
181#
182# Tilera-specific configuration
183#
184CONFIG_NR_CPUS=64
185CONFIG_TICK_ONESHOT=y
186CONFIG_NO_HZ=y
187CONFIG_HIGH_RES_TIMERS=y
188CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
189CONFIG_HZ_100=y
190# CONFIG_HZ_250 is not set
191# CONFIG_HZ_300 is not set
192# CONFIG_HZ_1000 is not set
193CONFIG_HZ=100
194CONFIG_SCHED_HRTICK=y
195# CONFIG_KEXEC is not set
196CONFIG_HIGHMEM=y
197CONFIG_NUMA=y
198CONFIG_NODES_SHIFT=2
199# CONFIG_VMSPLIT_3_75G is not set
200# CONFIG_VMSPLIT_3_5G is not set
201CONFIG_VMSPLIT_3G=y
202# CONFIG_VMSPLIT_2_75G is not set
203# CONFIG_VMSPLIT_2_5G is not set
204# CONFIG_VMSPLIT_2_25G is not set
205# CONFIG_VMSPLIT_2G is not set
206# CONFIG_VMSPLIT_1G is not set
207CONFIG_PAGE_OFFSET=0xC0000000
208CONFIG_SELECT_MEMORY_MODEL=y
209CONFIG_DISCONTIGMEM_MANUAL=y
210CONFIG_DISCONTIGMEM=y
211CONFIG_FLAT_NODE_MEM_MAP=y
212CONFIG_NEED_MULTIPLE_NODES=y
213CONFIG_PAGEFLAGS_EXTENDED=y
214CONFIG_SPLIT_PTLOCK_CPUS=4
215# CONFIG_COMPACTION is not set
216CONFIG_MIGRATION=y
217CONFIG_PHYS_ADDR_T_64BIT=y
218CONFIG_ZONE_DMA_FLAG=0
219CONFIG_BOUNCE=y
220CONFIG_VIRT_TO_BUS=y
221# CONFIG_KSM is not set
222CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
223# CONFIG_CMDLINE_BOOL is not set
224CONFIG_VMALLOC_RESERVE=0x1000000
225CONFIG_HARDWALL=y
226CONFIG_KERNEL_PL=1
227
228#
229# Bus options
230#
231CONFIG_PCI=y
232CONFIG_PCI_DOMAINS=y
233# CONFIG_NO_IOMEM is not set
234# CONFIG_NO_IOPORT is not set
235# CONFIG_ARCH_SUPPORTS_MSI is not set
236# CONFIG_PCI_DEBUG is not set
237# CONFIG_PCI_STUB is not set
238# CONFIG_PCI_IOV is not set
239# CONFIG_HOTPLUG_PCI is not set
240
241#
242# Executable file formats
243#
244CONFIG_KCORE_ELF=y
245CONFIG_BINFMT_ELF=y
246# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
247# CONFIG_HAVE_AOUT is not set
248# CONFIG_BINFMT_MISC is not set
249CONFIG_NET=y
250
251#
252# Networking options
253#
254CONFIG_PACKET=y
255CONFIG_UNIX=y
256CONFIG_XFRM=y
257# CONFIG_XFRM_USER is not set
258# CONFIG_XFRM_SUB_POLICY is not set
259# CONFIG_XFRM_MIGRATE is not set
260# CONFIG_XFRM_STATISTICS is not set
261# CONFIG_NET_KEY is not set
262CONFIG_INET=y
263CONFIG_IP_MULTICAST=y
264# CONFIG_IP_ADVANCED_ROUTER is not set
265# CONFIG_IP_PNP is not set
266# CONFIG_NET_IPIP is not set
267# CONFIG_NET_IPGRE_DEMUX is not set
268# CONFIG_IP_MROUTE is not set
269# CONFIG_ARPD is not set
270# CONFIG_SYN_COOKIES is not set
271# CONFIG_INET_AH is not set
272# CONFIG_INET_ESP is not set
273# CONFIG_INET_IPCOMP is not set
274# CONFIG_INET_XFRM_TUNNEL is not set
275CONFIG_INET_TUNNEL=y
276# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
277# CONFIG_INET_XFRM_MODE_TUNNEL is not set
278CONFIG_INET_XFRM_MODE_BEET=y
279# CONFIG_INET_LRO is not set
280# CONFIG_INET_DIAG is not set
281# CONFIG_TCP_CONG_ADVANCED is not set
282CONFIG_TCP_CONG_CUBIC=y
283CONFIG_DEFAULT_TCP_CONG="cubic"
284# CONFIG_TCP_MD5SIG is not set
285CONFIG_IPV6=y
286# CONFIG_IPV6_PRIVACY is not set
287# CONFIG_IPV6_ROUTER_PREF is not set
288# CONFIG_IPV6_OPTIMISTIC_DAD is not set
289# CONFIG_INET6_AH is not set
290# CONFIG_INET6_ESP is not set
291# CONFIG_INET6_IPCOMP is not set
292# CONFIG_IPV6_MIP6 is not set
293# CONFIG_INET6_XFRM_TUNNEL is not set
294# CONFIG_INET6_TUNNEL is not set
295CONFIG_INET6_XFRM_MODE_TRANSPORT=y
296CONFIG_INET6_XFRM_MODE_TUNNEL=y
297CONFIG_INET6_XFRM_MODE_BEET=y
298# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
299CONFIG_IPV6_SIT=y
300# CONFIG_IPV6_SIT_6RD is not set
301CONFIG_IPV6_NDISC_NODETYPE=y
302# CONFIG_IPV6_TUNNEL is not set
303# CONFIG_IPV6_MULTIPLE_TABLES is not set
304# CONFIG_IPV6_MROUTE is not set
305# CONFIG_NETWORK_SECMARK is not set
306# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
307# CONFIG_NETFILTER is not set
308# CONFIG_IP_DCCP is not set
309# CONFIG_IP_SCTP is not set
310# CONFIG_RDS is not set
311# CONFIG_TIPC is not set
312# CONFIG_ATM is not set
313# CONFIG_L2TP is not set
314# CONFIG_BRIDGE is not set
315# CONFIG_NET_DSA is not set
316# CONFIG_VLAN_8021Q is not set
317# CONFIG_DECNET is not set
318# CONFIG_LLC2 is not set
319# CONFIG_IPX is not set
320# CONFIG_ATALK is not set
321# CONFIG_X25 is not set
322# CONFIG_LAPB is not set
323# CONFIG_ECONET is not set
324# CONFIG_WAN_ROUTER is not set
325# CONFIG_PHONET is not set
326# CONFIG_IEEE802154 is not set
327# CONFIG_NET_SCHED is not set
328# CONFIG_DCB is not set
329# CONFIG_BATMAN_ADV is not set
330CONFIG_RPS=y
331CONFIG_RFS_ACCEL=y
332CONFIG_XPS=y
333
334#
335# Network testing
336#
337# CONFIG_NET_PKTGEN is not set
338# CONFIG_HAMRADIO is not set
339# CONFIG_CAN is not set
340# CONFIG_IRDA is not set
341# CONFIG_BT is not set
342# CONFIG_AF_RXRPC is not set
343# CONFIG_WIRELESS is not set
344# CONFIG_WIMAX is not set
345# CONFIG_RFKILL is not set
346# CONFIG_NET_9P is not set
347# CONFIG_CAIF is not set
348# CONFIG_CEPH_LIB is not set
349
350#
351# Device Drivers
352#
353
354#
355# Generic Driver Options
356#
357CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
358# CONFIG_DEVTMPFS is not set
359CONFIG_STANDALONE=y
360CONFIG_PREVENT_FIRMWARE_BUILD=y
361CONFIG_FW_LOADER=y
362CONFIG_FIRMWARE_IN_KERNEL=y
363CONFIG_EXTRA_FIRMWARE=""
364# CONFIG_DEBUG_DRIVER is not set
365# CONFIG_DEBUG_DEVRES is not set
366# CONFIG_SYS_HYPERVISOR is not set
367# CONFIG_CONNECTOR is not set
368# CONFIG_MTD is not set
369# CONFIG_PARPORT is not set
370CONFIG_BLK_DEV=y
371# CONFIG_BLK_CPQ_DA is not set
372# CONFIG_BLK_CPQ_CISS_DA is not set
373# CONFIG_BLK_DEV_DAC960 is not set
374# CONFIG_BLK_DEV_UMEM is not set
375# CONFIG_BLK_DEV_COW_COMMON is not set
376# CONFIG_BLK_DEV_LOOP is not set
377
378#
379# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
380#
381# CONFIG_BLK_DEV_NBD is not set
382# CONFIG_BLK_DEV_SX8 is not set
383# CONFIG_BLK_DEV_RAM is not set
384# CONFIG_CDROM_PKTCDVD is not set
385# CONFIG_ATA_OVER_ETH is not set
386# CONFIG_BLK_DEV_RBD is not set
387# CONFIG_SENSORS_LIS3LV02D is not set
388CONFIG_MISC_DEVICES=y
389# CONFIG_PHANTOM is not set
390# CONFIG_SGI_IOC4 is not set
391# CONFIG_TIFM_CORE is not set
392# CONFIG_ENCLOSURE_SERVICES is not set
393# CONFIG_HP_ILO is not set
394# CONFIG_PCH_PHUB is not set
395# CONFIG_C2PORT is not set
396
397#
398# EEPROM support
399#
400# CONFIG_EEPROM_93CX6 is not set
401# CONFIG_CB710_CORE is not set
402
403#
404# Texas Instruments shared transport line discipline
405#
406
407#
408# SCSI device support
409#
410CONFIG_SCSI_MOD=y
411# CONFIG_RAID_ATTRS is not set
412CONFIG_SCSI=y
413CONFIG_SCSI_DMA=y
414# CONFIG_SCSI_TGT is not set
415# CONFIG_SCSI_NETLINK is not set
416CONFIG_SCSI_PROC_FS=y
417
418#
419# SCSI support type (disk, tape, CD-ROM)
420#
421CONFIG_BLK_DEV_SD=y
422# CONFIG_CHR_DEV_ST is not set
423# CONFIG_CHR_DEV_OSST is not set
424# CONFIG_BLK_DEV_SR is not set
425# CONFIG_CHR_DEV_SG is not set
426# CONFIG_CHR_DEV_SCH is not set
427# CONFIG_SCSI_MULTI_LUN is not set
428CONFIG_SCSI_CONSTANTS=y
429CONFIG_SCSI_LOGGING=y
430# CONFIG_SCSI_SCAN_ASYNC is not set
431CONFIG_SCSI_WAIT_SCAN=m
432
433#
434# SCSI Transports
435#
436# CONFIG_SCSI_SPI_ATTRS is not set
437# CONFIG_SCSI_FC_ATTRS is not set
438# CONFIG_SCSI_ISCSI_ATTRS is not set
439# CONFIG_SCSI_SAS_ATTRS is not set
440# CONFIG_SCSI_SAS_LIBSAS is not set
441# CONFIG_SCSI_SRP_ATTRS is not set
442CONFIG_SCSI_LOWLEVEL=y
443# CONFIG_ISCSI_TCP is not set
444# CONFIG_ISCSI_BOOT_SYSFS is not set
445# CONFIG_SCSI_CXGB3_ISCSI is not set
446# CONFIG_SCSI_CXGB4_ISCSI is not set
447# CONFIG_SCSI_BNX2_ISCSI is not set
448# CONFIG_SCSI_BNX2X_FCOE is not set
449# CONFIG_BE2ISCSI is not set
450# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
451# CONFIG_SCSI_HPSA is not set
452# CONFIG_SCSI_3W_9XXX is not set
453# CONFIG_SCSI_3W_SAS is not set
454# CONFIG_SCSI_ACARD is not set
455# CONFIG_SCSI_AACRAID is not set
456# CONFIG_SCSI_AIC7XXX is not set
457# CONFIG_SCSI_AIC7XXX_OLD is not set
458# CONFIG_SCSI_AIC79XX is not set
459# CONFIG_SCSI_AIC94XX is not set
460# CONFIG_SCSI_MVSAS is not set
461# CONFIG_SCSI_DPT_I2O is not set
462# CONFIG_SCSI_ADVANSYS is not set
463# CONFIG_SCSI_ARCMSR is not set
464# CONFIG_MEGARAID_NEWGEN is not set
465# CONFIG_MEGARAID_LEGACY is not set
466# CONFIG_MEGARAID_SAS is not set
467# CONFIG_SCSI_MPT2SAS is not set
468# CONFIG_SCSI_HPTIOP is not set
469# CONFIG_LIBFC is not set
470# CONFIG_LIBFCOE is not set
471# CONFIG_FCOE is not set
472# CONFIG_SCSI_DMX3191D is not set
473# CONFIG_SCSI_FUTURE_DOMAIN is not set
474# CONFIG_SCSI_IPS is not set
475# CONFIG_SCSI_INITIO is not set
476# CONFIG_SCSI_INIA100 is not set
477# CONFIG_SCSI_STEX is not set
478# CONFIG_SCSI_SYM53C8XX_2 is not set
479# CONFIG_SCSI_QLOGIC_1280 is not set
480# CONFIG_SCSI_QLA_FC is not set
481# CONFIG_SCSI_QLA_ISCSI is not set
482# CONFIG_SCSI_LPFC is not set
483# CONFIG_SCSI_DC395x is not set
484# CONFIG_SCSI_DC390T is not set
485# CONFIG_SCSI_NSP32 is not set
486# CONFIG_SCSI_DEBUG is not set
487# CONFIG_SCSI_PMCRAID is not set
488# CONFIG_SCSI_PM8001 is not set
489# CONFIG_SCSI_SRP is not set
490# CONFIG_SCSI_BFA_FC is not set
491# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
492# CONFIG_SCSI_DH is not set
493# CONFIG_SCSI_OSD_INITIATOR is not set
494# CONFIG_ATA is not set
495# CONFIG_MD is not set
496# CONFIG_TARGET_CORE is not set
497# CONFIG_FUSION is not set
498
499#
500# IEEE 1394 (FireWire) support
501#
502# CONFIG_FIREWIRE is not set
503# CONFIG_FIREWIRE_NOSY is not set
504# CONFIG_I2O is not set
505CONFIG_NETDEVICES=y
506# CONFIG_DUMMY is not set
507# CONFIG_BONDING is not set
508# CONFIG_MACVLAN is not set
509# CONFIG_EQUALIZER is not set
510CONFIG_TUN=y
511# CONFIG_VETH is not set
512# CONFIG_ARCNET is not set
513# CONFIG_MII is not set
514# CONFIG_PHYLIB is not set
515# CONFIG_NET_ETHERNET is not set
516CONFIG_NETDEV_1000=y
517# CONFIG_ACENIC is not set
518# CONFIG_DL2K is not set
519# CONFIG_E1000 is not set
520# CONFIG_E1000E is not set
521# CONFIG_IP1000 is not set
522# CONFIG_IGB is not set
523# CONFIG_IGBVF is not set
524# CONFIG_NS83820 is not set
525# CONFIG_HAMACHI is not set
526# CONFIG_YELLOWFIN is not set
527# CONFIG_R8169 is not set
528# CONFIG_SIS190 is not set
529# CONFIG_SKGE is not set
530# CONFIG_SKY2 is not set
531# CONFIG_VIA_VELOCITY is not set
532# CONFIG_TIGON3 is not set
533# CONFIG_BNX2 is not set
534# CONFIG_CNIC is not set
535# CONFIG_QLA3XXX is not set
536# CONFIG_ATL1 is not set
537# CONFIG_ATL1E is not set
538# CONFIG_ATL1C is not set
539# CONFIG_JME is not set
540# CONFIG_STMMAC_ETH is not set
541# CONFIG_PCH_GBE is not set
542# CONFIG_NETDEV_10000 is not set
543# CONFIG_TR is not set
544# CONFIG_WLAN is not set
545
546#
547# Enable WiMAX (Networking options) to see the WiMAX drivers
548#
549# CONFIG_WAN is not set
550
551#
552# CAIF transport drivers
553#
554CONFIG_TILE_NET=y
555# CONFIG_FDDI is not set
556# CONFIG_HIPPI is not set
557# CONFIG_PPP is not set
558# CONFIG_SLIP is not set
559# CONFIG_NET_FC is not set
560# CONFIG_NETCONSOLE is not set
561# CONFIG_NETPOLL is not set
562# CONFIG_NET_POLL_CONTROLLER is not set
563# CONFIG_VMXNET3 is not set
564# CONFIG_ISDN is not set
565# CONFIG_PHONE is not set
566
567#
568# Input device support
569#
570CONFIG_INPUT=y
571# CONFIG_INPUT_FF_MEMLESS is not set
572# CONFIG_INPUT_POLLDEV is not set
573# CONFIG_INPUT_SPARSEKMAP is not set
574
575#
576# Userland interfaces
577#
578# CONFIG_INPUT_MOUSEDEV is not set
579# CONFIG_INPUT_JOYDEV is not set
580# CONFIG_INPUT_EVDEV is not set
581# CONFIG_INPUT_EVBUG is not set
582
583#
584# Input Device Drivers
585#
586# CONFIG_INPUT_KEYBOARD is not set
587# CONFIG_INPUT_MOUSE is not set
588# CONFIG_INPUT_JOYSTICK is not set
589# CONFIG_INPUT_TABLET is not set
590# CONFIG_INPUT_TOUCHSCREEN is not set
591# CONFIG_INPUT_MISC is not set
592
593#
594# Hardware I/O ports
595#
596# CONFIG_SERIO is not set
597# CONFIG_GAMEPORT is not set
598
599#
600# Character devices
601#
602# CONFIG_VT is not set
603CONFIG_UNIX98_PTYS=y
604# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
605# CONFIG_LEGACY_PTYS is not set
606# CONFIG_SERIAL_NONSTANDARD is not set
607# CONFIG_NOZOMI is not set
608# CONFIG_N_GSM is not set
609CONFIG_DEVKMEM=y
610
611#
612# Serial drivers
613#
614# CONFIG_SERIAL_8250 is not set
615
616#
617# Non-8250 serial port support
618#
619# CONFIG_SERIAL_MFD_HSU is not set
620# CONFIG_SERIAL_JSM is not set
621# CONFIG_SERIAL_TIMBERDALE is not set
622# CONFIG_SERIAL_ALTERA_JTAGUART is not set
623# CONFIG_SERIAL_ALTERA_UART is not set
624# CONFIG_SERIAL_PCH_UART is not set
625# CONFIG_TTY_PRINTK is not set
626CONFIG_HVC_DRIVER=y
627# CONFIG_IPMI_HANDLER is not set
628# CONFIG_HW_RANDOM is not set
629# CONFIG_R3964 is not set
630# CONFIG_APPLICOM is not set
631
632#
633# PCMCIA character devices
634#
635# CONFIG_RAW_DRIVER is not set
636# CONFIG_TCG_TPM is not set
637CONFIG_DEVPORT=y
638# CONFIG_RAMOOPS is not set
639# CONFIG_I2C is not set
640# CONFIG_SPI is not set
641
642#
643# PPS support
644#
645# CONFIG_PPS is not set
646
647#
648# PPS generators support
649#
650# CONFIG_W1 is not set
651# CONFIG_POWER_SUPPLY is not set
652CONFIG_HWMON=y
653# CONFIG_HWMON_VID is not set
654# CONFIG_HWMON_DEBUG_CHIP is not set
655
656#
657# Native drivers
658#
659# CONFIG_SENSORS_I5K_AMB is not set
660# CONFIG_SENSORS_F71805F is not set
661# CONFIG_SENSORS_F71882FG is not set
662# CONFIG_SENSORS_IT87 is not set
663# CONFIG_SENSORS_PC87360 is not set
664# CONFIG_SENSORS_PC87427 is not set
665# CONFIG_SENSORS_SIS5595 is not set
666# CONFIG_SENSORS_SMSC47M1 is not set
667# CONFIG_SENSORS_SMSC47B397 is not set
668# CONFIG_SENSORS_SCH5627 is not set
669# CONFIG_SENSORS_VIA686A is not set
670# CONFIG_SENSORS_VT1211 is not set
671# CONFIG_SENSORS_VT8231 is not set
672# CONFIG_SENSORS_W83627HF is not set
673# CONFIG_SENSORS_W83627EHF is not set
674# CONFIG_THERMAL is not set
675CONFIG_WATCHDOG=y
676CONFIG_WATCHDOG_NOWAYOUT=y
677
678#
679# Watchdog Device Drivers
680#
681# CONFIG_SOFT_WATCHDOG is not set
682# CONFIG_ALIM7101_WDT is not set
683
684#
685# PCI-based Watchdog Cards
686#
687# CONFIG_PCIPCWATCHDOG is not set
688# CONFIG_WDTPCI is not set
689CONFIG_SSB_POSSIBLE=y
690
691#
692# Sonics Silicon Backplane
693#
694# CONFIG_SSB is not set
695CONFIG_MFD_SUPPORT=y
696# CONFIG_MFD_CORE is not set
697# CONFIG_MFD_SM501 is not set
698# CONFIG_HTC_PASIC3 is not set
699# CONFIG_MFD_TMIO is not set
700# CONFIG_ABX500_CORE is not set
701# CONFIG_LPC_SCH is not set
702# CONFIG_MFD_RDC321X is not set
703# CONFIG_MFD_JANZ_CMODIO is not set
704# CONFIG_MFD_VX855 is not set
705# CONFIG_REGULATOR is not set
706# CONFIG_MEDIA_SUPPORT is not set
707
708#
709# Graphics support
710#
711CONFIG_VGA_ARB=y
712CONFIG_VGA_ARB_MAX_GPUS=16
713# CONFIG_DRM is not set
714# CONFIG_STUB_POULSBO is not set
715# CONFIG_VGASTATE is not set
716# CONFIG_VIDEO_OUTPUT_CONTROL is not set
717# CONFIG_FB is not set
718# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
719
720#
721# Display device support
722#
723# CONFIG_DISPLAY_SUPPORT is not set
724# CONFIG_SOUND is not set
725# CONFIG_HID_SUPPORT is not set
726CONFIG_USB_SUPPORT=y
727CONFIG_USB_ARCH_HAS_HCD=y
728CONFIG_USB_ARCH_HAS_OHCI=y
729CONFIG_USB_ARCH_HAS_EHCI=y
730# CONFIG_USB is not set
731# CONFIG_USB_OTG_WHITELIST is not set
732# CONFIG_USB_OTG_BLACKLIST_HUB is not set
733
734#
735# Enable Host or Gadget support to see Inventra options
736#
737
738#
739# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
740#
741# CONFIG_USB_GADGET is not set
742
743#
744# OTG and related infrastructure
745#
746# CONFIG_UWB is not set
747# CONFIG_MMC is not set
748# CONFIG_MEMSTICK is not set
749# CONFIG_NEW_LEDS is not set
750# CONFIG_NFC_DEVICES is not set
751# CONFIG_ACCESSIBILITY is not set
752# CONFIG_INFINIBAND is not set
753CONFIG_EDAC=y
754
755#
756# Reporting subsystems
757#
758# CONFIG_EDAC_DEBUG is not set
759CONFIG_EDAC_MM_EDAC=y
760CONFIG_EDAC_TILE=y
761CONFIG_RTC_LIB=y
762CONFIG_RTC_CLASS=y
763CONFIG_RTC_HCTOSYS=y
764CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
765# CONFIG_RTC_DEBUG is not set
766
767#
768# RTC interfaces
769#
770# CONFIG_RTC_INTF_SYSFS is not set
771# CONFIG_RTC_INTF_PROC is not set
772CONFIG_RTC_INTF_DEV=y
773# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
774# CONFIG_RTC_DRV_TEST is not set
775
776#
777# SPI RTC drivers
778#
779
780#
781# Platform RTC drivers
782#
783# CONFIG_RTC_DRV_DS1286 is not set
784# CONFIG_RTC_DRV_DS1511 is not set
785# CONFIG_RTC_DRV_DS1553 is not set
786# CONFIG_RTC_DRV_DS1742 is not set
787# CONFIG_RTC_DRV_STK17TA8 is not set
788# CONFIG_RTC_DRV_M48T86 is not set
789# CONFIG_RTC_DRV_M48T35 is not set
790# CONFIG_RTC_DRV_M48T59 is not set
791# CONFIG_RTC_DRV_MSM6242 is not set
792# CONFIG_RTC_DRV_BQ4802 is not set
793# CONFIG_RTC_DRV_RP5C01 is not set
794# CONFIG_RTC_DRV_V3020 is not set
795
796#
797# on-CPU RTC drivers
798#
799CONFIG_RTC_DRV_TILE=y
800# CONFIG_DMADEVICES is not set
801# CONFIG_AUXDISPLAY is not set
802# CONFIG_UIO is not set
803# CONFIG_STAGING is not set
804
805#
806# File systems
807#
808CONFIG_EXT2_FS=y
809# CONFIG_EXT2_FS_XATTR is not set
810# CONFIG_EXT2_FS_XIP is not set
811CONFIG_EXT3_FS=y
812# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
813CONFIG_EXT3_FS_XATTR=y
814# CONFIG_EXT3_FS_POSIX_ACL is not set
815# CONFIG_EXT3_FS_SECURITY is not set
816# CONFIG_EXT4_FS is not set
817CONFIG_JBD=y
818CONFIG_FS_MBCACHE=y
819# CONFIG_REISERFS_FS is not set
820# CONFIG_JFS_FS is not set
821# CONFIG_XFS_FS is not set
822# CONFIG_GFS2_FS is not set
823# CONFIG_BTRFS_FS is not set
824# CONFIG_NILFS2_FS is not set
825# CONFIG_FS_POSIX_ACL is not set
826CONFIG_EXPORTFS=y
827CONFIG_FILE_LOCKING=y
828CONFIG_FSNOTIFY=y
829CONFIG_DNOTIFY=y
830CONFIG_INOTIFY_USER=y
831# CONFIG_FANOTIFY is not set
832# CONFIG_QUOTA is not set
833# CONFIG_QUOTACTL is not set
834# CONFIG_AUTOFS4_FS is not set
835CONFIG_FUSE_FS=y
836# CONFIG_CUSE is not set
837
838#
839# Caches
840#
841# CONFIG_FSCACHE is not set
842
843#
844# CD-ROM/DVD Filesystems
845#
846# CONFIG_ISO9660_FS is not set
847# CONFIG_UDF_FS is not set
848
849#
850# DOS/FAT/NT Filesystems
851#
852CONFIG_FAT_FS=y
853CONFIG_MSDOS_FS=y
854CONFIG_VFAT_FS=m
855CONFIG_FAT_DEFAULT_CODEPAGE=437
856CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
857# CONFIG_NTFS_FS is not set
858
859#
860# Pseudo filesystems
861#
862CONFIG_PROC_FS=y
863# CONFIG_PROC_KCORE is not set
864CONFIG_PROC_SYSCTL=y
865CONFIG_PROC_PAGE_MONITOR=y
866CONFIG_SYSFS=y
867CONFIG_TMPFS=y
868# CONFIG_TMPFS_POSIX_ACL is not set
869CONFIG_HUGETLBFS=y
870CONFIG_HUGETLB_PAGE=y
871# CONFIG_CONFIGFS_FS is not set
872CONFIG_MISC_FILESYSTEMS=y
873# CONFIG_ADFS_FS is not set
874# CONFIG_AFFS_FS is not set
875# CONFIG_HFS_FS is not set
876# CONFIG_HFSPLUS_FS is not set
877# CONFIG_BEFS_FS is not set
878# CONFIG_BFS_FS is not set
879# CONFIG_EFS_FS is not set
880# CONFIG_LOGFS is not set
881# CONFIG_CRAMFS is not set
882# CONFIG_SQUASHFS is not set
883# CONFIG_VXFS_FS is not set
884# CONFIG_MINIX_FS is not set
885# CONFIG_OMFS_FS is not set
886# CONFIG_HPFS_FS is not set
887# CONFIG_QNX4FS_FS is not set
888# CONFIG_ROMFS_FS is not set
889# CONFIG_PSTORE is not set
890# CONFIG_SYSV_FS is not set
891# CONFIG_UFS_FS is not set
892CONFIG_NETWORK_FILESYSTEMS=y
893CONFIG_NFS_FS=m
894CONFIG_NFS_V3=y
895# CONFIG_NFS_V3_ACL is not set
896# CONFIG_NFS_V4 is not set
897# CONFIG_NFSD is not set
898CONFIG_LOCKD=m
899CONFIG_LOCKD_V4=y
900CONFIG_NFS_COMMON=y
901CONFIG_SUNRPC=m
902# CONFIG_RPCSEC_GSS_KRB5 is not set
903# CONFIG_CEPH_FS is not set
904# CONFIG_CIFS is not set
905# CONFIG_NCP_FS is not set
906# CONFIG_CODA_FS is not set
907# CONFIG_AFS_FS is not set
908
909#
910# Partition Types
911#
912# CONFIG_PARTITION_ADVANCED is not set
913CONFIG_MSDOS_PARTITION=y
914CONFIG_NLS=y
915CONFIG_NLS_DEFAULT="iso8859-1"
916CONFIG_NLS_CODEPAGE_437=y
917# CONFIG_NLS_CODEPAGE_737 is not set
918# CONFIG_NLS_CODEPAGE_775 is not set
919# CONFIG_NLS_CODEPAGE_850 is not set
920# CONFIG_NLS_CODEPAGE_852 is not set
921# CONFIG_NLS_CODEPAGE_855 is not set
922# CONFIG_NLS_CODEPAGE_857 is not set
923# CONFIG_NLS_CODEPAGE_860 is not set
924# CONFIG_NLS_CODEPAGE_861 is not set
925# CONFIG_NLS_CODEPAGE_862 is not set
926# CONFIG_NLS_CODEPAGE_863 is not set
927# CONFIG_NLS_CODEPAGE_864 is not set
928# CONFIG_NLS_CODEPAGE_865 is not set
929# CONFIG_NLS_CODEPAGE_866 is not set
930# CONFIG_NLS_CODEPAGE_869 is not set
931# CONFIG_NLS_CODEPAGE_936 is not set
932# CONFIG_NLS_CODEPAGE_950 is not set
933# CONFIG_NLS_CODEPAGE_932 is not set
934# CONFIG_NLS_CODEPAGE_949 is not set
935# CONFIG_NLS_CODEPAGE_874 is not set
936# CONFIG_NLS_ISO8859_8 is not set
937# CONFIG_NLS_CODEPAGE_1250 is not set
938# CONFIG_NLS_CODEPAGE_1251 is not set
939# CONFIG_NLS_ASCII is not set
940CONFIG_NLS_ISO8859_1=y
941# CONFIG_NLS_ISO8859_2 is not set
942# CONFIG_NLS_ISO8859_3 is not set
943# CONFIG_NLS_ISO8859_4 is not set
944# CONFIG_NLS_ISO8859_5 is not set
945# CONFIG_NLS_ISO8859_6 is not set
946# CONFIG_NLS_ISO8859_7 is not set
947# CONFIG_NLS_ISO8859_9 is not set
948# CONFIG_NLS_ISO8859_13 is not set
949# CONFIG_NLS_ISO8859_14 is not set
950# CONFIG_NLS_ISO8859_15 is not set
951# CONFIG_NLS_KOI8_R is not set
952# CONFIG_NLS_KOI8_U is not set
953# CONFIG_NLS_UTF8 is not set
954
955#
956# Kernel hacking
957#
958# CONFIG_PRINTK_TIME is not set
959CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
960CONFIG_ENABLE_WARN_DEPRECATED=y
961CONFIG_ENABLE_MUST_CHECK=y
962CONFIG_FRAME_WARN=2048
963CONFIG_MAGIC_SYSRQ=y
964# CONFIG_STRIP_ASM_SYMS is not set
965# CONFIG_UNUSED_SYMBOLS is not set
966# CONFIG_DEBUG_FS is not set
967# CONFIG_HEADERS_CHECK is not set
968# CONFIG_DEBUG_SECTION_MISMATCH is not set
969CONFIG_DEBUG_KERNEL=y
970# CONFIG_DEBUG_SHIRQ is not set
971# CONFIG_LOCKUP_DETECTOR is not set
972# CONFIG_HARDLOCKUP_DETECTOR is not set
973CONFIG_DETECT_HUNG_TASK=y
974# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
975CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
976CONFIG_SCHED_DEBUG=y
977# CONFIG_SCHEDSTATS is not set
978# CONFIG_TIMER_STATS is not set
979# CONFIG_DEBUG_OBJECTS is not set
980# CONFIG_SLUB_DEBUG_ON is not set
981# CONFIG_SLUB_STATS is not set
982# CONFIG_DEBUG_KMEMLEAK is not set
983# CONFIG_DEBUG_RT_MUTEXES is not set
984# CONFIG_RT_MUTEX_TESTER is not set
985# CONFIG_DEBUG_SPINLOCK is not set
986# CONFIG_DEBUG_MUTEXES is not set
987# CONFIG_DEBUG_LOCK_ALLOC is not set
988# CONFIG_PROVE_LOCKING is not set
989# CONFIG_SPARSE_RCU_POINTER is not set
990# CONFIG_LOCK_STAT is not set
991CONFIG_DEBUG_SPINLOCK_SLEEP=y
992# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
993CONFIG_STACKTRACE=y
994# CONFIG_DEBUG_KOBJECT is not set
995# CONFIG_DEBUG_HIGHMEM is not set
996CONFIG_DEBUG_INFO=y
997# CONFIG_DEBUG_INFO_REDUCED is not set
998CONFIG_DEBUG_VM=y
999# CONFIG_DEBUG_WRITECOUNT is not set
1000# CONFIG_DEBUG_MEMORY_INIT is not set
1001# CONFIG_DEBUG_LIST is not set
1002# CONFIG_TEST_LIST_SORT is not set
1003# CONFIG_DEBUG_SG is not set
1004# CONFIG_DEBUG_NOTIFIERS is not set
1005# CONFIG_DEBUG_CREDENTIALS is not set
1006# CONFIG_RCU_TORTURE_TEST is not set
1007# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1008# CONFIG_BACKTRACE_SELF_TEST is not set
1009# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1010# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1011# CONFIG_FAULT_INJECTION is not set
1012# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1013# CONFIG_DEBUG_PAGEALLOC is not set
1014CONFIG_TRACING_SUPPORT=y
1015CONFIG_FTRACE=y
1016# CONFIG_IRQSOFF_TRACER is not set
1017# CONFIG_SCHED_TRACER is not set
1018# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1019CONFIG_BRANCH_PROFILE_NONE=y
1020# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1021# CONFIG_PROFILE_ALL_BRANCHES is not set
1022# CONFIG_BLK_DEV_IO_TRACE is not set
1023# CONFIG_ATOMIC64_SELFTEST is not set
1024# CONFIG_SAMPLES is not set
1025# CONFIG_TEST_KSTRTOX is not set
1026CONFIG_EARLY_PRINTK=y
1027CONFIG_DEBUG_STACKOVERFLOW=y
1028# CONFIG_DEBUG_STACK_USAGE is not set
1029CONFIG_DEBUG_EXTRA_FLAGS="-femit-struct-debug-baseonly"
1030
1031#
1032# Security options
1033#
1034# CONFIG_KEYS is not set
1035# CONFIG_SECURITY_DMESG_RESTRICT is not set
1036# CONFIG_SECURITY is not set
1037# CONFIG_SECURITYFS is not set
1038CONFIG_DEFAULT_SECURITY_DAC=y
1039CONFIG_DEFAULT_SECURITY=""
1040CONFIG_CRYPTO=y
1041
1042#
1043# Crypto core or helper
1044#
1045# CONFIG_CRYPTO_FIPS is not set
1046CONFIG_CRYPTO_ALGAPI=m
1047CONFIG_CRYPTO_ALGAPI2=m
1048CONFIG_CRYPTO_RNG=m
1049CONFIG_CRYPTO_RNG2=m
1050# CONFIG_CRYPTO_MANAGER is not set
1051# CONFIG_CRYPTO_MANAGER2 is not set
1052# CONFIG_CRYPTO_GF128MUL is not set
1053# CONFIG_CRYPTO_NULL is not set
1054# CONFIG_CRYPTO_PCRYPT is not set
1055# CONFIG_CRYPTO_CRYPTD is not set
1056# CONFIG_CRYPTO_AUTHENC is not set
1057# CONFIG_CRYPTO_TEST is not set
1058
1059#
1060# Authenticated Encryption with Associated Data
1061#
1062# CONFIG_CRYPTO_CCM is not set
1063# CONFIG_CRYPTO_GCM is not set
1064# CONFIG_CRYPTO_SEQIV is not set
1065
1066#
1067# Block modes
1068#
1069# CONFIG_CRYPTO_CBC is not set
1070# CONFIG_CRYPTO_CTR is not set
1071# CONFIG_CRYPTO_CTS is not set
1072# CONFIG_CRYPTO_ECB is not set
1073# CONFIG_CRYPTO_LRW is not set
1074# CONFIG_CRYPTO_PCBC is not set
1075# CONFIG_CRYPTO_XTS is not set
1076
1077#
1078# Hash modes
1079#
1080# CONFIG_CRYPTO_HMAC is not set
1081# CONFIG_CRYPTO_XCBC is not set
1082# CONFIG_CRYPTO_VMAC is not set
1083
1084#
1085# Digest
1086#
1087# CONFIG_CRYPTO_CRC32C is not set
1088# CONFIG_CRYPTO_GHASH is not set
1089# CONFIG_CRYPTO_MD4 is not set
1090# CONFIG_CRYPTO_MD5 is not set
1091# CONFIG_CRYPTO_MICHAEL_MIC is not set
1092# CONFIG_CRYPTO_RMD128 is not set
1093# CONFIG_CRYPTO_RMD160 is not set
1094# CONFIG_CRYPTO_RMD256 is not set
1095# CONFIG_CRYPTO_RMD320 is not set
1096# CONFIG_CRYPTO_SHA1 is not set
1097# CONFIG_CRYPTO_SHA256 is not set
1098# CONFIG_CRYPTO_SHA512 is not set
1099# CONFIG_CRYPTO_TGR192 is not set
1100# CONFIG_CRYPTO_WP512 is not set
1101
1102#
1103# Ciphers
1104#
1105CONFIG_CRYPTO_AES=m
1106# CONFIG_CRYPTO_ANUBIS is not set
1107# CONFIG_CRYPTO_ARC4 is not set
1108# CONFIG_CRYPTO_BLOWFISH is not set
1109# CONFIG_CRYPTO_CAMELLIA is not set
1110# CONFIG_CRYPTO_CAST5 is not set
1111# CONFIG_CRYPTO_CAST6 is not set
1112# CONFIG_CRYPTO_DES is not set
1113# CONFIG_CRYPTO_FCRYPT is not set
1114# CONFIG_CRYPTO_KHAZAD is not set
1115# CONFIG_CRYPTO_SALSA20 is not set
1116# CONFIG_CRYPTO_SEED is not set
1117# CONFIG_CRYPTO_SERPENT is not set
1118# CONFIG_CRYPTO_TEA is not set
1119# CONFIG_CRYPTO_TWOFISH is not set
1120
1121#
1122# Compression
1123#
1124# CONFIG_CRYPTO_DEFLATE is not set
1125# CONFIG_CRYPTO_ZLIB is not set
1126# CONFIG_CRYPTO_LZO is not set
1127
1128#
1129# Random Number Generation
1130#
1131CONFIG_CRYPTO_ANSI_CPRNG=m
1132# CONFIG_CRYPTO_USER_API_HASH is not set
1133# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
1134CONFIG_CRYPTO_HW=y
1135# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1136# CONFIG_BINARY_PRINTF is not set
1137
1138#
1139# Library routines
1140#
1141CONFIG_BITREVERSE=y
1142CONFIG_GENERIC_FIND_FIRST_BIT=y
1143CONFIG_GENERIC_FIND_NEXT_BIT=y
1144CONFIG_GENERIC_FIND_LAST_BIT=y
1145# CONFIG_CRC_CCITT is not set
1146# CONFIG_CRC16 is not set
1147# CONFIG_CRC_T10DIF is not set
1148# CONFIG_CRC_ITU_T is not set
1149CONFIG_CRC32=y
1150# CONFIG_CRC7 is not set
1151# CONFIG_LIBCRC32C is not set
1152CONFIG_ZLIB_INFLATE=y
1153# CONFIG_XZ_DEC is not set
1154# CONFIG_XZ_DEC_BCJ is not set
1155CONFIG_DECOMPRESS_GZIP=y
1156CONFIG_HAS_IOMEM=y
1157CONFIG_HAS_IOPORT=y
1158CONFIG_HAS_DMA=y
1159CONFIG_CPU_RMAP=y
1160CONFIG_NLATTR=y
1161# CONFIG_AVERAGE is not set
1162CONFIG_HAVE_KVM=y
1163# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/tile/include/arch/chip_tilegx.h b/arch/tile/include/arch/chip_tilegx.h
new file mode 100644
index 000000000000..ea8e4f2c9483
--- /dev/null
+++ b/arch/tile/include/arch/chip_tilegx.h
@@ -0,0 +1,258 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * @file
17 * Global header file.
18 * This header file specifies defines for TILE-Gx.
19 */
20
21#ifndef __ARCH_CHIP_H__
22#define __ARCH_CHIP_H__
23
24/** Specify chip version.
25 * When possible, prefer the CHIP_xxx symbols below for future-proofing.
26 * This is intended for cross-compiling; native compilation should
27 * use the predefined __tile_chip__ symbol.
28 */
29#define TILE_CHIP 10
30
31/** Specify chip revision.
32 * This provides for the case of a respin of a particular chip type;
33 * the normal value for this symbol is "0".
34 * This is intended for cross-compiling; native compilation should
35 * use the predefined __tile_chip_rev__ symbol.
36 */
37#define TILE_CHIP_REV 0
38
39/** The name of this architecture. */
40#define CHIP_ARCH_NAME "tilegx"
41
42/** The ELF e_machine type for binaries for this chip. */
43#define CHIP_ELF_TYPE() EM_TILEGX
44
45/** The alternate ELF e_machine type for binaries for this chip. */
46#define CHIP_COMPAT_ELF_TYPE() 0x2597
47
48/** What is the native word size of the machine? */
49#define CHIP_WORD_SIZE() 64
50
51/** How many bits of a virtual address are used. Extra bits must be
52 * the sign extension of the low bits.
53 */
54#define CHIP_VA_WIDTH() 42
55
56/** How many bits are in a physical address? */
57#define CHIP_PA_WIDTH() 40
58
59/** Size of the L2 cache, in bytes. */
60#define CHIP_L2_CACHE_SIZE() 262144
61
62/** Log size of an L2 cache line in bytes. */
63#define CHIP_L2_LOG_LINE_SIZE() 6
64
65/** Size of an L2 cache line, in bytes. */
66#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
67
68/** Associativity of the L2 cache. */
69#define CHIP_L2_ASSOC() 8
70
71/** Size of the L1 data cache, in bytes. */
72#define CHIP_L1D_CACHE_SIZE() 32768
73
74/** Log size of an L1 data cache line in bytes. */
75#define CHIP_L1D_LOG_LINE_SIZE() 6
76
77/** Size of an L1 data cache line, in bytes. */
78#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
79
80/** Associativity of the L1 data cache. */
81#define CHIP_L1D_ASSOC() 2
82
83/** Size of the L1 instruction cache, in bytes. */
84#define CHIP_L1I_CACHE_SIZE() 32768
85
86/** Log size of an L1 instruction cache line in bytes. */
87#define CHIP_L1I_LOG_LINE_SIZE() 6
88
89/** Size of an L1 instruction cache line, in bytes. */
90#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
91
92/** Associativity of the L1 instruction cache. */
93#define CHIP_L1I_ASSOC() 2
94
95/** Stride with which flush instructions must be issued. */
96#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
97
98/** Stride with which inv instructions must be issued. */
99#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
100
101/** Stride with which finv instructions must be issued. */
102#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
103
104/** Can the local cache coherently cache data that is homed elsewhere? */
105#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
106
107/** How many simultaneous outstanding victims can the L2 cache have? */
108#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
109
110/** Does the TLB support the NC and NOALLOC bits? */
111#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
112
113/** Does the chip support hash-for-home caching? */
114#define CHIP_HAS_CBOX_HOME_MAP() 1
115
116/** Number of entries in the chip's home map tables. */
117#define CHIP_CBOX_HOME_MAP_SIZE() 128
118
119/** Do uncacheable requests miss in the cache regardless of whether
120 * there is matching data? */
121#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
122
123/** Does the mf instruction wait for victims? */
124#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
125
126/** Does the chip have an "inv" instruction that doesn't also flush? */
127#define CHIP_HAS_INV() 1
128
129/** Does the chip have a "wh64" instruction? */
130#define CHIP_HAS_WH64() 1
131
132/** Does this chip have a 'dword_align' instruction? */
133#define CHIP_HAS_DWORD_ALIGN() 0
134
135/** Number of performance counters. */
136#define CHIP_PERFORMANCE_COUNTERS() 4
137
138/** Does this chip have auxiliary performance counters? */
139#define CHIP_HAS_AUX_PERF_COUNTERS() 1
140
141/** Is the CBOX_MSR1 SPR supported? */
142#define CHIP_HAS_CBOX_MSR1() 0
143
144/** Is the TILE_RTF_HWM SPR supported? */
145#define CHIP_HAS_TILE_RTF_HWM() 1
146
147/** Is the TILE_WRITE_PENDING SPR supported? */
148#define CHIP_HAS_TILE_WRITE_PENDING() 0
149
150/** Is the PROC_STATUS SPR supported? */
151#define CHIP_HAS_PROC_STATUS_SPR() 1
152
153/** Is the DSTREAM_PF SPR supported? */
154#define CHIP_HAS_DSTREAM_PF() 1
155
156/** Log of the number of mshims we have. */
157#define CHIP_LOG_NUM_MSHIMS() 2
158
159/** Are the bases of the interrupt vector areas fixed? */
160#define CHIP_HAS_FIXED_INTVEC_BASE() 0
161
162/** Are the interrupt masks split up into 2 SPRs? */
163#define CHIP_HAS_SPLIT_INTR_MASK() 0
164
165/** Is the cycle count split up into 2 SPRs? */
166#define CHIP_HAS_SPLIT_CYCLE() 0
167
168/** Does the chip have a static network? */
169#define CHIP_HAS_SN() 0
170
171/** Does the chip have a static network processor? */
172#define CHIP_HAS_SN_PROC() 0
173
174/** Size of the L1 static network processor instruction cache, in bytes. */
175/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
176
177/** Does the chip have DMA support in each tile? */
178#define CHIP_HAS_TILE_DMA() 0
179
180/** Does the chip have the second revision of the directly accessible
181 * dynamic networks? This encapsulates a number of characteristics,
182 * including the absence of the catch-all, the absence of inline message
183 * tags, the absence of support for network context-switching, and so on.
184 */
185#define CHIP_HAS_REV1_XDN() 1
186
187/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
188#define CHIP_HAS_CMPEXCH() 1
189
190/** Does the chip have memory-mapped I/O support? */
191#define CHIP_HAS_MMIO() 1
192
193/** Does the chip have post-completion interrupts? */
194#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
195
196/** Does the chip have native single step support? */
197#define CHIP_HAS_SINGLE_STEP() 1
198
199#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
200
201/** How many entries are present in the instruction TLB? */
202#define CHIP_ITLB_ENTRIES() 16
203
204/** How many entries are present in the data TLB? */
205#define CHIP_DTLB_ENTRIES() 32
206
207/** How many MAF entries does the XAUI shim have? */
208#define CHIP_XAUI_MAF_ENTRIES() 32
209
210/** Does the memory shim have a source-id table? */
211#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
212
213/** Does the L1 instruction cache clear on reset? */
214#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
215
216/** Does the chip come out of reset with valid coordinates on all tiles?
217 * Note that if defined, this also implies that the upper left is 1,1.
218 */
219#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
220
221/** Does the chip have unified packet formats? */
222#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
223
224/** Does the chip support write reordering? */
225#define CHIP_HAS_WRITE_REORDERING() 1
226
227/** Does the chip support Y-X routing as well as X-Y? */
228#define CHIP_HAS_Y_X_ROUTING() 1
229
230/** Is INTCTRL_3 managed with the correct MPL? */
231#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
232
233/** Is it possible to configure the chip to be big-endian? */
234#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
235
236/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
237#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
238
239/** Is the DIAG_TRACE_WAY SPR supported? */
240#define CHIP_HAS_DIAG_TRACE_WAY() 0
241
242/** Is the MEM_STRIPE_CONFIG SPR supported? */
243#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
244
245/** Are the TLB_PERF SPRs supported? */
246#define CHIP_HAS_TLB_PERF() 1
247
248/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
249#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
250
251/** Does the chip support rev1 DMA packets? */
252#define CHIP_HAS_REV1_DMA_PACKETS() 1
253
254/** Does the chip have an IPI shim? */
255#define CHIP_HAS_IPI() 1
256
257#endif /* !__OPEN_SOURCE__ */
258#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/arch/icache.h b/arch/tile/include/arch/icache.h
index 5c87c9016338..762eafa8a11e 100644
--- a/arch/tile/include/arch/icache.h
+++ b/arch/tile/include/arch/icache.h
@@ -16,7 +16,7 @@
16/** 16/**
17 * @file 17 * @file
18 * 18 *
19 * Support for invalidating bytes in the instruction 19 * Support for invalidating bytes in the instruction cache.
20 */ 20 */
21 21
22#ifndef __ARCH_ICACHE_H__ 22#ifndef __ARCH_ICACHE_H__
@@ -30,11 +30,10 @@
30 * 30 *
31 * @param addr The start of memory to be invalidated. 31 * @param addr The start of memory to be invalidated.
32 * @param size The number of bytes to be invalidated. 32 * @param size The number of bytes to be invalidated.
33 * @param page_size The system's page size, typically the PAGE_SIZE constant 33 * @param page_size The system's page size, e.g. getpagesize() in userspace.
34 * in sys/page.h. This value must be a power of two no larger 34 * This value must be a power of two no larger than the page containing
35 * than the page containing the code to be invalidated. If the value 35 * the code to be invalidated. If the value is smaller than the actual page
36 * is smaller than the actual page size, this function will still 36 * size, this function will still work, but may run slower than necessary.
37 * work, but may run slower than necessary.
38 */ 37 */
39static __inline void 38static __inline void
40invalidate_icache(const void* addr, unsigned long size, 39invalidate_icache(const void* addr, unsigned long size,
diff --git a/arch/tile/include/arch/interrupts_32.h b/arch/tile/include/arch/interrupts_32.h
index 9d0bfa7e59be..96b5710505b6 100644
--- a/arch/tile/include/arch/interrupts_32.h
+++ b/arch/tile/include/arch/interrupts_32.h
@@ -16,10 +16,11 @@
16#define __ARCH_INTERRUPTS_H__ 16#define __ARCH_INTERRUPTS_H__
17 17
18/** Mask for an interrupt. */ 18/** Mask for an interrupt. */
19#ifdef __ASSEMBLER__
20/* Note: must handle breaking interrupts into high and low words manually. */ 19/* Note: must handle breaking interrupts into high and low words manually. */
21#define INT_MASK(intno) (1 << (intno)) 20#define INT_MASK_LO(intno) (1 << (intno))
22#else 21#define INT_MASK_HI(intno) (1 << ((intno) - 32))
22
23#ifndef __ASSEMBLER__
23#define INT_MASK(intno) (1ULL << (intno)) 24#define INT_MASK(intno) (1ULL << (intno))
24#endif 25#endif
25 26
@@ -89,6 +90,7 @@
89 90
90#define NUM_INTERRUPTS 49 91#define NUM_INTERRUPTS 49
91 92
93#ifndef __ASSEMBLER__
92#define QUEUED_INTERRUPTS ( \ 94#define QUEUED_INTERRUPTS ( \
93 INT_MASK(INT_MEM_ERROR) | \ 95 INT_MASK(INT_MEM_ERROR) | \
94 INT_MASK(INT_DMATLB_MISS) | \ 96 INT_MASK(INT_DMATLB_MISS) | \
@@ -301,4 +303,5 @@
301 INT_MASK(INT_DOUBLE_FAULT) | \ 303 INT_MASK(INT_DOUBLE_FAULT) | \
302 INT_MASK(INT_AUX_PERF_COUNT) | \ 304 INT_MASK(INT_AUX_PERF_COUNT) | \
303 0) 305 0)
306#endif /* !__ASSEMBLER__ */
304#endif /* !__ARCH_INTERRUPTS_H__ */ 307#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/arch/interrupts_64.h b/arch/tile/include/arch/interrupts_64.h
new file mode 100644
index 000000000000..5bb58b2e4e6f
--- /dev/null
+++ b/arch/tile/include/arch/interrupts_64.h
@@ -0,0 +1,276 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __ARCH_INTERRUPTS_H__
16#define __ARCH_INTERRUPTS_H__
17
18/** Mask for an interrupt. */
19#ifdef __ASSEMBLER__
20/* Note: must handle breaking interrupts into high and low words manually. */
21#define INT_MASK(intno) (1 << (intno))
22#else
23#define INT_MASK(intno) (1ULL << (intno))
24#endif
25
26
27/** Where a given interrupt executes */
28#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
29
30/** Where to store a vector for a given interrupt. */
31#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
32
33/** The base address of user-level interrupts. */
34#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
35
36
37/** Additional synthetic interrupt. */
38#define INT_BREAKPOINT (63)
39
40#define INT_MEM_ERROR 0
41#define INT_SINGLE_STEP_3 1
42#define INT_SINGLE_STEP_2 2
43#define INT_SINGLE_STEP_1 3
44#define INT_SINGLE_STEP_0 4
45#define INT_IDN_COMPLETE 5
46#define INT_UDN_COMPLETE 6
47#define INT_ITLB_MISS 7
48#define INT_ILL 8
49#define INT_GPV 9
50#define INT_IDN_ACCESS 10
51#define INT_UDN_ACCESS 11
52#define INT_SWINT_3 12
53#define INT_SWINT_2 13
54#define INT_SWINT_1 14
55#define INT_SWINT_0 15
56#define INT_ILL_TRANS 16
57#define INT_UNALIGN_DATA 17
58#define INT_DTLB_MISS 18
59#define INT_DTLB_ACCESS 19
60#define INT_IDN_FIREWALL 20
61#define INT_UDN_FIREWALL 21
62#define INT_TILE_TIMER 22
63#define INT_AUX_TILE_TIMER 23
64#define INT_IDN_TIMER 24
65#define INT_UDN_TIMER 25
66#define INT_IDN_AVAIL 26
67#define INT_UDN_AVAIL 27
68#define INT_IPI_3 28
69#define INT_IPI_2 29
70#define INT_IPI_1 30
71#define INT_IPI_0 31
72#define INT_PERF_COUNT 32
73#define INT_AUX_PERF_COUNT 33
74#define INT_INTCTRL_3 34
75#define INT_INTCTRL_2 35
76#define INT_INTCTRL_1 36
77#define INT_INTCTRL_0 37
78#define INT_BOOT_ACCESS 38
79#define INT_WORLD_ACCESS 39
80#define INT_I_ASID 40
81#define INT_D_ASID 41
82#define INT_DOUBLE_FAULT 42
83
84#define NUM_INTERRUPTS 43
85
86#ifndef __ASSEMBLER__
87#define QUEUED_INTERRUPTS ( \
88 INT_MASK(INT_MEM_ERROR) | \
89 INT_MASK(INT_IDN_COMPLETE) | \
90 INT_MASK(INT_UDN_COMPLETE) | \
91 INT_MASK(INT_IDN_FIREWALL) | \
92 INT_MASK(INT_UDN_FIREWALL) | \
93 INT_MASK(INT_TILE_TIMER) | \
94 INT_MASK(INT_AUX_TILE_TIMER) | \
95 INT_MASK(INT_IDN_TIMER) | \
96 INT_MASK(INT_UDN_TIMER) | \
97 INT_MASK(INT_IDN_AVAIL) | \
98 INT_MASK(INT_UDN_AVAIL) | \
99 INT_MASK(INT_IPI_3) | \
100 INT_MASK(INT_IPI_2) | \
101 INT_MASK(INT_IPI_1) | \
102 INT_MASK(INT_IPI_0) | \
103 INT_MASK(INT_PERF_COUNT) | \
104 INT_MASK(INT_AUX_PERF_COUNT) | \
105 INT_MASK(INT_INTCTRL_3) | \
106 INT_MASK(INT_INTCTRL_2) | \
107 INT_MASK(INT_INTCTRL_1) | \
108 INT_MASK(INT_INTCTRL_0) | \
109 INT_MASK(INT_BOOT_ACCESS) | \
110 INT_MASK(INT_WORLD_ACCESS) | \
111 INT_MASK(INT_I_ASID) | \
112 INT_MASK(INT_D_ASID) | \
113 INT_MASK(INT_DOUBLE_FAULT) | \
114 0)
115#define NONQUEUED_INTERRUPTS ( \
116 INT_MASK(INT_SINGLE_STEP_3) | \
117 INT_MASK(INT_SINGLE_STEP_2) | \
118 INT_MASK(INT_SINGLE_STEP_1) | \
119 INT_MASK(INT_SINGLE_STEP_0) | \
120 INT_MASK(INT_ITLB_MISS) | \
121 INT_MASK(INT_ILL) | \
122 INT_MASK(INT_GPV) | \
123 INT_MASK(INT_IDN_ACCESS) | \
124 INT_MASK(INT_UDN_ACCESS) | \
125 INT_MASK(INT_SWINT_3) | \
126 INT_MASK(INT_SWINT_2) | \
127 INT_MASK(INT_SWINT_1) | \
128 INT_MASK(INT_SWINT_0) | \
129 INT_MASK(INT_ILL_TRANS) | \
130 INT_MASK(INT_UNALIGN_DATA) | \
131 INT_MASK(INT_DTLB_MISS) | \
132 INT_MASK(INT_DTLB_ACCESS) | \
133 0)
134#define CRITICAL_MASKED_INTERRUPTS ( \
135 INT_MASK(INT_MEM_ERROR) | \
136 INT_MASK(INT_SINGLE_STEP_3) | \
137 INT_MASK(INT_SINGLE_STEP_2) | \
138 INT_MASK(INT_SINGLE_STEP_1) | \
139 INT_MASK(INT_SINGLE_STEP_0) | \
140 INT_MASK(INT_IDN_COMPLETE) | \
141 INT_MASK(INT_UDN_COMPLETE) | \
142 INT_MASK(INT_IDN_FIREWALL) | \
143 INT_MASK(INT_UDN_FIREWALL) | \
144 INT_MASK(INT_TILE_TIMER) | \
145 INT_MASK(INT_AUX_TILE_TIMER) | \
146 INT_MASK(INT_IDN_TIMER) | \
147 INT_MASK(INT_UDN_TIMER) | \
148 INT_MASK(INT_IDN_AVAIL) | \
149 INT_MASK(INT_UDN_AVAIL) | \
150 INT_MASK(INT_IPI_3) | \
151 INT_MASK(INT_IPI_2) | \
152 INT_MASK(INT_IPI_1) | \
153 INT_MASK(INT_IPI_0) | \
154 INT_MASK(INT_PERF_COUNT) | \
155 INT_MASK(INT_AUX_PERF_COUNT) | \
156 INT_MASK(INT_INTCTRL_3) | \
157 INT_MASK(INT_INTCTRL_2) | \
158 INT_MASK(INT_INTCTRL_1) | \
159 INT_MASK(INT_INTCTRL_0) | \
160 0)
161#define CRITICAL_UNMASKED_INTERRUPTS ( \
162 INT_MASK(INT_ITLB_MISS) | \
163 INT_MASK(INT_ILL) | \
164 INT_MASK(INT_GPV) | \
165 INT_MASK(INT_IDN_ACCESS) | \
166 INT_MASK(INT_UDN_ACCESS) | \
167 INT_MASK(INT_SWINT_3) | \
168 INT_MASK(INT_SWINT_2) | \
169 INT_MASK(INT_SWINT_1) | \
170 INT_MASK(INT_SWINT_0) | \
171 INT_MASK(INT_ILL_TRANS) | \
172 INT_MASK(INT_UNALIGN_DATA) | \
173 INT_MASK(INT_DTLB_MISS) | \
174 INT_MASK(INT_DTLB_ACCESS) | \
175 INT_MASK(INT_BOOT_ACCESS) | \
176 INT_MASK(INT_WORLD_ACCESS) | \
177 INT_MASK(INT_I_ASID) | \
178 INT_MASK(INT_D_ASID) | \
179 INT_MASK(INT_DOUBLE_FAULT) | \
180 0)
181#define MASKABLE_INTERRUPTS ( \
182 INT_MASK(INT_MEM_ERROR) | \
183 INT_MASK(INT_SINGLE_STEP_3) | \
184 INT_MASK(INT_SINGLE_STEP_2) | \
185 INT_MASK(INT_SINGLE_STEP_1) | \
186 INT_MASK(INT_SINGLE_STEP_0) | \
187 INT_MASK(INT_IDN_COMPLETE) | \
188 INT_MASK(INT_UDN_COMPLETE) | \
189 INT_MASK(INT_IDN_FIREWALL) | \
190 INT_MASK(INT_UDN_FIREWALL) | \
191 INT_MASK(INT_TILE_TIMER) | \
192 INT_MASK(INT_AUX_TILE_TIMER) | \
193 INT_MASK(INT_IDN_TIMER) | \
194 INT_MASK(INT_UDN_TIMER) | \
195 INT_MASK(INT_IDN_AVAIL) | \
196 INT_MASK(INT_UDN_AVAIL) | \
197 INT_MASK(INT_IPI_3) | \
198 INT_MASK(INT_IPI_2) | \
199 INT_MASK(INT_IPI_1) | \
200 INT_MASK(INT_IPI_0) | \
201 INT_MASK(INT_PERF_COUNT) | \
202 INT_MASK(INT_AUX_PERF_COUNT) | \
203 INT_MASK(INT_INTCTRL_3) | \
204 INT_MASK(INT_INTCTRL_2) | \
205 INT_MASK(INT_INTCTRL_1) | \
206 INT_MASK(INT_INTCTRL_0) | \
207 0)
208#define UNMASKABLE_INTERRUPTS ( \
209 INT_MASK(INT_ITLB_MISS) | \
210 INT_MASK(INT_ILL) | \
211 INT_MASK(INT_GPV) | \
212 INT_MASK(INT_IDN_ACCESS) | \
213 INT_MASK(INT_UDN_ACCESS) | \
214 INT_MASK(INT_SWINT_3) | \
215 INT_MASK(INT_SWINT_2) | \
216 INT_MASK(INT_SWINT_1) | \
217 INT_MASK(INT_SWINT_0) | \
218 INT_MASK(INT_ILL_TRANS) | \
219 INT_MASK(INT_UNALIGN_DATA) | \
220 INT_MASK(INT_DTLB_MISS) | \
221 INT_MASK(INT_DTLB_ACCESS) | \
222 INT_MASK(INT_BOOT_ACCESS) | \
223 INT_MASK(INT_WORLD_ACCESS) | \
224 INT_MASK(INT_I_ASID) | \
225 INT_MASK(INT_D_ASID) | \
226 INT_MASK(INT_DOUBLE_FAULT) | \
227 0)
228#define SYNC_INTERRUPTS ( \
229 INT_MASK(INT_SINGLE_STEP_3) | \
230 INT_MASK(INT_SINGLE_STEP_2) | \
231 INT_MASK(INT_SINGLE_STEP_1) | \
232 INT_MASK(INT_SINGLE_STEP_0) | \
233 INT_MASK(INT_IDN_COMPLETE) | \
234 INT_MASK(INT_UDN_COMPLETE) | \
235 INT_MASK(INT_ITLB_MISS) | \
236 INT_MASK(INT_ILL) | \
237 INT_MASK(INT_GPV) | \
238 INT_MASK(INT_IDN_ACCESS) | \
239 INT_MASK(INT_UDN_ACCESS) | \
240 INT_MASK(INT_SWINT_3) | \
241 INT_MASK(INT_SWINT_2) | \
242 INT_MASK(INT_SWINT_1) | \
243 INT_MASK(INT_SWINT_0) | \
244 INT_MASK(INT_ILL_TRANS) | \
245 INT_MASK(INT_UNALIGN_DATA) | \
246 INT_MASK(INT_DTLB_MISS) | \
247 INT_MASK(INT_DTLB_ACCESS) | \
248 0)
249#define NON_SYNC_INTERRUPTS ( \
250 INT_MASK(INT_MEM_ERROR) | \
251 INT_MASK(INT_IDN_FIREWALL) | \
252 INT_MASK(INT_UDN_FIREWALL) | \
253 INT_MASK(INT_TILE_TIMER) | \
254 INT_MASK(INT_AUX_TILE_TIMER) | \
255 INT_MASK(INT_IDN_TIMER) | \
256 INT_MASK(INT_UDN_TIMER) | \
257 INT_MASK(INT_IDN_AVAIL) | \
258 INT_MASK(INT_UDN_AVAIL) | \
259 INT_MASK(INT_IPI_3) | \
260 INT_MASK(INT_IPI_2) | \
261 INT_MASK(INT_IPI_1) | \
262 INT_MASK(INT_IPI_0) | \
263 INT_MASK(INT_PERF_COUNT) | \
264 INT_MASK(INT_AUX_PERF_COUNT) | \
265 INT_MASK(INT_INTCTRL_3) | \
266 INT_MASK(INT_INTCTRL_2) | \
267 INT_MASK(INT_INTCTRL_1) | \
268 INT_MASK(INT_INTCTRL_0) | \
269 INT_MASK(INT_BOOT_ACCESS) | \
270 INT_MASK(INT_WORLD_ACCESS) | \
271 INT_MASK(INT_I_ASID) | \
272 INT_MASK(INT_D_ASID) | \
273 INT_MASK(INT_DOUBLE_FAULT) | \
274 0)
275#endif /* !__ASSEMBLER__ */
276#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/arch/sim.h b/arch/tile/include/arch/sim.h
new file mode 100644
index 000000000000..e54b7b0527f3
--- /dev/null
+++ b/arch/tile/include/arch/sim.h
@@ -0,0 +1,643 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file
17 *
18 * Provides an API for controlling the simulator at runtime.
19 */
20
21/**
22 * @addtogroup arch_sim
23 * @{
24 *
25 * An API for controlling the simulator at runtime.
26 *
27 * The simulator's behavior can be modified while it is running.
28 * For example, human-readable trace output can be enabled and disabled
29 * around code of interest.
30 *
31 * There are two ways to modify simulator behavior:
32 * programmatically, by calling various sim_* functions, and
33 * interactively, by entering commands like "sim set functional true"
34 * at the tile-monitor prompt. Typing "sim help" at that prompt provides
35 * a list of interactive commands.
36 *
37 * All interactive commands can also be executed programmatically by
38 * passing a string to the sim_command function.
39 */
40
41#ifndef __ARCH_SIM_H__
42#define __ARCH_SIM_H__
43
44#include <arch/sim_def.h>
45#include <arch/abi.h>
46
47#ifndef __ASSEMBLER__
48
49#include <arch/spr_def.h>
50
51
52/**
53 * Return true if the current program is running under a simulator,
54 * rather than on real hardware. If running on hardware, other "sim_xxx()"
55 * calls have no useful effect.
56 */
57static inline int
58sim_is_simulator(void)
59{
60 return __insn_mfspr(SPR_SIM_CONTROL) != 0;
61}
62
63
64/**
65 * Checkpoint the simulator state to a checkpoint file.
66 *
67 * The checkpoint file name is either the default or the name specified
68 * on the command line with "--checkpoint-file".
69 */
70static __inline void
71sim_checkpoint(void)
72{
73 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_CHECKPOINT);
74}
75
76
77/**
78 * Report whether or not various kinds of simulator tracing are enabled.
79 *
80 * @return The bitwise OR of these values:
81 *
82 * SIM_TRACE_CYCLES (--trace-cycles),
83 * SIM_TRACE_ROUTER (--trace-router),
84 * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
85 * SIM_TRACE_DISASM (--trace-disasm),
86 * SIM_TRACE_STALL_INFO (--trace-stall-info)
87 * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
88 * SIM_TRACE_L2_CACHE (--trace-l2)
89 * SIM_TRACE_LINES (--trace-lines)
90 */
91static __inline unsigned int
92sim_get_tracing(void)
93{
94 return __insn_mfspr(SPR_SIM_CONTROL) & SIM_TRACE_FLAG_MASK;
95}
96
97
98/**
99 * Turn on or off different kinds of simulator tracing.
100 *
101 * @param mask Either one of these special values:
102 *
103 * SIM_TRACE_NONE (turns off tracing),
104 * SIM_TRACE_ALL (turns on all possible tracing).
105 *
106 * or the bitwise OR of these values:
107 *
108 * SIM_TRACE_CYCLES (--trace-cycles),
109 * SIM_TRACE_ROUTER (--trace-router),
110 * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
111 * SIM_TRACE_DISASM (--trace-disasm),
112 * SIM_TRACE_STALL_INFO (--trace-stall-info)
113 * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
114 * SIM_TRACE_L2_CACHE (--trace-l2)
115 * SIM_TRACE_LINES (--trace-lines)
116 */
117static __inline void
118sim_set_tracing(unsigned int mask)
119{
120 __insn_mtspr(SPR_SIM_CONTROL, SIM_TRACE_SPR_ARG(mask));
121}
122
123
124/**
125 * Request dumping of different kinds of simulator state.
126 *
127 * @param mask Either this special value:
128 *
129 * SIM_DUMP_ALL (dump all known state)
130 *
131 * or the bitwise OR of these values:
132 *
133 * SIM_DUMP_REGS (the register file),
134 * SIM_DUMP_SPRS (the SPRs),
135 * SIM_DUMP_ITLB (the iTLB),
136 * SIM_DUMP_DTLB (the dTLB),
137 * SIM_DUMP_L1I (the L1 I-cache),
138 * SIM_DUMP_L1D (the L1 D-cache),
139 * SIM_DUMP_L2 (the L2 cache),
140 * SIM_DUMP_SNREGS (the switch register file),
141 * SIM_DUMP_SNITLB (the switch iTLB),
142 * SIM_DUMP_SNL1I (the switch L1 I-cache),
143 * SIM_DUMP_BACKTRACE (the current backtrace)
144 */
145static __inline void
146sim_dump(unsigned int mask)
147{
148 __insn_mtspr(SPR_SIM_CONTROL, SIM_DUMP_SPR_ARG(mask));
149}
150
151
152/**
153 * Print a string to the simulator stdout.
154 *
155 * @param str The string to be written.
156 */
157static __inline void
158sim_print(const char* str)
159{
160 for ( ; *str != '\0'; str++)
161 {
162 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
163 (*str << _SIM_CONTROL_OPERATOR_BITS));
164 }
165 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
166 (SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS));
167}
168
169
170/**
171 * Print a string to the simulator stdout.
172 *
173 * @param str The string to be written (a newline is automatically added).
174 */
175static __inline void
176sim_print_string(const char* str)
177{
178 for ( ; *str != '\0'; str++)
179 {
180 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
181 (*str << _SIM_CONTROL_OPERATOR_BITS));
182 }
183 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
184 (SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
185}
186
187
188/**
189 * Execute a simulator command string.
190 *
191 * Type 'sim help' at the tile-monitor prompt to learn what commands
192 * are available. Note the use of the tile-monitor "sim" command to
193 * pass commands to the simulator.
194 *
195 * The argument to sim_command() does not include the leading "sim"
196 * prefix used at the tile-monitor prompt; for example, you might call
197 * sim_command("trace disasm").
198 */
199static __inline void
200sim_command(const char* str)
201{
202 int c;
203 do
204 {
205 c = *str++;
206 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_COMMAND |
207 (c << _SIM_CONTROL_OPERATOR_BITS));
208 }
209 while (c);
210}
211
212
213
214#ifndef __DOXYGEN__
215
216/**
217 * The underlying implementation of "_sim_syscall()".
218 *
219 * We use extra "and" instructions to ensure that all the values
220 * we are passing to the simulator are actually valid in the registers
221 * (i.e. returned from memory) prior to the SIM_CONTROL spr.
222 */
223static __inline long _sim_syscall0(int val)
224{
225 long result;
226 __asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
227 : "=R00" (result) : "R00" (val));
228 return result;
229}
230
231static __inline long _sim_syscall1(int val, long arg1)
232{
233 long result;
234 __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
235 : "=R00" (result) : "R00" (val), "R01" (arg1));
236 return result;
237}
238
239static __inline long _sim_syscall2(int val, long arg1, long arg2)
240{
241 long result;
242 __asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
243 : "=R00" (result)
244 : "R00" (val), "R01" (arg1), "R02" (arg2));
245 return result;
246}
247
248/* Note that _sim_syscall3() and higher are technically at risk of
249 receiving an interrupt right before the mtspr bundle, in which case
250 the register values for arguments 3 and up may still be in flight
251 to the core from a stack frame reload. */
252
253static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3)
254{
255 long result;
256 __asm__ __volatile__ ("{ and zero, r3, r3 };"
257 "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
258 : "=R00" (result)
259 : "R00" (val), "R01" (arg1), "R02" (arg2),
260 "R03" (arg3));
261 return result;
262}
263
264static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3,
265 long arg4)
266{
267 long result;
268 __asm__ __volatile__ ("{ and zero, r3, r4 };"
269 "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
270 : "=R00" (result)
271 : "R00" (val), "R01" (arg1), "R02" (arg2),
272 "R03" (arg3), "R04" (arg4));
273 return result;
274}
275
276static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3,
277 long arg4, long arg5)
278{
279 long result;
280 __asm__ __volatile__ ("{ and zero, r3, r4; and zero, r5, r5 };"
281 "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
282 : "=R00" (result)
283 : "R00" (val), "R01" (arg1), "R02" (arg2),
284 "R03" (arg3), "R04" (arg4), "R05" (arg5));
285 return result;
286}
287
288/**
289 * Make a special syscall to the simulator itself, if running under
290 * simulation. This is used as the implementation of other functions
291 * and should not be used outside this file.
292 *
293 * @param syscall_num The simulator syscall number.
294 * @param nr The number of additional arguments provided.
295 *
296 * @return Varies by syscall.
297 */
298#define _sim_syscall(syscall_num, nr, args...) \
299 _sim_syscall##nr( \
300 ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \
301 ##args)
302
303
304/* Values for the "access_mask" parameters below. */
305#define SIM_WATCHPOINT_READ 1
306#define SIM_WATCHPOINT_WRITE 2
307#define SIM_WATCHPOINT_EXECUTE 4
308
309
310static __inline int
311sim_add_watchpoint(unsigned int process_id,
312 unsigned long address,
313 unsigned long size,
314 unsigned int access_mask,
315 unsigned long user_data)
316{
317 return _sim_syscall(SIM_SYSCALL_ADD_WATCHPOINT, 5, process_id,
318 address, size, access_mask, user_data);
319}
320
321
322static __inline int
323sim_remove_watchpoint(unsigned int process_id,
324 unsigned long address,
325 unsigned long size,
326 unsigned int access_mask,
327 unsigned long user_data)
328{
329 return _sim_syscall(SIM_SYSCALL_REMOVE_WATCHPOINT, 5, process_id,
330 address, size, access_mask, user_data);
331}
332
333
334/**
335 * Return value from sim_query_watchpoint.
336 */
337struct SimQueryWatchpointStatus
338{
339 /**
340 * 0 if a watchpoint fired, 1 if no watchpoint fired, or -1 for
341 * error (meaning a bad process_id).
342 */
343 int syscall_status;
344
345 /**
346 * The address of the watchpoint that fired (this is the address
347 * passed to sim_add_watchpoint, not an address within that range
348 * that actually triggered the watchpoint).
349 */
350 unsigned long address;
351
352 /** The arbitrary user_data installed by sim_add_watchpoint. */
353 unsigned long user_data;
354};
355
356
357static __inline struct SimQueryWatchpointStatus
358sim_query_watchpoint(unsigned int process_id)
359{
360 struct SimQueryWatchpointStatus status;
361 long val = SIM_CONTROL_SYSCALL |
362 (SIM_SYSCALL_QUERY_WATCHPOINT << _SIM_CONTROL_OPERATOR_BITS);
363 __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
364 : "=R00" (status.syscall_status),
365 "=R01" (status.address),
366 "=R02" (status.user_data)
367 : "R00" (val), "R01" (process_id));
368 return status;
369}
370
371
372/* On the simulator, confirm lines have been evicted everywhere. */
373static __inline void
374sim_validate_lines_evicted(unsigned long long pa, unsigned long length)
375{
376#ifdef __LP64__
377 _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 2, pa, length);
378#else
379 _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 4,
380 0 /* dummy */, (long)(pa), (long)(pa >> 32), length);
381#endif
382}
383
384
385/* Return the current CPU speed in cycles per second. */
386static __inline long
387sim_query_cpu_speed(void)
388{
389 return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0);
390}
391
392#endif /* !__DOXYGEN__ */
393
394
395
396
397/**
398 * Modify the shaping parameters of a shim.
399 *
400 * @param shim The shim to modify. One of:
401 * SIM_CONTROL_SHAPING_GBE_0
402 * SIM_CONTROL_SHAPING_GBE_1
403 * SIM_CONTROL_SHAPING_GBE_2
404 * SIM_CONTROL_SHAPING_GBE_3
405 * SIM_CONTROL_SHAPING_XGBE_0
406 * SIM_CONTROL_SHAPING_XGBE_1
407 *
408 * @param type The type of shaping. This should be the same type of
409 * shaping that is already in place on the shim. One of:
410 * SIM_CONTROL_SHAPING_MULTIPLIER
411 * SIM_CONTROL_SHAPING_PPS
412 * SIM_CONTROL_SHAPING_BPS
413 *
414 * @param units The magnitude of the rate. One of:
415 * SIM_CONTROL_SHAPING_UNITS_SINGLE
416 * SIM_CONTROL_SHAPING_UNITS_KILO
417 * SIM_CONTROL_SHAPING_UNITS_MEGA
418 * SIM_CONTROL_SHAPING_UNITS_GIGA
419 *
420 * @param rate The rate to which to change it. This must fit in
421 * SIM_CONTROL_SHAPING_RATE_BITS bits or a warning is issued and
422 * the shaping is not changed.
423 *
424 * @return 0 if no problems were detected in the arguments to sim_set_shaping
425 * or 1 if problems were detected (for example, rate does not fit in 17 bits).
426 */
427static __inline int
428sim_set_shaping(unsigned shim,
429 unsigned type,
430 unsigned units,
431 unsigned rate)
432{
433 if ((rate & ~((1 << SIM_CONTROL_SHAPING_RATE_BITS) - 1)) != 0)
434 return 1;
435
436 __insn_mtspr(SPR_SIM_CONTROL, SIM_SHAPING_SPR_ARG(shim, type, units, rate));
437 return 0;
438}
439
440#ifdef __tilegx__
441
442/** Enable a set of mPIPE links. Pass a -1 link_mask to enable all links. */
443static __inline void
444sim_enable_mpipe_links(unsigned mpipe, unsigned long link_mask)
445{
446 __insn_mtspr(SPR_SIM_CONTROL,
447 (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
448 (mpipe << 8) | (1 << 16) | ((uint_reg_t)link_mask << 32)));
449}
450
451/** Disable a set of mPIPE links. Pass a -1 link_mask to disable all links. */
452static __inline void
453sim_disable_mpipe_links(unsigned mpipe, unsigned long link_mask)
454{
455 __insn_mtspr(SPR_SIM_CONTROL,
456 (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
457 (mpipe << 8) | (0 << 16) | ((uint_reg_t)link_mask << 32)));
458}
459
460#endif /* __tilegx__ */
461
462
463/*
464 * An API for changing "functional" mode.
465 */
466
467#ifndef __DOXYGEN__
468
469#define sim_enable_functional() \
470 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_ENABLE_FUNCTIONAL)
471
472#define sim_disable_functional() \
473 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_DISABLE_FUNCTIONAL)
474
475#endif /* __DOXYGEN__ */
476
477
478/*
479 * Profiler support.
480 */
481
482/**
483 * Turn profiling on for the current task.
484 *
485 * Note that this has no effect if run in an environment without
486 * profiling support (thus, the proper flags to the simulator must
487 * be supplied).
488 */
489static __inline void
490sim_profiler_enable(void)
491{
492 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_ENABLE);
493}
494
495
496/** Turn profiling off for the current task. */
497static __inline void
498sim_profiler_disable(void)
499{
500 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_DISABLE);
501}
502
503
504/**
505 * Turn profiling on or off for the current task.
506 *
507 * @param enabled If true, turns on profiling. If false, turns it off.
508 *
509 * Note that this has no effect if run in an environment without
510 * profiling support (thus, the proper flags to the simulator must
511 * be supplied).
512 */
513static __inline void
514sim_profiler_set_enabled(int enabled)
515{
516 int val =
517 enabled ? SIM_CONTROL_PROFILER_ENABLE : SIM_CONTROL_PROFILER_DISABLE;
518 __insn_mtspr(SPR_SIM_CONTROL, val);
519}
520
521
522/**
523 * Return true if and only if profiling is currently enabled
524 * for the current task.
525 *
526 * This returns false even if sim_profiler_enable() was called
527 * if the current execution environment does not support profiling.
528 */
529static __inline int
530sim_profiler_is_enabled(void)
531{
532 return ((__insn_mfspr(SPR_SIM_CONTROL) & SIM_PROFILER_ENABLED_MASK) != 0);
533}
534
535
536/**
537 * Reset profiling counters to zero for the current task.
538 *
539 * Resetting can be done while profiling is enabled. It does not affect
540 * the chip-wide profiling counters.
541 */
542static __inline void
543sim_profiler_clear(void)
544{
545 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_CLEAR);
546}
547
548
549/**
550 * Enable specified chip-level profiling counters.
551 *
552 * Does not affect the per-task profiling counters.
553 *
554 * @param mask Either this special value:
555 *
556 * SIM_CHIP_ALL (enables all chip-level components).
557 *
558 * or the bitwise OR of these values:
559 *
560 * SIM_CHIP_MEMCTL (enable all memory controllers)
561 * SIM_CHIP_XAUI (enable all XAUI controllers)
562 * SIM_CHIP_MPIPE (enable all MPIPE controllers)
563 */
564static __inline void
565sim_profiler_chip_enable(unsigned int mask)
566{
567 __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask));
568}
569
570
571/**
572 * Disable specified chip-level profiling counters.
573 *
574 * Does not affect the per-task profiling counters.
575 *
576 * @param mask Either this special value:
577 *
578 * SIM_CHIP_ALL (disables all chip-level components).
579 *
580 * or the bitwise OR of these values:
581 *
582 * SIM_CHIP_MEMCTL (disable all memory controllers)
583 * SIM_CHIP_XAUI (disable all XAUI controllers)
584 * SIM_CHIP_MPIPE (disable all MPIPE controllers)
585 */
586static __inline void
587sim_profiler_chip_disable(unsigned int mask)
588{
589 __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask));
590}
591
592
593/**
594 * Reset specified chip-level profiling counters to zero.
595 *
596 * Does not affect the per-task profiling counters.
597 *
598 * @param mask Either this special value:
599 *
600 * SIM_CHIP_ALL (clears all chip-level components).
601 *
602 * or the bitwise OR of these values:
603 *
604 * SIM_CHIP_MEMCTL (clear all memory controllers)
605 * SIM_CHIP_XAUI (clear all XAUI controllers)
606 * SIM_CHIP_MPIPE (clear all MPIPE controllers)
607 */
608static __inline void
609sim_profiler_chip_clear(unsigned int mask)
610{
611 __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask));
612}
613
614
615/*
616 * Event support.
617 */
618
619#ifndef __DOXYGEN__
620
621static __inline void
622sim_event_begin(unsigned int x)
623{
624#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
625 __insn_mtspr(SPR_EVENT_BEGIN, x);
626#endif
627}
628
629static __inline void
630sim_event_end(unsigned int x)
631{
632#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
633 __insn_mtspr(SPR_EVENT_END, x);
634#endif
635}
636
637#endif /* !__DOXYGEN__ */
638
639#endif /* !__ASSEMBLER__ */
640
641#endif /* !__ARCH_SIM_H__ */
642
643/** @} */
diff --git a/arch/tile/include/arch/sim_def.h b/arch/tile/include/arch/sim_def.h
index 6418fbde063e..4b44a2b6a09a 100644
--- a/arch/tile/include/arch/sim_def.h
+++ b/arch/tile/include/arch/sim_def.h
@@ -1,477 +1,464 @@
1// Copyright 2010 Tilera Corporation. All Rights Reserved. 1/*
2// 2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3// This program is free software; you can redistribute it and/or 3 *
4// modify it under the terms of the GNU General Public License 4 * This program is free software; you can redistribute it and/or
5// as published by the Free Software Foundation, version 2. 5 * modify it under the terms of the GNU General Public License
6// 6 * as published by the Free Software Foundation, version 2.
7// This program is distributed in the hope that it will be useful, but 7 *
8// WITHOUT ANY WARRANTY; without even the implied warranty of 8 * This program is distributed in the hope that it will be useful, but
9// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10// NON INFRINGEMENT. See the GNU General Public License for 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11// more details. 11 * NON INFRINGEMENT. See the GNU General Public License for
12 12 * more details.
13//! @file 13 */
14//! 14
15//! Some low-level simulator definitions. 15/**
16//! 16 * @file
17 *
18 * Some low-level simulator definitions.
19 */
17 20
18#ifndef __ARCH_SIM_DEF_H__ 21#ifndef __ARCH_SIM_DEF_H__
19#define __ARCH_SIM_DEF_H__ 22#define __ARCH_SIM_DEF_H__
20 23
21 24
22//! Internal: the low bits of the SIM_CONTROL_* SPR values specify 25/**
23//! the operation to perform, and the remaining bits are 26 * Internal: the low bits of the SIM_CONTROL_* SPR values specify
24//! an operation-specific parameter (often unused). 27 * the operation to perform, and the remaining bits are
25//! 28 * an operation-specific parameter (often unused).
29 */
26#define _SIM_CONTROL_OPERATOR_BITS 8 30#define _SIM_CONTROL_OPERATOR_BITS 8
27 31
28 32
29//== Values which can be written to SPR_SIM_CONTROL. 33/*
34 * Values which can be written to SPR_SIM_CONTROL.
35 */
30 36
31//! If written to SPR_SIM_CONTROL, stops profiling. 37/** If written to SPR_SIM_CONTROL, stops profiling. */
32//!
33#define SIM_CONTROL_PROFILER_DISABLE 0 38#define SIM_CONTROL_PROFILER_DISABLE 0
34 39
35//! If written to SPR_SIM_CONTROL, starts profiling. 40/** If written to SPR_SIM_CONTROL, starts profiling. */
36//!
37#define SIM_CONTROL_PROFILER_ENABLE 1 41#define SIM_CONTROL_PROFILER_ENABLE 1
38 42
39//! If written to SPR_SIM_CONTROL, clears profiling counters. 43/** If written to SPR_SIM_CONTROL, clears profiling counters. */
40//!
41#define SIM_CONTROL_PROFILER_CLEAR 2 44#define SIM_CONTROL_PROFILER_CLEAR 2
42 45
43//! If written to SPR_SIM_CONTROL, checkpoints the simulator. 46/** If written to SPR_SIM_CONTROL, checkpoints the simulator. */
44//!
45#define SIM_CONTROL_CHECKPOINT 3 47#define SIM_CONTROL_CHECKPOINT 3
46 48
47//! If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), 49/**
48//! sets the tracing mask to the given mask. See "sim_set_tracing()". 50 * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
49//! 51 * sets the tracing mask to the given mask. See "sim_set_tracing()".
52 */
50#define SIM_CONTROL_SET_TRACING 4 53#define SIM_CONTROL_SET_TRACING 4
51 54
52//! If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), 55/**
53//! dumps the requested items of machine state to the log. 56 * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
54//! 57 * dumps the requested items of machine state to the log.
58 */
55#define SIM_CONTROL_DUMP 5 59#define SIM_CONTROL_DUMP 5
56 60
57//! If written to SPR_SIM_CONTROL, clears chip-level profiling counters. 61/** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */
58//!
59#define SIM_CONTROL_PROFILER_CHIP_CLEAR 6 62#define SIM_CONTROL_PROFILER_CHIP_CLEAR 6
60 63
61//! If written to SPR_SIM_CONTROL, disables chip-level profiling. 64/** If written to SPR_SIM_CONTROL, disables chip-level profiling. */
62//!
63#define SIM_CONTROL_PROFILER_CHIP_DISABLE 7 65#define SIM_CONTROL_PROFILER_CHIP_DISABLE 7
64 66
65//! If written to SPR_SIM_CONTROL, enables chip-level profiling. 67/** If written to SPR_SIM_CONTROL, enables chip-level profiling. */
66//!
67#define SIM_CONTROL_PROFILER_CHIP_ENABLE 8 68#define SIM_CONTROL_PROFILER_CHIP_ENABLE 8
68 69
69//! If written to SPR_SIM_CONTROL, enables chip-level functional mode 70/** If written to SPR_SIM_CONTROL, enables chip-level functional mode */
70//!
71#define SIM_CONTROL_ENABLE_FUNCTIONAL 9 71#define SIM_CONTROL_ENABLE_FUNCTIONAL 9
72 72
73//! If written to SPR_SIM_CONTROL, disables chip-level functional mode. 73/** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */
74//!
75#define SIM_CONTROL_DISABLE_FUNCTIONAL 10 74#define SIM_CONTROL_DISABLE_FUNCTIONAL 10
76 75
77//! If written to SPR_SIM_CONTROL, enables chip-level functional mode. 76/**
78//! All tiles must perform this write for functional mode to be enabled. 77 * If written to SPR_SIM_CONTROL, enables chip-level functional mode.
79//! Ignored in naked boot mode unless --functional is specified. 78 * All tiles must perform this write for functional mode to be enabled.
80//! WARNING: Only the hypervisor startup code should use this! 79 * Ignored in naked boot mode unless --functional is specified.
81//! 80 * WARNING: Only the hypervisor startup code should use this!
81 */
82#define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11 82#define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11
83 83
84//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), 84/**
85//! writes a string directly to the simulator output. Written to once for 85 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
86//! each character in the string, plus a final NUL. Instead of NUL, 86 * writes a string directly to the simulator output. Written to once for
87//! you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY". 87 * each character in the string, plus a final NUL. Instead of NUL,
88//! 88 * you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY".
89// ISSUE: Document the meaning of "newline", and the handling of NUL. 89 */
90// 90/* ISSUE: Document the meaning of "newline", and the handling of NUL. */
91#define SIM_CONTROL_PUTC 12 91#define SIM_CONTROL_PUTC 12
92 92
93//! If written to SPR_SIM_CONTROL, clears the --grind-coherence state for 93/**
94//! this core. This is intended to be used before a loop that will 94 * If written to SPR_SIM_CONTROL, clears the --grind-coherence state for
95//! invalidate the cache by loading new data and evicting all current data. 95 * this core. This is intended to be used before a loop that will
96//! Generally speaking, this API should only be used by system code. 96 * invalidate the cache by loading new data and evicting all current data.
97//! 97 * Generally speaking, this API should only be used by system code.
98 */
98#define SIM_CONTROL_GRINDER_CLEAR 13 99#define SIM_CONTROL_GRINDER_CLEAR 13
99 100
100//! If written to SPR_SIM_CONTROL, shuts down the simulator. 101/** If written to SPR_SIM_CONTROL, shuts down the simulator. */
101//!
102#define SIM_CONTROL_SHUTDOWN 14 102#define SIM_CONTROL_SHUTDOWN 14
103 103
104//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), 104/**
105//! indicates that a fork syscall just created the given process. 105 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
106//! 106 * indicates that a fork syscall just created the given process.
107 */
107#define SIM_CONTROL_OS_FORK 15 108#define SIM_CONTROL_OS_FORK 15
108 109
109//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), 110/**
110//! indicates that an exit syscall was just executed by the given process. 111 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
111//! 112 * indicates that an exit syscall was just executed by the given process.
113 */
112#define SIM_CONTROL_OS_EXIT 16 114#define SIM_CONTROL_OS_EXIT 16
113 115
114//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), 116/**
115//! indicates that the OS just switched to the given process. 117 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
116//! 118 * indicates that the OS just switched to the given process.
119 */
117#define SIM_CONTROL_OS_SWITCH 17 120#define SIM_CONTROL_OS_SWITCH 17
118 121
119//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), 122/**
120//! indicates that an exec syscall was just executed. Written to once for 123 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
121//! each character in the executable name, plus a final NUL. 124 * indicates that an exec syscall was just executed. Written to once for
122//! 125 * each character in the executable name, plus a final NUL.
126 */
123#define SIM_CONTROL_OS_EXEC 18 127#define SIM_CONTROL_OS_EXEC 18
124 128
125//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), 129/**
126//! indicates that an interpreter (PT_INTERP) was loaded. Written to once 130 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
127//! for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a 131 * indicates that an interpreter (PT_INTERP) was loaded. Written to once
128//! hex load address starting with "0x", and "PATH" is the executable name. 132 * for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a
129//! 133 * hex load address starting with "0x", and "PATH" is the executable name.
134 */
130#define SIM_CONTROL_OS_INTERP 19 135#define SIM_CONTROL_OS_INTERP 19
131 136
132//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), 137/**
133//! indicates that a dll was loaded. Written to once for each character 138 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
134//! in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load 139 * indicates that a dll was loaded. Written to once for each character
135//! address starting with "0x", and "PATH" is the executable name. 140 * in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load
136//! 141 * address starting with "0x", and "PATH" is the executable name.
142 */
137#define SIM_CONTROL_DLOPEN 20 143#define SIM_CONTROL_DLOPEN 20
138 144
139//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), 145/**
140//! indicates that a dll was unloaded. Written to once for each character 146 * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
141//! in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load 147 * indicates that a dll was unloaded. Written to once for each character
142//! address starting with "0x". 148 * in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load
143//! 149 * address starting with "0x".
150 */
144#define SIM_CONTROL_DLCLOSE 21 151#define SIM_CONTROL_DLCLOSE 21
145 152
146//! If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8), 153/**
147//! indicates whether to allow data reads to remotely-cached 154 * If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8),
148//! dirty cache lines to be cached locally without grinder warnings or 155 * indicates whether to allow data reads to remotely-cached
149//! assertions (used by Linux kernel fast memcpy). 156 * dirty cache lines to be cached locally without grinder warnings or
150//! 157 * assertions (used by Linux kernel fast memcpy).
158 */
151#define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22 159#define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22
152 160
153//! If written to SPR_SIM_CONTROL, enables memory tracing. 161/** If written to SPR_SIM_CONTROL, enables memory tracing. */
154//!
155#define SIM_CONTROL_ENABLE_MEM_LOGGING 23 162#define SIM_CONTROL_ENABLE_MEM_LOGGING 23
156 163
157//! If written to SPR_SIM_CONTROL, disables memory tracing. 164/** If written to SPR_SIM_CONTROL, disables memory tracing. */
158//!
159#define SIM_CONTROL_DISABLE_MEM_LOGGING 24 165#define SIM_CONTROL_DISABLE_MEM_LOGGING 24
160 166
161//! If written to SPR_SIM_CONTROL, changes the shaping parameters of one of 167/**
162//! the gbe or xgbe shims. Must specify the shim id, the type, the units, and 168 * If written to SPR_SIM_CONTROL, changes the shaping parameters of one of
163//! the rate, as defined in SIM_SHAPING_SPR_ARG. 169 * the gbe or xgbe shims. Must specify the shim id, the type, the units, and
164//! 170 * the rate, as defined in SIM_SHAPING_SPR_ARG.
171 */
165#define SIM_CONTROL_SHAPING 25 172#define SIM_CONTROL_SHAPING 25
166 173
167//! If written to SPR_SIM_CONTROL, combined with character (shifted by 8), 174/**
168//! requests that a simulator command be executed. Written to once for each 175 * If written to SPR_SIM_CONTROL, combined with character (shifted by 8),
169//! character in the command, plus a final NUL. 176 * requests that a simulator command be executed. Written to once for each
170//! 177 * character in the command, plus a final NUL.
178 */
171#define SIM_CONTROL_COMMAND 26 179#define SIM_CONTROL_COMMAND 26
172 180
173//! If written to SPR_SIM_CONTROL, indicates that the simulated system 181/**
174//! is panicking, to allow debugging via --debug-on-panic. 182 * If written to SPR_SIM_CONTROL, indicates that the simulated system
175//! 183 * is panicking, to allow debugging via --debug-on-panic.
184 */
176#define SIM_CONTROL_PANIC 27 185#define SIM_CONTROL_PANIC 27
177 186
178//! If written to SPR_SIM_CONTROL, triggers a simulator syscall. 187/**
179//! See "sim_syscall()" for more info. 188 * If written to SPR_SIM_CONTROL, triggers a simulator syscall.
180//! 189 * See "sim_syscall()" for more info.
190 */
181#define SIM_CONTROL_SYSCALL 32 191#define SIM_CONTROL_SYSCALL 32
182 192
183//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), 193/**
184//! provides the pid that subsequent SIM_CONTROL_OS_FORK writes should 194 * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
185//! use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH. 195 * provides the pid that subsequent SIM_CONTROL_OS_FORK writes should
186//! 196 * use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH.
197 */
187#define SIM_CONTROL_OS_FORK_PARENT 33 198#define SIM_CONTROL_OS_FORK_PARENT 33
188 199
189//! If written to SPR_SIM_CONTROL, combined with a mPIPE shim number 200/**
190//! (shifted by 8), clears the pending magic data section. The cleared 201 * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
191//! pending magic data section and any subsequently appended magic bytes 202 * (shifted by 8), clears the pending magic data section. The cleared
192//! will only take effect when the classifier blast programmer is run. 203 * pending magic data section and any subsequently appended magic bytes
204 * will only take effect when the classifier blast programmer is run.
205 */
193#define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34 206#define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34
194 207
195//! If written to SPR_SIM_CONTROL, combined with a mPIPE shim number 208/**
196//! (shifted by 8) and a byte of data (shifted by 16), appends that byte 209 * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
197//! to the shim's pending magic data section. The pending magic data 210 * (shifted by 8) and a byte of data (shifted by 16), appends that byte
198//! section takes effect when the classifier blast programmer is run. 211 * to the shim's pending magic data section. The pending magic data
212 * section takes effect when the classifier blast programmer is run.
213 */
199#define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35 214#define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35
200 215
201//! If written to SPR_SIM_CONTROL, combined with a mPIPE shim number 216/**
202//! (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a 217 * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
203//! mask of links (shifted by 32), enable or disable the corresponding 218 * (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a
204//! mPIPE links. 219 * mask of links (shifted by 32), enable or disable the corresponding
220 * mPIPE links.
221 */
205#define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36 222#define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36
206 223
207//== Syscall numbers for use with "sim_syscall()".
208 224
209//! Syscall number for sim_add_watchpoint(). 225/*
210//! 226 * Syscall numbers for use with "sim_syscall()".
227 */
228
229/** Syscall number for sim_add_watchpoint(). */
211#define SIM_SYSCALL_ADD_WATCHPOINT 2 230#define SIM_SYSCALL_ADD_WATCHPOINT 2
212 231
213//! Syscall number for sim_remove_watchpoint(). 232/** Syscall number for sim_remove_watchpoint(). */
214//!
215#define SIM_SYSCALL_REMOVE_WATCHPOINT 3 233#define SIM_SYSCALL_REMOVE_WATCHPOINT 3
216 234
217//! Syscall number for sim_query_watchpoint(). 235/** Syscall number for sim_query_watchpoint(). */
218//!
219#define SIM_SYSCALL_QUERY_WATCHPOINT 4 236#define SIM_SYSCALL_QUERY_WATCHPOINT 4
220 237
221//! Syscall number that asserts that the cache lines whose 64-bit PA 238/**
222//! is passed as the second argument to sim_syscall(), and over a 239 * Syscall number that asserts that the cache lines whose 64-bit PA
223//! range passed as the third argument, are no longer in cache. 240 * is passed as the second argument to sim_syscall(), and over a
224//! The simulator raises an error if this is not the case. 241 * range passed as the third argument, are no longer in cache.
225//! 242 * The simulator raises an error if this is not the case.
243 */
226#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5 244#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
227 245
246/** Syscall number for sim_query_cpu_speed(). */
247#define SIM_SYSCALL_QUERY_CPU_SPEED 6
248
228 249
229//== Bit masks which can be shifted by 8, combined with 250/*
230//== SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL. 251 * Bit masks which can be shifted by 8, combined with
252 * SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL.
253 */
231 254
232//! @addtogroup arch_sim 255/**
233//! @{ 256 * @addtogroup arch_sim
257 * @{
258 */
234 259
235//! Enable --trace-cycle when passed to simulator_set_tracing(). 260/** Enable --trace-cycle when passed to simulator_set_tracing(). */
236//!
237#define SIM_TRACE_CYCLES 0x01 261#define SIM_TRACE_CYCLES 0x01
238 262
239//! Enable --trace-router when passed to simulator_set_tracing(). 263/** Enable --trace-router when passed to simulator_set_tracing(). */
240//!
241#define SIM_TRACE_ROUTER 0x02 264#define SIM_TRACE_ROUTER 0x02
242 265
243//! Enable --trace-register-writes when passed to simulator_set_tracing(). 266/** Enable --trace-register-writes when passed to simulator_set_tracing(). */
244//!
245#define SIM_TRACE_REGISTER_WRITES 0x04 267#define SIM_TRACE_REGISTER_WRITES 0x04
246 268
247//! Enable --trace-disasm when passed to simulator_set_tracing(). 269/** Enable --trace-disasm when passed to simulator_set_tracing(). */
248//!
249#define SIM_TRACE_DISASM 0x08 270#define SIM_TRACE_DISASM 0x08
250 271
251//! Enable --trace-stall-info when passed to simulator_set_tracing(). 272/** Enable --trace-stall-info when passed to simulator_set_tracing(). */
252//!
253#define SIM_TRACE_STALL_INFO 0x10 273#define SIM_TRACE_STALL_INFO 0x10
254 274
255//! Enable --trace-memory-controller when passed to simulator_set_tracing(). 275/** Enable --trace-memory-controller when passed to simulator_set_tracing(). */
256//!
257#define SIM_TRACE_MEMORY_CONTROLLER 0x20 276#define SIM_TRACE_MEMORY_CONTROLLER 0x20
258 277
259//! Enable --trace-l2 when passed to simulator_set_tracing(). 278/** Enable --trace-l2 when passed to simulator_set_tracing(). */
260//!
261#define SIM_TRACE_L2_CACHE 0x40 279#define SIM_TRACE_L2_CACHE 0x40
262 280
263//! Enable --trace-lines when passed to simulator_set_tracing(). 281/** Enable --trace-lines when passed to simulator_set_tracing(). */
264//!
265#define SIM_TRACE_LINES 0x80 282#define SIM_TRACE_LINES 0x80
266 283
267//! Turn off all tracing when passed to simulator_set_tracing(). 284/** Turn off all tracing when passed to simulator_set_tracing(). */
268//!
269#define SIM_TRACE_NONE 0 285#define SIM_TRACE_NONE 0
270 286
271//! Turn on all tracing when passed to simulator_set_tracing(). 287/** Turn on all tracing when passed to simulator_set_tracing(). */
272//!
273#define SIM_TRACE_ALL (-1) 288#define SIM_TRACE_ALL (-1)
274 289
275//! @} 290/** @} */
276 291
277//! Computes the value to write to SPR_SIM_CONTROL to set tracing flags. 292/** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */
278//!
279#define SIM_TRACE_SPR_ARG(mask) \ 293#define SIM_TRACE_SPR_ARG(mask) \
280 (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) 294 (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
281 295
282 296
283//== Bit masks which can be shifted by 8, combined with 297/*
284//== SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL. 298 * Bit masks which can be shifted by 8, combined with
299 * SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL.
300 */
285 301
286//! @addtogroup arch_sim 302/**
287//! @{ 303 * @addtogroup arch_sim
304 * @{
305 */
288 306
289//! Dump the general-purpose registers. 307/** Dump the general-purpose registers. */
290//!
291#define SIM_DUMP_REGS 0x001 308#define SIM_DUMP_REGS 0x001
292 309
293//! Dump the SPRs. 310/** Dump the SPRs. */
294//!
295#define SIM_DUMP_SPRS 0x002 311#define SIM_DUMP_SPRS 0x002
296 312
297//! Dump the ITLB. 313/** Dump the ITLB. */
298//!
299#define SIM_DUMP_ITLB 0x004 314#define SIM_DUMP_ITLB 0x004
300 315
301//! Dump the DTLB. 316/** Dump the DTLB. */
302//!
303#define SIM_DUMP_DTLB 0x008 317#define SIM_DUMP_DTLB 0x008
304 318
305//! Dump the L1 I-cache. 319/** Dump the L1 I-cache. */
306//!
307#define SIM_DUMP_L1I 0x010 320#define SIM_DUMP_L1I 0x010
308 321
309//! Dump the L1 D-cache. 322/** Dump the L1 D-cache. */
310//!
311#define SIM_DUMP_L1D 0x020 323#define SIM_DUMP_L1D 0x020
312 324
313//! Dump the L2 cache. 325/** Dump the L2 cache. */
314//!
315#define SIM_DUMP_L2 0x040 326#define SIM_DUMP_L2 0x040
316 327
317//! Dump the switch registers. 328/** Dump the switch registers. */
318//!
319#define SIM_DUMP_SNREGS 0x080 329#define SIM_DUMP_SNREGS 0x080
320 330
321//! Dump the switch ITLB. 331/** Dump the switch ITLB. */
322//!
323#define SIM_DUMP_SNITLB 0x100 332#define SIM_DUMP_SNITLB 0x100
324 333
325//! Dump the switch L1 I-cache. 334/** Dump the switch L1 I-cache. */
326//!
327#define SIM_DUMP_SNL1I 0x200 335#define SIM_DUMP_SNL1I 0x200
328 336
329//! Dump the current backtrace. 337/** Dump the current backtrace. */
330//!
331#define SIM_DUMP_BACKTRACE 0x400 338#define SIM_DUMP_BACKTRACE 0x400
332 339
333//! Only dump valid lines in caches. 340/** Only dump valid lines in caches. */
334//!
335#define SIM_DUMP_VALID_LINES 0x800 341#define SIM_DUMP_VALID_LINES 0x800
336 342
337//! Dump everything that is dumpable. 343/** Dump everything that is dumpable. */
338//!
339#define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES) 344#define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES)
340 345
341// @} 346/** @} */
342 347
343//! Computes the value to write to SPR_SIM_CONTROL to dump machine state. 348/** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */
344//!
345#define SIM_DUMP_SPR_ARG(mask) \ 349#define SIM_DUMP_SPR_ARG(mask) \
346 (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) 350 (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
347 351
348 352
349//== Bit masks which can be shifted by 8, combined with 353/*
350//== SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL. 354 * Bit masks which can be shifted by 8, combined with
355 * SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL.
356 */
351 357
352//! @addtogroup arch_sim 358/**
353//! @{ 359 * @addtogroup arch_sim
360 * @{
361 */
354 362
355//! Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. 363/** Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
356//!
357#define SIM_CHIP_MEMCTL 0x001 364#define SIM_CHIP_MEMCTL 0x001
358 365
359//! Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. 366/** Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
360//!
361#define SIM_CHIP_XAUI 0x002 367#define SIM_CHIP_XAUI 0x002
362 368
363//! Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. 369/** Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
364//!
365#define SIM_CHIP_PCIE 0x004 370#define SIM_CHIP_PCIE 0x004
366 371
367//! Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. 372/** Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
368//!
369#define SIM_CHIP_MPIPE 0x008 373#define SIM_CHIP_MPIPE 0x008
370 374
371//! Reference all chip devices. 375/** Use with with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
372//! 376#define SIM_CHIP_TRIO 0x010
377
378/** Reference all chip devices. */
373#define SIM_CHIP_ALL (-1) 379#define SIM_CHIP_ALL (-1)
374 380
375//! @} 381/** @} */
376 382
377//! Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. 383/** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */
378//!
379#define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \ 384#define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \
380 (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) 385 (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
381 386
382//! Computes the value to write to SPR_SIM_CONTROL to disable chip statistics. 387/** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/
383//!
384#define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \ 388#define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \
385 (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) 389 (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
386 390
387//! Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. 391/** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */
388//!
389#define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \ 392#define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \
390 (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) 393 (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
391 394
392 395
393 396
394// Shim bitrate controls. 397/* Shim bitrate controls. */
395 398
396//! The number of bits used to store the shim id. 399/** The number of bits used to store the shim id. */
397//!
398#define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3 400#define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3
399 401
400//! @addtogroup arch_sim 402/**
401//! @{ 403 * @addtogroup arch_sim
404 * @{
405 */
402 406
403//! Change the gbe 0 bitrate. 407/** Change the gbe 0 bitrate. */
404//!
405#define SIM_CONTROL_SHAPING_GBE_0 0x0 408#define SIM_CONTROL_SHAPING_GBE_0 0x0
406 409
407//! Change the gbe 1 bitrate. 410/** Change the gbe 1 bitrate. */
408//!
409#define SIM_CONTROL_SHAPING_GBE_1 0x1 411#define SIM_CONTROL_SHAPING_GBE_1 0x1
410 412
411//! Change the gbe 2 bitrate. 413/** Change the gbe 2 bitrate. */
412//!
413#define SIM_CONTROL_SHAPING_GBE_2 0x2 414#define SIM_CONTROL_SHAPING_GBE_2 0x2
414 415
415//! Change the gbe 3 bitrate. 416/** Change the gbe 3 bitrate. */
416//!
417#define SIM_CONTROL_SHAPING_GBE_3 0x3 417#define SIM_CONTROL_SHAPING_GBE_3 0x3
418 418
419//! Change the xgbe 0 bitrate. 419/** Change the xgbe 0 bitrate. */
420//!
421#define SIM_CONTROL_SHAPING_XGBE_0 0x4 420#define SIM_CONTROL_SHAPING_XGBE_0 0x4
422 421
423//! Change the xgbe 1 bitrate. 422/** Change the xgbe 1 bitrate. */
424//!
425#define SIM_CONTROL_SHAPING_XGBE_1 0x5 423#define SIM_CONTROL_SHAPING_XGBE_1 0x5
426 424
427//! The type of shaping to do. 425/** The type of shaping to do. */
428//!
429#define SIM_CONTROL_SHAPING_TYPE_BITS 2 426#define SIM_CONTROL_SHAPING_TYPE_BITS 2
430 427
431//! Control the multiplier. 428/** Control the multiplier. */
432//!
433#define SIM_CONTROL_SHAPING_MULTIPLIER 0 429#define SIM_CONTROL_SHAPING_MULTIPLIER 0
434 430
435//! Control the PPS. 431/** Control the PPS. */
436//!
437#define SIM_CONTROL_SHAPING_PPS 1 432#define SIM_CONTROL_SHAPING_PPS 1
438 433
439//! Control the BPS. 434/** Control the BPS. */
440//!
441#define SIM_CONTROL_SHAPING_BPS 2 435#define SIM_CONTROL_SHAPING_BPS 2
442 436
443//! The number of bits for the units for the shaping parameter. 437/** The number of bits for the units for the shaping parameter. */
444//!
445#define SIM_CONTROL_SHAPING_UNITS_BITS 2 438#define SIM_CONTROL_SHAPING_UNITS_BITS 2
446 439
447//! Provide a number in single units. 440/** Provide a number in single units. */
448//!
449#define SIM_CONTROL_SHAPING_UNITS_SINGLE 0 441#define SIM_CONTROL_SHAPING_UNITS_SINGLE 0
450 442
451//! Provide a number in kilo units. 443/** Provide a number in kilo units. */
452//!
453#define SIM_CONTROL_SHAPING_UNITS_KILO 1 444#define SIM_CONTROL_SHAPING_UNITS_KILO 1
454 445
455//! Provide a number in mega units. 446/** Provide a number in mega units. */
456//!
457#define SIM_CONTROL_SHAPING_UNITS_MEGA 2 447#define SIM_CONTROL_SHAPING_UNITS_MEGA 2
458 448
459//! Provide a number in giga units. 449/** Provide a number in giga units. */
460//!
461#define SIM_CONTROL_SHAPING_UNITS_GIGA 3 450#define SIM_CONTROL_SHAPING_UNITS_GIGA 3
462 451
463// @} 452/** @} */
464 453
465//! How many bits are available for the rate. 454/** How many bits are available for the rate. */
466//!
467#define SIM_CONTROL_SHAPING_RATE_BITS \ 455#define SIM_CONTROL_SHAPING_RATE_BITS \
468 (32 - (_SIM_CONTROL_OPERATOR_BITS + \ 456 (32 - (_SIM_CONTROL_OPERATOR_BITS + \
469 SIM_CONTROL_SHAPING_SHIM_ID_BITS + \ 457 SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
470 SIM_CONTROL_SHAPING_TYPE_BITS + \ 458 SIM_CONTROL_SHAPING_TYPE_BITS + \
471 SIM_CONTROL_SHAPING_UNITS_BITS)) 459 SIM_CONTROL_SHAPING_UNITS_BITS))
472 460
473//! Computes the value to write to SPR_SIM_CONTROL to change a bitrate. 461/** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */
474//!
475#define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \ 462#define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \
476 (SIM_CONTROL_SHAPING | \ 463 (SIM_CONTROL_SHAPING | \
477 ((shim) | \ 464 ((shim) | \
@@ -483,30 +470,36 @@
483 SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS) 470 SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS)
484 471
485 472
486//== Values returned when reading SPR_SIM_CONTROL. 473/*
487// ISSUE: These names should share a longer common prefix. 474 * Values returned when reading SPR_SIM_CONTROL.
475 * ISSUE: These names should share a longer common prefix.
476 */
488 477
489//! When reading SPR_SIM_CONTROL, the mask of simulator tracing bits 478/**
490//! (SIM_TRACE_xxx values). 479 * When reading SPR_SIM_CONTROL, the mask of simulator tracing bits
491//! 480 * (SIM_TRACE_xxx values).
481 */
492#define SIM_TRACE_FLAG_MASK 0xFFFF 482#define SIM_TRACE_FLAG_MASK 0xFFFF
493 483
494//! When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. 484/** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */
495//!
496#define SIM_PROFILER_ENABLED_MASK 0x10000 485#define SIM_PROFILER_ENABLED_MASK 0x10000
497 486
498 487
499//== Special arguments for "SIM_CONTROL_PUTC". 488/*
489 * Special arguments for "SIM_CONTROL_PUTC".
490 */
500 491
501//! Flag value for forcing a PUTC string-flush, including 492/**
502//! coordinate/cycle prefix and newline. 493 * Flag value for forcing a PUTC string-flush, including
503//! 494 * coordinate/cycle prefix and newline.
495 */
504#define SIM_PUTC_FLUSH_STRING 0x100 496#define SIM_PUTC_FLUSH_STRING 0x100
505 497
506//! Flag value for forcing a PUTC binary-data-flush, which skips the 498/**
507//! prefix and does not append a newline. 499 * Flag value for forcing a PUTC binary-data-flush, which skips the
508//! 500 * prefix and does not append a newline.
501 */
509#define SIM_PUTC_FLUSH_BINARY 0x101 502#define SIM_PUTC_FLUSH_BINARY 0x101
510 503
511 504
512#endif //__ARCH_SIM_DEF_H__ 505#endif /* __ARCH_SIM_DEF_H__ */
diff --git a/arch/tile/include/arch/spr_def.h b/arch/tile/include/arch/spr_def.h
index c8fdbd9a45e6..f548efeb2de3 100644
--- a/arch/tile/include/arch/spr_def.h
+++ b/arch/tile/include/arch/spr_def.h
@@ -12,8 +12,102 @@
12 * more details. 12 * more details.
13 */ 13 */
14 14
15/* Include the proper base SPR definition file. */
15#ifdef __tilegx__ 16#ifdef __tilegx__
16#include <arch/spr_def_64.h> 17#include <arch/spr_def_64.h>
17#else 18#else
18#include <arch/spr_def_32.h> 19#include <arch/spr_def_32.h>
19#endif 20#endif
21
22#ifdef __KERNEL__
23
24/*
25 * In addition to including the proper base SPR definition file, depending
26 * on machine architecture, this file defines several macros which allow
27 * kernel code to use protection-level dependent SPRs without worrying
28 * about which PL it's running at. In these macros, the PL that the SPR
29 * or interrupt number applies to is replaced by K.
30 */
31
32#if CONFIG_KERNEL_PL != 1 && CONFIG_KERNEL_PL != 2
33#error CONFIG_KERNEL_PL must be 1 or 2
34#endif
35
36/* Concatenate 4 strings. */
37#define __concat4(a, b, c, d) a ## b ## c ## d
38#define _concat4(a, b, c, d) __concat4(a, b, c, d)
39
40#ifdef __tilegx__
41
42/* TILE-Gx dependent, protection-level dependent SPRs. */
43
44#define SPR_INTERRUPT_MASK_K \
45 _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL,,)
46#define SPR_INTERRUPT_MASK_SET_K \
47 _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL,,)
48#define SPR_INTERRUPT_MASK_RESET_K \
49 _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL,,)
50#define SPR_INTERRUPT_VECTOR_BASE_K \
51 _concat4(SPR_INTERRUPT_VECTOR_BASE_, CONFIG_KERNEL_PL,,)
52
53#define SPR_IPI_MASK_K \
54 _concat4(SPR_IPI_MASK_, CONFIG_KERNEL_PL,,)
55#define SPR_IPI_MASK_RESET_K \
56 _concat4(SPR_IPI_MASK_RESET_, CONFIG_KERNEL_PL,,)
57#define SPR_IPI_MASK_SET_K \
58 _concat4(SPR_IPI_MASK_SET_, CONFIG_KERNEL_PL,,)
59#define SPR_IPI_EVENT_K \
60 _concat4(SPR_IPI_EVENT_, CONFIG_KERNEL_PL,,)
61#define SPR_IPI_EVENT_RESET_K \
62 _concat4(SPR_IPI_EVENT_RESET_, CONFIG_KERNEL_PL,,)
63#define SPR_IPI_MASK_SET_K \
64 _concat4(SPR_IPI_MASK_SET_, CONFIG_KERNEL_PL,,)
65#define INT_IPI_K \
66 _concat4(INT_IPI_, CONFIG_KERNEL_PL,,)
67
68#define SPR_SINGLE_STEP_CONTROL_K \
69 _concat4(SPR_SINGLE_STEP_CONTROL_, CONFIG_KERNEL_PL,,)
70#define SPR_SINGLE_STEP_EN_K_K \
71 _concat4(SPR_SINGLE_STEP_EN_, CONFIG_KERNEL_PL, _, CONFIG_KERNEL_PL)
72#define INT_SINGLE_STEP_K \
73 _concat4(INT_SINGLE_STEP_, CONFIG_KERNEL_PL,,)
74
75#else
76
77/* TILEPro dependent, protection-level dependent SPRs. */
78
79#define SPR_INTERRUPT_MASK_K_0 \
80 _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _0,)
81#define SPR_INTERRUPT_MASK_K_1 \
82 _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _1,)
83#define SPR_INTERRUPT_MASK_SET_K_0 \
84 _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _0,)
85#define SPR_INTERRUPT_MASK_SET_K_1 \
86 _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _1,)
87#define SPR_INTERRUPT_MASK_RESET_K_0 \
88 _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _0,)
89#define SPR_INTERRUPT_MASK_RESET_K_1 \
90 _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _1,)
91
92#endif
93
94/* Generic protection-level dependent SPRs. */
95
96#define SPR_SYSTEM_SAVE_K_0 \
97 _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _0,)
98#define SPR_SYSTEM_SAVE_K_1 \
99 _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _1,)
100#define SPR_SYSTEM_SAVE_K_2 \
101 _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _2,)
102#define SPR_SYSTEM_SAVE_K_3 \
103 _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _3,)
104#define SPR_EX_CONTEXT_K_0 \
105 _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _0,)
106#define SPR_EX_CONTEXT_K_1 \
107 _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _1,)
108#define SPR_INTCTRL_K_STATUS \
109 _concat4(SPR_INTCTRL_, CONFIG_KERNEL_PL, _STATUS,)
110#define INT_INTCTRL_K \
111 _concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,)
112
113#endif /* __KERNEL__ */
diff --git a/arch/tile/include/arch/spr_def_32.h b/arch/tile/include/arch/spr_def_32.h
index b4fc06864df6..bbc1f4c924ee 100644
--- a/arch/tile/include/arch/spr_def_32.h
+++ b/arch/tile/include/arch/spr_def_32.h
@@ -56,58 +56,93 @@
56#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 56#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
57#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 57#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
58#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 58#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
59#define SPR_EX_CONTEXT_2_0 0x4605
60#define SPR_EX_CONTEXT_2_1 0x4606
61#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
62#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
63#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
64#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
65#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
66#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
59#define SPR_FAIL 0x4e09 67#define SPR_FAIL 0x4e09
60#define SPR_INTCTRL_0_STATUS 0x4a07 68#define SPR_INTCTRL_0_STATUS 0x4a07
61#define SPR_INTCTRL_1_STATUS 0x4807 69#define SPR_INTCTRL_1_STATUS 0x4807
70#define SPR_INTCTRL_2_STATUS 0x4607
62#define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a 71#define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a
63#define SPR_INTERRUPT_MASK_0_0 0x4a08 72#define SPR_INTERRUPT_MASK_0_0 0x4a08
64#define SPR_INTERRUPT_MASK_0_1 0x4a09 73#define SPR_INTERRUPT_MASK_0_1 0x4a09
65#define SPR_INTERRUPT_MASK_1_0 0x4809 74#define SPR_INTERRUPT_MASK_1_0 0x4809
66#define SPR_INTERRUPT_MASK_1_1 0x480a 75#define SPR_INTERRUPT_MASK_1_1 0x480a
76#define SPR_INTERRUPT_MASK_2_0 0x4608
77#define SPR_INTERRUPT_MASK_2_1 0x4609
67#define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a 78#define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a
68#define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b 79#define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b
69#define SPR_INTERRUPT_MASK_RESET_1_0 0x480b 80#define SPR_INTERRUPT_MASK_RESET_1_0 0x480b
70#define SPR_INTERRUPT_MASK_RESET_1_1 0x480c 81#define SPR_INTERRUPT_MASK_RESET_1_1 0x480c
82#define SPR_INTERRUPT_MASK_RESET_2_0 0x460a
83#define SPR_INTERRUPT_MASK_RESET_2_1 0x460b
71#define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c 84#define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c
72#define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d 85#define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d
73#define SPR_INTERRUPT_MASK_SET_1_0 0x480d 86#define SPR_INTERRUPT_MASK_SET_1_0 0x480d
74#define SPR_INTERRUPT_MASK_SET_1_1 0x480e 87#define SPR_INTERRUPT_MASK_SET_1_1 0x480e
88#define SPR_INTERRUPT_MASK_SET_2_0 0x460c
89#define SPR_INTERRUPT_MASK_SET_2_1 0x460d
75#define SPR_MPL_DMA_CPL_SET_0 0x5800 90#define SPR_MPL_DMA_CPL_SET_0 0x5800
76#define SPR_MPL_DMA_CPL_SET_1 0x5801 91#define SPR_MPL_DMA_CPL_SET_1 0x5801
92#define SPR_MPL_DMA_CPL_SET_2 0x5802
77#define SPR_MPL_DMA_NOTIFY_SET_0 0x3800 93#define SPR_MPL_DMA_NOTIFY_SET_0 0x3800
78#define SPR_MPL_DMA_NOTIFY_SET_1 0x3801 94#define SPR_MPL_DMA_NOTIFY_SET_1 0x3801
95#define SPR_MPL_DMA_NOTIFY_SET_2 0x3802
79#define SPR_MPL_INTCTRL_0_SET_0 0x4a00 96#define SPR_MPL_INTCTRL_0_SET_0 0x4a00
80#define SPR_MPL_INTCTRL_0_SET_1 0x4a01 97#define SPR_MPL_INTCTRL_0_SET_1 0x4a01
98#define SPR_MPL_INTCTRL_0_SET_2 0x4a02
81#define SPR_MPL_INTCTRL_1_SET_0 0x4800 99#define SPR_MPL_INTCTRL_1_SET_0 0x4800
82#define SPR_MPL_INTCTRL_1_SET_1 0x4801 100#define SPR_MPL_INTCTRL_1_SET_1 0x4801
101#define SPR_MPL_INTCTRL_1_SET_2 0x4802
102#define SPR_MPL_INTCTRL_2_SET_0 0x4600
103#define SPR_MPL_INTCTRL_2_SET_1 0x4601
104#define SPR_MPL_INTCTRL_2_SET_2 0x4602
83#define SPR_MPL_SN_ACCESS_SET_0 0x0800 105#define SPR_MPL_SN_ACCESS_SET_0 0x0800
84#define SPR_MPL_SN_ACCESS_SET_1 0x0801 106#define SPR_MPL_SN_ACCESS_SET_1 0x0801
107#define SPR_MPL_SN_ACCESS_SET_2 0x0802
85#define SPR_MPL_SN_CPL_SET_0 0x5a00 108#define SPR_MPL_SN_CPL_SET_0 0x5a00
86#define SPR_MPL_SN_CPL_SET_1 0x5a01 109#define SPR_MPL_SN_CPL_SET_1 0x5a01
110#define SPR_MPL_SN_CPL_SET_2 0x5a02
87#define SPR_MPL_SN_FIREWALL_SET_0 0x2c00 111#define SPR_MPL_SN_FIREWALL_SET_0 0x2c00
88#define SPR_MPL_SN_FIREWALL_SET_1 0x2c01 112#define SPR_MPL_SN_FIREWALL_SET_1 0x2c01
113#define SPR_MPL_SN_FIREWALL_SET_2 0x2c02
89#define SPR_MPL_SN_NOTIFY_SET_0 0x2a00 114#define SPR_MPL_SN_NOTIFY_SET_0 0x2a00
90#define SPR_MPL_SN_NOTIFY_SET_1 0x2a01 115#define SPR_MPL_SN_NOTIFY_SET_1 0x2a01
116#define SPR_MPL_SN_NOTIFY_SET_2 0x2a02
91#define SPR_MPL_UDN_ACCESS_SET_0 0x0c00 117#define SPR_MPL_UDN_ACCESS_SET_0 0x0c00
92#define SPR_MPL_UDN_ACCESS_SET_1 0x0c01 118#define SPR_MPL_UDN_ACCESS_SET_1 0x0c01
119#define SPR_MPL_UDN_ACCESS_SET_2 0x0c02
93#define SPR_MPL_UDN_AVAIL_SET_0 0x4000 120#define SPR_MPL_UDN_AVAIL_SET_0 0x4000
94#define SPR_MPL_UDN_AVAIL_SET_1 0x4001 121#define SPR_MPL_UDN_AVAIL_SET_1 0x4001
122#define SPR_MPL_UDN_AVAIL_SET_2 0x4002
95#define SPR_MPL_UDN_CA_SET_0 0x3c00 123#define SPR_MPL_UDN_CA_SET_0 0x3c00
96#define SPR_MPL_UDN_CA_SET_1 0x3c01 124#define SPR_MPL_UDN_CA_SET_1 0x3c01
125#define SPR_MPL_UDN_CA_SET_2 0x3c02
97#define SPR_MPL_UDN_COMPLETE_SET_0 0x1400 126#define SPR_MPL_UDN_COMPLETE_SET_0 0x1400
98#define SPR_MPL_UDN_COMPLETE_SET_1 0x1401 127#define SPR_MPL_UDN_COMPLETE_SET_1 0x1401
128#define SPR_MPL_UDN_COMPLETE_SET_2 0x1402
99#define SPR_MPL_UDN_FIREWALL_SET_0 0x3000 129#define SPR_MPL_UDN_FIREWALL_SET_0 0x3000
100#define SPR_MPL_UDN_FIREWALL_SET_1 0x3001 130#define SPR_MPL_UDN_FIREWALL_SET_1 0x3001
131#define SPR_MPL_UDN_FIREWALL_SET_2 0x3002
101#define SPR_MPL_UDN_REFILL_SET_0 0x1000 132#define SPR_MPL_UDN_REFILL_SET_0 0x1000
102#define SPR_MPL_UDN_REFILL_SET_1 0x1001 133#define SPR_MPL_UDN_REFILL_SET_1 0x1001
134#define SPR_MPL_UDN_REFILL_SET_2 0x1002
103#define SPR_MPL_UDN_TIMER_SET_0 0x3600 135#define SPR_MPL_UDN_TIMER_SET_0 0x3600
104#define SPR_MPL_UDN_TIMER_SET_1 0x3601 136#define SPR_MPL_UDN_TIMER_SET_1 0x3601
137#define SPR_MPL_UDN_TIMER_SET_2 0x3602
105#define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00 138#define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00
106#define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01 139#define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01
140#define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02
107#define SPR_PASS 0x4e0b 141#define SPR_PASS 0x4e0b
108#define SPR_PERF_COUNT_0 0x4205 142#define SPR_PERF_COUNT_0 0x4205
109#define SPR_PERF_COUNT_1 0x4206 143#define SPR_PERF_COUNT_1 0x4206
110#define SPR_PERF_COUNT_CTL 0x4207 144#define SPR_PERF_COUNT_CTL 0x4207
145#define SPR_PERF_COUNT_DN_CTL 0x4210
111#define SPR_PERF_COUNT_STS 0x4208 146#define SPR_PERF_COUNT_STS 0x4208
112#define SPR_PROC_STATUS 0x4f00 147#define SPR_PROC_STATUS 0x4f00
113#define SPR_SIM_CONTROL 0x4e0c 148#define SPR_SIM_CONTROL 0x4e0c
@@ -124,6 +159,10 @@
124#define SPR_SYSTEM_SAVE_1_1 0x4901 159#define SPR_SYSTEM_SAVE_1_1 0x4901
125#define SPR_SYSTEM_SAVE_1_2 0x4902 160#define SPR_SYSTEM_SAVE_1_2 0x4902
126#define SPR_SYSTEM_SAVE_1_3 0x4903 161#define SPR_SYSTEM_SAVE_1_3 0x4903
162#define SPR_SYSTEM_SAVE_2_0 0x4700
163#define SPR_SYSTEM_SAVE_2_1 0x4701
164#define SPR_SYSTEM_SAVE_2_2 0x4702
165#define SPR_SYSTEM_SAVE_2_3 0x4703
127#define SPR_TILE_COORD 0x4c17 166#define SPR_TILE_COORD 0x4c17
128#define SPR_TILE_RTF_HWM 0x4e10 167#define SPR_TILE_RTF_HWM 0x4e10
129#define SPR_TILE_TIMER_CONTROL 0x3205 168#define SPR_TILE_TIMER_CONTROL 0x3205
diff --git a/arch/tile/include/arch/spr_def_64.h b/arch/tile/include/arch/spr_def_64.h
new file mode 100644
index 000000000000..cd3e5f95d5fd
--- /dev/null
+++ b/arch/tile/include/arch/spr_def_64.h
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __DOXYGEN__
16
17#ifndef __ARCH_SPR_DEF_H__
18#define __ARCH_SPR_DEF_H__
19
20#define SPR_AUX_PERF_COUNT_0 0x2105
21#define SPR_AUX_PERF_COUNT_1 0x2106
22#define SPR_AUX_PERF_COUNT_CTL 0x2107
23#define SPR_AUX_PERF_COUNT_STS 0x2108
24#define SPR_CMPEXCH_VALUE 0x2780
25#define SPR_CYCLE 0x2781
26#define SPR_DONE 0x2705
27#define SPR_DSTREAM_PF 0x2706
28#define SPR_EVENT_BEGIN 0x2782
29#define SPR_EVENT_END 0x2783
30#define SPR_EX_CONTEXT_0_0 0x2580
31#define SPR_EX_CONTEXT_0_1 0x2581
32#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
33#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
34#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
35#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
36#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
37#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
38#define SPR_EX_CONTEXT_1_0 0x2480
39#define SPR_EX_CONTEXT_1_1 0x2481
40#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
41#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
42#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
43#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
44#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
45#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
46#define SPR_EX_CONTEXT_2_0 0x2380
47#define SPR_EX_CONTEXT_2_1 0x2381
48#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
49#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
50#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
51#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
52#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
53#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
54#define SPR_FAIL 0x2707
55#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
56#define SPR_INTCTRL_0_STATUS 0x2505
57#define SPR_INTCTRL_1_STATUS 0x2405
58#define SPR_INTCTRL_2_STATUS 0x2305
59#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
60#define SPR_INTERRUPT_MASK_0 0x2506
61#define SPR_INTERRUPT_MASK_1 0x2406
62#define SPR_INTERRUPT_MASK_2 0x2306
63#define SPR_INTERRUPT_MASK_RESET_0 0x2507
64#define SPR_INTERRUPT_MASK_RESET_1 0x2407
65#define SPR_INTERRUPT_MASK_RESET_2 0x2307
66#define SPR_INTERRUPT_MASK_SET_0 0x2508
67#define SPR_INTERRUPT_MASK_SET_1 0x2408
68#define SPR_INTERRUPT_MASK_SET_2 0x2308
69#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
70#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
71#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
72#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
73#define SPR_IPI_EVENT_0 0x1f05
74#define SPR_IPI_EVENT_1 0x1e05
75#define SPR_IPI_EVENT_2 0x1d05
76#define SPR_IPI_EVENT_RESET_0 0x1f06
77#define SPR_IPI_EVENT_RESET_1 0x1e06
78#define SPR_IPI_EVENT_RESET_2 0x1d06
79#define SPR_IPI_EVENT_SET_0 0x1f07
80#define SPR_IPI_EVENT_SET_1 0x1e07
81#define SPR_IPI_EVENT_SET_2 0x1d07
82#define SPR_IPI_MASK_0 0x1f08
83#define SPR_IPI_MASK_1 0x1e08
84#define SPR_IPI_MASK_2 0x1d08
85#define SPR_IPI_MASK_RESET_0 0x1f09
86#define SPR_IPI_MASK_RESET_1 0x1e09
87#define SPR_IPI_MASK_RESET_2 0x1d09
88#define SPR_IPI_MASK_SET_0 0x1f0a
89#define SPR_IPI_MASK_SET_1 0x1e0a
90#define SPR_IPI_MASK_SET_2 0x1d0a
91#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
92#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
93#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
94#define SPR_MPL_INTCTRL_0_SET_0 0x2500
95#define SPR_MPL_INTCTRL_0_SET_1 0x2501
96#define SPR_MPL_INTCTRL_0_SET_2 0x2502
97#define SPR_MPL_INTCTRL_1_SET_0 0x2400
98#define SPR_MPL_INTCTRL_1_SET_1 0x2401
99#define SPR_MPL_INTCTRL_1_SET_2 0x2402
100#define SPR_MPL_INTCTRL_2_SET_0 0x2300
101#define SPR_MPL_INTCTRL_2_SET_1 0x2301
102#define SPR_MPL_INTCTRL_2_SET_2 0x2302
103#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
104#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
105#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
106#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
107#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
108#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
109#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
110#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
111#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
112#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
113#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
114#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
115#define SPR_MPL_UDN_TIMER_SET_0 0x1900
116#define SPR_MPL_UDN_TIMER_SET_1 0x1901
117#define SPR_MPL_UDN_TIMER_SET_2 0x1902
118#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
119#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
120#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
121#define SPR_PASS 0x2709
122#define SPR_PERF_COUNT_0 0x2005
123#define SPR_PERF_COUNT_1 0x2006
124#define SPR_PERF_COUNT_CTL 0x2007
125#define SPR_PERF_COUNT_DN_CTL 0x2008
126#define SPR_PERF_COUNT_STS 0x2009
127#define SPR_PROC_STATUS 0x2784
128#define SPR_SIM_CONTROL 0x2785
129#define SPR_SINGLE_STEP_CONTROL_0 0x0405
130#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
131#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
132#define SPR_SINGLE_STEP_CONTROL_1 0x0305
133#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
134#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
135#define SPR_SINGLE_STEP_CONTROL_2 0x0205
136#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
137#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
138#define SPR_SINGLE_STEP_EN_0_0 0x250a
139#define SPR_SINGLE_STEP_EN_0_1 0x240a
140#define SPR_SINGLE_STEP_EN_0_2 0x230a
141#define SPR_SINGLE_STEP_EN_1_0 0x250b
142#define SPR_SINGLE_STEP_EN_1_1 0x240b
143#define SPR_SINGLE_STEP_EN_1_2 0x230b
144#define SPR_SINGLE_STEP_EN_2_0 0x250c
145#define SPR_SINGLE_STEP_EN_2_1 0x240c
146#define SPR_SINGLE_STEP_EN_2_2 0x230c
147#define SPR_SYSTEM_SAVE_0_0 0x2582
148#define SPR_SYSTEM_SAVE_0_1 0x2583
149#define SPR_SYSTEM_SAVE_0_2 0x2584
150#define SPR_SYSTEM_SAVE_0_3 0x2585
151#define SPR_SYSTEM_SAVE_1_0 0x2482
152#define SPR_SYSTEM_SAVE_1_1 0x2483
153#define SPR_SYSTEM_SAVE_1_2 0x2484
154#define SPR_SYSTEM_SAVE_1_3 0x2485
155#define SPR_SYSTEM_SAVE_2_0 0x2382
156#define SPR_SYSTEM_SAVE_2_1 0x2383
157#define SPR_SYSTEM_SAVE_2_2 0x2384
158#define SPR_SYSTEM_SAVE_2_3 0x2385
159#define SPR_TILE_COORD 0x270b
160#define SPR_TILE_RTF_HWM 0x270c
161#define SPR_TILE_TIMER_CONTROL 0x1605
162#define SPR_UDN_AVAIL_EN 0x1b05
163#define SPR_UDN_DATA_AVAIL 0x0b80
164#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
165#define SPR_UDN_DEMUX_COUNT_0 0x0b05
166#define SPR_UDN_DEMUX_COUNT_1 0x0b06
167#define SPR_UDN_DEMUX_COUNT_2 0x0b07
168#define SPR_UDN_DEMUX_COUNT_3 0x0b08
169#define SPR_UDN_DIRECTION_PROTECT 0x1505
170
171#endif /* !defined(__ARCH_SPR_DEF_H__) */
172
173#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/asm/Kbuild b/arch/tile/include/asm/Kbuild
index 3b8f55b82dee..849ab2fa1f5c 100644
--- a/arch/tile/include/asm/Kbuild
+++ b/arch/tile/include/asm/Kbuild
@@ -1,3 +1,4 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += ucontext.h 3header-y += ucontext.h
4header-y += hardwall.h
diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h
index b8c49f98a44c..739cfe0499d1 100644
--- a/arch/tile/include/asm/atomic.h
+++ b/arch/tile/include/asm/atomic.h
@@ -32,7 +32,7 @@
32 */ 32 */
33static inline int atomic_read(const atomic_t *v) 33static inline int atomic_read(const atomic_t *v)
34{ 34{
35 return v->counter; 35 return ACCESS_ONCE(v->counter);
36} 36}
37 37
38/** 38/**
@@ -130,17 +130,52 @@ static inline int atomic_read(const atomic_t *v)
130 */ 130 */
131#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) 131#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
132 132
133
134/*
135 * We define xchg() and cmpxchg() in the included headers.
136 * Note that we do not define __HAVE_ARCH_CMPXCHG, since that would imply
137 * that cmpxchg() is an efficient operation, which is not particularly true.
138 */
139
140/* Nonexistent functions intended to cause link errors. */ 133/* Nonexistent functions intended to cause link errors. */
141extern unsigned long __xchg_called_with_bad_pointer(void); 134extern unsigned long __xchg_called_with_bad_pointer(void);
142extern unsigned long __cmpxchg_called_with_bad_pointer(void); 135extern unsigned long __cmpxchg_called_with_bad_pointer(void);
143 136
137#define xchg(ptr, x) \
138 ({ \
139 typeof(*(ptr)) __x; \
140 switch (sizeof(*(ptr))) { \
141 case 4: \
142 __x = (typeof(__x))(typeof(__x-__x))atomic_xchg( \
143 (atomic_t *)(ptr), \
144 (u32)(typeof((x)-(x)))(x)); \
145 break; \
146 case 8: \
147 __x = (typeof(__x))(typeof(__x-__x))atomic64_xchg( \
148 (atomic64_t *)(ptr), \
149 (u64)(typeof((x)-(x)))(x)); \
150 break; \
151 default: \
152 __xchg_called_with_bad_pointer(); \
153 } \
154 __x; \
155 })
156
157#define cmpxchg(ptr, o, n) \
158 ({ \
159 typeof(*(ptr)) __x; \
160 switch (sizeof(*(ptr))) { \
161 case 4: \
162 __x = (typeof(__x))(typeof(__x-__x))atomic_cmpxchg( \
163 (atomic_t *)(ptr), \
164 (u32)(typeof((o)-(o)))(o), \
165 (u32)(typeof((n)-(n)))(n)); \
166 break; \
167 case 8: \
168 __x = (typeof(__x))(typeof(__x-__x))atomic64_cmpxchg( \
169 (atomic64_t *)(ptr), \
170 (u64)(typeof((o)-(o)))(o), \
171 (u64)(typeof((n)-(n)))(n)); \
172 break; \
173 default: \
174 __cmpxchg_called_with_bad_pointer(); \
175 } \
176 __x; \
177 })
178
144#define tas(ptr) (xchg((ptr), 1)) 179#define tas(ptr) (xchg((ptr), 1))
145 180
146#endif /* __ASSEMBLY__ */ 181#endif /* __ASSEMBLY__ */
diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h
index ed359aee8837..92a8bee32311 100644
--- a/arch/tile/include/asm/atomic_32.h
+++ b/arch/tile/include/asm/atomic_32.h
@@ -110,16 +110,6 @@ static inline void atomic_set(atomic_t *v, int n)
110 _atomic_xchg(v, n); 110 _atomic_xchg(v, n);
111} 111}
112 112
113#define xchg(ptr, x) ((typeof(*(ptr))) \
114 ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
115 atomic_xchg((atomic_t *)(ptr), (long)(x)) : \
116 __xchg_called_with_bad_pointer()))
117
118#define cmpxchg(ptr, o, n) ((typeof(*(ptr))) \
119 ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
120 atomic_cmpxchg((atomic_t *)(ptr), (long)(o), (long)(n)) : \
121 __cmpxchg_called_with_bad_pointer()))
122
123/* A 64bit atomic type */ 113/* A 64bit atomic type */
124 114
125typedef struct { 115typedef struct {
diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h
new file mode 100644
index 000000000000..1c1e60d8ccb6
--- /dev/null
+++ b/arch/tile/include/asm/atomic_64.h
@@ -0,0 +1,156 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Do not include directly; use <asm/atomic.h>.
15 */
16
17#ifndef _ASM_TILE_ATOMIC_64_H
18#define _ASM_TILE_ATOMIC_64_H
19
20#ifndef __ASSEMBLY__
21
22#include <arch/spr_def.h>
23
24/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
25
26#define atomic_set(v, i) ((v)->counter = (i))
27
28/*
29 * The smp_mb() operations throughout are to support the fact that
30 * Linux requires memory barriers before and after the operation,
31 * on any routine which updates memory and returns a value.
32 */
33
34static inline int atomic_cmpxchg(atomic_t *v, int o, int n)
35{
36 int val;
37 __insn_mtspr(SPR_CMPEXCH_VALUE, o);
38 smp_mb(); /* barrier for proper semantics */
39 val = __insn_cmpexch4((void *)&v->counter, n);
40 smp_mb(); /* barrier for proper semantics */
41 return val;
42}
43
44static inline int atomic_xchg(atomic_t *v, int n)
45{
46 int val;
47 smp_mb(); /* barrier for proper semantics */
48 val = __insn_exch4((void *)&v->counter, n);
49 smp_mb(); /* barrier for proper semantics */
50 return val;
51}
52
53static inline void atomic_add(int i, atomic_t *v)
54{
55 __insn_fetchadd4((void *)&v->counter, i);
56}
57
58static inline int atomic_add_return(int i, atomic_t *v)
59{
60 int val;
61 smp_mb(); /* barrier for proper semantics */
62 val = __insn_fetchadd4((void *)&v->counter, i) + i;
63 barrier(); /* the "+ i" above will wait on memory */
64 return val;
65}
66
67static inline int atomic_add_unless(atomic_t *v, int a, int u)
68{
69 int guess, oldval = v->counter;
70 do {
71 if (oldval == u)
72 break;
73 guess = oldval;
74 oldval = atomic_cmpxchg(v, guess, guess + a);
75 } while (guess != oldval);
76 return oldval != u;
77}
78
79/* Now the true 64-bit operations. */
80
81#define ATOMIC64_INIT(i) { (i) }
82
83#define atomic64_read(v) ((v)->counter)
84#define atomic64_set(v, i) ((v)->counter = (i))
85
86static inline long atomic64_cmpxchg(atomic64_t *v, long o, long n)
87{
88 long val;
89 smp_mb(); /* barrier for proper semantics */
90 __insn_mtspr(SPR_CMPEXCH_VALUE, o);
91 val = __insn_cmpexch((void *)&v->counter, n);
92 smp_mb(); /* barrier for proper semantics */
93 return val;
94}
95
96static inline long atomic64_xchg(atomic64_t *v, long n)
97{
98 long val;
99 smp_mb(); /* barrier for proper semantics */
100 val = __insn_exch((void *)&v->counter, n);
101 smp_mb(); /* barrier for proper semantics */
102 return val;
103}
104
105static inline void atomic64_add(long i, atomic64_t *v)
106{
107 __insn_fetchadd((void *)&v->counter, i);
108}
109
110static inline long atomic64_add_return(long i, atomic64_t *v)
111{
112 int val;
113 smp_mb(); /* barrier for proper semantics */
114 val = __insn_fetchadd((void *)&v->counter, i) + i;
115 barrier(); /* the "+ i" above will wait on memory */
116 return val;
117}
118
119static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
120{
121 long guess, oldval = v->counter;
122 do {
123 if (oldval == u)
124 break;
125 guess = oldval;
126 oldval = atomic64_cmpxchg(v, guess, guess + a);
127 } while (guess != oldval);
128 return oldval != u;
129}
130
131#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
132#define atomic64_sub(i, v) atomic64_add(-(i), (v))
133#define atomic64_inc_return(v) atomic64_add_return(1, (v))
134#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
135#define atomic64_inc(v) atomic64_add(1, (v))
136#define atomic64_dec(v) atomic64_sub(1, (v))
137
138#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
139#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
140#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
141#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
142
143#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
144
145/* Atomic dec and inc don't implement barrier, so provide them if needed. */
146#define smp_mb__before_atomic_dec() smp_mb()
147#define smp_mb__after_atomic_dec() smp_mb()
148#define smp_mb__before_atomic_inc() smp_mb()
149#define smp_mb__after_atomic_inc() smp_mb()
150
151/* Define this to indicate that cmpxchg is an efficient operation. */
152#define __HAVE_ARCH_CMPXCHG
153
154#endif /* !__ASSEMBLY__ */
155
156#endif /* _ASM_TILE_ATOMIC_64_H */
diff --git a/arch/tile/include/asm/backtrace.h b/arch/tile/include/asm/backtrace.h
index 758ca4619d50..bd5399a69edf 100644
--- a/arch/tile/include/asm/backtrace.h
+++ b/arch/tile/include/asm/backtrace.h
@@ -12,80 +12,41 @@
12 * more details. 12 * more details.
13 */ 13 */
14 14
15#ifndef _TILE_BACKTRACE_H 15#ifndef _ASM_TILE_BACKTRACE_H
16#define _TILE_BACKTRACE_H 16#define _ASM_TILE_BACKTRACE_H
17
18
19 17
20#include <linux/types.h> 18#include <linux/types.h>
21 19
22#include <arch/chip.h> 20/* Reads 'size' bytes from 'address' and writes the data to 'result'.
23
24#if defined(__tile__)
25typedef unsigned long VirtualAddress;
26#elif CHIP_VA_WIDTH() > 32
27typedef unsigned long long VirtualAddress;
28#else
29typedef unsigned int VirtualAddress;
30#endif
31
32
33/** Reads 'size' bytes from 'address' and writes the data to 'result'.
34 * Returns true if successful, else false (e.g. memory not readable). 21 * Returns true if successful, else false (e.g. memory not readable).
35 */ 22 */
36typedef bool (*BacktraceMemoryReader)(void *result, 23typedef bool (*BacktraceMemoryReader)(void *result,
37 VirtualAddress address, 24 unsigned long address,
38 unsigned int size, 25 unsigned int size,
39 void *extra); 26 void *extra);
40 27
41typedef struct { 28typedef struct {
42 /** Current PC. */ 29 /* Current PC. */
43 VirtualAddress pc; 30 unsigned long pc;
44 31
45 /** Current stack pointer value. */ 32 /* Current stack pointer value. */
46 VirtualAddress sp; 33 unsigned long sp;
47 34
48 /** Current frame pointer value (i.e. caller's stack pointer) */ 35 /* Current frame pointer value (i.e. caller's stack pointer) */
49 VirtualAddress fp; 36 unsigned long fp;
50 37
51 /** Internal use only: caller's PC for first frame. */ 38 /* Internal use only: caller's PC for first frame. */
52 VirtualAddress initial_frame_caller_pc; 39 unsigned long initial_frame_caller_pc;
53 40
54 /** Internal use only: callback to read memory. */ 41 /* Internal use only: callback to read memory. */
55 BacktraceMemoryReader read_memory_func; 42 BacktraceMemoryReader read_memory_func;
56 43
57 /** Internal use only: arbitrary argument to read_memory_func. */ 44 /* Internal use only: arbitrary argument to read_memory_func. */
58 void *read_memory_func_extra; 45 void *read_memory_func_extra;
59 46
60} BacktraceIterator; 47} BacktraceIterator;
61 48
62 49
63/** Initializes a backtracer to start from the given location.
64 *
65 * If the frame pointer cannot be determined it is set to -1.
66 *
67 * @param state The state to be filled in.
68 * @param read_memory_func A callback that reads memory. If NULL, a default
69 * value is provided.
70 * @param read_memory_func_extra An arbitrary argument to read_memory_func.
71 * @param pc The current PC.
72 * @param lr The current value of the 'lr' register.
73 * @param sp The current value of the 'sp' register.
74 * @param r52 The current value of the 'r52' register.
75 */
76extern void backtrace_init(BacktraceIterator *state,
77 BacktraceMemoryReader read_memory_func,
78 void *read_memory_func_extra,
79 VirtualAddress pc, VirtualAddress lr,
80 VirtualAddress sp, VirtualAddress r52);
81
82
83/** Advances the backtracing state to the calling frame, returning
84 * true iff successful.
85 */
86extern bool backtrace_next(BacktraceIterator *state);
87
88
89typedef enum { 50typedef enum {
90 51
91 /* We have no idea what the caller's pc is. */ 52 /* We have no idea what the caller's pc is. */
@@ -138,7 +99,7 @@ enum {
138}; 99};
139 100
140 101
141/** Internal constants used to define 'info' operands. */ 102/* Internal constants used to define 'info' operands. */
142enum { 103enum {
143 /* 0 and 1 are reserved, as are all negative numbers. */ 104 /* 0 and 1 are reserved, as are all negative numbers. */
144 105
@@ -146,11 +107,11 @@ enum {
146 107
147 CALLER_SP_IN_R52_BASE = 4, 108 CALLER_SP_IN_R52_BASE = 4,
148 109
149 CALLER_SP_OFFSET_BASE = 8 110 CALLER_SP_OFFSET_BASE = 8,
150}; 111};
151 112
152 113
153/** Current backtracer state describing where it thinks the caller is. */ 114/* Current backtracer state describing where it thinks the caller is. */
154typedef struct { 115typedef struct {
155 /* 116 /*
156 * Public fields 117 * Public fields
@@ -189,7 +150,13 @@ typedef struct {
189 150
190} CallerLocation; 151} CallerLocation;
191 152
153extern void backtrace_init(BacktraceIterator *state,
154 BacktraceMemoryReader read_memory_func,
155 void *read_memory_func_extra,
156 unsigned long pc, unsigned long lr,
157 unsigned long sp, unsigned long r52);
192 158
193 159
160extern bool backtrace_next(BacktraceIterator *state);
194 161
195#endif /* _TILE_BACKTRACE_H */ 162#endif /* _ASM_TILE_BACKTRACE_H */
diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h
index 6832b4be8990..16f1fa51fea1 100644
--- a/arch/tile/include/asm/bitops.h
+++ b/arch/tile/include/asm/bitops.h
@@ -120,8 +120,9 @@ static inline unsigned long __arch_hweight64(__u64 w)
120 120
121#include <asm-generic/bitops/const_hweight.h> 121#include <asm-generic/bitops/const_hweight.h>
122#include <asm-generic/bitops/lock.h> 122#include <asm-generic/bitops/lock.h>
123#include <asm-generic/bitops/find.h>
123#include <asm-generic/bitops/sched.h> 124#include <asm-generic/bitops/sched.h>
124#include <asm-generic/bitops/ext2-non-atomic.h> 125#include <asm-generic/bitops/non-atomic.h>
125#include <asm-generic/bitops/minix.h> 126#include <asm-generic/bitops/le.h>
126 127
127#endif /* _ASM_TILE_BITOPS_H */ 128#endif /* _ASM_TILE_BITOPS_H */
diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h
index 7a93c001ac19..d31ab905cfa7 100644
--- a/arch/tile/include/asm/bitops_32.h
+++ b/arch/tile/include/asm/bitops_32.h
@@ -122,11 +122,10 @@ static inline int test_and_change_bit(unsigned nr,
122 return (_atomic_xor(addr, mask) & mask) != 0; 122 return (_atomic_xor(addr, mask) & mask) != 0;
123} 123}
124 124
125/* See discussion at smp_mb__before_atomic_dec() in <asm/atomic.h>. */ 125/* See discussion at smp_mb__before_atomic_dec() in <asm/atomic_32.h>. */
126#define smp_mb__before_clear_bit() smp_mb() 126#define smp_mb__before_clear_bit() smp_mb()
127#define smp_mb__after_clear_bit() do {} while (0) 127#define smp_mb__after_clear_bit() do {} while (0)
128 128
129#include <asm-generic/bitops/non-atomic.h>
130#include <asm-generic/bitops/ext2-atomic.h> 129#include <asm-generic/bitops/ext2-atomic.h>
131 130
132#endif /* _ASM_TILE_BITOPS_32_H */ 131#endif /* _ASM_TILE_BITOPS_32_H */
diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h
new file mode 100644
index 000000000000..99615e8d2d8b
--- /dev/null
+++ b/arch/tile/include/asm/bitops_64.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_BITOPS_64_H
16#define _ASM_TILE_BITOPS_64_H
17
18#include <linux/compiler.h>
19#include <asm/atomic.h>
20#include <asm/system.h>
21
22/* See <asm/bitops.h> for API comments. */
23
24static inline void set_bit(unsigned nr, volatile unsigned long *addr)
25{
26 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
27 __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask);
28}
29
30static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
31{
32 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
33 __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask);
34}
35
36#define smp_mb__before_clear_bit() smp_mb()
37#define smp_mb__after_clear_bit() smp_mb()
38
39
40static inline void change_bit(unsigned nr, volatile unsigned long *addr)
41{
42 unsigned long old, mask = (1UL << (nr % BITS_PER_LONG));
43 long guess, oldval;
44 addr += nr / BITS_PER_LONG;
45 old = *addr;
46 do {
47 guess = oldval;
48 oldval = atomic64_cmpxchg((atomic64_t *)addr,
49 guess, guess ^ mask);
50 } while (guess != oldval);
51}
52
53
54/*
55 * The test_and_xxx_bit() routines require a memory fence before we
56 * start the operation, and after the operation completes. We use
57 * smp_mb() before, and rely on the "!= 0" comparison, plus a compiler
58 * barrier(), to block until the atomic op is complete.
59 */
60
61static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
62{
63 int val;
64 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
65 smp_mb(); /* barrier for proper semantics */
66 val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask)
67 & mask) != 0;
68 barrier();
69 return val;
70}
71
72
73static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
74{
75 int val;
76 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
77 smp_mb(); /* barrier for proper semantics */
78 val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask)
79 & mask) != 0;
80 barrier();
81 return val;
82}
83
84
85static inline int test_and_change_bit(unsigned nr,
86 volatile unsigned long *addr)
87{
88 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
89 long guess, oldval = *addr;
90 addr += nr / BITS_PER_LONG;
91 oldval = *addr;
92 do {
93 guess = oldval;
94 oldval = atomic64_cmpxchg((atomic64_t *)addr,
95 guess, guess ^ mask);
96 } while (guess != oldval);
97 return (oldval & mask) != 0;
98}
99
100#define ext2_set_bit_atomic(lock, nr, addr) \
101 test_and_set_bit((nr), (unsigned long *)(addr))
102#define ext2_clear_bit_atomic(lock, nr, addr) \
103 test_and_clear_bit((nr), (unsigned long *)(addr))
104
105#endif /* _ASM_TILE_BITOPS_64_H */
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
index 08a2815b5e4e..392e5333dd8b 100644
--- a/arch/tile/include/asm/cache.h
+++ b/arch/tile/include/asm/cache.h
@@ -40,7 +40,7 @@
40#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES 40#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES
41 41
42/* Group together read-mostly things to avoid cache false sharing */ 42/* Group together read-mostly things to avoid cache false sharing */
43#define __read_mostly __attribute__((__section__(".data.read_mostly"))) 43#define __read_mostly __attribute__((__section__(".data..read_mostly")))
44 44
45/* 45/*
46 * Attribute for data that is kept read/write coherent until the end of 46 * Attribute for data that is kept read/write coherent until the end of
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index c5741da4eeac..e925f4bb498f 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -116,25 +116,40 @@ static inline void __finv_buffer(void *buffer, size_t size)
116} 116}
117 117
118 118
119/* Invalidate a VA range, then memory fence. */ 119/* Invalidate a VA range and wait for it to be complete. */
120static inline void inv_buffer(void *buffer, size_t size) 120static inline void inv_buffer(void *buffer, size_t size)
121{ 121{
122 __inv_buffer(buffer, size); 122 __inv_buffer(buffer, size);
123 mb_incoherent(); 123 mb();
124} 124}
125 125
126/* Flush a VA range, then memory fence. */ 126/*
127static inline void flush_buffer(void *buffer, size_t size) 127 * Flush a locally-homecached VA range and wait for the evicted
128 * cachelines to hit memory.
129 */
130static inline void flush_buffer_local(void *buffer, size_t size)
128{ 131{
129 __flush_buffer(buffer, size); 132 __flush_buffer(buffer, size);
130 mb_incoherent(); 133 mb_incoherent();
131} 134}
132 135
133/* Flush & invalidate a VA range, then memory fence. */ 136/*
134static inline void finv_buffer(void *buffer, size_t size) 137 * Flush and invalidate a locally-homecached VA range and wait for the
138 * evicted cachelines to hit memory.
139 */
140static inline void finv_buffer_local(void *buffer, size_t size)
135{ 141{
136 __finv_buffer(buffer, size); 142 __finv_buffer(buffer, size);
137 mb_incoherent(); 143 mb_incoherent();
138} 144}
139 145
146/*
147 * Flush and invalidate a VA range that is homed remotely, waiting
148 * until the memory controller holds the flushed values. If "hfh" is
149 * true, we will do a more expensive flush involving additional loads
150 * to make sure we have touched all the possible home cpus of a buffer
151 * that is homed with "hash for home".
152 */
153void finv_buffer_remote(void *buffer, size_t size, int hfh);
154
140#endif /* _ASM_TILE_CACHEFLUSH_H */ 155#endif /* _ASM_TILE_CACHEFLUSH_H */
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index 8b60ec8b2d19..bf95f55b82b0 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -215,16 +215,17 @@ struct compat_sigaction;
215struct compat_siginfo; 215struct compat_siginfo;
216struct compat_sigaltstack; 216struct compat_sigaltstack;
217long compat_sys_execve(const char __user *path, 217long compat_sys_execve(const char __user *path,
218 const compat_uptr_t __user *argv, 218 compat_uptr_t __user *argv,
219 const compat_uptr_t __user *envp); 219 compat_uptr_t __user *envp, struct pt_regs *);
220long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act, 220long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act,
221 struct compat_sigaction __user *oact, 221 struct compat_sigaction __user *oact,
222 size_t sigsetsize); 222 size_t sigsetsize);
223long compat_sys_rt_sigqueueinfo(int pid, int sig, 223long compat_sys_rt_sigqueueinfo(int pid, int sig,
224 struct compat_siginfo __user *uinfo); 224 struct compat_siginfo __user *uinfo);
225long compat_sys_rt_sigreturn(void); 225long compat_sys_rt_sigreturn(struct pt_regs *);
226long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, 226long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
227 struct compat_sigaltstack __user *uoss_ptr); 227 struct compat_sigaltstack __user *uoss_ptr,
228 struct pt_regs *);
228long compat_sys_truncate64(char __user *filename, u32 dummy, u32 low, u32 high); 229long compat_sys_truncate64(char __user *filename, u32 dummy, u32 low, u32 high);
229long compat_sys_ftruncate64(unsigned int fd, u32 dummy, u32 low, u32 high); 230long compat_sys_ftruncate64(unsigned int fd, u32 dummy, u32 low, u32 high);
230long compat_sys_pread64(unsigned int fd, char __user *ubuf, size_t count, 231long compat_sys_pread64(unsigned int fd, char __user *ubuf, size_t count,
@@ -255,4 +256,12 @@ long tile_compat_sys_ptrace(compat_long_t request, compat_long_t pid,
255/* Tilera Linux syscalls that don't have "compat" versions. */ 256/* Tilera Linux syscalls that don't have "compat" versions. */
256#define compat_sys_flush_cache sys_flush_cache 257#define compat_sys_flush_cache sys_flush_cache
257 258
259/* These are the intvec_64.S trampolines. */
260long _compat_sys_execve(const char __user *path,
261 const compat_uptr_t __user *argv,
262 const compat_uptr_t __user *envp);
263long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
264 struct compat_sigaltstack __user *uoss_ptr);
265long _compat_sys_rt_sigreturn(void);
266
258#endif /* _ASM_TILE_COMPAT_H */ 267#endif /* _ASM_TILE_COMPAT_H */
diff --git a/arch/tile/include/asm/dma-mapping.h b/arch/tile/include/asm/dma-mapping.h
index 15e1dceecc64..eaa06d175b39 100644
--- a/arch/tile/include/asm/dma-mapping.h
+++ b/arch/tile/include/asm/dma-mapping.h
@@ -65,7 +65,8 @@ extern void dma_sync_single_range_for_cpu(struct device *, dma_addr_t,
65extern void dma_sync_single_range_for_device(struct device *, dma_addr_t, 65extern void dma_sync_single_range_for_device(struct device *, dma_addr_t,
66 unsigned long offset, size_t, 66 unsigned long offset, size_t,
67 enum dma_data_direction); 67 enum dma_data_direction);
68extern void dma_cache_sync(void *vaddr, size_t, enum dma_data_direction); 68extern void dma_cache_sync(struct device *dev, void *vaddr, size_t,
69 enum dma_data_direction);
69 70
70static inline int 71static inline int
71dma_mapping_error(struct device *dev, dma_addr_t dma_addr) 72dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/tile/include/asm/edac.h b/arch/tile/include/asm/edac.h
new file mode 100644
index 000000000000..87fc83eeaffd
--- /dev/null
+++ b/arch/tile/include/asm/edac.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_EDAC_H
16#define _ASM_TILE_EDAC_H
17
18/* ECC atomic, DMA, SMP and interrupt safe scrub function */
19
20static inline void atomic_scrub(void *va, u32 size)
21{
22 /*
23 * These is nothing to be done here because CE is
24 * corrected by the mshim.
25 */
26 return;
27}
28
29#endif /* _ASM_TILE_EDAC_H */
diff --git a/arch/tile/include/asm/fb.h b/arch/tile/include/asm/fb.h
new file mode 100644
index 000000000000..3a4988e8df45
--- /dev/null
+++ b/arch/tile/include/asm/fb.h
@@ -0,0 +1 @@
#include <asm-generic/fb.h>
diff --git a/arch/tile/include/asm/futex.h b/arch/tile/include/asm/futex.h
index fe0d10dcae57..d03ec124a598 100644
--- a/arch/tile/include/asm/futex.h
+++ b/arch/tile/include/asm/futex.h
@@ -29,16 +29,16 @@
29#include <linux/uaccess.h> 29#include <linux/uaccess.h>
30#include <linux/errno.h> 30#include <linux/errno.h>
31 31
32extern struct __get_user futex_set(int __user *v, int i); 32extern struct __get_user futex_set(u32 __user *v, int i);
33extern struct __get_user futex_add(int __user *v, int n); 33extern struct __get_user futex_add(u32 __user *v, int n);
34extern struct __get_user futex_or(int __user *v, int n); 34extern struct __get_user futex_or(u32 __user *v, int n);
35extern struct __get_user futex_andn(int __user *v, int n); 35extern struct __get_user futex_andn(u32 __user *v, int n);
36extern struct __get_user futex_cmpxchg(int __user *v, int o, int n); 36extern struct __get_user futex_cmpxchg(u32 __user *v, int o, int n);
37 37
38#ifndef __tilegx__ 38#ifndef __tilegx__
39extern struct __get_user futex_xor(int __user *v, int n); 39extern struct __get_user futex_xor(u32 __user *v, int n);
40#else 40#else
41static inline struct __get_user futex_xor(int __user *uaddr, int n) 41static inline struct __get_user futex_xor(u32 __user *uaddr, int n)
42{ 42{
43 struct __get_user asm_ret = __get_user_4(uaddr); 43 struct __get_user asm_ret = __get_user_4(uaddr);
44 if (!asm_ret.err) { 44 if (!asm_ret.err) {
@@ -53,7 +53,7 @@ static inline struct __get_user futex_xor(int __user *uaddr, int n)
53} 53}
54#endif 54#endif
55 55
56static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) 56static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
57{ 57{
58 int op = (encoded_op >> 28) & 7; 58 int op = (encoded_op >> 28) & 7;
59 int cmp = (encoded_op >> 24) & 15; 59 int cmp = (encoded_op >> 24) & 15;
@@ -65,7 +65,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
65 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 65 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
66 oparg = 1 << oparg; 66 oparg = 1 << oparg;
67 67
68 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) 68 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
69 return -EFAULT; 69 return -EFAULT;
70 70
71 pagefault_disable(); 71 pagefault_disable();
@@ -119,16 +119,17 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
119 return ret; 119 return ret;
120} 120}
121 121
122static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, 122static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
123 int newval) 123 u32 oldval, u32 newval)
124{ 124{
125 struct __get_user asm_ret; 125 struct __get_user asm_ret;
126 126
127 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) 127 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
128 return -EFAULT; 128 return -EFAULT;
129 129
130 asm_ret = futex_cmpxchg(uaddr, oldval, newval); 130 asm_ret = futex_cmpxchg(uaddr, oldval, newval);
131 return asm_ret.err ? asm_ret.err : asm_ret.val; 131 *uval = asm_ret.val;
132 return asm_ret.err;
132} 133}
133 134
134#ifndef __tilegx__ 135#ifndef __tilegx__
diff --git a/arch/tile/include/asm/hardwall.h b/arch/tile/include/asm/hardwall.h
index 0bed3ec7b42c..2ac422848c7d 100644
--- a/arch/tile/include/asm/hardwall.h
+++ b/arch/tile/include/asm/hardwall.h
@@ -40,6 +40,10 @@
40#define HARDWALL_DEACTIVATE \ 40#define HARDWALL_DEACTIVATE \
41 _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE) 41 _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE)
42 42
43#define _HARDWALL_GET_ID 4
44#define HARDWALL_GET_ID \
45 _IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID)
46
43#ifndef __KERNEL__ 47#ifndef __KERNEL__
44 48
45/* This is the canonical name expected by userspace. */ 49/* This is the canonical name expected by userspace. */
@@ -47,9 +51,14 @@
47 51
48#else 52#else
49 53
50/* Hook for /proc/tile/hardwall. */ 54/* /proc hooks for hardwall. */
51struct seq_file; 55struct proc_dir_entry;
52int proc_tile_hardwall_show(struct seq_file *sf, void *v); 56#ifdef CONFIG_HARDWALL
57void proc_tile_hardwall_init(struct proc_dir_entry *root);
58int proc_pid_hardwall(struct task_struct *task, char *buffer);
59#else
60static inline void proc_tile_hardwall_init(struct proc_dir_entry *root) {}
61#endif
53 62
54#endif 63#endif
55 64
diff --git a/arch/tile/include/asm/highmem.h b/arch/tile/include/asm/highmem.h
index d155db6fa9bd..b2a6c5de79ab 100644
--- a/arch/tile/include/asm/highmem.h
+++ b/arch/tile/include/asm/highmem.h
@@ -23,7 +23,6 @@
23 23
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/threads.h> 25#include <linux/threads.h>
26#include <asm/kmap_types.h>
27#include <asm/tlbflush.h> 26#include <asm/tlbflush.h>
28#include <asm/homecache.h> 27#include <asm/homecache.h>
29 28
@@ -60,12 +59,12 @@ void *kmap_fix_kpte(struct page *page, int finished);
60/* This macro is used only in map_new_virtual() to map "page". */ 59/* This macro is used only in map_new_virtual() to map "page". */
61#define kmap_prot page_to_kpgprot(page) 60#define kmap_prot page_to_kpgprot(page)
62 61
63void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type); 62void *__kmap_atomic(struct page *page);
64void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); 63void __kunmap_atomic(void *kvaddr);
65void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); 64void *kmap_atomic_pfn(unsigned long pfn);
65void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot);
66struct page *kmap_atomic_to_page(void *ptr); 66struct page *kmap_atomic_to_page(void *ptr);
67void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot); 67void *kmap_atomic_prot(struct page *page, pgprot_t prot);
68void *kmap_atomic(struct page *page, enum km_type type);
69void kmap_atomic_fix_kpte(struct page *page, int finished); 68void kmap_atomic_fix_kpte(struct page *page, int finished);
70 69
71#define flush_cache_kmaps() do { } while (0) 70#define flush_cache_kmaps() do { } while (0)
diff --git a/arch/tile/include/asm/hugetlb.h b/arch/tile/include/asm/hugetlb.h
index 0521c277bbde..d396d1805163 100644
--- a/arch/tile/include/asm/hugetlb.h
+++ b/arch/tile/include/asm/hugetlb.h
@@ -54,7 +54,7 @@ static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
54static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, 54static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
55 pte_t *ptep, pte_t pte) 55 pte_t *ptep, pte_t pte)
56{ 56{
57 set_pte_order(ptep, pte, HUGETLB_PAGE_ORDER); 57 set_pte(ptep, pte);
58} 58}
59 59
60static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, 60static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index ee43328713ab..c9ea1652af03 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -52,12 +52,10 @@ extern void iounmap(volatile void __iomem *addr);
52#endif 52#endif
53 53
54#define ioremap_nocache(physaddr, size) ioremap(physaddr, size) 54#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
55#define ioremap_wc(physaddr, size) ioremap(physaddr, size)
55#define ioremap_writethrough(physaddr, size) ioremap(physaddr, size) 56#define ioremap_writethrough(physaddr, size) ioremap(physaddr, size)
56#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size) 57#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)
57 58
58void __iomem *ioport_map(unsigned long port, unsigned int len);
59extern inline void ioport_unmap(void __iomem *addr) {}
60
61#define mmiowb() 59#define mmiowb()
62 60
63/* Conversion between virtual and physical mappings. */ 61/* Conversion between virtual and physical mappings. */
@@ -164,6 +162,15 @@ static inline void _tile_writeq(u64 val, unsigned long addr)
164#define iowrite32 writel 162#define iowrite32 writel
165#define iowrite64 writeq 163#define iowrite64 writeq
166 164
165static inline void memset_io(void *dst, int val, size_t len)
166{
167 int x;
168 BUG_ON((unsigned long)dst & 0x3);
169 val = (val & 0xff) * 0x01010101;
170 for (x = 0; x < len; x += 4)
171 writel(val, dst + x);
172}
173
167static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, 174static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
168 size_t len) 175 size_t len)
169{ 176{
@@ -189,12 +196,22 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
189 * we never run, uses them unconditionally. 196 * we never run, uses them unconditionally.
190 */ 197 */
191 198
192static inline int ioport_panic(void) 199static inline long ioport_panic(void)
193{ 200{
194 panic("inb/outb and friends do not exist on tile"); 201 panic("inb/outb and friends do not exist on tile");
195 return 0; 202 return 0;
196} 203}
197 204
205static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
206{
207 return (void __iomem *) ioport_panic();
208}
209
210static inline void ioport_unmap(void __iomem *addr)
211{
212 ioport_panic();
213}
214
198static inline u8 inb(unsigned long addr) 215static inline u8 inb(unsigned long addr)
199{ 216{
200 return ioport_panic(); 217 return ioport_panic();
@@ -262,6 +279,11 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
262 ioport_panic(); 279 ioport_panic();
263} 280}
264 281
282#define ioread16be(addr) be16_to_cpu(ioread16(addr))
283#define ioread32be(addr) be32_to_cpu(ioread32(addr))
284#define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
285#define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr))
286
265#define ioread8_rep(p, dst, count) \ 287#define ioread8_rep(p, dst, count) \
266 insb((unsigned long) (p), (dst), (count)) 288 insb((unsigned long) (p), (dst), (count))
267#define ioread16_rep(p, dst, count) \ 289#define ioread16_rep(p, dst, count) \
@@ -276,4 +298,7 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
276#define iowrite32_rep(p, src, count) \ 298#define iowrite32_rep(p, src, count) \
277 outsl((unsigned long) (p), (src), (count)) 299 outsl((unsigned long) (p), (src), (count))
278 300
301#define virt_to_bus virt_to_phys
302#define bus_to_virt phys_to_virt
303
279#endif /* _ASM_TILE_IO_H */ 304#endif /* _ASM_TILE_IO_H */
diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h
index 572fd3ef1d73..94e9a511de84 100644
--- a/arch/tile/include/asm/irq.h
+++ b/arch/tile/include/asm/irq.h
@@ -23,6 +23,8 @@
23/* IRQ numbers used for linux IPIs. */ 23/* IRQ numbers used for linux IPIs. */
24#define IRQ_RESCHEDULE 1 24#define IRQ_RESCHEDULE 1
25 25
26#define irq_canonicalize(irq) (irq)
27
26void ack_bad_irq(unsigned int irq); 28void ack_bad_irq(unsigned int irq);
27 29
28/* 30/*
diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h
index 45cf67c2f286..5db0ce54284d 100644
--- a/arch/tile/include/asm/irqflags.h
+++ b/arch/tile/include/asm/irqflags.h
@@ -18,6 +18,8 @@
18#include <arch/interrupts.h> 18#include <arch/interrupts.h>
19#include <arch/chip.h> 19#include <arch/chip.h>
20 20
21#if !defined(__tilegx__) && defined(__ASSEMBLY__)
22
21/* 23/*
22 * The set of interrupts we want to allow when interrupts are nominally 24 * The set of interrupts we want to allow when interrupts are nominally
23 * disabled. The remainder are effectively "NMI" interrupts from 25 * disabled. The remainder are effectively "NMI" interrupts from
@@ -25,6 +27,16 @@
25 * interrupts (aka "non-queued") are not blocked by the mask in any case. 27 * interrupts (aka "non-queued") are not blocked by the mask in any case.
26 */ 28 */
27#if CHIP_HAS_AUX_PERF_COUNTERS() 29#if CHIP_HAS_AUX_PERF_COUNTERS()
30#define LINUX_MASKABLE_INTERRUPTS_HI \
31 (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
32#else
33#define LINUX_MASKABLE_INTERRUPTS_HI \
34 (~(INT_MASK_HI(INT_PERF_COUNT)))
35#endif
36
37#else
38
39#if CHIP_HAS_AUX_PERF_COUNTERS()
28#define LINUX_MASKABLE_INTERRUPTS \ 40#define LINUX_MASKABLE_INTERRUPTS \
29 (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT))) 41 (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
30#else 42#else
@@ -32,6 +44,8 @@
32 (~(INT_MASK(INT_PERF_COUNT))) 44 (~(INT_MASK(INT_PERF_COUNT)))
33#endif 45#endif
34 46
47#endif
48
35#ifndef __ASSEMBLY__ 49#ifndef __ASSEMBLY__
36 50
37/* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */ 51/* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
@@ -47,53 +61,53 @@
47 int __n = (n); \ 61 int __n = (n); \
48 int __mask = 1 << (__n & 0x1f); \ 62 int __mask = 1 << (__n & 0x1f); \
49 if (__n < 32) \ 63 if (__n < 32) \
50 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_0, __mask); \ 64 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
51 else \ 65 else \
52 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_1, __mask); \ 66 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
53} while (0) 67} while (0)
54#define interrupt_mask_reset(n) do { \ 68#define interrupt_mask_reset(n) do { \
55 int __n = (n); \ 69 int __n = (n); \
56 int __mask = 1 << (__n & 0x1f); \ 70 int __mask = 1 << (__n & 0x1f); \
57 if (__n < 32) \ 71 if (__n < 32) \
58 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_0, __mask); \ 72 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
59 else \ 73 else \
60 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_1, __mask); \ 74 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
61} while (0) 75} while (0)
62#define interrupt_mask_check(n) ({ \ 76#define interrupt_mask_check(n) ({ \
63 int __n = (n); \ 77 int __n = (n); \
64 (((__n < 32) ? \ 78 (((__n < 32) ? \
65 __insn_mfspr(SPR_INTERRUPT_MASK_1_0) : \ 79 __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
66 __insn_mfspr(SPR_INTERRUPT_MASK_1_1)) \ 80 __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
67 >> (__n & 0x1f)) & 1; \ 81 >> (__n & 0x1f)) & 1; \
68}) 82})
69#define interrupt_mask_set_mask(mask) do { \ 83#define interrupt_mask_set_mask(mask) do { \
70 unsigned long long __m = (mask); \ 84 unsigned long long __m = (mask); \
71 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_0, (unsigned long)(__m)); \ 85 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
72 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_1, (unsigned long)(__m>>32)); \ 86 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
73} while (0) 87} while (0)
74#define interrupt_mask_reset_mask(mask) do { \ 88#define interrupt_mask_reset_mask(mask) do { \
75 unsigned long long __m = (mask); \ 89 unsigned long long __m = (mask); \
76 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_0, (unsigned long)(__m)); \ 90 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
77 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_1, (unsigned long)(__m>>32)); \ 91 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
78} while (0) 92} while (0)
79#else 93#else
80#define interrupt_mask_set(n) \ 94#define interrupt_mask_set(n) \
81 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1, (1UL << (n))) 95 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
82#define interrupt_mask_reset(n) \ 96#define interrupt_mask_reset(n) \
83 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1, (1UL << (n))) 97 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
84#define interrupt_mask_check(n) \ 98#define interrupt_mask_check(n) \
85 ((__insn_mfspr(SPR_INTERRUPT_MASK_1) >> (n)) & 1) 99 ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
86#define interrupt_mask_set_mask(mask) \ 100#define interrupt_mask_set_mask(mask) \
87 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1, (mask)) 101 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
88#define interrupt_mask_reset_mask(mask) \ 102#define interrupt_mask_reset_mask(mask) \
89 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1, (mask)) 103 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
90#endif 104#endif
91 105
92/* 106/*
93 * The set of interrupts we want active if irqs are enabled. 107 * The set of interrupts we want active if irqs are enabled.
94 * Note that in particular, the tile timer interrupt comes and goes 108 * Note that in particular, the tile timer interrupt comes and goes
95 * from this set, since we have no other way to turn off the timer. 109 * from this set, since we have no other way to turn off the timer.
96 * Likewise, INTCTRL_1 is removed and re-added during device 110 * Likewise, INTCTRL_K is removed and re-added during device
97 * interrupts, as is the the hardwall UDN_FIREWALL interrupt. 111 * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
98 * We use a low bit (MEM_ERROR) as our sentinel value and make sure it 112 * We use a low bit (MEM_ERROR) as our sentinel value and make sure it
99 * is always claimed as an "active interrupt" so we can query that bit 113 * is always claimed as an "active interrupt" so we can query that bit
@@ -103,55 +117,57 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
103#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR) 117#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
104 118
105/* Disable interrupts. */ 119/* Disable interrupts. */
106#define raw_local_irq_disable() \ 120#define arch_local_irq_disable() \
107 interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS) 121 interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
108 122
109/* Disable all interrupts, including NMIs. */ 123/* Disable all interrupts, including NMIs. */
110#define raw_local_irq_disable_all() \ 124#define arch_local_irq_disable_all() \
111 interrupt_mask_set_mask(-1UL) 125 interrupt_mask_set_mask(-1UL)
112 126
113/* Re-enable all maskable interrupts. */ 127/* Re-enable all maskable interrupts. */
114#define raw_local_irq_enable() \ 128#define arch_local_irq_enable() \
115 interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask)) 129 interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask))
116 130
117/* Disable or enable interrupts based on flag argument. */ 131/* Disable or enable interrupts based on flag argument. */
118#define raw_local_irq_restore(disabled) do { \ 132#define arch_local_irq_restore(disabled) do { \
119 if (disabled) \ 133 if (disabled) \
120 raw_local_irq_disable(); \ 134 arch_local_irq_disable(); \
121 else \ 135 else \
122 raw_local_irq_enable(); \ 136 arch_local_irq_enable(); \
123} while (0) 137} while (0)
124 138
125/* Return true if "flags" argument means interrupts are disabled. */ 139/* Return true if "flags" argument means interrupts are disabled. */
126#define raw_irqs_disabled_flags(flags) ((flags) != 0) 140#define arch_irqs_disabled_flags(flags) ((flags) != 0)
127 141
128/* Return true if interrupts are currently disabled. */ 142/* Return true if interrupts are currently disabled. */
129#define raw_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR) 143#define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
130 144
131/* Save whether interrupts are currently disabled. */ 145/* Save whether interrupts are currently disabled. */
132#define raw_local_save_flags(flags) ((flags) = raw_irqs_disabled()) 146#define arch_local_save_flags() arch_irqs_disabled()
133 147
134/* Save whether interrupts are currently disabled, then disable them. */ 148/* Save whether interrupts are currently disabled, then disable them. */
135#define raw_local_irq_save(flags) \ 149#define arch_local_irq_save() ({ \
136 do { raw_local_save_flags(flags); raw_local_irq_disable(); } while (0) 150 unsigned long __flags = arch_local_save_flags(); \
151 arch_local_irq_disable(); \
152 __flags; })
137 153
138/* Prevent the given interrupt from being enabled next time we enable irqs. */ 154/* Prevent the given interrupt from being enabled next time we enable irqs. */
139#define raw_local_irq_mask(interrupt) \ 155#define arch_local_irq_mask(interrupt) \
140 (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt)) 156 (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
141 157
142/* Prevent the given interrupt from being enabled immediately. */ 158/* Prevent the given interrupt from being enabled immediately. */
143#define raw_local_irq_mask_now(interrupt) do { \ 159#define arch_local_irq_mask_now(interrupt) do { \
144 raw_local_irq_mask(interrupt); \ 160 arch_local_irq_mask(interrupt); \
145 interrupt_mask_set(interrupt); \ 161 interrupt_mask_set(interrupt); \
146} while (0) 162} while (0)
147 163
148/* Allow the given interrupt to be enabled next time we enable irqs. */ 164/* Allow the given interrupt to be enabled next time we enable irqs. */
149#define raw_local_irq_unmask(interrupt) \ 165#define arch_local_irq_unmask(interrupt) \
150 (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt)) 166 (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
151 167
152/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */ 168/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
153#define raw_local_irq_unmask_now(interrupt) do { \ 169#define arch_local_irq_unmask_now(interrupt) do { \
154 raw_local_irq_unmask(interrupt); \ 170 arch_local_irq_unmask(interrupt); \
155 if (!irqs_disabled()) \ 171 if (!irqs_disabled()) \
156 interrupt_mask_reset(interrupt); \ 172 interrupt_mask_reset(interrupt); \
157} while (0) 173} while (0)
@@ -168,14 +184,14 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
168 184
169/* Return 0 or 1 to indicate whether interrupts are currently disabled. */ 185/* Return 0 or 1 to indicate whether interrupts are currently disabled. */
170#define IRQS_DISABLED(tmp) \ 186#define IRQS_DISABLED(tmp) \
171 mfspr tmp, INTERRUPT_MASK_1; \ 187 mfspr tmp, SPR_INTERRUPT_MASK_K; \
172 andi tmp, tmp, 1 188 andi tmp, tmp, 1
173 189
174/* Load up a pointer to &interrupts_enabled_mask. */ 190/* Load up a pointer to &interrupts_enabled_mask. */
175#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \ 191#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
176 moveli reg, hw2_last(interrupts_enabled_mask); \ 192 moveli reg, hw2_last(interrupts_enabled_mask); \
177 shl16insli reg, reg, hw1(interrupts_enabled_mask); \ 193 shl16insli reg, reg, hw1(interrupts_enabled_mask); \
178 shl16insli reg, reg, hw0(interrupts_enabled_mask); \ 194 shl16insli reg, reg, hw0(interrupts_enabled_mask); \
179 add reg, reg, tp 195 add reg, reg, tp
180 196
181/* Disable interrupts. */ 197/* Disable interrupts. */
@@ -183,18 +199,18 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
183 moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \ 199 moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \
184 shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \ 200 shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \
185 shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \ 201 shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \
186 mtspr INTERRUPT_MASK_SET_1, tmp0 202 mtspr SPR_INTERRUPT_MASK_SET_K, tmp0
187 203
188/* Disable ALL synchronous interrupts (used by NMI entry). */ 204/* Disable ALL synchronous interrupts (used by NMI entry). */
189#define IRQ_DISABLE_ALL(tmp) \ 205#define IRQ_DISABLE_ALL(tmp) \
190 movei tmp, -1; \ 206 movei tmp, -1; \
191 mtspr INTERRUPT_MASK_SET_1, tmp 207 mtspr SPR_INTERRUPT_MASK_SET_K, tmp
192 208
193/* Enable interrupts. */ 209/* Enable interrupts. */
194#define IRQ_ENABLE(tmp0, tmp1) \ 210#define IRQ_ENABLE(tmp0, tmp1) \
195 GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \ 211 GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
196 ld tmp0, tmp0; \ 212 ld tmp0, tmp0; \
197 mtspr INTERRUPT_MASK_RESET_1, tmp0 213 mtspr SPR_INTERRUPT_MASK_RESET_K, tmp0
198 214
199#else /* !__tilegx__ */ 215#else /* !__tilegx__ */
200 216
@@ -208,33 +224,33 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
208 * (making the original code's write of the "high" mask word idempotent). 224 * (making the original code's write of the "high" mask word idempotent).
209 */ 225 */
210#define IRQS_DISABLED(tmp) \ 226#define IRQS_DISABLED(tmp) \
211 mfspr tmp, INTERRUPT_MASK_1_0; \ 227 mfspr tmp, SPR_INTERRUPT_MASK_K_0; \
212 shri tmp, tmp, INT_MEM_ERROR; \ 228 shri tmp, tmp, INT_MEM_ERROR; \
213 andi tmp, tmp, 1 229 andi tmp, tmp, 1
214 230
215/* Load up a pointer to &interrupts_enabled_mask. */ 231/* Load up a pointer to &interrupts_enabled_mask. */
216#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \ 232#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
217 moveli reg, lo16(interrupts_enabled_mask); \ 233 moveli reg, lo16(interrupts_enabled_mask); \
218 auli reg, reg, ha16(interrupts_enabled_mask);\ 234 auli reg, reg, ha16(interrupts_enabled_mask); \
219 add reg, reg, tp 235 add reg, reg, tp
220 236
221/* Disable interrupts. */ 237/* Disable interrupts. */
222#define IRQ_DISABLE(tmp0, tmp1) \ 238#define IRQ_DISABLE(tmp0, tmp1) \
223 { \ 239 { \
224 movei tmp0, -1; \ 240 movei tmp0, -1; \
225 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS) \ 241 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
226 }; \ 242 }; \
227 { \ 243 { \
228 mtspr INTERRUPT_MASK_SET_1_0, tmp0; \ 244 mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp0; \
229 auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS) \ 245 auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI) \
230 }; \ 246 }; \
231 mtspr INTERRUPT_MASK_SET_1_1, tmp1 247 mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1
232 248
233/* Disable ALL synchronous interrupts (used by NMI entry). */ 249/* Disable ALL synchronous interrupts (used by NMI entry). */
234#define IRQ_DISABLE_ALL(tmp) \ 250#define IRQ_DISABLE_ALL(tmp) \
235 movei tmp, -1; \ 251 movei tmp, -1; \
236 mtspr INTERRUPT_MASK_SET_1_0, tmp; \ 252 mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp; \
237 mtspr INTERRUPT_MASK_SET_1_1, tmp 253 mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp
238 254
239/* Enable interrupts. */ 255/* Enable interrupts. */
240#define IRQ_ENABLE(tmp0, tmp1) \ 256#define IRQ_ENABLE(tmp0, tmp1) \
@@ -244,8 +260,8 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
244 addi tmp1, tmp0, 4 \ 260 addi tmp1, tmp0, 4 \
245 }; \ 261 }; \
246 lw tmp1, tmp1; \ 262 lw tmp1, tmp1; \
247 mtspr INTERRUPT_MASK_RESET_1_0, tmp0; \ 263 mtspr SPR_INTERRUPT_MASK_RESET_K_0, tmp0; \
248 mtspr INTERRUPT_MASK_RESET_1_1, tmp1 264 mtspr SPR_INTERRUPT_MASK_RESET_K_1, tmp1
249#endif 265#endif
250 266
251/* 267/*
diff --git a/arch/tile/include/asm/kmap_types.h b/arch/tile/include/asm/kmap_types.h
index 1480106d1c05..3d0f20246260 100644
--- a/arch/tile/include/asm/kmap_types.h
+++ b/arch/tile/include/asm/kmap_types.h
@@ -16,28 +16,42 @@
16#define _ASM_TILE_KMAP_TYPES_H 16#define _ASM_TILE_KMAP_TYPES_H
17 17
18/* 18/*
19 * In TILE Linux each set of four of these uses another 16MB chunk of 19 * In 32-bit TILE Linux we have to balance the desire to have a lot of
20 * address space, given 64 tiles and 64KB pages, so we only enable 20 * nested atomic mappings with the fact that large page sizes and many
21 * ones that are required by the kernel configuration. 21 * processors chew up address space quickly. In a typical
22 * 64-processor, 64KB-page layout build, making KM_TYPE_NR one larger
23 * adds 4MB of required address-space. For now we leave KM_TYPE_NR
24 * set to depth 8.
22 */ 25 */
23enum km_type { 26enum km_type {
27 KM_TYPE_NR = 8
28};
29
30/*
31 * We provide dummy definitions of all the stray values that used to be
32 * required for kmap_atomic() and no longer are.
33 */
34enum {
24 KM_BOUNCE_READ, 35 KM_BOUNCE_READ,
25 KM_SKB_SUNRPC_DATA, 36 KM_SKB_SUNRPC_DATA,
26 KM_SKB_DATA_SOFTIRQ, 37 KM_SKB_DATA_SOFTIRQ,
27 KM_USER0, 38 KM_USER0,
28 KM_USER1, 39 KM_USER1,
29 KM_BIO_SRC_IRQ, 40 KM_BIO_SRC_IRQ,
41 KM_BIO_DST_IRQ,
42 KM_PTE0,
43 KM_PTE1,
30 KM_IRQ0, 44 KM_IRQ0,
31 KM_IRQ1, 45 KM_IRQ1,
32 KM_SOFTIRQ0, 46 KM_SOFTIRQ0,
33 KM_SOFTIRQ1, 47 KM_SOFTIRQ1,
34 KM_MEMCPY0, 48 KM_SYNC_ICACHE,
35 KM_MEMCPY1, 49 KM_SYNC_DCACHE,
36#if defined(CONFIG_HIGHPTE) 50 KM_UML_USERCOPY,
37 KM_PTE0, 51 KM_IRQ_PTE,
38 KM_PTE1, 52 KM_NMI,
39#endif 53 KM_NMI_PTE,
40 KM_TYPE_NR 54 KM_KDB
41}; 55};
42 56
43#endif /* _ASM_TILE_KMAP_TYPES_H */ 57#endif /* _ASM_TILE_KMAP_TYPES_H */
diff --git a/arch/tile/include/asm/mman.h b/arch/tile/include/asm/mman.h
index 4c6811e3e8dc..81b8fc348d63 100644
--- a/arch/tile/include/asm/mman.h
+++ b/arch/tile/include/asm/mman.h
@@ -23,6 +23,7 @@
23#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */ 23#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x0080 /* do not block on IO */ 24#define MAP_NONBLOCK 0x0080 /* do not block on IO */
25#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ 25#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
26#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */
26#define MAP_LOCKED 0x0200 /* pages are locked */ 27#define MAP_LOCKED 0x0200 /* pages are locked */
27#define MAP_NORESERVE 0x0400 /* don't check for reservations */ 28#define MAP_NORESERVE 0x0400 /* don't check for reservations */
28#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ 29#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
diff --git a/arch/tile/include/asm/mmu_context.h b/arch/tile/include/asm/mmu_context.h
index 9bc0d0725c28..15fb24641120 100644
--- a/arch/tile/include/asm/mmu_context.h
+++ b/arch/tile/include/asm/mmu_context.h
@@ -100,8 +100,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
100 __get_cpu_var(current_asid) = asid; 100 __get_cpu_var(current_asid) = asid;
101 101
102 /* Clear cpu from the old mm, and set it in the new one. */ 102 /* Clear cpu from the old mm, and set it in the new one. */
103 cpumask_clear_cpu(cpu, &prev->cpu_vm_mask); 103 cpumask_clear_cpu(cpu, mm_cpumask(prev));
104 cpumask_set_cpu(cpu, &next->cpu_vm_mask); 104 cpumask_set_cpu(cpu, mm_cpumask(next));
105 105
106 /* Re-load page tables */ 106 /* Re-load page tables */
107 install_page_table(next->pgd, asid); 107 install_page_table(next->pgd, asid);
diff --git a/arch/tile/include/asm/mmzone.h b/arch/tile/include/asm/mmzone.h
index c6344c4f32ac..9d3dbce8f953 100644
--- a/arch/tile/include/asm/mmzone.h
+++ b/arch/tile/include/asm/mmzone.h
@@ -40,17 +40,6 @@ static inline int pfn_to_nid(unsigned long pfn)
40 return highbits_to_node[__pfn_to_highbits(pfn)]; 40 return highbits_to_node[__pfn_to_highbits(pfn)];
41} 41}
42 42
43/*
44 * Following are macros that each numa implmentation must define.
45 */
46
47#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
48#define node_end_pfn(nid) \
49({ \
50 pg_data_t *__pgdat = NODE_DATA(nid); \
51 __pgdat->node_start_pfn + __pgdat->node_spanned_pages; \
52})
53
54#define kern_addr_valid(kaddr) virt_addr_valid((void *)kaddr) 43#define kern_addr_valid(kaddr) virt_addr_valid((void *)kaddr)
55 44
56static inline int pfn_valid(int pfn) 45static inline int pfn_valid(int pfn)
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h
index eda60ecbae3d..03df7b1e77bf 100644
--- a/arch/tile/include/asm/opcode-tile_32.h
+++ b/arch/tile/include/asm/opcode-tile_32.h
@@ -1502,5 +1502,12 @@ extern int parse_insn_tile(tile_bundle_bits bits,
1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
1503 1503
1504 1504
1505/* Given a set of bundle bits and a specific pipe, returns which
1506 * instruction the bundle contains in that pipe.
1507 */
1508extern const struct tile_opcode *
1509find_opcode(tile_bundle_bits bits, tile_pipeline pipe);
1510
1511
1505 1512
1506#endif /* opcode_tile_h */ 1513#endif /* opcode_tile_h */
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
index eda60ecbae3d..c0633466cd5c 100644
--- a/arch/tile/include/asm/opcode-tile_64.h
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -5,863 +5,711 @@
5#ifndef opcode_tile_h 5#ifndef opcode_tile_h
6#define opcode_tile_h 6#define opcode_tile_h
7 7
8typedef unsigned long long tile_bundle_bits; 8typedef unsigned long long tilegx_bundle_bits;
9 9
10 10
11enum 11enum
12{ 12{
13 TILE_MAX_OPERANDS = 5 /* mm */ 13 TILEGX_MAX_OPERANDS = 4 /* bfexts */
14}; 14};
15 15
16typedef enum 16typedef enum
17{ 17{
18 TILE_OPC_BPT, 18 TILEGX_OPC_BPT,
19 TILE_OPC_INFO, 19 TILEGX_OPC_INFO,
20 TILE_OPC_INFOL, 20 TILEGX_OPC_INFOL,
21 TILE_OPC_J, 21 TILEGX_OPC_MOVE,
22 TILE_OPC_JAL, 22 TILEGX_OPC_MOVEI,
23 TILE_OPC_MOVE, 23 TILEGX_OPC_MOVELI,
24 TILE_OPC_MOVE_SN, 24 TILEGX_OPC_PREFETCH,
25 TILE_OPC_MOVEI, 25 TILEGX_OPC_PREFETCH_ADD_L1,
26 TILE_OPC_MOVEI_SN, 26 TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
27 TILE_OPC_MOVELI, 27 TILEGX_OPC_PREFETCH_ADD_L2,
28 TILE_OPC_MOVELI_SN, 28 TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
29 TILE_OPC_MOVELIS, 29 TILEGX_OPC_PREFETCH_ADD_L3,
30 TILE_OPC_PREFETCH, 30 TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
31 TILE_OPC_RAISE, 31 TILEGX_OPC_PREFETCH_L1,
32 TILE_OPC_ADD, 32 TILEGX_OPC_PREFETCH_L1_FAULT,
33 TILE_OPC_ADD_SN, 33 TILEGX_OPC_PREFETCH_L2,
34 TILE_OPC_ADDB, 34 TILEGX_OPC_PREFETCH_L2_FAULT,
35 TILE_OPC_ADDB_SN, 35 TILEGX_OPC_PREFETCH_L3,
36 TILE_OPC_ADDBS_U, 36 TILEGX_OPC_PREFETCH_L3_FAULT,
37 TILE_OPC_ADDBS_U_SN, 37 TILEGX_OPC_RAISE,
38 TILE_OPC_ADDH, 38 TILEGX_OPC_ADD,
39 TILE_OPC_ADDH_SN, 39 TILEGX_OPC_ADDI,
40 TILE_OPC_ADDHS, 40 TILEGX_OPC_ADDLI,
41 TILE_OPC_ADDHS_SN, 41 TILEGX_OPC_ADDX,
42 TILE_OPC_ADDI, 42 TILEGX_OPC_ADDXI,
43 TILE_OPC_ADDI_SN, 43 TILEGX_OPC_ADDXLI,
44 TILE_OPC_ADDIB, 44 TILEGX_OPC_ADDXSC,
45 TILE_OPC_ADDIB_SN, 45 TILEGX_OPC_AND,
46 TILE_OPC_ADDIH, 46 TILEGX_OPC_ANDI,
47 TILE_OPC_ADDIH_SN, 47 TILEGX_OPC_BEQZ,
48 TILE_OPC_ADDLI, 48 TILEGX_OPC_BEQZT,
49 TILE_OPC_ADDLI_SN, 49 TILEGX_OPC_BFEXTS,
50 TILE_OPC_ADDLIS, 50 TILEGX_OPC_BFEXTU,
51 TILE_OPC_ADDS, 51 TILEGX_OPC_BFINS,
52 TILE_OPC_ADDS_SN, 52 TILEGX_OPC_BGEZ,
53 TILE_OPC_ADIFFB_U, 53 TILEGX_OPC_BGEZT,
54 TILE_OPC_ADIFFB_U_SN, 54 TILEGX_OPC_BGTZ,
55 TILE_OPC_ADIFFH, 55 TILEGX_OPC_BGTZT,
56 TILE_OPC_ADIFFH_SN, 56 TILEGX_OPC_BLBC,
57 TILE_OPC_AND, 57 TILEGX_OPC_BLBCT,
58 TILE_OPC_AND_SN, 58 TILEGX_OPC_BLBS,
59 TILE_OPC_ANDI, 59 TILEGX_OPC_BLBST,
60 TILE_OPC_ANDI_SN, 60 TILEGX_OPC_BLEZ,
61 TILE_OPC_AULI, 61 TILEGX_OPC_BLEZT,
62 TILE_OPC_AVGB_U, 62 TILEGX_OPC_BLTZ,
63 TILE_OPC_AVGB_U_SN, 63 TILEGX_OPC_BLTZT,
64 TILE_OPC_AVGH, 64 TILEGX_OPC_BNEZ,
65 TILE_OPC_AVGH_SN, 65 TILEGX_OPC_BNEZT,
66 TILE_OPC_BBNS, 66 TILEGX_OPC_CLZ,
67 TILE_OPC_BBNS_SN, 67 TILEGX_OPC_CMOVEQZ,
68 TILE_OPC_BBNST, 68 TILEGX_OPC_CMOVNEZ,
69 TILE_OPC_BBNST_SN, 69 TILEGX_OPC_CMPEQ,
70 TILE_OPC_BBS, 70 TILEGX_OPC_CMPEQI,
71 TILE_OPC_BBS_SN, 71 TILEGX_OPC_CMPEXCH,
72 TILE_OPC_BBST, 72 TILEGX_OPC_CMPEXCH4,
73 TILE_OPC_BBST_SN, 73 TILEGX_OPC_CMPLES,
74 TILE_OPC_BGEZ, 74 TILEGX_OPC_CMPLEU,
75 TILE_OPC_BGEZ_SN, 75 TILEGX_OPC_CMPLTS,
76 TILE_OPC_BGEZT, 76 TILEGX_OPC_CMPLTSI,
77 TILE_OPC_BGEZT_SN, 77 TILEGX_OPC_CMPLTU,
78 TILE_OPC_BGZ, 78 TILEGX_OPC_CMPLTUI,
79 TILE_OPC_BGZ_SN, 79 TILEGX_OPC_CMPNE,
80 TILE_OPC_BGZT, 80 TILEGX_OPC_CMUL,
81 TILE_OPC_BGZT_SN, 81 TILEGX_OPC_CMULA,
82 TILE_OPC_BITX, 82 TILEGX_OPC_CMULAF,
83 TILE_OPC_BITX_SN, 83 TILEGX_OPC_CMULF,
84 TILE_OPC_BLEZ, 84 TILEGX_OPC_CMULFR,
85 TILE_OPC_BLEZ_SN, 85 TILEGX_OPC_CMULH,
86 TILE_OPC_BLEZT, 86 TILEGX_OPC_CMULHR,
87 TILE_OPC_BLEZT_SN, 87 TILEGX_OPC_CRC32_32,
88 TILE_OPC_BLZ, 88 TILEGX_OPC_CRC32_8,
89 TILE_OPC_BLZ_SN, 89 TILEGX_OPC_CTZ,
90 TILE_OPC_BLZT, 90 TILEGX_OPC_DBLALIGN,
91 TILE_OPC_BLZT_SN, 91 TILEGX_OPC_DBLALIGN2,
92 TILE_OPC_BNZ, 92 TILEGX_OPC_DBLALIGN4,
93 TILE_OPC_BNZ_SN, 93 TILEGX_OPC_DBLALIGN6,
94 TILE_OPC_BNZT, 94 TILEGX_OPC_DRAIN,
95 TILE_OPC_BNZT_SN, 95 TILEGX_OPC_DTLBPR,
96 TILE_OPC_BYTEX, 96 TILEGX_OPC_EXCH,
97 TILE_OPC_BYTEX_SN, 97 TILEGX_OPC_EXCH4,
98 TILE_OPC_BZ, 98 TILEGX_OPC_FDOUBLE_ADD_FLAGS,
99 TILE_OPC_BZ_SN, 99 TILEGX_OPC_FDOUBLE_ADDSUB,
100 TILE_OPC_BZT, 100 TILEGX_OPC_FDOUBLE_MUL_FLAGS,
101 TILE_OPC_BZT_SN, 101 TILEGX_OPC_FDOUBLE_PACK1,
102 TILE_OPC_CLZ, 102 TILEGX_OPC_FDOUBLE_PACK2,
103 TILE_OPC_CLZ_SN, 103 TILEGX_OPC_FDOUBLE_SUB_FLAGS,
104 TILE_OPC_CRC32_32, 104 TILEGX_OPC_FDOUBLE_UNPACK_MAX,
105 TILE_OPC_CRC32_32_SN, 105 TILEGX_OPC_FDOUBLE_UNPACK_MIN,
106 TILE_OPC_CRC32_8, 106 TILEGX_OPC_FETCHADD,
107 TILE_OPC_CRC32_8_SN, 107 TILEGX_OPC_FETCHADD4,
108 TILE_OPC_CTZ, 108 TILEGX_OPC_FETCHADDGEZ,
109 TILE_OPC_CTZ_SN, 109 TILEGX_OPC_FETCHADDGEZ4,
110 TILE_OPC_DRAIN, 110 TILEGX_OPC_FETCHAND,
111 TILE_OPC_DTLBPR, 111 TILEGX_OPC_FETCHAND4,
112 TILE_OPC_DWORD_ALIGN, 112 TILEGX_OPC_FETCHOR,
113 TILE_OPC_DWORD_ALIGN_SN, 113 TILEGX_OPC_FETCHOR4,
114 TILE_OPC_FINV, 114 TILEGX_OPC_FINV,
115 TILE_OPC_FLUSH, 115 TILEGX_OPC_FLUSH,
116 TILE_OPC_FNOP, 116 TILEGX_OPC_FLUSHWB,
117 TILE_OPC_ICOH, 117 TILEGX_OPC_FNOP,
118 TILE_OPC_ILL, 118 TILEGX_OPC_FSINGLE_ADD1,
119 TILE_OPC_INTHB, 119 TILEGX_OPC_FSINGLE_ADDSUB2,
120 TILE_OPC_INTHB_SN, 120 TILEGX_OPC_FSINGLE_MUL1,
121 TILE_OPC_INTHH, 121 TILEGX_OPC_FSINGLE_MUL2,
122 TILE_OPC_INTHH_SN, 122 TILEGX_OPC_FSINGLE_PACK1,
123 TILE_OPC_INTLB, 123 TILEGX_OPC_FSINGLE_PACK2,
124 TILE_OPC_INTLB_SN, 124 TILEGX_OPC_FSINGLE_SUB1,
125 TILE_OPC_INTLH, 125 TILEGX_OPC_ICOH,
126 TILE_OPC_INTLH_SN, 126 TILEGX_OPC_ILL,
127 TILE_OPC_INV, 127 TILEGX_OPC_INV,
128 TILE_OPC_IRET, 128 TILEGX_OPC_IRET,
129 TILE_OPC_JALB, 129 TILEGX_OPC_J,
130 TILE_OPC_JALF, 130 TILEGX_OPC_JAL,
131 TILE_OPC_JALR, 131 TILEGX_OPC_JALR,
132 TILE_OPC_JALRP, 132 TILEGX_OPC_JALRP,
133 TILE_OPC_JB, 133 TILEGX_OPC_JR,
134 TILE_OPC_JF, 134 TILEGX_OPC_JRP,
135 TILE_OPC_JR, 135 TILEGX_OPC_LD,
136 TILE_OPC_JRP, 136 TILEGX_OPC_LD1S,
137 TILE_OPC_LB, 137 TILEGX_OPC_LD1S_ADD,
138 TILE_OPC_LB_SN, 138 TILEGX_OPC_LD1U,
139 TILE_OPC_LB_U, 139 TILEGX_OPC_LD1U_ADD,
140 TILE_OPC_LB_U_SN, 140 TILEGX_OPC_LD2S,
141 TILE_OPC_LBADD, 141 TILEGX_OPC_LD2S_ADD,
142 TILE_OPC_LBADD_SN, 142 TILEGX_OPC_LD2U,
143 TILE_OPC_LBADD_U, 143 TILEGX_OPC_LD2U_ADD,
144 TILE_OPC_LBADD_U_SN, 144 TILEGX_OPC_LD4S,
145 TILE_OPC_LH, 145 TILEGX_OPC_LD4S_ADD,
146 TILE_OPC_LH_SN, 146 TILEGX_OPC_LD4U,
147 TILE_OPC_LH_U, 147 TILEGX_OPC_LD4U_ADD,
148 TILE_OPC_LH_U_SN, 148 TILEGX_OPC_LD_ADD,
149 TILE_OPC_LHADD, 149 TILEGX_OPC_LDNA,
150 TILE_OPC_LHADD_SN, 150 TILEGX_OPC_LDNA_ADD,
151 TILE_OPC_LHADD_U, 151 TILEGX_OPC_LDNT,
152 TILE_OPC_LHADD_U_SN, 152 TILEGX_OPC_LDNT1S,
153 TILE_OPC_LNK, 153 TILEGX_OPC_LDNT1S_ADD,
154 TILE_OPC_LNK_SN, 154 TILEGX_OPC_LDNT1U,
155 TILE_OPC_LW, 155 TILEGX_OPC_LDNT1U_ADD,
156 TILE_OPC_LW_SN, 156 TILEGX_OPC_LDNT2S,
157 TILE_OPC_LW_NA, 157 TILEGX_OPC_LDNT2S_ADD,
158 TILE_OPC_LW_NA_SN, 158 TILEGX_OPC_LDNT2U,
159 TILE_OPC_LWADD, 159 TILEGX_OPC_LDNT2U_ADD,
160 TILE_OPC_LWADD_SN, 160 TILEGX_OPC_LDNT4S,
161 TILE_OPC_LWADD_NA, 161 TILEGX_OPC_LDNT4S_ADD,
162 TILE_OPC_LWADD_NA_SN, 162 TILEGX_OPC_LDNT4U,
163 TILE_OPC_MAXB_U, 163 TILEGX_OPC_LDNT4U_ADD,
164 TILE_OPC_MAXB_U_SN, 164 TILEGX_OPC_LDNT_ADD,
165 TILE_OPC_MAXH, 165 TILEGX_OPC_LNK,
166 TILE_OPC_MAXH_SN, 166 TILEGX_OPC_MF,
167 TILE_OPC_MAXIB_U, 167 TILEGX_OPC_MFSPR,
168 TILE_OPC_MAXIB_U_SN, 168 TILEGX_OPC_MM,
169 TILE_OPC_MAXIH, 169 TILEGX_OPC_MNZ,
170 TILE_OPC_MAXIH_SN, 170 TILEGX_OPC_MTSPR,
171 TILE_OPC_MF, 171 TILEGX_OPC_MUL_HS_HS,
172 TILE_OPC_MFSPR, 172 TILEGX_OPC_MUL_HS_HU,
173 TILE_OPC_MINB_U, 173 TILEGX_OPC_MUL_HS_LS,
174 TILE_OPC_MINB_U_SN, 174 TILEGX_OPC_MUL_HS_LU,
175 TILE_OPC_MINH, 175 TILEGX_OPC_MUL_HU_HU,
176 TILE_OPC_MINH_SN, 176 TILEGX_OPC_MUL_HU_LS,
177 TILE_OPC_MINIB_U, 177 TILEGX_OPC_MUL_HU_LU,
178 TILE_OPC_MINIB_U_SN, 178 TILEGX_OPC_MUL_LS_LS,
179 TILE_OPC_MINIH, 179 TILEGX_OPC_MUL_LS_LU,
180 TILE_OPC_MINIH_SN, 180 TILEGX_OPC_MUL_LU_LU,
181 TILE_OPC_MM, 181 TILEGX_OPC_MULA_HS_HS,
182 TILE_OPC_MNZ, 182 TILEGX_OPC_MULA_HS_HU,
183 TILE_OPC_MNZ_SN, 183 TILEGX_OPC_MULA_HS_LS,
184 TILE_OPC_MNZB, 184 TILEGX_OPC_MULA_HS_LU,
185 TILE_OPC_MNZB_SN, 185 TILEGX_OPC_MULA_HU_HU,
186 TILE_OPC_MNZH, 186 TILEGX_OPC_MULA_HU_LS,
187 TILE_OPC_MNZH_SN, 187 TILEGX_OPC_MULA_HU_LU,
188 TILE_OPC_MTSPR, 188 TILEGX_OPC_MULA_LS_LS,
189 TILE_OPC_MULHH_SS, 189 TILEGX_OPC_MULA_LS_LU,
190 TILE_OPC_MULHH_SS_SN, 190 TILEGX_OPC_MULA_LU_LU,
191 TILE_OPC_MULHH_SU, 191 TILEGX_OPC_MULAX,
192 TILE_OPC_MULHH_SU_SN, 192 TILEGX_OPC_MULX,
193 TILE_OPC_MULHH_UU, 193 TILEGX_OPC_MZ,
194 TILE_OPC_MULHH_UU_SN, 194 TILEGX_OPC_NAP,
195 TILE_OPC_MULHHA_SS, 195 TILEGX_OPC_NOP,
196 TILE_OPC_MULHHA_SS_SN, 196 TILEGX_OPC_NOR,
197 TILE_OPC_MULHHA_SU, 197 TILEGX_OPC_OR,
198 TILE_OPC_MULHHA_SU_SN, 198 TILEGX_OPC_ORI,
199 TILE_OPC_MULHHA_UU, 199 TILEGX_OPC_PCNT,
200 TILE_OPC_MULHHA_UU_SN, 200 TILEGX_OPC_REVBITS,
201 TILE_OPC_MULHHSA_UU, 201 TILEGX_OPC_REVBYTES,
202 TILE_OPC_MULHHSA_UU_SN, 202 TILEGX_OPC_ROTL,
203 TILE_OPC_MULHL_SS, 203 TILEGX_OPC_ROTLI,
204 TILE_OPC_MULHL_SS_SN, 204 TILEGX_OPC_SHL,
205 TILE_OPC_MULHL_SU, 205 TILEGX_OPC_SHL16INSLI,
206 TILE_OPC_MULHL_SU_SN, 206 TILEGX_OPC_SHL1ADD,
207 TILE_OPC_MULHL_US, 207 TILEGX_OPC_SHL1ADDX,
208 TILE_OPC_MULHL_US_SN, 208 TILEGX_OPC_SHL2ADD,
209 TILE_OPC_MULHL_UU, 209 TILEGX_OPC_SHL2ADDX,
210 TILE_OPC_MULHL_UU_SN, 210 TILEGX_OPC_SHL3ADD,
211 TILE_OPC_MULHLA_SS, 211 TILEGX_OPC_SHL3ADDX,
212 TILE_OPC_MULHLA_SS_SN, 212 TILEGX_OPC_SHLI,
213 TILE_OPC_MULHLA_SU, 213 TILEGX_OPC_SHLX,
214 TILE_OPC_MULHLA_SU_SN, 214 TILEGX_OPC_SHLXI,
215 TILE_OPC_MULHLA_US, 215 TILEGX_OPC_SHRS,
216 TILE_OPC_MULHLA_US_SN, 216 TILEGX_OPC_SHRSI,
217 TILE_OPC_MULHLA_UU, 217 TILEGX_OPC_SHRU,
218 TILE_OPC_MULHLA_UU_SN, 218 TILEGX_OPC_SHRUI,
219 TILE_OPC_MULHLSA_UU, 219 TILEGX_OPC_SHRUX,
220 TILE_OPC_MULHLSA_UU_SN, 220 TILEGX_OPC_SHRUXI,
221 TILE_OPC_MULLL_SS, 221 TILEGX_OPC_SHUFFLEBYTES,
222 TILE_OPC_MULLL_SS_SN, 222 TILEGX_OPC_ST,
223 TILE_OPC_MULLL_SU, 223 TILEGX_OPC_ST1,
224 TILE_OPC_MULLL_SU_SN, 224 TILEGX_OPC_ST1_ADD,
225 TILE_OPC_MULLL_UU, 225 TILEGX_OPC_ST2,
226 TILE_OPC_MULLL_UU_SN, 226 TILEGX_OPC_ST2_ADD,
227 TILE_OPC_MULLLA_SS, 227 TILEGX_OPC_ST4,
228 TILE_OPC_MULLLA_SS_SN, 228 TILEGX_OPC_ST4_ADD,
229 TILE_OPC_MULLLA_SU, 229 TILEGX_OPC_ST_ADD,
230 TILE_OPC_MULLLA_SU_SN, 230 TILEGX_OPC_STNT,
231 TILE_OPC_MULLLA_UU, 231 TILEGX_OPC_STNT1,
232 TILE_OPC_MULLLA_UU_SN, 232 TILEGX_OPC_STNT1_ADD,
233 TILE_OPC_MULLLSA_UU, 233 TILEGX_OPC_STNT2,
234 TILE_OPC_MULLLSA_UU_SN, 234 TILEGX_OPC_STNT2_ADD,
235 TILE_OPC_MVNZ, 235 TILEGX_OPC_STNT4,
236 TILE_OPC_MVNZ_SN, 236 TILEGX_OPC_STNT4_ADD,
237 TILE_OPC_MVZ, 237 TILEGX_OPC_STNT_ADD,
238 TILE_OPC_MVZ_SN, 238 TILEGX_OPC_SUB,
239 TILE_OPC_MZ, 239 TILEGX_OPC_SUBX,
240 TILE_OPC_MZ_SN, 240 TILEGX_OPC_SUBXSC,
241 TILE_OPC_MZB, 241 TILEGX_OPC_SWINT0,
242 TILE_OPC_MZB_SN, 242 TILEGX_OPC_SWINT1,
243 TILE_OPC_MZH, 243 TILEGX_OPC_SWINT2,
244 TILE_OPC_MZH_SN, 244 TILEGX_OPC_SWINT3,
245 TILE_OPC_NAP, 245 TILEGX_OPC_TBLIDXB0,
246 TILE_OPC_NOP, 246 TILEGX_OPC_TBLIDXB1,
247 TILE_OPC_NOR, 247 TILEGX_OPC_TBLIDXB2,
248 TILE_OPC_NOR_SN, 248 TILEGX_OPC_TBLIDXB3,
249 TILE_OPC_OR, 249 TILEGX_OPC_V1ADD,
250 TILE_OPC_OR_SN, 250 TILEGX_OPC_V1ADDI,
251 TILE_OPC_ORI, 251 TILEGX_OPC_V1ADDUC,
252 TILE_OPC_ORI_SN, 252 TILEGX_OPC_V1ADIFFU,
253 TILE_OPC_PACKBS_U, 253 TILEGX_OPC_V1AVGU,
254 TILE_OPC_PACKBS_U_SN, 254 TILEGX_OPC_V1CMPEQ,
255 TILE_OPC_PACKHB, 255 TILEGX_OPC_V1CMPEQI,
256 TILE_OPC_PACKHB_SN, 256 TILEGX_OPC_V1CMPLES,
257 TILE_OPC_PACKHS, 257 TILEGX_OPC_V1CMPLEU,
258 TILE_OPC_PACKHS_SN, 258 TILEGX_OPC_V1CMPLTS,
259 TILE_OPC_PACKLB, 259 TILEGX_OPC_V1CMPLTSI,
260 TILE_OPC_PACKLB_SN, 260 TILEGX_OPC_V1CMPLTU,
261 TILE_OPC_PCNT, 261 TILEGX_OPC_V1CMPLTUI,
262 TILE_OPC_PCNT_SN, 262 TILEGX_OPC_V1CMPNE,
263 TILE_OPC_RL, 263 TILEGX_OPC_V1DDOTPU,
264 TILE_OPC_RL_SN, 264 TILEGX_OPC_V1DDOTPUA,
265 TILE_OPC_RLI, 265 TILEGX_OPC_V1DDOTPUS,
266 TILE_OPC_RLI_SN, 266 TILEGX_OPC_V1DDOTPUSA,
267 TILE_OPC_S1A, 267 TILEGX_OPC_V1DOTP,
268 TILE_OPC_S1A_SN, 268 TILEGX_OPC_V1DOTPA,
269 TILE_OPC_S2A, 269 TILEGX_OPC_V1DOTPU,
270 TILE_OPC_S2A_SN, 270 TILEGX_OPC_V1DOTPUA,
271 TILE_OPC_S3A, 271 TILEGX_OPC_V1DOTPUS,
272 TILE_OPC_S3A_SN, 272 TILEGX_OPC_V1DOTPUSA,
273 TILE_OPC_SADAB_U, 273 TILEGX_OPC_V1INT_H,
274 TILE_OPC_SADAB_U_SN, 274 TILEGX_OPC_V1INT_L,
275 TILE_OPC_SADAH, 275 TILEGX_OPC_V1MAXU,
276 TILE_OPC_SADAH_SN, 276 TILEGX_OPC_V1MAXUI,
277 TILE_OPC_SADAH_U, 277 TILEGX_OPC_V1MINU,
278 TILE_OPC_SADAH_U_SN, 278 TILEGX_OPC_V1MINUI,
279 TILE_OPC_SADB_U, 279 TILEGX_OPC_V1MNZ,
280 TILE_OPC_SADB_U_SN, 280 TILEGX_OPC_V1MULTU,
281 TILE_OPC_SADH, 281 TILEGX_OPC_V1MULU,
282 TILE_OPC_SADH_SN, 282 TILEGX_OPC_V1MULUS,
283 TILE_OPC_SADH_U, 283 TILEGX_OPC_V1MZ,
284 TILE_OPC_SADH_U_SN, 284 TILEGX_OPC_V1SADAU,
285 TILE_OPC_SB, 285 TILEGX_OPC_V1SADU,
286 TILE_OPC_SBADD, 286 TILEGX_OPC_V1SHL,
287 TILE_OPC_SEQ, 287 TILEGX_OPC_V1SHLI,
288 TILE_OPC_SEQ_SN, 288 TILEGX_OPC_V1SHRS,
289 TILE_OPC_SEQB, 289 TILEGX_OPC_V1SHRSI,
290 TILE_OPC_SEQB_SN, 290 TILEGX_OPC_V1SHRU,
291 TILE_OPC_SEQH, 291 TILEGX_OPC_V1SHRUI,
292 TILE_OPC_SEQH_SN, 292 TILEGX_OPC_V1SUB,
293 TILE_OPC_SEQI, 293 TILEGX_OPC_V1SUBUC,
294 TILE_OPC_SEQI_SN, 294 TILEGX_OPC_V2ADD,
295 TILE_OPC_SEQIB, 295 TILEGX_OPC_V2ADDI,
296 TILE_OPC_SEQIB_SN, 296 TILEGX_OPC_V2ADDSC,
297 TILE_OPC_SEQIH, 297 TILEGX_OPC_V2ADIFFS,
298 TILE_OPC_SEQIH_SN, 298 TILEGX_OPC_V2AVGS,
299 TILE_OPC_SH, 299 TILEGX_OPC_V2CMPEQ,
300 TILE_OPC_SHADD, 300 TILEGX_OPC_V2CMPEQI,
301 TILE_OPC_SHL, 301 TILEGX_OPC_V2CMPLES,
302 TILE_OPC_SHL_SN, 302 TILEGX_OPC_V2CMPLEU,
303 TILE_OPC_SHLB, 303 TILEGX_OPC_V2CMPLTS,
304 TILE_OPC_SHLB_SN, 304 TILEGX_OPC_V2CMPLTSI,
305 TILE_OPC_SHLH, 305 TILEGX_OPC_V2CMPLTU,
306 TILE_OPC_SHLH_SN, 306 TILEGX_OPC_V2CMPLTUI,
307 TILE_OPC_SHLI, 307 TILEGX_OPC_V2CMPNE,
308 TILE_OPC_SHLI_SN, 308 TILEGX_OPC_V2DOTP,
309 TILE_OPC_SHLIB, 309 TILEGX_OPC_V2DOTPA,
310 TILE_OPC_SHLIB_SN, 310 TILEGX_OPC_V2INT_H,
311 TILE_OPC_SHLIH, 311 TILEGX_OPC_V2INT_L,
312 TILE_OPC_SHLIH_SN, 312 TILEGX_OPC_V2MAXS,
313 TILE_OPC_SHR, 313 TILEGX_OPC_V2MAXSI,
314 TILE_OPC_SHR_SN, 314 TILEGX_OPC_V2MINS,
315 TILE_OPC_SHRB, 315 TILEGX_OPC_V2MINSI,
316 TILE_OPC_SHRB_SN, 316 TILEGX_OPC_V2MNZ,
317 TILE_OPC_SHRH, 317 TILEGX_OPC_V2MULFSC,
318 TILE_OPC_SHRH_SN, 318 TILEGX_OPC_V2MULS,
319 TILE_OPC_SHRI, 319 TILEGX_OPC_V2MULTS,
320 TILE_OPC_SHRI_SN, 320 TILEGX_OPC_V2MZ,
321 TILE_OPC_SHRIB, 321 TILEGX_OPC_V2PACKH,
322 TILE_OPC_SHRIB_SN, 322 TILEGX_OPC_V2PACKL,
323 TILE_OPC_SHRIH, 323 TILEGX_OPC_V2PACKUC,
324 TILE_OPC_SHRIH_SN, 324 TILEGX_OPC_V2SADAS,
325 TILE_OPC_SLT, 325 TILEGX_OPC_V2SADAU,
326 TILE_OPC_SLT_SN, 326 TILEGX_OPC_V2SADS,
327 TILE_OPC_SLT_U, 327 TILEGX_OPC_V2SADU,
328 TILE_OPC_SLT_U_SN, 328 TILEGX_OPC_V2SHL,
329 TILE_OPC_SLTB, 329 TILEGX_OPC_V2SHLI,
330 TILE_OPC_SLTB_SN, 330 TILEGX_OPC_V2SHLSC,
331 TILE_OPC_SLTB_U, 331 TILEGX_OPC_V2SHRS,
332 TILE_OPC_SLTB_U_SN, 332 TILEGX_OPC_V2SHRSI,
333 TILE_OPC_SLTE, 333 TILEGX_OPC_V2SHRU,
334 TILE_OPC_SLTE_SN, 334 TILEGX_OPC_V2SHRUI,
335 TILE_OPC_SLTE_U, 335 TILEGX_OPC_V2SUB,
336 TILE_OPC_SLTE_U_SN, 336 TILEGX_OPC_V2SUBSC,
337 TILE_OPC_SLTEB, 337 TILEGX_OPC_V4ADD,
338 TILE_OPC_SLTEB_SN, 338 TILEGX_OPC_V4ADDSC,
339 TILE_OPC_SLTEB_U, 339 TILEGX_OPC_V4INT_H,
340 TILE_OPC_SLTEB_U_SN, 340 TILEGX_OPC_V4INT_L,
341 TILE_OPC_SLTEH, 341 TILEGX_OPC_V4PACKSC,
342 TILE_OPC_SLTEH_SN, 342 TILEGX_OPC_V4SHL,
343 TILE_OPC_SLTEH_U, 343 TILEGX_OPC_V4SHLSC,
344 TILE_OPC_SLTEH_U_SN, 344 TILEGX_OPC_V4SHRS,
345 TILE_OPC_SLTH, 345 TILEGX_OPC_V4SHRU,
346 TILE_OPC_SLTH_SN, 346 TILEGX_OPC_V4SUB,
347 TILE_OPC_SLTH_U, 347 TILEGX_OPC_V4SUBSC,
348 TILE_OPC_SLTH_U_SN, 348 TILEGX_OPC_WH64,
349 TILE_OPC_SLTI, 349 TILEGX_OPC_XOR,
350 TILE_OPC_SLTI_SN, 350 TILEGX_OPC_XORI,
351 TILE_OPC_SLTI_U, 351 TILEGX_OPC_NONE
352 TILE_OPC_SLTI_U_SN, 352} tilegx_mnemonic;
353 TILE_OPC_SLTIB,
354 TILE_OPC_SLTIB_SN,
355 TILE_OPC_SLTIB_U,
356 TILE_OPC_SLTIB_U_SN,
357 TILE_OPC_SLTIH,
358 TILE_OPC_SLTIH_SN,
359 TILE_OPC_SLTIH_U,
360 TILE_OPC_SLTIH_U_SN,
361 TILE_OPC_SNE,
362 TILE_OPC_SNE_SN,
363 TILE_OPC_SNEB,
364 TILE_OPC_SNEB_SN,
365 TILE_OPC_SNEH,
366 TILE_OPC_SNEH_SN,
367 TILE_OPC_SRA,
368 TILE_OPC_SRA_SN,
369 TILE_OPC_SRAB,
370 TILE_OPC_SRAB_SN,
371 TILE_OPC_SRAH,
372 TILE_OPC_SRAH_SN,
373 TILE_OPC_SRAI,
374 TILE_OPC_SRAI_SN,
375 TILE_OPC_SRAIB,
376 TILE_OPC_SRAIB_SN,
377 TILE_OPC_SRAIH,
378 TILE_OPC_SRAIH_SN,
379 TILE_OPC_SUB,
380 TILE_OPC_SUB_SN,
381 TILE_OPC_SUBB,
382 TILE_OPC_SUBB_SN,
383 TILE_OPC_SUBBS_U,
384 TILE_OPC_SUBBS_U_SN,
385 TILE_OPC_SUBH,
386 TILE_OPC_SUBH_SN,
387 TILE_OPC_SUBHS,
388 TILE_OPC_SUBHS_SN,
389 TILE_OPC_SUBS,
390 TILE_OPC_SUBS_SN,
391 TILE_OPC_SW,
392 TILE_OPC_SWADD,
393 TILE_OPC_SWINT0,
394 TILE_OPC_SWINT1,
395 TILE_OPC_SWINT2,
396 TILE_OPC_SWINT3,
397 TILE_OPC_TBLIDXB0,
398 TILE_OPC_TBLIDXB0_SN,
399 TILE_OPC_TBLIDXB1,
400 TILE_OPC_TBLIDXB1_SN,
401 TILE_OPC_TBLIDXB2,
402 TILE_OPC_TBLIDXB2_SN,
403 TILE_OPC_TBLIDXB3,
404 TILE_OPC_TBLIDXB3_SN,
405 TILE_OPC_TNS,
406 TILE_OPC_TNS_SN,
407 TILE_OPC_WH64,
408 TILE_OPC_XOR,
409 TILE_OPC_XOR_SN,
410 TILE_OPC_XORI,
411 TILE_OPC_XORI_SN,
412 TILE_OPC_NONE
413} tile_mnemonic;
414 353
415/* 64-bit pattern for a { bpt ; nop } bundle. */ 354/* 64-bit pattern for a { bpt ; nop } bundle. */
416#define TILE_BPT_BUNDLE 0x400b3cae70166000ULL 355#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
417 356
418 357
419#define TILE_ELF_MACHINE_CODE EM_TILEPRO 358#define TILE_ELF_MACHINE_CODE EM_TILE64
420 359
421#define TILE_ELF_NAME "elf32-tilepro" 360#define TILE_ELF_NAME "elf32-tile64"
422 361
423 362
424static __inline unsigned int 363static __inline unsigned int
425get_BrOff_SN(tile_bundle_bits num) 364get_BFEnd_X0(tilegx_bundle_bits num)
426{ 365{
427 const unsigned int n = (unsigned int)num; 366 const unsigned int n = (unsigned int)num;
428 return (((n >> 0)) & 0x3ff); 367 return (((n >> 12)) & 0x3f);
429} 368}
430 369
431static __inline unsigned int 370static __inline unsigned int
432get_BrOff_X1(tile_bundle_bits n) 371get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
433{ 372{
434 return (((unsigned int)(n >> 43)) & 0x00007fff) | 373 const unsigned int n = (unsigned int)num;
435 (((unsigned int)(n >> 20)) & 0x00018000); 374 return (((n >> 24)) & 0xf);
436} 375}
437 376
438static __inline unsigned int 377static __inline unsigned int
439get_BrType_X1(tile_bundle_bits n) 378get_BFStart_X0(tilegx_bundle_bits num)
440{ 379{
441 return (((unsigned int)(n >> 31)) & 0xf); 380 const unsigned int n = (unsigned int)num;
381 return (((n >> 18)) & 0x3f);
442} 382}
443 383
444static __inline unsigned int 384static __inline unsigned int
445get_Dest_Imm8_X1(tile_bundle_bits n) 385get_BrOff_X1(tilegx_bundle_bits n)
446{ 386{
447 return (((unsigned int)(n >> 31)) & 0x0000003f) | 387 return (((unsigned int)(n >> 31)) & 0x0000003f) |
448 (((unsigned int)(n >> 43)) & 0x000000c0); 388 (((unsigned int)(n >> 37)) & 0x0001ffc0);
449} 389}
450 390
451static __inline unsigned int 391static __inline unsigned int
452get_Dest_SN(tile_bundle_bits num) 392get_BrType_X1(tilegx_bundle_bits n)
453{ 393{
454 const unsigned int n = (unsigned int)num; 394 return (((unsigned int)(n >> 54)) & 0x1f);
455 return (((n >> 2)) & 0x3);
456} 395}
457 396
458static __inline unsigned int 397static __inline unsigned int
459get_Dest_X0(tile_bundle_bits num) 398get_Dest_Imm8_X1(tilegx_bundle_bits n)
399{
400 return (((unsigned int)(n >> 31)) & 0x0000003f) |
401 (((unsigned int)(n >> 43)) & 0x000000c0);
402}
403
404static __inline unsigned int
405get_Dest_X0(tilegx_bundle_bits num)
460{ 406{
461 const unsigned int n = (unsigned int)num; 407 const unsigned int n = (unsigned int)num;
462 return (((n >> 0)) & 0x3f); 408 return (((n >> 0)) & 0x3f);
463} 409}
464 410
465static __inline unsigned int 411static __inline unsigned int
466get_Dest_X1(tile_bundle_bits n) 412get_Dest_X1(tilegx_bundle_bits n)
467{ 413{
468 return (((unsigned int)(n >> 31)) & 0x3f); 414 return (((unsigned int)(n >> 31)) & 0x3f);
469} 415}
470 416
471static __inline unsigned int 417static __inline unsigned int
472get_Dest_Y0(tile_bundle_bits num) 418get_Dest_Y0(tilegx_bundle_bits num)
473{ 419{
474 const unsigned int n = (unsigned int)num; 420 const unsigned int n = (unsigned int)num;
475 return (((n >> 0)) & 0x3f); 421 return (((n >> 0)) & 0x3f);
476} 422}
477 423
478static __inline unsigned int 424static __inline unsigned int
479get_Dest_Y1(tile_bundle_bits n) 425get_Dest_Y1(tilegx_bundle_bits n)
480{ 426{
481 return (((unsigned int)(n >> 31)) & 0x3f); 427 return (((unsigned int)(n >> 31)) & 0x3f);
482} 428}
483 429
484static __inline unsigned int 430static __inline unsigned int
485get_Imm16_X0(tile_bundle_bits num) 431get_Imm16_X0(tilegx_bundle_bits num)
486{ 432{
487 const unsigned int n = (unsigned int)num; 433 const unsigned int n = (unsigned int)num;
488 return (((n >> 12)) & 0xffff); 434 return (((n >> 12)) & 0xffff);
489} 435}
490 436
491static __inline unsigned int 437static __inline unsigned int
492get_Imm16_X1(tile_bundle_bits n) 438get_Imm16_X1(tilegx_bundle_bits n)
493{ 439{
494 return (((unsigned int)(n >> 43)) & 0xffff); 440 return (((unsigned int)(n >> 43)) & 0xffff);
495} 441}
496 442
497static __inline unsigned int 443static __inline unsigned int
498get_Imm8_SN(tile_bundle_bits num) 444get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
499{
500 const unsigned int n = (unsigned int)num;
501 return (((n >> 0)) & 0xff);
502}
503
504static __inline unsigned int
505get_Imm8_X0(tile_bundle_bits num)
506{ 445{
507 const unsigned int n = (unsigned int)num; 446 const unsigned int n = (unsigned int)num;
508 return (((n >> 12)) & 0xff); 447 return (((n >> 20)) & 0xff);
509} 448}
510 449
511static __inline unsigned int 450static __inline unsigned int
512get_Imm8_X1(tile_bundle_bits n) 451get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
513{ 452{
514 return (((unsigned int)(n >> 43)) & 0xff); 453 return (((unsigned int)(n >> 51)) & 0xff);
515} 454}
516 455
517static __inline unsigned int 456static __inline unsigned int
518get_Imm8_Y0(tile_bundle_bits num) 457get_Imm8_X0(tilegx_bundle_bits num)
519{ 458{
520 const unsigned int n = (unsigned int)num; 459 const unsigned int n = (unsigned int)num;
521 return (((n >> 12)) & 0xff); 460 return (((n >> 12)) & 0xff);
522} 461}
523 462
524static __inline unsigned int 463static __inline unsigned int
525get_Imm8_Y1(tile_bundle_bits n) 464get_Imm8_X1(tilegx_bundle_bits n)
526{ 465{
527 return (((unsigned int)(n >> 43)) & 0xff); 466 return (((unsigned int)(n >> 43)) & 0xff);
528} 467}
529 468
530static __inline unsigned int 469static __inline unsigned int
531get_ImmOpcodeExtension_X0(tile_bundle_bits num) 470get_Imm8_Y0(tilegx_bundle_bits num)
532{
533 const unsigned int n = (unsigned int)num;
534 return (((n >> 20)) & 0x7f);
535}
536
537static __inline unsigned int
538get_ImmOpcodeExtension_X1(tile_bundle_bits n)
539{
540 return (((unsigned int)(n >> 51)) & 0x7f);
541}
542
543static __inline unsigned int
544get_ImmRROpcodeExtension_SN(tile_bundle_bits num)
545{ 471{
546 const unsigned int n = (unsigned int)num; 472 const unsigned int n = (unsigned int)num;
547 return (((n >> 8)) & 0x3); 473 return (((n >> 12)) & 0xff);
548}
549
550static __inline unsigned int
551get_JOffLong_X1(tile_bundle_bits n)
552{
553 return (((unsigned int)(n >> 43)) & 0x00007fff) |
554 (((unsigned int)(n >> 20)) & 0x00018000) |
555 (((unsigned int)(n >> 14)) & 0x001e0000) |
556 (((unsigned int)(n >> 16)) & 0x07e00000) |
557 (((unsigned int)(n >> 31)) & 0x18000000);
558}
559
560static __inline unsigned int
561get_JOff_X1(tile_bundle_bits n)
562{
563 return (((unsigned int)(n >> 43)) & 0x00007fff) |
564 (((unsigned int)(n >> 20)) & 0x00018000) |
565 (((unsigned int)(n >> 14)) & 0x001e0000) |
566 (((unsigned int)(n >> 16)) & 0x07e00000) |
567 (((unsigned int)(n >> 31)) & 0x08000000);
568}
569
570static __inline unsigned int
571get_MF_Imm15_X1(tile_bundle_bits n)
572{
573 return (((unsigned int)(n >> 37)) & 0x00003fff) |
574 (((unsigned int)(n >> 44)) & 0x00004000);
575} 474}
576 475
577static __inline unsigned int 476static __inline unsigned int
578get_MMEnd_X0(tile_bundle_bits num) 477get_Imm8_Y1(tilegx_bundle_bits n)
579{ 478{
580 const unsigned int n = (unsigned int)num; 479 return (((unsigned int)(n >> 43)) & 0xff);
581 return (((n >> 18)) & 0x1f);
582} 480}
583 481
584static __inline unsigned int 482static __inline unsigned int
585get_MMEnd_X1(tile_bundle_bits n) 483get_JumpOff_X1(tilegx_bundle_bits n)
586{ 484{
587 return (((unsigned int)(n >> 49)) & 0x1f); 485 return (((unsigned int)(n >> 31)) & 0x7ffffff);
588} 486}
589 487
590static __inline unsigned int 488static __inline unsigned int
591get_MMStart_X0(tile_bundle_bits num) 489get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
592{ 490{
593 const unsigned int n = (unsigned int)num; 491 return (((unsigned int)(n >> 58)) & 0x1);
594 return (((n >> 23)) & 0x1f);
595} 492}
596 493
597static __inline unsigned int 494static __inline unsigned int
598get_MMStart_X1(tile_bundle_bits n) 495get_MF_Imm14_X1(tilegx_bundle_bits n)
599{ 496{
600 return (((unsigned int)(n >> 54)) & 0x1f); 497 return (((unsigned int)(n >> 37)) & 0x3fff);
601} 498}
602 499
603static __inline unsigned int 500static __inline unsigned int
604get_MT_Imm15_X1(tile_bundle_bits n) 501get_MT_Imm14_X1(tilegx_bundle_bits n)
605{ 502{
606 return (((unsigned int)(n >> 31)) & 0x0000003f) | 503 return (((unsigned int)(n >> 31)) & 0x0000003f) |
607 (((unsigned int)(n >> 37)) & 0x00003fc0) | 504 (((unsigned int)(n >> 37)) & 0x00003fc0);
608 (((unsigned int)(n >> 44)) & 0x00004000);
609} 505}
610 506
611static __inline unsigned int 507static __inline unsigned int
612get_Mode(tile_bundle_bits n) 508get_Mode(tilegx_bundle_bits n)
613{ 509{
614 return (((unsigned int)(n >> 63)) & 0x1); 510 return (((unsigned int)(n >> 62)) & 0x3);
615} 511}
616 512
617static __inline unsigned int 513static __inline unsigned int
618get_NoRegOpcodeExtension_SN(tile_bundle_bits num) 514get_Opcode_X0(tilegx_bundle_bits num)
619{
620 const unsigned int n = (unsigned int)num;
621 return (((n >> 0)) & 0xf);
622}
623
624static __inline unsigned int
625get_Opcode_SN(tile_bundle_bits num)
626{
627 const unsigned int n = (unsigned int)num;
628 return (((n >> 10)) & 0x3f);
629}
630
631static __inline unsigned int
632get_Opcode_X0(tile_bundle_bits num)
633{ 515{
634 const unsigned int n = (unsigned int)num; 516 const unsigned int n = (unsigned int)num;
635 return (((n >> 28)) & 0x7); 517 return (((n >> 28)) & 0x7);
636} 518}
637 519
638static __inline unsigned int 520static __inline unsigned int
639get_Opcode_X1(tile_bundle_bits n) 521get_Opcode_X1(tilegx_bundle_bits n)
640{ 522{
641 return (((unsigned int)(n >> 59)) & 0xf); 523 return (((unsigned int)(n >> 59)) & 0x7);
642} 524}
643 525
644static __inline unsigned int 526static __inline unsigned int
645get_Opcode_Y0(tile_bundle_bits num) 527get_Opcode_Y0(tilegx_bundle_bits num)
646{ 528{
647 const unsigned int n = (unsigned int)num; 529 const unsigned int n = (unsigned int)num;
648 return (((n >> 27)) & 0xf); 530 return (((n >> 27)) & 0xf);
649} 531}
650 532
651static __inline unsigned int 533static __inline unsigned int
652get_Opcode_Y1(tile_bundle_bits n) 534get_Opcode_Y1(tilegx_bundle_bits n)
653{ 535{
654 return (((unsigned int)(n >> 59)) & 0xf); 536 return (((unsigned int)(n >> 58)) & 0xf);
655} 537}
656 538
657static __inline unsigned int 539static __inline unsigned int
658get_Opcode_Y2(tile_bundle_bits n) 540get_Opcode_Y2(tilegx_bundle_bits n)
659{ 541{
660 return (((unsigned int)(n >> 56)) & 0x7); 542 return (((n >> 26)) & 0x00000001) |
661} 543 (((unsigned int)(n >> 56)) & 0x00000002);
662
663static __inline unsigned int
664get_RROpcodeExtension_SN(tile_bundle_bits num)
665{
666 const unsigned int n = (unsigned int)num;
667 return (((n >> 4)) & 0xf);
668} 544}
669 545
670static __inline unsigned int 546static __inline unsigned int
671get_RRROpcodeExtension_X0(tile_bundle_bits num) 547get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
672{ 548{
673 const unsigned int n = (unsigned int)num; 549 const unsigned int n = (unsigned int)num;
674 return (((n >> 18)) & 0x1ff); 550 return (((n >> 18)) & 0x3ff);
675} 551}
676 552
677static __inline unsigned int 553static __inline unsigned int
678get_RRROpcodeExtension_X1(tile_bundle_bits n) 554get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
679{ 555{
680 return (((unsigned int)(n >> 49)) & 0x1ff); 556 return (((unsigned int)(n >> 49)) & 0x3ff);
681} 557}
682 558
683static __inline unsigned int 559static __inline unsigned int
684get_RRROpcodeExtension_Y0(tile_bundle_bits num) 560get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
685{ 561{
686 const unsigned int n = (unsigned int)num; 562 const unsigned int n = (unsigned int)num;
687 return (((n >> 18)) & 0x3); 563 return (((n >> 18)) & 0x3);
688} 564}
689 565
690static __inline unsigned int 566static __inline unsigned int
691get_RRROpcodeExtension_Y1(tile_bundle_bits n) 567get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
692{ 568{
693 return (((unsigned int)(n >> 49)) & 0x3); 569 return (((unsigned int)(n >> 49)) & 0x3);
694} 570}
695 571
696static __inline unsigned int 572static __inline unsigned int
697get_RouteOpcodeExtension_SN(tile_bundle_bits num) 573get_ShAmt_X0(tilegx_bundle_bits num)
698{
699 const unsigned int n = (unsigned int)num;
700 return (((n >> 0)) & 0x3ff);
701}
702
703static __inline unsigned int
704get_S_X0(tile_bundle_bits num)
705{ 574{
706 const unsigned int n = (unsigned int)num; 575 const unsigned int n = (unsigned int)num;
707 return (((n >> 27)) & 0x1); 576 return (((n >> 12)) & 0x3f);
708} 577}
709 578
710static __inline unsigned int 579static __inline unsigned int
711get_S_X1(tile_bundle_bits n) 580get_ShAmt_X1(tilegx_bundle_bits n)
712{ 581{
713 return (((unsigned int)(n >> 58)) & 0x1); 582 return (((unsigned int)(n >> 43)) & 0x3f);
714} 583}
715 584
716static __inline unsigned int 585static __inline unsigned int
717get_ShAmt_X0(tile_bundle_bits num) 586get_ShAmt_Y0(tilegx_bundle_bits num)
718{ 587{
719 const unsigned int n = (unsigned int)num; 588 const unsigned int n = (unsigned int)num;
720 return (((n >> 12)) & 0x1f); 589 return (((n >> 12)) & 0x3f);
721} 590}
722 591
723static __inline unsigned int 592static __inline unsigned int
724get_ShAmt_X1(tile_bundle_bits n) 593get_ShAmt_Y1(tilegx_bundle_bits n)
725{ 594{
726 return (((unsigned int)(n >> 43)) & 0x1f); 595 return (((unsigned int)(n >> 43)) & 0x3f);
727} 596}
728 597
729static __inline unsigned int 598static __inline unsigned int
730get_ShAmt_Y0(tile_bundle_bits num) 599get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
731{ 600{
732 const unsigned int n = (unsigned int)num; 601 const unsigned int n = (unsigned int)num;
733 return (((n >> 12)) & 0x1f); 602 return (((n >> 18)) & 0x3ff);
734} 603}
735 604
736static __inline unsigned int 605static __inline unsigned int
737get_ShAmt_Y1(tile_bundle_bits n) 606get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
738{ 607{
739 return (((unsigned int)(n >> 43)) & 0x1f); 608 return (((unsigned int)(n >> 49)) & 0x3ff);
740} 609}
741 610
742static __inline unsigned int 611static __inline unsigned int
743get_SrcA_X0(tile_bundle_bits num) 612get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
744{ 613{
745 const unsigned int n = (unsigned int)num; 614 const unsigned int n = (unsigned int)num;
746 return (((n >> 6)) & 0x3f); 615 return (((n >> 18)) & 0x3);
747} 616}
748 617
749static __inline unsigned int 618static __inline unsigned int
750get_SrcA_X1(tile_bundle_bits n) 619get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
751{ 620{
752 return (((unsigned int)(n >> 37)) & 0x3f); 621 return (((unsigned int)(n >> 49)) & 0x3);
753} 622}
754 623
755static __inline unsigned int 624static __inline unsigned int
756get_SrcA_Y0(tile_bundle_bits num) 625get_SrcA_X0(tilegx_bundle_bits num)
757{ 626{
758 const unsigned int n = (unsigned int)num; 627 const unsigned int n = (unsigned int)num;
759 return (((n >> 6)) & 0x3f); 628 return (((n >> 6)) & 0x3f);
760} 629}
761 630
762static __inline unsigned int 631static __inline unsigned int
763get_SrcA_Y1(tile_bundle_bits n) 632get_SrcA_X1(tilegx_bundle_bits n)
764{ 633{
765 return (((unsigned int)(n >> 37)) & 0x3f); 634 return (((unsigned int)(n >> 37)) & 0x3f);
766} 635}
767 636
768static __inline unsigned int 637static __inline unsigned int
769get_SrcA_Y2(tile_bundle_bits n) 638get_SrcA_Y0(tilegx_bundle_bits num)
770{ 639{
771 return (((n >> 26)) & 0x00000001) | 640 const unsigned int n = (unsigned int)num;
772 (((unsigned int)(n >> 50)) & 0x0000003e); 641 return (((n >> 6)) & 0x3f);
773} 642}
774 643
775static __inline unsigned int 644static __inline unsigned int
776get_SrcBDest_Y2(tile_bundle_bits num) 645get_SrcA_Y1(tilegx_bundle_bits n)
777{ 646{
778 const unsigned int n = (unsigned int)num; 647 return (((unsigned int)(n >> 37)) & 0x3f);
779 return (((n >> 20)) & 0x3f);
780} 648}
781 649
782static __inline unsigned int 650static __inline unsigned int
783get_SrcB_X0(tile_bundle_bits num) 651get_SrcA_Y2(tilegx_bundle_bits num)
784{ 652{
785 const unsigned int n = (unsigned int)num; 653 const unsigned int n = (unsigned int)num;
786 return (((n >> 12)) & 0x3f); 654 return (((n >> 20)) & 0x3f);
787} 655}
788 656
789static __inline unsigned int 657static __inline unsigned int
790get_SrcB_X1(tile_bundle_bits n) 658get_SrcBDest_Y2(tilegx_bundle_bits n)
791{ 659{
792 return (((unsigned int)(n >> 43)) & 0x3f); 660 return (((unsigned int)(n >> 51)) & 0x3f);
793} 661}
794 662
795static __inline unsigned int 663static __inline unsigned int
796get_SrcB_Y0(tile_bundle_bits num) 664get_SrcB_X0(tilegx_bundle_bits num)
797{ 665{
798 const unsigned int n = (unsigned int)num; 666 const unsigned int n = (unsigned int)num;
799 return (((n >> 12)) & 0x3f); 667 return (((n >> 12)) & 0x3f);
800} 668}
801 669
802static __inline unsigned int 670static __inline unsigned int
803get_SrcB_Y1(tile_bundle_bits n) 671get_SrcB_X1(tilegx_bundle_bits n)
804{ 672{
805 return (((unsigned int)(n >> 43)) & 0x3f); 673 return (((unsigned int)(n >> 43)) & 0x3f);
806} 674}
807 675
808static __inline unsigned int 676static __inline unsigned int
809get_Src_SN(tile_bundle_bits num) 677get_SrcB_Y0(tilegx_bundle_bits num)
810{ 678{
811 const unsigned int n = (unsigned int)num; 679 const unsigned int n = (unsigned int)num;
812 return (((n >> 0)) & 0x3); 680 return (((n >> 12)) & 0x3f);
813}
814
815static __inline unsigned int
816get_UnOpcodeExtension_X0(tile_bundle_bits num)
817{
818 const unsigned int n = (unsigned int)num;
819 return (((n >> 12)) & 0x1f);
820}
821
822static __inline unsigned int
823get_UnOpcodeExtension_X1(tile_bundle_bits n)
824{
825 return (((unsigned int)(n >> 43)) & 0x1f);
826}
827
828static __inline unsigned int
829get_UnOpcodeExtension_Y0(tile_bundle_bits num)
830{
831 const unsigned int n = (unsigned int)num;
832 return (((n >> 12)) & 0x1f);
833} 681}
834 682
835static __inline unsigned int 683static __inline unsigned int
836get_UnOpcodeExtension_Y1(tile_bundle_bits n) 684get_SrcB_Y1(tilegx_bundle_bits n)
837{ 685{
838 return (((unsigned int)(n >> 43)) & 0x1f); 686 return (((unsigned int)(n >> 43)) & 0x3f);
839} 687}
840 688
841static __inline unsigned int 689static __inline unsigned int
842get_UnShOpcodeExtension_X0(tile_bundle_bits num) 690get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
843{ 691{
844 const unsigned int n = (unsigned int)num; 692 const unsigned int n = (unsigned int)num;
845 return (((n >> 17)) & 0x3ff); 693 return (((n >> 12)) & 0x3f);
846} 694}
847 695
848static __inline unsigned int 696static __inline unsigned int
849get_UnShOpcodeExtension_X1(tile_bundle_bits n) 697get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
850{ 698{
851 return (((unsigned int)(n >> 48)) & 0x3ff); 699 return (((unsigned int)(n >> 43)) & 0x3f);
852} 700}
853 701
854static __inline unsigned int 702static __inline unsigned int
855get_UnShOpcodeExtension_Y0(tile_bundle_bits num) 703get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
856{ 704{
857 const unsigned int n = (unsigned int)num; 705 const unsigned int n = (unsigned int)num;
858 return (((n >> 17)) & 0x7); 706 return (((n >> 12)) & 0x3f);
859} 707}
860 708
861static __inline unsigned int 709static __inline unsigned int
862get_UnShOpcodeExtension_Y1(tile_bundle_bits n) 710get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
863{ 711{
864 return (((unsigned int)(n >> 48)) & 0x7); 712 return (((unsigned int)(n >> 43)) & 0x3f);
865} 713}
866 714
867 715
@@ -874,546 +722,441 @@ sign_extend(int n, int num_bits)
874 722
875 723
876 724
877static __inline tile_bundle_bits 725static __inline tilegx_bundle_bits
878create_BrOff_SN(int num) 726create_BFEnd_X0(int num)
879{ 727{
880 const unsigned int n = (unsigned int)num; 728 const unsigned int n = (unsigned int)num;
881 return ((n & 0x3ff) << 0); 729 return ((n & 0x3f) << 12);
882} 730}
883 731
884static __inline tile_bundle_bits 732static __inline tilegx_bundle_bits
885create_BrOff_X1(int num) 733create_BFOpcodeExtension_X0(int num)
886{ 734{
887 const unsigned int n = (unsigned int)num; 735 const unsigned int n = (unsigned int)num;
888 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | 736 return ((n & 0xf) << 24);
889 (((tile_bundle_bits)(n & 0x00018000)) << 20);
890} 737}
891 738
892static __inline tile_bundle_bits 739static __inline tilegx_bundle_bits
893create_BrType_X1(int num) 740create_BFStart_X0(int num)
894{ 741{
895 const unsigned int n = (unsigned int)num; 742 const unsigned int n = (unsigned int)num;
896 return (((tile_bundle_bits)(n & 0xf)) << 31); 743 return ((n & 0x3f) << 18);
897} 744}
898 745
899static __inline tile_bundle_bits 746static __inline tilegx_bundle_bits
900create_Dest_Imm8_X1(int num) 747create_BrOff_X1(int num)
901{ 748{
902 const unsigned int n = (unsigned int)num; 749 const unsigned int n = (unsigned int)num;
903 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) | 750 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
904 (((tile_bundle_bits)(n & 0x000000c0)) << 43); 751 (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
905} 752}
906 753
907static __inline tile_bundle_bits 754static __inline tilegx_bundle_bits
908create_Dest_SN(int num) 755create_BrType_X1(int num)
756{
757 const unsigned int n = (unsigned int)num;
758 return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
759}
760
761static __inline tilegx_bundle_bits
762create_Dest_Imm8_X1(int num)
909{ 763{
910 const unsigned int n = (unsigned int)num; 764 const unsigned int n = (unsigned int)num;
911 return ((n & 0x3) << 2); 765 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
766 (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
912} 767}
913 768
914static __inline tile_bundle_bits 769static __inline tilegx_bundle_bits
915create_Dest_X0(int num) 770create_Dest_X0(int num)
916{ 771{
917 const unsigned int n = (unsigned int)num; 772 const unsigned int n = (unsigned int)num;
918 return ((n & 0x3f) << 0); 773 return ((n & 0x3f) << 0);
919} 774}
920 775
921static __inline tile_bundle_bits 776static __inline tilegx_bundle_bits
922create_Dest_X1(int num) 777create_Dest_X1(int num)
923{ 778{
924 const unsigned int n = (unsigned int)num; 779 const unsigned int n = (unsigned int)num;
925 return (((tile_bundle_bits)(n & 0x3f)) << 31); 780 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
926} 781}
927 782
928static __inline tile_bundle_bits 783static __inline tilegx_bundle_bits
929create_Dest_Y0(int num) 784create_Dest_Y0(int num)
930{ 785{
931 const unsigned int n = (unsigned int)num; 786 const unsigned int n = (unsigned int)num;
932 return ((n & 0x3f) << 0); 787 return ((n & 0x3f) << 0);
933} 788}
934 789
935static __inline tile_bundle_bits 790static __inline tilegx_bundle_bits
936create_Dest_Y1(int num) 791create_Dest_Y1(int num)
937{ 792{
938 const unsigned int n = (unsigned int)num; 793 const unsigned int n = (unsigned int)num;
939 return (((tile_bundle_bits)(n & 0x3f)) << 31); 794 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
940} 795}
941 796
942static __inline tile_bundle_bits 797static __inline tilegx_bundle_bits
943create_Imm16_X0(int num) 798create_Imm16_X0(int num)
944{ 799{
945 const unsigned int n = (unsigned int)num; 800 const unsigned int n = (unsigned int)num;
946 return ((n & 0xffff) << 12); 801 return ((n & 0xffff) << 12);
947} 802}
948 803
949static __inline tile_bundle_bits 804static __inline tilegx_bundle_bits
950create_Imm16_X1(int num) 805create_Imm16_X1(int num)
951{ 806{
952 const unsigned int n = (unsigned int)num; 807 const unsigned int n = (unsigned int)num;
953 return (((tile_bundle_bits)(n & 0xffff)) << 43); 808 return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
954} 809}
955 810
956static __inline tile_bundle_bits 811static __inline tilegx_bundle_bits
957create_Imm8_SN(int num) 812create_Imm8OpcodeExtension_X0(int num)
958{ 813{
959 const unsigned int n = (unsigned int)num; 814 const unsigned int n = (unsigned int)num;
960 return ((n & 0xff) << 0); 815 return ((n & 0xff) << 20);
961} 816}
962 817
963static __inline tile_bundle_bits 818static __inline tilegx_bundle_bits
819create_Imm8OpcodeExtension_X1(int num)
820{
821 const unsigned int n = (unsigned int)num;
822 return (((tilegx_bundle_bits)(n & 0xff)) << 51);
823}
824
825static __inline tilegx_bundle_bits
964create_Imm8_X0(int num) 826create_Imm8_X0(int num)
965{ 827{
966 const unsigned int n = (unsigned int)num; 828 const unsigned int n = (unsigned int)num;
967 return ((n & 0xff) << 12); 829 return ((n & 0xff) << 12);
968} 830}
969 831
970static __inline tile_bundle_bits 832static __inline tilegx_bundle_bits
971create_Imm8_X1(int num) 833create_Imm8_X1(int num)
972{ 834{
973 const unsigned int n = (unsigned int)num; 835 const unsigned int n = (unsigned int)num;
974 return (((tile_bundle_bits)(n & 0xff)) << 43); 836 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
975} 837}
976 838
977static __inline tile_bundle_bits 839static __inline tilegx_bundle_bits
978create_Imm8_Y0(int num) 840create_Imm8_Y0(int num)
979{ 841{
980 const unsigned int n = (unsigned int)num; 842 const unsigned int n = (unsigned int)num;
981 return ((n & 0xff) << 12); 843 return ((n & 0xff) << 12);
982} 844}
983 845
984static __inline tile_bundle_bits 846static __inline tilegx_bundle_bits
985create_Imm8_Y1(int num) 847create_Imm8_Y1(int num)
986{ 848{
987 const unsigned int n = (unsigned int)num; 849 const unsigned int n = (unsigned int)num;
988 return (((tile_bundle_bits)(n & 0xff)) << 43); 850 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
989}
990
991static __inline tile_bundle_bits
992create_ImmOpcodeExtension_X0(int num)
993{
994 const unsigned int n = (unsigned int)num;
995 return ((n & 0x7f) << 20);
996}
997
998static __inline tile_bundle_bits
999create_ImmOpcodeExtension_X1(int num)
1000{
1001 const unsigned int n = (unsigned int)num;
1002 return (((tile_bundle_bits)(n & 0x7f)) << 51);
1003}
1004
1005static __inline tile_bundle_bits
1006create_ImmRROpcodeExtension_SN(int num)
1007{
1008 const unsigned int n = (unsigned int)num;
1009 return ((n & 0x3) << 8);
1010}
1011
1012static __inline tile_bundle_bits
1013create_JOffLong_X1(int num)
1014{
1015 const unsigned int n = (unsigned int)num;
1016 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1017 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1018 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1019 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1020 (((tile_bundle_bits)(n & 0x18000000)) << 31);
1021}
1022
1023static __inline tile_bundle_bits
1024create_JOff_X1(int num)
1025{
1026 const unsigned int n = (unsigned int)num;
1027 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1028 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1029 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1030 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1031 (((tile_bundle_bits)(n & 0x08000000)) << 31);
1032}
1033
1034static __inline tile_bundle_bits
1035create_MF_Imm15_X1(int num)
1036{
1037 const unsigned int n = (unsigned int)num;
1038 return (((tile_bundle_bits)(n & 0x00003fff)) << 37) |
1039 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1040} 851}
1041 852
1042static __inline tile_bundle_bits 853static __inline tilegx_bundle_bits
1043create_MMEnd_X0(int num) 854create_JumpOff_X1(int num)
1044{ 855{
1045 const unsigned int n = (unsigned int)num; 856 const unsigned int n = (unsigned int)num;
1046 return ((n & 0x1f) << 18); 857 return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
1047} 858}
1048 859
1049static __inline tile_bundle_bits 860static __inline tilegx_bundle_bits
1050create_MMEnd_X1(int num) 861create_JumpOpcodeExtension_X1(int num)
1051{ 862{
1052 const unsigned int n = (unsigned int)num; 863 const unsigned int n = (unsigned int)num;
1053 return (((tile_bundle_bits)(n & 0x1f)) << 49); 864 return (((tilegx_bundle_bits)(n & 0x1)) << 58);
1054} 865}
1055 866
1056static __inline tile_bundle_bits 867static __inline tilegx_bundle_bits
1057create_MMStart_X0(int num) 868create_MF_Imm14_X1(int num)
1058{ 869{
1059 const unsigned int n = (unsigned int)num; 870 const unsigned int n = (unsigned int)num;
1060 return ((n & 0x1f) << 23); 871 return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
1061} 872}
1062 873
1063static __inline tile_bundle_bits 874static __inline tilegx_bundle_bits
1064create_MMStart_X1(int num) 875create_MT_Imm14_X1(int num)
1065{ 876{
1066 const unsigned int n = (unsigned int)num; 877 const unsigned int n = (unsigned int)num;
1067 return (((tile_bundle_bits)(n & 0x1f)) << 54); 878 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
879 (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
1068} 880}
1069 881
1070static __inline tile_bundle_bits 882static __inline tilegx_bundle_bits
1071create_MT_Imm15_X1(int num)
1072{
1073 const unsigned int n = (unsigned int)num;
1074 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
1075 (((tile_bundle_bits)(n & 0x00003fc0)) << 37) |
1076 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1077}
1078
1079static __inline tile_bundle_bits
1080create_Mode(int num) 883create_Mode(int num)
1081{ 884{
1082 const unsigned int n = (unsigned int)num; 885 const unsigned int n = (unsigned int)num;
1083 return (((tile_bundle_bits)(n & 0x1)) << 63); 886 return (((tilegx_bundle_bits)(n & 0x3)) << 62);
1084} 887}
1085 888
1086static __inline tile_bundle_bits 889static __inline tilegx_bundle_bits
1087create_NoRegOpcodeExtension_SN(int num)
1088{
1089 const unsigned int n = (unsigned int)num;
1090 return ((n & 0xf) << 0);
1091}
1092
1093static __inline tile_bundle_bits
1094create_Opcode_SN(int num)
1095{
1096 const unsigned int n = (unsigned int)num;
1097 return ((n & 0x3f) << 10);
1098}
1099
1100static __inline tile_bundle_bits
1101create_Opcode_X0(int num) 890create_Opcode_X0(int num)
1102{ 891{
1103 const unsigned int n = (unsigned int)num; 892 const unsigned int n = (unsigned int)num;
1104 return ((n & 0x7) << 28); 893 return ((n & 0x7) << 28);
1105} 894}
1106 895
1107static __inline tile_bundle_bits 896static __inline tilegx_bundle_bits
1108create_Opcode_X1(int num) 897create_Opcode_X1(int num)
1109{ 898{
1110 const unsigned int n = (unsigned int)num; 899 const unsigned int n = (unsigned int)num;
1111 return (((tile_bundle_bits)(n & 0xf)) << 59); 900 return (((tilegx_bundle_bits)(n & 0x7)) << 59);
1112} 901}
1113 902
1114static __inline tile_bundle_bits 903static __inline tilegx_bundle_bits
1115create_Opcode_Y0(int num) 904create_Opcode_Y0(int num)
1116{ 905{
1117 const unsigned int n = (unsigned int)num; 906 const unsigned int n = (unsigned int)num;
1118 return ((n & 0xf) << 27); 907 return ((n & 0xf) << 27);
1119} 908}
1120 909
1121static __inline tile_bundle_bits 910static __inline tilegx_bundle_bits
1122create_Opcode_Y1(int num) 911create_Opcode_Y1(int num)
1123{ 912{
1124 const unsigned int n = (unsigned int)num; 913 const unsigned int n = (unsigned int)num;
1125 return (((tile_bundle_bits)(n & 0xf)) << 59); 914 return (((tilegx_bundle_bits)(n & 0xf)) << 58);
1126} 915}
1127 916
1128static __inline tile_bundle_bits 917static __inline tilegx_bundle_bits
1129create_Opcode_Y2(int num) 918create_Opcode_Y2(int num)
1130{ 919{
1131 const unsigned int n = (unsigned int)num; 920 const unsigned int n = (unsigned int)num;
1132 return (((tile_bundle_bits)(n & 0x7)) << 56); 921 return ((n & 0x00000001) << 26) |
1133} 922 (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
1134
1135static __inline tile_bundle_bits
1136create_RROpcodeExtension_SN(int num)
1137{
1138 const unsigned int n = (unsigned int)num;
1139 return ((n & 0xf) << 4);
1140} 923}
1141 924
1142static __inline tile_bundle_bits 925static __inline tilegx_bundle_bits
1143create_RRROpcodeExtension_X0(int num) 926create_RRROpcodeExtension_X0(int num)
1144{ 927{
1145 const unsigned int n = (unsigned int)num; 928 const unsigned int n = (unsigned int)num;
1146 return ((n & 0x1ff) << 18); 929 return ((n & 0x3ff) << 18);
1147} 930}
1148 931
1149static __inline tile_bundle_bits 932static __inline tilegx_bundle_bits
1150create_RRROpcodeExtension_X1(int num) 933create_RRROpcodeExtension_X1(int num)
1151{ 934{
1152 const unsigned int n = (unsigned int)num; 935 const unsigned int n = (unsigned int)num;
1153 return (((tile_bundle_bits)(n & 0x1ff)) << 49); 936 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1154} 937}
1155 938
1156static __inline tile_bundle_bits 939static __inline tilegx_bundle_bits
1157create_RRROpcodeExtension_Y0(int num) 940create_RRROpcodeExtension_Y0(int num)
1158{ 941{
1159 const unsigned int n = (unsigned int)num; 942 const unsigned int n = (unsigned int)num;
1160 return ((n & 0x3) << 18); 943 return ((n & 0x3) << 18);
1161} 944}
1162 945
1163static __inline tile_bundle_bits 946static __inline tilegx_bundle_bits
1164create_RRROpcodeExtension_Y1(int num) 947create_RRROpcodeExtension_Y1(int num)
1165{ 948{
1166 const unsigned int n = (unsigned int)num; 949 const unsigned int n = (unsigned int)num;
1167 return (((tile_bundle_bits)(n & 0x3)) << 49); 950 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1168} 951}
1169 952
1170static __inline tile_bundle_bits 953static __inline tilegx_bundle_bits
1171create_RouteOpcodeExtension_SN(int num) 954create_ShAmt_X0(int num)
1172{ 955{
1173 const unsigned int n = (unsigned int)num; 956 const unsigned int n = (unsigned int)num;
1174 return ((n & 0x3ff) << 0); 957 return ((n & 0x3f) << 12);
1175} 958}
1176 959
1177static __inline tile_bundle_bits 960static __inline tilegx_bundle_bits
1178create_S_X0(int num) 961create_ShAmt_X1(int num)
1179{ 962{
1180 const unsigned int n = (unsigned int)num; 963 const unsigned int n = (unsigned int)num;
1181 return ((n & 0x1) << 27); 964 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1182} 965}
1183 966
1184static __inline tile_bundle_bits 967static __inline tilegx_bundle_bits
1185create_S_X1(int num) 968create_ShAmt_Y0(int num)
1186{ 969{
1187 const unsigned int n = (unsigned int)num; 970 const unsigned int n = (unsigned int)num;
1188 return (((tile_bundle_bits)(n & 0x1)) << 58); 971 return ((n & 0x3f) << 12);
1189} 972}
1190 973
1191static __inline tile_bundle_bits 974static __inline tilegx_bundle_bits
1192create_ShAmt_X0(int num) 975create_ShAmt_Y1(int num)
1193{ 976{
1194 const unsigned int n = (unsigned int)num; 977 const unsigned int n = (unsigned int)num;
1195 return ((n & 0x1f) << 12); 978 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1196} 979}
1197 980
1198static __inline tile_bundle_bits 981static __inline tilegx_bundle_bits
1199create_ShAmt_X1(int num) 982create_ShiftOpcodeExtension_X0(int num)
1200{ 983{
1201 const unsigned int n = (unsigned int)num; 984 const unsigned int n = (unsigned int)num;
1202 return (((tile_bundle_bits)(n & 0x1f)) << 43); 985 return ((n & 0x3ff) << 18);
1203} 986}
1204 987
1205static __inline tile_bundle_bits 988static __inline tilegx_bundle_bits
1206create_ShAmt_Y0(int num) 989create_ShiftOpcodeExtension_X1(int num)
1207{ 990{
1208 const unsigned int n = (unsigned int)num; 991 const unsigned int n = (unsigned int)num;
1209 return ((n & 0x1f) << 12); 992 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1210} 993}
1211 994
1212static __inline tile_bundle_bits 995static __inline tilegx_bundle_bits
1213create_ShAmt_Y1(int num) 996create_ShiftOpcodeExtension_Y0(int num)
1214{ 997{
1215 const unsigned int n = (unsigned int)num; 998 const unsigned int n = (unsigned int)num;
1216 return (((tile_bundle_bits)(n & 0x1f)) << 43); 999 return ((n & 0x3) << 18);
1217} 1000}
1218 1001
1219static __inline tile_bundle_bits 1002static __inline tilegx_bundle_bits
1003create_ShiftOpcodeExtension_Y1(int num)
1004{
1005 const unsigned int n = (unsigned int)num;
1006 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1007}
1008
1009static __inline tilegx_bundle_bits
1220create_SrcA_X0(int num) 1010create_SrcA_X0(int num)
1221{ 1011{
1222 const unsigned int n = (unsigned int)num; 1012 const unsigned int n = (unsigned int)num;
1223 return ((n & 0x3f) << 6); 1013 return ((n & 0x3f) << 6);
1224} 1014}
1225 1015
1226static __inline tile_bundle_bits 1016static __inline tilegx_bundle_bits
1227create_SrcA_X1(int num) 1017create_SrcA_X1(int num)
1228{ 1018{
1229 const unsigned int n = (unsigned int)num; 1019 const unsigned int n = (unsigned int)num;
1230 return (((tile_bundle_bits)(n & 0x3f)) << 37); 1020 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1231} 1021}
1232 1022
1233static __inline tile_bundle_bits 1023static __inline tilegx_bundle_bits
1234create_SrcA_Y0(int num) 1024create_SrcA_Y0(int num)
1235{ 1025{
1236 const unsigned int n = (unsigned int)num; 1026 const unsigned int n = (unsigned int)num;
1237 return ((n & 0x3f) << 6); 1027 return ((n & 0x3f) << 6);
1238} 1028}
1239 1029
1240static __inline tile_bundle_bits 1030static __inline tilegx_bundle_bits
1241create_SrcA_Y1(int num) 1031create_SrcA_Y1(int num)
1242{ 1032{
1243 const unsigned int n = (unsigned int)num; 1033 const unsigned int n = (unsigned int)num;
1244 return (((tile_bundle_bits)(n & 0x3f)) << 37); 1034 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1245} 1035}
1246 1036
1247static __inline tile_bundle_bits 1037static __inline tilegx_bundle_bits
1248create_SrcA_Y2(int num) 1038create_SrcA_Y2(int num)
1249{ 1039{
1250 const unsigned int n = (unsigned int)num; 1040 const unsigned int n = (unsigned int)num;
1251 return ((n & 0x00000001) << 26) | 1041 return ((n & 0x3f) << 20);
1252 (((tile_bundle_bits)(n & 0x0000003e)) << 50);
1253} 1042}
1254 1043
1255static __inline tile_bundle_bits 1044static __inline tilegx_bundle_bits
1256create_SrcBDest_Y2(int num) 1045create_SrcBDest_Y2(int num)
1257{ 1046{
1258 const unsigned int n = (unsigned int)num; 1047 const unsigned int n = (unsigned int)num;
1259 return ((n & 0x3f) << 20); 1048 return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
1260} 1049}
1261 1050
1262static __inline tile_bundle_bits 1051static __inline tilegx_bundle_bits
1263create_SrcB_X0(int num) 1052create_SrcB_X0(int num)
1264{ 1053{
1265 const unsigned int n = (unsigned int)num; 1054 const unsigned int n = (unsigned int)num;
1266 return ((n & 0x3f) << 12); 1055 return ((n & 0x3f) << 12);
1267} 1056}
1268 1057
1269static __inline tile_bundle_bits 1058static __inline tilegx_bundle_bits
1270create_SrcB_X1(int num) 1059create_SrcB_X1(int num)
1271{ 1060{
1272 const unsigned int n = (unsigned int)num; 1061 const unsigned int n = (unsigned int)num;
1273 return (((tile_bundle_bits)(n & 0x3f)) << 43); 1062 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1274} 1063}
1275 1064
1276static __inline tile_bundle_bits 1065static __inline tilegx_bundle_bits
1277create_SrcB_Y0(int num) 1066create_SrcB_Y0(int num)
1278{ 1067{
1279 const unsigned int n = (unsigned int)num; 1068 const unsigned int n = (unsigned int)num;
1280 return ((n & 0x3f) << 12); 1069 return ((n & 0x3f) << 12);
1281} 1070}
1282 1071
1283static __inline tile_bundle_bits 1072static __inline tilegx_bundle_bits
1284create_SrcB_Y1(int num) 1073create_SrcB_Y1(int num)
1285{ 1074{
1286 const unsigned int n = (unsigned int)num; 1075 const unsigned int n = (unsigned int)num;
1287 return (((tile_bundle_bits)(n & 0x3f)) << 43); 1076 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1288} 1077}
1289 1078
1290static __inline tile_bundle_bits 1079static __inline tilegx_bundle_bits
1291create_Src_SN(int num) 1080create_UnaryOpcodeExtension_X0(int num)
1292{ 1081{
1293 const unsigned int n = (unsigned int)num; 1082 const unsigned int n = (unsigned int)num;
1294 return ((n & 0x3) << 0); 1083 return ((n & 0x3f) << 12);
1295}
1296
1297static __inline tile_bundle_bits
1298create_UnOpcodeExtension_X0(int num)
1299{
1300 const unsigned int n = (unsigned int)num;
1301 return ((n & 0x1f) << 12);
1302}
1303
1304static __inline tile_bundle_bits
1305create_UnOpcodeExtension_X1(int num)
1306{
1307 const unsigned int n = (unsigned int)num;
1308 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1309}
1310
1311static __inline tile_bundle_bits
1312create_UnOpcodeExtension_Y0(int num)
1313{
1314 const unsigned int n = (unsigned int)num;
1315 return ((n & 0x1f) << 12);
1316}
1317
1318static __inline tile_bundle_bits
1319create_UnOpcodeExtension_Y1(int num)
1320{
1321 const unsigned int n = (unsigned int)num;
1322 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1323}
1324
1325static __inline tile_bundle_bits
1326create_UnShOpcodeExtension_X0(int num)
1327{
1328 const unsigned int n = (unsigned int)num;
1329 return ((n & 0x3ff) << 17);
1330} 1084}
1331 1085
1332static __inline tile_bundle_bits 1086static __inline tilegx_bundle_bits
1333create_UnShOpcodeExtension_X1(int num) 1087create_UnaryOpcodeExtension_X1(int num)
1334{ 1088{
1335 const unsigned int n = (unsigned int)num; 1089 const unsigned int n = (unsigned int)num;
1336 return (((tile_bundle_bits)(n & 0x3ff)) << 48); 1090 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1337} 1091}
1338 1092
1339static __inline tile_bundle_bits 1093static __inline tilegx_bundle_bits
1340create_UnShOpcodeExtension_Y0(int num) 1094create_UnaryOpcodeExtension_Y0(int num)
1341{ 1095{
1342 const unsigned int n = (unsigned int)num; 1096 const unsigned int n = (unsigned int)num;
1343 return ((n & 0x7) << 17); 1097 return ((n & 0x3f) << 12);
1344} 1098}
1345 1099
1346static __inline tile_bundle_bits 1100static __inline tilegx_bundle_bits
1347create_UnShOpcodeExtension_Y1(int num) 1101create_UnaryOpcodeExtension_Y1(int num)
1348{ 1102{
1349 const unsigned int n = (unsigned int)num; 1103 const unsigned int n = (unsigned int)num;
1350 return (((tile_bundle_bits)(n & 0x7)) << 48); 1104 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1351} 1105}
1352 1106
1353 1107
1354
1355typedef enum 1108typedef enum
1356{ 1109{
1357 TILE_PIPELINE_X0, 1110 TILEGX_PIPELINE_X0,
1358 TILE_PIPELINE_X1, 1111 TILEGX_PIPELINE_X1,
1359 TILE_PIPELINE_Y0, 1112 TILEGX_PIPELINE_Y0,
1360 TILE_PIPELINE_Y1, 1113 TILEGX_PIPELINE_Y1,
1361 TILE_PIPELINE_Y2, 1114 TILEGX_PIPELINE_Y2,
1362} tile_pipeline; 1115} tilegx_pipeline;
1363 1116
1364#define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1) 1117#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
1365 1118
1366typedef enum 1119typedef enum
1367{ 1120{
1368 TILE_OP_TYPE_REGISTER, 1121 TILEGX_OP_TYPE_REGISTER,
1369 TILE_OP_TYPE_IMMEDIATE, 1122 TILEGX_OP_TYPE_IMMEDIATE,
1370 TILE_OP_TYPE_ADDRESS, 1123 TILEGX_OP_TYPE_ADDRESS,
1371 TILE_OP_TYPE_SPR 1124 TILEGX_OP_TYPE_SPR
1372} tile_operand_type; 1125} tilegx_operand_type;
1373 1126
1374/* This is the bit that determines if a bundle is in the Y encoding. */ 1127/* These are the bits that determine if a bundle is in the X encoding. */
1375#define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63) 1128#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
1376 1129
1377enum 1130enum
1378{ 1131{
1379 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ 1132 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1380 TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3, 1133 TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1381 1134
1382 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ 1135 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
1383 TILE_NUM_PIPELINE_ENCODINGS = 5, 1136 TILEGX_NUM_PIPELINE_ENCODINGS = 5,
1384 1137
1385 /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */ 1138 /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
1386 TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3, 1139 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1387 1140
1388 /* Instructions take this many bytes. */ 1141 /* Instructions take this many bytes. */
1389 TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES, 1142 TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
1390 1143
1391 /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */ 1144 /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
1392 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, 1145 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
1393 1146
1394 /* Bundles should be aligned modulo this number of bytes. */ 1147 /* Bundles should be aligned modulo this number of bytes. */
1395 TILE_BUNDLE_ALIGNMENT_IN_BYTES = 1148 TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
1396 (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), 1149 (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
1397
1398 /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */
1399 TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
1400
1401 /* Static network instructions take this many bytes. */
1402 TILE_SN_INSTRUCTION_SIZE_IN_BYTES =
1403 (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
1404 1150
1405 /* Number of registers (some are magic, such as network I/O). */ 1151 /* Number of registers (some are magic, such as network I/O). */
1406 TILE_NUM_REGISTERS = 64, 1152 TILEGX_NUM_REGISTERS = 64,
1407
1408 /* Number of static network registers. */
1409 TILE_NUM_SN_REGISTERS = 4
1410}; 1153};
1411 1154
1412 1155
1413struct tile_operand 1156struct tilegx_operand
1414{ 1157{
1415 /* Is this operand a register, immediate or address? */ 1158 /* Is this operand a register, immediate or address? */
1416 tile_operand_type type; 1159 tilegx_operand_type type;
1417 1160
1418 /* The default relocation type for this operand. */ 1161 /* The default relocation type for this operand. */
1419 signed int default_reloc : 16; 1162 signed int default_reloc : 16;
@@ -1437,27 +1180,27 @@ struct tile_operand
1437 unsigned int rightshift : 2; 1180 unsigned int rightshift : 2;
1438 1181
1439 /* Return the bits for this operand to be ORed into an existing bundle. */ 1182 /* Return the bits for this operand to be ORed into an existing bundle. */
1440 tile_bundle_bits (*insert) (int op); 1183 tilegx_bundle_bits (*insert) (int op);
1441 1184
1442 /* Extract this operand and return it. */ 1185 /* Extract this operand and return it. */
1443 unsigned int (*extract) (tile_bundle_bits bundle); 1186 unsigned int (*extract) (tilegx_bundle_bits bundle);
1444}; 1187};
1445 1188
1446 1189
1447extern const struct tile_operand tile_operands[]; 1190extern const struct tilegx_operand tilegx_operands[];
1448 1191
1449/* One finite-state machine per pipe for rapid instruction decoding. */ 1192/* One finite-state machine per pipe for rapid instruction decoding. */
1450extern const unsigned short * const 1193extern const unsigned short * const
1451tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS]; 1194tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
1452 1195
1453 1196
1454struct tile_opcode 1197struct tilegx_opcode
1455{ 1198{
1456 /* The opcode mnemonic, e.g. "add" */ 1199 /* The opcode mnemonic, e.g. "add" */
1457 const char *name; 1200 const char *name;
1458 1201
1459 /* The enum value for this mnemonic. */ 1202 /* The enum value for this mnemonic. */
1460 tile_mnemonic mnemonic; 1203 tilegx_mnemonic mnemonic;
1461 1204
1462 /* A bit mask of which of the five pipes this instruction 1205 /* A bit mask of which of the five pipes this instruction
1463 is compatible with: 1206 is compatible with:
@@ -1478,29 +1221,28 @@ struct tile_opcode
1478 unsigned char can_bundle; 1221 unsigned char can_bundle;
1479 1222
1480 /* The description of the operands. Each of these is an 1223 /* The description of the operands. Each of these is an
1481 * index into the tile_operands[] table. */ 1224 * index into the tilegx_operands[] table. */
1482 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS]; 1225 unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
1483 1226
1484}; 1227};
1485 1228
1486extern const struct tile_opcode tile_opcodes[]; 1229extern const struct tilegx_opcode tilegx_opcodes[];
1487
1488 1230
1489/* Used for non-textual disassembly into structs. */ 1231/* Used for non-textual disassembly into structs. */
1490struct tile_decoded_instruction 1232struct tilegx_decoded_instruction
1491{ 1233{
1492 const struct tile_opcode *opcode; 1234 const struct tilegx_opcode *opcode;
1493 const struct tile_operand *operands[TILE_MAX_OPERANDS]; 1235 const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
1494 int operand_values[TILE_MAX_OPERANDS]; 1236 long long operand_values[TILEGX_MAX_OPERANDS];
1495}; 1237};
1496 1238
1497 1239
1498/* Disassemble a bundle into a struct for machine processing. */ 1240/* Disassemble a bundle into a struct for machine processing. */
1499extern int parse_insn_tile(tile_bundle_bits bits, 1241extern int parse_insn_tilegx(tilegx_bundle_bits bits,
1500 unsigned int pc, 1242 unsigned long long pc,
1501 struct tile_decoded_instruction 1243 struct tilegx_decoded_instruction
1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1244 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
1503 1245
1504 1246
1505 1247
1506#endif /* opcode_tile_h */ 1248#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/asm/opcode_constants_64.h
index 227d033b180c..710192869476 100644
--- a/arch/tile/include/asm/opcode_constants_64.h
+++ b/arch/tile/include/asm/opcode_constants_64.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -19,462 +19,591 @@
19#define _TILE_OPCODE_CONSTANTS_H 19#define _TILE_OPCODE_CONSTANTS_H
20enum 20enum
21{ 21{
22 ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, 22 ADDI_IMM8_OPCODE_X0 = 1,
23 ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, 23 ADDI_IMM8_OPCODE_X1 = 1,
24 ADDB_SPECIAL_0_OPCODE_X0 = 1, 24 ADDI_OPCODE_Y0 = 0,
25 ADDB_SPECIAL_0_OPCODE_X1 = 1, 25 ADDI_OPCODE_Y1 = 1,
26 ADDHS_SPECIAL_0_OPCODE_X0 = 99, 26 ADDLI_OPCODE_X0 = 1,
27 ADDHS_SPECIAL_0_OPCODE_X1 = 69, 27 ADDLI_OPCODE_X1 = 0,
28 ADDH_SPECIAL_0_OPCODE_X0 = 2, 28 ADDXI_IMM8_OPCODE_X0 = 2,
29 ADDH_SPECIAL_0_OPCODE_X1 = 2, 29 ADDXI_IMM8_OPCODE_X1 = 2,
30 ADDIB_IMM_0_OPCODE_X0 = 1, 30 ADDXI_OPCODE_Y0 = 1,
31 ADDIB_IMM_0_OPCODE_X1 = 1, 31 ADDXI_OPCODE_Y1 = 2,
32 ADDIH_IMM_0_OPCODE_X0 = 2, 32 ADDXLI_OPCODE_X0 = 2,
33 ADDIH_IMM_0_OPCODE_X1 = 2, 33 ADDXLI_OPCODE_X1 = 1,
34 ADDI_IMM_0_OPCODE_X0 = 3, 34 ADDXSC_RRR_0_OPCODE_X0 = 1,
35 ADDI_IMM_0_OPCODE_X1 = 3, 35 ADDXSC_RRR_0_OPCODE_X1 = 1,
36 ADDI_IMM_1_OPCODE_SN = 1, 36 ADDX_RRR_0_OPCODE_X0 = 2,
37 ADDI_OPCODE_Y0 = 9, 37 ADDX_RRR_0_OPCODE_X1 = 2,
38 ADDI_OPCODE_Y1 = 7, 38 ADDX_RRR_0_OPCODE_Y0 = 0,
39 ADDLIS_OPCODE_X0 = 1, 39 ADDX_SPECIAL_0_OPCODE_Y1 = 0,
40 ADDLIS_OPCODE_X1 = 2, 40 ADD_RRR_0_OPCODE_X0 = 3,
41 ADDLI_OPCODE_X0 = 2, 41 ADD_RRR_0_OPCODE_X1 = 3,
42 ADDLI_OPCODE_X1 = 3, 42 ADD_RRR_0_OPCODE_Y0 = 1,
43 ADDS_SPECIAL_0_OPCODE_X0 = 96, 43 ADD_SPECIAL_0_OPCODE_Y1 = 1,
44 ADDS_SPECIAL_0_OPCODE_X1 = 66, 44 ANDI_IMM8_OPCODE_X0 = 3,
45 ADD_SPECIAL_0_OPCODE_X0 = 3, 45 ANDI_IMM8_OPCODE_X1 = 3,
46 ADD_SPECIAL_0_OPCODE_X1 = 3, 46 ANDI_OPCODE_Y0 = 2,
47 ADD_SPECIAL_0_OPCODE_Y0 = 0, 47 ANDI_OPCODE_Y1 = 3,
48 ADD_SPECIAL_0_OPCODE_Y1 = 0, 48 AND_RRR_0_OPCODE_X0 = 4,
49 ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, 49 AND_RRR_0_OPCODE_X1 = 4,
50 ADIFFH_SPECIAL_0_OPCODE_X0 = 5, 50 AND_RRR_5_OPCODE_Y0 = 0,
51 ANDI_IMM_0_OPCODE_X0 = 1, 51 AND_RRR_5_OPCODE_Y1 = 0,
52 ANDI_IMM_0_OPCODE_X1 = 4, 52 BEQZT_BRANCH_OPCODE_X1 = 16,
53 ANDI_OPCODE_Y0 = 10, 53 BEQZ_BRANCH_OPCODE_X1 = 17,
54 ANDI_OPCODE_Y1 = 8, 54 BFEXTS_BF_OPCODE_X0 = 4,
55 AND_SPECIAL_0_OPCODE_X0 = 6, 55 BFEXTU_BF_OPCODE_X0 = 5,
56 AND_SPECIAL_0_OPCODE_X1 = 4, 56 BFINS_BF_OPCODE_X0 = 6,
57 AND_SPECIAL_2_OPCODE_Y0 = 0, 57 BF_OPCODE_X0 = 3,
58 AND_SPECIAL_2_OPCODE_Y1 = 0, 58 BGEZT_BRANCH_OPCODE_X1 = 18,
59 AULI_OPCODE_X0 = 3, 59 BGEZ_BRANCH_OPCODE_X1 = 19,
60 AULI_OPCODE_X1 = 4, 60 BGTZT_BRANCH_OPCODE_X1 = 20,
61 AVGB_U_SPECIAL_0_OPCODE_X0 = 7, 61 BGTZ_BRANCH_OPCODE_X1 = 21,
62 AVGH_SPECIAL_0_OPCODE_X0 = 8, 62 BLBCT_BRANCH_OPCODE_X1 = 22,
63 BBNST_BRANCH_OPCODE_X1 = 15, 63 BLBC_BRANCH_OPCODE_X1 = 23,
64 BBNS_BRANCH_OPCODE_X1 = 14, 64 BLBST_BRANCH_OPCODE_X1 = 24,
65 BBNS_OPCODE_SN = 63, 65 BLBS_BRANCH_OPCODE_X1 = 25,
66 BBST_BRANCH_OPCODE_X1 = 13, 66 BLEZT_BRANCH_OPCODE_X1 = 26,
67 BBS_BRANCH_OPCODE_X1 = 12, 67 BLEZ_BRANCH_OPCODE_X1 = 27,
68 BBS_OPCODE_SN = 62, 68 BLTZT_BRANCH_OPCODE_X1 = 28,
69 BGEZT_BRANCH_OPCODE_X1 = 7, 69 BLTZ_BRANCH_OPCODE_X1 = 29,
70 BGEZ_BRANCH_OPCODE_X1 = 6, 70 BNEZT_BRANCH_OPCODE_X1 = 30,
71 BGEZ_OPCODE_SN = 61, 71 BNEZ_BRANCH_OPCODE_X1 = 31,
72 BGZT_BRANCH_OPCODE_X1 = 5, 72 BRANCH_OPCODE_X1 = 2,
73 BGZ_BRANCH_OPCODE_X1 = 4, 73 CMOVEQZ_RRR_0_OPCODE_X0 = 5,
74 BGZ_OPCODE_SN = 58, 74 CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
75 BITX_UN_0_SHUN_0_OPCODE_X0 = 1, 75 CMOVNEZ_RRR_0_OPCODE_X0 = 6,
76 BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, 76 CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
77 BLEZT_BRANCH_OPCODE_X1 = 11, 77 CMPEQI_IMM8_OPCODE_X0 = 4,
78 BLEZ_BRANCH_OPCODE_X1 = 10, 78 CMPEQI_IMM8_OPCODE_X1 = 4,
79 BLEZ_OPCODE_SN = 59, 79 CMPEQI_OPCODE_Y0 = 3,
80 BLZT_BRANCH_OPCODE_X1 = 9, 80 CMPEQI_OPCODE_Y1 = 4,
81 BLZ_BRANCH_OPCODE_X1 = 8, 81 CMPEQ_RRR_0_OPCODE_X0 = 7,
82 BLZ_OPCODE_SN = 60, 82 CMPEQ_RRR_0_OPCODE_X1 = 5,
83 BNZT_BRANCH_OPCODE_X1 = 3, 83 CMPEQ_RRR_3_OPCODE_Y0 = 0,
84 BNZ_BRANCH_OPCODE_X1 = 2, 84 CMPEQ_RRR_3_OPCODE_Y1 = 2,
85 BNZ_OPCODE_SN = 57, 85 CMPEXCH4_RRR_0_OPCODE_X1 = 6,
86 BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, 86 CMPEXCH_RRR_0_OPCODE_X1 = 7,
87 BRANCH_OPCODE_X1 = 5, 87 CMPLES_RRR_0_OPCODE_X0 = 8,
88 BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, 88 CMPLES_RRR_0_OPCODE_X1 = 8,
89 BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, 89 CMPLES_RRR_2_OPCODE_Y0 = 0,
90 BZT_BRANCH_OPCODE_X1 = 1, 90 CMPLES_RRR_2_OPCODE_Y1 = 0,
91 BZ_BRANCH_OPCODE_X1 = 0, 91 CMPLEU_RRR_0_OPCODE_X0 = 9,
92 BZ_OPCODE_SN = 56, 92 CMPLEU_RRR_0_OPCODE_X1 = 9,
93 CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, 93 CMPLEU_RRR_2_OPCODE_Y0 = 1,
94 CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, 94 CMPLEU_RRR_2_OPCODE_Y1 = 1,
95 CRC32_32_SPECIAL_0_OPCODE_X0 = 9, 95 CMPLTSI_IMM8_OPCODE_X0 = 5,
96 CRC32_8_SPECIAL_0_OPCODE_X0 = 10, 96 CMPLTSI_IMM8_OPCODE_X1 = 5,
97 CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, 97 CMPLTSI_OPCODE_Y0 = 4,
98 CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, 98 CMPLTSI_OPCODE_Y1 = 5,
99 DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, 99 CMPLTS_RRR_0_OPCODE_X0 = 10,
100 DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, 100 CMPLTS_RRR_0_OPCODE_X1 = 10,
101 DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, 101 CMPLTS_RRR_2_OPCODE_Y0 = 2,
102 FINV_UN_0_SHUN_0_OPCODE_X1 = 3, 102 CMPLTS_RRR_2_OPCODE_Y1 = 2,
103 FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, 103 CMPLTUI_IMM8_OPCODE_X0 = 6,
104 FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, 104 CMPLTUI_IMM8_OPCODE_X1 = 6,
105 FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, 105 CMPLTU_RRR_0_OPCODE_X0 = 11,
106 FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, 106 CMPLTU_RRR_0_OPCODE_X1 = 11,
107 FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, 107 CMPLTU_RRR_2_OPCODE_Y0 = 3,
108 FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, 108 CMPLTU_RRR_2_OPCODE_Y1 = 3,
109 HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, 109 CMPNE_RRR_0_OPCODE_X0 = 12,
110 ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, 110 CMPNE_RRR_0_OPCODE_X1 = 12,
111 ILL_UN_0_SHUN_0_OPCODE_X1 = 7, 111 CMPNE_RRR_3_OPCODE_Y0 = 1,
112 ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, 112 CMPNE_RRR_3_OPCODE_Y1 = 3,
113 IMM_0_OPCODE_SN = 0, 113 CMULAF_RRR_0_OPCODE_X0 = 13,
114 IMM_0_OPCODE_X0 = 4, 114 CMULA_RRR_0_OPCODE_X0 = 14,
115 IMM_0_OPCODE_X1 = 6, 115 CMULFR_RRR_0_OPCODE_X0 = 15,
116 IMM_1_OPCODE_SN = 1, 116 CMULF_RRR_0_OPCODE_X0 = 16,
117 IMM_OPCODE_0_X0 = 5, 117 CMULHR_RRR_0_OPCODE_X0 = 17,
118 INTHB_SPECIAL_0_OPCODE_X0 = 11, 118 CMULH_RRR_0_OPCODE_X0 = 18,
119 INTHB_SPECIAL_0_OPCODE_X1 = 5, 119 CMUL_RRR_0_OPCODE_X0 = 19,
120 INTHH_SPECIAL_0_OPCODE_X0 = 12, 120 CNTLZ_UNARY_OPCODE_X0 = 1,
121 INTHH_SPECIAL_0_OPCODE_X1 = 6, 121 CNTLZ_UNARY_OPCODE_Y0 = 1,
122 INTLB_SPECIAL_0_OPCODE_X0 = 13, 122 CNTTZ_UNARY_OPCODE_X0 = 2,
123 INTLB_SPECIAL_0_OPCODE_X1 = 7, 123 CNTTZ_UNARY_OPCODE_Y0 = 2,
124 INTLH_SPECIAL_0_OPCODE_X0 = 14, 124 CRC32_32_RRR_0_OPCODE_X0 = 20,
125 INTLH_SPECIAL_0_OPCODE_X1 = 8, 125 CRC32_8_RRR_0_OPCODE_X0 = 21,
126 INV_UN_0_SHUN_0_OPCODE_X1 = 8, 126 DBLALIGN2_RRR_0_OPCODE_X0 = 22,
127 IRET_UN_0_SHUN_0_OPCODE_X1 = 9, 127 DBLALIGN2_RRR_0_OPCODE_X1 = 13,
128 JALB_OPCODE_X1 = 13, 128 DBLALIGN4_RRR_0_OPCODE_X0 = 23,
129 JALF_OPCODE_X1 = 12, 129 DBLALIGN4_RRR_0_OPCODE_X1 = 14,
130 JALRP_SPECIAL_0_OPCODE_X1 = 9, 130 DBLALIGN6_RRR_0_OPCODE_X0 = 24,
131 JALRR_IMM_1_OPCODE_SN = 3, 131 DBLALIGN6_RRR_0_OPCODE_X1 = 15,
132 JALR_RR_IMM_0_OPCODE_SN = 5, 132 DBLALIGN_RRR_0_OPCODE_X0 = 25,
133 JALR_SPECIAL_0_OPCODE_X1 = 10, 133 DRAIN_UNARY_OPCODE_X1 = 1,
134 JB_OPCODE_X1 = 11, 134 DTLBPR_UNARY_OPCODE_X1 = 2,
135 JF_OPCODE_X1 = 10, 135 EXCH4_RRR_0_OPCODE_X1 = 16,
136 JRP_SPECIAL_0_OPCODE_X1 = 11, 136 EXCH_RRR_0_OPCODE_X1 = 17,
137 JRR_IMM_1_OPCODE_SN = 2, 137 FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
138 JR_RR_IMM_0_OPCODE_SN = 4, 138 FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
139 JR_SPECIAL_0_OPCODE_X1 = 12, 139 FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
140 LBADD_IMM_0_OPCODE_X1 = 22, 140 FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
141 LBADD_U_IMM_0_OPCODE_X1 = 23, 141 FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
142 LB_OPCODE_Y2 = 0, 142 FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
143 LB_UN_0_SHUN_0_OPCODE_X1 = 10, 143 FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
144 LB_U_OPCODE_Y2 = 1, 144 FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
145 LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, 145 FETCHADD4_RRR_0_OPCODE_X1 = 18,
146 LHADD_IMM_0_OPCODE_X1 = 24, 146 FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
147 LHADD_U_IMM_0_OPCODE_X1 = 25, 147 FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
148 LH_OPCODE_Y2 = 2, 148 FETCHADD_RRR_0_OPCODE_X1 = 21,
149 LH_UN_0_SHUN_0_OPCODE_X1 = 12, 149 FETCHAND4_RRR_0_OPCODE_X1 = 22,
150 LH_U_OPCODE_Y2 = 3, 150 FETCHAND_RRR_0_OPCODE_X1 = 23,
151 LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, 151 FETCHOR4_RRR_0_OPCODE_X1 = 24,
152 LNK_SPECIAL_0_OPCODE_X1 = 13, 152 FETCHOR_RRR_0_OPCODE_X1 = 25,
153 LWADD_IMM_0_OPCODE_X1 = 26, 153 FINV_UNARY_OPCODE_X1 = 3,
154 LWADD_NA_IMM_0_OPCODE_X1 = 27, 154 FLUSHWB_UNARY_OPCODE_X1 = 4,
155 LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, 155 FLUSH_UNARY_OPCODE_X1 = 5,
156 LW_OPCODE_Y2 = 4, 156 FNOP_UNARY_OPCODE_X0 = 3,
157 LW_UN_0_SHUN_0_OPCODE_X1 = 14, 157 FNOP_UNARY_OPCODE_X1 = 6,
158 MAXB_U_SPECIAL_0_OPCODE_X0 = 15, 158 FNOP_UNARY_OPCODE_Y0 = 3,
159 MAXB_U_SPECIAL_0_OPCODE_X1 = 14, 159 FNOP_UNARY_OPCODE_Y1 = 8,
160 MAXH_SPECIAL_0_OPCODE_X0 = 16, 160 FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
161 MAXH_SPECIAL_0_OPCODE_X1 = 15, 161 FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
162 MAXIB_U_IMM_0_OPCODE_X0 = 4, 162 FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
163 MAXIB_U_IMM_0_OPCODE_X1 = 5, 163 FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
164 MAXIH_IMM_0_OPCODE_X0 = 5, 164 FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
165 MAXIH_IMM_0_OPCODE_X1 = 6, 165 FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
166 MFSPR_IMM_0_OPCODE_X1 = 7, 166 FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
167 MF_UN_0_SHUN_0_OPCODE_X1 = 15, 167 FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
168 MINB_U_SPECIAL_0_OPCODE_X0 = 17, 168 ICOH_UNARY_OPCODE_X1 = 7,
169 MINB_U_SPECIAL_0_OPCODE_X1 = 16, 169 ILL_UNARY_OPCODE_X1 = 8,
170 MINH_SPECIAL_0_OPCODE_X0 = 18, 170 ILL_UNARY_OPCODE_Y1 = 9,
171 MINH_SPECIAL_0_OPCODE_X1 = 17, 171 IMM8_OPCODE_X0 = 4,
172 MINIB_U_IMM_0_OPCODE_X0 = 6, 172 IMM8_OPCODE_X1 = 3,
173 MINIB_U_IMM_0_OPCODE_X1 = 8, 173 INV_UNARY_OPCODE_X1 = 9,
174 MINIH_IMM_0_OPCODE_X0 = 7, 174 IRET_UNARY_OPCODE_X1 = 10,
175 MINIH_IMM_0_OPCODE_X1 = 9, 175 JALRP_UNARY_OPCODE_X1 = 11,
176 MM_OPCODE_X0 = 6, 176 JALRP_UNARY_OPCODE_Y1 = 10,
177 MM_OPCODE_X1 = 7, 177 JALR_UNARY_OPCODE_X1 = 12,
178 MNZB_SPECIAL_0_OPCODE_X0 = 19, 178 JALR_UNARY_OPCODE_Y1 = 11,
179 MNZB_SPECIAL_0_OPCODE_X1 = 18, 179 JAL_JUMP_OPCODE_X1 = 0,
180 MNZH_SPECIAL_0_OPCODE_X0 = 20, 180 JRP_UNARY_OPCODE_X1 = 13,
181 MNZH_SPECIAL_0_OPCODE_X1 = 19, 181 JRP_UNARY_OPCODE_Y1 = 12,
182 MNZ_SPECIAL_0_OPCODE_X0 = 21, 182 JR_UNARY_OPCODE_X1 = 14,
183 MNZ_SPECIAL_0_OPCODE_X1 = 20, 183 JR_UNARY_OPCODE_Y1 = 13,
184 MNZ_SPECIAL_1_OPCODE_Y0 = 0, 184 JUMP_OPCODE_X1 = 4,
185 MNZ_SPECIAL_1_OPCODE_Y1 = 1, 185 J_JUMP_OPCODE_X1 = 1,
186 MOVEI_IMM_1_OPCODE_SN = 0, 186 LD1S_ADD_IMM8_OPCODE_X1 = 7,
187 MOVE_RR_IMM_0_OPCODE_SN = 8, 187 LD1S_OPCODE_Y2 = 0,
188 MTSPR_IMM_0_OPCODE_X1 = 10, 188 LD1S_UNARY_OPCODE_X1 = 15,
189 MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, 189 LD1U_ADD_IMM8_OPCODE_X1 = 8,
190 MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, 190 LD1U_OPCODE_Y2 = 1,
191 MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, 191 LD1U_UNARY_OPCODE_X1 = 16,
192 MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, 192 LD2S_ADD_IMM8_OPCODE_X1 = 9,
193 MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, 193 LD2S_OPCODE_Y2 = 2,
194 MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, 194 LD2S_UNARY_OPCODE_X1 = 17,
195 MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, 195 LD2U_ADD_IMM8_OPCODE_X1 = 10,
196 MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, 196 LD2U_OPCODE_Y2 = 3,
197 MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, 197 LD2U_UNARY_OPCODE_X1 = 18,
198 MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, 198 LD4S_ADD_IMM8_OPCODE_X1 = 11,
199 MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, 199 LD4S_OPCODE_Y2 = 1,
200 MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, 200 LD4S_UNARY_OPCODE_X1 = 19,
201 MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, 201 LD4U_ADD_IMM8_OPCODE_X1 = 12,
202 MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, 202 LD4U_OPCODE_Y2 = 2,
203 MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, 203 LD4U_UNARY_OPCODE_X1 = 20,
204 MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, 204 LDNA_UNARY_OPCODE_X1 = 21,
205 MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, 205 LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
206 MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, 206 LDNT1S_UNARY_OPCODE_X1 = 22,
207 MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, 207 LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
208 MULHL_US_SPECIAL_0_OPCODE_X0 = 36, 208 LDNT1U_UNARY_OPCODE_X1 = 23,
209 MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, 209 LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
210 MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, 210 LDNT2S_UNARY_OPCODE_X1 = 24,
211 MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, 211 LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
212 MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, 212 LDNT2U_UNARY_OPCODE_X1 = 25,
213 MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, 213 LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
214 MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, 214 LDNT4S_UNARY_OPCODE_X1 = 26,
215 MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, 215 LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
216 MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, 216 LDNT4U_UNARY_OPCODE_X1 = 27,
217 MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, 217 LDNT_ADD_IMM8_OPCODE_X1 = 19,
218 MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, 218 LDNT_UNARY_OPCODE_X1 = 28,
219 MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, 219 LD_ADD_IMM8_OPCODE_X1 = 20,
220 MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, 220 LD_OPCODE_Y2 = 3,
221 MVNZ_SPECIAL_0_OPCODE_X0 = 45, 221 LD_UNARY_OPCODE_X1 = 29,
222 MVNZ_SPECIAL_1_OPCODE_Y0 = 1, 222 LNK_UNARY_OPCODE_X1 = 30,
223 MVZ_SPECIAL_0_OPCODE_X0 = 46, 223 LNK_UNARY_OPCODE_Y1 = 14,
224 MVZ_SPECIAL_1_OPCODE_Y0 = 2, 224 LWNA_ADD_IMM8_OPCODE_X1 = 21,
225 MZB_SPECIAL_0_OPCODE_X0 = 47, 225 MFSPR_IMM8_OPCODE_X1 = 22,
226 MZB_SPECIAL_0_OPCODE_X1 = 21, 226 MF_UNARY_OPCODE_X1 = 31,
227 MZH_SPECIAL_0_OPCODE_X0 = 48, 227 MM_BF_OPCODE_X0 = 7,
228 MZH_SPECIAL_0_OPCODE_X1 = 22, 228 MNZ_RRR_0_OPCODE_X0 = 40,
229 MZ_SPECIAL_0_OPCODE_X0 = 49, 229 MNZ_RRR_0_OPCODE_X1 = 26,
230 MZ_SPECIAL_0_OPCODE_X1 = 23, 230 MNZ_RRR_4_OPCODE_Y0 = 2,
231 MZ_SPECIAL_1_OPCODE_Y0 = 3, 231 MNZ_RRR_4_OPCODE_Y1 = 2,
232 MZ_SPECIAL_1_OPCODE_Y1 = 2, 232 MODE_OPCODE_YA2 = 1,
233 NAP_UN_0_SHUN_0_OPCODE_X1 = 16, 233 MODE_OPCODE_YB2 = 2,
234 NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, 234 MODE_OPCODE_YC2 = 3,
235 NOP_UN_0_SHUN_0_OPCODE_X0 = 6, 235 MTSPR_IMM8_OPCODE_X1 = 23,
236 NOP_UN_0_SHUN_0_OPCODE_X1 = 17, 236 MULAX_RRR_0_OPCODE_X0 = 41,
237 NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, 237 MULAX_RRR_3_OPCODE_Y0 = 2,
238 NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, 238 MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
239 NOREG_RR_IMM_0_OPCODE_SN = 0, 239 MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
240 NOR_SPECIAL_0_OPCODE_X0 = 50, 240 MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
241 NOR_SPECIAL_0_OPCODE_X1 = 24, 241 MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
242 NOR_SPECIAL_2_OPCODE_Y0 = 1, 242 MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
243 NOR_SPECIAL_2_OPCODE_Y1 = 1, 243 MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
244 ORI_IMM_0_OPCODE_X0 = 8, 244 MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
245 ORI_IMM_0_OPCODE_X1 = 11, 245 MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
246 ORI_OPCODE_Y0 = 11, 246 MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
247 ORI_OPCODE_Y1 = 9, 247 MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
248 OR_SPECIAL_0_OPCODE_X0 = 51, 248 MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
249 OR_SPECIAL_0_OPCODE_X1 = 25, 249 MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
250 OR_SPECIAL_2_OPCODE_Y0 = 2, 250 MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
251 OR_SPECIAL_2_OPCODE_Y1 = 2, 251 MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
252 PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, 252 MULX_RRR_0_OPCODE_X0 = 52,
253 PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, 253 MULX_RRR_3_OPCODE_Y0 = 3,
254 PACKHB_SPECIAL_0_OPCODE_X0 = 52, 254 MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
255 PACKHB_SPECIAL_0_OPCODE_X1 = 26, 255 MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
256 PACKHS_SPECIAL_0_OPCODE_X0 = 102, 256 MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
257 PACKHS_SPECIAL_0_OPCODE_X1 = 72, 257 MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
258 PACKLB_SPECIAL_0_OPCODE_X0 = 53, 258 MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
259 PACKLB_SPECIAL_0_OPCODE_X1 = 27, 259 MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
260 PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, 260 MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
261 PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, 261 MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
262 RLI_SHUN_0_OPCODE_X0 = 1, 262 MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
263 RLI_SHUN_0_OPCODE_X1 = 1, 263 MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
264 RLI_SHUN_0_OPCODE_Y0 = 1, 264 MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
265 RLI_SHUN_0_OPCODE_Y1 = 1, 265 MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
266 RL_SPECIAL_0_OPCODE_X0 = 54, 266 MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
267 RL_SPECIAL_0_OPCODE_X1 = 28, 267 MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
268 RL_SPECIAL_3_OPCODE_Y0 = 0, 268 MZ_RRR_0_OPCODE_X0 = 63,
269 RL_SPECIAL_3_OPCODE_Y1 = 0, 269 MZ_RRR_0_OPCODE_X1 = 27,
270 RR_IMM_0_OPCODE_SN = 0, 270 MZ_RRR_4_OPCODE_Y0 = 3,
271 S1A_SPECIAL_0_OPCODE_X0 = 55, 271 MZ_RRR_4_OPCODE_Y1 = 3,
272 S1A_SPECIAL_0_OPCODE_X1 = 29, 272 NAP_UNARY_OPCODE_X1 = 32,
273 S1A_SPECIAL_0_OPCODE_Y0 = 1, 273 NOP_UNARY_OPCODE_X0 = 5,
274 S1A_SPECIAL_0_OPCODE_Y1 = 1, 274 NOP_UNARY_OPCODE_X1 = 33,
275 S2A_SPECIAL_0_OPCODE_X0 = 56, 275 NOP_UNARY_OPCODE_Y0 = 5,
276 S2A_SPECIAL_0_OPCODE_X1 = 30, 276 NOP_UNARY_OPCODE_Y1 = 15,
277 S2A_SPECIAL_0_OPCODE_Y0 = 2, 277 NOR_RRR_0_OPCODE_X0 = 64,
278 S2A_SPECIAL_0_OPCODE_Y1 = 2, 278 NOR_RRR_0_OPCODE_X1 = 28,
279 S3A_SPECIAL_0_OPCODE_X0 = 57, 279 NOR_RRR_5_OPCODE_Y0 = 1,
280 S3A_SPECIAL_0_OPCODE_X1 = 31, 280 NOR_RRR_5_OPCODE_Y1 = 1,
281 S3A_SPECIAL_5_OPCODE_Y0 = 1, 281 ORI_IMM8_OPCODE_X0 = 7,
282 S3A_SPECIAL_5_OPCODE_Y1 = 1, 282 ORI_IMM8_OPCODE_X1 = 24,
283 SADAB_U_SPECIAL_0_OPCODE_X0 = 58, 283 OR_RRR_0_OPCODE_X0 = 65,
284 SADAH_SPECIAL_0_OPCODE_X0 = 59, 284 OR_RRR_0_OPCODE_X1 = 29,
285 SADAH_U_SPECIAL_0_OPCODE_X0 = 60, 285 OR_RRR_5_OPCODE_Y0 = 2,
286 SADB_U_SPECIAL_0_OPCODE_X0 = 61, 286 OR_RRR_5_OPCODE_Y1 = 2,
287 SADH_SPECIAL_0_OPCODE_X0 = 62, 287 PCNT_UNARY_OPCODE_X0 = 6,
288 SADH_U_SPECIAL_0_OPCODE_X0 = 63, 288 PCNT_UNARY_OPCODE_Y0 = 6,
289 SBADD_IMM_0_OPCODE_X1 = 28, 289 REVBITS_UNARY_OPCODE_X0 = 7,
290 SB_OPCODE_Y2 = 5, 290 REVBITS_UNARY_OPCODE_Y0 = 7,
291 SB_SPECIAL_0_OPCODE_X1 = 32, 291 REVBYTES_UNARY_OPCODE_X0 = 8,
292 SEQB_SPECIAL_0_OPCODE_X0 = 64, 292 REVBYTES_UNARY_OPCODE_Y0 = 8,
293 SEQB_SPECIAL_0_OPCODE_X1 = 33, 293 ROTLI_SHIFT_OPCODE_X0 = 1,
294 SEQH_SPECIAL_0_OPCODE_X0 = 65, 294 ROTLI_SHIFT_OPCODE_X1 = 1,
295 SEQH_SPECIAL_0_OPCODE_X1 = 34, 295 ROTLI_SHIFT_OPCODE_Y0 = 0,
296 SEQIB_IMM_0_OPCODE_X0 = 9, 296 ROTLI_SHIFT_OPCODE_Y1 = 0,
297 SEQIB_IMM_0_OPCODE_X1 = 12, 297 ROTL_RRR_0_OPCODE_X0 = 66,
298 SEQIH_IMM_0_OPCODE_X0 = 10, 298 ROTL_RRR_0_OPCODE_X1 = 30,
299 SEQIH_IMM_0_OPCODE_X1 = 13, 299 ROTL_RRR_6_OPCODE_Y0 = 0,
300 SEQI_IMM_0_OPCODE_X0 = 11, 300 ROTL_RRR_6_OPCODE_Y1 = 0,
301 SEQI_IMM_0_OPCODE_X1 = 14, 301 RRR_0_OPCODE_X0 = 5,
302 SEQI_OPCODE_Y0 = 12, 302 RRR_0_OPCODE_X1 = 5,
303 SEQI_OPCODE_Y1 = 10, 303 RRR_0_OPCODE_Y0 = 5,
304 SEQ_SPECIAL_0_OPCODE_X0 = 66, 304 RRR_0_OPCODE_Y1 = 6,
305 SEQ_SPECIAL_0_OPCODE_X1 = 35, 305 RRR_1_OPCODE_Y0 = 6,
306 SEQ_SPECIAL_5_OPCODE_Y0 = 2, 306 RRR_1_OPCODE_Y1 = 7,
307 SEQ_SPECIAL_5_OPCODE_Y1 = 2, 307 RRR_2_OPCODE_Y0 = 7,
308 SHADD_IMM_0_OPCODE_X1 = 29, 308 RRR_2_OPCODE_Y1 = 8,
309 SHL8II_IMM_0_OPCODE_SN = 3, 309 RRR_3_OPCODE_Y0 = 8,
310 SHLB_SPECIAL_0_OPCODE_X0 = 67, 310 RRR_3_OPCODE_Y1 = 9,
311 SHLB_SPECIAL_0_OPCODE_X1 = 36, 311 RRR_4_OPCODE_Y0 = 9,
312 SHLH_SPECIAL_0_OPCODE_X0 = 68, 312 RRR_4_OPCODE_Y1 = 10,
313 SHLH_SPECIAL_0_OPCODE_X1 = 37, 313 RRR_5_OPCODE_Y0 = 10,
314 SHLIB_SHUN_0_OPCODE_X0 = 2, 314 RRR_5_OPCODE_Y1 = 11,
315 SHLIB_SHUN_0_OPCODE_X1 = 2, 315 RRR_6_OPCODE_Y0 = 11,
316 SHLIH_SHUN_0_OPCODE_X0 = 3, 316 RRR_6_OPCODE_Y1 = 12,
317 SHLIH_SHUN_0_OPCODE_X1 = 3, 317 RRR_7_OPCODE_Y0 = 12,
318 SHLI_SHUN_0_OPCODE_X0 = 4, 318 RRR_7_OPCODE_Y1 = 13,
319 SHLI_SHUN_0_OPCODE_X1 = 4, 319 RRR_8_OPCODE_Y0 = 13,
320 SHLI_SHUN_0_OPCODE_Y0 = 2, 320 RRR_9_OPCODE_Y0 = 14,
321 SHLI_SHUN_0_OPCODE_Y1 = 2, 321 SHIFT_OPCODE_X0 = 6,
322 SHL_SPECIAL_0_OPCODE_X0 = 69, 322 SHIFT_OPCODE_X1 = 6,
323 SHL_SPECIAL_0_OPCODE_X1 = 38, 323 SHIFT_OPCODE_Y0 = 15,
324 SHL_SPECIAL_3_OPCODE_Y0 = 1, 324 SHIFT_OPCODE_Y1 = 14,
325 SHL_SPECIAL_3_OPCODE_Y1 = 1, 325 SHL16INSLI_OPCODE_X0 = 7,
326 SHR1_RR_IMM_0_OPCODE_SN = 9, 326 SHL16INSLI_OPCODE_X1 = 7,
327 SHRB_SPECIAL_0_OPCODE_X0 = 70, 327 SHL1ADDX_RRR_0_OPCODE_X0 = 67,
328 SHRB_SPECIAL_0_OPCODE_X1 = 39, 328 SHL1ADDX_RRR_0_OPCODE_X1 = 31,
329 SHRH_SPECIAL_0_OPCODE_X0 = 71, 329 SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
330 SHRH_SPECIAL_0_OPCODE_X1 = 40, 330 SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
331 SHRIB_SHUN_0_OPCODE_X0 = 5, 331 SHL1ADD_RRR_0_OPCODE_X0 = 68,
332 SHRIB_SHUN_0_OPCODE_X1 = 5, 332 SHL1ADD_RRR_0_OPCODE_X1 = 32,
333 SHRIH_SHUN_0_OPCODE_X0 = 6, 333 SHL1ADD_RRR_1_OPCODE_Y0 = 0,
334 SHRIH_SHUN_0_OPCODE_X1 = 6, 334 SHL1ADD_RRR_1_OPCODE_Y1 = 0,
335 SHRI_SHUN_0_OPCODE_X0 = 7, 335 SHL2ADDX_RRR_0_OPCODE_X0 = 69,
336 SHRI_SHUN_0_OPCODE_X1 = 7, 336 SHL2ADDX_RRR_0_OPCODE_X1 = 33,
337 SHRI_SHUN_0_OPCODE_Y0 = 3, 337 SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
338 SHRI_SHUN_0_OPCODE_Y1 = 3, 338 SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
339 SHR_SPECIAL_0_OPCODE_X0 = 72, 339 SHL2ADD_RRR_0_OPCODE_X0 = 70,
340 SHR_SPECIAL_0_OPCODE_X1 = 41, 340 SHL2ADD_RRR_0_OPCODE_X1 = 34,
341 SHR_SPECIAL_3_OPCODE_Y0 = 2, 341 SHL2ADD_RRR_1_OPCODE_Y0 = 1,
342 SHR_SPECIAL_3_OPCODE_Y1 = 2, 342 SHL2ADD_RRR_1_OPCODE_Y1 = 1,
343 SHUN_0_OPCODE_X0 = 7, 343 SHL3ADDX_RRR_0_OPCODE_X0 = 71,
344 SHUN_0_OPCODE_X1 = 8, 344 SHL3ADDX_RRR_0_OPCODE_X1 = 35,
345 SHUN_0_OPCODE_Y0 = 13, 345 SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
346 SHUN_0_OPCODE_Y1 = 11, 346 SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
347 SH_OPCODE_Y2 = 6, 347 SHL3ADD_RRR_0_OPCODE_X0 = 72,
348 SH_SPECIAL_0_OPCODE_X1 = 42, 348 SHL3ADD_RRR_0_OPCODE_X1 = 36,
349 SLTB_SPECIAL_0_OPCODE_X0 = 73, 349 SHL3ADD_RRR_1_OPCODE_Y0 = 2,
350 SLTB_SPECIAL_0_OPCODE_X1 = 43, 350 SHL3ADD_RRR_1_OPCODE_Y1 = 2,
351 SLTB_U_SPECIAL_0_OPCODE_X0 = 74, 351 SHLI_SHIFT_OPCODE_X0 = 2,
352 SLTB_U_SPECIAL_0_OPCODE_X1 = 44, 352 SHLI_SHIFT_OPCODE_X1 = 2,
353 SLTEB_SPECIAL_0_OPCODE_X0 = 75, 353 SHLI_SHIFT_OPCODE_Y0 = 1,
354 SLTEB_SPECIAL_0_OPCODE_X1 = 45, 354 SHLI_SHIFT_OPCODE_Y1 = 1,
355 SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, 355 SHLXI_SHIFT_OPCODE_X0 = 3,
356 SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, 356 SHLXI_SHIFT_OPCODE_X1 = 3,
357 SLTEH_SPECIAL_0_OPCODE_X0 = 77, 357 SHLX_RRR_0_OPCODE_X0 = 73,
358 SLTEH_SPECIAL_0_OPCODE_X1 = 47, 358 SHLX_RRR_0_OPCODE_X1 = 37,
359 SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, 359 SHL_RRR_0_OPCODE_X0 = 74,
360 SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, 360 SHL_RRR_0_OPCODE_X1 = 38,
361 SLTE_SPECIAL_0_OPCODE_X0 = 79, 361 SHL_RRR_6_OPCODE_Y0 = 1,
362 SLTE_SPECIAL_0_OPCODE_X1 = 49, 362 SHL_RRR_6_OPCODE_Y1 = 1,
363 SLTE_SPECIAL_4_OPCODE_Y0 = 0, 363 SHRSI_SHIFT_OPCODE_X0 = 4,
364 SLTE_SPECIAL_4_OPCODE_Y1 = 0, 364 SHRSI_SHIFT_OPCODE_X1 = 4,
365 SLTE_U_SPECIAL_0_OPCODE_X0 = 80, 365 SHRSI_SHIFT_OPCODE_Y0 = 2,
366 SLTE_U_SPECIAL_0_OPCODE_X1 = 50, 366 SHRSI_SHIFT_OPCODE_Y1 = 2,
367 SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, 367 SHRS_RRR_0_OPCODE_X0 = 75,
368 SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, 368 SHRS_RRR_0_OPCODE_X1 = 39,
369 SLTH_SPECIAL_0_OPCODE_X0 = 81, 369 SHRS_RRR_6_OPCODE_Y0 = 2,
370 SLTH_SPECIAL_0_OPCODE_X1 = 51, 370 SHRS_RRR_6_OPCODE_Y1 = 2,
371 SLTH_U_SPECIAL_0_OPCODE_X0 = 82, 371 SHRUI_SHIFT_OPCODE_X0 = 5,
372 SLTH_U_SPECIAL_0_OPCODE_X1 = 52, 372 SHRUI_SHIFT_OPCODE_X1 = 5,
373 SLTIB_IMM_0_OPCODE_X0 = 12, 373 SHRUI_SHIFT_OPCODE_Y0 = 3,
374 SLTIB_IMM_0_OPCODE_X1 = 15, 374 SHRUI_SHIFT_OPCODE_Y1 = 3,
375 SLTIB_U_IMM_0_OPCODE_X0 = 13, 375 SHRUXI_SHIFT_OPCODE_X0 = 6,
376 SLTIB_U_IMM_0_OPCODE_X1 = 16, 376 SHRUXI_SHIFT_OPCODE_X1 = 6,
377 SLTIH_IMM_0_OPCODE_X0 = 14, 377 SHRUX_RRR_0_OPCODE_X0 = 76,
378 SLTIH_IMM_0_OPCODE_X1 = 17, 378 SHRUX_RRR_0_OPCODE_X1 = 40,
379 SLTIH_U_IMM_0_OPCODE_X0 = 15, 379 SHRU_RRR_0_OPCODE_X0 = 77,
380 SLTIH_U_IMM_0_OPCODE_X1 = 18, 380 SHRU_RRR_0_OPCODE_X1 = 41,
381 SLTI_IMM_0_OPCODE_X0 = 16, 381 SHRU_RRR_6_OPCODE_Y0 = 3,
382 SLTI_IMM_0_OPCODE_X1 = 19, 382 SHRU_RRR_6_OPCODE_Y1 = 3,
383 SLTI_OPCODE_Y0 = 14, 383 SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
384 SLTI_OPCODE_Y1 = 12, 384 ST1_ADD_IMM8_OPCODE_X1 = 25,
385 SLTI_U_IMM_0_OPCODE_X0 = 17, 385 ST1_OPCODE_Y2 = 0,
386 SLTI_U_IMM_0_OPCODE_X1 = 20, 386 ST1_RRR_0_OPCODE_X1 = 42,
387 SLTI_U_OPCODE_Y0 = 15, 387 ST2_ADD_IMM8_OPCODE_X1 = 26,
388 SLTI_U_OPCODE_Y1 = 13, 388 ST2_OPCODE_Y2 = 1,
389 SLT_SPECIAL_0_OPCODE_X0 = 83, 389 ST2_RRR_0_OPCODE_X1 = 43,
390 SLT_SPECIAL_0_OPCODE_X1 = 53, 390 ST4_ADD_IMM8_OPCODE_X1 = 27,
391 SLT_SPECIAL_4_OPCODE_Y0 = 2, 391 ST4_OPCODE_Y2 = 2,
392 SLT_SPECIAL_4_OPCODE_Y1 = 2, 392 ST4_RRR_0_OPCODE_X1 = 44,
393 SLT_U_SPECIAL_0_OPCODE_X0 = 84, 393 STNT1_ADD_IMM8_OPCODE_X1 = 28,
394 SLT_U_SPECIAL_0_OPCODE_X1 = 54, 394 STNT1_RRR_0_OPCODE_X1 = 45,
395 SLT_U_SPECIAL_4_OPCODE_Y0 = 3, 395 STNT2_ADD_IMM8_OPCODE_X1 = 29,
396 SLT_U_SPECIAL_4_OPCODE_Y1 = 3, 396 STNT2_RRR_0_OPCODE_X1 = 46,
397 SNEB_SPECIAL_0_OPCODE_X0 = 85, 397 STNT4_ADD_IMM8_OPCODE_X1 = 30,
398 SNEB_SPECIAL_0_OPCODE_X1 = 55, 398 STNT4_RRR_0_OPCODE_X1 = 47,
399 SNEH_SPECIAL_0_OPCODE_X0 = 86, 399 STNT_ADD_IMM8_OPCODE_X1 = 31,
400 SNEH_SPECIAL_0_OPCODE_X1 = 56, 400 STNT_RRR_0_OPCODE_X1 = 48,
401 SNE_SPECIAL_0_OPCODE_X0 = 87, 401 ST_ADD_IMM8_OPCODE_X1 = 32,
402 SNE_SPECIAL_0_OPCODE_X1 = 57, 402 ST_OPCODE_Y2 = 3,
403 SNE_SPECIAL_5_OPCODE_Y0 = 3, 403 ST_RRR_0_OPCODE_X1 = 49,
404 SNE_SPECIAL_5_OPCODE_Y1 = 3, 404 SUBXSC_RRR_0_OPCODE_X0 = 79,
405 SPECIAL_0_OPCODE_X0 = 0, 405 SUBXSC_RRR_0_OPCODE_X1 = 50,
406 SPECIAL_0_OPCODE_X1 = 1, 406 SUBX_RRR_0_OPCODE_X0 = 80,
407 SPECIAL_0_OPCODE_Y0 = 1, 407 SUBX_RRR_0_OPCODE_X1 = 51,
408 SPECIAL_0_OPCODE_Y1 = 1, 408 SUBX_RRR_0_OPCODE_Y0 = 2,
409 SPECIAL_1_OPCODE_Y0 = 2, 409 SUBX_RRR_0_OPCODE_Y1 = 2,
410 SPECIAL_1_OPCODE_Y1 = 2, 410 SUB_RRR_0_OPCODE_X0 = 81,
411 SPECIAL_2_OPCODE_Y0 = 3, 411 SUB_RRR_0_OPCODE_X1 = 52,
412 SPECIAL_2_OPCODE_Y1 = 3, 412 SUB_RRR_0_OPCODE_Y0 = 3,
413 SPECIAL_3_OPCODE_Y0 = 4, 413 SUB_RRR_0_OPCODE_Y1 = 3,
414 SPECIAL_3_OPCODE_Y1 = 4, 414 SWINT0_UNARY_OPCODE_X1 = 34,
415 SPECIAL_4_OPCODE_Y0 = 5, 415 SWINT1_UNARY_OPCODE_X1 = 35,
416 SPECIAL_4_OPCODE_Y1 = 5, 416 SWINT2_UNARY_OPCODE_X1 = 36,
417 SPECIAL_5_OPCODE_Y0 = 6, 417 SWINT3_UNARY_OPCODE_X1 = 37,
418 SPECIAL_5_OPCODE_Y1 = 6, 418 TBLIDXB0_UNARY_OPCODE_X0 = 9,
419 SPECIAL_6_OPCODE_Y0 = 7, 419 TBLIDXB0_UNARY_OPCODE_Y0 = 9,
420 SPECIAL_7_OPCODE_Y0 = 8, 420 TBLIDXB1_UNARY_OPCODE_X0 = 10,
421 SRAB_SPECIAL_0_OPCODE_X0 = 88, 421 TBLIDXB1_UNARY_OPCODE_Y0 = 10,
422 SRAB_SPECIAL_0_OPCODE_X1 = 58, 422 TBLIDXB2_UNARY_OPCODE_X0 = 11,
423 SRAH_SPECIAL_0_OPCODE_X0 = 89, 423 TBLIDXB2_UNARY_OPCODE_Y0 = 11,
424 SRAH_SPECIAL_0_OPCODE_X1 = 59, 424 TBLIDXB3_UNARY_OPCODE_X0 = 12,
425 SRAIB_SHUN_0_OPCODE_X0 = 8, 425 TBLIDXB3_UNARY_OPCODE_Y0 = 12,
426 SRAIB_SHUN_0_OPCODE_X1 = 8, 426 UNARY_RRR_0_OPCODE_X0 = 82,
427 SRAIH_SHUN_0_OPCODE_X0 = 9, 427 UNARY_RRR_0_OPCODE_X1 = 53,
428 SRAIH_SHUN_0_OPCODE_X1 = 9, 428 UNARY_RRR_1_OPCODE_Y0 = 3,
429 SRAI_SHUN_0_OPCODE_X0 = 10, 429 UNARY_RRR_1_OPCODE_Y1 = 3,
430 SRAI_SHUN_0_OPCODE_X1 = 10, 430 V1ADDI_IMM8_OPCODE_X0 = 8,
431 SRAI_SHUN_0_OPCODE_Y0 = 4, 431 V1ADDI_IMM8_OPCODE_X1 = 33,
432 SRAI_SHUN_0_OPCODE_Y1 = 4, 432 V1ADDUC_RRR_0_OPCODE_X0 = 83,
433 SRA_SPECIAL_0_OPCODE_X0 = 90, 433 V1ADDUC_RRR_0_OPCODE_X1 = 54,
434 SRA_SPECIAL_0_OPCODE_X1 = 60, 434 V1ADD_RRR_0_OPCODE_X0 = 84,
435 SRA_SPECIAL_3_OPCODE_Y0 = 3, 435 V1ADD_RRR_0_OPCODE_X1 = 55,
436 SRA_SPECIAL_3_OPCODE_Y1 = 3, 436 V1ADIFFU_RRR_0_OPCODE_X0 = 85,
437 SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, 437 V1AVGU_RRR_0_OPCODE_X0 = 86,
438 SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, 438 V1CMPEQI_IMM8_OPCODE_X0 = 9,
439 SUBB_SPECIAL_0_OPCODE_X0 = 91, 439 V1CMPEQI_IMM8_OPCODE_X1 = 34,
440 SUBB_SPECIAL_0_OPCODE_X1 = 61, 440 V1CMPEQ_RRR_0_OPCODE_X0 = 87,
441 SUBHS_SPECIAL_0_OPCODE_X0 = 101, 441 V1CMPEQ_RRR_0_OPCODE_X1 = 56,
442 SUBHS_SPECIAL_0_OPCODE_X1 = 71, 442 V1CMPLES_RRR_0_OPCODE_X0 = 88,
443 SUBH_SPECIAL_0_OPCODE_X0 = 92, 443 V1CMPLES_RRR_0_OPCODE_X1 = 57,
444 SUBH_SPECIAL_0_OPCODE_X1 = 62, 444 V1CMPLEU_RRR_0_OPCODE_X0 = 89,
445 SUBS_SPECIAL_0_OPCODE_X0 = 97, 445 V1CMPLEU_RRR_0_OPCODE_X1 = 58,
446 SUBS_SPECIAL_0_OPCODE_X1 = 67, 446 V1CMPLTSI_IMM8_OPCODE_X0 = 10,
447 SUB_SPECIAL_0_OPCODE_X0 = 93, 447 V1CMPLTSI_IMM8_OPCODE_X1 = 35,
448 SUB_SPECIAL_0_OPCODE_X1 = 63, 448 V1CMPLTS_RRR_0_OPCODE_X0 = 90,
449 SUB_SPECIAL_0_OPCODE_Y0 = 3, 449 V1CMPLTS_RRR_0_OPCODE_X1 = 59,
450 SUB_SPECIAL_0_OPCODE_Y1 = 3, 450 V1CMPLTUI_IMM8_OPCODE_X0 = 11,
451 SWADD_IMM_0_OPCODE_X1 = 30, 451 V1CMPLTUI_IMM8_OPCODE_X1 = 36,
452 SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, 452 V1CMPLTU_RRR_0_OPCODE_X0 = 91,
453 SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, 453 V1CMPLTU_RRR_0_OPCODE_X1 = 60,
454 SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, 454 V1CMPNE_RRR_0_OPCODE_X0 = 92,
455 SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, 455 V1CMPNE_RRR_0_OPCODE_X1 = 61,
456 SW_OPCODE_Y2 = 7, 456 V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
457 SW_SPECIAL_0_OPCODE_X1 = 64, 457 V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
458 TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, 458 V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
459 TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, 459 V1DDOTPU_RRR_0_OPCODE_X0 = 162,
460 TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, 460 V1DOTPA_RRR_0_OPCODE_X0 = 95,
461 TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, 461 V1DOTPUA_RRR_0_OPCODE_X0 = 163,
462 TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, 462 V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
463 TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, 463 V1DOTPUS_RRR_0_OPCODE_X0 = 97,
464 TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, 464 V1DOTPU_RRR_0_OPCODE_X0 = 164,
465 TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, 465 V1DOTP_RRR_0_OPCODE_X0 = 98,
466 TNS_UN_0_SHUN_0_OPCODE_X1 = 22, 466 V1INT_H_RRR_0_OPCODE_X0 = 99,
467 UN_0_SHUN_0_OPCODE_X0 = 11, 467 V1INT_H_RRR_0_OPCODE_X1 = 62,
468 UN_0_SHUN_0_OPCODE_X1 = 11, 468 V1INT_L_RRR_0_OPCODE_X0 = 100,
469 UN_0_SHUN_0_OPCODE_Y0 = 5, 469 V1INT_L_RRR_0_OPCODE_X1 = 63,
470 UN_0_SHUN_0_OPCODE_Y1 = 5, 470 V1MAXUI_IMM8_OPCODE_X0 = 12,
471 WH64_UN_0_SHUN_0_OPCODE_X1 = 23, 471 V1MAXUI_IMM8_OPCODE_X1 = 37,
472 XORI_IMM_0_OPCODE_X0 = 2, 472 V1MAXU_RRR_0_OPCODE_X0 = 101,
473 XORI_IMM_0_OPCODE_X1 = 21, 473 V1MAXU_RRR_0_OPCODE_X1 = 64,
474 XOR_SPECIAL_0_OPCODE_X0 = 94, 474 V1MINUI_IMM8_OPCODE_X0 = 13,
475 XOR_SPECIAL_0_OPCODE_X1 = 65, 475 V1MINUI_IMM8_OPCODE_X1 = 38,
476 XOR_SPECIAL_2_OPCODE_Y0 = 3, 476 V1MINU_RRR_0_OPCODE_X0 = 102,
477 XOR_SPECIAL_2_OPCODE_Y1 = 3 477 V1MINU_RRR_0_OPCODE_X1 = 65,
478 V1MNZ_RRR_0_OPCODE_X0 = 103,
479 V1MNZ_RRR_0_OPCODE_X1 = 66,
480 V1MULTU_RRR_0_OPCODE_X0 = 104,
481 V1MULUS_RRR_0_OPCODE_X0 = 105,
482 V1MULU_RRR_0_OPCODE_X0 = 106,
483 V1MZ_RRR_0_OPCODE_X0 = 107,
484 V1MZ_RRR_0_OPCODE_X1 = 67,
485 V1SADAU_RRR_0_OPCODE_X0 = 108,
486 V1SADU_RRR_0_OPCODE_X0 = 109,
487 V1SHLI_SHIFT_OPCODE_X0 = 7,
488 V1SHLI_SHIFT_OPCODE_X1 = 7,
489 V1SHL_RRR_0_OPCODE_X0 = 110,
490 V1SHL_RRR_0_OPCODE_X1 = 68,
491 V1SHRSI_SHIFT_OPCODE_X0 = 8,
492 V1SHRSI_SHIFT_OPCODE_X1 = 8,
493 V1SHRS_RRR_0_OPCODE_X0 = 111,
494 V1SHRS_RRR_0_OPCODE_X1 = 69,
495 V1SHRUI_SHIFT_OPCODE_X0 = 9,
496 V1SHRUI_SHIFT_OPCODE_X1 = 9,
497 V1SHRU_RRR_0_OPCODE_X0 = 112,
498 V1SHRU_RRR_0_OPCODE_X1 = 70,
499 V1SUBUC_RRR_0_OPCODE_X0 = 113,
500 V1SUBUC_RRR_0_OPCODE_X1 = 71,
501 V1SUB_RRR_0_OPCODE_X0 = 114,
502 V1SUB_RRR_0_OPCODE_X1 = 72,
503 V2ADDI_IMM8_OPCODE_X0 = 14,
504 V2ADDI_IMM8_OPCODE_X1 = 39,
505 V2ADDSC_RRR_0_OPCODE_X0 = 115,
506 V2ADDSC_RRR_0_OPCODE_X1 = 73,
507 V2ADD_RRR_0_OPCODE_X0 = 116,
508 V2ADD_RRR_0_OPCODE_X1 = 74,
509 V2ADIFFS_RRR_0_OPCODE_X0 = 117,
510 V2AVGS_RRR_0_OPCODE_X0 = 118,
511 V2CMPEQI_IMM8_OPCODE_X0 = 15,
512 V2CMPEQI_IMM8_OPCODE_X1 = 40,
513 V2CMPEQ_RRR_0_OPCODE_X0 = 119,
514 V2CMPEQ_RRR_0_OPCODE_X1 = 75,
515 V2CMPLES_RRR_0_OPCODE_X0 = 120,
516 V2CMPLES_RRR_0_OPCODE_X1 = 76,
517 V2CMPLEU_RRR_0_OPCODE_X0 = 121,
518 V2CMPLEU_RRR_0_OPCODE_X1 = 77,
519 V2CMPLTSI_IMM8_OPCODE_X0 = 16,
520 V2CMPLTSI_IMM8_OPCODE_X1 = 41,
521 V2CMPLTS_RRR_0_OPCODE_X0 = 122,
522 V2CMPLTS_RRR_0_OPCODE_X1 = 78,
523 V2CMPLTUI_IMM8_OPCODE_X0 = 17,
524 V2CMPLTUI_IMM8_OPCODE_X1 = 42,
525 V2CMPLTU_RRR_0_OPCODE_X0 = 123,
526 V2CMPLTU_RRR_0_OPCODE_X1 = 79,
527 V2CMPNE_RRR_0_OPCODE_X0 = 124,
528 V2CMPNE_RRR_0_OPCODE_X1 = 80,
529 V2DOTPA_RRR_0_OPCODE_X0 = 125,
530 V2DOTP_RRR_0_OPCODE_X0 = 126,
531 V2INT_H_RRR_0_OPCODE_X0 = 127,
532 V2INT_H_RRR_0_OPCODE_X1 = 81,
533 V2INT_L_RRR_0_OPCODE_X0 = 128,
534 V2INT_L_RRR_0_OPCODE_X1 = 82,
535 V2MAXSI_IMM8_OPCODE_X0 = 18,
536 V2MAXSI_IMM8_OPCODE_X1 = 43,
537 V2MAXS_RRR_0_OPCODE_X0 = 129,
538 V2MAXS_RRR_0_OPCODE_X1 = 83,
539 V2MINSI_IMM8_OPCODE_X0 = 19,
540 V2MINSI_IMM8_OPCODE_X1 = 44,
541 V2MINS_RRR_0_OPCODE_X0 = 130,
542 V2MINS_RRR_0_OPCODE_X1 = 84,
543 V2MNZ_RRR_0_OPCODE_X0 = 131,
544 V2MNZ_RRR_0_OPCODE_X1 = 85,
545 V2MULFSC_RRR_0_OPCODE_X0 = 132,
546 V2MULS_RRR_0_OPCODE_X0 = 133,
547 V2MULTS_RRR_0_OPCODE_X0 = 134,
548 V2MZ_RRR_0_OPCODE_X0 = 135,
549 V2MZ_RRR_0_OPCODE_X1 = 86,
550 V2PACKH_RRR_0_OPCODE_X0 = 136,
551 V2PACKH_RRR_0_OPCODE_X1 = 87,
552 V2PACKL_RRR_0_OPCODE_X0 = 137,
553 V2PACKL_RRR_0_OPCODE_X1 = 88,
554 V2PACKUC_RRR_0_OPCODE_X0 = 138,
555 V2PACKUC_RRR_0_OPCODE_X1 = 89,
556 V2SADAS_RRR_0_OPCODE_X0 = 139,
557 V2SADAU_RRR_0_OPCODE_X0 = 140,
558 V2SADS_RRR_0_OPCODE_X0 = 141,
559 V2SADU_RRR_0_OPCODE_X0 = 142,
560 V2SHLI_SHIFT_OPCODE_X0 = 10,
561 V2SHLI_SHIFT_OPCODE_X1 = 10,
562 V2SHLSC_RRR_0_OPCODE_X0 = 143,
563 V2SHLSC_RRR_0_OPCODE_X1 = 90,
564 V2SHL_RRR_0_OPCODE_X0 = 144,
565 V2SHL_RRR_0_OPCODE_X1 = 91,
566 V2SHRSI_SHIFT_OPCODE_X0 = 11,
567 V2SHRSI_SHIFT_OPCODE_X1 = 11,
568 V2SHRS_RRR_0_OPCODE_X0 = 145,
569 V2SHRS_RRR_0_OPCODE_X1 = 92,
570 V2SHRUI_SHIFT_OPCODE_X0 = 12,
571 V2SHRUI_SHIFT_OPCODE_X1 = 12,
572 V2SHRU_RRR_0_OPCODE_X0 = 146,
573 V2SHRU_RRR_0_OPCODE_X1 = 93,
574 V2SUBSC_RRR_0_OPCODE_X0 = 147,
575 V2SUBSC_RRR_0_OPCODE_X1 = 94,
576 V2SUB_RRR_0_OPCODE_X0 = 148,
577 V2SUB_RRR_0_OPCODE_X1 = 95,
578 V4ADDSC_RRR_0_OPCODE_X0 = 149,
579 V4ADDSC_RRR_0_OPCODE_X1 = 96,
580 V4ADD_RRR_0_OPCODE_X0 = 150,
581 V4ADD_RRR_0_OPCODE_X1 = 97,
582 V4INT_H_RRR_0_OPCODE_X0 = 151,
583 V4INT_H_RRR_0_OPCODE_X1 = 98,
584 V4INT_L_RRR_0_OPCODE_X0 = 152,
585 V4INT_L_RRR_0_OPCODE_X1 = 99,
586 V4PACKSC_RRR_0_OPCODE_X0 = 153,
587 V4PACKSC_RRR_0_OPCODE_X1 = 100,
588 V4SHLSC_RRR_0_OPCODE_X0 = 154,
589 V4SHLSC_RRR_0_OPCODE_X1 = 101,
590 V4SHL_RRR_0_OPCODE_X0 = 155,
591 V4SHL_RRR_0_OPCODE_X1 = 102,
592 V4SHRS_RRR_0_OPCODE_X0 = 156,
593 V4SHRS_RRR_0_OPCODE_X1 = 103,
594 V4SHRU_RRR_0_OPCODE_X0 = 157,
595 V4SHRU_RRR_0_OPCODE_X1 = 104,
596 V4SUBSC_RRR_0_OPCODE_X0 = 158,
597 V4SUBSC_RRR_0_OPCODE_X1 = 105,
598 V4SUB_RRR_0_OPCODE_X0 = 159,
599 V4SUB_RRR_0_OPCODE_X1 = 106,
600 WH64_UNARY_OPCODE_X1 = 38,
601 XORI_IMM8_OPCODE_X0 = 20,
602 XORI_IMM8_OPCODE_X1 = 45,
603 XOR_RRR_0_OPCODE_X0 = 160,
604 XOR_RRR_0_OPCODE_X1 = 107,
605 XOR_RRR_5_OPCODE_Y0 = 3,
606 XOR_RRR_5_OPCODE_Y1 = 3
478}; 607};
479 608
480#endif /* !_TILE_OPCODE_CONSTANTS_H */ 609#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h
index 7d90641cf18d..db93518fac03 100644
--- a/arch/tile/include/asm/page.h
+++ b/arch/tile/include/asm/page.h
@@ -16,10 +16,12 @@
16#define _ASM_TILE_PAGE_H 16#define _ASM_TILE_PAGE_H
17 17
18#include <linux/const.h> 18#include <linux/const.h>
19#include <hv/hypervisor.h>
20#include <arch/chip.h>
19 21
20/* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */ 22/* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */
21#define PAGE_SHIFT 16 23#define PAGE_SHIFT HV_LOG2_PAGE_SIZE_SMALL
22#define HPAGE_SHIFT 24 24#define HPAGE_SHIFT HV_LOG2_PAGE_SIZE_LARGE
23 25
24#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) 26#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
25#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 27#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
@@ -27,25 +29,13 @@
27#define PAGE_MASK (~(PAGE_SIZE - 1)) 29#define PAGE_MASK (~(PAGE_SIZE - 1))
28#define HPAGE_MASK (~(HPAGE_SIZE - 1)) 30#define HPAGE_MASK (~(HPAGE_SIZE - 1))
29 31
30#ifdef __KERNEL__
31
32#include <hv/hypervisor.h>
33#include <arch/chip.h>
34
35/* 32/*
36 * The {,H}PAGE_SHIFT values must match the HV_LOG2_PAGE_SIZE_xxx 33 * If the Kconfig doesn't specify, set a maximum zone order that
37 * definitions in <hv/hypervisor.h>. We validate this at build time 34 * is enough so that we can create huge pages from small pages given
38 * here, and again at runtime during early boot. We provide a 35 * the respective sizes of the two page types. See <linux/mmzone.h>.
39 * separate definition since userspace doesn't have <hv/hypervisor.h>.
40 *
41 * Be careful to distinguish PAGE_SHIFT from HV_PTE_INDEX_PFN, since
42 * they are the same on i386 but not TILE.
43 */ 36 */
44#if HV_LOG2_PAGE_SIZE_SMALL != PAGE_SHIFT 37#ifndef CONFIG_FORCE_MAX_ZONEORDER
45# error Small page size mismatch in Linux 38#define CONFIG_FORCE_MAX_ZONEORDER (HPAGE_SHIFT - PAGE_SHIFT + 1)
46#endif
47#if HV_LOG2_PAGE_SIZE_LARGE != HPAGE_SHIFT
48# error Huge page size mismatch in Linux
49#endif 39#endif
50 40
51#ifndef __ASSEMBLY__ 41#ifndef __ASSEMBLY__
@@ -81,12 +71,6 @@ static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
81 * Hypervisor page tables are made of the same basic structure. 71 * Hypervisor page tables are made of the same basic structure.
82 */ 72 */
83 73
84typedef __u64 pteval_t;
85typedef __u64 pmdval_t;
86typedef __u64 pudval_t;
87typedef __u64 pgdval_t;
88typedef __u64 pgprotval_t;
89
90typedef HV_PTE pte_t; 74typedef HV_PTE pte_t;
91typedef HV_PTE pgd_t; 75typedef HV_PTE pgd_t;
92typedef HV_PTE pgprot_t; 76typedef HV_PTE pgprot_t;
@@ -103,6 +87,10 @@ typedef struct page *pgtable_t;
103/* Must be a macro since it is used to create constants. */ 87/* Must be a macro since it is used to create constants. */
104#define __pgprot(val) hv_pte(val) 88#define __pgprot(val) hv_pte(val)
105 89
90/* Rarely-used initializers, typically with a "zero" value. */
91#define __pte(x) hv_pte(x)
92#define __pgd(x) hv_pte(x)
93
106static inline u64 pgprot_val(pgprot_t pgprot) 94static inline u64 pgprot_val(pgprot_t pgprot)
107{ 95{
108 return hv_pte_val(pgprot); 96 return hv_pte_val(pgprot);
@@ -122,6 +110,8 @@ static inline u64 pgd_val(pgd_t pgd)
122 110
123typedef HV_PTE pmd_t; 111typedef HV_PTE pmd_t;
124 112
113#define __pmd(x) hv_pte(x)
114
125static inline u64 pmd_val(pmd_t pmd) 115static inline u64 pmd_val(pmd_t pmd)
126{ 116{
127 return hv_pte_val(pmd); 117 return hv_pte_val(pmd);
@@ -199,17 +189,17 @@ static inline __attribute_const__ int get_order(unsigned long size)
199 * If you want more physical memory than this then see the CONFIG_HIGHMEM 189 * If you want more physical memory than this then see the CONFIG_HIGHMEM
200 * option in the kernel configuration. 190 * option in the kernel configuration.
201 * 191 *
202 * The top two 16MB chunks in the table below (VIRT and HV) are 192 * The top 16MB chunk in the table below is unavailable to Linux. Since
203 * unavailable to Linux. Since the kernel interrupt vectors must live 193 * the kernel interrupt vectors must live at ether 0xfe000000 or 0xfd000000
204 * at 0xfd000000, we map all of the bottom of RAM at this address with 194 * (depending on whether the kernel is at PL2 or Pl1), we map all of the
205 * a huge page table entry to minimize its ITLB footprint (as well as 195 * bottom of RAM at this address with a huge page table entry to minimize
206 * at PAGE_OFFSET). The last architected requirement is that user 196 * its ITLB footprint (as well as at PAGE_OFFSET). The last architected
207 * interrupt vectors live at 0xfc000000, so we make that range of 197 * requirement is that user interrupt vectors live at 0xfc000000, so we
208 * memory available to user processes. The remaining regions are sized 198 * make that range of memory available to user processes. The remaining
209 * as shown; after the first four addresses, we show "typical" values, 199 * regions are sized as shown; the first four addresses use the PL 1
210 * since the actual addresses depend on kernel #defines. 200 * values, and after that, we show "typical" values, since the actual
201 * addresses depend on kernel #defines.
211 * 202 *
212 * MEM_VIRT_INTRPT 0xff000000
213 * MEM_HV_INTRPT 0xfe000000 203 * MEM_HV_INTRPT 0xfe000000
214 * MEM_SV_INTRPT (kernel code) 0xfd000000 204 * MEM_SV_INTRPT (kernel code) 0xfd000000
215 * MEM_USER_INTRPT (user vector) 0xfc000000 205 * MEM_USER_INTRPT (user vector) 0xfc000000
@@ -221,9 +211,14 @@ static inline __attribute_const__ int get_order(unsigned long size)
221 */ 211 */
222 212
223#define MEM_USER_INTRPT _AC(0xfc000000, UL) 213#define MEM_USER_INTRPT _AC(0xfc000000, UL)
214#if CONFIG_KERNEL_PL == 1
224#define MEM_SV_INTRPT _AC(0xfd000000, UL) 215#define MEM_SV_INTRPT _AC(0xfd000000, UL)
225#define MEM_HV_INTRPT _AC(0xfe000000, UL) 216#define MEM_HV_INTRPT _AC(0xfe000000, UL)
226#define MEM_VIRT_INTRPT _AC(0xff000000, UL) 217#else
218#define MEM_GUEST_INTRPT _AC(0xfd000000, UL)
219#define MEM_SV_INTRPT _AC(0xfe000000, UL)
220#define MEM_HV_INTRPT _AC(0xff000000, UL)
221#endif
227 222
228#define INTRPT_SIZE 0x4000 223#define INTRPT_SIZE 0x4000
229 224
@@ -325,7 +320,7 @@ static inline int pfn_valid(unsigned long pfn)
325 320
326/* Provide as macros since these require some other headers included. */ 321/* Provide as macros since these require some other headers included. */
327#define page_to_pa(page) ((phys_addr_t)(page_to_pfn(page)) << PAGE_SHIFT) 322#define page_to_pa(page) ((phys_addr_t)(page_to_pfn(page)) << PAGE_SHIFT)
328#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn(kaddr)) 323#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn((void *)(kaddr)))
329#define page_to_virt(page) pfn_to_kaddr(page_to_pfn(page)) 324#define page_to_virt(page) pfn_to_kaddr(page_to_pfn(page))
330 325
331struct mm_struct; 326struct mm_struct;
@@ -338,6 +333,4 @@ extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
338 333
339#include <asm-generic/memory_model.h> 334#include <asm-generic/memory_model.h>
340 335
341#endif /* __KERNEL__ */
342
343#endif /* _ASM_TILE_PAGE_H */ 336#endif /* _ASM_TILE_PAGE_H */
diff --git a/arch/tile/include/asm/parport.h b/arch/tile/include/asm/parport.h
new file mode 100644
index 000000000000..cf252af64590
--- /dev/null
+++ b/arch/tile/include/asm/parport.h
@@ -0,0 +1 @@
#include <asm-generic/parport.h>
diff --git a/arch/tile/include/asm/pci-bridge.h b/arch/tile/include/asm/pci-bridge.h
deleted file mode 100644
index e853b0e2793b..000000000000
--- a/arch/tile/include/asm/pci-bridge.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_PCI_BRIDGE_H
16#define _ASM_TILE_PCI_BRIDGE_H
17
18#include <linux/ioport.h>
19#include <linux/pci.h>
20
21struct device_node;
22struct pci_controller;
23
24/*
25 * pci_io_base returns the memory address at which you can access
26 * the I/O space for PCI bus number `bus' (or NULL on error).
27 */
28extern void __iomem *pci_bus_io_base(unsigned int bus);
29extern unsigned long pci_bus_io_base_phys(unsigned int bus);
30extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
31
32/* Allocate a new PCI host bridge structure */
33extern struct pci_controller *pcibios_alloc_controller(void);
34
35/* Helper function for setting up resources */
36extern void pci_init_resource(struct resource *res, unsigned long start,
37 unsigned long end, int flags, char *name);
38
39/* Get the PCI host controller for a bus */
40extern struct pci_controller *pci_bus_to_hose(int bus);
41
42/*
43 * Structure of a PCI controller (host bridge)
44 */
45struct pci_controller {
46 int index; /* PCI domain number */
47 struct pci_bus *root_bus;
48
49 int first_busno;
50 int last_busno;
51
52 int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
53 int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
54
55 struct pci_ops *ops;
56
57 int irq_base; /* Base IRQ from the Hypervisor */
58 int plx_gen1; /* flag for PLX Gen 1 configuration */
59
60 /* Address ranges that are routed to this controller/bridge. */
61 struct resource mem_resources[3];
62};
63
64static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
65{
66 return bus->sysdata;
67}
68
69extern void setup_indirect_pci_nomap(struct pci_controller *hose,
70 void __iomem *cfg_addr, void __iomem *cfg_data);
71extern void setup_indirect_pci(struct pci_controller *hose,
72 u32 cfg_addr, u32 cfg_data);
73extern void setup_grackle(struct pci_controller *hose);
74
75extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
76
77/*
78 * The following code swizzles for exactly one bridge. The routine
79 * common_swizzle below handles multiple bridges. But there are a
80 * some boards that don't follow the PCI spec's suggestion so we
81 * break this piece out separately.
82 */
83static inline unsigned char bridge_swizzle(unsigned char pin,
84 unsigned char idsel)
85{
86 return (((pin-1) + idsel) % 4) + 1;
87}
88
89/*
90 * The following macro is used to lookup irqs in a standard table
91 * format for those PPC systems that do not already have PCI
92 * interrupts properly routed.
93 */
94/* FIXME - double check this */
95#define PCI_IRQ_TABLE_LOOKUP ({ \
96 long _ctl_ = -1; \
97 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
98 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
99 _ctl_; \
100})
101
102/*
103 * Scan the buses below a given PCI host bridge and assign suitable
104 * resources to all devices found.
105 */
106extern int pciauto_bus_scan(struct pci_controller *, int);
107
108#ifdef CONFIG_PCI
109extern unsigned long pci_address_to_pio(phys_addr_t address);
110#else
111static inline unsigned long pci_address_to_pio(phys_addr_t address)
112{
113 return (unsigned long)-1;
114}
115#endif
116
117#endif /* _ASM_TILE_PCI_BRIDGE_H */
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index b0c15da2d5d5..7f03cefed1b9 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -15,7 +15,29 @@
15#ifndef _ASM_TILE_PCI_H 15#ifndef _ASM_TILE_PCI_H
16#define _ASM_TILE_PCI_H 16#define _ASM_TILE_PCI_H
17 17
18#include <asm/pci-bridge.h> 18#include <linux/pci.h>
19
20/*
21 * Structure of a PCI controller (host bridge)
22 */
23struct pci_controller {
24 int index; /* PCI domain number */
25 struct pci_bus *root_bus;
26
27 int first_busno;
28 int last_busno;
29
30 int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
31 int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
32
33 struct pci_ops *ops;
34
35 int irq_base; /* Base IRQ from the Hypervisor */
36 int plx_gen1; /* flag for PLX Gen 1 configuration */
37
38 /* Address ranges that are routed to this controller/bridge. */
39 struct resource mem_resources[3];
40};
19 41
20/* 42/*
21 * The hypervisor maps the entirety of CPA-space as bus addresses, so 43 * The hypervisor maps the entirety of CPA-space as bus addresses, so
@@ -24,56 +46,13 @@
24 */ 46 */
25#define PCI_DMA_BUS_IS_PHYS 1 47#define PCI_DMA_BUS_IS_PHYS 1
26 48
27struct pci_controller *pci_bus_to_hose(int bus); 49int __devinit tile_pci_init(void);
28unsigned char __init common_swizzle(struct pci_dev *dev, unsigned char *pinp); 50int __devinit pcibios_init(void);
29int __init tile_pci_init(void);
30void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
31void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
32void __devinit pcibios_fixup_bus(struct pci_bus *bus);
33 51
34int __devinit _tile_cfg_read(struct pci_controller *hose, 52void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
35 int bus, 53static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
36 int slot,
37 int function,
38 int offset,
39 int size,
40 u32 *val);
41int __devinit _tile_cfg_write(struct pci_controller *hose,
42 int bus,
43 int slot,
44 int function,
45 int offset,
46 int size,
47 u32 val);
48 54
49/* 55void __devinit pcibios_fixup_bus(struct pci_bus *bus);
50 * These are used to to config reads and writes in the early stages of
51 * setup before the driver infrastructure has been set up enough to be
52 * able to do config reads and writes.
53 */
54#define early_cfg_read(where, size, value) \
55 _tile_cfg_read(controller, \
56 current_bus, \
57 pci_slot, \
58 pci_fn, \
59 where, \
60 size, \
61 value)
62
63#define early_cfg_write(where, size, value) \
64 _tile_cfg_write(controller, \
65 current_bus, \
66 pci_slot, \
67 pci_fn, \
68 where, \
69 size, \
70 value)
71
72
73
74#define PCICFG_BYTE 1
75#define PCICFG_WORD 2
76#define PCICFG_DWORD 4
77 56
78#define TILE_NUM_PCIE 2 57#define TILE_NUM_PCIE 2
79 58
@@ -88,33 +67,33 @@ static inline int pci_proc_domain(struct pci_bus *bus)
88} 67}
89 68
90/* 69/*
91 * I/O space is currently not supported. 70 * pcibios_assign_all_busses() tells whether or not the bus numbers
71 * should be reassigned, in case the BIOS didn't do it correctly, or
72 * in case we don't have a BIOS and we want to let Linux do it.
92 */ 73 */
74static inline int pcibios_assign_all_busses(void)
75{
76 return 1;
77}
93 78
94#define TILE_PCIE_LOWER_IO 0x0 79/*
95#define TILE_PCIE_UPPER_IO 0x10000 80 * No special bus mastering setup handling.
96#define TILE_PCIE_PCIE_IO_SIZE 0x0000FFFF 81 */
97
98#define _PAGE_NO_CACHE 0
99#define _PAGE_GUARDED 0
100
101
102#define pcibios_assign_all_busses() pci_assign_all_buses
103extern int pci_assign_all_buses;
104
105static inline void pcibios_set_master(struct pci_dev *dev) 82static inline void pcibios_set_master(struct pci_dev *dev)
106{ 83{
107 /* No special bus mastering setup handling */
108} 84}
109 85
110#define PCIBIOS_MIN_MEM 0 86#define PCIBIOS_MIN_MEM 0
111#define PCIBIOS_MIN_IO TILE_PCIE_LOWER_IO 87#define PCIBIOS_MIN_IO 0
112 88
113/* 89/*
114 * This flag tells if the platform is TILEmpower that needs 90 * This flag tells if the platform is TILEmpower that needs
115 * special configuration for the PLX switch chip. 91 * special configuration for the PLX switch chip.
116 */ 92 */
117extern int blade_pci; 93extern int tile_plx_gen1;
94
95/* Use any cpu for PCI. */
96#define cpumask_of_pcibus(bus) cpu_online_mask
118 97
119/* implement the pci_ DMA API in terms of the generic device dma_ one */ 98/* implement the pci_ DMA API in terms of the generic device dma_ one */
120#include <asm-generic/pci-dma-compat.h> 99#include <asm-generic/pci-dma-compat.h>
@@ -122,7 +101,4 @@ extern int blade_pci;
122/* generic pci stuff */ 101/* generic pci stuff */
123#include <asm-generic/pci.h> 102#include <asm-generic/pci.h>
124 103
125/* Use any cpu for PCI. */
126#define cpumask_of_pcibus(bus) cpu_online_mask
127
128#endif /* _ASM_TILE_PCI_H */ 104#endif /* _ASM_TILE_PCI_H */
diff --git a/arch/tile/include/asm/pgalloc.h b/arch/tile/include/asm/pgalloc.h
index cf52791a5501..e919c0bdc22d 100644
--- a/arch/tile/include/asm/pgalloc.h
+++ b/arch/tile/include/asm/pgalloc.h
@@ -41,9 +41,9 @@
41static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 41static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
42{ 42{
43#ifdef CONFIG_64BIT 43#ifdef CONFIG_64BIT
44 set_pte_order(pmdp, pmd, L2_USER_PGTABLE_ORDER); 44 set_pte(pmdp, pmd);
45#else 45#else
46 set_pte_order(&pmdp->pud.pgd, pmd.pud.pgd, L2_USER_PGTABLE_ORDER); 46 set_pte(&pmdp->pud.pgd, pmd.pud.pgd);
47#endif 47#endif
48} 48}
49 49
@@ -100,6 +100,9 @@ pte_t *get_prealloc_pte(unsigned long pfn);
100/* During init, we can shatter kernel huge pages if needed. */ 100/* During init, we can shatter kernel huge pages if needed. */
101void shatter_pmd(pmd_t *pmd); 101void shatter_pmd(pmd_t *pmd);
102 102
103/* After init, a more complex technique is required. */
104void shatter_huge_page(unsigned long addr);
105
103#ifdef __tilegx__ 106#ifdef __tilegx__
104/* We share a single page allocator for both L1 and L2 page tables. */ 107/* We share a single page allocator for both L1 and L2 page tables. */
105#if HV_L1_SIZE != HV_L2_SIZE 108#if HV_L1_SIZE != HV_L2_SIZE
diff --git a/arch/tile/include/asm/pgtable.h b/arch/tile/include/asm/pgtable.h
index b3367379d537..1a20b7ef8ea2 100644
--- a/arch/tile/include/asm/pgtable.h
+++ b/arch/tile/include/asm/pgtable.h
@@ -233,15 +233,23 @@ static inline void __pte_clear(pte_t *ptep)
233#define pgd_ERROR(e) \ 233#define pgd_ERROR(e) \
234 pr_err("%s:%d: bad pgd 0x%016llx.\n", __FILE__, __LINE__, pgd_val(e)) 234 pr_err("%s:%d: bad pgd 0x%016llx.\n", __FILE__, __LINE__, pgd_val(e))
235 235
236/* Return PA and protection info for a given kernel VA. */
237int va_to_cpa_and_pte(void *va, phys_addr_t *cpa, pte_t *pte);
238
239/*
240 * __set_pte() ensures we write the 64-bit PTE with 32-bit words in
241 * the right order on 32-bit platforms and also allows us to write
242 * hooks to check valid PTEs, etc., if we want.
243 */
244void __set_pte(pte_t *ptep, pte_t pte);
245
236/* 246/*
237 * set_pte_order() sets the given PTE and also sanity-checks the 247 * set_pte() sets the given PTE and also sanity-checks the
238 * requested PTE against the page homecaching. Unspecified parts 248 * requested PTE against the page homecaching. Unspecified parts
239 * of the PTE are filled in when it is written to memory, i.e. all 249 * of the PTE are filled in when it is written to memory, i.e. all
240 * caching attributes if "!forcecache", or the home cpu if "anyhome". 250 * caching attributes if "!forcecache", or the home cpu if "anyhome".
241 */ 251 */
242extern void set_pte_order(pte_t *ptep, pte_t pte, int order); 252extern void set_pte(pte_t *ptep, pte_t pte);
243
244#define set_pte(ptep, pteval) set_pte_order(ptep, pteval, 0)
245#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) 253#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
246#define set_pte_atomic(pteptr, pteval) set_pte(pteptr, pteval) 254#define set_pte_atomic(pteptr, pteval) set_pte(pteptr, pteval)
247 255
@@ -293,21 +301,6 @@ extern void check_mm_caching(struct mm_struct *prev, struct mm_struct *next);
293#define __swp_entry_to_pte(swp) ((pte_t) { (((long long) ((swp).val)) << 32) }) 301#define __swp_entry_to_pte(swp) ((pte_t) { (((long long) ((swp).val)) << 32) })
294 302
295/* 303/*
296 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
297 *
298 * dst - pointer to pgd range anwhere on a pgd page
299 * src - ""
300 * count - the number of pgds to copy.
301 *
302 * dst and src can be on the same page, but the range must not overlap,
303 * and must not cross a page boundary.
304 */
305static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
306{
307 memcpy(dst, src, count * sizeof(pgd_t));
308}
309
310/*
311 * Conversion functions: convert a page and protection to a page entry, 304 * Conversion functions: convert a page and protection to a page entry,
312 * and a page entry and page directory to the page they refer to. 305 * and a page entry and page directory to the page they refer to.
313 */ 306 */
@@ -344,18 +337,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
344#define pgd_offset_k(address) pgd_offset(&init_mm, address) 337#define pgd_offset_k(address) pgd_offset(&init_mm, address)
345 338
346#if defined(CONFIG_HIGHPTE) 339#if defined(CONFIG_HIGHPTE)
347extern pte_t *_pte_offset_map(pmd_t *, unsigned long address, enum km_type); 340extern pte_t *pte_offset_map(pmd_t *, unsigned long address);
348#define pte_offset_map(dir, address) \ 341#define pte_unmap(pte) kunmap_atomic(pte)
349 _pte_offset_map(dir, address, KM_PTE0)
350#define pte_offset_map_nested(dir, address) \
351 _pte_offset_map(dir, address, KM_PTE1)
352#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
353#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
354#else 342#else
355#define pte_offset_map(dir, address) pte_offset_kernel(dir, address) 343#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
356#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
357#define pte_unmap(pte) do { } while (0) 344#define pte_unmap(pte) do { } while (0)
358#define pte_unmap_nested(pte) do { } while (0)
359#endif 345#endif
360 346
361/* Clear a non-executable kernel PTE and flush it from the TLB. */ 347/* Clear a non-executable kernel PTE and flush it from the TLB. */
diff --git a/arch/tile/include/asm/pgtable_32.h b/arch/tile/include/asm/pgtable_32.h
index 53ec34884744..9f98529761fd 100644
--- a/arch/tile/include/asm/pgtable_32.h
+++ b/arch/tile/include/asm/pgtable_32.h
@@ -24,6 +24,7 @@
24#define PGDIR_SIZE HV_PAGE_SIZE_LARGE 24#define PGDIR_SIZE HV_PAGE_SIZE_LARGE
25#define PGDIR_MASK (~(PGDIR_SIZE-1)) 25#define PGDIR_MASK (~(PGDIR_SIZE-1))
26#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) 26#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
27#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
27 28
28/* 29/*
29 * The level-2 index is defined by the difference between the huge 30 * The level-2 index is defined by the difference between the huge
@@ -33,6 +34,7 @@
33 * this nomenclature is somewhat confusing. 34 * this nomenclature is somewhat confusing.
34 */ 35 */
35#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL)) 36#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
37#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
36 38
37#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
38 40
@@ -94,7 +96,6 @@ static inline int pgd_addr_invalid(unsigned long addr)
94 */ 96 */
95#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 97#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
96#define __HAVE_ARCH_PTEP_SET_WRPROTECT 98#define __HAVE_ARCH_PTEP_SET_WRPROTECT
97#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
98 99
99extern int ptep_test_and_clear_young(struct vm_area_struct *, 100extern int ptep_test_and_clear_young(struct vm_area_struct *,
100 unsigned long addr, pte_t *); 101 unsigned long addr, pte_t *);
@@ -110,6 +111,11 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
110 return pte; 111 return pte;
111} 112}
112 113
114static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
115{
116 set_pte(&pmdp->pud.pgd, pmdval.pud.pgd);
117}
118
113/* Create a pmd from a PTFN. */ 119/* Create a pmd from a PTFN. */
114static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot) 120static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
115{ 121{
diff --git a/arch/tile/include/asm/pgtable_64.h b/arch/tile/include/asm/pgtable_64.h
new file mode 100644
index 000000000000..fd80328523b4
--- /dev/null
+++ b/arch/tile/include/asm/pgtable_64.h
@@ -0,0 +1,175 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#ifndef _ASM_TILE_PGTABLE_64_H
17#define _ASM_TILE_PGTABLE_64_H
18
19/* The level-0 page table breaks the address space into 32-bit chunks. */
20#define PGDIR_SHIFT HV_LOG2_L1_SPAN
21#define PGDIR_SIZE HV_L1_SPAN
22#define PGDIR_MASK (~(PGDIR_SIZE-1))
23#define PTRS_PER_PGD HV_L0_ENTRIES
24#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
25
26/*
27 * The level-1 index is defined by the huge page size. A PMD is composed
28 * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
29 */
30#define PMD_SHIFT HV_LOG2_PAGE_SIZE_LARGE
31#define PMD_SIZE HV_PAGE_SIZE_LARGE
32#define PMD_MASK (~(PMD_SIZE-1))
33#define PTRS_PER_PMD (1 << (PGDIR_SHIFT - PMD_SHIFT))
34#define SIZEOF_PMD (PTRS_PER_PMD * sizeof(pmd_t))
35
36/*
37 * The level-2 index is defined by the difference between the huge
38 * page size and the normal page size. A PTE is composed of
39 * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
40 * Note that the hypervisor docs use PTE for what we call pte_t, so
41 * this nomenclature is somewhat confusing.
42 */
43#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
44#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
45
46/*
47 * Align the vmalloc area to an L2 page table, and leave a guard page
48 * at the beginning and end. The vmalloc code also puts in an internal
49 * guard page between each allocation.
50 */
51#define _VMALLOC_END HUGE_VMAP_BASE
52#define VMALLOC_END (_VMALLOC_END - PAGE_SIZE)
53#define VMALLOC_START (_VMALLOC_START + PAGE_SIZE)
54
55#define HUGE_VMAP_END (HUGE_VMAP_BASE + PGDIR_SIZE)
56
57#ifndef __ASSEMBLY__
58
59/* We have no pud since we are a three-level page table. */
60#include <asm-generic/pgtable-nopud.h>
61
62static inline int pud_none(pud_t pud)
63{
64 return pud_val(pud) == 0;
65}
66
67static inline int pud_present(pud_t pud)
68{
69 return pud_val(pud) & _PAGE_PRESENT;
70}
71
72#define pmd_ERROR(e) \
73 pr_err("%s:%d: bad pmd 0x%016llx.\n", __FILE__, __LINE__, pmd_val(e))
74
75static inline void pud_clear(pud_t *pudp)
76{
77 __pte_clear(&pudp->pgd);
78}
79
80static inline int pud_bad(pud_t pud)
81{
82 return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
83}
84
85/* Return the page-table frame number (ptfn) that a pud_t points at. */
86#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
87
88/*
89 * A given kernel pud_t maps to a kernel pmd_t table at a specific
90 * virtual address. Since kernel pmd_t tables can be aligned at
91 * sub-page granularity, this macro can return non-page-aligned
92 * pointers, despite its name.
93 */
94#define pud_page_vaddr(pud) \
95 (__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
96
97/*
98 * A pud_t points to a pmd_t array. Since we can have multiple per
99 * page, we don't have a one-to-one mapping of pud_t's to pages.
100 */
101#define pud_page(pud) pfn_to_page(HV_PTFN_TO_PFN(pud_ptfn(pud)))
102
103static inline unsigned long pud_index(unsigned long address)
104{
105 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
106}
107
108#define pmd_offset(pud, address) \
109 ((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
110
111static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
112{
113 set_pte(pmdp, pmdval);
114}
115
116/* Create a pmd from a PTFN and pgprot. */
117static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
118{
119 return hv_pte_set_ptfn(prot, ptfn);
120}
121
122/* Return the page-table frame number (ptfn) that a pmd_t points at. */
123static inline unsigned long pmd_ptfn(pmd_t pmd)
124{
125 return hv_pte_get_ptfn(pmd);
126}
127
128static inline void pmd_clear(pmd_t *pmdp)
129{
130 __pte_clear(pmdp);
131}
132
133/* Normalize an address to having the correct high bits set. */
134#define pgd_addr_normalize pgd_addr_normalize
135static inline unsigned long pgd_addr_normalize(unsigned long addr)
136{
137 return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
138 (CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
139}
140
141/* We don't define any pgds for these addresses. */
142static inline int pgd_addr_invalid(unsigned long addr)
143{
144 return addr >= MEM_HV_START ||
145 (addr > MEM_LOW_END && addr < MEM_HIGH_START);
146}
147
148/*
149 * Use atomic instructions to provide atomicity against the hypervisor.
150 */
151#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
152static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
153 unsigned long addr, pte_t *ptep)
154{
155 return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
156 HV_PTE_INDEX_ACCESSED) & 0x1;
157}
158
159#define __HAVE_ARCH_PTEP_SET_WRPROTECT
160static inline void ptep_set_wrprotect(struct mm_struct *mm,
161 unsigned long addr, pte_t *ptep)
162{
163 __insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
164}
165
166#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
167static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
168 unsigned long addr, pte_t *ptep)
169{
170 return hv_pte(__insn_exch(&ptep->val, 0UL));
171}
172
173#endif /* __ASSEMBLY__ */
174
175#endif /* _ASM_TILE_PGTABLE_64_H */
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index ccd5f8425688..34c1e01ffb5e 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -215,6 +215,8 @@ static inline void release_thread(struct task_struct *dead_task)
215 215
216extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); 216extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
217 217
218extern int do_work_pending(struct pt_regs *regs, u32 flags);
219
218 220
219/* 221/*
220 * Return saved (kernel) PC of a blocked thread. 222 * Return saved (kernel) PC of a blocked thread.
@@ -255,10 +257,6 @@ static inline void cpu_relax(void)
255 barrier(); 257 barrier();
256} 258}
257 259
258struct siginfo;
259extern void arch_coredump_signal(struct siginfo *, struct pt_regs *);
260#define arch_coredump_signal arch_coredump_signal
261
262/* Info on this processor (see fs/proc/cpuinfo.c) */ 260/* Info on this processor (see fs/proc/cpuinfo.c) */
263struct seq_operations; 261struct seq_operations;
264extern const struct seq_operations cpuinfo_op; 262extern const struct seq_operations cpuinfo_op;
@@ -269,10 +267,6 @@ extern char chip_model[64];
269/* Data on which physical memory controller corresponds to which NUMA node. */ 267/* Data on which physical memory controller corresponds to which NUMA node. */
270extern int node_controller[]; 268extern int node_controller[];
271 269
272
273/* Do we dump information to the console when a user application crashes? */
274extern int show_crashinfo;
275
276#if CHIP_HAS_CBOX_HOME_MAP() 270#if CHIP_HAS_CBOX_HOME_MAP()
277/* Does the heap allocator return hash-for-home pages by default? */ 271/* Does the heap allocator return hash-for-home pages by default? */
278extern int hash_default; 272extern int hash_default;
@@ -292,8 +286,18 @@ extern int kstack_hash;
292/* Are we using huge pages in the TLB for kernel data? */ 286/* Are we using huge pages in the TLB for kernel data? */
293extern int kdata_huge; 287extern int kdata_huge;
294 288
289/* Support standard Linux prefetching. */
290#define ARCH_HAS_PREFETCH
291#define prefetch(x) __builtin_prefetch(x)
295#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE() 292#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
296 293
294/* Bring a value into the L1D, faulting the TLB if necessary. */
295#ifdef __tilegx__
296#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
297#else
298#define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
299#endif
300
297#else /* __ASSEMBLY__ */ 301#else /* __ASSEMBLY__ */
298 302
299/* Do some slow action (e.g. read a slow SPR). */ 303/* Do some slow action (e.g. read a slow SPR). */
@@ -328,18 +332,21 @@ extern int kdata_huge;
328 * Note that assembly code assumes that USER_PL is zero. 332 * Note that assembly code assumes that USER_PL is zero.
329 */ 333 */
330#define USER_PL 0 334#define USER_PL 0
331#define KERNEL_PL 1 335#if CONFIG_KERNEL_PL == 2
336#define GUEST_PL 1
337#endif
338#define KERNEL_PL CONFIG_KERNEL_PL
332 339
333/* SYSTEM_SAVE_1_0 holds the current cpu number ORed with ksp0. */ 340/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
334#define CPU_LOG_MASK_VALUE 12 341#define CPU_LOG_MASK_VALUE 12
335#define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1) 342#define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1)
336#if CONFIG_NR_CPUS > CPU_MASK_VALUE 343#if CONFIG_NR_CPUS > CPU_MASK_VALUE
337# error Too many cpus! 344# error Too many cpus!
338#endif 345#endif
339#define raw_smp_processor_id() \ 346#define raw_smp_processor_id() \
340 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & CPU_MASK_VALUE) 347 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & CPU_MASK_VALUE)
341#define get_current_ksp0() \ 348#define get_current_ksp0() \
342 (__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & ~CPU_MASK_VALUE) 349 (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~CPU_MASK_VALUE)
343#define next_current_ksp0(task) ({ \ 350#define next_current_ksp0(task) ({ \
344 unsigned long __ksp0 = task_ksp0(task); \ 351 unsigned long __ksp0 = task_ksp0(task); \
345 int __cpu = raw_smp_processor_id(); \ 352 int __cpu = raw_smp_processor_id(); \
diff --git a/arch/tile/include/asm/ptrace.h b/arch/tile/include/asm/ptrace.h
index 4a02bb073979..6be2246e015c 100644
--- a/arch/tile/include/asm/ptrace.h
+++ b/arch/tile/include/asm/ptrace.h
@@ -62,8 +62,8 @@ struct pt_regs {
62 pt_reg_t lr; /* aliases regs[TREG_LR] */ 62 pt_reg_t lr; /* aliases regs[TREG_LR] */
63 63
64 /* Saved special registers. */ 64 /* Saved special registers. */
65 pt_reg_t pc; /* stored in EX_CONTEXT_1_0 */ 65 pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */
66 pt_reg_t ex1; /* stored in EX_CONTEXT_1_1 (PL and ICS bit) */ 66 pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
67 pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */ 67 pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
68 pt_reg_t orig_r0; /* r0 at syscall entry, else zero */ 68 pt_reg_t orig_r0; /* r0 at syscall entry, else zero */
69 pt_reg_t flags; /* flags (see below) */ 69 pt_reg_t flags; /* flags (see below) */
@@ -141,6 +141,9 @@ struct single_step_state {
141/* Single-step the instruction at regs->pc */ 141/* Single-step the instruction at regs->pc */
142extern void single_step_once(struct pt_regs *regs); 142extern void single_step_once(struct pt_regs *regs);
143 143
144/* Clean up after execve(). */
145extern void single_step_execve(void);
146
144struct task_struct; 147struct task_struct;
145 148
146extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, 149extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
diff --git a/arch/tile/include/asm/serial.h b/arch/tile/include/asm/serial.h
new file mode 100644
index 000000000000..a0cb0caff152
--- /dev/null
+++ b/arch/tile/include/asm/serial.h
@@ -0,0 +1 @@
#include <asm-generic/serial.h>
diff --git a/arch/tile/include/asm/signal.h b/arch/tile/include/asm/signal.h
index c1ee1d61d44c..1e1e616783eb 100644
--- a/arch/tile/include/asm/signal.h
+++ b/arch/tile/include/asm/signal.h
@@ -25,9 +25,13 @@
25 25
26#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 26#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
27struct pt_regs; 27struct pt_regs;
28int restore_sigcontext(struct pt_regs *, struct sigcontext __user *, long *); 28int restore_sigcontext(struct pt_regs *, struct sigcontext __user *);
29int setup_sigcontext(struct sigcontext __user *, struct pt_regs *); 29int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
30void do_signal(struct pt_regs *regs); 30void do_signal(struct pt_regs *regs);
31void signal_fault(const char *type, struct pt_regs *,
32 void __user *frame, int sig);
33void trace_unhandled_signal(const char *type, struct pt_regs *regs,
34 unsigned long address, int signo);
31#endif 35#endif
32 36
33#endif /* _ASM_TILE_SIGNAL_H */ 37#endif /* _ASM_TILE_SIGNAL_H */
diff --git a/arch/tile/include/asm/spinlock_32.h b/arch/tile/include/asm/spinlock_32.h
index 88efdde8dd2b..a8f2c6e31a87 100644
--- a/arch/tile/include/asm/spinlock_32.h
+++ b/arch/tile/include/asm/spinlock_32.h
@@ -78,13 +78,6 @@ void arch_spin_unlock_wait(arch_spinlock_t *lock);
78#define _RD_COUNT_SHIFT 24 78#define _RD_COUNT_SHIFT 24
79#define _RD_COUNT_WIDTH 8 79#define _RD_COUNT_WIDTH 8
80 80
81/* Internal functions; do not use. */
82void arch_read_lock_slow(arch_rwlock_t *, u32);
83int arch_read_trylock_slow(arch_rwlock_t *);
84void arch_read_unlock_slow(arch_rwlock_t *);
85void arch_write_lock_slow(arch_rwlock_t *, u32);
86void arch_write_unlock_slow(arch_rwlock_t *, u32);
87
88/** 81/**
89 * arch_read_can_lock() - would read_trylock() succeed? 82 * arch_read_can_lock() - would read_trylock() succeed?
90 */ 83 */
@@ -104,94 +97,32 @@ static inline int arch_write_can_lock(arch_rwlock_t *rwlock)
104/** 97/**
105 * arch_read_lock() - acquire a read lock. 98 * arch_read_lock() - acquire a read lock.
106 */ 99 */
107static inline void arch_read_lock(arch_rwlock_t *rwlock) 100void arch_read_lock(arch_rwlock_t *rwlock);
108{
109 u32 val = __insn_tns((int *)&rwlock->lock);
110 if (unlikely(val << _RD_COUNT_WIDTH)) {
111 arch_read_lock_slow(rwlock, val);
112 return;
113 }
114 rwlock->lock = val + (1 << _RD_COUNT_SHIFT);
115}
116 101
117/** 102/**
118 * arch_read_lock() - acquire a write lock. 103 * arch_write_lock() - acquire a write lock.
119 */ 104 */
120static inline void arch_write_lock(arch_rwlock_t *rwlock) 105void arch_write_lock(arch_rwlock_t *rwlock);
121{
122 u32 val = __insn_tns((int *)&rwlock->lock);
123 if (unlikely(val != 0)) {
124 arch_write_lock_slow(rwlock, val);
125 return;
126 }
127 rwlock->lock = 1 << _WR_NEXT_SHIFT;
128}
129 106
130/** 107/**
131 * arch_read_trylock() - try to acquire a read lock. 108 * arch_read_trylock() - try to acquire a read lock.
132 */ 109 */
133static inline int arch_read_trylock(arch_rwlock_t *rwlock) 110int arch_read_trylock(arch_rwlock_t *rwlock);
134{
135 int locked;
136 u32 val = __insn_tns((int *)&rwlock->lock);
137 if (unlikely(val & 1))
138 return arch_read_trylock_slow(rwlock);
139 locked = (val << _RD_COUNT_WIDTH) == 0;
140 rwlock->lock = val + (locked << _RD_COUNT_SHIFT);
141 return locked;
142}
143 111
144/** 112/**
145 * arch_write_trylock() - try to acquire a write lock. 113 * arch_write_trylock() - try to acquire a write lock.
146 */ 114 */
147static inline int arch_write_trylock(arch_rwlock_t *rwlock) 115int arch_write_trylock(arch_rwlock_t *rwlock);
148{
149 u32 val = __insn_tns((int *)&rwlock->lock);
150
151 /*
152 * If a tns is in progress, or there's a waiting or active locker,
153 * or active readers, we can't take the lock, so give up.
154 */
155 if (unlikely(val != 0)) {
156 if (!(val & 1))
157 rwlock->lock = val;
158 return 0;
159 }
160
161 /* Set the "next" field to mark it locked. */
162 rwlock->lock = 1 << _WR_NEXT_SHIFT;
163 return 1;
164}
165 116
166/** 117/**
167 * arch_read_unlock() - release a read lock. 118 * arch_read_unlock() - release a read lock.
168 */ 119 */
169static inline void arch_read_unlock(arch_rwlock_t *rwlock) 120void arch_read_unlock(arch_rwlock_t *rwlock);
170{
171 u32 val;
172 mb(); /* guarantee anything modified under the lock is visible */
173 val = __insn_tns((int *)&rwlock->lock);
174 if (unlikely(val & 1)) {
175 arch_read_unlock_slow(rwlock);
176 return;
177 }
178 rwlock->lock = val - (1 << _RD_COUNT_SHIFT);
179}
180 121
181/** 122/**
182 * arch_write_unlock() - release a write lock. 123 * arch_write_unlock() - release a write lock.
183 */ 124 */
184static inline void arch_write_unlock(arch_rwlock_t *rwlock) 125void arch_write_unlock(arch_rwlock_t *rwlock);
185{
186 u32 val;
187 mb(); /* guarantee anything modified under the lock is visible */
188 val = __insn_tns((int *)&rwlock->lock);
189 if (unlikely(val != (1 << _WR_NEXT_SHIFT))) {
190 arch_write_unlock_slow(rwlock, val);
191 return;
192 }
193 rwlock->lock = 0;
194}
195 126
196#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) 127#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
197#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) 128#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
diff --git a/arch/tile/include/asm/spinlock_64.h b/arch/tile/include/asm/spinlock_64.h
new file mode 100644
index 000000000000..72be5904e020
--- /dev/null
+++ b/arch/tile/include/asm/spinlock_64.h
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * 64-bit SMP ticket spinlocks, allowing only a single CPU anywhere
15 * (the type definitions are in asm/spinlock_types.h)
16 */
17
18#ifndef _ASM_TILE_SPINLOCK_64_H
19#define _ASM_TILE_SPINLOCK_64_H
20
21/* Shifts and masks for the various fields in "lock". */
22#define __ARCH_SPIN_CURRENT_SHIFT 17
23#define __ARCH_SPIN_NEXT_MASK 0x7fff
24#define __ARCH_SPIN_NEXT_OVERFLOW 0x8000
25
26/*
27 * Return the "current" portion of a ticket lock value,
28 * i.e. the number that currently owns the lock.
29 */
30static inline int arch_spin_current(u32 val)
31{
32 return val >> __ARCH_SPIN_CURRENT_SHIFT;
33}
34
35/*
36 * Return the "next" portion of a ticket lock value,
37 * i.e. the number that the next task to try to acquire the lock will get.
38 */
39static inline int arch_spin_next(u32 val)
40{
41 return val & __ARCH_SPIN_NEXT_MASK;
42}
43
44/* The lock is locked if a task would have to wait to get it. */
45static inline int arch_spin_is_locked(arch_spinlock_t *lock)
46{
47 u32 val = lock->lock;
48 return arch_spin_current(val) != arch_spin_next(val);
49}
50
51/* Bump the current ticket so the next task owns the lock. */
52static inline void arch_spin_unlock(arch_spinlock_t *lock)
53{
54 wmb(); /* guarantee anything modified under the lock is visible */
55 __insn_fetchadd4(&lock->lock, 1U << __ARCH_SPIN_CURRENT_SHIFT);
56}
57
58void arch_spin_unlock_wait(arch_spinlock_t *lock);
59
60void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
61
62/* Grab the "next" ticket number and bump it atomically.
63 * If the current ticket is not ours, go to the slow path.
64 * We also take the slow path if the "next" value overflows.
65 */
66static inline void arch_spin_lock(arch_spinlock_t *lock)
67{
68 u32 val = __insn_fetchadd4(&lock->lock, 1);
69 u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW);
70 if (unlikely(arch_spin_current(val) != ticket))
71 arch_spin_lock_slow(lock, ticket);
72}
73
74/* Try to get the lock, and return whether we succeeded. */
75int arch_spin_trylock(arch_spinlock_t *lock);
76
77/* We cannot take an interrupt after getting a ticket, so don't enable them. */
78#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
79
80/*
81 * Read-write spinlocks, allowing multiple readers
82 * but only one writer.
83 *
84 * We use fetchadd() for readers, and fetchor() with the sign bit
85 * for writers.
86 */
87
88#define __WRITE_LOCK_BIT (1 << 31)
89
90static inline int arch_write_val_locked(int val)
91{
92 return val < 0; /* Optimize "val & __WRITE_LOCK_BIT". */
93}
94
95/**
96 * read_can_lock - would read_trylock() succeed?
97 * @lock: the rwlock in question.
98 */
99static inline int arch_read_can_lock(arch_rwlock_t *rw)
100{
101 return !arch_write_val_locked(rw->lock);
102}
103
104/**
105 * write_can_lock - would write_trylock() succeed?
106 * @lock: the rwlock in question.
107 */
108static inline int arch_write_can_lock(arch_rwlock_t *rw)
109{
110 return rw->lock == 0;
111}
112
113extern void __read_lock_failed(arch_rwlock_t *rw);
114
115static inline void arch_read_lock(arch_rwlock_t *rw)
116{
117 u32 val = __insn_fetchaddgez4(&rw->lock, 1);
118 if (unlikely(arch_write_val_locked(val)))
119 __read_lock_failed(rw);
120}
121
122extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
123
124static inline void arch_write_lock(arch_rwlock_t *rw)
125{
126 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
127 if (unlikely(val != 0))
128 __write_lock_failed(rw, val);
129}
130
131static inline void arch_read_unlock(arch_rwlock_t *rw)
132{
133 __insn_mf();
134 __insn_fetchadd4(&rw->lock, -1);
135}
136
137static inline void arch_write_unlock(arch_rwlock_t *rw)
138{
139 __insn_mf();
140 rw->lock = 0;
141}
142
143static inline int arch_read_trylock(arch_rwlock_t *rw)
144{
145 return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1));
146}
147
148static inline int arch_write_trylock(arch_rwlock_t *rw)
149{
150 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
151 if (likely(val == 0))
152 return 1;
153 if (!arch_write_val_locked(val))
154 __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
155 return 0;
156}
157
158#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
159#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
160
161#endif /* _ASM_TILE_SPINLOCK_64_H */
diff --git a/arch/tile/include/asm/stack.h b/arch/tile/include/asm/stack.h
index f908473c322d..4d97a2db932e 100644
--- a/arch/tile/include/asm/stack.h
+++ b/arch/tile/include/asm/stack.h
@@ -18,13 +18,14 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <asm/backtrace.h> 20#include <asm/backtrace.h>
21#include <asm/page.h>
21#include <hv/hypervisor.h> 22#include <hv/hypervisor.h>
22 23
23/* Everything we need to keep track of a backtrace iteration */ 24/* Everything we need to keep track of a backtrace iteration */
24struct KBacktraceIterator { 25struct KBacktraceIterator {
25 BacktraceIterator it; 26 BacktraceIterator it;
26 struct task_struct *task; /* task we are backtracing */ 27 struct task_struct *task; /* task we are backtracing */
27 HV_PTE *pgtable; /* page table for user space access */ 28 pte_t *pgtable; /* page table for user space access */
28 int end; /* iteration complete. */ 29 int end; /* iteration complete. */
29 int new_context; /* new context is starting */ 30 int new_context; /* new context is starting */
30 int profile; /* profiling, so stop on async intrpt */ 31 int profile; /* profiling, so stop on async intrpt */
diff --git a/arch/tile/include/asm/stat.h b/arch/tile/include/asm/stat.h
index 3dc90fa92c70..c0db34d56be3 100644
--- a/arch/tile/include/asm/stat.h
+++ b/arch/tile/include/asm/stat.h
@@ -1 +1,4 @@
1#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
2#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
3#endif
1#include <asm-generic/stat.h> 4#include <asm-generic/stat.h>
diff --git a/arch/tile/include/asm/swab.h b/arch/tile/include/asm/swab.h
index 25c686a00f1d..7c37b38f6c8d 100644
--- a/arch/tile/include/asm/swab.h
+++ b/arch/tile/include/asm/swab.h
@@ -18,12 +18,6 @@
18/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */ 18/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
19#define __arch_swab32(x) __builtin_bswap32(x) 19#define __arch_swab32(x) __builtin_bswap32(x)
20#define __arch_swab64(x) __builtin_bswap64(x) 20#define __arch_swab64(x) __builtin_bswap64(x)
21
22/* Use the variant that is natural for the wordsize. */
23#ifdef CONFIG_64BIT
24#define __arch_swab16(x) (__builtin_bswap64(x) >> 48)
25#else
26#define __arch_swab16(x) (__builtin_bswap32(x) >> 16) 21#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
27#endif
28 22
29#endif /* _ASM_TILE_SWAB_H */ 23#endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/asm/syscalls.h b/arch/tile/include/asm/syscalls.h
index ce99ffefeacf..3b5507c31eae 100644
--- a/arch/tile/include/asm/syscalls.h
+++ b/arch/tile/include/asm/syscalls.h
@@ -32,8 +32,9 @@ extern void *compat_sys_call_table[];
32 32
33/* 33/*
34 * Note that by convention, any syscall which requires the current 34 * Note that by convention, any syscall which requires the current
35 * register set takes an additional "struct pt_regs *" pointer; the 35 * register set takes an additional "struct pt_regs *" pointer; a
36 * sys_xxx() function just adds the pointer and tail-calls to _sys_xxx(). 36 * _sys_xxx() trampoline in intvec*.S just sets up the pointer and
37 * jumps to sys_xxx().
37 */ 38 */
38 39
39/* kernel/sys.c */ 40/* kernel/sys.c */
@@ -43,66 +44,17 @@ long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi,
43int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi, 44int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi,
44 u32 len_lo, u32 len_hi, int advice); 45 u32 len_lo, u32 len_hi, int advice);
45long sys_flush_cache(void); 46long sys_flush_cache(void);
46long sys_mmap2(unsigned long addr, unsigned long len, 47#ifndef __tilegx__ /* No mmap() in the 32-bit kernel. */
47 unsigned long prot, unsigned long flags, 48#define sys_mmap sys_mmap
48 unsigned long fd, unsigned long pgoff);
49#ifdef __tilegx__
50long sys_mmap(unsigned long addr, unsigned long len,
51 unsigned long prot, unsigned long flags,
52 unsigned long fd, off_t pgoff);
53#endif 49#endif
54 50
55/* kernel/process.c */
56long sys_clone(unsigned long clone_flags, unsigned long newsp,
57 void __user *parent_tid, void __user *child_tid);
58long _sys_clone(unsigned long clone_flags, unsigned long newsp,
59 void __user *parent_tid, void __user *child_tid,
60 struct pt_regs *regs);
61long sys_fork(void);
62long _sys_fork(struct pt_regs *regs);
63long sys_vfork(void);
64long _sys_vfork(struct pt_regs *regs);
65long sys_execve(const char __user *filename,
66 const char __user *const __user *argv,
67 const char __user *const __user *envp);
68long _sys_execve(const char __user *filename,
69 const char __user *const __user *argv,
70 const char __user *const __user *envp, struct pt_regs *regs);
71
72/* kernel/signal.c */
73long sys_sigaltstack(const stack_t __user *, stack_t __user *);
74long _sys_sigaltstack(const stack_t __user *, stack_t __user *,
75 struct pt_regs *);
76long sys_rt_sigreturn(void);
77long _sys_rt_sigreturn(struct pt_regs *regs);
78
79/* platform-independent functions */
80long sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize);
81long sys_rt_sigaction(int sig, const struct sigaction __user *act,
82 struct sigaction __user *oact, size_t sigsetsize);
83
84#ifndef __tilegx__ 51#ifndef __tilegx__
85/* mm/fault.c */ 52/* mm/fault.c */
86int sys_cmpxchg_badaddr(unsigned long address); 53long sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *);
87int _sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *); 54long _sys_cmpxchg_badaddr(unsigned long address);
88#endif 55#endif
89 56
90#ifdef CONFIG_COMPAT 57#ifdef CONFIG_COMPAT
91long compat_sys_execve(const char __user *path,
92 const compat_uptr_t __user *argv,
93 const compat_uptr_t __user *envp);
94long _compat_sys_execve(const char __user *path,
95 const compat_uptr_t __user *argv,
96 const compat_uptr_t __user *envp,
97 struct pt_regs *regs);
98long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
99 struct compat_sigaltstack __user *uoss_ptr);
100long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
101 struct compat_sigaltstack __user *uoss_ptr,
102 struct pt_regs *regs);
103long compat_sys_rt_sigreturn(void);
104long _compat_sys_rt_sigreturn(struct pt_regs *regs);
105
106/* These four are not defined for 64-bit, but serve as "compat" syscalls. */ 58/* These four are not defined for 64-bit, but serve as "compat" syscalls. */
107long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg); 59long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg);
108long sys_fstat64(unsigned long fd, struct stat64 __user *statbuf); 60long sys_fstat64(unsigned long fd, struct stat64 __user *statbuf);
@@ -110,4 +62,15 @@ long sys_truncate64(const char __user *path, loff_t length);
110long sys_ftruncate64(unsigned int fd, loff_t length); 62long sys_ftruncate64(unsigned int fd, loff_t length);
111#endif 63#endif
112 64
65/* These are the intvec*.S trampolines. */
66long _sys_sigaltstack(const stack_t __user *, stack_t __user *);
67long _sys_rt_sigreturn(void);
68long _sys_clone(unsigned long clone_flags, unsigned long newsp,
69 void __user *parent_tid, void __user *child_tid);
70long _sys_execve(const char __user *filename,
71 const char __user *const __user *argv,
72 const char __user *const __user *envp);
73
74#include <asm-generic/syscalls.h>
75
113#endif /* _ASM_TILE_SYSCALLS_H */ 76#endif /* _ASM_TILE_SYSCALLS_H */
diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h
index f749be327ce0..23d1842f4839 100644
--- a/arch/tile/include/asm/system.h
+++ b/arch/tile/include/asm/system.h
@@ -89,6 +89,27 @@
89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */ 89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
90#endif 90#endif
91 91
92#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
93#include <hv/syscall_public.h>
94/*
95 * Issue an uncacheable load to each memory controller, then
96 * wait until those loads have completed.
97 */
98static inline void __mb_incoherent(void)
99{
100 long clobber_r10;
101 asm volatile("swint2"
102 : "=R10" (clobber_r10)
103 : "R10" (HV_SYS_fence_incoherent)
104 : "r0", "r1", "r2", "r3", "r4",
105 "r5", "r6", "r7", "r8", "r9",
106 "r11", "r12", "r13", "r14",
107 "r15", "r16", "r17", "r18", "r19",
108 "r20", "r21", "r22", "r23", "r24",
109 "r25", "r26", "r27", "r28", "r29");
110}
111#endif
112
92/* Fence to guarantee visibility of stores to incoherent memory. */ 113/* Fence to guarantee visibility of stores to incoherent memory. */
93static inline void 114static inline void
94mb_incoherent(void) 115mb_incoherent(void)
@@ -97,7 +118,6 @@ mb_incoherent(void)
97 118
98#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() 119#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
99 { 120 {
100 int __mb_incoherent(void);
101#if CHIP_HAS_TILE_WRITE_PENDING() 121#if CHIP_HAS_TILE_WRITE_PENDING()
102 const unsigned long WRITE_TIMEOUT_CYCLES = 400; 122 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
103 unsigned long start = get_cycles_low(); 123 unsigned long start = get_cycles_low();
@@ -161,7 +181,7 @@ extern struct task_struct *_switch_to(struct task_struct *prev,
161/* Helper function for _switch_to(). */ 181/* Helper function for _switch_to(). */
162extern struct task_struct *__switch_to(struct task_struct *prev, 182extern struct task_struct *__switch_to(struct task_struct *prev,
163 struct task_struct *next, 183 struct task_struct *next,
164 unsigned long new_system_save_1_0); 184 unsigned long new_system_save_k_0);
165 185
166/* Address that switched-away from tasks are at. */ 186/* Address that switched-away from tasks are at. */
167extern unsigned long get_switch_to_pc(void); 187extern unsigned long get_switch_to_pc(void);
@@ -214,13 +234,6 @@ int hardwall_deactivate(struct task_struct *task);
214} while (0) 234} while (0)
215#endif 235#endif
216 236
217/* Invoke the simulator "syscall" mechanism (see arch/tile/kernel/entry.S). */
218extern int _sim_syscall(int syscall_num, ...);
219#define sim_syscall(syscall_num, ...) \
220 _sim_syscall(SIM_CONTROL_SYSCALL + \
221 ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS), \
222 ## __VA_ARGS__)
223
224/* 237/*
225 * Kernel threads can check to see if they need to migrate their 238 * Kernel threads can check to see if they need to migrate their
226 * stack whenever they return from a context switch; for user 239 * stack whenever they return from a context switch; for user
diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h
index 3872f2b345d2..bc4f562bd459 100644
--- a/arch/tile/include/asm/thread_info.h
+++ b/arch/tile/include/asm/thread_info.h
@@ -68,6 +68,7 @@ struct thread_info {
68#else 68#else
69#define THREAD_SIZE_ORDER (0) 69#define THREAD_SIZE_ORDER (0)
70#endif 70#endif
71#define THREAD_SIZE_PAGES (1 << THREAD_SIZE_ORDER)
71 72
72#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) 73#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
73#define LOG2_THREAD_SIZE (PAGE_SHIFT + THREAD_SIZE_ORDER) 74#define LOG2_THREAD_SIZE (PAGE_SHIFT + THREAD_SIZE_ORDER)
@@ -83,7 +84,7 @@ register unsigned long stack_pointer __asm__("sp");
83 ((struct thread_info *)(stack_pointer & -THREAD_SIZE)) 84 ((struct thread_info *)(stack_pointer & -THREAD_SIZE))
84 85
85#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 86#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
86extern struct thread_info *alloc_thread_info(struct task_struct *task); 87extern struct thread_info *alloc_thread_info_node(struct task_struct *task, int node);
87extern void free_thread_info(struct thread_info *info); 88extern void free_thread_info(struct thread_info *info);
88 89
89/* Sit on a nap instruction until interrupted. */ 90/* Sit on a nap instruction until interrupted. */
@@ -124,6 +125,7 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
124#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ 125#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
125#define TIF_SECCOMP 6 /* secure computing */ 126#define TIF_SECCOMP 6 /* secure computing */
126#define TIF_MEMDIE 7 /* OOM killer at work */ 127#define TIF_MEMDIE 7 /* OOM killer at work */
128#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
127 129
128#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 130#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
129#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 131#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
@@ -133,10 +135,12 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
133#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 135#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
134#define _TIF_SECCOMP (1<<TIF_SECCOMP) 136#define _TIF_SECCOMP (1<<TIF_SECCOMP)
135#define _TIF_MEMDIE (1<<TIF_MEMDIE) 137#define _TIF_MEMDIE (1<<TIF_MEMDIE)
138#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
136 139
137/* Work to do on any return to user space. */ 140/* Work to do on any return to user space. */
138#define _TIF_ALLWORK_MASK \ 141#define _TIF_ALLWORK_MASK \
139 (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|_TIF_ASYNC_TLB) 142 (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|\
143 _TIF_ASYNC_TLB|_TIF_NOTIFY_RESUME)
140 144
141/* 145/*
142 * Thread-synchronous status. 146 * Thread-synchronous status.
diff --git a/arch/tile/include/asm/timex.h b/arch/tile/include/asm/timex.h
index 3baf5fc4c0a1..29921f0b86da 100644
--- a/arch/tile/include/asm/timex.h
+++ b/arch/tile/include/asm/timex.h
@@ -38,6 +38,9 @@ static inline cycles_t get_cycles(void)
38 38
39cycles_t get_clock_rate(void); 39cycles_t get_clock_rate(void);
40 40
41/* Convert nanoseconds to core clock cycles. */
42cycles_t ns2cycles(unsigned long nsecs);
43
41/* Called at cpu initialization to set some low-level constants. */ 44/* Called at cpu initialization to set some low-level constants. */
42void setup_clock(void); 45void setup_clock(void);
43 46
diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h
index 343172d422a9..6fdd0c860193 100644
--- a/arch/tile/include/asm/topology.h
+++ b/arch/tile/include/asm/topology.h
@@ -44,25 +44,64 @@ static inline const struct cpumask *cpumask_of_node(int node)
44/* For now, use numa node -1 for global allocation. */ 44/* For now, use numa node -1 for global allocation. */
45#define pcibus_to_node(bus) ((void)(bus), -1) 45#define pcibus_to_node(bus) ((void)(bus), -1)
46 46
47/*
48 * TILE architecture has many cores integrated in one processor, so we need
49 * setup bigger balance_interval for both CPU/NODE scheduling domains to
50 * reduce process scheduling costs.
51 */
52
53/* sched_domains SD_CPU_INIT for TILE architecture */
54#define SD_CPU_INIT (struct sched_domain) { \
55 .min_interval = 4, \
56 .max_interval = 128, \
57 .busy_factor = 64, \
58 .imbalance_pct = 125, \
59 .cache_nice_tries = 1, \
60 .busy_idx = 2, \
61 .idle_idx = 1, \
62 .newidle_idx = 0, \
63 .wake_idx = 0, \
64 .forkexec_idx = 0, \
65 \
66 .flags = 1*SD_LOAD_BALANCE \
67 | 1*SD_BALANCE_NEWIDLE \
68 | 1*SD_BALANCE_EXEC \
69 | 1*SD_BALANCE_FORK \
70 | 0*SD_BALANCE_WAKE \
71 | 0*SD_WAKE_AFFINE \
72 | 0*SD_PREFER_LOCAL \
73 | 0*SD_SHARE_CPUPOWER \
74 | 0*SD_SHARE_PKG_RESOURCES \
75 | 0*SD_SERIALIZE \
76 , \
77 .last_balance = jiffies, \
78 .balance_interval = 32, \
79}
80
47/* sched_domains SD_NODE_INIT for TILE architecture */ 81/* sched_domains SD_NODE_INIT for TILE architecture */
48#define SD_NODE_INIT (struct sched_domain) { \ 82#define SD_NODE_INIT (struct sched_domain) { \
49 .min_interval = 8, \ 83 .min_interval = 16, \
50 .max_interval = 32, \ 84 .max_interval = 512, \
51 .busy_factor = 32, \ 85 .busy_factor = 32, \
52 .imbalance_pct = 125, \ 86 .imbalance_pct = 125, \
53 .cache_nice_tries = 1, \ 87 .cache_nice_tries = 1, \
54 .busy_idx = 3, \ 88 .busy_idx = 3, \
55 .idle_idx = 1, \ 89 .idle_idx = 1, \
56 .newidle_idx = 2, \ 90 .newidle_idx = 2, \
57 .wake_idx = 1, \ 91 .wake_idx = 1, \
58 .flags = SD_LOAD_BALANCE \ 92 .flags = 1*SD_LOAD_BALANCE \
59 | SD_BALANCE_NEWIDLE \ 93 | 1*SD_BALANCE_NEWIDLE \
60 | SD_BALANCE_EXEC \ 94 | 1*SD_BALANCE_EXEC \
61 | SD_BALANCE_FORK \ 95 | 1*SD_BALANCE_FORK \
62 | SD_WAKE_AFFINE \ 96 | 0*SD_BALANCE_WAKE \
63 | SD_SERIALIZE, \ 97 | 0*SD_WAKE_AFFINE \
64 .last_balance = jiffies, \ 98 | 0*SD_PREFER_LOCAL \
65 .balance_interval = 1, \ 99 | 0*SD_SHARE_CPUPOWER \
100 | 0*SD_SHARE_PKG_RESOURCES \
101 | 1*SD_SERIALIZE \
102 , \
103 .last_balance = jiffies, \
104 .balance_interval = 128, \
66} 105}
67 106
68/* By definition, we create nodes based on online memory. */ 107/* By definition, we create nodes based on online memory. */
diff --git a/arch/tile/include/asm/traps.h b/arch/tile/include/asm/traps.h
index 432a9c15c8a2..5f20f920f932 100644
--- a/arch/tile/include/asm/traps.h
+++ b/arch/tile/include/asm/traps.h
@@ -15,10 +15,14 @@
15#ifndef _ASM_TILE_TRAPS_H 15#ifndef _ASM_TILE_TRAPS_H
16#define _ASM_TILE_TRAPS_H 16#define _ASM_TILE_TRAPS_H
17 17
18#include <arch/chip.h>
19
18/* mm/fault.c */ 20/* mm/fault.c */
19void do_page_fault(struct pt_regs *, int fault_num, 21void do_page_fault(struct pt_regs *, int fault_num,
20 unsigned long address, unsigned long write); 22 unsigned long address, unsigned long write);
23#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
21void do_async_page_fault(struct pt_regs *); 24void do_async_page_fault(struct pt_regs *);
25#endif
22 26
23#ifndef __tilegx__ 27#ifndef __tilegx__
24/* 28/*
@@ -59,4 +63,8 @@ void do_hardwall_trap(struct pt_regs *, int fault_num);
59void do_breakpoint(struct pt_regs *, int fault_num); 63void do_breakpoint(struct pt_regs *, int fault_num);
60 64
61 65
66#ifdef __tilegx__
67void gx_singlestep_handle(struct pt_regs *, int fault_num);
68#endif
69
62#endif /* _ASM_TILE_SYSCALLS_H */ 70#endif /* _ASM_TILE_SYSCALLS_H */
diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
index f2e3ff485333..f70bf1c541f1 100644
--- a/arch/tile/include/asm/unistd.h
+++ b/arch/tile/include/asm/unistd.h
@@ -15,7 +15,7 @@
15#if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL) 15#if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL)
16#define _ASM_TILE_UNISTD_H 16#define _ASM_TILE_UNISTD_H
17 17
18#ifndef __LP64__ 18#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
19/* Use the flavor of this syscall that matches the 32-bit API better. */ 19/* Use the flavor of this syscall that matches the 32-bit API better. */
20#define __ARCH_WANT_SYNC_FILE_RANGE2 20#define __ARCH_WANT_SYNC_FILE_RANGE2
21#endif 21#endif
@@ -41,6 +41,7 @@ __SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
41#ifdef CONFIG_COMPAT 41#ifdef CONFIG_COMPAT
42#define __ARCH_WANT_SYS_LLSEEK 42#define __ARCH_WANT_SYS_LLSEEK
43#endif 43#endif
44#define __ARCH_WANT_SYS_NEWFSTATAT
44#endif 45#endif
45 46
46#endif /* _ASM_TILE_UNISTD_H */ 47#endif /* _ASM_TILE_UNISTD_H */
diff --git a/arch/tile/lib/mb_incoherent.S b/arch/tile/include/asm/vga.h
index 989ad7b68d5a..7b46e754d611 100644
--- a/arch/tile/lib/mb_incoherent.S
+++ b/arch/tile/include/asm/vga.h
@@ -11,24 +11,29 @@
11 * NON INFRINGEMENT. See the GNU General Public License for 11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details. 12 * more details.
13 * 13 *
14 * Assembly code for invoking the HV's fence_incoherent syscall. 14 * Access to VGA videoram.
15 */ 15 */
16 16
17#include <linux/linkage.h> 17#ifndef _ASM_TILE_VGA_H
18#include <hv/syscall_public.h> 18#define _ASM_TILE_VGA_H
19#include <arch/abi.h>
20#include <arch/chip.h>
21 19
22#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() 20#include <asm/io.h>
23 21
24/* 22#define VT_BUF_HAVE_RW
25 * Invoke the hypervisor's fence_incoherent syscall, which guarantees 23
26 * that all victims for cachelines homed on this tile have reached memory. 24static inline void scr_writew(u16 val, volatile u16 *addr)
27 */ 25{
28STD_ENTRY(__mb_incoherent) 26 __raw_writew(val, (volatile u16 __iomem *) addr);
29 moveli TREG_SYSCALL_NR_NAME, HV_SYS_fence_incoherent 27}
30 swint2 28
31 jrp lr 29static inline u16 scr_readw(volatile const u16 *addr)
32 STD_ENDPROC(__mb_incoherent) 30{
31 return __raw_readw((volatile const u16 __iomem *) addr);
32}
33
34#define vga_readb(a) readb((u8 __iomem *)(a))
35#define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
36
37#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap(x, s))
33 38
34#endif 39#endif
diff --git a/arch/tile/include/hv/drv_mshim_intf.h b/arch/tile/include/hv/drv_mshim_intf.h
new file mode 100644
index 000000000000..c6ef3bdc55cf
--- /dev/null
+++ b/arch/tile/include/hv/drv_mshim_intf.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file drv_mshim_intf.h
17 * Interface definitions for the Linux EDAC memory controller driver.
18 */
19
20#ifndef _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H
21#define _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H
22
23/** Number of memory controllers in the public API. */
24#define TILE_MAX_MSHIMS 4
25
26/** Memory info under each memory controller. */
27struct mshim_mem_info
28{
29 uint64_t mem_size; /**< Total memory size in bytes. */
30 uint8_t mem_type; /**< Memory type, DDR2 or DDR3. */
31 uint8_t mem_ecc; /**< Memory supports ECC. */
32};
33
34/**
35 * DIMM error structure.
36 * For now, only correctable errors are counted and the mshim doesn't record
37 * the error PA. HV takes panic upon uncorrectable errors.
38 */
39struct mshim_mem_error
40{
41 uint32_t sbe_count; /**< Number of single-bit errors. */
42};
43
44/** Read this offset to get the memory info per mshim. */
45#define MSHIM_MEM_INFO_OFF 0x100
46
47/** Read this offset to check DIMM error. */
48#define MSHIM_MEM_ERROR_OFF 0x200
49
50#endif /* _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H */
diff --git a/arch/tile/include/hv/drv_xgbe_impl.h b/arch/tile/include/hv/drv_xgbe_impl.h
new file mode 100644
index 000000000000..3a73b2b44913
--- /dev/null
+++ b/arch/tile/include/hv/drv_xgbe_impl.h
@@ -0,0 +1,300 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file drivers/xgbe/impl.h
17 * Implementation details for the NetIO library.
18 */
19
20#ifndef __DRV_XGBE_IMPL_H__
21#define __DRV_XGBE_IMPL_H__
22
23#include <hv/netio_errors.h>
24#include <hv/netio_intf.h>
25#include <hv/drv_xgbe_intf.h>
26
27
28/** How many groups we have (log2). */
29#define LOG2_NUM_GROUPS (12)
30/** How many groups we have. */
31#define NUM_GROUPS (1 << LOG2_NUM_GROUPS)
32
33/** Number of output requests we'll buffer per tile. */
34#define EPP_REQS_PER_TILE (32)
35
36/** Words used in an eDMA command without checksum acceleration. */
37#define EDMA_WDS_NO_CSUM 8
38/** Words used in an eDMA command with checksum acceleration. */
39#define EDMA_WDS_CSUM 10
40/** Total available words in the eDMA command FIFO. */
41#define EDMA_WDS_TOTAL 128
42
43
44/*
45 * FIXME: These definitions are internal and should have underscores!
46 * NOTE: The actual numeric values here are intentional and allow us to
47 * optimize the concept "if small ... else if large ... else ...", by
48 * checking for the low bit being set, and then for non-zero.
49 * These are used as array indices, so they must have the values (0, 1, 2)
50 * in some order.
51 */
52#define SIZE_SMALL (1) /**< Small packet queue. */
53#define SIZE_LARGE (2) /**< Large packet queue. */
54#define SIZE_JUMBO (0) /**< Jumbo packet queue. */
55
56/** The number of "SIZE_xxx" values. */
57#define NETIO_NUM_SIZES 3
58
59
60/*
61 * Default numbers of packets for IPP drivers. These values are chosen
62 * such that CIPP1 will not overflow its L2 cache.
63 */
64
65/** The default number of small packets. */
66#define NETIO_DEFAULT_SMALL_PACKETS 2750
67/** The default number of large packets. */
68#define NETIO_DEFAULT_LARGE_PACKETS 2500
69/** The default number of jumbo packets. */
70#define NETIO_DEFAULT_JUMBO_PACKETS 250
71
72
73/** Log2 of the size of a memory arena. */
74#define NETIO_ARENA_SHIFT 24 /* 16 MB */
75/** Size of a memory arena. */
76#define NETIO_ARENA_SIZE (1 << NETIO_ARENA_SHIFT)
77
78
79/** A queue of packets.
80 *
81 * This structure partially defines a queue of packets waiting to be
82 * processed. The queue as a whole is written to by an interrupt handler and
83 * read by non-interrupt code; this data structure is what's touched by the
84 * interrupt handler. The other part of the queue state, the read offset, is
85 * kept in user space, not in hypervisor space, so it is in a separate data
86 * structure.
87 *
88 * The read offset (__packet_receive_read in the user part of the queue
89 * structure) points to the next packet to be read. When the read offset is
90 * equal to the write offset, the queue is empty; therefore the queue must
91 * contain one more slot than the required maximum queue size.
92 *
93 * Here's an example of all 3 state variables and what they mean. All
94 * pointers move left to right.
95 *
96 * @code
97 * I I V V V V I I I I
98 * 0 1 2 3 4 5 6 7 8 9 10
99 * ^ ^ ^ ^
100 * | | |
101 * | | __last_packet_plus_one
102 * | __buffer_write
103 * __packet_receive_read
104 * @endcode
105 *
106 * This queue has 10 slots, and thus can hold 9 packets (_last_packet_plus_one
107 * = 10). The read pointer is at 2, and the write pointer is at 6; thus,
108 * there are valid, unread packets in slots 2, 3, 4, and 5. The remaining
109 * slots are invalid (do not contain a packet).
110 */
111typedef struct {
112 /** Byte offset of the next notify packet to be written: zero for the first
113 * packet on the queue, sizeof (netio_pkt_t) for the second packet on the
114 * queue, etc. */
115 volatile uint32_t __packet_write;
116
117 /** Offset of the packet after the last valid packet (i.e., when any
118 * pointer is incremented to this value, it wraps back to zero). */
119 uint32_t __last_packet_plus_one;
120}
121__netio_packet_queue_t;
122
123
124/** A queue of buffers.
125 *
126 * This structure partially defines a queue of empty buffers which have been
127 * obtained via requests to the IPP. (The elements of the queue are packet
128 * handles, which are transformed into a full netio_pkt_t when the buffer is
129 * retrieved.) The queue as a whole is written to by an interrupt handler and
130 * read by non-interrupt code; this data structure is what's touched by the
131 * interrupt handler. The other parts of the queue state, the read offset and
132 * requested write offset, are kept in user space, not in hypervisor space, so
133 * they are in a separate data structure.
134 *
135 * The read offset (__buffer_read in the user part of the queue structure)
136 * points to the next buffer to be read. When the read offset is equal to the
137 * write offset, the queue is empty; therefore the queue must contain one more
138 * slot than the required maximum queue size.
139 *
140 * The requested write offset (__buffer_requested_write in the user part of
141 * the queue structure) points to the slot which will hold the next buffer we
142 * request from the IPP, once we get around to sending such a request. When
143 * the requested write offset is equal to the write offset, no requests for
144 * new buffers are outstanding; when the requested write offset is one greater
145 * than the read offset, no more requests may be sent.
146 *
147 * Note that, unlike the packet_queue, the buffer_queue places incoming
148 * buffers at decreasing addresses. This makes the check for "is it time to
149 * wrap the buffer pointer" cheaper in the assembly code which receives new
150 * buffers, and means that the value which defines the queue size,
151 * __last_buffer, is different than in the packet queue. Also, the offset
152 * used in the packet_queue is already scaled by the size of a packet; here we
153 * use unscaled slot indices for the offsets. (These differences are
154 * historical, and in the future it's possible that the packet_queue will look
155 * more like this queue.)
156 *
157 * @code
158 * Here's an example of all 4 state variables and what they mean. Remember:
159 * all pointers move right to left.
160 *
161 * V V V I I R R V V V
162 * 0 1 2 3 4 5 6 7 8 9
163 * ^ ^ ^ ^
164 * | | | |
165 * | | | __last_buffer
166 * | | __buffer_write
167 * | __buffer_requested_write
168 * __buffer_read
169 * @endcode
170 *
171 * This queue has 10 slots, and thus can hold 9 buffers (_last_buffer = 9).
172 * The read pointer is at 2, and the write pointer is at 6; thus, there are
173 * valid, unread buffers in slots 2, 1, 0, 9, 8, and 7. The requested write
174 * pointer is at 4; thus, requests have been made to the IPP for buffers which
175 * will be placed in slots 6 and 5 when they arrive. Finally, the remaining
176 * slots are invalid (do not contain a buffer).
177 */
178typedef struct
179{
180 /** Ordinal number of the next buffer to be written: 0 for the first slot in
181 * the queue, 1 for the second slot in the queue, etc. */
182 volatile uint32_t __buffer_write;
183
184 /** Ordinal number of the last buffer (i.e., when any pointer is decremented
185 * below zero, it is reloaded with this value). */
186 uint32_t __last_buffer;
187}
188__netio_buffer_queue_t;
189
190
191/**
192 * An object for providing Ethernet packets to a process.
193 */
194typedef struct __netio_queue_impl_t
195{
196 /** The queue of packets waiting to be received. */
197 __netio_packet_queue_t __packet_receive_queue;
198 /** The intr bit mask that IDs this device. */
199 unsigned int __intr_id;
200 /** Offset to queues of empty buffers, one per size. */
201 uint32_t __buffer_queue[NETIO_NUM_SIZES];
202 /** The address of the first EPP tile, or -1 if no EPP. */
203 /* ISSUE: Actually this is always "0" or "~0". */
204 uint32_t __epp_location;
205 /** The queue ID that this queue represents. */
206 unsigned int __queue_id;
207 /** Number of acknowledgements received. */
208 volatile uint32_t __acks_received;
209 /** Last completion number received for packet_sendv. */
210 volatile uint32_t __last_completion_rcv;
211 /** Number of packets allowed to be outstanding. */
212 uint32_t __max_outstanding;
213 /** First VA available for packets. */
214 void* __va_0;
215 /** First VA in second range available for packets. */
216 void* __va_1;
217 /** Padding to align the "__packets" field to the size of a netio_pkt_t. */
218 uint32_t __padding[3];
219 /** The packets themselves. */
220 netio_pkt_t __packets[0];
221}
222netio_queue_impl_t;
223
224
225/**
226 * An object for managing the user end of a NetIO queue.
227 */
228typedef struct __netio_queue_user_impl_t
229{
230 /** The next incoming packet to be read. */
231 uint32_t __packet_receive_read;
232 /** The next empty buffers to be read, one index per size. */
233 uint8_t __buffer_read[NETIO_NUM_SIZES];
234 /** Where the empty buffer we next request from the IPP will go, one index
235 * per size. */
236 uint8_t __buffer_requested_write[NETIO_NUM_SIZES];
237 /** PCIe interface flag. */
238 uint8_t __pcie;
239 /** Number of packets left to be received before we send a credit update. */
240 uint32_t __receive_credit_remaining;
241 /** Value placed in __receive_credit_remaining when it reaches zero. */
242 uint32_t __receive_credit_interval;
243 /** First fast I/O routine index. */
244 uint32_t __fastio_index;
245 /** Number of acknowledgements expected. */
246 uint32_t __acks_outstanding;
247 /** Last completion number requested. */
248 uint32_t __last_completion_req;
249 /** File descriptor for driver. */
250 int __fd;
251}
252netio_queue_user_impl_t;
253
254
255#define NETIO_GROUP_CHUNK_SIZE 64 /**< Max # groups in one IPP request */
256#define NETIO_BUCKET_CHUNK_SIZE 64 /**< Max # buckets in one IPP request */
257
258
259/** Internal structure used to convey packet send information to the
260 * hypervisor. FIXME: Actually, it's not used for that anymore, but
261 * netio_packet_send() still uses it internally.
262 */
263typedef struct
264{
265 uint16_t flags; /**< Packet flags (__NETIO_SEND_FLG_xxx) */
266 uint16_t transfer_size; /**< Size of packet */
267 uint32_t va; /**< VA of start of packet */
268 __netio_pkt_handle_t handle; /**< Packet handle */
269 uint32_t csum0; /**< First checksum word */
270 uint32_t csum1; /**< Second checksum word */
271}
272__netio_send_cmd_t;
273
274
275/** Flags used in two contexts:
276 * - As the "flags" member in the __netio_send_cmd_t, above; used only
277 * for netio_pkt_send_{prepare,commit}.
278 * - As part of the flags passed to the various send packet fast I/O calls.
279 */
280
281/** Need acknowledgement on this packet. Note that some code in the
282 * normal send_pkt fast I/O handler assumes that this is equal to 1. */
283#define __NETIO_SEND_FLG_ACK 0x1
284
285/** Do checksum on this packet. (Only used with the __netio_send_cmd_t;
286 * normal packet sends use a special fast I/O index to denote checksumming,
287 * and multi-segment sends test the checksum descriptor.) */
288#define __NETIO_SEND_FLG_CSUM 0x2
289
290/** Get a completion on this packet. Only used with multi-segment sends. */
291#define __NETIO_SEND_FLG_COMPLETION 0x4
292
293/** Position of the number-of-extra-segments value in the flags word.
294 Only used with multi-segment sends. */
295#define __NETIO_SEND_FLG_XSEG_SHIFT 3
296
297/** Width of the number-of-extra-segments value in the flags word. */
298#define __NETIO_SEND_FLG_XSEG_WIDTH 2
299
300#endif /* __DRV_XGBE_IMPL_H__ */
diff --git a/arch/tile/include/hv/drv_xgbe_intf.h b/arch/tile/include/hv/drv_xgbe_intf.h
new file mode 100644
index 000000000000..f13188ac281a
--- /dev/null
+++ b/arch/tile/include/hv/drv_xgbe_intf.h
@@ -0,0 +1,615 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file drv_xgbe_intf.h
17 * Interface to the hypervisor XGBE driver.
18 */
19
20#ifndef __DRV_XGBE_INTF_H__
21#define __DRV_XGBE_INTF_H__
22
23/**
24 * An object for forwarding VAs and PAs to the hypervisor.
25 * @ingroup types
26 *
27 * This allows the supervisor to specify a number of areas of memory to
28 * store packet buffers.
29 */
30typedef struct
31{
32 /** The physical address of the memory. */
33 HV_PhysAddr pa;
34 /** Page table entry for the memory. This is only used to derive the
35 * memory's caching mode; the PA bits are ignored. */
36 HV_PTE pte;
37 /** The virtual address of the memory. */
38 HV_VirtAddr va;
39 /** Size (in bytes) of the memory area. */
40 int size;
41
42}
43netio_ipp_address_t;
44
45/** The various pread/pwrite offsets into the hypervisor-level driver.
46 * @ingroup types
47 */
48typedef enum
49{
50 /** Inform the Linux driver of the address of the NetIO arena memory.
51 * This offset is actually only used to convey information from netio
52 * to the Linux driver; it never makes it from there to the hypervisor.
53 * Write-only; takes a uint32_t specifying the VA address. */
54 NETIO_FIXED_ADDR = 0x5000000000000000ULL,
55
56 /** Inform the Linux driver of the size of the NetIO arena memory.
57 * This offset is actually only used to convey information from netio
58 * to the Linux driver; it never makes it from there to the hypervisor.
59 * Write-only; takes a uint32_t specifying the VA size. */
60 NETIO_FIXED_SIZE = 0x5100000000000000ULL,
61
62 /** Register current tile with IPP. Write then read: write, takes a
63 * netio_input_config_t, read returns a pointer to a netio_queue_impl_t. */
64 NETIO_IPP_INPUT_REGISTER_OFF = 0x6000000000000000ULL,
65
66 /** Unregister current tile from IPP. Write-only, takes a dummy argument. */
67 NETIO_IPP_INPUT_UNREGISTER_OFF = 0x6100000000000000ULL,
68
69 /** Start packets flowing. Write-only, takes a dummy argument. */
70 NETIO_IPP_INPUT_INIT_OFF = 0x6200000000000000ULL,
71
72 /** Stop packets flowing. Write-only, takes a dummy argument. */
73 NETIO_IPP_INPUT_UNINIT_OFF = 0x6300000000000000ULL,
74
75 /** Configure group (typically we group on VLAN). Write-only: takes an
76 * array of netio_group_t's, low 24 bits of the offset is the base group
77 * number times the size of a netio_group_t. */
78 NETIO_IPP_INPUT_GROUP_CFG_OFF = 0x6400000000000000ULL,
79
80 /** Configure bucket. Write-only: takes an array of netio_bucket_t's, low
81 * 24 bits of the offset is the base bucket number times the size of a
82 * netio_bucket_t. */
83 NETIO_IPP_INPUT_BUCKET_CFG_OFF = 0x6500000000000000ULL,
84
85 /** Get/set a parameter. Read or write: read or write data is the parameter
86 * value, low 32 bits of the offset is a __netio_getset_offset_t. */
87 NETIO_IPP_PARAM_OFF = 0x6600000000000000ULL,
88
89 /** Get fast I/O index. Read-only; returns a 4-byte base index value. */
90 NETIO_IPP_GET_FASTIO_OFF = 0x6700000000000000ULL,
91
92 /** Configure hijack IP address. Packets with this IPv4 dest address
93 * go to bucket NETIO_NUM_BUCKETS - 1. Write-only: takes an IP address
94 * in some standard form. FIXME: Define the form! */
95 NETIO_IPP_INPUT_HIJACK_CFG_OFF = 0x6800000000000000ULL,
96
97 /**
98 * Offsets beyond this point are reserved for the supervisor (although that
99 * enforcement must be done by the supervisor driver itself).
100 */
101 NETIO_IPP_USER_MAX_OFF = 0x6FFFFFFFFFFFFFFFULL,
102
103 /** Register I/O memory. Write-only, takes a netio_ipp_address_t. */
104 NETIO_IPP_IOMEM_REGISTER_OFF = 0x7000000000000000ULL,
105
106 /** Unregister I/O memory. Write-only, takes a netio_ipp_address_t. */
107 NETIO_IPP_IOMEM_UNREGISTER_OFF = 0x7100000000000000ULL,
108
109 /* Offsets greater than 0x7FFFFFFF can't be used directly from Linux
110 * userspace code due to limitations in the pread/pwrite syscalls. */
111
112 /** Drain LIPP buffers. */
113 NETIO_IPP_DRAIN_OFF = 0xFA00000000000000ULL,
114
115 /** Supply a netio_ipp_address_t to be used as shared memory for the
116 * LEPP command queue. */
117 NETIO_EPP_SHM_OFF = 0xFB00000000000000ULL,
118
119 /* 0xFC... is currently unused. */
120
121 /** Stop IPP/EPP tiles. Write-only, takes a dummy argument. */
122 NETIO_IPP_STOP_SHIM_OFF = 0xFD00000000000000ULL,
123
124 /** Start IPP/EPP tiles. Write-only, takes a dummy argument. */
125 NETIO_IPP_START_SHIM_OFF = 0xFE00000000000000ULL,
126
127 /** Supply packet arena. Write-only, takes an array of
128 * netio_ipp_address_t values. */
129 NETIO_IPP_ADDRESS_OFF = 0xFF00000000000000ULL,
130} netio_hv_offset_t;
131
132/** Extract the base offset from an offset */
133#define NETIO_BASE_OFFSET(off) ((off) & 0xFF00000000000000ULL)
134/** Extract the local offset from an offset */
135#define NETIO_LOCAL_OFFSET(off) ((off) & 0x00FFFFFFFFFFFFFFULL)
136
137
138/**
139 * Get/set offset.
140 */
141typedef union
142{
143 struct
144 {
145 uint64_t addr:48; /**< Class-specific address */
146 unsigned int class:8; /**< Class (e.g., NETIO_PARAM) */
147 unsigned int opcode:8; /**< High 8 bits of NETIO_IPP_PARAM_OFF */
148 }
149 bits; /**< Bitfields */
150 uint64_t word; /**< Aggregated value to use as the offset */
151}
152__netio_getset_offset_t;
153
154/**
155 * Fast I/O index offsets (must be contiguous).
156 */
157typedef enum
158{
159 NETIO_FASTIO_ALLOCATE = 0, /**< Get empty packet buffer */
160 NETIO_FASTIO_FREE_BUFFER = 1, /**< Give buffer back to IPP */
161 NETIO_FASTIO_RETURN_CREDITS = 2, /**< Give credits to IPP */
162 NETIO_FASTIO_SEND_PKT_NOCK = 3, /**< Send a packet, no checksum */
163 NETIO_FASTIO_SEND_PKT_CK = 4, /**< Send a packet, with checksum */
164 NETIO_FASTIO_SEND_PKT_VEC = 5, /**< Send a vector of packets */
165 NETIO_FASTIO_SENDV_PKT = 6, /**< Sendv one packet */
166 NETIO_FASTIO_NUM_INDEX = 7, /**< Total number of fast I/O indices */
167} netio_fastio_index_t;
168
169/** 3-word return type for Fast I/O call. */
170typedef struct
171{
172 int err; /**< Error code. */
173 uint32_t val0; /**< Value. Meaning depends upon the specific call. */
174 uint32_t val1; /**< Value. Meaning depends upon the specific call. */
175} netio_fastio_rv3_t;
176
177/** 0-argument fast I/O call */
178int __netio_fastio0(uint32_t fastio_index);
179/** 1-argument fast I/O call */
180int __netio_fastio1(uint32_t fastio_index, uint32_t arg0);
181/** 3-argument fast I/O call, 2-word return value */
182netio_fastio_rv3_t __netio_fastio3_rv3(uint32_t fastio_index, uint32_t arg0,
183 uint32_t arg1, uint32_t arg2);
184/** 4-argument fast I/O call */
185int __netio_fastio4(uint32_t fastio_index, uint32_t arg0, uint32_t arg1,
186 uint32_t arg2, uint32_t arg3);
187/** 6-argument fast I/O call */
188int __netio_fastio6(uint32_t fastio_index, uint32_t arg0, uint32_t arg1,
189 uint32_t arg2, uint32_t arg3, uint32_t arg4, uint32_t arg5);
190/** 9-argument fast I/O call */
191int __netio_fastio9(uint32_t fastio_index, uint32_t arg0, uint32_t arg1,
192 uint32_t arg2, uint32_t arg3, uint32_t arg4, uint32_t arg5,
193 uint32_t arg6, uint32_t arg7, uint32_t arg8);
194
195/** Allocate an empty packet.
196 * @param fastio_index Fast I/O index.
197 * @param size Size of the packet to allocate.
198 */
199#define __netio_fastio_allocate(fastio_index, size) \
200 __netio_fastio1((fastio_index) + NETIO_FASTIO_ALLOCATE, size)
201
202/** Free a buffer.
203 * @param fastio_index Fast I/O index.
204 * @param handle Handle for the packet to free.
205 */
206#define __netio_fastio_free_buffer(fastio_index, handle) \
207 __netio_fastio1((fastio_index) + NETIO_FASTIO_FREE_BUFFER, handle)
208
209/** Increment our receive credits.
210 * @param fastio_index Fast I/O index.
211 * @param credits Number of credits to add.
212 */
213#define __netio_fastio_return_credits(fastio_index, credits) \
214 __netio_fastio1((fastio_index) + NETIO_FASTIO_RETURN_CREDITS, credits)
215
216/** Send packet, no checksum.
217 * @param fastio_index Fast I/O index.
218 * @param ackflag Nonzero if we want an ack.
219 * @param size Size of the packet.
220 * @param va Virtual address of start of packet.
221 * @param handle Packet handle.
222 */
223#define __netio_fastio_send_pkt_nock(fastio_index, ackflag, size, va, handle) \
224 __netio_fastio4((fastio_index) + NETIO_FASTIO_SEND_PKT_NOCK, ackflag, \
225 size, va, handle)
226
227/** Send packet, calculate checksum.
228 * @param fastio_index Fast I/O index.
229 * @param ackflag Nonzero if we want an ack.
230 * @param size Size of the packet.
231 * @param va Virtual address of start of packet.
232 * @param handle Packet handle.
233 * @param csum0 Shim checksum header.
234 * @param csum1 Checksum seed.
235 */
236#define __netio_fastio_send_pkt_ck(fastio_index, ackflag, size, va, handle, \
237 csum0, csum1) \
238 __netio_fastio6((fastio_index) + NETIO_FASTIO_SEND_PKT_CK, ackflag, \
239 size, va, handle, csum0, csum1)
240
241
242/** Format for the "csum0" argument to the __netio_fastio_send routines
243 * and LEPP. Note that this is currently exactly identical to the
244 * ShimProtocolOffloadHeader.
245 */
246typedef union
247{
248 struct
249 {
250 unsigned int start_byte:7; /**< The first byte to be checksummed */
251 unsigned int count:14; /**< Number of bytes to be checksummed. */
252 unsigned int destination_byte:7; /**< The byte to write the checksum to. */
253 unsigned int reserved:4; /**< Reserved. */
254 } bits; /**< Decomposed method of access. */
255 unsigned int word; /**< To send out the IDN. */
256} __netio_checksum_header_t;
257
258
259/** Sendv packet with 1 or 2 segments.
260 * @param fastio_index Fast I/O index.
261 * @param flags Ack/csum/notify flags in low 3 bits; number of segments minus
262 * 1 in next 2 bits; expected checksum in high 16 bits.
263 * @param confno Confirmation number to request, if notify flag set.
264 * @param csum0 Checksum descriptor; if zero, no checksum.
265 * @param va_F Virtual address of first segment.
266 * @param va_L Virtual address of last segment, if 2 segments.
267 * @param len_F_L Length of first segment in low 16 bits; length of last
268 * segment, if 2 segments, in high 16 bits.
269 */
270#define __netio_fastio_sendv_pkt_1_2(fastio_index, flags, confno, csum0, \
271 va_F, va_L, len_F_L) \
272 __netio_fastio6((fastio_index) + NETIO_FASTIO_SENDV_PKT, flags, confno, \
273 csum0, va_F, va_L, len_F_L)
274
275/** Send packet on PCIe interface.
276 * @param fastio_index Fast I/O index.
277 * @param flags Ack/csum/notify flags in low 3 bits.
278 * @param confno Confirmation number to request, if notify flag set.
279 * @param csum0 Checksum descriptor; Hard wired 0, not needed for PCIe.
280 * @param va_F Virtual address of the packet buffer.
281 * @param va_L Virtual address of last segment, if 2 segments. Hard wired 0.
282 * @param len_F_L Length of the packet buffer in low 16 bits.
283 */
284#define __netio_fastio_send_pcie_pkt(fastio_index, flags, confno, csum0, \
285 va_F, va_L, len_F_L) \
286 __netio_fastio6((fastio_index) + PCIE_FASTIO_SENDV_PKT, flags, confno, \
287 csum0, va_F, va_L, len_F_L)
288
289/** Sendv packet with 3 or 4 segments.
290 * @param fastio_index Fast I/O index.
291 * @param flags Ack/csum/notify flags in low 3 bits; number of segments minus
292 * 1 in next 2 bits; expected checksum in high 16 bits.
293 * @param confno Confirmation number to request, if notify flag set.
294 * @param csum0 Checksum descriptor; if zero, no checksum.
295 * @param va_F Virtual address of first segment.
296 * @param va_L Virtual address of last segment (third segment if 3 segments,
297 * fourth segment if 4 segments).
298 * @param len_F_L Length of first segment in low 16 bits; length of last
299 * segment in high 16 bits.
300 * @param va_M0 Virtual address of "middle 0" segment; this segment is sent
301 * second when there are three segments, and third if there are four.
302 * @param va_M1 Virtual address of "middle 1" segment; this segment is sent
303 * second when there are four segments.
304 * @param len_M0_M1 Length of middle 0 segment in low 16 bits; length of middle
305 * 1 segment, if 4 segments, in high 16 bits.
306 */
307#define __netio_fastio_sendv_pkt_3_4(fastio_index, flags, confno, csum0, va_F, \
308 va_L, len_F_L, va_M0, va_M1, len_M0_M1) \
309 __netio_fastio9((fastio_index) + NETIO_FASTIO_SENDV_PKT, flags, confno, \
310 csum0, va_F, va_L, len_F_L, va_M0, va_M1, len_M0_M1)
311
312/** Send vector of packets.
313 * @param fastio_index Fast I/O index.
314 * @param seqno Number of packets transmitted so far on this interface;
315 * used to decide which packets should be acknowledged.
316 * @param nentries Number of entries in vector.
317 * @param va Virtual address of start of vector entry array.
318 * @return 3-word netio_fastio_rv3_t structure. The structure's err member
319 * is an error code, or zero if no error. The val0 member is the
320 * updated value of seqno; it has been incremented by 1 for each
321 * packet sent. That increment may be less than nentries if an
322 * error occurred, or if some of the entries in the vector contain
323 * handles equal to NETIO_PKT_HANDLE_NONE. The val1 member is the
324 * updated value of nentries; it has been decremented by 1 for each
325 * vector entry processed. Again, that decrement may be less than
326 * nentries (leaving the returned value positive) if an error
327 * occurred.
328 */
329#define __netio_fastio_send_pkt_vec(fastio_index, seqno, nentries, va) \
330 __netio_fastio3_rv3((fastio_index) + NETIO_FASTIO_SEND_PKT_VEC, seqno, \
331 nentries, va)
332
333
334/** An egress DMA command for LEPP. */
335typedef struct
336{
337 /** Is this a TSO transfer?
338 *
339 * NOTE: This field is always 0, to distinguish it from
340 * lepp_tso_cmd_t. It must come first!
341 */
342 uint8_t tso : 1;
343
344 /** Unused padding bits. */
345 uint8_t _unused : 3;
346
347 /** Should this packet be sent directly from caches instead of DRAM,
348 * using hash-for-home to locate the packet data?
349 */
350 uint8_t hash_for_home : 1;
351
352 /** Should we compute a checksum? */
353 uint8_t compute_checksum : 1;
354
355 /** Is this the final buffer for this packet?
356 *
357 * A single packet can be split over several input buffers (a "gather"
358 * operation). This flag indicates that this is the last buffer
359 * in a packet.
360 */
361 uint8_t end_of_packet : 1;
362
363 /** Should LEPP advance 'comp_busy' when this DMA is fully finished? */
364 uint8_t send_completion : 1;
365
366 /** High bits of Client Physical Address of the start of the buffer
367 * to be egressed.
368 *
369 * NOTE: Only 6 bits are actually needed here, as CPAs are
370 * currently 38 bits. So two bits could be scavenged from this.
371 */
372 uint8_t cpa_hi;
373
374 /** The number of bytes to be egressed. */
375 uint16_t length;
376
377 /** Low 32 bits of Client Physical Address of the start of the buffer
378 * to be egressed.
379 */
380 uint32_t cpa_lo;
381
382 /** Checksum information (only used if 'compute_checksum'). */
383 __netio_checksum_header_t checksum_data;
384
385} lepp_cmd_t;
386
387
388/** A chunk of physical memory for a TSO egress. */
389typedef struct
390{
391 /** The low bits of the CPA. */
392 uint32_t cpa_lo;
393 /** The high bits of the CPA. */
394 uint16_t cpa_hi : 15;
395 /** Should this packet be sent directly from caches instead of DRAM,
396 * using hash-for-home to locate the packet data?
397 */
398 uint16_t hash_for_home : 1;
399 /** The length in bytes. */
400 uint16_t length;
401} lepp_frag_t;
402
403
404/** An LEPP command that handles TSO. */
405typedef struct
406{
407 /** Is this a TSO transfer?
408 *
409 * NOTE: This field is always 1, to distinguish it from
410 * lepp_cmd_t. It must come first!
411 */
412 uint8_t tso : 1;
413
414 /** Unused padding bits. */
415 uint8_t _unused : 7;
416
417 /** Size of the header[] array in bytes. It must be in the range
418 * [40, 127], which are the smallest header for a TCP packet over
419 * Ethernet and the maximum possible prepend size supported by
420 * hardware, respectively. Note that the array storage must be
421 * padded out to a multiple of four bytes so that the following
422 * LEPP command is aligned properly.
423 */
424 uint8_t header_size;
425
426 /** Byte offset of the IP header in header[]. */
427 uint8_t ip_offset;
428
429 /** Byte offset of the TCP header in header[]. */
430 uint8_t tcp_offset;
431
432 /** The number of bytes to use for the payload of each packet,
433 * except of course the last one, which may not have enough bytes.
434 * This means that each Ethernet packet except the last will have a
435 * size of header_size + payload_size.
436 */
437 uint16_t payload_size;
438
439 /** The length of the 'frags' array that follows this struct. */
440 uint16_t num_frags;
441
442 /** The actual frags. */
443 lepp_frag_t frags[0 /* Variable-sized; num_frags entries. */];
444
445 /*
446 * The packet header template logically follows frags[],
447 * but you can't declare that in C.
448 *
449 * uint32_t header[header_size_in_words_rounded_up];
450 */
451
452} lepp_tso_cmd_t;
453
454
455/** An LEPP completion ring entry. */
456typedef void* lepp_comp_t;
457
458
459/** Maximum number of frags for one TSO command. This is adapted from
460 * linux's "MAX_SKB_FRAGS", and presumably over-estimates by one, for
461 * our page size of exactly 65536. We add one for a "body" fragment.
462 */
463#define LEPP_MAX_FRAGS (65536 / HV_PAGE_SIZE_SMALL + 2 + 1)
464
465/** Total number of bytes needed for an lepp_tso_cmd_t. */
466#define LEPP_TSO_CMD_SIZE(num_frags, header_size) \
467 (sizeof(lepp_tso_cmd_t) + \
468 (num_frags) * sizeof(lepp_frag_t) + \
469 (((header_size) + 3) & -4))
470
471/** The size of the lepp "cmd" queue. */
472#define LEPP_CMD_QUEUE_BYTES \
473 (((CHIP_L2_CACHE_SIZE() - 2 * CHIP_L2_LINE_SIZE()) / \
474 (sizeof(lepp_cmd_t) + sizeof(lepp_comp_t))) * sizeof(lepp_cmd_t))
475
476/** The largest possible command that can go in lepp_queue_t::cmds[]. */
477#define LEPP_MAX_CMD_SIZE LEPP_TSO_CMD_SIZE(LEPP_MAX_FRAGS, 128)
478
479/** The largest possible value of lepp_queue_t::cmd_{head, tail} (inclusive).
480 */
481#define LEPP_CMD_LIMIT \
482 (LEPP_CMD_QUEUE_BYTES - LEPP_MAX_CMD_SIZE)
483
484/** The maximum number of completions in an LEPP queue. */
485#define LEPP_COMP_QUEUE_SIZE \
486 ((LEPP_CMD_LIMIT + sizeof(lepp_cmd_t) - 1) / sizeof(lepp_cmd_t))
487
488/** Increment an index modulo the queue size. */
489#define LEPP_QINC(var) \
490 (var = __insn_mnz(var - (LEPP_COMP_QUEUE_SIZE - 1), var + 1))
491
492/** A queue used to convey egress commands from the client to LEPP. */
493typedef struct
494{
495 /** Index of first completion not yet processed by user code.
496 * If this is equal to comp_busy, there are no such completions.
497 *
498 * NOTE: This is only read/written by the user.
499 */
500 unsigned int comp_head;
501
502 /** Index of first completion record not yet completed.
503 * If this is equal to comp_tail, there are no such completions.
504 * This index gets advanced (modulo LEPP_QUEUE_SIZE) whenever
505 * a command with the 'completion' bit set is finished.
506 *
507 * NOTE: This is only written by LEPP, only read by the user.
508 */
509 volatile unsigned int comp_busy;
510
511 /** Index of the first empty slot in the completion ring.
512 * Entries from this up to but not including comp_head (in ring order)
513 * can be filled in with completion data.
514 *
515 * NOTE: This is only read/written by the user.
516 */
517 unsigned int comp_tail;
518
519 /** Byte index of first command enqueued for LEPP but not yet processed.
520 *
521 * This is always divisible by sizeof(void*) and always <= LEPP_CMD_LIMIT.
522 *
523 * NOTE: LEPP advances this counter as soon as it no longer needs
524 * the cmds[] storage for this entry, but the transfer is not actually
525 * complete (i.e. the buffer pointed to by the command is no longer
526 * needed) until comp_busy advances.
527 *
528 * If this is equal to cmd_tail, the ring is empty.
529 *
530 * NOTE: This is only written by LEPP, only read by the user.
531 */
532 volatile unsigned int cmd_head;
533
534 /** Byte index of first empty slot in the command ring. This field can
535 * be incremented up to but not equal to cmd_head (because that would
536 * mean the ring is empty).
537 *
538 * This is always divisible by sizeof(void*) and always <= LEPP_CMD_LIMIT.
539 *
540 * NOTE: This is read/written by the user, only read by LEPP.
541 */
542 volatile unsigned int cmd_tail;
543
544 /** A ring of variable-sized egress DMA commands.
545 *
546 * NOTE: Only written by the user, only read by LEPP.
547 */
548 char cmds[LEPP_CMD_QUEUE_BYTES]
549 __attribute__((aligned(CHIP_L2_LINE_SIZE())));
550
551 /** A ring of user completion data.
552 * NOTE: Only read/written by the user.
553 */
554 lepp_comp_t comps[LEPP_COMP_QUEUE_SIZE]
555 __attribute__((aligned(CHIP_L2_LINE_SIZE())));
556} lepp_queue_t;
557
558
559/** An internal helper function for determining the number of entries
560 * available in a ring buffer, given that there is one sentinel.
561 */
562static inline unsigned int
563_lepp_num_free_slots(unsigned int head, unsigned int tail)
564{
565 /*
566 * One entry is reserved for use as a sentinel, to distinguish
567 * "empty" from "full". So we compute
568 * (head - tail - 1) % LEPP_QUEUE_SIZE, but without using a slow % operation.
569 */
570 return (head - tail - 1) + ((head <= tail) ? LEPP_COMP_QUEUE_SIZE : 0);
571}
572
573
574/** Returns how many new comp entries can be enqueued. */
575static inline unsigned int
576lepp_num_free_comp_slots(const lepp_queue_t* q)
577{
578 return _lepp_num_free_slots(q->comp_head, q->comp_tail);
579}
580
581static inline int
582lepp_qsub(int v1, int v2)
583{
584 int delta = v1 - v2;
585 return delta + ((delta >> 31) & LEPP_COMP_QUEUE_SIZE);
586}
587
588
589/** FIXME: Check this from linux, via a new "pwrite()" call. */
590#define LIPP_VERSION 1
591
592
593/** We use exactly two bytes of alignment padding. */
594#define LIPP_PACKET_PADDING 2
595
596/** The minimum size of a "small" buffer (including the padding). */
597#define LIPP_SMALL_PACKET_SIZE 128
598
599/*
600 * NOTE: The following two values should total to less than around
601 * 13582, to keep the total size used for "lipp_state_t" below 64K.
602 */
603
604/** The maximum number of "small" buffers.
605 * This is enough for 53 network cpus with 128 credits. Note that
606 * if these are exhausted, we will fall back to using large buffers.
607 */
608#define LIPP_SMALL_BUFFERS 6785
609
610/** The maximum number of "large" buffers.
611 * This is enough for 53 network cpus with 128 credits.
612 */
613#define LIPP_LARGE_BUFFERS 6785
614
615#endif /* __DRV_XGBE_INTF_H__ */
diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/include/hv/hypervisor.h
index 9bd303a141b2..72ec1e972f15 100644
--- a/arch/tile/include/hv/hypervisor.h
+++ b/arch/tile/include/hv/hypervisor.h
@@ -22,8 +22,6 @@
22 22
23#include <arch/chip.h> 23#include <arch/chip.h>
24 24
25#include <hv/pagesize.h>
26
27/* Linux builds want unsigned long constants, but assembler wants numbers */ 25/* Linux builds want unsigned long constants, but assembler wants numbers */
28#ifdef __ASSEMBLER__ 26#ifdef __ASSEMBLER__
29/** One, for assembler */ 27/** One, for assembler */
@@ -44,11 +42,21 @@
44 */ 42 */
45#define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN) 43#define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN)
46 44
45/** The log2 of the size of small pages, in bytes. This value should
46 * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
47 */
48#define HV_LOG2_PAGE_SIZE_SMALL 16
49
47/** The size of small pages, in bytes. This value should be verified 50/** The size of small pages, in bytes. This value should be verified
48 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL). 51 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
49 */ 52 */
50#define HV_PAGE_SIZE_SMALL (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_SMALL) 53#define HV_PAGE_SIZE_SMALL (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_SMALL)
51 54
55/** The log2 of the size of large pages, in bytes. This value should be
56 * verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
57 */
58#define HV_LOG2_PAGE_SIZE_LARGE 24
59
52/** The size of large pages, in bytes. This value should be verified 60/** The size of large pages, in bytes. This value should be verified
53 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE). 61 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
54 */ 62 */
@@ -338,9 +346,10 @@ typedef int HV_Errno;
338#define HV_ENOTREADY -812 /**< Device not ready */ 346#define HV_ENOTREADY -812 /**< Device not ready */
339#define HV_EIO -813 /**< I/O error */ 347#define HV_EIO -813 /**< I/O error */
340#define HV_ENOMEM -814 /**< Out of memory */ 348#define HV_ENOMEM -814 /**< Out of memory */
349#define HV_EAGAIN -815 /**< Try again */
341 350
342#define HV_ERR_MAX -801 /**< Largest HV error code */ 351#define HV_ERR_MAX -801 /**< Largest HV error code */
343#define HV_ERR_MIN -814 /**< Smallest HV error code */ 352#define HV_ERR_MIN -815 /**< Smallest HV error code */
344 353
345#ifndef __ASSEMBLER__ 354#ifndef __ASSEMBLER__
346 355
@@ -867,6 +876,43 @@ typedef struct
867 */ 876 */
868HV_PhysAddrRange hv_inquire_physical(int idx); 877HV_PhysAddrRange hv_inquire_physical(int idx);
869 878
879/** Possible DIMM types. */
880typedef enum
881{
882 NO_DIMM = 0, /**< No DIMM */
883 DDR2 = 1, /**< DDR2 */
884 DDR3 = 2 /**< DDR3 */
885} HV_DIMM_Type;
886
887#ifdef __tilegx__
888
889/** Log2 of minimum DIMM bytes supported by the memory controller. */
890#define HV_MSH_MIN_DIMM_SIZE_SHIFT 29
891
892/** Max number of DIMMs contained by one memory controller. */
893#define HV_MSH_MAX_DIMMS 8
894
895#else
896
897/** Log2 of minimum DIMM bytes supported by the memory controller. */
898#define HV_MSH_MIN_DIMM_SIZE_SHIFT 26
899
900/** Max number of DIMMs contained by one memory controller. */
901#define HV_MSH_MAX_DIMMS 2
902
903#endif
904
905/** Number of bits to right-shift to get the DIMM type. */
906#define HV_DIMM_TYPE_SHIFT 0
907
908/** Bits to mask to get the DIMM type. */
909#define HV_DIMM_TYPE_MASK 0xf
910
911/** Number of bits to right-shift to get the DIMM size. */
912#define HV_DIMM_SIZE_SHIFT 4
913
914/** Bits to mask to get the DIMM size. */
915#define HV_DIMM_SIZE_MASK 0xf
870 916
871/** Memory controller information. */ 917/** Memory controller information. */
872typedef struct 918typedef struct
@@ -964,6 +1010,11 @@ HV_ASIDRange hv_inquire_asid(int idx);
964 1010
965/** Waits for at least the specified number of nanoseconds then returns. 1011/** Waits for at least the specified number of nanoseconds then returns.
966 * 1012 *
1013 * NOTE: this deprecated function currently assumes a 750 MHz clock,
1014 * and is thus not generally suitable for use. New code should call
1015 * hv_sysconf(HV_SYSCONF_CPU_SPEED), compute a cycle count to wait for,
1016 * and delay by looping while checking the cycle counter SPR.
1017 *
967 * @param nanosecs The number of nanoseconds to sleep. 1018 * @param nanosecs The number of nanoseconds to sleep.
968 */ 1019 */
969void hv_nanosleep(int nanosecs); 1020void hv_nanosleep(int nanosecs);
@@ -1003,41 +1054,42 @@ int hv_console_write(HV_VirtAddr bytes, int len);
1003 * when these occur in a client's interrupt critical section, they must 1054 * when these occur in a client's interrupt critical section, they must
1004 * be delivered through the downcall mechanism. 1055 * be delivered through the downcall mechanism.
1005 * 1056 *
1006 * A downcall is initially delivered to the client as an INTCTRL_1 1057 * A downcall is initially delivered to the client as an INTCTRL_CL
1007 * interrupt. Upon entry to the INTCTRL_1 vector, the client must 1058 * interrupt, where CL is the client's PL. Upon entry to the INTCTRL_CL
1008 * immediately invoke the hv_downcall_dispatch service. This service 1059 * vector, the client must immediately invoke the hv_downcall_dispatch
1009 * will not return; instead it will cause one of the client's actual 1060 * service. This service will not return; instead it will cause one of
1010 * downcall-handling interrupt vectors to be entered. The EX_CONTEXT 1061 * the client's actual downcall-handling interrupt vectors to be entered.
1011 * registers in the client will be set so that when the client irets, 1062 * The EX_CONTEXT registers in the client will be set so that when the
1012 * it will return to the code which was interrupted by the INTCTRL_1 1063 * client irets, it will return to the code which was interrupted by the
1013 * interrupt. 1064 * INTCTRL_CL interrupt.
1014 * 1065 *
1015 * Under some circumstances, the firing of INTCTRL_1 can race with 1066 * Under some circumstances, the firing of INTCTRL_CL can race with
1016 * the lowering of a device interrupt. In such a case, the 1067 * the lowering of a device interrupt. In such a case, the
1017 * hv_downcall_dispatch service may issue an iret instruction instead 1068 * hv_downcall_dispatch service may issue an iret instruction instead
1018 * of entering one of the client's actual downcall-handling interrupt 1069 * of entering one of the client's actual downcall-handling interrupt
1019 * vectors. This will return execution to the location that was 1070 * vectors. This will return execution to the location that was
1020 * interrupted by INTCTRL_1. 1071 * interrupted by INTCTRL_CL.
1021 * 1072 *
1022 * Any saving of registers should be done by the actual handling 1073 * Any saving of registers should be done by the actual handling
1023 * vectors; no registers should be changed by the INTCTRL_1 handler. 1074 * vectors; no registers should be changed by the INTCTRL_CL handler.
1024 * In particular, the client should not use a jal instruction to invoke 1075 * In particular, the client should not use a jal instruction to invoke
1025 * the hv_downcall_dispatch service, as that would overwrite the client's 1076 * the hv_downcall_dispatch service, as that would overwrite the client's
1026 * lr register. Note that the hv_downcall_dispatch service may overwrite 1077 * lr register. Note that the hv_downcall_dispatch service may overwrite
1027 * one or more of the client's system save registers. 1078 * one or more of the client's system save registers.
1028 * 1079 *
1029 * The client must not modify the INTCTRL_1_STATUS SPR. The hypervisor 1080 * The client must not modify the INTCTRL_CL_STATUS SPR. The hypervisor
1030 * will set this register to cause a downcall to happen, and will clear 1081 * will set this register to cause a downcall to happen, and will clear
1031 * it when no further downcalls are pending. 1082 * it when no further downcalls are pending.
1032 * 1083 *
1033 * When a downcall vector is entered, the INTCTRL_1 interrupt will be 1084 * When a downcall vector is entered, the INTCTRL_CL interrupt will be
1034 * masked. When the client is done processing a downcall, and is ready 1085 * masked. When the client is done processing a downcall, and is ready
1035 * to accept another, it must unmask this interrupt; if more downcalls 1086 * to accept another, it must unmask this interrupt; if more downcalls
1036 * are pending, this will cause the INTCTRL_1 vector to be reentered. 1087 * are pending, this will cause the INTCTRL_CL vector to be reentered.
1037 * Currently the following interrupt vectors can be entered through a 1088 * Currently the following interrupt vectors can be entered through a
1038 * downcall: 1089 * downcall:
1039 * 1090 *
1040 * INT_MESSAGE_RCV_DWNCL (hypervisor message available) 1091 * INT_MESSAGE_RCV_DWNCL (hypervisor message available)
1092 * INT_DEV_INTR_DWNCL (device interrupt)
1041 * INT_DMATLB_MISS_DWNCL (DMA TLB miss) 1093 * INT_DMATLB_MISS_DWNCL (DMA TLB miss)
1042 * INT_SNITLB_MISS_DWNCL (SNI TLB miss) 1094 * INT_SNITLB_MISS_DWNCL (SNI TLB miss)
1043 * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation) 1095 * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation)
@@ -1296,7 +1348,7 @@ typedef struct
1296 * this operation. If any permanent delivery errors were encountered, 1348 * this operation. If any permanent delivery errors were encountered,
1297 * the routine returns HV_ERECIP. In the event of permanent delivery 1349 * the routine returns HV_ERECIP. In the event of permanent delivery
1298 * errors, it may be the case that delivery was not attempted to all 1350 * errors, it may be the case that delivery was not attempted to all
1299 * recipients; if any messages were succesfully delivered, however, 1351 * recipients; if any messages were successfully delivered, however,
1300 * recipients' state values will be updated appropriately. 1352 * recipients' state values will be updated appropriately.
1301 * 1353 *
1302 * It is explicitly legal to specify a recipient structure whose state 1354 * It is explicitly legal to specify a recipient structure whose state
@@ -1315,7 +1367,7 @@ typedef struct
1315 * never call hv_receive_message, or could register a different state 1367 * never call hv_receive_message, or could register a different state
1316 * buffer, losing the message. 1368 * buffer, losing the message.
1317 * 1369 *
1318 * Specifiying the same recipient more than once in the recipient list 1370 * Specifying the same recipient more than once in the recipient list
1319 * is an error, which will not result in an error return but which may 1371 * is an error, which will not result in an error return but which may
1320 * or may not result in more than one message being delivered to the 1372 * or may not result in more than one message being delivered to the
1321 * recipient tile. 1373 * recipient tile.
diff --git a/arch/tile/include/hv/netio_errors.h b/arch/tile/include/hv/netio_errors.h
new file mode 100644
index 000000000000..e1591bff61b5
--- /dev/null
+++ b/arch/tile/include/hv/netio_errors.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * Error codes returned from NetIO routines.
17 */
18
19#ifndef __NETIO_ERRORS_H__
20#define __NETIO_ERRORS_H__
21
22/**
23 * @addtogroup error
24 *
25 * @brief The error codes returned by NetIO functions.
26 *
27 * NetIO functions return 0 (defined as ::NETIO_NO_ERROR) on success, and
28 * a negative value if an error occurs.
29 *
30 * In cases where a NetIO function failed due to a error reported by
31 * system libraries, the error code will be the negation of the
32 * system errno at the time of failure. The @ref netio_strerror()
33 * function will deliver error strings for both NetIO and system error
34 * codes.
35 *
36 * @{
37 */
38
39/** The set of all NetIO errors. */
40typedef enum
41{
42 /** Operation successfully completed. */
43 NETIO_NO_ERROR = 0,
44
45 /** A packet was successfully retrieved from an input queue. */
46 NETIO_PKT = 0,
47
48 /** Largest NetIO error number. */
49 NETIO_ERR_MAX = -701,
50
51 /** The tile is not registered with the IPP. */
52 NETIO_NOT_REGISTERED = -701,
53
54 /** No packet was available to retrieve from the input queue. */
55 NETIO_NOPKT = -702,
56
57 /** The requested function is not implemented. */
58 NETIO_NOT_IMPLEMENTED = -703,
59
60 /** On a registration operation, the target queue already has the maximum
61 * number of tiles registered for it, and no more may be added. On a
62 * packet send operation, the output queue is full and nothing more can
63 * be queued until some of the queued packets are actually transmitted. */
64 NETIO_QUEUE_FULL = -704,
65
66 /** The calling process or thread is not bound to exactly one CPU. */
67 NETIO_BAD_AFFINITY = -705,
68
69 /** Cannot allocate memory on requested controllers. */
70 NETIO_CANNOT_HOME = -706,
71
72 /** On a registration operation, the IPP specified is not configured
73 * to support the options requested; for instance, the application
74 * wants a specific type of tagged headers which the configured IPP
75 * doesn't support. Or, the supplied configuration information is
76 * not self-consistent, or is out of range; for instance, specifying
77 * both NETIO_RECV and NETIO_NO_RECV, or asking for more than
78 * NETIO_MAX_SEND_BUFFERS to be preallocated. On a VLAN or bucket
79 * configure operation, the number of items, or the base item, was
80 * out of range.
81 */
82 NETIO_BAD_CONFIG = -707,
83
84 /** Too many tiles have registered to transmit packets. */
85 NETIO_TOOMANY_XMIT = -708,
86
87 /** Packet transmission was attempted on a queue which was registered
88 with transmit disabled. */
89 NETIO_UNREG_XMIT = -709,
90
91 /** This tile is already registered with the IPP. */
92 NETIO_ALREADY_REGISTERED = -710,
93
94 /** The Ethernet link is down. The application should try again later. */
95 NETIO_LINK_DOWN = -711,
96
97 /** An invalid memory buffer has been specified. This may be an unmapped
98 * virtual address, or one which does not meet alignment requirements.
99 * For netio_input_register(), this error may be returned when multiple
100 * processes specify different memory regions to be used for NetIO
101 * buffers. That can happen if these processes specify explicit memory
102 * regions with the ::NETIO_FIXED_BUFFER_VA flag, or if tmc_cmem_init()
103 * has not been called by a common ancestor of the processes.
104 */
105 NETIO_FAULT = -712,
106
107 /** Cannot combine user-managed shared memory and cache coherence. */
108 NETIO_BAD_CACHE_CONFIG = -713,
109
110 /** Smallest NetIO error number. */
111 NETIO_ERR_MIN = -713,
112
113#ifndef __DOXYGEN__
114 /** Used internally to mean that no response is needed; never returned to
115 * an application. */
116 NETIO_NO_RESPONSE = 1
117#endif
118} netio_error_t;
119
120/** @} */
121
122#endif /* __NETIO_ERRORS_H__ */
diff --git a/arch/tile/include/hv/netio_intf.h b/arch/tile/include/hv/netio_intf.h
new file mode 100644
index 000000000000..8d20972aba2c
--- /dev/null
+++ b/arch/tile/include/hv/netio_intf.h
@@ -0,0 +1,2975 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * NetIO interface structures and macros.
17 */
18
19#ifndef __NETIO_INTF_H__
20#define __NETIO_INTF_H__
21
22#include <hv/netio_errors.h>
23
24#ifdef __KERNEL__
25#include <linux/types.h>
26#else
27#include <stdint.h>
28#endif
29
30#if !defined(__HV__) && !defined(__BOGUX__) && !defined(__KERNEL__)
31#include <assert.h>
32#define netio_assert assert /**< Enable assertions from macros */
33#else
34#define netio_assert(...) ((void)(0)) /**< Disable assertions from macros */
35#endif
36
37/*
38 * If none of these symbols are defined, we're building libnetio in an
39 * environment where we have pthreads, so we'll enable locking.
40 */
41#if !defined(__HV__) && !defined(__BOGUX__) && !defined(__KERNEL__) && \
42 !defined(__NEWLIB__)
43#define _NETIO_PTHREAD /**< Include a mutex in netio_queue_t below */
44
45/*
46 * If NETIO_UNLOCKED is defined, we don't do use per-cpu locks on
47 * per-packet NetIO operations. We still do pthread locking on things
48 * like netio_input_register, though. This is used for building
49 * libnetio_unlocked.
50 */
51#ifndef NETIO_UNLOCKED
52
53/* Avoid PLT overhead by using our own inlined per-cpu lock. */
54#include <sched.h>
55typedef int _netio_percpu_mutex_t;
56
57static __inline int
58_netio_percpu_mutex_init(_netio_percpu_mutex_t* lock)
59{
60 *lock = 0;
61 return 0;
62}
63
64static __inline int
65_netio_percpu_mutex_lock(_netio_percpu_mutex_t* lock)
66{
67 while (__builtin_expect(__insn_tns(lock), 0))
68 sched_yield();
69 return 0;
70}
71
72static __inline int
73_netio_percpu_mutex_unlock(_netio_percpu_mutex_t* lock)
74{
75 *lock = 0;
76 return 0;
77}
78
79#else /* NETIO_UNLOCKED */
80
81/* Don't do any locking for per-packet NetIO operations. */
82typedef int _netio_percpu_mutex_t;
83#define _netio_percpu_mutex_init(L)
84#define _netio_percpu_mutex_lock(L)
85#define _netio_percpu_mutex_unlock(L)
86
87#endif /* NETIO_UNLOCKED */
88#endif /* !__HV__, !__BOGUX, !__KERNEL__, !__NEWLIB__ */
89
90/** How many tiles can register for a given queue.
91 * @ingroup setup */
92#define NETIO_MAX_TILES_PER_QUEUE 64
93
94
95/** Largest permissible queue identifier.
96 * @ingroup setup */
97#define NETIO_MAX_QUEUE_ID 255
98
99
100#ifndef __DOXYGEN__
101
102/* Metadata packet checksum/ethertype flags. */
103
104/** The L4 checksum has not been calculated. */
105#define _NETIO_PKT_NO_L4_CSUM_SHIFT 0
106#define _NETIO_PKT_NO_L4_CSUM_RMASK 1
107#define _NETIO_PKT_NO_L4_CSUM_MASK \
108 (_NETIO_PKT_NO_L4_CSUM_RMASK << _NETIO_PKT_NO_L4_CSUM_SHIFT)
109
110/** The L3 checksum has not been calculated. */
111#define _NETIO_PKT_NO_L3_CSUM_SHIFT 1
112#define _NETIO_PKT_NO_L3_CSUM_RMASK 1
113#define _NETIO_PKT_NO_L3_CSUM_MASK \
114 (_NETIO_PKT_NO_L3_CSUM_RMASK << _NETIO_PKT_NO_L3_CSUM_SHIFT)
115
116/** The L3 checksum is incorrect (or perhaps has not been calculated). */
117#define _NETIO_PKT_BAD_L3_CSUM_SHIFT 2
118#define _NETIO_PKT_BAD_L3_CSUM_RMASK 1
119#define _NETIO_PKT_BAD_L3_CSUM_MASK \
120 (_NETIO_PKT_BAD_L3_CSUM_RMASK << _NETIO_PKT_BAD_L3_CSUM_SHIFT)
121
122/** The Ethernet packet type is unrecognized. */
123#define _NETIO_PKT_TYPE_UNRECOGNIZED_SHIFT 3
124#define _NETIO_PKT_TYPE_UNRECOGNIZED_RMASK 1
125#define _NETIO_PKT_TYPE_UNRECOGNIZED_MASK \
126 (_NETIO_PKT_TYPE_UNRECOGNIZED_RMASK << \
127 _NETIO_PKT_TYPE_UNRECOGNIZED_SHIFT)
128
129/* Metadata packet type flags. */
130
131/** Where the packet type bits are; this field is the index into
132 * _netio_pkt_info. */
133#define _NETIO_PKT_TYPE_SHIFT 4
134#define _NETIO_PKT_TYPE_RMASK 0x3F
135
136/** How many VLAN tags the packet has, and, if we have two, which one we
137 * actually grouped on. A VLAN within a proprietary (Marvell or Broadcom)
138 * tag is counted here. */
139#define _NETIO_PKT_VLAN_SHIFT 4
140#define _NETIO_PKT_VLAN_RMASK 0x3
141#define _NETIO_PKT_VLAN_MASK \
142 (_NETIO_PKT_VLAN_RMASK << _NETIO_PKT_VLAN_SHIFT)
143#define _NETIO_PKT_VLAN_NONE 0 /* No VLAN tag. */
144#define _NETIO_PKT_VLAN_ONE 1 /* One VLAN tag. */
145#define _NETIO_PKT_VLAN_TWO_OUTER 2 /* Two VLAN tags, outer one used. */
146#define _NETIO_PKT_VLAN_TWO_INNER 3 /* Two VLAN tags, inner one used. */
147
148/** Which proprietary tags the packet has. */
149#define _NETIO_PKT_TAG_SHIFT 6
150#define _NETIO_PKT_TAG_RMASK 0x3
151#define _NETIO_PKT_TAG_MASK \
152 (_NETIO_PKT_TAG_RMASK << _NETIO_PKT_TAG_SHIFT)
153#define _NETIO_PKT_TAG_NONE 0 /* No proprietary tags. */
154#define _NETIO_PKT_TAG_MRVL 1 /* Marvell HyperG.Stack tags. */
155#define _NETIO_PKT_TAG_MRVL_EXT 2 /* HyperG.Stack extended tags. */
156#define _NETIO_PKT_TAG_BRCM 3 /* Broadcom HiGig tags. */
157
158/** Whether a packet has an LLC + SNAP header. */
159#define _NETIO_PKT_SNAP_SHIFT 8
160#define _NETIO_PKT_SNAP_RMASK 0x1
161#define _NETIO_PKT_SNAP_MASK \
162 (_NETIO_PKT_SNAP_RMASK << _NETIO_PKT_SNAP_SHIFT)
163
164/* NOTE: Bits 9 and 10 are unused. */
165
166/** Length of any custom data before the L2 header, in words. */
167#define _NETIO_PKT_CUSTOM_LEN_SHIFT 11
168#define _NETIO_PKT_CUSTOM_LEN_RMASK 0x1F
169#define _NETIO_PKT_CUSTOM_LEN_MASK \
170 (_NETIO_PKT_CUSTOM_LEN_RMASK << _NETIO_PKT_CUSTOM_LEN_SHIFT)
171
172/** The L4 checksum is incorrect (or perhaps has not been calculated). */
173#define _NETIO_PKT_BAD_L4_CSUM_SHIFT 16
174#define _NETIO_PKT_BAD_L4_CSUM_RMASK 0x1
175#define _NETIO_PKT_BAD_L4_CSUM_MASK \
176 (_NETIO_PKT_BAD_L4_CSUM_RMASK << _NETIO_PKT_BAD_L4_CSUM_SHIFT)
177
178/** Length of the L2 header, in words. */
179#define _NETIO_PKT_L2_LEN_SHIFT 17
180#define _NETIO_PKT_L2_LEN_RMASK 0x1F
181#define _NETIO_PKT_L2_LEN_MASK \
182 (_NETIO_PKT_L2_LEN_RMASK << _NETIO_PKT_L2_LEN_SHIFT)
183
184
185/* Flags in minimal packet metadata. */
186
187/** We need an eDMA checksum on this packet. */
188#define _NETIO_PKT_NEED_EDMA_CSUM_SHIFT 0
189#define _NETIO_PKT_NEED_EDMA_CSUM_RMASK 1
190#define _NETIO_PKT_NEED_EDMA_CSUM_MASK \
191 (_NETIO_PKT_NEED_EDMA_CSUM_RMASK << _NETIO_PKT_NEED_EDMA_CSUM_SHIFT)
192
193/* Data within the packet information table. */
194
195/* Note that, for efficiency, code which uses these fields assumes that none
196 * of the shift values below are zero. See uses below for an explanation. */
197
198/** Offset within the L2 header of the innermost ethertype (in halfwords). */
199#define _NETIO_PKT_INFO_ETYPE_SHIFT 6
200#define _NETIO_PKT_INFO_ETYPE_RMASK 0x1F
201
202/** Offset within the L2 header of the VLAN tag (in halfwords). */
203#define _NETIO_PKT_INFO_VLAN_SHIFT 11
204#define _NETIO_PKT_INFO_VLAN_RMASK 0x1F
205
206#endif
207
208
209/** The size of a memory buffer representing a small packet.
210 * @ingroup egress */
211#define SMALL_PACKET_SIZE 256
212
213/** The size of a memory buffer representing a large packet.
214 * @ingroup egress */
215#define LARGE_PACKET_SIZE 2048
216
217/** The size of a memory buffer representing a jumbo packet.
218 * @ingroup egress */
219#define JUMBO_PACKET_SIZE (12 * 1024)
220
221
222/* Common ethertypes.
223 * @ingroup ingress */
224/** @{ */
225/** The ethertype of IPv4. */
226#define ETHERTYPE_IPv4 (0x0800)
227/** The ethertype of ARP. */
228#define ETHERTYPE_ARP (0x0806)
229/** The ethertype of VLANs. */
230#define ETHERTYPE_VLAN (0x8100)
231/** The ethertype of a Q-in-Q header. */
232#define ETHERTYPE_Q_IN_Q (0x9100)
233/** The ethertype of IPv6. */
234#define ETHERTYPE_IPv6 (0x86DD)
235/** The ethertype of MPLS. */
236#define ETHERTYPE_MPLS (0x8847)
237/** @} */
238
239
240/** The possible return values of NETIO_PKT_STATUS.
241 * @ingroup ingress
242 */
243typedef enum
244{
245 /** No problems were detected with this packet. */
246 NETIO_PKT_STATUS_OK,
247 /** The packet is undersized; this is expected behavior if the packet's
248 * ethertype is unrecognized, but otherwise the packet is likely corrupt. */
249 NETIO_PKT_STATUS_UNDERSIZE,
250 /** The packet is oversized and some trailing bytes have been discarded.
251 This is expected behavior for short packets, since it's impossible to
252 precisely determine the amount of padding which may have been added to
253 them to make them meet the minimum Ethernet packet size. */
254 NETIO_PKT_STATUS_OVERSIZE,
255 /** The packet was judged to be corrupt by hardware (for instance, it had
256 a bad CRC, or part of it was discarded due to lack of buffer space in
257 the I/O shim) and should be discarded. */
258 NETIO_PKT_STATUS_BAD
259} netio_pkt_status_t;
260
261
262/** Log2 of how many buckets we have. */
263#define NETIO_LOG2_NUM_BUCKETS (10)
264
265/** How many buckets we have.
266 * @ingroup ingress */
267#define NETIO_NUM_BUCKETS (1 << NETIO_LOG2_NUM_BUCKETS)
268
269
270/**
271 * @brief A group-to-bucket identifier.
272 *
273 * @ingroup setup
274 *
275 * This tells us what to do with a given group.
276 */
277typedef union {
278 /** The header broken down into bits. */
279 struct {
280 /** Whether we should balance on L4, if available */
281 unsigned int __balance_on_l4:1;
282 /** Whether we should balance on L3, if available */
283 unsigned int __balance_on_l3:1;
284 /** Whether we should balance on L2, if available */
285 unsigned int __balance_on_l2:1;
286 /** Reserved for future use */
287 unsigned int __reserved:1;
288 /** The base bucket to use to send traffic */
289 unsigned int __bucket_base:NETIO_LOG2_NUM_BUCKETS;
290 /** The mask to apply to the balancing value. This must be one less
291 * than a power of two, e.g. 0x3 or 0xFF.
292 */
293 unsigned int __bucket_mask:NETIO_LOG2_NUM_BUCKETS;
294 /** Pad to 32 bits */
295 unsigned int __padding:(32 - 4 - 2 * NETIO_LOG2_NUM_BUCKETS);
296 } bits;
297 /** To send out the IDN. */
298 unsigned int word;
299}
300netio_group_t;
301
302
303/**
304 * @brief A VLAN-to-bucket identifier.
305 *
306 * @ingroup setup
307 *
308 * This tells us what to do with a given VLAN.
309 */
310typedef netio_group_t netio_vlan_t;
311
312
313/**
314 * A bucket-to-queue mapping.
315 * @ingroup setup
316 */
317typedef unsigned char netio_bucket_t;
318
319
320/**
321 * A packet size can always fit in a netio_size_t.
322 * @ingroup setup
323 */
324typedef unsigned int netio_size_t;
325
326
327/**
328 * @brief Ethernet standard (ingress) packet metadata.
329 *
330 * @ingroup ingress
331 *
332 * This is additional data associated with each packet.
333 * This structure is opaque and accessed through the @ref ingress.
334 *
335 * Also, the buffer population operation currently assumes that standard
336 * metadata is at least as large as minimal metadata, and will need to be
337 * modified if that is no longer the case.
338 */
339typedef struct
340{
341#ifdef __DOXYGEN__
342 /** This structure is opaque. */
343 unsigned char opaque[24];
344#else
345 /** The overall ordinal of the packet */
346 unsigned int __packet_ordinal;
347 /** The ordinal of the packet within the group */
348 unsigned int __group_ordinal;
349 /** The best flow hash IPP could compute. */
350 unsigned int __flow_hash;
351 /** Flags pertaining to checksum calculation, packet type, etc. */
352 unsigned int __flags;
353 /** The first word of "user data". */
354 unsigned int __user_data_0;
355 /** The second word of "user data". */
356 unsigned int __user_data_1;
357#endif
358}
359netio_pkt_metadata_t;
360
361
362/** To ensure that the L3 header is aligned mod 4, the L2 header should be
363 * aligned mod 4 plus 2, since every supported L2 header is 4n + 2 bytes
364 * long. The standard way to do this is to simply add 2 bytes of padding
365 * before the L2 header.
366 */
367#define NETIO_PACKET_PADDING 2
368
369
370
371/**
372 * @brief Ethernet minimal (egress) packet metadata.
373 *
374 * @ingroup egress
375 *
376 * This structure represents information about packets which have
377 * been processed by @ref netio_populate_buffer() or
378 * @ref netio_populate_prepend_buffer(). This structure is opaque
379 * and accessed through the @ref egress.
380 *
381 * @internal This structure is actually copied into the memory used by
382 * standard metadata, which is assumed to be large enough.
383 */
384typedef struct
385{
386#ifdef __DOXYGEN__
387 /** This structure is opaque. */
388 unsigned char opaque[14];
389#else
390 /** The offset of the L2 header from the start of the packet data. */
391 unsigned short l2_offset;
392 /** The offset of the L3 header from the start of the packet data. */
393 unsigned short l3_offset;
394 /** Where to write the checksum. */
395 unsigned char csum_location;
396 /** Where to start checksumming from. */
397 unsigned char csum_start;
398 /** Flags pertaining to checksum calculation etc. */
399 unsigned short flags;
400 /** The L2 length of the packet. */
401 unsigned short l2_length;
402 /** The checksum with which to seed the checksum generator. */
403 unsigned short csum_seed;
404 /** How much to checksum. */
405 unsigned short csum_length;
406#endif
407}
408netio_pkt_minimal_metadata_t;
409
410
411#ifndef __DOXYGEN__
412
413/**
414 * @brief An I/O notification header.
415 *
416 * This is the first word of data received from an I/O shim in a notification
417 * packet. It contains framing and status information.
418 */
419typedef union
420{
421 unsigned int word; /**< The whole word. */
422 /** The various fields. */
423 struct
424 {
425 unsigned int __channel:7; /**< Resource channel. */
426 unsigned int __type:4; /**< Type. */
427 unsigned int __ack:1; /**< Whether an acknowledgement is needed. */
428 unsigned int __reserved:1; /**< Reserved. */
429 unsigned int __protocol:1; /**< A protocol-specific word is added. */
430 unsigned int __status:2; /**< Status of the transfer. */
431 unsigned int __framing:2; /**< Framing of the transfer. */
432 unsigned int __transfer_size:14; /**< Transfer size in bytes (total). */
433 } bits;
434}
435__netio_pkt_notif_t;
436
437
438/**
439 * Returns the base address of the packet.
440 */
441#define _NETIO_PKT_HANDLE_BASE(p) \
442 ((unsigned char*)((p).word & 0xFFFFFFC0))
443
444/**
445 * Returns the base address of the packet.
446 */
447#define _NETIO_PKT_BASE(p) \
448 _NETIO_PKT_HANDLE_BASE(p->__packet)
449
450/**
451 * @brief An I/O notification packet (second word)
452 *
453 * This is the second word of data received from an I/O shim in a notification
454 * packet. This is the virtual address of the packet buffer, plus some flag
455 * bits. (The virtual address of the packet is always 256-byte aligned so we
456 * have room for 8 bits' worth of flags in the low 8 bits.)
457 *
458 * @internal
459 * NOTE: The low two bits must contain "__queue", so the "packet size"
460 * (SIZE_SMALL, SIZE_LARGE, or SIZE_JUMBO) can be determined quickly.
461 *
462 * If __addr or __offset are moved, _NETIO_PKT_BASE
463 * (defined right below this) must be changed.
464 */
465typedef union
466{
467 unsigned int word; /**< The whole word. */
468 /** The various fields. */
469 struct
470 {
471 /** Which queue the packet will be returned to once it is sent back to
472 the IPP. This is one of the SIZE_xxx values. */
473 unsigned int __queue:2;
474
475 /** The IPP handle of the sending IPP. */
476 unsigned int __ipp_handle:2;
477
478 /** Reserved for future use. */
479 unsigned int __reserved:1;
480
481 /** If 1, this packet has minimal (egress) metadata; otherwise, it
482 has standard (ingress) metadata. */
483 unsigned int __minimal:1;
484
485 /** Offset of the metadata within the packet. This value is multiplied
486 * by 64 and added to the base packet address to get the metadata
487 * address. Note that this field is aligned within the word such that
488 * you can easily extract the metadata address with a 26-bit mask. */
489 unsigned int __offset:2;
490
491 /** The top 24 bits of the packet's virtual address. */
492 unsigned int __addr:24;
493 } bits;
494}
495__netio_pkt_handle_t;
496
497#endif /* !__DOXYGEN__ */
498
499
500/**
501 * @brief A handle for an I/O packet's storage.
502 * @ingroup ingress
503 *
504 * netio_pkt_handle_t encodes the concept of a ::netio_pkt_t with its
505 * packet metadata removed. It is a much smaller type that exists to
506 * facilitate applications where the full ::netio_pkt_t type is too
507 * large, such as those that cache enormous numbers of packets or wish
508 * to transmit packet descriptors over the UDN.
509 *
510 * Because there is no metadata, most ::netio_pkt_t operations cannot be
511 * performed on a netio_pkt_handle_t. It supports only
512 * netio_free_handle() (to free the buffer) and
513 * NETIO_PKT_CUSTOM_DATA_H() (to access a pointer to its contents).
514 * The application must acquire any additional metadata it wants from the
515 * original ::netio_pkt_t and record it separately.
516 *
517 * A netio_pkt_handle_t can be extracted from a ::netio_pkt_t by calling
518 * NETIO_PKT_HANDLE(). An invalid handle (analogous to NULL) can be
519 * created by assigning the value ::NETIO_PKT_HANDLE_NONE. A handle can
520 * be tested for validity with NETIO_PKT_HANDLE_IS_VALID().
521 */
522typedef struct
523{
524 unsigned int word; /**< Opaque bits. */
525} netio_pkt_handle_t;
526
527/**
528 * @brief A packet descriptor.
529 *
530 * @ingroup ingress
531 * @ingroup egress
532 *
533 * This data structure represents a packet. The structure is manipulated
534 * through the @ref ingress and the @ref egress.
535 *
536 * While the contents of a netio_pkt_t are opaque, the structure itself is
537 * portable. This means that it may be shared between all tiles which have
538 * done a netio_input_register() call for the interface on which the pkt_t
539 * was initially received (via netio_get_packet()) or retrieved (via
540 * netio_get_buffer()). The contents of a netio_pkt_t can be transmitted to
541 * another tile via shared memory, or via a UDN message, or by other means.
542 * The destination tile may then use the pkt_t as if it had originally been
543 * received locally; it may read or write the packet's data, read its
544 * metadata, free the packet, send the packet, transfer the netio_pkt_t to
545 * yet another tile, and so forth.
546 *
547 * Once a netio_pkt_t has been transferred to a second tile, the first tile
548 * should not reference the original copy; in particular, if more than one
549 * tile frees or sends the same netio_pkt_t, the IPP's packet free lists will
550 * become corrupted. Note also that each tile which reads or modifies
551 * packet data must obey the memory coherency rules outlined in @ref input.
552 */
553typedef struct
554{
555#ifdef __DOXYGEN__
556 /** This structure is opaque. */
557 unsigned char opaque[32];
558#else
559 /** For an ingress packet (one with standard metadata), this is the
560 * notification header we got from the I/O shim. For an egress packet
561 * (one with minimal metadata), this word is zero if the packet has not
562 * been populated, and nonzero if it has. */
563 __netio_pkt_notif_t __notif_header;
564
565 /** Virtual address of the packet buffer, plus state flags. */
566 __netio_pkt_handle_t __packet;
567
568 /** Metadata associated with the packet. */
569 netio_pkt_metadata_t __metadata;
570#endif
571}
572netio_pkt_t;
573
574
575#ifndef __DOXYGEN__
576
577#define __NETIO_PKT_NOTIF_HEADER(pkt) ((pkt)->__notif_header)
578#define __NETIO_PKT_IPP_HANDLE(pkt) ((pkt)->__packet.bits.__ipp_handle)
579#define __NETIO_PKT_QUEUE(pkt) ((pkt)->__packet.bits.__queue)
580#define __NETIO_PKT_NOTIF_HEADER_M(mda, pkt) ((pkt)->__notif_header)
581#define __NETIO_PKT_IPP_HANDLE_M(mda, pkt) ((pkt)->__packet.bits.__ipp_handle)
582#define __NETIO_PKT_MINIMAL(pkt) ((pkt)->__packet.bits.__minimal)
583#define __NETIO_PKT_QUEUE_M(mda, pkt) ((pkt)->__packet.bits.__queue)
584#define __NETIO_PKT_FLAGS_M(mda, pkt) ((mda)->__flags)
585
586/* Packet information table, used by the attribute access functions below. */
587extern const uint16_t _netio_pkt_info[];
588
589#endif /* __DOXYGEN__ */
590
591
592#ifndef __DOXYGEN__
593/* These macros are deprecated and will disappear in a future MDE release. */
594#define NETIO_PKT_GOOD_CHECKSUM(pkt) \
595 NETIO_PKT_L4_CSUM_CORRECT(pkt)
596#define NETIO_PKT_GOOD_CHECKSUM_M(mda, pkt) \
597 NETIO_PKT_L4_CSUM_CORRECT_M(mda, pkt)
598#endif /* __DOXYGEN__ */
599
600
601/* Packet attribute access functions. */
602
603/** Return a pointer to the metadata for a packet.
604 * @ingroup ingress
605 *
606 * Calling this function once and passing the result to other retrieval
607 * functions with a "_M" suffix usually improves performance. This
608 * function must be called on an 'ingress' packet (i.e. one retrieved
609 * by @ref netio_get_packet(), on which @ref netio_populate_buffer() or
610 * @ref netio_populate_prepend_buffer have not been called). Use of this
611 * function on an 'egress' packet will cause an assertion failure.
612 *
613 * @param[in] pkt Packet on which to operate.
614 * @return A pointer to the packet's standard metadata.
615 */
616static __inline netio_pkt_metadata_t*
617NETIO_PKT_METADATA(netio_pkt_t* pkt)
618{
619 netio_assert(!pkt->__packet.bits.__minimal);
620 return &pkt->__metadata;
621}
622
623
624/** Return a pointer to the minimal metadata for a packet.
625 * @ingroup egress
626 *
627 * Calling this function once and passing the result to other retrieval
628 * functions with a "_MM" suffix usually improves performance. This
629 * function must be called on an 'egress' packet (i.e. one on which
630 * @ref netio_populate_buffer() or @ref netio_populate_prepend_buffer()
631 * have been called, or one retrieved by @ref netio_get_buffer()). Use of
632 * this function on an 'ingress' packet will cause an assertion failure.
633 *
634 * @param[in] pkt Packet on which to operate.
635 * @return A pointer to the packet's standard metadata.
636 */
637static __inline netio_pkt_minimal_metadata_t*
638NETIO_PKT_MINIMAL_METADATA(netio_pkt_t* pkt)
639{
640 netio_assert(pkt->__packet.bits.__minimal);
641 return (netio_pkt_minimal_metadata_t*) &pkt->__metadata;
642}
643
644
645/** Determine whether a packet has 'minimal' metadata.
646 * @ingroup pktfuncs
647 *
648 * This function will return nonzero if the packet is an 'egress'
649 * packet (i.e. one on which @ref netio_populate_buffer() or
650 * @ref netio_populate_prepend_buffer() have been called, or one
651 * retrieved by @ref netio_get_buffer()), and zero if the packet
652 * is an 'ingress' packet (i.e. one retrieved by @ref netio_get_packet(),
653 * which has not been converted into an 'egress' packet).
654 *
655 * @param[in] pkt Packet on which to operate.
656 * @return Nonzero if the packet has minimal metadata.
657 */
658static __inline unsigned int
659NETIO_PKT_IS_MINIMAL(netio_pkt_t* pkt)
660{
661 return pkt->__packet.bits.__minimal;
662}
663
664
665/** Return a handle for a packet's storage.
666 * @ingroup pktfuncs
667 *
668 * @param[in] pkt Packet on which to operate.
669 * @return A handle for the packet's storage.
670 */
671static __inline netio_pkt_handle_t
672NETIO_PKT_HANDLE(netio_pkt_t* pkt)
673{
674 netio_pkt_handle_t h;
675 h.word = pkt->__packet.word;
676 return h;
677}
678
679
680/** A special reserved value indicating the absence of a packet handle.
681 *
682 * @ingroup pktfuncs
683 */
684#define NETIO_PKT_HANDLE_NONE ((netio_pkt_handle_t) { 0 })
685
686
687/** Test whether a packet handle is valid.
688 *
689 * Applications may wish to use the reserved value NETIO_PKT_HANDLE_NONE
690 * to indicate no packet at all. This function tests to see if a packet
691 * handle is a real handle, not this special reserved value.
692 *
693 * @ingroup pktfuncs
694 *
695 * @param[in] handle Handle on which to operate.
696 * @return One if the packet handle is valid, else zero.
697 */
698static __inline unsigned int
699NETIO_PKT_HANDLE_IS_VALID(netio_pkt_handle_t handle)
700{
701 return handle.word != 0;
702}
703
704
705
706/** Return a pointer to the start of the packet's custom header.
707 * A custom header may or may not be present, depending upon the IPP; its
708 * contents and alignment are also IPP-dependent. Currently, none of the
709 * standard IPPs supplied by Tilera produce a custom header. If present,
710 * the custom header precedes the L2 header in the packet buffer.
711 * @ingroup ingress
712 *
713 * @param[in] handle Handle on which to operate.
714 * @return A pointer to start of the packet.
715 */
716static __inline unsigned char*
717NETIO_PKT_CUSTOM_DATA_H(netio_pkt_handle_t handle)
718{
719 return _NETIO_PKT_HANDLE_BASE(handle) + NETIO_PACKET_PADDING;
720}
721
722
723/** Return the length of the packet's custom header.
724 * A custom header may or may not be present, depending upon the IPP; its
725 * contents and alignment are also IPP-dependent. Currently, none of the
726 * standard IPPs supplied by Tilera produce a custom header. If present,
727 * the custom header precedes the L2 header in the packet buffer.
728 *
729 * @ingroup ingress
730 *
731 * @param[in] mda Pointer to packet's standard metadata.
732 * @param[in] pkt Packet on which to operate.
733 * @return The length of the packet's custom header, in bytes.
734 */
735static __inline netio_size_t
736NETIO_PKT_CUSTOM_HEADER_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
737{
738 /*
739 * Note that we effectively need to extract a quantity from the flags word
740 * which is measured in words, and then turn it into bytes by shifting
741 * it left by 2. We do this all at once by just shifting right two less
742 * bits, and shifting the mask up two bits.
743 */
744 return ((mda->__flags >> (_NETIO_PKT_CUSTOM_LEN_SHIFT - 2)) &
745 (_NETIO_PKT_CUSTOM_LEN_RMASK << 2));
746}
747
748
749/** Return the length of the packet, starting with the custom header.
750 * A custom header may or may not be present, depending upon the IPP; its
751 * contents and alignment are also IPP-dependent. Currently, none of the
752 * standard IPPs supplied by Tilera produce a custom header. If present,
753 * the custom header precedes the L2 header in the packet buffer.
754 * @ingroup ingress
755 *
756 * @param[in] mda Pointer to packet's standard metadata.
757 * @param[in] pkt Packet on which to operate.
758 * @return The length of the packet, in bytes.
759 */
760static __inline netio_size_t
761NETIO_PKT_CUSTOM_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
762{
763 return (__NETIO_PKT_NOTIF_HEADER(pkt).bits.__transfer_size -
764 NETIO_PACKET_PADDING);
765}
766
767
768/** Return a pointer to the start of the packet's custom header.
769 * A custom header may or may not be present, depending upon the IPP; its
770 * contents and alignment are also IPP-dependent. Currently, none of the
771 * standard IPPs supplied by Tilera produce a custom header. If present,
772 * the custom header precedes the L2 header in the packet buffer.
773 * @ingroup ingress
774 *
775 * @param[in] mda Pointer to packet's standard metadata.
776 * @param[in] pkt Packet on which to operate.
777 * @return A pointer to start of the packet.
778 */
779static __inline unsigned char*
780NETIO_PKT_CUSTOM_DATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
781{
782 return NETIO_PKT_CUSTOM_DATA_H(NETIO_PKT_HANDLE(pkt));
783}
784
785
786/** Return the length of the packet's L2 (Ethernet plus VLAN or SNAP) header.
787 * @ingroup ingress
788 *
789 * @param[in] mda Pointer to packet's standard metadata.
790 * @param[in] pkt Packet on which to operate.
791 * @return The length of the packet's L2 header, in bytes.
792 */
793static __inline netio_size_t
794NETIO_PKT_L2_HEADER_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
795{
796 /*
797 * Note that we effectively need to extract a quantity from the flags word
798 * which is measured in words, and then turn it into bytes by shifting
799 * it left by 2. We do this all at once by just shifting right two less
800 * bits, and shifting the mask up two bits. We then add two bytes.
801 */
802 return ((mda->__flags >> (_NETIO_PKT_L2_LEN_SHIFT - 2)) &
803 (_NETIO_PKT_L2_LEN_RMASK << 2)) + 2;
804}
805
806
807/** Return the length of the packet, starting with the L2 (Ethernet) header.
808 * @ingroup ingress
809 *
810 * @param[in] mda Pointer to packet's standard metadata.
811 * @param[in] pkt Packet on which to operate.
812 * @return The length of the packet, in bytes.
813 */
814static __inline netio_size_t
815NETIO_PKT_L2_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
816{
817 return (NETIO_PKT_CUSTOM_LENGTH_M(mda, pkt) -
818 NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda,pkt));
819}
820
821
822/** Return a pointer to the start of the packet's L2 (Ethernet) header.
823 * @ingroup ingress
824 *
825 * @param[in] mda Pointer to packet's standard metadata.
826 * @param[in] pkt Packet on which to operate.
827 * @return A pointer to start of the packet.
828 */
829static __inline unsigned char*
830NETIO_PKT_L2_DATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
831{
832 return (NETIO_PKT_CUSTOM_DATA_M(mda, pkt) +
833 NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda, pkt));
834}
835
836
837/** Retrieve the length of the packet, starting with the L3 (generally,
838 * the IP) header.
839 * @ingroup ingress
840 *
841 * @param[in] mda Pointer to packet's standard metadata.
842 * @param[in] pkt Packet on which to operate.
843 * @return Length of the packet's L3 header and data, in bytes.
844 */
845static __inline netio_size_t
846NETIO_PKT_L3_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
847{
848 return (NETIO_PKT_L2_LENGTH_M(mda, pkt) -
849 NETIO_PKT_L2_HEADER_LENGTH_M(mda,pkt));
850}
851
852
853/** Return a pointer to the packet's L3 (generally, the IP) header.
854 * @ingroup ingress
855 *
856 * Note that we guarantee word alignment of the L3 header.
857 *
858 * @param[in] mda Pointer to packet's standard metadata.
859 * @param[in] pkt Packet on which to operate.
860 * @return A pointer to the packet's L3 header.
861 */
862static __inline unsigned char*
863NETIO_PKT_L3_DATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
864{
865 return (NETIO_PKT_L2_DATA_M(mda, pkt) +
866 NETIO_PKT_L2_HEADER_LENGTH_M(mda, pkt));
867}
868
869
870/** Return the ordinal of the packet.
871 * @ingroup ingress
872 *
873 * Each packet is given an ordinal number when it is delivered by the IPP.
874 * In the medium term, the ordinal is unique and monotonically increasing,
875 * being incremented by 1 for each packet; the ordinal of the first packet
876 * delivered after the IPP starts is zero. (Since the ordinal is of finite
877 * size, given enough input packets, it will eventually wrap around to zero;
878 * in the long term, therefore, ordinals are not unique.) The ordinals
879 * handed out by different IPPs are not disjoint, so two packets from
880 * different IPPs may have identical ordinals. Packets dropped by the
881 * IPP or by the I/O shim are not assigned ordinals.
882 *
883 * @param[in] mda Pointer to packet's standard metadata.
884 * @param[in] pkt Packet on which to operate.
885 * @return The packet's per-IPP packet ordinal.
886 */
887static __inline unsigned int
888NETIO_PKT_ORDINAL_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
889{
890 return mda->__packet_ordinal;
891}
892
893
894/** Return the per-group ordinal of the packet.
895 * @ingroup ingress
896 *
897 * Each packet is given a per-group ordinal number when it is
898 * delivered by the IPP. By default, the group is the packet's VLAN,
899 * although IPP can be recompiled to use different values. In
900 * the medium term, the ordinal is unique and monotonically
901 * increasing, being incremented by 1 for each packet; the ordinal of
902 * the first packet distributed to a particular group is zero.
903 * (Since the ordinal is of finite size, given enough input packets,
904 * it will eventually wrap around to zero; in the long term,
905 * therefore, ordinals are not unique.) The ordinals handed out by
906 * different IPPs are not disjoint, so two packets from different IPPs
907 * may have identical ordinals; similarly, packets distributed to
908 * different groups may have identical ordinals. Packets dropped by
909 * the IPP or by the I/O shim are not assigned ordinals.
910 *
911 * @param[in] mda Pointer to packet's standard metadata.
912 * @param[in] pkt Packet on which to operate.
913 * @return The packet's per-IPP, per-group ordinal.
914 */
915static __inline unsigned int
916NETIO_PKT_GROUP_ORDINAL_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
917{
918 return mda->__group_ordinal;
919}
920
921
922/** Return the VLAN ID assigned to the packet.
923 * @ingroup ingress
924 *
925 * This value is usually contained within the packet header.
926 *
927 * This value will be zero if the packet does not have a VLAN tag, or if
928 * this value was not extracted from the packet.
929 *
930 * @param[in] mda Pointer to packet's standard metadata.
931 * @param[in] pkt Packet on which to operate.
932 * @return The packet's VLAN ID.
933 */
934static __inline unsigned short
935NETIO_PKT_VLAN_ID_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
936{
937 int vl = (mda->__flags >> _NETIO_PKT_VLAN_SHIFT) & _NETIO_PKT_VLAN_RMASK;
938 unsigned short* pkt_p;
939 int index;
940 unsigned short val;
941
942 if (vl == _NETIO_PKT_VLAN_NONE)
943 return 0;
944
945 pkt_p = (unsigned short*) NETIO_PKT_L2_DATA_M(mda, pkt);
946 index = (mda->__flags >> _NETIO_PKT_TYPE_SHIFT) & _NETIO_PKT_TYPE_RMASK;
947
948 val = pkt_p[(_netio_pkt_info[index] >> _NETIO_PKT_INFO_VLAN_SHIFT) &
949 _NETIO_PKT_INFO_VLAN_RMASK];
950
951#ifdef __TILECC__
952 return (__insn_bytex(val) >> 16) & 0xFFF;
953#else
954 return (__builtin_bswap32(val) >> 16) & 0xFFF;
955#endif
956}
957
958
959/** Return the ethertype of the packet.
960 * @ingroup ingress
961 *
962 * This value is usually contained within the packet header.
963 *
964 * This value is reliable if @ref NETIO_PKT_ETHERTYPE_RECOGNIZED_M()
965 * returns true, and otherwise, may not be well defined.
966 *
967 * @param[in] mda Pointer to packet's standard metadata.
968 * @param[in] pkt Packet on which to operate.
969 * @return The packet's ethertype.
970 */
971static __inline unsigned short
972NETIO_PKT_ETHERTYPE_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
973{
974 unsigned short* pkt_p = (unsigned short*) NETIO_PKT_L2_DATA_M(mda, pkt);
975 int index = (mda->__flags >> _NETIO_PKT_TYPE_SHIFT) & _NETIO_PKT_TYPE_RMASK;
976
977 unsigned short val =
978 pkt_p[(_netio_pkt_info[index] >> _NETIO_PKT_INFO_ETYPE_SHIFT) &
979 _NETIO_PKT_INFO_ETYPE_RMASK];
980
981 return __builtin_bswap32(val) >> 16;
982}
983
984
985/** Return the flow hash computed on the packet.
986 * @ingroup ingress
987 *
988 * For TCP and UDP packets, this hash is calculated by hashing together
989 * the "5-tuple" values, specifically the source IP address, destination
990 * IP address, protocol type, source port and destination port.
991 * The hash value is intended to be helpful for millions of distinct
992 * flows.
993 *
994 * For IPv4 or IPv6 packets which are neither TCP nor UDP, the flow hash is
995 * derived by hashing together the source and destination IP addresses.
996 *
997 * For MPLS-encapsulated packets, the flow hash is derived by hashing
998 * the first MPLS label.
999 *
1000 * For all other packets the flow hash is computed from the source
1001 * and destination Ethernet addresses.
1002 *
1003 * The hash is symmetric, meaning it produces the same value if the
1004 * source and destination are swapped. The only exceptions are
1005 * tunneling protocols 0x04 (IP in IP Encapsulation), 0x29 (Simple
1006 * Internet Protocol), 0x2F (General Routing Encapsulation) and 0x32
1007 * (Encap Security Payload), which use only the destination address
1008 * since the source address is not meaningful.
1009 *
1010 * @param[in] mda Pointer to packet's standard metadata.
1011 * @param[in] pkt Packet on which to operate.
1012 * @return The packet's 32-bit flow hash.
1013 */
1014static __inline unsigned int
1015NETIO_PKT_FLOW_HASH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1016{
1017 return mda->__flow_hash;
1018}
1019
1020
1021/** Return the first word of "user data" for the packet.
1022 *
1023 * The contents of the user data words depend on the IPP.
1024 *
1025 * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the first
1026 * word of user data contains the least significant bits of the 64-bit
1027 * arrival cycle count (see @c get_cycle_count_low()).
1028 *
1029 * See the <em>System Programmer's Guide</em> for details.
1030 *
1031 * @ingroup ingress
1032 *
1033 * @param[in] mda Pointer to packet's standard metadata.
1034 * @param[in] pkt Packet on which to operate.
1035 * @return The packet's first word of "user data".
1036 */
1037static __inline unsigned int
1038NETIO_PKT_USER_DATA_0_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1039{
1040 return mda->__user_data_0;
1041}
1042
1043
1044/** Return the second word of "user data" for the packet.
1045 *
1046 * The contents of the user data words depend on the IPP.
1047 *
1048 * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the second
1049 * word of user data contains the most significant bits of the 64-bit
1050 * arrival cycle count (see @c get_cycle_count_high()).
1051 *
1052 * See the <em>System Programmer's Guide</em> for details.
1053 *
1054 * @ingroup ingress
1055 *
1056 * @param[in] mda Pointer to packet's standard metadata.
1057 * @param[in] pkt Packet on which to operate.
1058 * @return The packet's second word of "user data".
1059 */
1060static __inline unsigned int
1061NETIO_PKT_USER_DATA_1_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1062{
1063 return mda->__user_data_1;
1064}
1065
1066
1067/** Determine whether the L4 (TCP/UDP) checksum was calculated.
1068 * @ingroup ingress
1069 *
1070 * @param[in] mda Pointer to packet's standard metadata.
1071 * @param[in] pkt Packet on which to operate.
1072 * @return Nonzero if the L4 checksum was calculated.
1073 */
1074static __inline unsigned int
1075NETIO_PKT_L4_CSUM_CALCULATED_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1076{
1077 return !(mda->__flags & _NETIO_PKT_NO_L4_CSUM_MASK);
1078}
1079
1080
1081/** Determine whether the L4 (TCP/UDP) checksum was calculated and found to
1082 * be correct.
1083 * @ingroup ingress
1084 *
1085 * @param[in] mda Pointer to packet's standard metadata.
1086 * @param[in] pkt Packet on which to operate.
1087 * @return Nonzero if the checksum was calculated and is correct.
1088 */
1089static __inline unsigned int
1090NETIO_PKT_L4_CSUM_CORRECT_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1091{
1092 return !(mda->__flags &
1093 (_NETIO_PKT_BAD_L4_CSUM_MASK | _NETIO_PKT_NO_L4_CSUM_MASK));
1094}
1095
1096
1097/** Determine whether the L3 (IP) checksum was calculated.
1098 * @ingroup ingress
1099 *
1100 * @param[in] mda Pointer to packet's standard metadata.
1101 * @param[in] pkt Packet on which to operate.
1102 * @return Nonzero if the L3 (IP) checksum was calculated.
1103*/
1104static __inline unsigned int
1105NETIO_PKT_L3_CSUM_CALCULATED_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1106{
1107 return !(mda->__flags & _NETIO_PKT_NO_L3_CSUM_MASK);
1108}
1109
1110
1111/** Determine whether the L3 (IP) checksum was calculated and found to be
1112 * correct.
1113 * @ingroup ingress
1114 *
1115 * @param[in] mda Pointer to packet's standard metadata.
1116 * @param[in] pkt Packet on which to operate.
1117 * @return Nonzero if the checksum was calculated and is correct.
1118 */
1119static __inline unsigned int
1120NETIO_PKT_L3_CSUM_CORRECT_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1121{
1122 return !(mda->__flags &
1123 (_NETIO_PKT_BAD_L3_CSUM_MASK | _NETIO_PKT_NO_L3_CSUM_MASK));
1124}
1125
1126
1127/** Determine whether the ethertype was recognized and L3 packet data was
1128 * processed.
1129 * @ingroup ingress
1130 *
1131 * @param[in] mda Pointer to packet's standard metadata.
1132 * @param[in] pkt Packet on which to operate.
1133 * @return Nonzero if the ethertype was recognized and L3 packet data was
1134 * processed.
1135 */
1136static __inline unsigned int
1137NETIO_PKT_ETHERTYPE_RECOGNIZED_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1138{
1139 return !(mda->__flags & _NETIO_PKT_TYPE_UNRECOGNIZED_MASK);
1140}
1141
1142
1143/** Retrieve the status of a packet and any errors that may have occurred
1144 * during ingress processing (length mismatches, CRC errors, etc.).
1145 * @ingroup ingress
1146 *
1147 * Note that packets for which @ref NETIO_PKT_ETHERTYPE_RECOGNIZED()
1148 * returns zero are always reported as underlength, as there is no a priori
1149 * means to determine their length. Normally, applications should use
1150 * @ref NETIO_PKT_BAD_M() instead of explicitly checking status with this
1151 * function.
1152 *
1153 * @param[in] mda Pointer to packet's standard metadata.
1154 * @param[in] pkt Packet on which to operate.
1155 * @return The packet's status.
1156 */
1157static __inline netio_pkt_status_t
1158NETIO_PKT_STATUS_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1159{
1160 return (netio_pkt_status_t) __NETIO_PKT_NOTIF_HEADER(pkt).bits.__status;
1161}
1162
1163
1164/** Report whether a packet is bad (i.e., was shorter than expected based on
1165 * its headers, or had a bad CRC).
1166 * @ingroup ingress
1167 *
1168 * Note that this function does not verify L3 or L4 checksums.
1169 *
1170 * @param[in] mda Pointer to packet's standard metadata.
1171 * @param[in] pkt Packet on which to operate.
1172 * @return Nonzero if the packet is bad and should be discarded.
1173 */
1174static __inline unsigned int
1175NETIO_PKT_BAD_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1176{
1177 return ((NETIO_PKT_STATUS_M(mda, pkt) & 1) &&
1178 (NETIO_PKT_ETHERTYPE_RECOGNIZED_M(mda, pkt) ||
1179 NETIO_PKT_STATUS_M(mda, pkt) == NETIO_PKT_STATUS_BAD));
1180}
1181
1182
1183/** Return the length of the packet, starting with the L2 (Ethernet) header.
1184 * @ingroup egress
1185 *
1186 * @param[in] mmd Pointer to packet's minimal metadata.
1187 * @param[in] pkt Packet on which to operate.
1188 * @return The length of the packet, in bytes.
1189 */
1190static __inline netio_size_t
1191NETIO_PKT_L2_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
1192{
1193 return mmd->l2_length;
1194}
1195
1196
1197/** Return the length of the L2 (Ethernet) header.
1198 * @ingroup egress
1199 *
1200 * @param[in] mmd Pointer to packet's minimal metadata.
1201 * @param[in] pkt Packet on which to operate.
1202 * @return The length of the packet's L2 header, in bytes.
1203 */
1204static __inline netio_size_t
1205NETIO_PKT_L2_HEADER_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd,
1206 netio_pkt_t* pkt)
1207{
1208 return mmd->l3_offset - mmd->l2_offset;
1209}
1210
1211
1212/** Return the length of the packet, starting with the L3 (IP) header.
1213 * @ingroup egress
1214 *
1215 * @param[in] mmd Pointer to packet's minimal metadata.
1216 * @param[in] pkt Packet on which to operate.
1217 * @return Length of the packet's L3 header and data, in bytes.
1218 */
1219static __inline netio_size_t
1220NETIO_PKT_L3_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
1221{
1222 return (NETIO_PKT_L2_LENGTH_MM(mmd, pkt) -
1223 NETIO_PKT_L2_HEADER_LENGTH_MM(mmd, pkt));
1224}
1225
1226
1227/** Return a pointer to the packet's L3 (generally, the IP) header.
1228 * @ingroup egress
1229 *
1230 * Note that we guarantee word alignment of the L3 header.
1231 *
1232 * @param[in] mmd Pointer to packet's minimal metadata.
1233 * @param[in] pkt Packet on which to operate.
1234 * @return A pointer to the packet's L3 header.
1235 */
1236static __inline unsigned char*
1237NETIO_PKT_L3_DATA_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
1238{
1239 return _NETIO_PKT_BASE(pkt) + mmd->l3_offset;
1240}
1241
1242
1243/** Return a pointer to the packet's L2 (Ethernet) header.
1244 * @ingroup egress
1245 *
1246 * @param[in] mmd Pointer to packet's minimal metadata.
1247 * @param[in] pkt Packet on which to operate.
1248 * @return A pointer to start of the packet.
1249 */
1250static __inline unsigned char*
1251NETIO_PKT_L2_DATA_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
1252{
1253 return _NETIO_PKT_BASE(pkt) + mmd->l2_offset;
1254}
1255
1256
1257/** Retrieve the status of a packet and any errors that may have occurred
1258 * during ingress processing (length mismatches, CRC errors, etc.).
1259 * @ingroup ingress
1260 *
1261 * Note that packets for which @ref NETIO_PKT_ETHERTYPE_RECOGNIZED()
1262 * returns zero are always reported as underlength, as there is no a priori
1263 * means to determine their length. Normally, applications should use
1264 * @ref NETIO_PKT_BAD() instead of explicitly checking status with this
1265 * function.
1266 *
1267 * @param[in] pkt Packet on which to operate.
1268 * @return The packet's status.
1269 */
1270static __inline netio_pkt_status_t
1271NETIO_PKT_STATUS(netio_pkt_t* pkt)
1272{
1273 netio_assert(!pkt->__packet.bits.__minimal);
1274
1275 return (netio_pkt_status_t) __NETIO_PKT_NOTIF_HEADER(pkt).bits.__status;
1276}
1277
1278
1279/** Report whether a packet is bad (i.e., was shorter than expected based on
1280 * its headers, or had a bad CRC).
1281 * @ingroup ingress
1282 *
1283 * Note that this function does not verify L3 or L4 checksums.
1284 *
1285 * @param[in] pkt Packet on which to operate.
1286 * @return Nonzero if the packet is bad and should be discarded.
1287 */
1288static __inline unsigned int
1289NETIO_PKT_BAD(netio_pkt_t* pkt)
1290{
1291 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1292
1293 return NETIO_PKT_BAD_M(mda, pkt);
1294}
1295
1296
1297/** Return the length of the packet's custom header.
1298 * A custom header may or may not be present, depending upon the IPP; its
1299 * contents and alignment are also IPP-dependent. Currently, none of the
1300 * standard IPPs supplied by Tilera produce a custom header. If present,
1301 * the custom header precedes the L2 header in the packet buffer.
1302 * @ingroup pktfuncs
1303 *
1304 * @param[in] pkt Packet on which to operate.
1305 * @return The length of the packet's custom header, in bytes.
1306 */
1307static __inline netio_size_t
1308NETIO_PKT_CUSTOM_HEADER_LENGTH(netio_pkt_t* pkt)
1309{
1310 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1311
1312 return NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda, pkt);
1313}
1314
1315
1316/** Return the length of the packet, starting with the custom header.
1317 * A custom header may or may not be present, depending upon the IPP; its
1318 * contents and alignment are also IPP-dependent. Currently, none of the
1319 * standard IPPs supplied by Tilera produce a custom header. If present,
1320 * the custom header precedes the L2 header in the packet buffer.
1321 * @ingroup pktfuncs
1322 *
1323 * @param[in] pkt Packet on which to operate.
1324 * @return The length of the packet, in bytes.
1325 */
1326static __inline netio_size_t
1327NETIO_PKT_CUSTOM_LENGTH(netio_pkt_t* pkt)
1328{
1329 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1330
1331 return NETIO_PKT_CUSTOM_LENGTH_M(mda, pkt);
1332}
1333
1334
1335/** Return a pointer to the packet's custom header.
1336 * A custom header may or may not be present, depending upon the IPP; its
1337 * contents and alignment are also IPP-dependent. Currently, none of the
1338 * standard IPPs supplied by Tilera produce a custom header. If present,
1339 * the custom header precedes the L2 header in the packet buffer.
1340 * @ingroup pktfuncs
1341 *
1342 * @param[in] pkt Packet on which to operate.
1343 * @return A pointer to start of the packet.
1344 */
1345static __inline unsigned char*
1346NETIO_PKT_CUSTOM_DATA(netio_pkt_t* pkt)
1347{
1348 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1349
1350 return NETIO_PKT_CUSTOM_DATA_M(mda, pkt);
1351}
1352
1353
1354/** Return the length of the packet's L2 (Ethernet plus VLAN or SNAP) header.
1355 * @ingroup pktfuncs
1356 *
1357 * @param[in] pkt Packet on which to operate.
1358 * @return The length of the packet's L2 header, in bytes.
1359 */
1360static __inline netio_size_t
1361NETIO_PKT_L2_HEADER_LENGTH(netio_pkt_t* pkt)
1362{
1363 if (NETIO_PKT_IS_MINIMAL(pkt))
1364 {
1365 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1366
1367 return NETIO_PKT_L2_HEADER_LENGTH_MM(mmd, pkt);
1368 }
1369 else
1370 {
1371 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1372
1373 return NETIO_PKT_L2_HEADER_LENGTH_M(mda, pkt);
1374 }
1375}
1376
1377
1378/** Return the length of the packet, starting with the L2 (Ethernet) header.
1379 * @ingroup pktfuncs
1380 *
1381 * @param[in] pkt Packet on which to operate.
1382 * @return The length of the packet, in bytes.
1383 */
1384static __inline netio_size_t
1385NETIO_PKT_L2_LENGTH(netio_pkt_t* pkt)
1386{
1387 if (NETIO_PKT_IS_MINIMAL(pkt))
1388 {
1389 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1390
1391 return NETIO_PKT_L2_LENGTH_MM(mmd, pkt);
1392 }
1393 else
1394 {
1395 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1396
1397 return NETIO_PKT_L2_LENGTH_M(mda, pkt);
1398 }
1399}
1400
1401
1402/** Return a pointer to the packet's L2 (Ethernet) header.
1403 * @ingroup pktfuncs
1404 *
1405 * @param[in] pkt Packet on which to operate.
1406 * @return A pointer to start of the packet.
1407 */
1408static __inline unsigned char*
1409NETIO_PKT_L2_DATA(netio_pkt_t* pkt)
1410{
1411 if (NETIO_PKT_IS_MINIMAL(pkt))
1412 {
1413 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1414
1415 return NETIO_PKT_L2_DATA_MM(mmd, pkt);
1416 }
1417 else
1418 {
1419 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1420
1421 return NETIO_PKT_L2_DATA_M(mda, pkt);
1422 }
1423}
1424
1425
1426/** Retrieve the length of the packet, starting with the L3 (generally, the IP)
1427 * header.
1428 * @ingroup pktfuncs
1429 *
1430 * @param[in] pkt Packet on which to operate.
1431 * @return Length of the packet's L3 header and data, in bytes.
1432 */
1433static __inline netio_size_t
1434NETIO_PKT_L3_LENGTH(netio_pkt_t* pkt)
1435{
1436 if (NETIO_PKT_IS_MINIMAL(pkt))
1437 {
1438 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1439
1440 return NETIO_PKT_L3_LENGTH_MM(mmd, pkt);
1441 }
1442 else
1443 {
1444 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1445
1446 return NETIO_PKT_L3_LENGTH_M(mda, pkt);
1447 }
1448}
1449
1450
1451/** Return a pointer to the packet's L3 (generally, the IP) header.
1452 * @ingroup pktfuncs
1453 *
1454 * Note that we guarantee word alignment of the L3 header.
1455 *
1456 * @param[in] pkt Packet on which to operate.
1457 * @return A pointer to the packet's L3 header.
1458 */
1459static __inline unsigned char*
1460NETIO_PKT_L3_DATA(netio_pkt_t* pkt)
1461{
1462 if (NETIO_PKT_IS_MINIMAL(pkt))
1463 {
1464 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1465
1466 return NETIO_PKT_L3_DATA_MM(mmd, pkt);
1467 }
1468 else
1469 {
1470 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1471
1472 return NETIO_PKT_L3_DATA_M(mda, pkt);
1473 }
1474}
1475
1476
1477/** Return the ordinal of the packet.
1478 * @ingroup ingress
1479 *
1480 * Each packet is given an ordinal number when it is delivered by the IPP.
1481 * In the medium term, the ordinal is unique and monotonically increasing,
1482 * being incremented by 1 for each packet; the ordinal of the first packet
1483 * delivered after the IPP starts is zero. (Since the ordinal is of finite
1484 * size, given enough input packets, it will eventually wrap around to zero;
1485 * in the long term, therefore, ordinals are not unique.) The ordinals
1486 * handed out by different IPPs are not disjoint, so two packets from
1487 * different IPPs may have identical ordinals. Packets dropped by the
1488 * IPP or by the I/O shim are not assigned ordinals.
1489 *
1490 *
1491 * @param[in] pkt Packet on which to operate.
1492 * @return The packet's per-IPP packet ordinal.
1493 */
1494static __inline unsigned int
1495NETIO_PKT_ORDINAL(netio_pkt_t* pkt)
1496{
1497 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1498
1499 return NETIO_PKT_ORDINAL_M(mda, pkt);
1500}
1501
1502
1503/** Return the per-group ordinal of the packet.
1504 * @ingroup ingress
1505 *
1506 * Each packet is given a per-group ordinal number when it is
1507 * delivered by the IPP. By default, the group is the packet's VLAN,
1508 * although IPP can be recompiled to use different values. In
1509 * the medium term, the ordinal is unique and monotonically
1510 * increasing, being incremented by 1 for each packet; the ordinal of
1511 * the first packet distributed to a particular group is zero.
1512 * (Since the ordinal is of finite size, given enough input packets,
1513 * it will eventually wrap around to zero; in the long term,
1514 * therefore, ordinals are not unique.) The ordinals handed out by
1515 * different IPPs are not disjoint, so two packets from different IPPs
1516 * may have identical ordinals; similarly, packets distributed to
1517 * different groups may have identical ordinals. Packets dropped by
1518 * the IPP or by the I/O shim are not assigned ordinals.
1519 *
1520 * @param[in] pkt Packet on which to operate.
1521 * @return The packet's per-IPP, per-group ordinal.
1522 */
1523static __inline unsigned int
1524NETIO_PKT_GROUP_ORDINAL(netio_pkt_t* pkt)
1525{
1526 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1527
1528 return NETIO_PKT_GROUP_ORDINAL_M(mda, pkt);
1529}
1530
1531
1532/** Return the VLAN ID assigned to the packet.
1533 * @ingroup ingress
1534 *
1535 * This is usually also contained within the packet header. If the packet
1536 * does not have a VLAN tag, the VLAN ID returned by this function is zero.
1537 *
1538 * @param[in] pkt Packet on which to operate.
1539 * @return The packet's VLAN ID.
1540 */
1541static __inline unsigned short
1542NETIO_PKT_VLAN_ID(netio_pkt_t* pkt)
1543{
1544 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1545
1546 return NETIO_PKT_VLAN_ID_M(mda, pkt);
1547}
1548
1549
1550/** Return the ethertype of the packet.
1551 * @ingroup ingress
1552 *
1553 * This value is reliable if @ref NETIO_PKT_ETHERTYPE_RECOGNIZED()
1554 * returns true, and otherwise, may not be well defined.
1555 *
1556 * @param[in] pkt Packet on which to operate.
1557 * @return The packet's ethertype.
1558 */
1559static __inline unsigned short
1560NETIO_PKT_ETHERTYPE(netio_pkt_t* pkt)
1561{
1562 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1563
1564 return NETIO_PKT_ETHERTYPE_M(mda, pkt);
1565}
1566
1567
1568/** Return the flow hash computed on the packet.
1569 * @ingroup ingress
1570 *
1571 * For TCP and UDP packets, this hash is calculated by hashing together
1572 * the "5-tuple" values, specifically the source IP address, destination
1573 * IP address, protocol type, source port and destination port.
1574 * The hash value is intended to be helpful for millions of distinct
1575 * flows.
1576 *
1577 * For IPv4 or IPv6 packets which are neither TCP nor UDP, the flow hash is
1578 * derived by hashing together the source and destination IP addresses.
1579 *
1580 * For MPLS-encapsulated packets, the flow hash is derived by hashing
1581 * the first MPLS label.
1582 *
1583 * For all other packets the flow hash is computed from the source
1584 * and destination Ethernet addresses.
1585 *
1586 * The hash is symmetric, meaning it produces the same value if the
1587 * source and destination are swapped. The only exceptions are
1588 * tunneling protocols 0x04 (IP in IP Encapsulation), 0x29 (Simple
1589 * Internet Protocol), 0x2F (General Routing Encapsulation) and 0x32
1590 * (Encap Security Payload), which use only the destination address
1591 * since the source address is not meaningful.
1592 *
1593 * @param[in] pkt Packet on which to operate.
1594 * @return The packet's 32-bit flow hash.
1595 */
1596static __inline unsigned int
1597NETIO_PKT_FLOW_HASH(netio_pkt_t* pkt)
1598{
1599 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1600
1601 return NETIO_PKT_FLOW_HASH_M(mda, pkt);
1602}
1603
1604
1605/** Return the first word of "user data" for the packet.
1606 *
1607 * The contents of the user data words depend on the IPP.
1608 *
1609 * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the first
1610 * word of user data contains the least significant bits of the 64-bit
1611 * arrival cycle count (see @c get_cycle_count_low()).
1612 *
1613 * See the <em>System Programmer's Guide</em> for details.
1614 *
1615 * @ingroup ingress
1616 *
1617 * @param[in] pkt Packet on which to operate.
1618 * @return The packet's first word of "user data".
1619 */
1620static __inline unsigned int
1621NETIO_PKT_USER_DATA_0(netio_pkt_t* pkt)
1622{
1623 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1624
1625 return NETIO_PKT_USER_DATA_0_M(mda, pkt);
1626}
1627
1628
1629/** Return the second word of "user data" for the packet.
1630 *
1631 * The contents of the user data words depend on the IPP.
1632 *
1633 * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the second
1634 * word of user data contains the most significant bits of the 64-bit
1635 * arrival cycle count (see @c get_cycle_count_high()).
1636 *
1637 * See the <em>System Programmer's Guide</em> for details.
1638 *
1639 * @ingroup ingress
1640 *
1641 * @param[in] pkt Packet on which to operate.
1642 * @return The packet's second word of "user data".
1643 */
1644static __inline unsigned int
1645NETIO_PKT_USER_DATA_1(netio_pkt_t* pkt)
1646{
1647 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1648
1649 return NETIO_PKT_USER_DATA_1_M(mda, pkt);
1650}
1651
1652
1653/** Determine whether the L4 (TCP/UDP) checksum was calculated.
1654 * @ingroup ingress
1655 *
1656 * @param[in] pkt Packet on which to operate.
1657 * @return Nonzero if the L4 checksum was calculated.
1658 */
1659static __inline unsigned int
1660NETIO_PKT_L4_CSUM_CALCULATED(netio_pkt_t* pkt)
1661{
1662 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1663
1664 return NETIO_PKT_L4_CSUM_CALCULATED_M(mda, pkt);
1665}
1666
1667
1668/** Determine whether the L4 (TCP/UDP) checksum was calculated and found to
1669 * be correct.
1670 * @ingroup ingress
1671 *
1672 * @param[in] pkt Packet on which to operate.
1673 * @return Nonzero if the checksum was calculated and is correct.
1674 */
1675static __inline unsigned int
1676NETIO_PKT_L4_CSUM_CORRECT(netio_pkt_t* pkt)
1677{
1678 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1679
1680 return NETIO_PKT_L4_CSUM_CORRECT_M(mda, pkt);
1681}
1682
1683
1684/** Determine whether the L3 (IP) checksum was calculated.
1685 * @ingroup ingress
1686 *
1687 * @param[in] pkt Packet on which to operate.
1688 * @return Nonzero if the L3 (IP) checksum was calculated.
1689*/
1690static __inline unsigned int
1691NETIO_PKT_L3_CSUM_CALCULATED(netio_pkt_t* pkt)
1692{
1693 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1694
1695 return NETIO_PKT_L3_CSUM_CALCULATED_M(mda, pkt);
1696}
1697
1698
1699/** Determine whether the L3 (IP) checksum was calculated and found to be
1700 * correct.
1701 * @ingroup ingress
1702 *
1703 * @param[in] pkt Packet on which to operate.
1704 * @return Nonzero if the checksum was calculated and is correct.
1705 */
1706static __inline unsigned int
1707NETIO_PKT_L3_CSUM_CORRECT(netio_pkt_t* pkt)
1708{
1709 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1710
1711 return NETIO_PKT_L3_CSUM_CORRECT_M(mda, pkt);
1712}
1713
1714
1715/** Determine whether the Ethertype was recognized and L3 packet data was
1716 * processed.
1717 * @ingroup ingress
1718 *
1719 * @param[in] pkt Packet on which to operate.
1720 * @return Nonzero if the Ethertype was recognized and L3 packet data was
1721 * processed.
1722 */
1723static __inline unsigned int
1724NETIO_PKT_ETHERTYPE_RECOGNIZED(netio_pkt_t* pkt)
1725{
1726 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1727
1728 return NETIO_PKT_ETHERTYPE_RECOGNIZED_M(mda, pkt);
1729}
1730
1731
1732/** Set an egress packet's L2 length, using a metadata pointer to speed the
1733 * computation.
1734 * @ingroup egress
1735 *
1736 * @param[in,out] mmd Pointer to packet's minimal metadata.
1737 * @param[in] pkt Packet on which to operate.
1738 * @param[in] len Packet L2 length, in bytes.
1739 */
1740static __inline void
1741NETIO_PKT_SET_L2_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt,
1742 int len)
1743{
1744 mmd->l2_length = len;
1745}
1746
1747
1748/** Set an egress packet's L2 length.
1749 * @ingroup egress
1750 *
1751 * @param[in,out] pkt Packet on which to operate.
1752 * @param[in] len Packet L2 length, in bytes.
1753 */
1754static __inline void
1755NETIO_PKT_SET_L2_LENGTH(netio_pkt_t* pkt, int len)
1756{
1757 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1758
1759 NETIO_PKT_SET_L2_LENGTH_MM(mmd, pkt, len);
1760}
1761
1762
1763/** Set an egress packet's L2 header length, using a metadata pointer to
1764 * speed the computation.
1765 * @ingroup egress
1766 *
1767 * It is not normally necessary to call this routine; only the L2 length,
1768 * not the header length, is needed to transmit a packet. It may be useful if
1769 * the egress packet will later be processed by code which expects to use
1770 * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload.
1771 *
1772 * @param[in,out] mmd Pointer to packet's minimal metadata.
1773 * @param[in] pkt Packet on which to operate.
1774 * @param[in] len Packet L2 header length, in bytes.
1775 */
1776static __inline void
1777NETIO_PKT_SET_L2_HEADER_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd,
1778 netio_pkt_t* pkt, int len)
1779{
1780 mmd->l3_offset = mmd->l2_offset + len;
1781}
1782
1783
1784/** Set an egress packet's L2 header length.
1785 * @ingroup egress
1786 *
1787 * It is not normally necessary to call this routine; only the L2 length,
1788 * not the header length, is needed to transmit a packet. It may be useful if
1789 * the egress packet will later be processed by code which expects to use
1790 * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload.
1791 *
1792 * @param[in,out] pkt Packet on which to operate.
1793 * @param[in] len Packet L2 header length, in bytes.
1794 */
1795static __inline void
1796NETIO_PKT_SET_L2_HEADER_LENGTH(netio_pkt_t* pkt, int len)
1797{
1798 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1799
1800 NETIO_PKT_SET_L2_HEADER_LENGTH_MM(mmd, pkt, len);
1801}
1802
1803
1804/** Set up an egress packet for hardware checksum computation, using a
1805 * metadata pointer to speed the operation.
1806 * @ingroup egress
1807 *
1808 * NetIO provides the ability to automatically calculate a standard
1809 * 16-bit Internet checksum on transmitted packets. The application
1810 * may specify the point in the packet where the checksum starts, the
1811 * number of bytes to be checksummed, and the two bytes in the packet
1812 * which will be replaced with the completed checksum. (If the range
1813 * of bytes to be checksummed includes the bytes to be replaced, the
1814 * initial values of those bytes will be included in the checksum.)
1815 *
1816 * For some protocols, the packet checksum covers data which is not present
1817 * in the packet, or is at least not contiguous to the main data payload.
1818 * For instance, the TCP checksum includes a "pseudo-header" which includes
1819 * the source and destination IP addresses of the packet. To accommodate
1820 * this, the checksum engine may be "seeded" with an initial value, which
1821 * the application would need to compute based on the specific protocol's
1822 * requirements. Note that the seed is given in host byte order (little-
1823 * endian), not network byte order (big-endian); code written to compute a
1824 * pseudo-header checksum in network byte order will need to byte-swap it
1825 * before use as the seed.
1826 *
1827 * Note that the checksum is computed as part of the transmission process,
1828 * so it will not be present in the packet upon completion of this routine.
1829 *
1830 * @param[in,out] mmd Pointer to packet's minimal metadata.
1831 * @param[in] pkt Packet on which to operate.
1832 * @param[in] start Offset within L2 packet of the first byte to include in
1833 * the checksum.
1834 * @param[in] length Number of bytes to include in the checksum.
1835 * the checksum.
1836 * @param[in] location Offset within L2 packet of the first of the two bytes
1837 * to be replaced with the calculated checksum.
1838 * @param[in] seed Initial value of the running checksum before any of the
1839 * packet data is added.
1840 */
1841static __inline void
1842NETIO_PKT_DO_EGRESS_CSUM_MM(netio_pkt_minimal_metadata_t* mmd,
1843 netio_pkt_t* pkt, int start, int length,
1844 int location, uint16_t seed)
1845{
1846 mmd->csum_start = start;
1847 mmd->csum_length = length;
1848 mmd->csum_location = location;
1849 mmd->csum_seed = seed;
1850 mmd->flags |= _NETIO_PKT_NEED_EDMA_CSUM_MASK;
1851}
1852
1853
1854/** Set up an egress packet for hardware checksum computation.
1855 * @ingroup egress
1856 *
1857 * NetIO provides the ability to automatically calculate a standard
1858 * 16-bit Internet checksum on transmitted packets. The application
1859 * may specify the point in the packet where the checksum starts, the
1860 * number of bytes to be checksummed, and the two bytes in the packet
1861 * which will be replaced with the completed checksum. (If the range
1862 * of bytes to be checksummed includes the bytes to be replaced, the
1863 * initial values of those bytes will be included in the checksum.)
1864 *
1865 * For some protocols, the packet checksum covers data which is not present
1866 * in the packet, or is at least not contiguous to the main data payload.
1867 * For instance, the TCP checksum includes a "pseudo-header" which includes
1868 * the source and destination IP addresses of the packet. To accommodate
1869 * this, the checksum engine may be "seeded" with an initial value, which
1870 * the application would need to compute based on the specific protocol's
1871 * requirements. Note that the seed is given in host byte order (little-
1872 * endian), not network byte order (big-endian); code written to compute a
1873 * pseudo-header checksum in network byte order will need to byte-swap it
1874 * before use as the seed.
1875 *
1876 * Note that the checksum is computed as part of the transmission process,
1877 * so it will not be present in the packet upon completion of this routine.
1878 *
1879 * @param[in,out] pkt Packet on which to operate.
1880 * @param[in] start Offset within L2 packet of the first byte to include in
1881 * the checksum.
1882 * @param[in] length Number of bytes to include in the checksum.
1883 * the checksum.
1884 * @param[in] location Offset within L2 packet of the first of the two bytes
1885 * to be replaced with the calculated checksum.
1886 * @param[in] seed Initial value of the running checksum before any of the
1887 * packet data is added.
1888 */
1889static __inline void
1890NETIO_PKT_DO_EGRESS_CSUM(netio_pkt_t* pkt, int start, int length,
1891 int location, uint16_t seed)
1892{
1893 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1894
1895 NETIO_PKT_DO_EGRESS_CSUM_MM(mmd, pkt, start, length, location, seed);
1896}
1897
1898
1899/** Return the number of bytes which could be prepended to a packet, using a
1900 * metadata pointer to speed the operation.
1901 * See @ref netio_populate_prepend_buffer() to get a full description of
1902 * prepending.
1903 *
1904 * @param[in,out] mda Pointer to packet's standard metadata.
1905 * @param[in] pkt Packet on which to operate.
1906 */
1907static __inline int
1908NETIO_PKT_PREPEND_AVAIL_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
1909{
1910 return (pkt->__packet.bits.__offset << 6) +
1911 NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda, pkt);
1912}
1913
1914
1915/** Return the number of bytes which could be prepended to a packet, using a
1916 * metadata pointer to speed the operation.
1917 * See @ref netio_populate_prepend_buffer() to get a full description of
1918 * prepending.
1919 * @ingroup egress
1920 *
1921 * @param[in,out] mmd Pointer to packet's minimal metadata.
1922 * @param[in] pkt Packet on which to operate.
1923 */
1924static __inline int
1925NETIO_PKT_PREPEND_AVAIL_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
1926{
1927 return (pkt->__packet.bits.__offset << 6) + mmd->l2_offset;
1928}
1929
1930
1931/** Return the number of bytes which could be prepended to a packet.
1932 * See @ref netio_populate_prepend_buffer() to get a full description of
1933 * prepending.
1934 * @ingroup egress
1935 *
1936 * @param[in] pkt Packet on which to operate.
1937 */
1938static __inline int
1939NETIO_PKT_PREPEND_AVAIL(netio_pkt_t* pkt)
1940{
1941 if (NETIO_PKT_IS_MINIMAL(pkt))
1942 {
1943 netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
1944
1945 return NETIO_PKT_PREPEND_AVAIL_MM(mmd, pkt);
1946 }
1947 else
1948 {
1949 netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
1950
1951 return NETIO_PKT_PREPEND_AVAIL_M(mda, pkt);
1952 }
1953}
1954
1955
1956/** Flush a packet's minimal metadata from the cache, using a metadata pointer
1957 * to speed the operation.
1958 * @ingroup egress
1959 *
1960 * @param[in] mmd Pointer to packet's minimal metadata.
1961 * @param[in] pkt Packet on which to operate.
1962 */
1963static __inline void
1964NETIO_PKT_FLUSH_MINIMAL_METADATA_MM(netio_pkt_minimal_metadata_t* mmd,
1965 netio_pkt_t* pkt)
1966{
1967}
1968
1969
1970/** Invalidate a packet's minimal metadata from the cache, using a metadata
1971 * pointer to speed the operation.
1972 * @ingroup egress
1973 *
1974 * @param[in] mmd Pointer to packet's minimal metadata.
1975 * @param[in] pkt Packet on which to operate.
1976 */
1977static __inline void
1978NETIO_PKT_INV_MINIMAL_METADATA_MM(netio_pkt_minimal_metadata_t* mmd,
1979 netio_pkt_t* pkt)
1980{
1981}
1982
1983
1984/** Flush and then invalidate a packet's minimal metadata from the cache,
1985 * using a metadata pointer to speed the operation.
1986 * @ingroup egress
1987 *
1988 * @param[in] mmd Pointer to packet's minimal metadata.
1989 * @param[in] pkt Packet on which to operate.
1990 */
1991static __inline void
1992NETIO_PKT_FLUSH_INV_MINIMAL_METADATA_MM(netio_pkt_minimal_metadata_t* mmd,
1993 netio_pkt_t* pkt)
1994{
1995}
1996
1997
1998/** Flush a packet's metadata from the cache, using a metadata pointer
1999 * to speed the operation.
2000 * @ingroup ingress
2001 *
2002 * @param[in] mda Pointer to packet's minimal metadata.
2003 * @param[in] pkt Packet on which to operate.
2004 */
2005static __inline void
2006NETIO_PKT_FLUSH_METADATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
2007{
2008}
2009
2010
2011/** Invalidate a packet's metadata from the cache, using a metadata
2012 * pointer to speed the operation.
2013 * @ingroup ingress
2014 *
2015 * @param[in] mda Pointer to packet's metadata.
2016 * @param[in] pkt Packet on which to operate.
2017 */
2018static __inline void
2019NETIO_PKT_INV_METADATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
2020{
2021}
2022
2023
2024/** Flush and then invalidate a packet's metadata from the cache,
2025 * using a metadata pointer to speed the operation.
2026 * @ingroup ingress
2027 *
2028 * @param[in] mda Pointer to packet's metadata.
2029 * @param[in] pkt Packet on which to operate.
2030 */
2031static __inline void
2032NETIO_PKT_FLUSH_INV_METADATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
2033{
2034}
2035
2036
2037/** Flush a packet's minimal metadata from the cache.
2038 * @ingroup egress
2039 *
2040 * @param[in] pkt Packet on which to operate.
2041 */
2042static __inline void
2043NETIO_PKT_FLUSH_MINIMAL_METADATA(netio_pkt_t* pkt)
2044{
2045}
2046
2047
2048/** Invalidate a packet's minimal metadata from the cache.
2049 * @ingroup egress
2050 *
2051 * @param[in] pkt Packet on which to operate.
2052 */
2053static __inline void
2054NETIO_PKT_INV_MINIMAL_METADATA(netio_pkt_t* pkt)
2055{
2056}
2057
2058
2059/** Flush and then invalidate a packet's minimal metadata from the cache.
2060 * @ingroup egress
2061 *
2062 * @param[in] pkt Packet on which to operate.
2063 */
2064static __inline void
2065NETIO_PKT_FLUSH_INV_MINIMAL_METADATA(netio_pkt_t* pkt)
2066{
2067}
2068
2069
2070/** Flush a packet's metadata from the cache.
2071 * @ingroup ingress
2072 *
2073 * @param[in] pkt Packet on which to operate.
2074 */
2075static __inline void
2076NETIO_PKT_FLUSH_METADATA(netio_pkt_t* pkt)
2077{
2078}
2079
2080
2081/** Invalidate a packet's metadata from the cache.
2082 * @ingroup ingress
2083 *
2084 * @param[in] pkt Packet on which to operate.
2085 */
2086static __inline void
2087NETIO_PKT_INV_METADATA(netio_pkt_t* pkt)
2088{
2089}
2090
2091
2092/** Flush and then invalidate a packet's metadata from the cache.
2093 * @ingroup ingress
2094 *
2095 * @param[in] pkt Packet on which to operate.
2096 */
2097static __inline void
2098NETIO_PKT_FLUSH_INV_METADATA(netio_pkt_t* pkt)
2099{
2100}
2101
2102/** Number of NUMA nodes we can distribute buffers to.
2103 * @ingroup setup */
2104#define NETIO_NUM_NODE_WEIGHTS 16
2105
2106/**
2107 * @brief An object for specifying the characteristics of NetIO communication
2108 * endpoint.
2109 *
2110 * @ingroup setup
2111 *
2112 * The @ref netio_input_register() function uses this structure to define
2113 * how an application tile will communicate with an IPP.
2114 *
2115 *
2116 * Future updates to NetIO may add new members to this structure,
2117 * which can affect the success of the registration operation. Thus,
2118 * if dynamically initializing the structure, applications are urged to
2119 * zero it out first, for example:
2120 *
2121 * @code
2122 * netio_input_config_t config;
2123 * memset(&config, 0, sizeof (config));
2124 * config.flags = NETIO_RECV | NETIO_XMIT_CSUM | NETIO_TAG_NONE;
2125 * config.num_receive_packets = NETIO_MAX_RECEIVE_PKTS;
2126 * config.queue_id = 0;
2127 * .
2128 * .
2129 * .
2130 * @endcode
2131 *
2132 * since that guarantees that any unused structure members, including
2133 * members which did not exist when the application was first developed,
2134 * will not have unexpected values.
2135 *
2136 * If statically initializing the structure, we strongly recommend use of
2137 * C99-style named initializers, for example:
2138 *
2139 * @code
2140 * netio_input_config_t config = {
2141 * .flags = NETIO_RECV | NETIO_XMIT_CSUM | NETIO_TAG_NONE,
2142 * .num_receive_packets = NETIO_MAX_RECEIVE_PKTS,
2143 * .queue_id = 0,
2144 * },
2145 * @endcode
2146 *
2147 * instead of the old-style structure initialization:
2148 *
2149 * @code
2150 * // Bad example! Currently equivalent to the above, but don't do this.
2151 * netio_input_config_t config = {
2152 * NETIO_RECV | NETIO_XMIT_CSUM | NETIO_TAG_NONE, NETIO_MAX_RECEIVE_PKTS, 0
2153 * },
2154 * @endcode
2155 *
2156 * since the C99 style requires no changes to the code if elements of the
2157 * config structure are rearranged. (It also makes the initialization much
2158 * easier to understand.)
2159 *
2160 * Except for items which address a particular tile's transmit or receive
2161 * characteristics, such as the ::NETIO_RECV flag, applications are advised
2162 * to specify the same set of configuration data on all registrations.
2163 * This prevents differing results if multiple tiles happen to do their
2164 * registration operations in a different order on different invocations of
2165 * the application. This is particularly important for things like link
2166 * management flags, and buffer size and homing specifications.
2167 *
2168 * Unless the ::NETIO_FIXED_BUFFER_VA flag is specified in flags, the NetIO
2169 * buffer pool is automatically created and mapped into the application's
2170 * virtual address space at an address chosen by the operating system,
2171 * using the common memory (cmem) facility in the Tilera Multicore
2172 * Components library. The cmem facility allows multiple processes to gain
2173 * access to shared memory which is mapped into each process at an
2174 * identical virtual address. In order for this to work, the processes
2175 * must have a common ancestor, which must create the common memory using
2176 * tmc_cmem_init().
2177 *
2178 * In programs using the iLib process creation API, or in programs which use
2179 * only one process (which include programs using the pthreads library),
2180 * tmc_cmem_init() is called automatically. All other applications
2181 * must call it explicitly, before any child processes which might call
2182 * netio_input_register() are created.
2183 */
2184typedef struct
2185{
2186 /** Registration characteristics.
2187
2188 This value determines several characteristics of the registration;
2189 flags for different types of behavior are ORed together to make the
2190 final flag value. Generally applications should specify exactly
2191 one flag from each of the following categories:
2192
2193 - Whether the application will be receiving packets on this queue
2194 (::NETIO_RECV or ::NETIO_NO_RECV).
2195
2196 - Whether the application will be transmitting packets on this queue,
2197 and if so, whether it will request egress checksum calculation
2198 (::NETIO_XMIT, ::NETIO_XMIT_CSUM, or ::NETIO_NO_XMIT). It is
2199 legal to call netio_get_buffer() without one of the XMIT flags,
2200 as long as ::NETIO_RECV is specified; in this case, the retrieved
2201 buffers must be passed to another tile for transmission.
2202
2203 - Whether the application expects any vendor-specific tags in
2204 its packets' L2 headers (::NETIO_TAG_NONE, ::NETIO_TAG_BRCM,
2205 or ::NETIO_TAG_MRVL). This must match the configuration of the
2206 target IPP.
2207
2208 To accommodate applications written to previous versions of the NetIO
2209 interface, none of the flags above are currently required; if omitted,
2210 NetIO behaves more or less as if ::NETIO_RECV | ::NETIO_XMIT_CSUM |
2211 ::NETIO_TAG_NONE were used. However, explicit specification of
2212 the relevant flags allows NetIO to do a better job of resource
2213 allocation, allows earlier detection of certain configuration errors,
2214 and may enable advanced features or higher performance in the future,
2215 so their use is strongly recommended.
2216
2217 Note that specifying ::NETIO_NO_RECV along with ::NETIO_NO_XMIT
2218 is a special case, intended primarily for use by programs which
2219 retrieve network statistics or do link management operations.
2220 When these flags are both specified, the resulting queue may not
2221 be used with NetIO routines other than netio_get(), netio_set(),
2222 and netio_input_unregister(). See @ref link for more information
2223 on link management.
2224
2225 Other flags are optional; their use is described below.
2226 */
2227 int flags;
2228
2229 /** Interface name. This is a string which identifies the specific
2230 Ethernet controller hardware to be used. The format of the string
2231 is a device type and a device index, separated by a slash; so,
2232 the first 10 Gigabit Ethernet controller is named "xgbe/0", while
2233 the second 10/100/1000 Megabit Ethernet controller is named "gbe/1".
2234 */
2235 const char* interface;
2236
2237 /** Receive packet queue size. This specifies the maximum number
2238 of ingress packets that can be received on this queue without
2239 being retrieved by @ref netio_get_packet(). If the IPP's distribution
2240 algorithm calls for a packet to be sent to this queue, and this
2241 number of packets are already pending there, the new packet
2242 will either be discarded, or sent to another tile registered
2243 for the same queue_id (see @ref drops). This value must
2244 be at least ::NETIO_MIN_RECEIVE_PKTS, can always be at least
2245 ::NETIO_MAX_RECEIVE_PKTS, and may be larger than that on certain
2246 interfaces.
2247 */
2248 int num_receive_packets;
2249
2250 /** The queue ID being requested. Legal values for this range from 0
2251 to ::NETIO_MAX_QUEUE_ID, inclusive. ::NETIO_MAX_QUEUE_ID is always
2252 greater than or equal to the number of tiles; this allows one queue
2253 for each tile, plus at least one additional queue. Some applications
2254 may wish to use the additional queue as a destination for unwanted
2255 packets, since packets delivered to queues for which no tiles have
2256 registered are discarded.
2257 */
2258 unsigned int queue_id;
2259
2260 /** Maximum number of small send buffers to be held in the local empty
2261 buffer cache. This specifies the size of the area which holds
2262 empty small egress buffers requested from the IPP but not yet
2263 retrieved via @ref netio_get_buffer(). This value must be greater
2264 than zero if the application will ever use @ref netio_get_buffer()
2265 to allocate empty small egress buffers; it may be no larger than
2266 ::NETIO_MAX_SEND_BUFFERS. See @ref epp for more details on empty
2267 buffer caching.
2268 */
2269 int num_send_buffers_small_total;
2270
2271 /** Number of small send buffers to be preallocated at registration.
2272 If this value is nonzero, the specified number of empty small egress
2273 buffers will be requested from the IPP during the netio_input_register
2274 operation; this may speed the execution of @ref netio_get_buffer().
2275 This may be no larger than @ref num_send_buffers_small_total. See @ref
2276 epp for more details on empty buffer caching.
2277 */
2278 int num_send_buffers_small_prealloc;
2279
2280 /** Maximum number of large send buffers to be held in the local empty
2281 buffer cache. This specifies the size of the area which holds empty
2282 large egress buffers requested from the IPP but not yet retrieved via
2283 @ref netio_get_buffer(). This value must be greater than zero if the
2284 application will ever use @ref netio_get_buffer() to allocate empty
2285 large egress buffers; it may be no larger than ::NETIO_MAX_SEND_BUFFERS.
2286 See @ref epp for more details on empty buffer caching.
2287 */
2288 int num_send_buffers_large_total;
2289
2290 /** Number of large send buffers to be preallocated at registration.
2291 If this value is nonzero, the specified number of empty large egress
2292 buffers will be requested from the IPP during the netio_input_register
2293 operation; this may speed the execution of @ref netio_get_buffer().
2294 This may be no larger than @ref num_send_buffers_large_total. See @ref
2295 epp for more details on empty buffer caching.
2296 */
2297 int num_send_buffers_large_prealloc;
2298
2299 /** Maximum number of jumbo send buffers to be held in the local empty
2300 buffer cache. This specifies the size of the area which holds empty
2301 jumbo egress buffers requested from the IPP but not yet retrieved via
2302 @ref netio_get_buffer(). This value must be greater than zero if the
2303 application will ever use @ref netio_get_buffer() to allocate empty
2304 jumbo egress buffers; it may be no larger than ::NETIO_MAX_SEND_BUFFERS.
2305 See @ref epp for more details on empty buffer caching.
2306 */
2307 int num_send_buffers_jumbo_total;
2308
2309 /** Number of jumbo send buffers to be preallocated at registration.
2310 If this value is nonzero, the specified number of empty jumbo egress
2311 buffers will be requested from the IPP during the netio_input_register
2312 operation; this may speed the execution of @ref netio_get_buffer().
2313 This may be no larger than @ref num_send_buffers_jumbo_total. See @ref
2314 epp for more details on empty buffer caching.
2315 */
2316 int num_send_buffers_jumbo_prealloc;
2317
2318 /** Total packet buffer size. This determines the total size, in bytes,
2319 of the NetIO buffer pool. Note that the maximum number of available
2320 buffers of each size is determined during hypervisor configuration
2321 (see the <em>System Programmer's Guide</em> for details); this just
2322 influences how much host memory is allocated for those buffers.
2323
2324 The buffer pool is allocated from common memory, which will be
2325 automatically initialized if needed. If your buffer pool is larger
2326 than 240 MB, you might need to explicitly call @c tmc_cmem_init(),
2327 as described in the Application Libraries Reference Manual (UG227).
2328
2329 Packet buffers are currently allocated in chunks of 16 MB; this
2330 value will be rounded up to the next larger multiple of 16 MB.
2331 If this value is zero, a default of 32 MB will be used; this was
2332 the value used by previous versions of NetIO. Note that taking this
2333 default also affects the placement of buffers on Linux NUMA nodes.
2334 See @ref buffer_node_weights for an explanation of buffer placement.
2335
2336 In order to successfully allocate packet buffers, Linux must have
2337 available huge pages on the relevant Linux NUMA nodes. See the
2338 <em>System Programmer's Guide</em> for information on configuring
2339 huge page support in Linux.
2340 */
2341 uint64_t total_buffer_size;
2342
2343 /** Buffer placement weighting factors.
2344
2345 This array specifies the relative amount of buffering to place
2346 on each of the available Linux NUMA nodes. This array is
2347 indexed by the NUMA node, and the values in the array are
2348 proportional to the amount of buffer space to allocate on that
2349 node.
2350
2351 If memory striping is enabled in the Hypervisor, then there is
2352 only one logical NUMA node (node 0). In that case, NetIO will by
2353 default ignore the suggested buffer node weights, and buffers
2354 will be striped across the physical memory controllers. See
2355 UG209 System Programmer's Guide for a description of the
2356 hypervisor option that controls memory striping.
2357
2358 If memory striping is disabled, then there are up to four NUMA
2359 nodes, corresponding to the four DDRAM controllers in the TILE
2360 processor architecture. See UG100 Tile Processor Architecture
2361 Overview for a diagram showing the location of each of the DDRAM
2362 controllers relative to the tile array.
2363
2364 For instance, if memory striping is disabled, the following
2365 configuration strucure:
2366
2367 @code
2368 netio_input_config_t config = {
2369 .
2370 .
2371 .
2372 .total_buffer_size = 4 * 16 * 1024 * 1024;
2373 .buffer_node_weights = { 1, 0, 1, 0 },
2374 },
2375 @endcode
2376
2377 would result in 32 MB of buffers being placed on controller 0, and
2378 32 MB on controller 2. (Since buffers are allocated in units of
2379 16 MB, some sets of weights will not be able to be matched exactly.)
2380
2381 For the weights to be effective, @ref total_buffer_size must be
2382 nonzero. If @ref total_buffer_size is zero, causing the default
2383 32 MB of buffer space to be used, then any specified weights will
2384 be ignored, and buffers will positioned as they were in previous
2385 versions of NetIO:
2386
2387 - For xgbe/0 and gbe/0, 16 MB of buffers will be placed on controller 1,
2388 and the other 16 MB will be placed on controller 2.
2389
2390 - For xgbe/1 and gbe/1, 16 MB of buffers will be placed on controller 2,
2391 and the other 16 MB will be placed on controller 3.
2392
2393 If @ref total_buffer_size is nonzero, but all weights are zero,
2394 then all buffer space will be allocated on Linux NUMA node zero.
2395
2396 By default, the specified buffer placement is treated as a hint;
2397 if sufficient free memory is not available on the specified
2398 controllers, the buffers will be allocated elsewhere. However,
2399 if the ::NETIO_STRICT_HOMING flag is specified in @ref flags, then a
2400 failure to allocate buffer space exactly as requested will cause the
2401 registration operation to fail with an error of ::NETIO_CANNOT_HOME.
2402
2403 Note that maximal network performance cannot be achieved with
2404 only one memory controller.
2405 */
2406 uint8_t buffer_node_weights[NETIO_NUM_NODE_WEIGHTS];
2407
2408 /** Fixed virtual address for packet buffers. Only valid when
2409 ::NETIO_FIXED_BUFFER_VA is specified in @ref flags; see the
2410 description of that flag for details.
2411 */
2412 void* fixed_buffer_va;
2413
2414 /**
2415 Maximum number of outstanding send packet requests. This value is
2416 only relevant when an EPP is in use; it determines the number of
2417 slots in the EPP's outgoing packet queue which this tile is allowed
2418 to consume, and thus the number of packets which may be sent before
2419 the sending tile must wait for an acknowledgment from the EPP.
2420 Modifying this value is generally only helpful when using @ref
2421 netio_send_packet_vector(), where it can help improve performance by
2422 allowing a single vector send operation to process more packets.
2423 Typically it is not specified, and the default, which divides the
2424 outgoing packet slots evenly between all tiles on the chip, is used.
2425
2426 If a registration asks for more outgoing packet queue slots than are
2427 available, ::NETIO_TOOMANY_XMIT will be returned. The total number
2428 of packet queue slots which are available for all tiles for each EPP
2429 is subject to change, but is currently ::NETIO_TOTAL_SENDS_OUTSTANDING.
2430
2431
2432 This value is ignored if ::NETIO_XMIT is not specified in flags.
2433 If you want to specify a large value here for a specific tile, you are
2434 advised to specify NETIO_NO_XMIT on other, non-transmitting tiles so
2435 that they do not consume a default number of packet slots. Any tile
2436 transmitting is required to have at least ::NETIO_MIN_SENDS_OUTSTANDING
2437 slots allocated to it; values less than that will be silently
2438 increased by the NetIO library.
2439 */
2440 int num_sends_outstanding;
2441}
2442netio_input_config_t;
2443
2444
2445/** Registration flags; used in the @ref netio_input_config_t structure.
2446 * @addtogroup setup
2447 */
2448/** @{ */
2449
2450/** Fail a registration request if we can't put packet buffers
2451 on the specified memory controllers. */
2452#define NETIO_STRICT_HOMING 0x00000002
2453
2454/** This application expects no tags on its L2 headers. */
2455#define NETIO_TAG_NONE 0x00000004
2456
2457/** This application expects Marvell extended tags on its L2 headers. */
2458#define NETIO_TAG_MRVL 0x00000008
2459
2460/** This application expects Broadcom tags on its L2 headers. */
2461#define NETIO_TAG_BRCM 0x00000010
2462
2463/** This registration may call routines which receive packets. */
2464#define NETIO_RECV 0x00000020
2465
2466/** This registration may not call routines which receive packets. */
2467#define NETIO_NO_RECV 0x00000040
2468
2469/** This registration may call routines which transmit packets. */
2470#define NETIO_XMIT 0x00000080
2471
2472/** This registration may call routines which transmit packets with
2473 checksum acceleration. */
2474#define NETIO_XMIT_CSUM 0x00000100
2475
2476/** This registration may not call routines which transmit packets. */
2477#define NETIO_NO_XMIT 0x00000200
2478
2479/** This registration wants NetIO buffers mapped at an application-specified
2480 virtual address.
2481
2482 NetIO buffers are by default created by the TMC common memory facility,
2483 which must be configured by a common ancestor of all processes sharing
2484 a network interface. When this flag is specified, NetIO buffers are
2485 instead mapped at an address chosen by the application (and specified
2486 in @ref netio_input_config_t::fixed_buffer_va). This allows multiple
2487 unrelated but cooperating processes to share a NetIO interface.
2488 All processes sharing the same interface must specify this flag,
2489 and all must specify the same fixed virtual address.
2490
2491 @ref netio_input_config_t::fixed_buffer_va must be a
2492 multiple of 16 MB, and the packet buffers will occupy @ref
2493 netio_input_config_t::total_buffer_size bytes of virtual address
2494 space, beginning at that address. If any of those virtual addresses
2495 are currently occupied by other memory objects, like application or
2496 shared library code or data, @ref netio_input_register() will return
2497 ::NETIO_FAULT. While it is impossible to provide a fixed_buffer_va
2498 which will work for all applications, a good first guess might be to
2499 use 0xb0000000 minus @ref netio_input_config_t::total_buffer_size.
2500 If that fails, it might be helpful to consult the running application's
2501 virtual address description file (/proc/<em>pid</em>/maps) to see
2502 which regions of virtual address space are available.
2503 */
2504#define NETIO_FIXED_BUFFER_VA 0x00000400
2505
2506/** This registration call will not complete unless the network link
2507 is up. The process will wait several seconds for this to happen (the
2508 precise interval is link-dependent), but if the link does not come up,
2509 ::NETIO_LINK_DOWN will be returned. This flag is the default if
2510 ::NETIO_NOREQUIRE_LINK_UP is not specified. Note that this flag by
2511 itself does not request that the link be brought up; that can be done
2512 with the ::NETIO_AUTO_LINK_UPDN or ::NETIO_AUTO_LINK_UP flags (the
2513 latter is the default if no NETIO_AUTO_LINK_xxx flags are specified),
2514 or by explicitly setting the link's desired state via netio_set().
2515 If the link is not brought up by one of those methods, and this flag
2516 is specified, the registration operation will return ::NETIO_LINK_DOWN.
2517 This flag is ignored if it is specified along with ::NETIO_NO_XMIT and
2518 ::NETIO_NO_RECV. See @ref link for more information on link
2519 management.
2520 */
2521#define NETIO_REQUIRE_LINK_UP 0x00000800
2522
2523/** This registration call will complete even if the network link is not up.
2524 Whenever the link is not up, packets will not be sent or received:
2525 netio_get_packet() will return ::NETIO_NOPKT once all queued packets
2526 have been drained, and netio_send_packet() and similar routines will
2527 return NETIO_QUEUE_FULL once the outgoing packet queue in the EPP
2528 or the I/O shim is full. See @ref link for more information on link
2529 management.
2530 */
2531#define NETIO_NOREQUIRE_LINK_UP 0x00001000
2532
2533#ifndef __DOXYGEN__
2534/*
2535 * These are part of the implementation of the NETIO_AUTO_LINK_xxx flags,
2536 * but should not be used directly by applications, and are thus not
2537 * documented.
2538 */
2539#define _NETIO_AUTO_UP 0x00002000
2540#define _NETIO_AUTO_DN 0x00004000
2541#define _NETIO_AUTO_PRESENT 0x00008000
2542#endif
2543
2544/** Set the desired state of the link to up, allowing any speeds which are
2545 supported by the link hardware, as part of this registration operation.
2546 Do not take down the link automatically. This is the default if
2547 no other NETIO_AUTO_LINK_xxx flags are specified. This flag is ignored
2548 if it is specified along with ::NETIO_NO_XMIT and ::NETIO_NO_RECV.
2549 See @ref link for more information on link management.
2550 */
2551#define NETIO_AUTO_LINK_UP (_NETIO_AUTO_PRESENT | _NETIO_AUTO_UP)
2552
2553/** Set the desired state of the link to up, allowing any speeds which are
2554 supported by the link hardware, as part of this registration operation.
2555 Set the desired state of the link to down the next time no tiles are
2556 registered for packet reception or transmission. This flag is ignored
2557 if it is specified along with ::NETIO_NO_XMIT and ::NETIO_NO_RECV.
2558 See @ref link for more information on link management.
2559 */
2560#define NETIO_AUTO_LINK_UPDN (_NETIO_AUTO_PRESENT | _NETIO_AUTO_UP | \
2561 _NETIO_AUTO_DN)
2562
2563/** Set the desired state of the link to down the next time no tiles are
2564 registered for packet reception or transmission. This flag is ignored
2565 if it is specified along with ::NETIO_NO_XMIT and ::NETIO_NO_RECV.
2566 See @ref link for more information on link management.
2567 */
2568#define NETIO_AUTO_LINK_DN (_NETIO_AUTO_PRESENT | _NETIO_AUTO_DN)
2569
2570/** Do not bring up the link automatically as part of this registration
2571 operation. Do not take down the link automatically. This flag
2572 is ignored if it is specified along with ::NETIO_NO_XMIT and
2573 ::NETIO_NO_RECV. See @ref link for more information on link management.
2574 */
2575#define NETIO_AUTO_LINK_NONE _NETIO_AUTO_PRESENT
2576
2577
2578/** Minimum number of receive packets. */
2579#define NETIO_MIN_RECEIVE_PKTS 16
2580
2581/** Lower bound on the maximum number of receive packets; may be higher
2582 than this on some interfaces. */
2583#define NETIO_MAX_RECEIVE_PKTS 128
2584
2585/** Maximum number of send buffers, per packet size. */
2586#define NETIO_MAX_SEND_BUFFERS 16
2587
2588/** Number of EPP queue slots, and thus outstanding sends, per EPP. */
2589#define NETIO_TOTAL_SENDS_OUTSTANDING 2015
2590
2591/** Minimum number of EPP queue slots, and thus outstanding sends, per
2592 * transmitting tile. */
2593#define NETIO_MIN_SENDS_OUTSTANDING 16
2594
2595
2596/**@}*/
2597
2598#ifndef __DOXYGEN__
2599
2600/**
2601 * An object for providing Ethernet packets to a process.
2602 */
2603struct __netio_queue_impl_t;
2604
2605/**
2606 * An object for managing the user end of a NetIO queue.
2607 */
2608struct __netio_queue_user_impl_t;
2609
2610#endif /* !__DOXYGEN__ */
2611
2612
2613/** A netio_queue_t describes a NetIO communications endpoint.
2614 * @ingroup setup
2615 */
2616typedef struct
2617{
2618#ifdef __DOXYGEN__
2619 uint8_t opaque[8]; /**< This is an opaque structure. */
2620#else
2621 struct __netio_queue_impl_t* __system_part; /**< The system part. */
2622 struct __netio_queue_user_impl_t* __user_part; /**< The user part. */
2623#ifdef _NETIO_PTHREAD
2624 _netio_percpu_mutex_t lock; /**< Queue lock. */
2625#endif
2626#endif
2627}
2628netio_queue_t;
2629
2630
2631/**
2632 * @brief Packet send context.
2633 *
2634 * @ingroup egress
2635 *
2636 * Packet send context for use with netio_send_packet_prepare and _commit.
2637 */
2638typedef struct
2639{
2640#ifdef __DOXYGEN__
2641 uint8_t opaque[44]; /**< This is an opaque structure. */
2642#else
2643 uint8_t flags; /**< Defined below */
2644 uint8_t datalen; /**< Number of valid words pointed to by data. */
2645 uint32_t request[9]; /**< Request to be sent to the EPP or shim. Note
2646 that this is smaller than the 11-word maximum
2647 request size, since some constant values are
2648 not saved in the context. */
2649 uint32_t *data; /**< Data to be sent to the EPP or shim via IDN. */
2650#endif
2651}
2652netio_send_pkt_context_t;
2653
2654
2655#ifndef __DOXYGEN__
2656#define SEND_PKT_CTX_USE_EPP 1 /**< We're sending to an EPP. */
2657#define SEND_PKT_CTX_SEND_CSUM 2 /**< Request includes a checksum. */
2658#endif
2659
2660/**
2661 * @brief Packet vector entry.
2662 *
2663 * @ingroup egress
2664 *
2665 * This data structure is used with netio_send_packet_vector() to send multiple
2666 * packets with one NetIO call. The structure should be initialized by
2667 * calling netio_pkt_vector_set(), rather than by setting the fields
2668 * directly.
2669 *
2670 * This structure is guaranteed to be a power of two in size, no
2671 * bigger than one L2 cache line, and to be aligned modulo its size.
2672 */
2673typedef struct
2674#ifndef __DOXYGEN__
2675__attribute__((aligned(8)))
2676#endif
2677{
2678 /** Reserved for use by the user application. When initialized with
2679 * the netio_set_pkt_vector_entry() function, this field is guaranteed
2680 * to be visible to readers only after all other fields are already
2681 * visible. This way it can be used as a valid flag or generation
2682 * counter. */
2683 uint8_t user_data;
2684
2685 /* Structure members below this point should not be accessed directly by
2686 * applications, as they may change in the future. */
2687
2688 /** Low 8 bits of the packet address to send. The high bits are
2689 * acquired from the 'handle' field. */
2690 uint8_t buffer_address_low;
2691
2692 /** Number of bytes to transmit. */
2693 uint16_t size;
2694
2695 /** The raw handle from a netio_pkt_t. If this is NETIO_PKT_HANDLE_NONE,
2696 * this vector entry will be skipped and no packet will be transmitted. */
2697 netio_pkt_handle_t handle;
2698}
2699netio_pkt_vector_entry_t;
2700
2701
2702/**
2703 * @brief Initialize fields in a packet vector entry.
2704 *
2705 * @ingroup egress
2706 *
2707 * @param[out] v Pointer to the vector entry to be initialized.
2708 * @param[in] pkt Packet to be transmitted when the vector entry is passed to
2709 * netio_send_packet_vector(). Note that the packet's attributes
2710 * (e.g., its L2 offset and length) are captured at the time this
2711 * routine is called; subsequent changes in those attributes will not
2712 * be reflected in the packet which is actually transmitted.
2713 * Changes in the packet's contents, however, will be so reflected.
2714 * If this is NULL, no packet will be transmitted.
2715 * @param[in] user_data User data to be set in the vector entry.
2716 * This function guarantees that the "user_data" field will become
2717 * visible to a reader only after all other fields have become visible.
2718 * This allows a structure in a ring buffer to be written and read
2719 * by a polling reader without any locks or other synchronization.
2720 */
2721static __inline void
2722netio_pkt_vector_set(volatile netio_pkt_vector_entry_t* v, netio_pkt_t* pkt,
2723 uint8_t user_data)
2724{
2725 if (pkt)
2726 {
2727 if (NETIO_PKT_IS_MINIMAL(pkt))
2728 {
2729 netio_pkt_minimal_metadata_t* mmd =
2730 (netio_pkt_minimal_metadata_t*) &pkt->__metadata;
2731 v->buffer_address_low = (uintptr_t) NETIO_PKT_L2_DATA_MM(mmd, pkt) & 0xFF;
2732 v->size = NETIO_PKT_L2_LENGTH_MM(mmd, pkt);
2733 }
2734 else
2735 {
2736 netio_pkt_metadata_t* mda = &pkt->__metadata;
2737 v->buffer_address_low = (uintptr_t) NETIO_PKT_L2_DATA_M(mda, pkt) & 0xFF;
2738 v->size = NETIO_PKT_L2_LENGTH_M(mda, pkt);
2739 }
2740 v->handle.word = pkt->__packet.word;
2741 }
2742 else
2743 {
2744 v->handle.word = 0; /* Set handle to NETIO_PKT_HANDLE_NONE. */
2745 }
2746
2747 __asm__("" : : : "memory");
2748
2749 v->user_data = user_data;
2750}
2751
2752
2753/**
2754 * Flags and structures for @ref netio_get() and @ref netio_set().
2755 * @ingroup config
2756 */
2757
2758/** @{ */
2759/** Parameter class; addr is a NETIO_PARAM_xxx value. */
2760#define NETIO_PARAM 0
2761/** Interface MAC address. This address is only valid with @ref netio_get().
2762 * The value is a 6-byte MAC address. Depending upon the overall system
2763 * design, a MAC address may or may not be available for each interface. */
2764#define NETIO_PARAM_MAC 0
2765
2766/** Determine whether to suspend output on the receipt of pause frames.
2767 * If the value is nonzero, the I/O shim will suspend output when a pause
2768 * frame is received. If the value is zero, pause frames will be ignored. */
2769#define NETIO_PARAM_PAUSE_IN 1
2770
2771/** Determine whether to send pause frames if the I/O shim packet FIFOs are
2772 * nearly full. If the value is zero, pause frames are not sent. If
2773 * the value is nonzero, it is the delay value which will be sent in any
2774 * pause frames which are output, in units of 512 bit times. */
2775#define NETIO_PARAM_PAUSE_OUT 2
2776
2777/** Jumbo frame support. The value is a 4-byte integer. If the value is
2778 * nonzero, the MAC will accept frames of up to 10240 bytes. If the value
2779 * is zero, the MAC will only accept frames of up to 1544 bytes. */
2780#define NETIO_PARAM_JUMBO 3
2781
2782/** I/O shim's overflow statistics register. The value is two 16-bit integers.
2783 * The first 16-bit value (or the low 16 bits, if the value is treated as a
2784 * 32-bit number) is the count of packets which were completely dropped and
2785 * not delivered by the shim. The second 16-bit value (or the high 16 bits,
2786 * if the value is treated as a 32-bit number) is the count of packets
2787 * which were truncated and thus only partially delivered by the shim. This
2788 * register is automatically reset to zero after it has been read.
2789 */
2790#define NETIO_PARAM_OVERFLOW 4
2791
2792/** IPP statistics. This address is only valid with @ref netio_get(). The
2793 * value is a netio_stat_t structure. Unlike the I/O shim statistics, the
2794 * IPP statistics are not all reset to zero on read; see the description
2795 * of the netio_stat_t for details. */
2796#define NETIO_PARAM_STAT 5
2797
2798/** Possible link state. The value is a combination of "NETIO_LINK_xxx"
2799 * flags. With @ref netio_get(), this will indicate which flags are
2800 * actually supported by the hardware.
2801 *
2802 * For historical reasons, specifying this value to netio_set() will have
2803 * the same behavior as using ::NETIO_PARAM_LINK_CONFIG, but this usage is
2804 * discouraged.
2805 */
2806#define NETIO_PARAM_LINK_POSSIBLE_STATE 6
2807
2808/** Link configuration. The value is a combination of "NETIO_LINK_xxx" flags.
2809 * With @ref netio_set(), this will attempt to immediately bring up the
2810 * link using whichever of the requested flags are supported by the
2811 * hardware, or take down the link if the flags are zero; if this is
2812 * not possible, an error will be returned. Many programs will want
2813 * to use ::NETIO_PARAM_LINK_DESIRED_STATE instead.
2814 *
2815 * For historical reasons, specifying this value to netio_get() will
2816 * have the same behavior as using ::NETIO_PARAM_LINK_POSSIBLE_STATE,
2817 * but this usage is discouraged.
2818 */
2819#define NETIO_PARAM_LINK_CONFIG NETIO_PARAM_LINK_POSSIBLE_STATE
2820
2821/** Current link state. This address is only valid with @ref netio_get().
2822 * The value is zero or more of the "NETIO_LINK_xxx" flags, ORed together.
2823 * If the link is down, the value ANDed with NETIO_LINK_SPEED will be
2824 * zero; if the link is up, the value ANDed with NETIO_LINK_SPEED will
2825 * result in exactly one of the NETIO_LINK_xxx values, indicating the
2826 * current speed. */
2827#define NETIO_PARAM_LINK_CURRENT_STATE 7
2828
2829/** Variant symbol for current state, retained for compatibility with
2830 * pre-MDE-2.1 programs. */
2831#define NETIO_PARAM_LINK_STATUS NETIO_PARAM_LINK_CURRENT_STATE
2832
2833/** Packet Coherence protocol. This address is only valid with @ref netio_get().
2834 * The value is nonzero if the interface is configured for cache-coherent DMA.
2835 */
2836#define NETIO_PARAM_COHERENT 8
2837
2838/** Desired link state. The value is a conbination of "NETIO_LINK_xxx"
2839 * flags, which specify the desired state for the link. With @ref
2840 * netio_set(), this will, in the background, attempt to bring up the link
2841 * using whichever of the requested flags are reasonable, or take down the
2842 * link if the flags are zero. The actual link up or down operation may
2843 * happen after this call completes. If the link state changes in the
2844 * future, the system will continue to try to get back to the desired link
2845 * state; for instance, if the link is brought up successfully, and then
2846 * the network cable is disconnected, the link will go down. However, the
2847 * desired state of the link is still up, so if the cable is reconnected,
2848 * the link will be brought up again.
2849 *
2850 * With @ref netio_get(), this will indicate the desired state for the
2851 * link, as set with a previous netio_set() call, or implicitly by a
2852 * netio_input_register() or netio_input_unregister() operation. This may
2853 * not reflect the current state of the link; to get that, use
2854 * ::NETIO_PARAM_LINK_CURRENT_STATE. */
2855#define NETIO_PARAM_LINK_DESIRED_STATE 9
2856
2857/** NetIO statistics structure. Retrieved using the ::NETIO_PARAM_STAT
2858 * address passed to @ref netio_get(). */
2859typedef struct
2860{
2861 /** Number of packets which have been received by the IPP and forwarded
2862 * to a tile's receive queue for processing. This value wraps at its
2863 * maximum, and is not cleared upon read. */
2864 uint32_t packets_received;
2865
2866 /** Number of packets which have been dropped by the IPP, because they could
2867 * not be received, or could not be forwarded to a tile. The former happens
2868 * when the IPP does not have a free packet buffer of suitable size for an
2869 * incoming frame. The latter happens when all potential destination tiles
2870 * for a packet, as defined by the group, bucket, and queue configuration,
2871 * have full receive queues. This value wraps at its maximum, and is not
2872 * cleared upon read. */
2873 uint32_t packets_dropped;
2874
2875 /*
2876 * Note: the #defines after each of the following four one-byte values
2877 * denote their location within the third word of the netio_stat_t. They
2878 * are intended for use only by the IPP implementation and are thus omitted
2879 * from the Doxygen output.
2880 */
2881
2882 /** Number of packets dropped because no worker was able to accept a new
2883 * packet. This value saturates at its maximum, and is cleared upon
2884 * read. */
2885 uint8_t drops_no_worker;
2886#ifndef __DOXYGEN__
2887#define NETIO_STAT_DROPS_NO_WORKER 0
2888#endif
2889
2890 /** Number of packets dropped because no small buffers were available.
2891 * This value saturates at its maximum, and is cleared upon read. */
2892 uint8_t drops_no_smallbuf;
2893#ifndef __DOXYGEN__
2894#define NETIO_STAT_DROPS_NO_SMALLBUF 1
2895#endif
2896
2897 /** Number of packets dropped because no large buffers were available.
2898 * This value saturates at its maximum, and is cleared upon read. */
2899 uint8_t drops_no_largebuf;
2900#ifndef __DOXYGEN__
2901#define NETIO_STAT_DROPS_NO_LARGEBUF 2
2902#endif
2903
2904 /** Number of packets dropped because no jumbo buffers were available.
2905 * This value saturates at its maximum, and is cleared upon read. */
2906 uint8_t drops_no_jumbobuf;
2907#ifndef __DOXYGEN__
2908#define NETIO_STAT_DROPS_NO_JUMBOBUF 3
2909#endif
2910}
2911netio_stat_t;
2912
2913
2914/** Link can run, should run, or is running at 10 Mbps. */
2915#define NETIO_LINK_10M 0x01
2916
2917/** Link can run, should run, or is running at 100 Mbps. */
2918#define NETIO_LINK_100M 0x02
2919
2920/** Link can run, should run, or is running at 1 Gbps. */
2921#define NETIO_LINK_1G 0x04
2922
2923/** Link can run, should run, or is running at 10 Gbps. */
2924#define NETIO_LINK_10G 0x08
2925
2926/** Link should run at the highest speed supported by the link and by
2927 * the device connected to the link. Only usable as a value for
2928 * the link's desired state; never returned as a value for the current
2929 * or possible states. */
2930#define NETIO_LINK_ANYSPEED 0x10
2931
2932/** All legal link speeds. */
2933#define NETIO_LINK_SPEED (NETIO_LINK_10M | \
2934 NETIO_LINK_100M | \
2935 NETIO_LINK_1G | \
2936 NETIO_LINK_10G | \
2937 NETIO_LINK_ANYSPEED)
2938
2939
2940/** MAC register class. Addr is a register offset within the MAC.
2941 * Registers within the XGbE and GbE MACs are documented in the Tile
2942 * Processor I/O Device Guide (UG104). MAC registers start at address
2943 * 0x4000, and do not include the MAC_INTERFACE registers. */
2944#define NETIO_MAC 1
2945
2946/** MDIO register class (IEEE 802.3 clause 22 format). Addr is the "addr"
2947 * member of a netio_mdio_addr_t structure. */
2948#define NETIO_MDIO 2
2949
2950/** MDIO register class (IEEE 802.3 clause 45 format). Addr is the "addr"
2951 * member of a netio_mdio_addr_t structure. */
2952#define NETIO_MDIO_CLAUSE45 3
2953
2954/** NetIO MDIO address type. Retrieved or provided using the ::NETIO_MDIO
2955 * address passed to @ref netio_get() or @ref netio_set(). */
2956typedef union
2957{
2958 struct
2959 {
2960 unsigned int reg:16; /**< MDIO register offset. For clause 22 access,
2961 must be less than 32. */
2962 unsigned int phy:5; /**< Which MDIO PHY to access. */
2963 unsigned int dev:5; /**< Which MDIO device to access within that PHY.
2964 Applicable for clause 45 access only; ignored
2965 for clause 22 access. */
2966 }
2967 bits; /**< Container for bitfields. */
2968 uint64_t addr; /**< Value to pass to @ref netio_get() or
2969 * @ref netio_set(). */
2970}
2971netio_mdio_addr_t;
2972
2973/** @} */
2974
2975#endif /* __NETIO_INTF_H__ */
diff --git a/arch/tile/include/hv/pagesize.h b/arch/tile/include/hv/pagesize.h
deleted file mode 100644
index 58bed114fedd..000000000000
--- a/arch/tile/include/hv/pagesize.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file pagesize.h
17 */
18
19#ifndef _HV_PAGESIZE_H
20#define _HV_PAGESIZE_H
21
22/** The log2 of the size of small pages, in bytes. This value should
23 * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
24 */
25#define HV_LOG2_PAGE_SIZE_SMALL 16
26
27/** The log2 of the size of large pages, in bytes. This value should be
28 * verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
29 */
30#define HV_LOG2_PAGE_SIZE_LARGE 24
31
32#endif /* _HV_PAGESIZE_H */
diff --git a/arch/tile/kernel/Makefile b/arch/tile/kernel/Makefile
index 112b1e248f05..b4dbc057baad 100644
--- a/arch/tile/kernel/Makefile
+++ b/arch/tile/kernel/Makefile
@@ -5,7 +5,7 @@
5extra-y := vmlinux.lds head_$(BITS).o 5extra-y := vmlinux.lds head_$(BITS).o
6obj-y := backtrace.o entry.o init_task.o irq.o messaging.o \ 6obj-y := backtrace.o entry.o init_task.o irq.o messaging.o \
7 pci-dma.o proc.o process.o ptrace.o reboot.o \ 7 pci-dma.o proc.o process.o ptrace.o reboot.o \
8 setup.o signal.o single_step.o stack.o sys.o time.o traps.o \ 8 setup.o signal.o single_step.o stack.o sys.o sysfs.o time.o traps.o \
9 intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o 9 intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o
10 10
11obj-$(CONFIG_HARDWALL) += hardwall.o 11obj-$(CONFIG_HARDWALL) += hardwall.o
@@ -15,3 +15,4 @@ obj-$(CONFIG_SMP) += smpboot.o smp.o tlb.o
15obj-$(CONFIG_MODULES) += module.o 15obj-$(CONFIG_MODULES) += module.o
16obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 16obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
17obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o 17obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
18obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c
index d3c41c1ff6bd..1dc71eabfc5a 100644
--- a/arch/tile/kernel/backtrace.c
+++ b/arch/tile/kernel/backtrace.c
@@ -14,19 +14,11 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/string.h> 16#include <linux/string.h>
17
18#include <asm/backtrace.h> 17#include <asm/backtrace.h>
19
20#include <arch/chip.h>
21
22#include <asm/opcode-tile.h> 18#include <asm/opcode-tile.h>
19#include <arch/abi.h>
23 20
24 21#ifdef __tilegx__
25#define TREG_SP 54
26#define TREG_LR 55
27
28
29#if TILE_CHIP >= 10
30#define tile_bundle_bits tilegx_bundle_bits 22#define tile_bundle_bits tilegx_bundle_bits
31#define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE 23#define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE
32#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES 24#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
@@ -47,7 +39,7 @@ typedef long long bt_int_reg_t;
47typedef int bt_int_reg_t; 39typedef int bt_int_reg_t;
48#endif 40#endif
49 41
50/** A decoded bundle used for backtracer analysis. */ 42/* A decoded bundle used for backtracer analysis. */
51struct BacktraceBundle { 43struct BacktraceBundle {
52 tile_bundle_bits bits; 44 tile_bundle_bits bits;
53 int num_insns; 45 int num_insns;
@@ -56,23 +48,7 @@ struct BacktraceBundle {
56}; 48};
57 49
58 50
59/* This implementation only makes sense for native tools. */ 51/* Locates an instruction inside the given bundle that
60/** Default function to read memory. */
61static bool bt_read_memory(void *result, VirtualAddress addr,
62 unsigned int size, void *extra)
63{
64 /* FIXME: this should do some horrible signal stuff to catch
65 * SEGV cleanly and fail.
66 *
67 * Or else the caller should do the setjmp for efficiency.
68 */
69
70 memcpy(result, (const void *)addr, size);
71 return true;
72}
73
74
75/** Locates an instruction inside the given bundle that
76 * has the specified mnemonic, and whose first 'num_operands_to_match' 52 * has the specified mnemonic, and whose first 'num_operands_to_match'
77 * operands exactly match those in 'operand_values'. 53 * operands exactly match those in 'operand_values'.
78 */ 54 */
@@ -107,13 +83,13 @@ static const struct tile_decoded_instruction *find_matching_insn(
107 return NULL; 83 return NULL;
108} 84}
109 85
110/** Does this bundle contain an 'iret' instruction? */ 86/* Does this bundle contain an 'iret' instruction? */
111static inline bool bt_has_iret(const struct BacktraceBundle *bundle) 87static inline bool bt_has_iret(const struct BacktraceBundle *bundle)
112{ 88{
113 return find_matching_insn(bundle, TILE_OPC_IRET, NULL, 0) != NULL; 89 return find_matching_insn(bundle, TILE_OPC_IRET, NULL, 0) != NULL;
114} 90}
115 91
116/** Does this bundle contain an 'addi sp, sp, OFFSET' or 92/* Does this bundle contain an 'addi sp, sp, OFFSET' or
117 * 'addli sp, sp, OFFSET' instruction, and if so, what is OFFSET? 93 * 'addli sp, sp, OFFSET' instruction, and if so, what is OFFSET?
118 */ 94 */
119static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust) 95static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
@@ -124,7 +100,7 @@ static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
124 find_matching_insn(bundle, TILE_OPC_ADDI, vals, 2); 100 find_matching_insn(bundle, TILE_OPC_ADDI, vals, 2);
125 if (insn == NULL) 101 if (insn == NULL)
126 insn = find_matching_insn(bundle, TILE_OPC_ADDLI, vals, 2); 102 insn = find_matching_insn(bundle, TILE_OPC_ADDLI, vals, 2);
127#if TILE_CHIP >= 10 103#ifdef __tilegx__
128 if (insn == NULL) 104 if (insn == NULL)
129 insn = find_matching_insn(bundle, TILEGX_OPC_ADDXLI, vals, 2); 105 insn = find_matching_insn(bundle, TILEGX_OPC_ADDXLI, vals, 2);
130 if (insn == NULL) 106 if (insn == NULL)
@@ -137,7 +113,7 @@ static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
137 return true; 113 return true;
138} 114}
139 115
140/** Does this bundle contain any 'info OP' or 'infol OP' 116/* Does this bundle contain any 'info OP' or 'infol OP'
141 * instruction, and if so, what are their OP? Note that OP is interpreted 117 * instruction, and if so, what are their OP? Note that OP is interpreted
142 * as an unsigned value by this code since that's what the caller wants. 118 * as an unsigned value by this code since that's what the caller wants.
143 * Returns the number of info ops found. 119 * Returns the number of info ops found.
@@ -161,7 +137,7 @@ static int bt_get_info_ops(const struct BacktraceBundle *bundle,
161 return num_ops; 137 return num_ops;
162} 138}
163 139
164/** Does this bundle contain a jrp instruction, and if so, to which 140/* Does this bundle contain a jrp instruction, and if so, to which
165 * register is it jumping? 141 * register is it jumping?
166 */ 142 */
167static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg) 143static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg)
@@ -175,7 +151,7 @@ static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg)
175 return true; 151 return true;
176} 152}
177 153
178/** Does this bundle modify the specified register in any way? */ 154/* Does this bundle modify the specified register in any way? */
179static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg) 155static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg)
180{ 156{
181 int i, j; 157 int i, j;
@@ -195,34 +171,34 @@ static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg)
195 return false; 171 return false;
196} 172}
197 173
198/** Does this bundle modify sp? */ 174/* Does this bundle modify sp? */
199static inline bool bt_modifies_sp(const struct BacktraceBundle *bundle) 175static inline bool bt_modifies_sp(const struct BacktraceBundle *bundle)
200{ 176{
201 return bt_modifies_reg(bundle, TREG_SP); 177 return bt_modifies_reg(bundle, TREG_SP);
202} 178}
203 179
204/** Does this bundle modify lr? */ 180/* Does this bundle modify lr? */
205static inline bool bt_modifies_lr(const struct BacktraceBundle *bundle) 181static inline bool bt_modifies_lr(const struct BacktraceBundle *bundle)
206{ 182{
207 return bt_modifies_reg(bundle, TREG_LR); 183 return bt_modifies_reg(bundle, TREG_LR);
208} 184}
209 185
210/** Does this bundle contain the instruction 'move fp, sp'? */ 186/* Does this bundle contain the instruction 'move fp, sp'? */
211static inline bool bt_has_move_r52_sp(const struct BacktraceBundle *bundle) 187static inline bool bt_has_move_r52_sp(const struct BacktraceBundle *bundle)
212{ 188{
213 static const int vals[2] = { 52, TREG_SP }; 189 static const int vals[2] = { 52, TREG_SP };
214 return find_matching_insn(bundle, TILE_OPC_MOVE, vals, 2) != NULL; 190 return find_matching_insn(bundle, TILE_OPC_MOVE, vals, 2) != NULL;
215} 191}
216 192
217/** Does this bundle contain a store of lr to sp? */ 193/* Does this bundle contain a store of lr to sp? */
218static inline bool bt_has_sw_sp_lr(const struct BacktraceBundle *bundle) 194static inline bool bt_has_sw_sp_lr(const struct BacktraceBundle *bundle)
219{ 195{
220 static const int vals[2] = { TREG_SP, TREG_LR }; 196 static const int vals[2] = { TREG_SP, TREG_LR };
221 return find_matching_insn(bundle, OPCODE_STORE, vals, 2) != NULL; 197 return find_matching_insn(bundle, OPCODE_STORE, vals, 2) != NULL;
222} 198}
223 199
224#if TILE_CHIP >= 10 200#ifdef __tilegx__
225/** Track moveli values placed into registers. */ 201/* Track moveli values placed into registers. */
226static inline void bt_update_moveli(const struct BacktraceBundle *bundle, 202static inline void bt_update_moveli(const struct BacktraceBundle *bundle,
227 int moveli_args[]) 203 int moveli_args[])
228{ 204{
@@ -238,7 +214,7 @@ static inline void bt_update_moveli(const struct BacktraceBundle *bundle,
238 } 214 }
239} 215}
240 216
241/** Does this bundle contain an 'add sp, sp, reg' instruction 217/* Does this bundle contain an 'add sp, sp, reg' instruction
242 * from a register that we saw a moveli into, and if so, what 218 * from a register that we saw a moveli into, and if so, what
243 * is the value in the register? 219 * is the value in the register?
244 */ 220 */
@@ -260,11 +236,11 @@ static bool bt_has_add_sp(const struct BacktraceBundle *bundle, int *adjust,
260} 236}
261#endif 237#endif
262 238
263/** Locates the caller's PC and SP for a program starting at the 239/* Locates the caller's PC and SP for a program starting at the
264 * given address. 240 * given address.
265 */ 241 */
266static void find_caller_pc_and_caller_sp(CallerLocation *location, 242static void find_caller_pc_and_caller_sp(CallerLocation *location,
267 const VirtualAddress start_pc, 243 const unsigned long start_pc,
268 BacktraceMemoryReader read_memory_func, 244 BacktraceMemoryReader read_memory_func,
269 void *read_memory_func_extra) 245 void *read_memory_func_extra)
270{ 246{
@@ -288,9 +264,9 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
288 tile_bundle_bits prefetched_bundles[32]; 264 tile_bundle_bits prefetched_bundles[32];
289 int num_bundles_prefetched = 0; 265 int num_bundles_prefetched = 0;
290 int next_bundle = 0; 266 int next_bundle = 0;
291 VirtualAddress pc; 267 unsigned long pc;
292 268
293#if TILE_CHIP >= 10 269#ifdef __tilegx__
294 /* Naively try to track moveli values to support addx for -m32. */ 270 /* Naively try to track moveli values to support addx for -m32. */
295 int moveli_args[TILEGX_NUM_REGISTERS] = { 0 }; 271 int moveli_args[TILEGX_NUM_REGISTERS] = { 0 };
296#endif 272#endif
@@ -449,7 +425,7 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
449 if (!sp_determined) { 425 if (!sp_determined) {
450 int adjust; 426 int adjust;
451 if (bt_has_addi_sp(&bundle, &adjust) 427 if (bt_has_addi_sp(&bundle, &adjust)
452#if TILE_CHIP >= 10 428#ifdef __tilegx__
453 || bt_has_add_sp(&bundle, &adjust, moveli_args) 429 || bt_has_add_sp(&bundle, &adjust, moveli_args)
454#endif 430#endif
455 ) { 431 ) {
@@ -500,7 +476,7 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
500 } 476 }
501 } 477 }
502 478
503#if TILE_CHIP >= 10 479#ifdef __tilegx__
504 /* Track moveli arguments for -m32 mode. */ 480 /* Track moveli arguments for -m32 mode. */
505 bt_update_moveli(&bundle, moveli_args); 481 bt_update_moveli(&bundle, moveli_args);
506#endif 482#endif
@@ -542,18 +518,26 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
542 } 518 }
543} 519}
544 520
521/* Initializes a backtracer to start from the given location.
522 *
523 * If the frame pointer cannot be determined it is set to -1.
524 *
525 * state: The state to be filled in.
526 * read_memory_func: A callback that reads memory.
527 * read_memory_func_extra: An arbitrary argument to read_memory_func.
528 * pc: The current PC.
529 * lr: The current value of the 'lr' register.
530 * sp: The current value of the 'sp' register.
531 * r52: The current value of the 'r52' register.
532 */
545void backtrace_init(BacktraceIterator *state, 533void backtrace_init(BacktraceIterator *state,
546 BacktraceMemoryReader read_memory_func, 534 BacktraceMemoryReader read_memory_func,
547 void *read_memory_func_extra, 535 void *read_memory_func_extra,
548 VirtualAddress pc, VirtualAddress lr, 536 unsigned long pc, unsigned long lr,
549 VirtualAddress sp, VirtualAddress r52) 537 unsigned long sp, unsigned long r52)
550{ 538{
551 CallerLocation location; 539 CallerLocation location;
552 VirtualAddress fp, initial_frame_caller_pc; 540 unsigned long fp, initial_frame_caller_pc;
553
554 if (read_memory_func == NULL) {
555 read_memory_func = bt_read_memory;
556 }
557 541
558 /* Find out where we are in the initial frame. */ 542 /* Find out where we are in the initial frame. */
559 find_caller_pc_and_caller_sp(&location, pc, 543 find_caller_pc_and_caller_sp(&location, pc,
@@ -626,12 +610,15 @@ void backtrace_init(BacktraceIterator *state,
626/* Handle the case where the register holds more bits than the VA. */ 610/* Handle the case where the register holds more bits than the VA. */
627static bool valid_addr_reg(bt_int_reg_t reg) 611static bool valid_addr_reg(bt_int_reg_t reg)
628{ 612{
629 return ((VirtualAddress)reg == reg); 613 return ((unsigned long)reg == reg);
630} 614}
631 615
616/* Advances the backtracing state to the calling frame, returning
617 * true iff successful.
618 */
632bool backtrace_next(BacktraceIterator *state) 619bool backtrace_next(BacktraceIterator *state)
633{ 620{
634 VirtualAddress next_fp, next_pc; 621 unsigned long next_fp, next_pc;
635 bt_int_reg_t next_frame[2]; 622 bt_int_reg_t next_frame[2];
636 623
637 if (state->fp == -1) { 624 if (state->fp == -1) {
diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c
index b1e06d041555..bf5e9d70266c 100644
--- a/arch/tile/kernel/compat.c
+++ b/arch/tile/kernel/compat.c
@@ -21,7 +21,6 @@
21#include <linux/kdev_t.h> 21#include <linux/kdev_t.h>
22#include <linux/fs.h> 22#include <linux/fs.h>
23#include <linux/fcntl.h> 23#include <linux/fcntl.h>
24#include <linux/smp_lock.h>
25#include <linux/uaccess.h> 24#include <linux/uaccess.h>
26#include <linux/signal.h> 25#include <linux/signal.h>
27#include <asm/syscalls.h> 26#include <asm/syscalls.h>
@@ -136,26 +135,21 @@ long tile_compat_sys_msgrcv(int msqid,
136 135
137/* Provide the compat syscall number to call mapping. */ 136/* Provide the compat syscall number to call mapping. */
138#undef __SYSCALL 137#undef __SYSCALL
139#define __SYSCALL(nr, call) [nr] = (compat_##call), 138#define __SYSCALL(nr, call) [nr] = (call),
140 139
141/* The generic versions of these don't work for Tile. */ 140/* The generic versions of these don't work for Tile. */
142#define compat_sys_msgrcv tile_compat_sys_msgrcv 141#define compat_sys_msgrcv tile_compat_sys_msgrcv
143#define compat_sys_msgsnd tile_compat_sys_msgsnd 142#define compat_sys_msgsnd tile_compat_sys_msgsnd
144 143
145/* See comments in sys.c */ 144/* See comments in sys.c */
146#define compat_sys_fadvise64 sys32_fadvise64
147#define compat_sys_fadvise64_64 sys32_fadvise64_64 145#define compat_sys_fadvise64_64 sys32_fadvise64_64
148#define compat_sys_readahead sys32_readahead 146#define compat_sys_readahead sys32_readahead
149#define compat_sys_sync_file_range compat_sys_sync_file_range2
150 147
151/* The native 64-bit "struct stat" matches the 32-bit "struct stat64". */ 148/* Call the trampolines to manage pt_regs where necessary. */
152#define compat_sys_stat64 sys_newstat 149#define compat_sys_execve _compat_sys_execve
153#define compat_sys_lstat64 sys_newlstat 150#define compat_sys_sigaltstack _compat_sys_sigaltstack
154#define compat_sys_fstat64 sys_newfstat 151#define compat_sys_rt_sigreturn _compat_sys_rt_sigreturn
155#define compat_sys_fstatat64 sys_newfstatat 152#define sys_clone _sys_clone
156
157/* Pass full 64-bit values through ptrace. */
158#define compat_sys_ptrace tile_compat_sys_ptrace
159 153
160/* 154/*
161 * Note that we can't include <linux/unistd.h> here since the header 155 * Note that we can't include <linux/unistd.h> here since the header
diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c
index 9c710db43f13..a7869ad62776 100644
--- a/arch/tile/kernel/compat_signal.c
+++ b/arch/tile/kernel/compat_signal.c
@@ -15,7 +15,6 @@
15#include <linux/sched.h> 15#include <linux/sched.h>
16#include <linux/mm.h> 16#include <linux/mm.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <linux/smp_lock.h>
19#include <linux/kernel.h> 18#include <linux/kernel.h>
20#include <linux/signal.h> 19#include <linux/signal.h>
21#include <linux/errno.h> 20#include <linux/errno.h>
@@ -256,9 +255,9 @@ int copy_siginfo_from_user32(siginfo_t *to, struct compat_siginfo __user *from)
256 return err; 255 return err;
257} 256}
258 257
259long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, 258long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
260 struct compat_sigaltstack __user *uoss_ptr, 259 struct compat_sigaltstack __user *uoss_ptr,
261 struct pt_regs *regs) 260 struct pt_regs *regs)
262{ 261{
263 stack_t uss, uoss; 262 stack_t uss, uoss;
264 int ret; 263 int ret;
@@ -291,12 +290,12 @@ long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
291 return ret; 290 return ret;
292} 291}
293 292
294long _compat_sys_rt_sigreturn(struct pt_regs *regs) 293/* The assembly shim for this function arranges to ignore the return value. */
294long compat_sys_rt_sigreturn(struct pt_regs *regs)
295{ 295{
296 struct compat_rt_sigframe __user *frame = 296 struct compat_rt_sigframe __user *frame =
297 (struct compat_rt_sigframe __user *) compat_ptr(regs->sp); 297 (struct compat_rt_sigframe __user *) compat_ptr(regs->sp);
298 sigset_t set; 298 sigset_t set;
299 long r0;
300 299
301 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 300 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
302 goto badframe; 301 goto badframe;
@@ -309,16 +308,16 @@ long _compat_sys_rt_sigreturn(struct pt_regs *regs)
309 recalc_sigpending(); 308 recalc_sigpending();
310 spin_unlock_irq(&current->sighand->siglock); 309 spin_unlock_irq(&current->sighand->siglock);
311 310
312 if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) 311 if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
313 goto badframe; 312 goto badframe;
314 313
315 if (_compat_sys_sigaltstack(&frame->uc.uc_stack, NULL, regs) != 0) 314 if (compat_sys_sigaltstack(&frame->uc.uc_stack, NULL, regs) != 0)
316 goto badframe; 315 goto badframe;
317 316
318 return r0; 317 return 0;
319 318
320badframe: 319badframe:
321 force_sig(SIGSEGV, current); 320 signal_fault("bad sigreturn frame", regs, frame, 0);
322 return 0; 321 return 0;
323} 322}
324 323
@@ -432,6 +431,6 @@ int compat_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
432 return 0; 431 return 0;
433 432
434give_sigsegv: 433give_sigsegv:
435 force_sigsegv(sig, current); 434 signal_fault("bad setup frame", regs, frame, sig);
436 return -EFAULT; 435 return -EFAULT;
437} 436}
diff --git a/arch/tile/kernel/early_printk.c b/arch/tile/kernel/early_printk.c
index 2c54fd43a8a0..493a0e66d916 100644
--- a/arch/tile/kernel/early_printk.c
+++ b/arch/tile/kernel/early_printk.c
@@ -54,7 +54,7 @@ void early_printk(const char *fmt, ...)
54void early_panic(const char *fmt, ...) 54void early_panic(const char *fmt, ...)
55{ 55{
56 va_list ap; 56 va_list ap;
57 raw_local_irq_disable_all(); 57 arch_local_irq_disable_all();
58 va_start(ap, fmt); 58 va_start(ap, fmt);
59 early_printk("Kernel panic - not syncing: "); 59 early_printk("Kernel panic - not syncing: ");
60 early_vprintk(fmt, ap); 60 early_vprintk(fmt, ap);
diff --git a/arch/tile/kernel/entry.S b/arch/tile/kernel/entry.S
index 3d01383b1b0e..431e9ae60488 100644
--- a/arch/tile/kernel/entry.S
+++ b/arch/tile/kernel/entry.S
@@ -15,7 +15,9 @@
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <linux/unistd.h> 16#include <linux/unistd.h>
17#include <asm/irqflags.h> 17#include <asm/irqflags.h>
18#include <asm/processor.h>
18#include <arch/abi.h> 19#include <arch/abi.h>
20#include <arch/spr_def.h>
19 21
20#ifdef __tilegx__ 22#ifdef __tilegx__
21#define bnzt bnezt 23#define bnzt bnezt
@@ -25,28 +27,6 @@ STD_ENTRY(current_text_addr)
25 { move r0, lr; jrp lr } 27 { move r0, lr; jrp lr }
26 STD_ENDPROC(current_text_addr) 28 STD_ENDPROC(current_text_addr)
27 29
28STD_ENTRY(_sim_syscall)
29 /*
30 * Wait for r0-r9 to be ready (and lr on the off chance we
31 * want the syscall to locate its caller), then make a magic
32 * simulator syscall.
33 *
34 * We carefully stall until the registers are readable in case they
35 * are the target of a slow load, etc. so that tile-sim will
36 * definitely be able to read all of them inside the magic syscall.
37 *
38 * Technically this is wrong for r3-r9 and lr, since an interrupt
39 * could come in and restore the registers with a slow load right
40 * before executing the mtspr. We may need to modify tile-sim to
41 * explicitly stall for this case, but we do not yet have
42 * a way to implement such a stall.
43 */
44 { and zero, lr, r9 ; and zero, r8, r7 }
45 { and zero, r6, r5 ; and zero, r4, r3 }
46 { and zero, r2, r1 ; mtspr SIM_CONTROL, r0 }
47 { jrp lr }
48 STD_ENDPROC(_sim_syscall)
49
50/* 30/*
51 * Implement execve(). The i386 code has a note that forking from kernel 31 * Implement execve(). The i386 code has a note that forking from kernel
52 * space results in no copy on write until the execve, so we should be 32 * space results in no copy on write until the execve, so we should be
@@ -58,12 +38,6 @@ STD_ENTRY(kernel_execve)
58 jrp lr 38 jrp lr
59 STD_ENDPROC(kernel_execve) 39 STD_ENDPROC(kernel_execve)
60 40
61/* Delay a fixed number of cycles. */
62STD_ENTRY(__delay)
63 { addi r0, r0, -1; bnzt r0, . }
64 jrp lr
65 STD_ENDPROC(__delay)
66
67/* 41/*
68 * We don't run this function directly, but instead copy it to a page 42 * We don't run this function directly, but instead copy it to a page
69 * we map into every user process. See vdso_setup(). 43 * we map into every user process. See vdso_setup().
@@ -102,7 +76,7 @@ STD_ENTRY(KBacktraceIterator_init_current)
102STD_ENTRY(cpu_idle_on_new_stack) 76STD_ENTRY(cpu_idle_on_new_stack)
103 { 77 {
104 move sp, r1 78 move sp, r1
105 mtspr SYSTEM_SAVE_1_0, r2 79 mtspr SPR_SYSTEM_SAVE_K_0, r2
106 } 80 }
107 jal free_thread_info 81 jal free_thread_info
108 j cpu_idle 82 j cpu_idle
@@ -117,23 +91,17 @@ STD_ENTRY(smp_nap)
117 91
118/* 92/*
119 * Enable interrupts racelessly and then nap until interrupted. 93 * Enable interrupts racelessly and then nap until interrupted.
94 * Architecturally, we are guaranteed that enabling interrupts via
95 * mtspr to INTERRUPT_CRITICAL_SECTION only interrupts at the next PC.
120 * This function's _cpu_idle_nap address is special; see intvec.S. 96 * This function's _cpu_idle_nap address is special; see intvec.S.
121 * When interrupted at _cpu_idle_nap, we bump the PC forward 8, and 97 * When interrupted at _cpu_idle_nap, we bump the PC forward 8, and
122 * as a result return to the function that called _cpu_idle(). 98 * as a result return to the function that called _cpu_idle().
123 */ 99 */
124STD_ENTRY(_cpu_idle) 100STD_ENTRY(_cpu_idle)
125 { 101 movei r1, 1
126 lnk r0 102 mtspr INTERRUPT_CRITICAL_SECTION, r1
127 movei r1, 1 103 IRQ_ENABLE(r2, r3) /* unmask, but still with ICS set */
128 } 104 mtspr INTERRUPT_CRITICAL_SECTION, zero
129 {
130 addli r0, r0, _cpu_idle_nap - .
131 mtspr INTERRUPT_CRITICAL_SECTION, r1
132 }
133 IRQ_ENABLE(r2, r3) /* unmask, but still with ICS set */
134 mtspr EX_CONTEXT_1_1, r1 /* PL1, ICS clear */
135 mtspr EX_CONTEXT_1_0, r0
136 iret
137 .global _cpu_idle_nap 105 .global _cpu_idle_nap
138_cpu_idle_nap: 106_cpu_idle_nap:
139 nap 107 nap
diff --git a/arch/tile/kernel/futex_64.S b/arch/tile/kernel/futex_64.S
new file mode 100644
index 000000000000..f465d1eda20f
--- /dev/null
+++ b/arch/tile/kernel/futex_64.S
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Atomically access user memory, but use MMU to avoid propagating
15 * kernel exceptions.
16 */
17
18#include <linux/linkage.h>
19#include <asm/errno.h>
20#include <asm/futex.h>
21#include <asm/page.h>
22#include <asm/processor.h>
23
24/*
25 * Provide a set of atomic memory operations supporting <asm/futex.h>.
26 *
27 * r0: user address to manipulate
28 * r1: new value to write, or for cmpxchg, old value to compare against
29 * r2: (cmpxchg only) new value to write
30 *
31 * Return __get_user struct, r0 with value, r1 with error.
32 */
33#define FUTEX_OP(name, ...) \
34STD_ENTRY(futex_##name) \
35 __VA_ARGS__; \
36 { \
37 move r1, zero; \
38 jrp lr \
39 }; \
40 STD_ENDPROC(futex_##name); \
41 .pushsection __ex_table,"a"; \
42 .quad 1b, get_user_fault; \
43 .popsection
44
45 .pushsection .fixup,"ax"
46get_user_fault:
47 { movei r1, -EFAULT; jrp lr }
48 ENDPROC(get_user_fault)
49 .popsection
50
51FUTEX_OP(cmpxchg, mtspr CMPEXCH_VALUE, r1; 1: cmpexch4 r0, r0, r2)
52FUTEX_OP(set, 1: exch4 r0, r0, r1)
53FUTEX_OP(add, 1: fetchadd4 r0, r0, r1)
54FUTEX_OP(or, 1: fetchor4 r0, r0, r1)
55FUTEX_OP(andn, nor r1, r1, zero; 1: fetchand4 r0, r0, r1)
diff --git a/arch/tile/kernel/hardwall.c b/arch/tile/kernel/hardwall.c
index 584b965dc824..8c41891aab34 100644
--- a/arch/tile/kernel/hardwall.c
+++ b/arch/tile/kernel/hardwall.c
@@ -40,16 +40,25 @@
40struct hardwall_info { 40struct hardwall_info {
41 struct list_head list; /* "rectangles" list */ 41 struct list_head list; /* "rectangles" list */
42 struct list_head task_head; /* head of tasks in this hardwall */ 42 struct list_head task_head; /* head of tasks in this hardwall */
43 struct cpumask cpumask; /* cpus in the rectangle */
43 int ulhc_x; /* upper left hand corner x coord */ 44 int ulhc_x; /* upper left hand corner x coord */
44 int ulhc_y; /* upper left hand corner y coord */ 45 int ulhc_y; /* upper left hand corner y coord */
45 int width; /* rectangle width */ 46 int width; /* rectangle width */
46 int height; /* rectangle height */ 47 int height; /* rectangle height */
48 int id; /* integer id for this hardwall */
47 int teardown_in_progress; /* are we tearing this one down? */ 49 int teardown_in_progress; /* are we tearing this one down? */
48}; 50};
49 51
50/* Currently allocated hardwall rectangles */ 52/* Currently allocated hardwall rectangles */
51static LIST_HEAD(rectangles); 53static LIST_HEAD(rectangles);
52 54
55/* /proc/tile/hardwall */
56static struct proc_dir_entry *hardwall_proc_dir;
57
58/* Functions to manage files in /proc/tile/hardwall. */
59static void hardwall_add_proc(struct hardwall_info *rect);
60static void hardwall_remove_proc(struct hardwall_info *rect);
61
53/* 62/*
54 * Guard changes to the hardwall data structures. 63 * Guard changes to the hardwall data structures.
55 * This could be finer grained (e.g. one lock for the list of hardwall 64 * This could be finer grained (e.g. one lock for the list of hardwall
@@ -105,6 +114,8 @@ static int setup_rectangle(struct hardwall_info *r, struct cpumask *mask)
105 r->ulhc_y = cpu_y(ulhc); 114 r->ulhc_y = cpu_y(ulhc);
106 r->width = cpu_x(lrhc) - r->ulhc_x + 1; 115 r->width = cpu_x(lrhc) - r->ulhc_x + 1;
107 r->height = cpu_y(lrhc) - r->ulhc_y + 1; 116 r->height = cpu_y(lrhc) - r->ulhc_y + 1;
117 cpumask_copy(&r->cpumask, mask);
118 r->id = ulhc; /* The ulhc cpu id can be the hardwall id. */
108 119
109 /* Width and height must be positive */ 120 /* Width and height must be positive */
110 if (r->width <= 0 || r->height <= 0) 121 if (r->width <= 0 || r->height <= 0)
@@ -151,12 +162,12 @@ enum direction_protect {
151 162
152static void enable_firewall_interrupts(void) 163static void enable_firewall_interrupts(void)
153{ 164{
154 raw_local_irq_unmask_now(INT_UDN_FIREWALL); 165 arch_local_irq_unmask_now(INT_UDN_FIREWALL);
155} 166}
156 167
157static void disable_firewall_interrupts(void) 168static void disable_firewall_interrupts(void)
158{ 169{
159 raw_local_irq_mask_now(INT_UDN_FIREWALL); 170 arch_local_irq_mask_now(INT_UDN_FIREWALL);
160} 171}
161 172
162/* Set up hardwall on this cpu based on the passed hardwall_info. */ 173/* Set up hardwall on this cpu based on the passed hardwall_info. */
@@ -268,12 +279,10 @@ void __kprobes do_hardwall_trap(struct pt_regs* regs, int fault_num)
268 found_processes = 0; 279 found_processes = 0;
269 list_for_each_entry(p, &rect->task_head, thread.hardwall_list) { 280 list_for_each_entry(p, &rect->task_head, thread.hardwall_list) {
270 BUG_ON(p->thread.hardwall != rect); 281 BUG_ON(p->thread.hardwall != rect);
271 if (p->sighand) { 282 if (!(p->flags & PF_EXITING)) {
272 found_processes = 1; 283 found_processes = 1;
273 pr_notice("hardwall: killing %d\n", p->pid); 284 pr_notice("hardwall: killing %d\n", p->pid);
274 spin_lock(&p->sighand->siglock); 285 do_send_sig_info(info.si_signo, &info, p, false);
275 __group_send_sig_info(info.si_signo, &info, p);
276 spin_unlock(&p->sighand->siglock);
277 } 286 }
278 } 287 }
279 if (!found_processes) 288 if (!found_processes)
@@ -390,6 +399,9 @@ static struct hardwall_info *hardwall_create(
390 /* Set up appropriate hardwalling on all affected cpus. */ 399 /* Set up appropriate hardwalling on all affected cpus. */
391 hardwall_setup(rect); 400 hardwall_setup(rect);
392 401
402 /* Create a /proc/tile/hardwall entry. */
403 hardwall_add_proc(rect);
404
393 return rect; 405 return rect;
394} 406}
395 407
@@ -647,6 +659,9 @@ static void hardwall_destroy(struct hardwall_info *rect)
647 /* Restart switch and disable firewall. */ 659 /* Restart switch and disable firewall. */
648 on_each_cpu_mask(&mask, restart_udn_switch, NULL, 1); 660 on_each_cpu_mask(&mask, restart_udn_switch, NULL, 1);
649 661
662 /* Remove the /proc/tile/hardwall entry. */
663 hardwall_remove_proc(rect);
664
650 /* Now free the rectangle from the list. */ 665 /* Now free the rectangle from the list. */
651 spin_lock_irqsave(&hardwall_lock, flags); 666 spin_lock_irqsave(&hardwall_lock, flags);
652 BUG_ON(!list_empty(&rect->task_head)); 667 BUG_ON(!list_empty(&rect->task_head));
@@ -656,35 +671,57 @@ static void hardwall_destroy(struct hardwall_info *rect)
656} 671}
657 672
658 673
659/* 674static int hardwall_proc_show(struct seq_file *sf, void *v)
660 * Dump hardwall state via /proc; initialized in arch/tile/sys/proc.c.
661 */
662int proc_tile_hardwall_show(struct seq_file *sf, void *v)
663{ 675{
664 struct hardwall_info *r; 676 struct hardwall_info *rect = sf->private;
677 char buf[256];
665 678
666 if (udn_disabled) { 679 int rc = cpulist_scnprintf(buf, sizeof(buf), &rect->cpumask);
667 seq_printf(sf, "%dx%d 0,0 pids:\n", smp_width, smp_height); 680 buf[rc++] = '\n';
668 return 0; 681 seq_write(sf, buf, rc);
669 }
670
671 spin_lock_irq(&hardwall_lock);
672 list_for_each_entry(r, &rectangles, list) {
673 struct task_struct *p;
674 seq_printf(sf, "%dx%d %d,%d pids:",
675 r->width, r->height, r->ulhc_x, r->ulhc_y);
676 list_for_each_entry(p, &r->task_head, thread.hardwall_list) {
677 unsigned int cpu = cpumask_first(&p->cpus_allowed);
678 unsigned int x = cpu % smp_width;
679 unsigned int y = cpu / smp_width;
680 seq_printf(sf, " %d@%d,%d", p->pid, x, y);
681 }
682 seq_printf(sf, "\n");
683 }
684 spin_unlock_irq(&hardwall_lock);
685 return 0; 682 return 0;
686} 683}
687 684
685static int hardwall_proc_open(struct inode *inode,
686 struct file *file)
687{
688 return single_open(file, hardwall_proc_show, PDE(inode)->data);
689}
690
691static const struct file_operations hardwall_proc_fops = {
692 .open = hardwall_proc_open,
693 .read = seq_read,
694 .llseek = seq_lseek,
695 .release = single_release,
696};
697
698static void hardwall_add_proc(struct hardwall_info *rect)
699{
700 char buf[64];
701 snprintf(buf, sizeof(buf), "%d", rect->id);
702 proc_create_data(buf, 0444, hardwall_proc_dir,
703 &hardwall_proc_fops, rect);
704}
705
706static void hardwall_remove_proc(struct hardwall_info *rect)
707{
708 char buf[64];
709 snprintf(buf, sizeof(buf), "%d", rect->id);
710 remove_proc_entry(buf, hardwall_proc_dir);
711}
712
713int proc_pid_hardwall(struct task_struct *task, char *buffer)
714{
715 struct hardwall_info *rect = task->thread.hardwall;
716 return rect ? sprintf(buffer, "%d\n", rect->id) : 0;
717}
718
719void proc_tile_hardwall_init(struct proc_dir_entry *root)
720{
721 if (!udn_disabled)
722 hardwall_proc_dir = proc_mkdir("hardwall", root);
723}
724
688 725
689/* 726/*
690 * Character device support via ioctl/close. 727 * Character device support via ioctl/close.
@@ -718,6 +755,9 @@ static long hardwall_ioctl(struct file *file, unsigned int a, unsigned long b)
718 return -EINVAL; 755 return -EINVAL;
719 return hardwall_deactivate(current); 756 return hardwall_deactivate(current);
720 757
758 case _HARDWALL_GET_ID:
759 return rect ? rect->id : -EINVAL;
760
721 default: 761 default:
722 return -EINVAL; 762 return -EINVAL;
723 } 763 }
@@ -768,6 +808,7 @@ static int hardwall_release(struct inode *inode, struct file *file)
768} 808}
769 809
770static const struct file_operations dev_hardwall_fops = { 810static const struct file_operations dev_hardwall_fops = {
811 .open = nonseekable_open,
771 .unlocked_ioctl = hardwall_ioctl, 812 .unlocked_ioctl = hardwall_ioctl,
772#ifdef CONFIG_COMPAT 813#ifdef CONFIG_COMPAT
773 .compat_ioctl = hardwall_compat_ioctl, 814 .compat_ioctl = hardwall_compat_ioctl,
diff --git a/arch/tile/kernel/head_32.S b/arch/tile/kernel/head_32.S
index 2b4f6c091701..1a39b7c1c87e 100644
--- a/arch/tile/kernel/head_32.S
+++ b/arch/tile/kernel/head_32.S
@@ -23,6 +23,7 @@
23#include <asm/asm-offsets.h> 23#include <asm/asm-offsets.h>
24#include <hv/hypervisor.h> 24#include <hv/hypervisor.h>
25#include <arch/chip.h> 25#include <arch/chip.h>
26#include <arch/spr_def.h>
26 27
27/* 28/*
28 * This module contains the entry code for kernel images. It performs the 29 * This module contains the entry code for kernel images. It performs the
@@ -76,7 +77,7 @@ ENTRY(_start)
76 } 77 }
771: 781:
78 79
79 /* Get our processor number and save it away in SAVE_1_0. */ 80 /* Get our processor number and save it away in SAVE_K_0. */
80 jal hv_inquire_topology 81 jal hv_inquire_topology
81 mulll_uu r4, r1, r2 /* r1 == y, r2 == width */ 82 mulll_uu r4, r1, r2 /* r1 == y, r2 == width */
82 add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */ 83 add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */
@@ -124,7 +125,7 @@ ENTRY(_start)
124 lw r0, r0 125 lw r0, r0
125 lw sp, r1 126 lw sp, r1
126 or r4, sp, r4 127 or r4, sp, r4
127 mtspr SYSTEM_SAVE_1_0, r4 /* save ksp0 + cpu */ 128 mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
128 addi sp, sp, -STACK_TOP_DELTA 129 addi sp, sp, -STACK_TOP_DELTA
129 { 130 {
130 move lr, zero /* stop backtraces in the called function */ 131 move lr, zero /* stop backtraces in the called function */
@@ -132,7 +133,7 @@ ENTRY(_start)
132 } 133 }
133 ENDPROC(_start) 134 ENDPROC(_start)
134 135
135.section ".bss.page_aligned","w" 136__PAGE_ALIGNED_BSS
136 .align PAGE_SIZE 137 .align PAGE_SIZE
137ENTRY(empty_zero_page) 138ENTRY(empty_zero_page)
138 .fill PAGE_SIZE,1,0 139 .fill PAGE_SIZE,1,0
@@ -144,10 +145,10 @@ ENTRY(empty_zero_page)
144 .endif 145 .endif
145 .word HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED | \ 146 .word HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED | \
146 (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE) 147 (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
147 .word (\bits1) | (HV_CPA_TO_PFN(\cpa) << HV_PTE_INDEX_PFN) 148 .word (\bits1) | (HV_CPA_TO_PFN(\cpa) << (HV_PTE_INDEX_PFN - 32))
148 .endm 149 .endm
149 150
150.section ".data.page_aligned","wa" 151__PAGE_ALIGNED_DATA
151 .align PAGE_SIZE 152 .align PAGE_SIZE
152ENTRY(swapper_pg_dir) 153ENTRY(swapper_pg_dir)
153 /* 154 /*
@@ -157,12 +158,14 @@ ENTRY(swapper_pg_dir)
157 */ 158 */
158 .set addr, 0 159 .set addr, 0
159 .rept (MEM_USER_INTRPT - PAGE_OFFSET) >> PGDIR_SHIFT 160 .rept (MEM_USER_INTRPT - PAGE_OFFSET) >> PGDIR_SHIFT
160 PTE addr + PAGE_OFFSET, addr, HV_PTE_READABLE | HV_PTE_WRITABLE 161 PTE addr + PAGE_OFFSET, addr, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
162 (1 << (HV_PTE_INDEX_WRITABLE - 32))
161 .set addr, addr + PGDIR_SIZE 163 .set addr, addr + PGDIR_SIZE
162 .endr 164 .endr
163 165
164 /* The true text VAs are mapped as VA = PA + MEM_SV_INTRPT */ 166 /* The true text VAs are mapped as VA = PA + MEM_SV_INTRPT */
165 PTE MEM_SV_INTRPT, 0, HV_PTE_READABLE | HV_PTE_EXECUTABLE 167 PTE MEM_SV_INTRPT, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
168 (1 << (HV_PTE_INDEX_EXECUTABLE - 32))
166 .org swapper_pg_dir + HV_L1_SIZE 169 .org swapper_pg_dir + HV_L1_SIZE
167 END(swapper_pg_dir) 170 END(swapper_pg_dir)
168 171
@@ -175,6 +178,7 @@ ENTRY(swapper_pg_dir)
175 __INITDATA 178 __INITDATA
176 .align CHIP_L2_LINE_SIZE() 179 .align CHIP_L2_LINE_SIZE()
177ENTRY(swapper_pgprot) 180ENTRY(swapper_pgprot)
178 PTE 0, 0, HV_PTE_READABLE | HV_PTE_WRITABLE, 1 181 PTE 0, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
182 (1 << (HV_PTE_INDEX_WRITABLE - 32)), 1
179 .align CHIP_L2_LINE_SIZE() 183 .align CHIP_L2_LINE_SIZE()
180 END(swapper_pgprot) 184 END(swapper_pgprot)
diff --git a/arch/tile/kernel/head_64.S b/arch/tile/kernel/head_64.S
new file mode 100644
index 000000000000..6bc3a932fe45
--- /dev/null
+++ b/arch/tile/kernel/head_64.S
@@ -0,0 +1,269 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * TILE startup code.
15 */
16
17#include <linux/linkage.h>
18#include <linux/init.h>
19#include <asm/page.h>
20#include <asm/pgtable.h>
21#include <asm/thread_info.h>
22#include <asm/processor.h>
23#include <asm/asm-offsets.h>
24#include <hv/hypervisor.h>
25#include <arch/chip.h>
26#include <arch/spr_def.h>
27
28/*
29 * This module contains the entry code for kernel images. It performs the
30 * minimal setup needed to call the generic C routines.
31 */
32
33 __HEAD
34ENTRY(_start)
35 /* Notify the hypervisor of what version of the API we want */
36 {
37 movei r1, TILE_CHIP
38 movei r2, TILE_CHIP_REV
39 }
40 {
41 moveli r0, _HV_VERSION
42 jal hv_init
43 }
44 /* Get a reasonable default ASID in r0 */
45 {
46 move r0, zero
47 jal hv_inquire_asid
48 }
49
50 /*
51 * Install the default page table. The relocation required to
52 * statically define the table is a bit too complex, so we have
53 * to plug in the pointer from the L0 to the L1 table by hand.
54 * We only do this on the first cpu to boot, though, since the
55 * other CPUs should see a properly-constructed page table.
56 */
57 {
58 v4int_l r2, zero, r0 /* ASID for hv_install_context */
59 moveli r4, hw1_last(swapper_pgprot - PAGE_OFFSET)
60 }
61 {
62 shl16insli r4, r4, hw0(swapper_pgprot - PAGE_OFFSET)
63 }
64 {
65 ld r1, r4 /* access_pte for hv_install_context */
66 }
67 {
68 moveli r0, hw1_last(.Lsv_data_pmd - PAGE_OFFSET)
69 moveli r6, hw1_last(temp_data_pmd - PAGE_OFFSET)
70 }
71 {
72 /* After initializing swapper_pgprot, HV_PTE_GLOBAL is set. */
73 bfextu r7, r1, HV_PTE_INDEX_GLOBAL, HV_PTE_INDEX_GLOBAL
74 inv r4
75 }
76 bnez r7, .Lno_write
77 {
78 shl16insli r0, r0, hw0(.Lsv_data_pmd - PAGE_OFFSET)
79 shl16insli r6, r6, hw0(temp_data_pmd - PAGE_OFFSET)
80 }
81 {
82 /* Cut off the low bits of the PT address. */
83 shrui r6, r6, HV_LOG2_PAGE_TABLE_ALIGN
84 /* Start with our access pte. */
85 move r5, r1
86 }
87 {
88 /* Stuff the address into the page table pointer slot of the PTE. */
89 bfins r5, r6, HV_PTE_INDEX_PTFN, \
90 HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
91 }
92 {
93 /* Store the L0 data PTE. */
94 st r0, r5
95 addli r6, r6, (temp_code_pmd - temp_data_pmd) >> \
96 HV_LOG2_PAGE_TABLE_ALIGN
97 }
98 {
99 addli r0, r0, .Lsv_code_pmd - .Lsv_data_pmd
100 bfins r5, r6, HV_PTE_INDEX_PTFN, \
101 HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
102 }
103 /* Store the L0 code PTE. */
104 st r0, r5
105
106.Lno_write:
107 moveli lr, hw2_last(1f)
108 {
109 shl16insli lr, lr, hw1(1f)
110 moveli r0, hw1_last(swapper_pg_dir - PAGE_OFFSET)
111 }
112 {
113 shl16insli lr, lr, hw0(1f)
114 shl16insli r0, r0, hw0(swapper_pg_dir - PAGE_OFFSET)
115 }
116 {
117 move r3, zero
118 j hv_install_context
119 }
1201:
121
122 /* Install the interrupt base. */
123 moveli r0, hw2_last(MEM_SV_START)
124 shl16insli r0, r0, hw1(MEM_SV_START)
125 shl16insli r0, r0, hw0(MEM_SV_START)
126 mtspr SPR_INTERRUPT_VECTOR_BASE_K, r0
127
128 /*
129 * Get our processor number and save it away in SAVE_K_0.
130 * Extract stuff from the topology structure: r4 = y, r6 = x,
131 * r5 = width. FIXME: consider whether we want to just make these
132 * 64-bit values (and if so fix smp_topology write below, too).
133 */
134 jal hv_inquire_topology
135 {
136 v4int_l r5, zero, r1 /* r5 = width */
137 shrui r4, r0, 32 /* r4 = y */
138 }
139 {
140 v4int_l r6, zero, r0 /* r6 = x */
141 mul_lu_lu r4, r4, r5
142 }
143 {
144 add r4, r4, r6 /* r4 == cpu == y*width + x */
145 }
146
147#ifdef CONFIG_SMP
148 /*
149 * Load up our per-cpu offset. When the first (master) tile
150 * boots, this value is still zero, so we will load boot_pc
151 * with start_kernel, and boot_sp with init_stack + THREAD_SIZE.
152 * The master tile initializes the per-cpu offset array, so that
153 * when subsequent (secondary) tiles boot, they will instead load
154 * from their per-cpu versions of boot_sp and boot_pc.
155 */
156 moveli r5, hw2_last(__per_cpu_offset)
157 shl16insli r5, r5, hw1(__per_cpu_offset)
158 shl16insli r5, r5, hw0(__per_cpu_offset)
159 shl3add r5, r4, r5
160 ld r5, r5
161 bnez r5, 1f
162
163 /*
164 * Save the width and height to the smp_topology variable
165 * for later use.
166 */
167 moveli r0, hw2_last(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
168 shl16insli r0, r0, hw1(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
169 shl16insli r0, r0, hw0(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
170 st r0, r1
1711:
172#else
173 move r5, zero
174#endif
175
176 /* Load and go with the correct pc and sp. */
177 {
178 moveli r1, hw2_last(boot_sp)
179 moveli r0, hw2_last(boot_pc)
180 }
181 {
182 shl16insli r1, r1, hw1(boot_sp)
183 shl16insli r0, r0, hw1(boot_pc)
184 }
185 {
186 shl16insli r1, r1, hw0(boot_sp)
187 shl16insli r0, r0, hw0(boot_pc)
188 }
189 {
190 add r1, r1, r5
191 add r0, r0, r5
192 }
193 ld r0, r0
194 ld sp, r1
195 or r4, sp, r4
196 mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
197 addi sp, sp, -STACK_TOP_DELTA
198 {
199 move lr, zero /* stop backtraces in the called function */
200 jr r0
201 }
202 ENDPROC(_start)
203
204__PAGE_ALIGNED_BSS
205 .align PAGE_SIZE
206ENTRY(empty_zero_page)
207 .fill PAGE_SIZE,1,0
208 END(empty_zero_page)
209
210 .macro PTE cpa, bits1
211 .quad HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED |\
212 HV_PTE_GLOBAL | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE) |\
213 (\bits1) | (HV_CPA_TO_PFN(\cpa) << HV_PTE_INDEX_PFN)
214 .endm
215
216__PAGE_ALIGNED_DATA
217 .align PAGE_SIZE
218ENTRY(swapper_pg_dir)
219 .org swapper_pg_dir + HV_L0_INDEX(PAGE_OFFSET) * HV_PTE_SIZE
220.Lsv_data_pmd:
221 .quad 0 /* PTE temp_data_pmd - PAGE_OFFSET, 0 */
222 .org swapper_pg_dir + HV_L0_INDEX(MEM_SV_START) * HV_PTE_SIZE
223.Lsv_code_pmd:
224 .quad 0 /* PTE temp_code_pmd - PAGE_OFFSET, 0 */
225 .org swapper_pg_dir + HV_L0_SIZE
226 END(swapper_pg_dir)
227
228 .align HV_PAGE_TABLE_ALIGN
229ENTRY(temp_data_pmd)
230 /*
231 * We fill the PAGE_OFFSET pmd with huge pages with
232 * VA = PA + PAGE_OFFSET. We remap things with more precise access
233 * permissions later.
234 */
235 .set addr, 0
236 .rept HV_L1_ENTRIES
237 PTE addr, HV_PTE_READABLE | HV_PTE_WRITABLE
238 .set addr, addr + HV_PAGE_SIZE_LARGE
239 .endr
240 .org temp_data_pmd + HV_L1_SIZE
241 END(temp_data_pmd)
242
243 .align HV_PAGE_TABLE_ALIGN
244ENTRY(temp_code_pmd)
245 /*
246 * We fill the MEM_SV_START pmd with huge pages with
247 * VA = PA + PAGE_OFFSET. We remap things with more precise access
248 * permissions later.
249 */
250 .set addr, 0
251 .rept HV_L1_ENTRIES
252 PTE addr, HV_PTE_READABLE | HV_PTE_EXECUTABLE
253 .set addr, addr + HV_PAGE_SIZE_LARGE
254 .endr
255 .org temp_code_pmd + HV_L1_SIZE
256 END(temp_code_pmd)
257
258 /*
259 * Isolate swapper_pgprot to its own cache line, since each cpu
260 * starting up will read it using VA-is-PA and local homing.
261 * This would otherwise likely conflict with other data on the cache
262 * line, once we have set its permanent home in the page tables.
263 */
264 __INITDATA
265 .align CHIP_L2_LINE_SIZE()
266ENTRY(swapper_pgprot)
267 .quad HV_PTE_PRESENT | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
268 .align CHIP_L2_LINE_SIZE()
269 END(swapper_pgprot)
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index 8f58bdff20d7..72ade79b621b 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -32,10 +32,6 @@
32# error "No support for kernel preemption currently" 32# error "No support for kernel preemption currently"
33#endif 33#endif
34 34
35#if INT_INTCTRL_1 < 32 || INT_INTCTRL_1 >= 48
36# error INT_INTCTRL_1 coded to set high interrupt mask
37#endif
38
39#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg) 35#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
40 36
41#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR) 37#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
@@ -132,8 +128,8 @@ intvec_\vecname:
132 128
133 /* Temporarily save a register so we have somewhere to work. */ 129 /* Temporarily save a register so we have somewhere to work. */
134 130
135 mtspr SYSTEM_SAVE_1_1, r0 131 mtspr SPR_SYSTEM_SAVE_K_1, r0
136 mfspr r0, EX_CONTEXT_1_1 132 mfspr r0, SPR_EX_CONTEXT_K_1
137 133
138 /* The cmpxchg code clears sp to force us to reset it here on fault. */ 134 /* The cmpxchg code clears sp to force us to reset it here on fault. */
139 { 135 {
@@ -167,18 +163,18 @@ intvec_\vecname:
167 * The page_fault handler may be downcalled directly by the 163 * The page_fault handler may be downcalled directly by the
168 * hypervisor even when Linux is running and has ICS set. 164 * hypervisor even when Linux is running and has ICS set.
169 * 165 *
170 * In this case the contents of EX_CONTEXT_1_1 reflect the 166 * In this case the contents of EX_CONTEXT_K_1 reflect the
171 * previous fault and can't be relied on to choose whether or 167 * previous fault and can't be relied on to choose whether or
172 * not to reinitialize the stack pointer. So we add a test 168 * not to reinitialize the stack pointer. So we add a test
173 * to see whether SYSTEM_SAVE_1_2 has the high bit set, 169 * to see whether SYSTEM_SAVE_K_2 has the high bit set,
174 * and if so we don't reinitialize sp, since we must be coming 170 * and if so we don't reinitialize sp, since we must be coming
175 * from Linux. (In fact the precise case is !(val & ~1), 171 * from Linux. (In fact the precise case is !(val & ~1),
176 * but any Linux PC has to have the high bit set.) 172 * but any Linux PC has to have the high bit set.)
177 * 173 *
178 * Note that the hypervisor *always* sets SYSTEM_SAVE_1_2 for 174 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
179 * any path that turns into a downcall to one of our TLB handlers. 175 * any path that turns into a downcall to one of our TLB handlers.
180 */ 176 */
181 mfspr r0, SYSTEM_SAVE_1_2 177 mfspr r0, SPR_SYSTEM_SAVE_K_2
182 { 178 {
183 blz r0, 0f /* high bit in S_S_1_2 is for a PC to use */ 179 blz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
184 move r0, sp 180 move r0, sp
@@ -187,12 +183,12 @@ intvec_\vecname:
187 183
1882: 1842:
189 /* 185 /*
190 * SYSTEM_SAVE_1_0 holds the cpu number in the low bits, and 186 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
191 * the current stack top in the higher bits. So we recover 187 * the current stack top in the higher bits. So we recover
192 * our stack top by just masking off the low bits, then 188 * our stack top by just masking off the low bits, then
193 * point sp at the top aligned address on the actual stack page. 189 * point sp at the top aligned address on the actual stack page.
194 */ 190 */
195 mfspr r0, SYSTEM_SAVE_1_0 191 mfspr r0, SPR_SYSTEM_SAVE_K_0
196 mm r0, r0, zero, LOG2_THREAD_SIZE, 31 192 mm r0, r0, zero, LOG2_THREAD_SIZE, 31
197 193
1980: 1940:
@@ -254,7 +250,7 @@ intvec_\vecname:
254 sw sp, r3 250 sw sp, r3
255 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3) 251 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
256 } 252 }
257 mfspr r0, EX_CONTEXT_1_0 253 mfspr r0, SPR_EX_CONTEXT_K_0
258 .ifc \processing,handle_syscall 254 .ifc \processing,handle_syscall
259 /* 255 /*
260 * Bump the saved PC by one bundle so that when we return, we won't 256 * Bump the saved PC by one bundle so that when we return, we won't
@@ -267,7 +263,7 @@ intvec_\vecname:
267 sw sp, r0 263 sw sp, r0
268 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC 264 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
269 } 265 }
270 mfspr r0, EX_CONTEXT_1_1 266 mfspr r0, SPR_EX_CONTEXT_K_1
271 { 267 {
272 sw sp, r0 268 sw sp, r0
273 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1 269 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
@@ -289,7 +285,7 @@ intvec_\vecname:
289 .endif 285 .endif
290 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM 286 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
291 } 287 }
292 mfspr r0, SYSTEM_SAVE_1_1 /* Original r0 */ 288 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
293 { 289 {
294 sw sp, r0 290 sw sp, r0
295 addi sp, sp, -PTREGS_OFFSET_REG(0) - 4 291 addi sp, sp, -PTREGS_OFFSET_REG(0) - 4
@@ -309,12 +305,12 @@ intvec_\vecname:
309 * See discussion below at "finish_interrupt_save". 305 * See discussion below at "finish_interrupt_save".
310 */ 306 */
311 .ifc \c_routine, do_page_fault 307 .ifc \c_routine, do_page_fault
312 mfspr r2, SYSTEM_SAVE_1_3 /* address of page fault */ 308 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
313 mfspr r3, SYSTEM_SAVE_1_2 /* info about page fault */ 309 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
314 .else 310 .else
315 .ifc \vecnum, INT_DOUBLE_FAULT 311 .ifc \vecnum, INT_DOUBLE_FAULT
316 { 312 {
317 mfspr r2, SYSTEM_SAVE_1_2 /* double fault info from HV */ 313 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
318 movei r3, 0 314 movei r3, 0
319 } 315 }
320 .else 316 .else
@@ -467,7 +463,7 @@ intvec_\vecname:
467 /* Load tp with our per-cpu offset. */ 463 /* Load tp with our per-cpu offset. */
468#ifdef CONFIG_SMP 464#ifdef CONFIG_SMP
469 { 465 {
470 mfspr r20, SYSTEM_SAVE_1_0 466 mfspr r20, SPR_SYSTEM_SAVE_K_0
471 moveli r21, lo16(__per_cpu_offset) 467 moveli r21, lo16(__per_cpu_offset)
472 } 468 }
473 { 469 {
@@ -487,7 +483,7 @@ intvec_\vecname:
487 * We load flags in r32 here so we can jump to .Lrestore_regs 483 * We load flags in r32 here so we can jump to .Lrestore_regs
488 * directly after do_page_fault_ics() if necessary. 484 * directly after do_page_fault_ics() if necessary.
489 */ 485 */
490 mfspr r32, EX_CONTEXT_1_1 486 mfspr r32, SPR_EX_CONTEXT_K_1
491 { 487 {
492 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 488 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
493 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS) 489 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
@@ -855,14 +851,27 @@ STD_ENTRY(interrupt_return)
855 /* Check to see if there is any work to do before returning to user. */ 851 /* Check to see if there is any work to do before returning to user. */
856 { 852 {
857 addi r29, r32, THREAD_INFO_FLAGS_OFFSET 853 addi r29, r32, THREAD_INFO_FLAGS_OFFSET
858 moveli r28, lo16(_TIF_ALLWORK_MASK) 854 moveli r1, lo16(_TIF_ALLWORK_MASK)
859 } 855 }
860 { 856 {
861 lw r29, r29 857 lw r29, r29
862 auli r28, r28, ha16(_TIF_ALLWORK_MASK) 858 auli r1, r1, ha16(_TIF_ALLWORK_MASK)
863 } 859 }
864 and r28, r29, r28 860 and r1, r29, r1
865 bnz r28, .Lwork_pending 861 bzt r1, .Lrestore_all
862
863 /*
864 * Make sure we have all the registers saved for signal
865 * handling or single-step. Call out to C code to figure out
866 * exactly what we need to do for each flag bit, then if
867 * necessary, reload the flags and recheck.
868 */
869 push_extra_callee_saves r0
870 {
871 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
872 jal do_work_pending
873 }
874 bnz r0, .Lresume_userspace
866 875
867 /* 876 /*
868 * In the NMI case we 877 * In the NMI case we
@@ -957,11 +966,11 @@ STD_ENTRY(interrupt_return)
957 pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC 966 pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
958 pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1 967 pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1
959 { 968 {
960 mtspr EX_CONTEXT_1_0, r21 969 mtspr SPR_EX_CONTEXT_K_0, r21
961 move r5, zero 970 move r5, zero
962 } 971 }
963 { 972 {
964 mtspr EX_CONTEXT_1_1, lr 973 mtspr SPR_EX_CONTEXT_K_1, lr
965 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ 974 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
966 } 975 }
967 976
@@ -1020,7 +1029,7 @@ STD_ENTRY(interrupt_return)
1020 1029
1021 /* Set r1 to errno if we are returning an error, otherwise zero. */ 1030 /* Set r1 to errno if we are returning an error, otherwise zero. */
1022 { 1031 {
1023 moveli r29, 1024 1032 moveli r29, 4096
1024 sub r1, zero, r0 1033 sub r1, zero, r0
1025 } 1034 }
1026 slt_u r29, r1, r29 1035 slt_u r29, r1, r29
@@ -1103,142 +1112,9 @@ STD_ENTRY(interrupt_return)
1103 pop_reg r50 1112 pop_reg r50
1104 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51) 1113 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
1105 j .Lcontinue_restore_regs 1114 j .Lcontinue_restore_regs
1106
1107.Lwork_pending:
1108 /* Mask the reschedule flag */
1109 andi r28, r29, _TIF_NEED_RESCHED
1110
1111 {
1112 /*
1113 * If the NEED_RESCHED flag is called, we call schedule(), which
1114 * may drop this context right here and go do something else.
1115 * On return, jump back to .Lresume_userspace and recheck.
1116 */
1117 bz r28, .Lasync_tlb
1118
1119 /* Mask the async-tlb flag */
1120 andi r28, r29, _TIF_ASYNC_TLB
1121 }
1122
1123 jal schedule
1124 FEEDBACK_REENTER(interrupt_return)
1125
1126 /* Reload the flags and check again */
1127 j .Lresume_userspace
1128
1129.Lasync_tlb:
1130 {
1131 bz r28, .Lneed_sigpending
1132
1133 /* Mask the sigpending flag */
1134 andi r28, r29, _TIF_SIGPENDING
1135 }
1136
1137 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1138 jal do_async_page_fault
1139 FEEDBACK_REENTER(interrupt_return)
1140
1141 /*
1142 * Go restart the "resume userspace" process. We may have
1143 * fired a signal, and we need to disable interrupts again.
1144 */
1145 j .Lresume_userspace
1146
1147.Lneed_sigpending:
1148 /*
1149 * At this point we are either doing signal handling or single-step,
1150 * so either way make sure we have all the registers saved.
1151 */
1152 push_extra_callee_saves r0
1153
1154 {
1155 /* If no signal pending, skip to singlestep check */
1156 bz r28, .Lneed_singlestep
1157
1158 /* Mask the singlestep flag */
1159 andi r28, r29, _TIF_SINGLESTEP
1160 }
1161
1162 jal do_signal
1163 FEEDBACK_REENTER(interrupt_return)
1164
1165 /* Reload the flags and check again */
1166 j .Lresume_userspace
1167
1168.Lneed_singlestep:
1169 {
1170 /* Get a pointer to the EX1 field */
1171 PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
1172
1173 /* If we get here, our bit must be set. */
1174 bz r28, .Lwork_confusion
1175 }
1176 /* If we are in priv mode, don't single step */
1177 lw r28, r29
1178 andi r28, r28, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
1179 bnz r28, .Lrestore_all
1180
1181 /* Allow interrupts within the single step code */
1182 TRACE_IRQS_ON /* Note: clobbers registers r0-r29 */
1183 IRQ_ENABLE(r20, r21)
1184
1185 /* try to single-step the current instruction */
1186 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1187 jal single_step_once
1188 FEEDBACK_REENTER(interrupt_return)
1189
1190 /* Re-disable interrupts. TRACE_IRQS_OFF in .Lrestore_all. */
1191 IRQ_DISABLE(r20,r21)
1192
1193 j .Lrestore_all
1194
1195.Lwork_confusion:
1196 move r0, r28
1197 panic "thread_info allwork flags unhandled on userspace resume: %#x"
1198
1199 STD_ENDPROC(interrupt_return) 1115 STD_ENDPROC(interrupt_return)
1200 1116
1201 /* 1117 /*
1202 * This interrupt variant clears the INT_INTCTRL_1 interrupt mask bit
1203 * before returning, so we can properly get more downcalls.
1204 */
1205 .pushsection .text.handle_interrupt_downcall,"ax"
1206handle_interrupt_downcall:
1207 finish_interrupt_save handle_interrupt_downcall
1208 check_single_stepping normal, .Ldispatch_downcall
1209.Ldispatch_downcall:
1210
1211 /* Clear INTCTRL_1 from the set of interrupts we ever enable. */
1212 GET_INTERRUPTS_ENABLED_MASK_PTR(r30)
1213 {
1214 addi r30, r30, 4
1215 movei r31, INT_MASK(INT_INTCTRL_1)
1216 }
1217 {
1218 lw r20, r30
1219 nor r21, r31, zero
1220 }
1221 and r20, r20, r21
1222 sw r30, r20
1223
1224 {
1225 jalr r0
1226 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
1227 }
1228 FEEDBACK_REENTER(handle_interrupt_downcall)
1229
1230 /* Allow INTCTRL_1 to be enabled next time we enable interrupts. */
1231 lw r20, r30
1232 or r20, r20, r31
1233 sw r30, r20
1234
1235 {
1236 movei r30, 0 /* not an NMI */
1237 j interrupt_return
1238 }
1239 STD_ENDPROC(handle_interrupt_downcall)
1240
1241 /*
1242 * Some interrupts don't check for single stepping 1118 * Some interrupts don't check for single stepping
1243 */ 1119 */
1244 .pushsection .text.handle_interrupt_no_single_step,"ax" 1120 .pushsection .text.handle_interrupt_no_single_step,"ax"
@@ -1342,8 +1218,8 @@ handle_syscall:
1342 lw r20, r20 1218 lw r20, r20
1343 1219
1344 /* Jump to syscall handler. */ 1220 /* Jump to syscall handler. */
1345 jalr r20; .Lhandle_syscall_link: 1221 jalr r20
1346 FEEDBACK_REENTER(handle_syscall) 1222.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
1347 1223
1348 /* 1224 /*
1349 * Write our r0 onto the stack so it gets restored instead 1225 * Write our r0 onto the stack so it gets restored instead
@@ -1352,6 +1228,9 @@ handle_syscall:
1352 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) 1228 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1353 sw r29, r0 1229 sw r29, r0
1354 1230
1231.Lsyscall_sigreturn_skip:
1232 FEEDBACK_REENTER(handle_syscall)
1233
1355 /* Do syscall trace again, if requested. */ 1234 /* Do syscall trace again, if requested. */
1356 lw r30, r31 1235 lw r30, r31
1357 andi r30, r30, _TIF_SYSCALL_TRACE 1236 andi r30, r30, _TIF_SYSCALL_TRACE
@@ -1472,7 +1351,12 @@ handle_ill:
1472 lw r26, r24 1351 lw r26, r24
1473 sw r28, r26 1352 sw r28, r26
1474 1353
1475 /* Clear TIF_SINGLESTEP */ 1354 /*
1355 * Clear TIF_SINGLESTEP to prevent recursion if we execute an ill.
1356 * The normal non-arch flow redundantly clears TIF_SINGLESTEP, but we
1357 * need to clear it here and can't really impose on all other arches.
1358 * So what's another write between friends?
1359 */
1476 GET_THREAD_INFO(r0) 1360 GET_THREAD_INFO(r0)
1477 1361
1478 addi r1, r0, THREAD_INFO_FLAGS_OFFSET 1362 addi r1, r0, THREAD_INFO_FLAGS_OFFSET
@@ -1509,7 +1393,7 @@ handle_ill:
1509/* Various stub interrupt handlers and syscall handlers */ 1393/* Various stub interrupt handlers and syscall handlers */
1510 1394
1511STD_ENTRY_LOCAL(_kernel_double_fault) 1395STD_ENTRY_LOCAL(_kernel_double_fault)
1512 mfspr r1, EX_CONTEXT_1_0 1396 mfspr r1, SPR_EX_CONTEXT_K_0
1513 move r2, lr 1397 move r2, lr
1514 move r3, sp 1398 move r3, sp
1515 move r4, r52 1399 move r4, r52
@@ -1518,34 +1402,44 @@ STD_ENTRY_LOCAL(_kernel_double_fault)
1518 STD_ENDPROC(_kernel_double_fault) 1402 STD_ENDPROC(_kernel_double_fault)
1519 1403
1520STD_ENTRY_LOCAL(bad_intr) 1404STD_ENTRY_LOCAL(bad_intr)
1521 mfspr r2, EX_CONTEXT_1_0 1405 mfspr r2, SPR_EX_CONTEXT_K_0
1522 panic "Unhandled interrupt %#x: PC %#lx" 1406 panic "Unhandled interrupt %#x: PC %#lx"
1523 STD_ENDPROC(bad_intr) 1407 STD_ENDPROC(bad_intr)
1524 1408
1525/* Put address of pt_regs in reg and jump. */ 1409/* Put address of pt_regs in reg and jump. */
1526#define PTREGS_SYSCALL(x, reg) \ 1410#define PTREGS_SYSCALL(x, reg) \
1527 STD_ENTRY(x); \ 1411 STD_ENTRY(_##x); \
1528 { \ 1412 { \
1529 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \ 1413 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1530 j _##x \ 1414 j x \
1531 }; \ 1415 }; \
1532 STD_ENDPROC(x) 1416 STD_ENDPROC(_##x)
1417
1418/*
1419 * Special-case sigreturn to not write r0 to the stack on return.
1420 * This is technically more efficient, but it also avoids difficulties
1421 * in the 64-bit OS when handling 32-bit compat code, since we must not
1422 * sign-extend r0 for the sigreturn return-value case.
1423 */
1424#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
1425 STD_ENTRY(_##x); \
1426 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
1427 { \
1428 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1429 j x \
1430 }; \
1431 STD_ENDPROC(_##x)
1533 1432
1534PTREGS_SYSCALL(sys_execve, r3) 1433PTREGS_SYSCALL(sys_execve, r3)
1535PTREGS_SYSCALL(sys_sigaltstack, r2) 1434PTREGS_SYSCALL(sys_sigaltstack, r2)
1536PTREGS_SYSCALL(sys_rt_sigreturn, r0) 1435PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
1537 1436PTREGS_SYSCALL(sys_cmpxchg_badaddr, r1)
1538/* Save additional callee-saves to pt_regs, put address in reg and jump. */
1539#define PTREGS_SYSCALL_ALL_REGS(x, reg) \
1540 STD_ENTRY(x); \
1541 push_extra_callee_saves reg; \
1542 j _##x; \
1543 STD_ENDPROC(x)
1544 1437
1545PTREGS_SYSCALL_ALL_REGS(sys_fork, r0) 1438/* Save additional callee-saves to pt_regs, put address in r4 and jump. */
1546PTREGS_SYSCALL_ALL_REGS(sys_vfork, r0) 1439STD_ENTRY(_sys_clone)
1547PTREGS_SYSCALL_ALL_REGS(sys_clone, r4) 1440 push_extra_callee_saves r4
1548PTREGS_SYSCALL_ALL_REGS(sys_cmpxchg_badaddr, r1) 1441 j sys_clone
1442 STD_ENDPROC(_sys_clone)
1549 1443
1550/* 1444/*
1551 * This entrypoint is taken for the cmpxchg and atomic_update fast 1445 * This entrypoint is taken for the cmpxchg and atomic_update fast
@@ -1558,12 +1452,14 @@ PTREGS_SYSCALL_ALL_REGS(sys_cmpxchg_badaddr, r1)
1558 * to be available to it on entry. It does not modify any callee-save 1452 * to be available to it on entry. It does not modify any callee-save
1559 * registers (including "lr"). It does not check what PL it is being 1453 * registers (including "lr"). It does not check what PL it is being
1560 * called at, so you'd better not call it other than at PL0. 1454 * called at, so you'd better not call it other than at PL0.
1455 * The <atomic.h> wrapper assumes it only clobbers r20-r29, so if
1456 * it ever is necessary to use more registers, be aware.
1561 * 1457 *
1562 * It does not use the stack, but since it might be re-interrupted by 1458 * It does not use the stack, but since it might be re-interrupted by
1563 * a page fault which would assume the stack was valid, it does 1459 * a page fault which would assume the stack was valid, it does
1564 * save/restore the stack pointer and zero it out to make sure it gets reset. 1460 * save/restore the stack pointer and zero it out to make sure it gets reset.
1565 * Since we always keep interrupts disabled, the hypervisor won't 1461 * Since we always keep interrupts disabled, the hypervisor won't
1566 * clobber our EX_CONTEXT_1_x registers, so we don't save/restore them 1462 * clobber our EX_CONTEXT_K_x registers, so we don't save/restore them
1567 * (other than to advance the PC on return). 1463 * (other than to advance the PC on return).
1568 * 1464 *
1569 * We have to manually validate the user vs kernel address range 1465 * We have to manually validate the user vs kernel address range
@@ -1574,13 +1470,19 @@ PTREGS_SYSCALL_ALL_REGS(sys_cmpxchg_badaddr, r1)
1574 * We place it in the __HEAD section to ensure it is relatively 1470 * We place it in the __HEAD section to ensure it is relatively
1575 * near to the intvec_SWINT_1 code (reachable by a conditional branch). 1471 * near to the intvec_SWINT_1 code (reachable by a conditional branch).
1576 * 1472 *
1577 * Must match register usage in do_page_fault(). 1473 * Our use of ATOMIC_LOCK_REG here must match do_page_fault_ics().
1474 *
1475 * As we do in lib/atomic_asm_32.S, we bypass a store if the value we
1476 * would store is the same as the value we just loaded.
1578 */ 1477 */
1579 __HEAD 1478 __HEAD
1580 .align 64 1479 .align 64
1581 /* Align much later jump on the start of a cache line. */ 1480 /* Align much later jump on the start of a cache line. */
1582#if !ATOMIC_LOCKS_FOUND_VIA_TABLE() 1481#if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
1583 nop; nop 1482 nop
1483#if PAGE_SIZE >= 0x10000
1484 nop
1485#endif
1584#endif 1486#endif
1585ENTRY(sys_cmpxchg) 1487ENTRY(sys_cmpxchg)
1586 1488
@@ -1608,9 +1510,13 @@ ENTRY(sys_cmpxchg)
1608 * about aliasing among multiple mappings of the same physical page, 1510 * about aliasing among multiple mappings of the same physical page,
1609 * and we ignore the low 3 bits so we have one lock that covers 1511 * and we ignore the low 3 bits so we have one lock that covers
1610 * both a cmpxchg64() and a cmpxchg() on either its low or high word. 1512 * both a cmpxchg64() and a cmpxchg() on either its low or high word.
1611 * NOTE: this code must match __atomic_hashed_lock() in lib/atomic.c. 1513 * NOTE: this must match __atomic_hashed_lock() in lib/atomic_32.c.
1612 */ 1514 */
1613 1515
1516#if (PAGE_OFFSET & 0xffff) != 0
1517# error Code here assumes PAGE_OFFSET can be loaded with just hi16()
1518#endif
1519
1614#if ATOMIC_LOCKS_FOUND_VIA_TABLE() 1520#if ATOMIC_LOCKS_FOUND_VIA_TABLE()
1615 { 1521 {
1616 /* Check for unaligned input. */ 1522 /* Check for unaligned input. */
@@ -1628,17 +1534,7 @@ ENTRY(sys_cmpxchg)
1628 { 1534 {
1629 shri r20, r25, 32 - ATOMIC_HASH_L1_SHIFT 1535 shri r20, r25, 32 - ATOMIC_HASH_L1_SHIFT
1630 slt_u r23, r0, r23 1536 slt_u r23, r0, r23
1631 1537 lw r26, r0 /* see comment in the "#else" for the "lw r26". */
1632 /*
1633 * Ensure that the TLB is loaded before we take out the lock.
1634 * On TILEPro, this will start fetching the value all the way
1635 * into our L1 as well (and if it gets modified before we
1636 * grab the lock, it will be invalidated from our cache
1637 * before we reload it). On tile64, we'll start fetching it
1638 * into our L1 if we're the home, and if we're not, we'll
1639 * still at least start fetching it into the home's L2.
1640 */
1641 lw r26, r0
1642 } 1538 }
1643 { 1539 {
1644 s2a r21, r20, r21 1540 s2a r21, r20, r21
@@ -1654,18 +1550,9 @@ ENTRY(sys_cmpxchg)
1654 bbs r23, .Lcmpxchg64 1550 bbs r23, .Lcmpxchg64
1655 andi r23, r0, 7 /* Precompute alignment for cmpxchg64. */ 1551 andi r23, r0, 7 /* Precompute alignment for cmpxchg64. */
1656 } 1552 }
1657
1658 { 1553 {
1659 /*
1660 * We very carefully align the code that actually runs with
1661 * the lock held (nine bundles) so that we know it is all in
1662 * the icache when we start. This instruction (the jump) is
1663 * at the start of the first cache line, address zero mod 64;
1664 * we jump to somewhere in the second cache line to issue the
1665 * tns, then jump back to finish up.
1666 */
1667 s2a ATOMIC_LOCK_REG_NAME, r25, r21 1554 s2a ATOMIC_LOCK_REG_NAME, r25, r21
1668 j .Lcmpxchg32_tns 1555 j .Lcmpxchg32_tns /* see comment in the #else for the jump. */
1669 } 1556 }
1670 1557
1671#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 1558#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
@@ -1703,11 +1590,14 @@ ENTRY(sys_cmpxchg)
1703 lw r26, r0 1590 lw r26, r0
1704 } 1591 }
1705 { 1592 {
1706 /* atomic_locks is page aligned so this suffices to get its addr. */ 1593 auli r21, zero, ha16(atomic_locks)
1707 auli r21, zero, hi16(atomic_locks)
1708 1594
1709 bbns r23, .Lcmpxchg_badaddr 1595 bbns r23, .Lcmpxchg_badaddr
1710 } 1596 }
1597#if PAGE_SIZE < 0x10000
1598 /* atomic_locks is page-aligned so for big pages we don't need this. */
1599 addli r21, r21, lo16(atomic_locks)
1600#endif
1711 { 1601 {
1712 /* 1602 /*
1713 * Insert the hash bits into the page-aligned pointer. 1603 * Insert the hash bits into the page-aligned pointer.
@@ -1727,24 +1617,25 @@ ENTRY(sys_cmpxchg)
1727 { 1617 {
1728 /* 1618 /*
1729 * We very carefully align the code that actually runs with 1619 * We very carefully align the code that actually runs with
1730 * the lock held (nine bundles) so that we know it is all in 1620 * the lock held (twelve bundles) so that we know it is all in
1731 * the icache when we start. This instruction (the jump) is 1621 * the icache when we start. This instruction (the jump) is
1732 * at the start of the first cache line, address zero mod 64; 1622 * at the start of the first cache line, address zero mod 64;
1733 * we jump to somewhere in the second cache line to issue the 1623 * we jump to the very end of the second cache line to get that
1734 * tns, then jump back to finish up. 1624 * line loaded in the icache, then fall through to issue the tns
1625 * in the third cache line, at which point it's all cached.
1626 * Note that is for performance, not correctness.
1735 */ 1627 */
1736 j .Lcmpxchg32_tns 1628 j .Lcmpxchg32_tns
1737 } 1629 }
1738 1630
1739#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 1631#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
1740 1632
1741 ENTRY(__sys_cmpxchg_grab_lock) 1633/* Symbol for do_page_fault_ics() to use to compare against the PC. */
1634.global __sys_cmpxchg_grab_lock
1635__sys_cmpxchg_grab_lock:
1742 1636
1743 /* 1637 /*
1744 * Perform the actual cmpxchg or atomic_update. 1638 * Perform the actual cmpxchg or atomic_update.
1745 * Note that __futex_mark_unlocked() in uClibc relies on
1746 * atomic_update() to always perform an "mf", so don't make
1747 * it optional or conditional without modifying that code.
1748 */ 1639 */
1749.Ldo_cmpxchg32: 1640.Ldo_cmpxchg32:
1750 { 1641 {
@@ -1762,18 +1653,20 @@ ENTRY(sys_cmpxchg)
1762 } 1653 }
1763 { 1654 {
1764 mvnz r24, r23, r25 /* Use atomic_update value if appropriate. */ 1655 mvnz r24, r23, r25 /* Use atomic_update value if appropriate. */
1765 bbns r22, .Lcmpxchg32_mismatch 1656 bbns r22, .Lcmpxchg32_nostore
1766 } 1657 }
1658 seq r22, r24, r21 /* Are we storing the value we loaded? */
1659 bbs r22, .Lcmpxchg32_nostore
1767 sw r0, r24 1660 sw r0, r24
1768 1661
1662 /* The following instruction is the start of the second cache line. */
1769 /* Do slow mtspr here so the following "mf" waits less. */ 1663 /* Do slow mtspr here so the following "mf" waits less. */
1770 { 1664 {
1771 move sp, r27 1665 move sp, r27
1772 mtspr EX_CONTEXT_1_0, r28 1666 mtspr SPR_EX_CONTEXT_K_0, r28
1773 } 1667 }
1774 mf 1668 mf
1775 1669
1776 /* The following instruction is the start of the second cache line. */
1777 { 1670 {
1778 move r0, r21 1671 move r0, r21
1779 sw ATOMIC_LOCK_REG_NAME, zero 1672 sw ATOMIC_LOCK_REG_NAME, zero
@@ -1781,14 +1674,14 @@ ENTRY(sys_cmpxchg)
1781 iret 1674 iret
1782 1675
1783 /* Duplicated code here in the case where we don't overlap "mf" */ 1676 /* Duplicated code here in the case where we don't overlap "mf" */
1784.Lcmpxchg32_mismatch: 1677.Lcmpxchg32_nostore:
1785 { 1678 {
1786 move r0, r21 1679 move r0, r21
1787 sw ATOMIC_LOCK_REG_NAME, zero 1680 sw ATOMIC_LOCK_REG_NAME, zero
1788 } 1681 }
1789 { 1682 {
1790 move sp, r27 1683 move sp, r27
1791 mtspr EX_CONTEXT_1_0, r28 1684 mtspr SPR_EX_CONTEXT_K_0, r28
1792 } 1685 }
1793 iret 1686 iret
1794 1687
@@ -1797,8 +1690,6 @@ ENTRY(sys_cmpxchg)
1797 * and for 64-bit cmpxchg. We provide it as a macro and put 1690 * and for 64-bit cmpxchg. We provide it as a macro and put
1798 * it into both versions. We can't share the code literally 1691 * it into both versions. We can't share the code literally
1799 * since it depends on having the right branch-back address. 1692 * since it depends on having the right branch-back address.
1800 * Note that the first few instructions should share the cache
1801 * line with the second half of the actual locked code.
1802 */ 1693 */
1803 .macro cmpxchg_lock, bitwidth 1694 .macro cmpxchg_lock, bitwidth
1804 1695
@@ -1816,7 +1707,7 @@ ENTRY(sys_cmpxchg)
1816#endif 1707#endif
1817 1708
1818 /* Issue the slow SPR here while the tns result is in flight. */ 1709 /* Issue the slow SPR here while the tns result is in flight. */
1819 mfspr r28, EX_CONTEXT_1_0 1710 mfspr r28, SPR_EX_CONTEXT_K_0
1820 1711
1821 { 1712 {
1822 addi r28, r28, 8 /* return to the instruction after the swint1 */ 1713 addi r28, r28, 8 /* return to the instruction after the swint1 */
@@ -1824,7 +1715,7 @@ ENTRY(sys_cmpxchg)
1824 } 1715 }
1825 /* 1716 /*
1826 * The preceding instruction is the last thing that must be 1717 * The preceding instruction is the last thing that must be
1827 * on the second cache line. 1718 * hot in the icache before we do the "tns" above.
1828 */ 1719 */
1829 1720
1830#ifdef CONFIG_SMP 1721#ifdef CONFIG_SMP
@@ -1855,6 +1746,12 @@ ENTRY(sys_cmpxchg)
1855 .endm 1746 .endm
1856 1747
1857.Lcmpxchg32_tns: 1748.Lcmpxchg32_tns:
1749 /*
1750 * This is the last instruction on the second cache line.
1751 * The nop here loads the second line, then we fall through
1752 * to the tns to load the third line before we take the lock.
1753 */
1754 nop
1858 cmpxchg_lock 32 1755 cmpxchg_lock 32
1859 1756
1860 /* 1757 /*
@@ -1904,7 +1801,7 @@ ENTRY(sys_cmpxchg)
1904.Lcmpxchg64_mismatch: 1801.Lcmpxchg64_mismatch:
1905 { 1802 {
1906 move sp, r27 1803 move sp, r27
1907 mtspr EX_CONTEXT_1_0, r28 1804 mtspr SPR_EX_CONTEXT_K_0, r28
1908 } 1805 }
1909 mf 1806 mf
1910 { 1807 {
@@ -1985,21 +1882,26 @@ int_unalign:
1985 int_hand INT_PERF_COUNT, PERF_COUNT, \ 1882 int_hand INT_PERF_COUNT, PERF_COUNT, \
1986 op_handle_perf_interrupt, handle_nmi 1883 op_handle_perf_interrupt, handle_nmi
1987 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr 1884 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
1885#if CONFIG_KERNEL_PL == 2
1886 dc_dispatch INT_INTCTRL_2, INTCTRL_2
1887 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
1888#else
1988 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr 1889 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
1989 dc_dispatch INT_INTCTRL_1, INTCTRL_1 1890 dc_dispatch INT_INTCTRL_1, INTCTRL_1
1891#endif
1990 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr 1892 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
1991 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \ 1893 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
1992 hv_message_intr, handle_interrupt_downcall 1894 hv_message_intr
1993 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, \ 1895 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, \
1994 tile_dev_intr, handle_interrupt_downcall 1896 tile_dev_intr
1995 int_hand INT_I_ASID, I_ASID, bad_intr 1897 int_hand INT_I_ASID, I_ASID, bad_intr
1996 int_hand INT_D_ASID, D_ASID, bad_intr 1898 int_hand INT_D_ASID, D_ASID, bad_intr
1997 int_hand INT_DMATLB_MISS_DWNCL, DMATLB_MISS_DWNCL, \ 1899 int_hand INT_DMATLB_MISS_DWNCL, DMATLB_MISS_DWNCL, \
1998 do_page_fault, handle_interrupt_downcall 1900 do_page_fault
1999 int_hand INT_SNITLB_MISS_DWNCL, SNITLB_MISS_DWNCL, \ 1901 int_hand INT_SNITLB_MISS_DWNCL, SNITLB_MISS_DWNCL, \
2000 do_page_fault, handle_interrupt_downcall 1902 do_page_fault
2001 int_hand INT_DMATLB_ACCESS_DWNCL, DMATLB_ACCESS_DWNCL, \ 1903 int_hand INT_DMATLB_ACCESS_DWNCL, DMATLB_ACCESS_DWNCL, \
2002 do_page_fault, handle_interrupt_downcall 1904 do_page_fault
2003 int_hand INT_SN_CPL, SN_CPL, bad_intr 1905 int_hand INT_SN_CPL, SN_CPL, bad_intr
2004 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap 1906 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
2005#if CHIP_HAS_AUX_PERF_COUNTERS() 1907#if CHIP_HAS_AUX_PERF_COUNTERS()
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
new file mode 100644
index 000000000000..79c93e10ba27
--- /dev/null
+++ b/arch/tile/kernel/intvec_64.S
@@ -0,0 +1,1231 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Linux interrupt vectors.
15 */
16
17#include <linux/linkage.h>
18#include <linux/errno.h>
19#include <linux/unistd.h>
20#include <asm/ptrace.h>
21#include <asm/thread_info.h>
22#include <asm/irqflags.h>
23#include <asm/asm-offsets.h>
24#include <asm/types.h>
25#include <hv/hypervisor.h>
26#include <arch/abi.h>
27#include <arch/interrupts.h>
28#include <arch/spr_def.h>
29
30#ifdef CONFIG_PREEMPT
31# error "No support for kernel preemption currently"
32#endif
33
34#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
35
36#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
37
38
39 .macro push_reg reg, ptr=sp, delta=-8
40 {
41 st \ptr, \reg
42 addli \ptr, \ptr, \delta
43 }
44 .endm
45
46 .macro pop_reg reg, ptr=sp, delta=8
47 {
48 ld \reg, \ptr
49 addli \ptr, \ptr, \delta
50 }
51 .endm
52
53 .macro pop_reg_zero reg, zreg, ptr=sp, delta=8
54 {
55 move \zreg, zero
56 ld \reg, \ptr
57 addi \ptr, \ptr, \delta
58 }
59 .endm
60
61 .macro push_extra_callee_saves reg
62 PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
63 push_reg r51, \reg
64 push_reg r50, \reg
65 push_reg r49, \reg
66 push_reg r48, \reg
67 push_reg r47, \reg
68 push_reg r46, \reg
69 push_reg r45, \reg
70 push_reg r44, \reg
71 push_reg r43, \reg
72 push_reg r42, \reg
73 push_reg r41, \reg
74 push_reg r40, \reg
75 push_reg r39, \reg
76 push_reg r38, \reg
77 push_reg r37, \reg
78 push_reg r36, \reg
79 push_reg r35, \reg
80 push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
81 .endm
82
83 .macro panic str
84 .pushsection .rodata, "a"
851:
86 .asciz "\str"
87 .popsection
88 {
89 moveli r0, hw2_last(1b)
90 }
91 {
92 shl16insli r0, r0, hw1(1b)
93 }
94 {
95 shl16insli r0, r0, hw0(1b)
96 jal panic
97 }
98 .endm
99
100
101#ifdef __COLLECT_LINKER_FEEDBACK__
102 .pushsection .text.intvec_feedback,"ax"
103intvec_feedback:
104 .popsection
105#endif
106
107 /*
108 * Default interrupt handler.
109 *
110 * vecnum is where we'll put this code.
111 * c_routine is the C routine we'll call.
112 *
113 * The C routine is passed two arguments:
114 * - A pointer to the pt_regs state.
115 * - The interrupt vector number.
116 *
117 * The "processing" argument specifies the code for processing
118 * the interrupt. Defaults to "handle_interrupt".
119 */
120 .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
121 .org (\vecnum << 8)
122intvec_\vecname:
123 /* Temporarily save a register so we have somewhere to work. */
124
125 mtspr SPR_SYSTEM_SAVE_K_1, r0
126 mfspr r0, SPR_EX_CONTEXT_K_1
127
128 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
129
130 .ifc \vecnum, INT_DOUBLE_FAULT
131 /*
132 * For double-faults from user-space, fall through to the normal
133 * register save and stack setup path. Otherwise, it's the
134 * hypervisor giving us one last chance to dump diagnostics, and we
135 * branch to the kernel_double_fault routine to do so.
136 */
137 beqz r0, 1f
138 j _kernel_double_fault
1391:
140 .else
141 /*
142 * If we're coming from user-space, then set sp to the top of
143 * the kernel stack. Otherwise, assume sp is already valid.
144 */
145 {
146 bnez r0, 0f
147 move r0, sp
148 }
149 .endif
150
151 .ifc \c_routine, do_page_fault
152 /*
153 * The page_fault handler may be downcalled directly by the
154 * hypervisor even when Linux is running and has ICS set.
155 *
156 * In this case the contents of EX_CONTEXT_K_1 reflect the
157 * previous fault and can't be relied on to choose whether or
158 * not to reinitialize the stack pointer. So we add a test
159 * to see whether SYSTEM_SAVE_K_2 has the high bit set,
160 * and if so we don't reinitialize sp, since we must be coming
161 * from Linux. (In fact the precise case is !(val & ~1),
162 * but any Linux PC has to have the high bit set.)
163 *
164 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
165 * any path that turns into a downcall to one of our TLB handlers.
166 *
167 * FIXME: if we end up never using this path, perhaps we should
168 * prevent the hypervisor from generating downcalls in this case.
169 * The advantage of getting a downcall is we can panic in Linux.
170 */
171 mfspr r0, SPR_SYSTEM_SAVE_K_2
172 {
173 bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
174 move r0, sp
175 }
176 .endif
177
178
179 /*
180 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
181 * the current stack top in the higher bits. So we recover
182 * our stack top by just masking off the low bits, then
183 * point sp at the top aligned address on the actual stack page.
184 */
185 mfspr r0, SPR_SYSTEM_SAVE_K_0
186 mm r0, zero, LOG2_THREAD_SIZE, 63
187
1880:
189 /*
190 * Align the stack mod 64 so we can properly predict what
191 * cache lines we need to write-hint to reduce memory fetch
192 * latency as we enter the kernel. The layout of memory is
193 * as follows, with cache line 0 at the lowest VA, and cache
194 * line 8 just below the r0 value this "andi" computes.
195 * Note that we never write to cache line 8, and we skip
196 * cache lines 1-3 for syscalls.
197 *
198 * cache line 8: ptregs padding (two words)
199 * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
200 * cache line 6: r46...r53 (tp)
201 * cache line 5: r38...r45
202 * cache line 4: r30...r37
203 * cache line 3: r22...r29
204 * cache line 2: r14...r21
205 * cache line 1: r6...r13
206 * cache line 0: 2 x frame, r0..r5
207 */
208 andi r0, r0, -64
209
210 /*
211 * Push the first four registers on the stack, so that we can set
212 * them to vector-unique values before we jump to the common code.
213 *
214 * Registers are pushed on the stack as a struct pt_regs,
215 * with the sp initially just above the struct, and when we're
216 * done, sp points to the base of the struct, minus
217 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
218 *
219 * This routine saves just the first four registers, plus the
220 * stack context so we can do proper backtracing right away,
221 * and defers to handle_interrupt to save the rest.
222 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum.
223 */
224 addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
225 wh64 r0 /* cache line 7 */
226 {
227 st r0, lr
228 addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
229 }
230 {
231 st r0, sp
232 addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
233 }
234 wh64 sp /* cache line 6 */
235 {
236 st sp, r52
237 addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
238 }
239 wh64 sp /* cache line 0 */
240 {
241 st sp, r1
242 addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
243 }
244 {
245 st sp, r2
246 addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
247 }
248 {
249 st sp, r3
250 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
251 }
252 mfspr r0, SPR_EX_CONTEXT_K_0
253 .ifc \processing,handle_syscall
254 /*
255 * Bump the saved PC by one bundle so that when we return, we won't
256 * execute the same swint instruction again. We need to do this while
257 * we're in the critical section.
258 */
259 addi r0, r0, 8
260 .endif
261 {
262 st sp, r0
263 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
264 }
265 mfspr r0, SPR_EX_CONTEXT_K_1
266 {
267 st sp, r0
268 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
269 /*
270 * Use r0 for syscalls so it's a temporary; use r1 for interrupts
271 * so that it gets passed through unchanged to the handler routine.
272 * Note that the .if conditional confusingly spans bundles.
273 */
274 .ifc \processing,handle_syscall
275 movei r0, \vecnum
276 }
277 {
278 st sp, r0
279 .else
280 movei r1, \vecnum
281 }
282 {
283 st sp, r1
284 .endif
285 addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
286 }
287 mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
288 {
289 st sp, r0
290 addi sp, sp, -PTREGS_OFFSET_REG(0) - 8
291 }
292 {
293 st sp, zero /* write zero into "Next SP" frame pointer */
294 addi sp, sp, -8 /* leave SP pointing at bottom of frame */
295 }
296 .ifc \processing,handle_syscall
297 j handle_syscall
298 .else
299 /* Capture per-interrupt SPR context to registers. */
300 .ifc \c_routine, do_page_fault
301 mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
302 mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
303 .else
304 .ifc \vecnum, INT_ILL_TRANS
305 mfspr r2, ILL_TRANS_REASON
306 .else
307 .ifc \vecnum, INT_DOUBLE_FAULT
308 mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
309 .else
310 .ifc \c_routine, do_trap
311 mfspr r2, GPV_REASON
312 .else
313 .ifc \c_routine, op_handle_perf_interrupt
314 mfspr r2, PERF_COUNT_STS
315#if CHIP_HAS_AUX_PERF_COUNTERS()
316 .else
317 .ifc \c_routine, op_handle_aux_perf_interrupt
318 mfspr r2, AUX_PERF_COUNT_STS
319 .endif
320#endif
321 .endif
322 .endif
323 .endif
324 .endif
325 .endif
326 /* Put function pointer in r0 */
327 moveli r0, hw2_last(\c_routine)
328 shl16insli r0, r0, hw1(\c_routine)
329 {
330 shl16insli r0, r0, hw0(\c_routine)
331 j \processing
332 }
333 .endif
334 ENDPROC(intvec_\vecname)
335
336#ifdef __COLLECT_LINKER_FEEDBACK__
337 .pushsection .text.intvec_feedback,"ax"
338 .org (\vecnum << 5)
339 FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
340 jrp lr
341 .popsection
342#endif
343
344 .endm
345
346
347 /*
348 * Save the rest of the registers that we didn't save in the actual
349 * vector itself. We can't use r0-r10 inclusive here.
350 */
351 .macro finish_interrupt_save, function
352
353 /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
354 PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
355 {
356 .ifc \function,handle_syscall
357 st r52, r0
358 .else
359 st r52, zero
360 .endif
361 PTREGS_PTR(r52, PTREGS_OFFSET_TP)
362 }
363 st r52, tp
364 {
365 mfspr tp, CMPEXCH_VALUE
366 PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
367 }
368
369 /*
370 * For ordinary syscalls, we save neither caller- nor callee-
371 * save registers, since the syscall invoker doesn't expect the
372 * caller-saves to be saved, and the called kernel functions will
373 * take care of saving the callee-saves for us.
374 *
375 * For interrupts we save just the caller-save registers. Saving
376 * them is required (since the "caller" can't save them). Again,
377 * the called kernel functions will restore the callee-save
378 * registers for us appropriately.
379 *
380 * On return, we normally restore nothing special for syscalls,
381 * and just the caller-save registers for interrupts.
382 *
383 * However, there are some important caveats to all this:
384 *
385 * - We always save a few callee-save registers to give us
386 * some scratchpad registers to carry across function calls.
387 *
388 * - fork/vfork/etc require us to save all the callee-save
389 * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
390 *
391 * - We always save r0..r5 and r10 for syscalls, since we need
392 * to reload them a bit later for the actual kernel call, and
393 * since we might need them for -ERESTARTNOINTR, etc.
394 *
395 * - Before invoking a signal handler, we save the unsaved
396 * callee-save registers so they are visible to the
397 * signal handler or any ptracer.
398 *
399 * - If the unsaved callee-save registers are modified, we set
400 * a bit in pt_regs so we know to reload them from pt_regs
401 * and not just rely on the kernel function unwinding.
402 * (Done for ptrace register writes and SA_SIGINFO handler.)
403 */
404 {
405 st r52, tp
406 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
407 }
408 wh64 r52 /* cache line 4 */
409 push_reg r33, r52
410 push_reg r32, r52
411 push_reg r31, r52
412 .ifc \function,handle_syscall
413 push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
414 push_reg TREG_SYSCALL_NR_NAME, r52, \
415 PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
416 .else
417
418 push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
419 wh64 r52 /* cache line 3 */
420 push_reg r29, r52
421 push_reg r28, r52
422 push_reg r27, r52
423 push_reg r26, r52
424 push_reg r25, r52
425 push_reg r24, r52
426 push_reg r23, r52
427 push_reg r22, r52
428 wh64 r52 /* cache line 2 */
429 push_reg r21, r52
430 push_reg r20, r52
431 push_reg r19, r52
432 push_reg r18, r52
433 push_reg r17, r52
434 push_reg r16, r52
435 push_reg r15, r52
436 push_reg r14, r52
437 wh64 r52 /* cache line 1 */
438 push_reg r13, r52
439 push_reg r12, r52
440 push_reg r11, r52
441 push_reg r10, r52
442 push_reg r9, r52
443 push_reg r8, r52
444 push_reg r7, r52
445 push_reg r6, r52
446
447 .endif
448
449 push_reg r5, r52
450 st r52, r4
451
452 /* Load tp with our per-cpu offset. */
453#ifdef CONFIG_SMP
454 {
455 mfspr r20, SPR_SYSTEM_SAVE_K_0
456 moveli r21, hw2_last(__per_cpu_offset)
457 }
458 {
459 shl16insli r21, r21, hw1(__per_cpu_offset)
460 bfextu r20, r20, 0, LOG2_THREAD_SIZE-1
461 }
462 shl16insli r21, r21, hw0(__per_cpu_offset)
463 shl3add r20, r20, r21
464 ld tp, r20
465#else
466 move tp, zero
467#endif
468
469 /*
470 * If we will be returning to the kernel, we will need to
471 * reset the interrupt masks to the state they had before.
472 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
473 */
474 mfspr r32, SPR_EX_CONTEXT_K_1
475 {
476 andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
477 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
478 }
479 beqzt r32, 1f /* zero if from user space */
480 IRQS_DISABLED(r32) /* zero if irqs enabled */
481#if PT_FLAGS_DISABLE_IRQ != 1
482# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
483#endif
4841:
485 .ifnc \function,handle_syscall
486 /* Record the fact that we saved the caller-save registers above. */
487 ori r32, r32, PT_FLAGS_CALLER_SAVES
488 .endif
489 st r21, r32
490
491#ifdef __COLLECT_LINKER_FEEDBACK__
492 /*
493 * Notify the feedback routines that we were in the
494 * appropriate fixed interrupt vector area. Note that we
495 * still have ICS set at this point, so we can't invoke any
496 * atomic operations or we will panic. The feedback
497 * routines internally preserve r0..r10 and r30 up.
498 */
499 .ifnc \function,handle_syscall
500 shli r20, r1, 5
501 .else
502 moveli r20, INT_SWINT_1 << 5
503 .endif
504 moveli r21, hw2_last(intvec_feedback)
505 shl16insli r21, r21, hw1(intvec_feedback)
506 shl16insli r21, r21, hw0(intvec_feedback)
507 add r20, r20, r21
508 jalr r20
509
510 /* And now notify the feedback routines that we are here. */
511 FEEDBACK_ENTER(\function)
512#endif
513
514 /*
515 * we've captured enough state to the stack (including in
516 * particular our EX_CONTEXT state) that we can now release
517 * the interrupt critical section and replace it with our
518 * standard "interrupts disabled" mask value. This allows
519 * synchronous interrupts (and profile interrupts) to punch
520 * through from this point onwards.
521 */
522 .ifc \function,handle_nmi
523 IRQ_DISABLE_ALL(r20)
524 .else
525 IRQ_DISABLE(r20, r21)
526 .endif
527 mtspr INTERRUPT_CRITICAL_SECTION, zero
528
529 /*
530 * Prepare the first 256 stack bytes to be rapidly accessible
531 * without having to fetch the background data.
532 */
533 addi r52, sp, -64
534 {
535 wh64 r52
536 addi r52, r52, -64
537 }
538 {
539 wh64 r52
540 addi r52, r52, -64
541 }
542 {
543 wh64 r52
544 addi r52, r52, -64
545 }
546 wh64 r52
547
548#ifdef CONFIG_TRACE_IRQFLAGS
549 .ifnc \function,handle_nmi
550 /*
551 * We finally have enough state set up to notify the irq
552 * tracing code that irqs were disabled on entry to the handler.
553 * The TRACE_IRQS_OFF call clobbers registers r0-r29.
554 * For syscalls, we already have the register state saved away
555 * on the stack, so we don't bother to do any register saves here,
556 * and later we pop the registers back off the kernel stack.
557 * For interrupt handlers, save r0-r3 in callee-saved registers.
558 */
559 .ifnc \function,handle_syscall
560 { move r30, r0; move r31, r1 }
561 { move r32, r2; move r33, r3 }
562 .endif
563 TRACE_IRQS_OFF
564 .ifnc \function,handle_syscall
565 { move r0, r30; move r1, r31 }
566 { move r2, r32; move r3, r33 }
567 .endif
568 .endif
569#endif
570
571 .endm
572
573 /*
574 * Redispatch a downcall.
575 */
576 .macro dc_dispatch vecnum, vecname
577 .org (\vecnum << 8)
578intvec_\vecname:
579 j hv_downcall_dispatch
580 ENDPROC(intvec_\vecname)
581 .endm
582
583 /*
584 * Common code for most interrupts. The C function we're eventually
585 * going to is in r0, and the faultnum is in r1; the original
586 * values for those registers are on the stack.
587 */
588 .pushsection .text.handle_interrupt,"ax"
589handle_interrupt:
590 finish_interrupt_save handle_interrupt
591
592 /* Jump to the C routine; it should enable irqs as soon as possible. */
593 {
594 jalr r0
595 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
596 }
597 FEEDBACK_REENTER(handle_interrupt)
598 {
599 movei r30, 0 /* not an NMI */
600 j interrupt_return
601 }
602 STD_ENDPROC(handle_interrupt)
603
604/*
605 * This routine takes a boolean in r30 indicating if this is an NMI.
606 * If so, we also expect a boolean in r31 indicating whether to
607 * re-enable the oprofile interrupts.
608 */
609STD_ENTRY(interrupt_return)
610 /* If we're resuming to kernel space, don't check thread flags. */
611 {
612 bnez r30, .Lrestore_all /* NMIs don't special-case user-space */
613 PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
614 }
615 ld r29, r29
616 andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
617 {
618 beqzt r29, .Lresume_userspace
619 PTREGS_PTR(r29, PTREGS_OFFSET_PC)
620 }
621
622 /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
623 moveli r27, hw2_last(_cpu_idle_nap)
624 {
625 ld r28, r29
626 shl16insli r27, r27, hw1(_cpu_idle_nap)
627 }
628 {
629 shl16insli r27, r27, hw0(_cpu_idle_nap)
630 }
631 {
632 cmpeq r27, r27, r28
633 }
634 {
635 blbc r27, .Lrestore_all
636 addi r28, r28, 8
637 }
638 st r29, r28
639 j .Lrestore_all
640
641.Lresume_userspace:
642 FEEDBACK_REENTER(interrupt_return)
643
644 /*
645 * Disable interrupts so as to make sure we don't
646 * miss an interrupt that sets any of the thread flags (like
647 * need_resched or sigpending) between sampling and the iret.
648 * Routines like schedule() or do_signal() may re-enable
649 * interrupts before returning.
650 */
651 IRQ_DISABLE(r20, r21)
652 TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
653
654 /* Get base of stack in r32; note r30/31 are used as arguments here. */
655 GET_THREAD_INFO(r32)
656
657
658 /* Check to see if there is any work to do before returning to user. */
659 {
660 addi r29, r32, THREAD_INFO_FLAGS_OFFSET
661 moveli r1, hw1_last(_TIF_ALLWORK_MASK)
662 }
663 {
664 ld r29, r29
665 shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK)
666 }
667 and r1, r29, r1
668 beqzt r1, .Lrestore_all
669
670 /*
671 * Make sure we have all the registers saved for signal
672 * handling or single-step. Call out to C code to figure out
673 * exactly what we need to do for each flag bit, then if
674 * necessary, reload the flags and recheck.
675 */
676 push_extra_callee_saves r0
677 {
678 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
679 jal do_work_pending
680 }
681 bnez r0, .Lresume_userspace
682
683 /*
684 * In the NMI case we
685 * omit the call to single_process_check_nohz, which normally checks
686 * to see if we should start or stop the scheduler tick, because
687 * we can't call arbitrary Linux code from an NMI context.
688 * We always call the homecache TLB deferral code to re-trigger
689 * the deferral mechanism.
690 *
691 * The other chunk of responsibility this code has is to reset the
692 * interrupt masks appropriately to reset irqs and NMIs. We have
693 * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
694 * lockdep-type stuff, but we can't set ICS until afterwards, since
695 * ICS can only be used in very tight chunks of code to avoid
696 * tripping over various assertions that it is off.
697 */
698.Lrestore_all:
699 PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
700 {
701 ld r0, r0
702 PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
703 }
704 {
705 andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
706 ld r32, r32
707 }
708 bnez r0, 1f
709 j 2f
710#if PT_FLAGS_DISABLE_IRQ != 1
711# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
712#endif
7131: blbct r32, 2f
714 IRQ_DISABLE(r20,r21)
715 TRACE_IRQS_OFF
716 movei r0, 1
717 mtspr INTERRUPT_CRITICAL_SECTION, r0
718 beqzt r30, .Lrestore_regs
719 j 3f
7202: TRACE_IRQS_ON
721 movei r0, 1
722 mtspr INTERRUPT_CRITICAL_SECTION, r0
723 IRQ_ENABLE(r20, r21)
724 beqzt r30, .Lrestore_regs
7253:
726
727
728 /*
729 * We now commit to returning from this interrupt, since we will be
730 * doing things like setting EX_CONTEXT SPRs and unwinding the stack
731 * frame. No calls should be made to any other code after this point.
732 * This code should only be entered with ICS set.
733 * r32 must still be set to ptregs.flags.
734 * We launch loads to each cache line separately first, so we can
735 * get some parallelism out of the memory subsystem.
736 * We start zeroing caller-saved registers throughout, since
737 * that will save some cycles if this turns out to be a syscall.
738 */
739.Lrestore_regs:
740 FEEDBACK_REENTER(interrupt_return) /* called from elsewhere */
741
742 /*
743 * Rotate so we have one high bit and one low bit to test.
744 * - low bit says whether to restore all the callee-saved registers,
745 * or just r30-r33, and r52 up.
746 * - high bit (i.e. sign bit) says whether to restore all the
747 * caller-saved registers, or just r0.
748 */
749#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
750# error Rotate trick does not work :-)
751#endif
752 {
753 rotli r20, r32, 62
754 PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
755 }
756
757 /*
758 * Load cache lines 0, 4, 6 and 7, in that order, then use
759 * the last loaded value, which makes it likely that the other
760 * cache lines have also loaded, at which point we should be
761 * able to safely read all the remaining words on those cache
762 * lines without waiting for the memory subsystem.
763 */
764 pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
765 pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
766 pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
767 pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
768 pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
769 {
770 mtspr CMPEXCH_VALUE, r21
771 move r4, zero
772 }
773 pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
774 {
775 mtspr SPR_EX_CONTEXT_K_1, lr
776 andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
777 }
778 {
779 mtspr SPR_EX_CONTEXT_K_0, r21
780 move r5, zero
781 }
782
783 /* Restore callee-saveds that we actually use. */
784 pop_reg_zero r31, r6
785 pop_reg_zero r32, r7
786 pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
787
788 /*
789 * If we modified other callee-saveds, restore them now.
790 * This is rare, but could be via ptrace or signal handler.
791 */
792 {
793 move r9, zero
794 blbs r20, .Lrestore_callees
795 }
796.Lcontinue_restore_regs:
797
798 /* Check if we're returning from a syscall. */
799 {
800 move r10, zero
801 bltzt r20, 1f /* no, so go restore callee-save registers */
802 }
803
804 /*
805 * Check if we're returning to userspace.
806 * Note that if we're not, we don't worry about zeroing everything.
807 */
808 {
809 addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
810 bnez lr, .Lkernel_return
811 }
812
813 /*
814 * On return from syscall, we've restored r0 from pt_regs, but we
815 * clear the remainder of the caller-saved registers. We could
816 * restore the syscall arguments, but there's not much point,
817 * and it ensures user programs aren't trying to use the
818 * caller-saves if we clear them, as well as avoiding leaking
819 * kernel pointers into userspace.
820 */
821 pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
822 pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
823 {
824 ld sp, sp
825 move r13, zero
826 move r14, zero
827 }
828 { move r15, zero; move r16, zero }
829 { move r17, zero; move r18, zero }
830 { move r19, zero; move r20, zero }
831 { move r21, zero; move r22, zero }
832 { move r23, zero; move r24, zero }
833 { move r25, zero; move r26, zero }
834
835 /* Set r1 to errno if we are returning an error, otherwise zero. */
836 {
837 moveli r29, 4096
838 sub r1, zero, r0
839 }
840 {
841 move r28, zero
842 cmpltu r29, r1, r29
843 }
844 {
845 mnz r1, r29, r1
846 move r29, zero
847 }
848 iret
849
850 /*
851 * Not a syscall, so restore caller-saved registers.
852 * First kick off loads for cache lines 1-3, which we're touching
853 * for the first time here.
854 */
855 .align 64
8561: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
857 pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
858 pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
859 pop_reg r1
860 pop_reg r2
861 pop_reg r3
862 pop_reg r4
863 pop_reg r5
864 pop_reg r6
865 pop_reg r7
866 pop_reg r8
867 pop_reg r9
868 pop_reg r10
869 pop_reg r11
870 pop_reg r12, sp, 16
871 /* r13 already restored above */
872 pop_reg r14
873 pop_reg r15
874 pop_reg r16
875 pop_reg r17
876 pop_reg r18
877 pop_reg r19
878 pop_reg r20, sp, 16
879 /* r21 already restored above */
880 pop_reg r22
881 pop_reg r23
882 pop_reg r24
883 pop_reg r25
884 pop_reg r26
885 pop_reg r27
886 pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
887 /* r29 already restored above */
888 bnez lr, .Lkernel_return
889 pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
890 pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
891 ld sp, sp
892 iret
893
894 /*
895 * We can't restore tp when in kernel mode, since a thread might
896 * have migrated from another cpu and brought a stale tp value.
897 */
898.Lkernel_return:
899 pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
900 ld sp, sp
901 iret
902
903 /* Restore callee-saved registers from r34 to r51. */
904.Lrestore_callees:
905 addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
906 pop_reg r34
907 pop_reg r35
908 pop_reg r36
909 pop_reg r37
910 pop_reg r38
911 pop_reg r39
912 pop_reg r40
913 pop_reg r41
914 pop_reg r42
915 pop_reg r43
916 pop_reg r44
917 pop_reg r45
918 pop_reg r46
919 pop_reg r47
920 pop_reg r48
921 pop_reg r49
922 pop_reg r50
923 pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
924 j .Lcontinue_restore_regs
925 STD_ENDPROC(interrupt_return)
926
927 /*
928 * "NMI" interrupts mask ALL interrupts before calling the
929 * handler, and don't check thread flags, etc., on the way
930 * back out. In general, the only things we do here for NMIs
931 * are register save/restore and dataplane kernel-TLB management.
932 * We don't (for example) deal with start/stop of the sched tick.
933 */
934 .pushsection .text.handle_nmi,"ax"
935handle_nmi:
936 finish_interrupt_save handle_nmi
937 {
938 jalr r0
939 PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
940 }
941 FEEDBACK_REENTER(handle_nmi)
942 {
943 movei r30, 1
944 move r31, r0
945 }
946 j interrupt_return
947 STD_ENDPROC(handle_nmi)
948
949 /*
950 * Parallel code for syscalls to handle_interrupt.
951 */
952 .pushsection .text.handle_syscall,"ax"
953handle_syscall:
954 finish_interrupt_save handle_syscall
955
956 /* Enable irqs. */
957 TRACE_IRQS_ON
958 IRQ_ENABLE(r20, r21)
959
960 /* Bump the counter for syscalls made on this tile. */
961 moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
962 shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
963 shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
964 add r20, r20, tp
965 ld4s r21, r20
966 addi r21, r21, 1
967 st4 r20, r21
968
969 /* Trace syscalls, if requested. */
970 GET_THREAD_INFO(r31)
971 addi r31, r31, THREAD_INFO_FLAGS_OFFSET
972 ld r30, r31
973 andi r30, r30, _TIF_SYSCALL_TRACE
974 {
975 addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
976 beqzt r30, .Lrestore_syscall_regs
977 }
978 jal do_syscall_trace
979 FEEDBACK_REENTER(handle_syscall)
980
981 /*
982 * We always reload our registers from the stack at this
983 * point. They might be valid, if we didn't build with
984 * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
985 * doing syscall tracing, but there are enough cases now that it
986 * seems simplest just to do the reload unconditionally.
987 */
988.Lrestore_syscall_regs:
989 {
990 ld r30, r30
991 PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
992 }
993 pop_reg r0, r11
994 pop_reg r1, r11
995 pop_reg r2, r11
996 pop_reg r3, r11
997 pop_reg r4, r11
998 pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
999 {
1000 ld TREG_SYSCALL_NR_NAME, r11
1001 moveli r21, __NR_syscalls
1002 }
1003
1004 /* Ensure that the syscall number is within the legal range. */
1005 {
1006 moveli r20, hw2(sys_call_table)
1007 blbs r30, .Lcompat_syscall
1008 }
1009 {
1010 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1011 shl16insli r20, r20, hw1(sys_call_table)
1012 }
1013 {
1014 blbc r21, .Linvalid_syscall
1015 shl16insli r20, r20, hw0(sys_call_table)
1016 }
1017.Lload_syscall_pointer:
1018 shl3add r20, TREG_SYSCALL_NR_NAME, r20
1019 ld r20, r20
1020
1021 /* Jump to syscall handler. */
1022 jalr r20
1023.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
1024
1025 /*
1026 * Write our r0 onto the stack so it gets restored instead
1027 * of whatever the user had there before.
1028 * In compat mode, sign-extend r0 before storing it.
1029 */
1030 {
1031 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1032 blbct r30, 1f
1033 }
1034 addxi r0, r0, 0
10351: st r29, r0
1036
1037.Lsyscall_sigreturn_skip:
1038 FEEDBACK_REENTER(handle_syscall)
1039
1040 /* Do syscall trace again, if requested. */
1041 ld r30, r31
1042 andi r30, r30, _TIF_SYSCALL_TRACE
1043 beqzt r30, 1f
1044 jal do_syscall_trace
1045 FEEDBACK_REENTER(handle_syscall)
10461: j .Lresume_userspace /* jump into middle of interrupt_return */
1047
1048.Lcompat_syscall:
1049 /*
1050 * Load the base of the compat syscall table in r20, and
1051 * range-check the syscall number (duplicated from 64-bit path).
1052 * Sign-extend all the user's passed arguments to make them consistent.
1053 * Also save the original "r(n)" values away in "r(11+n)" in
1054 * case the syscall table entry wants to validate them.
1055 */
1056 moveli r20, hw2(compat_sys_call_table)
1057 {
1058 cmpltu r21, TREG_SYSCALL_NR_NAME, r21
1059 shl16insli r20, r20, hw1(compat_sys_call_table)
1060 }
1061 {
1062 blbc r21, .Linvalid_syscall
1063 shl16insli r20, r20, hw0(compat_sys_call_table)
1064 }
1065 { move r11, r0; addxi r0, r0, 0 }
1066 { move r12, r1; addxi r1, r1, 0 }
1067 { move r13, r2; addxi r2, r2, 0 }
1068 { move r14, r3; addxi r3, r3, 0 }
1069 { move r15, r4; addxi r4, r4, 0 }
1070 { move r16, r5; addxi r5, r5, 0 }
1071 j .Lload_syscall_pointer
1072
1073.Linvalid_syscall:
1074 /* Report an invalid syscall back to the user program */
1075 {
1076 PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
1077 movei r28, -ENOSYS
1078 }
1079 st r29, r28
1080 j .Lresume_userspace /* jump into middle of interrupt_return */
1081 STD_ENDPROC(handle_syscall)
1082
1083 /* Return the address for oprofile to suppress in backtraces. */
1084STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
1085 lnk r0
1086 {
1087 addli r0, r0, .Lhandle_syscall_link - .
1088 jrp lr
1089 }
1090 STD_ENDPROC(handle_syscall_link_address)
1091
1092STD_ENTRY(ret_from_fork)
1093 jal sim_notify_fork
1094 jal schedule_tail
1095 FEEDBACK_REENTER(ret_from_fork)
1096 j .Lresume_userspace
1097 STD_ENDPROC(ret_from_fork)
1098
1099/* Various stub interrupt handlers and syscall handlers */
1100
1101STD_ENTRY_LOCAL(_kernel_double_fault)
1102 mfspr r1, SPR_EX_CONTEXT_K_0
1103 move r2, lr
1104 move r3, sp
1105 move r4, r52
1106 addi sp, sp, -C_ABI_SAVE_AREA_SIZE
1107 j kernel_double_fault
1108 STD_ENDPROC(_kernel_double_fault)
1109
1110STD_ENTRY_LOCAL(bad_intr)
1111 mfspr r2, SPR_EX_CONTEXT_K_0
1112 panic "Unhandled interrupt %#x: PC %#lx"
1113 STD_ENDPROC(bad_intr)
1114
1115/* Put address of pt_regs in reg and jump. */
1116#define PTREGS_SYSCALL(x, reg) \
1117 STD_ENTRY(_##x); \
1118 { \
1119 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1120 j x \
1121 }; \
1122 STD_ENDPROC(_##x)
1123
1124/*
1125 * Special-case sigreturn to not write r0 to the stack on return.
1126 * This is technically more efficient, but it also avoids difficulties
1127 * in the 64-bit OS when handling 32-bit compat code, since we must not
1128 * sign-extend r0 for the sigreturn return-value case.
1129 */
1130#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
1131 STD_ENTRY(_##x); \
1132 addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
1133 { \
1134 PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
1135 j x \
1136 }; \
1137 STD_ENDPROC(_##x)
1138
1139PTREGS_SYSCALL(sys_execve, r3)
1140PTREGS_SYSCALL(sys_sigaltstack, r2)
1141PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
1142#ifdef CONFIG_COMPAT
1143PTREGS_SYSCALL(compat_sys_execve, r3)
1144PTREGS_SYSCALL(compat_sys_sigaltstack, r2)
1145PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
1146#endif
1147
1148/* Save additional callee-saves to pt_regs, put address in r4 and jump. */
1149STD_ENTRY(_sys_clone)
1150 push_extra_callee_saves r4
1151 j sys_clone
1152 STD_ENDPROC(_sys_clone)
1153
1154/* The single-step support may need to read all the registers. */
1155int_unalign:
1156 push_extra_callee_saves r0
1157 j do_trap
1158
1159/* Include .intrpt1 array of interrupt vectors */
1160 .section ".intrpt1", "ax"
1161
1162#define op_handle_perf_interrupt bad_intr
1163#define op_handle_aux_perf_interrupt bad_intr
1164
1165#ifndef CONFIG_HARDWALL
1166#define do_hardwall_trap bad_intr
1167#endif
1168
1169 int_hand INT_MEM_ERROR, MEM_ERROR, bad_intr
1170 int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
1171#if CONFIG_KERNEL_PL == 2
1172 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
1173 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
1174#else
1175 int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
1176 int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
1177#endif
1178 int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
1179 int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
1180 int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
1181 int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault
1182 int_hand INT_ILL, ILL, do_trap
1183 int_hand INT_GPV, GPV, do_trap
1184 int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
1185 int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
1186 int_hand INT_SWINT_3, SWINT_3, do_trap
1187 int_hand INT_SWINT_2, SWINT_2, do_trap
1188 int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
1189 int_hand INT_SWINT_0, SWINT_0, do_trap
1190 int_hand INT_ILL_TRANS, ILL_TRANS, do_trap
1191 int_hand INT_UNALIGN_DATA, UNALIGN_DATA, int_unalign
1192 int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
1193 int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
1194 int_hand INT_IDN_FIREWALL, IDN_FIREWALL, bad_intr
1195 int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
1196 int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
1197 int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
1198 int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
1199 int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
1200 int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
1201 int_hand INT_IPI_3, IPI_3, bad_intr
1202#if CONFIG_KERNEL_PL == 2
1203 int_hand INT_IPI_2, IPI_2, tile_dev_intr
1204 int_hand INT_IPI_1, IPI_1, bad_intr
1205#else
1206 int_hand INT_IPI_2, IPI_2, bad_intr
1207 int_hand INT_IPI_1, IPI_1, tile_dev_intr
1208#endif
1209 int_hand INT_IPI_0, IPI_0, bad_intr
1210 int_hand INT_PERF_COUNT, PERF_COUNT, \
1211 op_handle_perf_interrupt, handle_nmi
1212 int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
1213 op_handle_perf_interrupt, handle_nmi
1214 int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
1215#if CONFIG_KERNEL_PL == 2
1216 dc_dispatch INT_INTCTRL_2, INTCTRL_2
1217 int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
1218#else
1219 int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
1220 dc_dispatch INT_INTCTRL_1, INTCTRL_1
1221#endif
1222 int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
1223 int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
1224 hv_message_intr
1225 int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
1226 int_hand INT_I_ASID, I_ASID, bad_intr
1227 int_hand INT_D_ASID, D_ASID, bad_intr
1228 int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
1229
1230 /* Synthetic interrupt delivered only by the simulator */
1231 int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint
diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c
index 596c60086930..aa0134db2dd6 100644
--- a/arch/tile/kernel/irq.c
+++ b/arch/tile/kernel/irq.c
@@ -26,7 +26,7 @@
26#define IS_HW_CLEARED 1 26#define IS_HW_CLEARED 1
27 27
28/* 28/*
29 * The set of interrupts we enable for raw_local_irq_enable(). 29 * The set of interrupts we enable for arch_local_irq_enable().
30 * This is initialized to have just a single interrupt that the kernel 30 * This is initialized to have just a single interrupt that the kernel
31 * doesn't actually use as a sentinel. During kernel init, 31 * doesn't actually use as a sentinel. During kernel init,
32 * interrupts are added as the kernel gets prepared to support them. 32 * interrupts are added as the kernel gets prepared to support them.
@@ -61,9 +61,9 @@ static DEFINE_SPINLOCK(available_irqs_lock);
61 61
62#if CHIP_HAS_IPI() 62#if CHIP_HAS_IPI()
63/* Use SPRs to manipulate device interrupts. */ 63/* Use SPRs to manipulate device interrupts. */
64#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_1, irq_mask) 64#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask)
65#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_1, irq_mask) 65#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask)
66#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_1, irq_mask) 66#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask)
67#else 67#else
68/* Use HV to manipulate device interrupts. */ 68/* Use HV to manipulate device interrupts. */
69#define mask_irqs(irq_mask) hv_disable_intr(irq_mask) 69#define mask_irqs(irq_mask) hv_disable_intr(irq_mask)
@@ -89,16 +89,16 @@ void tile_dev_intr(struct pt_regs *regs, int intnum)
89 * masked by a previous interrupt. Then, mask out the ones 89 * masked by a previous interrupt. Then, mask out the ones
90 * we're going to handle. 90 * we're going to handle.
91 */ 91 */
92 unsigned long masked = __insn_mfspr(SPR_IPI_MASK_1); 92 unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K);
93 original_irqs = __insn_mfspr(SPR_IPI_EVENT_1) & ~masked; 93 original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked;
94 __insn_mtspr(SPR_IPI_MASK_SET_1, original_irqs); 94 __insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs);
95#else 95#else
96 /* 96 /*
97 * Hypervisor performs the equivalent of the Gx code above and 97 * Hypervisor performs the equivalent of the Gx code above and
98 * then puts the pending interrupt mask into a system save reg 98 * then puts the pending interrupt mask into a system save reg
99 * for us to find. 99 * for us to find.
100 */ 100 */
101 original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_1_3); 101 original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3);
102#endif 102#endif
103 remaining_irqs = original_irqs; 103 remaining_irqs = original_irqs;
104 104
@@ -176,43 +176,43 @@ void disable_percpu_irq(unsigned int irq)
176EXPORT_SYMBOL(disable_percpu_irq); 176EXPORT_SYMBOL(disable_percpu_irq);
177 177
178/* Mask an interrupt. */ 178/* Mask an interrupt. */
179static void tile_irq_chip_mask(unsigned int irq) 179static void tile_irq_chip_mask(struct irq_data *d)
180{ 180{
181 mask_irqs(1UL << irq); 181 mask_irqs(1UL << d->irq);
182} 182}
183 183
184/* Unmask an interrupt. */ 184/* Unmask an interrupt. */
185static void tile_irq_chip_unmask(unsigned int irq) 185static void tile_irq_chip_unmask(struct irq_data *d)
186{ 186{
187 unmask_irqs(1UL << irq); 187 unmask_irqs(1UL << d->irq);
188} 188}
189 189
190/* 190/*
191 * Clear an interrupt before processing it so that any new assertions 191 * Clear an interrupt before processing it so that any new assertions
192 * will trigger another irq. 192 * will trigger another irq.
193 */ 193 */
194static void tile_irq_chip_ack(unsigned int irq) 194static void tile_irq_chip_ack(struct irq_data *d)
195{ 195{
196 if ((unsigned long)get_irq_chip_data(irq) != IS_HW_CLEARED) 196 if ((unsigned long)irq_data_get_irq_chip_data(d) != IS_HW_CLEARED)
197 clear_irqs(1UL << irq); 197 clear_irqs(1UL << d->irq);
198} 198}
199 199
200/* 200/*
201 * For per-cpu interrupts, we need to avoid unmasking any interrupts 201 * For per-cpu interrupts, we need to avoid unmasking any interrupts
202 * that we disabled via disable_percpu_irq(). 202 * that we disabled via disable_percpu_irq().
203 */ 203 */
204static void tile_irq_chip_eoi(unsigned int irq) 204static void tile_irq_chip_eoi(struct irq_data *d)
205{ 205{
206 if (!(__get_cpu_var(irq_disable_mask) & (1UL << irq))) 206 if (!(__get_cpu_var(irq_disable_mask) & (1UL << d->irq)))
207 unmask_irqs(1UL << irq); 207 unmask_irqs(1UL << d->irq);
208} 208}
209 209
210static struct irq_chip tile_irq_chip = { 210static struct irq_chip tile_irq_chip = {
211 .typename = "tile_irq_chip", 211 .name = "tile_irq_chip",
212 .ack = tile_irq_chip_ack, 212 .irq_ack = tile_irq_chip_ack,
213 .eoi = tile_irq_chip_eoi, 213 .irq_eoi = tile_irq_chip_eoi,
214 .mask = tile_irq_chip_mask, 214 .irq_mask = tile_irq_chip_mask,
215 .unmask = tile_irq_chip_unmask, 215 .irq_unmask = tile_irq_chip_unmask,
216}; 216};
217 217
218void __init init_IRQ(void) 218void __init init_IRQ(void)
@@ -225,7 +225,7 @@ void __cpuinit setup_irq_regs(void)
225 /* Enable interrupt delivery. */ 225 /* Enable interrupt delivery. */
226 unmask_irqs(~0UL); 226 unmask_irqs(~0UL);
227#if CHIP_HAS_IPI() 227#if CHIP_HAS_IPI()
228 raw_local_irq_unmask(INT_IPI_1); 228 arch_local_irq_unmask(INT_IPI_K);
229#endif 229#endif
230} 230}
231 231
@@ -241,14 +241,14 @@ void tile_irq_activate(unsigned int irq, int tile_irq_type)
241 irq_flow_handler_t handle = handle_level_irq; 241 irq_flow_handler_t handle = handle_level_irq;
242 if (tile_irq_type == TILE_IRQ_PERCPU) 242 if (tile_irq_type == TILE_IRQ_PERCPU)
243 handle = handle_percpu_irq; 243 handle = handle_percpu_irq;
244 set_irq_chip_and_handler(irq, &tile_irq_chip, handle); 244 irq_set_chip_and_handler(irq, &tile_irq_chip, handle);
245 245
246 /* 246 /*
247 * Flag interrupts that are hardware-cleared so that ack() 247 * Flag interrupts that are hardware-cleared so that ack()
248 * won't clear them. 248 * won't clear them.
249 */ 249 */
250 if (tile_irq_type == TILE_IRQ_HW_CLEAR) 250 if (tile_irq_type == TILE_IRQ_HW_CLEAR)
251 set_irq_chip_data(irq, (void *)IS_HW_CLEARED); 251 irq_set_chip_data(irq, (void *)IS_HW_CLEARED);
252} 252}
253EXPORT_SYMBOL(tile_irq_activate); 253EXPORT_SYMBOL(tile_irq_activate);
254 254
@@ -262,45 +262,6 @@ void ack_bad_irq(unsigned int irq)
262 * Generic, controller-independent functions: 262 * Generic, controller-independent functions:
263 */ 263 */
264 264
265int show_interrupts(struct seq_file *p, void *v)
266{
267 int i = *(loff_t *) v, j;
268 struct irqaction *action;
269 unsigned long flags;
270
271 if (i == 0) {
272 seq_printf(p, " ");
273 for (j = 0; j < NR_CPUS; j++)
274 if (cpu_online(j))
275 seq_printf(p, "CPU%-8d", j);
276 seq_putc(p, '\n');
277 }
278
279 if (i < NR_IRQS) {
280 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
281 action = irq_desc[i].action;
282 if (!action)
283 goto skip;
284 seq_printf(p, "%3d: ", i);
285#ifndef CONFIG_SMP
286 seq_printf(p, "%10u ", kstat_irqs(i));
287#else
288 for_each_online_cpu(j)
289 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
290#endif
291 seq_printf(p, " %14s", irq_desc[i].chip->typename);
292 seq_printf(p, " %s", action->name);
293
294 for (action = action->next; action; action = action->next)
295 seq_printf(p, ", %s", action->name);
296
297 seq_putc(p, '\n');
298skip:
299 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
300 }
301 return 0;
302}
303
304#if CHIP_HAS_IPI() 265#if CHIP_HAS_IPI()
305int create_irq(void) 266int create_irq(void)
306{ 267{
diff --git a/arch/tile/kernel/machine_kexec.c b/arch/tile/kernel/machine_kexec.c
index ba7a265d6179..e00d7179989e 100644
--- a/arch/tile/kernel/machine_kexec.c
+++ b/arch/tile/kernel/machine_kexec.c
@@ -182,13 +182,13 @@ static void kexec_find_and_set_command_line(struct kimage *image)
182 182
183 if ((entry & IND_SOURCE)) { 183 if ((entry & IND_SOURCE)) {
184 void *va = 184 void *va =
185 kmap_atomic_pfn(entry >> PAGE_SHIFT, KM_USER0); 185 kmap_atomic_pfn(entry >> PAGE_SHIFT);
186 r = kexec_bn2cl(va); 186 r = kexec_bn2cl(va);
187 if (r) { 187 if (r) {
188 command_line = r; 188 command_line = r;
189 break; 189 break;
190 } 190 }
191 kunmap_atomic(va, KM_USER0); 191 kunmap_atomic(va);
192 } 192 }
193 } 193 }
194 194
@@ -198,7 +198,7 @@ static void kexec_find_and_set_command_line(struct kimage *image)
198 198
199 hverr = hv_set_command_line( 199 hverr = hv_set_command_line(
200 (HV_VirtAddr) command_line, strlen(command_line)); 200 (HV_VirtAddr) command_line, strlen(command_line));
201 kunmap_atomic(command_line, KM_USER0); 201 kunmap_atomic(command_line);
202 } else { 202 } else {
203 pr_info("%s: no command line found; making empty\n", 203 pr_info("%s: no command line found; making empty\n",
204 __func__); 204 __func__);
@@ -240,8 +240,11 @@ static void setup_quasi_va_is_pa(void)
240 pte = hv_pte(_PAGE_KERNEL | _PAGE_HUGE_PAGE); 240 pte = hv_pte(_PAGE_KERNEL | _PAGE_HUGE_PAGE);
241 pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3); 241 pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
242 242
243 for (i = 0; i < pgd_index(PAGE_OFFSET); i++) 243 for (i = 0; i < pgd_index(PAGE_OFFSET); i++) {
244 pgtable[i] = pfn_pte(i << (HPAGE_SHIFT - PAGE_SHIFT), pte); 244 unsigned long pfn = i << (HPAGE_SHIFT - PAGE_SHIFT);
245 if (pfn_valid(pfn))
246 __set_pte(&pgtable[i], pfn_pte(pfn, pte));
247 }
245} 248}
246 249
247 250
diff --git a/arch/tile/kernel/messaging.c b/arch/tile/kernel/messaging.c
index 6d23ed271d10..0858ee6b520f 100644
--- a/arch/tile/kernel/messaging.c
+++ b/arch/tile/kernel/messaging.c
@@ -34,7 +34,7 @@ void __cpuinit init_messaging(void)
34 panic("hv_register_message_state: error %d", rc); 34 panic("hv_register_message_state: error %d", rc);
35 35
36 /* Make sure downcall interrupts will be enabled. */ 36 /* Make sure downcall interrupts will be enabled. */
37 raw_local_irq_unmask(INT_INTCTRL_1); 37 arch_local_irq_unmask(INT_INTCTRL_K);
38} 38}
39 39
40void hv_message_intr(struct pt_regs *regs, int intnum) 40void hv_message_intr(struct pt_regs *regs, int intnum)
diff --git a/arch/tile/kernel/module.c b/arch/tile/kernel/module.c
index e2ab82b7c7e7..f68df69f1f67 100644
--- a/arch/tile/kernel/module.c
+++ b/arch/tile/kernel/module.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <asm/opcode-tile.h> 23#include <asm/opcode-tile.h>
24#include <asm/pgtable.h> 24#include <asm/pgtable.h>
25#include <asm/homecache.h>
25 26
26#ifdef __tilegx__ 27#ifdef __tilegx__
27# define Elf_Rela Elf64_Rela 28# define Elf_Rela Elf64_Rela
@@ -86,8 +87,13 @@ error:
86void module_free(struct module *mod, void *module_region) 87void module_free(struct module *mod, void *module_region)
87{ 88{
88 vfree(module_region); 89 vfree(module_region);
90
91 /* Globally flush the L1 icache. */
92 flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
93 0, 0, 0, NULL, NULL, 0);
94
89 /* 95 /*
90 * FIXME: If module_region == mod->init_region, trim exception 96 * FIXME: If module_region == mod->module_init, trim exception
91 * table entries. 97 * table entries.
92 */ 98 */
93} 99}
diff --git a/arch/tile/kernel/pci-dma.c b/arch/tile/kernel/pci-dma.c
index 5ad5e13b0fa6..658f2ce426a4 100644
--- a/arch/tile/kernel/pci-dma.c
+++ b/arch/tile/kernel/pci-dma.c
@@ -86,6 +86,21 @@ EXPORT_SYMBOL(dma_free_coherent);
86 * can count on nothing having been touched. 86 * can count on nothing having been touched.
87 */ 87 */
88 88
89/* Flush a PA range from cache page by page. */
90static void __dma_map_pa_range(dma_addr_t dma_addr, size_t size)
91{
92 struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
93 size_t bytesleft = PAGE_SIZE - (dma_addr & (PAGE_SIZE - 1));
94
95 while ((ssize_t)size > 0) {
96 /* Flush the page. */
97 homecache_flush_cache(page++, 0);
98
99 /* Figure out if we need to continue on the next page. */
100 size -= bytesleft;
101 bytesleft = PAGE_SIZE;
102 }
103}
89 104
90/* 105/*
91 * dma_map_single can be passed any memory address, and there appear 106 * dma_map_single can be passed any memory address, and there appear
@@ -97,26 +112,12 @@ EXPORT_SYMBOL(dma_free_coherent);
97dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, 112dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
98 enum dma_data_direction direction) 113 enum dma_data_direction direction)
99{ 114{
100 struct page *page; 115 dma_addr_t dma_addr = __pa(ptr);
101 dma_addr_t dma_addr;
102 int thispage;
103 116
104 BUG_ON(!valid_dma_direction(direction)); 117 BUG_ON(!valid_dma_direction(direction));
105 WARN_ON(size == 0); 118 WARN_ON(size == 0);
106 119
107 dma_addr = __pa(ptr); 120 __dma_map_pa_range(dma_addr, size);
108
109 /* We might have been handed a buffer that wraps a page boundary */
110 while ((int)size > 0) {
111 /* The amount to flush that's on this page */
112 thispage = PAGE_SIZE - ((unsigned long)ptr & (PAGE_SIZE - 1));
113 thispage = min((int)thispage, (int)size);
114 /* Is this valid for any page we could be handed? */
115 page = pfn_to_page(kaddr_to_pfn(ptr));
116 homecache_flush_cache(page, 0);
117 ptr += thispage;
118 size -= thispage;
119 }
120 121
121 return dma_addr; 122 return dma_addr;
122} 123}
@@ -140,10 +141,8 @@ int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
140 WARN_ON(nents == 0 || sglist->length == 0); 141 WARN_ON(nents == 0 || sglist->length == 0);
141 142
142 for_each_sg(sglist, sg, nents, i) { 143 for_each_sg(sglist, sg, nents, i) {
143 struct page *page;
144 sg->dma_address = sg_phys(sg); 144 sg->dma_address = sg_phys(sg);
145 page = pfn_to_page(sg->dma_address >> PAGE_SHIFT); 145 __dma_map_pa_range(sg->dma_address, sg->length);
146 homecache_flush_cache(page, 0);
147 } 146 }
148 147
149 return nents; 148 return nents;
@@ -163,6 +162,7 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page,
163{ 162{
164 BUG_ON(!valid_dma_direction(direction)); 163 BUG_ON(!valid_dma_direction(direction));
165 164
165 BUG_ON(offset + size > PAGE_SIZE);
166 homecache_flush_cache(page, 0); 166 homecache_flush_cache(page, 0);
167 167
168 return page_to_pa(page) + offset; 168 return page_to_pa(page) + offset;
@@ -244,7 +244,7 @@ EXPORT_SYMBOL(dma_sync_single_range_for_device);
244 * dma_alloc_noncoherent() returns non-cacheable memory, so there's no 244 * dma_alloc_noncoherent() returns non-cacheable memory, so there's no
245 * need to do any flushing here. 245 * need to do any flushing here.
246 */ 246 */
247void dma_cache_sync(void *vaddr, size_t size, 247void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
248 enum dma_data_direction direction) 248 enum dma_data_direction direction)
249{ 249{
250} 250}
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
new file mode 100644
index 000000000000..6d4cb5d7a9fd
--- /dev/null
+++ b/arch/tile/kernel/pci.c
@@ -0,0 +1,647 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20#include <linux/capability.h>
21#include <linux/sched.h>
22#include <linux/errno.h>
23#include <linux/bootmem.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/uaccess.h>
27
28#include <asm/processor.h>
29#include <asm/sections.h>
30#include <asm/byteorder.h>
31#include <asm/hv_driver.h>
32#include <hv/drv_pcie_rc_intf.h>
33
34
35/*
36 * Initialization flow and process
37 * -------------------------------
38 *
39 * This files contains the routines to search for PCI buses,
40 * enumerate the buses, and configure any attached devices.
41 *
42 * There are two entry points here:
43 * 1) tile_pci_init
44 * This sets up the pci_controller structs, and opens the
45 * FDs to the hypervisor. This is called from setup_arch() early
46 * in the boot process.
47 * 2) pcibios_init
48 * This probes the PCI bus(es) for any attached hardware. It's
49 * called by subsys_initcall. All of the real work is done by the
50 * generic Linux PCI layer.
51 *
52 */
53
54/*
55 * This flag tells if the platform is TILEmpower that needs
56 * special configuration for the PLX switch chip.
57 */
58int __write_once tile_plx_gen1;
59
60static struct pci_controller controllers[TILE_NUM_PCIE];
61static int num_controllers;
62static int pci_scan_flags[TILE_NUM_PCIE];
63
64static struct pci_ops tile_cfg_ops;
65
66
67/*
68 * We don't need to worry about the alignment of resources.
69 */
70resource_size_t pcibios_align_resource(void *data, const struct resource *res,
71 resource_size_t size, resource_size_t align)
72{
73 return res->start;
74}
75EXPORT_SYMBOL(pcibios_align_resource);
76
77/*
78 * Open a FD to the hypervisor PCI device.
79 *
80 * controller_id is the controller number, config type is 0 or 1 for
81 * config0 or config1 operations.
82 */
83static int __devinit tile_pcie_open(int controller_id, int config_type)
84{
85 char filename[32];
86 int fd;
87
88 sprintf(filename, "pcie/%d/config%d", controller_id, config_type);
89
90 fd = hv_dev_open((HV_VirtAddr)filename, 0);
91
92 return fd;
93}
94
95
96/*
97 * Get the IRQ numbers from the HV and set up the handlers for them.
98 */
99static int __devinit tile_init_irqs(int controller_id,
100 struct pci_controller *controller)
101{
102 char filename[32];
103 int fd;
104 int ret;
105 int x;
106 struct pcie_rc_config rc_config;
107
108 sprintf(filename, "pcie/%d/ctl", controller_id);
109 fd = hv_dev_open((HV_VirtAddr)filename, 0);
110 if (fd < 0) {
111 pr_err("PCI: hv_dev_open(%s) failed\n", filename);
112 return -1;
113 }
114 ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
115 sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
116 hv_dev_close(fd);
117 if (ret != sizeof(rc_config)) {
118 pr_err("PCI: wanted %zd bytes, got %d\n",
119 sizeof(rc_config), ret);
120 return -1;
121 }
122 /* Record irq_base so that we can map INTx to IRQ # later. */
123 controller->irq_base = rc_config.intr;
124
125 for (x = 0; x < 4; x++)
126 tile_irq_activate(rc_config.intr + x,
127 TILE_IRQ_HW_CLEAR);
128
129 if (rc_config.plx_gen1)
130 controller->plx_gen1 = 1;
131
132 return 0;
133}
134
135/*
136 * First initialization entry point, called from setup_arch().
137 *
138 * Find valid controllers and fill in pci_controller structs for each
139 * of them.
140 *
141 * Returns the number of controllers discovered.
142 */
143int __devinit tile_pci_init(void)
144{
145 int i;
146
147 pr_info("PCI: Searching for controllers...\n");
148
149 /* Re-init number of PCIe controllers to support hot-plug feature. */
150 num_controllers = 0;
151
152 /* Do any configuration we need before using the PCIe */
153
154 for (i = 0; i < TILE_NUM_PCIE; i++) {
155 /*
156 * To see whether we need a real config op based on
157 * the results of pcibios_init(), to support PCIe hot-plug.
158 */
159 if (pci_scan_flags[i] == 0) {
160 int hv_cfg_fd0 = -1;
161 int hv_cfg_fd1 = -1;
162 int hv_mem_fd = -1;
163 char name[32];
164 struct pci_controller *controller;
165
166 /*
167 * Open the fd to the HV. If it fails then this
168 * device doesn't exist.
169 */
170 hv_cfg_fd0 = tile_pcie_open(i, 0);
171 if (hv_cfg_fd0 < 0)
172 continue;
173 hv_cfg_fd1 = tile_pcie_open(i, 1);
174 if (hv_cfg_fd1 < 0) {
175 pr_err("PCI: Couldn't open config fd to HV "
176 "for controller %d\n", i);
177 goto err_cont;
178 }
179
180 sprintf(name, "pcie/%d/mem", i);
181 hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
182 if (hv_mem_fd < 0) {
183 pr_err("PCI: Could not open mem fd to HV!\n");
184 goto err_cont;
185 }
186
187 pr_info("PCI: Found PCI controller #%d\n", i);
188
189 controller = &controllers[i];
190
191 controller->index = i;
192 controller->hv_cfg_fd[0] = hv_cfg_fd0;
193 controller->hv_cfg_fd[1] = hv_cfg_fd1;
194 controller->hv_mem_fd = hv_mem_fd;
195 controller->first_busno = 0;
196 controller->last_busno = 0xff;
197 controller->ops = &tile_cfg_ops;
198
199 num_controllers++;
200 continue;
201
202err_cont:
203 if (hv_cfg_fd0 >= 0)
204 hv_dev_close(hv_cfg_fd0);
205 if (hv_cfg_fd1 >= 0)
206 hv_dev_close(hv_cfg_fd1);
207 if (hv_mem_fd >= 0)
208 hv_dev_close(hv_mem_fd);
209 continue;
210 }
211 }
212
213 /*
214 * Before using the PCIe, see if we need to do any platform-specific
215 * configuration, such as the PLX switch Gen 1 issue on TILEmpower.
216 */
217 for (i = 0; i < num_controllers; i++) {
218 struct pci_controller *controller = &controllers[i];
219
220 if (controller->plx_gen1)
221 tile_plx_gen1 = 1;
222 }
223
224 return num_controllers;
225}
226
227/*
228 * (pin - 1) converts from the PCI standard's [1:4] convention to
229 * a normal [0:3] range.
230 */
231static int tile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
232{
233 struct pci_controller *controller =
234 (struct pci_controller *)dev->sysdata;
235 return (pin - 1) + controller->irq_base;
236}
237
238
239static void __devinit fixup_read_and_payload_sizes(void)
240{
241 struct pci_dev *dev = NULL;
242 int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
243 int max_read_size = 0x2; /* Limit to 512 byte reads. */
244 u16 new_values;
245
246 /* Scan for the smallest maximum payload size. */
247 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
248 int pcie_caps_offset;
249 u32 devcap;
250 int max_payload;
251
252 pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
253 if (pcie_caps_offset == 0)
254 continue;
255
256 pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
257 &devcap);
258 max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
259 if (max_payload < smallest_max_payload)
260 smallest_max_payload = max_payload;
261 }
262
263 /* Now, set the max_payload_size for all devices to that value. */
264 new_values = (max_read_size << 12) | (smallest_max_payload << 5);
265 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
266 int pcie_caps_offset;
267 u16 devctl;
268
269 pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
270 if (pcie_caps_offset == 0)
271 continue;
272
273 pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
274 &devctl);
275 devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
276 devctl |= new_values;
277 pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
278 devctl);
279 }
280}
281
282
283/*
284 * Second PCI initialization entry point, called by subsys_initcall.
285 *
286 * The controllers have been set up by the time we get here, by a call to
287 * tile_pci_init.
288 */
289int __devinit pcibios_init(void)
290{
291 int i;
292
293 pr_info("PCI: Probing PCI hardware\n");
294
295 /*
296 * Delay a bit in case devices aren't ready. Some devices are
297 * known to require at least 20ms here, but we use a more
298 * conservative value.
299 */
300 mdelay(250);
301
302 /* Scan all of the recorded PCI controllers. */
303 for (i = 0; i < TILE_NUM_PCIE; i++) {
304 /*
305 * Do real pcibios init ops if the controller is initialized
306 * by tile_pci_init() successfully and not initialized by
307 * pcibios_init() yet to support PCIe hot-plug.
308 */
309 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
310 struct pci_controller *controller = &controllers[i];
311 struct pci_bus *bus;
312
313 if (tile_init_irqs(i, controller)) {
314 pr_err("PCI: Could not initialize IRQs\n");
315 continue;
316 }
317
318 pr_info("PCI: initializing controller #%d\n", i);
319
320 /*
321 * This comes from the generic Linux PCI driver.
322 *
323 * It reads the PCI tree for this bus into the Linux
324 * data structures.
325 *
326 * This is inlined in linux/pci.h and calls into
327 * pci_scan_bus_parented() in probe.c.
328 */
329 bus = pci_scan_bus(0, controller->ops, controller);
330 controller->root_bus = bus;
331 controller->last_busno = bus->subordinate;
332 }
333 }
334
335 /* Do machine dependent PCI interrupt routing */
336 pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
337
338 /*
339 * This comes from the generic Linux PCI driver.
340 *
341 * It allocates all of the resources (I/O memory, etc)
342 * associated with the devices read in above.
343 */
344 pci_assign_unassigned_resources();
345
346 /* Configure the max_read_size and max_payload_size values. */
347 fixup_read_and_payload_sizes();
348
349 /* Record the I/O resources in the PCI controller structure. */
350 for (i = 0; i < TILE_NUM_PCIE; i++) {
351 /*
352 * Do real pcibios init ops if the controller is initialized
353 * by tile_pci_init() successfully and not initialized by
354 * pcibios_init() yet to support PCIe hot-plug.
355 */
356 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
357 struct pci_bus *root_bus = controllers[i].root_bus;
358 struct pci_bus *next_bus;
359 struct pci_dev *dev;
360
361 list_for_each_entry(dev, &root_bus->devices, bus_list) {
362 /*
363 * Find the PCI host controller, ie. the 1st
364 * bridge.
365 */
366 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
367 (PCI_SLOT(dev->devfn) == 0)) {
368 next_bus = dev->subordinate;
369 controllers[i].mem_resources[0] =
370 *next_bus->resource[0];
371 controllers[i].mem_resources[1] =
372 *next_bus->resource[1];
373 controllers[i].mem_resources[2] =
374 *next_bus->resource[2];
375
376 /* Setup flags. */
377 pci_scan_flags[i] = 1;
378
379 break;
380 }
381 }
382 }
383 }
384
385 return 0;
386}
387subsys_initcall(pcibios_init);
388
389/*
390 * No bus fixups needed.
391 */
392void __devinit pcibios_fixup_bus(struct pci_bus *bus)
393{
394 /* Nothing needs to be done. */
395}
396
397/*
398 * This can be called from the generic PCI layer, but doesn't need to
399 * do anything.
400 */
401char __devinit *pcibios_setup(char *str)
402{
403 /* Nothing needs to be done. */
404 return str;
405}
406
407/*
408 * This is called from the generic Linux layer.
409 */
410void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
411{
412 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
413}
414
415/*
416 * Enable memory and/or address decoding, as appropriate, for the
417 * device described by the 'dev' struct.
418 *
419 * This is called from the generic PCI layer, and can be called
420 * for bridges or endpoints.
421 */
422int pcibios_enable_device(struct pci_dev *dev, int mask)
423{
424 u16 cmd, old_cmd;
425 u8 header_type;
426 int i;
427 struct resource *r;
428
429 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
430
431 pci_read_config_word(dev, PCI_COMMAND, &cmd);
432 old_cmd = cmd;
433 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
434 /*
435 * For bridges, we enable both memory and I/O decoding
436 * in call cases.
437 */
438 cmd |= PCI_COMMAND_IO;
439 cmd |= PCI_COMMAND_MEMORY;
440 } else {
441 /*
442 * For endpoints, we enable memory and/or I/O decoding
443 * only if they have a memory resource of that type.
444 */
445 for (i = 0; i < 6; i++) {
446 r = &dev->resource[i];
447 if (r->flags & IORESOURCE_UNSET) {
448 pr_err("PCI: Device %s not available "
449 "because of resource collisions\n",
450 pci_name(dev));
451 return -EINVAL;
452 }
453 if (r->flags & IORESOURCE_IO)
454 cmd |= PCI_COMMAND_IO;
455 if (r->flags & IORESOURCE_MEM)
456 cmd |= PCI_COMMAND_MEMORY;
457 }
458 }
459
460 /*
461 * We only write the command if it changed.
462 */
463 if (cmd != old_cmd)
464 pci_write_config_word(dev, PCI_COMMAND, cmd);
465 return 0;
466}
467
468void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
469{
470 unsigned long start = pci_resource_start(dev, bar);
471 unsigned long len = pci_resource_len(dev, bar);
472 unsigned long flags = pci_resource_flags(dev, bar);
473
474 if (!len)
475 return NULL;
476 if (max && len > max)
477 len = max;
478
479 if (!(flags & IORESOURCE_MEM)) {
480 pr_info("PCI: Trying to map invalid resource %#lx\n", flags);
481 start = 0;
482 }
483
484 return (void __iomem *)start;
485}
486EXPORT_SYMBOL(pci_iomap);
487
488
489/****************************************************************
490 *
491 * Tile PCI config space read/write routines
492 *
493 ****************************************************************/
494
495/*
496 * These are the normal read and write ops
497 * These are expanded with macros from pci_bus_read_config_byte() etc.
498 *
499 * devfn is the combined PCI slot & function.
500 *
501 * offset is in bytes, from the start of config space for the
502 * specified bus & slot.
503 */
504
505static int __devinit tile_cfg_read(struct pci_bus *bus,
506 unsigned int devfn,
507 int offset,
508 int size,
509 u32 *val)
510{
511 struct pci_controller *controller = bus->sysdata;
512 int busnum = bus->number & 0xff;
513 int slot = (devfn >> 3) & 0x1f;
514 int function = devfn & 0x7;
515 u32 addr;
516 int config_mode = 1;
517
518 /*
519 * There is no bridge between the Tile and bus 0, so we
520 * use config0 to talk to bus 0.
521 *
522 * If we're talking to a bus other than zero then we
523 * must have found a bridge.
524 */
525 if (busnum == 0) {
526 /*
527 * We fake an empty slot for (busnum == 0) && (slot > 0),
528 * since there is only one slot on bus 0.
529 */
530 if (slot) {
531 *val = 0xFFFFFFFF;
532 return 0;
533 }
534 config_mode = 0;
535 }
536
537 addr = busnum << 20; /* Bus in 27:20 */
538 addr |= slot << 15; /* Slot (device) in 19:15 */
539 addr |= function << 12; /* Function is in 14:12 */
540 addr |= (offset & 0xFFF); /* byte address in 0:11 */
541
542 return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
543 (HV_VirtAddr)(val), size, addr);
544}
545
546
547/*
548 * See tile_cfg_read() for relevant comments.
549 * Note that "val" is the value to write, not a pointer to that value.
550 */
551static int __devinit tile_cfg_write(struct pci_bus *bus,
552 unsigned int devfn,
553 int offset,
554 int size,
555 u32 val)
556{
557 struct pci_controller *controller = bus->sysdata;
558 int busnum = bus->number & 0xff;
559 int slot = (devfn >> 3) & 0x1f;
560 int function = devfn & 0x7;
561 u32 addr;
562 int config_mode = 1;
563 HV_VirtAddr valp = (HV_VirtAddr)&val;
564
565 /*
566 * For bus 0 slot 0 we use config 0 accesses.
567 */
568 if (busnum == 0) {
569 /*
570 * We fake an empty slot for (busnum == 0) && (slot > 0),
571 * since there is only one slot on bus 0.
572 */
573 if (slot)
574 return 0;
575 config_mode = 0;
576 }
577
578 addr = busnum << 20; /* Bus in 27:20 */
579 addr |= slot << 15; /* Slot (device) in 19:15 */
580 addr |= function << 12; /* Function is in 14:12 */
581 addr |= (offset & 0xFFF); /* byte address in 0:11 */
582
583#ifdef __BIG_ENDIAN
584 /* Point to the correct part of the 32-bit "val". */
585 valp += 4 - size;
586#endif
587
588 return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
589 valp, size, addr);
590}
591
592
593static struct pci_ops tile_cfg_ops = {
594 .read = tile_cfg_read,
595 .write = tile_cfg_write,
596};
597
598
599/*
600 * In the following, each PCI controller's mem_resources[1]
601 * represents its (non-prefetchable) PCI memory resource.
602 * mem_resources[0] and mem_resources[2] refer to its PCI I/O and
603 * prefetchable PCI memory resources, respectively.
604 * For more details, see pci_setup_bridge() in setup-bus.c.
605 * By comparing the target PCI memory address against the
606 * end address of controller 0, we can determine the controller
607 * that should accept the PCI memory access.
608 */
609#define TILE_READ(size, type) \
610type _tile_read##size(unsigned long addr) \
611{ \
612 type val; \
613 int idx = 0; \
614 if (addr > controllers[0].mem_resources[1].end && \
615 addr > controllers[0].mem_resources[2].end) \
616 idx = 1; \
617 if (hv_dev_pread(controllers[idx].hv_mem_fd, 0, \
618 (HV_VirtAddr)(&val), sizeof(type), addr)) \
619 pr_err("PCI: read %zd bytes at 0x%lX failed\n", \
620 sizeof(type), addr); \
621 return val; \
622} \
623EXPORT_SYMBOL(_tile_read##size)
624
625TILE_READ(b, u8);
626TILE_READ(w, u16);
627TILE_READ(l, u32);
628TILE_READ(q, u64);
629
630#define TILE_WRITE(size, type) \
631void _tile_write##size(type val, unsigned long addr) \
632{ \
633 int idx = 0; \
634 if (addr > controllers[0].mem_resources[1].end && \
635 addr > controllers[0].mem_resources[2].end) \
636 idx = 1; \
637 if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0, \
638 (HV_VirtAddr)(&val), sizeof(type), addr)) \
639 pr_err("PCI: write %zd bytes at 0x%lX failed\n", \
640 sizeof(type), addr); \
641} \
642EXPORT_SYMBOL(_tile_write##size)
643
644TILE_WRITE(b, u8);
645TILE_WRITE(w, u16);
646TILE_WRITE(l, u32);
647TILE_WRITE(q, u64);
diff --git a/arch/tile/kernel/proc.c b/arch/tile/kernel/proc.c
index 2e02c41ddf3b..62d820833c68 100644
--- a/arch/tile/kernel/proc.c
+++ b/arch/tile/kernel/proc.c
@@ -27,6 +27,7 @@
27#include <asm/processor.h> 27#include <asm/processor.h>
28#include <asm/sections.h> 28#include <asm/sections.h>
29#include <asm/homecache.h> 29#include <asm/homecache.h>
30#include <asm/hardwall.h>
30#include <arch/chip.h> 31#include <arch/chip.h>
31 32
32 33
@@ -88,3 +89,75 @@ const struct seq_operations cpuinfo_op = {
88 .stop = c_stop, 89 .stop = c_stop,
89 .show = show_cpuinfo, 90 .show = show_cpuinfo,
90}; 91};
92
93/*
94 * Support /proc/tile directory
95 */
96
97static int __init proc_tile_init(void)
98{
99 struct proc_dir_entry *root = proc_mkdir("tile", NULL);
100 if (root == NULL)
101 return 0;
102
103 proc_tile_hardwall_init(root);
104
105 return 0;
106}
107
108arch_initcall(proc_tile_init);
109
110/*
111 * Support /proc/sys/tile directory
112 */
113
114#ifndef __tilegx__ /* FIXME: GX: no support for unaligned access yet */
115static ctl_table unaligned_subtable[] = {
116 {
117 .procname = "enabled",
118 .data = &unaligned_fixup,
119 .maxlen = sizeof(int),
120 .mode = 0644,
121 .proc_handler = &proc_dointvec
122 },
123 {
124 .procname = "printk",
125 .data = &unaligned_printk,
126 .maxlen = sizeof(int),
127 .mode = 0644,
128 .proc_handler = &proc_dointvec
129 },
130 {
131 .procname = "count",
132 .data = &unaligned_fixup_count,
133 .maxlen = sizeof(int),
134 .mode = 0644,
135 .proc_handler = &proc_dointvec
136 },
137 {}
138};
139
140static ctl_table unaligned_table[] = {
141 {
142 .procname = "unaligned_fixup",
143 .mode = 0555,
144 .child = unaligned_subtable
145 },
146 {}
147};
148#endif
149
150static struct ctl_path tile_path[] = {
151 { .procname = "tile" },
152 { }
153};
154
155static int __init proc_sys_tile_init(void)
156{
157#ifndef __tilegx__ /* FIXME: GX: no support for unaligned access yet */
158 register_sysctl_paths(tile_path, unaligned_table);
159#endif
160 return 0;
161}
162
163arch_initcall(proc_sys_tile_init);
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 84c29111756c..9c45d8bbdf57 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -25,10 +25,13 @@
25#include <linux/hardirq.h> 25#include <linux/hardirq.h>
26#include <linux/syscalls.h> 26#include <linux/syscalls.h>
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/tracehook.h>
29#include <linux/signal.h>
28#include <asm/system.h> 30#include <asm/system.h>
29#include <asm/stack.h> 31#include <asm/stack.h>
30#include <asm/homecache.h> 32#include <asm/homecache.h>
31#include <asm/syscalls.h> 33#include <asm/syscalls.h>
34#include <asm/traps.h>
32#ifdef CONFIG_HARDWALL 35#ifdef CONFIG_HARDWALL
33#include <asm/hardwall.h> 36#include <asm/hardwall.h>
34#endif 37#endif
@@ -109,7 +112,7 @@ void cpu_idle(void)
109 } 112 }
110} 113}
111 114
112struct thread_info *alloc_thread_info(struct task_struct *task) 115struct thread_info *alloc_thread_info_node(struct task_struct *task, int node)
113{ 116{
114 struct page *page; 117 struct page *page;
115 gfp_t flags = GFP_KERNEL; 118 gfp_t flags = GFP_KERNEL;
@@ -118,7 +121,7 @@ struct thread_info *alloc_thread_info(struct task_struct *task)
118 flags |= __GFP_ZERO; 121 flags |= __GFP_ZERO;
119#endif 122#endif
120 123
121 page = alloc_pages(flags, THREAD_SIZE_ORDER); 124 page = alloc_pages_node(node, flags, THREAD_SIZE_ORDER);
122 if (!page) 125 if (!page)
123 return NULL; 126 return NULL;
124 127
@@ -165,7 +168,7 @@ void free_thread_info(struct thread_info *info)
165 kfree(step_state); 168 kfree(step_state);
166 } 169 }
167 170
168 free_page((unsigned long)info); 171 free_pages((unsigned long)info, THREAD_SIZE_ORDER);
169} 172}
170 173
171static void save_arch_state(struct thread_struct *t); 174static void save_arch_state(struct thread_struct *t);
@@ -212,11 +215,19 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
212 childregs->sp = sp; /* override with new user stack pointer */ 215 childregs->sp = sp; /* override with new user stack pointer */
213 216
214 /* 217 /*
218 * If CLONE_SETTLS is set, set "tp" in the new task to "r4",
219 * which is passed in as arg #5 to sys_clone().
220 */
221 if (clone_flags & CLONE_SETTLS)
222 childregs->tp = regs->regs[4];
223
224 /*
215 * Copy the callee-saved registers from the passed pt_regs struct 225 * Copy the callee-saved registers from the passed pt_regs struct
216 * into the context-switch callee-saved registers area. 226 * into the context-switch callee-saved registers area.
217 * We have to restore the callee-saved registers since we may 227 * This way when we start the interrupt-return sequence, the
218 * be cloning a userspace task with userspace register state, 228 * callee-save registers will be correctly in registers, which
219 * and we won't be unwinding the same kernel frames to restore them. 229 * is how we assume the compiler leaves them as we start doing
230 * the normal return-from-interrupt path after calling C code.
220 * Zero out the C ABI save area to mark the top of the stack. 231 * Zero out the C ABI save area to mark the top of the stack.
221 */ 232 */
222 ksp = (unsigned long) childregs; 233 ksp = (unsigned long) childregs;
@@ -304,15 +315,25 @@ int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
304/* Allow user processes to access the DMA SPRs */ 315/* Allow user processes to access the DMA SPRs */
305void grant_dma_mpls(void) 316void grant_dma_mpls(void)
306{ 317{
318#if CONFIG_KERNEL_PL == 2
319 __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
320 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
321#else
307 __insn_mtspr(SPR_MPL_DMA_CPL_SET_0, 1); 322 __insn_mtspr(SPR_MPL_DMA_CPL_SET_0, 1);
308 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_0, 1); 323 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_0, 1);
324#endif
309} 325}
310 326
311/* Forbid user processes from accessing the DMA SPRs */ 327/* Forbid user processes from accessing the DMA SPRs */
312void restrict_dma_mpls(void) 328void restrict_dma_mpls(void)
313{ 329{
330#if CONFIG_KERNEL_PL == 2
331 __insn_mtspr(SPR_MPL_DMA_CPL_SET_2, 1);
332 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_2, 1);
333#else
314 __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1); 334 __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
315 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1); 335 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
336#endif
316} 337}
317 338
318/* Pause the DMA engine, then save off its state registers. */ 339/* Pause the DMA engine, then save off its state registers. */
@@ -523,19 +544,60 @@ struct task_struct *__sched _switch_to(struct task_struct *prev,
523 * Switch kernel SP, PC, and callee-saved registers. 544 * Switch kernel SP, PC, and callee-saved registers.
524 * In the context of the new task, return the old task pointer 545 * In the context of the new task, return the old task pointer
525 * (i.e. the task that actually called __switch_to). 546 * (i.e. the task that actually called __switch_to).
526 * Pass the value to use for SYSTEM_SAVE_1_0 when we reset our sp. 547 * Pass the value to use for SYSTEM_SAVE_K_0 when we reset our sp.
527 */ 548 */
528 return __switch_to(prev, next, next_current_ksp0(next)); 549 return __switch_to(prev, next, next_current_ksp0(next));
529} 550}
530 551
531long _sys_fork(struct pt_regs *regs) 552/*
553 * This routine is called on return from interrupt if any of the
554 * TIF_WORK_MASK flags are set in thread_info->flags. It is
555 * entered with interrupts disabled so we don't miss an event
556 * that modified the thread_info flags. If any flag is set, we
557 * handle it and return, and the calling assembly code will
558 * re-disable interrupts, reload the thread flags, and call back
559 * if more flags need to be handled.
560 *
561 * We return whether we need to check the thread_info flags again
562 * or not. Note that we don't clear TIF_SINGLESTEP here, so it's
563 * important that it be tested last, and then claim that we don't
564 * need to recheck the flags.
565 */
566int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
532{ 567{
533 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); 568 if (thread_info_flags & _TIF_NEED_RESCHED) {
569 schedule();
570 return 1;
571 }
572#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
573 if (thread_info_flags & _TIF_ASYNC_TLB) {
574 do_async_page_fault(regs);
575 return 1;
576 }
577#endif
578 if (thread_info_flags & _TIF_SIGPENDING) {
579 do_signal(regs);
580 return 1;
581 }
582 if (thread_info_flags & _TIF_NOTIFY_RESUME) {
583 clear_thread_flag(TIF_NOTIFY_RESUME);
584 tracehook_notify_resume(regs);
585 if (current->replacement_session_keyring)
586 key_replace_session_keyring();
587 return 1;
588 }
589 if (thread_info_flags & _TIF_SINGLESTEP) {
590 if ((regs->ex1 & SPR_EX_CONTEXT_1_1__PL_MASK) == 0)
591 single_step_once(regs);
592 return 0;
593 }
594 panic("work_pending: bad flags %#x\n", thread_info_flags);
534} 595}
535 596
536long _sys_clone(unsigned long clone_flags, unsigned long newsp, 597/* Note there is an implicit fifth argument if (clone_flags & CLONE_SETTLS). */
537 void __user *parent_tidptr, void __user *child_tidptr, 598SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp,
538 struct pt_regs *regs) 599 void __user *, parent_tidptr, void __user *, child_tidptr,
600 struct pt_regs *, regs)
539{ 601{
540 if (!newsp) 602 if (!newsp)
541 newsp = regs->sp; 603 newsp = regs->sp;
@@ -543,18 +605,13 @@ long _sys_clone(unsigned long clone_flags, unsigned long newsp,
543 parent_tidptr, child_tidptr); 605 parent_tidptr, child_tidptr);
544} 606}
545 607
546long _sys_vfork(struct pt_regs *regs)
547{
548 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp,
549 regs, 0, NULL, NULL);
550}
551
552/* 608/*
553 * sys_execve() executes a new program. 609 * sys_execve() executes a new program.
554 */ 610 */
555long _sys_execve(const char __user *path, 611SYSCALL_DEFINE4(execve, const char __user *, path,
556 const char __user *const __user *argv, 612 const char __user *const __user *, argv,
557 const char __user *const __user *envp, struct pt_regs *regs) 613 const char __user *const __user *, envp,
614 struct pt_regs *, regs)
558{ 615{
559 long error; 616 long error;
560 char *filename; 617 char *filename;
@@ -565,14 +622,17 @@ long _sys_execve(const char __user *path,
565 goto out; 622 goto out;
566 error = do_execve(filename, argv, envp, regs); 623 error = do_execve(filename, argv, envp, regs);
567 putname(filename); 624 putname(filename);
625 if (error == 0)
626 single_step_execve();
568out: 627out:
569 return error; 628 return error;
570} 629}
571 630
572#ifdef CONFIG_COMPAT 631#ifdef CONFIG_COMPAT
573long _compat_sys_execve(const char __user *path, 632long compat_sys_execve(const char __user *path,
574 const compat_uptr_t __user *argv, 633 compat_uptr_t __user *argv,
575 const compat_uptr_t __user *envp, struct pt_regs *regs) 634 compat_uptr_t __user *envp,
635 struct pt_regs *regs)
576{ 636{
577 long error; 637 long error;
578 char *filename; 638 char *filename;
@@ -583,6 +643,8 @@ long _compat_sys_execve(const char __user *path,
583 goto out; 643 goto out;
584 error = compat_do_execve(filename, argv, envp, regs); 644 error = compat_do_execve(filename, argv, envp, regs);
585 putname(filename); 645 putname(filename);
646 if (error == 0)
647 single_step_execve();
586out: 648out:
587 return error; 649 return error;
588} 650}
diff --git a/arch/tile/kernel/ptrace.c b/arch/tile/kernel/ptrace.c
index 7161bd03d2fd..e92e40527d6d 100644
--- a/arch/tile/kernel/ptrace.c
+++ b/arch/tile/kernel/ptrace.c
@@ -32,25 +32,6 @@ void user_disable_single_step(struct task_struct *child)
32} 32}
33 33
34/* 34/*
35 * This routine will put a word on the process's privileged stack.
36 */
37static void putreg(struct task_struct *task,
38 unsigned long addr, unsigned long value)
39{
40 unsigned int regno = addr / sizeof(unsigned long);
41 struct pt_regs *childregs = task_pt_regs(task);
42 childregs->regs[regno] = value;
43 childregs->flags |= PT_FLAGS_RESTORE_REGS;
44}
45
46static unsigned long getreg(struct task_struct *task, unsigned long addr)
47{
48 unsigned int regno = addr / sizeof(unsigned long);
49 struct pt_regs *childregs = task_pt_regs(task);
50 return childregs->regs[regno];
51}
52
53/*
54 * Called by kernel/ptrace.c when detaching.. 35 * Called by kernel/ptrace.c when detaching..
55 */ 36 */
56void ptrace_disable(struct task_struct *child) 37void ptrace_disable(struct task_struct *child)
@@ -64,61 +45,80 @@ void ptrace_disable(struct task_struct *child)
64 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); 45 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
65} 46}
66 47
67long arch_ptrace(struct task_struct *child, long request, long addr, long data) 48long arch_ptrace(struct task_struct *child, long request,
49 unsigned long addr, unsigned long data)
68{ 50{
69 unsigned long __user *datap; 51 unsigned long __user *datap = (long __user __force *)data;
70 unsigned long tmp; 52 unsigned long tmp;
71 int i;
72 long ret = -EIO; 53 long ret = -EIO;
73 54 char *childreg;
74#ifdef CONFIG_COMPAT 55 struct pt_regs copyregs;
75 if (task_thread_info(current)->status & TS_COMPAT) 56 int ex1_offset;
76 data = (u32)data;
77 if (task_thread_info(child)->status & TS_COMPAT)
78 addr = (u32)addr;
79#endif
80 datap = (unsigned long __user __force *)data;
81 57
82 switch (request) { 58 switch (request) {
83 59
84 case PTRACE_PEEKUSR: /* Read register from pt_regs. */ 60 case PTRACE_PEEKUSR: /* Read register from pt_regs. */
85 if (addr & (sizeof(data)-1)) 61 if (addr >= PTREGS_SIZE)
86 break;
87 if (addr < 0 || addr >= PTREGS_SIZE)
88 break; 62 break;
89 tmp = getreg(child, addr); /* Read register */ 63 childreg = (char *)task_pt_regs(child) + addr;
90 ret = put_user(tmp, datap); 64#ifdef CONFIG_COMPAT
65 if (is_compat_task()) {
66 if (addr & (sizeof(compat_long_t)-1))
67 break;
68 ret = put_user(*(compat_long_t *)childreg,
69 (compat_long_t __user *)datap);
70 } else
71#endif
72 {
73 if (addr & (sizeof(long)-1))
74 break;
75 ret = put_user(*(long *)childreg, datap);
76 }
91 break; 77 break;
92 78
93 case PTRACE_POKEUSR: /* Write register in pt_regs. */ 79 case PTRACE_POKEUSR: /* Write register in pt_regs. */
94 if (addr & (sizeof(data)-1)) 80 if (addr >= PTREGS_SIZE)
95 break; 81 break;
96 if (addr < 0 || addr >= PTREGS_SIZE) 82 childreg = (char *)task_pt_regs(child) + addr;
97 break; 83
98 putreg(child, addr, data); /* Write register */ 84 /* Guard against overwrites of the privilege level. */
85 ex1_offset = PTREGS_OFFSET_EX1;
86#if defined(CONFIG_COMPAT) && defined(__BIG_ENDIAN)
87 if (is_compat_task()) /* point at low word */
88 ex1_offset += sizeof(compat_long_t);
89#endif
90 if (addr == ex1_offset)
91 data = PL_ICS_EX1(USER_PL, EX1_ICS(data));
92
93#ifdef CONFIG_COMPAT
94 if (is_compat_task()) {
95 if (addr & (sizeof(compat_long_t)-1))
96 break;
97 *(compat_long_t *)childreg = data;
98 } else
99#endif
100 {
101 if (addr & (sizeof(long)-1))
102 break;
103 *(long *)childreg = data;
104 }
99 ret = 0; 105 ret = 0;
100 break; 106 break;
101 107
102 case PTRACE_GETREGS: /* Get all registers from the child. */ 108 case PTRACE_GETREGS: /* Get all registers from the child. */
103 if (!access_ok(VERIFY_WRITE, datap, PTREGS_SIZE)) 109 if (copy_to_user(datap, task_pt_regs(child),
104 break; 110 sizeof(struct pt_regs)) == 0) {
105 for (i = 0; i < PTREGS_SIZE; i += sizeof(long)) { 111 ret = 0;
106 ret = __put_user(getreg(child, i), datap);
107 if (ret != 0)
108 break;
109 datap++;
110 } 112 }
111 break; 113 break;
112 114
113 case PTRACE_SETREGS: /* Set all registers in the child. */ 115 case PTRACE_SETREGS: /* Set all registers in the child. */
114 if (!access_ok(VERIFY_READ, datap, PTREGS_SIZE)) 116 if (copy_from_user(&copyregs, datap,
115 break; 117 sizeof(struct pt_regs)) == 0) {
116 for (i = 0; i < PTREGS_SIZE; i += sizeof(long)) { 118 copyregs.ex1 =
117 ret = __get_user(tmp, datap); 119 PL_ICS_EX1(USER_PL, EX1_ICS(copyregs.ex1));
118 if (ret != 0) 120 *task_pt_regs(child) = copyregs;
119 break; 121 ret = 0;
120 putreg(child, i, tmp);
121 datap++;
122 } 122 }
123 break; 123 break;
124 124
diff --git a/arch/tile/kernel/reboot.c b/arch/tile/kernel/reboot.c
index acd86d20beba..baa3d905fee2 100644
--- a/arch/tile/kernel/reboot.c
+++ b/arch/tile/kernel/reboot.c
@@ -27,7 +27,7 @@
27void machine_halt(void) 27void machine_halt(void)
28{ 28{
29 warn_early_printk(); 29 warn_early_printk();
30 raw_local_irq_disable_all(); 30 arch_local_irq_disable_all();
31 smp_send_stop(); 31 smp_send_stop();
32 hv_halt(); 32 hv_halt();
33} 33}
@@ -35,14 +35,14 @@ void machine_halt(void)
35void machine_power_off(void) 35void machine_power_off(void)
36{ 36{
37 warn_early_printk(); 37 warn_early_printk();
38 raw_local_irq_disable_all(); 38 arch_local_irq_disable_all();
39 smp_send_stop(); 39 smp_send_stop();
40 hv_power_off(); 40 hv_power_off();
41} 41}
42 42
43void machine_restart(char *cmd) 43void machine_restart(char *cmd)
44{ 44{
45 raw_local_irq_disable_all(); 45 arch_local_irq_disable_all();
46 smp_send_stop(); 46 smp_send_stop();
47 hv_restart((HV_VirtAddr) "vmlinux", (HV_VirtAddr) cmd); 47 hv_restart((HV_VirtAddr) "vmlinux", (HV_VirtAddr) cmd);
48} 48}
diff --git a/arch/tile/kernel/regs_32.S b/arch/tile/kernel/regs_32.S
index e88d6e122783..caa13101c264 100644
--- a/arch/tile/kernel/regs_32.S
+++ b/arch/tile/kernel/regs_32.S
@@ -85,7 +85,7 @@ STD_ENTRY_SECTION(__switch_to, .sched.text)
85 { 85 {
86 /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */ 86 /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
87 move sp, r13 87 move sp, r13
88 mtspr SYSTEM_SAVE_1_0, r2 88 mtspr SPR_SYSTEM_SAVE_K_0, r2
89 } 89 }
90 FOR_EACH_CALLEE_SAVED_REG(LOAD_REG) 90 FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
91.L__switch_to_pc: 91.L__switch_to_pc:
diff --git a/arch/tile/kernel/regs_64.S b/arch/tile/kernel/regs_64.S
new file mode 100644
index 000000000000..f748c1e85285
--- /dev/null
+++ b/arch/tile/kernel/regs_64.S
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/linkage.h>
16#include <asm/system.h>
17#include <asm/ptrace.h>
18#include <asm/asm-offsets.h>
19#include <arch/spr_def.h>
20#include <asm/processor.h>
21
22/*
23 * See <asm/system.h>; called with prev and next task_struct pointers.
24 * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
25 *
26 * We want to save pc/sp in "prev", and get the new pc/sp from "next".
27 * We also need to save all the callee-saved registers on the stack.
28 *
29 * Intel enables/disables access to the hardware cycle counter in
30 * seccomp (secure computing) environments if necessary, based on
31 * has_secure_computing(). We might want to do this at some point,
32 * though it would require virtualizing the other SPRs under WORLD_ACCESS.
33 *
34 * Since we're saving to the stack, we omit sp from this list.
35 * And for parallels with other architectures, we save lr separately,
36 * in the thread_struct itself (as the "pc" field).
37 *
38 * This code also needs to be aligned with process.c copy_thread()
39 */
40
41#if CALLEE_SAVED_REGS_COUNT != 24
42# error Mismatch between <asm/system.h> and kernel/entry.S
43#endif
44#define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
45
46#define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
47#define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
48#define FOR_EACH_CALLEE_SAVED_REG(f) \
49 f(r30); f(r31); \
50 f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
51 f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
52 f(r48); f(r49); f(r50); f(r51); f(r52);
53
54STD_ENTRY_SECTION(__switch_to, .sched.text)
55 {
56 move r10, sp
57 st sp, lr
58 }
59 {
60 addli r11, sp, -FRAME_SIZE + 8
61 addli sp, sp, -FRAME_SIZE
62 }
63 {
64 st r11, r10
65 addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
66 }
67 {
68 ld r13, r4 /* Load new sp to a temp register early. */
69 addi r12, sp, 16
70 }
71 FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
72 addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
73 {
74 st r3, sp
75 addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
76 }
77 {
78 st r3, lr
79 addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
80 }
81 {
82 ld lr, r4
83 addi r12, r13, 16
84 }
85 {
86 /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
87 move sp, r13
88 mtspr SPR_SYSTEM_SAVE_K_0, r2
89 }
90 FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
91.L__switch_to_pc:
92 {
93 addli sp, sp, FRAME_SIZE
94 jrp lr /* r0 is still valid here, so return it */
95 }
96 STD_ENDPROC(__switch_to)
97
98/* Return a suitable address for the backtracer for suspended threads */
99STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
100 lnk r0
101 {
102 addli r0, r0, .L__switch_to_pc - .
103 jrp lr
104 }
105 STD_ENDPROC(get_switch_to_pc)
106
107STD_ENTRY(get_pt_regs)
108 .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
109 r8, r9, r10, r11, r12, r13, r14, r15, \
110 r16, r17, r18, r19, r20, r21, r22, r23, \
111 r24, r25, r26, r27, r28, r29, r30, r31, \
112 r32, r33, r34, r35, r36, r37, r38, r39, \
113 r40, r41, r42, r43, r44, r45, r46, r47, \
114 r48, r49, r50, r51, r52, tp, sp
115 {
116 st r0, \reg
117 addi r0, r0, 8
118 }
119 .endr
120 {
121 st r0, lr
122 addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
123 }
124 lnk r1
125 {
126 st r0, r1
127 addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
128 }
129 mfspr r1, INTERRUPT_CRITICAL_SECTION
130 shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
131 ori r1, r1, KERNEL_PL
132 {
133 st r0, r1
134 addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
135 }
136 {
137 st r0, zero /* clear faultnum */
138 addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
139 }
140 {
141 st r0, zero /* clear orig_r0 */
142 addli r0, r0, -PTREGS_OFFSET_ORIG_R0 /* restore r0 to base */
143 }
144 jrp lr
145 STD_ENDPROC(get_pt_regs)
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index e7d54c73d5c1..6cdc9ba55fe0 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -30,8 +30,6 @@
30#include <linux/timex.h> 30#include <linux/timex.h>
31#include <asm/setup.h> 31#include <asm/setup.h>
32#include <asm/sections.h> 32#include <asm/sections.h>
33#include <asm/sections.h>
34#include <asm/cacheflush.h>
35#include <asm/cacheflush.h> 33#include <asm/cacheflush.h>
36#include <asm/pgalloc.h> 34#include <asm/pgalloc.h>
37#include <asm/mmu_context.h> 35#include <asm/mmu_context.h>
@@ -61,6 +59,8 @@ unsigned long __initdata node_memmap_pfn[MAX_NUMNODES];
61unsigned long __initdata node_percpu_pfn[MAX_NUMNODES]; 59unsigned long __initdata node_percpu_pfn[MAX_NUMNODES];
62unsigned long __initdata node_free_pfn[MAX_NUMNODES]; 60unsigned long __initdata node_free_pfn[MAX_NUMNODES];
63 61
62static unsigned long __initdata node_percpu[MAX_NUMNODES];
63
64#ifdef CONFIG_HIGHMEM 64#ifdef CONFIG_HIGHMEM
65/* Page frame index of end of lowmem on each controller. */ 65/* Page frame index of end of lowmem on each controller. */
66unsigned long __cpuinitdata node_lowmem_end_pfn[MAX_NUMNODES]; 66unsigned long __cpuinitdata node_lowmem_end_pfn[MAX_NUMNODES];
@@ -187,11 +187,11 @@ early_param("vmalloc", parse_vmalloc);
187 187
188#ifdef CONFIG_HIGHMEM 188#ifdef CONFIG_HIGHMEM
189/* 189/*
190 * Determine for each controller where its lowmem is mapped and how 190 * Determine for each controller where its lowmem is mapped and how much of
191 * much of it is mapped there. On controller zero, the first few 191 * it is mapped there. On controller zero, the first few megabytes are
192 * megabytes are mapped at 0xfd000000 as code, so in principle we 192 * already mapped in as code at MEM_SV_INTRPT, so in principle we could
193 * could start our data mappings higher up, but for now we don't 193 * start our data mappings higher up, but for now we don't bother, to avoid
194 * bother, to avoid additional confusion. 194 * additional confusion.
195 * 195 *
196 * One question is whether, on systems with more than 768 Mb and 196 * One question is whether, on systems with more than 768 Mb and
197 * controllers of different sizes, to map in a proportionate amount of 197 * controllers of different sizes, to map in a proportionate amount of
@@ -311,7 +311,7 @@ static void __init setup_memory(void)
311#endif 311#endif
312 312
313 /* We are using a char to hold the cpu_2_node[] mapping */ 313 /* We are using a char to hold the cpu_2_node[] mapping */
314 BUG_ON(MAX_NUMNODES > 127); 314 BUILD_BUG_ON(MAX_NUMNODES > 127);
315 315
316 /* Discover the ranges of memory available to us */ 316 /* Discover the ranges of memory available to us */
317 for (i = 0; ; ++i) { 317 for (i = 0; ; ++i) {
@@ -556,7 +556,6 @@ static void __init setup_bootmem_allocator(void)
556 reserve_bootmem(crashk_res.start, 556 reserve_bootmem(crashk_res.start,
557 crashk_res.end - crashk_res.start + 1, 0); 557 crashk_res.end - crashk_res.start + 1, 0);
558#endif 558#endif
559
560} 559}
561 560
562void *__init alloc_remap(int nid, unsigned long size) 561void *__init alloc_remap(int nid, unsigned long size)
@@ -570,11 +569,13 @@ void *__init alloc_remap(int nid, unsigned long size)
570 569
571static int __init percpu_size(void) 570static int __init percpu_size(void)
572{ 571{
573 int size = ALIGN(__per_cpu_end - __per_cpu_start, PAGE_SIZE); 572 int size = __per_cpu_end - __per_cpu_start;
574#ifdef CONFIG_MODULES 573 size += PERCPU_MODULE_RESERVE;
575 if (size < PERCPU_ENOUGH_ROOM) 574 size += PERCPU_DYNAMIC_EARLY_SIZE;
576 size = PERCPU_ENOUGH_ROOM; 575 if (size < PCPU_MIN_UNIT_SIZE)
577#endif 576 size = PCPU_MIN_UNIT_SIZE;
577 size = roundup(size, PAGE_SIZE);
578
578 /* In several places we assume the per-cpu data fits on a huge page. */ 579 /* In several places we assume the per-cpu data fits on a huge page. */
579 BUG_ON(kdata_huge && size > HPAGE_SIZE); 580 BUG_ON(kdata_huge && size > HPAGE_SIZE);
580 return size; 581 return size;
@@ -591,7 +592,6 @@ static inline unsigned long alloc_bootmem_pfn(int size, unsigned long goal)
591static void __init zone_sizes_init(void) 592static void __init zone_sizes_init(void)
592{ 593{
593 unsigned long zones_size[MAX_NR_ZONES] = { 0 }; 594 unsigned long zones_size[MAX_NR_ZONES] = { 0 };
594 unsigned long node_percpu[MAX_NUMNODES] = { 0 };
595 int size = percpu_size(); 595 int size = percpu_size();
596 int num_cpus = smp_height * smp_width; 596 int num_cpus = smp_height * smp_width;
597 int i; 597 int i;
@@ -676,7 +676,7 @@ static void __init zone_sizes_init(void)
676 NODE_DATA(i)->bdata = NODE_DATA(0)->bdata; 676 NODE_DATA(i)->bdata = NODE_DATA(0)->bdata;
677 677
678 free_area_init_node(i, zones_size, start, NULL); 678 free_area_init_node(i, zones_size, start, NULL);
679 printk(KERN_DEBUG " DMA zone: %ld per-cpu pages\n", 679 printk(KERN_DEBUG " Normal zone: %ld per-cpu pages\n",
680 PFN_UP(node_percpu[i])); 680 PFN_UP(node_percpu[i]));
681 681
682 /* Track the type of memory on each node */ 682 /* Track the type of memory on each node */
@@ -842,7 +842,7 @@ static int __init topology_init(void)
842 for_each_online_node(i) 842 for_each_online_node(i)
843 register_one_node(i); 843 register_one_node(i);
844 844
845 for_each_present_cpu(i) 845 for (i = 0; i < smp_height * smp_width; ++i)
846 register_cpu(&cpu_devices[i], i); 846 register_cpu(&cpu_devices[i], i);
847 847
848 return 0; 848 return 0;
@@ -870,11 +870,14 @@ void __cpuinit setup_cpu(int boot)
870 870
871 /* Allow asynchronous TLB interrupts. */ 871 /* Allow asynchronous TLB interrupts. */
872#if CHIP_HAS_TILE_DMA() 872#if CHIP_HAS_TILE_DMA()
873 raw_local_irq_unmask(INT_DMATLB_MISS); 873 arch_local_irq_unmask(INT_DMATLB_MISS);
874 raw_local_irq_unmask(INT_DMATLB_ACCESS); 874 arch_local_irq_unmask(INT_DMATLB_ACCESS);
875#endif 875#endif
876#if CHIP_HAS_SN_PROC() 876#if CHIP_HAS_SN_PROC()
877 raw_local_irq_unmask(INT_SNITLB_MISS); 877 arch_local_irq_unmask(INT_SNITLB_MISS);
878#endif
879#ifdef __tilegx__
880 arch_local_irq_unmask(INT_SINGLE_STEP_K);
878#endif 881#endif
879 882
880 /* 883 /*
@@ -893,11 +896,12 @@ void __cpuinit setup_cpu(int boot)
893#endif 896#endif
894 897
895 /* 898 /*
896 * Set the MPL for interrupt control 0 to user level. 899 * Set the MPL for interrupt control 0 & 1 to the corresponding
897 * This includes access to the SYSTEM_SAVE and EX_CONTEXT SPRs, 900 * values. This includes access to the SYSTEM_SAVE and EX_CONTEXT
898 * as well as the PL 0 interrupt mask. 901 * SPRs, as well as the interrupt mask.
899 */ 902 */
900 __insn_mtspr(SPR_MPL_INTCTRL_0_SET_0, 1); 903 __insn_mtspr(SPR_MPL_INTCTRL_0_SET_0, 1);
904 __insn_mtspr(SPR_MPL_INTCTRL_1_SET_1, 1);
901 905
902 /* Initialize IRQ support for this cpu. */ 906 /* Initialize IRQ support for this cpu. */
903 setup_irq_regs(); 907 setup_irq_regs();
@@ -908,6 +912,8 @@ void __cpuinit setup_cpu(int boot)
908#endif 912#endif
909} 913}
910 914
915#ifdef CONFIG_BLK_DEV_INITRD
916
911static int __initdata set_initramfs_file; 917static int __initdata set_initramfs_file;
912static char __initdata initramfs_file[128] = "initramfs.cpio.gz"; 918static char __initdata initramfs_file[128] = "initramfs.cpio.gz";
913 919
@@ -965,6 +971,10 @@ void __init free_initrd_mem(unsigned long begin, unsigned long end)
965 free_bootmem(__pa(begin), end - begin); 971 free_bootmem(__pa(begin), end - begin);
966} 972}
967 973
974#else
975static inline void load_hv_initrd(void) {}
976#endif /* CONFIG_BLK_DEV_INITRD */
977
968static void __init validate_hv(void) 978static void __init validate_hv(void)
969{ 979{
970 /* 980 /*
@@ -1033,7 +1043,7 @@ static void __init validate_va(void)
1033 * In addition, make sure we CAN'T use the end of memory, since 1043 * In addition, make sure we CAN'T use the end of memory, since
1034 * we use the last chunk of each pgd for the pgd_list. 1044 * we use the last chunk of each pgd for the pgd_list.
1035 */ 1045 */
1036 int i, fc_fd_ok = 0; 1046 int i, user_kernel_ok = 0;
1037 unsigned long max_va = 0; 1047 unsigned long max_va = 0;
1038 unsigned long list_va = 1048 unsigned long list_va =
1039 ((PGD_LIST_OFFSET / sizeof(pgd_t)) << PGDIR_SHIFT); 1049 ((PGD_LIST_OFFSET / sizeof(pgd_t)) << PGDIR_SHIFT);
@@ -1044,13 +1054,13 @@ static void __init validate_va(void)
1044 break; 1054 break;
1045 if (range.start <= MEM_USER_INTRPT && 1055 if (range.start <= MEM_USER_INTRPT &&
1046 range.start + range.size >= MEM_HV_INTRPT) 1056 range.start + range.size >= MEM_HV_INTRPT)
1047 fc_fd_ok = 1; 1057 user_kernel_ok = 1;
1048 if (range.start == 0) 1058 if (range.start == 0)
1049 max_va = range.size; 1059 max_va = range.size;
1050 BUG_ON(range.start + range.size > list_va); 1060 BUG_ON(range.start + range.size > list_va);
1051 } 1061 }
1052 if (!fc_fd_ok) 1062 if (!user_kernel_ok)
1053 early_panic("Hypervisor not configured for VAs 0xfc/0xfd\n"); 1063 early_panic("Hypervisor not configured for user/kernel VAs\n");
1054 if (max_va == 0) 1064 if (max_va == 0)
1055 early_panic("Hypervisor not configured for low VAs\n"); 1065 early_panic("Hypervisor not configured for low VAs\n");
1056 if (max_va < KERNEL_HIGH_VADDR) 1066 if (max_va < KERNEL_HIGH_VADDR)
@@ -1310,6 +1320,8 @@ static void *__init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
1310 1320
1311 BUG_ON(size % PAGE_SIZE != 0); 1321 BUG_ON(size % PAGE_SIZE != 0);
1312 pfn_offset[nid] += size / PAGE_SIZE; 1322 pfn_offset[nid] += size / PAGE_SIZE;
1323 BUG_ON(node_percpu[nid] < size);
1324 node_percpu[nid] -= size;
1313 if (percpu_pfn[cpu] == 0) 1325 if (percpu_pfn[cpu] == 0)
1314 percpu_pfn[cpu] = pfn; 1326 percpu_pfn[cpu] = pfn;
1315 return pfn_to_kaddr(pfn); 1327 return pfn_to_kaddr(pfn);
@@ -1334,6 +1346,10 @@ static void __init pcpu_fc_populate_pte(unsigned long addr)
1334 pte_t *pte; 1346 pte_t *pte;
1335 1347
1336 BUG_ON(pgd_addr_invalid(addr)); 1348 BUG_ON(pgd_addr_invalid(addr));
1349 if (addr < VMALLOC_START || addr >= VMALLOC_END)
1350 panic("PCPU addr %#lx outside vmalloc range %#lx..%#lx;"
1351 " try increasing CONFIG_VMALLOC_RESERVE\n",
1352 addr, VMALLOC_START, VMALLOC_END);
1337 1353
1338 pgd = swapper_pg_dir + pgd_index(addr); 1354 pgd = swapper_pg_dir + pgd_index(addr);
1339 pud = pud_offset(pgd, addr); 1355 pud = pud_offset(pgd, addr);
diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c
index ce183aa1492c..bedaf4e9f3a7 100644
--- a/arch/tile/kernel/signal.c
+++ b/arch/tile/kernel/signal.c
@@ -16,7 +16,6 @@
16#include <linux/sched.h> 16#include <linux/sched.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/smp.h> 18#include <linux/smp.h>
19#include <linux/smp_lock.h>
20#include <linux/kernel.h> 19#include <linux/kernel.h>
21#include <linux/signal.h> 20#include <linux/signal.h>
22#include <linux/errno.h> 21#include <linux/errno.h>
@@ -40,9 +39,8 @@
40 39
41#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 40#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
42 41
43 42SYSCALL_DEFINE3(sigaltstack, const stack_t __user *, uss,
44long _sys_sigaltstack(const stack_t __user *uss, 43 stack_t __user *, uoss, struct pt_regs *, regs)
45 stack_t __user *uoss, struct pt_regs *regs)
46{ 44{
47 return do_sigaltstack(uss, uoss, regs->sp); 45 return do_sigaltstack(uss, uoss, regs->sp);
48} 46}
@@ -53,7 +51,7 @@ long _sys_sigaltstack(const stack_t __user *uss,
53 */ 51 */
54 52
55int restore_sigcontext(struct pt_regs *regs, 53int restore_sigcontext(struct pt_regs *regs,
56 struct sigcontext __user *sc, long *pr0) 54 struct sigcontext __user *sc)
57{ 55{
58 int err = 0; 56 int err = 0;
59 int i; 57 int i;
@@ -71,19 +69,27 @@ int restore_sigcontext(struct pt_regs *regs,
71 for (i = 0; i < sizeof(struct pt_regs)/sizeof(long); ++i) 69 for (i = 0; i < sizeof(struct pt_regs)/sizeof(long); ++i)
72 err |= __get_user(regs->regs[i], &sc->gregs[i]); 70 err |= __get_user(regs->regs[i], &sc->gregs[i]);
73 71
72 /* Ensure that the PL is always set to USER_PL. */
73 regs->ex1 = PL_ICS_EX1(USER_PL, EX1_ICS(regs->ex1));
74
74 regs->faultnum = INT_SWINT_1_SIGRETURN; 75 regs->faultnum = INT_SWINT_1_SIGRETURN;
75 76
76 err |= __get_user(*pr0, &sc->gregs[0]);
77 return err; 77 return err;
78} 78}
79 79
80/* sigreturn() returns long since it restores r0 in the interrupted code. */ 80void signal_fault(const char *type, struct pt_regs *regs,
81long _sys_rt_sigreturn(struct pt_regs *regs) 81 void __user *frame, int sig)
82{
83 trace_unhandled_signal(type, regs, (unsigned long)frame, SIGSEGV);
84 force_sigsegv(sig, current);
85}
86
87/* The assembly shim for this function arranges to ignore the return value. */
88SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs)
82{ 89{
83 struct rt_sigframe __user *frame = 90 struct rt_sigframe __user *frame =
84 (struct rt_sigframe __user *)(regs->sp); 91 (struct rt_sigframe __user *)(regs->sp);
85 sigset_t set; 92 sigset_t set;
86 long r0;
87 93
88 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 94 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
89 goto badframe; 95 goto badframe;
@@ -96,16 +102,16 @@ long _sys_rt_sigreturn(struct pt_regs *regs)
96 recalc_sigpending(); 102 recalc_sigpending();
97 spin_unlock_irq(&current->sighand->siglock); 103 spin_unlock_irq(&current->sighand->siglock);
98 104
99 if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) 105 if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
100 goto badframe; 106 goto badframe;
101 107
102 if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT) 108 if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT)
103 goto badframe; 109 goto badframe;
104 110
105 return r0; 111 return 0;
106 112
107badframe: 113badframe:
108 force_sig(SIGSEGV, current); 114 signal_fault("bad sigreturn frame", regs, frame, 0);
109 return 0; 115 return 0;
110} 116}
111 117
@@ -231,7 +237,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
231 return 0; 237 return 0;
232 238
233give_sigsegv: 239give_sigsegv:
234 force_sigsegv(sig, current); 240 signal_fault("bad setup frame", regs, frame, sig);
235 return -EFAULT; 241 return -EFAULT;
236} 242}
237 243
@@ -245,7 +251,6 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
245{ 251{
246 int ret; 252 int ret;
247 253
248
249 /* Are we from a system call? */ 254 /* Are we from a system call? */
250 if (regs->faultnum == INT_SWINT_1) { 255 if (regs->faultnum == INT_SWINT_1) {
251 /* If so, check system call restarting.. */ 256 /* If so, check system call restarting.. */
@@ -330,7 +335,7 @@ void do_signal(struct pt_regs *regs)
330 current_thread_info()->status &= ~TS_RESTORE_SIGMASK; 335 current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
331 } 336 }
332 337
333 return; 338 goto done;
334 } 339 }
335 340
336 /* Did we come from a system call? */ 341 /* Did we come from a system call? */
@@ -358,4 +363,123 @@ void do_signal(struct pt_regs *regs)
358 current_thread_info()->status &= ~TS_RESTORE_SIGMASK; 363 current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
359 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL); 364 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
360 } 365 }
366
367done:
368 /* Avoid double syscall restart if there are nested signals. */
369 regs->faultnum = INT_SWINT_1_SIGRETURN;
370}
371
372int show_unhandled_signals = 1;
373
374static int __init crashinfo(char *str)
375{
376 unsigned long val;
377 const char *word;
378
379 if (*str == '\0')
380 val = 2;
381 else if (*str != '=' || strict_strtoul(++str, 0, &val) != 0)
382 return 0;
383 show_unhandled_signals = val;
384 switch (show_unhandled_signals) {
385 case 0:
386 word = "No";
387 break;
388 case 1:
389 word = "One-line";
390 break;
391 default:
392 word = "Detailed";
393 break;
394 }
395 pr_info("%s crash reports will be generated on the console\n", word);
396 return 1;
397}
398__setup("crashinfo", crashinfo);
399
400static void dump_mem(void __user *address)
401{
402 void __user *addr;
403 enum { region_size = 256, bytes_per_line = 16 };
404 int i, j, k;
405 int found_readable_mem = 0;
406
407 pr_err("\n");
408 if (!access_ok(VERIFY_READ, address, 1)) {
409 pr_err("Not dumping at address 0x%lx (kernel address)\n",
410 (unsigned long)address);
411 return;
412 }
413
414 addr = (void __user *)
415 (((unsigned long)address & -bytes_per_line) - region_size/2);
416 if (addr > address)
417 addr = NULL;
418 for (i = 0; i < region_size;
419 addr += bytes_per_line, i += bytes_per_line) {
420 unsigned char buf[bytes_per_line];
421 char line[100];
422 if (copy_from_user(buf, addr, bytes_per_line))
423 continue;
424 if (!found_readable_mem) {
425 pr_err("Dumping memory around address 0x%lx:\n",
426 (unsigned long)address);
427 found_readable_mem = 1;
428 }
429 j = sprintf(line, REGFMT":", (unsigned long)addr);
430 for (k = 0; k < bytes_per_line; ++k)
431 j += sprintf(&line[j], " %02x", buf[k]);
432 pr_err("%s\n", line);
433 }
434 if (!found_readable_mem)
435 pr_err("No readable memory around address 0x%lx\n",
436 (unsigned long)address);
437}
438
439void trace_unhandled_signal(const char *type, struct pt_regs *regs,
440 unsigned long address, int sig)
441{
442 struct task_struct *tsk = current;
443
444 if (show_unhandled_signals == 0)
445 return;
446
447 /* If the signal is handled, don't show it here. */
448 if (!is_global_init(tsk)) {
449 void __user *handler =
450 tsk->sighand->action[sig-1].sa.sa_handler;
451 if (handler != SIG_IGN && handler != SIG_DFL)
452 return;
453 }
454
455 /* Rate-limit the one-line output, not the detailed output. */
456 if (show_unhandled_signals <= 1 && !printk_ratelimit())
457 return;
458
459 printk("%s%s[%d]: %s at %lx pc "REGFMT" signal %d",
460 task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
461 tsk->comm, task_pid_nr(tsk), type, address, regs->pc, sig);
462
463 print_vma_addr(KERN_CONT " in ", regs->pc);
464
465 printk(KERN_CONT "\n");
466
467 if (show_unhandled_signals > 1) {
468 switch (sig) {
469 case SIGILL:
470 case SIGFPE:
471 case SIGSEGV:
472 case SIGBUS:
473 pr_err("User crash: signal %d,"
474 " trap %ld, address 0x%lx\n",
475 sig, regs->faultnum, address);
476 show_regs(regs);
477 dump_mem((void __user *)address);
478 break;
479 default:
480 pr_err("User crash: signal %d, trap %ld\n",
481 sig, regs->faultnum);
482 break;
483 }
484 }
361} 485}
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c
index 5ec4b9c651f2..4032ca8e51b6 100644
--- a/arch/tile/kernel/single_step.c
+++ b/arch/tile/kernel/single_step.c
@@ -15,7 +15,7 @@
15 * Derived from iLib's single-stepping code. 15 * Derived from iLib's single-stepping code.
16 */ 16 */
17 17
18#ifndef __tilegx__ /* No support for single-step yet. */ 18#ifndef __tilegx__ /* Hardware support for single step unavailable. */
19 19
20/* These functions are only used on the TILE platform */ 20/* These functions are only used on the TILE platform */
21#include <linux/slab.h> 21#include <linux/slab.h>
@@ -56,7 +56,7 @@ enum mem_op {
56 MEMOP_STORE_POSTINCR 56 MEMOP_STORE_POSTINCR
57}; 57};
58 58
59static inline tile_bundle_bits set_BrOff_X1(tile_bundle_bits n, int32_t offset) 59static inline tile_bundle_bits set_BrOff_X1(tile_bundle_bits n, s32 offset)
60{ 60{
61 tile_bundle_bits result; 61 tile_bundle_bits result;
62 62
@@ -186,6 +186,8 @@ static tile_bundle_bits rewrite_load_store_unaligned(
186 .si_code = SEGV_MAPERR, 186 .si_code = SEGV_MAPERR,
187 .si_addr = addr 187 .si_addr = addr
188 }; 188 };
189 trace_unhandled_signal("segfault", regs,
190 (unsigned long)addr, SIGSEGV);
189 force_sig_info(info.si_signo, &info, current); 191 force_sig_info(info.si_signo, &info, current);
190 return (tile_bundle_bits) 0; 192 return (tile_bundle_bits) 0;
191 } 193 }
@@ -196,6 +198,8 @@ static tile_bundle_bits rewrite_load_store_unaligned(
196 .si_code = BUS_ADRALN, 198 .si_code = BUS_ADRALN,
197 .si_addr = addr 199 .si_addr = addr
198 }; 200 };
201 trace_unhandled_signal("unaligned trap", regs,
202 (unsigned long)addr, SIGBUS);
199 force_sig_info(info.si_signo, &info, current); 203 force_sig_info(info.si_signo, &info, current);
200 return (tile_bundle_bits) 0; 204 return (tile_bundle_bits) 0;
201 } 205 }
@@ -254,6 +258,18 @@ P("\n");
254 return bundle; 258 return bundle;
255} 259}
256 260
261/*
262 * Called after execve() has started the new image. This allows us
263 * to reset the info state. Note that the the mmap'ed memory, if there
264 * was any, has already been unmapped by the exec.
265 */
266void single_step_execve(void)
267{
268 struct thread_info *ti = current_thread_info();
269 kfree(ti->step_state);
270 ti->step_state = NULL;
271}
272
257/** 273/**
258 * single_step_once() - entry point when single stepping has been triggered. 274 * single_step_once() - entry point when single stepping has been triggered.
259 * @regs: The machine register state 275 * @regs: The machine register state
@@ -306,6 +322,14 @@ void single_step_once(struct pt_regs *regs)
306" .popsection\n" 322" .popsection\n"
307 ); 323 );
308 324
325 /*
326 * Enable interrupts here to allow touching userspace and the like.
327 * The callers expect this: do_trap() already has interrupts
328 * enabled, and do_work_pending() handles functions that enable
329 * interrupts internally.
330 */
331 local_irq_enable();
332
309 if (state == NULL) { 333 if (state == NULL) {
310 /* allocate a page of writable, executable memory */ 334 /* allocate a page of writable, executable memory */
311 state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL); 335 state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL);
@@ -373,7 +397,7 @@ void single_step_once(struct pt_regs *regs)
373 /* branches */ 397 /* branches */
374 case BRANCH_OPCODE_X1: 398 case BRANCH_OPCODE_X1:
375 { 399 {
376 int32_t offset = signExtend17(get_BrOff_X1(bundle)); 400 s32 offset = signExtend17(get_BrOff_X1(bundle));
377 401
378 /* 402 /*
379 * For branches, we use a rewriting trick to let the 403 * For branches, we use a rewriting trick to let the
@@ -660,4 +684,80 @@ void single_step_once(struct pt_regs *regs)
660 regs->pc += 8; 684 regs->pc += 8;
661} 685}
662 686
687#else
688#include <linux/smp.h>
689#include <linux/ptrace.h>
690#include <arch/spr_def.h>
691
692static DEFINE_PER_CPU(unsigned long, ss_saved_pc);
693
694
695/*
696 * Called directly on the occasion of an interrupt.
697 *
698 * If the process doesn't have single step set, then we use this as an
699 * opportunity to turn single step off.
700 *
701 * It has been mentioned that we could conditionally turn off single stepping
702 * on each entry into the kernel and rely on single_step_once to turn it
703 * on for the processes that matter (as we already do), but this
704 * implementation is somewhat more efficient in that we muck with registers
705 * once on a bum interrupt rather than on every entry into the kernel.
706 *
707 * If SINGLE_STEP_CONTROL_K has CANCELED set, then an interrupt occurred,
708 * so we have to run through this process again before we can say that an
709 * instruction has executed.
710 *
711 * swint will set CANCELED, but it's a legitimate instruction. Fortunately
712 * it changes the PC. If it hasn't changed, then we know that the interrupt
713 * wasn't generated by swint and we'll need to run this process again before
714 * we can say an instruction has executed.
715 *
716 * If either CANCELED == 0 or the PC's changed, we send out SIGTRAPs and get
717 * on with our lives.
718 */
719
720void gx_singlestep_handle(struct pt_regs *regs, int fault_num)
721{
722 unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc);
723 struct thread_info *info = (void *)current_thread_info();
724 int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
725 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
726
727 if (is_single_step == 0) {
728 __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 0);
729
730 } else if ((*ss_pc != regs->pc) ||
731 (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) {
732
733 ptrace_notify(SIGTRAP);
734 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
735 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
736 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
737 }
738}
739
740
741/*
742 * Called from need_singlestep. Set up the control registers and the enable
743 * register, then return back.
744 */
745
746void single_step_once(struct pt_regs *regs)
747{
748 unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc);
749 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
750
751 *ss_pc = regs->pc;
752 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
753 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
754 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
755 __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 1 << USER_PL);
756}
757
758void single_step_execve(void)
759{
760 /* Nothing */
761}
762
663#endif /* !__tilegx__ */ 763#endif /* !__tilegx__ */
diff --git a/arch/tile/kernel/smp.c b/arch/tile/kernel/smp.c
index 1cb5ec79de04..c52224d5ed45 100644
--- a/arch/tile/kernel/smp.c
+++ b/arch/tile/kernel/smp.c
@@ -36,6 +36,22 @@ static unsigned long __iomem *ipi_mappings[NR_CPUS];
36/* Set by smp_send_stop() to avoid recursive panics. */ 36/* Set by smp_send_stop() to avoid recursive panics. */
37static int stopping_cpus; 37static int stopping_cpus;
38 38
39static void __send_IPI_many(HV_Recipient *recip, int nrecip, int tag)
40{
41 int sent = 0;
42 while (sent < nrecip) {
43 int rc = hv_send_message(recip, nrecip,
44 (HV_VirtAddr)&tag, sizeof(tag));
45 if (rc < 0) {
46 if (!stopping_cpus) /* avoid recursive panic */
47 panic("hv_send_message returned %d", rc);
48 break;
49 }
50 WARN_ONCE(rc == 0, "hv_send_message() returned zero\n");
51 sent += rc;
52 }
53}
54
39void send_IPI_single(int cpu, int tag) 55void send_IPI_single(int cpu, int tag)
40{ 56{
41 HV_Recipient recip = { 57 HV_Recipient recip = {
@@ -43,14 +59,13 @@ void send_IPI_single(int cpu, int tag)
43 .x = cpu % smp_width, 59 .x = cpu % smp_width,
44 .state = HV_TO_BE_SENT 60 .state = HV_TO_BE_SENT
45 }; 61 };
46 int rc = hv_send_message(&recip, 1, (HV_VirtAddr)&tag, sizeof(tag)); 62 __send_IPI_many(&recip, 1, tag);
47 BUG_ON(rc <= 0);
48} 63}
49 64
50void send_IPI_many(const struct cpumask *mask, int tag) 65void send_IPI_many(const struct cpumask *mask, int tag)
51{ 66{
52 HV_Recipient recip[NR_CPUS]; 67 HV_Recipient recip[NR_CPUS];
53 int cpu, sent; 68 int cpu;
54 int nrecip = 0; 69 int nrecip = 0;
55 int my_cpu = smp_processor_id(); 70 int my_cpu = smp_processor_id();
56 for_each_cpu(cpu, mask) { 71 for_each_cpu(cpu, mask) {
@@ -61,17 +76,7 @@ void send_IPI_many(const struct cpumask *mask, int tag)
61 r->x = cpu % smp_width; 76 r->x = cpu % smp_width;
62 r->state = HV_TO_BE_SENT; 77 r->state = HV_TO_BE_SENT;
63 } 78 }
64 sent = 0; 79 __send_IPI_many(recip, nrecip, tag);
65 while (sent < nrecip) {
66 int rc = hv_send_message(recip, nrecip,
67 (HV_VirtAddr)&tag, sizeof(tag));
68 if (rc <= 0) {
69 if (!stopping_cpus) /* avoid recursive panic */
70 panic("hv_send_message returned %d", rc);
71 break;
72 }
73 sent += rc;
74 }
75} 80}
76 81
77void send_IPI_allbutself(int tag) 82void send_IPI_allbutself(int tag)
@@ -115,7 +120,7 @@ static void smp_start_cpu_interrupt(void)
115static void smp_stop_cpu_interrupt(void) 120static void smp_stop_cpu_interrupt(void)
116{ 121{
117 set_cpu_online(smp_processor_id(), 0); 122 set_cpu_online(smp_processor_id(), 0);
118 raw_local_irq_disable_all(); 123 arch_local_irq_disable_all();
119 for (;;) 124 for (;;)
120 asm("nap"); 125 asm("nap");
121} 126}
@@ -184,12 +189,8 @@ void flush_icache_range(unsigned long start, unsigned long end)
184/* Called when smp_send_reschedule() triggers IRQ_RESCHEDULE. */ 189/* Called when smp_send_reschedule() triggers IRQ_RESCHEDULE. */
185static irqreturn_t handle_reschedule_ipi(int irq, void *token) 190static irqreturn_t handle_reschedule_ipi(int irq, void *token)
186{ 191{
187 /*
188 * Nothing to do here; when we return from interrupt, the
189 * rescheduling will occur there. But do bump the interrupt
190 * profiler count in the meantime.
191 */
192 __get_cpu_var(irq_stat).irq_resched_count++; 192 __get_cpu_var(irq_stat).irq_resched_count++;
193 scheduler_ipi();
193 194
194 return IRQ_HANDLED; 195 return IRQ_HANDLED;
195} 196}
@@ -212,7 +213,7 @@ void __init ipi_init(void)
212 213
213 tile.x = cpu_x(cpu); 214 tile.x = cpu_x(cpu);
214 tile.y = cpu_y(cpu); 215 tile.y = cpu_y(cpu);
215 if (hv_get_ipi_pte(tile, 1, &pte) != 0) 216 if (hv_get_ipi_pte(tile, KERNEL_PL, &pte) != 0)
216 panic("Failed to initialize IPI for cpu %d\n", cpu); 217 panic("Failed to initialize IPI for cpu %d\n", cpu);
217 218
218 offset = hv_pte_get_pfn(pte) << PAGE_SHIFT; 219 offset = hv_pte_get_pfn(pte) << PAGE_SHIFT;
diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c
index 74d62d098edf..b949edcec200 100644
--- a/arch/tile/kernel/smpboot.c
+++ b/arch/tile/kernel/smpboot.c
@@ -18,7 +18,6 @@
18#include <linux/mm.h> 18#include <linux/mm.h>
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/kernel_stat.h> 20#include <linux/kernel_stat.h>
21#include <linux/smp_lock.h>
22#include <linux/bootmem.h> 21#include <linux/bootmem.h>
23#include <linux/notifier.h> 22#include <linux/notifier.h>
24#include <linux/cpu.h> 23#include <linux/cpu.h>
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
index ea2e0ce28380..37ee4d037e0b 100644
--- a/arch/tile/kernel/stack.c
+++ b/arch/tile/kernel/stack.c
@@ -30,9 +30,13 @@
30#include <arch/abi.h> 30#include <arch/abi.h>
31#include <arch/interrupts.h> 31#include <arch/interrupts.h>
32 32
33#define KBT_ONGOING 0 /* Backtrace still ongoing */
34#define KBT_DONE 1 /* Backtrace cleanly completed */
35#define KBT_RUNNING 2 /* Can't run backtrace on a running task */
36#define KBT_LOOP 3 /* Backtrace entered a loop */
33 37
34/* Is address on the specified kernel stack? */ 38/* Is address on the specified kernel stack? */
35static int in_kernel_stack(struct KBacktraceIterator *kbt, VirtualAddress sp) 39static int in_kernel_stack(struct KBacktraceIterator *kbt, unsigned long sp)
36{ 40{
37 ulong kstack_base = (ulong) kbt->task->stack; 41 ulong kstack_base = (ulong) kbt->task->stack;
38 if (kstack_base == 0) /* corrupt task pointer; just follow stack... */ 42 if (kstack_base == 0) /* corrupt task pointer; just follow stack... */
@@ -40,15 +44,8 @@ static int in_kernel_stack(struct KBacktraceIterator *kbt, VirtualAddress sp)
40 return sp >= kstack_base && sp < kstack_base + THREAD_SIZE; 44 return sp >= kstack_base && sp < kstack_base + THREAD_SIZE;
41} 45}
42 46
43/* Is address in the specified kernel code? */
44static int in_kernel_text(VirtualAddress address)
45{
46 return (address >= MEM_SV_INTRPT &&
47 address < MEM_SV_INTRPT + HPAGE_SIZE);
48}
49
50/* Is address valid for reading? */ 47/* Is address valid for reading? */
51static int valid_address(struct KBacktraceIterator *kbt, VirtualAddress address) 48static int valid_address(struct KBacktraceIterator *kbt, unsigned long address)
52{ 49{
53 HV_PTE *l1_pgtable = kbt->pgtable; 50 HV_PTE *l1_pgtable = kbt->pgtable;
54 HV_PTE *l2_pgtable; 51 HV_PTE *l2_pgtable;
@@ -59,6 +56,23 @@ static int valid_address(struct KBacktraceIterator *kbt, VirtualAddress address)
59 if (l1_pgtable == NULL) 56 if (l1_pgtable == NULL)
60 return 0; /* can't read user space in other tasks */ 57 return 0; /* can't read user space in other tasks */
61 58
59#ifdef CONFIG_64BIT
60 /* Find the real l1_pgtable by looking in the l0_pgtable. */
61 pte = l1_pgtable[HV_L0_INDEX(address)];
62 if (!hv_pte_get_present(pte))
63 return 0;
64 pfn = hv_pte_get_pfn(pte);
65 if (pte_huge(pte)) {
66 if (!pfn_valid(pfn)) {
67 pr_err("L0 huge page has bad pfn %#lx\n", pfn);
68 return 0;
69 }
70 return hv_pte_get_present(pte) && hv_pte_get_readable(pte);
71 }
72 page = pfn_to_page(pfn);
73 BUG_ON(PageHighMem(page)); /* No HIGHMEM on 64-bit. */
74 l1_pgtable = (HV_PTE *)pfn_to_kaddr(pfn);
75#endif
62 pte = l1_pgtable[HV_L1_INDEX(address)]; 76 pte = l1_pgtable[HV_L1_INDEX(address)];
63 if (!hv_pte_get_present(pte)) 77 if (!hv_pte_get_present(pte))
64 return 0; 78 return 0;
@@ -83,12 +97,12 @@ static int valid_address(struct KBacktraceIterator *kbt, VirtualAddress address)
83} 97}
84 98
85/* Callback for backtracer; basically a glorified memcpy */ 99/* Callback for backtracer; basically a glorified memcpy */
86static bool read_memory_func(void *result, VirtualAddress address, 100static bool read_memory_func(void *result, unsigned long address,
87 unsigned int size, void *vkbt) 101 unsigned int size, void *vkbt)
88{ 102{
89 int retval; 103 int retval;
90 struct KBacktraceIterator *kbt = (struct KBacktraceIterator *)vkbt; 104 struct KBacktraceIterator *kbt = (struct KBacktraceIterator *)vkbt;
91 if (in_kernel_text(address)) { 105 if (__kernel_text_address(address)) {
92 /* OK to read kernel code. */ 106 /* OK to read kernel code. */
93 } else if (address >= PAGE_OFFSET) { 107 } else if (address >= PAGE_OFFSET) {
94 /* We only tolerate kernel-space reads of this task's stack */ 108 /* We only tolerate kernel-space reads of this task's stack */
@@ -110,7 +124,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
110{ 124{
111 const char *fault = NULL; /* happy compiler */ 125 const char *fault = NULL; /* happy compiler */
112 char fault_buf[64]; 126 char fault_buf[64];
113 VirtualAddress sp = kbt->it.sp; 127 unsigned long sp = kbt->it.sp;
114 struct pt_regs *p; 128 struct pt_regs *p;
115 129
116 if (!in_kernel_stack(kbt, sp)) 130 if (!in_kernel_stack(kbt, sp))
@@ -128,7 +142,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
128 } 142 }
129 } 143 }
130 if (EX1_PL(p->ex1) == KERNEL_PL && 144 if (EX1_PL(p->ex1) == KERNEL_PL &&
131 in_kernel_text(p->pc) && 145 __kernel_text_address(p->pc) &&
132 in_kernel_stack(kbt, p->sp) && 146 in_kernel_stack(kbt, p->sp) &&
133 p->sp >= sp) { 147 p->sp >= sp) {
134 if (kbt->verbose) 148 if (kbt->verbose)
@@ -149,7 +163,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
149} 163}
150 164
151/* Is the pc pointing to a sigreturn trampoline? */ 165/* Is the pc pointing to a sigreturn trampoline? */
152static int is_sigreturn(VirtualAddress pc) 166static int is_sigreturn(unsigned long pc)
153{ 167{
154 return (pc == VDSO_BASE); 168 return (pc == VDSO_BASE);
155} 169}
@@ -207,11 +221,11 @@ static int KBacktraceIterator_next_item_inclusive(
207 for (;;) { 221 for (;;) {
208 do { 222 do {
209 if (!KBacktraceIterator_is_sigreturn(kbt)) 223 if (!KBacktraceIterator_is_sigreturn(kbt))
210 return 1; 224 return KBT_ONGOING;
211 } while (backtrace_next(&kbt->it)); 225 } while (backtrace_next(&kbt->it));
212 226
213 if (!KBacktraceIterator_restart(kbt)) 227 if (!KBacktraceIterator_restart(kbt))
214 return 0; 228 return KBT_DONE;
215 } 229 }
216} 230}
217 231
@@ -246,7 +260,7 @@ static void validate_stack(struct pt_regs *regs)
246void KBacktraceIterator_init(struct KBacktraceIterator *kbt, 260void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
247 struct task_struct *t, struct pt_regs *regs) 261 struct task_struct *t, struct pt_regs *regs)
248{ 262{
249 VirtualAddress pc, lr, sp, r52; 263 unsigned long pc, lr, sp, r52;
250 int is_current; 264 int is_current;
251 265
252 /* 266 /*
@@ -264,7 +278,7 @@ void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
264 kbt->pgtable = NULL; 278 kbt->pgtable = NULL;
265 kbt->verbose = 0; /* override in caller if desired */ 279 kbt->verbose = 0; /* override in caller if desired */
266 kbt->profile = 0; /* override in caller if desired */ 280 kbt->profile = 0; /* override in caller if desired */
267 kbt->end = 0; 281 kbt->end = KBT_ONGOING;
268 kbt->new_context = 0; 282 kbt->new_context = 0;
269 if (is_current) { 283 if (is_current) {
270 HV_PhysAddr pgdir_pa = hv_inquire_context().page_table; 284 HV_PhysAddr pgdir_pa = hv_inquire_context().page_table;
@@ -290,7 +304,7 @@ void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
290 if (regs == NULL) { 304 if (regs == NULL) {
291 if (is_current || t->state == TASK_RUNNING) { 305 if (is_current || t->state == TASK_RUNNING) {
292 /* Can't do this; we need registers */ 306 /* Can't do this; we need registers */
293 kbt->end = 1; 307 kbt->end = KBT_RUNNING;
294 return; 308 return;
295 } 309 }
296 pc = get_switch_to_pc(); 310 pc = get_switch_to_pc();
@@ -305,26 +319,29 @@ void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
305 } 319 }
306 320
307 backtrace_init(&kbt->it, read_memory_func, kbt, pc, lr, sp, r52); 321 backtrace_init(&kbt->it, read_memory_func, kbt, pc, lr, sp, r52);
308 kbt->end = !KBacktraceIterator_next_item_inclusive(kbt); 322 kbt->end = KBacktraceIterator_next_item_inclusive(kbt);
309} 323}
310EXPORT_SYMBOL(KBacktraceIterator_init); 324EXPORT_SYMBOL(KBacktraceIterator_init);
311 325
312int KBacktraceIterator_end(struct KBacktraceIterator *kbt) 326int KBacktraceIterator_end(struct KBacktraceIterator *kbt)
313{ 327{
314 return kbt->end; 328 return kbt->end != KBT_ONGOING;
315} 329}
316EXPORT_SYMBOL(KBacktraceIterator_end); 330EXPORT_SYMBOL(KBacktraceIterator_end);
317 331
318void KBacktraceIterator_next(struct KBacktraceIterator *kbt) 332void KBacktraceIterator_next(struct KBacktraceIterator *kbt)
319{ 333{
334 unsigned long old_pc = kbt->it.pc, old_sp = kbt->it.sp;
320 kbt->new_context = 0; 335 kbt->new_context = 0;
321 if (!backtrace_next(&kbt->it) && 336 if (!backtrace_next(&kbt->it) && !KBacktraceIterator_restart(kbt)) {
322 !KBacktraceIterator_restart(kbt)) { 337 kbt->end = KBT_DONE;
323 kbt->end = 1; 338 return;
324 return; 339 }
325 } 340 kbt->end = KBacktraceIterator_next_item_inclusive(kbt);
326 341 if (old_pc == kbt->it.pc && old_sp == kbt->it.sp) {
327 kbt->end = !KBacktraceIterator_next_item_inclusive(kbt); 342 /* Trapped in a loop; give up. */
343 kbt->end = KBT_LOOP;
344 }
328} 345}
329EXPORT_SYMBOL(KBacktraceIterator_next); 346EXPORT_SYMBOL(KBacktraceIterator_next);
330 347
@@ -387,6 +404,8 @@ void tile_show_stack(struct KBacktraceIterator *kbt, int headers)
387 break; 404 break;
388 } 405 }
389 } 406 }
407 if (kbt->end == KBT_LOOP)
408 pr_err("Stack dump stopped; next frame identical to this one\n");
390 if (headers) 409 if (headers)
391 pr_err("Stack dump complete\n"); 410 pr_err("Stack dump complete\n");
392} 411}
diff --git a/arch/tile/kernel/sys.c b/arch/tile/kernel/sys.c
index f0f87eab8c39..cb44ba7ccd2d 100644
--- a/arch/tile/kernel/sys.c
+++ b/arch/tile/kernel/sys.c
@@ -20,7 +20,6 @@
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23#include <linux/smp_lock.h>
24#include <linux/syscalls.h> 23#include <linux/syscalls.h>
25#include <linux/mman.h> 24#include <linux/mman.h>
26#include <linux/file.h> 25#include <linux/file.h>
@@ -57,13 +56,6 @@ ssize_t sys32_readahead(int fd, u32 offset_lo, u32 offset_hi, u32 count)
57 return sys_readahead(fd, ((loff_t)offset_hi << 32) | offset_lo, count); 56 return sys_readahead(fd, ((loff_t)offset_hi << 32) | offset_lo, count);
58} 57}
59 58
60long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi,
61 u32 len, int advice)
62{
63 return sys_fadvise64_64(fd, ((loff_t)offset_hi << 32) | offset_lo,
64 len, advice);
65}
66
67int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi, 59int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi,
68 u32 len_lo, u32 len_hi, int advice) 60 u32 len_lo, u32 len_hi, int advice)
69{ 61{
@@ -104,10 +96,17 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
104 96
105#ifndef __tilegx__ 97#ifndef __tilegx__
106/* See comments at the top of the file. */ 98/* See comments at the top of the file. */
107#define sys_fadvise64 sys32_fadvise64
108#define sys_fadvise64_64 sys32_fadvise64_64 99#define sys_fadvise64_64 sys32_fadvise64_64
109#define sys_readahead sys32_readahead 100#define sys_readahead sys32_readahead
110#define sys_sync_file_range sys_sync_file_range2 101#endif
102
103/* Call the trampolines to manage pt_regs where necessary. */
104#define sys_execve _sys_execve
105#define sys_sigaltstack _sys_sigaltstack
106#define sys_rt_sigreturn _sys_rt_sigreturn
107#define sys_clone _sys_clone
108#ifndef __tilegx__
109#define sys_cmpxchg_badaddr _sys_cmpxchg_badaddr
111#endif 110#endif
112 111
113/* 112/*
diff --git a/arch/tile/kernel/sysfs.c b/arch/tile/kernel/sysfs.c
new file mode 100644
index 000000000000..b671a86f4515
--- /dev/null
+++ b/arch/tile/kernel/sysfs.c
@@ -0,0 +1,185 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * /sys entry support.
15 */
16
17#include <linux/sysdev.h>
18#include <linux/cpu.h>
19#include <linux/slab.h>
20#include <linux/smp.h>
21#include <hv/hypervisor.h>
22
23/* Return a string queried from the hypervisor, truncated to page size. */
24static ssize_t get_hv_confstr(char *page, int query)
25{
26 ssize_t n = hv_confstr(query, (unsigned long)page, PAGE_SIZE - 1);
27 n = n < 0 ? 0 : min(n, (ssize_t)PAGE_SIZE - 1) - 1;
28 if (n)
29 page[n++] = '\n';
30 page[n] = '\0';
31 return n;
32}
33
34static ssize_t chip_width_show(struct sysdev_class *dev,
35 struct sysdev_class_attribute *attr,
36 char *page)
37{
38 return sprintf(page, "%u\n", smp_width);
39}
40static SYSDEV_CLASS_ATTR(chip_width, 0444, chip_width_show, NULL);
41
42static ssize_t chip_height_show(struct sysdev_class *dev,
43 struct sysdev_class_attribute *attr,
44 char *page)
45{
46 return sprintf(page, "%u\n", smp_height);
47}
48static SYSDEV_CLASS_ATTR(chip_height, 0444, chip_height_show, NULL);
49
50static ssize_t chip_serial_show(struct sysdev_class *dev,
51 struct sysdev_class_attribute *attr,
52 char *page)
53{
54 return get_hv_confstr(page, HV_CONFSTR_CHIP_SERIAL_NUM);
55}
56static SYSDEV_CLASS_ATTR(chip_serial, 0444, chip_serial_show, NULL);
57
58static ssize_t chip_revision_show(struct sysdev_class *dev,
59 struct sysdev_class_attribute *attr,
60 char *page)
61{
62 return get_hv_confstr(page, HV_CONFSTR_CHIP_REV);
63}
64static SYSDEV_CLASS_ATTR(chip_revision, 0444, chip_revision_show, NULL);
65
66
67static ssize_t type_show(struct sysdev_class *dev,
68 struct sysdev_class_attribute *attr,
69 char *page)
70{
71 return sprintf(page, "tilera\n");
72}
73static SYSDEV_CLASS_ATTR(type, 0444, type_show, NULL);
74
75#define HV_CONF_ATTR(name, conf) \
76 static ssize_t name ## _show(struct sysdev_class *dev, \
77 struct sysdev_class_attribute *attr, \
78 char *page) \
79 { \
80 return get_hv_confstr(page, conf); \
81 } \
82 static SYSDEV_CLASS_ATTR(name, 0444, name ## _show, NULL);
83
84HV_CONF_ATTR(version, HV_CONFSTR_HV_SW_VER)
85HV_CONF_ATTR(config_version, HV_CONFSTR_HV_CONFIG_VER)
86
87HV_CONF_ATTR(board_part, HV_CONFSTR_BOARD_PART_NUM)
88HV_CONF_ATTR(board_serial, HV_CONFSTR_BOARD_SERIAL_NUM)
89HV_CONF_ATTR(board_revision, HV_CONFSTR_BOARD_REV)
90HV_CONF_ATTR(board_description, HV_CONFSTR_BOARD_DESC)
91HV_CONF_ATTR(mezz_part, HV_CONFSTR_MEZZ_PART_NUM)
92HV_CONF_ATTR(mezz_serial, HV_CONFSTR_MEZZ_SERIAL_NUM)
93HV_CONF_ATTR(mezz_revision, HV_CONFSTR_MEZZ_REV)
94HV_CONF_ATTR(mezz_description, HV_CONFSTR_MEZZ_DESC)
95HV_CONF_ATTR(switch_control, HV_CONFSTR_SWITCH_CONTROL)
96
97static struct attribute *board_attrs[] = {
98 &attr_board_part.attr,
99 &attr_board_serial.attr,
100 &attr_board_revision.attr,
101 &attr_board_description.attr,
102 &attr_mezz_part.attr,
103 &attr_mezz_serial.attr,
104 &attr_mezz_revision.attr,
105 &attr_mezz_description.attr,
106 &attr_switch_control.attr,
107 NULL
108};
109
110static struct attribute_group board_attr_group = {
111 .name = "board",
112 .attrs = board_attrs,
113};
114
115
116static struct bin_attribute hvconfig_bin;
117
118static ssize_t
119hvconfig_bin_read(struct file *filp, struct kobject *kobj,
120 struct bin_attribute *bin_attr,
121 char *buf, loff_t off, size_t count)
122{
123 static size_t size;
124
125 /* Lazily learn the true size (minus the trailing NUL). */
126 if (size == 0)
127 size = hv_confstr(HV_CONFSTR_HV_CONFIG, 0, 0) - 1;
128
129 /* Check and adjust input parameters. */
130 if (off > size)
131 return -EINVAL;
132 if (count > size - off)
133 count = size - off;
134
135 if (count) {
136 /* Get a copy of the hvc and copy out the relevant portion. */
137 char *hvc;
138
139 size = off + count;
140 hvc = kmalloc(size, GFP_KERNEL);
141 if (hvc == NULL)
142 return -ENOMEM;
143 hv_confstr(HV_CONFSTR_HV_CONFIG, (unsigned long)hvc, size);
144 memcpy(buf, hvc + off, count);
145 kfree(hvc);
146 }
147
148 return count;
149}
150
151static int __init create_sysfs_entries(void)
152{
153 struct sysdev_class *cls = &cpu_sysdev_class;
154 int err = 0;
155
156#define create_cpu_attr(name) \
157 if (!err) \
158 err = sysfs_create_file(&cls->kset.kobj, &attr_##name.attr);
159 create_cpu_attr(chip_width);
160 create_cpu_attr(chip_height);
161 create_cpu_attr(chip_serial);
162 create_cpu_attr(chip_revision);
163
164#define create_hv_attr(name) \
165 if (!err) \
166 err = sysfs_create_file(hypervisor_kobj, &attr_##name.attr);
167 create_hv_attr(type);
168 create_hv_attr(version);
169 create_hv_attr(config_version);
170
171 if (!err)
172 err = sysfs_create_group(hypervisor_kobj, &board_attr_group);
173
174 if (!err) {
175 sysfs_bin_attr_init(&hvconfig_bin);
176 hvconfig_bin.attr.name = "hvconfig";
177 hvconfig_bin.attr.mode = S_IRUGO;
178 hvconfig_bin.read = hvconfig_bin_read;
179 hvconfig_bin.size = PAGE_SIZE;
180 err = sysfs_create_bin_file(hypervisor_kobj, &hvconfig_bin);
181 }
182
183 return err;
184}
185subsys_initcall(create_sysfs_entries);
diff --git a/arch/tile/kernel/tile-desc_32.c b/arch/tile/kernel/tile-desc_32.c
index 69af0e150f78..7e31a1285788 100644
--- a/arch/tile/kernel/tile-desc_32.c
+++ b/arch/tile/kernel/tile-desc_32.c
@@ -2413,12 +2413,13 @@ const struct tile_operand tile_operands[43] =
2413 2413
2414 2414
2415 2415
2416/* Given a set of bundle bits and the lookup FSM for a specific pipe, 2416/* Given a set of bundle bits and a specific pipe, returns which
2417 * returns which instruction the bundle contains in that pipe. 2417 * instruction the bundle contains in that pipe.
2418 */ 2418 */
2419static const struct tile_opcode * 2419const struct tile_opcode *
2420find_opcode(tile_bundle_bits bits, const unsigned short *table) 2420find_opcode(tile_bundle_bits bits, tile_pipeline pipe)
2421{ 2421{
2422 const unsigned short *table = tile_bundle_decoder_fsms[pipe];
2422 int index = 0; 2423 int index = 0;
2423 2424
2424 while (1) 2425 while (1)
@@ -2465,7 +2466,7 @@ parse_insn_tile(tile_bundle_bits bits,
2465 int i; 2466 int i;
2466 2467
2467 d = &decoded[num_instructions++]; 2468 d = &decoded[num_instructions++];
2468 opc = find_opcode (bits, tile_bundle_decoder_fsms[pipe]); 2469 opc = find_opcode (bits, (tile_pipeline)pipe);
2469 d->opcode = opc; 2470 d->opcode = opc;
2470 2471
2471 /* Decode each operand, sign extending, etc. as appropriate. */ 2472 /* Decode each operand, sign extending, etc. as appropriate. */
diff --git a/arch/tile/kernel/tile-desc_64.c b/arch/tile/kernel/tile-desc_64.c
new file mode 100644
index 000000000000..d57007bed77f
--- /dev/null
+++ b/arch/tile/kernel/tile-desc_64.c
@@ -0,0 +1,2200 @@
1/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
2#define BFD_RELOC(x) -1
3
4/* Special registers. */
5#define TREG_LR 55
6#define TREG_SN 56
7#define TREG_ZERO 63
8
9/* FIXME: Rename this. */
10#include <asm/opcode-tile_64.h>
11
12#include <linux/stddef.h>
13
14const struct tilegx_opcode tilegx_opcodes[334] =
15{
16 { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
17 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
18 },
19 { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
20 { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
21 },
22 { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
23 { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
24 },
25 { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
26 { { 6, 7 }, { 8, 9 }, { 10, 11 }, { 12, 13 }, { 0, } },
27 },
28 { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
29 { { 6, 0 }, { 8, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
30 },
31 { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
32 { { 6, 4 }, { 8, 5 }, { 0, }, { 0, }, { 0, } },
33 },
34 { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
35 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
36 },
37 { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
38 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
39 },
40 { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
41 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
42 },
43 { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
44 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
45 },
46 { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
47 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
48 },
49 { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
50 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
51 },
52 { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
53 { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
54 },
55 { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
56 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
57 },
58 { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
59 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
60 },
61 { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
62 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
63 },
64 { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
65 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
66 },
67 { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
68 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
69 },
70 { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
71 { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
72 },
73 { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
74 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
75 },
76 { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
77 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
78 },
79 { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
80 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
81 },
82 { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
83 { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
84 },
85 { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
86 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
87 },
88 { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
89 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
90 },
91 { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
92 { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
93 },
94 { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
95 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
96 },
97 { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
98 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
99 },
100 { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
101 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
102 },
103 { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
104 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
105 },
106 { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
107 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
108 },
109 { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
110 { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
111 },
112 { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
113 { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
114 },
115 { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
116 { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
117 },
118 { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
119 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
120 },
121 { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
122 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
123 },
124 { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
125 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
126 },
127 { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
128 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
129 },
130 { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
131 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
132 },
133 { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
134 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
135 },
136 { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
137 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
138 },
139 { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
140 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
141 },
142 { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
143 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
144 },
145 { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
146 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
147 },
148 { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
149 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
150 },
151 { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
152 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
153 },
154 { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
155 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
156 },
157 { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
158 { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
159 },
160 { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
161 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
162 },
163 { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
164 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
165 },
166 { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
167 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
168 },
169 { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
170 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
171 },
172 { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
173 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
174 },
175 { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
176 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
177 },
178 { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
179 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
180 },
181 { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
182 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
183 },
184 { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
185 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
186 },
187 { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
188 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
189 },
190 { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
191 { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
192 },
193 { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
194 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
195 },
196 { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
197 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
198 },
199 { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
200 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
201 },
202 { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
203 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
204 },
205 { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
206 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
207 },
208 { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
209 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
210 },
211 { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
212 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
213 },
214 { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
215 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
216 },
217 { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
218 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
219 },
220 { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
221 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
222 },
223 { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
224 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
225 },
226 { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
227 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
228 },
229 { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
230 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
231 },
232 { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
233 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
234 },
235 { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
236 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
237 },
238 { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
239 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
240 },
241 { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
242 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
243 },
244 { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
245 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
246 },
247 { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
248 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
249 },
250 { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
251 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
252 },
253 { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
254 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
255 },
256 { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
257 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
258 },
259 { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
260 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
261 },
262 { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
263 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
264 },
265 { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
266 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
267 },
268 { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
269 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
270 },
271 { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
272 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
273 },
274 { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
275 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
276 },
277 { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
278 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
279 },
280 { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
281 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
282 },
283 { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
284 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
285 },
286 { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
287 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
288 },
289 { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
290 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
291 },
292 { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
293 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
294 },
295 { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
296 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
297 },
298 { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
299 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
300 },
301 { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
302 { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
303 },
304 { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
305 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
306 },
307 { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
308 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
309 },
310 { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
311 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
312 },
313 { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
314 { { }, { }, { }, { }, { 0, } },
315 },
316 { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
317 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
318 },
319 { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
320 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
321 },
322 { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
323 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
324 },
325 { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
326 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
327 },
328 { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
329 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
330 },
331 { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
332 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
333 },
334 { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
335 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
336 },
337 { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
338 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
339 },
340 { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
341 { { 0, }, { }, { 0, }, { }, { 0, } },
342 },
343 { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
344 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
345 },
346 { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
347 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
348 },
349 { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
350 { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
351 },
352 { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
353 { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
354 },
355 { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
356 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
357 },
358 { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
359 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
360 },
361 { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
362 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
363 },
364 { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
365 { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
366 },
367 { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
368 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
369 },
370 { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
371 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
372 },
373 { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
374 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
375 },
376 { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
377 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
378 },
379 { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
380 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
381 },
382 { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
383 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
384 },
385 { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
386 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
387 },
388 { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
389 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
390 },
391 { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
392 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
393 },
394 { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
395 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
396 },
397 { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
398 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
399 },
400 { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
401 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
402 },
403 { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
404 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
405 },
406 { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
407 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
408 },
409 { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
410 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
411 },
412 { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
413 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
414 },
415 { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
416 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
417 },
418 { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
419 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
420 },
421 { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
422 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
423 },
424 { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
425 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
426 },
427 { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
428 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
429 },
430 { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
431 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
432 },
433 { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
434 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
435 },
436 { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
437 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
438 },
439 { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
440 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
441 },
442 { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
443 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
444 },
445 { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
446 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
447 },
448 { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
449 { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
450 },
451 { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
452 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
453 },
454 { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
455 { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
456 },
457 { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
458 { { 0, }, { 8 }, { 0, }, { 12 }, { 0, } },
459 },
460 { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
461 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
462 },
463 { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
464 { { 0, }, { 8, 27 }, { 0, }, { 0, }, { 0, } },
465 },
466 { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
467 { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
468 },
469 { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
470 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
471 },
472 { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
473 { { 0, }, { 28, 9 }, { 0, }, { 0, }, { 0, } },
474 },
475 { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
476 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
477 },
478 { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
479 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
480 },
481 { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
482 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
483 },
484 { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
485 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
486 },
487 { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
488 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
489 },
490 { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
491 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
492 },
493 { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
494 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
495 },
496 { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
497 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
498 },
499 { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
500 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
501 },
502 { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
503 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
504 },
505 { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
506 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
507 },
508 { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
509 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
510 },
511 { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
512 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
513 },
514 { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
515 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
516 },
517 { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
518 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
519 },
520 { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
521 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
522 },
523 { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
524 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
525 },
526 { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
527 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
528 },
529 { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
530 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
531 },
532 { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
533 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
534 },
535 { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
536 { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
537 },
538 { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
539 { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
540 },
541 { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
542 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
543 },
544 { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
545 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
546 },
547 { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
548 { { }, { }, { }, { }, { 0, } },
549 },
550 { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
551 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
552 },
553 { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
554 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
555 },
556 { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
557 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
558 },
559 { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
560 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
561 },
562 { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
563 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
564 },
565 { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
566 { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
567 },
568 { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
569 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
570 },
571 { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
572 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
573 },
574 { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
575 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
576 },
577 { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
578 { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
579 },
580 { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
581 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
582 },
583 { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
584 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
585 },
586 { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
587 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
588 },
589 { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
590 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
591 },
592 { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
593 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
594 },
595 { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
596 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
597 },
598 { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
599 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
600 },
601 { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
602 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
603 },
604 { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
605 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
606 },
607 { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
608 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
609 },
610 { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
611 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
612 },
613 { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
614 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
615 },
616 { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
617 { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
618 },
619 { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
620 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
621 },
622 { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
623 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
624 },
625 { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
626 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
627 },
628 { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
629 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
630 },
631 { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
632 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
633 },
634 { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
635 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
636 },
637 { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
638 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
639 },
640 { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
641 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
642 },
643 { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
644 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
645 },
646 { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
647 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
648 },
649 { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
650 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
651 },
652 { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
653 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
654 },
655 { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
656 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
657 },
658 { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
659 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
660 },
661 { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
662 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
663 },
664 { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
665 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
666 },
667 { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
668 { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
669 },
670 { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
671 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
672 },
673 { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
674 { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
675 },
676 { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
677 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
678 },
679 { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
680 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
681 },
682 { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
683 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
684 },
685 { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
686 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
687 },
688 { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
689 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
690 },
691 { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
692 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
693 },
694 { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
695 { { 0, }, { }, { 0, }, { 0, }, { 0, } },
696 },
697 { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
698 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
699 },
700 { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
701 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
702 },
703 { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
704 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
705 },
706 { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
707 { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
708 },
709 { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
710 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
711 },
712 { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
713 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
714 },
715 { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
716 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
717 },
718 { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
719 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
720 },
721 { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
722 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
723 },
724 { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
725 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
726 },
727 { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
728 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
729 },
730 { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
731 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
732 },
733 { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
734 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
735 },
736 { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
737 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
738 },
739 { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
740 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
741 },
742 { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
743 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
744 },
745 { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
746 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
747 },
748 { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
749 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
750 },
751 { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
752 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
753 },
754 { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
755 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
756 },
757 { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
758 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
759 },
760 { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
761 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
762 },
763 { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
764 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
765 },
766 { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
767 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
768 },
769 { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
770 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
771 },
772 { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
773 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
774 },
775 { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
776 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
777 },
778 { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
779 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
780 },
781 { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
782 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
783 },
784 { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
785 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
786 },
787 { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
788 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
789 },
790 { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
791 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
792 },
793 { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
794 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
795 },
796 { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
797 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
798 },
799 { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
800 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
801 },
802 { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
803 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
804 },
805 { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
806 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
807 },
808 { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
809 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
810 },
811 { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
812 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
813 },
814 { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
815 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
816 },
817 { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
818 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
819 },
820 { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
821 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
822 },
823 { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
824 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
825 },
826 { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
827 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
828 },
829 { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
830 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
831 },
832 { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
833 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
834 },
835 { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
836 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
837 },
838 { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
839 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
840 },
841 { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
842 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
843 },
844 { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
845 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
846 },
847 { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
848 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
849 },
850 { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
851 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
852 },
853 { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
854 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
855 },
856 { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
857 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
858 },
859 { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
860 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
861 },
862 { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
863 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
864 },
865 { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
866 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
867 },
868 { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
869 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
870 },
871 { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
872 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
873 },
874 { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
875 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
876 },
877 { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
878 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
879 },
880 { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
881 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
882 },
883 { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
884 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
885 },
886 { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
887 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
888 },
889 { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
890 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
891 },
892 { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
893 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
894 },
895 { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
896 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
897 },
898 { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
899 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
900 },
901 { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
902 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
903 },
904 { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
905 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
906 },
907 { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
908 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
909 },
910 { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
911 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
912 },
913 { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
914 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
915 },
916 { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
917 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
918 },
919 { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
920 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
921 },
922 { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
923 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
924 },
925 { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
926 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
927 },
928 { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
929 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
930 },
931 { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
932 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
933 },
934 { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
935 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
936 },
937 { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
938 { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
939 },
940 { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
941 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
942 },
943 { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
944 { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
945 },
946 { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
947 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
948 },
949 { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
950 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
951 },
952 { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
953 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
954 },
955 { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
956 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
957 },
958 { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
959 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
960 },
961 { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
962 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
963 },
964 { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
965 { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
966 },
967 { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
968 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
969 },
970 { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
971 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
972 },
973 { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
974 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
975 },
976 { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
977 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
978 },
979 { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
980 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
981 },
982 { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
983 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
984 },
985 { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
986 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
987 },
988 { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
989 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
990 },
991 { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
992 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
993 },
994 { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
995 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
996 },
997 { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
998 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
999 },
1000 { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
1001 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
1002 },
1003 { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
1004 { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
1005 },
1006 { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
1007 { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
1008 },
1009 { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
1010 { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
1011 },
1012 { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
1013 { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
1014 },
1015 { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
1016 }
1017};
1018#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
1019#define CHILD(array_index) (TILEGX_OPC_NONE + (array_index))
1020
1021static const unsigned short decode_X0_fsm[936] =
1022{
1023 BITFIELD(22, 9) /* index 0 */,
1024 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1025 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1026 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1027 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1028 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1029 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1030 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1031 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1032 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1033 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1034 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1035 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1036 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1037 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1038 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1039 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1040 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1041 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1042 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1043 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1044 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1045 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1046 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1047 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1048 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1049 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1050 CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
1051 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1052 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1053 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1054 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1055 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1056 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1057 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1058 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1059 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1060 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1061 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1062 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1063 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1064 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1065 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1066 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
1067 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1068 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1069 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1070 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS,
1071 TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU,
1072 TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS,
1073 TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM,
1074 TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE,
1075 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1076 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1077 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1078 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1079 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1080 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1081 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1082 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578),
1083 CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE,
1084 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1085 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1086 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1087 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1088 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1089 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1090 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1091 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1092 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1093 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1094 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1095 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1096 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1097 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1098 TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671),
1099 CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865),
1100 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1101 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1102 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1103 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1104 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1105 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1106 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1107 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1108 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1109 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1110 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1111 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1112 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1113 TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1114 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1115 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1116 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1117 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1118 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1119 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1120 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1121 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1122 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1123 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1124 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1125 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1126 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1127 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1128 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1129 TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1130 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1131 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1132 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1133 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1134 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1135 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1136 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1137 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1138 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1139 CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
1140 BITFIELD(6, 2) /* index 513 */,
1141 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
1142 BITFIELD(8, 2) /* index 518 */,
1143 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
1144 BITFIELD(10, 2) /* index 523 */,
1145 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
1146 BITFIELD(20, 2) /* index 528 */,
1147 TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
1148 BITFIELD(6, 2) /* index 533 */,
1149 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
1150 BITFIELD(8, 2) /* index 538 */,
1151 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
1152 BITFIELD(10, 2) /* index 543 */,
1153 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1154 BITFIELD(0, 2) /* index 548 */,
1155 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
1156 BITFIELD(2, 2) /* index 553 */,
1157 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
1158 BITFIELD(4, 2) /* index 558 */,
1159 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
1160 BITFIELD(6, 2) /* index 563 */,
1161 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
1162 BITFIELD(8, 2) /* index 568 */,
1163 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
1164 BITFIELD(10, 2) /* index 573 */,
1165 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1166 BITFIELD(20, 2) /* index 578 */,
1167 TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI,
1168 BITFIELD(20, 2) /* index 583 */,
1169 TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI,
1170 TILEGX_OPC_V1CMPLTUI,
1171 BITFIELD(20, 2) /* index 588 */,
1172 TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI,
1173 TILEGX_OPC_V2CMPEQI,
1174 BITFIELD(20, 2) /* index 593 */,
1175 TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI,
1176 TILEGX_OPC_V2MINSI,
1177 BITFIELD(20, 2) /* index 598 */,
1178 TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1179 BITFIELD(18, 4) /* index 603 */,
1180 TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
1181 TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ,
1182 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1183 TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR,
1184 BITFIELD(18, 4) /* index 620 */,
1185 TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL,
1186 TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2,
1187 TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN,
1188 TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS,
1189 TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1,
1190 TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS,
1191 BITFIELD(18, 4) /* index 637 */,
1192 TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN,
1193 TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2,
1194 TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2,
1195 TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX,
1196 TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS,
1197 TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS,
1198 BITFIELD(18, 4) /* index 654 */,
1199 TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU,
1200 TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS,
1201 TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU,
1202 TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU,
1203 TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU,
1204 TILEGX_OPC_MZ,
1205 BITFIELD(18, 4) /* index 671 */,
1206 TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
1207 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
1208 TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
1209 TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES,
1210 TILEGX_OPC_SUBXSC,
1211 BITFIELD(12, 2) /* index 688 */,
1212 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693),
1213 BITFIELD(14, 2) /* index 693 */,
1214 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698),
1215 BITFIELD(16, 2) /* index 698 */,
1216 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1217 BITFIELD(18, 4) /* index 703 */,
1218 TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC,
1219 TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU,
1220 TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
1221 TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
1222 TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA,
1223 BITFIELD(12, 4) /* index 720 */,
1224 TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757),
1225 CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787),
1226 CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1227 BITFIELD(16, 2) /* index 737 */,
1228 TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1229 BITFIELD(16, 2) /* index 742 */,
1230 TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1231 BITFIELD(16, 2) /* index 747 */,
1232 TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1233 BITFIELD(16, 2) /* index 752 */,
1234 TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1235 BITFIELD(16, 2) /* index 757 */,
1236 TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1237 BITFIELD(16, 2) /* index 762 */,
1238 TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1239 BITFIELD(16, 2) /* index 767 */,
1240 TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1241 BITFIELD(16, 2) /* index 772 */,
1242 TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1243 BITFIELD(16, 2) /* index 777 */,
1244 TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1245 BITFIELD(16, 2) /* index 782 */,
1246 TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1247 BITFIELD(16, 2) /* index 787 */,
1248 TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1249 BITFIELD(16, 2) /* index 792 */,
1250 TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1251 BITFIELD(18, 4) /* index 797 */,
1252 TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP,
1253 TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU,
1254 TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS,
1255 TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU,
1256 TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS,
1257 BITFIELD(18, 4) /* index 814 */,
1258 TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC,
1259 TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS,
1260 TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU,
1261 TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE,
1262 TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H,
1263 BITFIELD(18, 4) /* index 831 */,
1264 TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ,
1265 TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ,
1266 TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
1267 TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS,
1268 TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC,
1269 BITFIELD(18, 4) /* index 848 */,
1270 TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC,
1271 TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
1272 TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
1273 TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
1274 TILEGX_OPC_V4SUB,
1275 BITFIELD(18, 3) /* index 865 */,
1276 CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE,
1277 TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1278 BITFIELD(21, 1) /* index 874 */,
1279 TILEGX_OPC_XOR, TILEGX_OPC_NONE,
1280 BITFIELD(21, 1) /* index 877 */,
1281 TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE,
1282 BITFIELD(21, 1) /* index 880 */,
1283 TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE,
1284 BITFIELD(21, 1) /* index 883 */,
1285 TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE,
1286 BITFIELD(21, 1) /* index 886 */,
1287 TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE,
1288 BITFIELD(18, 4) /* index 889 */,
1289 TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
1290 TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
1291 TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
1292 TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1293 TILEGX_OPC_NONE,
1294 BITFIELD(0, 2) /* index 906 */,
1295 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1296 CHILD(911),
1297 BITFIELD(2, 2) /* index 911 */,
1298 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1299 CHILD(916),
1300 BITFIELD(4, 2) /* index 916 */,
1301 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1302 CHILD(921),
1303 BITFIELD(6, 2) /* index 921 */,
1304 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1305 CHILD(926),
1306 BITFIELD(8, 2) /* index 926 */,
1307 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1308 CHILD(931),
1309 BITFIELD(10, 2) /* index 931 */,
1310 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1311 TILEGX_OPC_INFOL,
1312};
1313
1314static const unsigned short decode_X1_fsm[1206] =
1315{
1316 BITFIELD(53, 9) /* index 0 */,
1317 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1318 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1319 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1320 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1321 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1322 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1323 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1324 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1325 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1326 CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
1327 CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
1328 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1329 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1330 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1331 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1332 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1333 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1334 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1335 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1336 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1337 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1338 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1339 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1340 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1341 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1342 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
1343 TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
1344 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1345 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1346 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1347 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1348 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1349 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1350 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1351 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT,
1352 TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT,
1353 TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT,
1354 TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT,
1355 TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
1356 TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
1357 TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
1358 TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
1359 TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
1360 CHILD(598), CHILD(663), CHILD(683), CHILD(688), CHILD(693), CHILD(698),
1361 CHILD(703), CHILD(708), CHILD(713), CHILD(718), TILEGX_OPC_NONE,
1362 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1363 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1364 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1365 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1366 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1367 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1368 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1369 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1370 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1371 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1372 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1373 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1374 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL,
1375 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1376 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1377 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1378 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1379 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1380 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1381 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
1382 TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J,
1383 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1384 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1385 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1386 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1387 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1388 TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
1389 CHILD(723), CHILD(740), CHILD(772), CHILD(789), CHILD(1108), CHILD(1125),
1390 CHILD(1142), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1391 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1392 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1393 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1394 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1395 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1396 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1397 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1398 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1399 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1400 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1401 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1402 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1403 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1404 TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1159), TILEGX_OPC_NONE,
1405 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1406 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1407 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1408 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1409 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1410 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1411 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1412 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1413 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1414 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1415 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1416 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1417 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1418 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1419 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1420 TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1176), CHILD(1176), CHILD(1176),
1421 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1422 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1423 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1424 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1425 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1426 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1427 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1428 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1429 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1430 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1431 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1432 CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
1433 CHILD(1176),
1434 BITFIELD(37, 2) /* index 513 */,
1435 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
1436 BITFIELD(39, 2) /* index 518 */,
1437 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
1438 BITFIELD(41, 2) /* index 523 */,
1439 TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
1440 BITFIELD(51, 2) /* index 528 */,
1441 TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
1442 BITFIELD(37, 2) /* index 533 */,
1443 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
1444 BITFIELD(39, 2) /* index 538 */,
1445 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
1446 BITFIELD(41, 2) /* index 543 */,
1447 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1448 BITFIELD(31, 2) /* index 548 */,
1449 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
1450 BITFIELD(33, 2) /* index 553 */,
1451 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
1452 BITFIELD(35, 2) /* index 558 */,
1453 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
1454 BITFIELD(37, 2) /* index 563 */,
1455 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
1456 BITFIELD(39, 2) /* index 568 */,
1457 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
1458 BITFIELD(41, 2) /* index 573 */,
1459 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1460 BITFIELD(51, 2) /* index 578 */,
1461 TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583),
1462 BITFIELD(31, 2) /* index 583 */,
1463 TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588),
1464 BITFIELD(33, 2) /* index 588 */,
1465 TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593),
1466 BITFIELD(35, 2) /* index 593 */,
1467 TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD,
1468 TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
1469 BITFIELD(51, 2) /* index 598 */,
1470 CHILD(603), CHILD(618), CHILD(633), CHILD(648),
1471 BITFIELD(31, 2) /* index 603 */,
1472 TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608),
1473 BITFIELD(33, 2) /* index 608 */,
1474 TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613),
1475 BITFIELD(35, 2) /* index 613 */,
1476 TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD,
1477 TILEGX_OPC_PREFETCH_ADD_L1,
1478 BITFIELD(31, 2) /* index 618 */,
1479 TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623),
1480 BITFIELD(33, 2) /* index 623 */,
1481 TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628),
1482 BITFIELD(35, 2) /* index 628 */,
1483 TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD,
1484 TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
1485 BITFIELD(31, 2) /* index 633 */,
1486 TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638),
1487 BITFIELD(33, 2) /* index 638 */,
1488 TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
1489 BITFIELD(35, 2) /* index 643 */,
1490 TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
1491 TILEGX_OPC_PREFETCH_ADD_L2,
1492 BITFIELD(31, 2) /* index 648 */,
1493 TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(653),
1494 BITFIELD(33, 2) /* index 653 */,
1495 TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(658),
1496 BITFIELD(35, 2) /* index 658 */,
1497 TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
1498 TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
1499 BITFIELD(51, 2) /* index 663 */,
1500 CHILD(668), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
1501 TILEGX_OPC_LDNT2S_ADD,
1502 BITFIELD(31, 2) /* index 668 */,
1503 TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(673),
1504 BITFIELD(33, 2) /* index 673 */,
1505 TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(678),
1506 BITFIELD(35, 2) /* index 678 */,
1507 TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
1508 TILEGX_OPC_PREFETCH_ADD_L3,
1509 BITFIELD(51, 2) /* index 683 */,
1510 TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
1511 TILEGX_OPC_LDNT_ADD,
1512 BITFIELD(51, 2) /* index 688 */,
1513 TILEGX_OPC_LD_ADD, TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
1514 BITFIELD(51, 2) /* index 693 */,
1515 TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
1516 BITFIELD(51, 2) /* index 698 */,
1517 TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
1518 TILEGX_OPC_STNT_ADD,
1519 BITFIELD(51, 2) /* index 703 */,
1520 TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
1521 TILEGX_OPC_V1CMPLTSI,
1522 BITFIELD(51, 2) /* index 708 */,
1523 TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
1524 TILEGX_OPC_V2ADDI,
1525 BITFIELD(51, 2) /* index 713 */,
1526 TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
1527 TILEGX_OPC_V2MAXSI,
1528 BITFIELD(51, 2) /* index 718 */,
1529 TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1530 BITFIELD(49, 4) /* index 723 */,
1531 TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
1532 TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
1533 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1534 TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
1535 TILEGX_OPC_DBLALIGN6,
1536 BITFIELD(49, 4) /* index 740 */,
1537 TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
1538 TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
1539 TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
1540 TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
1541 CHILD(757), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
1542 BITFIELD(43, 2) /* index 757 */,
1543 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(762),
1544 BITFIELD(45, 2) /* index 762 */,
1545 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(767),
1546 BITFIELD(47, 2) /* index 767 */,
1547 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1548 BITFIELD(49, 4) /* index 772 */,
1549 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
1550 TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
1551 TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
1552 TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
1553 TILEGX_OPC_STNT4,
1554 BITFIELD(46, 7) /* index 789 */,
1555 TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
1556 TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
1557 TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
1558 TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
1559 TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
1560 TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
1561 TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
1562 TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
1563 TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
1564 TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(918), CHILD(927),
1565 CHILD(1006), CHILD(1090), CHILD(1099), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1566 TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
1567 TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
1568 TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
1569 TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
1570 TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
1571 TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
1572 TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
1573 TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
1574 TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
1575 TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
1576 TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
1577 TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
1578 TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
1579 TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
1580 TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
1581 TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
1582 TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
1583 TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
1584 TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
1585 TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
1586 TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
1587 TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
1588 TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
1589 TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
1590 TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
1591 TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
1592 BITFIELD(43, 3) /* index 918 */,
1593 TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
1594 TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
1595 BITFIELD(43, 3) /* index 927 */,
1596 CHILD(936), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
1597 TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(991),
1598 BITFIELD(31, 2) /* index 936 */,
1599 CHILD(941), CHILD(966), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1600 BITFIELD(33, 2) /* index 941 */,
1601 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(946),
1602 BITFIELD(35, 2) /* index 946 */,
1603 TILEGX_OPC_ILL, CHILD(951), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1604 BITFIELD(37, 2) /* index 951 */,
1605 TILEGX_OPC_ILL, CHILD(956), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1606 BITFIELD(39, 2) /* index 956 */,
1607 TILEGX_OPC_ILL, CHILD(961), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1608 BITFIELD(41, 2) /* index 961 */,
1609 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
1610 BITFIELD(33, 2) /* index 966 */,
1611 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(971),
1612 BITFIELD(35, 2) /* index 971 */,
1613 TILEGX_OPC_ILL, CHILD(976), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1614 BITFIELD(37, 2) /* index 976 */,
1615 TILEGX_OPC_ILL, CHILD(981), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1616 BITFIELD(39, 2) /* index 981 */,
1617 TILEGX_OPC_ILL, CHILD(986), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
1618 BITFIELD(41, 2) /* index 986 */,
1619 TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
1620 BITFIELD(31, 2) /* index 991 */,
1621 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(996),
1622 BITFIELD(33, 2) /* index 996 */,
1623 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1001),
1624 BITFIELD(35, 2) /* index 1001 */,
1625 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
1626 TILEGX_OPC_PREFETCH_L1_FAULT,
1627 BITFIELD(43, 3) /* index 1006 */,
1628 CHILD(1015), CHILD(1030), CHILD(1045), CHILD(1060), CHILD(1075),
1629 TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
1630 BITFIELD(31, 2) /* index 1015 */,
1631 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1020),
1632 BITFIELD(33, 2) /* index 1020 */,
1633 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1025),
1634 BITFIELD(35, 2) /* index 1025 */,
1635 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
1636 BITFIELD(31, 2) /* index 1030 */,
1637 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1035),
1638 BITFIELD(33, 2) /* index 1035 */,
1639 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1040),
1640 BITFIELD(35, 2) /* index 1040 */,
1641 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
1642 TILEGX_OPC_PREFETCH_L2_FAULT,
1643 BITFIELD(31, 2) /* index 1045 */,
1644 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1050),
1645 BITFIELD(33, 2) /* index 1050 */,
1646 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1055),
1647 BITFIELD(35, 2) /* index 1055 */,
1648 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
1649 BITFIELD(31, 2) /* index 1060 */,
1650 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1065),
1651 BITFIELD(33, 2) /* index 1065 */,
1652 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1070),
1653 BITFIELD(35, 2) /* index 1070 */,
1654 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
1655 TILEGX_OPC_PREFETCH_L3_FAULT,
1656 BITFIELD(31, 2) /* index 1075 */,
1657 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1080),
1658 BITFIELD(33, 2) /* index 1080 */,
1659 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1085),
1660 BITFIELD(35, 2) /* index 1085 */,
1661 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
1662 BITFIELD(43, 3) /* index 1090 */,
1663 TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
1664 TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
1665 BITFIELD(43, 3) /* index 1099 */,
1666 TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
1667 TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
1668 BITFIELD(49, 4) /* index 1108 */,
1669 TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
1670 TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
1671 TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
1672 TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
1673 TILEGX_OPC_V2CMPLTU,
1674 BITFIELD(49, 4) /* index 1125 */,
1675 TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
1676 TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
1677 TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
1678 TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
1679 TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
1680 BITFIELD(49, 4) /* index 1142 */,
1681 TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
1682 TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
1683 TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
1684 TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1685 TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1686 BITFIELD(49, 4) /* index 1159 */,
1687 TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
1688 TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
1689 TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
1690 TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1691 TILEGX_OPC_NONE,
1692 BITFIELD(31, 2) /* index 1176 */,
1693 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1694 CHILD(1181),
1695 BITFIELD(33, 2) /* index 1181 */,
1696 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1697 CHILD(1186),
1698 BITFIELD(35, 2) /* index 1186 */,
1699 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1700 CHILD(1191),
1701 BITFIELD(37, 2) /* index 1191 */,
1702 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1703 CHILD(1196),
1704 BITFIELD(39, 2) /* index 1196 */,
1705 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1706 CHILD(1201),
1707 BITFIELD(41, 2) /* index 1201 */,
1708 TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
1709 TILEGX_OPC_INFOL,
1710};
1711
1712static const unsigned short decode_Y0_fsm[178] =
1713{
1714 BITFIELD(27, 4) /* index 0 */,
1715 CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
1716 TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123),
1717 CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168),
1718 CHILD(173),
1719 BITFIELD(6, 2) /* index 17 */,
1720 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
1721 BITFIELD(8, 2) /* index 22 */,
1722 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
1723 BITFIELD(10, 2) /* index 27 */,
1724 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1725 BITFIELD(0, 2) /* index 32 */,
1726 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
1727 BITFIELD(2, 2) /* index 37 */,
1728 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
1729 BITFIELD(4, 2) /* index 42 */,
1730 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
1731 BITFIELD(6, 2) /* index 47 */,
1732 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
1733 BITFIELD(8, 2) /* index 52 */,
1734 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
1735 BITFIELD(10, 2) /* index 57 */,
1736 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1737 BITFIELD(18, 2) /* index 62 */,
1738 TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
1739 BITFIELD(15, 5) /* index 67 */,
1740 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
1741 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
1742 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD,
1743 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
1744 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
1745 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
1746 TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
1747 TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100),
1748 CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1749 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1750 BITFIELD(12, 3) /* index 100 */,
1751 TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP,
1752 TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT,
1753 TILEGX_OPC_REVBITS,
1754 BITFIELD(12, 3) /* index 109 */,
1755 TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1,
1756 TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1757 TILEGX_OPC_NONE,
1758 BITFIELD(18, 2) /* index 118 */,
1759 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1760 BITFIELD(18, 2) /* index 123 */,
1761 TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX,
1762 BITFIELD(18, 2) /* index 128 */,
1763 TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
1764 BITFIELD(18, 2) /* index 133 */,
1765 TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR,
1766 BITFIELD(12, 2) /* index 138 */,
1767 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143),
1768 BITFIELD(14, 2) /* index 143 */,
1769 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148),
1770 BITFIELD(16, 2) /* index 148 */,
1771 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1772 BITFIELD(18, 2) /* index 153 */,
1773 TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
1774 BITFIELD(18, 2) /* index 158 */,
1775 TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
1776 TILEGX_OPC_SHL3ADDX,
1777 BITFIELD(18, 2) /* index 163 */,
1778 TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS,
1779 TILEGX_OPC_MUL_LU_LU,
1780 BITFIELD(18, 2) /* index 168 */,
1781 TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS,
1782 TILEGX_OPC_MULA_LU_LU,
1783 BITFIELD(18, 2) /* index 173 */,
1784 TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
1785};
1786
1787static const unsigned short decode_Y1_fsm[167] =
1788{
1789 BITFIELD(58, 4) /* index 0 */,
1790 TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
1791 TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122),
1792 CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE,
1793 BITFIELD(37, 2) /* index 17 */,
1794 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
1795 BITFIELD(39, 2) /* index 22 */,
1796 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
1797 BITFIELD(41, 2) /* index 27 */,
1798 TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
1799 BITFIELD(31, 2) /* index 32 */,
1800 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
1801 BITFIELD(33, 2) /* index 37 */,
1802 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
1803 BITFIELD(35, 2) /* index 42 */,
1804 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
1805 BITFIELD(37, 2) /* index 47 */,
1806 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
1807 BITFIELD(39, 2) /* index 52 */,
1808 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
1809 BITFIELD(41, 2) /* index 57 */,
1810 TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
1811 BITFIELD(49, 2) /* index 62 */,
1812 TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
1813 BITFIELD(47, 4) /* index 67 */,
1814 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
1815 TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
1816 TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD,
1817 TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84),
1818 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
1819 BITFIELD(43, 3) /* index 84 */,
1820 CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108),
1821 CHILD(111), CHILD(114),
1822 BITFIELD(46, 1) /* index 93 */,
1823 TILEGX_OPC_NONE, TILEGX_OPC_FNOP,
1824 BITFIELD(46, 1) /* index 96 */,
1825 TILEGX_OPC_NONE, TILEGX_OPC_ILL,
1826 BITFIELD(46, 1) /* index 99 */,
1827 TILEGX_OPC_NONE, TILEGX_OPC_JALRP,
1828 BITFIELD(46, 1) /* index 102 */,
1829 TILEGX_OPC_NONE, TILEGX_OPC_JALR,
1830 BITFIELD(46, 1) /* index 105 */,
1831 TILEGX_OPC_NONE, TILEGX_OPC_JRP,
1832 BITFIELD(46, 1) /* index 108 */,
1833 TILEGX_OPC_NONE, TILEGX_OPC_JR,
1834 BITFIELD(46, 1) /* index 111 */,
1835 TILEGX_OPC_NONE, TILEGX_OPC_LNK,
1836 BITFIELD(46, 1) /* index 114 */,
1837 TILEGX_OPC_NONE, TILEGX_OPC_NOP,
1838 BITFIELD(49, 2) /* index 117 */,
1839 TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
1840 BITFIELD(49, 2) /* index 122 */,
1841 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE,
1842 BITFIELD(49, 2) /* index 127 */,
1843 TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
1844 BITFIELD(49, 2) /* index 132 */,
1845 TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR,
1846 BITFIELD(43, 2) /* index 137 */,
1847 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142),
1848 BITFIELD(45, 2) /* index 142 */,
1849 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147),
1850 BITFIELD(47, 2) /* index 147 */,
1851 TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
1852 BITFIELD(49, 2) /* index 152 */,
1853 TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
1854 BITFIELD(49, 2) /* index 157 */,
1855 TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
1856 TILEGX_OPC_SHL3ADDX,
1857 BITFIELD(49, 2) /* index 162 */,
1858 TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
1859};
1860
1861static const unsigned short decode_Y2_fsm[118] =
1862{
1863 BITFIELD(62, 2) /* index 0 */,
1864 TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109),
1865 BITFIELD(55, 3) /* index 5 */,
1866 CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40),
1867 CHILD(43),
1868 BITFIELD(26, 1) /* index 14 */,
1869 TILEGX_OPC_LD1S, TILEGX_OPC_LD1U,
1870 BITFIELD(26, 1) /* index 17 */,
1871 CHILD(20), CHILD(30),
1872 BITFIELD(51, 2) /* index 20 */,
1873 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25),
1874 BITFIELD(53, 2) /* index 25 */,
1875 TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
1876 TILEGX_OPC_PREFETCH_L1_FAULT,
1877 BITFIELD(51, 2) /* index 30 */,
1878 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35),
1879 BITFIELD(53, 2) /* index 35 */,
1880 TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
1881 BITFIELD(26, 1) /* index 40 */,
1882 TILEGX_OPC_LD2S, TILEGX_OPC_LD2U,
1883 BITFIELD(26, 1) /* index 43 */,
1884 CHILD(46), CHILD(56),
1885 BITFIELD(51, 2) /* index 46 */,
1886 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51),
1887 BITFIELD(53, 2) /* index 51 */,
1888 TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
1889 TILEGX_OPC_PREFETCH_L2_FAULT,
1890 BITFIELD(51, 2) /* index 56 */,
1891 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61),
1892 BITFIELD(53, 2) /* index 61 */,
1893 TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
1894 BITFIELD(56, 2) /* index 66 */,
1895 CHILD(71), CHILD(74), CHILD(90), CHILD(93),
1896 BITFIELD(26, 1) /* index 71 */,
1897 TILEGX_OPC_NONE, TILEGX_OPC_LD4S,
1898 BITFIELD(26, 1) /* index 74 */,
1899 TILEGX_OPC_NONE, CHILD(77),
1900 BITFIELD(51, 2) /* index 77 */,
1901 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82),
1902 BITFIELD(53, 2) /* index 82 */,
1903 TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87),
1904 BITFIELD(55, 1) /* index 87 */,
1905 TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT,
1906 BITFIELD(26, 1) /* index 90 */,
1907 TILEGX_OPC_LD4U, TILEGX_OPC_LD,
1908 BITFIELD(26, 1) /* index 93 */,
1909 CHILD(96), TILEGX_OPC_LD,
1910 BITFIELD(51, 2) /* index 96 */,
1911 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101),
1912 BITFIELD(53, 2) /* index 101 */,
1913 TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106),
1914 BITFIELD(55, 1) /* index 106 */,
1915 TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
1916 BITFIELD(26, 1) /* index 109 */,
1917 CHILD(112), CHILD(115),
1918 BITFIELD(57, 1) /* index 112 */,
1919 TILEGX_OPC_ST1, TILEGX_OPC_ST4,
1920 BITFIELD(57, 1) /* index 115 */,
1921 TILEGX_OPC_ST2, TILEGX_OPC_ST,
1922};
1923
1924#undef BITFIELD
1925#undef CHILD
1926const unsigned short * const
1927tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] =
1928{
1929 decode_X0_fsm,
1930 decode_X1_fsm,
1931 decode_Y0_fsm,
1932 decode_Y1_fsm,
1933 decode_Y2_fsm
1934};
1935const struct tilegx_operand tilegx_operands[35] =
1936{
1937 {
1938 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0),
1939 8, 1, 0, 0, 0, 0,
1940 create_Imm8_X0, get_Imm8_X0
1941 },
1942 {
1943 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1),
1944 8, 1, 0, 0, 0, 0,
1945 create_Imm8_X1, get_Imm8_X1
1946 },
1947 {
1948 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0),
1949 8, 1, 0, 0, 0, 0,
1950 create_Imm8_Y0, get_Imm8_Y0
1951 },
1952 {
1953 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1),
1954 8, 1, 0, 0, 0, 0,
1955 create_Imm8_Y1, get_Imm8_Y1
1956 },
1957 {
1958 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST),
1959 16, 1, 0, 0, 0, 0,
1960 create_Imm16_X0, get_Imm16_X0
1961 },
1962 {
1963 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST),
1964 16, 1, 0, 0, 0, 0,
1965 create_Imm16_X1, get_Imm16_X1
1966 },
1967 {
1968 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1969 6, 0, 0, 1, 0, 0,
1970 create_Dest_X0, get_Dest_X0
1971 },
1972 {
1973 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1974 6, 0, 1, 0, 0, 0,
1975 create_SrcA_X0, get_SrcA_X0
1976 },
1977 {
1978 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1979 6, 0, 0, 1, 0, 0,
1980 create_Dest_X1, get_Dest_X1
1981 },
1982 {
1983 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1984 6, 0, 1, 0, 0, 0,
1985 create_SrcA_X1, get_SrcA_X1
1986 },
1987 {
1988 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1989 6, 0, 0, 1, 0, 0,
1990 create_Dest_Y0, get_Dest_Y0
1991 },
1992 {
1993 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1994 6, 0, 1, 0, 0, 0,
1995 create_SrcA_Y0, get_SrcA_Y0
1996 },
1997 {
1998 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
1999 6, 0, 0, 1, 0, 0,
2000 create_Dest_Y1, get_Dest_Y1
2001 },
2002 {
2003 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2004 6, 0, 1, 0, 0, 0,
2005 create_SrcA_Y1, get_SrcA_Y1
2006 },
2007 {
2008 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2009 6, 0, 1, 0, 0, 0,
2010 create_SrcA_Y2, get_SrcA_Y2
2011 },
2012 {
2013 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2014 6, 0, 1, 1, 0, 0,
2015 create_SrcA_X1, get_SrcA_X1
2016 },
2017 {
2018 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2019 6, 0, 1, 0, 0, 0,
2020 create_SrcB_X0, get_SrcB_X0
2021 },
2022 {
2023 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2024 6, 0, 1, 0, 0, 0,
2025 create_SrcB_X1, get_SrcB_X1
2026 },
2027 {
2028 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2029 6, 0, 1, 0, 0, 0,
2030 create_SrcB_Y0, get_SrcB_Y0
2031 },
2032 {
2033 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2034 6, 0, 1, 0, 0, 0,
2035 create_SrcB_Y1, get_SrcB_Y1
2036 },
2037 {
2038 TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1),
2039 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
2040 create_BrOff_X1, get_BrOff_X1
2041 },
2042 {
2043 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
2044 6, 0, 0, 0, 0, 0,
2045 create_BFStart_X0, get_BFStart_X0
2046 },
2047 {
2048 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
2049 6, 0, 0, 0, 0, 0,
2050 create_BFEnd_X0, get_BFEnd_X0
2051 },
2052 {
2053 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2054 6, 0, 1, 1, 0, 0,
2055 create_Dest_X0, get_Dest_X0
2056 },
2057 {
2058 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2059 6, 0, 1, 1, 0, 0,
2060 create_Dest_Y0, get_Dest_Y0
2061 },
2062 {
2063 TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1),
2064 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
2065 create_JumpOff_X1, get_JumpOff_X1
2066 },
2067 {
2068 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2069 6, 0, 0, 1, 0, 0,
2070 create_SrcBDest_Y2, get_SrcBDest_Y2
2071 },
2072 {
2073 TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1),
2074 14, 0, 0, 0, 0, 0,
2075 create_MF_Imm14_X1, get_MF_Imm14_X1
2076 },
2077 {
2078 TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1),
2079 14, 0, 0, 0, 0, 0,
2080 create_MT_Imm14_X1, get_MT_Imm14_X1
2081 },
2082 {
2083 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0),
2084 6, 0, 0, 0, 0, 0,
2085 create_ShAmt_X0, get_ShAmt_X0
2086 },
2087 {
2088 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1),
2089 6, 0, 0, 0, 0, 0,
2090 create_ShAmt_X1, get_ShAmt_X1
2091 },
2092 {
2093 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0),
2094 6, 0, 0, 0, 0, 0,
2095 create_ShAmt_Y0, get_ShAmt_Y0
2096 },
2097 {
2098 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1),
2099 6, 0, 0, 0, 0, 0,
2100 create_ShAmt_Y1, get_ShAmt_Y1
2101 },
2102 {
2103 TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
2104 6, 0, 1, 0, 0, 0,
2105 create_SrcBDest_Y2, get_SrcBDest_Y2
2106 },
2107 {
2108 TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1),
2109 8, 1, 0, 0, 0, 0,
2110 create_Dest_Imm8_X1, get_Dest_Imm8_X1
2111 }
2112};
2113
2114
2115
2116
2117/* Given a set of bundle bits and the lookup FSM for a specific pipe,
2118 * returns which instruction the bundle contains in that pipe.
2119 */
2120static const struct tilegx_opcode *
2121find_opcode(tilegx_bundle_bits bits, const unsigned short *table)
2122{
2123 int index = 0;
2124
2125 while (1)
2126 {
2127 unsigned short bitspec = table[index];
2128 unsigned int bitfield =
2129 ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
2130
2131 unsigned short next = table[index + 1 + bitfield];
2132 if (next <= TILEGX_OPC_NONE)
2133 return &tilegx_opcodes[next];
2134
2135 index = next - TILEGX_OPC_NONE;
2136 }
2137}
2138
2139
2140int
2141parse_insn_tilegx(tilegx_bundle_bits bits,
2142 unsigned long long pc,
2143 struct tilegx_decoded_instruction
2144 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE])
2145{
2146 int num_instructions = 0;
2147 int pipe;
2148
2149 int min_pipe, max_pipe;
2150 if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0)
2151 {
2152 min_pipe = TILEGX_PIPELINE_X0;
2153 max_pipe = TILEGX_PIPELINE_X1;
2154 }
2155 else
2156 {
2157 min_pipe = TILEGX_PIPELINE_Y0;
2158 max_pipe = TILEGX_PIPELINE_Y2;
2159 }
2160
2161 /* For each pipe, find an instruction that fits. */
2162 for (pipe = min_pipe; pipe <= max_pipe; pipe++)
2163 {
2164 const struct tilegx_opcode *opc;
2165 struct tilegx_decoded_instruction *d;
2166 int i;
2167
2168 d = &decoded[num_instructions++];
2169 opc = find_opcode (bits, tilegx_bundle_decoder_fsms[pipe]);
2170 d->opcode = opc;
2171
2172 /* Decode each operand, sign extending, etc. as appropriate. */
2173 for (i = 0; i < opc->num_operands; i++)
2174 {
2175 const struct tilegx_operand *op =
2176 &tilegx_operands[opc->operands[pipe][i]];
2177 int raw_opval = op->extract (bits);
2178 long long opval;
2179
2180 if (op->is_signed)
2181 {
2182 /* Sign-extend the operand. */
2183 int shift = (int)((sizeof(int) * 8) - op->num_bits);
2184 raw_opval = (raw_opval << shift) >> shift;
2185 }
2186
2187 /* Adjust PC-relative scaled branch offsets. */
2188 if (op->type == TILEGX_OP_TYPE_ADDRESS)
2189 opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc;
2190 else
2191 opval = raw_opval;
2192
2193 /* Record the final value. */
2194 d->operands[i] = op;
2195 d->operand_values[i] = opval;
2196 }
2197 }
2198
2199 return num_instructions;
2200}
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
index 6bed820e1421..c4be58cc5d50 100644
--- a/arch/tile/kernel/time.c
+++ b/arch/tile/kernel/time.c
@@ -22,6 +22,7 @@
22#include <linux/sched.h> 22#include <linux/sched.h>
23#include <linux/smp.h> 23#include <linux/smp.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <linux/module.h>
25#include <asm/irq_regs.h> 26#include <asm/irq_regs.h>
26#include <asm/traps.h> 27#include <asm/traps.h>
27#include <hv/hypervisor.h> 28#include <hv/hypervisor.h>
@@ -56,6 +57,7 @@ cycles_t get_cycles(void)
56 57
57 return (((cycles_t)high) << 32) | low; 58 return (((cycles_t)high) << 32) | low;
58} 59}
60EXPORT_SYMBOL(get_cycles);
59#endif 61#endif
60 62
61/* 63/*
@@ -132,7 +134,7 @@ static int tile_timer_set_next_event(unsigned long ticks,
132{ 134{
133 BUG_ON(ticks > MAX_TICK); 135 BUG_ON(ticks > MAX_TICK);
134 __insn_mtspr(SPR_TILE_TIMER_CONTROL, ticks); 136 __insn_mtspr(SPR_TILE_TIMER_CONTROL, ticks);
135 raw_local_irq_unmask_now(INT_TILE_TIMER); 137 arch_local_irq_unmask_now(INT_TILE_TIMER);
136 return 0; 138 return 0;
137} 139}
138 140
@@ -143,7 +145,7 @@ static int tile_timer_set_next_event(unsigned long ticks,
143static void tile_timer_set_mode(enum clock_event_mode mode, 145static void tile_timer_set_mode(enum clock_event_mode mode,
144 struct clock_event_device *evt) 146 struct clock_event_device *evt)
145{ 147{
146 raw_local_irq_mask_now(INT_TILE_TIMER); 148 arch_local_irq_mask_now(INT_TILE_TIMER);
147} 149}
148 150
149/* 151/*
@@ -172,7 +174,7 @@ void __cpuinit setup_tile_timer(void)
172 evt->cpumask = cpumask_of(smp_processor_id()); 174 evt->cpumask = cpumask_of(smp_processor_id());
173 175
174 /* Start out with timer not firing. */ 176 /* Start out with timer not firing. */
175 raw_local_irq_mask_now(INT_TILE_TIMER); 177 arch_local_irq_mask_now(INT_TILE_TIMER);
176 178
177 /* Register tile timer. */ 179 /* Register tile timer. */
178 clockevents_register_device(evt); 180 clockevents_register_device(evt);
@@ -188,7 +190,7 @@ void do_timer_interrupt(struct pt_regs *regs, int fault_num)
188 * Mask the timer interrupt here, since we are a oneshot timer 190 * Mask the timer interrupt here, since we are a oneshot timer
189 * and there are now by definition no events pending. 191 * and there are now by definition no events pending.
190 */ 192 */
191 raw_local_irq_mask(INT_TILE_TIMER); 193 arch_local_irq_mask(INT_TILE_TIMER);
192 194
193 /* Track time spent here in an interrupt context */ 195 /* Track time spent here in an interrupt context */
194 irq_enter(); 196 irq_enter();
@@ -224,3 +226,13 @@ int setup_profiling_timer(unsigned int multiplier)
224{ 226{
225 return -EINVAL; 227 return -EINVAL;
226} 228}
229
230/*
231 * Use the tile timer to convert nsecs to core clock cycles, relying
232 * on it having the same frequency as SPR_CYCLE.
233 */
234cycles_t ns2cycles(unsigned long nsecs)
235{
236 struct clock_event_device *dev = &__get_cpu_var(tile_timer);
237 return ((u64)nsecs * dev->mult) >> dev->shift;
238}
diff --git a/arch/tile/kernel/tlb.c b/arch/tile/kernel/tlb.c
index 2dffc1044d83..a5f241c24cac 100644
--- a/arch/tile/kernel/tlb.c
+++ b/arch/tile/kernel/tlb.c
@@ -34,13 +34,13 @@ void flush_tlb_mm(struct mm_struct *mm)
34{ 34{
35 HV_Remote_ASID asids[NR_CPUS]; 35 HV_Remote_ASID asids[NR_CPUS];
36 int i = 0, cpu; 36 int i = 0, cpu;
37 for_each_cpu(cpu, &mm->cpu_vm_mask) { 37 for_each_cpu(cpu, mm_cpumask(mm)) {
38 HV_Remote_ASID *asid = &asids[i++]; 38 HV_Remote_ASID *asid = &asids[i++];
39 asid->y = cpu / smp_topology.width; 39 asid->y = cpu / smp_topology.width;
40 asid->x = cpu % smp_topology.width; 40 asid->x = cpu % smp_topology.width;
41 asid->asid = per_cpu(current_asid, cpu); 41 asid->asid = per_cpu(current_asid, cpu);
42 } 42 }
43 flush_remote(0, HV_FLUSH_EVICT_L1I, &mm->cpu_vm_mask, 43 flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(mm),
44 0, 0, 0, NULL, asids, i); 44 0, 0, 0, NULL, asids, i);
45} 45}
46 46
@@ -54,8 +54,8 @@ void flush_tlb_page_mm(const struct vm_area_struct *vma, struct mm_struct *mm,
54{ 54{
55 unsigned long size = hv_page_size(vma); 55 unsigned long size = hv_page_size(vma);
56 int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0; 56 int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
57 flush_remote(0, cache, &mm->cpu_vm_mask, 57 flush_remote(0, cache, mm_cpumask(mm),
58 va, size, size, &mm->cpu_vm_mask, NULL, 0); 58 va, size, size, mm_cpumask(mm), NULL, 0);
59} 59}
60 60
61void flush_tlb_page(const struct vm_area_struct *vma, unsigned long va) 61void flush_tlb_page(const struct vm_area_struct *vma, unsigned long va)
@@ -70,8 +70,8 @@ void flush_tlb_range(const struct vm_area_struct *vma,
70 unsigned long size = hv_page_size(vma); 70 unsigned long size = hv_page_size(vma);
71 struct mm_struct *mm = vma->vm_mm; 71 struct mm_struct *mm = vma->vm_mm;
72 int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0; 72 int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
73 flush_remote(0, cache, &mm->cpu_vm_mask, start, end - start, size, 73 flush_remote(0, cache, mm_cpumask(mm), start, end - start, size,
74 &mm->cpu_vm_mask, NULL, 0); 74 mm_cpumask(mm), NULL, 0);
75} 75}
76 76
77void flush_tlb_all(void) 77void flush_tlb_all(void)
diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c
index 0f362dc2c57f..f9803dfa7357 100644
--- a/arch/tile/kernel/traps.c
+++ b/arch/tile/kernel/traps.c
@@ -260,7 +260,7 @@ void __kprobes do_trap(struct pt_regs *regs, int fault_num,
260 address = regs->pc; 260 address = regs->pc;
261 break; 261 break;
262 case INT_UNALIGN_DATA: 262 case INT_UNALIGN_DATA:
263#ifndef __tilegx__ /* FIXME: GX: no single-step yet */ 263#ifndef __tilegx__ /* Emulated support for single step debugging */
264 if (unaligned_fixup >= 0) { 264 if (unaligned_fixup >= 0) {
265 struct single_step_state *state = 265 struct single_step_state *state =
266 current_thread_info()->step_state; 266 current_thread_info()->step_state;
@@ -278,7 +278,7 @@ void __kprobes do_trap(struct pt_regs *regs, int fault_num,
278 case INT_DOUBLE_FAULT: 278 case INT_DOUBLE_FAULT:
279 /* 279 /*
280 * For double fault, "reason" is actually passed as 280 * For double fault, "reason" is actually passed as
281 * SYSTEM_SAVE_1_2, the hypervisor's double-fault info, so 281 * SYSTEM_SAVE_K_2, the hypervisor's double-fault info, so
282 * we can provide the original fault number rather than 282 * we can provide the original fault number rather than
283 * the uninteresting "INT_DOUBLE_FAULT" so the user can 283 * the uninteresting "INT_DOUBLE_FAULT" so the user can
284 * learn what actually struck while PL0 ICS was set. 284 * learn what actually struck while PL0 ICS was set.
@@ -308,6 +308,7 @@ void __kprobes do_trap(struct pt_regs *regs, int fault_num,
308 info.si_addr = (void __user *)address; 308 info.si_addr = (void __user *)address;
309 if (signo == SIGILL) 309 if (signo == SIGILL)
310 info.si_trapno = fault_num; 310 info.si_trapno = fault_num;
311 trace_unhandled_signal("trap", regs, address, signo);
311 force_sig_info(signo, &info, current); 312 force_sig_info(signo, &info, current);
312} 313}
313 314
diff --git a/arch/tile/kernel/vmlinux.lds.S b/arch/tile/kernel/vmlinux.lds.S
index 25fdc0c1839a..631f10de12fe 100644
--- a/arch/tile/kernel/vmlinux.lds.S
+++ b/arch/tile/kernel/vmlinux.lds.S
@@ -59,11 +59,8 @@ SECTIONS
59 59
60 . = ALIGN(PAGE_SIZE); 60 . = ALIGN(PAGE_SIZE);
61 VMLINUX_SYMBOL(_sinitdata) = .; 61 VMLINUX_SYMBOL(_sinitdata) = .;
62 .init.page : AT (ADDR(.init.page) - LOAD_OFFSET) { 62 INIT_DATA_SECTION(16) :data =0
63 *(.init.page) 63 PERCPU_SECTION(L2_CACHE_BYTES)
64 } :data =0
65 INIT_DATA_SECTION(16)
66 PERCPU(PAGE_SIZE)
67 . = ALIGN(PAGE_SIZE); 64 . = ALIGN(PAGE_SIZE);
68 VMLINUX_SYMBOL(_einitdata) = .; 65 VMLINUX_SYMBOL(_einitdata) = .;
69 66
diff --git a/arch/tile/kvm/Kconfig b/arch/tile/kvm/Kconfig
new file mode 100644
index 000000000000..b88f9c047781
--- /dev/null
+++ b/arch/tile/kvm/Kconfig
@@ -0,0 +1,38 @@
1#
2# KVM configuration
3#
4
5source "virt/kvm/Kconfig"
6
7menuconfig VIRTUALIZATION
8 bool "Virtualization"
9 ---help---
10 Say Y here to get to see options for using your Linux host to run
11 other operating systems inside virtual machines (guests).
12 This option alone does not add any kernel code.
13
14 If you say N, all options in this submenu will be skipped and
15 disabled.
16
17if VIRTUALIZATION
18
19config KVM
20 tristate "Kernel-based Virtual Machine (KVM) support"
21 depends on HAVE_KVM && MODULES && EXPERIMENTAL
22 select PREEMPT_NOTIFIERS
23 select ANON_INODES
24 ---help---
25 Support hosting paravirtualized guest machines.
26
27 This module provides access to the hardware capabilities through
28 a character device node named /dev/kvm.
29
30 To compile this as a module, choose M here: the module
31 will be called kvm.
32
33 If unsure, say N.
34
35source drivers/vhost/Kconfig
36source drivers/virtio/Kconfig
37
38endif # VIRTUALIZATION
diff --git a/arch/tile/lib/Makefile b/arch/tile/lib/Makefile
index 746dc81ed3c4..0c26086ecbef 100644
--- a/arch/tile/lib/Makefile
+++ b/arch/tile/lib/Makefile
@@ -2,9 +2,8 @@
2# Makefile for TILE-specific library files.. 2# Makefile for TILE-specific library files..
3# 3#
4 4
5lib-y = cacheflush.o checksum.o cpumask.o delay.o \ 5lib-y = cacheflush.o checksum.o cpumask.o delay.o uaccess.o \
6 mb_incoherent.o uaccess.o \ 6 memmove.o memcpy_$(BITS).o memchr_$(BITS).o memset_$(BITS).o \
7 memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \
8 strchr_$(BITS).o strlen_$(BITS).o 7 strchr_$(BITS).o strlen_$(BITS).o
9 8
10ifeq ($(CONFIG_TILEGX),y) 9ifeq ($(CONFIG_TILEGX),y)
diff --git a/arch/tile/lib/atomic_32.c b/arch/tile/lib/atomic_32.c
index 8040b42a8eea..46570211df52 100644
--- a/arch/tile/lib/atomic_32.c
+++ b/arch/tile/lib/atomic_32.c
@@ -46,14 +46,13 @@ struct atomic_locks_on_cpu *atomic_lock_ptr[ATOMIC_HASH_L1_SIZE]
46#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 46#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
47 47
48/* This page is remapped on startup to be hash-for-home. */ 48/* This page is remapped on startup to be hash-for-home. */
49int atomic_locks[PAGE_SIZE / sizeof(int) /* Only ATOMIC_HASH_SIZE is used */] 49int atomic_locks[PAGE_SIZE / sizeof(int)] __page_aligned_bss;
50 __attribute__((aligned(PAGE_SIZE), section(".bss.page_aligned")));
51 50
52#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 51#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
53 52
54static inline int *__atomic_hashed_lock(volatile void *v) 53static inline int *__atomic_hashed_lock(volatile void *v)
55{ 54{
56 /* NOTE: this code must match "sys_cmpxchg" in kernel/intvec.S */ 55 /* NOTE: this code must match "sys_cmpxchg" in kernel/intvec_32.S */
57#if ATOMIC_LOCKS_FOUND_VIA_TABLE() 56#if ATOMIC_LOCKS_FOUND_VIA_TABLE()
58 unsigned long i = 57 unsigned long i =
59 (unsigned long) v & ((PAGE_SIZE-1) & -sizeof(long long)); 58 (unsigned long) v & ((PAGE_SIZE-1) & -sizeof(long long));
@@ -203,32 +202,32 @@ static inline int *__futex_setup(int __user *v)
203 return __atomic_hashed_lock((int __force *)v); 202 return __atomic_hashed_lock((int __force *)v);
204} 203}
205 204
206struct __get_user futex_set(int __user *v, int i) 205struct __get_user futex_set(u32 __user *v, int i)
207{ 206{
208 return __atomic_xchg((int __force *)v, __futex_setup(v), i); 207 return __atomic_xchg((int __force *)v, __futex_setup(v), i);
209} 208}
210 209
211struct __get_user futex_add(int __user *v, int n) 210struct __get_user futex_add(u32 __user *v, int n)
212{ 211{
213 return __atomic_xchg_add((int __force *)v, __futex_setup(v), n); 212 return __atomic_xchg_add((int __force *)v, __futex_setup(v), n);
214} 213}
215 214
216struct __get_user futex_or(int __user *v, int n) 215struct __get_user futex_or(u32 __user *v, int n)
217{ 216{
218 return __atomic_or((int __force *)v, __futex_setup(v), n); 217 return __atomic_or((int __force *)v, __futex_setup(v), n);
219} 218}
220 219
221struct __get_user futex_andn(int __user *v, int n) 220struct __get_user futex_andn(u32 __user *v, int n)
222{ 221{
223 return __atomic_andn((int __force *)v, __futex_setup(v), n); 222 return __atomic_andn((int __force *)v, __futex_setup(v), n);
224} 223}
225 224
226struct __get_user futex_xor(int __user *v, int n) 225struct __get_user futex_xor(u32 __user *v, int n)
227{ 226{
228 return __atomic_xor((int __force *)v, __futex_setup(v), n); 227 return __atomic_xor((int __force *)v, __futex_setup(v), n);
229} 228}
230 229
231struct __get_user futex_cmpxchg(int __user *v, int o, int n) 230struct __get_user futex_cmpxchg(u32 __user *v, int o, int n)
232{ 231{
233 return __atomic_cmpxchg((int __force *)v, __futex_setup(v), o, n); 232 return __atomic_cmpxchg((int __force *)v, __futex_setup(v), o, n);
234} 233}
@@ -300,7 +299,7 @@ void __init __init_atomic_per_cpu(void)
300#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 299#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
301 300
302 /* Validate power-of-two and "bigger than cpus" assumption */ 301 /* Validate power-of-two and "bigger than cpus" assumption */
303 BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1)); 302 BUILD_BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1));
304 BUG_ON(ATOMIC_HASH_SIZE < nr_cpu_ids); 303 BUG_ON(ATOMIC_HASH_SIZE < nr_cpu_ids);
305 304
306 /* 305 /*
@@ -314,17 +313,17 @@ void __init __init_atomic_per_cpu(void)
314 BUG_ON((unsigned long)atomic_locks % PAGE_SIZE != 0); 313 BUG_ON((unsigned long)atomic_locks % PAGE_SIZE != 0);
315 314
316 /* The locks must all fit on one page. */ 315 /* The locks must all fit on one page. */
317 BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE); 316 BUILD_BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE);
318 317
319 /* 318 /*
320 * We use the page offset of the atomic value's address as 319 * We use the page offset of the atomic value's address as
321 * an index into atomic_locks, excluding the low 3 bits. 320 * an index into atomic_locks, excluding the low 3 bits.
322 * That should not produce more indices than ATOMIC_HASH_SIZE. 321 * That should not produce more indices than ATOMIC_HASH_SIZE.
323 */ 322 */
324 BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE); 323 BUILD_BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE);
325 324
326#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ 325#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
327 326
328 /* The futex code makes this assumption, so we validate it here. */ 327 /* The futex code makes this assumption, so we validate it here. */
329 BUG_ON(sizeof(atomic_t) != sizeof(int)); 328 BUILD_BUG_ON(sizeof(atomic_t) != sizeof(int));
330} 329}
diff --git a/arch/tile/lib/atomic_asm_32.S b/arch/tile/lib/atomic_asm_32.S
index 5a5514b77e78..24448734f6f1 100644
--- a/arch/tile/lib/atomic_asm_32.S
+++ b/arch/tile/lib/atomic_asm_32.S
@@ -14,7 +14,7 @@
14 * Support routines for atomic operations. Each function takes: 14 * Support routines for atomic operations. Each function takes:
15 * 15 *
16 * r0: address to manipulate 16 * r0: address to manipulate
17 * r1: pointer to atomic lock guarding this operation (for FUTEX_LOCK_REG) 17 * r1: pointer to atomic lock guarding this operation (for ATOMIC_LOCK_REG)
18 * r2: new value to write, or for cmpxchg/add_unless, value to compare against 18 * r2: new value to write, or for cmpxchg/add_unless, value to compare against
19 * r3: (cmpxchg/xchg_add_unless) new value to write or add; 19 * r3: (cmpxchg/xchg_add_unless) new value to write or add;
20 * (atomic64 ops) high word of value to write 20 * (atomic64 ops) high word of value to write
@@ -59,7 +59,7 @@
59 * bad kernel addresses). 59 * bad kernel addresses).
60 * 60 *
61 * Note that if the value we would store is the same as what we 61 * Note that if the value we would store is the same as what we
62 * loaded, we bypass the load. Other platforms with true atomics can 62 * loaded, we bypass the store. Other platforms with true atomics can
63 * make the guarantee that a non-atomic __clear_bit(), for example, 63 * make the guarantee that a non-atomic __clear_bit(), for example,
64 * can safely race with an atomic test_and_set_bit(); this example is 64 * can safely race with an atomic test_and_set_bit(); this example is
65 * from bit_spinlock.h in slub_lock() / slub_unlock(). We can't do 65 * from bit_spinlock.h in slub_lock() / slub_unlock(). We can't do
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index 11b6164c2097..8928aace7a64 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -15,9 +15,129 @@
15#include <asm/page.h> 15#include <asm/page.h>
16#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
17#include <arch/icache.h> 17#include <arch/icache.h>
18#include <arch/spr_def.h>
18 19
19 20
20void __flush_icache_range(unsigned long start, unsigned long end) 21void __flush_icache_range(unsigned long start, unsigned long end)
21{ 22{
22 invalidate_icache((const void *)start, end - start, PAGE_SIZE); 23 invalidate_icache((const void *)start, end - start, PAGE_SIZE);
23} 24}
25
26
27/* Force a load instruction to issue. */
28static inline void force_load(char *p)
29{
30 *(volatile char *)p;
31}
32
33/*
34 * Flush and invalidate a VA range that is homed remotely on a single
35 * core (if "!hfh") or homed via hash-for-home (if "hfh"), waiting
36 * until the memory controller holds the flushed values.
37 */
38void finv_buffer_remote(void *buffer, size_t size, int hfh)
39{
40 char *p, *base;
41 size_t step_size, load_count;
42 const unsigned long STRIPE_WIDTH = 8192;
43#ifdef __tilegx__
44 /*
45 * On TILE-Gx, we must disable the dstream prefetcher before doing
46 * a cache flush; otherwise, we could end up with data in the cache
47 * that we don't want there. Note that normally we'd do an mf
48 * after the SPR write to disabling the prefetcher, but we do one
49 * below, before any further loads, so there's no need to do it
50 * here.
51 */
52 uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
53 __insn_mtspr(SPR_DSTREAM_PF, 0);
54#endif
55
56 /*
57 * Flush and invalidate the buffer out of the local L1/L2
58 * and request the home cache to flush and invalidate as well.
59 */
60 __finv_buffer(buffer, size);
61
62 /*
63 * Wait for the home cache to acknowledge that it has processed
64 * all the flush-and-invalidate requests. This does not mean
65 * that the flushed data has reached the memory controller yet,
66 * but it does mean the home cache is processing the flushes.
67 */
68 __insn_mf();
69
70 /*
71 * Issue a load to the last cache line, which can't complete
72 * until all the previously-issued flushes to the same memory
73 * controller have also completed. If we weren't striping
74 * memory, that one load would be sufficient, but since we may
75 * be, we also need to back up to the last load issued to
76 * another memory controller, which would be the point where
77 * we crossed an 8KB boundary (the granularity of striping
78 * across memory controllers). Keep backing up and doing this
79 * until we are before the beginning of the buffer, or have
80 * hit all the controllers.
81 *
82 * If we are flushing a hash-for-home buffer, it's even worse.
83 * Each line may be homed on a different tile, and each tile
84 * may have up to four lines that are on different
85 * controllers. So as we walk backwards, we have to touch
86 * enough cache lines to satisfy these constraints. In
87 * practice this ends up being close enough to "load from
88 * every cache line on a full memory stripe on each
89 * controller" that we simply do that, to simplify the logic.
90 *
91 * FIXME: See bug 9535 for some issues with this code.
92 */
93 if (hfh) {
94 step_size = L2_CACHE_BYTES;
95 load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
96 (1 << CHIP_LOG_NUM_MSHIMS());
97 } else {
98 step_size = STRIPE_WIDTH;
99 load_count = (1 << CHIP_LOG_NUM_MSHIMS());
100 }
101
102 /* Load the last byte of the buffer. */
103 p = (char *)buffer + size - 1;
104 force_load(p);
105
106 /* Bump down to the end of the previous stripe or cache line. */
107 p -= step_size;
108 p = (char *)((unsigned long)p | (step_size - 1));
109
110 /* Figure out how far back we need to go. */
111 base = p - (step_size * (load_count - 2));
112 if ((long)base < (long)buffer)
113 base = buffer;
114
115 /*
116 * Fire all the loads we need. The MAF only has eight entries
117 * so we can have at most eight outstanding loads, so we
118 * unroll by that amount.
119 */
120#pragma unroll 8
121 for (; p >= base; p -= step_size)
122 force_load(p);
123
124 /*
125 * Repeat, but with inv's instead of loads, to get rid of the
126 * data we just loaded into our own cache and the old home L3.
127 * No need to unroll since inv's don't target a register.
128 */
129 p = (char *)buffer + size - 1;
130 __insn_inv(p);
131 p -= step_size;
132 p = (char *)((unsigned long)p | (step_size - 1));
133 for (; p >= base; p -= step_size)
134 __insn_inv(p);
135
136 /* Wait for the load+inv's (and thus finvs) to have completed. */
137 __insn_mf();
138
139#ifdef __tilegx__
140 /* Reenable the prefetcher. */
141 __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
142#endif
143}
diff --git a/arch/tile/lib/delay.c b/arch/tile/lib/delay.c
index 5801b03c13ef..cdacdd11d360 100644
--- a/arch/tile/lib/delay.c
+++ b/arch/tile/lib/delay.c
@@ -15,20 +15,31 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/delay.h> 16#include <linux/delay.h>
17#include <linux/thread_info.h> 17#include <linux/thread_info.h>
18#include <asm/fixmap.h> 18#include <asm/timex.h>
19#include <hv/hypervisor.h>
20 19
21void __udelay(unsigned long usecs) 20void __udelay(unsigned long usecs)
22{ 21{
23 hv_nanosleep(usecs * 1000); 22 if (usecs > ULONG_MAX / 1000) {
23 WARN_ON_ONCE(usecs > ULONG_MAX / 1000);
24 usecs = ULONG_MAX / 1000;
25 }
26 __ndelay(usecs * 1000);
24} 27}
25EXPORT_SYMBOL(__udelay); 28EXPORT_SYMBOL(__udelay);
26 29
27void __ndelay(unsigned long nsecs) 30void __ndelay(unsigned long nsecs)
28{ 31{
29 hv_nanosleep(nsecs); 32 cycles_t target = get_cycles();
33 target += ns2cycles(nsecs);
34 while (get_cycles() < target)
35 cpu_relax();
30} 36}
31EXPORT_SYMBOL(__ndelay); 37EXPORT_SYMBOL(__ndelay);
32 38
33/* FIXME: should be declared in a header somewhere. */ 39void __delay(unsigned long cycles)
40{
41 cycles_t target = get_cycles() + cycles;
42 while (get_cycles() < target)
43 cpu_relax();
44}
34EXPORT_SYMBOL(__delay); 45EXPORT_SYMBOL(__delay);
diff --git a/arch/tile/lib/exports.c b/arch/tile/lib/exports.c
index ce5dbf56578f..49284fae9d09 100644
--- a/arch/tile/lib/exports.c
+++ b/arch/tile/lib/exports.c
@@ -29,6 +29,9 @@ EXPORT_SYMBOL(__put_user_8);
29EXPORT_SYMBOL(strnlen_user_asm); 29EXPORT_SYMBOL(strnlen_user_asm);
30EXPORT_SYMBOL(strncpy_from_user_asm); 30EXPORT_SYMBOL(strncpy_from_user_asm);
31EXPORT_SYMBOL(clear_user_asm); 31EXPORT_SYMBOL(clear_user_asm);
32EXPORT_SYMBOL(flush_user_asm);
33EXPORT_SYMBOL(inv_user_asm);
34EXPORT_SYMBOL(finv_user_asm);
32 35
33/* arch/tile/kernel/entry.S */ 36/* arch/tile/kernel/entry.S */
34#include <linux/kernel.h> 37#include <linux/kernel.h>
@@ -82,4 +85,8 @@ int64_t __muldi3(int64_t, int64_t);
82EXPORT_SYMBOL(__muldi3); 85EXPORT_SYMBOL(__muldi3);
83uint64_t __lshrdi3(uint64_t, unsigned int); 86uint64_t __lshrdi3(uint64_t, unsigned int);
84EXPORT_SYMBOL(__lshrdi3); 87EXPORT_SYMBOL(__lshrdi3);
88uint64_t __ashrdi3(uint64_t, unsigned int);
89EXPORT_SYMBOL(__ashrdi3);
90uint64_t __ashldi3(uint64_t, unsigned int);
91EXPORT_SYMBOL(__ashldi3);
85#endif 92#endif
diff --git a/arch/tile/lib/memchr_32.c b/arch/tile/lib/memchr_32.c
index 6235283b4859..cc3d9badf030 100644
--- a/arch/tile/lib/memchr_32.c
+++ b/arch/tile/lib/memchr_32.c
@@ -18,12 +18,24 @@
18 18
19void *memchr(const void *s, int c, size_t n) 19void *memchr(const void *s, int c, size_t n)
20{ 20{
21 const uint32_t *last_word_ptr;
22 const uint32_t *p;
23 const char *last_byte_ptr;
24 uintptr_t s_int;
25 uint32_t goal, before_mask, v, bits;
26 char *ret;
27
28 if (__builtin_expect(n == 0, 0)) {
29 /* Don't dereference any memory if the array is empty. */
30 return NULL;
31 }
32
21 /* Get an aligned pointer. */ 33 /* Get an aligned pointer. */
22 const uintptr_t s_int = (uintptr_t) s; 34 s_int = (uintptr_t) s;
23 const uint32_t *p = (const uint32_t *)(s_int & -4); 35 p = (const uint32_t *)(s_int & -4);
24 36
25 /* Create four copies of the byte for which we are looking. */ 37 /* Create four copies of the byte for which we are looking. */
26 const uint32_t goal = 0x01010101 * (uint8_t) c; 38 goal = 0x01010101 * (uint8_t) c;
27 39
28 /* Read the first word, but munge it so that bytes before the array 40 /* Read the first word, but munge it so that bytes before the array
29 * will not match goal. 41 * will not match goal.
@@ -31,23 +43,14 @@ void *memchr(const void *s, int c, size_t n)
31 * Note that this shift count expression works because we know 43 * Note that this shift count expression works because we know
32 * shift counts are taken mod 32. 44 * shift counts are taken mod 32.
33 */ 45 */
34 const uint32_t before_mask = (1 << (s_int << 3)) - 1; 46 before_mask = (1 << (s_int << 3)) - 1;
35 uint32_t v = (*p | before_mask) ^ (goal & before_mask); 47 v = (*p | before_mask) ^ (goal & before_mask);
36 48
37 /* Compute the address of the last byte. */ 49 /* Compute the address of the last byte. */
38 const char *const last_byte_ptr = (const char *)s + n - 1; 50 last_byte_ptr = (const char *)s + n - 1;
39 51
40 /* Compute the address of the word containing the last byte. */ 52 /* Compute the address of the word containing the last byte. */
41 const uint32_t *const last_word_ptr = 53 last_word_ptr = (const uint32_t *)((uintptr_t) last_byte_ptr & -4);
42 (const uint32_t *)((uintptr_t) last_byte_ptr & -4);
43
44 uint32_t bits;
45 char *ret;
46
47 if (__builtin_expect(n == 0, 0)) {
48 /* Don't dereference any memory if the array is empty. */
49 return NULL;
50 }
51 54
52 while ((bits = __insn_seqb(v, goal)) == 0) { 55 while ((bits = __insn_seqb(v, goal)) == 0) {
53 if (__builtin_expect(p == last_word_ptr, 0)) { 56 if (__builtin_expect(p == last_word_ptr, 0)) {
diff --git a/arch/tile/lib/memchr_64.c b/arch/tile/lib/memchr_64.c
new file mode 100644
index 000000000000..84fdc8d8e735
--- /dev/null
+++ b/arch/tile/lib/memchr_64.c
@@ -0,0 +1,71 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18
19void *memchr(const void *s, int c, size_t n)
20{
21 const uint64_t *last_word_ptr;
22 const uint64_t *p;
23 const char *last_byte_ptr;
24 uintptr_t s_int;
25 uint64_t goal, before_mask, v, bits;
26 char *ret;
27
28 if (__builtin_expect(n == 0, 0)) {
29 /* Don't dereference any memory if the array is empty. */
30 return NULL;
31 }
32
33 /* Get an aligned pointer. */
34 s_int = (uintptr_t) s;
35 p = (const uint64_t *)(s_int & -8);
36
37 /* Create eight copies of the byte for which we are looking. */
38 goal = 0x0101010101010101ULL * (uint8_t) c;
39
40 /* Read the first word, but munge it so that bytes before the array
41 * will not match goal.
42 *
43 * Note that this shift count expression works because we know
44 * shift counts are taken mod 64.
45 */
46 before_mask = (1ULL << (s_int << 3)) - 1;
47 v = (*p | before_mask) ^ (goal & before_mask);
48
49 /* Compute the address of the last byte. */
50 last_byte_ptr = (const char *)s + n - 1;
51
52 /* Compute the address of the word containing the last byte. */
53 last_word_ptr = (const uint64_t *)((uintptr_t) last_byte_ptr & -8);
54
55 while ((bits = __insn_v1cmpeq(v, goal)) == 0) {
56 if (__builtin_expect(p == last_word_ptr, 0)) {
57 /* We already read the last word in the array,
58 * so give up.
59 */
60 return NULL;
61 }
62 v = *++p;
63 }
64
65 /* We found a match, but it might be in a byte past the end
66 * of the array.
67 */
68 ret = ((char *)p) + (__insn_ctz(bits) >> 3);
69 return (ret <= last_byte_ptr) ? ret : NULL;
70}
71EXPORT_SYMBOL(memchr);
diff --git a/arch/tile/lib/memcpy_32.S b/arch/tile/lib/memcpy_32.S
index 30c3b7ebb55d..2a419a6122db 100644
--- a/arch/tile/lib/memcpy_32.S
+++ b/arch/tile/lib/memcpy_32.S
@@ -10,14 +10,16 @@
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for 11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details. 12 * more details.
13 *
14 * This file shares the implementation of the userspace memcpy and
15 * the kernel's memcpy, copy_to_user and copy_from_user.
16 */ 13 */
17 14
18#include <arch/chip.h> 15#include <arch/chip.h>
19 16
20 17
18/*
19 * This file shares the implementation of the userspace memcpy and
20 * the kernel's memcpy, copy_to_user and copy_from_user.
21 */
22
21#include <linux/linkage.h> 23#include <linux/linkage.h>
22 24
23/* On TILE64, we wrap these functions via arch/tile/lib/memcpy_tile64.c */ 25/* On TILE64, we wrap these functions via arch/tile/lib/memcpy_tile64.c */
@@ -53,9 +55,9 @@
53 */ 55 */
54ENTRY(__copy_from_user_inatomic) 56ENTRY(__copy_from_user_inatomic)
55.type __copy_from_user_inatomic, @function 57.type __copy_from_user_inatomic, @function
56 FEEDBACK_ENTER_EXPLICIT(__copy_from_user_inatomic, \ 58 FEEDBACK_ENTER_EXPLICIT(__copy_from_user_inatomic, \
57 .text.memcpy_common, \ 59 .text.memcpy_common, \
58 .Lend_memcpy_common - __copy_from_user_inatomic) 60 .Lend_memcpy_common - __copy_from_user_inatomic)
59 { movei r29, IS_COPY_FROM_USER; j memcpy_common } 61 { movei r29, IS_COPY_FROM_USER; j memcpy_common }
60 .size __copy_from_user_inatomic, . - __copy_from_user_inatomic 62 .size __copy_from_user_inatomic, . - __copy_from_user_inatomic
61 63
@@ -64,7 +66,7 @@ ENTRY(__copy_from_user_inatomic)
64 */ 66 */
65ENTRY(__copy_from_user_zeroing) 67ENTRY(__copy_from_user_zeroing)
66.type __copy_from_user_zeroing, @function 68.type __copy_from_user_zeroing, @function
67 FEEDBACK_REENTER(__copy_from_user_inatomic) 69 FEEDBACK_REENTER(__copy_from_user_inatomic)
68 { movei r29, IS_COPY_FROM_USER_ZEROING; j memcpy_common } 70 { movei r29, IS_COPY_FROM_USER_ZEROING; j memcpy_common }
69 .size __copy_from_user_zeroing, . - __copy_from_user_zeroing 71 .size __copy_from_user_zeroing, . - __copy_from_user_zeroing
70 72
@@ -74,13 +76,13 @@ ENTRY(__copy_from_user_zeroing)
74 */ 76 */
75ENTRY(__copy_to_user_inatomic) 77ENTRY(__copy_to_user_inatomic)
76.type __copy_to_user_inatomic, @function 78.type __copy_to_user_inatomic, @function
77 FEEDBACK_REENTER(__copy_from_user_inatomic) 79 FEEDBACK_REENTER(__copy_from_user_inatomic)
78 { movei r29, IS_COPY_TO_USER; j memcpy_common } 80 { movei r29, IS_COPY_TO_USER; j memcpy_common }
79 .size __copy_to_user_inatomic, . - __copy_to_user_inatomic 81 .size __copy_to_user_inatomic, . - __copy_to_user_inatomic
80 82
81ENTRY(memcpy) 83ENTRY(memcpy)
82.type memcpy, @function 84.type memcpy, @function
83 FEEDBACK_REENTER(__copy_from_user_inatomic) 85 FEEDBACK_REENTER(__copy_from_user_inatomic)
84 { movei r29, IS_MEMCPY } 86 { movei r29, IS_MEMCPY }
85 .size memcpy, . - memcpy 87 .size memcpy, . - memcpy
86 /* Fall through */ 88 /* Fall through */
@@ -157,35 +159,35 @@ EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
157 { addi r3, r1, 60; andi r9, r9, -64 } 159 { addi r3, r1, 60; andi r9, r9, -64 }
158 160
159#if CHIP_HAS_WH64() 161#if CHIP_HAS_WH64()
160 /* No need to prefetch dst, we'll just do the wh64 162 /* No need to prefetch dst, we'll just do the wh64
161 * right before we copy a line. 163 * right before we copy a line.
162 */ 164 */
163#endif 165#endif
164 166
165EX: { lw r5, r3; addi r3, r3, 64; movei r4, 1 } 167EX: { lw r5, r3; addi r3, r3, 64; movei r4, 1 }
166 /* Intentionally stall for a few cycles to leave L2 cache alone. */ 168 /* Intentionally stall for a few cycles to leave L2 cache alone. */
167 { bnzt zero, .; move r27, lr } 169 { bnzt zero, .; move r27, lr }
168EX: { lw r6, r3; addi r3, r3, 64 } 170EX: { lw r6, r3; addi r3, r3, 64 }
169 /* Intentionally stall for a few cycles to leave L2 cache alone. */ 171 /* Intentionally stall for a few cycles to leave L2 cache alone. */
170 { bnzt zero, . } 172 { bnzt zero, . }
171EX: { lw r7, r3; addi r3, r3, 64 } 173EX: { lw r7, r3; addi r3, r3, 64 }
172#if !CHIP_HAS_WH64() 174#if !CHIP_HAS_WH64()
173 /* Prefetch the dest */ 175 /* Prefetch the dest */
174 /* Intentionally stall for a few cycles to leave L2 cache alone. */ 176 /* Intentionally stall for a few cycles to leave L2 cache alone. */
175 { bnzt zero, . } 177 { bnzt zero, . }
176 /* Use a real load to cause a TLB miss if necessary. We aren't using 178 /* Use a real load to cause a TLB miss if necessary. We aren't using
177 * r28, so this should be fine. 179 * r28, so this should be fine.
178 */ 180 */
179EX: { lw r28, r9; addi r9, r9, 64 } 181EX: { lw r28, r9; addi r9, r9, 64 }
180 /* Intentionally stall for a few cycles to leave L2 cache alone. */ 182 /* Intentionally stall for a few cycles to leave L2 cache alone. */
181 { bnzt zero, . } 183 { bnzt zero, . }
182 { prefetch r9; addi r9, r9, 64 } 184 { prefetch r9; addi r9, r9, 64 }
183 /* Intentionally stall for a few cycles to leave L2 cache alone. */ 185 /* Intentionally stall for a few cycles to leave L2 cache alone. */
184 { bnzt zero, . } 186 { bnzt zero, . }
185 { prefetch r9; addi r9, r9, 64 } 187 { prefetch r9; addi r9, r9, 64 }
186#endif 188#endif
187 /* Intentionally stall for a few cycles to leave L2 cache alone. */ 189 /* Intentionally stall for a few cycles to leave L2 cache alone. */
188 { bz zero, .Lbig_loop2 } 190 { bz zero, .Lbig_loop2 }
189 191
190 /* On entry to this loop: 192 /* On entry to this loop:
191 * - r0 points to the start of dst line 0 193 * - r0 points to the start of dst line 0
@@ -197,7 +199,7 @@ EX: { lw r28, r9; addi r9, r9, 64 }
197 * to some "safe" recently loaded address. 199 * to some "safe" recently loaded address.
198 * - r5 contains *(r1 + 60) [i.e. last word of source line 0] 200 * - r5 contains *(r1 + 60) [i.e. last word of source line 0]
199 * - r6 contains *(r1 + 64 + 60) [i.e. last word of source line 1] 201 * - r6 contains *(r1 + 64 + 60) [i.e. last word of source line 1]
200 * - r9 contains ((r0 + 63) & -64) 202 * - r9 contains ((r0 + 63) & -64)
201 * [start of next dst cache line.] 203 * [start of next dst cache line.]
202 */ 204 */
203 205
@@ -208,137 +210,137 @@ EX: { lw r28, r9; addi r9, r9, 64 }
208 /* Copy line 0, first stalling until r5 is ready. */ 210 /* Copy line 0, first stalling until r5 is ready. */
209EX: { move r12, r5; lw r16, r1 } 211EX: { move r12, r5; lw r16, r1 }
210 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 } 212 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
211 /* Prefetch several lines ahead. */ 213 /* Prefetch several lines ahead. */
212EX: { lw r5, r3; addi r3, r3, 64 } 214EX: { lw r5, r3; addi r3, r3, 64 }
213 { jal .Lcopy_line } 215 { jal .Lcopy_line }
214 216
215 /* Copy line 1, first stalling until r6 is ready. */ 217 /* Copy line 1, first stalling until r6 is ready. */
216EX: { move r12, r6; lw r16, r1 } 218EX: { move r12, r6; lw r16, r1 }
217 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 } 219 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
218 /* Prefetch several lines ahead. */ 220 /* Prefetch several lines ahead. */
219EX: { lw r6, r3; addi r3, r3, 64 } 221EX: { lw r6, r3; addi r3, r3, 64 }
220 { jal .Lcopy_line } 222 { jal .Lcopy_line }
221 223
222 /* Copy line 2, first stalling until r7 is ready. */ 224 /* Copy line 2, first stalling until r7 is ready. */
223EX: { move r12, r7; lw r16, r1 } 225EX: { move r12, r7; lw r16, r1 }
224 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 } 226 { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
225 /* Prefetch several lines ahead. */ 227 /* Prefetch several lines ahead. */
226EX: { lw r7, r3; addi r3, r3, 64 } 228EX: { lw r7, r3; addi r3, r3, 64 }
227 /* Use up a caches-busy cycle by jumping back to the top of the 229 /* Use up a caches-busy cycle by jumping back to the top of the
228 * loop. Might as well get it out of the way now. 230 * loop. Might as well get it out of the way now.
229 */ 231 */
230 { j .Lbig_loop } 232 { j .Lbig_loop }
231 233
232 234
233 /* On entry: 235 /* On entry:
234 * - r0 points to the destination line. 236 * - r0 points to the destination line.
235 * - r1 points to the source line. 237 * - r1 points to the source line.
236 * - r3 is the next prefetch address. 238 * - r3 is the next prefetch address.
237 * - r9 holds the last address used for wh64. 239 * - r9 holds the last address used for wh64.
238 * - r12 = WORD_15 240 * - r12 = WORD_15
239 * - r16 = WORD_0. 241 * - r16 = WORD_0.
240 * - r17 == r1 + 16. 242 * - r17 == r1 + 16.
241 * - r27 holds saved lr to restore. 243 * - r27 holds saved lr to restore.
242 * 244 *
243 * On exit: 245 * On exit:
244 * - r0 is incremented by 64. 246 * - r0 is incremented by 64.
245 * - r1 is incremented by 64, unless that would point to a word 247 * - r1 is incremented by 64, unless that would point to a word
246 * beyond the end of the source array, in which case it is redirected 248 * beyond the end of the source array, in which case it is redirected
247 * to point to an arbitrary word already in the cache. 249 * to point to an arbitrary word already in the cache.
248 * - r2 is decremented by 64. 250 * - r2 is decremented by 64.
249 * - r3 is unchanged, unless it points to a word beyond the 251 * - r3 is unchanged, unless it points to a word beyond the
250 * end of the source array, in which case it is redirected 252 * end of the source array, in which case it is redirected
251 * to point to an arbitrary word already in the cache. 253 * to point to an arbitrary word already in the cache.
252 * Redirecting is OK since if we are that close to the end 254 * Redirecting is OK since if we are that close to the end
253 * of the array we will not come back to this subroutine 255 * of the array we will not come back to this subroutine
254 * and use the contents of the prefetched address. 256 * and use the contents of the prefetched address.
255 * - r4 is nonzero iff r2 >= 64. 257 * - r4 is nonzero iff r2 >= 64.
256 * - r9 is incremented by 64, unless it points beyond the 258 * - r9 is incremented by 64, unless it points beyond the
257 * end of the last full destination cache line, in which 259 * end of the last full destination cache line, in which
258 * case it is redirected to a "safe address" that can be 260 * case it is redirected to a "safe address" that can be
259 * clobbered (sp - 64) 261 * clobbered (sp - 64)
260 * - lr contains the value in r27. 262 * - lr contains the value in r27.
261 */ 263 */
262 264
263/* r26 unused */ 265/* r26 unused */
264 266
265.Lcopy_line: 267.Lcopy_line:
266 /* TODO: when r3 goes past the end, we would like to redirect it 268 /* TODO: when r3 goes past the end, we would like to redirect it
267 * to prefetch the last partial cache line (if any) just once, for the 269 * to prefetch the last partial cache line (if any) just once, for the
268 * benefit of the final cleanup loop. But we don't want to 270 * benefit of the final cleanup loop. But we don't want to
269 * prefetch that line more than once, or subsequent prefetches 271 * prefetch that line more than once, or subsequent prefetches
270 * will go into the RTF. But then .Lbig_loop should unconditionally 272 * will go into the RTF. But then .Lbig_loop should unconditionally
271 * branch to top of loop to execute final prefetch, and its 273 * branch to top of loop to execute final prefetch, and its
272 * nop should become a conditional branch. 274 * nop should become a conditional branch.
273 */ 275 */
274 276
275 /* We need two non-memory cycles here to cover the resources 277 /* We need two non-memory cycles here to cover the resources
276 * used by the loads initiated by the caller. 278 * used by the loads initiated by the caller.
277 */ 279 */
278 { add r15, r1, r2 } 280 { add r15, r1, r2 }
279.Lcopy_line2: 281.Lcopy_line2:
280 { slt_u r13, r3, r15; addi r17, r1, 16 } 282 { slt_u r13, r3, r15; addi r17, r1, 16 }
281 283
282 /* NOTE: this will stall for one cycle as L1 is busy. */ 284 /* NOTE: this will stall for one cycle as L1 is busy. */
283 285
284 /* Fill second L1D line. */ 286 /* Fill second L1D line. */
285EX: { lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */ 287EX: { lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */
286 288
287#if CHIP_HAS_WH64() 289#if CHIP_HAS_WH64()
288 /* Prepare destination line for writing. */ 290 /* Prepare destination line for writing. */
289EX: { wh64 r9; addi r9, r9, 64 } 291EX: { wh64 r9; addi r9, r9, 64 }
290#else 292#else
291 /* Prefetch dest line */ 293 /* Prefetch dest line */
292 { prefetch r9; addi r9, r9, 64 } 294 { prefetch r9; addi r9, r9, 64 }
293#endif 295#endif
294 /* Load seven words that are L1D hits to cover wh64 L2 usage. */ 296 /* Load seven words that are L1D hits to cover wh64 L2 usage. */
295 297
296 /* Load the three remaining words from the last L1D line, which 298 /* Load the three remaining words from the last L1D line, which
297 * we know has already filled the L1D. 299 * we know has already filled the L1D.
298 */ 300 */
299EX: { lw r4, r1; addi r1, r1, 4; addi r20, r1, 16 } /* r4 = WORD_12 */ 301EX: { lw r4, r1; addi r1, r1, 4; addi r20, r1, 16 } /* r4 = WORD_12 */
300EX: { lw r8, r1; addi r1, r1, 4; slt_u r13, r20, r15 }/* r8 = WORD_13 */ 302EX: { lw r8, r1; addi r1, r1, 4; slt_u r13, r20, r15 }/* r8 = WORD_13 */
301EX: { lw r11, r1; addi r1, r1, -52; mvz r20, r13, r1 } /* r11 = WORD_14 */ 303EX: { lw r11, r1; addi r1, r1, -52; mvz r20, r13, r1 } /* r11 = WORD_14 */
302 304
303 /* Load the three remaining words from the first L1D line, first 305 /* Load the three remaining words from the first L1D line, first
304 * stalling until it has filled by "looking at" r16. 306 * stalling until it has filled by "looking at" r16.
305 */ 307 */
306EX: { lw r13, r1; addi r1, r1, 4; move zero, r16 } /* r13 = WORD_1 */ 308EX: { lw r13, r1; addi r1, r1, 4; move zero, r16 } /* r13 = WORD_1 */
307EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_2 */ 309EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_2 */
308EX: { lw r15, r1; addi r1, r1, 8; addi r10, r0, 60 } /* r15 = WORD_3 */ 310EX: { lw r15, r1; addi r1, r1, 8; addi r10, r0, 60 } /* r15 = WORD_3 */
309 311
310 /* Load second word from the second L1D line, first 312 /* Load second word from the second L1D line, first
311 * stalling until it has filled by "looking at" r17. 313 * stalling until it has filled by "looking at" r17.
312 */ 314 */
313EX: { lw r19, r1; addi r1, r1, 4; move zero, r17 } /* r19 = WORD_5 */ 315EX: { lw r19, r1; addi r1, r1, 4; move zero, r17 } /* r19 = WORD_5 */
314 316
315 /* Store last word to the destination line, potentially dirtying it 317 /* Store last word to the destination line, potentially dirtying it
316 * for the first time, which keeps the L2 busy for two cycles. 318 * for the first time, which keeps the L2 busy for two cycles.
317 */ 319 */
318EX: { sw r10, r12 } /* store(WORD_15) */ 320EX: { sw r10, r12 } /* store(WORD_15) */
319 321
320 /* Use two L1D hits to cover the sw L2 access above. */ 322 /* Use two L1D hits to cover the sw L2 access above. */
321EX: { lw r10, r1; addi r1, r1, 4 } /* r10 = WORD_6 */ 323EX: { lw r10, r1; addi r1, r1, 4 } /* r10 = WORD_6 */
322EX: { lw r12, r1; addi r1, r1, 4 } /* r12 = WORD_7 */ 324EX: { lw r12, r1; addi r1, r1, 4 } /* r12 = WORD_7 */
323 325
324 /* Fill third L1D line. */ 326 /* Fill third L1D line. */
325EX: { lw r18, r1; addi r1, r1, 4 } /* r18 = WORD_8 */ 327EX: { lw r18, r1; addi r1, r1, 4 } /* r18 = WORD_8 */
326 328
327 /* Store first L1D line. */ 329 /* Store first L1D line. */
328EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */ 330EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */
329EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */ 331EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */
330EX: { sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */ 332EX: { sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */
331#if CHIP_HAS_WH64() 333#if CHIP_HAS_WH64()
332EX: { sw r0, r15; addi r0, r0, 4; addi r13, sp, -64 } /* store(WORD_3) */ 334EX: { sw r0, r15; addi r0, r0, 4; addi r13, sp, -64 } /* store(WORD_3) */
333#else 335#else
334 /* Back up the r9 to a cache line we are already storing to 336 /* Back up the r9 to a cache line we are already storing to
335 * if it gets past the end of the dest vector. Strictly speaking, 337 * if it gets past the end of the dest vector. Strictly speaking,
336 * we don't need to back up to the start of a cache line, but it's free 338 * we don't need to back up to the start of a cache line, but it's free
337 * and tidy, so why not? 339 * and tidy, so why not?
338 */ 340 */
339EX: { sw r0, r15; addi r0, r0, 4; andi r13, r0, -64 } /* store(WORD_3) */ 341EX: { sw r0, r15; addi r0, r0, 4; andi r13, r0, -64 } /* store(WORD_3) */
340#endif 342#endif
341 /* Store second L1D line. */ 343 /* Store second L1D line. */
342EX: { sw r0, r17; addi r0, r0, 4; mvz r9, r16, r13 }/* store(WORD_4) */ 344EX: { sw r0, r17; addi r0, r0, 4; mvz r9, r16, r13 }/* store(WORD_4) */
343EX: { sw r0, r19; addi r0, r0, 4 } /* store(WORD_5) */ 345EX: { sw r0, r19; addi r0, r0, 4 } /* store(WORD_5) */
344EX: { sw r0, r10; addi r0, r0, 4 } /* store(WORD_6) */ 346EX: { sw r0, r10; addi r0, r0, 4 } /* store(WORD_6) */
@@ -348,30 +350,30 @@ EX: { lw r13, r1; addi r1, r1, 4; move zero, r18 } /* r13 = WORD_9 */
348EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_10 */ 350EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_10 */
349EX: { lw r15, r1; move r1, r20 } /* r15 = WORD_11 */ 351EX: { lw r15, r1; move r1, r20 } /* r15 = WORD_11 */
350 352
351 /* Store third L1D line. */ 353 /* Store third L1D line. */
352EX: { sw r0, r18; addi r0, r0, 4 } /* store(WORD_8) */ 354EX: { sw r0, r18; addi r0, r0, 4 } /* store(WORD_8) */
353EX: { sw r0, r13; addi r0, r0, 4 } /* store(WORD_9) */ 355EX: { sw r0, r13; addi r0, r0, 4 } /* store(WORD_9) */
354EX: { sw r0, r14; addi r0, r0, 4 } /* store(WORD_10) */ 356EX: { sw r0, r14; addi r0, r0, 4 } /* store(WORD_10) */
355EX: { sw r0, r15; addi r0, r0, 4 } /* store(WORD_11) */ 357EX: { sw r0, r15; addi r0, r0, 4 } /* store(WORD_11) */
356 358
357 /* Store rest of fourth L1D line. */ 359 /* Store rest of fourth L1D line. */
358EX: { sw r0, r4; addi r0, r0, 4 } /* store(WORD_12) */ 360EX: { sw r0, r4; addi r0, r0, 4 } /* store(WORD_12) */
359 { 361 {
360EX: sw r0, r8 /* store(WORD_13) */ 362EX: sw r0, r8 /* store(WORD_13) */
361 addi r0, r0, 4 363 addi r0, r0, 4
362 /* Will r2 be > 64 after we subtract 64 below? */ 364 /* Will r2 be > 64 after we subtract 64 below? */
363 shri r4, r2, 7 365 shri r4, r2, 7
364 } 366 }
365 { 367 {
366EX: sw r0, r11 /* store(WORD_14) */ 368EX: sw r0, r11 /* store(WORD_14) */
367 addi r0, r0, 8 369 addi r0, r0, 8
368 /* Record 64 bytes successfully copied. */ 370 /* Record 64 bytes successfully copied. */
369 addi r2, r2, -64 371 addi r2, r2, -64
370 } 372 }
371 373
372 { jrp lr; move lr, r27 } 374 { jrp lr; move lr, r27 }
373 375
374 /* Convey to the backtrace library that the stack frame is size 376 /* Convey to the backtrace library that the stack frame is size
375 * zero, and the real return address is on the stack rather than 377 * zero, and the real return address is on the stack rather than
376 * in 'lr'. 378 * in 'lr'.
377 */ 379 */
diff --git a/arch/tile/lib/memcpy_64.c b/arch/tile/lib/memcpy_64.c
new file mode 100644
index 000000000000..3fab9a6a2bbe
--- /dev/null
+++ b/arch/tile/lib/memcpy_64.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18#define __memcpy memcpy
19/* EXPORT_SYMBOL() is in arch/tile/lib/exports.c since this should be asm. */
20
21/* Must be 8 bytes in size. */
22#define word_t uint64_t
23
24#if CHIP_L2_LINE_SIZE() != 64 && CHIP_L2_LINE_SIZE() != 128
25#error "Assumes 64 or 128 byte line size"
26#endif
27
28/* How many cache lines ahead should we prefetch? */
29#define PREFETCH_LINES_AHEAD 3
30
31/*
32 * Provide "base versions" of load and store for the normal code path.
33 * The kernel provides other versions for userspace copies.
34 */
35#define ST(p, v) (*(p) = (v))
36#define LD(p) (*(p))
37
38#ifndef USERCOPY_FUNC
39#define ST1 ST
40#define ST2 ST
41#define ST4 ST
42#define ST8 ST
43#define LD1 LD
44#define LD2 LD
45#define LD4 LD
46#define LD8 LD
47#define RETVAL dstv
48void *memcpy(void *__restrict dstv, const void *__restrict srcv, size_t n)
49#else
50/*
51 * Special kernel version will provide implementation of the LDn/STn
52 * macros to return a count of uncopied bytes due to mm fault.
53 */
54#define RETVAL 0
55int USERCOPY_FUNC(void *__restrict dstv, const void *__restrict srcv, size_t n)
56#endif
57{
58 char *__restrict dst1 = (char *)dstv;
59 const char *__restrict src1 = (const char *)srcv;
60 const char *__restrict src1_end;
61 const char *__restrict prefetch;
62 word_t *__restrict dst8; /* 8-byte pointer to destination memory. */
63 word_t final; /* Final bytes to write to trailing word, if any */
64 long i;
65
66 if (n < 16) {
67 for (; n; n--)
68 ST1(dst1++, LD1(src1++));
69 return RETVAL;
70 }
71
72 /*
73 * Locate the end of source memory we will copy. Don't
74 * prefetch past this.
75 */
76 src1_end = src1 + n - 1;
77
78 /* Prefetch ahead a few cache lines, but not past the end. */
79 prefetch = src1;
80 for (i = 0; i < PREFETCH_LINES_AHEAD; i++) {
81 __insn_prefetch(prefetch);
82 prefetch += CHIP_L2_LINE_SIZE();
83 prefetch = (prefetch > src1_end) ? prefetch : src1;
84 }
85
86 /* Copy bytes until dst is word-aligned. */
87 for (; (uintptr_t)dst1 & (sizeof(word_t) - 1); n--)
88 ST1(dst1++, LD1(src1++));
89
90 /* 8-byte pointer to destination memory. */
91 dst8 = (word_t *)dst1;
92
93 if (__builtin_expect((uintptr_t)src1 & (sizeof(word_t) - 1), 0)) {
94 /*
95 * Misaligned copy. Copy 8 bytes at a time, but don't
96 * bother with other fanciness.
97 *
98 * TODO: Consider prefetching and using wh64 as well.
99 */
100
101 /* Create an aligned src8. */
102 const word_t *__restrict src8 =
103 (const word_t *)((uintptr_t)src1 & -sizeof(word_t));
104 word_t b;
105
106 word_t a = LD8(src8++);
107 for (; n >= sizeof(word_t); n -= sizeof(word_t)) {
108 b = LD8(src8++);
109 a = __insn_dblalign(a, b, src1);
110 ST8(dst8++, a);
111 a = b;
112 }
113
114 if (n == 0)
115 return RETVAL;
116
117 b = ((const char *)src8 <= src1_end) ? *src8 : 0;
118
119 /*
120 * Final source bytes to write to trailing partial
121 * word, if any.
122 */
123 final = __insn_dblalign(a, b, src1);
124 } else {
125 /* Aligned copy. */
126
127 const word_t* __restrict src8 = (const word_t *)src1;
128
129 /* src8 and dst8 are both word-aligned. */
130 if (n >= CHIP_L2_LINE_SIZE()) {
131 /* Copy until 'dst' is cache-line-aligned. */
132 for (; (uintptr_t)dst8 & (CHIP_L2_LINE_SIZE() - 1);
133 n -= sizeof(word_t))
134 ST8(dst8++, LD8(src8++));
135
136 for (; n >= CHIP_L2_LINE_SIZE(); ) {
137 __insn_wh64(dst8);
138
139 /*
140 * Prefetch and advance to next line
141 * to prefetch, but don't go past the end
142 */
143 __insn_prefetch(prefetch);
144 prefetch += CHIP_L2_LINE_SIZE();
145 prefetch = (prefetch > src1_end) ? prefetch :
146 (const char *)src8;
147
148 /*
149 * Copy an entire cache line. Manually
150 * unrolled to avoid idiosyncracies of
151 * compiler unrolling.
152 */
153#define COPY_WORD(offset) ({ ST8(dst8+offset, LD8(src8+offset)); n -= 8; })
154 COPY_WORD(0);
155 COPY_WORD(1);
156 COPY_WORD(2);
157 COPY_WORD(3);
158 COPY_WORD(4);
159 COPY_WORD(5);
160 COPY_WORD(6);
161 COPY_WORD(7);
162#if CHIP_L2_LINE_SIZE() == 128
163 COPY_WORD(8);
164 COPY_WORD(9);
165 COPY_WORD(10);
166 COPY_WORD(11);
167 COPY_WORD(12);
168 COPY_WORD(13);
169 COPY_WORD(14);
170 COPY_WORD(15);
171#elif CHIP_L2_LINE_SIZE() != 64
172# error Fix code that assumes particular L2 cache line sizes
173#endif
174
175 dst8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
176 src8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
177 }
178 }
179
180 for (; n >= sizeof(word_t); n -= sizeof(word_t))
181 ST8(dst8++, LD8(src8++));
182
183 if (__builtin_expect(n == 0, 1))
184 return RETVAL;
185
186 final = LD8(src8);
187 }
188
189 /* n != 0 if we get here. Write out any trailing bytes. */
190 dst1 = (char *)dst8;
191 if (n & 4) {
192 ST4((uint32_t *)dst1, final);
193 dst1 += 4;
194 final >>= 32;
195 n &= 3;
196 }
197 if (n & 2) {
198 ST2((uint16_t *)dst1, final);
199 dst1 += 2;
200 final >>= 16;
201 n &= 1;
202 }
203 if (n)
204 ST1((uint8_t *)dst1, final);
205
206 return RETVAL;
207}
208
209
210#ifdef USERCOPY_FUNC
211#undef ST1
212#undef ST2
213#undef ST4
214#undef ST8
215#undef LD1
216#undef LD2
217#undef LD4
218#undef LD8
219#undef USERCOPY_FUNC
220#endif
diff --git a/arch/tile/lib/memcpy_tile64.c b/arch/tile/lib/memcpy_tile64.c
index dfedea7b266b..b2fe15e01075 100644
--- a/arch/tile/lib/memcpy_tile64.c
+++ b/arch/tile/lib/memcpy_tile64.c
@@ -54,7 +54,7 @@ typedef unsigned long (*memcpy_t)(void *, const void *, unsigned long);
54 * we must run with interrupts disabled to avoid the risk of some 54 * we must run with interrupts disabled to avoid the risk of some
55 * other code seeing the incoherent data in our cache. (Recall that 55 * other code seeing the incoherent data in our cache. (Recall that
56 * our cache is indexed by PA, so even if the other code doesn't use 56 * our cache is indexed by PA, so even if the other code doesn't use
57 * our KM_MEMCPY virtual addresses, they'll still hit in cache using 57 * our kmap_atomic virtual addresses, they'll still hit in cache using
58 * the normal VAs that aren't supposed to hit in cache.) 58 * the normal VAs that aren't supposed to hit in cache.)
59 */ 59 */
60static void memcpy_multicache(void *dest, const void *source, 60static void memcpy_multicache(void *dest, const void *source,
@@ -64,6 +64,7 @@ static void memcpy_multicache(void *dest, const void *source,
64 unsigned long flags, newsrc, newdst; 64 unsigned long flags, newsrc, newdst;
65 pmd_t *pmdp; 65 pmd_t *pmdp;
66 pte_t *ptep; 66 pte_t *ptep;
67 int type0, type1;
67 int cpu = get_cpu(); 68 int cpu = get_cpu();
68 69
69 /* 70 /*
@@ -77,7 +78,8 @@ static void memcpy_multicache(void *dest, const void *source,
77 sim_allow_multiple_caching(1); 78 sim_allow_multiple_caching(1);
78 79
79 /* Set up the new dest mapping */ 80 /* Set up the new dest mapping */
80 idx = FIX_KMAP_BEGIN + (KM_TYPE_NR * cpu) + KM_MEMCPY0; 81 type0 = kmap_atomic_idx_push();
82 idx = FIX_KMAP_BEGIN + (KM_TYPE_NR * cpu) + type0;
81 newdst = __fix_to_virt(idx) + ((unsigned long)dest & (PAGE_SIZE-1)); 83 newdst = __fix_to_virt(idx) + ((unsigned long)dest & (PAGE_SIZE-1));
82 pmdp = pmd_offset(pud_offset(pgd_offset_k(newdst), newdst), newdst); 84 pmdp = pmd_offset(pud_offset(pgd_offset_k(newdst), newdst), newdst);
83 ptep = pte_offset_kernel(pmdp, newdst); 85 ptep = pte_offset_kernel(pmdp, newdst);
@@ -87,13 +89,14 @@ static void memcpy_multicache(void *dest, const void *source,
87 } 89 }
88 90
89 /* Set up the new source mapping */ 91 /* Set up the new source mapping */
90 idx += (KM_MEMCPY0 - KM_MEMCPY1); 92 type1 = kmap_atomic_idx_push();
93 idx += (type0 - type1);
91 src_pte = hv_pte_set_nc(src_pte); 94 src_pte = hv_pte_set_nc(src_pte);
92 src_pte = hv_pte_clear_writable(src_pte); /* be paranoid */ 95 src_pte = hv_pte_clear_writable(src_pte); /* be paranoid */
93 newsrc = __fix_to_virt(idx) + ((unsigned long)source & (PAGE_SIZE-1)); 96 newsrc = __fix_to_virt(idx) + ((unsigned long)source & (PAGE_SIZE-1));
94 pmdp = pmd_offset(pud_offset(pgd_offset_k(newsrc), newsrc), newsrc); 97 pmdp = pmd_offset(pud_offset(pgd_offset_k(newsrc), newsrc), newsrc);
95 ptep = pte_offset_kernel(pmdp, newsrc); 98 ptep = pte_offset_kernel(pmdp, newsrc);
96 *ptep = src_pte; /* set_pte() would be confused by this */ 99 __set_pte(ptep, src_pte); /* set_pte() would be confused by this */
97 local_flush_tlb_page(NULL, newsrc, PAGE_SIZE); 100 local_flush_tlb_page(NULL, newsrc, PAGE_SIZE);
98 101
99 /* Actually move the data. */ 102 /* Actually move the data. */
@@ -106,7 +109,7 @@ static void memcpy_multicache(void *dest, const void *source,
106 */ 109 */
107 src_pte = hv_pte_set_mode(src_pte, HV_PTE_MODE_CACHE_NO_L3); 110 src_pte = hv_pte_set_mode(src_pte, HV_PTE_MODE_CACHE_NO_L3);
108 src_pte = hv_pte_set_writable(src_pte); /* need write access for inv */ 111 src_pte = hv_pte_set_writable(src_pte); /* need write access for inv */
109 *ptep = src_pte; /* set_pte() would be confused by this */ 112 __set_pte(ptep, src_pte); /* set_pte() would be confused by this */
110 local_flush_tlb_page(NULL, newsrc, PAGE_SIZE); 113 local_flush_tlb_page(NULL, newsrc, PAGE_SIZE);
111 114
112 /* 115 /*
@@ -119,6 +122,8 @@ static void memcpy_multicache(void *dest, const void *source,
119 * We're done: notify the simulator that all is back to normal, 122 * We're done: notify the simulator that all is back to normal,
120 * and re-enable interrupts and pre-emption. 123 * and re-enable interrupts and pre-emption.
121 */ 124 */
125 kmap_atomic_idx_pop();
126 kmap_atomic_idx_pop();
122 sim_allow_multiple_caching(0); 127 sim_allow_multiple_caching(0);
123 local_irq_restore(flags); 128 local_irq_restore(flags);
124 put_cpu(); 129 put_cpu();
diff --git a/arch/tile/lib/memcpy_user_64.c b/arch/tile/lib/memcpy_user_64.c
new file mode 100644
index 000000000000..4763b3aff1cc
--- /dev/null
+++ b/arch/tile/lib/memcpy_user_64.c
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Do memcpy(), but trap and return "n" when a load or store faults.
15 *
16 * Note: this idiom only works when memcpy() compiles to a leaf function.
17 * If "sp" is updated during memcpy, the "jrp lr" will be incorrect.
18 *
19 * Also note that we are capturing "n" from the containing scope here.
20 */
21
22#define _ST(p, inst, v) \
23 ({ \
24 asm("1: " #inst " %0, %1;" \
25 ".pushsection .coldtext.memcpy,\"ax\";" \
26 "2: { move r0, %2; jrp lr };" \
27 ".section __ex_table,\"a\";" \
28 ".quad 1b, 2b;" \
29 ".popsection" \
30 : "=m" (*(p)) : "r" (v), "r" (n)); \
31 })
32
33#define _LD(p, inst) \
34 ({ \
35 unsigned long __v; \
36 asm("1: " #inst " %0, %1;" \
37 ".pushsection .coldtext.memcpy,\"ax\";" \
38 "2: { move r0, %2; jrp lr };" \
39 ".section __ex_table,\"a\";" \
40 ".quad 1b, 2b;" \
41 ".popsection" \
42 : "=r" (__v) : "m" (*(p)), "r" (n)); \
43 __v; \
44 })
45
46#define USERCOPY_FUNC __copy_to_user_inatomic
47#define ST1(p, v) _ST((p), st1, (v))
48#define ST2(p, v) _ST((p), st2, (v))
49#define ST4(p, v) _ST((p), st4, (v))
50#define ST8(p, v) _ST((p), st, (v))
51#define LD1 LD
52#define LD2 LD
53#define LD4 LD
54#define LD8 LD
55#include "memcpy_64.c"
56
57#define USERCOPY_FUNC __copy_from_user_inatomic
58#define ST1 ST
59#define ST2 ST
60#define ST4 ST
61#define ST8 ST
62#define LD1(p) _LD((p), ld1u)
63#define LD2(p) _LD((p), ld2u)
64#define LD4(p) _LD((p), ld4u)
65#define LD8(p) _LD((p), ld)
66#include "memcpy_64.c"
67
68#define USERCOPY_FUNC __copy_in_user_inatomic
69#define ST1(p, v) _ST((p), st1, (v))
70#define ST2(p, v) _ST((p), st2, (v))
71#define ST4(p, v) _ST((p), st4, (v))
72#define ST8(p, v) _ST((p), st, (v))
73#define LD1(p) _LD((p), ld1u)
74#define LD2(p) _LD((p), ld2u)
75#define LD4(p) _LD((p), ld4u)
76#define LD8(p) _LD((p), ld)
77#include "memcpy_64.c"
78
79unsigned long __copy_from_user_zeroing(void *to, const void __user *from,
80 unsigned long n)
81{
82 unsigned long rc = __copy_from_user_inatomic(to, from, n);
83 if (unlikely(rc))
84 memset(to + n - rc, 0, rc);
85 return rc;
86}
diff --git a/arch/tile/lib/memmove_32.c b/arch/tile/lib/memmove.c
index fd615ae6ade7..fd615ae6ade7 100644
--- a/arch/tile/lib/memmove_32.c
+++ b/arch/tile/lib/memmove.c
diff --git a/arch/tile/lib/memset_32.c b/arch/tile/lib/memset_32.c
index d014c1fbcbc2..57dbb3a5bff8 100644
--- a/arch/tile/lib/memset_32.c
+++ b/arch/tile/lib/memset_32.c
@@ -18,6 +18,7 @@
18#include <linux/string.h> 18#include <linux/string.h>
19#include <linux/module.h> 19#include <linux/module.h>
20 20
21#undef memset
21 22
22void *memset(void *s, int c, size_t n) 23void *memset(void *s, int c, size_t n)
23{ 24{
diff --git a/arch/tile/lib/memset_64.c b/arch/tile/lib/memset_64.c
new file mode 100644
index 000000000000..3873085711d5
--- /dev/null
+++ b/arch/tile/lib/memset_64.c
@@ -0,0 +1,145 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <arch/chip.h>
16
17#include <linux/types.h>
18#include <linux/string.h>
19#include <linux/module.h>
20
21#undef memset
22
23void *memset(void *s, int c, size_t n)
24{
25 uint64_t *out64;
26 int n64, to_align64;
27 uint64_t v64;
28 uint8_t *out8 = s;
29
30 /* Experimentation shows that a trivial tight loop is a win up until
31 * around a size of 20, where writing a word at a time starts to win.
32 */
33#define BYTE_CUTOFF 20
34
35#if BYTE_CUTOFF < 7
36 /* This must be at least at least this big, or some code later
37 * on doesn't work.
38 */
39#error "BYTE_CUTOFF is too small"
40#endif
41
42 if (n < BYTE_CUTOFF) {
43 /* Strangely, this turns out to be the tightest way to
44 * write this loop.
45 */
46 if (n != 0) {
47 do {
48 /* Strangely, combining these into one line
49 * performs worse.
50 */
51 *out8 = c;
52 out8++;
53 } while (--n != 0);
54 }
55
56 return s;
57 }
58
59 /* Align 'out8'. We know n >= 7 so this won't write past the end. */
60 while (((uintptr_t) out8 & 7) != 0) {
61 *out8++ = c;
62 --n;
63 }
64
65 /* Align 'n'. */
66 while (n & 7)
67 out8[--n] = c;
68
69 out64 = (uint64_t *) out8;
70 n64 = n >> 3;
71
72 /* Tile input byte out to 64 bits. */
73 /* KLUDGE */
74 v64 = 0x0101010101010101ULL * (uint8_t)c;
75
76 /* This must be at least 8 or the following loop doesn't work. */
77#define CACHE_LINE_SIZE_IN_DOUBLEWORDS (CHIP_L2_LINE_SIZE() / 8)
78
79 /* Determine how many words we need to emit before the 'out32'
80 * pointer becomes aligned modulo the cache line size.
81 */
82 to_align64 = (-((uintptr_t)out64 >> 3)) &
83 (CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1);
84
85 /* Only bother aligning and using wh64 if there is at least
86 * one full cache line to process. This check also prevents
87 * overrunning the end of the buffer with alignment words.
88 */
89 if (to_align64 <= n64 - CACHE_LINE_SIZE_IN_DOUBLEWORDS) {
90 int lines_left;
91
92 /* Align out64 mod the cache line size so we can use wh64. */
93 n64 -= to_align64;
94 for (; to_align64 != 0; to_align64--) {
95 *out64 = v64;
96 out64++;
97 }
98
99 /* Use unsigned divide to turn this into a right shift. */
100 lines_left = (unsigned)n64 / CACHE_LINE_SIZE_IN_DOUBLEWORDS;
101
102 do {
103 /* Only wh64 a few lines at a time, so we don't
104 * exceed the maximum number of victim lines.
105 */
106 int x = ((lines_left < CHIP_MAX_OUTSTANDING_VICTIMS())
107 ? lines_left
108 : CHIP_MAX_OUTSTANDING_VICTIMS());
109 uint64_t *wh = out64;
110 int i = x;
111 int j;
112
113 lines_left -= x;
114
115 do {
116 __insn_wh64(wh);
117 wh += CACHE_LINE_SIZE_IN_DOUBLEWORDS;
118 } while (--i);
119
120 for (j = x * (CACHE_LINE_SIZE_IN_DOUBLEWORDS / 4);
121 j != 0; j--) {
122 *out64++ = v64;
123 *out64++ = v64;
124 *out64++ = v64;
125 *out64++ = v64;
126 }
127 } while (lines_left != 0);
128
129 /* We processed all full lines above, so only this many
130 * words remain to be processed.
131 */
132 n64 &= CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1;
133 }
134
135 /* Now handle any leftover values. */
136 if (n64 != 0) {
137 do {
138 *out64 = v64;
139 out64++;
140 } while (--n64 != 0);
141 }
142
143 return s;
144}
145EXPORT_SYMBOL(memset);
diff --git a/arch/tile/lib/spinlock_32.c b/arch/tile/lib/spinlock_32.c
index 485e24d62c6b..cb0999fb64b4 100644
--- a/arch/tile/lib/spinlock_32.c
+++ b/arch/tile/lib/spinlock_32.c
@@ -15,6 +15,7 @@
15#include <linux/spinlock.h> 15#include <linux/spinlock.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <arch/spr_def.h>
18 19
19#include "spinlock_common.h" 20#include "spinlock_common.h"
20 21
@@ -91,75 +92,75 @@ EXPORT_SYMBOL(arch_spin_unlock_wait);
91#define RD_COUNT_MASK ((1 << RD_COUNT_WIDTH) - 1) 92#define RD_COUNT_MASK ((1 << RD_COUNT_WIDTH) - 1)
92 93
93 94
94/* Lock the word, spinning until there are no tns-ers. */ 95/*
95static inline u32 get_rwlock(arch_rwlock_t *rwlock) 96 * We can get the read lock if everything but the reader bits (which
96{ 97 * are in the high part of the word) is zero, i.e. no active or
97 u32 iterations = 0; 98 * waiting writers, no tns.
98 for (;;) { 99 *
99 u32 val = __insn_tns((int *)&rwlock->lock); 100 * We guard the tns/store-back with an interrupt critical section to
100 if (unlikely(val & 1)) { 101 * preserve the semantic that the same read lock can be acquired in an
101 delay_backoff(iterations++); 102 * interrupt context.
102 continue; 103 */
103 } 104inline int arch_read_trylock(arch_rwlock_t *rwlock)
104 return val;
105 }
106}
107
108int arch_read_trylock_slow(arch_rwlock_t *rwlock)
109{
110 u32 val = get_rwlock(rwlock);
111 int locked = (val << RD_COUNT_WIDTH) == 0;
112 rwlock->lock = val + (locked << RD_COUNT_SHIFT);
113 return locked;
114}
115EXPORT_SYMBOL(arch_read_trylock_slow);
116
117void arch_read_unlock_slow(arch_rwlock_t *rwlock)
118{
119 u32 val = get_rwlock(rwlock);
120 rwlock->lock = val - (1 << RD_COUNT_SHIFT);
121}
122EXPORT_SYMBOL(arch_read_unlock_slow);
123
124void arch_write_unlock_slow(arch_rwlock_t *rwlock, u32 val)
125{ 105{
126 u32 eq, mask = 1 << WR_CURR_SHIFT; 106 u32 val;
127 while (unlikely(val & 1)) { 107 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 1);
128 /* Limited backoff since we are the highest-priority task. */ 108 val = __insn_tns((int *)&rwlock->lock);
129 relax(4); 109 if (likely((val << _RD_COUNT_WIDTH) == 0)) {
130 val = __insn_tns((int *)&rwlock->lock); 110 val += 1 << RD_COUNT_SHIFT;
111 rwlock->lock = val;
112 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
113 BUG_ON(val == 0); /* we don't expect wraparound */
114 return 1;
131 } 115 }
132 val = __insn_addb(val, mask); 116 if ((val & 1) == 0)
133 eq = __insn_seqb(val, val << (WR_CURR_SHIFT - WR_NEXT_SHIFT)); 117 rwlock->lock = val;
134 val = __insn_mz(eq & mask, val); 118 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
135 rwlock->lock = val; 119 return 0;
136} 120}
137EXPORT_SYMBOL(arch_write_unlock_slow); 121EXPORT_SYMBOL(arch_read_trylock);
138 122
139/* 123/*
140 * We spin until everything but the reader bits (which are in the high 124 * Spin doing arch_read_trylock() until we acquire the lock.
141 * part of the word) are zero, i.e. no active or waiting writers, no tns.
142 *
143 * ISSUE: This approach can permanently starve readers. A reader who sees 125 * ISSUE: This approach can permanently starve readers. A reader who sees
144 * a writer could instead take a ticket lock (just like a writer would), 126 * a writer could instead take a ticket lock (just like a writer would),
145 * and atomically enter read mode (with 1 reader) when it gets the ticket. 127 * and atomically enter read mode (with 1 reader) when it gets the ticket.
146 * This way both readers and writers will always make forward progress 128 * This way both readers and writers would always make forward progress
147 * in a finite time. 129 * in a finite time.
148 */ 130 */
149void arch_read_lock_slow(arch_rwlock_t *rwlock, u32 val) 131void arch_read_lock(arch_rwlock_t *rwlock)
150{ 132{
151 u32 iterations = 0; 133 u32 iterations = 0;
152 do { 134 while (unlikely(!arch_read_trylock(rwlock)))
153 if (!(val & 1))
154 rwlock->lock = val;
155 delay_backoff(iterations++); 135 delay_backoff(iterations++);
136}
137EXPORT_SYMBOL(arch_read_lock);
138
139void arch_read_unlock(arch_rwlock_t *rwlock)
140{
141 u32 val, iterations = 0;
142
143 mb(); /* guarantee anything modified under the lock is visible */
144 for (;;) {
145 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 1);
156 val = __insn_tns((int *)&rwlock->lock); 146 val = __insn_tns((int *)&rwlock->lock);
157 } while ((val << RD_COUNT_WIDTH) != 0); 147 if (likely(val & 1) == 0) {
158 rwlock->lock = val + (1 << RD_COUNT_SHIFT); 148 rwlock->lock = val - (1 << _RD_COUNT_SHIFT);
149 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
150 break;
151 }
152 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
153 delay_backoff(iterations++);
154 }
159} 155}
160EXPORT_SYMBOL(arch_read_lock_slow); 156EXPORT_SYMBOL(arch_read_unlock);
161 157
162void arch_write_lock_slow(arch_rwlock_t *rwlock, u32 val) 158/*
159 * We don't need an interrupt critical section here (unlike for
160 * arch_read_lock) since we should never use a bare write lock where
161 * it could be interrupted by code that could try to re-acquire it.
162 */
163void arch_write_lock(arch_rwlock_t *rwlock)
163{ 164{
164 /* 165 /*
165 * The trailing underscore on this variable (and curr_ below) 166 * The trailing underscore on this variable (and curr_ below)
@@ -167,23 +168,36 @@ void arch_write_lock_slow(arch_rwlock_t *rwlock, u32 val)
167 * when we compare them. 168 * when we compare them.
168 */ 169 */
169 u32 my_ticket_; 170 u32 my_ticket_;
171 u32 iterations = 0;
172 u32 val = __insn_tns((int *)&rwlock->lock);
170 173
171 /* Take out the next ticket; this will also stop would-be readers. */ 174 if (likely(val == 0)) {
172 if (val & 1) 175 rwlock->lock = 1 << _WR_NEXT_SHIFT;
173 val = get_rwlock(rwlock); 176 return;
174 rwlock->lock = __insn_addb(val, 1 << WR_NEXT_SHIFT); 177 }
175
176 /* Extract my ticket value from the original word. */
177 my_ticket_ = val >> WR_NEXT_SHIFT;
178 178
179 /* 179 /*
180 * Wait until the "current" field matches our ticket, and 180 * Wait until there are no readers, then bump up the next
181 * there are no remaining readers. 181 * field and capture the ticket value.
182 */ 182 */
183 for (;;) { 183 for (;;) {
184 if (!(val & 1)) {
185 if ((val >> RD_COUNT_SHIFT) == 0)
186 break;
187 rwlock->lock = val;
188 }
189 delay_backoff(iterations++);
190 val = __insn_tns((int *)&rwlock->lock);
191 }
192
193 /* Take out the next ticket and extract my ticket value. */
194 rwlock->lock = __insn_addb(val, 1 << WR_NEXT_SHIFT);
195 my_ticket_ = val >> WR_NEXT_SHIFT;
196
197 /* Wait until the "current" field matches our ticket. */
198 for (;;) {
184 u32 curr_ = val >> WR_CURR_SHIFT; 199 u32 curr_ = val >> WR_CURR_SHIFT;
185 u32 readers = val >> RD_COUNT_SHIFT; 200 u32 delta = ((my_ticket_ - curr_) & WR_MASK);
186 u32 delta = ((my_ticket_ - curr_) & WR_MASK) + !!readers;
187 if (likely(delta == 0)) 201 if (likely(delta == 0))
188 break; 202 break;
189 203
@@ -199,23 +213,47 @@ void arch_write_lock_slow(arch_rwlock_t *rwlock, u32 val)
199 relax(4); 213 relax(4);
200 } 214 }
201} 215}
202EXPORT_SYMBOL(arch_write_lock_slow); 216EXPORT_SYMBOL(arch_write_lock);
203 217
204int __tns_atomic_acquire(atomic_t *lock) 218int arch_write_trylock(arch_rwlock_t *rwlock)
205{ 219{
206 int ret; 220 u32 val = __insn_tns((int *)&rwlock->lock);
207 u32 iterations = 0;
208 221
209 BUG_ON(__insn_mfspr(SPR_INTERRUPT_CRITICAL_SECTION)); 222 /*
210 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 1); 223 * If a tns is in progress, or there's a waiting or active locker,
224 * or active readers, we can't take the lock, so give up.
225 */
226 if (unlikely(val != 0)) {
227 if (!(val & 1))
228 rwlock->lock = val;
229 return 0;
230 }
211 231
212 while ((ret = __insn_tns((void *)&lock->counter)) == 1) 232 /* Set the "next" field to mark it locked. */
213 delay_backoff(iterations++); 233 rwlock->lock = 1 << _WR_NEXT_SHIFT;
214 return ret; 234 return 1;
215} 235}
236EXPORT_SYMBOL(arch_write_trylock);
216 237
217void __tns_atomic_release(atomic_t *p, int v) 238void arch_write_unlock(arch_rwlock_t *rwlock)
218{ 239{
219 p->counter = v; 240 u32 val, eq, mask;
220 __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0); 241
242 mb(); /* guarantee anything modified under the lock is visible */
243 val = __insn_tns((int *)&rwlock->lock);
244 if (likely(val == (1 << _WR_NEXT_SHIFT))) {
245 rwlock->lock = 0;
246 return;
247 }
248 while (unlikely(val & 1)) {
249 /* Limited backoff since we are the highest-priority task. */
250 relax(4);
251 val = __insn_tns((int *)&rwlock->lock);
252 }
253 mask = 1 << WR_CURR_SHIFT;
254 val = __insn_addb(val, mask);
255 eq = __insn_seqb(val, val << (WR_CURR_SHIFT - WR_NEXT_SHIFT));
256 val = __insn_mz(eq & mask, val);
257 rwlock->lock = val;
221} 258}
259EXPORT_SYMBOL(arch_write_unlock);
diff --git a/arch/tile/lib/spinlock_64.c b/arch/tile/lib/spinlock_64.c
new file mode 100644
index 000000000000..d6fb9581e980
--- /dev/null
+++ b/arch/tile/lib/spinlock_64.c
@@ -0,0 +1,104 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/spinlock.h>
16#include <linux/module.h>
17#include <asm/processor.h>
18
19#include "spinlock_common.h"
20
21/*
22 * Read the spinlock value without allocating in our cache and without
23 * causing an invalidation to another cpu with a copy of the cacheline.
24 * This is important when we are spinning waiting for the lock.
25 */
26static inline u32 arch_spin_read_noalloc(void *lock)
27{
28 return atomic_cmpxchg((atomic_t *)lock, -1, -1);
29}
30
31/*
32 * Wait until the high bits (current) match my ticket.
33 * If we notice the overflow bit set on entry, we clear it.
34 */
35void arch_spin_lock_slow(arch_spinlock_t *lock, u32 my_ticket)
36{
37 if (unlikely(my_ticket & __ARCH_SPIN_NEXT_OVERFLOW)) {
38 __insn_fetchand4(&lock->lock, ~__ARCH_SPIN_NEXT_OVERFLOW);
39 my_ticket &= ~__ARCH_SPIN_NEXT_OVERFLOW;
40 }
41
42 for (;;) {
43 u32 val = arch_spin_read_noalloc(lock);
44 u32 delta = my_ticket - arch_spin_current(val);
45 if (delta == 0)
46 return;
47 relax((128 / CYCLES_PER_RELAX_LOOP) * delta);
48 }
49}
50EXPORT_SYMBOL(arch_spin_lock_slow);
51
52/*
53 * Check the lock to see if it is plausible, and try to get it with cmpxchg().
54 */
55int arch_spin_trylock(arch_spinlock_t *lock)
56{
57 u32 val = arch_spin_read_noalloc(lock);
58 if (unlikely(arch_spin_current(val) != arch_spin_next(val)))
59 return 0;
60 return cmpxchg(&lock->lock, val, (val + 1) & ~__ARCH_SPIN_NEXT_OVERFLOW)
61 == val;
62}
63EXPORT_SYMBOL(arch_spin_trylock);
64
65void arch_spin_unlock_wait(arch_spinlock_t *lock)
66{
67 u32 iterations = 0;
68 while (arch_spin_is_locked(lock))
69 delay_backoff(iterations++);
70}
71EXPORT_SYMBOL(arch_spin_unlock_wait);
72
73/*
74 * If the read lock fails due to a writer, we retry periodically
75 * until the value is positive and we write our incremented reader count.
76 */
77void __read_lock_failed(arch_rwlock_t *rw)
78{
79 u32 val;
80 int iterations = 0;
81 do {
82 delay_backoff(iterations++);
83 val = __insn_fetchaddgez4(&rw->lock, 1);
84 } while (unlikely(arch_write_val_locked(val)));
85}
86EXPORT_SYMBOL(__read_lock_failed);
87
88/*
89 * If we failed because there were readers, clear the "writer" bit
90 * so we don't block additional readers. Otherwise, there was another
91 * writer anyway, so our "fetchor" made no difference. Then wait,
92 * issuing periodic fetchor instructions, till we get the lock.
93 */
94void __write_lock_failed(arch_rwlock_t *rw, u32 val)
95{
96 int iterations = 0;
97 do {
98 if (!arch_write_val_locked(val))
99 val = __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
100 delay_backoff(iterations++);
101 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
102 } while (val != 0);
103}
104EXPORT_SYMBOL(__write_lock_failed);
diff --git a/arch/tile/lib/strchr_64.c b/arch/tile/lib/strchr_64.c
new file mode 100644
index 000000000000..617a9273aaa8
--- /dev/null
+++ b/arch/tile/lib/strchr_64.c
@@ -0,0 +1,67 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18
19#undef strchr
20
21char *strchr(const char *s, int c)
22{
23 int z, g;
24
25 /* Get an aligned pointer. */
26 const uintptr_t s_int = (uintptr_t) s;
27 const uint64_t *p = (const uint64_t *)(s_int & -8);
28
29 /* Create eight copies of the byte for which we are looking. */
30 const uint64_t goal = 0x0101010101010101ULL * (uint8_t) c;
31
32 /* Read the first aligned word, but force bytes before the string to
33 * match neither zero nor goal (we make sure the high bit of each
34 * byte is 1, and the low 7 bits are all the opposite of the goal
35 * byte).
36 *
37 * Note that this shift count expression works because we know shift
38 * counts are taken mod 64.
39 */
40 const uint64_t before_mask = (1ULL << (s_int << 3)) - 1;
41 uint64_t v = (*p | before_mask) ^
42 (goal & __insn_v1shrsi(before_mask, 1));
43
44 uint64_t zero_matches, goal_matches;
45 while (1) {
46 /* Look for a terminating '\0'. */
47 zero_matches = __insn_v1cmpeqi(v, 0);
48
49 /* Look for the goal byte. */
50 goal_matches = __insn_v1cmpeq(v, goal);
51
52 if (__builtin_expect((zero_matches | goal_matches) != 0, 0))
53 break;
54
55 v = *++p;
56 }
57
58 z = __insn_ctz(zero_matches);
59 g = __insn_ctz(goal_matches);
60
61 /* If we found c before '\0' we got a match. Note that if c == '\0'
62 * then g == z, and we correctly return the address of the '\0'
63 * rather than NULL.
64 */
65 return (g <= z) ? ((char *)p) + (g >> 3) : NULL;
66}
67EXPORT_SYMBOL(strchr);
diff --git a/arch/tile/lib/strlen_32.c b/arch/tile/lib/strlen_32.c
index f26f88e11e4a..4974292a5534 100644
--- a/arch/tile/lib/strlen_32.c
+++ b/arch/tile/lib/strlen_32.c
@@ -16,6 +16,8 @@
16#include <linux/string.h> 16#include <linux/string.h>
17#include <linux/module.h> 17#include <linux/module.h>
18 18
19#undef strlen
20
19size_t strlen(const char *s) 21size_t strlen(const char *s)
20{ 22{
21 /* Get an aligned pointer. */ 23 /* Get an aligned pointer. */
diff --git a/arch/tile/lib/strlen_64.c b/arch/tile/lib/strlen_64.c
new file mode 100644
index 000000000000..1c92d46202a8
--- /dev/null
+++ b/arch/tile/lib/strlen_64.c
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/types.h>
16#include <linux/string.h>
17#include <linux/module.h>
18
19#undef strlen
20
21size_t strlen(const char *s)
22{
23 /* Get an aligned pointer. */
24 const uintptr_t s_int = (uintptr_t) s;
25 const uint64_t *p = (const uint64_t *)(s_int & -8);
26
27 /* Read the first word, but force bytes before the string to be nonzero.
28 * This expression works because we know shift counts are taken mod 64.
29 */
30 uint64_t v = *p | ((1ULL << (s_int << 3)) - 1);
31
32 uint64_t bits;
33 while ((bits = __insn_v1cmpeqi(v, 0)) == 0)
34 v = *++p;
35
36 return ((const char *)p) + (__insn_ctz(bits) >> 3) - s;
37}
38EXPORT_SYMBOL(strlen);
diff --git a/arch/tile/lib/usercopy_64.S b/arch/tile/lib/usercopy_64.S
new file mode 100644
index 000000000000..2ff44f87b78e
--- /dev/null
+++ b/arch/tile/lib/usercopy_64.S
@@ -0,0 +1,196 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/linkage.h>
16#include <asm/errno.h>
17#include <asm/cache.h>
18#include <arch/chip.h>
19
20/* Access user memory, but use MMU to avoid propagating kernel exceptions. */
21
22 .pushsection .fixup,"ax"
23
24get_user_fault:
25 { movei r1, -EFAULT; move r0, zero }
26 jrp lr
27 ENDPROC(get_user_fault)
28
29put_user_fault:
30 { movei r0, -EFAULT; jrp lr }
31 ENDPROC(put_user_fault)
32
33 .popsection
34
35/*
36 * __get_user_N functions take a pointer in r0, and return 0 in r1
37 * on success, with the value in r0; or else -EFAULT in r1.
38 */
39#define __get_user_N(bytes, LOAD) \
40 STD_ENTRY(__get_user_##bytes); \
411: { LOAD r0, r0; move r1, zero }; \
42 jrp lr; \
43 STD_ENDPROC(__get_user_##bytes); \
44 .pushsection __ex_table,"a"; \
45 .quad 1b, get_user_fault; \
46 .popsection
47
48__get_user_N(1, ld1u)
49__get_user_N(2, ld2u)
50__get_user_N(4, ld4u)
51__get_user_N(8, ld)
52
53/*
54 * __put_user_N functions take a value in r0 and a pointer in r1,
55 * and return 0 in r0 on success or -EFAULT on failure.
56 */
57#define __put_user_N(bytes, STORE) \
58 STD_ENTRY(__put_user_##bytes); \
591: { STORE r1, r0; move r0, zero }; \
60 jrp lr; \
61 STD_ENDPROC(__put_user_##bytes); \
62 .pushsection __ex_table,"a"; \
63 .quad 1b, put_user_fault; \
64 .popsection
65
66__put_user_N(1, st1)
67__put_user_N(2, st2)
68__put_user_N(4, st4)
69__put_user_N(8, st)
70
71/*
72 * strnlen_user_asm takes the pointer in r0, and the length bound in r1.
73 * It returns the length, including the terminating NUL, or zero on exception.
74 * If length is greater than the bound, returns one plus the bound.
75 */
76STD_ENTRY(strnlen_user_asm)
77 { beqz r1, 2f; addi r3, r0, -1 } /* bias down to include NUL */
781: { ld1u r4, r0; addi r1, r1, -1 }
79 beqz r4, 2f
80 { bnezt r1, 1b; addi r0, r0, 1 }
812: { sub r0, r0, r3; jrp lr }
82 STD_ENDPROC(strnlen_user_asm)
83 .pushsection .fixup,"ax"
84strnlen_user_fault:
85 { move r0, zero; jrp lr }
86 ENDPROC(strnlen_user_fault)
87 .section __ex_table,"a"
88 .quad 1b, strnlen_user_fault
89 .popsection
90
91/*
92 * strncpy_from_user_asm takes the kernel target pointer in r0,
93 * the userspace source pointer in r1, and the length bound (including
94 * the trailing NUL) in r2. On success, it returns the string length
95 * (not including the trailing NUL), or -EFAULT on failure.
96 */
97STD_ENTRY(strncpy_from_user_asm)
98 { beqz r2, 2f; move r3, r0 }
991: { ld1u r4, r1; addi r1, r1, 1; addi r2, r2, -1 }
100 { st1 r0, r4; addi r0, r0, 1 }
101 beqz r2, 2f
102 bnezt r4, 1b
103 addi r0, r0, -1 /* don't count the trailing NUL */
1042: { sub r0, r0, r3; jrp lr }
105 STD_ENDPROC(strncpy_from_user_asm)
106 .pushsection .fixup,"ax"
107strncpy_from_user_fault:
108 { movei r0, -EFAULT; jrp lr }
109 ENDPROC(strncpy_from_user_fault)
110 .section __ex_table,"a"
111 .quad 1b, strncpy_from_user_fault
112 .popsection
113
114/*
115 * clear_user_asm takes the user target address in r0 and the
116 * number of bytes to zero in r1.
117 * It returns the number of uncopiable bytes (hopefully zero) in r0.
118 * Note that we don't use a separate .fixup section here since we fall
119 * through into the "fixup" code as the last straight-line bundle anyway.
120 */
121STD_ENTRY(clear_user_asm)
122 { beqz r1, 2f; or r2, r0, r1 }
123 andi r2, r2, 7
124 beqzt r2, .Lclear_aligned_user_asm
1251: { st1 r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
126 bnezt r1, 1b
1272: { move r0, r1; jrp lr }
128 .pushsection __ex_table,"a"
129 .quad 1b, 2b
130 .popsection
131
132.Lclear_aligned_user_asm:
1331: { st r0, zero; addi r0, r0, 8; addi r1, r1, -8 }
134 bnezt r1, 1b
1352: { move r0, r1; jrp lr }
136 STD_ENDPROC(clear_user_asm)
137 .pushsection __ex_table,"a"
138 .quad 1b, 2b
139 .popsection
140
141/*
142 * flush_user_asm takes the user target address in r0 and the
143 * number of bytes to flush in r1.
144 * It returns the number of unflushable bytes (hopefully zero) in r0.
145 */
146STD_ENTRY(flush_user_asm)
147 beqz r1, 2f
148 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
149 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
150 { and r0, r0, r2; and r1, r1, r2 }
151 { sub r1, r1, r0 }
1521: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
153 { addi r0, r0, CHIP_FLUSH_STRIDE(); bnezt r1, 1b }
1542: { move r0, r1; jrp lr }
155 STD_ENDPROC(flush_user_asm)
156 .pushsection __ex_table,"a"
157 .quad 1b, 2b
158 .popsection
159
160/*
161 * inv_user_asm takes the user target address in r0 and the
162 * number of bytes to invalidate in r1.
163 * It returns the number of not inv'able bytes (hopefully zero) in r0.
164 */
165STD_ENTRY(inv_user_asm)
166 beqz r1, 2f
167 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
168 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
169 { and r0, r0, r2; and r1, r1, r2 }
170 { sub r1, r1, r0 }
1711: { inv r0; addi r1, r1, -CHIP_INV_STRIDE() }
172 { addi r0, r0, CHIP_INV_STRIDE(); bnezt r1, 1b }
1732: { move r0, r1; jrp lr }
174 STD_ENDPROC(inv_user_asm)
175 .pushsection __ex_table,"a"
176 .quad 1b, 2b
177 .popsection
178
179/*
180 * finv_user_asm takes the user target address in r0 and the
181 * number of bytes to flush-invalidate in r1.
182 * It returns the number of not finv'able bytes (hopefully zero) in r0.
183 */
184STD_ENTRY(finv_user_asm)
185 beqz r1, 2f
186 { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
187 { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
188 { and r0, r0, r2; and r1, r1, r2 }
189 { sub r1, r1, r0 }
1901: { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
191 { addi r0, r0, CHIP_FINV_STRIDE(); bnezt r1, 1b }
1922: { move r0, r1; jrp lr }
193 STD_ENDPROC(finv_user_asm)
194 .pushsection __ex_table,"a"
195 .quad 1b, 2b
196 .popsection
diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c
index 704f3e8a4385..25b7b90fd620 100644
--- a/arch/tile/mm/fault.c
+++ b/arch/tile/mm/fault.c
@@ -24,7 +24,6 @@
24#include <linux/mman.h> 24#include <linux/mman.h>
25#include <linux/mm.h> 25#include <linux/mm.h>
26#include <linux/smp.h> 26#include <linux/smp.h>
27#include <linux/smp_lock.h>
28#include <linux/interrupt.h> 27#include <linux/interrupt.h>
29#include <linux/init.h> 28#include <linux/init.h>
30#include <linux/tty.h> 29#include <linux/tty.h>
@@ -44,8 +43,11 @@
44 43
45#include <arch/interrupts.h> 44#include <arch/interrupts.h>
46 45
47static noinline void force_sig_info_fault(int si_signo, int si_code, 46static noinline void force_sig_info_fault(const char *type, int si_signo,
48 unsigned long address, int fault_num, struct task_struct *tsk) 47 int si_code, unsigned long address,
48 int fault_num,
49 struct task_struct *tsk,
50 struct pt_regs *regs)
49{ 51{
50 siginfo_t info; 52 siginfo_t info;
51 53
@@ -60,23 +62,25 @@ static noinline void force_sig_info_fault(int si_signo, int si_code,
60 info.si_code = si_code; 62 info.si_code = si_code;
61 info.si_addr = (void __user *)address; 63 info.si_addr = (void __user *)address;
62 info.si_trapno = fault_num; 64 info.si_trapno = fault_num;
65 trace_unhandled_signal(type, regs, address, si_signo);
63 force_sig_info(si_signo, &info, tsk); 66 force_sig_info(si_signo, &info, tsk);
64} 67}
65 68
66#ifndef __tilegx__ 69#ifndef __tilegx__
67/* 70/*
68 * Synthesize the fault a PL0 process would get by doing a word-load of 71 * Synthesize the fault a PL0 process would get by doing a word-load of
69 * an unaligned address or a high kernel address. Called indirectly 72 * an unaligned address or a high kernel address.
70 * from sys_cmpxchg() in kernel/intvec.S.
71 */ 73 */
72int _sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *regs) 74SYSCALL_DEFINE2(cmpxchg_badaddr, unsigned long, address,
75 struct pt_regs *, regs)
73{ 76{
74 if (address >= PAGE_OFFSET) 77 if (address >= PAGE_OFFSET)
75 force_sig_info_fault(SIGSEGV, SEGV_MAPERR, address, 78 force_sig_info_fault("atomic segfault", SIGSEGV, SEGV_MAPERR,
76 INT_DTLB_MISS, current); 79 address, INT_DTLB_MISS, current, regs);
77 else 80 else
78 force_sig_info_fault(SIGBUS, BUS_ADRALN, address, 81 force_sig_info_fault("atomic alignment fault", SIGBUS,
79 INT_UNALIGN_DATA, current); 82 BUS_ADRALN, address,
83 INT_UNALIGN_DATA, current, regs);
80 84
81 /* 85 /*
82 * Adjust pc to point at the actual instruction, which is unusual 86 * Adjust pc to point at the actual instruction, which is unusual
@@ -291,7 +295,7 @@ static int handle_page_fault(struct pt_regs *regs,
291 /* 295 /*
292 * Early on, we need to check for migrating PTE entries; 296 * Early on, we need to check for migrating PTE entries;
293 * see homecache.c. If we find a migrating PTE, we wait until 297 * see homecache.c. If we find a migrating PTE, we wait until
294 * the backing page claims to be done migrating, then we procede. 298 * the backing page claims to be done migrating, then we proceed.
295 * For kernel PTEs, we rewrite the PTE and return and retry. 299 * For kernel PTEs, we rewrite the PTE and return and retry.
296 * Otherwise, we treat the fault like a normal "no PTE" fault, 300 * Otherwise, we treat the fault like a normal "no PTE" fault,
297 * rather than trying to patch up the existing PTE. 301 * rather than trying to patch up the existing PTE.
@@ -472,8 +476,8 @@ bad_area_nosemaphore:
472 */ 476 */
473 local_irq_enable(); 477 local_irq_enable();
474 478
475 force_sig_info_fault(SIGSEGV, si_code, address, 479 force_sig_info_fault("segfault", SIGSEGV, si_code, address,
476 fault_num, tsk); 480 fault_num, tsk, regs);
477 return 0; 481 return 0;
478 } 482 }
479 483
@@ -548,7 +552,8 @@ do_sigbus:
548 if (is_kernel_mode) 552 if (is_kernel_mode)
549 goto no_context; 553 goto no_context;
550 554
551 force_sig_info_fault(SIGBUS, BUS_ADRERR, address, fault_num, tsk); 555 force_sig_info_fault("bus error", SIGBUS, BUS_ADRERR, address,
556 fault_num, tsk, regs);
552 return 0; 557 return 0;
553} 558}
554 559
@@ -563,10 +568,10 @@ do_sigbus:
563/* 568/*
564 * When we take an ITLB or DTLB fault or access violation in the 569 * When we take an ITLB or DTLB fault or access violation in the
565 * supervisor while the critical section bit is set, the hypervisor is 570 * supervisor while the critical section bit is set, the hypervisor is
566 * reluctant to write new values into the EX_CONTEXT_1_x registers, 571 * reluctant to write new values into the EX_CONTEXT_K_x registers,
567 * since that might indicate we have not yet squirreled the SPR 572 * since that might indicate we have not yet squirreled the SPR
568 * contents away and can thus safely take a recursive interrupt. 573 * contents away and can thus safely take a recursive interrupt.
569 * Accordingly, the hypervisor passes us the PC via SYSTEM_SAVE_1_2. 574 * Accordingly, the hypervisor passes us the PC via SYSTEM_SAVE_K_2.
570 * 575 *
571 * Note that this routine is called before homecache_tlb_defer_enter(), 576 * Note that this routine is called before homecache_tlb_defer_enter(),
572 * which means that we can properly unlock any atomics that might 577 * which means that we can properly unlock any atomics that might
@@ -610,7 +615,7 @@ struct intvec_state do_page_fault_ics(struct pt_regs *regs, int fault_num,
610 * fault. We didn't set up a kernel stack on initial entry to 615 * fault. We didn't set up a kernel stack on initial entry to
611 * sys_cmpxchg, but instead had one set up by the fault, which 616 * sys_cmpxchg, but instead had one set up by the fault, which
612 * (because sys_cmpxchg never releases ICS) came to us via the 617 * (because sys_cmpxchg never releases ICS) came to us via the
613 * SYSTEM_SAVE_1_2 mechanism, and thus EX_CONTEXT_1_[01] are 618 * SYSTEM_SAVE_K_2 mechanism, and thus EX_CONTEXT_K_[01] are
614 * still referencing the original user code. We release the 619 * still referencing the original user code. We release the
615 * atomic lock and rewrite pt_regs so that it appears that we 620 * atomic lock and rewrite pt_regs so that it appears that we
616 * came from user-space directly, and after we finish the 621 * came from user-space directly, and after we finish the
@@ -656,14 +661,6 @@ struct intvec_state do_page_fault_ics(struct pt_regs *regs, int fault_num,
656 } 661 }
657 662
658 /* 663 /*
659 * NOTE: the one other type of access that might bring us here
660 * are the memory ops in __tns_atomic_acquire/__tns_atomic_release,
661 * but we don't have to check specially for them since we can
662 * always safely return to the address of the fault and retry,
663 * since no separate atomic locks are involved.
664 */
665
666 /*
667 * Now that we have released the atomic lock (if necessary), 664 * Now that we have released the atomic lock (if necessary),
668 * it's safe to spin if the PTE that caused the fault was migrating. 665 * it's safe to spin if the PTE that caused the fault was migrating.
669 */ 666 */
@@ -741,6 +738,7 @@ void do_page_fault(struct pt_regs *regs, int fault_num,
741 panic("Bad fault number %d in do_page_fault", fault_num); 738 panic("Bad fault number %d in do_page_fault", fault_num);
742 } 739 }
743 740
741#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
744 if (EX1_PL(regs->ex1) != USER_PL) { 742 if (EX1_PL(regs->ex1) != USER_PL) {
745 struct async_tlb *async; 743 struct async_tlb *async;
746 switch (fault_num) { 744 switch (fault_num) {
@@ -784,6 +782,7 @@ void do_page_fault(struct pt_regs *regs, int fault_num,
784 return; 782 return;
785 } 783 }
786 } 784 }
785#endif
787 786
788 handle_page_fault(regs, fault_num, is_page_fault, address, write); 787 handle_page_fault(regs, fault_num, is_page_fault, address, write);
789} 788}
@@ -810,8 +809,6 @@ static void handle_async_page_fault(struct pt_regs *regs,
810 async->address, async->is_write); 809 async->address, async->is_write);
811 } 810 }
812} 811}
813#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
814
815 812
816/* 813/*
817 * This routine effectively re-issues asynchronous page faults 814 * This routine effectively re-issues asynchronous page faults
@@ -833,6 +830,8 @@ void do_async_page_fault(struct pt_regs *regs)
833 handle_async_page_fault(regs, &current->thread.sn_async_tlb); 830 handle_async_page_fault(regs, &current->thread.sn_async_tlb);
834#endif 831#endif
835} 832}
833#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
834
836 835
837void vmalloc_sync_all(void) 836void vmalloc_sync_all(void)
838{ 837{
diff --git a/arch/tile/mm/highmem.c b/arch/tile/mm/highmem.c
index 12ab137e7d4f..31dbbd9afe47 100644
--- a/arch/tile/mm/highmem.c
+++ b/arch/tile/mm/highmem.c
@@ -56,50 +56,6 @@ void kunmap(struct page *page)
56} 56}
57EXPORT_SYMBOL(kunmap); 57EXPORT_SYMBOL(kunmap);
58 58
59static void debug_kmap_atomic_prot(enum km_type type)
60{
61#ifdef CONFIG_DEBUG_HIGHMEM
62 static unsigned warn_count = 10;
63
64 if (unlikely(warn_count == 0))
65 return;
66
67 if (unlikely(in_interrupt())) {
68 if (in_irq()) {
69 if (type != KM_IRQ0 && type != KM_IRQ1 &&
70 type != KM_BIO_SRC_IRQ &&
71 /* type != KM_BIO_DST_IRQ && */
72 type != KM_BOUNCE_READ) {
73 WARN_ON(1);
74 warn_count--;
75 }
76 } else if (!irqs_disabled()) { /* softirq */
77 if (type != KM_IRQ0 && type != KM_IRQ1 &&
78 type != KM_SOFTIRQ0 && type != KM_SOFTIRQ1 &&
79 type != KM_SKB_SUNRPC_DATA &&
80 type != KM_SKB_DATA_SOFTIRQ &&
81 type != KM_BOUNCE_READ) {
82 WARN_ON(1);
83 warn_count--;
84 }
85 }
86 }
87
88 if (type == KM_IRQ0 || type == KM_IRQ1 || type == KM_BOUNCE_READ ||
89 type == KM_BIO_SRC_IRQ /* || type == KM_BIO_DST_IRQ */) {
90 if (!irqs_disabled()) {
91 WARN_ON(1);
92 warn_count--;
93 }
94 } else if (type == KM_SOFTIRQ0 || type == KM_SOFTIRQ1) {
95 if (irq_count() == 0 && !irqs_disabled()) {
96 WARN_ON(1);
97 warn_count--;
98 }
99 }
100#endif
101}
102
103/* 59/*
104 * Describe a single atomic mapping of a page on a given cpu at a 60 * Describe a single atomic mapping of a page on a given cpu at a
105 * given address, and allow it to be linked into a list. 61 * given address, and allow it to be linked into a list.
@@ -240,10 +196,10 @@ void kmap_atomic_fix_kpte(struct page *page, int finished)
240 * When holding an atomic kmap is is not legal to sleep, so atomic 196 * When holding an atomic kmap is is not legal to sleep, so atomic
241 * kmaps are appropriate for short, tight code paths only. 197 * kmaps are appropriate for short, tight code paths only.
242 */ 198 */
243void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot) 199void *kmap_atomic_prot(struct page *page, pgprot_t prot)
244{ 200{
245 enum fixed_addresses idx;
246 unsigned long vaddr; 201 unsigned long vaddr;
202 int idx, type;
247 pte_t *pte; 203 pte_t *pte;
248 204
249 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ 205 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
@@ -255,8 +211,7 @@ void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
255 if (!PageHighMem(page)) 211 if (!PageHighMem(page))
256 return page_address(page); 212 return page_address(page);
257 213
258 debug_kmap_atomic_prot(type); 214 type = kmap_atomic_idx_push();
259
260 idx = type + KM_TYPE_NR*smp_processor_id(); 215 idx = type + KM_TYPE_NR*smp_processor_id();
261 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); 216 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
262 pte = kmap_get_pte(vaddr); 217 pte = kmap_get_pte(vaddr);
@@ -269,28 +224,35 @@ void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
269} 224}
270EXPORT_SYMBOL(kmap_atomic_prot); 225EXPORT_SYMBOL(kmap_atomic_prot);
271 226
272void *kmap_atomic(struct page *page, enum km_type type) 227void *__kmap_atomic(struct page *page)
273{ 228{
274 /* PAGE_NONE is a magic value that tells us to check immutability. */ 229 /* PAGE_NONE is a magic value that tells us to check immutability. */
275 return kmap_atomic_prot(page, type, PAGE_NONE); 230 return kmap_atomic_prot(page, PAGE_NONE);
276} 231}
277EXPORT_SYMBOL(kmap_atomic); 232EXPORT_SYMBOL(__kmap_atomic);
278 233
279void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type) 234void __kunmap_atomic(void *kvaddr)
280{ 235{
281 unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; 236 unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
282 enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
283 237
284 /* 238 if (vaddr >= __fix_to_virt(FIX_KMAP_END) &&
285 * Force other mappings to Oops if they try to access this pte without 239 vaddr <= __fix_to_virt(FIX_KMAP_BEGIN)) {
286 * first remapping it. Keeping stale mappings around is a bad idea.
287 */
288 if (vaddr == __fix_to_virt(FIX_KMAP_BEGIN+idx)) {
289 pte_t *pte = kmap_get_pte(vaddr); 240 pte_t *pte = kmap_get_pte(vaddr);
290 pte_t pteval = *pte; 241 pte_t pteval = *pte;
242 int idx, type;
243
244 type = kmap_atomic_idx();
245 idx = type + KM_TYPE_NR*smp_processor_id();
246
247 /*
248 * Force other mappings to Oops if they try to access this pte
249 * without first remapping it. Keeping stale mappings around
250 * is a bad idea.
251 */
291 BUG_ON(!pte_present(pteval) && !pte_migrating(pteval)); 252 BUG_ON(!pte_present(pteval) && !pte_migrating(pteval));
292 kmap_atomic_unregister(pte_page(pteval), vaddr); 253 kmap_atomic_unregister(pte_page(pteval), vaddr);
293 kpte_clear_flush(pte, vaddr); 254 kpte_clear_flush(pte, vaddr);
255 kmap_atomic_idx_pop();
294 } else { 256 } else {
295 /* Must be a lowmem page */ 257 /* Must be a lowmem page */
296 BUG_ON(vaddr < PAGE_OFFSET); 258 BUG_ON(vaddr < PAGE_OFFSET);
@@ -300,19 +262,19 @@ void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type)
300 arch_flush_lazy_mmu_mode(); 262 arch_flush_lazy_mmu_mode();
301 pagefault_enable(); 263 pagefault_enable();
302} 264}
303EXPORT_SYMBOL(kunmap_atomic_notypecheck); 265EXPORT_SYMBOL(__kunmap_atomic);
304 266
305/* 267/*
306 * This API is supposed to allow us to map memory without a "struct page". 268 * This API is supposed to allow us to map memory without a "struct page".
307 * Currently we don't support this, though this may change in the future. 269 * Currently we don't support this, though this may change in the future.
308 */ 270 */
309void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) 271void *kmap_atomic_pfn(unsigned long pfn)
310{ 272{
311 return kmap_atomic(pfn_to_page(pfn), type); 273 return kmap_atomic(pfn_to_page(pfn));
312} 274}
313void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot) 275void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot)
314{ 276{
315 return kmap_atomic_prot(pfn_to_page(pfn), type, prot); 277 return kmap_atomic_prot(pfn_to_page(pfn), prot);
316} 278}
317 279
318struct page *kmap_atomic_to_page(void *ptr) 280struct page *kmap_atomic_to_page(void *ptr)
diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c
index fb3b4a55cec4..cbe6f4f9eca3 100644
--- a/arch/tile/mm/homecache.c
+++ b/arch/tile/mm/homecache.c
@@ -37,6 +37,8 @@
37#include <asm/pgalloc.h> 37#include <asm/pgalloc.h>
38#include <asm/homecache.h> 38#include <asm/homecache.h>
39 39
40#include <arch/sim.h>
41
40#include "migrate.h" 42#include "migrate.h"
41 43
42 44
@@ -177,23 +179,46 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
177 panic("Unsafe to continue."); 179 panic("Unsafe to continue.");
178} 180}
179 181
182void flush_remote_page(struct page *page, int order)
183{
184 int i, pages = (1 << order);
185 for (i = 0; i < pages; ++i, ++page) {
186 void *p = kmap_atomic(page);
187 int hfh = 0;
188 int home = page_home(page);
189#if CHIP_HAS_CBOX_HOME_MAP()
190 if (home == PAGE_HOME_HASH)
191 hfh = 1;
192 else
193#endif
194 BUG_ON(home < 0 || home >= NR_CPUS);
195 finv_buffer_remote(p, PAGE_SIZE, hfh);
196 kunmap_atomic(p);
197 }
198}
199
180void homecache_evict(const struct cpumask *mask) 200void homecache_evict(const struct cpumask *mask)
181{ 201{
182 flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0); 202 flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
183} 203}
184 204
185/* Return a mask of the cpus whose caches currently own these pages. */ 205/*
186static void homecache_mask(struct page *page, int pages, 206 * Return a mask of the cpus whose caches currently own these pages.
187 struct cpumask *home_mask) 207 * The return value is whether the pages are all coherently cached
208 * (i.e. none are immutable, incoherent, or uncached).
209 */
210static int homecache_mask(struct page *page, int pages,
211 struct cpumask *home_mask)
188{ 212{
189 int i; 213 int i;
214 int cached_coherently = 1;
190 cpumask_clear(home_mask); 215 cpumask_clear(home_mask);
191 for (i = 0; i < pages; ++i) { 216 for (i = 0; i < pages; ++i) {
192 int home = page_home(&page[i]); 217 int home = page_home(&page[i]);
193 if (home == PAGE_HOME_IMMUTABLE || 218 if (home == PAGE_HOME_IMMUTABLE ||
194 home == PAGE_HOME_INCOHERENT) { 219 home == PAGE_HOME_INCOHERENT) {
195 cpumask_copy(home_mask, cpu_possible_mask); 220 cpumask_copy(home_mask, cpu_possible_mask);
196 return; 221 return 0;
197 } 222 }
198#if CHIP_HAS_CBOX_HOME_MAP() 223#if CHIP_HAS_CBOX_HOME_MAP()
199 if (home == PAGE_HOME_HASH) { 224 if (home == PAGE_HOME_HASH) {
@@ -201,11 +226,14 @@ static void homecache_mask(struct page *page, int pages,
201 continue; 226 continue;
202 } 227 }
203#endif 228#endif
204 if (home == PAGE_HOME_UNCACHED) 229 if (home == PAGE_HOME_UNCACHED) {
230 cached_coherently = 0;
205 continue; 231 continue;
232 }
206 BUG_ON(home < 0 || home >= NR_CPUS); 233 BUG_ON(home < 0 || home >= NR_CPUS);
207 cpumask_set_cpu(home, home_mask); 234 cpumask_set_cpu(home, home_mask);
208 } 235 }
236 return cached_coherently;
209} 237}
210 238
211/* 239/*
@@ -217,13 +245,6 @@ static unsigned long cache_flush_length(unsigned long length)
217 return (length >= CHIP_L2_CACHE_SIZE()) ? HV_FLUSH_EVICT_L2 : length; 245 return (length >= CHIP_L2_CACHE_SIZE()) ? HV_FLUSH_EVICT_L2 : length;
218} 246}
219 247
220/* On the simulator, confirm lines have been evicted everywhere. */
221static void validate_lines_evicted(unsigned long pfn, size_t length)
222{
223 sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED,
224 (HV_PhysAddr)pfn << PAGE_SHIFT, length);
225}
226
227/* Flush a page out of whatever cache(s) it is in. */ 248/* Flush a page out of whatever cache(s) it is in. */
228void homecache_flush_cache(struct page *page, int order) 249void homecache_flush_cache(struct page *page, int order)
229{ 250{
@@ -234,7 +255,7 @@ void homecache_flush_cache(struct page *page, int order)
234 255
235 homecache_mask(page, pages, &home_mask); 256 homecache_mask(page, pages, &home_mask);
236 flush_remote(pfn, length, &home_mask, 0, 0, 0, NULL, NULL, 0); 257 flush_remote(pfn, length, &home_mask, 0, 0, 0, NULL, NULL, 0);
237 validate_lines_evicted(pfn, pages * PAGE_SIZE); 258 sim_validate_lines_evicted(PFN_PHYS(pfn), pages * PAGE_SIZE);
238} 259}
239 260
240 261
@@ -391,7 +412,7 @@ void homecache_change_page_home(struct page *page, int order, int home)
391 pte_t *ptep = virt_to_pte(NULL, kva); 412 pte_t *ptep = virt_to_pte(NULL, kva);
392 pte_t pteval = *ptep; 413 pte_t pteval = *ptep;
393 BUG_ON(!pte_present(pteval) || pte_huge(pteval)); 414 BUG_ON(!pte_present(pteval) || pte_huge(pteval));
394 *ptep = pte_set_home(pteval, home); 415 __set_pte(ptep, pte_set_home(pteval, home));
395 } 416 }
396} 417}
397 418
diff --git a/arch/tile/mm/hugetlbpage.c b/arch/tile/mm/hugetlbpage.c
index 24688b697a8d..42cfcba4e1ef 100644
--- a/arch/tile/mm/hugetlbpage.c
+++ b/arch/tile/mm/hugetlbpage.c
@@ -21,7 +21,6 @@
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/hugetlb.h> 22#include <linux/hugetlb.h>
23#include <linux/pagemap.h> 23#include <linux/pagemap.h>
24#include <linux/smp_lock.h>
25#include <linux/slab.h> 24#include <linux/slab.h>
26#include <linux/err.h> 25#include <linux/err.h>
27#include <linux/sysctl.h> 26#include <linux/sysctl.h>
@@ -220,7 +219,7 @@ try_again:
220 if (mm->free_area_cache < len) 219 if (mm->free_area_cache < len)
221 goto fail; 220 goto fail;
222 221
223 /* either no address requested or cant fit in requested address hole */ 222 /* either no address requested or can't fit in requested address hole */
224 addr = (mm->free_area_cache - len) & huge_page_mask(h); 223 addr = (mm->free_area_cache - len) & huge_page_mask(h);
225 do { 224 do {
226 /* 225 /*
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index d89c9eacd162..4e10c4023028 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -53,26 +53,13 @@
53 53
54#include "migrate.h" 54#include "migrate.h"
55 55
56/*
57 * We could set FORCE_MAX_ZONEORDER to "(HPAGE_SHIFT - PAGE_SHIFT + 1)"
58 * in the Tile Kconfig, but this generates configure warnings.
59 * Do it here and force people to get it right to compile this file.
60 * The problem is that with 4KB small pages and 16MB huge pages,
61 * the default value doesn't allow us to group enough small pages
62 * together to make up a huge page.
63 */
64#if CONFIG_FORCE_MAX_ZONEORDER < HPAGE_SHIFT - PAGE_SHIFT + 1
65# error "Change FORCE_MAX_ZONEORDER in arch/tile/Kconfig to match page size"
66#endif
67
68#define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0)) 56#define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
69 57
70#ifndef __tilegx__ 58#ifndef __tilegx__
71unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE; 59unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE;
60EXPORT_SYMBOL(VMALLOC_RESERVE);
72#endif 61#endif
73 62
74DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
75
76/* Create an L2 page table */ 63/* Create an L2 page table */
77static pte_t * __init alloc_pte(void) 64static pte_t * __init alloc_pte(void)
78{ 65{
@@ -445,7 +432,7 @@ static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
445 432
446/* Temporary page table we use for staging. */ 433/* Temporary page table we use for staging. */
447static pgd_t pgtables[PTRS_PER_PGD] 434static pgd_t pgtables[PTRS_PER_PGD]
448 __attribute__((section(".init.page"))); 435 __attribute__((aligned(HV_PAGE_TABLE_ALIGN)));
449 436
450/* 437/*
451 * This maps the physical memory to kernel virtual address space, a total 438 * This maps the physical memory to kernel virtual address space, a total
@@ -653,6 +640,17 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
653 memcpy(pgd_base, pgtables, sizeof(pgtables)); 640 memcpy(pgd_base, pgtables, sizeof(pgtables));
654 __install_page_table(pgd_base, __get_cpu_var(current_asid), 641 __install_page_table(pgd_base, __get_cpu_var(current_asid),
655 swapper_pgprot); 642 swapper_pgprot);
643
644 /*
645 * We just read swapper_pgprot and thus brought it into the cache,
646 * with its new home & caching mode. When we start the other CPUs,
647 * they're going to reference swapper_pgprot via their initial fake
648 * VA-is-PA mappings, which cache everything locally. At that
649 * time, if it's in our cache with a conflicting home, the
650 * simulator's coherence checker will complain. So, flush it out
651 * of our cache; we're not going to ever use it again anyway.
652 */
653 __insn_finv(&swapper_pgprot);
656} 654}
657 655
658/* 656/*
@@ -950,11 +948,7 @@ struct kmem_cache *pgd_cache;
950 948
951void __init pgtable_cache_init(void) 949void __init pgtable_cache_init(void)
952{ 950{
953 pgd_cache = kmem_cache_create("pgd", 951 pgd_cache = kmem_cache_create("pgd", SIZEOF_PGD, SIZEOF_PGD, 0, NULL);
954 PTRS_PER_PGD*sizeof(pgd_t),
955 PTRS_PER_PGD*sizeof(pgd_t),
956 0,
957 NULL);
958 if (!pgd_cache) 952 if (!pgd_cache)
959 panic("pgtable_cache_init(): Cannot create pgd cache"); 953 panic("pgtable_cache_init(): Cannot create pgd cache");
960} 954}
@@ -988,8 +982,12 @@ static long __write_once initfree = 1;
988/* Select whether to free (1) or mark unusable (0) the __init pages. */ 982/* Select whether to free (1) or mark unusable (0) the __init pages. */
989static int __init set_initfree(char *str) 983static int __init set_initfree(char *str)
990{ 984{
991 strict_strtol(str, 0, &initfree); 985 long val;
992 pr_info("initfree: %s free init pages\n", initfree ? "will" : "won't"); 986 if (strict_strtol(str, 0, &val) == 0) {
987 initfree = val;
988 pr_info("initfree: %s free init pages\n",
989 initfree ? "will" : "won't");
990 }
993 return 1; 991 return 1;
994} 992}
995__setup("initfree=", set_initfree); 993__setup("initfree=", set_initfree);
@@ -1060,7 +1058,7 @@ void free_initmem(void)
1060 1058
1061 /* 1059 /*
1062 * Free the pages mapped from 0xc0000000 that correspond to code 1060 * Free the pages mapped from 0xc0000000 that correspond to code
1063 * pages from 0xfd000000 that we won't use again after init. 1061 * pages from MEM_SV_INTRPT that we won't use again after init.
1064 */ 1062 */
1065 free_init_pages("unused kernel text", 1063 free_init_pages("unused kernel text",
1066 (unsigned long)_sinittext - text_delta, 1064 (unsigned long)_sinittext - text_delta,
diff --git a/arch/tile/mm/migrate_32.S b/arch/tile/mm/migrate_32.S
index f738765cd1e6..ac01a7cdf77f 100644
--- a/arch/tile/mm/migrate_32.S
+++ b/arch/tile/mm/migrate_32.S
@@ -18,6 +18,7 @@
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <linux/threads.h> 19#include <linux/threads.h>
20#include <asm/page.h> 20#include <asm/page.h>
21#include <asm/thread_info.h>
21#include <asm/types.h> 22#include <asm/types.h>
22#include <asm/asm-offsets.h> 23#include <asm/asm-offsets.h>
23#include <hv/hypervisor.h> 24#include <hv/hypervisor.h>
diff --git a/arch/tile/mm/migrate_64.S b/arch/tile/mm/migrate_64.S
new file mode 100644
index 000000000000..e76fea688beb
--- /dev/null
+++ b/arch/tile/mm/migrate_64.S
@@ -0,0 +1,187 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * This routine is a helper for migrating the home of a set of pages to
15 * a new cpu. See the documentation in homecache.c for more information.
16 */
17
18#include <linux/linkage.h>
19#include <linux/threads.h>
20#include <asm/page.h>
21#include <asm/thread_info.h>
22#include <asm/types.h>
23#include <asm/asm-offsets.h>
24#include <hv/hypervisor.h>
25
26 .text
27
28/*
29 * First, some definitions that apply to all the code in the file.
30 */
31
32/* Locals (caller-save) */
33#define r_tmp r10
34#define r_save_sp r11
35
36/* What we save where in the stack frame; must include all callee-saves. */
37#define FRAME_SP 8
38#define FRAME_R30 16
39#define FRAME_R31 24
40#define FRAME_R32 32
41#define FRAME_R33 40
42#define FRAME_SIZE 48
43
44
45
46
47/*
48 * On entry:
49 *
50 * r0 the new context PA to install (moved to r_context)
51 * r1 PTE to use for context access (moved to r_access)
52 * r2 ASID to use for new context (moved to r_asid)
53 * r3 pointer to cpumask with just this cpu set in it (r_my_cpumask)
54 */
55
56/* Arguments (caller-save) */
57#define r_context_in r0
58#define r_access_in r1
59#define r_asid_in r2
60#define r_my_cpumask r3
61
62/* Locals (callee-save); must not be more than FRAME_xxx above. */
63#define r_save_ics r30
64#define r_context r31
65#define r_access r32
66#define r_asid r33
67
68/*
69 * Caller-save locals and frame constants are the same as
70 * for homecache_migrate_stack_and_flush.
71 */
72
73STD_ENTRY(flush_and_install_context)
74 /*
75 * Create a stack frame; we can't touch it once we flush the
76 * cache until we install the new page table and flush the TLB.
77 */
78 {
79 move r_save_sp, sp
80 st sp, lr
81 addi sp, sp, -FRAME_SIZE
82 }
83 addi r_tmp, sp, FRAME_SP
84 {
85 st r_tmp, r_save_sp
86 addi r_tmp, sp, FRAME_R30
87 }
88 {
89 st r_tmp, r30
90 addi r_tmp, sp, FRAME_R31
91 }
92 {
93 st r_tmp, r31
94 addi r_tmp, sp, FRAME_R32
95 }
96 {
97 st r_tmp, r32
98 addi r_tmp, sp, FRAME_R33
99 }
100 st r_tmp, r33
101
102 /* Move some arguments to callee-save registers. */
103 {
104 move r_context, r_context_in
105 move r_access, r_access_in
106 }
107 move r_asid, r_asid_in
108
109 /* Disable interrupts, since we can't use our stack. */
110 {
111 mfspr r_save_ics, INTERRUPT_CRITICAL_SECTION
112 movei r_tmp, 1
113 }
114 mtspr INTERRUPT_CRITICAL_SECTION, r_tmp
115
116 /* First, flush our L2 cache. */
117 {
118 move r0, zero /* cache_pa */
119 moveli r1, hw2_last(HV_FLUSH_EVICT_L2) /* cache_control */
120 }
121 {
122 shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
123 move r2, r_my_cpumask /* cache_cpumask */
124 }
125 {
126 shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2)
127 move r3, zero /* tlb_va */
128 }
129 {
130 move r4, zero /* tlb_length */
131 move r5, zero /* tlb_pgsize */
132 }
133 {
134 move r6, zero /* tlb_cpumask */
135 move r7, zero /* asids */
136 }
137 {
138 move r8, zero /* asidcount */
139 jal hv_flush_remote
140 }
141 bnez r0, 1f
142
143 /* Now install the new page table. */
144 {
145 move r0, r_context
146 move r1, r_access
147 }
148 {
149 move r2, r_asid
150 movei r3, HV_CTX_DIRECTIO
151 }
152 jal hv_install_context
153 bnez r0, 1f
154
155 /* Finally, flush the TLB. */
156 {
157 movei r0, 0 /* preserve_global */
158 jal hv_flush_all
159 }
160
1611: /* Reset interrupts back how they were before. */
162 mtspr INTERRUPT_CRITICAL_SECTION, r_save_ics
163
164 /* Restore the callee-saved registers and return. */
165 addli lr, sp, FRAME_SIZE
166 {
167 ld lr, lr
168 addli r_tmp, sp, FRAME_R30
169 }
170 {
171 ld r30, r_tmp
172 addli r_tmp, sp, FRAME_R31
173 }
174 {
175 ld r31, r_tmp
176 addli r_tmp, sp, FRAME_R32
177 }
178 {
179 ld r32, r_tmp
180 addli r_tmp, sp, FRAME_R33
181 }
182 {
183 ld r33, r_tmp
184 addi sp, sp, FRAME_SIZE
185 }
186 jrp lr
187 STD_ENDPROC(flush_and_install_context)
diff --git a/arch/tile/mm/pgtable.c b/arch/tile/mm/pgtable.c
index 335c24621c41..de7d8e21e01d 100644
--- a/arch/tile/mm/pgtable.c
+++ b/arch/tile/mm/pgtable.c
@@ -41,7 +41,7 @@
41 * The normal show_free_areas() is too verbose on Tile, with dozens 41 * The normal show_free_areas() is too verbose on Tile, with dozens
42 * of processors and often four NUMA zones each with high and lowmem. 42 * of processors and often four NUMA zones each with high and lowmem.
43 */ 43 */
44void show_mem(void) 44void show_mem(unsigned int filter)
45{ 45{
46 struct zone *zone; 46 struct zone *zone;
47 47
@@ -134,14 +134,84 @@ void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t flags)
134} 134}
135 135
136#if defined(CONFIG_HIGHPTE) 136#if defined(CONFIG_HIGHPTE)
137pte_t *_pte_offset_map(pmd_t *dir, unsigned long address, enum km_type type) 137pte_t *_pte_offset_map(pmd_t *dir, unsigned long address)
138{ 138{
139 pte_t *pte = kmap_atomic(pmd_page(*dir), type) + 139 pte_t *pte = kmap_atomic(pmd_page(*dir)) +
140 (pmd_ptfn(*dir) << HV_LOG2_PAGE_TABLE_ALIGN) & ~PAGE_MASK; 140 (pmd_ptfn(*dir) << HV_LOG2_PAGE_TABLE_ALIGN) & ~PAGE_MASK;
141 return &pte[pte_index(address)]; 141 return &pte[pte_index(address)];
142} 142}
143#endif 143#endif
144 144
145/**
146 * shatter_huge_page() - ensure a given address is mapped by a small page.
147 *
148 * This function converts a huge PTE mapping kernel LOWMEM into a bunch
149 * of small PTEs with the same caching. No cache flush required, but we
150 * must do a global TLB flush.
151 *
152 * Any caller that wishes to modify a kernel mapping that might
153 * have been made with a huge page should call this function,
154 * since doing so properly avoids race conditions with installing the
155 * newly-shattered page and then flushing all the TLB entries.
156 *
157 * @addr: Address at which to shatter any existing huge page.
158 */
159void shatter_huge_page(unsigned long addr)
160{
161 pgd_t *pgd;
162 pud_t *pud;
163 pmd_t *pmd;
164 unsigned long flags = 0; /* happy compiler */
165#ifdef __PAGETABLE_PMD_FOLDED
166 struct list_head *pos;
167#endif
168
169 /* Get a pointer to the pmd entry that we need to change. */
170 addr &= HPAGE_MASK;
171 BUG_ON(pgd_addr_invalid(addr));
172 BUG_ON(addr < PAGE_OFFSET); /* only for kernel LOWMEM */
173 pgd = swapper_pg_dir + pgd_index(addr);
174 pud = pud_offset(pgd, addr);
175 BUG_ON(!pud_present(*pud));
176 pmd = pmd_offset(pud, addr);
177 BUG_ON(!pmd_present(*pmd));
178 if (!pmd_huge_page(*pmd))
179 return;
180
181 /*
182 * Grab the pgd_lock, since we may need it to walk the pgd_list,
183 * and since we need some kind of lock here to avoid races.
184 */
185 spin_lock_irqsave(&pgd_lock, flags);
186 if (!pmd_huge_page(*pmd)) {
187 /* Lost the race to convert the huge page. */
188 spin_unlock_irqrestore(&pgd_lock, flags);
189 return;
190 }
191
192 /* Shatter the huge page into the preallocated L2 page table. */
193 pmd_populate_kernel(&init_mm, pmd,
194 get_prealloc_pte(pte_pfn(*(pte_t *)pmd)));
195
196#ifdef __PAGETABLE_PMD_FOLDED
197 /* Walk every pgd on the system and update the pmd there. */
198 list_for_each(pos, &pgd_list) {
199 pmd_t *copy_pmd;
200 pgd = list_to_pgd(pos) + pgd_index(addr);
201 pud = pud_offset(pgd, addr);
202 copy_pmd = pmd_offset(pud, addr);
203 __set_pmd(copy_pmd, *pmd);
204 }
205#endif
206
207 /* Tell every cpu to notice the change. */
208 flush_remote(0, 0, NULL, addr, HPAGE_SIZE, HPAGE_SIZE,
209 cpu_possible_mask, NULL, 0);
210
211 /* Hold the lock until the TLB flush is finished to avoid races. */
212 spin_unlock_irqrestore(&pgd_lock, flags);
213}
214
145/* 215/*
146 * List of all pgd's needed so it can invalidate entries in both cached 216 * List of all pgd's needed so it can invalidate entries in both cached
147 * and uncached pgd's. This is essentially codepath-based locking 217 * and uncached pgd's. This is essentially codepath-based locking
@@ -184,9 +254,9 @@ static void pgd_ctor(pgd_t *pgd)
184 BUG_ON(((u64 *)swapper_pg_dir)[pgd_index(MEM_USER_INTRPT)] != 0); 254 BUG_ON(((u64 *)swapper_pg_dir)[pgd_index(MEM_USER_INTRPT)] != 0);
185#endif 255#endif
186 256
187 clone_pgd_range(pgd + KERNEL_PGD_INDEX_START, 257 memcpy(pgd + KERNEL_PGD_INDEX_START,
188 swapper_pg_dir + KERNEL_PGD_INDEX_START, 258 swapper_pg_dir + KERNEL_PGD_INDEX_START,
189 KERNEL_PGD_PTRS); 259 KERNEL_PGD_PTRS * sizeof(pgd_t));
190 260
191 pgd_list_add(pgd); 261 pgd_list_add(pgd);
192 spin_unlock_irqrestore(&pgd_lock, flags); 262 spin_unlock_irqrestore(&pgd_lock, flags);
@@ -220,8 +290,11 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd)
220 290
221struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) 291struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
222{ 292{
223 gfp_t flags = GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO|__GFP_COMP; 293 gfp_t flags = GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO;
224 struct page *p; 294 struct page *p;
295#if L2_USER_PGTABLE_ORDER > 0
296 int i;
297#endif
225 298
226#ifdef CONFIG_HIGHPTE 299#ifdef CONFIG_HIGHPTE
227 flags |= __GFP_HIGHMEM; 300 flags |= __GFP_HIGHMEM;
@@ -231,6 +304,18 @@ struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
231 if (p == NULL) 304 if (p == NULL)
232 return NULL; 305 return NULL;
233 306
307#if L2_USER_PGTABLE_ORDER > 0
308 /*
309 * Make every page have a page_count() of one, not just the first.
310 * We don't use __GFP_COMP since it doesn't look like it works
311 * correctly with tlb_remove_page().
312 */
313 for (i = 1; i < L2_USER_PGTABLE_PAGES; ++i) {
314 init_page_count(p+i);
315 inc_zone_page_state(p+i, NR_PAGETABLE);
316 }
317#endif
318
234 pgtable_page_ctor(p); 319 pgtable_page_ctor(p);
235 return p; 320 return p;
236} 321}
@@ -242,8 +327,15 @@ struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
242 */ 327 */
243void pte_free(struct mm_struct *mm, struct page *p) 328void pte_free(struct mm_struct *mm, struct page *p)
244{ 329{
330 int i;
331
245 pgtable_page_dtor(p); 332 pgtable_page_dtor(p);
246 __free_pages(p, L2_USER_PGTABLE_ORDER); 333 __free_page(p);
334
335 for (i = 1; i < L2_USER_PGTABLE_PAGES; ++i) {
336 __free_page(p+i);
337 dec_zone_page_state(p+i, NR_PAGETABLE);
338 }
247} 339}
248 340
249void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte, 341void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte,
@@ -252,18 +344,11 @@ void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte,
252 int i; 344 int i;
253 345
254 pgtable_page_dtor(pte); 346 pgtable_page_dtor(pte);
255 tlb->need_flush = 1; 347 tlb_remove_page(tlb, pte);
256 if (tlb_fast_mode(tlb)) { 348
257 struct page *pte_pages[L2_USER_PGTABLE_PAGES]; 349 for (i = 1; i < L2_USER_PGTABLE_PAGES; ++i) {
258 for (i = 0; i < L2_USER_PGTABLE_PAGES; ++i) 350 tlb_remove_page(tlb, pte + i);
259 pte_pages[i] = pte + i; 351 dec_zone_page_state(pte + i, NR_PAGETABLE);
260 free_pages_and_swap_cache(pte_pages, L2_USER_PGTABLE_PAGES);
261 return;
262 }
263 for (i = 0; i < L2_USER_PGTABLE_PAGES; ++i) {
264 tlb->pages[tlb->nr++] = pte + i;
265 if (tlb->nr >= FREE_PTE_NR)
266 tlb_flush_mmu(tlb, 0, 0);
267 } 352 }
268} 353}
269 354
@@ -346,35 +431,51 @@ int get_remote_cache_cpu(pgprot_t prot)
346 return x + y * smp_width; 431 return x + y * smp_width;
347} 432}
348 433
349void set_pte_order(pte_t *ptep, pte_t pte, int order) 434/*
435 * Convert a kernel VA to a PA and homing information.
436 */
437int va_to_cpa_and_pte(void *va, unsigned long long *cpa, pte_t *pte)
350{ 438{
351 unsigned long pfn = pte_pfn(pte); 439 struct page *page = virt_to_page(va);
352 struct page *page = pfn_to_page(pfn); 440 pte_t null_pte = { 0 };
353 441
354 /* Update the home of a PTE if necessary */ 442 *cpa = __pa(va);
355 pte = pte_set_home(pte, page_home(page));
356 443
444 /* Note that this is not writing a page table, just returning a pte. */
445 *pte = pte_set_home(null_pte, page_home(page));
446
447 return 0; /* return non-zero if not hfh? */
448}
449EXPORT_SYMBOL(va_to_cpa_and_pte);
450
451void __set_pte(pte_t *ptep, pte_t pte)
452{
357#ifdef __tilegx__ 453#ifdef __tilegx__
358 *ptep = pte; 454 *ptep = pte;
359#else 455#else
360 /* 456# if HV_PTE_INDEX_PRESENT >= 32 || HV_PTE_INDEX_MIGRATING >= 32
361 * When setting a PTE, write the high bits first, then write 457# error Must write the present and migrating bits last
362 * the low bits. This sets the "present" bit only after the 458# endif
363 * other bits are in place. If a particular PTE update 459 if (pte_present(pte)) {
364 * involves transitioning from one valid PTE to another, it 460 ((u32 *)ptep)[1] = (u32)(pte_val(pte) >> 32);
365 * may be necessary to call set_pte_order() more than once, 461 barrier();
366 * transitioning via a suitable intermediate state. 462 ((u32 *)ptep)[0] = (u32)(pte_val(pte));
367 * Note that this sequence also means that if we are transitioning 463 } else {
368 * from any migrating PTE to a non-migrating one, we will not 464 ((u32 *)ptep)[0] = (u32)(pte_val(pte));
369 * see a half-updated PTE with the migrating bit off. 465 barrier();
370 */ 466 ((u32 *)ptep)[1] = (u32)(pte_val(pte) >> 32);
371#if HV_PTE_INDEX_PRESENT >= 32 || HV_PTE_INDEX_MIGRATING >= 32 467 }
372# error Must write the present and migrating bits last 468#endif /* __tilegx__ */
373#endif 469}
374 ((u32 *)ptep)[1] = (u32)(pte_val(pte) >> 32); 470
375 barrier(); 471void set_pte(pte_t *ptep, pte_t pte)
376 ((u32 *)ptep)[0] = (u32)(pte_val(pte)); 472{
377#endif 473 struct page *page = pfn_to_page(pte_pfn(pte));
474
475 /* Update the home of a PTE if necessary */
476 pte = pte_set_home(pte, page_home(page));
477
478 __set_pte(ptep, pte);
378} 479}
379 480
380/* Can this mm load a PTE with cached_priority set? */ 481/* Can this mm load a PTE with cached_priority set? */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-13 02:03:56 -0400