6 files changed, 558 insertions, 64 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index e073e3eb4c3d..eedddad13835 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -77,9 +77,10 @@ struct clk div4_clks[DIV4_NR] = {
 
 #define MSTPCR0         0xffc80030
 #define MSTPCR1         0xffc80034
+#define MSTPCR2         0xffc10028
 
 enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
-       MSTP111, MSTP110, MSTP103, MSTP102,
+       MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
        MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
@@ -95,6 +96,9 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
         [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
         [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
+
+        /* MSTPCR2 */
+        [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
 };
 
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
@@ -140,6 +144,7 @@ static struct clk_lookup lookups[] = {
                 .clk            = &mstp_clks[MSTP110],
         },
         CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
+        CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
 };
 
 int __init arch_clk_init(void)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 9c1de2633ac3..423dabf542d3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -1,7 +1,7 @@
 /*
  * SH7757 Setup
  *
- * Copyright (C) 2009  Renesas Solutions Corp.
+ * Copyright (C) 2009, 2011  Renesas Solutions Corp.
  *
  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
  *
@@ -16,6 +16,10 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/sh_timer.h>
+#include <linux/sh_dma.h>
+
+#include <cpu/dma-register.h>
+#include <cpu/sh7757.h>
 
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xfe4b0000,           /* SCIF2 */
@@ -124,12 +128,548 @@ static struct platform_device tmu1_device = {
         .num_resources  = ARRAY_SIZE(tmu1_resources),
 };
 
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = 0xfe002000,
+                .end    = 0xfe0020ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 86,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* DMA */
+static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SDHI_TX,
+                .addr           = 0x1fe50030,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc5,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SDHI_RX,
+                .addr           = 0x1fe50030,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc6,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0x1fcb0034,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd3,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0x1fcb0034,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd7,
+        },
+};
+
+static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+                .addr           = 0x1f4b000c,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+                .addr           = 0x1f4b0014,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF3_TX,
+                .addr           = 0x1f4c000c,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF3_RX,
+                .addr           = 0x1f4c0014,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF4_TX,
+                .addr           = 0x1f4d000c,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x41,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF4_RX,
+                .addr           = 0x1f4d0014,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x42,
+        },
+};
+
+static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC0_TX,
+                .addr           = 0x1e500012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC0_RX,
+                .addr           = 0x1e500013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC1_TX,
+                .addr           = 0x1e510012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC1_RX,
+                .addr           = 0x1e510013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC2_TX,
+                .addr           = 0x1e520012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xa1,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC2_RX,
+                .addr           = 0x1e520013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xa2,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC3_TX,
+                .addr           = 0x1e530012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xab,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC3_RX,
+                .addr           = 0x1e530013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xaf,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC4_TX,
+                .addr           = 0x1e540012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xc1,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC4_RX,
+                .addr           = 0x1e540013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xc2,
+        },
+};
+
+static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC5_TX,
+                .addr           = 0x1e550012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC5_RX,
+                .addr           = 0x1e550013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC6_TX,
+                .addr           = 0x1e560012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC6_RX,
+                .addr           = 0x1e560013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC7_TX,
+                .addr           = 0x1e570012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x41,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC7_RX,
+                .addr           = 0x1e570013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x42,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC8_TX,
+                .addr           = 0x1e580012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x45,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC8_RX,
+                .addr           = 0x1e580013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x46,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC9_TX,
+                .addr           = 0x1e590012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x51,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC9_RX,
+                .addr           = 0x1e590013,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x52,
+        },
+};
+
+static const struct sh_dmae_channel sh7757_dmae_channels[] = {
+        {
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
+        }
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma0_platform_data = {
+        .slave          = sh7757_dmae0_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae0_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma1_platform_data = {
+        .slave          = sh7757_dmae1_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae1_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma2_platform_data = {
+        .slave          = sh7757_dmae2_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae2_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma3_platform_data = {
+        .slave          = sh7757_dmae3_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae3_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+/* channel 0 to 5 */
+static struct resource sh7757_dmae0_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff608020,
+                .end    = 0xff60808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff609000,
+                .end    = 0xff60900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 34,
+                .end    = 34,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+/* channel 6 to 11 */
+static struct resource sh7757_dmae1_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff618020,
+                .end    = 0xff61808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff619000,
+                .end    = 0xff61900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error */
+                .start  = 34,
+                .end    = 34,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 4 */
+                .start  = 46,
+                .end    = 46,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 5 */
+                .start  = 46,
+                .end    = 46,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 6 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 7 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 8 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 9 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 10 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 11 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+/* channel 12 to 17 */
+static struct resource sh7757_dmae2_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff708020,
+                .end    = 0xff70808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff709000,
+                .end    = 0xff70900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error */
+                .start  = 323,
+                .end    = 323,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 12 to 16 */
+                .start  = 272,
+                .end    = 276,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channel 17 */
+                .start  = 279,
+                .end    = 279,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* channel 18 to 23 */
+static struct resource sh7757_dmae3_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff718020,
+                .end    = 0xff71808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff719000,
+                .end    = 0xff71900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error */
+                .start  = 324,
+                .end    = 324,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 18 to 22 */
+                .start  = 280,
+                .end    = 284,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channel 23 */
+                .start  = 288,
+                .end    = 288,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh7757_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma0_platform_data,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh7757_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae1_resources),
+        .dev            = {
+                .platform_data  = &dma1_platform_data,
+        },
+};
+
+static struct platform_device dma2_device = {
+        .name           = "sh-dma-engine",
+        .id             = 2,
+        .resource       = sh7757_dmae2_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae2_resources),
+        .dev            = {
+                .platform_data  = &dma2_platform_data,
+        },
+};
+
+static struct platform_device dma3_device = {
+        .name           = "sh-dma-engine",
+        .id             = 3,
+        .resource       = sh7757_dmae3_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae3_resources),
+        .dev            = {
+                .platform_data  = &dma3_platform_data,
+        },
+};
+
+static struct platform_device spi0_device = {
+        .name   = "sh_spi",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+        .resource       = spi0_resources,
+};
+
 static struct platform_device *sh7757_devices[] __initdata = {
         &scif2_device,
         &scif3_device,
         &scif4_device,
         &tmu0_device,
         &tmu1_device,
+        &dma0_device,
+        &dma1_device,
+        &dma2_device,
+        &dma3_device,
+        &spi0_device,
 };
 
 static int __init sh7757_devices_setup(void)
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index c19e2a940e3f..e4469e7233cb 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -75,7 +75,7 @@ void sh_mobile_setup_cpuidle(void)
         i = CPUIDLE_DRIVER_STATE_START;
 
         state = &dev->states[i++];
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C0");
+        snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
         strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN);
         state->exit_latency = 1;
         state->target_residency = 1 * 2;
@@ -88,7 +88,7 @@ void sh_mobile_setup_cpuidle(void)
 
         if (sh_mobile_sleep_supported & SUSP_SH_SF) {
                 state = &dev->states[i++];
-                snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
+                snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
                 strncpy(state->desc, "SuperH Sleep Mode [SF]",
                         CPUIDLE_DESC_LEN);
                 state->exit_latency = 100;
@@ -101,7 +101,7 @@ void sh_mobile_setup_cpuidle(void)
 
         if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) {
                 state = &dev->states[i++];
-                snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
+                snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
                 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]",
                         CPUIDLE_DESC_LEN);
                 state->exit_latency = 2300;
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 68ecbe6c881a..64ea0b165399 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -34,9 +34,9 @@ void ack_bad_irq(unsigned int irq)
 
 #if defined(CONFIG_PROC_FS)
 /*
- * /proc/interrupts printing:
+ * /proc/interrupts printing for arch specific interrupts
  */
-static int show_other_interrupts(struct seq_file *p, int prec)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
         int j;
 
@@ -49,63 +49,6 @@ static int show_other_interrupts(struct seq_file *p, int prec)
 
         return 0;
 }
-
-int show_interrupts(struct seq_file *p, void *v)
-{
-        unsigned long flags, any_count = 0;
-        int i = *(loff_t *)v, j, prec;
-        struct irqaction *action;
-        struct irq_desc *desc;
-        struct irq_data *data;
-        struct irq_chip *chip;
-
-        if (i > nr_irqs)
-                return 0;
-
-        for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
-                j *= 10;
-
-        if (i == nr_irqs)
-                return show_other_interrupts(p, prec);
-
-        if (i == 0) {
-                seq_printf(p, "%*s", prec + 8, "");
-                for_each_online_cpu(j)
-                        seq_printf(p, "CPU%-8d", j);
-                seq_putc(p, '\n');
-        }
-
-        desc = irq_to_desc(i);
-        if (!desc)
-                return 0;
-
-        data = irq_get_irq_data(i);
-        chip = irq_data_get_irq_chip(data);
-
-        raw_spin_lock_irqsave(&desc->lock, flags);
-        for_each_online_cpu(j)
-                any_count |= kstat_irqs_cpu(i, j);
-        action = desc->action;
-        if (!action && !any_count)
-                goto out;
-
-        seq_printf(p, "%*d: ", prec, i);
-        for_each_online_cpu(j)
-                seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-        seq_printf(p, " %14s", chip->name);
-        seq_printf(p, "-%-8s", desc->name);
-
-        if (action) {
-                seq_printf(p, "  %s", action->name);
-                while ((action = action->next) != NULL)
-                        seq_printf(p, ", %s", action->name);
-        }
-
-        seq_putc(p, '\n');
-out:
-        raw_spin_unlock_irqrestore(&desc->lock, flags);
-        return 0;
-}
 #endif
 
 #ifdef CONFIG_IRQSTACKS
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 6fc347ebe59d..768fb33fdd35 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -376,3 +376,6 @@ ENTRY(sys_call_table)
         .long sys_recvmsg
         .long sys_recvmmsg
         .long sys_accept4
+        .long sys_name_to_handle_at
+        .long sys_open_by_handle_at     /* 360 */
+        .long sys_clock_adjtime
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index 66585708ce90..44e7b00c8067 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -396,3 +396,6 @@ sys_call_table:
         .long sys_fanotify_init
         .long sys_fanotify_mark
         .long sys_prlimit64
+        .long sys_name_to_handle_at     /* 370 */
+        .long sys_open_by_handle_at
+        .long sys_clock_adjtime