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-rw-r--r--arch/sh/Kconfig3
-rw-r--r--arch/sh/boards/board-espt.c7
-rw-r--r--arch/sh/boards/board-sh7757lcr.c185
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c2
-rw-r--r--arch/sh/boards/mach-sh7763rdp/setup.c6
-rw-r--r--arch/sh/boot/compressed/Makefile2
-rw-r--r--arch/sh/configs/sh7757lcr_defconfig19
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.c46
-rw-r--r--arch/sh/include/asm/unistd_32.h5
-rw-r--r--arch/sh/include/asm/unistd_64.h5
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-register.h5
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7757.h32
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c7
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c542
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c6
-rw-r--r--arch/sh/kernel/irq.c61
-rw-r--r--arch/sh/kernel/syscalls_32.S3
-rw-r--r--arch/sh/kernel/syscalls_64.S3
-rw-r--r--arch/sh/mm/Makefile2
19 files changed, 857 insertions, 84 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8a9011dced14..2d264fa84959 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -25,6 +25,7 @@ config SUPERH
25 select GENERIC_ATOMIC64 25 select GENERIC_ATOMIC64
26 # Support the deprecated APIs until MFD and GPIOLIB catch up. 26 # Support the deprecated APIs until MFD and GPIOLIB catch up.
27 select GENERIC_HARDIRQS_NO_DEPRECATED if !MFD_SUPPORT && !GPIOLIB 27 select GENERIC_HARDIRQS_NO_DEPRECATED if !MFD_SUPPORT && !GPIOLIB
28 select GENERIC_IRQ_SHOW
28 help 29 help
29 The SuperH is a RISC processor targeted for use in embedded systems 30 The SuperH is a RISC processor targeted for use in embedded systems
30 and consumer electronics; it was also used in the Sega Dreamcast 31 and consumer electronics; it was also used in the Sega Dreamcast
@@ -434,6 +435,8 @@ config CPU_SUBTYPE_SH7757
434 select CPU_SH4A 435 select CPU_SH4A
435 select CPU_SHX2 436 select CPU_SHX2
436 select ARCH_WANT_OPTIONAL_GPIOLIB 437 select ARCH_WANT_OPTIONAL_GPIOLIB
438 select USB_ARCH_HAS_OHCI
439 select USB_ARCH_HAS_EHCI
437 help 440 help
438 Select SH7757 if you have a SH4A SH7757 CPU. 441 Select SH7757 if you have a SH4A SH7757 CPU.
439 442
diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c
index d5ce5e18eb37..9da92ac36533 100644
--- a/arch/sh/boards/board-espt.c
+++ b/arch/sh/boards/board-espt.c
@@ -66,6 +66,11 @@ static struct resource sh_eth_resources[] = {
66 .end = 0xFEE00F7C - 1, 66 .end = 0xFEE00F7C - 1,
67 .flags = IORESOURCE_MEM, 67 .flags = IORESOURCE_MEM,
68 }, { 68 }, {
69 .start = 0xFEE01800, /* TSU */
70 .end = 0xFEE01FFF,
71 .flags = IORESOURCE_MEM,
72 }, {
73
69 .start = 57, /* irq number */ 74 .start = 57, /* irq number */
70 .flags = IORESOURCE_IRQ, 75 .flags = IORESOURCE_IRQ,
71 }, 76 },
@@ -74,6 +79,8 @@ static struct resource sh_eth_resources[] = {
74static struct sh_eth_plat_data sh7763_eth_pdata = { 79static struct sh_eth_plat_data sh7763_eth_pdata = {
75 .phy = 0, 80 .phy = 0,
76 .edmac_endian = EDMAC_LITTLE_ENDIAN, 81 .edmac_endian = EDMAC_LITTLE_ENDIAN,
82 .register_type = SH_ETH_REG_GIGABIT,
83 .phy_interface = PHY_INTERFACE_MODE_MII,
77}; 84};
78 85
79static struct platform_device espt_eth_device = { 86static struct platform_device espt_eth_device = {
diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c
index c475f1056ab4..a9e33569ad38 100644
--- a/arch/sh/boards/board-sh7757lcr.c
+++ b/arch/sh/boards/board-sh7757lcr.c
@@ -15,6 +15,9 @@
15#include <linux/spi/spi.h> 15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h> 16#include <linux/spi/flash.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/sh_mmcif.h>
20#include <linux/mfd/sh_mobile_sdhi.h>
18#include <cpu/sh7757.h> 21#include <cpu/sh7757.h>
19#include <asm/sh_eth.h> 22#include <asm/sh_eth.h>
20#include <asm/heartbeat.h> 23#include <asm/heartbeat.h>
@@ -44,6 +47,17 @@ static struct platform_device heartbeat_device = {
44}; 47};
45 48
46/* Fast Ethernet */ 49/* Fast Ethernet */
50#define GBECONT 0xffc10100
51#define GBECONT_RMII1 BIT(17)
52#define GBECONT_RMII0 BIT(16)
53static void sh7757_eth_set_mdio_gate(unsigned long addr)
54{
55 if ((addr & 0x00000fff) < 0x0800)
56 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
57 else
58 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
59}
60
47static struct resource sh_eth0_resources[] = { 61static struct resource sh_eth0_resources[] = {
48 { 62 {
49 .start = 0xfef00000, 63 .start = 0xfef00000,
@@ -59,6 +73,8 @@ static struct resource sh_eth0_resources[] = {
59static struct sh_eth_plat_data sh7757_eth0_pdata = { 73static struct sh_eth_plat_data sh7757_eth0_pdata = {
60 .phy = 1, 74 .phy = 1,
61 .edmac_endian = EDMAC_LITTLE_ENDIAN, 75 .edmac_endian = EDMAC_LITTLE_ENDIAN,
76 .register_type = SH_ETH_REG_FAST_SH4,
77 .set_mdio_gate = sh7757_eth_set_mdio_gate,
62}; 78};
63 79
64static struct platform_device sh7757_eth0_device = { 80static struct platform_device sh7757_eth0_device = {
@@ -86,6 +102,8 @@ static struct resource sh_eth1_resources[] = {
86static struct sh_eth_plat_data sh7757_eth1_pdata = { 102static struct sh_eth_plat_data sh7757_eth1_pdata = {
87 .phy = 1, 103 .phy = 1,
88 .edmac_endian = EDMAC_LITTLE_ENDIAN, 104 .edmac_endian = EDMAC_LITTLE_ENDIAN,
105 .register_type = SH_ETH_REG_FAST_SH4,
106 .set_mdio_gate = sh7757_eth_set_mdio_gate,
89}; 107};
90 108
91static struct platform_device sh7757_eth1_device = { 109static struct platform_device sh7757_eth1_device = {
@@ -98,10 +116,173 @@ static struct platform_device sh7757_eth1_device = {
98 }, 116 },
99}; 117};
100 118
119static void sh7757_eth_giga_set_mdio_gate(unsigned long addr)
120{
121 if ((addr & 0x00000fff) < 0x0800) {
122 gpio_set_value(GPIO_PTT4, 1);
123 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
124 } else {
125 gpio_set_value(GPIO_PTT4, 0);
126 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
127 }
128}
129
130static struct resource sh_eth_giga0_resources[] = {
131 {
132 .start = 0xfee00000,
133 .end = 0xfee007ff,
134 .flags = IORESOURCE_MEM,
135 }, {
136 /* TSU */
137 .start = 0xfee01800,
138 .end = 0xfee01fff,
139 .flags = IORESOURCE_MEM,
140 }, {
141 .start = 315,
142 .end = 315,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
148 .phy = 18,
149 .edmac_endian = EDMAC_LITTLE_ENDIAN,
150 .register_type = SH_ETH_REG_GIGABIT,
151 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
152 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
153};
154
155static struct platform_device sh7757_eth_giga0_device = {
156 .name = "sh-eth",
157 .resource = sh_eth_giga0_resources,
158 .id = 2,
159 .num_resources = ARRAY_SIZE(sh_eth_giga0_resources),
160 .dev = {
161 .platform_data = &sh7757_eth_giga0_pdata,
162 },
163};
164
165static struct resource sh_eth_giga1_resources[] = {
166 {
167 .start = 0xfee00800,
168 .end = 0xfee00fff,
169 .flags = IORESOURCE_MEM,
170 }, {
171 .start = 316,
172 .end = 316,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
178 .phy = 19,
179 .edmac_endian = EDMAC_LITTLE_ENDIAN,
180 .register_type = SH_ETH_REG_GIGABIT,
181 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
182 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
183};
184
185static struct platform_device sh7757_eth_giga1_device = {
186 .name = "sh-eth",
187 .resource = sh_eth_giga1_resources,
188 .id = 3,
189 .num_resources = ARRAY_SIZE(sh_eth_giga1_resources),
190 .dev = {
191 .platform_data = &sh7757_eth_giga1_pdata,
192 },
193};
194
195/* SH_MMCIF */
196static struct resource sh_mmcif_resources[] = {
197 [0] = {
198 .start = 0xffcb0000,
199 .end = 0xffcb00ff,
200 .flags = IORESOURCE_MEM,
201 },
202 [1] = {
203 .start = 211,
204 .flags = IORESOURCE_IRQ,
205 },
206 [2] = {
207 .start = 212,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212static struct sh_mmcif_dma sh7757lcr_mmcif_dma = {
213 .chan_priv_tx = SHDMA_SLAVE_MMCIF_TX,
214 .chan_priv_rx = SHDMA_SLAVE_MMCIF_RX,
215};
216
217static struct sh_mmcif_plat_data sh_mmcif_plat = {
218 .dma = &sh7757lcr_mmcif_dma,
219 .sup_pclk = 0x0f,
220 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
221 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
222};
223
224static struct platform_device sh_mmcif_device = {
225 .name = "sh_mmcif",
226 .id = 0,
227 .dev = {
228 .platform_data = &sh_mmcif_plat,
229 },
230 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
231 .resource = sh_mmcif_resources,
232};
233
234/* SDHI0 */
235static struct sh_mobile_sdhi_info sdhi_info = {
236 .dma_slave_tx = SHDMA_SLAVE_SDHI_TX,
237 .dma_slave_rx = SHDMA_SLAVE_SDHI_RX,
238 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
239};
240
241static struct resource sdhi_resources[] = {
242 [0] = {
243 .start = 0xffe50000,
244 .end = 0xffe501ff,
245 .flags = IORESOURCE_MEM,
246 },
247 [1] = {
248 .start = 20,
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct platform_device sdhi_device = {
254 .name = "sh_mobile_sdhi",
255 .num_resources = ARRAY_SIZE(sdhi_resources),
256 .resource = sdhi_resources,
257 .id = 0,
258 .dev = {
259 .platform_data = &sdhi_info,
260 },
261};
262
101static struct platform_device *sh7757lcr_devices[] __initdata = { 263static struct platform_device *sh7757lcr_devices[] __initdata = {
102 &heartbeat_device, 264 &heartbeat_device,
103 &sh7757_eth0_device, 265 &sh7757_eth0_device,
104 &sh7757_eth1_device, 266 &sh7757_eth1_device,
267 &sh7757_eth_giga0_device,
268 &sh7757_eth_giga1_device,
269 &sh_mmcif_device,
270 &sdhi_device,
271};
272
273static struct flash_platform_data spi_flash_data = {
274 .name = "m25p80",
275 .type = "m25px64",
276};
277
278static struct spi_board_info spi_board_info[] = {
279 {
280 .modalias = "m25p80",
281 .max_speed_hz = 25000000,
282 .bus_num = 0,
283 .chip_select = 1,
284 .platform_data = &spi_flash_data,
285 },
105}; 286};
106 287
107static int __init sh7757lcr_devices_setup(void) 288static int __init sh7757lcr_devices_setup(void)
@@ -332,6 +513,10 @@ static int __init sh7757lcr_devices_setup(void)
332 gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ 513 gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */
333 gpio_direction_output(GPIO_PTT5, 1); 514 gpio_direction_output(GPIO_PTT5, 1);
334 515
516 /* register SPI device information */
517 spi_register_board_info(spi_board_info,
518 ARRAY_SIZE(spi_board_info));
519
335 /* General platform */ 520 /* General platform */
336 return platform_add_devices(sh7757lcr_devices, 521 return platform_add_devices(sh7757lcr_devices,
337 ARRAY_SIZE(sh7757lcr_devices)); 522 ARRAY_SIZE(sh7757lcr_devices));
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 701667acfd89..3b71d2190de1 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -142,6 +142,8 @@ static struct resource sh_eth_resources[] = {
142static struct sh_eth_plat_data sh_eth_plat = { 142static struct sh_eth_plat_data sh_eth_plat = {
143 .phy = 0x1f, /* SMSC LAN8700 */ 143 .phy = 0x1f, /* SMSC LAN8700 */
144 .edmac_endian = EDMAC_LITTLE_ENDIAN, 144 .edmac_endian = EDMAC_LITTLE_ENDIAN,
145 .register_type = SH_ETH_REG_FAST_SH4,
146 .phy_interface = PHY_INTERFACE_MODE_MII,
145 .ether_link_active_low = 1 147 .ether_link_active_low = 1
146}; 148};
147 149
diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
index f64a6918224c..f3d828f133e5 100644
--- a/arch/sh/boards/mach-sh7763rdp/setup.c
+++ b/arch/sh/boards/mach-sh7763rdp/setup.c
@@ -75,6 +75,10 @@ static struct resource sh_eth_resources[] = {
75 .end = 0xFEE00F7C - 1, 75 .end = 0xFEE00F7C - 1,
76 .flags = IORESOURCE_MEM, 76 .flags = IORESOURCE_MEM,
77 }, { 77 }, {
78 .start = 0xFEE01800, /* TSU */
79 .end = 0xFEE01FFF,
80 .flags = IORESOURCE_MEM,
81 }, {
78 .start = 57, /* irq number */ 82 .start = 57, /* irq number */
79 .flags = IORESOURCE_IRQ, 83 .flags = IORESOURCE_IRQ,
80 }, 84 },
@@ -83,6 +87,8 @@ static struct resource sh_eth_resources[] = {
83static struct sh_eth_plat_data sh7763_eth_pdata = { 87static struct sh_eth_plat_data sh7763_eth_pdata = {
84 .phy = 1, 88 .phy = 1,
85 .edmac_endian = EDMAC_LITTLE_ENDIAN, 89 .edmac_endian = EDMAC_LITTLE_ENDIAN,
90 .register_type = SH_ETH_REG_GIGABIT,
91 .phy_interface = PHY_INTERFACE_MODE_MII,
86}; 92};
87 93
88static struct platform_device sh7763rdp_eth_device = { 94static struct platform_device sh7763rdp_eth_device = {
diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile
index e0b0293bae63..780e083e4d17 100644
--- a/arch/sh/boot/compressed/Makefile
+++ b/arch/sh/boot/compressed/Makefile
@@ -11,6 +11,8 @@ targets := vmlinux vmlinux.bin vmlinux.bin.gz \
11 11
12OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o 12OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o
13 13
14GCOV_PROFILE := n
15
14# 16#
15# IMAGE_OFFSET is the load offset of the compression loader 17# IMAGE_OFFSET is the load offset of the compression loader
16# 18#
diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig
index 5f7f667b9f3b..fa0ecf87034c 100644
--- a/arch/sh/configs/sh7757lcr_defconfig
+++ b/arch/sh/configs/sh7757lcr_defconfig
@@ -38,7 +38,15 @@ CONFIG_IPV6=y
38# CONFIG_WIRELESS is not set 38# CONFIG_WIRELESS is not set
39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
40# CONFIG_FW_LOADER is not set 40# CONFIG_FW_LOADER is not set
41CONFIG_MTD=y
42CONFIG_MTD_CONCAT=y
43CONFIG_MTD_PARTITIONS=y
44CONFIG_MTD_CHAR=y
45CONFIG_MTD_BLOCK=y
46CONFIG_MTD_M25P80=y
41CONFIG_BLK_DEV_RAM=y 47CONFIG_BLK_DEV_RAM=y
48CONFIG_SCSI=y
49CONFIG_BLK_DEV_SD=y
42CONFIG_NETDEVICES=y 50CONFIG_NETDEVICES=y
43CONFIG_VITESSE_PHY=y 51CONFIG_VITESSE_PHY=y
44CONFIG_NET_ETHERNET=y 52CONFIG_NET_ETHERNET=y
@@ -53,8 +61,17 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=3
53CONFIG_SERIAL_SH_SCI_CONSOLE=y 61CONFIG_SERIAL_SH_SCI_CONSOLE=y
54# CONFIG_LEGACY_PTYS is not set 62# CONFIG_LEGACY_PTYS is not set
55# CONFIG_HW_RANDOM is not set 63# CONFIG_HW_RANDOM is not set
64CONFIG_SPI=y
65CONFIG_SPI_SH=y
56# CONFIG_HWMON is not set 66# CONFIG_HWMON is not set
57# CONFIG_USB_SUPPORT is not set 67CONFIG_MFD_SH_MOBILE_SDHI=y
68CONFIG_USB=y
69CONFIG_USB_EHCI_HCD=y
70CONFIG_USB_OHCI_HCD=y
71CONFIG_USB_STORAGE=y
72CONFIG_MMC=y
73CONFIG_MMC_TMIO=y
74CONFIG_MMC_SH_MMCIF=y
58CONFIG_EXT2_FS=y 75CONFIG_EXT2_FS=y
59CONFIG_EXT3_FS=y 76CONFIG_EXT3_FS=y
60CONFIG_ISO9660_FS=y 77CONFIG_ISO9660_FS=y
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 96e9b058aa1d..4418f9070ed1 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -1,16 +1,19 @@
1/* 1/*
2 * Low-Level PCI Express Support for the SH7786 2 * Low-Level PCI Express Support for the SH7786
3 * 3 *
4 * Copyright (C) 2009 - 2010 Paul Mundt 4 * Copyright (C) 2009 - 2011 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10#define pr_fmt(fmt) "PCI: " fmt
11
10#include <linux/pci.h> 12#include <linux/pci.h>
11#include <linux/init.h> 13#include <linux/init.h>
12#include <linux/kernel.h> 14#include <linux/kernel.h>
13#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/async.h>
14#include <linux/delay.h> 17#include <linux/delay.h>
15#include <linux/slab.h> 18#include <linux/slab.h>
16#include <linux/clk.h> 19#include <linux/clk.h>
@@ -31,7 +34,7 @@ static unsigned int nr_ports;
31 34
32static struct sh7786_pcie_hwops { 35static struct sh7786_pcie_hwops {
33 int (*core_init)(void); 36 int (*core_init)(void);
34 int (*port_init_hw)(struct sh7786_pcie_port *port); 37 async_func_ptr *port_init_hw;
35} *sh7786_pcie_hwops; 38} *sh7786_pcie_hwops;
36 39
37static struct resource sh7786_pci0_resources[] = { 40static struct resource sh7786_pci0_resources[] = {
@@ -474,8 +477,9 @@ static int __init sh7786_pcie_core_init(void)
474 return test_mode_pin(MODE_PIN12) ? 3 : 2; 477 return test_mode_pin(MODE_PIN12) ? 3 : 2;
475} 478}
476 479
477static int __init sh7786_pcie_init_hw(struct sh7786_pcie_port *port) 480static void __init sh7786_pcie_init_hw(void *data, async_cookie_t cookie)
478{ 481{
482 struct sh7786_pcie_port *port = data;
479 int ret; 483 int ret;
480 484
481 /* 485 /*
@@ -488,18 +492,30 @@ static int __init sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
488 * Setup clocks, needed both for PHY and PCIe registers. 492 * Setup clocks, needed both for PHY and PCIe registers.
489 */ 493 */
490 ret = pcie_clk_init(port); 494 ret = pcie_clk_init(port);
491 if (unlikely(ret < 0)) 495 if (unlikely(ret < 0)) {
492 return ret; 496 pr_err("clock initialization failed for port#%d\n",
497 port->index);
498 return;
499 }
493 500
494 ret = phy_init(port); 501 ret = phy_init(port);
495 if (unlikely(ret < 0)) 502 if (unlikely(ret < 0)) {
496 return ret; 503 pr_err("phy initialization failed for port#%d\n",
504 port->index);
505 return;
506 }
497 507
498 ret = pcie_init(port); 508 ret = pcie_init(port);
499 if (unlikely(ret < 0)) 509 if (unlikely(ret < 0)) {
500 return ret; 510 pr_err("core initialization failed for port#%d\n",
511 port->index);
512 return;
513 }
501 514
502 return register_pci_controller(port->hose); 515 /* In the interest of preserving device ordering, synchronize */
516 async_synchronize_cookie(cookie);
517
518 register_pci_controller(port->hose);
503} 519}
504 520
505static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { 521static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
@@ -510,7 +526,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
510static int __init sh7786_pcie_init(void) 526static int __init sh7786_pcie_init(void)
511{ 527{
512 struct clk *platclk; 528 struct clk *platclk;
513 int ret = 0, i; 529 int i;
514 530
515 printk(KERN_NOTICE "PCI: Starting initialization.\n"); 531 printk(KERN_NOTICE "PCI: Starting initialization.\n");
516 532
@@ -552,14 +568,10 @@ static int __init sh7786_pcie_init(void)
552 port->hose = sh7786_pci_channels + i; 568 port->hose = sh7786_pci_channels + i;
553 port->hose->io_map_base = port->hose->resources[0].start; 569 port->hose->io_map_base = port->hose->resources[0].start;
554 570
555 ret |= sh7786_pcie_hwops->port_init_hw(port); 571 async_schedule(sh7786_pcie_hwops->port_init_hw, port);
556 } 572 }
557 573
558 if (unlikely(ret)) { 574 async_synchronize_full();
559 clk_disable(platclk);
560 clk_put(platclk);
561 return ret;
562 }
563 575
564 return 0; 576 return 0;
565} 577}
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index d6741fca89a4..b5a74e88028d 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -369,8 +369,11 @@
369#define __NR_recvmsg 356 369#define __NR_recvmsg 356
370#define __NR_recvmmsg 357 370#define __NR_recvmmsg 357
371#define __NR_accept4 358 371#define __NR_accept4 358
372#define __NR_name_to_handle_at 359
373#define __NR_open_by_handle_at 360
374#define __NR_clock_adjtime 361
372 375
373#define NR_syscalls 359 376#define NR_syscalls 362
374 377
375#ifdef __KERNEL__ 378#ifdef __KERNEL__
376 379
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 09aa93f9eb70..953da4a52199 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -390,10 +390,13 @@
390#define __NR_fanotify_init 367 390#define __NR_fanotify_init 367
391#define __NR_fanotify_mark 368 391#define __NR_fanotify_mark 368
392#define __NR_prlimit64 369 392#define __NR_prlimit64 369
393#define __NR_name_to_handle_at 370
394#define __NR_open_by_handle_at 371
395#define __NR_clock_adjtime 372
393 396
394#ifdef __KERNEL__ 397#ifdef __KERNEL__
395 398
396#define NR_syscalls 370 399#define NR_syscalls 373
397 400
398#define __ARCH_WANT_IPC_PARSE_VERSION 401#define __ARCH_WANT_IPC_PARSE_VERSION
399#define __ARCH_WANT_OLD_READDIR 402#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h
index 9a6125eb0079..18fa80aba15e 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-register.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h
@@ -40,6 +40,11 @@
40#define CHCR_TS_LOW_SHIFT 3 40#define CHCR_TS_LOW_SHIFT 3
41#define CHCR_TS_HIGH_MASK 0 41#define CHCR_TS_HIGH_MASK 0
42#define CHCR_TS_HIGH_SHIFT 0 42#define CHCR_TS_HIGH_SHIFT 0
43#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
44#define CHCR_TS_LOW_MASK 0x00000018
45#define CHCR_TS_LOW_SHIFT 3
46#define CHCR_TS_HIGH_MASK 0x00100000
47#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
43#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 48#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
44#define CHCR_TS_LOW_MASK 0x00000018 49#define CHCR_TS_LOW_MASK 0x00000018
45#define CHCR_TS_LOW_SHIFT 3 50#define CHCR_TS_LOW_SHIFT 3
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h
index 15f3de11c55a..05b8196c7753 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7757.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h
@@ -251,4 +251,36 @@ enum {
251 GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, 251 GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0,
252}; 252};
253 253
254enum {
255 SHDMA_SLAVE_SDHI_TX,
256 SHDMA_SLAVE_SDHI_RX,
257 SHDMA_SLAVE_MMCIF_TX,
258 SHDMA_SLAVE_MMCIF_RX,
259 SHDMA_SLAVE_SCIF2_TX,
260 SHDMA_SLAVE_SCIF2_RX,
261 SHDMA_SLAVE_SCIF3_TX,
262 SHDMA_SLAVE_SCIF3_RX,
263 SHDMA_SLAVE_SCIF4_TX,
264 SHDMA_SLAVE_SCIF4_RX,
265 SHDMA_SLAVE_RIIC0_TX,
266 SHDMA_SLAVE_RIIC0_RX,
267 SHDMA_SLAVE_RIIC1_TX,
268 SHDMA_SLAVE_RIIC1_RX,
269 SHDMA_SLAVE_RIIC2_TX,
270 SHDMA_SLAVE_RIIC2_RX,
271 SHDMA_SLAVE_RIIC3_TX,
272 SHDMA_SLAVE_RIIC3_RX,
273 SHDMA_SLAVE_RIIC4_TX,
274 SHDMA_SLAVE_RIIC4_RX,
275 SHDMA_SLAVE_RIIC5_TX,
276 SHDMA_SLAVE_RIIC5_RX,
277 SHDMA_SLAVE_RIIC6_TX,
278 SHDMA_SLAVE_RIIC6_RX,
279 SHDMA_SLAVE_RIIC7_TX,
280 SHDMA_SLAVE_RIIC7_RX,
281 SHDMA_SLAVE_RIIC8_TX,
282 SHDMA_SLAVE_RIIC8_RX,
283 SHDMA_SLAVE_RIIC9_TX,
284 SHDMA_SLAVE_RIIC9_RX,
285};
254#endif /* __ASM_SH7757_H__ */ 286#endif /* __ASM_SH7757_H__ */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index e073e3eb4c3d..eedddad13835 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -77,9 +77,10 @@ struct clk div4_clks[DIV4_NR] = {
77 77
78#define MSTPCR0 0xffc80030 78#define MSTPCR0 0xffc80030
79#define MSTPCR1 0xffc80034 79#define MSTPCR1 0xffc80034
80#define MSTPCR2 0xffc10028
80 81
81enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112, 82enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
82 MSTP111, MSTP110, MSTP103, MSTP102, 83 MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
83 MSTP_NR }; 84 MSTP_NR };
84 85
85static struct clk mstp_clks[MSTP_NR] = { 86static struct clk mstp_clks[MSTP_NR] = {
@@ -95,6 +96,9 @@ static struct clk mstp_clks[MSTP_NR] = {
95 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), 96 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
96 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), 97 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
97 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), 98 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
99
100 /* MSTPCR2 */
101 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
98}; 102};
99 103
100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 104#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
@@ -140,6 +144,7 @@ static struct clk_lookup lookups[] = {
140 .clk = &mstp_clks[MSTP110], 144 .clk = &mstp_clks[MSTP110],
141 }, 145 },
142 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), 146 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
147 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
143}; 148};
144 149
145int __init arch_clk_init(void) 150int __init arch_clk_init(void)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 9c1de2633ac3..423dabf542d3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7757 Setup 2 * SH7757 Setup
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009, 2011 Renesas Solutions Corp.
5 * 5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 * 7 *
@@ -16,6 +16,10 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/sh_timer.h> 18#include <linux/sh_timer.h>
19#include <linux/sh_dma.h>
20
21#include <cpu/dma-register.h>
22#include <cpu/sh7757.h>
19 23
20static struct plat_sci_port scif2_platform_data = { 24static struct plat_sci_port scif2_platform_data = {
21 .mapbase = 0xfe4b0000, /* SCIF2 */ 25 .mapbase = 0xfe4b0000, /* SCIF2 */
@@ -124,12 +128,548 @@ static struct platform_device tmu1_device = {
124 .num_resources = ARRAY_SIZE(tmu1_resources), 128 .num_resources = ARRAY_SIZE(tmu1_resources),
125}; 129};
126 130
131static struct resource spi0_resources[] = {
132 [0] = {
133 .start = 0xfe002000,
134 .end = 0xfe0020ff,
135 .flags = IORESOURCE_MEM,
136 },
137 [1] = {
138 .start = 86,
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143/* DMA */
144static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
145 {
146 .slave_id = SHDMA_SLAVE_SDHI_TX,
147 .addr = 0x1fe50030,
148 .chcr = SM_INC | 0x800 | 0x40000000 |
149 TS_INDEX2VAL(XMIT_SZ_16BIT),
150 .mid_rid = 0xc5,
151 },
152 {
153 .slave_id = SHDMA_SLAVE_SDHI_RX,
154 .addr = 0x1fe50030,
155 .chcr = DM_INC | 0x800 | 0x40000000 |
156 TS_INDEX2VAL(XMIT_SZ_16BIT),
157 .mid_rid = 0xc6,
158 },
159 {
160 .slave_id = SHDMA_SLAVE_MMCIF_TX,
161 .addr = 0x1fcb0034,
162 .chcr = SM_INC | 0x800 | 0x40000000 |
163 TS_INDEX2VAL(XMIT_SZ_32BIT),
164 .mid_rid = 0xd3,
165 },
166 {
167 .slave_id = SHDMA_SLAVE_MMCIF_RX,
168 .addr = 0x1fcb0034,
169 .chcr = DM_INC | 0x800 | 0x40000000 |
170 TS_INDEX2VAL(XMIT_SZ_32BIT),
171 .mid_rid = 0xd7,
172 },
173};
174
175static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
176 {
177 .slave_id = SHDMA_SLAVE_SCIF2_TX,
178 .addr = 0x1f4b000c,
179 .chcr = SM_INC | 0x800 | 0x40000000 |
180 TS_INDEX2VAL(XMIT_SZ_8BIT),
181 .mid_rid = 0x21,
182 },
183 {
184 .slave_id = SHDMA_SLAVE_SCIF2_RX,
185 .addr = 0x1f4b0014,
186 .chcr = SM_INC | 0x800 | 0x40000000 |
187 TS_INDEX2VAL(XMIT_SZ_8BIT),
188 .mid_rid = 0x22,
189 },
190 {
191 .slave_id = SHDMA_SLAVE_SCIF3_TX,
192 .addr = 0x1f4c000c,
193 .chcr = SM_INC | 0x800 | 0x40000000 |
194 TS_INDEX2VAL(XMIT_SZ_8BIT),
195 .mid_rid = 0x29,
196 },
197 {
198 .slave_id = SHDMA_SLAVE_SCIF3_RX,
199 .addr = 0x1f4c0014,
200 .chcr = SM_INC | 0x800 | 0x40000000 |
201 TS_INDEX2VAL(XMIT_SZ_8BIT),
202 .mid_rid = 0x2a,
203 },
204 {
205 .slave_id = SHDMA_SLAVE_SCIF4_TX,
206 .addr = 0x1f4d000c,
207 .chcr = SM_INC | 0x800 | 0x40000000 |
208 TS_INDEX2VAL(XMIT_SZ_8BIT),
209 .mid_rid = 0x41,
210 },
211 {
212 .slave_id = SHDMA_SLAVE_SCIF4_RX,
213 .addr = 0x1f4d0014,
214 .chcr = SM_INC | 0x800 | 0x40000000 |
215 TS_INDEX2VAL(XMIT_SZ_8BIT),
216 .mid_rid = 0x42,
217 },
218};
219
220static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
221 {
222 .slave_id = SHDMA_SLAVE_RIIC0_TX,
223 .addr = 0x1e500012,
224 .chcr = SM_INC | 0x800 | 0x40000000 |
225 TS_INDEX2VAL(XMIT_SZ_8BIT),
226 .mid_rid = 0x21,
227 },
228 {
229 .slave_id = SHDMA_SLAVE_RIIC0_RX,
230 .addr = 0x1e500013,
231 .chcr = SM_INC | 0x800 | 0x40000000 |
232 TS_INDEX2VAL(XMIT_SZ_8BIT),
233 .mid_rid = 0x22,
234 },
235 {
236 .slave_id = SHDMA_SLAVE_RIIC1_TX,
237 .addr = 0x1e510012,
238 .chcr = SM_INC | 0x800 | 0x40000000 |
239 TS_INDEX2VAL(XMIT_SZ_8BIT),
240 .mid_rid = 0x29,
241 },
242 {
243 .slave_id = SHDMA_SLAVE_RIIC1_RX,
244 .addr = 0x1e510013,
245 .chcr = SM_INC | 0x800 | 0x40000000 |
246 TS_INDEX2VAL(XMIT_SZ_8BIT),
247 .mid_rid = 0x2a,
248 },
249 {
250 .slave_id = SHDMA_SLAVE_RIIC2_TX,
251 .addr = 0x1e520012,
252 .chcr = SM_INC | 0x800 | 0x40000000 |
253 TS_INDEX2VAL(XMIT_SZ_8BIT),
254 .mid_rid = 0xa1,
255 },
256 {
257 .slave_id = SHDMA_SLAVE_RIIC2_RX,
258 .addr = 0x1e520013,
259 .chcr = SM_INC | 0x800 | 0x40000000 |
260 TS_INDEX2VAL(XMIT_SZ_8BIT),
261 .mid_rid = 0xa2,
262 },
263 {
264 .slave_id = SHDMA_SLAVE_RIIC3_TX,
265 .addr = 0x1e530012,
266 .chcr = SM_INC | 0x800 | 0x40000000 |
267 TS_INDEX2VAL(XMIT_SZ_8BIT),
268 .mid_rid = 0xab,
269 },
270 {
271 .slave_id = SHDMA_SLAVE_RIIC3_RX,
272 .addr = 0x1e530013,
273 .chcr = SM_INC | 0x800 | 0x40000000 |
274 TS_INDEX2VAL(XMIT_SZ_8BIT),
275 .mid_rid = 0xaf,
276 },
277 {
278 .slave_id = SHDMA_SLAVE_RIIC4_TX,
279 .addr = 0x1e540012,
280 .chcr = SM_INC | 0x800 | 0x40000000 |
281 TS_INDEX2VAL(XMIT_SZ_8BIT),
282 .mid_rid = 0xc1,
283 },
284 {
285 .slave_id = SHDMA_SLAVE_RIIC4_RX,
286 .addr = 0x1e540013,
287 .chcr = SM_INC | 0x800 | 0x40000000 |
288 TS_INDEX2VAL(XMIT_SZ_8BIT),
289 .mid_rid = 0xc2,
290 },
291};
292
293static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
294 {
295 .slave_id = SHDMA_SLAVE_RIIC5_TX,
296 .addr = 0x1e550012,
297 .chcr = SM_INC | 0x800 | 0x40000000 |
298 TS_INDEX2VAL(XMIT_SZ_8BIT),
299 .mid_rid = 0x21,
300 },
301 {
302 .slave_id = SHDMA_SLAVE_RIIC5_RX,
303 .addr = 0x1e550013,
304 .chcr = SM_INC | 0x800 | 0x40000000 |
305 TS_INDEX2VAL(XMIT_SZ_8BIT),
306 .mid_rid = 0x22,
307 },
308 {
309 .slave_id = SHDMA_SLAVE_RIIC6_TX,
310 .addr = 0x1e560012,
311 .chcr = SM_INC | 0x800 | 0x40000000 |
312 TS_INDEX2VAL(XMIT_SZ_8BIT),
313 .mid_rid = 0x29,
314 },
315 {
316 .slave_id = SHDMA_SLAVE_RIIC6_RX,
317 .addr = 0x1e560013,
318 .chcr = SM_INC | 0x800 | 0x40000000 |
319 TS_INDEX2VAL(XMIT_SZ_8BIT),
320 .mid_rid = 0x2a,
321 },
322 {
323 .slave_id = SHDMA_SLAVE_RIIC7_TX,
324 .addr = 0x1e570012,
325 .chcr = SM_INC | 0x800 | 0x40000000 |
326 TS_INDEX2VAL(XMIT_SZ_8BIT),
327 .mid_rid = 0x41,
328 },
329 {
330 .slave_id = SHDMA_SLAVE_RIIC7_RX,
331 .addr = 0x1e570013,
332 .chcr = SM_INC | 0x800 | 0x40000000 |
333 TS_INDEX2VAL(XMIT_SZ_8BIT),
334 .mid_rid = 0x42,
335 },
336 {
337 .slave_id = SHDMA_SLAVE_RIIC8_TX,
338 .addr = 0x1e580012,
339 .chcr = SM_INC | 0x800 | 0x40000000 |
340 TS_INDEX2VAL(XMIT_SZ_8BIT),
341 .mid_rid = 0x45,
342 },
343 {
344 .slave_id = SHDMA_SLAVE_RIIC8_RX,
345 .addr = 0x1e580013,
346 .chcr = SM_INC | 0x800 | 0x40000000 |
347 TS_INDEX2VAL(XMIT_SZ_8BIT),
348 .mid_rid = 0x46,
349 },
350 {
351 .slave_id = SHDMA_SLAVE_RIIC9_TX,
352 .addr = 0x1e590012,
353 .chcr = SM_INC | 0x800 | 0x40000000 |
354 TS_INDEX2VAL(XMIT_SZ_8BIT),
355 .mid_rid = 0x51,
356 },
357 {
358 .slave_id = SHDMA_SLAVE_RIIC9_RX,
359 .addr = 0x1e590013,
360 .chcr = SM_INC | 0x800 | 0x40000000 |
361 TS_INDEX2VAL(XMIT_SZ_8BIT),
362 .mid_rid = 0x52,
363 },
364};
365
366static const struct sh_dmae_channel sh7757_dmae_channels[] = {
367 {
368 .offset = 0,
369 .dmars = 0,
370 .dmars_bit = 0,
371 }, {
372 .offset = 0x10,
373 .dmars = 0,
374 .dmars_bit = 8,
375 }, {
376 .offset = 0x20,
377 .dmars = 4,
378 .dmars_bit = 0,
379 }, {
380 .offset = 0x30,
381 .dmars = 4,
382 .dmars_bit = 8,
383 }, {
384 .offset = 0x50,
385 .dmars = 8,
386 .dmars_bit = 0,
387 }, {
388 .offset = 0x60,
389 .dmars = 8,
390 .dmars_bit = 8,
391 }
392};
393
394static const unsigned int ts_shift[] = TS_SHIFT;
395
396static struct sh_dmae_pdata dma0_platform_data = {
397 .slave = sh7757_dmae0_slaves,
398 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves),
399 .channel = sh7757_dmae_channels,
400 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
401 .ts_low_shift = CHCR_TS_LOW_SHIFT,
402 .ts_low_mask = CHCR_TS_LOW_MASK,
403 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
404 .ts_high_mask = CHCR_TS_HIGH_MASK,
405 .ts_shift = ts_shift,
406 .ts_shift_num = ARRAY_SIZE(ts_shift),
407 .dmaor_init = DMAOR_INIT,
408};
409
410static struct sh_dmae_pdata dma1_platform_data = {
411 .slave = sh7757_dmae1_slaves,
412 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves),
413 .channel = sh7757_dmae_channels,
414 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
415 .ts_low_shift = CHCR_TS_LOW_SHIFT,
416 .ts_low_mask = CHCR_TS_LOW_MASK,
417 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
418 .ts_high_mask = CHCR_TS_HIGH_MASK,
419 .ts_shift = ts_shift,
420 .ts_shift_num = ARRAY_SIZE(ts_shift),
421 .dmaor_init = DMAOR_INIT,
422};
423
424static struct sh_dmae_pdata dma2_platform_data = {
425 .slave = sh7757_dmae2_slaves,
426 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves),
427 .channel = sh7757_dmae_channels,
428 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
429 .ts_low_shift = CHCR_TS_LOW_SHIFT,
430 .ts_low_mask = CHCR_TS_LOW_MASK,
431 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
432 .ts_high_mask = CHCR_TS_HIGH_MASK,
433 .ts_shift = ts_shift,
434 .ts_shift_num = ARRAY_SIZE(ts_shift),
435 .dmaor_init = DMAOR_INIT,
436};
437
438static struct sh_dmae_pdata dma3_platform_data = {
439 .slave = sh7757_dmae3_slaves,
440 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves),
441 .channel = sh7757_dmae_channels,
442 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
443 .ts_low_shift = CHCR_TS_LOW_SHIFT,
444 .ts_low_mask = CHCR_TS_LOW_MASK,
445 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
446 .ts_high_mask = CHCR_TS_HIGH_MASK,
447 .ts_shift = ts_shift,
448 .ts_shift_num = ARRAY_SIZE(ts_shift),
449 .dmaor_init = DMAOR_INIT,
450};
451
452/* channel 0 to 5 */
453static struct resource sh7757_dmae0_resources[] = {
454 [0] = {
455 /* Channel registers and DMAOR */
456 .start = 0xff608020,
457 .end = 0xff60808f,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 /* DMARSx */
462 .start = 0xff609000,
463 .end = 0xff60900b,
464 .flags = IORESOURCE_MEM,
465 },
466 {
467 .start = 34,
468 .end = 34,
469 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
470 },
471};
472
473/* channel 6 to 11 */
474static struct resource sh7757_dmae1_resources[] = {
475 [0] = {
476 /* Channel registers and DMAOR */
477 .start = 0xff618020,
478 .end = 0xff61808f,
479 .flags = IORESOURCE_MEM,
480 },
481 [1] = {
482 /* DMARSx */
483 .start = 0xff619000,
484 .end = 0xff61900b,
485 .flags = IORESOURCE_MEM,
486 },
487 {
488 /* DMA error */
489 .start = 34,
490 .end = 34,
491 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
492 },
493 {
494 /* IRQ for channels 4 */
495 .start = 46,
496 .end = 46,
497 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
498 },
499 {
500 /* IRQ for channels 5 */
501 .start = 46,
502 .end = 46,
503 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
504 },
505 {
506 /* IRQ for channels 6 */
507 .start = 88,
508 .end = 88,
509 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
510 },
511 {
512 /* IRQ for channels 7 */
513 .start = 88,
514 .end = 88,
515 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
516 },
517 {
518 /* IRQ for channels 8 */
519 .start = 88,
520 .end = 88,
521 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
522 },
523 {
524 /* IRQ for channels 9 */
525 .start = 88,
526 .end = 88,
527 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
528 },
529 {
530 /* IRQ for channels 10 */
531 .start = 88,
532 .end = 88,
533 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
534 },
535 {
536 /* IRQ for channels 11 */
537 .start = 88,
538 .end = 88,
539 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
540 },
541};
542
543/* channel 12 to 17 */
544static struct resource sh7757_dmae2_resources[] = {
545 [0] = {
546 /* Channel registers and DMAOR */
547 .start = 0xff708020,
548 .end = 0xff70808f,
549 .flags = IORESOURCE_MEM,
550 },
551 [1] = {
552 /* DMARSx */
553 .start = 0xff709000,
554 .end = 0xff70900b,
555 .flags = IORESOURCE_MEM,
556 },
557 {
558 /* DMA error */
559 .start = 323,
560 .end = 323,
561 .flags = IORESOURCE_IRQ,
562 },
563 {
564 /* IRQ for channels 12 to 16 */
565 .start = 272,
566 .end = 276,
567 .flags = IORESOURCE_IRQ,
568 },
569 {
570 /* IRQ for channel 17 */
571 .start = 279,
572 .end = 279,
573 .flags = IORESOURCE_IRQ,
574 },
575};
576
577/* channel 18 to 23 */
578static struct resource sh7757_dmae3_resources[] = {
579 [0] = {
580 /* Channel registers and DMAOR */
581 .start = 0xff718020,
582 .end = 0xff71808f,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 /* DMARSx */
587 .start = 0xff719000,
588 .end = 0xff71900b,
589 .flags = IORESOURCE_MEM,
590 },
591 {
592 /* DMA error */
593 .start = 324,
594 .end = 324,
595 .flags = IORESOURCE_IRQ,
596 },
597 {
598 /* IRQ for channels 18 to 22 */
599 .start = 280,
600 .end = 284,
601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 /* IRQ for channel 23 */
605 .start = 288,
606 .end = 288,
607 .flags = IORESOURCE_IRQ,
608 },
609};
610
611static struct platform_device dma0_device = {
612 .name = "sh-dma-engine",
613 .id = 0,
614 .resource = sh7757_dmae0_resources,
615 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources),
616 .dev = {
617 .platform_data = &dma0_platform_data,
618 },
619};
620
621static struct platform_device dma1_device = {
622 .name = "sh-dma-engine",
623 .id = 1,
624 .resource = sh7757_dmae1_resources,
625 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources),
626 .dev = {
627 .platform_data = &dma1_platform_data,
628 },
629};
630
631static struct platform_device dma2_device = {
632 .name = "sh-dma-engine",
633 .id = 2,
634 .resource = sh7757_dmae2_resources,
635 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources),
636 .dev = {
637 .platform_data = &dma2_platform_data,
638 },
639};
640
641static struct platform_device dma3_device = {
642 .name = "sh-dma-engine",
643 .id = 3,
644 .resource = sh7757_dmae3_resources,
645 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources),
646 .dev = {
647 .platform_data = &dma3_platform_data,
648 },
649};
650
651static struct platform_device spi0_device = {
652 .name = "sh_spi",
653 .id = 0,
654 .dev = {
655 .dma_mask = NULL,
656 .coherent_dma_mask = 0xffffffff,
657 },
658 .num_resources = ARRAY_SIZE(spi0_resources),
659 .resource = spi0_resources,
660};
661
127static struct platform_device *sh7757_devices[] __initdata = { 662static struct platform_device *sh7757_devices[] __initdata = {
128 &scif2_device, 663 &scif2_device,
129 &scif3_device, 664 &scif3_device,
130 &scif4_device, 665 &scif4_device,
131 &tmu0_device, 666 &tmu0_device,
132 &tmu1_device, 667 &tmu1_device,
668 &dma0_device,
669 &dma1_device,
670 &dma2_device,
671 &dma3_device,
672 &spi0_device,
133}; 673};
134 674
135static int __init sh7757_devices_setup(void) 675static int __init sh7757_devices_setup(void)
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index c19e2a940e3f..e4469e7233cb 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -75,7 +75,7 @@ void sh_mobile_setup_cpuidle(void)
75 i = CPUIDLE_DRIVER_STATE_START; 75 i = CPUIDLE_DRIVER_STATE_START;
76 76
77 state = &dev->states[i++]; 77 state = &dev->states[i++];
78 snprintf(state->name, CPUIDLE_NAME_LEN, "C0"); 78 snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
79 strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN); 79 strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN);
80 state->exit_latency = 1; 80 state->exit_latency = 1;
81 state->target_residency = 1 * 2; 81 state->target_residency = 1 * 2;
@@ -88,7 +88,7 @@ void sh_mobile_setup_cpuidle(void)
88 88
89 if (sh_mobile_sleep_supported & SUSP_SH_SF) { 89 if (sh_mobile_sleep_supported & SUSP_SH_SF) {
90 state = &dev->states[i++]; 90 state = &dev->states[i++];
91 snprintf(state->name, CPUIDLE_NAME_LEN, "C1"); 91 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
92 strncpy(state->desc, "SuperH Sleep Mode [SF]", 92 strncpy(state->desc, "SuperH Sleep Mode [SF]",
93 CPUIDLE_DESC_LEN); 93 CPUIDLE_DESC_LEN);
94 state->exit_latency = 100; 94 state->exit_latency = 100;
@@ -101,7 +101,7 @@ void sh_mobile_setup_cpuidle(void)
101 101
102 if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) { 102 if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) {
103 state = &dev->states[i++]; 103 state = &dev->states[i++];
104 snprintf(state->name, CPUIDLE_NAME_LEN, "C2"); 104 snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
105 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]", 105 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]",
106 CPUIDLE_DESC_LEN); 106 CPUIDLE_DESC_LEN);
107 state->exit_latency = 2300; 107 state->exit_latency = 2300;
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 68ecbe6c881a..64ea0b165399 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -34,9 +34,9 @@ void ack_bad_irq(unsigned int irq)
34 34
35#if defined(CONFIG_PROC_FS) 35#if defined(CONFIG_PROC_FS)
36/* 36/*
37 * /proc/interrupts printing: 37 * /proc/interrupts printing for arch specific interrupts
38 */ 38 */
39static int show_other_interrupts(struct seq_file *p, int prec) 39int arch_show_interrupts(struct seq_file *p, int prec)
40{ 40{
41 int j; 41 int j;
42 42
@@ -49,63 +49,6 @@ static int show_other_interrupts(struct seq_file *p, int prec)
49 49
50 return 0; 50 return 0;
51} 51}
52
53int show_interrupts(struct seq_file *p, void *v)
54{
55 unsigned long flags, any_count = 0;
56 int i = *(loff_t *)v, j, prec;
57 struct irqaction *action;
58 struct irq_desc *desc;
59 struct irq_data *data;
60 struct irq_chip *chip;
61
62 if (i > nr_irqs)
63 return 0;
64
65 for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
66 j *= 10;
67
68 if (i == nr_irqs)
69 return show_other_interrupts(p, prec);
70
71 if (i == 0) {
72 seq_printf(p, "%*s", prec + 8, "");
73 for_each_online_cpu(j)
74 seq_printf(p, "CPU%-8d", j);
75 seq_putc(p, '\n');
76 }
77
78 desc = irq_to_desc(i);
79 if (!desc)
80 return 0;
81
82 data = irq_get_irq_data(i);
83 chip = irq_data_get_irq_chip(data);
84
85 raw_spin_lock_irqsave(&desc->lock, flags);
86 for_each_online_cpu(j)
87 any_count |= kstat_irqs_cpu(i, j);
88 action = desc->action;
89 if (!action && !any_count)
90 goto out;
91
92 seq_printf(p, "%*d: ", prec, i);
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
95 seq_printf(p, " %14s", chip->name);
96 seq_printf(p, "-%-8s", desc->name);
97
98 if (action) {
99 seq_printf(p, " %s", action->name);
100 while ((action = action->next) != NULL)
101 seq_printf(p, ", %s", action->name);
102 }
103
104 seq_putc(p, '\n');
105out:
106 raw_spin_unlock_irqrestore(&desc->lock, flags);
107 return 0;
108}
109#endif 52#endif
110 53
111#ifdef CONFIG_IRQSTACKS 54#ifdef CONFIG_IRQSTACKS
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 6fc347ebe59d..768fb33fdd35 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -376,3 +376,6 @@ ENTRY(sys_call_table)
376 .long sys_recvmsg 376 .long sys_recvmsg
377 .long sys_recvmmsg 377 .long sys_recvmmsg
378 .long sys_accept4 378 .long sys_accept4
379 .long sys_name_to_handle_at
380 .long sys_open_by_handle_at /* 360 */
381 .long sys_clock_adjtime
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index 66585708ce90..44e7b00c8067 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -396,3 +396,6 @@ sys_call_table:
396 .long sys_fanotify_init 396 .long sys_fanotify_init
397 .long sys_fanotify_mark 397 .long sys_fanotify_mark
398 .long sys_prlimit64 398 .long sys_prlimit64
399 .long sys_name_to_handle_at /* 370 */
400 .long sys_open_by_handle_at
401 .long sys_clock_adjtime
diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile
index 150aa326afff..2228c8cee4d6 100644
--- a/arch/sh/mm/Makefile
+++ b/arch/sh/mm/Makefile
@@ -42,6 +42,8 @@ obj-$(CONFIG_IOREMAP_FIXED) += ioremap_fixed.o
42obj-$(CONFIG_UNCACHED_MAPPING) += uncached.o 42obj-$(CONFIG_UNCACHED_MAPPING) += uncached.o
43obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o 43obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o
44 44
45GCOV_PROFILE_pmb.o := n
46
45# Special flags for fault_64.o. This puts restrictions on the number of 47# Special flags for fault_64.o. This puts restrictions on the number of
46# caller-save registers that the compiler can target when building this file. 48# caller-save registers that the compiler can target when building this file.
47# This is required because the code is called from a context in entry.S where 49# This is required because the code is called from a context in entry.S where
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 18:59:46 -0400