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-rw-r--r--arch/sh/kernel/cpu/Makefile1
-rw-r--r--arch/sh/kernel/cpu/clock.c95
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c34
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c65
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c224
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c236
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c154
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh3/entry.S357
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c61
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c68
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c69
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c68
-rw-r--r--arch/sh/kernel/cpu/sh3/swsusp.S147
-rw-r--r--arch/sh/kernel/cpu/sh4/Makefile1
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c7
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c87
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c148
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c950
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c34
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c114
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c97
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c95
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c490
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile6
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm.c92
-rw-r--r--arch/sh/kernel/cpu/shmobile/sleep.S125
31 files changed, 2859 insertions, 1073 deletions
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index f471d242774e..2600641a483f 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SH5) = sh5/
11# Special cases for family ancestry. 11# Special cases for family ancestry.
12 12
13obj-$(CONFIG_CPU_SH4A) += sh4a/ 13obj-$(CONFIG_CPU_SH4A) += sh4a/
14obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
14 15
15# Common interfaces. 16# Common interfaces.
16 17
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 7b17137536d6..1dc896483b59 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -20,6 +20,8 @@
20#include <linux/mutex.h> 20#include <linux/mutex.h>
21#include <linux/list.h> 21#include <linux/list.h>
22#include <linux/kref.h> 22#include <linux/kref.h>
23#include <linux/kobject.h>
24#include <linux/sysdev.h>
23#include <linux/seq_file.h> 25#include <linux/seq_file.h>
24#include <linux/err.h> 26#include <linux/err.h>
25#include <linux/platform_device.h> 27#include <linux/platform_device.h>
@@ -239,6 +241,35 @@ void clk_recalc_rate(struct clk *clk)
239} 241}
240EXPORT_SYMBOL_GPL(clk_recalc_rate); 242EXPORT_SYMBOL_GPL(clk_recalc_rate);
241 243
244int clk_set_parent(struct clk *clk, struct clk *parent)
245{
246 int ret = -EINVAL;
247 struct clk *old;
248
249 if (!parent || !clk)
250 return ret;
251
252 old = clk->parent;
253 if (likely(clk->ops && clk->ops->set_parent)) {
254 unsigned long flags;
255 spin_lock_irqsave(&clock_lock, flags);
256 ret = clk->ops->set_parent(clk, parent);
257 spin_unlock_irqrestore(&clock_lock, flags);
258 clk->parent = (ret ? old : parent);
259 }
260
261 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
262 propagate_rate(clk);
263 return ret;
264}
265EXPORT_SYMBOL_GPL(clk_set_parent);
266
267struct clk *clk_get_parent(struct clk *clk)
268{
269 return clk->parent;
270}
271EXPORT_SYMBOL_GPL(clk_get_parent);
272
242long clk_round_rate(struct clk *clk, unsigned long rate) 273long clk_round_rate(struct clk *clk, unsigned long rate)
243{ 274{
244 if (likely(clk->ops && clk->ops->round_rate)) { 275 if (likely(clk->ops && clk->ops->round_rate)) {
@@ -329,6 +360,70 @@ static int show_clocks(char *buf, char **start, off_t off,
329 return p - buf; 360 return p - buf;
330} 361}
331 362
363#ifdef CONFIG_PM
364static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
365{
366 static pm_message_t prev_state;
367 struct clk *clkp;
368
369 switch (state.event) {
370 case PM_EVENT_ON:
371 /* Resumeing from hibernation */
372 if (prev_state.event == PM_EVENT_FREEZE) {
373 list_for_each_entry(clkp, &clock_list, node)
374 if (likely(clkp->ops)) {
375 unsigned long rate = clkp->rate;
376
377 if (likely(clkp->ops->set_parent))
378 clkp->ops->set_parent(clkp,
379 clkp->parent);
380 if (likely(clkp->ops->set_rate))
381 clkp->ops->set_rate(clkp,
382 rate, NO_CHANGE);
383 else if (likely(clkp->ops->recalc))
384 clkp->ops->recalc(clkp);
385 }
386 }
387 break;
388 case PM_EVENT_FREEZE:
389 break;
390 case PM_EVENT_SUSPEND:
391 break;
392 }
393
394 prev_state = state;
395 return 0;
396}
397
398static int clks_sysdev_resume(struct sys_device *dev)
399{
400 return clks_sysdev_suspend(dev, PMSG_ON);
401}
402
403static struct sysdev_class clks_sysdev_class = {
404 .name = "clks",
405};
406
407static struct sysdev_driver clks_sysdev_driver = {
408 .suspend = clks_sysdev_suspend,
409 .resume = clks_sysdev_resume,
410};
411
412static struct sys_device clks_sysdev_dev = {
413 .cls = &clks_sysdev_class,
414};
415
416static int __init clk_sysdev_init(void)
417{
418 sysdev_class_register(&clks_sysdev_class);
419 sysdev_driver_register(&clks_sysdev_class, &clks_sysdev_driver);
420 sysdev_register(&clks_sysdev_dev);
421
422 return 0;
423}
424subsys_initcall(clk_sysdev_init);
425#endif
426
332int __init clk_init(void) 427int __init clk_init(void)
333{ 428{
334 int i, ret = 0; 429 int i, ret = 0;
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 56e5878e5516..0e32d8e448ca 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -2,6 +2,7 @@
2 * SH7619 Setup 2 * SH7619 Setup
3 * 3 *
4 * Copyright (C) 2006 Yoshinori Sato 4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -18,15 +19,10 @@ enum {
18 /* interrupt sources */ 19 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 WDT, EDMAC, CMT0, CMT1, 21 WDT, EDMAC, CMT0, CMT1,
21 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 22 SCIF0, SCIF1, SCIF2,
22 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
23 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
24 HIF_HIFI, HIF_HIFBI, 23 HIF_HIFI, HIF_HIFBI,
25 DMAC0, DMAC1, DMAC2, DMAC3, 24 DMAC0, DMAC1, DMAC2, DMAC3,
26 SIOF, 25 SIOF,
27
28 /* interrupt groups */
29 SCIF0, SCIF1, SCIF2,
30}; 26};
31 27
32static struct intc_vect vectors[] __initdata = { 28static struct intc_vect vectors[] __initdata = {
@@ -36,24 +32,18 @@ static struct intc_vect vectors[] __initdata = {
36 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83), 32 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
37 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85), 33 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
38 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87), 34 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
39 INTC_IRQ(SCIF0_ERI, 88), INTC_IRQ(SCIF0_RXI, 89), 35 INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
40 INTC_IRQ(SCIF0_BRI, 90), INTC_IRQ(SCIF0_TXI, 91), 36 INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
41 INTC_IRQ(SCIF1_ERI, 92), INTC_IRQ(SCIF1_RXI, 93), 37 INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
42 INTC_IRQ(SCIF1_BRI, 94), INTC_IRQ(SCIF1_TXI, 95), 38 INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
43 INTC_IRQ(SCIF2_ERI, 96), INTC_IRQ(SCIF2_RXI, 97), 39 INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
44 INTC_IRQ(SCIF2_BRI, 98), INTC_IRQ(SCIF2_TXI, 99), 40 INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
45 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101), 41 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
46 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105), 42 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
47 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107), 43 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
48 INTC_IRQ(SIOF, 108), 44 INTC_IRQ(SIOF, 108),
49}; 45};
50 46
51static struct intc_group groups[] __initdata = {
52 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
53 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
54 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
55};
56
57static struct intc_prio_reg prio_registers[] __initdata = { 47static struct intc_prio_reg prio_registers[] __initdata = {
58 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 48 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
59 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 49 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
@@ -64,7 +54,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
64 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } }, 54 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
65}; 55};
66 56
67static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, groups, 57static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
68 NULL, prio_registers, NULL); 58 NULL, prio_registers, NULL);
69 59
70static struct plat_sci_port sci_platform_data[] = { 60static struct plat_sci_port sci_platform_data[] = {
@@ -72,17 +62,17 @@ static struct plat_sci_port sci_platform_data[] = {
72 .mapbase = 0xf8400000, 62 .mapbase = 0xf8400000,
73 .flags = UPF_BOOT_AUTOCONF, 63 .flags = UPF_BOOT_AUTOCONF,
74 .type = PORT_SCIF, 64 .type = PORT_SCIF,
75 .irqs = { 88, 89, 91, 90}, 65 .irqs = { 88, 88, 88, 88 },
76 }, { 66 }, {
77 .mapbase = 0xf8410000, 67 .mapbase = 0xf8410000,
78 .flags = UPF_BOOT_AUTOCONF, 68 .flags = UPF_BOOT_AUTOCONF,
79 .type = PORT_SCIF, 69 .type = PORT_SCIF,
80 .irqs = { 92, 93, 95, 94}, 70 .irqs = { 92, 92, 92, 92 },
81 }, { 71 }, {
82 .mapbase = 0xf8420000, 72 .mapbase = 0xf8420000,
83 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
84 .type = PORT_SCIF, 74 .type = PORT_SCIF,
85 .irqs = { 96, 97, 99, 98}, 75 .irqs = { 96, 96, 96, 96 },
86 }, { 76 }, {
87 .flags = 0, 77 .flags = 0,
88 } 78 }
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index e611d79fac4c..844293723cfc 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Renesas MX-G (R8A03022BG) Setup 2 * Renesas MX-G (R8A03022BG) Setup
3 * 3 *
4 * Copyright (C) 2008 Paul Mundt 4 * Copyright (C) 2008, 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -20,23 +20,15 @@ enum {
20 IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15, 20 IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
21 21
22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
23
24 SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1, 23 SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
25 24
26 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 25 SCIF0, SCIF1,
27 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
28 26
29 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, 27 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
30 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, 28 MTU2_TGI3B, MTU2_TGI3C,
31 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
32 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
33 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
34 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
35 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
36 29
37 /* interrupt groups */ 30 /* interrupt groups */
38 PINT, SCIF0, SCIF1, 31 PINT,
39 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5
40}; 32};
41 33
42static struct intc_vect vectors[] __initdata = { 34static struct intc_vect vectors[] __initdata = {
@@ -59,47 +51,36 @@ static struct intc_vect vectors[] __initdata = {
59 INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99), 51 INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
60 INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101), 52 INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
61 53
62 INTC_IRQ(SCIF0_RXI, 220), INTC_IRQ(SCIF0_TXI, 221), 54 INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221),
63 INTC_IRQ(SCIF0_BRI, 222), INTC_IRQ(SCIF0_ERI, 223), 55 INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223),
64 INTC_IRQ(SCIF1_RXI, 224), INTC_IRQ(SCIF1_TXI, 225), 56 INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225),
65 INTC_IRQ(SCIF1_BRI, 226), INTC_IRQ(SCIF1_ERI, 227), 57 INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227),
66 58
67 INTC_IRQ(MTU2_TGI0A, 228), INTC_IRQ(MTU2_TGI0B, 229), 59 INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229),
68 INTC_IRQ(MTU2_TGI0C, 230), INTC_IRQ(MTU2_TGI0D, 231), 60 INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231),
69 INTC_IRQ(MTU2_TCI0V, 232), INTC_IRQ(MTU2_TGI0E, 233), 61 INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233),
70 62
71 INTC_IRQ(MTU2_TGI0F, 234), INTC_IRQ(MTU2_TGI1A, 235), 63 INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235),
72 INTC_IRQ(MTU2_TGI1B, 236), INTC_IRQ(MTU2_TCI1V, 237), 64 INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237),
73 INTC_IRQ(MTU2_TCI1U, 238), INTC_IRQ(MTU2_TGI2A, 239), 65 INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239),
74 66
75 INTC_IRQ(MTU2_TGI2B, 240), INTC_IRQ(MTU2_TCI2V, 241), 67 INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241),
76 INTC_IRQ(MTU2_TCI2U, 242), INTC_IRQ(MTU2_TGI3A, 243), 68 INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243),
77 69
78 INTC_IRQ(MTU2_TGI3B, 244), 70 INTC_IRQ(MTU2_TGI3B, 244),
79 INTC_IRQ(MTU2_TGI3C, 245), 71 INTC_IRQ(MTU2_TGI3C, 245),
80 72
81 INTC_IRQ(MTU2_TGI3D, 246), INTC_IRQ(MTU2_TCI3V, 247), 73 INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247),
82 INTC_IRQ(MTU2_TGI4A, 248), INTC_IRQ(MTU2_TGI4B, 249), 74 INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249),
83 INTC_IRQ(MTU2_TGI4C, 250), INTC_IRQ(MTU2_TGI4D, 251), 75 INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251),
84 76
85 INTC_IRQ(MTU2_TCI4V, 252), INTC_IRQ(MTU2_TGI5U, 253), 77 INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253),
86 INTC_IRQ(MTU2_TGI5V, 254), INTC_IRQ(MTU2_TGI5W, 255), 78 INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255),
87}; 79};
88 80
89static struct intc_group groups[] __initdata = { 81static struct intc_group groups[] __initdata = {
90 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 82 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
91 PINT4, PINT5, PINT6, PINT7), 83 PINT4, PINT5, PINT6, PINT7),
92 INTC_GROUP(MTU2_GROUP1, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
93 MTU2_TCI0V, MTU2_TGI0E),
94 INTC_GROUP(MTU2_GROUP2, MTU2_TGI0F, MTU2_TGI1A, MTU2_TGI1B,
95 MTU2_TCI1V, MTU2_TCI1U, MTU2_TGI2A),
96 INTC_GROUP(MTU2_GROUP3, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
97 MTU2_TGI3A),
98 INTC_GROUP(MTU2_GROUP4, MTU2_TGI3D, MTU2_TCI3V, MTU2_TGI4A,
99 MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
100 INTC_GROUP(MTU2_GROUP5, MTU2_TCI4V, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
101 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
102 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
103}; 84};
104 85
105static struct intc_prio_reg prio_registers[] __initdata = { 86static struct intc_prio_reg prio_registers[] __initdata = {
@@ -137,7 +118,7 @@ static struct plat_sci_port sci_platform_data[] = {
137 .mapbase = 0xff804000, 118 .mapbase = 0xff804000,
138 .flags = UPF_BOOT_AUTOCONF, 119 .flags = UPF_BOOT_AUTOCONF,
139 .type = PORT_SCIF, 120 .type = PORT_SCIF,
140 .irqs = { 223, 220, 221, 222 }, 121 .irqs = { 220, 220, 220, 220 },
141 }, { 122 }, {
142 .flags = 0, 123 .flags = 0,
143 } 124 }
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 0631e421c022..00f42f9e3f5c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -2,6 +2,7 @@
2 * SH7201 setup 2 * SH7201 setup
3 * 3 *
4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk 4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -18,57 +19,32 @@ enum {
18 /* interrupt sources */ 19 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 21 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
22
21 ADC_ADI, 23 ADC_ADI,
22 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, 24
23 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, 25 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
24 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, 26 MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
25 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, 27
26 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, 28 RTC, WDT,
27 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, 29
28 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W, 30 IIC30, IIC31, IIC32,
29 RTC_ARM, RTC_PRD, RTC_CUP,
30 WDT,
31 IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
32 IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
33 IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
34 31
35 DMAC0_DMINT0, DMAC1_DMINT1, 32 DMAC0_DMINT0, DMAC1_DMINT1,
36 DMAC2_DMINT2, DMAC3_DMINT3, 33 DMAC2_DMINT2, DMAC3_DMINT3,
37 34
38 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 35 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
39 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
40 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
41 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
42 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
43 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
44 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
45 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
46 36
47 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, 37 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
48 DMAC7_DMINT7, 38 DMAC7_DMINT7,
49 39
50 RCAN0_ERS, RCAN0_OVR, 40 RCAN0, RCAN1,
51 RCAN0_SLE,
52 RCAN0_RM0, RCAN0_RM1,
53
54 RCAN1_ERS, RCAN1_OVR,
55 RCAN1_SLE,
56 RCAN1_RM0, RCAN1_RM1,
57 41
58 SSI0_SSII, SSI1_SSII, 42 SSI0_SSII, SSI1_SSII,
59 43
60 TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0, 44 TMR0, TMR1,
61 TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1,
62 45
63 /* interrupt groups */ 46 /* interrupt groups */
64 47 PINT,
65 IRQ, PINT, ADC,
66 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
67 MTU23_ABCD, MTU24_ABCD, MTU25_UVW,
68 RTC, IIC30, IIC31, IIC32,
69 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
70 RCAN0, RCAN1, TMR0, TMR1
71
72}; 48};
73 49
74static struct intc_vect vectors[] __initdata = { 50static struct intc_vect vectors[] __initdata = {
@@ -76,6 +52,7 @@ static struct intc_vect vectors[] __initdata = {
76 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 52 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
77 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 53 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
78 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 54 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
55
79 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 56 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
80 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 57 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
81 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 58 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
@@ -83,123 +60,92 @@ static struct intc_vect vectors[] __initdata = {
83 60
84 INTC_IRQ(ADC_ADI, 92), 61 INTC_IRQ(ADC_ADI, 92),
85 62
86 INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109), 63 INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
87 INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111), 64 INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
88 INTC_IRQ(MTU2_TCI0V, 112), 65
89 INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114), 66 INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
67 INTC_IRQ(MTU20_VEF, 114),
68
69 INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
70 INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
90 71
91 INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117), 72 INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
92 INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121), 73 INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
93 74
94 INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125), 75 INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
95 INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129), 76 INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
96 77
97 INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133),
98 INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135),
99 INTC_IRQ(MTU2_TCI3V, 136), 78 INTC_IRQ(MTU2_TCI3V, 136),
100 79
101 INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141), 80 INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
102 INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143), 81 INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
82
103 INTC_IRQ(MTU2_TCI4V, 144), 83 INTC_IRQ(MTU2_TCI4V, 144),
104 84
105 INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149), 85 INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
106 INTC_IRQ(MTU2_TGI5W, 150), 86 INTC_IRQ(MTU25_UVW, 150),
87
88 INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
89 INTC_IRQ(RTC, 154),
107 90
108 INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153), 91 INTC_IRQ(WDT, 156),
109 INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156),
110 92
111 INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158), 93 INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
112 INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160), 94 INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
113 INTC_IRQ(IIC30_TEI, 161), 95 INTC_IRQ(IIC30, 161),
114 96
115 INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165), 97 INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
116 INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167), 98 INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
117 INTC_IRQ(IIC31_TEI, 168), 99 INTC_IRQ(IIC31, 168),
118 100
119 INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171), 101 INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
120 INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173), 102 INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
121 INTC_IRQ(IIC32_TEI, 174), 103 INTC_IRQ(IIC32, 174),
122 104
123 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), 105 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
124 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), 106 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
125 107
126 INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181), 108 INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
127 INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183), 109 INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
128 INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185), 110 INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
129 INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187), 111 INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
130 INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189), 112 INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
131 INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191), 113 INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
132 INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193), 114 INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
133 INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195), 115 INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
134 INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197), 116 INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
135 INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199), 117 INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
136 INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201), 118 INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
137 INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203), 119 INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
138 INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205), 120 INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
139 INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207), 121 INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
140 INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209), 122 INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
141 INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211), 123 INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
142 124
143 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), 125 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
144 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), 126 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
145 INTC_IRQ(DMAC7_DMINT7, 219), 127 INTC_IRQ(DMAC7_DMINT7, 219),
146 128
147 INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229), 129 INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
148 INTC_IRQ(RCAN0_SLE, 230), 130 INTC_IRQ(RCAN0, 230),
149 INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232), 131 INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
150 132
151 INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235), 133 INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
152 INTC_IRQ(RCAN1_SLE, 236), 134 INTC_IRQ(RCAN1, 236),
153 INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238), 135 INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
154 136
155 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), 137 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
156 138
157 INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247), 139 INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
158 INTC_IRQ(TMR0_OVI0, 248), 140 INTC_IRQ(TMR0, 248),
159
160 INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253),
161 INTC_IRQ(TMR1_OVI1, 254),
162 141
142 INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
143 INTC_IRQ(TMR1, 254),
163}; 144};
164 145
165static struct intc_group groups[] __initdata = { 146static struct intc_group groups[] __initdata = {
166 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 147 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
167 PINT4, PINT5, PINT6, PINT7), 148 PINT4, PINT5, PINT6, PINT7),
168 INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
169 INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
170
171 INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B),
172 INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U),
173 INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B),
174 INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U),
175 INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
176 INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
177 INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
178 INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ),
179
180 INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
181 IIC30_TEI),
182 INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
183 IIC31_TEI),
184 INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
185 IIC32_TEI),
186
187 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
188 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
189 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
190 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
191 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
192 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
193 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
194 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
195
196 INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
197 RCAN0_SLE),
198 INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
199 RCAN1_SLE),
200
201 INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0),
202 INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1),
203}; 149};
204 150
205static struct intc_prio_reg prio_registers[] __initdata = { 151static struct intc_prio_reg prio_registers[] __initdata = {
@@ -212,7 +158,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
212 158
213 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, 159 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
214 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, 160 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
215 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } }, 161 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
216 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, 162 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
217 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, 163 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
218 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, 164 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
@@ -234,42 +180,42 @@ static struct plat_sci_port sci_platform_data[] = {
234 .mapbase = 0xfffe8000, 180 .mapbase = 0xfffe8000,
235 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
236 .type = PORT_SCIF, 182 .type = PORT_SCIF,
237 .irqs = { 181, 182, 183, 180} 183 .irqs = { 180, 180, 180, 180 }
238 }, { 184 }, {
239 .mapbase = 0xfffe8800, 185 .mapbase = 0xfffe8800,
240 .flags = UPF_BOOT_AUTOCONF, 186 .flags = UPF_BOOT_AUTOCONF,
241 .type = PORT_SCIF, 187 .type = PORT_SCIF,
242 .irqs = { 185, 186, 187, 184} 188 .irqs = { 184, 184, 184, 184 }
243 }, { 189 }, {
244 .mapbase = 0xfffe9000, 190 .mapbase = 0xfffe9000,
245 .flags = UPF_BOOT_AUTOCONF, 191 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF, 192 .type = PORT_SCIF,
247 .irqs = { 189, 186, 187, 188} 193 .irqs = { 188, 188, 188, 188 }
248 }, { 194 }, {
249 .mapbase = 0xfffe9800, 195 .mapbase = 0xfffe9800,
250 .flags = UPF_BOOT_AUTOCONF, 196 .flags = UPF_BOOT_AUTOCONF,
251 .type = PORT_SCIF, 197 .type = PORT_SCIF,
252 .irqs = { 193, 194, 195, 192} 198 .irqs = { 192, 192, 192, 192 }
253 }, { 199 }, {
254 .mapbase = 0xfffea000, 200 .mapbase = 0xfffea000,
255 .flags = UPF_BOOT_AUTOCONF, 201 .flags = UPF_BOOT_AUTOCONF,
256 .type = PORT_SCIF, 202 .type = PORT_SCIF,
257 .irqs = { 196, 198, 199, 196} 203 .irqs = { 196, 196, 196, 196 }
258 }, { 204 }, {
259 .mapbase = 0xfffea800, 205 .mapbase = 0xfffea800,
260 .flags = UPF_BOOT_AUTOCONF, 206 .flags = UPF_BOOT_AUTOCONF,
261 .type = PORT_SCIF, 207 .type = PORT_SCIF,
262 .irqs = { 201, 202, 203, 200} 208 .irqs = { 200, 200, 200, 200 }
263 }, { 209 }, {
264 .mapbase = 0xfffeb000, 210 .mapbase = 0xfffeb000,
265 .flags = UPF_BOOT_AUTOCONF, 211 .flags = UPF_BOOT_AUTOCONF,
266 .type = PORT_SCIF, 212 .type = PORT_SCIF,
267 .irqs = { 205, 206, 207, 204} 213 .irqs = { 204, 204, 204, 204 }
268 }, { 214 }, {
269 .mapbase = 0xfffeb800, 215 .mapbase = 0xfffeb800,
270 .flags = UPF_BOOT_AUTOCONF, 216 .flags = UPF_BOOT_AUTOCONF,
271 .type = PORT_SCIF, 217 .type = PORT_SCIF,
272 .irqs = { 209, 210, 211, 208} 218 .irqs = { 208, 208, 208, 208 }
273 }, { 219 }, {
274 .flags = 0, 220 .flags = 0,
275 } 221 }
@@ -290,17 +236,7 @@ static struct resource rtc_resources[] = {
290 .flags = IORESOURCE_IO, 236 .flags = IORESOURCE_IO,
291 }, 237 },
292 [1] = { 238 [1] = {
293 /* Period IRQ */ 239 /* Shared Period/Carry/Alarm IRQ */
294 .start = 153,
295 .flags = IORESOURCE_IRQ,
296 },
297 [2] = {
298 /* Carry IRQ */
299 .start = 154,
300 .flags = IORESOURCE_IRQ,
301 },
302 [3] = {
303 /* Alarm IRQ */
304 .start = 152, 240 .start = 152,
305 .flags = IORESOURCE_IRQ, 241 .flags = IORESOURCE_IRQ,
306 }, 242 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index e98dc4450352..820dfb2e8656 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7203 and SH7263 Setup 2 * SH7203 and SH7263 Setup
3 * 3 *
4 * Copyright (C) 2007 Paul Mundt 4 * Copyright (C) 2007 - 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -18,50 +18,27 @@ enum {
18 /* interrupt sources */ 18 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI, 21 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
22 DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
23 DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
24 DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
25 USB, LCDC, CMT0, CMT1, BSC, WDT, 22 USB, LCDC, CMT0, CMT1, BSC, WDT,
26 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
27 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
28 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
29 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
30 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
31 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
32 ADC_ADI,
33 IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
34 IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
35 IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
36 IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI,
37 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
38 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
39 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
40 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
41 SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,
42 SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,
43 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
44 23
45 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ 24 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
46 ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF, 25 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
47 ROMDEC_IREADY,
48 26
49 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 27 ADC_ADI,
28
29 IIC30, IIC31, IIC32, IIC33,
30 SCIF0, SCIF1, SCIF2, SCIF3,
50 31
51 SDHI3, SDHI0, SDHI1, 32 SSU0, SSU1,
52 33
53 RTC_ARM, RTC_PRD, RTC_CUP, 34 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
54 RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,
55 RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,
56 35
57 SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI, 36 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
37 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
38 SRC, IEBI,
58 39
59 /* interrupt groups */ 40 /* interrupt groups */
60 PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 41 PINT,
61 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
62 MTU3_ABCD, MTU4_ABCD,
63 IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,
64 SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC
65}; 42};
66 43
67static struct intc_vect vectors[] __initdata = { 44static struct intc_vect vectors[] __initdata = {
@@ -73,79 +50,80 @@ static struct intc_vect vectors[] __initdata = {
73 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
74 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
75 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
76 INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109), 53 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
77 INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113), 54 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
78 INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117), 55 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
79 INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121), 56 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
80 INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125), 57 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
81 INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129), 58 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
82 INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133), 59 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
83 INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137), 60 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
84 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141), 61 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
85 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143), 62 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
86 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145), 63 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
87 INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147), 64 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
88 INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149), 65 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
89 INTC_IRQ(MTU2_TCI0V, 150), 66 INTC_IRQ(MTU0_VEF, 150),
90 INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152), 67 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
91 INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154), 68 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
92 INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156), 69 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
93 INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158), 70 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
94 INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160), 71 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
95 INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162), 72 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
96 INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164), 73 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
97 INTC_IRQ(MTU2_TCI3V, 165), 74 INTC_IRQ(MTU2_TCI3V, 165),
98 INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167), 75 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
99 INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169), 76 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
100 INTC_IRQ(MTU2_TCI4V, 170), 77 INTC_IRQ(MTU2_TCI4V, 170),
101 INTC_IRQ(ADC_ADI, 171), 78 INTC_IRQ(ADC_ADI, 171),
102 INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173), 79 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
103 INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175), 80 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
104 INTC_IRQ(IIC30_TEI, 176), 81 INTC_IRQ(IIC30, 176),
105 INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178), 82 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
106 INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180), 83 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
107 INTC_IRQ(IIC31_TEI, 181), 84 INTC_IRQ(IIC31, 181),
108 INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183), 85 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
109 INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185), 86 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
110 INTC_IRQ(IIC32_TEI, 186), 87 INTC_IRQ(IIC32, 186),
111 INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188), 88 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
112 INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190), 89 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
113 INTC_IRQ(IIC33_TEI, 191), 90 INTC_IRQ(IIC33, 191),
114 INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193), 91 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
115 INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195), 92 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
116 INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197), 93 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
117 INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199), 94 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
118 INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201), 95 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
119 INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203), 96 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
120 INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205), 97 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
121 INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207), 98 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
122 INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209), 99 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
123 INTC_IRQ(SSU0_SSTXI, 210), 100 INTC_IRQ(SSU0, 210),
124 INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212), 101 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
125 INTC_IRQ(SSU1_SSTXI, 213), 102 INTC_IRQ(SSU1, 213),
126 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215), 103 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
127 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217), 104 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
128 INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225), 105 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
129 INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227), 106 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
130 INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232), 107 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
131 INTC_IRQ(RTC_CUP, 233), 108 INTC_IRQ(RTC, 233),
132 INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235), 109 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
133 INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237), 110 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
134 INTC_IRQ(RCAN0_SLE, 238), 111 INTC_IRQ(RCAN0, 238),
135 INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240), 112 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
136 INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242), 113 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
137 INTC_IRQ(RCAN1_SLE, 243), 114 INTC_IRQ(RCAN1, 243),
138 115
139 /* SH7263-specific trash */ 116 /* SH7263-specific trash */
140#ifdef CONFIG_CPU_SUBTYPE_SH7263 117#ifdef CONFIG_CPU_SUBTYPE_SH7263
141 INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219), 118 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
142 INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221), 119 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
143 INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223), 120 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
144 121
145 INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230), 122 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
123 INTC_IRQ(SDHI, 230),
146 124
147 INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245), 125 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
148 INTC_IRQ(SRC_IDEI, 246), 126 INTC_IRQ(SRC, 246),
149 127
150 INTC_IRQ(IEBI, 247), 128 INTC_IRQ(IEBI, 247),
151#endif 129#endif
@@ -154,50 +132,6 @@ static struct intc_vect vectors[] __initdata = {
154static struct intc_group groups[] __initdata = { 132static struct intc_group groups[] __initdata = {
155 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 133 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
156 PINT4, PINT5, PINT6, PINT7), 134 PINT4, PINT5, PINT6, PINT7),
157 INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
158 INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
159 INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
160 INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
161 INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
162 INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
163 INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
164 INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
165 INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
166 INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
167 INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
168 INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
169 INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
170 INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
171 INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
172 INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
173 INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
174 IIC30_TEI),
175 INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
176 IIC31_TEI),
177 INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
178 IIC32_TEI),
179 INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI,
180 IIC33_TEI),
181 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
182 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
183 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
184 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
185 INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI),
186 INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI),
187 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I,
188 FLCTL_FLTREQ1I),
189 INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP),
190 INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
191 RCAN0_SLE),
192 INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
193 RCAN1_SLE),
194
195#ifdef CONFIG_CPU_SUBTYPE_SH7263
196 INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG,
197 ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY),
198 INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1),
199 INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI),
200#endif
201}; 135};
202 136
203static struct intc_prio_reg prio_registers[] __initdata = { 137static struct intc_prio_reg prio_registers[] __initdata = {
@@ -242,22 +176,22 @@ static struct plat_sci_port sci_platform_data[] = {
242 .mapbase = 0xfffe8000, 176 .mapbase = 0xfffe8000,
243 .flags = UPF_BOOT_AUTOCONF, 177 .flags = UPF_BOOT_AUTOCONF,
244 .type = PORT_SCIF, 178 .type = PORT_SCIF,
245 .irqs = { 193, 194, 195, 192 }, 179 .irqs = { 192, 192, 192, 192 },
246 }, { 180 }, {
247 .mapbase = 0xfffe8800, 181 .mapbase = 0xfffe8800,
248 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
249 .type = PORT_SCIF, 183 .type = PORT_SCIF,
250 .irqs = { 197, 198, 199, 196 }, 184 .irqs = { 196, 196, 196, 196 },
251 }, { 185 }, {
252 .mapbase = 0xfffe9000, 186 .mapbase = 0xfffe9000,
253 .flags = UPF_BOOT_AUTOCONF, 187 .flags = UPF_BOOT_AUTOCONF,
254 .type = PORT_SCIF, 188 .type = PORT_SCIF,
255 .irqs = { 201, 202, 203, 200 }, 189 .irqs = { 200, 200, 200, 200 },
256 }, { 190 }, {
257 .mapbase = 0xfffe9800, 191 .mapbase = 0xfffe9800,
258 .flags = UPF_BOOT_AUTOCONF, 192 .flags = UPF_BOOT_AUTOCONF,
259 .type = PORT_SCIF, 193 .type = PORT_SCIF,
260 .irqs = { 205, 206, 207, 204 }, 194 .irqs = { 204, 204, 204, 204 },
261 }, { 195 }, {
262 .flags = 0, 196 .flags = 0,
263 } 197 }
@@ -278,17 +212,7 @@ static struct resource rtc_resources[] = {
278 .flags = IORESOURCE_IO, 212 .flags = IORESOURCE_IO,
279 }, 213 },
280 [1] = { 214 [1] = {
281 /* Period IRQ */ 215 /* Shared Period/Carry/Alarm IRQ */
282 .start = 232,
283 .flags = IORESOURCE_IRQ,
284 },
285 [2] = {
286 /* Carry IRQ */
287 .start = 233,
288 .flags = IORESOURCE_IRQ,
289 },
290 [3] = {
291 /* Alarm IRQ */
292 .start = 231, 216 .start = 231,
293 .flags = IORESOURCE_IRQ, 217 .flags = IORESOURCE_IRQ,
294 }, 218 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index e6d4ec445dd8..c46a8355726d 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -2,6 +2,7 @@
2 * SH7206 Setup 2 * SH7206 Setup
3 * 3 *
4 * Copyright (C) 2006 Yoshinori Sato 4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -19,34 +20,23 @@ enum {
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 21 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 ADC_ADI0, ADC_ADI1, 22 ADC_ADI0, ADC_ADI1,
22 DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI, 23
23 DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI, 24 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
24 DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI, 25
25 DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI, 26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
27 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
28 IIC3,
29
26 CMT0, CMT1, BSC, WDT, 30 CMT0, CMT1, BSC, WDT,
27 MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, 31
28 MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, 32 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
29 MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, 33
30 MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
31 MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
32 MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
33 MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
34 POE2_OEI1, POE2_OEI2,
35 MTU2S_TGI3A, MTU2S_TGI3B, MTU2S_TGI3C, MTU2S_TGI3D, MTU2S_TCI3V,
36 MTU2S_TGI4A, MTU2S_TGI4B, MTU2S_TGI4C, MTU2S_TGI4D, MTU2S_TCI4V,
37 MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W,
38 POE2_OEI3, 34 POE2_OEI3,
39 IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI, 35
40 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 36 SCIF0, SCIF1, SCIF2, SCIF3,
41 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
42 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
43 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
44 37
45 /* interrupt groups */ 38 /* interrupt groups */
46 PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 39 PINT,
47 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
48 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
49 IIC3, SCIF0, SCIF1, SCIF2, SCIF3,
50}; 40};
51 41
52static struct intc_vect vectors[] __initdata = { 42static struct intc_vect vectors[] __initdata = {
@@ -59,86 +49,58 @@ static struct intc_vect vectors[] __initdata = {
59 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 49 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
60 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 50 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
61 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96), 51 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
62 INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109), 52 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
63 INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113), 53 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
64 INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117), 54 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
65 INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121), 55 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
66 INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125), 56 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
67 INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129), 57 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
68 INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133), 58 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
69 INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137), 59 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
70 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144), 60 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
71 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152), 61 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
72 INTC_IRQ(MTU2_TGI0A, 156), INTC_IRQ(MTU2_TGI0B, 157), 62 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
73 INTC_IRQ(MTU2_TGI0C, 158), INTC_IRQ(MTU2_TGI0D, 159), 63 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
74 INTC_IRQ(MTU2_TCI0V, 160), 64 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
75 INTC_IRQ(MTU2_TGI0E, 161), INTC_IRQ(MTU2_TGI0F, 162), 65 INTC_IRQ(MTU0_VEF, 162),
76 INTC_IRQ(MTU2_TGI1A, 164), INTC_IRQ(MTU2_TGI1B, 165), 66 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
77 INTC_IRQ(MTU2_TCI1V, 168), INTC_IRQ(MTU2_TCI1U, 169), 67 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
78 INTC_IRQ(MTU2_TGI2A, 172), INTC_IRQ(MTU2_TGI2B, 173), 68 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
79 INTC_IRQ(MTU2_TCI2V, 176), INTC_IRQ(MTU2_TCI2U, 177), 69 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
80 INTC_IRQ(MTU2_TGI3A, 180), INTC_IRQ(MTU2_TGI3B, 181), 70 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
81 INTC_IRQ(MTU2_TGI3C, 182), INTC_IRQ(MTU2_TGI3D, 183), 71 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
82 INTC_IRQ(MTU2_TCI3V, 184), 72 INTC_IRQ(MTU2_TCI3V, 184),
83 INTC_IRQ(MTU2_TGI4A, 188), INTC_IRQ(MTU2_TGI4B, 189), 73 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
84 INTC_IRQ(MTU2_TGI4C, 190), INTC_IRQ(MTU2_TGI4D, 191), 74 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
85 INTC_IRQ(MTU2_TCI4V, 192), 75 INTC_IRQ(MTU2_TCI4V, 192),
86 INTC_IRQ(MTU2_TGI5U, 196), INTC_IRQ(MTU2_TGI5V, 197), 76 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
87 INTC_IRQ(MTU2_TGI5W, 198), 77 INTC_IRQ(MTU5, 198),
88 INTC_IRQ(POE2_OEI1, 200), INTC_IRQ(POE2_OEI2, 201), 78 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
89 INTC_IRQ(MTU2S_TGI3A, 204), INTC_IRQ(MTU2S_TGI3B, 205), 79 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
90 INTC_IRQ(MTU2S_TGI3C, 206), INTC_IRQ(MTU2S_TGI3D, 207), 80 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
91 INTC_IRQ(MTU2S_TCI3V, 208), 81 INTC_IRQ(MTU2S_TCI3V, 208),
92 INTC_IRQ(MTU2S_TGI4A, 212), INTC_IRQ(MTU2S_TGI4B, 213), 82 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
93 INTC_IRQ(MTU2S_TGI4C, 214), INTC_IRQ(MTU2S_TGI4D, 215), 83 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
94 INTC_IRQ(MTU2S_TCI4V, 216), 84 INTC_IRQ(MTU2S_TCI4V, 216),
95 INTC_IRQ(MTU2S_TGI5U, 220), INTC_IRQ(MTU2S_TGI5V, 221), 85 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
96 INTC_IRQ(MTU2S_TGI5W, 222), 86 INTC_IRQ(MTU5S, 222),
97 INTC_IRQ(POE2_OEI3, 224), 87 INTC_IRQ(POE2_OEI3, 224),
98 INTC_IRQ(IIC3_STPI, 228), INTC_IRQ(IIC3_NAKI, 229), 88 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
99 INTC_IRQ(IIC3_RXI, 230), INTC_IRQ(IIC3_TXI, 231), 89 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
100 INTC_IRQ(IIC3_TEI, 232), 90 INTC_IRQ(IIC3, 232),
101 INTC_IRQ(SCIF0_BRI, 240), INTC_IRQ(SCIF0_ERI, 241), 91 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
102 INTC_IRQ(SCIF0_RXI, 242), INTC_IRQ(SCIF0_TXI, 243), 92 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
103 INTC_IRQ(SCIF1_BRI, 244), INTC_IRQ(SCIF1_ERI, 245), 93 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
104 INTC_IRQ(SCIF1_RXI, 246), INTC_IRQ(SCIF1_TXI, 247), 94 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
105 INTC_IRQ(SCIF2_BRI, 248), INTC_IRQ(SCIF2_ERI, 249), 95 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
106 INTC_IRQ(SCIF2_RXI, 250), INTC_IRQ(SCIF2_TXI, 251), 96 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
107 INTC_IRQ(SCIF3_BRI, 252), INTC_IRQ(SCIF3_ERI, 253), 97 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
108 INTC_IRQ(SCIF3_RXI, 254), INTC_IRQ(SCIF3_TXI, 255), 98 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
109}; 99};
110 100
111static struct intc_group groups[] __initdata = { 101static struct intc_group groups[] __initdata = {
112 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 102 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
113 PINT4, PINT5, PINT6, PINT7), 103 PINT4, PINT5, PINT6, PINT7),
114 INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
115 INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
116 INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
117 INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
118 INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
119 INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
120 INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
121 INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
122 INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
123 INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
124 INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
125 INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
126 INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
127 INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
128 INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
129 INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
130 INTC_GROUP(MTU5, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
131 INTC_GROUP(POE2_12, POE2_OEI1, POE2_OEI2),
132 INTC_GROUP(MTU3S_ABCD, MTU2S_TGI3A, MTU2S_TGI3B,
133 MTU2S_TGI3C, MTU2S_TGI3D),
134 INTC_GROUP(MTU4S_ABCD, MTU2S_TGI4A, MTU2S_TGI4B,
135 MTU2S_TGI4C, MTU2S_TGI4D),
136 INTC_GROUP(MTU5S, MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W),
137 INTC_GROUP(IIC3, IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI),
138 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
139 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
140 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
141 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
142}; 104};
143 105
144static struct intc_prio_reg prio_registers[] __initdata = { 106static struct intc_prio_reg prio_registers[] __initdata = {
@@ -174,22 +136,22 @@ static struct plat_sci_port sci_platform_data[] = {
174 .mapbase = 0xfffe8000, 136 .mapbase = 0xfffe8000,
175 .flags = UPF_BOOT_AUTOCONF, 137 .flags = UPF_BOOT_AUTOCONF,
176 .type = PORT_SCIF, 138 .type = PORT_SCIF,
177 .irqs = { 241, 242, 243, 240 }, 139 .irqs = { 240, 240, 240, 240 },
178 }, { 140 }, {
179 .mapbase = 0xfffe8800, 141 .mapbase = 0xfffe8800,
180 .flags = UPF_BOOT_AUTOCONF, 142 .flags = UPF_BOOT_AUTOCONF,
181 .type = PORT_SCIF, 143 .type = PORT_SCIF,
182 .irqs = { 245, 246, 247, 244 }, 144 .irqs = { 244, 244, 244, 244 },
183 }, { 145 }, {
184 .mapbase = 0xfffe9000, 146 .mapbase = 0xfffe9000,
185 .flags = UPF_BOOT_AUTOCONF, 147 .flags = UPF_BOOT_AUTOCONF,
186 .type = PORT_SCIF, 148 .type = PORT_SCIF,
187 .irqs = { 249, 250, 251, 248 }, 149 .irqs = { 248, 248, 248, 248 },
188 }, { 150 }, {
189 .mapbase = 0xfffe9800, 151 .mapbase = 0xfffe9800,
190 .flags = UPF_BOOT_AUTOCONF, 152 .flags = UPF_BOOT_AUTOCONF,
191 .type = PORT_SCIF, 153 .type = PORT_SCIF,
192 .irqs = { 253, 254, 255, 252 }, 154 .irqs = { 252, 252, 252, 252 },
193 }, { 155 }, {
194 .flags = 0, 156 .flags = 0,
195 } 157 }
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index e07c69e16d9b..ecab274141a8 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -4,6 +4,8 @@
4 4
5obj-y := ex.o probe.o entry.o setup-sh3.o 5obj-y := ex.o probe.o entry.o setup-sh3.o
6 6
7obj-$(CONFIG_HIBERNATION) += swsusp.o
8
7# CPU subtype setup 9# CPU subtype setup
8obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index b4106d0c68ec..55da0ff9848d 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -16,6 +16,7 @@
16#include <asm/unistd.h> 16#include <asm/unistd.h>
17#include <cpu/mmu_context.h> 17#include <cpu/mmu_context.h>
18#include <asm/page.h> 18#include <asm/page.h>
19#include <asm/cache.h>
19 20
20! NOTE: 21! NOTE:
21! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address 22! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
@@ -187,44 +188,35 @@ call_dae:
187#if defined(CONFIG_SH_STANDARD_BIOS) 188#if defined(CONFIG_SH_STANDARD_BIOS)
188 /* Unwind the stack and jmp to the debug entry */ 189 /* Unwind the stack and jmp to the debug entry */
189ENTRY(sh_bios_handler) 190ENTRY(sh_bios_handler)
190 mov.l @r15+, r0 191 mov.l 1f, r8
191 mov.l @r15+, r1 192 bsr restore_regs
192 mov.l @r15+, r2 193 nop
193 mov.l @r15+, r3 194
194 mov.l @r15+, r4 195 lds k2, pr ! restore pr
195 mov.l @r15+, r5 196 mov k4, r15
196 mov.l @r15+, r6
197 mov.l @r15+, r7
198 stc sr, r8
199 mov.l 1f, r9 ! BL =1, RB=1, IMASK=0x0F
200 or r9, r8
201 ldc r8, sr ! here, change the register bank
202 mov.l @r15+, r8
203 mov.l @r15+, r9
204 mov.l @r15+, r10
205 mov.l @r15+, r11
206 mov.l @r15+, r12
207 mov.l @r15+, r13
208 mov.l @r15+, r14
209 mov.l @r15+, k0
210 ldc.l @r15+, spc
211 lds.l @r15+, pr
212 mov.l @r15+, k1
213 ldc.l @r15+, gbr
214 lds.l @r15+, mach
215 lds.l @r15+, macl
216 mov k0, r15
217 ! 197 !
218 mov.l 2f, k0 198 mov.l 2f, k0
219 mov.l @k0, k0 199 mov.l @k0, k0
220 jmp @k0 200 jmp @k0
221 ldc k1, ssr 201 ldc k3, ssr
222 .align 2 202 .align 2
2231: .long 0x300000f0 2031: .long 0x300000f0
2242: .long gdb_vbr_vector 2042: .long gdb_vbr_vector
225#endif /* CONFIG_SH_STANDARD_BIOS */ 205#endif /* CONFIG_SH_STANDARD_BIOS */
226 206
227restore_all: 207! restore_regs()
208! - restore r0, r1, r2, r3, r4, r5, r6, r7 from the stack
209! - switch bank
210! - restore r8, r9, r10, r11, r12, r13, r14, r15 from the stack
211! - restore spc, pr*, ssr, gbr, mach, macl, skip default tra
212! k2 returns original pr
213! k3 returns original sr
214! k4 returns original stack pointer
215! r8 passes SR bitmask, overwritten with restored data on return
216! r9 trashed
217! BL=0 on entry, on exit BL=1 (depending on r8).
218
219ENTRY(restore_regs)
228 mov.l @r15+, r0 220 mov.l @r15+, r0
229 mov.l @r15+, r1 221 mov.l @r15+, r1
230 mov.l @r15+, r2 222 mov.l @r15+, r2
@@ -234,10 +226,9 @@ restore_all:
234 mov.l @r15+, r6 226 mov.l @r15+, r6
235 mov.l @r15+, r7 227 mov.l @r15+, r7
236 ! 228 !
237 stc sr, r8 229 stc sr, r9
238 mov.l 7f, r9 230 or r8, r9
239 or r9, r8 ! BL =1, RB=1 231 ldc r9, sr
240 ldc r8, sr ! here, change the register bank
241 ! 232 !
242 mov.l @r15+, r8 233 mov.l @r15+, r8
243 mov.l @r15+, r9 234 mov.l @r15+, r9
@@ -248,12 +239,20 @@ restore_all:
248 mov.l @r15+, r14 239 mov.l @r15+, r14
249 mov.l @r15+, k4 ! original stack pointer 240 mov.l @r15+, k4 ! original stack pointer
250 ldc.l @r15+, spc 241 ldc.l @r15+, spc
251 lds.l @r15+, pr 242 mov.l @r15+, k2 ! original PR
252 mov.l @r15+, k3 ! original SR 243 mov.l @r15+, k3 ! original SR
253 ldc.l @r15+, gbr 244 ldc.l @r15+, gbr
254 lds.l @r15+, mach 245 lds.l @r15+, mach
255 lds.l @r15+, macl 246 lds.l @r15+, macl
256 add #4, r15 ! Skip syscall number 247 rts
248 add #4, r15 ! Skip syscall number
249
250restore_all:
251 mov.l 7f, r8
252 bsr restore_regs
253 nop
254
255 lds k2, pr ! restore pr
257 ! 256 !
258#ifdef CONFIG_SH_DSP 257#ifdef CONFIG_SH_DSP
259 mov.l @r15+, k0 ! DSP mode marker 258 mov.l @r15+, k0 ! DSP mode marker
@@ -294,7 +293,7 @@ skip_restore:
294 mov #0xf0, k1 293 mov #0xf0, k1
295 extu.b k1, k1 294 extu.b k1, k1
296 not k1, k1 295 not k1, k1
297 and k1, k2 ! Mask orignal SR value 296 and k1, k2 ! Mask original SR value
298 ! 297 !
299 mov k3, k0 ! Calculate IMASK-bits 298 mov k3, k0 ! Calculate IMASK-bits
300 shlr2 k0 299 shlr2 k0
@@ -313,7 +312,6 @@ skip_restore:
313 mov #0, k1 312 mov #0, k1
314 mov.b k1, @k0 313 mov.b k1, @k0
315#endif 314#endif
316 mov.l @r15+, k2 ! restore EXPEVT
317 mov k4, r15 315 mov k4, r15
318 rte 316 rte
319 nop 317 nop
@@ -336,81 +334,55 @@ skip_restore:
336ENTRY(vbr_base) 334ENTRY(vbr_base)
337 .long 0 335 .long 0
338! 336!
337! 0x100: General exception vector
338!
339 .balign 256,0,256 339 .balign 256,0,256
340general_exception: 340general_exception:
341 mov.l 1f, k2 341#ifndef CONFIG_CPU_SUBTYPE_SHX3
342 mov.l 2f, k3 342 bra handle_exception
343#ifdef CONFIG_CPU_SUBTYPE_SHX3 343 sts pr, k3 ! save original pr value in k3
344 mov.l @k2, k2 344#else
345 mov.l 1f, k4
346 mov.l @k4, k4
345 347
346 ! Is EXPEVT larger than 0x800? 348 ! Is EXPEVT larger than 0x800?
347 mov #0x8, k0 349 mov #0x8, k0
348 shll8 k0 350 shll8 k0
349 cmp/hs k0, k2 351 cmp/hs k0, k4
350 bf 0f 352 bf 0f
351 353
352 ! then add 0x580 (k2 is 0xd80 or 0xda0) 354 ! then add 0x580 (k2 is 0xd80 or 0xda0)
353 mov #0x58, k0 355 mov #0x58, k0
354 shll2 k0 356 shll2 k0
355 shll2 k0 357 shll2 k0
356 add k0, k2 358 add k0, k4
3570: 3590:
358 bra handle_exception 360 ! Setup stack and save DSP context (k0 contains original r15 on return)
361 bsr prepare_stack_save_dsp
359 nop 362 nop
360#else
361 bra handle_exception
362 mov.l @k2, k2
363#endif
364 .align 2
3651: .long EXPEVT
3662: .long ret_from_exception
367!
368!
369 363
370 .balign 1024,0,1024 364 ! Save registers / Switch to bank 0
371tlb_miss: 365 mov k4, k2 ! keep vector in k2
372 mov.l 1f, k2 366 mov.l 1f, k4 ! SR bits to clear in k4
373 mov.l 4f, k3 367 bsr save_regs ! needs original pr value in k3
374 bra handle_exception 368 nop
375 mov.l @k2, k2 369
376! 370 bra handle_exception_special
377 .balign 512,0,512
378interrupt:
379 mov.l 3f, k3
380#if defined(CONFIG_KGDB)
381 mov.l 2f, k2
382 ! Debounce (filter nested NMI)
383 mov.l @k2, k0
384 mov.l 5f, k1
385 cmp/eq k1, k0
386 bf 0f
387 mov.l 6f, k1
388 tas.b @k1
389 bt 0f
390 rte
391 nop 371 nop
392 .align 2
3932: .long INTEVT
3945: .long NMI_VEC
3956: .long in_nmi
3960:
397#endif /* defined(CONFIG_KGDB) */
398 bra handle_exception
399 mov #-1, k2 ! interrupt exception marker
400 372
401 .align 2 373 .align 2
4021: .long EXPEVT 3741: .long EXPEVT
4033: .long ret_from_irq 375#endif
4044: .long ret_from_exception
405 376
406! 377! prepare_stack_save_dsp()
407! 378! - roll back gRB
408 .align 2 379! - switch to kernel stack
409ENTRY(handle_exception) 380! - save DSP
410 ! Using k0, k1 for scratch registers (r0_bank1, r1_bank), 381! k0 returns original sp (after roll back)
411 ! save all registers onto stack. 382! k1 trashed
412 ! 383! k2 trashed
413 384
385prepare_stack_save_dsp:
414#ifdef CONFIG_GUSA 386#ifdef CONFIG_GUSA
415 ! Check for roll back gRB (User and Kernel) 387 ! Check for roll back gRB (User and Kernel)
416 mov r15, k0 388 mov r15, k0
@@ -430,7 +402,7 @@ ENTRY(handle_exception)
4302: mov k1, r15 ! SP = r1 4022: mov k1, r15 ! SP = r1
4311: 4031:
432#endif 404#endif
433 405 ! Switch to kernel stack if needed
434 stc ssr, k0 ! Is it from kernel space? 406 stc ssr, k0 ! Is it from kernel space?
435 shll k0 ! Check MD bit (bit30) by shifting it into... 407 shll k0 ! Check MD bit (bit30) by shifting it into...
436 shll k0 ! ...the T bit 408 shll k0 ! ...the T bit
@@ -443,18 +415,17 @@ ENTRY(handle_exception)
443 add current, k1 415 add current, k1
444 mov k1, r15 ! change to kernel stack 416 mov k1, r15 ! change to kernel stack
445 ! 417 !
4461: mov.l 2f, k1 4181:
447 !
448#ifdef CONFIG_SH_DSP 419#ifdef CONFIG_SH_DSP
449 mov.l r2, @-r15 ! Save r2, we need another reg 420 ! Save DSP context if needed
450 stc sr, k4 421 stc sr, k1
451 mov.l 1f, r2 422 mov #0x10, k2
452 tst r2, k4 ! Check if in DSP mode 423 shll8 k2 ! DSP=1 (0x00001000)
453 mov.l @r15+, r2 ! Restore r2 now 424 tst k2, k1 ! Check if in DSP mode (passed in k2)
454 bt/s skip_save 425 bt/s skip_save
455 mov #0, k4 ! Set marker for no stack frame 426 mov #0, k1 ! Set marker for no stack frame
456 427
457 mov r2, k4 ! Backup r2 (in k4) for later 428 mov k2, k1 ! Save has-frame marker
458 429
459 ! Save DSP registers on stack 430 ! Save DSP registers on stack
460 stc.l mod, @-r15 431 stc.l mod, @-r15
@@ -473,35 +444,74 @@ ENTRY(handle_exception)
473 ! as we're not at all interested in supporting ancient toolchains at 444 ! as we're not at all interested in supporting ancient toolchains at
474 ! this point. -- PFM. 445 ! this point. -- PFM.
475 446
476 mov r15, r2 447 mov r15, k2
477 .word 0xf653 ! movs.l a1, @-r2 448 .word 0xf653 ! movs.l a1, @-r2
478 .word 0xf6f3 ! movs.l a0g, @-r2 449 .word 0xf6f3 ! movs.l a0g, @-r2
479 .word 0xf6d3 ! movs.l a1g, @-r2 450 .word 0xf6d3 ! movs.l a1g, @-r2
480 .word 0xf6c3 ! movs.l m0, @-r2 451 .word 0xf6c3 ! movs.l m0, @-r2
481 .word 0xf6e3 ! movs.l m1, @-r2 452 .word 0xf6e3 ! movs.l m1, @-r2
482 mov r2, r15 453 mov k2, r15
483 454
484 mov k4, r2 ! Restore r2
485 mov.l 1f, k4 ! Force DSP stack frame
486skip_save: 455skip_save:
487 mov.l k4, @-r15 ! Push DSP mode marker onto stack 456 mov.l k1, @-r15 ! Push DSP mode marker onto stack
488#endif 457#endif
489 ! Save the user registers on the stack. 458 rts
490 mov.l k2, @-r15 ! EXPEVT 459 nop
491 460!
492 mov #-1, k4 461! 0x400: Instruction and Data TLB miss exception vector
493 mov.l k4, @-r15 ! set TRA (default: -1) 462!
494 ! 463 .balign 1024,0,1024
464tlb_miss:
465 sts pr, k3 ! save original pr value in k3
466
467handle_exception:
468 mova exception_data, k0
469
470 ! Setup stack and save DSP context (k0 contains original r15 on return)
471 bsr prepare_stack_save_dsp
472 PREF(k0)
473
474 ! Save registers / Switch to bank 0
475 mov.l 5f, k2 ! vector register address
476 mov.l 1f, k4 ! SR bits to clear in k4
477 bsr save_regs ! needs original pr value in k3
478 mov.l @k2, k2 ! read out vector and keep in k2
479
480handle_exception_special:
481 ! Setup return address and jump to exception handler
482 mov.l 7f, r9 ! fetch return address
483 stc r2_bank, r0 ! k2 (vector)
484 mov.l 6f, r10
485 shlr2 r0
486 shlr r0
487 mov.l @(r0, r10), r10
488 jmp @r10
489 lds r9, pr ! put return address in pr
490
491 .align L1_CACHE_SHIFT
492
493! save_regs()
494! - save default tra, macl, mach, gbr, ssr, pr* and spc on the stack
495! - save r15*, r14, r13, r12, r11, r10, r9, r8 on the stack
496! - switch bank
497! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
498! k0 contains original stack pointer*
499! k1 trashed
500! k3 passes original pr*
501! k4 passes SR bitmask
502! BL=1 on entry, on exit BL=0.
503
504ENTRY(save_regs)
505 mov #-1, r1
506 mov.l k1, @-r15 ! set TRA (default: -1)
495 sts.l macl, @-r15 507 sts.l macl, @-r15
496 sts.l mach, @-r15 508 sts.l mach, @-r15
497 stc.l gbr, @-r15 509 stc.l gbr, @-r15
498 stc.l ssr, @-r15 510 stc.l ssr, @-r15
499 sts.l pr, @-r15 511 mov.l k3, @-r15 ! original pr in k3
500 stc.l spc, @-r15 512 stc.l spc, @-r15
501 ! 513
502 lds k3, pr ! Set the return address to pr 514 mov.l k0, @-r15 ! original stack pointer in k0
503 !
504 mov.l k0, @-r15 ! save orignal stack
505 mov.l r14, @-r15 515 mov.l r14, @-r15
506 mov.l r13, @-r15 516 mov.l r13, @-r15
507 mov.l r12, @-r15 517 mov.l r12, @-r15
@@ -509,13 +519,23 @@ skip_save:
509 mov.l r10, @-r15 519 mov.l r10, @-r15
510 mov.l r9, @-r15 520 mov.l r9, @-r15
511 mov.l r8, @-r15 521 mov.l r8, @-r15
512 ! 522
513 stc sr, r8 ! Back to normal register bank, and 523 mov.l 0f, k3 ! SR bits to set in k3
514 or k1, r8 ! Block all interrupts 524
515 mov.l 3f, k1 525 ! fall-through
516 and k1, r8 ! ... 526
517 ldc r8, sr ! ...changed here. 527! save_low_regs()
518 ! 528! - modify SR for bank switch
529! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
530! k3 passes bits to set in SR
531! k4 passes bits to clear in SR
532
533ENTRY(save_low_regs)
534 stc sr, r8
535 or k3, r8
536 and k4, r8
537 ldc r8, sr
538
519 mov.l r7, @-r15 539 mov.l r7, @-r15
520 mov.l r6, @-r15 540 mov.l r6, @-r15
521 mov.l r5, @-r15 541 mov.l r5, @-r15
@@ -523,52 +543,63 @@ skip_save:
523 mov.l r3, @-r15 543 mov.l r3, @-r15
524 mov.l r2, @-r15 544 mov.l r2, @-r15
525 mov.l r1, @-r15 545 mov.l r1, @-r15
526 mov.l r0, @-r15
527
528 /*
529 * This gets a bit tricky.. in the INTEVT case we don't want to use
530 * the VBR offset as a destination in the jump call table, since all
531 * of the destinations are the same. In this case, (interrupt) sets
532 * a marker in r2 (now r2_bank since SR.RB changed), which we check
533 * to determine the exception type. For all other exceptions, we
534 * forcibly read EXPEVT from memory and fix up the jump address, in
535 * the interrupt exception case we jump to do_IRQ() and defer the
536 * INTEVT read until there. As a bonus, we can also clean up the SR.RB
537 * checks that do_IRQ() was doing..
538 */
539 stc r2_bank, r8
540 cmp/pz r8
541 bf interrupt_exception
542 shlr2 r8
543 shlr r8
544 mov.l 4f, r9
545 add r8, r9
546 mov.l @r9, r9
547 jmp @r9
548 nop
549 rts 546 rts
550 nop 547 mov.l r0, @-r15
551 548
549!
550! 0x600: Interrupt / NMI vector
551!
552 .balign 512,0,512
553ENTRY(handle_interrupt)
554#if defined(CONFIG_KGDB)
555 mov.l 2f, k2
556 ! Debounce (filter nested NMI)
557 mov.l @k2, k0
558 mov.l 9f, k1
559 cmp/eq k1, k0
560 bf 11f
561 mov.l 10f, k1
562 tas.b @k1
563 bt 11f
564 rte
565 nop
552 .align 2 566 .align 2
5531: .long 0x00001000 ! DSP=1 5679: .long NMI_VEC
5542: .long 0x000080f0 ! FD=1, IMASK=15 56810: .long in_nmi
5553: .long 0xcfffffff ! RB=0, BL=0 56911:
5564: .long exception_handling_table 570#endif /* defined(CONFIG_KGDB) */
571 sts pr, k3 ! save original pr value in k3
572 mova exception_data, k0
557 573
558interrupt_exception: 574 ! Setup stack and save DSP context (k0 contains original r15 on return)
559 mov.l 1f, r9 575 bsr prepare_stack_save_dsp
576 PREF(k0)
577
578 ! Save registers / Switch to bank 0
579 mov.l 1f, k4 ! SR bits to clear in k4
580 bsr save_regs ! needs original pr value in k3
581 mov #-1, k2 ! default vector kept in k2
582
583 ! Setup return address and jump to do_IRQ
584 mov.l 4f, r9 ! fetch return address
585 lds r9, pr ! put return address in pr
560 mov.l 2f, r4 586 mov.l 2f, r4
561 mov.l @r4, r4 587 mov.l 3f, r9
588 mov.l @r4, r4 ! pass INTEVT vector as arg0
562 jmp @r9 589 jmp @r9
563 mov r15, r5 590 mov r15, r5 ! pass saved registers as arg1
564 rts
565 nop
566
567 .align 2
5681: .long do_IRQ
5692: .long INTEVT
570 591
571 .align 2
572ENTRY(exception_none) 592ENTRY(exception_none)
573 rts 593 rts
574 nop 594 nop
595
596 .align L1_CACHE_SHIFT
597exception_data:
5980: .long 0x000080f0 ! FD=1, IMASK=15
5991: .long 0xcfffffff ! RB=0, BL=0
6002: .long INTEVT
6013: .long do_IRQ
6024: .long ret_from_irq
6035: .long EXPEVT
6046: .long exception_handling_table
6057: .long ret_from_exception
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 6468ae86b944..63b67badd67e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7705 Setup 2 * SH7705 Setup
3 * 3 *
4 * Copyright (C) 2006, 2007 Paul Mundt 4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -21,51 +21,36 @@ enum {
21 /* interrupt sources */ 21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 PINT07, PINT815, 23 PINT07, PINT815,
24 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 24
25 SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 25 DMAC, SCIF0, SCIF2, ADC_ADI, USB,
26 SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, 26
27 ADC_ADI,
28 USB_USI0, USB_USI1,
29 TPU0, TPU1, TPU2, TPU3, 27 TPU0, TPU1, TPU2, TPU3,
30 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 28 TMU0, TMU1, TMU2,
31 RTC_ATI, RTC_PRI, RTC_CUI,
32 WDT,
33 REF_RCMI,
34 29
35 /* interrupt groups */ 30 RTC, WDT, REF_RCMI,
36 RTC, TMU2, DMAC, USB, SCIF2, SCIF0,
37}; 31};
38 32
39static struct intc_vect vectors[] __initdata = { 33static struct intc_vect vectors[] __initdata = {
40 /* IRQ0->5 are handled in setup-sh3.c */ 34 /* IRQ0->5 are handled in setup-sh3.c */
41 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 35 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 36 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 37 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 38 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
45 INTC_VECT(SCIF0_TXI, 0x8e0), 39 INTC_VECT(SCIF0, 0x8e0),
46 INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920), 40 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
47 INTC_VECT(SCIF2_TXI, 0x960), 41 INTC_VECT(SCIF2, 0x960),
48 INTC_VECT(ADC_ADI, 0x980), 42 INTC_VECT(ADC_ADI, 0x980),
49 INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40), 43 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
50 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20), 44 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
51 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0), 45 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),
52 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 46 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
53 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 47 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
54 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 48 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
55 INTC_VECT(RTC_CUI, 0x4c0), 49 INTC_VECT(RTC, 0x4c0),
56 INTC_VECT(WDT, 0x560), 50 INTC_VECT(WDT, 0x560),
57 INTC_VECT(REF_RCMI, 0x580), 51 INTC_VECT(REF_RCMI, 0x580),
58}; 52};
59 53
60static struct intc_group groups[] __initdata = {
61 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
62 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
63 INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
64 INTC_GROUP(USB, USB_USI0, USB_USI1),
65 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
66 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
67};
68
69static struct intc_prio_reg prio_registers[] __initdata = { 54static struct intc_prio_reg prio_registers[] __initdata = {
70 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 55 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
71 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } }, 56 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
@@ -78,7 +63,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
78 63
79}; 64};
80 65
81static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups, 66static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
82 NULL, prio_registers, NULL); 67 NULL, prio_registers, NULL);
83 68
84static struct plat_sci_port sci_platform_data[] = { 69static struct plat_sci_port sci_platform_data[] = {
@@ -86,12 +71,12 @@ static struct plat_sci_port sci_platform_data[] = {
86 .mapbase = 0xa4410000, 71 .mapbase = 0xa4410000,
87 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
88 .type = PORT_SCIF, 73 .type = PORT_SCIF,
89 .irqs = { 56, 57, 59 }, 74 .irqs = { 56, 56, 56 },
90 }, { 75 }, {
91 .mapbase = 0xa4400000, 76 .mapbase = 0xa4400000,
92 .flags = UPF_BOOT_AUTOCONF, 77 .flags = UPF_BOOT_AUTOCONF,
93 .type = PORT_SCIF, 78 .type = PORT_SCIF,
94 .irqs = { 52, 53, 55 }, 79 .irqs = { 52, 52, 52 },
95 }, { 80 }, {
96 .flags = 0, 81 .flags = 0,
97 } 82 }
@@ -115,14 +100,6 @@ static struct resource rtc_resources[] = {
115 .start = 20, 100 .start = 20,
116 .flags = IORESOURCE_IRQ, 101 .flags = IORESOURCE_IRQ,
117 }, 102 },
118 [2] = {
119 .start = 21,
120 .flags = IORESOURCE_IRQ,
121 },
122 [3] = {
123 .start = 22,
124 .flags = IORESOURCE_IRQ,
125 },
126}; 103};
127 104
128static struct sh_rtc_platform_info rtc_info = { 105static struct sh_rtc_platform_info rtc_info = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 93c55e2ed952..a74f960b5e79 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -2,6 +2,7 @@
2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
3 * 3 *
4 * Copyright (C) 2007 Magnus Damm 4 * Copyright (C) 2007 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * Based on setup-sh7709.c 7 * Based on setup-sh7709.c
7 * 8 *
@@ -24,46 +25,37 @@ enum {
24 /* interrupt sources */ 25 /* interrupt sources */
25 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 26 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
26 PINT07, PINT815, 27 PINT07, PINT815,
27 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 28 DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
28 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
29 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
30 SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
31 ADC_ADI,
32 LCDC, PCC0, PCC1, 29 LCDC, PCC0, PCC1,
33 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 30 TMU0, TMU1, TMU2,
34 RTC_ATI, RTC_PRI, RTC_CUI, 31 RTC, WDT, REF,
35 WDT,
36 REF_RCMI, REF_ROVI,
37
38 /* interrupt groups */
39 RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
40}; 32};
41 33
42static struct intc_vect vectors[] __initdata = { 34static struct intc_vect vectors[] __initdata = {
43 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 35 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
44 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 36 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
45 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 37 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
46 INTC_VECT(RTC_CUI, 0x4c0), 38 INTC_VECT(RTC, 0x4c0),
47 INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500), 39 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
48 INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540), 40 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
49 INTC_VECT(WDT, 0x560), 41 INTC_VECT(WDT, 0x560),
50 INTC_VECT(REF_RCMI, 0x580), 42 INTC_VECT(REF, 0x580),
51 INTC_VECT(REF_ROVI, 0x5a0), 43 INTC_VECT(REF, 0x5a0),
52#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 44#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
53 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 45 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
54 defined(CONFIG_CPU_SUBTYPE_SH7709) 46 defined(CONFIG_CPU_SUBTYPE_SH7709)
55 /* IRQ0->5 are handled in setup-sh3.c */ 47 /* IRQ0->5 are handled in setup-sh3.c */
56 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 48 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
57 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 49 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
58 INTC_VECT(ADC_ADI, 0x980), 50 INTC_VECT(ADC_ADI, 0x980),
59 INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920), 51 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
60 INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960), 52 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
61#endif 53#endif
62#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 54#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
63 defined(CONFIG_CPU_SUBTYPE_SH7709) 55 defined(CONFIG_CPU_SUBTYPE_SH7709)
64 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 56 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
65 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 57 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
66 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 58 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
67#endif 59#endif
68#if defined(CONFIG_CPU_SUBTYPE_SH7707) 60#if defined(CONFIG_CPU_SUBTYPE_SH7707)
69 INTC_VECT(LCDC, 0x9a0), 61 INTC_VECT(LCDC, 0x9a0),
@@ -71,16 +63,6 @@ static struct intc_vect vectors[] __initdata = {
71#endif 63#endif
72}; 64};
73 65
74static struct intc_group groups[] __initdata = {
75 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
76 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
77 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
78 INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
79 INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
80 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
81 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
82};
83
84static struct intc_prio_reg prio_registers[] __initdata = { 66static struct intc_prio_reg prio_registers[] __initdata = {
85 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 67 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
86 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, 68 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
@@ -101,7 +83,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
101#endif 83#endif
102}; 84};
103 85
104static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups, 86static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
105 NULL, prio_registers, NULL); 87 NULL, prio_registers, NULL);
106 88
107static struct resource rtc_resources[] = { 89static struct resource rtc_resources[] = {
@@ -111,14 +93,6 @@ static struct resource rtc_resources[] = {
111 .flags = IORESOURCE_IO, 93 .flags = IORESOURCE_IO,
112 }, 94 },
113 [1] = { 95 [1] = {
114 .start = 21,
115 .flags = IORESOURCE_IRQ,
116 },
117 [2] = {
118 .start = 22,
119 .flags = IORESOURCE_IRQ,
120 },
121 [3] = {
122 .start = 20, 96 .start = 20,
123 .flags = IORESOURCE_IRQ, 97 .flags = IORESOURCE_IRQ,
124 }, 98 },
@@ -136,7 +110,7 @@ static struct plat_sci_port sci_platform_data[] = {
136 .mapbase = 0xfffffe80, 110 .mapbase = 0xfffffe80,
137 .flags = UPF_BOOT_AUTOCONF, 111 .flags = UPF_BOOT_AUTOCONF,
138 .type = PORT_SCI, 112 .type = PORT_SCI,
139 .irqs = { 23, 24, 25, 0 }, 113 .irqs = { 23, 23, 23, 0 },
140 }, 114 },
141#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 115#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
142 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 116 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
@@ -145,7 +119,7 @@ static struct plat_sci_port sci_platform_data[] = {
145 .mapbase = 0xa4000150, 119 .mapbase = 0xa4000150,
146 .flags = UPF_BOOT_AUTOCONF, 120 .flags = UPF_BOOT_AUTOCONF,
147 .type = PORT_SCIF, 121 .type = PORT_SCIF,
148 .irqs = { 56, 57, 59, 58 }, 122 .irqs = { 56, 56, 56, 56 },
149 }, 123 },
150#endif 124#endif
151#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 125#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
@@ -154,7 +128,7 @@ static struct plat_sci_port sci_platform_data[] = {
154 .mapbase = 0xa4000140, 128 .mapbase = 0xa4000140,
155 .flags = UPF_BOOT_AUTOCONF, 129 .flags = UPF_BOOT_AUTOCONF,
156 .type = PORT_IRDA, 130 .type = PORT_IRDA,
157 .irqs = { 52, 53, 55, 54 }, 131 .irqs = { 52, 52, 52, 52 },
158 }, 132 },
159#endif 133#endif
160 { 134 {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 77eee481de47..335098b66e2f 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH3 Setup code for SH7710, SH7712 2 * SH3 Setup code for SH7710, SH7712
3 * 3 *
4 * Copyright (C) 2006, 2007 Paul Mundt 4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -20,59 +20,40 @@ enum {
20 20
21 /* interrupt sources */ 21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 23 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC,
24 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
25 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
26 DMAC_DEI4, DMAC_DEI5,
27 IPSEC,
28 EDMAC0, EDMAC1, EDMAC2, 24 EDMAC0, EDMAC1, EDMAC2,
29 SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI, 25 SIOF0, SIOF1,
30 SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
31 TMU0, TMU1, TMU2,
32 RTC_ATI, RTC_PRI, RTC_CUI,
33 WDT,
34 REF,
35 26
36 /* interrupt groups */ 27 TMU0, TMU1, TMU2,
37 RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1, 28 RTC, WDT, REF,
38}; 29};
39 30
40static struct intc_vect vectors[] __initdata = { 31static struct intc_vect vectors[] __initdata = {
41 /* IRQ0->5 are handled in setup-sh3.c */ 32 /* IRQ0->5 are handled in setup-sh3.c */
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
45 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), 36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
46 INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920), 37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
47 INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960), 38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
48 INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0), 39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
49#ifdef CONFIG_CPU_SUBTYPE_SH7710 40#ifdef CONFIG_CPU_SUBTYPE_SH7710
50 INTC_VECT(IPSEC, 0xbe0), 41 INTC_VECT(IPSEC, 0xbe0),
51#endif 42#endif
52 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), 43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
53 INTC_VECT(EDMAC2, 0xc40), 44 INTC_VECT(EDMAC2, 0xc40),
54 INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20), 45 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20),
55 INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60), 46 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60),
56 INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0), 47 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0),
57 INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0), 48 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0),
58 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 49 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
59 INTC_VECT(TMU2, 0x440), 50 INTC_VECT(TMU2, 0x440),
60 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 51 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
61 INTC_VECT(RTC_CUI, 0x4c0), 52 INTC_VECT(RTC, 0x4c0),
62 INTC_VECT(WDT, 0x560), 53 INTC_VECT(WDT, 0x560),
63 INTC_VECT(REF, 0x580), 54 INTC_VECT(REF, 0x580),
64}; 55};
65 56
66static struct intc_group groups[] __initdata = {
67 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
68 INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
69 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
70 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
71 INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
72 INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
73 INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
74};
75
76static struct intc_prio_reg prio_registers[] __initdata = { 57static struct intc_prio_reg prio_registers[] __initdata = {
77 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 58 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
78 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, 59 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
@@ -85,7 +66,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
85 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, 66 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
86}; 67};
87 68
88static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, 69static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL,
89 NULL, prio_registers, NULL); 70 NULL, prio_registers, NULL);
90 71
91static struct resource rtc_resources[] = { 72static struct resource rtc_resources[] = {
@@ -98,14 +79,6 @@ static struct resource rtc_resources[] = {
98 .start = 20, 79 .start = 20,
99 .flags = IORESOURCE_IRQ, 80 .flags = IORESOURCE_IRQ,
100 }, 81 },
101 [2] = {
102 .start = 21,
103 .flags = IORESOURCE_IRQ,
104 },
105 [3] = {
106 .start = 22,
107 .flags = IORESOURCE_IRQ,
108 },
109}; 82};
110 83
111static struct sh_rtc_platform_info rtc_info = { 84static struct sh_rtc_platform_info rtc_info = {
@@ -127,12 +100,12 @@ static struct plat_sci_port sci_platform_data[] = {
127 .mapbase = 0xa4400000, 100 .mapbase = 0xa4400000,
128 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
129 .type = PORT_SCIF, 102 .type = PORT_SCIF,
130 .irqs = { 52, 53, 55, 54 }, 103 .irqs = { 52, 52, 52, 52 },
131 }, { 104 }, {
132 .mapbase = 0xa4410000, 105 .mapbase = 0xa4410000,
133 .flags = UPF_BOOT_AUTOCONF, 106 .flags = UPF_BOOT_AUTOCONF,
134 .type = PORT_SCIF, 107 .type = PORT_SCIF,
135 .irqs = { 56, 57, 59, 58 }, 108 .irqs = { 56, 56, 56, 56 },
136 }, { 109 }, {
137 110
138 .flags = 0, 111 .flags = 0,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index f807a21b066c..003874a2fd2a 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -2,6 +2,7 @@
2 * SH7720 Setup 2 * SH7720 Setup
3 * 3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas 4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c: 7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
7 * 8 *
@@ -26,17 +27,7 @@ static struct resource rtc_resources[] = {
26 .flags = IORESOURCE_IO, 27 .flags = IORESOURCE_IO,
27 }, 28 },
28 [1] = { 29 [1] = {
29 /* Period IRQ */ 30 /* Shared Period/Carry/Alarm IRQ */
30 .start = 21,
31 .flags = IORESOURCE_IRQ,
32 },
33 [2] = {
34 /* Carry IRQ */
35 .start = 22,
36 .flags = IORESOURCE_IRQ,
37 },
38 [3] = {
39 /* Alarm IRQ */
40 .start = 20, 31 .start = 20,
41 .flags = IORESOURCE_IRQ, 32 .flags = IORESOURCE_IRQ,
42 }, 33 },
@@ -150,62 +141,49 @@ enum {
150 UNUSED = 0, 141 UNUSED = 0,
151 142
152 /* interrupt sources */ 143 /* interrupt sources */
153 TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI, 144 TMU0, TMU1, TMU2, RTC,
154 WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND, 145 WDT, REF_RCMI, SIM,
155 IRQ0, IRQ1, IRQ2, IRQ3, 146 IRQ0, IRQ1, IRQ2, IRQ3,
156 USBF_SPD, TMU_SUNI, IRQ5, IRQ4, 147 USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
157 DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL, 148 DMAC1, LCDC, SSL,
158 ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT, 149 ADC, DMAC2, USBFI, CMT,
159 SCIF0, SCIF1, 150 SCIF0, SCIF1,
160 PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC, 151 PINT07, PINT815, TPU, IIC,
161 SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC, 152 SIOF0, SIOF1, MMC, PCC,
162 USBHI, AFEIF, 153 USBHI, AFEIF,
163 H_UDI, 154 H_UDI,
164 /* interrupt groups */
165 TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC,
166}; 155};
167 156
168static struct intc_vect vectors[] __initdata = { 157static struct intc_vect vectors[] __initdata = {
169 /* IRQ0->5 are handled in setup-sh3.c */ 158 /* IRQ0->5 are handled in setup-sh3.c */
170 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 159 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
171 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480), 160 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
172 INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0), 161 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
173 INTC_VECT(SIM_ERI, 0x4e0), INTC_VECT(SIM_RXI, 0x500), 162 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
174 INTC_VECT(SIM_TXI, 0x520), INTC_VECT(SIM_TEND, 0x540), 163 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
175 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580), 164 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
176 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0), 165 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
177 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), 166 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
178 INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), 167 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
179 INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), 168 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
180#if defined(CONFIG_CPU_SUBTYPE_SH7720) 169#if defined(CONFIG_CPU_SUBTYPE_SH7720)
181 INTC_VECT(SSL, 0x980), 170 INTC_VECT(SSL, 0x980),
182#endif 171#endif
183 INTC_VECT(USBFI0, 0xa20), INTC_VECT(USBFI1, 0xa40), 172 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
184 INTC_VECT(USBHI, 0xa60), 173 INTC_VECT(USBHI, 0xa60),
185 INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), 174 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
186 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 175 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
187 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 176 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
188 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00), 177 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
189 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU0, 0xd80), 178 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
190 INTC_VECT(TPU1, 0xda0), INTC_VECT(TPU2, 0xdc0), 179 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
191 INTC_VECT(TPU3, 0xde0), INTC_VECT(IIC, 0xe00), 180 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
192 INTC_VECT(MMCI0, 0xe80), INTC_VECT(MMCI1, 0xea0), 181 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
193 INTC_VECT(MMCI2, 0xec0), INTC_VECT(MMCI3, 0xee0), 182 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
194 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60), 183 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
195 INTC_VECT(AFEIF, 0xfe0), 184 INTC_VECT(AFEIF, 0xfe0),
196}; 185};
197 186
198static struct intc_group groups[] __initdata = {
199 INTC_GROUP(TMU, TMU0, TMU1, TMU2),
200 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
201 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
202 INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3),
203 INTC_GROUP(USBFI, USBFI0, USBFI1),
204 INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5),
205 INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3),
206 INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3),
207};
208
209static struct intc_prio_reg prio_registers[] __initdata = { 187static struct intc_prio_reg prio_registers[] __initdata = {
210 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 188 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
211 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 189 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
@@ -219,7 +197,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
219 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } }, 197 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
220}; 198};
221 199
222static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups, 200static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
223 NULL, prio_registers, NULL); 201 NULL, prio_registers, NULL);
224 202
225void __init plat_irq_setup(void) 203void __init plat_irq_setup(void)
diff --git a/arch/sh/kernel/cpu/sh3/swsusp.S b/arch/sh/kernel/cpu/sh3/swsusp.S
new file mode 100644
index 000000000000..01145426a2b8
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/swsusp.S
@@ -0,0 +1,147 @@
1/*
2 * arch/sh/kernel/cpu/sh3/swsusp.S
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/sys.h>
11#include <linux/errno.h>
12#include <linux/linkage.h>
13#include <asm/asm-offsets.h>
14#include <asm/page.h>
15
16#define k0 r0
17#define k1 r1
18#define k2 r2
19#define k3 r3
20#define k4 r4
21
22! swsusp_arch_resume()
23! - copy restore_pblist pages
24! - restore registers from swsusp_arch_regs_cpu0
25
26ENTRY(swsusp_arch_resume)
27 mov.l 1f, r15
28 mov.l 2f, r4
29 mov.l @r4, r4
30
31swsusp_copy_loop:
32 mov r4, r0
33 cmp/eq #0, r0
34 bt swsusp_restore_regs
35
36 mov.l @(PBE_ADDRESS, r4), r2
37 mov.l @(PBE_ORIG_ADDRESS, r4), r5
38
39 mov #(PAGE_SIZE >> 10), r3
40 shll8 r3
41 shlr2 r3 /* PAGE_SIZE / 16 */
42swsusp_copy_page:
43 dt r3
44 mov.l @r2+,r1 /* 16n+0 */
45 mov.l r1,@r5
46 add #4,r5
47 mov.l @r2+,r1 /* 16n+4 */
48 mov.l r1,@r5
49 add #4,r5
50 mov.l @r2+,r1 /* 16n+8 */
51 mov.l r1,@r5
52 add #4,r5
53 mov.l @r2+,r1 /* 16n+12 */
54 mov.l r1,@r5
55 bf/s swsusp_copy_page
56 add #4,r5
57
58 bra swsusp_copy_loop
59 mov.l @(PBE_NEXT, r4), r4
60
61swsusp_restore_regs:
62 ! BL=0: R7->R0 is bank0
63 mov.l 3f, r8
64 mov.l 4f, r5
65 jsr @r5
66 nop
67
68 ! BL=1: R7->R0 is bank1
69 lds k2, pr
70 ldc k3, ssr
71
72 mov.l @r15+, r0
73 mov.l @r15+, r1
74 mov.l @r15+, r2
75 mov.l @r15+, r3
76 mov.l @r15+, r4
77 mov.l @r15+, r5
78 mov.l @r15+, r6
79 mov.l @r15+, r7
80
81 rte
82 nop
83 ! BL=0: R7->R0 is bank0
84
85 .align 2
861: .long swsusp_arch_regs_cpu0
872: .long restore_pblist
883: .long 0x20000000 ! RB=1
894: .long restore_regs
90
91! swsusp_arch_suspend()
92! - prepare pc for resume, return from function without swsusp_save on resume
93! - save registers in swsusp_arch_regs_cpu0
94! - call swsusp_save write suspend image
95
96ENTRY(swsusp_arch_suspend)
97 sts pr, r0 ! save pr in r0
98 mov r15, r2 ! save sp in r2
99 mov r8, r5 ! save r8 in r5
100 stc sr, r1
101 ldc r1, ssr ! save sr in ssr
102 mov.l 1f, r1
103 ldc r1, spc ! setup pc value for resuming
104 mov.l 5f, r15 ! use swsusp_arch_regs_cpu0 as stack
105 mov.l 6f, r3
106 add r3, r15 ! save from top of structure
107
108 ! BL=0: R7->R0 is bank0
109 mov.l 2f, r3 ! get new SR value for bank1
110 mov #0, r4
111 mov.l 7f, r1
112 jsr @r1 ! switch to bank1 and save bank1 r7->r0
113 not r4, r4
114
115 ! BL=1: R7->R0 is bank1
116 stc r2_bank, k0 ! fetch old sp from r2_bank0
117 mov.l 3f, k4 ! SR bits to clear in k4
118 mov.l 8f, k1
119 jsr @k1 ! switch to bank0 and save all regs
120 stc r0_bank, k3 ! fetch old pr from r0_bank0
121
122 ! BL=0: R7->R0 is bank0
123 mov r2, r15 ! restore old sp
124 mov r5, r8 ! restore old r8
125 stc ssr, r1
126 ldc r1, sr ! restore old sr
127 lds r0, pr ! restore old pr
128 mov.l 4f, r0
129 jmp @r0
130 nop
131
132swsusp_call_save:
133 mov r2, r15 ! restore old sp
134 mov r5, r8 ! restore old r8
135 lds r0, pr ! restore old pr
136 rts
137 mov #0, r0
138
139 .align 2
1401: .long swsusp_call_save
1412: .long 0x20000000 ! RB=1
1423: .long 0xdfffffff ! RB=0
1434: .long swsusp_save
1445: .long swsusp_arch_regs_cpu0
1456: .long SWSUSP_ARCH_REGS_SIZE
1467: .long save_low_regs
1478: .long save_regs
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index d608557c7a3f..203b18347b83 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -5,6 +5,7 @@
5obj-y := probe.o common.o 5obj-y := probe.o common.o
6common-y += $(addprefix ../sh3/, entry.o ex.o) 6common-y += $(addprefix ../sh3/, entry.o ex.o)
7 7
8obj-$(CONFIG_HIBERNATION) += $(addprefix ../sh3/, swsusp.o)
8obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o 9obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o
9obj-$(CONFIG_SH_STORE_QUEUES) += sq.o 10obj-$(CONFIG_SH_STORE_QUEUES) += sq.o
10 11
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 2e42572b1b11..3d3a3c4425a9 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -129,6 +129,13 @@ int __init detect_cpu_and_cache_system(void)
129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
130 CPU_HAS_LLSC; 130 CPU_HAS_LLSC;
131 break; 131 break;
132 case 0x4004:
133 boot_cpu_data.type = CPU_SH7786;
134 boot_cpu_data.icache.ways = 4;
135 boot_cpu_data.dcache.ways = 4;
136 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
137 CPU_HAS_LLSC | CPU_HAS_PTEAEX;
138 break;
132 case 0x3008: 139 case 0x3008:
133 boot_cpu_data.icache.ways = 4; 140 boot_cpu_data.icache.ways = 4;
134 boot_cpu_data.dcache.ways = 4; 141 boot_cpu_data.dcache.ways = 4;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index ec884039b914..a1c80d909cd6 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -21,17 +21,7 @@ static struct resource rtc_resources[] = {
21 .flags = IORESOURCE_IO, 21 .flags = IORESOURCE_IO,
22 }, 22 },
23 [1] = { 23 [1] = {
24 /* Period IRQ */ 24 /* Shared Period/Carry/Alarm IRQ */
25 .start = 21,
26 .flags = IORESOURCE_IRQ,
27 },
28 [2] = {
29 /* Carry IRQ */
30 .start = 22,
31 .flags = IORESOURCE_IRQ,
32 },
33 [3] = {
34 /* Alarm IRQ */
35 .start = 20, 25 .start = 20,
36 .flags = IORESOURCE_IRQ, 26 .flags = IORESOURCE_IRQ,
37 }, 27 },
@@ -50,13 +40,13 @@ static struct plat_sci_port sci_platform_data[] = {
50 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
51 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCI, 42 .type = PORT_SCI,
53 .irqs = { 23, 24, 25, 0 }, 43 .irqs = { 23, 23, 23, 0 },
54 }, { 44 }, {
55#endif 45#endif
56 .mapbase = 0xffe80000, 46 .mapbase = 0xffe80000,
57 .flags = UPF_BOOT_AUTOCONF, 47 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIF, 48 .type = PORT_SCIF,
59 .irqs = { 40, 41, 43, 42 }, 49 .irqs = { 40, 40, 40, 40 },
60 }, { 50 }, {
61 .flags = 0, 51 .flags = 0,
62 } 52 }
@@ -87,43 +77,27 @@ enum {
87 77
88 /* interrupt sources */ 78 /* interrupt sources */
89 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ 79 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
90 HUDI, GPIOI, 80 HUDI, GPIOI, DMAC,
91 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
92 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
93 DMAC_DMAE,
94 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 81 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
95 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 82 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
96 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 83 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
97 RTC_ATI, RTC_PRI, RTC_CUI,
98 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
99 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
100 WDT,
101 REF_RCMI, REF_ROVI,
102 84
103 /* interrupt groups */ 85 /* interrupt groups */
104 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 86 PCIC1,
105}; 87};
106 88
107static struct intc_vect vectors[] __initdata = { 89static struct intc_vect vectors[] __initdata = {
108 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 90 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
109 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 91 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
110 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 92 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
111 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 93 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
112 INTC_VECT(RTC_CUI, 0x4c0), 94 INTC_VECT(RTC, 0x4c0),
113 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 95 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
114 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 96 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
115 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 97 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
116 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 98 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
117 INTC_VECT(WDT, 0x560), 99 INTC_VECT(WDT, 0x560),
118 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 100 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
119};
120
121static struct intc_group groups[] __initdata = {
122 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
123 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
124 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
125 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
126 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
127}; 101};
128 102
129static struct intc_prio_reg prio_registers[] __initdata = { 103static struct intc_prio_reg prio_registers[] __initdata = {
@@ -136,7 +110,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
136 PCIC1, PCIC0_PCISERR } }, 110 PCIC1, PCIC0_PCISERR } },
137}; 111};
138 112
139static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups, 113static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
140 NULL, prio_registers, NULL); 114 NULL, prio_registers, NULL);
141 115
142/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 116/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
@@ -145,39 +119,28 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
145 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 119 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
146 defined(CONFIG_CPU_SUBTYPE_SH7091) 120 defined(CONFIG_CPU_SUBTYPE_SH7091)
147static struct intc_vect vectors_dma4[] __initdata = { 121static struct intc_vect vectors_dma4[] __initdata = {
148 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 122 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
149 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 123 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
150 INTC_VECT(DMAC_DMAE, 0x6c0), 124 INTC_VECT(DMAC, 0x6c0),
151};
152
153static struct intc_group groups_dma4[] __initdata = {
154 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
155 DMAC_DMTE3, DMAC_DMAE),
156}; 125};
157 126
158static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", 127static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
159 vectors_dma4, groups_dma4, 128 vectors_dma4, NULL,
160 NULL, prio_registers, NULL); 129 NULL, prio_registers, NULL);
161#endif 130#endif
162 131
163/* SH7750R and SH7751R both have 8-channel DMA controllers */ 132/* SH7750R and SH7751R both have 8-channel DMA controllers */
164#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) 133#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
165static struct intc_vect vectors_dma8[] __initdata = { 134static struct intc_vect vectors_dma8[] __initdata = {
166 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 135 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
167 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 136 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
168 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 137 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
169 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 138 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
170 INTC_VECT(DMAC_DMAE, 0x6c0), 139 INTC_VECT(DMAC, 0x6c0),
171};
172
173static struct intc_group groups_dma8[] __initdata = {
174 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
175 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
176 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
177}; 140};
178 141
179static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", 142static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
180 vectors_dma8, groups_dma8, 143 vectors_dma8, NULL,
181 NULL, prio_registers, NULL); 144 NULL, prio_registers, NULL);
182#endif 145#endif
183 146
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 8e344ec5847e..1a92361feeb9 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
@@ -21,6 +22,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
21clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o 22clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
22clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 23clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
23clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o 26clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
@@ -31,6 +33,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
31pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 33pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
32pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 34pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
33pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 35pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
34 37
35obj-y += $(clock-y) 38obj-y += $(clock-y)
36obj-$(CONFIG_SMP) += $(smp-y) 39obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
new file mode 100644
index 000000000000..f84a9c134471
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -0,0 +1,148 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
3 *
4 * SH7786 support for the clock framework
5 *
6 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
7 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 *
9 * Based on SH7785
10 * Copyright (C) 2007 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <asm/clock.h>
19#include <asm/freq.h>
20#include <asm/io.h>
21
22static int ifc_divisors[] = { 1, 2, 4, 1 };
23static int sfc_divisors[] = { 1, 1, 4, 1 };
24static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
25 24, 32, 1, 1, 1, 1, 1, 1 };
26static int mfc_divisors[] = { 1, 1, 4, 1 };
27static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
28 24, 32, 1, 48, 1, 1, 1, 1 };
29
30static void master_clk_init(struct clk *clk)
31{
32 clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
33}
34
35static struct clk_ops sh7786_master_clk_ops = {
36 .init = master_clk_init,
37};
38
39static void module_clk_recalc(struct clk *clk)
40{
41 int idx = (ctrl_inl(FRQMR1) & 0x000f);
42 clk->rate = clk->parent->rate / pfc_divisors[idx];
43}
44
45static struct clk_ops sh7786_module_clk_ops = {
46 .recalc = module_clk_recalc,
47};
48
49static void bus_clk_recalc(struct clk *clk)
50{
51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52 clk->rate = clk->parent->rate / bfc_divisors[idx];
53}
54
55static struct clk_ops sh7786_bus_clk_ops = {
56 .recalc = bus_clk_recalc,
57};
58
59static void cpu_clk_recalc(struct clk *clk)
60{
61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62 clk->rate = clk->parent->rate / ifc_divisors[idx];
63}
64
65static struct clk_ops sh7786_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc,
67};
68
69static struct clk_ops *sh7786_clk_ops[] = {
70 &sh7786_master_clk_ops,
71 &sh7786_module_clk_ops,
72 &sh7786_bus_clk_ops,
73 &sh7786_cpu_clk_ops,
74};
75
76void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
77{
78 if (idx < ARRAY_SIZE(sh7786_clk_ops))
79 *ops = sh7786_clk_ops[idx];
80}
81
82static void shyway_clk_recalc(struct clk *clk)
83{
84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85 clk->rate = clk->parent->rate / sfc_divisors[idx];
86}
87
88static struct clk_ops sh7786_shyway_clk_ops = {
89 .recalc = shyway_clk_recalc,
90};
91
92static struct clk sh7786_shyway_clk = {
93 .name = "shyway_clk",
94 .flags = CLK_ALWAYS_ENABLED,
95 .ops = &sh7786_shyway_clk_ops,
96};
97
98static void ddr_clk_recalc(struct clk *clk)
99{
100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101 clk->rate = clk->parent->rate / mfc_divisors[idx];
102}
103
104static struct clk_ops sh7786_ddr_clk_ops = {
105 .recalc = ddr_clk_recalc,
106};
107
108static struct clk sh7786_ddr_clk = {
109 .name = "ddr_clk",
110 .flags = CLK_ALWAYS_ENABLED,
111 .ops = &sh7786_ddr_clk_ops,
112};
113
114/*
115 * Additional SH7786-specific on-chip clocks that aren't already part of the
116 * clock framework
117 */
118static struct clk *sh7786_onchip_clocks[] = {
119 &sh7786_shyway_clk,
120 &sh7786_ddr_clk,
121};
122
123static int __init sh7786_clk_init(void)
124{
125 struct clk *clk = clk_get(NULL, "master_clk");
126 int i;
127
128 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
129 struct clk *clkp = sh7786_onchip_clocks[i];
130
131 clkp->parent = clk;
132 clk_register(clkp);
133 clk_enable(clkp);
134 }
135
136 /*
137 * Now that we have the rest of the clocks registered, we need to
138 * force the parent clock to propagate so that these clocks will
139 * automatically figure out their rate. We cheat by handing the
140 * parent clock its current rate and forcing child propagation.
141 */
142 clk_set_rate(clk, clk_get_rate(clk));
143
144 clk_put(clk);
145
146 return 0;
147}
148arch_initcall(sh7786_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
new file mode 100644
index 000000000000..373b3447bfdf
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -0,0 +1,950 @@
1/*
2 * SH7786 Pinmux
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 pinmux
8 *
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7786.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
26 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
27 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
28 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
29 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
30 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
31 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
32 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
33 PE7_DATA, PE6_DATA,
34 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
35 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
36 PG7_DATA, PG6_DATA, PG5_DATA,
37 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
38 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
39 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
40 PJ3_DATA, PJ2_DATA, PJ1_DATA,
41 PINMUX_DATA_END,
42
43 PINMUX_INPUT_BEGIN,
44 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
45 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
46 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
47 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
48 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
49 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
50 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
51 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
52 PE7_IN, PE6_IN,
53 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
54 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
55 PG7_IN, PG6_IN, PG5_IN,
56 PH7_IN, PH6_IN, PH5_IN, PH4_IN,
57 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
58 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
59 PJ3_IN, PJ2_IN, PJ1_IN,
60 PINMUX_INPUT_END,
61
62 PINMUX_INPUT_PULLUP_BEGIN,
63 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
64 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
65 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
66 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
67 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
68 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
69 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
70 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
71 PE7_IN_PU, PE6_IN_PU,
72 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
73 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
74 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
75 PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
76 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
77 PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
78 PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
79 PINMUX_INPUT_PULLUP_END,
80
81 PINMUX_OUTPUT_BEGIN,
82 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
83 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
84 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
85 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
86 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
87 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
88 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
89 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
90 PE7_OUT, PE6_OUT,
91 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
92 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
93 PG7_OUT, PG6_OUT, PG5_OUT,
94 PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
95 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
96 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
97 PJ3_OUT, PJ2_OUT, PJ1_OUT,
98 PINMUX_OUTPUT_END,
99
100 PINMUX_FUNCTION_BEGIN,
101 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
102 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
103 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
104 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
105 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
106 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
107 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
108 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
109 PE7_FN, PE6_FN,
110 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
111 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
112 PG7_FN, PG6_FN, PG5_FN,
113 PH7_FN, PH6_FN, PH5_FN, PH4_FN,
114 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
115 PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
116 PJ3_FN, PJ2_FN, PJ1_FN,
117 P1MSEL14_0, P1MSEL14_1,
118 P1MSEL13_0, P1MSEL13_1,
119 P1MSEL12_0, P1MSEL12_1,
120 P1MSEL11_0, P1MSEL11_1,
121 P1MSEL10_0, P1MSEL10_1,
122 P1MSEL9_0, P1MSEL9_1,
123 P1MSEL8_0, P1MSEL8_1,
124 P1MSEL7_0, P1MSEL7_1,
125 P1MSEL6_0, P1MSEL6_1,
126 P1MSEL5_0, P1MSEL5_1,
127 P1MSEL4_0, P1MSEL4_1,
128 P1MSEL3_0, P1MSEL3_1,
129 P1MSEL2_0, P1MSEL2_1,
130 P1MSEL1_0, P1MSEL1_1,
131 P1MSEL0_0, P1MSEL0_1,
132
133 P2MSEL15_0, P2MSEL15_1,
134 P2MSEL14_0, P2MSEL14_1,
135 P2MSEL13_0, P2MSEL13_1,
136 P2MSEL12_0, P2MSEL12_1,
137 P2MSEL11_0, P2MSEL11_1,
138 P2MSEL10_0, P2MSEL10_1,
139 P2MSEL9_0, P2MSEL9_1,
140 P2MSEL8_0, P2MSEL8_1,
141 P2MSEL7_0, P2MSEL7_1,
142 P2MSEL6_0, P2MSEL6_1,
143 P2MSEL5_0, P2MSEL5_1,
144 P2MSEL4_0, P2MSEL4_1,
145 P2MSEL3_0, P2MSEL3_1,
146 P2MSEL2_0, P2MSEL2_1,
147 P2MSEL1_0, P2MSEL1_1,
148 P2MSEL0_0, P2MSEL0_1,
149 PINMUX_FUNCTION_END,
150
151 PINMUX_MARK_BEGIN,
152 CDE_MARK,
153 ETH_MAGIC_MARK,
154 DISP_MARK,
155 ETH_LINK_MARK,
156 DR5_MARK,
157 ETH_TX_ER_MARK,
158 DR4_MARK,
159 ETH_TX_EN_MARK,
160 DR3_MARK,
161 ETH_TXD3_MARK,
162 DR2_MARK,
163 ETH_TXD2_MARK,
164 DR1_MARK,
165 ETH_TXD1_MARK,
166 DR0_MARK,
167 ETH_TXD0_MARK,
168
169 VSYNC_MARK,
170 HSPI_CLK_MARK,
171 ODDF_MARK,
172 HSPI_CS_MARK,
173 DG5_MARK,
174 ETH_MDIO_MARK,
175 DG4_MARK,
176 ETH_RX_CLK_MARK,
177 DG3_MARK,
178 ETH_MDC_MARK,
179 DG2_MARK,
180 ETH_COL_MARK,
181 DG1_MARK,
182 ETH_TX_CLK_MARK,
183 DG0_MARK,
184 ETH_CRS_MARK,
185
186 DCLKIN_MARK,
187 HSPI_RX_MARK,
188 HSYNC_MARK,
189 HSPI_TX_MARK,
190 DB5_MARK,
191 ETH_RXD3_MARK,
192 DB4_MARK,
193 ETH_RXD2_MARK,
194 DB3_MARK,
195 ETH_RXD1_MARK,
196 DB2_MARK,
197 ETH_RXD0_MARK,
198 DB1_MARK,
199 ETH_RX_DV_MARK,
200 DB0_MARK,
201 ETH_RX_ER_MARK,
202
203 DCLKOUT_MARK,
204 SCIF1_SLK_MARK,
205 SCIF1_RXD_MARK,
206 SCIF1_TXD_MARK,
207 DACK1_MARK,
208 BACK_MARK,
209 FALE_MARK,
210 DACK0_MARK,
211 FCLE_MARK,
212 DREQ1_MARK,
213 BREQ_MARK,
214 USB_OVC1_MARK,
215 DREQ0_MARK,
216 USB_OVC0_MARK,
217
218 USB_PENC1_MARK,
219 USB_PENC0_MARK,
220
221 HAC1_SDOUT_MARK,
222 SSI1_SDATA_MARK,
223 SDIF1CMD_MARK,
224 HAC1_SDIN_MARK,
225 SSI1_SCK_MARK,
226 SDIF1CD_MARK,
227 HAC1_SYNC_MARK,
228 SSI1_WS_MARK,
229 SDIF1WP_MARK,
230 HAC1_BITCLK_MARK,
231 SSI1_CLK_MARK,
232 SDIF1CLK_MARK,
233 HAC0_SDOUT_MARK,
234 SSI0_SDATA_MARK,
235 SDIF1D3_MARK,
236 HAC0_SDIN_MARK,
237 SSI0_SCK_MARK,
238 SDIF1D2_MARK,
239 HAC0_SYNC_MARK,
240 SSI0_WS_MARK,
241 SDIF1D1_MARK,
242 HAC0_BITCLK_MARK,
243 SSI0_CLK_MARK,
244 SDIF1D0_MARK,
245
246 SCIF3_SCK_MARK,
247 SSI2_SDATA_MARK,
248 SCIF3_RXD_MARK,
249 TCLK_MARK,
250 SSI2_SCK_MARK,
251 SCIF3_TXD_MARK,
252 HAC_RES_MARK,
253 SSI2_WS_MARK,
254
255 DACK3_MARK,
256 SDIF0CMD_MARK,
257 DACK2_MARK,
258 SDIF0CD_MARK,
259 DREQ3_MARK,
260 SDIF0WP_MARK,
261 SCIF0_CTS_MARK,
262 DREQ2_MARK,
263 SDIF0CLK_MARK,
264 SCIF0_RTS_MARK,
265 IRL7_MARK,
266 SDIF0D3_MARK,
267 SCIF0_SCK_MARK,
268 IRL6_MARK,
269 SDIF0D2_MARK,
270 SCIF0_RXD_MARK,
271 IRL5_MARK,
272 SDIF0D1_MARK,
273 SCIF0_TXD_MARK,
274 IRL4_MARK,
275 SDIF0D0_MARK,
276
277 SCIF5_SCK_MARK,
278 FRB_MARK,
279 SCIF5_RXD_MARK,
280 IOIS16_MARK,
281 SCIF5_TXD_MARK,
282 CE2B_MARK,
283 DRAK3_MARK,
284 CE2A_MARK,
285 SCIF4_SCK_MARK,
286 DRAK2_MARK,
287 SSI3_WS_MARK,
288 SCIF4_RXD_MARK,
289 DRAK1_MARK,
290 SSI3_SDATA_MARK,
291 FSTATUS_MARK,
292 SCIF4_TXD_MARK,
293 DRAK0_MARK,
294 SSI3_SCK_MARK,
295 FSE_MARK,
296 PINMUX_MARK_END,
297};
298
299static pinmux_enum_t pinmux_data[] = {
300
301 /* PA GPIO */
302 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
303 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
304 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
305 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
306 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
307 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
308 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
309 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
310
311 /* PB GPIO */
312 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
313 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
314 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
315 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
316 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
317 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
318 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
319 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
320
321 /* PC GPIO */
322 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
323 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
324 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
325 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
326 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
327 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
328 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
329 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
330
331 /* PD GPIO */
332 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
333 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
334 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
335 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
336 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
337 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
338 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
339 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
340
341 /* PE GPIO */
342 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
343 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
344
345 /* PF GPIO */
346 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
347 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
348 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
349 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
350 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
351 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
352 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
353 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
354
355 /* PG GPIO */
356 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
357 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
358 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
359
360 /* PH GPIO */
361 PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
362 PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
363 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
364 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
365 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
366 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
367 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
368 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
369
370 /* PJ GPIO */
371 PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
372 PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
373 PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
374 PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
375 PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
376 PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
377 PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
378
379 /* PA FN */
380 PINMUX_MARK_BEGIN,
381 PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
382 PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
383 PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
384 PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
385 PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
386 PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
387 PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
388 PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
389 PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
390 PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
391 PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
392 PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
393 PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
394 PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
395 PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
396 PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
397
398 /* PB FN */
399 PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
400 PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
401 PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
402 PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
403 PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
404 PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
405 PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
406 PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
407 PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
408 PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
409 PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
410 PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
411 PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
412 PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
413 PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
414 PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
415
416 /* PC FN */
417 PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
418 PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
419 PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
420 PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
421 PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
422 PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
423 PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
424 PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
425
426 PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
427 PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
428 PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
429 PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
430 PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
431 PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
432 PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
433 PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
434
435 /* PD FN */
436 PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
437 PINMUX_DATA(SCIF1_SLK_MARK, PD6_FN),
438 PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
439 PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
440 PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
441 PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
442 PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
443 PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
444 PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
445 PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
446 PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
447 PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
448 PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
449 PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
450
451 /* PE FN */
452 PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
453 PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
454
455 /* PF FN */
456 PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
457 PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
458 PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
459 PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
460 PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
461 PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
462 PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
463 PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
464 PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
465 PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
466 PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
467 PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
468 PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
469 PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
470 PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
471 PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
472 PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
473 PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
474 PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
475 PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
476 PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
477 PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
478 PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
479 PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
480
481 /* PG FN */
482 PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
483 PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
484 PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
485 PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
486 PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
487 PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
488 PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
489 PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
490
491 /* PH FN */
492 PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
493 PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
494 PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
495 PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
496 PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
497 PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
498 PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
499 PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
500 PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
501 PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
502 PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
503 PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
504 PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
505 PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
506 PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
507 PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
508 PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
509 PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
510 PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
511 PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
512 PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
513
514 /* PJ FN */
515 PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
516 PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
517 PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
518 PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
519 PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
520 PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
521 PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
522 PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
523 PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
524 PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
525 PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
526 PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
527 PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
528 PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
529 PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
530 PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
531 PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
532 PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
533 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
534};
535
536static struct pinmux_gpio pinmux_gpios[] = {
537 /* PA */
538 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
539 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
540 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
541 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
542 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
543 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
544 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
545 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
546
547 /* PB */
548 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
549 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
550 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
551 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
552 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
553 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
554 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
555 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
556
557 /* PC */
558 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
559 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
560 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
561 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
562 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
563 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
564 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
565 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
566
567 /* PD */
568 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
569 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
570 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
571 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
572 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
573 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
574 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
575 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
576
577 /* PE */
578 PINMUX_GPIO(GPIO_PE5, PE7_DATA),
579 PINMUX_GPIO(GPIO_PE4, PE6_DATA),
580
581 /* PF */
582 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
583 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
584 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
585 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
586 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
587 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
588 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
589 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
590
591 /* PG */
592 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
593 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
594 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
595
596 /* PH */
597 PINMUX_GPIO(GPIO_PH7, PH7_DATA),
598 PINMUX_GPIO(GPIO_PH6, PH6_DATA),
599 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
600 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
601 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
602 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
603 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
604 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
605
606 /* PJ */
607 PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
608 PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
609 PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
610 PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
611 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
612 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
613 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
614
615 /* FN */
616 PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
617 PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
618 PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
619 PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
620 PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
621 PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
622 PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
623 PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
624 PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
625 PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
626 PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
627 PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
628 PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
629 PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
630 PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
631 PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
632 PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
633 PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
634 PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
635 PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
636 PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
637 PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
638 PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
639 PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
640 PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
641 PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
642 PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
643 PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
644 PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
645 PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
646 PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
647 PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
648 PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
649 PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
650 PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
651 PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
652 PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
653 PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
654 PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
655 PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
656 PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
657 PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
658 PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
659 PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
660 PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
661 PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
662 PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
663 PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
664 PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
665 PINMUX_GPIO(GPIO_FN_SCIF1_SLK, SCIF1_SLK_MARK),
666 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
667 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
668 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
669 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
670 PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
671 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
672 PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
673 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
674 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
675 PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
676 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
677 PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
678 PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
679 PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
680 PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
681 PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
682 PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
683 PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
684 PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
685 PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
686 PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
687 PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
688 PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
689 PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
690 PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
691 PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
692 PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
693 PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
694 PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
695 PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
696 PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
697 PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
698 PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
699 PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
700 PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
701 PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
702 PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
703 PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
704 PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
705 PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
706 PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
707 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
708 PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
709 PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
710 PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
711 PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
712 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
713 PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
714 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
715 PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
716 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
717 PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
718 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
719 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
720 PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
721 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
722 PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
723 PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
724 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
725 PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
726 PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
727 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
728 PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
729 PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
730 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
731 PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
732 PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
733 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
734 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
735 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
736 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
737 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
738 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
739 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
740 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
741 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
742 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
743 PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
744 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
745 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
746 PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
747 PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
748 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
749 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
750 PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
751 PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
752};
753
754static struct pinmux_cfg_reg pinmux_config_regs[] = {
755 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
756 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
757 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
758 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
759 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
760 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
761 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
762 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
763 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
764 },
765 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
766 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
767 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
768 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
769 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
770 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
771 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
772 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
773 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
774 },
775 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
776 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
777 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
778 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
779 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
780 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
781 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
782 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
783 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
784 },
785 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
786 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
787 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
788 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
789 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
790 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
791 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
792 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
793 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
794 },
795 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
796 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
797 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
798 0, 0, 0, 0,
799 0, 0, 0, 0,
800 0, 0, 0, 0,
801 0, 0, 0, 0,
802 0, 0, 0, 0,
803 0, 0, 0, 0, }
804 },
805 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
806 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
807 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
808 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
809 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
810 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
811 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
812 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
813 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
814 },
815 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
816 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
817 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
818 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
819 0, 0, 0, 0,
820 0, 0, 0, 0,
821 0, 0, 0, 0,
822 0, 0, 0, 0,
823 0, 0, 0, 0, }
824 },
825 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
826 PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
827 PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
828 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
829 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
830 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
831 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
832 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
833 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
834 },
835 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
836 PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
837 PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
838 PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
839 PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
840 PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
841 PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
842 PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
843 0, 0, 0, 0, }
844 },
845 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
846 0, 0,
847 P1MSEL14_0, P1MSEL14_1,
848 P1MSEL13_0, P1MSEL13_1,
849 P1MSEL12_0, P1MSEL12_1,
850 P1MSEL11_0, P1MSEL11_1,
851 P1MSEL10_0, P1MSEL10_1,
852 P1MSEL9_0, P1MSEL9_1,
853 P1MSEL8_0, P1MSEL8_1,
854 P1MSEL7_0, P1MSEL7_1,
855 P1MSEL6_0, P1MSEL6_1,
856 P1MSEL5_0, P1MSEL5_1,
857 P1MSEL4_0, P1MSEL4_1,
858 P1MSEL3_0, P1MSEL3_1,
859 P1MSEL2_0, P1MSEL2_1,
860 P1MSEL1_0, P1MSEL1_1,
861 P1MSEL0_0, P1MSEL0_1 }
862 },
863 { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
864 P2MSEL15_0, P2MSEL15_1,
865 P2MSEL14_0, P2MSEL14_1,
866 P2MSEL13_0, P2MSEL13_1,
867 P2MSEL12_0, P2MSEL12_1,
868 P2MSEL11_0, P2MSEL11_1,
869 P2MSEL10_0, P2MSEL10_1,
870 P2MSEL9_0, P2MSEL9_1,
871 P2MSEL8_0, P2MSEL8_1,
872 P2MSEL7_0, P2MSEL7_1,
873 P2MSEL6_0, P2MSEL6_1,
874 P2MSEL5_0, P2MSEL5_1,
875 P2MSEL4_0, P2MSEL4_1,
876 P2MSEL3_0, P2MSEL3_1,
877 P2MSEL2_0, P2MSEL2_1,
878 P2MSEL1_0, P2MSEL1_1,
879 P2MSEL0_0, P2MSEL0_1 }
880 },
881 {}
882};
883
884static struct pinmux_data_reg pinmux_data_regs[] = {
885 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
886 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
887 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
888 },
889 { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
890 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
891 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
892 },
893 { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
894 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
895 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
896 },
897 { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
898 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
899 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
900 },
901 { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
902 PE7_DATA, PE6_DATA,
903 0, 0, 0, 0, 0, 0 }
904 },
905 { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
906 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
907 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
908 },
909 { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
910 PG7_DATA, PG6_DATA, PG5_DATA, 0,
911 0, 0, 0, 0 }
912 },
913 { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
914 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
915 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
916 },
917 { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
918 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
919 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
920 },
921 { },
922};
923
924static struct pinmux_info sh7786_pinmux_info = {
925 .name = "sh7786_pfc",
926 .reserved_id = PINMUX_RESERVED,
927 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
928 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
929 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
930 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
931 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
932 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
933
934 .first_gpio = GPIO_PA7,
935 .last_gpio = GPIO_FN_FSE,
936
937 .gpios = pinmux_gpios,
938 .cfg_regs = pinmux_config_regs,
939 .data_regs = pinmux_data_regs,
940
941 .gpio_data = pinmux_data,
942 .gpio_data_size = ARRAY_SIZE(pinmux_data),
943};
944
945static int __init plat_pinmux_setup(void)
946{
947 return register_pinmux(&sh7786_pinmux_info);
948}
949
950arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 4ff4dc64520c..c1549382c87c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -12,6 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/uio_driver.h> 14#include <linux/uio_driver.h>
15#include <linux/sh_cmt.h>
15#include <asm/clock.h> 16#include <asm/clock.h>
16 17
17static struct resource iic0_resources[] = { 18static struct resource iic0_resources[] = {
@@ -140,6 +141,38 @@ static struct platform_device jpu_device = {
140 .num_resources = ARRAY_SIZE(jpu_resources), 141 .num_resources = ARRAY_SIZE(jpu_resources),
141}; 142};
142 143
144static struct sh_cmt_config cmt_platform_data = {
145 .name = "CMT",
146 .channel_offset = 0x60,
147 .timer_bit = 5,
148 .clk = "cmt0",
149 .clockevent_rating = 125,
150 .clocksource_rating = 200,
151};
152
153static struct resource cmt_resources[] = {
154 [0] = {
155 .name = "CMT",
156 .start = 0x044a0060,
157 .end = 0x044a006b,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = 104,
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device cmt_device = {
167 .name = "sh_cmt",
168 .id = 0,
169 .dev = {
170 .platform_data = &cmt_platform_data,
171 },
172 .resource = cmt_resources,
173 .num_resources = ARRAY_SIZE(cmt_resources),
174};
175
143static struct plat_sci_port sci_platform_data[] = { 176static struct plat_sci_port sci_platform_data[] = {
144 { 177 {
145 .mapbase = 0xffe00000, 178 .mapbase = 0xffe00000,
@@ -175,6 +208,7 @@ static struct platform_device sci_device = {
175}; 208};
176 209
177static struct platform_device *sh7343_devices[] __initdata = { 210static struct platform_device *sh7343_devices[] __initdata = {
211 &cmt_device,
178 &iic0_device, 212 &iic0_device,
179 &iic1_device, 213 &iic1_device,
180 &sci_device, 214 &sci_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 839ae97a7fd2..93ecf8ed5c6c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -14,6 +14,7 @@
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/uio_driver.h> 16#include <linux/uio_driver.h>
17#include <linux/sh_cmt.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18 19
19static struct resource iic_resources[] = { 20static struct resource iic_resources[] = {
@@ -147,6 +148,38 @@ static struct platform_device veu1_device = {
147 .num_resources = ARRAY_SIZE(veu1_resources), 148 .num_resources = ARRAY_SIZE(veu1_resources),
148}; 149};
149 150
151static struct sh_cmt_config cmt_platform_data = {
152 .name = "CMT",
153 .channel_offset = 0x60,
154 .timer_bit = 5,
155 .clk = "cmt0",
156 .clockevent_rating = 125,
157 .clocksource_rating = 200,
158};
159
160static struct resource cmt_resources[] = {
161 [0] = {
162 .name = "CMT",
163 .start = 0x044a0060,
164 .end = 0x044a006b,
165 .flags = IORESOURCE_MEM,
166 },
167 [1] = {
168 .start = 104,
169 .flags = IORESOURCE_IRQ,
170 },
171};
172
173static struct platform_device cmt_device = {
174 .name = "sh_cmt",
175 .id = 0,
176 .dev = {
177 .platform_data = &cmt_platform_data,
178 },
179 .resource = cmt_resources,
180 .num_resources = ARRAY_SIZE(cmt_resources),
181};
182
150static struct plat_sci_port sci_platform_data[] = { 183static struct plat_sci_port sci_platform_data[] = {
151 { 184 {
152 .mapbase = 0xffe00000, 185 .mapbase = 0xffe00000,
@@ -167,6 +200,7 @@ static struct platform_device sci_device = {
167}; 200};
168 201
169static struct platform_device *sh7366_devices[] __initdata = { 202static struct platform_device *sh7366_devices[] __initdata = {
203 &cmt_device,
170 &iic_device, 204 &iic_device,
171 &sci_device, 205 &sci_device,
172 &usb_host_device, 206 &usb_host_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5146afc156e0..0e5d204bc792 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,6 +13,7 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h>
16#include <asm/clock.h> 17#include <asm/clock.h>
17#include <asm/mmzone.h> 18#include <asm/mmzone.h>
18 19
@@ -176,6 +177,38 @@ static struct platform_device jpu_device = {
176 .num_resources = ARRAY_SIZE(jpu_resources), 177 .num_resources = ARRAY_SIZE(jpu_resources),
177}; 178};
178 179
180static struct sh_cmt_config cmt_platform_data = {
181 .name = "CMT",
182 .channel_offset = 0x60,
183 .timer_bit = 5,
184 .clk = "cmt0",
185 .clockevent_rating = 125,
186 .clocksource_rating = 200,
187};
188
189static struct resource cmt_resources[] = {
190 [0] = {
191 .name = "CMT",
192 .start = 0x044a0060,
193 .end = 0x044a006b,
194 .flags = IORESOURCE_MEM,
195 },
196 [1] = {
197 .start = 104,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device cmt_device = {
203 .name = "sh_cmt",
204 .id = 0,
205 .dev = {
206 .platform_data = &cmt_platform_data,
207 },
208 .resource = cmt_resources,
209 .num_resources = ARRAY_SIZE(cmt_resources),
210};
211
179static struct plat_sci_port sci_platform_data[] = { 212static struct plat_sci_port sci_platform_data[] = {
180 { 213 {
181 .mapbase = 0xffe00000, 214 .mapbase = 0xffe00000,
@@ -209,6 +242,7 @@ static struct platform_device sci_device = {
209}; 242};
210 243
211static struct platform_device *sh7722_devices[] __initdata = { 244static struct platform_device *sh7722_devices[] __initdata = {
245 &cmt_device,
212 &rtc_device, 246 &rtc_device,
213 &usbf_device, 247 &usbf_device,
214 &iic_device, 248 &iic_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 849770d780ae..5338dacbcfba 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -13,6 +13,7 @@
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h>
16#include <asm/clock.h> 17#include <asm/clock.h>
17#include <asm/mmzone.h> 18#include <asm/mmzone.h>
18 19
@@ -100,6 +101,38 @@ static struct platform_device veu1_device = {
100 .num_resources = ARRAY_SIZE(veu1_resources), 101 .num_resources = ARRAY_SIZE(veu1_resources),
101}; 102};
102 103
104static struct sh_cmt_config cmt_platform_data = {
105 .name = "CMT",
106 .channel_offset = 0x60,
107 .timer_bit = 5,
108 .clk = "cmt0",
109 .clockevent_rating = 125,
110 .clocksource_rating = 200,
111};
112
113static struct resource cmt_resources[] = {
114 [0] = {
115 .name = "CMT",
116 .start = 0x044a0060,
117 .end = 0x044a006b,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = 104,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device cmt_device = {
127 .name = "sh_cmt",
128 .id = 0,
129 .dev = {
130 .platform_data = &cmt_platform_data,
131 },
132 .resource = cmt_resources,
133 .num_resources = ARRAY_SIZE(cmt_resources),
134};
135
103static struct plat_sci_port sci_platform_data[] = { 136static struct plat_sci_port sci_platform_data[] = {
104 { 137 {
105 .mapbase = 0xffe00000, 138 .mapbase = 0xffe00000,
@@ -221,6 +254,7 @@ static struct platform_device iic_device = {
221}; 254};
222 255
223static struct platform_device *sh7723_devices[] __initdata = { 256static struct platform_device *sh7723_devices[] __initdata = {
257 &cmt_device,
224 &sci_device, 258 &sci_device,
225 &rtc_device, 259 &rtc_device,
226 &iic_device, 260 &iic_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 3c5b629887a8..bdf0f61ae1ed 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2007 Yoshihiro Shimoda 5 * Copyright (C) 2007 Yoshihiro Shimoda
6 * Copyright (C) 2008 Nobuhiro Iwamatsu 6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -22,18 +22,8 @@ static struct resource rtc_resources[] = {
22 .flags = IORESOURCE_IO, 22 .flags = IORESOURCE_IO,
23 }, 23 },
24 [1] = { 24 [1] = {
25 /* Period IRQ */ 25 /* Shared Period/Carry/Alarm IRQ */
26 .start = 21, 26 .start = 20,
27 .flags = IORESOURCE_IRQ,
28 },
29 [2] = {
30 /* Carry IRQ */
31 .start = 22,
32 .flags = IORESOURCE_IRQ,
33 },
34 [3] = {
35 /* Alarm IRQ */
36 .start = 20,
37 .flags = IORESOURCE_IRQ, 27 .flags = IORESOURCE_IRQ,
38 }, 28 },
39}; 29};
@@ -50,17 +40,17 @@ static struct plat_sci_port sci_platform_data[] = {
50 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
51 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF, 42 .type = PORT_SCIF,
53 .irqs = { 40, 41, 43, 42 }, 43 .irqs = { 40, 40, 40, 40 },
54 }, { 44 }, {
55 .mapbase = 0xffe08000, 45 .mapbase = 0xffe08000,
56 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
57 .type = PORT_SCIF, 47 .type = PORT_SCIF,
58 .irqs = { 76, 77, 79, 78 }, 48 .irqs = { 76, 76, 76, 76 },
59 }, { 49 }, {
60 .mapbase = 0xffe10000, 50 .mapbase = 0xffe10000,
61 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
62 .type = PORT_SCIF, 52 .type = PORT_SCIF,
63 .irqs = { 104, 105, 107, 106 }, 53 .irqs = { 104, 104, 104, 104 },
64 }, { 54 }, {
65 .flags = 0, 55 .flags = 0,
66 } 56 }
@@ -148,93 +138,65 @@ enum {
148 IRL_HHLL, IRL_HHLH, IRL_HHHL, 138 IRL_HHLL, IRL_HHLH, IRL_HHHL,
149 139
150 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 140 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
151 RTC_ATI, RTC_PRI, RTC_CUI, 141 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
152 WDT, TMU0, TMU1, TMU2, TMU2_TICPI, 142 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
153 HUDI, LCDC, 143 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
154 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE, 144 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
155 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, 145 USBH, USBF, TPU, PCC, MMCIF, SIM,
156 DMAC0_DMINT4, DMAC0_DMINT5,
157 IIC0, IIC1,
158 CMT,
159 GEINT0, GEINT1, GEINT2,
160 HAC,
161 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
162 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
163 STIF0, STIF1,
164 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
165 SIOF0, SIOF1, SIOF2,
166 USBH, USBFI0, USBFI1,
167 TPU, PCC,
168 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
169 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
170 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, 146 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
171 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, 147 SCIF2, GPIO,
172 GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3,
173 148
174 /* interrupt groups */ 149 /* interrupt groups */
175 150
176 TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5, 151 TMU012, TMU345,
177 SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO,
178}; 152};
179 153
180static struct intc_vect vectors[] __initdata = { 154static struct intc_vect vectors[] __initdata = {
181 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 155 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
182 INTC_VECT(RTC_CUI, 0x4c0), 156 INTC_VECT(RTC, 0x4c0),
183 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), 157 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
184 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), 158 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
185 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), 159 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
186 INTC_VECT(LCDC, 0x620), 160 INTC_VECT(LCDC, 0x620),
187 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), 161 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
188 INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), 162 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
189 INTC_VECT(DMAC0_DMAE, 0x6c0), 163 INTC_VECT(DMAC, 0x6c0),
190 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 164 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
191 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 165 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
192 INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), 166 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
193 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), 167 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
194 INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920), 168 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
195 INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960), 169 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
196 INTC_VECT(HAC, 0x980), 170 INTC_VECT(HAC, 0x980),
197 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 171 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
198 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 172 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
199 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 173 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
200 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 174 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
201 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 175 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
202 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), 176 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
203 INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), 177 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
204 INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), 178 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
205 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), 179 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
206 INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80), 180 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
207 INTC_VECT(USBFI1, 0xca0), 181 INTC_VECT(USBF, 0xca0),
208 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), 182 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
209 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 183 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
210 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 184 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
211 INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0), 185 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
212 INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0), 186 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
213 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 187 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
214 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), 188 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
215 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 189 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
216 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), 190 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
217 INTC_VECT(SCIF2_ERI, 0xf00), INTC_VECT(SCIF2_RXI, 0xf20), 191 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
218 INTC_VECT(SCIF2_BRI, 0xf40), INTC_VECT(SCIF2_TXI, 0xf60), 192 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
219 INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0), 193 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
220 INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0), 194 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
221}; 195};
222 196
223static struct intc_group groups[] __initdata = { 197static struct intc_group groups[] __initdata = {
224 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 198 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
225 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 199 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
226 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
227 INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
228 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
229 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
230 INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2),
231 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
232 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
233 INTC_GROUP(USBF, USBFI0, USBFI1),
234 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
235 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
236 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
237 INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
238}; 200};
239 201
240static struct intc_mask_reg mask_registers[] __initdata = { 202static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index fb8200cc7440..6f7227cd65bf 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -20,17 +20,7 @@ static struct resource rtc_resources[] = {
20 .flags = IORESOURCE_IO, 20 .flags = IORESOURCE_IO,
21 }, 21 },
22 [1] = { 22 [1] = {
23 /* Period IRQ */ 23 /* Shared Period/Carry/Alarm IRQ */
24 .start = 21,
25 .flags = IORESOURCE_IRQ,
26 },
27 [2] = {
28 /* Carry IRQ */
29 .start = 22,
30 .flags = IORESOURCE_IRQ,
31 },
32 [3] = {
33 /* Alarm IRQ */
34 .start = 20, 24 .start = 20,
35 .flags = IORESOURCE_IRQ, 25 .flags = IORESOURCE_IRQ,
36 }, 26 },
@@ -48,12 +38,12 @@ static struct plat_sci_port sci_platform_data[] = {
48 .mapbase = 0xffe00000, 38 .mapbase = 0xffe00000,
49 .flags = UPF_BOOT_AUTOCONF, 39 .flags = UPF_BOOT_AUTOCONF,
50 .type = PORT_SCIF, 40 .type = PORT_SCIF,
51 .irqs = { 40, 41, 43, 42 }, 41 .irqs = { 40, 40, 40, 40 },
52 }, { 42 }, {
53 .mapbase = 0xffe10000, 43 .mapbase = 0xffe10000,
54 .flags = UPF_BOOT_AUTOCONF, 44 .flags = UPF_BOOT_AUTOCONF,
55 .type = PORT_SCIF, 45 .type = PORT_SCIF,
56 .irqs = { 76, 77, 79, 78 }, 46 .irqs = { 76, 76, 76, 76 },
57 }, { 47 }, {
58 .flags = 0, 48 .flags = 0,
59 } 49 }
@@ -90,82 +80,55 @@ enum {
90 IRL_HHLL, IRL_HHLH, IRL_HHHL, 80 IRL_HHLL, IRL_HHLH, IRL_HHHL,
91 81
92 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 82 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
93 RTC_ATI, RTC_PRI, RTC_CUI, 83 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
94 WDT, 84 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
95 TMU0, TMU1, TMU2, TMU2_TICPI, 85 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
96 HUDI, 86 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
98 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
99 DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
100 CMT, HAC,
101 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
102 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
103 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
104 SIOF, HSPI,
105 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
106 DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
107 TMU3, TMU4, TMU5,
108 SSI,
109 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
110 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
111 87
112 /* interrupt groups */ 88 /* interrupt groups */
113 89
114 RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1, 90 TMU012, TMU345,
115 PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
116}; 91};
117 92
118static struct intc_vect vectors[] __initdata = { 93static struct intc_vect vectors[] __initdata = {
119 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 94 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
120 INTC_VECT(RTC_CUI, 0x4c0), 95 INTC_VECT(RTC, 0x4c0),
121 INTC_VECT(WDT, 0x560), 96 INTC_VECT(WDT, 0x560),
122 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 97 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
123 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 98 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
124 INTC_VECT(HUDI, 0x600), 99 INTC_VECT(HUDI, 0x600),
125 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), 100 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
126 INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), 101 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
127 INTC_VECT(DMAC0_DMAE, 0x6c0), 102 INTC_VECT(DMAC0, 0x6c0),
128 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 103 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
129 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 104 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
130 INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), 105 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
131 INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0), 106 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
132 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980), 107 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
133 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 108 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
134 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 109 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
135 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 110 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
136 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 111 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
137 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 112 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
138 INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), 113 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
139 INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), 114 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
140 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80), 115 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
141 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 116 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
142 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 117 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
143 INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0), 118 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
144 INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0), 119 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
145 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 120 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
146 INTC_VECT(TMU5, 0xe40), 121 INTC_VECT(TMU5, 0xe40),
147 INTC_VECT(SSI, 0xe80), 122 INTC_VECT(SSI, 0xe80),
148 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), 123 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
149 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), 124 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
150 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), 125 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
151 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 126 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
152}; 127};
153 128
154static struct intc_group groups[] __initdata = { 129static struct intc_group groups[] __initdata = {
155 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
156 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 130 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
157 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
158 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
159 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
160 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
161 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
162 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
163 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
164 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
165 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 131 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
166 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
167 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
168 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
169}; 132};
170 133
171static struct intc_mask_reg mask_registers[] __initdata = { 134static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 30baa63b24c8..d80802a49dbd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,18 +20,13 @@ static struct plat_sci_port sci_platform_data[] = {
20 .mapbase = 0xffea0000, 20 .mapbase = 0xffea0000,
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 40, 41, 43, 42 }, 23 .irqs = { 40, 40, 40, 40 },
24 }, { 24 }, {
25 .mapbase = 0xffeb0000, 25 .mapbase = 0xffeb0000,
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 44, 45, 47, 46 }, 28 .irqs = { 44, 44, 44, 44 },
29 }, 29 }, {
30
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffec0000, 30 .mapbase = 0xffec0000,
36 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF, 32 .type = PORT_SCIF,
@@ -91,33 +86,19 @@ enum {
91 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 86 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
92 87
93 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 88 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
94 WDT, 89 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
95 TMU0, TMU1, TMU2, TMU2_TICPI, 90 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
96 HUDI,
97 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
98 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
99 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
100 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
101 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
102 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
103 HSPI,
104 SCIF2, SCIF3, SCIF4, SCIF5, 91 SCIF2, SCIF3, SCIF4, SCIF5,
105 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, 92 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
106 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0, 93 SIOF, MMCIF, DU, GDTA,
107 SIOF,
108 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
109 DU,
110 GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
111 TMU3, TMU4, TMU5, 94 TMU3, TMU4, TMU5,
112 SSI0, SSI1, 95 SSI0, SSI1,
113 HAC0, HAC1, 96 HAC0, HAC1,
114 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1, 97 FLCTL, GPIO,
115 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
116 98
117 /* interrupt groups */ 99 /* interrupt groups */
118 100
119 TMU012, DMAC0, SCIF0, SCIF1, DMAC1, 101 TMU012, TMU345
120 PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
121}; 102};
122 103
123static struct intc_vect vectors[] __initdata = { 104static struct intc_vect vectors[] __initdata = {
@@ -125,57 +106,45 @@ static struct intc_vect vectors[] __initdata = {
125 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), 106 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
126 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), 107 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
127 INTC_VECT(HUDI, 0x600), 108 INTC_VECT(HUDI, 0x600),
128 INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640), 109 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
129 INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680), 110 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
130 INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0), 111 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
131 INTC_VECT(DMAC0_DMAE, 0x6e0), 112 INTC_VECT(DMAC0, 0x6e0),
132 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), 113 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
133 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 114 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
134 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), 115 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
135 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), 116 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
136 INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0), 117 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
137 INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0), 118 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
138 INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920), 119 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
139 INTC_VECT(DMAC1_DMAE, 0x940), 120 INTC_VECT(DMAC1, 0x940),
140 INTC_VECT(HSPI, 0x960), 121 INTC_VECT(HSPI, 0x960),
141 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0), 122 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
142 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0), 123 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
143 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), 124 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
144 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), 125 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
145 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), 126 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
146 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), 127 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
147 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), 128 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
148 INTC_VECT(SIOF, 0xc00), 129 INTC_VECT(SIOF, 0xc00),
149 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), 130 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
150 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), 131 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
151 INTC_VECT(DU, 0xd80), 132 INTC_VECT(DU, 0xd80),
152 INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0), 133 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
153 INTC_VECT(GDTA_GAERI, 0xde0), 134 INTC_VECT(GDTA, 0xde0),
154 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), 135 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
155 INTC_VECT(TMU5, 0xe40), 136 INTC_VECT(TMU5, 0xe40),
156 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), 137 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
157 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0), 138 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
158 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20), 139 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
159 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60), 140 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
160 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0), 141 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
161 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), 142 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
162}; 143};
163 144
164static struct intc_group groups[] __initdata = { 145static struct intc_group groups[] __initdata = {
165 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), 146 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
166 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
167 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
168 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
169 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
170 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
171 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
172 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
173 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
174 INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
175 INTC_GROUP(TMU345, TMU3, TMU4, TMU5), 147 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
176 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
177 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
178 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
179}; 148};
180 149
181static struct intc_mask_reg mask_registers[] __initdata = { 150static struct intc_mask_reg mask_registers[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
new file mode 100644
index 000000000000..5a47e1cf442e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -0,0 +1,490 @@
1/*
2 * SH7786 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 Setup
8 *
9 * Copyright (C) 2007 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/serial_sci.h>
19#include <linux/io.h>
20#include <linux/mm.h>
21#include <linux/dma-mapping.h>
22#include <asm/mmzone.h>
23
24static struct plat_sci_port sci_platform_data[] = {
25 {
26 .mapbase = 0xffea0000,
27 .flags = UPF_BOOT_AUTOCONF,
28 .type = PORT_SCIF,
29 .irqs = { 40, 41, 43, 42 },
30 },
31 /*
32 * The rest of these all have multiplexed IRQs
33 */
34 {
35 .mapbase = 0xffeb0000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 44, 44, 44, 44 },
39 }, {
40 .mapbase = 0xffec0000,
41 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF,
43 .irqs = { 50, 50, 50, 50 },
44 }, {
45 .mapbase = 0xffed0000,
46 .flags = UPF_BOOT_AUTOCONF,
47 .type = PORT_SCIF,
48 .irqs = { 51, 51, 51, 51 },
49 }, {
50 .mapbase = 0xffee0000,
51 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF,
53 .irqs = { 52, 52, 52, 52 },
54 }, {
55 .mapbase = 0xffef0000,
56 .flags = UPF_BOOT_AUTOCONF,
57 .type = PORT_SCIF,
58 .irqs = { 53, 53, 53, 53 },
59 }, {
60 .flags = 0,
61 }
62};
63
64static struct platform_device sci_device = {
65 .name = "sh-sci",
66 .id = -1,
67 .dev = {
68 .platform_data = sci_platform_data,
69 },
70};
71
72static struct resource usb_ohci_resources[] = {
73 [0] = {
74 .start = 0xffe70400,
75 .end = 0xffe704ff,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = 77,
80 .end = 77,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
86static struct platform_device usb_ohci_device = {
87 .name = "sh_ohci",
88 .id = -1,
89 .dev = {
90 .dma_mask = &usb_ohci_dma_mask,
91 .coherent_dma_mask = DMA_BIT_MASK(32),
92 },
93 .num_resources = ARRAY_SIZE(usb_ohci_resources),
94 .resource = usb_ohci_resources,
95};
96
97static struct platform_device *sh7786_devices[] __initdata = {
98 &sci_device,
99 &usb_ohci_device,
100};
101
102
103/*
104 * Please call this function if your platform board
105 * use external clock for USB
106 * */
107#define USBCTL0 0xffe70858
108#define CLOCK_MODE_MASK 0xffffff7f
109#define EXT_CLOCK_MODE 0x00000080
110void __init sh7786_usb_use_exclock(void)
111{
112 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
113 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
114}
115
116#define USBINITREG1 0xffe70094
117#define USBINITREG2 0xffe7009c
118#define USBINITVAL1 0x00ff0040
119#define USBINITVAL2 0x00000001
120
121#define USBPCTL1 0xffe70804
122#define USBST 0xffe70808
123#define PHY_ENB 0x00000001
124#define PLL_ENB 0x00000002
125#define PHY_RST 0x00000004
126#define ACT_PLL_STATUS 0xc0000000
127static void __init sh7786_usb_setup(void)
128{
129 int i = 1000000;
130
131 /*
132 * USB initial settings
133 *
134 * The following settings are necessary
135 * for using the USB modules.
136 *
137 * see "USB Inital Settings" for detail
138 */
139 __raw_writel(USBINITVAL1, USBINITREG1);
140 __raw_writel(USBINITVAL2, USBINITREG2);
141
142 /*
143 * Set the PHY and PLL enable bit
144 */
145 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
146 while (i-- &&
147 ((__raw_readl(USBST) & ACT_PLL_STATUS) != ACT_PLL_STATUS))
148 cpu_relax();
149
150 if (i) {
151 /* Set the PHY RST bit */
152 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
153 printk(KERN_INFO "sh7786 usb setup done\n");
154 }
155}
156
157static int __init sh7786_devices_setup(void)
158{
159 sh7786_usb_setup();
160 return platform_add_devices(sh7786_devices,
161 ARRAY_SIZE(sh7786_devices));
162}
163device_initcall(sh7786_devices_setup);
164
165enum {
166 UNUSED = 0,
167
168 /* interrupt sources */
169
170 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
171 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
172 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
173 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
174
175 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
176 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
177 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
178 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
179
180 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
181 WDT,
182 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
183 TMU1_0, TMU1_1, TMU1_2,
184 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
185 HUDI1, HUDI0,
186 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
187 HPB_0, HPB_1, HPB_2,
188 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
189 SCIF1,
190 TMU2, TMU3,
191 SCIF2, SCIF3, SCIF4, SCIF5,
192 Eth_0, Eth_1,
193 PCIeC0_0, PCIeC0_1, PCIeC0_2,
194 PCIeC1_0, PCIeC1_1, PCIeC1_2,
195 USB,
196 I2C0, I2C1,
197 DU,
198 SSI0, SSI1, SSI2, SSI3,
199 PCIeC2_0, PCIeC2_1, PCIeC2_2,
200 HAC0, HAC1,
201 FLCTL,
202 HSPI,
203 GPIO0, GPIO1,
204 Thermal,
205 INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
206
207 /* interrupt groups */
208};
209
210static struct intc_vect vectors[] __initdata = {
211 INTC_VECT(WDT, 0x3e0),
212 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
213 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
214 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
215 INTC_VECT(TMU1_2, 0x4c0),
216 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
217 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
218 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
219 INTC_VECT(DMAC0_6, 0x5c0),
220 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
221 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
222 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
223 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
224 INTC_VECT(HPB_2, 0x6e0),
225 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
226 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
227 INTC_VECT(SCIF1, 0x780),
228 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
229 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
230 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
231 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
232 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
233 INTC_VECT(PCIeC0_2, 0xb20),
234 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
235 INTC_VECT(PCIeC1_2, 0xb80),
236 INTC_VECT(USB, 0xba0),
237 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
238 INTC_VECT(DU, 0xd00),
239 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
240 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
241 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
242 INTC_VECT(PCIeC2_2, 0xde0),
243 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
244 INTC_VECT(FLCTL, 0xe40),
245 INTC_VECT(HSPI, 0xe80),
246 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
247 INTC_VECT(Thermal, 0xee0),
248};
249
250/* FIXME: Main CPU support only now */
251#if 1 /* Main CPU */
252#define CnINTMSK0 0xfe410030
253#define CnINTMSK1 0xfe410040
254#define CnINTMSKCLR0 0xfe410050
255#define CnINTMSKCLR1 0xfe410060
256#define CnINT2MSKR0 0xfe410a20
257#define CnINT2MSKR1 0xfe410a24
258#define CnINT2MSKR2 0xfe410a28
259#define CnINT2MSKR3 0xfe410a2c
260#define CnINT2MSKCR0 0xfe410a30
261#define CnINT2MSKCR1 0xfe410a34
262#define CnINT2MSKCR2 0xfe410a38
263#define CnINT2MSKCR3 0xfe410a3c
264#else /* Sub CPU */
265#define CnINTMSK0 0xfe410034
266#define CnINTMSK1 0xfe410044
267#define CnINTMSKCLR0 0xfe410054
268#define CnINTMSKCLR1 0xfe410064
269#define CnINT2MSKR0 0xfe410b20
270#define CnINT2MSKR1 0xfe410b24
271#define CnINT2MSKR2 0xfe410b28
272#define CnINT2MSKR3 0xfe410b2c
273#define CnINT2MSKCR0 0xfe410b30
274#define CnINT2MSKCR1 0xfe410b34
275#define CnINT2MSKCR2 0xfe410b38
276#define CnINT2MSKCR3 0xfe410b3c
277#endif
278
279#define INTMSK2 0xfe410068
280#define INTMSKCLR2 0xfe41006c
281
282static struct intc_mask_reg mask_registers[] __initdata = {
283 { CnINTMSK0, CnINTMSKCLR0, 32,
284 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
285 { INTMSK2, INTMSKCLR2, 32,
286 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
287 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
288 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
289 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
290 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
291 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
292 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
293 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
294 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
295 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
297 { CnINT2MSKR1, CnINT2MSKCR1, 32,
298 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
299 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
300 HUDI1, HUDI0,
301 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
302 HPB_0, HPB_1, HPB_2,
303 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
304 SCIF1,
305 TMU2, TMU3, 0, } },
306 { CnINT2MSKR2, CnINT2MSKCR2, 32,
307 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
308 Eth_0, Eth_1,
309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
310 PCIeC0_0, PCIeC0_1, PCIeC0_2,
311 PCIeC1_0, PCIeC1_1, PCIeC1_2,
312 USB, 0, 0 } },
313 { CnINT2MSKR3, CnINT2MSKCR3, 32,
314 { 0, 0, 0, 0, 0, 0,
315 I2C0, I2C1,
316 DU, SSI0, SSI1, SSI2, SSI3,
317 PCIeC2_0, PCIeC2_1, PCIeC2_2,
318 HAC0, HAC1,
319 FLCTL, 0,
320 HSPI, GPIO0, GPIO1, Thermal,
321 0, 0, 0, 0, 0, 0, 0, 0 } },
322};
323
324static struct intc_prio_reg prio_registers[] __initdata = {
325 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
326 IRQ4, IRQ5, IRQ6, IRQ7 } },
327 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
328 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
329 TMU0_2, TMU0_3 } },
330 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
331 TMU1_2, 0 } },
332 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
333 DMAC0_2, DMAC0_3 } },
334 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
335 DMAC0_6, HUDI1 } },
336 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
337 DMAC1_1, DMAC1_2 } },
338 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
339 HPB_1, HPB_2 } },
340 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
341 SCIF0_2, SCIF0_3 } },
342 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
343 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
344 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
345 Eth_0, Eth_1 } },
346 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
347 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
348 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
349 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
350 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
351 PCIeC1_0, PCIeC1_1 } },
352 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
353 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
354 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
355 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
356 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
357 PCIeC2_1, PCIeC2_2 } },
358 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
359 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
360 GPIO1, Thermal } },
361 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
362 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
363};
364
365static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
366 mask_registers, prio_registers, NULL);
367
368/* Support for external interrupt pins in IRQ mode */
369
370static struct intc_vect vectors_irq0123[] __initdata = {
371 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
372 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
373};
374
375static struct intc_vect vectors_irq4567[] __initdata = {
376 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
377 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
378};
379
380static struct intc_sense_reg sense_registers[] __initdata = {
381 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
382 IRQ4, IRQ5, IRQ6, IRQ7 } },
383};
384
385static struct intc_mask_reg ack_registers[] __initdata = {
386 { 0xfe410024, 0, 32, /* INTREQ */
387 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
388};
389
390static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
391 vectors_irq0123, NULL, mask_registers,
392 prio_registers, sense_registers, ack_registers);
393
394static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
395 vectors_irq4567, NULL, mask_registers,
396 prio_registers, sense_registers, ack_registers);
397
398/* External interrupt pins in IRL mode */
399
400static struct intc_vect vectors_irl0123[] __initdata = {
401 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
402 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
403 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
404 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
405 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
406 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
407 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
408 INTC_VECT(IRL0_HHHL, 0x3c0),
409};
410
411static struct intc_vect vectors_irl4567[] __initdata = {
412 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
413 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
414 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
415 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
416 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
417 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
418 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
419 INTC_VECT(IRL4_HHHL, 0xac0),
420};
421
422static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
423 NULL, mask_registers, NULL, NULL);
424
425static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
426 NULL, mask_registers, NULL, NULL);
427
428#define INTC_ICR0 0xfe410000
429#define INTC_INTMSK0 CnINTMSK0
430#define INTC_INTMSK1 CnINTMSK1
431#define INTC_INTMSK2 INTMSK2
432#define INTC_INTMSKCLR1 CnINTMSKCLR1
433#define INTC_INTMSKCLR2 INTMSKCLR2
434
435void __init plat_irq_setup(void)
436{
437 /* disable IRQ3-0 + IRQ7-4 */
438 ctrl_outl(0xff000000, INTC_INTMSK0);
439
440 /* disable IRL3-0 + IRL7-4 */
441 ctrl_outl(0xc0000000, INTC_INTMSK1);
442 ctrl_outl(0xfffefffe, INTC_INTMSK2);
443
444 /* select IRL mode for IRL3-0 + IRL7-4 */
445 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
446
447 register_intc_controller(&intc_desc);
448}
449
450void __init plat_irq_setup_pins(int mode)
451{
452 switch (mode) {
453 case IRQ_MODE_IRQ7654:
454 /* select IRQ mode for IRL7-4 */
455 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
456 register_intc_controller(&intc_desc_irq4567);
457 break;
458 case IRQ_MODE_IRQ3210:
459 /* select IRQ mode for IRL3-0 */
460 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
461 register_intc_controller(&intc_desc_irq0123);
462 break;
463 case IRQ_MODE_IRL7654:
464 /* enable IRL7-4 but don't provide any masking */
465 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
466 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
467 break;
468 case IRQ_MODE_IRL3210:
469 /* enable IRL0-3 but don't provide any masking */
470 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
471 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
472 break;
473 case IRQ_MODE_IRL7654_MASK:
474 /* enable IRL7-4 and mask using cpu intc controller */
475 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
476 register_intc_controller(&intc_desc_irl4567);
477 break;
478 case IRQ_MODE_IRL3210_MASK:
479 /* enable IRL0-3 and mask using cpu intc controller */
480 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
481 register_intc_controller(&intc_desc_irl0123);
482 break;
483 default:
484 BUG();
485 }
486}
487
488void __init plat_mem_setup(void)
489{
490}
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
new file mode 100644
index 000000000000..08bfa7c7db29
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the Linux/SuperH SH-Mobile backends.
3#
4
5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
new file mode 100644
index 000000000000..8c067adf6830
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -0,0 +1,92 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/pm-sh_mobile.c
3 *
4 * Power management support code for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/suspend.h>
16#include <asm/suspend.h>
17#include <asm/uaccess.h>
18
19/*
20 * Sleep modes available on SuperH Mobile:
21 *
22 * Sleep mode is just plain "sleep" instruction
23 * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
24 * Standby Self-Refresh mode is above plus stopped clocks
25 */
26#define SUSP_MODE_SLEEP (SUSP_SH_SLEEP)
27#define SUSP_MODE_SLEEP_SF (SUSP_SH_SLEEP | SUSP_SH_SF)
28#define SUSP_MODE_STANDBY_SF (SUSP_SH_STANDBY | SUSP_SH_SF)
29
30/*
31 * The following modes are not there yet:
32 *
33 * R-standby mode is unsupported, but will be added in the future
34 * U-standby mode is low priority since it needs bootloader hacks
35 *
36 * All modes should be tied in with cpuidle. But before that can
37 * happen we need to keep track of enabled hardware blocks so we
38 * can avoid entering sleep modes that stop clocks to hardware
39 * blocks that are in use even though the cpu core is idle.
40 */
41
42extern const unsigned char sh_mobile_standby[];
43extern const unsigned int sh_mobile_standby_size;
44
45static void sh_mobile_call_standby(unsigned long mode)
46{
47 extern void *vbr_base;
48 void *onchip_mem = (void *)0xe5200000; /* ILRAM */
49 void (*standby_onchip_mem)(unsigned long) = onchip_mem;
50
51 /* Note: Wake up from sleep may generate exceptions!
52 * Setup VBR to point to on-chip ram if self-refresh is
53 * going to be used.
54 */
55 if (mode & SUSP_SH_SF)
56 asm volatile("ldc %0, vbr" : : "r" (onchip_mem) : "memory");
57
58 /* Copy the assembly snippet to the otherwise ununsed ILRAM */
59 memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
60 wmb();
61 ctrl_barrier();
62
63 /* Let assembly snippet in on-chip memory handle the rest */
64 standby_onchip_mem(mode);
65
66 /* Put VBR back in System RAM again */
67 if (mode & SUSP_SH_SF)
68 asm volatile("ldc %0, vbr" : : "r" (&vbr_base) : "memory");
69}
70
71static int sh_pm_enter(suspend_state_t state)
72{
73 local_irq_disable();
74 set_bl_bit();
75 sh_mobile_call_standby(SUSP_MODE_STANDBY_SF);
76 local_irq_disable();
77 clear_bl_bit();
78 return 0;
79}
80
81static struct platform_suspend_ops sh_pm_ops = {
82 .enter = sh_pm_enter,
83 .valid = suspend_valid_only_mem,
84};
85
86static int __init sh_pm_init(void)
87{
88 suspend_set_ops(&sh_pm_ops);
89 return 0;
90}
91
92late_initcall(sh_pm_init);
diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S
new file mode 100644
index 000000000000..5d888ef53d82
--- /dev/null
+++ b/arch/sh/kernel/cpu/shmobile/sleep.S
@@ -0,0 +1,125 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/sleep-sh_mobile.S
3 *
4 * Sleep mode and Standby modes support for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/sys.h>
14#include <linux/errno.h>
15#include <linux/linkage.h>
16#include <asm/asm-offsets.h>
17#include <asm/suspend.h>
18
19/* manage self-refresh and enter standby mode.
20 * this code will be copied to on-chip memory and executed from there.
21 */
22
23 .balign 4096,0,4096
24ENTRY(sh_mobile_standby)
25 mov r4, r0
26
27 tst #SUSP_SH_SF, r0
28 bt skip_set_sf
29
30 /* SDRAM: disable power down and put in self-refresh mode */
31 mov.l 1f, r4
32 mov.l 2f, r1
33 mov.l @r4, r2
34 or r1, r2
35 mov.l 3f, r3
36 and r3, r2
37 mov.l r2, @r4
38
39skip_set_sf:
40 tst #SUSP_SH_SLEEP, r0
41 bt test_standby
42
43 /* set mode to "sleep mode" */
44 bra do_sleep
45 mov #0x00, r1
46
47test_standby:
48 tst #SUSP_SH_STANDBY, r0
49 bt test_rstandby
50
51 /* set mode to "software standby mode" */
52 bra do_sleep
53 mov #0x80, r1
54
55test_rstandby:
56 tst #SUSP_SH_RSTANDBY, r0
57 bt test_ustandby
58
59 /* set mode to "r-standby mode" */
60 bra do_sleep
61 mov #0x20, r1
62
63test_ustandby:
64 tst #SUSP_SH_USTANDBY, r0
65 bt done_sleep
66
67 /* set mode to "u-standby mode" */
68 mov #0x10, r1
69
70 /* fall-through */
71
72do_sleep:
73 /* setup and enter selected standby mode */
74 mov.l 5f, r4
75 mov.l r1, @r4
76 sleep
77
78done_sleep:
79 /* reset standby mode to sleep mode */
80 mov.l 5f, r4
81 mov #0x00, r1
82 mov.l r1, @r4
83
84 tst #SUSP_SH_SF, r0
85 bt skip_restore_sf
86
87 /* SDRAM: set auto-refresh mode */
88 mov.l 1f, r4
89 mov.l @r4, r2
90 mov.l 4f, r3
91 and r3, r2
92 mov.l r2, @r4
93 mov.l 6f, r4
94 mov.l 7f, r1
95 mov.l 8f, r2
96 mov.l @r4, r3
97 mov #-1, r4
98 add r4, r3
99 or r2, r3
100 mov.l r3, @r1
101skip_restore_sf:
102 rts
103 nop
104
105 .balign 4
1061: .long 0xfe400008 /* SDCR0 */
1072: .long 0x00000400
1083: .long 0xffff7fff
1094: .long 0xfffffbff
1105: .long 0xa4150020 /* STBCR */
1116: .long 0xfe40001c /* RTCOR */
1127: .long 0xfe400018 /* RTCNT */
1138: .long 0xa55a0000
114
115/* interrupt vector @ 0x600 */
116 .balign 0x400,0,0x400
117 .long 0xdeadbeef
118 .balign 0x200,0,0x200
119 /* sh7722 will end up here in sleep mode */
120 rte
121 nop
122sh_mobile_standby_end:
123
124ENTRY(sh_mobile_standby_size)
125 .long sh_mobile_standby_end - sh_mobile_standby
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 13:28:02 -0400