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-rw-r--r--arch/sh/kernel/cpu/Makefile3
-rw-r--r--arch/sh/kernel/cpu/adc.c12
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c104
-rw-r--r--arch/sh/kernel/cpu/clock.c6
-rw-r--r--arch/sh/kernel/cpu/fpu.c85
-rw-r--r--arch/sh/kernel/cpu/hwblk.c1
-rw-r--r--arch/sh/kernel/cpu/init.c147
-rw-r--r--arch/sh/kernel/cpu/irq/intc-sh5.c14
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c7
-rw-r--r--arch/sh/kernel/cpu/sh2/clock-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c71
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7203.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7206.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/fpu.c110
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c23
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c181
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c89
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c89
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh3.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7705.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7706.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7709.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7710.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7712.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/entry.S36
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S2
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c28
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh3.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c49
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c80
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c50
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c50
-rw-r--r--arch/sh/kernel/cpu/sh4/Makefile8
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c10
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4.c8
-rw-r--r--arch/sh/kernel/cpu/sh4/fpu.c161
-rw-r--r--arch/sh/kernel/cpu/sh4/perf_event.c253
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c14
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c25
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c49
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c91
-rw-r--r--arch/sh/kernel/cpu/sh4/sq.c25
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c29
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c21
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7770.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c184
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/perf_event.c269
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c21
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c112
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c39
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c295
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c199
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c617
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c118
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c101
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c245
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c200
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c291
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c156
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c121
-rw-r--r--arch/sh/kernel/cpu/sh4a/smp-shx3.c40
-rw-r--r--arch/sh/kernel/cpu/sh4a/ubc.c133
-rw-r--r--arch/sh/kernel/cpu/sh5/clock-sh5.c8
-rw-r--r--arch/sh/kernel/cpu/sh5/entry.S8
-rw-r--r--arch/sh/kernel/cpu/sh5/fpu.c67
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c22
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c42
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm.c118
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm_runtime.c17
-rw-r--r--arch/sh/kernel/cpu/shmobile/sleep.S461
-rw-r--r--arch/sh/kernel/cpu/ubc.S59
81 files changed, 4262 insertions, 1788 deletions
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 3d6b9312dc47..0e48bc61c272 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -15,8 +15,9 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
15 15
16# Common interfaces. 16# Common interfaces.
17 17
18obj-$(CONFIG_UBC_WAKEUP) += ubc.o
19obj-$(CONFIG_SH_ADC) += adc.o 18obj-$(CONFIG_SH_ADC) += adc.o
20obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o
20obj-$(CONFIG_SH_FPU) += fpu.o
21obj-$(CONFIG_SH_FPU_EMU) += fpu.o
21 22
22obj-y += irq/ init.o clock.o hwblk.o 23obj-y += irq/ init.o clock.o hwblk.o
diff --git a/arch/sh/kernel/cpu/adc.c b/arch/sh/kernel/cpu/adc.c
index da3d6877f93d..d307571d54b6 100644
--- a/arch/sh/kernel/cpu/adc.c
+++ b/arch/sh/kernel/cpu/adc.c
@@ -18,19 +18,19 @@ int adc_single(unsigned int channel)
18 18
19 off = (channel & 0x03) << 2; 19 off = (channel & 0x03) << 2;
20 20
21 csr = ctrl_inb(ADCSR); 21 csr = __raw_readb(ADCSR);
22 csr = channel | ADCSR_ADST | ADCSR_CKS; 22 csr = channel | ADCSR_ADST | ADCSR_CKS;
23 ctrl_outb(csr, ADCSR); 23 __raw_writeb(csr, ADCSR);
24 24
25 do { 25 do {
26 csr = ctrl_inb(ADCSR); 26 csr = __raw_readb(ADCSR);
27 } while ((csr & ADCSR_ADF) == 0); 27 } while ((csr & ADCSR_ADF) == 0);
28 28
29 csr &= ~(ADCSR_ADF | ADCSR_ADST); 29 csr &= ~(ADCSR_ADF | ADCSR_ADST);
30 ctrl_outb(csr, ADCSR); 30 __raw_writeb(csr, ADCSR);
31 31
32 return (((ctrl_inb(ADDRAH + off) << 8) | 32 return (((__raw_readb(ADDRAH + off) << 8) |
33 ctrl_inb(ADDRAL + off)) >> 6); 33 __raw_readb(ADDRAL + off)) >> 6);
34} 34}
35 35
36EXPORT_SYMBOL(adc_single); 36EXPORT_SYMBOL(adc_single);
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 6dfe2cced3fc..eed5eaff96ba 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -149,7 +149,8 @@ int __init sh_clk_div6_register(struct clk *clks, int nr)
149 149
150static unsigned long sh_clk_div4_recalc(struct clk *clk) 150static unsigned long sh_clk_div4_recalc(struct clk *clk)
151{ 151{
152 struct clk_div_mult_table *table = clk->priv; 152 struct clk_div4_table *d4t = clk->priv;
153 struct clk_div_mult_table *table = d4t->div_mult_table;
153 unsigned int idx; 154 unsigned int idx;
154 155
155 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, 156 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
@@ -160,17 +161,90 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk)
160 return clk->freq_table[idx].frequency; 161 return clk->freq_table[idx].frequency;
161} 162}
162 163
164static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
165{
166 struct clk_div4_table *d4t = clk->priv;
167 struct clk_div_mult_table *table = d4t->div_mult_table;
168 u32 value;
169 int ret;
170
171 if (!strcmp("pll_clk", parent->name))
172 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
173 else
174 value = __raw_readl(clk->enable_reg) | (1 << 7);
175
176 ret = clk_reparent(clk, parent);
177 if (ret < 0)
178 return ret;
179
180 __raw_writel(value, clk->enable_reg);
181
182 /* Rebiuld the frequency table */
183 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
184 table, &clk->arch_flags);
185
186 return 0;
187}
188
189static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
190{
191 struct clk_div4_table *d4t = clk->priv;
192 unsigned long value;
193 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
194 if (idx < 0)
195 return idx;
196
197 value = __raw_readl(clk->enable_reg);
198 value &= ~(0xf << clk->enable_bit);
199 value |= (idx << clk->enable_bit);
200 __raw_writel(value, clk->enable_reg);
201
202 if (d4t->kick)
203 d4t->kick(clk);
204
205 return 0;
206}
207
208static int sh_clk_div4_enable(struct clk *clk)
209{
210 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
211 return 0;
212}
213
214static void sh_clk_div4_disable(struct clk *clk)
215{
216 __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
217}
218
163static struct clk_ops sh_clk_div4_clk_ops = { 219static struct clk_ops sh_clk_div4_clk_ops = {
164 .recalc = sh_clk_div4_recalc, 220 .recalc = sh_clk_div4_recalc,
221 .set_rate = sh_clk_div4_set_rate,
165 .round_rate = sh_clk_div_round_rate, 222 .round_rate = sh_clk_div_round_rate,
166}; 223};
167 224
168int __init sh_clk_div4_register(struct clk *clks, int nr, 225static struct clk_ops sh_clk_div4_enable_clk_ops = {
169 struct clk_div_mult_table *table) 226 .recalc = sh_clk_div4_recalc,
227 .set_rate = sh_clk_div4_set_rate,
228 .round_rate = sh_clk_div_round_rate,
229 .enable = sh_clk_div4_enable,
230 .disable = sh_clk_div4_disable,
231};
232
233static struct clk_ops sh_clk_div4_reparent_clk_ops = {
234 .recalc = sh_clk_div4_recalc,
235 .set_rate = sh_clk_div4_set_rate,
236 .round_rate = sh_clk_div_round_rate,
237 .enable = sh_clk_div4_enable,
238 .disable = sh_clk_div4_disable,
239 .set_parent = sh_clk_div4_set_parent,
240};
241
242static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
243 struct clk_div4_table *table, struct clk_ops *ops)
170{ 244{
171 struct clk *clkp; 245 struct clk *clkp;
172 void *freq_table; 246 void *freq_table;
173 int nr_divs = table->nr_divisors; 247 int nr_divs = table->div_mult_table->nr_divisors;
174 int freq_table_size = sizeof(struct cpufreq_frequency_table); 248 int freq_table_size = sizeof(struct cpufreq_frequency_table);
175 int ret = 0; 249 int ret = 0;
176 int k; 250 int k;
@@ -185,7 +259,7 @@ int __init sh_clk_div4_register(struct clk *clks, int nr,
185 for (k = 0; !ret && (k < nr); k++) { 259 for (k = 0; !ret && (k < nr); k++) {
186 clkp = clks + k; 260 clkp = clks + k;
187 261
188 clkp->ops = &sh_clk_div4_clk_ops; 262 clkp->ops = ops;
189 clkp->id = -1; 263 clkp->id = -1;
190 clkp->priv = table; 264 clkp->priv = table;
191 265
@@ -198,6 +272,26 @@ int __init sh_clk_div4_register(struct clk *clks, int nr,
198 return ret; 272 return ret;
199} 273}
200 274
275int __init sh_clk_div4_register(struct clk *clks, int nr,
276 struct clk_div4_table *table)
277{
278 return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
279}
280
281int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
282 struct clk_div4_table *table)
283{
284 return sh_clk_div4_register_ops(clks, nr, table,
285 &sh_clk_div4_enable_clk_ops);
286}
287
288int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
289 struct clk_div4_table *table)
290{
291 return sh_clk_div4_register_ops(clks, nr, table,
292 &sh_clk_div4_reparent_clk_ops);
293}
294
201#ifdef CONFIG_SH_CLK_CPG_LEGACY 295#ifdef CONFIG_SH_CLK_CPG_LEGACY
202static struct clk master_clk = { 296static struct clk master_clk = {
203 .name = "master_clk", 297 .name = "master_clk",
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index f3a46be2ae81..e9fa1bfed53e 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -404,7 +404,7 @@ EXPORT_SYMBOL_GPL(clk_round_rate);
404 * If an entry has a device ID, it must match 404 * If an entry has a device ID, it must match
405 * If an entry has a connection ID, it must match 405 * If an entry has a connection ID, it must match
406 * Then we take the most specific entry - with the following 406 * Then we take the most specific entry - with the following
407 * order of precidence: dev+con > dev only > con only. 407 * order of precedence: dev+con > dev only > con only.
408 */ 408 */
409static struct clk *clk_find(const char *dev_id, const char *con_id) 409static struct clk *clk_find(const char *dev_id, const char *con_id)
410{ 410{
@@ -598,7 +598,7 @@ static struct dentry *clk_debugfs_root;
598static int clk_debugfs_register_one(struct clk *c) 598static int clk_debugfs_register_one(struct clk *c)
599{ 599{
600 int err; 600 int err;
601 struct dentry *d, *child; 601 struct dentry *d, *child, *child_tmp;
602 struct clk *pa = c->parent; 602 struct clk *pa = c->parent;
603 char s[255]; 603 char s[255];
604 char *p = s; 604 char *p = s;
@@ -630,7 +630,7 @@ static int clk_debugfs_register_one(struct clk *c)
630 630
631err_out: 631err_out:
632 d = c->dentry; 632 d = c->dentry;
633 list_for_each_entry(child, &d->d_subdirs, d_u.d_child) 633 list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
634 debugfs_remove(child); 634 debugfs_remove(child);
635 debugfs_remove(c->dentry); 635 debugfs_remove(c->dentry);
636 return err; 636 return err;
diff --git a/arch/sh/kernel/cpu/fpu.c b/arch/sh/kernel/cpu/fpu.c
new file mode 100644
index 000000000000..7f1b70cace35
--- /dev/null
+++ b/arch/sh/kernel/cpu/fpu.c
@@ -0,0 +1,85 @@
1#include <linux/sched.h>
2#include <linux/slab.h>
3#include <asm/processor.h>
4#include <asm/fpu.h>
5
6int init_fpu(struct task_struct *tsk)
7{
8 if (tsk_used_math(tsk)) {
9 if ((boot_cpu_data.flags & CPU_HAS_FPU) && tsk == current)
10 unlazy_fpu(tsk, task_pt_regs(tsk));
11 return 0;
12 }
13
14 /*
15 * Memory allocation at the first usage of the FPU and other state.
16 */
17 if (!tsk->thread.xstate) {
18 tsk->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
19 GFP_KERNEL);
20 if (!tsk->thread.xstate)
21 return -ENOMEM;
22 }
23
24 if (boot_cpu_data.flags & CPU_HAS_FPU) {
25 struct sh_fpu_hard_struct *fp = &tsk->thread.xstate->hardfpu;
26 memset(fp, 0, xstate_size);
27 fp->fpscr = FPSCR_INIT;
28 } else {
29 struct sh_fpu_soft_struct *fp = &tsk->thread.xstate->softfpu;
30 memset(fp, 0, xstate_size);
31 fp->fpscr = FPSCR_INIT;
32 }
33
34 set_stopped_child_used_math(tsk);
35 return 0;
36}
37
38#ifdef CONFIG_SH_FPU
39void __fpu_state_restore(void)
40{
41 struct task_struct *tsk = current;
42
43 restore_fpu(tsk);
44
45 task_thread_info(tsk)->status |= TS_USEDFPU;
46 tsk->fpu_counter++;
47}
48
49void fpu_state_restore(struct pt_regs *regs)
50{
51 struct task_struct *tsk = current;
52
53 if (unlikely(!user_mode(regs))) {
54 printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
55 BUG();
56 return;
57 }
58
59 if (!tsk_used_math(tsk)) {
60 local_irq_enable();
61 /*
62 * does a slab alloc which can sleep
63 */
64 if (init_fpu(tsk)) {
65 /*
66 * ran out of memory!
67 */
68 do_group_exit(SIGKILL);
69 return;
70 }
71 local_irq_disable();
72 }
73
74 grab_fpu(regs);
75
76 __fpu_state_restore();
77}
78
79BUILD_TRAP_HANDLER(fpu_state_restore)
80{
81 TRAP_HANDLER_DECL;
82
83 fpu_state_restore(regs);
84}
85#endif /* CONFIG_SH_FPU */
diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c
index c0ad7d46e784..67a1e811cfe8 100644
--- a/arch/sh/kernel/cpu/hwblk.c
+++ b/arch/sh/kernel/cpu/hwblk.c
@@ -1,6 +1,5 @@
1#include <linux/clk.h> 1#include <linux/clk.h>
2#include <linux/compiler.h> 2#include <linux/compiler.h>
3#include <linux/slab.h>
4#include <linux/io.h> 3#include <linux/io.h>
5#include <linux/spinlock.h> 4#include <linux/spinlock.h>
6#include <asm/suspend.h> 5#include <asm/suspend.h>
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index e932ebef4738..c736422344eb 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -24,22 +24,32 @@
24#include <asm/elf.h> 24#include <asm/elf.h>
25#include <asm/io.h> 25#include <asm/io.h>
26#include <asm/smp.h> 26#include <asm/smp.h>
27#ifdef CONFIG_SUPERH32 27#include <asm/sh_bios.h>
28#include <asm/ubc.h> 28
29#ifdef CONFIG_SH_FPU
30#define cpu_has_fpu 1
31#else
32#define cpu_has_fpu 0
33#endif
34
35#ifdef CONFIG_SH_DSP
36#define cpu_has_dsp 1
37#else
38#define cpu_has_dsp 0
29#endif 39#endif
30 40
31/* 41/*
32 * Generic wrapper for command line arguments to disable on-chip 42 * Generic wrapper for command line arguments to disable on-chip
33 * peripherals (nofpu, nodsp, and so forth). 43 * peripherals (nofpu, nodsp, and so forth).
34 */ 44 */
35#define onchip_setup(x) \ 45#define onchip_setup(x) \
36static int x##_disabled __initdata = 0; \ 46static int x##_disabled __initdata = !cpu_has_##x; \
37 \ 47 \
38static int __init x##_setup(char *opts) \ 48static int __init x##_setup(char *opts) \
39{ \ 49{ \
40 x##_disabled = 1; \ 50 x##_disabled = 1; \
41 return 1; \ 51 return 1; \
42} \ 52} \
43__setup("no" __stringify(x), x##_setup); 53__setup("no" __stringify(x), x##_setup);
44 54
45onchip_setup(fpu); 55onchip_setup(fpu);
@@ -52,10 +62,10 @@ onchip_setup(dsp);
52static void __init speculative_execution_init(void) 62static void __init speculative_execution_init(void)
53{ 63{
54 /* Clear RABD */ 64 /* Clear RABD */
55 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 65 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
56 66
57 /* Flush the update */ 67 /* Flush the update */
58 (void)ctrl_inl(CPUOPM); 68 (void)__raw_readl(CPUOPM);
59 ctrl_barrier(); 69 ctrl_barrier();
60} 70}
61#else 71#else
@@ -75,16 +85,11 @@ static void __init expmask_init(void)
75 /* 85 /*
76 * Future proofing. 86 * Future proofing.
77 * 87 *
78 * Disable support for slottable sleep instruction 88 * Disable support for slottable sleep instruction, non-nop
79 * and non-nop instructions in the rte delay slot. 89 * instructions in the rte delay slot, and associative writes to
90 * the memory-mapped cache array.
80 */ 91 */
81 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP); 92 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW);
82
83 /*
84 * Enable associative writes to the memory-mapped cache array
85 * until the cache flush ops have been rewritten.
86 */
87 expmask |= EXPMASK_MMCAW;
88 93
89 __raw_writel(expmask, EXPMASK); 94 __raw_writel(expmask, EXPMASK);
90 ctrl_barrier(); 95 ctrl_barrier();
@@ -94,7 +99,7 @@ static void __init expmask_init(void)
94#endif 99#endif
95 100
96/* 2nd-level cache init */ 101/* 2nd-level cache init */
97void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) 102void __attribute__ ((weak)) l2_cache_init(void)
98{ 103{
99} 104}
100 105
@@ -102,12 +107,12 @@ void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
102 * Generic first-level cache init 107 * Generic first-level cache init
103 */ 108 */
104#ifdef CONFIG_SUPERH32 109#ifdef CONFIG_SUPERH32
105static void __uses_jump_to_uncached cache_init(void) 110static void cache_init(void)
106{ 111{
107 unsigned long ccr, flags; 112 unsigned long ccr, flags;
108 113
109 jump_to_uncached(); 114 jump_to_uncached();
110 ccr = ctrl_inl(CCR); 115 ccr = __raw_readl(CCR);
111 116
112 /* 117 /*
113 * At this point we don't know whether the cache is enabled or not - a 118 * At this point we don't know whether the cache is enabled or not - a
@@ -151,7 +156,7 @@ static void __uses_jump_to_uncached cache_init(void)
151 for (addr = addrstart; 156 for (addr = addrstart;
152 addr < addrstart + waysize; 157 addr < addrstart + waysize;
153 addr += current_cpu_data.dcache.linesz) 158 addr += current_cpu_data.dcache.linesz)
154 ctrl_outl(0, addr); 159 __raw_writel(0, addr);
155 160
156 addrstart += current_cpu_data.dcache.way_incr; 161 addrstart += current_cpu_data.dcache.way_incr;
157 } while (--ways); 162 } while (--ways);
@@ -184,7 +189,7 @@ static void __uses_jump_to_uncached cache_init(void)
184 189
185 l2_cache_init(); 190 l2_cache_init();
186 191
187 ctrl_outl(flags, CCR); 192 __raw_writel(flags, CCR);
188 back_to_cached(); 193 back_to_cached();
189} 194}
190#else 195#else
@@ -212,6 +217,18 @@ static void detect_cache_shape(void)
212 l2_cache_shape = -1; /* No S-cache */ 217 l2_cache_shape = -1; /* No S-cache */
213} 218}
214 219
220static void __init fpu_init(void)
221{
222 /* Disable the FPU */
223 if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) {
224 printk("FPU Disabled\n");
225 current_cpu_data.flags &= ~CPU_HAS_FPU;
226 }
227
228 disable_fpu();
229 clear_used_math();
230}
231
215#ifdef CONFIG_SH_DSP 232#ifdef CONFIG_SH_DSP
216static void __init release_dsp(void) 233static void __init release_dsp(void)
217{ 234{
@@ -249,28 +266,35 @@ static void __init dsp_init(void)
249 if (sr & SR_DSP) 266 if (sr & SR_DSP)
250 current_cpu_data.flags |= CPU_HAS_DSP; 267 current_cpu_data.flags |= CPU_HAS_DSP;
251 268
269 /* Disable the DSP */
270 if (dsp_disabled && (current_cpu_data.flags & CPU_HAS_DSP)) {
271 printk("DSP Disabled\n");
272 current_cpu_data.flags &= ~CPU_HAS_DSP;
273 }
274
252 /* Now that we've determined the DSP status, clear the DSP bit. */ 275 /* Now that we've determined the DSP status, clear the DSP bit. */
253 release_dsp(); 276 release_dsp();
254} 277}
278#else
279static inline void __init dsp_init(void) { }
255#endif /* CONFIG_SH_DSP */ 280#endif /* CONFIG_SH_DSP */
256 281
257/** 282/**
258 * sh_cpu_init 283 * sh_cpu_init
259 * 284 *
260 * This is our initial entry point for each CPU, and is invoked on the boot 285 * This is our initial entry point for each CPU, and is invoked on the
261 * CPU prior to calling start_kernel(). For SMP, a combination of this and 286 * boot CPU prior to calling start_kernel(). For SMP, a combination of
262 * start_secondary() will bring up each processor to a ready state prior 287 * this and start_secondary() will bring up each processor to a ready
263 * to hand forking the idle loop. 288 * state prior to hand forking the idle loop.
264 * 289 *
265 * We do all of the basic processor init here, including setting up the 290 * We do all of the basic processor init here, including setting up
266 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is 291 * the caches, FPU, DSP, etc. By the time start_kernel() is hit (and
267 * hit (and subsequently platform_setup()) things like determining the 292 * subsequently platform_setup()) things like determining the CPU
268 * CPU subtype and initial configuration will all be done. 293 * subtype and initial configuration will all be done.
269 * 294 *
270 * Each processor family is still responsible for doing its own probing 295 * Each processor family is still responsible for doing its own probing
271 * and cache configuration in detect_cpu_and_cache_system(). 296 * and cache configuration in detect_cpu_and_cache_system().
272 */ 297 */
273
274asmlinkage void __init sh_cpu_init(void) 298asmlinkage void __init sh_cpu_init(void)
275{ 299{
276 current_thread_info()->cpu = hard_smp_processor_id(); 300 current_thread_info()->cpu = hard_smp_processor_id();
@@ -307,18 +331,8 @@ asmlinkage void __init sh_cpu_init(void)
307 detect_cache_shape(); 331 detect_cache_shape();
308 } 332 }
309 333
310 /* Disable the FPU */ 334 fpu_init();
311 if (fpu_disabled) { 335 dsp_init();
312 printk("FPU Disabled\n");
313 current_cpu_data.flags &= ~CPU_HAS_FPU;
314 disable_fpu();
315 }
316
317 /* FPU initialization */
318 if ((current_cpu_data.flags & CPU_HAS_FPU)) {
319 clear_thread_flag(TIF_USEDFPU);
320 clear_used_math();
321 }
322 336
323 /* 337 /*
324 * Initialize the per-CPU ASID cache very early, since the 338 * Initialize the per-CPU ASID cache very early, since the
@@ -326,29 +340,24 @@ asmlinkage void __init sh_cpu_init(void)
326 */ 340 */
327 current_cpu_data.asid_cache = NO_CONTEXT; 341 current_cpu_data.asid_cache = NO_CONTEXT;
328 342
329#ifdef CONFIG_SH_DSP 343 speculative_execution_init();
330 /* Probe for DSP */ 344 expmask_init();
331 dsp_init();
332 345
333 /* Disable the DSP */ 346 /* Do the rest of the boot processor setup */
334 if (dsp_disabled) { 347 if (raw_smp_processor_id() == 0) {
335 printk("DSP Disabled\n"); 348 /* Save off the BIOS VBR, if there is one */
336 current_cpu_data.flags &= ~CPU_HAS_DSP; 349 sh_bios_vbr_init();
337 release_dsp();
338 }
339#endif
340 350
341 /* 351 /*
342 * Some brain-damaged loaders decided it would be a good idea to put 352 * Setup VBR for boot CPU. Secondary CPUs do this through
343 * the UBC to sleep. This causes some issues when it comes to things 353 * start_secondary().
344 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. 354 */
345 * we wake it up and hope that all is well. 355 per_cpu_trap_init();
346 */
347#ifdef CONFIG_SUPERH32
348 if (raw_smp_processor_id() == 0)
349 ubc_wakeup();
350#endif
351 356
352 speculative_execution_init(); 357 /*
353 expmask_init(); 358 * Boot processor to setup the FP and extended state
359 * context info.
360 */
361 init_thread_xstate();
362 }
354} 363}
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 06e7e2959b54..96a239583948 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -123,7 +123,7 @@ static void enable_intc_irq(unsigned int irq)
123 bitmask = 1 << (irq - 32); 123 bitmask = 1 << (irq - 32);
124 } 124 }
125 125
126 ctrl_outl(bitmask, reg); 126 __raw_writel(bitmask, reg);
127} 127}
128 128
129static void disable_intc_irq(unsigned int irq) 129static void disable_intc_irq(unsigned int irq)
@@ -139,7 +139,7 @@ static void disable_intc_irq(unsigned int irq)
139 bitmask = 1 << (irq - 32); 139 bitmask = 1 << (irq - 32);
140 } 140 }
141 141
142 ctrl_outl(bitmask, reg); 142 __raw_writel(bitmask, reg);
143} 143}
144 144
145static void mask_and_ack_intc(unsigned int irq) 145static void mask_and_ack_intc(unsigned int irq)
@@ -170,11 +170,11 @@ void __init plat_irq_setup(void)
170 170
171 171
172 /* Disable all interrupts and set all priorities to 0 to avoid trouble */ 172 /* Disable all interrupts and set all priorities to 0 to avoid trouble */
173 ctrl_outl(-1, INTC_INTDSB_0); 173 __raw_writel(-1, INTC_INTDSB_0);
174 ctrl_outl(-1, INTC_INTDSB_1); 174 __raw_writel(-1, INTC_INTDSB_1);
175 175
176 for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8) 176 for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
177 ctrl_outl( NO_PRIORITY, reg); 177 __raw_writel( NO_PRIORITY, reg);
178 178
179 179
180#ifdef CONFIG_SH_CAYMAN 180#ifdef CONFIG_SH_CAYMAN
@@ -199,7 +199,7 @@ void __init plat_irq_setup(void)
199 reg = INTC_ICR_SET; 199 reg = INTC_ICR_SET;
200 i = IRQ_IRL0; 200 i = IRQ_IRL0;
201 } 201 }
202 ctrl_outl(INTC_ICR_IRLM, reg); 202 __raw_writel(INTC_ICR_IRLM, reg);
203 203
204 /* Set interrupt priorities according to platform description */ 204 /* Set interrupt priorities according to platform description */
205 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { 205 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
@@ -207,7 +207,7 @@ void __init plat_irq_setup(void)
207 ((i % INTC_INTPRI_PPREG) * 4); 207 ((i % INTC_INTPRI_PPREG) * 4);
208 if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) { 208 if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
209 /* Upon the 7th, set Priority Register */ 209 /* Upon the 7th, set Priority Register */
210 ctrl_outl(data, reg); 210 __raw_writel(data, reg);
211 data = 0; 211 data = 0;
212 reg += 8; 212 reg += 8;
213 } 213 }
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index c1508a90fc6a..9282d965a1b6 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -17,16 +17,17 @@
17 * for more details. 17 * for more details.
18 */ 18 */
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
20#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/kernel.h>
21#include <linux/module.h> 24#include <linux/module.h>
22#include <linux/io.h>
23#include <linux/interrupt.h>
24#include <linux/topology.h> 25#include <linux/topology.h>
25 26
26static inline struct ipr_desc *get_ipr_desc(unsigned int irq) 27static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
27{ 28{
28 struct irq_chip *chip = get_irq_chip(irq); 29 struct irq_chip *chip = get_irq_chip(irq);
29 return (void *)((char *)chip - offsetof(struct ipr_desc, chip)); 30 return container_of(chip, struct ipr_desc, chip);
30} 31}
31 32
32static void disable_ipr_irq(unsigned int irq) 33static void disable_ipr_irq(unsigned int irq)
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 4fe863170e31..0c9f24d7a02f 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -31,7 +31,7 @@ static const int pfc_divisors[] = {1,2,0,4};
31 31
32static void master_clk_init(struct clk *clk) 32static void master_clk_init(struct clk *clk)
33{ 33{
34 clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; 34 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
35} 35}
36 36
37static struct clk_ops sh7619_master_clk_ops = { 37static struct clk_ops sh7619_master_clk_ops = {
@@ -40,7 +40,7 @@ static struct clk_ops sh7619_master_clk_ops = {
40 40
41static unsigned long module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inw(FREQCR) & 0x0007); 43 int idx = (__raw_readw(FREQCR) & 0x0007);
44 return clk->parent->rate / pfc_divisors[idx]; 44 return clk->parent->rate / pfc_divisors[idx];
45} 45}
46 46
@@ -50,7 +50,7 @@ static struct clk_ops sh7619_module_clk_ops = {
50 50
51static unsigned long bus_clk_recalc(struct clk *clk) 51static unsigned long bus_clk_recalc(struct clk *clk)
52{ 52{
53 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; 53 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
54} 54}
55 55
56static struct clk_ops sh7619_bus_clk_ops = { 56static struct clk_ops sh7619_bus_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 8555c05e8667..114c7cee7184 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -59,32 +59,48 @@ static struct intc_prio_reg prio_registers[] __initdata = {
59static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, 59static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
60 NULL, prio_registers, NULL); 60 NULL, prio_registers, NULL);
61 61
62static struct plat_sci_port sci_platform_data[] = { 62static struct plat_sci_port scif0_platform_data = {
63 { 63 .mapbase = 0xf8400000,
64 .mapbase = 0xf8400000, 64 .flags = UPF_BOOT_AUTOCONF,
65 .flags = UPF_BOOT_AUTOCONF, 65 .type = PORT_SCIF,
66 .type = PORT_SCIF, 66 .irqs = { 88, 88, 88, 88 },
67 .irqs = { 88, 88, 88, 88 }, 67};
68 }, { 68
69 .mapbase = 0xf8410000, 69static struct platform_device scif0_device = {
70 .flags = UPF_BOOT_AUTOCONF, 70 .name = "sh-sci",
71 .type = PORT_SCIF, 71 .id = 0,
72 .irqs = { 92, 92, 92, 92 }, 72 .dev = {
73 }, { 73 .platform_data = &scif0_platform_data,
74 .mapbase = 0xf8420000, 74 },
75 .flags = UPF_BOOT_AUTOCONF, 75};
76 .type = PORT_SCIF, 76
77 .irqs = { 96, 96, 96, 96 }, 77static struct plat_sci_port scif1_platform_data = {
78 }, { 78 .mapbase = 0xf8410000,
79 .flags = 0, 79 .flags = UPF_BOOT_AUTOCONF,
80 } 80 .type = PORT_SCIF,
81}; 81 .irqs = { 92, 92, 92, 92 },
82 82};
83static struct platform_device sci_device = { 83
84static struct platform_device scif1_device = {
85 .name = "sh-sci",
86 .id = 1,
87 .dev = {
88 .platform_data = &scif1_platform_data,
89 },
90};
91
92static struct plat_sci_port scif2_platform_data = {
93 .mapbase = 0xf8420000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .type = PORT_SCIF,
96 .irqs = { 96, 96, 96, 96 },
97};
98
99static struct platform_device scif2_device = {
84 .name = "sh-sci", 100 .name = "sh-sci",
85 .id = -1, 101 .id = 2,
86 .dev = { 102 .dev = {
87 .platform_data = sci_platform_data, 103 .platform_data = &scif2_platform_data,
88 }, 104 },
89}; 105};
90 106
@@ -176,7 +192,9 @@ static struct platform_device cmt1_device = {
176}; 192};
177 193
178static struct platform_device *sh7619_devices[] __initdata = { 194static struct platform_device *sh7619_devices[] __initdata = {
179 &sci_device, 195 &scif0_device,
196 &scif1_device,
197 &scif2_device,
180 &eth_device, 198 &eth_device,
181 &cmt0_device, 199 &cmt0_device,
182 &cmt1_device, 200 &cmt1_device,
@@ -195,6 +213,9 @@ void __init plat_irq_setup(void)
195} 213}
196 214
197static struct platform_device *sh7619_early_devices[] __initdata = { 215static struct platform_device *sh7619_early_devices[] __initdata = {
216 &scif0_device,
217 &scif1_device,
218 &scif2_device,
198 &cmt0_device, 219 &cmt0_device,
199 &cmt1_device, 220 &cmt1_device,
200}; 221};
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 7814c76159a7..b26264dc2aef 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -34,7 +34,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
34 34
35static void master_clk_init(struct clk *clk) 35static void master_clk_init(struct clk *clk)
36{ 36{
37 return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 37 return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 38}
39 39
40static struct clk_ops sh7201_master_clk_ops = { 40static struct clk_ops sh7201_master_clk_ops = {
@@ -43,7 +43,7 @@ static struct clk_ops sh7201_master_clk_ops = {
43 43
44static unsigned long module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (__raw_readw(FREQCR) & 0x0007);
47 return clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
@@ -53,7 +53,7 @@ static struct clk_ops sh7201_module_clk_ops = {
53 53
54static unsigned long bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 int idx = (ctrl_inw(FREQCR) & 0x0007); 56 int idx = (__raw_readw(FREQCR) & 0x0007);
57 return clk->parent->rate / pfc_divisors[idx]; 57 return clk->parent->rate / pfc_divisors[idx];
58} 58}
59 59
@@ -63,7 +63,7 @@ static struct clk_ops sh7201_bus_clk_ops = {
63 63
64static unsigned long cpu_clk_recalc(struct clk *clk) 64static unsigned long cpu_clk_recalc(struct clk *clk)
65{ 65{
66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); 66 int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
67 return clk->parent->rate / ifc_divisors[idx]; 67 return clk->parent->rate / ifc_divisors[idx];
68} 68}
69 69
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 940986965102..7e75d8f79502 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -39,7 +39,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
39 39
40static void master_clk_init(struct clk *clk) 40static void master_clk_init(struct clk *clk)
41{ 41{
42 clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ; 42 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ;
43} 43}
44 44
45static struct clk_ops sh7203_master_clk_ops = { 45static struct clk_ops sh7203_master_clk_ops = {
@@ -48,7 +48,7 @@ static struct clk_ops sh7203_master_clk_ops = {
48 48
49static unsigned long module_clk_recalc(struct clk *clk) 49static unsigned long module_clk_recalc(struct clk *clk)
50{ 50{
51 int idx = (ctrl_inw(FREQCR) & 0x0007); 51 int idx = (__raw_readw(FREQCR) & 0x0007);
52 return clk->parent->rate / pfc_divisors[idx]; 52 return clk->parent->rate / pfc_divisors[idx];
53} 53}
54 54
@@ -58,7 +58,7 @@ static struct clk_ops sh7203_module_clk_ops = {
58 58
59static unsigned long bus_clk_recalc(struct clk *clk) 59static unsigned long bus_clk_recalc(struct clk *clk)
60{ 60{
61 int idx = (ctrl_inw(FREQCR) & 0x0007); 61 int idx = (__raw_readw(FREQCR) & 0x0007);
62 return clk->parent->rate / pfc_divisors[idx-2]; 62 return clk->parent->rate / pfc_divisors[idx-2];
63} 63}
64 64
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index c2268bdeceeb..b27a5e2687ab 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -34,7 +34,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
34 34
35static void master_clk_init(struct clk *clk) 35static void master_clk_init(struct clk *clk)
36{ 36{
37 clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 37 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 38}
39 39
40static struct clk_ops sh7206_master_clk_ops = { 40static struct clk_ops sh7206_master_clk_ops = {
@@ -43,7 +43,7 @@ static struct clk_ops sh7206_master_clk_ops = {
43 43
44static unsigned long module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (__raw_readw(FREQCR) & 0x0007);
47 return clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
@@ -53,7 +53,7 @@ static struct clk_ops sh7206_module_clk_ops = {
53 53
54static unsigned long bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 56 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
57} 57}
58 58
59static struct clk_ops sh7206_bus_clk_ops = { 59static struct clk_ops sh7206_bus_clk_ops = {
@@ -62,7 +62,7 @@ static struct clk_ops sh7206_bus_clk_ops = {
62 62
63static unsigned long cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = (ctrl_inw(FREQCR) & 0x0007); 65 int idx = (__raw_readw(FREQCR) & 0x0007);
66 return clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
diff --git a/arch/sh/kernel/cpu/sh2a/fpu.c b/arch/sh/kernel/cpu/sh2a/fpu.c
index 6df2fb98eb30..488d24e0cdf0 100644
--- a/arch/sh/kernel/cpu/sh2a/fpu.c
+++ b/arch/sh/kernel/cpu/sh2a/fpu.c
@@ -25,14 +25,11 @@
25 25
26/* 26/*
27 * Save FPU registers onto task structure. 27 * Save FPU registers onto task structure.
28 * Assume called with FPU enabled (SR.FD=0).
29 */ 28 */
30void 29void save_fpu(struct task_struct *tsk)
31save_fpu(struct task_struct *tsk, struct pt_regs *regs)
32{ 30{
33 unsigned long dummy; 31 unsigned long dummy;
34 32
35 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
36 enable_fpu(); 33 enable_fpu();
37 asm volatile("sts.l fpul, @-%0\n\t" 34 asm volatile("sts.l fpul, @-%0\n\t"
38 "sts.l fpscr, @-%0\n\t" 35 "sts.l fpscr, @-%0\n\t"
@@ -54,17 +51,15 @@ save_fpu(struct task_struct *tsk, struct pt_regs *regs)
54 "fmov.s fr0, @-%0\n\t" 51 "fmov.s fr0, @-%0\n\t"
55 "lds %3, fpscr\n\t" 52 "lds %3, fpscr\n\t"
56 : "=r" (dummy) 53 : "=r" (dummy)
57 : "0" ((char *)(&tsk->thread.fpu.hard.status)), 54 : "0" ((char *)(&tsk->thread.xstate->hardfpu.status)),
58 "r" (FPSCR_RCHG), 55 "r" (FPSCR_RCHG),
59 "r" (FPSCR_INIT) 56 "r" (FPSCR_INIT)
60 : "memory"); 57 : "memory");
61 58
62 disable_fpu(); 59 disable_fpu();
63 release_fpu(regs);
64} 60}
65 61
66static void 62void restore_fpu(struct task_struct *tsk)
67restore_fpu(struct task_struct *tsk)
68{ 63{
69 unsigned long dummy; 64 unsigned long dummy;
70 65
@@ -88,45 +83,12 @@ restore_fpu(struct task_struct *tsk)
88 "lds.l @%0+, fpscr\n\t" 83 "lds.l @%0+, fpscr\n\t"
89 "lds.l @%0+, fpul\n\t" 84 "lds.l @%0+, fpul\n\t"
90 : "=r" (dummy) 85 : "=r" (dummy)
91 : "0" (&tsk->thread.fpu), "r" (FPSCR_RCHG) 86 : "0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
92 : "memory"); 87 : "memory");
93 disable_fpu(); 88 disable_fpu();
94} 89}
95 90
96/* 91/*
97 * Load the FPU with signalling NANS. This bit pattern we're using
98 * has the property that no matter wether considered as single or as
99 * double precission represents signaling NANS.
100 */
101
102static void
103fpu_init(void)
104{
105 enable_fpu();
106 asm volatile("lds %0, fpul\n\t"
107 "fsts fpul, fr0\n\t"
108 "fsts fpul, fr1\n\t"
109 "fsts fpul, fr2\n\t"
110 "fsts fpul, fr3\n\t"
111 "fsts fpul, fr4\n\t"
112 "fsts fpul, fr5\n\t"
113 "fsts fpul, fr6\n\t"
114 "fsts fpul, fr7\n\t"
115 "fsts fpul, fr8\n\t"
116 "fsts fpul, fr9\n\t"
117 "fsts fpul, fr10\n\t"
118 "fsts fpul, fr11\n\t"
119 "fsts fpul, fr12\n\t"
120 "fsts fpul, fr13\n\t"
121 "fsts fpul, fr14\n\t"
122 "fsts fpul, fr15\n\t"
123 "lds %2, fpscr\n\t"
124 : /* no output */
125 : "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
126 disable_fpu();
127}
128
129/*
130 * Emulate arithmetic ops on denormalized number for some FPU insns. 92 * Emulate arithmetic ops on denormalized number for some FPU insns.
131 */ 93 */
132 94
@@ -493,9 +455,9 @@ ieee_fpe_handler (struct pt_regs *regs)
493 if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */ 455 if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
494 struct task_struct *tsk = current; 456 struct task_struct *tsk = current;
495 457
496 if ((tsk->thread.fpu.hard.fpscr & FPSCR_FPU_ERROR)) { 458 if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_FPU_ERROR)) {
497 /* FPU error */ 459 /* FPU error */
498 denormal_to_double (&tsk->thread.fpu.hard, 460 denormal_to_double (&tsk->thread.xstate->hardfpu,
499 (finsn >> 8) & 0xf); 461 (finsn >> 8) & 0xf);
500 } else 462 } else
501 return 0; 463 return 0;
@@ -510,9 +472,9 @@ ieee_fpe_handler (struct pt_regs *regs)
510 472
511 n = (finsn >> 8) & 0xf; 473 n = (finsn >> 8) & 0xf;
512 m = (finsn >> 4) & 0xf; 474 m = (finsn >> 4) & 0xf;
513 hx = tsk->thread.fpu.hard.fp_regs[n]; 475 hx = tsk->thread.xstate->hardfpu.fp_regs[n];
514 hy = tsk->thread.fpu.hard.fp_regs[m]; 476 hy = tsk->thread.xstate->hardfpu.fp_regs[m];
515 fpscr = tsk->thread.fpu.hard.fpscr; 477 fpscr = tsk->thread.xstate->hardfpu.fpscr;
516 prec = fpscr & (1 << 19); 478 prec = fpscr & (1 << 19);
517 479
518 if ((fpscr & FPSCR_FPU_ERROR) 480 if ((fpscr & FPSCR_FPU_ERROR)
@@ -522,15 +484,15 @@ ieee_fpe_handler (struct pt_regs *regs)
522 484
523 /* FPU error because of denormal */ 485 /* FPU error because of denormal */
524 llx = ((long long) hx << 32) 486 llx = ((long long) hx << 32)
525 | tsk->thread.fpu.hard.fp_regs[n+1]; 487 | tsk->thread.xstate->hardfpu.fp_regs[n+1];
526 lly = ((long long) hy << 32) 488 lly = ((long long) hy << 32)
527 | tsk->thread.fpu.hard.fp_regs[m+1]; 489 | tsk->thread.xstate->hardfpu.fp_regs[m+1];
528 if ((hx & 0x7fffffff) >= 0x00100000) 490 if ((hx & 0x7fffffff) >= 0x00100000)
529 llx = denormal_muld(lly, llx); 491 llx = denormal_muld(lly, llx);
530 else 492 else
531 llx = denormal_muld(llx, lly); 493 llx = denormal_muld(llx, lly);
532 tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; 494 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
533 tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff; 495 tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
534 } else if ((fpscr & FPSCR_FPU_ERROR) 496 } else if ((fpscr & FPSCR_FPU_ERROR)
535 && (!prec && ((hx & 0x7fffffff) < 0x00800000 497 && (!prec && ((hx & 0x7fffffff) < 0x00800000
536 || (hy & 0x7fffffff) < 0x00800000))) { 498 || (hy & 0x7fffffff) < 0x00800000))) {
@@ -539,7 +501,7 @@ ieee_fpe_handler (struct pt_regs *regs)
539 hx = denormal_mulf(hy, hx); 501 hx = denormal_mulf(hy, hx);
540 else 502 else
541 hx = denormal_mulf(hx, hy); 503 hx = denormal_mulf(hx, hy);
542 tsk->thread.fpu.hard.fp_regs[n] = hx; 504 tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
543 } else 505 } else
544 return 0; 506 return 0;
545 507
@@ -553,9 +515,9 @@ ieee_fpe_handler (struct pt_regs *regs)
553 515
554 n = (finsn >> 8) & 0xf; 516 n = (finsn >> 8) & 0xf;
555 m = (finsn >> 4) & 0xf; 517 m = (finsn >> 4) & 0xf;
556 hx = tsk->thread.fpu.hard.fp_regs[n]; 518 hx = tsk->thread.xstate->hardfpu.fp_regs[n];
557 hy = tsk->thread.fpu.hard.fp_regs[m]; 519 hy = tsk->thread.xstate->hardfpu.fp_regs[m];
558 fpscr = tsk->thread.fpu.hard.fpscr; 520 fpscr = tsk->thread.xstate->hardfpu.fpscr;
559 prec = fpscr & (1 << 19); 521 prec = fpscr & (1 << 19);
560 522
561 if ((fpscr & FPSCR_FPU_ERROR) 523 if ((fpscr & FPSCR_FPU_ERROR)
@@ -565,15 +527,15 @@ ieee_fpe_handler (struct pt_regs *regs)
565 527
566 /* FPU error because of denormal */ 528 /* FPU error because of denormal */
567 llx = ((long long) hx << 32) 529 llx = ((long long) hx << 32)
568 | tsk->thread.fpu.hard.fp_regs[n+1]; 530 | tsk->thread.xstate->hardfpu.fp_regs[n+1];
569 lly = ((long long) hy << 32) 531 lly = ((long long) hy << 32)
570 | tsk->thread.fpu.hard.fp_regs[m+1]; 532 | tsk->thread.xstate->hardfpu.fp_regs[m+1];
571 if ((finsn & 0xf00f) == 0xf000) 533 if ((finsn & 0xf00f) == 0xf000)
572 llx = denormal_addd(llx, lly); 534 llx = denormal_addd(llx, lly);
573 else 535 else
574 llx = denormal_addd(llx, lly ^ (1LL << 63)); 536 llx = denormal_addd(llx, lly ^ (1LL << 63));
575 tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; 537 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
576 tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff; 538 tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
577 } else if ((fpscr & FPSCR_FPU_ERROR) 539 } else if ((fpscr & FPSCR_FPU_ERROR)
578 && (!prec && ((hx & 0x7fffffff) < 0x00800000 540 && (!prec && ((hx & 0x7fffffff) < 0x00800000
579 || (hy & 0x7fffffff) < 0x00800000))) { 541 || (hy & 0x7fffffff) < 0x00800000))) {
@@ -582,7 +544,7 @@ ieee_fpe_handler (struct pt_regs *regs)
582 hx = denormal_addf(hx, hy); 544 hx = denormal_addf(hx, hy);
583 else 545 else
584 hx = denormal_addf(hx, hy ^ 0x80000000); 546 hx = denormal_addf(hx, hy ^ 0x80000000);
585 tsk->thread.fpu.hard.fp_regs[n] = hx; 547 tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
586 } else 548 } else
587 return 0; 549 return 0;
588 550
@@ -598,37 +560,15 @@ BUILD_TRAP_HANDLER(fpu_error)
598 struct task_struct *tsk = current; 560 struct task_struct *tsk = current;
599 TRAP_HANDLER_DECL; 561 TRAP_HANDLER_DECL;
600 562
601 save_fpu(tsk, regs); 563 __unlazy_fpu(tsk, regs);
602 if (ieee_fpe_handler(regs)) { 564 if (ieee_fpe_handler(regs)) {
603 tsk->thread.fpu.hard.fpscr &= 565 tsk->thread.xstate->hardfpu.fpscr &=
604 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK); 566 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
605 grab_fpu(regs); 567 grab_fpu(regs);
606 restore_fpu(tsk); 568 restore_fpu(tsk);
607 set_tsk_thread_flag(tsk, TIF_USEDFPU); 569 task_thread_info(tsk)->status |= TS_USEDFPU;
608 return; 570 return;
609 } 571 }
610 572
611 force_sig(SIGFPE, tsk); 573 force_sig(SIGFPE, tsk);
612} 574}
613
614BUILD_TRAP_HANDLER(fpu_state_restore)
615{
616 struct task_struct *tsk = current;
617 TRAP_HANDLER_DECL;
618
619 grab_fpu(regs);
620 if (!user_mode(regs)) {
621 printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
622 return;
623 }
624
625 if (used_math()) {
626 /* Using the FPU again. */
627 restore_fpu(tsk);
628 } else {
629 /* First time FPU user. */
630 fpu_init();
631 set_used_math();
632 }
633 set_tsk_thread_flag(tsk, TIF_USEDFPU);
634}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index b67376445315..8f669dc9b0da 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -207,27 +207,23 @@ static struct platform_device mtu2_2_device = {
207 .num_resources = ARRAY_SIZE(mtu2_2_resources), 207 .num_resources = ARRAY_SIZE(mtu2_2_resources),
208}; 208};
209 209
210static struct plat_sci_port sci_platform_data[] = { 210static struct plat_sci_port scif0_platform_data = {
211 { 211 .mapbase = 0xff804000,
212 .mapbase = 0xff804000, 212 .flags = UPF_BOOT_AUTOCONF,
213 .flags = UPF_BOOT_AUTOCONF, 213 .type = PORT_SCIF,
214 .type = PORT_SCIF, 214 .irqs = { 220, 220, 220, 220 },
215 .irqs = { 220, 220, 220, 220 },
216 }, {
217 .flags = 0,
218 }
219}; 215};
220 216
221static struct platform_device sci_device = { 217static struct platform_device scif0_device = {
222 .name = "sh-sci", 218 .name = "sh-sci",
223 .id = -1, 219 .id = 0,
224 .dev = { 220 .dev = {
225 .platform_data = sci_platform_data, 221 .platform_data = &scif0_platform_data,
226 }, 222 },
227}; 223};
228 224
229static struct platform_device *mxg_devices[] __initdata = { 225static struct platform_device *mxg_devices[] __initdata = {
230 &sci_device, 226 &scif0_device,
231 &mtu2_0_device, 227 &mtu2_0_device,
232 &mtu2_1_device, 228 &mtu2_1_device,
233 &mtu2_2_device, 229 &mtu2_2_device,
@@ -246,6 +242,7 @@ void __init plat_irq_setup(void)
246} 242}
247 243
248static struct platform_device *mxg_early_devices[] __initdata = { 244static struct platform_device *mxg_early_devices[] __initdata = {
245 &scif0_device,
249 &mtu2_0_device, 246 &mtu2_0_device,
250 &mtu2_1_device, 247 &mtu2_1_device,
251 &mtu2_2_device, 248 &mtu2_2_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index fbde5b75deb9..4ccfeb59eb1a 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -177,57 +177,123 @@ static struct intc_mask_reg mask_registers[] __initdata = {
177static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, 177static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
178 mask_registers, prio_registers, NULL); 178 mask_registers, prio_registers, NULL);
179 179
180static struct plat_sci_port sci_platform_data[] = { 180static struct plat_sci_port scif0_platform_data = {
181 { 181 .mapbase = 0xfffe8000,
182 .mapbase = 0xfffe8000, 182 .flags = UPF_BOOT_AUTOCONF,
183 .flags = UPF_BOOT_AUTOCONF, 183 .type = PORT_SCIF,
184 .type = PORT_SCIF, 184 .irqs = { 180, 180, 180, 180 }
185 .irqs = { 180, 180, 180, 180 } 185};
186 }, { 186
187 .mapbase = 0xfffe8800, 187static struct platform_device scif0_device = {
188 .flags = UPF_BOOT_AUTOCONF,
189 .type = PORT_SCIF,
190 .irqs = { 184, 184, 184, 184 }
191 }, {
192 .mapbase = 0xfffe9000,
193 .flags = UPF_BOOT_AUTOCONF,
194 .type = PORT_SCIF,
195 .irqs = { 188, 188, 188, 188 }
196 }, {
197 .mapbase = 0xfffe9800,
198 .flags = UPF_BOOT_AUTOCONF,
199 .type = PORT_SCIF,
200 .irqs = { 192, 192, 192, 192 }
201 }, {
202 .mapbase = 0xfffea000,
203 .flags = UPF_BOOT_AUTOCONF,
204 .type = PORT_SCIF,
205 .irqs = { 196, 196, 196, 196 }
206 }, {
207 .mapbase = 0xfffea800,
208 .flags = UPF_BOOT_AUTOCONF,
209 .type = PORT_SCIF,
210 .irqs = { 200, 200, 200, 200 }
211 }, {
212 .mapbase = 0xfffeb000,
213 .flags = UPF_BOOT_AUTOCONF,
214 .type = PORT_SCIF,
215 .irqs = { 204, 204, 204, 204 }
216 }, {
217 .mapbase = 0xfffeb800,
218 .flags = UPF_BOOT_AUTOCONF,
219 .type = PORT_SCIF,
220 .irqs = { 208, 208, 208, 208 }
221 }, {
222 .flags = 0,
223 }
224};
225
226static struct platform_device sci_device = {
227 .name = "sh-sci", 188 .name = "sh-sci",
228 .id = -1, 189 .id = 0,
190 .dev = {
191 .platform_data = &scif0_platform_data,
192 },
193};
194
195static struct plat_sci_port scif1_platform_data = {
196 .mapbase = 0xfffe8800,
197 .flags = UPF_BOOT_AUTOCONF,
198 .type = PORT_SCIF,
199 .irqs = { 184, 184, 184, 184 }
200};
201
202static struct platform_device scif1_device = {
203 .name = "sh-sci",
204 .id = 1,
205 .dev = {
206 .platform_data = &scif1_platform_data,
207 },
208};
209
210static struct plat_sci_port scif2_platform_data = {
211 .mapbase = 0xfffe9000,
212 .flags = UPF_BOOT_AUTOCONF,
213 .type = PORT_SCIF,
214 .irqs = { 188, 188, 188, 188 }
215};
216
217static struct platform_device scif2_device = {
218 .name = "sh-sci",
219 .id = 2,
220 .dev = {
221 .platform_data = &scif2_platform_data,
222 },
223};
224
225static struct plat_sci_port scif3_platform_data = {
226 .mapbase = 0xfffe9800,
227 .flags = UPF_BOOT_AUTOCONF,
228 .type = PORT_SCIF,
229 .irqs = { 192, 192, 192, 192 }
230};
231
232static struct platform_device scif3_device = {
233 .name = "sh-sci",
234 .id = 3,
235 .dev = {
236 .platform_data = &scif3_platform_data,
237 },
238};
239
240static struct plat_sci_port scif4_platform_data = {
241 .mapbase = 0xfffea000,
242 .flags = UPF_BOOT_AUTOCONF,
243 .type = PORT_SCIF,
244 .irqs = { 196, 196, 196, 196 }
245};
246
247static struct platform_device scif4_device = {
248 .name = "sh-sci",
249 .id = 4,
250 .dev = {
251 .platform_data = &scif4_platform_data,
252 },
253};
254
255static struct plat_sci_port scif5_platform_data = {
256 .mapbase = 0xfffea800,
257 .flags = UPF_BOOT_AUTOCONF,
258 .type = PORT_SCIF,
259 .irqs = { 200, 200, 200, 200 }
260};
261
262static struct platform_device scif5_device = {
263 .name = "sh-sci",
264 .id = 5,
265 .dev = {
266 .platform_data = &scif5_platform_data,
267 },
268};
269
270static struct plat_sci_port scif6_platform_data = {
271 .mapbase = 0xfffeb000,
272 .flags = UPF_BOOT_AUTOCONF,
273 .type = PORT_SCIF,
274 .irqs = { 204, 204, 204, 204 }
275};
276
277static struct platform_device scif6_device = {
278 .name = "sh-sci",
279 .id = 6,
280 .dev = {
281 .platform_data = &scif6_platform_data,
282 },
283};
284
285static struct plat_sci_port scif7_platform_data = {
286 .mapbase = 0xfffeb800,
287 .flags = UPF_BOOT_AUTOCONF,
288 .type = PORT_SCIF,
289 .irqs = { 208, 208, 208, 208 }
290};
291
292static struct platform_device scif7_device = {
293 .name = "sh-sci",
294 .id = 7,
229 .dev = { 295 .dev = {
230 .platform_data = sci_platform_data, 296 .platform_data = &scif7_platform_data,
231 }, 297 },
232}; 298};
233 299
@@ -345,7 +411,14 @@ static struct platform_device mtu2_2_device = {
345}; 411};
346 412
347static struct platform_device *sh7201_devices[] __initdata = { 413static struct platform_device *sh7201_devices[] __initdata = {
348 &sci_device, 414 &scif0_device,
415 &scif1_device,
416 &scif2_device,
417 &scif3_device,
418 &scif4_device,
419 &scif5_device,
420 &scif6_device,
421 &scif7_device,
349 &rtc_device, 422 &rtc_device,
350 &mtu2_0_device, 423 &mtu2_0_device,
351 &mtu2_1_device, 424 &mtu2_1_device,
@@ -365,6 +438,14 @@ void __init plat_irq_setup(void)
365} 438}
366 439
367static struct platform_device *sh7201_early_devices[] __initdata = { 440static struct platform_device *sh7201_early_devices[] __initdata = {
441 &scif0_device,
442 &scif1_device,
443 &scif2_device,
444 &scif3_device,
445 &scif4_device,
446 &scif5_device,
447 &scif6_device,
448 &scif7_device,
368 &mtu2_0_device, 449 &mtu2_0_device,
369 &mtu2_1_device, 450 &mtu2_1_device,
370 &mtu2_2_device, 451 &mtu2_2_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index d3fd536c9a84..3136966cc9b3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -173,37 +173,63 @@ static struct intc_mask_reg mask_registers[] __initdata = {
173static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, 173static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
174 mask_registers, prio_registers, NULL); 174 mask_registers, prio_registers, NULL);
175 175
176static struct plat_sci_port sci_platform_data[] = { 176static struct plat_sci_port scif0_platform_data = {
177 { 177 .mapbase = 0xfffe8000,
178 .mapbase = 0xfffe8000, 178 .flags = UPF_BOOT_AUTOCONF,
179 .flags = UPF_BOOT_AUTOCONF, 179 .type = PORT_SCIF,
180 .type = PORT_SCIF, 180 .irqs = { 192, 192, 192, 192 },
181 .irqs = { 192, 192, 192, 192 },
182 }, {
183 .mapbase = 0xfffe8800,
184 .flags = UPF_BOOT_AUTOCONF,
185 .type = PORT_SCIF,
186 .irqs = { 196, 196, 196, 196 },
187 }, {
188 .mapbase = 0xfffe9000,
189 .flags = UPF_BOOT_AUTOCONF,
190 .type = PORT_SCIF,
191 .irqs = { 200, 200, 200, 200 },
192 }, {
193 .mapbase = 0xfffe9800,
194 .flags = UPF_BOOT_AUTOCONF,
195 .type = PORT_SCIF,
196 .irqs = { 204, 204, 204, 204 },
197 }, {
198 .flags = 0,
199 }
200}; 181};
201 182
202static struct platform_device sci_device = { 183static struct platform_device scif0_device = {
203 .name = "sh-sci", 184 .name = "sh-sci",
204 .id = -1, 185 .id = 0,
186 .dev = {
187 .platform_data = &scif0_platform_data,
188 },
189};
190
191static struct plat_sci_port scif1_platform_data = {
192 .mapbase = 0xfffe8800,
193 .flags = UPF_BOOT_AUTOCONF,
194 .type = PORT_SCIF,
195 .irqs = { 196, 196, 196, 196 },
196};
197
198static struct platform_device scif1_device = {
199 .name = "sh-sci",
200 .id = 1,
201 .dev = {
202 .platform_data = &scif1_platform_data,
203 },
204};
205
206static struct plat_sci_port scif2_platform_data = {
207 .mapbase = 0xfffe9000,
208 .flags = UPF_BOOT_AUTOCONF,
209 .type = PORT_SCIF,
210 .irqs = { 200, 200, 200, 200 },
211};
212
213static struct platform_device scif2_device = {
214 .name = "sh-sci",
215 .id = 2,
216 .dev = {
217 .platform_data = &scif2_platform_data,
218 },
219};
220
221static struct plat_sci_port scif3_platform_data = {
222 .mapbase = 0xfffe9800,
223 .flags = UPF_BOOT_AUTOCONF,
224 .type = PORT_SCIF,
225 .irqs = { 204, 204, 204, 204 },
226};
227
228static struct platform_device scif3_device = {
229 .name = "sh-sci",
230 .id = 3,
205 .dev = { 231 .dev = {
206 .platform_data = sci_platform_data, 232 .platform_data = &scif3_platform_data,
207 }, 233 },
208}; 234};
209 235
@@ -354,7 +380,10 @@ static struct platform_device rtc_device = {
354}; 380};
355 381
356static struct platform_device *sh7203_devices[] __initdata = { 382static struct platform_device *sh7203_devices[] __initdata = {
357 &sci_device, 383 &scif0_device,
384 &scif1_device,
385 &scif2_device,
386 &scif3_device,
358 &cmt0_device, 387 &cmt0_device,
359 &cmt1_device, 388 &cmt1_device,
360 &mtu2_0_device, 389 &mtu2_0_device,
@@ -375,6 +404,10 @@ void __init plat_irq_setup(void)
375} 404}
376 405
377static struct platform_device *sh7203_early_devices[] __initdata = { 406static struct platform_device *sh7203_early_devices[] __initdata = {
407 &scif0_device,
408 &scif1_device,
409 &scif2_device,
410 &scif3_device,
378 &cmt0_device, 411 &cmt0_device,
379 &cmt1_device, 412 &cmt1_device,
380 &mtu2_0_device, 413 &mtu2_0_device,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index a9ccc5e8d9e9..064873585a8b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -133,37 +133,63 @@ static struct intc_mask_reg mask_registers[] __initdata = {
133static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, 133static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
134 mask_registers, prio_registers, NULL); 134 mask_registers, prio_registers, NULL);
135 135
136static struct plat_sci_port sci_platform_data[] = { 136static struct plat_sci_port scif0_platform_data = {
137 { 137 .mapbase = 0xfffe8000,
138 .mapbase = 0xfffe8000, 138 .flags = UPF_BOOT_AUTOCONF,
139 .flags = UPF_BOOT_AUTOCONF, 139 .type = PORT_SCIF,
140 .type = PORT_SCIF, 140 .irqs = { 240, 240, 240, 240 },
141 .irqs = { 240, 240, 240, 240 },
142 }, {
143 .mapbase = 0xfffe8800,
144 .flags = UPF_BOOT_AUTOCONF,
145 .type = PORT_SCIF,
146 .irqs = { 244, 244, 244, 244 },
147 }, {
148 .mapbase = 0xfffe9000,
149 .flags = UPF_BOOT_AUTOCONF,
150 .type = PORT_SCIF,
151 .irqs = { 248, 248, 248, 248 },
152 }, {
153 .mapbase = 0xfffe9800,
154 .flags = UPF_BOOT_AUTOCONF,
155 .type = PORT_SCIF,
156 .irqs = { 252, 252, 252, 252 },
157 }, {
158 .flags = 0,
159 }
160}; 141};
161 142
162static struct platform_device sci_device = { 143static struct platform_device scif0_device = {
163 .name = "sh-sci", 144 .name = "sh-sci",
164 .id = -1, 145 .id = 0,
146 .dev = {
147 .platform_data = &scif0_platform_data,
148 },
149};
150
151static struct plat_sci_port scif1_platform_data = {
152 .mapbase = 0xfffe8800,
153 .flags = UPF_BOOT_AUTOCONF,
154 .type = PORT_SCIF,
155 .irqs = { 244, 244, 244, 244 },
156};
157
158static struct platform_device scif1_device = {
159 .name = "sh-sci",
160 .id = 1,
161 .dev = {
162 .platform_data = &scif1_platform_data,
163 },
164};
165
166static struct plat_sci_port scif2_platform_data = {
167 .mapbase = 0xfffe9000,
168 .flags = UPF_BOOT_AUTOCONF,
169 .type = PORT_SCIF,
170 .irqs = { 248, 248, 248, 248 },
171};
172
173static struct platform_device scif2_device = {
174 .name = "sh-sci",
175 .id = 2,
176 .dev = {
177 .platform_data = &scif2_platform_data,
178 },
179};
180
181static struct plat_sci_port scif3_platform_data = {
182 .mapbase = 0xfffe9800,
183 .flags = UPF_BOOT_AUTOCONF,
184 .type = PORT_SCIF,
185 .irqs = { 252, 252, 252, 252 },
186};
187
188static struct platform_device scif3_device = {
189 .name = "sh-sci",
190 .id = 3,
165 .dev = { 191 .dev = {
166 .platform_data = sci_platform_data, 192 .platform_data = &scif3_platform_data,
167 }, 193 },
168}; 194};
169 195
@@ -325,7 +351,10 @@ static struct platform_device mtu2_2_device = {
325}; 351};
326 352
327static struct platform_device *sh7206_devices[] __initdata = { 353static struct platform_device *sh7206_devices[] __initdata = {
328 &sci_device, 354 &scif0_device,
355 &scif1_device,
356 &scif2_device,
357 &scif3_device,
329 &cmt0_device, 358 &cmt0_device,
330 &cmt1_device, 359 &cmt1_device,
331 &mtu2_0_device, 360 &mtu2_0_device,
@@ -346,6 +375,10 @@ void __init plat_irq_setup(void)
346} 375}
347 376
348static struct platform_device *sh7206_early_devices[] __initdata = { 377static struct platform_device *sh7206_early_devices[] __initdata = {
378 &scif0_device,
379 &scif1_device,
380 &scif2_device,
381 &scif3_device,
349 &cmt0_device, 382 &cmt0_device,
350 &cmt1_device, 383 &cmt1_device,
351 &mtu2_0_device, 384 &mtu2_0_device,
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index 27b8738f0b09..b78384afac09 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -28,7 +28,7 @@ static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
28 28
29static void master_clk_init(struct clk *clk) 29static void master_clk_init(struct clk *clk)
30{ 30{
31 int frqcr = ctrl_inw(FRQCR); 31 int frqcr = __raw_readw(FRQCR);
32 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 32 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
33 33
34 clk->rate *= pfc_divisors[idx]; 34 clk->rate *= pfc_divisors[idx];
@@ -40,7 +40,7 @@ static struct clk_ops sh3_master_clk_ops = {
40 40
41static unsigned long module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int frqcr = ctrl_inw(FRQCR); 43 int frqcr = __raw_readw(FRQCR);
44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
45 45
46 return clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
@@ -52,7 +52,7 @@ static struct clk_ops sh3_module_clk_ops = {
52 52
53static unsigned long bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int frqcr = ctrl_inw(FRQCR); 55 int frqcr = __raw_readw(FRQCR);
56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
57 57
58 return clk->parent->rate / stc_multipliers[idx]; 58 return clk->parent->rate / stc_multipliers[idx];
@@ -64,7 +64,7 @@ static struct clk_ops sh3_bus_clk_ops = {
64 64
65static unsigned long cpu_clk_recalc(struct clk *clk) 65static unsigned long cpu_clk_recalc(struct clk *clk)
66{ 66{
67 int frqcr = ctrl_inw(FRQCR); 67 int frqcr = __raw_readw(FRQCR);
68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
69 69
70 return clk->parent->rate / ifc_divisors[idx]; 70 return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index 0ca8f2c3646c..0ecea1451c6f 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -32,7 +32,7 @@ static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
32 32
33static void master_clk_init(struct clk *clk) 33static void master_clk_init(struct clk *clk)
34{ 34{
35 clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0003]; 35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
36} 36}
37 37
38static struct clk_ops sh7705_master_clk_ops = { 38static struct clk_ops sh7705_master_clk_ops = {
@@ -41,7 +41,7 @@ static struct clk_ops sh7705_master_clk_ops = {
41 41
42static unsigned long module_clk_recalc(struct clk *clk) 42static unsigned long module_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ctrl_inw(FRQCR) & 0x0003; 44 int idx = __raw_readw(FRQCR) & 0x0003;
45 return clk->parent->rate / pfc_divisors[idx]; 45 return clk->parent->rate / pfc_divisors[idx];
46} 46}
47 47
@@ -51,7 +51,7 @@ static struct clk_ops sh7705_module_clk_ops = {
51 51
52static unsigned long bus_clk_recalc(struct clk *clk) 52static unsigned long bus_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8; 54 int idx = (__raw_readw(FRQCR) & 0x0300) >> 8;
55 return clk->parent->rate / stc_multipliers[idx]; 55 return clk->parent->rate / stc_multipliers[idx];
56} 56}
57 57
@@ -61,7 +61,7 @@ static struct clk_ops sh7705_bus_clk_ops = {
61 61
62static unsigned long cpu_clk_recalc(struct clk *clk) 62static unsigned long cpu_clk_recalc(struct clk *clk)
63{ 63{
64 int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4; 64 int idx = (__raw_readw(FRQCR) & 0x0030) >> 4;
65 return clk->parent->rate / ifc_divisors[idx]; 65 return clk->parent->rate / ifc_divisors[idx];
66} 66}
67 67
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 4bf7887d310a..6f9ff8b57dd6 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -24,7 +24,7 @@ static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
24 24
25static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
26{ 26{
27 int frqcr = ctrl_inw(FRQCR); 27 int frqcr = __raw_readw(FRQCR);
28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
29 29
30 clk->rate *= pfc_divisors[idx]; 30 clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7706_master_clk_ops = {
36 36
37static unsigned long module_clk_recalc(struct clk *clk) 37static unsigned long module_clk_recalc(struct clk *clk)
38{ 38{
39 int frqcr = ctrl_inw(FRQCR); 39 int frqcr = __raw_readw(FRQCR);
40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
41 41
42 return clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7706_module_clk_ops = {
48 48
49static unsigned long bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int frqcr = ctrl_inw(FRQCR); 51 int frqcr = __raw_readw(FRQCR);
52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
53 53
54 return clk->parent->rate / stc_multipliers[idx]; 54 return clk->parent->rate / stc_multipliers[idx];
@@ -60,7 +60,7 @@ static struct clk_ops sh7706_bus_clk_ops = {
60 60
61static unsigned long cpu_clk_recalc(struct clk *clk) 61static unsigned long cpu_clk_recalc(struct clk *clk)
62{ 62{
63 int frqcr = ctrl_inw(FRQCR); 63 int frqcr = __raw_readw(FRQCR);
64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
65 65
66 return clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index e8749505bd2a..f302ba09e681 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -24,7 +24,7 @@ static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
24 24
25static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
26{ 26{
27 int frqcr = ctrl_inw(FRQCR); 27 int frqcr = __raw_readw(FRQCR);
28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
29 29
30 clk->rate *= pfc_divisors[idx]; 30 clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7709_master_clk_ops = {
36 36
37static unsigned long module_clk_recalc(struct clk *clk) 37static unsigned long module_clk_recalc(struct clk *clk)
38{ 38{
39 int frqcr = ctrl_inw(FRQCR); 39 int frqcr = __raw_readw(FRQCR);
40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
41 41
42 return clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7709_module_clk_ops = {
48 48
49static unsigned long bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int frqcr = ctrl_inw(FRQCR); 51 int frqcr = __raw_readw(FRQCR);
52 int idx = (frqcr & 0x0080) ? 52 int idx = (frqcr & 0x0080) ?
53 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1; 53 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
54 54
@@ -61,7 +61,7 @@ static struct clk_ops sh7709_bus_clk_ops = {
61 61
62static unsigned long cpu_clk_recalc(struct clk *clk) 62static unsigned long cpu_clk_recalc(struct clk *clk)
63{ 63{
64 int frqcr = ctrl_inw(FRQCR); 64 int frqcr = __raw_readw(FRQCR);
65 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 65 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
66 66
67 return clk->parent->rate / ifc_divisors[idx]; 67 return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 030a58ba18a5..29a87d8946a4 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -26,7 +26,7 @@ static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
26 26
27static void master_clk_init(struct clk *clk) 27static void master_clk_init(struct clk *clk)
28{ 28{
29 clk->rate *= md_table[ctrl_inw(FRQCR) & 0x0007]; 29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
30} 30}
31 31
32static struct clk_ops sh7710_master_clk_ops = { 32static struct clk_ops sh7710_master_clk_ops = {
@@ -35,7 +35,7 @@ static struct clk_ops sh7710_master_clk_ops = {
35 35
36static unsigned long module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int idx = (ctrl_inw(FRQCR) & 0x0007); 38 int idx = (__raw_readw(FRQCR) & 0x0007);
39 return clk->parent->rate / md_table[idx]; 39 return clk->parent->rate / md_table[idx];
40} 40}
41 41
@@ -45,7 +45,7 @@ static struct clk_ops sh7710_module_clk_ops = {
45 45
46static unsigned long bus_clk_recalc(struct clk *clk) 46static unsigned long bus_clk_recalc(struct clk *clk)
47{ 47{
48 int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8; 48 int idx = (__raw_readw(FRQCR) & 0x0700) >> 8;
49 return clk->parent->rate / md_table[idx]; 49 return clk->parent->rate / md_table[idx];
50} 50}
51 51
@@ -55,7 +55,7 @@ static struct clk_ops sh7710_bus_clk_ops = {
55 55
56static unsigned long cpu_clk_recalc(struct clk *clk) 56static unsigned long cpu_clk_recalc(struct clk *clk)
57{ 57{
58 int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4; 58 int idx = (__raw_readw(FRQCR) & 0x0070) >> 4;
59 return clk->parent->rate / md_table[idx]; 59 return clk->parent->rate / md_table[idx];
60} 60}
61 61
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index 6428ee6c77ed..b0d0c5203996 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -23,7 +23,7 @@ static int divisors[] = { 1, 2, 3, 4, 6 };
23 23
24static void master_clk_init(struct clk *clk) 24static void master_clk_init(struct clk *clk)
25{ 25{
26 int frqcr = ctrl_inw(FRQCR); 26 int frqcr = __raw_readw(FRQCR);
27 int idx = (frqcr & 0x0300) >> 8; 27 int idx = (frqcr & 0x0300) >> 8;
28 28
29 clk->rate *= multipliers[idx]; 29 clk->rate *= multipliers[idx];
@@ -35,7 +35,7 @@ static struct clk_ops sh7712_master_clk_ops = {
35 35
36static unsigned long module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int frqcr = ctrl_inw(FRQCR); 38 int frqcr = __raw_readw(FRQCR);
39 int idx = frqcr & 0x0007; 39 int idx = frqcr & 0x0007;
40 40
41 return clk->parent->rate / divisors[idx]; 41 return clk->parent->rate / divisors[idx];
@@ -47,7 +47,7 @@ static struct clk_ops sh7712_module_clk_ops = {
47 47
48static unsigned long cpu_clk_recalc(struct clk *clk) 48static unsigned long cpu_clk_recalc(struct clk *clk)
49{ 49{
50 int frqcr = ctrl_inw(FRQCR); 50 int frqcr = __raw_readw(FRQCR);
51 int idx = (frqcr & 0x0030) >> 4; 51 int idx = (frqcr & 0x0030) >> 4;
52 52
53 return clk->parent->rate / divisors[idx]; 53 return clk->parent->rate / divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index bb407ef0b91e..f6a389c996cb 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -132,7 +132,6 @@ ENTRY(tlb_protection_violation_store)
132 mov #1, r5 132 mov #1, r5
133 133
134call_handle_tlbmiss: 134call_handle_tlbmiss:
135 setup_frame_reg
136 mov.l 1f, r0 135 mov.l 1f, r0
137 mov r5, r8 136 mov r5, r8
138 mov.l @r0, r6 137 mov.l @r0, r6
@@ -297,41 +296,8 @@ ENTRY(vbr_base)
297! 296!
298 .balign 256,0,256 297 .balign 256,0,256
299general_exception: 298general_exception:
300#ifndef CONFIG_CPU_SUBTYPE_SHX3
301 bra handle_exception 299 bra handle_exception
302 sts pr, k3 ! save original pr value in k3 300 sts pr, k3 ! save original pr value in k3
303#else
304 mov.l 1f, k4
305 mov.l @k4, k4
306
307 ! Is EXPEVT larger than 0x800?
308 mov #0x8, k0
309 shll8 k0
310 cmp/hs k0, k4
311 bf 0f
312
313 ! then add 0x580 (k2 is 0xd80 or 0xda0)
314 mov #0x58, k0
315 shll2 k0
316 shll2 k0
317 add k0, k4
3180:
319 ! Setup stack and save DSP context (k0 contains original r15 on return)
320 bsr prepare_stack
321 nop
322
323 ! Save registers / Switch to bank 0
324 mov k4, k2 ! keep vector in k2
325 mov.l 1f, k4 ! SR bits to clear in k4
326 bsr save_regs ! needs original pr value in k3
327 nop
328
329 bra handle_exception_special
330 nop
331
332 .align 2
3331: .long EXPEVT
334#endif
335 301
336! prepare_stack() 302! prepare_stack()
337! - roll back gRB 303! - roll back gRB
@@ -398,6 +364,8 @@ handle_exception:
398 mov.l @k2, k2 ! read out vector and keep in k2 364 mov.l @k2, k2 ! read out vector and keep in k2
399 365
400handle_exception_special: 366handle_exception_special:
367 setup_frame_reg
368
401 ! Setup return address and jump to exception handler 369 ! Setup return address and jump to exception handler
402 mov.l 7f, r9 ! fetch return address 370 mov.l 7f, r9 ! fetch return address
403 stc r2_bank, r0 ! k2 (vector) 371 stc r2_bank, r0 ! k2 (vector)
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index 46610c35c232..99b4d020179a 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -49,7 +49,7 @@ ENTRY(exception_handling_table)
49 .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */ 49 .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */
50 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/ 50 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
51 .long nmi_trap_handler /* 1C0 */ ! Allow trap to debugger 51 .long nmi_trap_handler /* 1C0 */ ! Allow trap to debugger
52 .long break_point_trap /* 1E0 */ 52 .long breakpoint_trap_handler /* 1E0 */
53 53
54 /* 54 /*
55 * Pad the remainder of the table out, exceptions residing in far 55 * Pad the remainder of the table out, exceptions residing in far
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index f9c7df64eb01..295ec4c99e98 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -16,7 +16,7 @@
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <asm/io.h> 17#include <asm/io.h>
18 18
19int __uses_jump_to_uncached detect_cpu_and_cache_system(void) 19int detect_cpu_and_cache_system(void)
20{ 20{
21 unsigned long addr0, addr1, data0, data1, data2, data3; 21 unsigned long addr0, addr1, data0, data1, data2, data3;
22 22
@@ -30,23 +30,23 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12); 30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
31 31
32 /* First, write back & invalidate */ 32 /* First, write back & invalidate */
33 data0 = ctrl_inl(addr0); 33 data0 = __raw_readl(addr0);
34 ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0); 34 __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
35 data1 = ctrl_inl(addr1); 35 data1 = __raw_readl(addr1);
36 ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1); 36 __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
37 37
38 /* Next, check if there's shadow or not */ 38 /* Next, check if there's shadow or not */
39 data0 = ctrl_inl(addr0); 39 data0 = __raw_readl(addr0);
40 data0 ^= SH_CACHE_VALID; 40 data0 ^= SH_CACHE_VALID;
41 ctrl_outl(data0, addr0); 41 __raw_writel(data0, addr0);
42 data1 = ctrl_inl(addr1); 42 data1 = __raw_readl(addr1);
43 data2 = data1 ^ SH_CACHE_VALID; 43 data2 = data1 ^ SH_CACHE_VALID;
44 ctrl_outl(data2, addr1); 44 __raw_writel(data2, addr1);
45 data3 = ctrl_inl(addr0); 45 data3 = __raw_readl(addr0);
46 46
47 /* Lastly, invaliate them. */ 47 /* Lastly, invaliate them. */
48 ctrl_outl(data0&~SH_CACHE_VALID, addr0); 48 __raw_writel(data0&~SH_CACHE_VALID, addr0);
49 ctrl_outl(data2&~SH_CACHE_VALID, addr1); 49 __raw_writel(data2&~SH_CACHE_VALID, addr1);
50 50
51 back_to_cached(); 51 back_to_cached();
52 52
@@ -94,9 +94,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
94 boot_cpu_data.dcache.way_incr = (1 << 13); 94 boot_cpu_data.dcache.way_incr = (1 << 13);
95 boot_cpu_data.dcache.entry_mask = 0x1ff0; 95 boot_cpu_data.dcache.entry_mask = 0x1ff0;
96 boot_cpu_data.dcache.sets = 512; 96 boot_cpu_data.dcache.sets = 512;
97 ctrl_outl(CCR_CACHE_32KB, CCR3_REG); 97 __raw_writel(CCR_CACHE_32KB, CCR3_REG);
98#else 98#else
99 ctrl_outl(CCR_CACHE_16KB, CCR3_REG); 99 __raw_writel(CCR_CACHE_16KB, CCR3_REG);
100#endif 100#endif
101#endif 101#endif
102 } 102 }
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh3.c b/arch/sh/kernel/cpu/sh3/setup-sh3.c
index c98846857855..53be70b98116 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh3.c
@@ -58,7 +58,7 @@ static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
58void __init plat_irq_setup_pins(int mode) 58void __init plat_irq_setup_pins(int mode)
59{ 59{
60 if (mode == IRQ_MODE_IRQ) { 60 if (mode == IRQ_MODE_IRQ) {
61 ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); 61 __raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
62 register_intc_controller(&intc_desc_irq0123); 62 register_intc_controller(&intc_desc_irq0123);
63 return; 63 return;
64 } 64 }
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index c23105983878..7b892d60e3a0 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -67,27 +67,33 @@ static struct intc_prio_reg prio_registers[] __initdata = {
67static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL, 67static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
68 NULL, prio_registers, NULL); 68 NULL, prio_registers, NULL);
69 69
70static struct plat_sci_port sci_platform_data[] = { 70static struct plat_sci_port scif0_platform_data = {
71 { 71 .mapbase = 0xa4410000,
72 .mapbase = 0xa4410000, 72 .flags = UPF_BOOT_AUTOCONF,
73 .flags = UPF_BOOT_AUTOCONF, 73 .type = PORT_SCIF,
74 .type = PORT_SCIF, 74 .irqs = { 56, 56, 56 },
75 .irqs = { 56, 56, 56 }, 75};
76 }, { 76
77 .mapbase = 0xa4400000, 77static struct platform_device scif0_device = {
78 .flags = UPF_BOOT_AUTOCONF,
79 .type = PORT_SCIF,
80 .irqs = { 52, 52, 52 },
81 }, {
82 .flags = 0,
83 }
84};
85
86static struct platform_device sci_device = {
87 .name = "sh-sci", 78 .name = "sh-sci",
88 .id = -1, 79 .id = 0,
80 .dev = {
81 .platform_data = &scif0_platform_data,
82 },
83};
84
85static struct plat_sci_port scif1_platform_data = {
86 .mapbase = 0xa4400000,
87 .flags = UPF_BOOT_AUTOCONF,
88 .type = PORT_SCIF,
89 .irqs = { 52, 52, 52 },
90};
91
92static struct platform_device scif1_device = {
93 .name = "sh-sci",
94 .id = 1,
89 .dev = { 95 .dev = {
90 .platform_data = sci_platform_data, 96 .platform_data = &scif1_platform_data,
91 }, 97 },
92}; 98};
93 99
@@ -210,10 +216,11 @@ static struct platform_device tmu2_device = {
210}; 216};
211 217
212static struct platform_device *sh7705_devices[] __initdata = { 218static struct platform_device *sh7705_devices[] __initdata = {
219 &scif0_device,
220 &scif1_device,
213 &tmu0_device, 221 &tmu0_device,
214 &tmu1_device, 222 &tmu1_device,
215 &tmu2_device, 223 &tmu2_device,
216 &sci_device,
217 &rtc_device, 224 &rtc_device,
218}; 225};
219 226
@@ -225,6 +232,8 @@ static int __init sh7705_devices_setup(void)
225arch_initcall(sh7705_devices_setup); 232arch_initcall(sh7705_devices_setup);
226 233
227static struct platform_device *sh7705_early_devices[] __initdata = { 234static struct platform_device *sh7705_early_devices[] __initdata = {
235 &scif0_device,
236 &scif1_device,
228 &tmu0_device, 237 &tmu0_device,
229 &tmu1_device, 238 &tmu1_device,
230 &tmu2_device, 239 &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 347ab35d0697..bc0c4f68c7c7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -106,44 +106,55 @@ static struct platform_device rtc_device = {
106 .resource = rtc_resources, 106 .resource = rtc_resources,
107}; 107};
108 108
109static struct plat_sci_port sci_platform_data[] = { 109static struct plat_sci_port scif0_platform_data = {
110 { 110 .mapbase = 0xfffffe80,
111 .mapbase = 0xfffffe80, 111 .flags = UPF_BOOT_AUTOCONF,
112 .flags = UPF_BOOT_AUTOCONF, 112 .type = PORT_SCI,
113 .type = PORT_SCI, 113 .irqs = { 23, 23, 23, 0 },
114 .irqs = { 23, 23, 23, 0 }, 114};
115
116static struct platform_device scif0_device = {
117 .name = "sh-sci",
118 .id = 0,
119 .dev = {
120 .platform_data = &scif0_platform_data,
115 }, 121 },
122};
116#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 123#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
117 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 124 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
118 defined(CONFIG_CPU_SUBTYPE_SH7709) 125 defined(CONFIG_CPU_SUBTYPE_SH7709)
119 { 126static struct plat_sci_port scif1_platform_data = {
120 .mapbase = 0xa4000150, 127 .mapbase = 0xa4000150,
121 .flags = UPF_BOOT_AUTOCONF, 128 .flags = UPF_BOOT_AUTOCONF,
122 .type = PORT_SCIF, 129 .type = PORT_SCIF,
123 .irqs = { 56, 56, 56, 56 }, 130 .irqs = { 56, 56, 56, 56 },
131};
132
133static struct platform_device scif1_device = {
134 .name = "sh-sci",
135 .id = 1,
136 .dev = {
137 .platform_data = &scif1_platform_data,
124 }, 138 },
139};
125#endif 140#endif
126#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 141#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
127 defined(CONFIG_CPU_SUBTYPE_SH7709) 142 defined(CONFIG_CPU_SUBTYPE_SH7709)
128 { 143static struct plat_sci_port scif2_platform_data = {
129 .mapbase = 0xa4000140, 144 .mapbase = 0xa4000140,
130 .flags = UPF_BOOT_AUTOCONF, 145 .flags = UPF_BOOT_AUTOCONF,
131 .type = PORT_IRDA, 146 .type = PORT_IRDA,
132 .irqs = { 52, 52, 52, 52 }, 147 .irqs = { 52, 52, 52, 52 },
133 },
134#endif
135 {
136 .flags = 0,
137 }
138}; 148};
139 149
140static struct platform_device sci_device = { 150static struct platform_device scif2_device = {
141 .name = "sh-sci", 151 .name = "sh-sci",
142 .id = -1, 152 .id = 2,
143 .dev = { 153 .dev = {
144 .platform_data = sci_platform_data, 154 .platform_data = &scif2_platform_data,
145 }, 155 },
146}; 156};
157#endif
147 158
148static struct sh_timer_config tmu0_platform_data = { 159static struct sh_timer_config tmu0_platform_data = {
149 .name = "TMU0", 160 .name = "TMU0",
@@ -238,10 +249,19 @@ static struct platform_device tmu2_device = {
238}; 249};
239 250
240static struct platform_device *sh770x_devices[] __initdata = { 251static struct platform_device *sh770x_devices[] __initdata = {
252 &scif0_device,
253#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
254 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
255 defined(CONFIG_CPU_SUBTYPE_SH7709)
256 &scif1_device,
257#endif
258#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7709)
260 &scif2_device,
261#endif
241 &tmu0_device, 262 &tmu0_device,
242 &tmu1_device, 263 &tmu1_device,
243 &tmu2_device, 264 &tmu2_device,
244 &sci_device,
245 &rtc_device, 265 &rtc_device,
246}; 266};
247 267
@@ -253,6 +273,16 @@ static int __init sh770x_devices_setup(void)
253arch_initcall(sh770x_devices_setup); 273arch_initcall(sh770x_devices_setup);
254 274
255static struct platform_device *sh770x_early_devices[] __initdata = { 275static struct platform_device *sh770x_early_devices[] __initdata = {
276 &scif0_device,
277#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
278 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
279 defined(CONFIG_CPU_SUBTYPE_SH7709)
280 &scif1_device,
281#endif
282#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7709)
284 &scif2_device,
285#endif
256 &tmu0_device, 286 &tmu0_device,
257 &tmu1_device, 287 &tmu1_device,
258 &tmu2_device, 288 &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 717e90ae1097..0845a3ad006d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -96,28 +96,33 @@ static struct platform_device rtc_device = {
96 }, 96 },
97}; 97};
98 98
99static struct plat_sci_port sci_platform_data[] = { 99static struct plat_sci_port scif0_platform_data = {
100 { 100 .mapbase = 0xa4400000,
101 .mapbase = 0xa4400000, 101 .flags = UPF_BOOT_AUTOCONF,
102 .flags = UPF_BOOT_AUTOCONF, 102 .type = PORT_SCIF,
103 .type = PORT_SCIF, 103 .irqs = { 52, 52, 52, 52 },
104 .irqs = { 52, 52, 52, 52 }, 104};
105 }, { 105
106 .mapbase = 0xa4410000, 106static struct platform_device scif0_device = {
107 .flags = UPF_BOOT_AUTOCONF,
108 .type = PORT_SCIF,
109 .irqs = { 56, 56, 56, 56 },
110 }, {
111
112 .flags = 0,
113 }
114};
115
116static struct platform_device sci_device = {
117 .name = "sh-sci", 107 .name = "sh-sci",
118 .id = -1, 108 .id = 0,
109 .dev = {
110 .platform_data = &scif0_platform_data,
111 },
112};
113
114static struct plat_sci_port scif1_platform_data = {
115 .mapbase = 0xa4410000,
116 .flags = UPF_BOOT_AUTOCONF,
117 .type = PORT_SCIF,
118 .irqs = { 56, 56, 56, 56 },
119};
120
121static struct platform_device scif1_device = {
122 .name = "sh-sci",
123 .id = 1,
119 .dev = { 124 .dev = {
120 .platform_data = sci_platform_data, 125 .platform_data = &scif1_platform_data,
121 }, 126 },
122}; 127};
123 128
@@ -214,10 +219,11 @@ static struct platform_device tmu2_device = {
214}; 219};
215 220
216static struct platform_device *sh7710_devices[] __initdata = { 221static struct platform_device *sh7710_devices[] __initdata = {
222 &scif0_device,
223 &scif1_device,
217 &tmu0_device, 224 &tmu0_device,
218 &tmu1_device, 225 &tmu1_device,
219 &tmu2_device, 226 &tmu2_device,
220 &sci_device,
221 &rtc_device, 227 &rtc_device,
222}; 228};
223 229
@@ -229,6 +235,8 @@ static int __init sh7710_devices_setup(void)
229arch_initcall(sh7710_devices_setup); 235arch_initcall(sh7710_devices_setup);
230 236
231static struct platform_device *sh7710_early_devices[] __initdata = { 237static struct platform_device *sh7710_early_devices[] __initdata = {
238 &scif0_device,
239 &scif1_device,
232 &tmu0_device, 240 &tmu0_device,
233 &tmu1_device, 241 &tmu1_device,
234 &tmu2_device, 242 &tmu2_device,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 74d8baaf8e96..a718a6231091 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -48,28 +48,33 @@ static struct platform_device rtc_device = {
48 }, 48 },
49}; 49};
50 50
51static struct plat_sci_port sci_platform_data[] = { 51static struct plat_sci_port scif0_platform_data = {
52 { 52 .mapbase = 0xa4430000,
53 .mapbase = 0xa4430000, 53 .flags = UPF_BOOT_AUTOCONF,
54 .flags = UPF_BOOT_AUTOCONF, 54 .type = PORT_SCIF,
55 .type = PORT_SCIF, 55 .irqs = { 80, 80, 80, 80 },
56 .irqs = { 80, 80, 80, 80 }, 56};
57 }, { 57
58 .mapbase = 0xa4438000, 58static struct platform_device scif0_device = {
59 .flags = UPF_BOOT_AUTOCONF,
60 .type = PORT_SCIF,
61 .irqs = { 81, 81, 81, 81 },
62 }, {
63
64 .flags = 0,
65 }
66};
67
68static struct platform_device sci_device = {
69 .name = "sh-sci", 59 .name = "sh-sci",
70 .id = -1, 60 .id = 0,
61 .dev = {
62 .platform_data = &scif0_platform_data,
63 },
64};
65
66static struct plat_sci_port scif1_platform_data = {
67 .mapbase = 0xa4438000,
68 .flags = UPF_BOOT_AUTOCONF,
69 .type = PORT_SCIF,
70 .irqs = { 81, 81, 81, 81 },
71};
72
73static struct platform_device scif1_device = {
74 .name = "sh-sci",
75 .id = 1,
71 .dev = { 76 .dev = {
72 .platform_data = sci_platform_data, 77 .platform_data = &scif1_platform_data,
73 }, 78 },
74}; 79};
75 80
@@ -369,6 +374,8 @@ static struct platform_device tmu2_device = {
369}; 374};
370 375
371static struct platform_device *sh7720_devices[] __initdata = { 376static struct platform_device *sh7720_devices[] __initdata = {
377 &scif0_device,
378 &scif1_device,
372 &cmt0_device, 379 &cmt0_device,
373 &cmt1_device, 380 &cmt1_device,
374 &cmt2_device, 381 &cmt2_device,
@@ -378,7 +385,6 @@ static struct platform_device *sh7720_devices[] __initdata = {
378 &tmu1_device, 385 &tmu1_device,
379 &tmu2_device, 386 &tmu2_device,
380 &rtc_device, 387 &rtc_device,
381 &sci_device,
382 &usb_ohci_device, 388 &usb_ohci_device,
383 &usbf_device, 389 &usbf_device,
384}; 390};
@@ -391,6 +397,8 @@ static int __init sh7720_devices_setup(void)
391arch_initcall(sh7720_devices_setup); 397arch_initcall(sh7720_devices_setup);
392 398
393static struct platform_device *sh7720_early_devices[] __initdata = { 399static struct platform_device *sh7720_early_devices[] __initdata = {
400 &scif0_device,
401 &scif1_device,
394 &cmt0_device, 402 &cmt0_device,
395 &cmt1_device, 403 &cmt1_device,
396 &cmt2_device, 404 &cmt2_device,
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index 203b18347b83..3a1dbc709831 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -9,6 +9,11 @@ obj-$(CONFIG_HIBERNATION) += $(addprefix ../sh3/, swsusp.o)
9obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o 9obj-$(CONFIG_SH_FPU) += fpu.o softfloat.o
10obj-$(CONFIG_SH_STORE_QUEUES) += sq.o 10obj-$(CONFIG_SH_STORE_QUEUES) += sq.o
11 11
12# Perf events
13perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o
14perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o
15perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o
16
12# CPU subtype setup 17# CPU subtype setup
13obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o 18obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o 19obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o
@@ -27,4 +32,5 @@ endif
27# Additional clocks by subtype 32# Additional clocks by subtype
28clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o 33clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
29 34
30obj-y += $(clock-y) 35obj-y += $(clock-y)
36obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 21421e34e7d5..6b80850294da 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -23,7 +23,7 @@ static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
23 23
24static unsigned long emi_clk_recalc(struct clk *clk) 24static unsigned long emi_clk_recalc(struct clk *clk)
25{ 25{
26 int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007; 26 int idx = __raw_readl(CPG2_FRQCR3) & 0x0007;
27 return clk->parent->rate / frqcr3_divisors[idx]; 27 return clk->parent->rate / frqcr3_divisors[idx];
28} 28}
29 29
@@ -52,7 +52,7 @@ static struct clk sh4202_emi_clk = {
52 52
53static unsigned long femi_clk_recalc(struct clk *clk) 53static unsigned long femi_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007; 55 int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007;
56 return clk->parent->rate / frqcr3_divisors[idx]; 56 return clk->parent->rate / frqcr3_divisors[idx];
57} 57}
58 58
@@ -92,7 +92,7 @@ static void shoc_clk_init(struct clk *clk)
92 92
93static unsigned long shoc_clk_recalc(struct clk *clk) 93static unsigned long shoc_clk_recalc(struct clk *clk)
94{ 94{
95 int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007; 95 int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007;
96 return clk->parent->rate / frqcr3_divisors[idx]; 96 return clk->parent->rate / frqcr3_divisors[idx];
97} 97}
98 98
@@ -122,10 +122,10 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
122 122
123 tmp = frqcr3_lookup(clk, rate); 123 tmp = frqcr3_lookup(clk, rate);
124 124
125 frqcr3 = ctrl_inl(CPG2_FRQCR3); 125 frqcr3 = __raw_readl(CPG2_FRQCR3);
126 frqcr3 &= ~(0x0007 << 6); 126 frqcr3 &= ~(0x0007 << 6);
127 frqcr3 |= tmp << 6; 127 frqcr3 |= tmp << 6;
128 ctrl_outl(frqcr3, CPG2_FRQCR3); 128 __raw_writel(frqcr3, CPG2_FRQCR3);
129 129
130 clk->rate = clk->parent->rate / frqcr3_divisors[tmp]; 130 clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
131 131
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index 73294d9cd049..5add75c1f539 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -28,7 +28,7 @@ static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
28 28
29static void master_clk_init(struct clk *clk) 29static void master_clk_init(struct clk *clk)
30{ 30{
31 clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007]; 31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];
32} 32}
33 33
34static struct clk_ops sh4_master_clk_ops = { 34static struct clk_ops sh4_master_clk_ops = {
@@ -37,7 +37,7 @@ static struct clk_ops sh4_master_clk_ops = {
37 37
38static unsigned long module_clk_recalc(struct clk *clk) 38static unsigned long module_clk_recalc(struct clk *clk)
39{ 39{
40 int idx = (ctrl_inw(FRQCR) & 0x0007); 40 int idx = (__raw_readw(FRQCR) & 0x0007);
41 return clk->parent->rate / pfc_divisors[idx]; 41 return clk->parent->rate / pfc_divisors[idx];
42} 42}
43 43
@@ -47,7 +47,7 @@ static struct clk_ops sh4_module_clk_ops = {
47 47
48static unsigned long bus_clk_recalc(struct clk *clk) 48static unsigned long bus_clk_recalc(struct clk *clk)
49{ 49{
50 int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007; 50 int idx = (__raw_readw(FRQCR) >> 3) & 0x0007;
51 return clk->parent->rate / bfc_divisors[idx]; 51 return clk->parent->rate / bfc_divisors[idx];
52} 52}
53 53
@@ -57,7 +57,7 @@ static struct clk_ops sh4_bus_clk_ops = {
57 57
58static unsigned long cpu_clk_recalc(struct clk *clk) 58static unsigned long cpu_clk_recalc(struct clk *clk)
59{ 59{
60 int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007; 60 int idx = (__raw_readw(FRQCR) >> 6) & 0x0007;
61 return clk->parent->rate / ifc_divisors[idx]; 61 return clk->parent->rate / ifc_divisors[idx];
62} 62}
63 63
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index e3ea5411da6d..447482d7f65e 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -41,13 +41,11 @@ static unsigned int fpu_exception_flags;
41 41
42/* 42/*
43 * Save FPU registers onto task structure. 43 * Save FPU registers onto task structure.
44 * Assume called with FPU enabled (SR.FD=0).
45 */ 44 */
46void save_fpu(struct task_struct *tsk, struct pt_regs *regs) 45void save_fpu(struct task_struct *tsk)
47{ 46{
48 unsigned long dummy; 47 unsigned long dummy;
49 48
50 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
51 enable_fpu(); 49 enable_fpu();
52 asm volatile ("sts.l fpul, @-%0\n\t" 50 asm volatile ("sts.l fpul, @-%0\n\t"
53 "sts.l fpscr, @-%0\n\t" 51 "sts.l fpscr, @-%0\n\t"
@@ -87,15 +85,14 @@ void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
87 "fmov.s fr1, @-%0\n\t" 85 "fmov.s fr1, @-%0\n\t"
88 "fmov.s fr0, @-%0\n\t" 86 "fmov.s fr0, @-%0\n\t"
89 "lds %3, fpscr\n\t":"=r" (dummy) 87 "lds %3, fpscr\n\t":"=r" (dummy)
90 :"0"((char *)(&tsk->thread.fpu.hard.status)), 88 :"0"((char *)(&tsk->thread.xstate->hardfpu.status)),
91 "r"(FPSCR_RCHG), "r"(FPSCR_INIT) 89 "r"(FPSCR_RCHG), "r"(FPSCR_INIT)
92 :"memory"); 90 :"memory");
93 91
94 disable_fpu(); 92 disable_fpu();
95 release_fpu(regs);
96} 93}
97 94
98static void restore_fpu(struct task_struct *tsk) 95void restore_fpu(struct task_struct *tsk)
99{ 96{
100 unsigned long dummy; 97 unsigned long dummy;
101 98
@@ -138,62 +135,11 @@ static void restore_fpu(struct task_struct *tsk)
138 "lds.l @%0+, fpscr\n\t" 135 "lds.l @%0+, fpscr\n\t"
139 "lds.l @%0+, fpul\n\t" 136 "lds.l @%0+, fpul\n\t"
140 :"=r" (dummy) 137 :"=r" (dummy)
141 :"0"(&tsk->thread.fpu), "r"(FPSCR_RCHG) 138 :"0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
142 :"memory"); 139 :"memory");
143 disable_fpu(); 140 disable_fpu();
144} 141}
145 142
146/*
147 * Load the FPU with signalling NANS. This bit pattern we're using
148 * has the property that no matter wether considered as single or as
149 * double precision represents signaling NANS.
150 */
151
152static void fpu_init(void)
153{
154 enable_fpu();
155 asm volatile ( "lds %0, fpul\n\t"
156 "lds %1, fpscr\n\t"
157 "fsts fpul, fr0\n\t"
158 "fsts fpul, fr1\n\t"
159 "fsts fpul, fr2\n\t"
160 "fsts fpul, fr3\n\t"
161 "fsts fpul, fr4\n\t"
162 "fsts fpul, fr5\n\t"
163 "fsts fpul, fr6\n\t"
164 "fsts fpul, fr7\n\t"
165 "fsts fpul, fr8\n\t"
166 "fsts fpul, fr9\n\t"
167 "fsts fpul, fr10\n\t"
168 "fsts fpul, fr11\n\t"
169 "fsts fpul, fr12\n\t"
170 "fsts fpul, fr13\n\t"
171 "fsts fpul, fr14\n\t"
172 "fsts fpul, fr15\n\t"
173 "frchg\n\t"
174 "fsts fpul, fr0\n\t"
175 "fsts fpul, fr1\n\t"
176 "fsts fpul, fr2\n\t"
177 "fsts fpul, fr3\n\t"
178 "fsts fpul, fr4\n\t"
179 "fsts fpul, fr5\n\t"
180 "fsts fpul, fr6\n\t"
181 "fsts fpul, fr7\n\t"
182 "fsts fpul, fr8\n\t"
183 "fsts fpul, fr9\n\t"
184 "fsts fpul, fr10\n\t"
185 "fsts fpul, fr11\n\t"
186 "fsts fpul, fr12\n\t"
187 "fsts fpul, fr13\n\t"
188 "fsts fpul, fr14\n\t"
189 "fsts fpul, fr15\n\t"
190 "frchg\n\t"
191 "lds %2, fpscr\n\t"
192 : /* no output */
193 :"r" (0), "r"(FPSCR_RCHG), "r"(FPSCR_INIT));
194 disable_fpu();
195}
196
197/** 143/**
198 * denormal_to_double - Given denormalized float number, 144 * denormal_to_double - Given denormalized float number,
199 * store double float 145 * store double float
@@ -285,10 +231,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
285 /* fcnvsd */ 231 /* fcnvsd */
286 struct task_struct *tsk = current; 232 struct task_struct *tsk = current;
287 233
288 save_fpu(tsk, regs); 234 if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR))
289 if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR))
290 /* FPU error */ 235 /* FPU error */
291 denormal_to_double(&tsk->thread.fpu.hard, 236 denormal_to_double(&tsk->thread.xstate->hardfpu,
292 (finsn >> 8) & 0xf); 237 (finsn >> 8) & 0xf);
293 else 238 else
294 return 0; 239 return 0;
@@ -304,9 +249,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
304 249
305 n = (finsn >> 8) & 0xf; 250 n = (finsn >> 8) & 0xf;
306 m = (finsn >> 4) & 0xf; 251 m = (finsn >> 4) & 0xf;
307 hx = tsk->thread.fpu.hard.fp_regs[n]; 252 hx = tsk->thread.xstate->hardfpu.fp_regs[n];
308 hy = tsk->thread.fpu.hard.fp_regs[m]; 253 hy = tsk->thread.xstate->hardfpu.fp_regs[m];
309 fpscr = tsk->thread.fpu.hard.fpscr; 254 fpscr = tsk->thread.xstate->hardfpu.fpscr;
310 prec = fpscr & FPSCR_DBL_PRECISION; 255 prec = fpscr & FPSCR_DBL_PRECISION;
311 256
312 if ((fpscr & FPSCR_CAUSE_ERROR) 257 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -316,18 +261,18 @@ static int ieee_fpe_handler(struct pt_regs *regs)
316 261
317 /* FPU error because of denormal (doubles) */ 262 /* FPU error because of denormal (doubles) */
318 llx = ((long long)hx << 32) 263 llx = ((long long)hx << 32)
319 | tsk->thread.fpu.hard.fp_regs[n + 1]; 264 | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
320 lly = ((long long)hy << 32) 265 lly = ((long long)hy << 32)
321 | tsk->thread.fpu.hard.fp_regs[m + 1]; 266 | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
322 llx = float64_mul(llx, lly); 267 llx = float64_mul(llx, lly);
323 tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; 268 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
324 tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff; 269 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
325 } else if ((fpscr & FPSCR_CAUSE_ERROR) 270 } else if ((fpscr & FPSCR_CAUSE_ERROR)
326 && (!prec && ((hx & 0x7fffffff) < 0x00800000 271 && (!prec && ((hx & 0x7fffffff) < 0x00800000
327 || (hy & 0x7fffffff) < 0x00800000))) { 272 || (hy & 0x7fffffff) < 0x00800000))) {
328 /* FPU error because of denormal (floats) */ 273 /* FPU error because of denormal (floats) */
329 hx = float32_mul(hx, hy); 274 hx = float32_mul(hx, hy);
330 tsk->thread.fpu.hard.fp_regs[n] = hx; 275 tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
331 } else 276 } else
332 return 0; 277 return 0;
333 278
@@ -342,9 +287,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
342 287
343 n = (finsn >> 8) & 0xf; 288 n = (finsn >> 8) & 0xf;
344 m = (finsn >> 4) & 0xf; 289 m = (finsn >> 4) & 0xf;
345 hx = tsk->thread.fpu.hard.fp_regs[n]; 290 hx = tsk->thread.xstate->hardfpu.fp_regs[n];
346 hy = tsk->thread.fpu.hard.fp_regs[m]; 291 hy = tsk->thread.xstate->hardfpu.fp_regs[m];
347 fpscr = tsk->thread.fpu.hard.fpscr; 292 fpscr = tsk->thread.xstate->hardfpu.fpscr;
348 prec = fpscr & FPSCR_DBL_PRECISION; 293 prec = fpscr & FPSCR_DBL_PRECISION;
349 294
350 if ((fpscr & FPSCR_CAUSE_ERROR) 295 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -354,15 +299,15 @@ static int ieee_fpe_handler(struct pt_regs *regs)
354 299
355 /* FPU error because of denormal (doubles) */ 300 /* FPU error because of denormal (doubles) */
356 llx = ((long long)hx << 32) 301 llx = ((long long)hx << 32)
357 | tsk->thread.fpu.hard.fp_regs[n + 1]; 302 | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
358 lly = ((long long)hy << 32) 303 lly = ((long long)hy << 32)
359 | tsk->thread.fpu.hard.fp_regs[m + 1]; 304 | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
360 if ((finsn & 0xf00f) == 0xf000) 305 if ((finsn & 0xf00f) == 0xf000)
361 llx = float64_add(llx, lly); 306 llx = float64_add(llx, lly);
362 else 307 else
363 llx = float64_sub(llx, lly); 308 llx = float64_sub(llx, lly);
364 tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; 309 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
365 tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff; 310 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
366 } else if ((fpscr & FPSCR_CAUSE_ERROR) 311 } else if ((fpscr & FPSCR_CAUSE_ERROR)
367 && (!prec && ((hx & 0x7fffffff) < 0x00800000 312 && (!prec && ((hx & 0x7fffffff) < 0x00800000
368 || (hy & 0x7fffffff) < 0x00800000))) { 313 || (hy & 0x7fffffff) < 0x00800000))) {
@@ -371,7 +316,7 @@ static int ieee_fpe_handler(struct pt_regs *regs)
371 hx = float32_add(hx, hy); 316 hx = float32_add(hx, hy);
372 else 317 else
373 hx = float32_sub(hx, hy); 318 hx = float32_sub(hx, hy);
374 tsk->thread.fpu.hard.fp_regs[n] = hx; 319 tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
375 } else 320 } else
376 return 0; 321 return 0;
377 322
@@ -386,9 +331,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
386 331
387 n = (finsn >> 8) & 0xf; 332 n = (finsn >> 8) & 0xf;
388 m = (finsn >> 4) & 0xf; 333 m = (finsn >> 4) & 0xf;
389 hx = tsk->thread.fpu.hard.fp_regs[n]; 334 hx = tsk->thread.xstate->hardfpu.fp_regs[n];
390 hy = tsk->thread.fpu.hard.fp_regs[m]; 335 hy = tsk->thread.xstate->hardfpu.fp_regs[m];
391 fpscr = tsk->thread.fpu.hard.fpscr; 336 fpscr = tsk->thread.xstate->hardfpu.fpscr;
392 prec = fpscr & FPSCR_DBL_PRECISION; 337 prec = fpscr & FPSCR_DBL_PRECISION;
393 338
394 if ((fpscr & FPSCR_CAUSE_ERROR) 339 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -398,20 +343,20 @@ static int ieee_fpe_handler(struct pt_regs *regs)
398 343
399 /* FPU error because of denormal (doubles) */ 344 /* FPU error because of denormal (doubles) */
400 llx = ((long long)hx << 32) 345 llx = ((long long)hx << 32)
401 | tsk->thread.fpu.hard.fp_regs[n + 1]; 346 | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
402 lly = ((long long)hy << 32) 347 lly = ((long long)hy << 32)
403 | tsk->thread.fpu.hard.fp_regs[m + 1]; 348 | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
404 349
405 llx = float64_div(llx, lly); 350 llx = float64_div(llx, lly);
406 351
407 tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; 352 tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
408 tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff; 353 tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
409 } else if ((fpscr & FPSCR_CAUSE_ERROR) 354 } else if ((fpscr & FPSCR_CAUSE_ERROR)
410 && (!prec && ((hx & 0x7fffffff) < 0x00800000 355 && (!prec && ((hx & 0x7fffffff) < 0x00800000
411 || (hy & 0x7fffffff) < 0x00800000))) { 356 || (hy & 0x7fffffff) < 0x00800000))) {
412 /* FPU error because of denormal (floats) */ 357 /* FPU error because of denormal (floats) */
413 hx = float32_div(hx, hy); 358 hx = float32_div(hx, hy);
414 tsk->thread.fpu.hard.fp_regs[n] = hx; 359 tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
415 } else 360 } else
416 return 0; 361 return 0;
417 362
@@ -424,17 +369,17 @@ static int ieee_fpe_handler(struct pt_regs *regs)
424 unsigned int hx; 369 unsigned int hx;
425 370
426 m = (finsn >> 8) & 0x7; 371 m = (finsn >> 8) & 0x7;
427 hx = tsk->thread.fpu.hard.fp_regs[m]; 372 hx = tsk->thread.xstate->hardfpu.fp_regs[m];
428 373
429 if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR) 374 if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR)
430 && ((hx & 0x7fffffff) < 0x00100000)) { 375 && ((hx & 0x7fffffff) < 0x00100000)) {
431 /* subnormal double to float conversion */ 376 /* subnormal double to float conversion */
432 long long llx; 377 long long llx;
433 378
434 llx = ((long long)tsk->thread.fpu.hard.fp_regs[m] << 32) 379 llx = ((long long)tsk->thread.xstate->hardfpu.fp_regs[m] << 32)
435 | tsk->thread.fpu.hard.fp_regs[m + 1]; 380 | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
436 381
437 tsk->thread.fpu.hard.fpul = float64_to_float32(llx); 382 tsk->thread.xstate->hardfpu.fpul = float64_to_float32(llx);
438 } else 383 } else
439 return 0; 384 return 0;
440 385
@@ -453,7 +398,7 @@ void float_raise(unsigned int flags)
453int float_rounding_mode(void) 398int float_rounding_mode(void)
454{ 399{
455 struct task_struct *tsk = current; 400 struct task_struct *tsk = current;
456 int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.fpu.hard.fpscr); 401 int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.xstate->hardfpu.fpscr);
457 return roundingMode; 402 return roundingMode;
458} 403}
459 404
@@ -462,19 +407,19 @@ BUILD_TRAP_HANDLER(fpu_error)
462 struct task_struct *tsk = current; 407 struct task_struct *tsk = current;
463 TRAP_HANDLER_DECL; 408 TRAP_HANDLER_DECL;
464 409
465 save_fpu(tsk, regs); 410 __unlazy_fpu(tsk, regs);
466 fpu_exception_flags = 0; 411 fpu_exception_flags = 0;
467 if (ieee_fpe_handler(regs)) { 412 if (ieee_fpe_handler(regs)) {
468 tsk->thread.fpu.hard.fpscr &= 413 tsk->thread.xstate->hardfpu.fpscr &=
469 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK); 414 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
470 tsk->thread.fpu.hard.fpscr |= fpu_exception_flags; 415 tsk->thread.xstate->hardfpu.fpscr |= fpu_exception_flags;
471 /* Set the FPSCR flag as well as cause bits - simply 416 /* Set the FPSCR flag as well as cause bits - simply
472 * replicate the cause */ 417 * replicate the cause */
473 tsk->thread.fpu.hard.fpscr |= (fpu_exception_flags >> 10); 418 tsk->thread.xstate->hardfpu.fpscr |= (fpu_exception_flags >> 10);
474 grab_fpu(regs); 419 grab_fpu(regs);
475 restore_fpu(tsk); 420 restore_fpu(tsk);
476 set_tsk_thread_flag(tsk, TIF_USEDFPU); 421 task_thread_info(tsk)->status |= TS_USEDFPU;
477 if ((((tsk->thread.fpu.hard.fpscr & FPSCR_ENABLE_MASK) >> 7) & 422 if ((((tsk->thread.xstate->hardfpu.fpscr & FPSCR_ENABLE_MASK) >> 7) &
478 (fpu_exception_flags >> 2)) == 0) { 423 (fpu_exception_flags >> 2)) == 0) {
479 return; 424 return;
480 } 425 }
@@ -482,25 +427,3 @@ BUILD_TRAP_HANDLER(fpu_error)
482 427
483 force_sig(SIGFPE, tsk); 428 force_sig(SIGFPE, tsk);
484} 429}
485
486BUILD_TRAP_HANDLER(fpu_state_restore)
487{
488 struct task_struct *tsk = current;
489 TRAP_HANDLER_DECL;
490
491 grab_fpu(regs);
492 if (!user_mode(regs)) {
493 printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
494 return;
495 }
496
497 if (used_math()) {
498 /* Using the FPU again. */
499 restore_fpu(tsk);
500 } else {
501 /* First time FPU user. */
502 fpu_init();
503 set_used_math();
504 }
505 set_tsk_thread_flag(tsk, TIF_USEDFPU);
506}
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
new file mode 100644
index 000000000000..7f9ecc9c2d02
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -0,0 +1,253 @@
1/*
2 * Performance events support for SH7750-style performance counters
3 *
4 * Copyright (C) 2009 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/perf_event.h>
15#include <asm/processor.h>
16
17#define PM_CR_BASE 0xff000084 /* 16-bit */
18#define PM_CTR_BASE 0xff100004 /* 32-bit */
19
20#define PMCR(n) (PM_CR_BASE + ((n) * 0x04))
21#define PMCTRH(n) (PM_CTR_BASE + 0x00 + ((n) * 0x08))
22#define PMCTRL(n) (PM_CTR_BASE + 0x04 + ((n) * 0x08))
23
24#define PMCR_PMM_MASK 0x0000003f
25
26#define PMCR_CLKF 0x00000100
27#define PMCR_PMCLR 0x00002000
28#define PMCR_PMST 0x00004000
29#define PMCR_PMEN 0x00008000
30
31static struct sh_pmu sh7750_pmu;
32
33/*
34 * There are a number of events supported by each counter (33 in total).
35 * Since we have 2 counters, each counter will take the event code as it
36 * corresponds to the PMCR PMM setting. Each counter can be configured
37 * independently.
38 *
39 * Event Code Description
40 * ---------- -----------
41 *
42 * 0x01 Operand read access
43 * 0x02 Operand write access
44 * 0x03 UTLB miss
45 * 0x04 Operand cache read miss
46 * 0x05 Operand cache write miss
47 * 0x06 Instruction fetch (w/ cache)
48 * 0x07 Instruction TLB miss
49 * 0x08 Instruction cache miss
50 * 0x09 All operand accesses
51 * 0x0a All instruction accesses
52 * 0x0b OC RAM operand access
53 * 0x0d On-chip I/O space access
54 * 0x0e Operand access (r/w)
55 * 0x0f Operand cache miss (r/w)
56 * 0x10 Branch instruction
57 * 0x11 Branch taken
58 * 0x12 BSR/BSRF/JSR
59 * 0x13 Instruction execution
60 * 0x14 Instruction execution in parallel
61 * 0x15 FPU Instruction execution
62 * 0x16 Interrupt
63 * 0x17 NMI
64 * 0x18 trapa instruction execution
65 * 0x19 UBCA match
66 * 0x1a UBCB match
67 * 0x21 Instruction cache fill
68 * 0x22 Operand cache fill
69 * 0x23 Elapsed time
70 * 0x24 Pipeline freeze by I-cache miss
71 * 0x25 Pipeline freeze by D-cache miss
72 * 0x27 Pipeline freeze by branch instruction
73 * 0x28 Pipeline freeze by CPU register
74 * 0x29 Pipeline freeze by FPU
75 */
76
77static const int sh7750_general_events[] = {
78 [PERF_COUNT_HW_CPU_CYCLES] = 0x0023,
79 [PERF_COUNT_HW_INSTRUCTIONS] = 0x000a,
80 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0006, /* I-cache */
81 [PERF_COUNT_HW_CACHE_MISSES] = 0x0008, /* I-cache */
82 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0010,
83 [PERF_COUNT_HW_BRANCH_MISSES] = -1,
84 [PERF_COUNT_HW_BUS_CYCLES] = -1,
85};
86
87#define C(x) PERF_COUNT_HW_CACHE_##x
88
89static const int sh7750_cache_events
90 [PERF_COUNT_HW_CACHE_MAX]
91 [PERF_COUNT_HW_CACHE_OP_MAX]
92 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
93{
94 [ C(L1D) ] = {
95 [ C(OP_READ) ] = {
96 [ C(RESULT_ACCESS) ] = 0x0001,
97 [ C(RESULT_MISS) ] = 0x0004,
98 },
99 [ C(OP_WRITE) ] = {
100 [ C(RESULT_ACCESS) ] = 0x0002,
101 [ C(RESULT_MISS) ] = 0x0005,
102 },
103 [ C(OP_PREFETCH) ] = {
104 [ C(RESULT_ACCESS) ] = 0,
105 [ C(RESULT_MISS) ] = 0,
106 },
107 },
108
109 [ C(L1I) ] = {
110 [ C(OP_READ) ] = {
111 [ C(RESULT_ACCESS) ] = 0x0006,
112 [ C(RESULT_MISS) ] = 0x0008,
113 },
114 [ C(OP_WRITE) ] = {
115 [ C(RESULT_ACCESS) ] = -1,
116 [ C(RESULT_MISS) ] = -1,
117 },
118 [ C(OP_PREFETCH) ] = {
119 [ C(RESULT_ACCESS) ] = 0,
120 [ C(RESULT_MISS) ] = 0,
121 },
122 },
123
124 [ C(LL) ] = {
125 [ C(OP_READ) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
127 [ C(RESULT_MISS) ] = 0,
128 },
129 [ C(OP_WRITE) ] = {
130 [ C(RESULT_ACCESS) ] = 0,
131 [ C(RESULT_MISS) ] = 0,
132 },
133 [ C(OP_PREFETCH) ] = {
134 [ C(RESULT_ACCESS) ] = 0,
135 [ C(RESULT_MISS) ] = 0,
136 },
137 },
138
139 [ C(DTLB) ] = {
140 [ C(OP_READ) ] = {
141 [ C(RESULT_ACCESS) ] = 0,
142 [ C(RESULT_MISS) ] = 0x0003,
143 },
144 [ C(OP_WRITE) ] = {
145 [ C(RESULT_ACCESS) ] = 0,
146 [ C(RESULT_MISS) ] = 0,
147 },
148 [ C(OP_PREFETCH) ] = {
149 [ C(RESULT_ACCESS) ] = 0,
150 [ C(RESULT_MISS) ] = 0,
151 },
152 },
153
154 [ C(ITLB) ] = {
155 [ C(OP_READ) ] = {
156 [ C(RESULT_ACCESS) ] = 0,
157 [ C(RESULT_MISS) ] = 0x0007,
158 },
159 [ C(OP_WRITE) ] = {
160 [ C(RESULT_ACCESS) ] = -1,
161 [ C(RESULT_MISS) ] = -1,
162 },
163 [ C(OP_PREFETCH) ] = {
164 [ C(RESULT_ACCESS) ] = -1,
165 [ C(RESULT_MISS) ] = -1,
166 },
167 },
168
169 [ C(BPU) ] = {
170 [ C(OP_READ) ] = {
171 [ C(RESULT_ACCESS) ] = -1,
172 [ C(RESULT_MISS) ] = -1,
173 },
174 [ C(OP_WRITE) ] = {
175 [ C(RESULT_ACCESS) ] = -1,
176 [ C(RESULT_MISS) ] = -1,
177 },
178 [ C(OP_PREFETCH) ] = {
179 [ C(RESULT_ACCESS) ] = -1,
180 [ C(RESULT_MISS) ] = -1,
181 },
182 },
183};
184
185static int sh7750_event_map(int event)
186{
187 return sh7750_general_events[event];
188}
189
190static u64 sh7750_pmu_read(int idx)
191{
192 return (u64)((u64)(__raw_readl(PMCTRH(idx)) & 0xffff) << 32) |
193 __raw_readl(PMCTRL(idx));
194}
195
196static void sh7750_pmu_disable(struct hw_perf_event *hwc, int idx)
197{
198 unsigned int tmp;
199
200 tmp = __raw_readw(PMCR(idx));
201 tmp &= ~(PMCR_PMM_MASK | PMCR_PMEN);
202 __raw_writew(tmp, PMCR(idx));
203}
204
205static void sh7750_pmu_enable(struct hw_perf_event *hwc, int idx)
206{
207 __raw_writew(__raw_readw(PMCR(idx)) | PMCR_PMCLR, PMCR(idx));
208 __raw_writew(hwc->config | PMCR_PMEN | PMCR_PMST, PMCR(idx));
209}
210
211static void sh7750_pmu_disable_all(void)
212{
213 int i;
214
215 for (i = 0; i < sh7750_pmu.num_events; i++)
216 __raw_writew(__raw_readw(PMCR(i)) & ~PMCR_PMEN, PMCR(i));
217}
218
219static void sh7750_pmu_enable_all(void)
220{
221 int i;
222
223 for (i = 0; i < sh7750_pmu.num_events; i++)
224 __raw_writew(__raw_readw(PMCR(i)) | PMCR_PMEN, PMCR(i));
225}
226
227static struct sh_pmu sh7750_pmu = {
228 .name = "SH7750",
229 .num_events = 2,
230 .event_map = sh7750_event_map,
231 .max_events = ARRAY_SIZE(sh7750_general_events),
232 .raw_event_mask = PMCR_PMM_MASK,
233 .cache_events = &sh7750_cache_events,
234 .read = sh7750_pmu_read,
235 .disable = sh7750_pmu_disable,
236 .enable = sh7750_pmu_enable,
237 .disable_all = sh7750_pmu_disable_all,
238 .enable_all = sh7750_pmu_enable_all,
239};
240
241static int __init sh7750_pmu_init(void)
242{
243 /*
244 * Make sure this CPU actually has perf counters.
245 */
246 if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) {
247 pr_notice("HW perf events unsupported, software events only.\n");
248 return -ENODEV;
249 }
250
251 return register_sh_pmu(&sh7750_pmu);
252}
253arch_initcall(sh7750_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index d36f0c45f55f..822977a06d84 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -28,9 +28,9 @@ int __init detect_cpu_and_cache_system(void)
28 [9] = (1 << 16) 28 [9] = (1 << 16)
29 }; 29 };
30 30
31 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff; 31 pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
32 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff; 32 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
33 cvr = (ctrl_inl(CCN_CVR)); 33 cvr = (__raw_readl(CCN_CVR));
34 34
35 /* 35 /*
36 * Setup some sane SH-4 defaults for the icache 36 * Setup some sane SH-4 defaults for the icache
@@ -71,11 +71,11 @@ int __init detect_cpu_and_cache_system(void)
71 boot_cpu_data.dcache.ways = 4; 71 boot_cpu_data.dcache.ways = 4;
72 } else { 72 } else {
73 /* And some SH-4 defaults.. */ 73 /* And some SH-4 defaults.. */
74 boot_cpu_data.flags |= CPU_HAS_PTEA; 74 boot_cpu_data.flags |= CPU_HAS_PTEA | CPU_HAS_FPU;
75 boot_cpu_data.family = CPU_FAMILY_SH4; 75 boot_cpu_data.family = CPU_FAMILY_SH4;
76 } 76 }
77 77
78 /* FPU detection works for everyone */ 78 /* FPU detection works for almost everyone */
79 if ((cvr & 0x20000000)) 79 if ((cvr & 0x20000000))
80 boot_cpu_data.flags |= CPU_HAS_FPU; 80 boot_cpu_data.flags |= CPU_HAS_FPU;
81 81
@@ -124,6 +124,7 @@ int __init detect_cpu_and_cache_system(void)
124 boot_cpu_data.type = CPU_SH7785; 124 boot_cpu_data.type = CPU_SH7785;
125 break; 125 break;
126 case 0x4004: 126 case 0x4004:
127 case 0x4005:
127 boot_cpu_data.type = CPU_SH7786; 128 boot_cpu_data.type = CPU_SH7786;
128 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE; 129 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
129 break; 130 break;
@@ -160,6 +161,7 @@ int __init detect_cpu_and_cache_system(void)
160 break; 161 break;
161 case 0x700: 162 case 0x700:
162 boot_cpu_data.type = CPU_SH4_501; 163 boot_cpu_data.type = CPU_SH4_501;
164 boot_cpu_data.flags &= ~CPU_HAS_FPU;
163 boot_cpu_data.icache.ways = 2; 165 boot_cpu_data.icache.ways = 2;
164 boot_cpu_data.dcache.ways = 2; 166 boot_cpu_data.dcache.ways = 2;
165 break; 167 break;
@@ -227,7 +229,7 @@ int __init detect_cpu_and_cache_system(void)
227 * Size calculation is much more sensible 229 * Size calculation is much more sensible
228 * than it is for the L1. 230 * than it is for the L1.
229 * 231 *
230 * Sizes are 128KB, 258KB, 512KB, and 1MB. 232 * Sizes are 128KB, 256KB, 512KB, and 1MB.
231 */ 233 */
232 size = (cvr & 0xf) << 17; 234 size = (cvr & 0xf) << 17;
233 235
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index de4827df19aa..b9b7e10ad68f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -15,22 +15,18 @@
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18static struct plat_sci_port sci_platform_data[] = { 18static struct plat_sci_port scif0_platform_data = {
19 { 19 .mapbase = 0xffe80000,
20 .mapbase = 0xffe80000, 20 .flags = UPF_BOOT_AUTOCONF,
21 .flags = UPF_BOOT_AUTOCONF, 21 .type = PORT_SCIF,
22 .type = PORT_SCIF, 22 .irqs = { 40, 41, 43, 42 },
23 .irqs = { 40, 41, 43, 42 },
24 }, {
25 .flags = 0,
26 }
27}; 23};
28 24
29static struct platform_device sci_device = { 25static struct platform_device scif0_device = {
30 .name = "sh-sci", 26 .name = "sh-sci",
31 .id = -1, 27 .id = 0,
32 .dev = { 28 .dev = {
33 .platform_data = sci_platform_data, 29 .platform_data = &scif0_platform_data,
34 }, 30 },
35}; 31};
36 32
@@ -127,7 +123,7 @@ static struct platform_device tmu2_device = {
127}; 123};
128 124
129static struct platform_device *sh4202_devices[] __initdata = { 125static struct platform_device *sh4202_devices[] __initdata = {
130 &sci_device, 126 &scif0_device,
131 &tmu0_device, 127 &tmu0_device,
132 &tmu1_device, 128 &tmu1_device,
133 &tmu2_device, 129 &tmu2_device,
@@ -141,6 +137,7 @@ static int __init sh4202_devices_setup(void)
141arch_initcall(sh4202_devices_setup); 137arch_initcall(sh4202_devices_setup);
142 138
143static struct platform_device *sh4202_early_devices[] __initdata = { 139static struct platform_device *sh4202_early_devices[] __initdata = {
140 &scif0_device,
144 &tmu0_device, 141 &tmu0_device,
145 &tmu1_device, 142 &tmu1_device,
146 &tmu2_device, 143 &tmu2_device,
@@ -201,7 +198,7 @@ void __init plat_irq_setup_pins(int mode)
201{ 198{
202 switch (mode) { 199 switch (mode) {
203 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 200 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
204 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 201 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
205 register_intc_controller(&intc_desc_irlm); 202 register_intc_controller(&intc_desc_irlm);
206 break; 203 break;
207 default: 204 default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 1b8b122e8f3d..ffd79e57254f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -35,29 +35,33 @@ static struct platform_device rtc_device = {
35 .resource = rtc_resources, 35 .resource = rtc_resources,
36}; 36};
37 37
38static struct plat_sci_port sci_platform_data[] = { 38static struct plat_sci_port scif0_platform_data = {
39 { 39 .mapbase = 0xffe00000,
40#ifndef CONFIG_SH_RTS7751R2D 40 .flags = UPF_BOOT_AUTOCONF,
41 .mapbase = 0xffe00000, 41 .type = PORT_SCI,
42 .flags = UPF_BOOT_AUTOCONF, 42 .irqs = { 23, 23, 23, 0 },
43 .type = PORT_SCI,
44 .irqs = { 23, 23, 23, 0 },
45 }, {
46#endif
47 .mapbase = 0xffe80000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIF,
50 .irqs = { 40, 40, 40, 40 },
51 }, {
52 .flags = 0,
53 }
54}; 43};
55 44
56static struct platform_device sci_device = { 45static struct platform_device scif0_device = {
57 .name = "sh-sci", 46 .name = "sh-sci",
58 .id = -1, 47 .id = 0,
48 .dev = {
49 .platform_data = &scif0_platform_data,
50 },
51};
52
53static struct plat_sci_port scif1_platform_data = {
54 .mapbase = 0xffe80000,
55 .flags = UPF_BOOT_AUTOCONF,
56 .type = PORT_SCIF,
57 .irqs = { 40, 40, 40, 40 },
58};
59
60static struct platform_device scif1_device = {
61 .name = "sh-sci",
62 .id = 1,
59 .dev = { 63 .dev = {
60 .platform_data = sci_platform_data, 64 .platform_data = &scif1_platform_data,
61 }, 65 },
62}; 66};
63 67
@@ -221,8 +225,9 @@ static struct platform_device tmu4_device = {
221#endif 225#endif
222 226
223static struct platform_device *sh7750_devices[] __initdata = { 227static struct platform_device *sh7750_devices[] __initdata = {
228 &scif0_device,
229 &scif1_device,
224 &rtc_device, 230 &rtc_device,
225 &sci_device,
226 &tmu0_device, 231 &tmu0_device,
227 &tmu1_device, 232 &tmu1_device,
228 &tmu2_device, 233 &tmu2_device,
@@ -242,6 +247,8 @@ static int __init sh7750_devices_setup(void)
242arch_initcall(sh7750_devices_setup); 247arch_initcall(sh7750_devices_setup);
243 248
244static struct platform_device *sh7750_early_devices[] __initdata = { 249static struct platform_device *sh7750_early_devices[] __initdata = {
250 &scif0_device,
251 &scif1_device,
245 &tmu0_device, 252 &tmu0_device,
246 &tmu1_device, 253 &tmu1_device,
247 &tmu2_device, 254 &tmu2_device,
@@ -435,7 +442,7 @@ void __init plat_irq_setup_pins(int mode)
435 442
436 switch (mode) { 443 switch (mode) {
437 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 444 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
438 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 445 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
439 register_intc_controller(&intc_desc_irlm); 446 register_intc_controller(&intc_desc_irlm);
440 break; 447 break;
441 default: 448 default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 7fbb7be9284c..a16eb3656f4b 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -126,37 +126,63 @@ static struct intc_vect vectors_irq[] __initdata = {
126static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, 126static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
127 mask_registers, prio_registers, NULL); 127 mask_registers, prio_registers, NULL);
128 128
129static struct plat_sci_port sci_platform_data[] = { 129static struct plat_sci_port scif0_platform_data = {
130 { 130 .mapbase = 0xfe600000,
131 .mapbase = 0xfe600000, 131 .flags = UPF_BOOT_AUTOCONF,
132 .flags = UPF_BOOT_AUTOCONF, 132 .type = PORT_SCIF,
133 .type = PORT_SCIF, 133 .irqs = { 52, 53, 55, 54 },
134 .irqs = { 52, 53, 55, 54 }, 134};
135 }, { 135
136 .mapbase = 0xfe610000, 136static struct platform_device scif0_device = {
137 .flags = UPF_BOOT_AUTOCONF, 137 .name = "sh-sci",
138 .type = PORT_SCIF, 138 .id = 0,
139 .irqs = { 72, 73, 75, 74 }, 139 .dev = {
140 }, { 140 .platform_data = &scif0_platform_data,
141 .mapbase = 0xfe620000, 141 },
142 .flags = UPF_BOOT_AUTOCONF, 142};
143 .type = PORT_SCIF, 143
144 .irqs = { 76, 77, 79, 78 }, 144static struct plat_sci_port scif1_platform_data = {
145 }, { 145 .mapbase = 0xfe610000,
146 .mapbase = 0xfe480000, 146 .flags = UPF_BOOT_AUTOCONF,
147 .flags = UPF_BOOT_AUTOCONF, 147 .type = PORT_SCIF,
148 .type = PORT_SCI, 148 .irqs = { 72, 73, 75, 74 },
149 .irqs = { 80, 81, 82, 0 }, 149};
150 }, { 150
151 .flags = 0, 151static struct platform_device scif1_device = {
152 } 152 .name = "sh-sci",
153 .id = 1,
154 .dev = {
155 .platform_data = &scif1_platform_data,
156 },
157};
158
159static struct plat_sci_port scif2_platform_data = {
160 .mapbase = 0xfe620000,
161 .flags = UPF_BOOT_AUTOCONF,
162 .type = PORT_SCIF,
163 .irqs = { 76, 77, 79, 78 },
164};
165
166static struct platform_device scif2_device = {
167 .name = "sh-sci",
168 .id = 2,
169 .dev = {
170 .platform_data = &scif2_platform_data,
171 },
172};
173
174static struct plat_sci_port scif3_platform_data = {
175 .mapbase = 0xfe480000,
176 .flags = UPF_BOOT_AUTOCONF,
177 .type = PORT_SCI,
178 .irqs = { 80, 81, 82, 0 },
153}; 179};
154 180
155static struct platform_device sci_device = { 181static struct platform_device scif3_device = {
156 .name = "sh-sci", 182 .name = "sh-sci",
157 .id = -1, 183 .id = 3,
158 .dev = { 184 .dev = {
159 .platform_data = sci_platform_data, 185 .platform_data = &scif3_platform_data,
160 }, 186 },
161}; 187};
162 188
@@ -254,7 +280,10 @@ static struct platform_device tmu2_device = {
254 280
255 281
256static struct platform_device *sh7760_devices[] __initdata = { 282static struct platform_device *sh7760_devices[] __initdata = {
257 &sci_device, 283 &scif0_device,
284 &scif1_device,
285 &scif2_device,
286 &scif3_device,
258 &tmu0_device, 287 &tmu0_device,
259 &tmu1_device, 288 &tmu1_device,
260 &tmu2_device, 289 &tmu2_device,
@@ -268,6 +297,10 @@ static int __init sh7760_devices_setup(void)
268arch_initcall(sh7760_devices_setup); 297arch_initcall(sh7760_devices_setup);
269 298
270static struct platform_device *sh7760_early_devices[] __initdata = { 299static struct platform_device *sh7760_early_devices[] __initdata = {
300 &scif0_device,
301 &scif1_device,
302 &scif2_device,
303 &scif3_device,
271 &tmu0_device, 304 &tmu0_device,
272 &tmu1_device, 305 &tmu1_device,
273 &tmu2_device, 306 &tmu2_device,
@@ -286,7 +319,7 @@ void __init plat_irq_setup_pins(int mode)
286{ 319{
287 switch (mode) { 320 switch (mode) {
288 case IRQ_MODE_IRQ: 321 case IRQ_MODE_IRQ:
289 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 322 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
290 register_intc_controller(&intc_desc_irq); 323 register_intc_controller(&intc_desc_irq);
291 break; 324 break;
292 default: 325 default:
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index 8a8a993f55ea..14726eef1ce0 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -43,9 +43,9 @@ static unsigned long *sq_bitmap;
43 43
44#define store_queue_barrier() \ 44#define store_queue_barrier() \
45do { \ 45do { \
46 (void)ctrl_inl(P4SEG_STORE_QUE); \ 46 (void)__raw_readl(P4SEG_STORE_QUE); \
47 ctrl_outl(0, P4SEG_STORE_QUE + 0); \ 47 __raw_writel(0, P4SEG_STORE_QUE + 0); \
48 ctrl_outl(0, P4SEG_STORE_QUE + 8); \ 48 __raw_writel(0, P4SEG_STORE_QUE + 8); \
49} while (0); 49} while (0);
50 50
51/** 51/**
@@ -100,7 +100,7 @@ static inline void sq_mapping_list_del(struct sq_mapping *map)
100 spin_unlock_irq(&sq_mapping_lock); 100 spin_unlock_irq(&sq_mapping_lock);
101} 101}
102 102
103static int __sq_remap(struct sq_mapping *map, unsigned long flags) 103static int __sq_remap(struct sq_mapping *map, pgprot_t prot)
104{ 104{
105#if defined(CONFIG_MMU) 105#if defined(CONFIG_MMU)
106 struct vm_struct *vma; 106 struct vm_struct *vma;
@@ -113,7 +113,7 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
113 113
114 if (ioremap_page_range((unsigned long)vma->addr, 114 if (ioremap_page_range((unsigned long)vma->addr,
115 (unsigned long)vma->addr + map->size, 115 (unsigned long)vma->addr + map->size,
116 vma->phys_addr, __pgprot(flags))) { 116 vma->phys_addr, prot)) {
117 vunmap(vma->addr); 117 vunmap(vma->addr);
118 return -EAGAIN; 118 return -EAGAIN;
119 } 119 }
@@ -123,8 +123,8 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
123 * straightforward, as we can just load up each queue's QACR with 123 * straightforward, as we can just load up each queue's QACR with
124 * the physical address appropriately masked. 124 * the physical address appropriately masked.
125 */ 125 */
126 ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0); 126 __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0);
127 ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1); 127 __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1);
128#endif 128#endif
129 129
130 return 0; 130 return 0;
@@ -135,14 +135,14 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
135 * @phys: Physical address of mapping. 135 * @phys: Physical address of mapping.
136 * @size: Length of mapping. 136 * @size: Length of mapping.
137 * @name: User invoking mapping. 137 * @name: User invoking mapping.
138 * @flags: Protection flags. 138 * @prot: Protection bits.
139 * 139 *
140 * Remaps the physical address @phys through the next available store queue 140 * Remaps the physical address @phys through the next available store queue
141 * address of @size length. @name is logged at boot time as well as through 141 * address of @size length. @name is logged at boot time as well as through
142 * the sysfs interface. 142 * the sysfs interface.
143 */ 143 */
144unsigned long sq_remap(unsigned long phys, unsigned int size, 144unsigned long sq_remap(unsigned long phys, unsigned int size,
145 const char *name, unsigned long flags) 145 const char *name, pgprot_t prot)
146{ 146{
147 struct sq_mapping *map; 147 struct sq_mapping *map;
148 unsigned long end; 148 unsigned long end;
@@ -177,7 +177,7 @@ unsigned long sq_remap(unsigned long phys, unsigned int size,
177 177
178 map->sq_addr = P4SEG_STORE_QUE + (page << PAGE_SHIFT); 178 map->sq_addr = P4SEG_STORE_QUE + (page << PAGE_SHIFT);
179 179
180 ret = __sq_remap(map, pgprot_val(PAGE_KERNEL_NOCACHE) | flags); 180 ret = __sq_remap(map, prot);
181 if (unlikely(ret != 0)) 181 if (unlikely(ret != 0))
182 goto out; 182 goto out;
183 183
@@ -309,8 +309,7 @@ static ssize_t mapping_store(const char *buf, size_t count)
309 return -EIO; 309 return -EIO;
310 310
311 if (likely(len)) { 311 if (likely(len)) {
312 int ret = sq_remap(base, len, "Userspace", 312 int ret = sq_remap(base, len, "Userspace", PAGE_SHARED);
313 pgprot_val(PAGE_SHARED));
314 if (ret < 0) 313 if (ret < 0)
315 return ret; 314 return ret;
316 } else 315 } else
@@ -327,7 +326,7 @@ static struct attribute *sq_sysfs_attrs[] = {
327 NULL, 326 NULL,
328}; 327};
329 328
330static struct sysfs_ops sq_sysfs_ops = { 329static const struct sysfs_ops sq_sysfs_ops = {
331 .show = sq_sysfs_show, 330 .show = sq_sysfs_show,
332 .store = sq_sysfs_store, 331 .store = sq_sysfs_store,
333}; 332};
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 490d5dc9e372..b144e8af89dc 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -41,6 +41,8 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
43 43
44obj-y += $(clock-y) 44obj-y += $(clock-y)
45obj-$(CONFIG_SMP) += $(smp-y) 45obj-$(CONFIG_SMP) += $(smp-y)
46obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) 46obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
47obj-$(CONFIG_PERF_EVENTS) += perf_event.o
48obj-$(CONFIG_HAVE_HW_BREAKPOINT) += ubc.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 0ee3ee861252..2c16df37eda6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -107,13 +107,17 @@ struct clk *main_clks[] = {
107static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 107static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
108static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 108static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
109 109
110static struct clk_div_mult_table div4_table = { 110static struct clk_div_mult_table div4_div_mult_table = {
111 .divisors = divisors, 111 .divisors = divisors,
112 .nr_divisors = ARRAY_SIZE(divisors), 112 .nr_divisors = ARRAY_SIZE(divisors),
113 .multipliers = multipliers, 113 .multipliers = multipliers,
114 .nr_multipliers = ARRAY_SIZE(multipliers), 114 .nr_multipliers = ARRAY_SIZE(multipliers),
115}; 115};
116 116
117static struct clk_div4_table div4_table = {
118 .div_mult_table = &div4_div_mult_table,
119};
120
117enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 121enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
118 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 122 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
119 123
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index a95ebaba095c..91588d280cd8 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -110,13 +110,17 @@ struct clk *main_clks[] = {
110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
112 112
113static struct clk_div_mult_table div4_table = { 113static struct clk_div_mult_table div4_div_mult_table = {
114 .divisors = divisors, 114 .divisors = divisors,
115 .nr_divisors = ARRAY_SIZE(divisors), 115 .nr_divisors = ARRAY_SIZE(divisors),
116 .multipliers = multipliers, 116 .multipliers = multipliers,
117 .nr_multipliers = ARRAY_SIZE(multipliers), 117 .nr_multipliers = ARRAY_SIZE(multipliers),
118}; 118};
119 119
120static struct clk_div4_table div4_table = {
121 .div_mult_table = &div4_div_mult_table,
122};
123
120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 124enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
121 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 125 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
122 126
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index ea38b554dc05..15db6d521c5c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -110,19 +110,22 @@ struct clk *main_clks[] = {
110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
112 112
113static struct clk_div_mult_table div4_table = { 113static struct clk_div_mult_table div4_div_mult_table = {
114 .divisors = divisors, 114 .divisors = divisors,
115 .nr_divisors = ARRAY_SIZE(divisors), 115 .nr_divisors = ARRAY_SIZE(divisors),
116 .multipliers = multipliers, 116 .multipliers = multipliers,
117 .nr_multipliers = ARRAY_SIZE(multipliers), 117 .nr_multipliers = ARRAY_SIZE(multipliers),
118}; 118};
119 119
120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 120static struct clk_div4_table div4_table = {
121 DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; 121 .div_mult_table = &div4_div_mult_table,
122};
122 123
123#define DIV4(_str, _reg, _bit, _mask, _flags) \ 124#define DIV4(_str, _reg, _bit, _mask, _flags) \
124 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
125 126
127enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
128
126struct clk div4_clks[DIV4_NR] = { 129struct clk div4_clks[DIV4_NR] = {
127 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 130 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
128 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 131 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
@@ -130,9 +133,19 @@ struct clk div4_clks[DIV4_NR] = {
130 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 133 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 134 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 135 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
136};
137
138enum { DIV4_IRDA, DIV4_ENABLE_NR };
139
140struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
141 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
142};
143
144enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
145
146struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
133 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 147 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
134 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 148 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
135 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
136}; 149};
137 150
138struct clk div6_clks[] = { 151struct clk div6_clks[] = {
@@ -189,6 +202,14 @@ int __init arch_clk_init(void)
189 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
190 203
191 if (!ret) 204 if (!ret)
205 ret = sh_clk_div4_enable_register(div4_enable_clks,
206 DIV4_ENABLE_NR, &div4_table);
207
208 if (!ret)
209 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
210 DIV4_REPARENT_NR, &div4_table);
211
212 if (!ret)
192 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 213 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
193 214
194 if (!ret) 215 if (!ret)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 20a31c2255a8..50babe01fe44 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -110,15 +110,18 @@ struct clk *main_clks[] = {
110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
112 112
113static struct clk_div_mult_table div4_table = { 113static struct clk_div_mult_table div4_div_mult_table = {
114 .divisors = divisors, 114 .divisors = divisors,
115 .nr_divisors = ARRAY_SIZE(divisors), 115 .nr_divisors = ARRAY_SIZE(divisors),
116 .multipliers = multipliers, 116 .multipliers = multipliers,
117 .nr_multipliers = ARRAY_SIZE(multipliers), 117 .nr_multipliers = ARRAY_SIZE(multipliers),
118}; 118};
119 119
120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 120static struct clk_div4_table div4_table = {
121 DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR }; 121 .div_mult_table = &div4_div_mult_table,
122};
123
124enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
122 125
123#define DIV4(_str, _reg, _bit, _mask, _flags) \ 126#define DIV4(_str, _reg, _bit, _mask, _flags) \
124 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 127 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
@@ -130,11 +133,20 @@ struct clk div4_clks[DIV4_NR] = {
130 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 133 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 134 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
132 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), 135 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
133 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), 136};
134 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), 137
138enum { DIV4_IRDA, DIV4_ENABLE_NR };
139
140struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
135 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), 141 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
136}; 142};
137 143
144enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
145
146struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
147 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
148 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
149};
138struct clk div6_clks[] = { 150struct clk div6_clks[] = {
139 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 151 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
140}; 152};
@@ -216,6 +228,14 @@ int __init arch_clk_init(void)
216 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 228 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
217 229
218 if (!ret) 230 if (!ret)
231 ret = sh_clk_div4_enable_register(div4_enable_clks,
232 DIV4_ENABLE_NR, &div4_table);
233
234 if (!ret)
235 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
236 DIV4_REPARENT_NR, &div4_table);
237
238 if (!ret)
219 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 239 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
220 240
221 if (!ret) 241 if (!ret)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index dfe9192be63e..6707061fbf54 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -127,13 +127,28 @@ struct clk *main_clks[] = {
127 &div3_clk, 127 &div3_clk,
128}; 128};
129 129
130static void div4_kick(struct clk *clk)
131{
132 unsigned long value;
133
134 /* set KICK bit in FRQCRA to update hardware setting */
135 value = __raw_readl(FRQCRA);
136 value |= (1 << 31);
137 __raw_writel(value, FRQCRA);
138}
139
130static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; 140static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
131 141
132static struct clk_div_mult_table div4_table = { 142static struct clk_div_mult_table div4_div_mult_table = {
133 .divisors = divisors, 143 .divisors = divisors,
134 .nr_divisors = ARRAY_SIZE(divisors), 144 .nr_divisors = ARRAY_SIZE(divisors),
135}; 145};
136 146
147static struct clk_div4_table div4_table = {
148 .div_mult_table = &div4_div_mult_table,
149 .kick = div4_kick,
150};
151
137enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 152enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
138 153
139#define DIV4(_str, _reg, _bit, _mask, _flags) \ 154#define DIV4(_str, _reg, _bit, _mask, _flags) \
@@ -144,7 +159,7 @@ struct clk div4_clks[DIV4_NR] = {
144 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 159 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
145 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 160 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
146 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 161 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
147 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0), 162 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
148}; 163};
149 164
150struct clk div6_clks[] = { 165struct clk div6_clks[] = {
@@ -152,7 +167,7 @@ struct clk div6_clks[] = {
152 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), 167 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
153 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), 168 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
154 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), 169 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
155 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0), 170 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
156}; 171};
157 172
158#define R_CLK (&r_clk) 173#define R_CLK (&r_clk)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index ddc235ca9664..86aae60677dc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -35,7 +35,7 @@ static struct clk_ops sh7757_master_clk_ops = {
35 35
36static void module_clk_recalc(struct clk *clk) 36static void module_clk_recalc(struct clk *clk)
37{ 37{
38 int idx = ctrl_inl(FRQCR) & 0x0000000f; 38 int idx = __raw_readl(FRQCR) & 0x0000000f;
39 clk->rate = clk->parent->rate / p1fc_divisors[idx]; 39 clk->rate = clk->parent->rate / p1fc_divisors[idx];
40} 40}
41 41
@@ -45,7 +45,7 @@ static struct clk_ops sh7757_module_clk_ops = {
45 45
46static void bus_clk_recalc(struct clk *clk) 46static void bus_clk_recalc(struct clk *clk)
47{ 47{
48 int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f; 48 int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f;
49 clk->rate = clk->parent->rate / bfc_divisors[idx]; 49 clk->rate = clk->parent->rate / bfc_divisors[idx];
50} 50}
51 51
@@ -55,7 +55,7 @@ static struct clk_ops sh7757_bus_clk_ops = {
55 55
56static void cpu_clk_recalc(struct clk *clk) 56static void cpu_clk_recalc(struct clk *clk)
57{ 57{
58 int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f; 58 int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
59 clk->rate = clk->parent->rate / ifc_divisors[idx]; 59 clk->rate = clk->parent->rate / ifc_divisors[idx];
60} 60}
61 61
@@ -78,7 +78,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
78 78
79static void shyway_clk_recalc(struct clk *clk) 79static void shyway_clk_recalc(struct clk *clk)
80{ 80{
81 int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f; 81 int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
82 clk->rate = clk->parent->rate / sfc_divisors[idx]; 82 clk->rate = clk->parent->rate / sfc_divisors[idx];
83} 83}
84 84
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 370cd47642ef..9f401163e71e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
22 22
23static void master_clk_init(struct clk *clk) 23static void master_clk_init(struct clk *clk)
24{ 24{
25 clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07]; 25 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
26} 26}
27 27
28static struct clk_ops sh7763_master_clk_ops = { 28static struct clk_ops sh7763_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7763_master_clk_ops = {
31 31
32static unsigned long module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); 34 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
35 return clk->parent->rate / p0fc_divisors[idx]; 35 return clk->parent->rate / p0fc_divisors[idx];
36} 36}
37 37
@@ -41,7 +41,7 @@ static struct clk_ops sh7763_module_clk_ops = {
41 41
42static unsigned long bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); 44 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
45 return clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
@@ -68,7 +68,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
68 68
69static unsigned long shyway_clk_recalc(struct clk *clk) 69static unsigned long shyway_clk_recalc(struct clk *clk)
70{ 70{
71 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); 71 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
72 return clk->parent->rate / cfc_divisors[idx]; 72 return clk->parent->rate / cfc_divisors[idx];
73} 73}
74 74
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index e0b896769205..9e3354365d40 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -21,7 +21,7 @@ static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
21 21
22static void master_clk_init(struct clk *clk) 22static void master_clk_init(struct clk *clk)
23{ 23{
24 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f]; 24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
25} 25}
26 26
27static struct clk_ops sh7770_master_clk_ops = { 27static struct clk_ops sh7770_master_clk_ops = {
@@ -30,7 +30,7 @@ static struct clk_ops sh7770_master_clk_ops = {
30 30
31static unsigned long module_clk_recalc(struct clk *clk) 31static unsigned long module_clk_recalc(struct clk *clk)
32{ 32{
33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f); 33 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
34 return clk->parent->rate / pfc_divisors[idx]; 34 return clk->parent->rate / pfc_divisors[idx];
35} 35}
36 36
@@ -40,7 +40,7 @@ static struct clk_ops sh7770_module_clk_ops = {
40 40
41static unsigned long bus_clk_recalc(struct clk *clk) 41static unsigned long bus_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inl(FRQCR) & 0x000f); 43 int idx = (__raw_readl(FRQCR) & 0x000f);
44 return clk->parent->rate / bfc_divisors[idx]; 44 return clk->parent->rate / bfc_divisors[idx];
45} 45}
46 46
@@ -50,7 +50,7 @@ static struct clk_ops sh7770_bus_clk_ops = {
50 50
51static unsigned long cpu_clk_recalc(struct clk *clk) 51static unsigned long cpu_clk_recalc(struct clk *clk)
52{ 52{
53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f); 53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
54 return clk->parent->rate / ifc_divisors[idx]; 54 return clk->parent->rate / ifc_divisors[idx];
55} 55}
56 56
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index a249d823578e..150963a6001e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
22 22
23static void master_clk_init(struct clk *clk) 23static void master_clk_init(struct clk *clk)
24{ 24{
25 clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003]; 25 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
26} 26}
27 27
28static struct clk_ops sh7780_master_clk_ops = { 28static struct clk_ops sh7780_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7780_master_clk_ops = {
31 31
32static unsigned long module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = (ctrl_inl(FRQCR) & 0x0003); 34 int idx = (__raw_readl(FRQCR) & 0x0003);
35 return clk->parent->rate / pfc_divisors[idx]; 35 return clk->parent->rate / pfc_divisors[idx];
36} 36}
37 37
@@ -41,7 +41,7 @@ static struct clk_ops sh7780_module_clk_ops = {
41 41
42static unsigned long bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); 44 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);
45 return clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
@@ -51,7 +51,7 @@ static struct clk_ops sh7780_bus_clk_ops = {
51 51
52static unsigned long cpu_clk_recalc(struct clk *clk) 52static unsigned long cpu_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); 54 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);
55 return clk->parent->rate / ifc_divisors[idx]; 55 return clk->parent->rate / ifc_divisors[idx];
56} 56}
57 57
@@ -74,7 +74,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
74 74
75static unsigned long shyway_clk_recalc(struct clk *clk) 75static unsigned long shyway_clk_recalc(struct clk *clk)
76{ 76{
77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); 77 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
78 return clk->parent->rate / cfc_divisors[idx]; 78 return clk->parent->rate / cfc_divisors[idx];
79} 79}
80 80
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 73abfbf2f16d..d997f0a25b10 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -57,11 +57,15 @@ static struct clk *clks[] = {
57static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 57static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
58 24, 32, 36, 48 }; 58 24, 32, 36, 48 };
59 59
60static struct clk_div_mult_table div4_table = { 60static struct clk_div_mult_table div4_div_mult_table = {
61 .divisors = div2, 61 .divisors = div2,
62 .nr_divisors = ARRAY_SIZE(div2), 62 .nr_divisors = ARRAY_SIZE(div2),
63}; 63};
64 64
65static struct clk_div4_table div4_table = {
66 .div_mult_table = &div4_div_mult_table,
67};
68
65enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 69enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
66 DIV4_DU, DIV4_P, DIV4_NR }; 70 DIV4_DU, DIV4_P, DIV4_NR };
67 71
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index a0e8869071ac..af69fd468703 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -3,11 +3,7 @@
3 * 3 *
4 * SH7786 support for the clock framework 4 * SH7786 support for the clock framework
5 * 5 *
6 * Copyright (C) 2008, 2009 Renesas Solutions Corp. 6 * Copyright (C) 2010 Paul Mundt
7 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 *
9 * Based on SH7785
10 * Copyright (C) 2007 Paul Mundt
11 * 7 *
12 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -15,127 +11,127 @@
15 */ 11 */
16#include <linux/init.h> 12#include <linux/init.h>
17#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h>
15#include <linux/io.h>
18#include <asm/clock.h> 16#include <asm/clock.h>
19#include <asm/freq.h> 17#include <asm/freq.h>
20#include <asm/io.h>
21
22static int ifc_divisors[] = { 1, 2, 4, 1 };
23static int sfc_divisors[] = { 1, 1, 4, 1 };
24static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
25 24, 32, 1, 1, 1, 1, 1, 1 };
26static int mfc_divisors[] = { 1, 1, 4, 1 };
27static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
28 24, 32, 1, 48, 1, 1, 1, 1 };
29 18
30static void master_clk_init(struct clk *clk) 19/*
31{ 20 * Default rate for the root input clock, reset this with clk_set_rate()
32 clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f]; 21 * from the platform code.
33} 22 */
34 23static struct clk extal_clk = {
35static struct clk_ops sh7786_master_clk_ops = { 24 .name = "extal",
36 .init = master_clk_init, 25 .id = -1,
26 .rate = 33333333,
37}; 27};
38 28
39static unsigned long module_clk_recalc(struct clk *clk) 29static unsigned long pll_recalc(struct clk *clk)
40{ 30{
41 int idx = (ctrl_inl(FRQMR1) & 0x000f); 31 int multiplier;
42 return clk->parent->rate / pfc_divisors[idx];
43}
44 32
45static struct clk_ops sh7786_module_clk_ops = { 33 /*
46 .recalc = module_clk_recalc, 34 * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
47}; 35 * while modes 3, 4, and 5 use an x32.
36 */
37 multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
48 38
49static unsigned long bus_clk_recalc(struct clk *clk) 39 return clk->parent->rate * multiplier;
50{
51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52 return clk->parent->rate / bfc_divisors[idx];
53} 40}
54 41
55static struct clk_ops sh7786_bus_clk_ops = { 42static struct clk_ops pll_clk_ops = {
56 .recalc = bus_clk_recalc, 43 .recalc = pll_recalc,
57}; 44};
58 45
59static unsigned long cpu_clk_recalc(struct clk *clk) 46static struct clk pll_clk = {
60{ 47 .name = "pll_clk",
61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); 48 .id = -1,
62 return clk->parent->rate / ifc_divisors[idx]; 49 .ops = &pll_clk_ops,
63} 50 .parent = &extal_clk,
64 51 .flags = CLK_ENABLE_ON_INIT,
65static struct clk_ops sh7786_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc,
67}; 52};
68 53
69static struct clk_ops *sh7786_clk_ops[] = { 54static struct clk *clks[] = {
70 &sh7786_master_clk_ops, 55 &extal_clk,
71 &sh7786_module_clk_ops, 56 &pll_clk,
72 &sh7786_bus_clk_ops,
73 &sh7786_cpu_clk_ops,
74}; 57};
75 58
76void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 59static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
77{ 60 24, 32, 36, 48 };
78 if (idx < ARRAY_SIZE(sh7786_clk_ops))
79 *ops = sh7786_clk_ops[idx];
80}
81 61
82static unsigned long shyway_clk_recalc(struct clk *clk) 62static struct clk_div_mult_table div4_div_mult_table = {
83{ 63 .divisors = div2,
84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); 64 .nr_divisors = ARRAY_SIZE(div2),
85 return clk->parent->rate / sfc_divisors[idx];
86}
87
88static struct clk_ops sh7786_shyway_clk_ops = {
89 .recalc = shyway_clk_recalc,
90}; 65};
91 66
92static struct clk sh7786_shyway_clk = { 67static struct clk_div4_table div4_table = {
93 .name = "shyway_clk", 68 .div_mult_table = &div4_div_mult_table,
94 .flags = CLK_ENABLE_ON_INIT,
95 .ops = &sh7786_shyway_clk_ops,
96}; 69};
97 70
98static unsigned long ddr_clk_recalc(struct clk *clk) 71enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
99{
100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101 return clk->parent->rate / mfc_divisors[idx];
102}
103 72
104static struct clk_ops sh7786_ddr_clk_ops = { 73#define DIV4(_str, _bit, _mask, _flags) \
105 .recalc = ddr_clk_recalc, 74 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
106};
107 75
108static struct clk sh7786_ddr_clk = { 76struct clk div4_clks[DIV4_NR] = {
109 .name = "ddr_clk", 77 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
110 .flags = CLK_ENABLE_ON_INIT, 78 [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
111 .ops = &sh7786_ddr_clk_ops, 79 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
80 [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
81 [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
82 [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
112}; 83};
113 84
114/* 85#define MSTPCR0 0xffc40030
115 * Additional SH7786-specific on-chip clocks that aren't already part of the 86#define MSTPCR1 0xffc40034
116 * clock framework 87
117 */ 88static struct clk mstp_clks[] = {
118static struct clk *sh7786_onchip_clocks[] = { 89 /* MSTPCR0 */
119 &sh7786_shyway_clk, 90 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
120 &sh7786_ddr_clk, 91 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
92 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
93 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
94 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
95 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
96 SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
97 SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
98 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
99 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
100 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
101 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
102 SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
103 SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
104 SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
105 SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
106 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
107 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
108 SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
109 SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
110 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
111
112 /* MSTPCR1 */
113 SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
114 SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
115 SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
116 SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
117 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
118 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
119 SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
120 SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
121}; 121};
122 122
123int __init arch_clk_init(void) 123int __init arch_clk_init(void)
124{ 124{
125 struct clk *clk;
126 int i, ret = 0; 125 int i, ret = 0;
127 126
128 cpg_clk_init(); 127 for (i = 0; i < ARRAY_SIZE(clks); i++)
129 128 ret |= clk_register(clks[i]);
130 clk = clk_get(NULL, "master_clk");
131 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
132 struct clk *clkp = sh7786_onchip_clocks[i];
133
134 clkp->parent = clk;
135 ret |= clk_register(clkp);
136 }
137 129
138 clk_put(clk); 130 if (!ret)
131 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
132 &div4_table);
133 if (!ret)
134 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
139 135
140 return ret; 136 return ret;
141} 137}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 23c27d32d982..e75c57bdfa5e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -33,7 +33,7 @@ static int cfc_divisors[] = { 1, 1, 4, 6 };
33 33
34static void master_clk_init(struct clk *clk) 34static void master_clk_init(struct clk *clk)
35{ 35{
36 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK]; 36 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
37} 37}
38 38
39static struct clk_ops shx3_master_clk_ops = { 39static struct clk_ops shx3_master_clk_ops = {
@@ -42,7 +42,7 @@ static struct clk_ops shx3_master_clk_ops = {
42 42
43static unsigned long module_clk_recalc(struct clk *clk) 43static unsigned long module_clk_recalc(struct clk *clk)
44{ 44{
45 int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); 45 int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
46 return clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
47} 47}
48 48
@@ -52,7 +52,7 @@ static struct clk_ops shx3_module_clk_ops = {
52 52
53static unsigned long bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); 55 int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
56 return clk->parent->rate / bfc_divisors[idx]; 56 return clk->parent->rate / bfc_divisors[idx];
57} 57}
58 58
@@ -62,7 +62,7 @@ static struct clk_ops shx3_bus_clk_ops = {
62 62
63static unsigned long cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); 65 int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
66 return clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
@@ -85,7 +85,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
85 85
86static unsigned long shyway_clk_recalc(struct clk *clk) 86static unsigned long shyway_clk_recalc(struct clk *clk)
87{ 87{
88 int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); 88 int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
89 return clk->parent->rate / cfc_divisors[idx]; 89 return clk->parent->rate / cfc_divisors[idx];
90} 90}
91 91
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
new file mode 100644
index 000000000000..eddc21973fa1
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -0,0 +1,269 @@
1/*
2 * Performance events support for SH-4A performance counters
3 *
4 * Copyright (C) 2009 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/perf_event.h>
15#include <asm/processor.h>
16
17#define PPC_CCBR(idx) (0xff200800 + (sizeof(u32) * idx))
18#define PPC_PMCTR(idx) (0xfc100000 + (sizeof(u32) * idx))
19
20#define CCBR_CIT_MASK (0x7ff << 6)
21#define CCBR_DUC (1 << 3)
22#define CCBR_CMDS (1 << 1)
23#define CCBR_PPCE (1 << 0)
24
25#define PPC_PMCAT 0xfc100080
26
27#define PMCAT_OVF3 (1 << 27)
28#define PMCAT_CNN3 (1 << 26)
29#define PMCAT_CLR3 (1 << 25)
30#define PMCAT_OVF2 (1 << 19)
31#define PMCAT_CLR2 (1 << 17)
32#define PMCAT_OVF1 (1 << 11)
33#define PMCAT_CNN1 (1 << 10)
34#define PMCAT_CLR1 (1 << 9)
35#define PMCAT_OVF0 (1 << 3)
36#define PMCAT_CLR0 (1 << 1)
37
38static struct sh_pmu sh4a_pmu;
39
40/*
41 * Supported raw event codes:
42 *
43 * Event Code Description
44 * ---------- -----------
45 *
46 * 0x0000 number of elapsed cycles
47 * 0x0200 number of elapsed cycles in privileged mode
48 * 0x0280 number of elapsed cycles while SR.BL is asserted
49 * 0x0202 instruction execution
50 * 0x0203 instruction execution in parallel
51 * 0x0204 number of unconditional branches
52 * 0x0208 number of exceptions
53 * 0x0209 number of interrupts
54 * 0x0220 UTLB miss caused by instruction fetch
55 * 0x0222 UTLB miss caused by operand access
56 * 0x02a0 number of ITLB misses
57 * 0x0028 number of accesses to instruction memories
58 * 0x0029 number of accesses to instruction cache
59 * 0x002a instruction cache miss
60 * 0x022e number of access to instruction X/Y memory
61 * 0x0030 number of reads to operand memories
62 * 0x0038 number of writes to operand memories
63 * 0x0031 number of operand cache read accesses
64 * 0x0039 number of operand cache write accesses
65 * 0x0032 operand cache read miss
66 * 0x003a operand cache write miss
67 * 0x0236 number of reads to operand X/Y memory
68 * 0x023e number of writes to operand X/Y memory
69 * 0x0237 number of reads to operand U memory
70 * 0x023f number of writes to operand U memory
71 * 0x0337 number of U memory read buffer misses
72 * 0x02b4 number of wait cycles due to operand read access
73 * 0x02bc number of wait cycles due to operand write access
74 * 0x0033 number of wait cycles due to operand cache read miss
75 * 0x003b number of wait cycles due to operand cache write miss
76 */
77
78/*
79 * Special reserved bits used by hardware emulators, read values will
80 * vary, but writes must always be 0.
81 */
82#define PMCAT_EMU_CLR_MASK ((1 << 24) | (1 << 16) | (1 << 8) | (1 << 0))
83
84static const int sh4a_general_events[] = {
85 [PERF_COUNT_HW_CPU_CYCLES] = 0x0000,
86 [PERF_COUNT_HW_INSTRUCTIONS] = 0x0202,
87 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0029, /* I-cache */
88 [PERF_COUNT_HW_CACHE_MISSES] = 0x002a, /* I-cache */
89 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0204,
90 [PERF_COUNT_HW_BRANCH_MISSES] = -1,
91 [PERF_COUNT_HW_BUS_CYCLES] = -1,
92};
93
94#define C(x) PERF_COUNT_HW_CACHE_##x
95
96static const int sh4a_cache_events
97 [PERF_COUNT_HW_CACHE_MAX]
98 [PERF_COUNT_HW_CACHE_OP_MAX]
99 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
100{
101 [ C(L1D) ] = {
102 [ C(OP_READ) ] = {
103 [ C(RESULT_ACCESS) ] = 0x0031,
104 [ C(RESULT_MISS) ] = 0x0032,
105 },
106 [ C(OP_WRITE) ] = {
107 [ C(RESULT_ACCESS) ] = 0x0039,
108 [ C(RESULT_MISS) ] = 0x003a,
109 },
110 [ C(OP_PREFETCH) ] = {
111 [ C(RESULT_ACCESS) ] = 0,
112 [ C(RESULT_MISS) ] = 0,
113 },
114 },
115
116 [ C(L1I) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0029,
119 [ C(RESULT_MISS) ] = 0x002a,
120 },
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = -1,
123 [ C(RESULT_MISS) ] = -1,
124 },
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
127 [ C(RESULT_MISS) ] = 0,
128 },
129 },
130
131 [ C(LL) ] = {
132 [ C(OP_READ) ] = {
133 [ C(RESULT_ACCESS) ] = 0x0030,
134 [ C(RESULT_MISS) ] = 0,
135 },
136 [ C(OP_WRITE) ] = {
137 [ C(RESULT_ACCESS) ] = 0x0038,
138 [ C(RESULT_MISS) ] = 0,
139 },
140 [ C(OP_PREFETCH) ] = {
141 [ C(RESULT_ACCESS) ] = 0,
142 [ C(RESULT_MISS) ] = 0,
143 },
144 },
145
146 [ C(DTLB) ] = {
147 [ C(OP_READ) ] = {
148 [ C(RESULT_ACCESS) ] = 0x0222,
149 [ C(RESULT_MISS) ] = 0x0220,
150 },
151 [ C(OP_WRITE) ] = {
152 [ C(RESULT_ACCESS) ] = 0,
153 [ C(RESULT_MISS) ] = 0,
154 },
155 [ C(OP_PREFETCH) ] = {
156 [ C(RESULT_ACCESS) ] = 0,
157 [ C(RESULT_MISS) ] = 0,
158 },
159 },
160
161 [ C(ITLB) ] = {
162 [ C(OP_READ) ] = {
163 [ C(RESULT_ACCESS) ] = 0,
164 [ C(RESULT_MISS) ] = 0x02a0,
165 },
166 [ C(OP_WRITE) ] = {
167 [ C(RESULT_ACCESS) ] = -1,
168 [ C(RESULT_MISS) ] = -1,
169 },
170 [ C(OP_PREFETCH) ] = {
171 [ C(RESULT_ACCESS) ] = -1,
172 [ C(RESULT_MISS) ] = -1,
173 },
174 },
175
176 [ C(BPU) ] = {
177 [ C(OP_READ) ] = {
178 [ C(RESULT_ACCESS) ] = -1,
179 [ C(RESULT_MISS) ] = -1,
180 },
181 [ C(OP_WRITE) ] = {
182 [ C(RESULT_ACCESS) ] = -1,
183 [ C(RESULT_MISS) ] = -1,
184 },
185 [ C(OP_PREFETCH) ] = {
186 [ C(RESULT_ACCESS) ] = -1,
187 [ C(RESULT_MISS) ] = -1,
188 },
189 },
190};
191
192static int sh4a_event_map(int event)
193{
194 return sh4a_general_events[event];
195}
196
197static u64 sh4a_pmu_read(int idx)
198{
199 return __raw_readl(PPC_PMCTR(idx));
200}
201
202static void sh4a_pmu_disable(struct hw_perf_event *hwc, int idx)
203{
204 unsigned int tmp;
205
206 tmp = __raw_readl(PPC_CCBR(idx));
207 tmp &= ~(CCBR_CIT_MASK | CCBR_DUC);
208 __raw_writel(tmp, PPC_CCBR(idx));
209}
210
211static void sh4a_pmu_enable(struct hw_perf_event *hwc, int idx)
212{
213 unsigned int tmp;
214
215 tmp = __raw_readl(PPC_PMCAT);
216 tmp &= ~PMCAT_EMU_CLR_MASK;
217 tmp |= idx ? PMCAT_CLR1 : PMCAT_CLR0;
218 __raw_writel(tmp, PPC_PMCAT);
219
220 tmp = __raw_readl(PPC_CCBR(idx));
221 tmp |= (hwc->config << 6) | CCBR_CMDS | CCBR_PPCE;
222 __raw_writel(tmp, PPC_CCBR(idx));
223
224 __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx));
225}
226
227static void sh4a_pmu_disable_all(void)
228{
229 int i;
230
231 for (i = 0; i < sh4a_pmu.num_events; i++)
232 __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i));
233}
234
235static void sh4a_pmu_enable_all(void)
236{
237 int i;
238
239 for (i = 0; i < sh4a_pmu.num_events; i++)
240 __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i));
241}
242
243static struct sh_pmu sh4a_pmu = {
244 .name = "SH-4A",
245 .num_events = 2,
246 .event_map = sh4a_event_map,
247 .max_events = ARRAY_SIZE(sh4a_general_events),
248 .raw_event_mask = 0x3ff,
249 .cache_events = &sh4a_cache_events,
250 .read = sh4a_pmu_read,
251 .disable = sh4a_pmu_disable,
252 .enable = sh4a_pmu_enable,
253 .disable_all = sh4a_pmu_disable_all,
254 .enable_all = sh4a_pmu_enable_all,
255};
256
257static int __init sh4a_pmu_init(void)
258{
259 /*
260 * Make sure this CPU actually has perf counters.
261 */
262 if (!(boot_cpu_data.flags & CPU_HAS_PERF_COUNTER)) {
263 pr_notice("HW perf events unsupported, software events only.\n");
264 return -ENODEV;
265 }
266
267 return register_sh_pmu(&sh4a_pmu);
268}
269arch_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index cb9d07bd59f8..0688a7502f86 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -278,6 +278,7 @@ enum {
278 HIZA8_LCDC, HIZA8_HIZ, 278 HIZA8_LCDC, HIZA8_HIZ,
279 HIZA7_LCDC, HIZA7_HIZ, 279 HIZA7_LCDC, HIZA7_HIZ,
280 HIZA6_LCDC, HIZA6_HIZ, 280 HIZA6_LCDC, HIZA6_HIZ,
281 HIZB4_SIUA, HIZB4_HIZ,
281 HIZB1_VIO, HIZB1_HIZ, 282 HIZB1_VIO, HIZB1_HIZ,
282 HIZB0_VIO, HIZB0_HIZ, 283 HIZB0_VIO, HIZB0_HIZ,
283 HIZC15_IRQ7, HIZC15_HIZ, 284 HIZC15_IRQ7, HIZC15_HIZ,
@@ -546,7 +547,7 @@ static pinmux_enum_t pinmux_data[] = {
546 PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2, 547 PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
547 HIZB0_VIO, FOE_VIO_VD2), 548 HIZB0_VIO, FOE_VIO_VD2),
548 PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2, 549 PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
549 HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2), 550 HIZB1_VIO, FCE_VIO_HD2),
550 PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2, 551 PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
551 HIZB1_VIO, FRB_VIO_CLK2), 552 HIZB1_VIO, FRB_VIO_CLK2),
552 553
@@ -658,14 +659,14 @@ static pinmux_enum_t pinmux_data[] = {
658 PINMUX_DATA(SDHICLK_MARK, SDHICLK), 659 PINMUX_DATA(SDHICLK_MARK, SDHICLK),
659 660
660 /* SIU - Port A */ 661 /* SIU - Port A */
661 PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC), 662 PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, HIZB4_SIUA, SIUAOLR_SIOF1_SYNC),
662 PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK), 663 PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, HIZB4_SIUA, SIUAOBT_SIOF1_SCK),
663 PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD), 664 PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, HIZB4_SIUA, SIUAISLD_SIOF1_RXD),
664 PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2), 665 PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, HIZB4_SIUA, SIUAILR_SIOF1_SS2),
665 PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1), 666 PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, HIZB4_SIUA, SIUAIBT_SIOF1_SS1),
666 PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD), 667 PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, HIZB4_SIUA, SIUAOSLD_SIOF1_TXD),
667 PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0), 668 PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, HIZB4_SIUA, PSB1_SIUMCKA, PTK0),
668 PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0), 669 PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, HIZB4_SIUA, PTK0),
669 670
670 /* SIU - Port B */ 671 /* SIU - Port B */
671 PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR), 672 PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
@@ -1612,7 +1613,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1612 0, 0, 1613 0, 0,
1613 0, 0, 1614 0, 0,
1614 0, 0, 1615 0, 0,
1615 0, 0, 1616 HIZB4_SIUA, HIZB4_HIZ,
1616 0, 0, 1617 0, 0,
1617 0, 0, 1618 0, 0,
1618 HIZB1_VIO, HIZB1_HIZ, 1619 HIZB1_VIO, HIZB1_HIZ,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index ac4d5672ec1a..45eb1bfd42c9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -15,6 +15,71 @@
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <asm/clock.h> 16#include <asm/clock.h>
17 17
18/* Serial */
19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF,
23 .irqs = { 80, 80, 80, 80 },
24 .clk = "scif0",
25};
26
27static struct platform_device scif0_device = {
28 .name = "sh-sci",
29 .id = 0,
30 .dev = {
31 .platform_data = &scif0_platform_data,
32 },
33};
34
35static struct plat_sci_port scif1_platform_data = {
36 .mapbase = 0xffe10000,
37 .flags = UPF_BOOT_AUTOCONF,
38 .type = PORT_SCIF,
39 .irqs = { 81, 81, 81, 81 },
40 .clk = "scif1",
41};
42
43static struct platform_device scif1_device = {
44 .name = "sh-sci",
45 .id = 1,
46 .dev = {
47 .platform_data = &scif1_platform_data,
48 },
49};
50
51static struct plat_sci_port scif2_platform_data = {
52 .mapbase = 0xffe20000,
53 .flags = UPF_BOOT_AUTOCONF,
54 .type = PORT_SCIF,
55 .irqs = { 82, 82, 82, 82 },
56 .clk = "scif2",
57};
58
59static struct platform_device scif2_device = {
60 .name = "sh-sci",
61 .id = 2,
62 .dev = {
63 .platform_data = &scif2_platform_data,
64 },
65};
66
67static struct plat_sci_port scif3_platform_data = {
68 .mapbase = 0xffe30000,
69 .flags = UPF_BOOT_AUTOCONF,
70 .type = PORT_SCIF,
71 .irqs = { 83, 83, 83, 83 },
72 .clk = "scif3",
73};
74
75static struct platform_device scif3_device = {
76 .name = "sh-sci",
77 .id = 3,
78 .dev = {
79 .platform_data = &scif3_platform_data,
80 },
81};
82
18static struct resource iic0_resources[] = { 83static struct resource iic0_resources[] = {
19 [0] = { 84 [0] = {
20 .name = "IIC0", 85 .name = "IIC0",
@@ -265,52 +330,17 @@ static struct platform_device tmu2_device = {
265 .num_resources = ARRAY_SIZE(tmu2_resources), 330 .num_resources = ARRAY_SIZE(tmu2_resources),
266}; 331};
267 332
268static struct plat_sci_port sci_platform_data[] = {
269 {
270 .mapbase = 0xffe00000,
271 .flags = UPF_BOOT_AUTOCONF,
272 .type = PORT_SCIF,
273 .irqs = { 80, 80, 80, 80 },
274 .clk = "scif0",
275 }, {
276 .mapbase = 0xffe10000,
277 .flags = UPF_BOOT_AUTOCONF,
278 .type = PORT_SCIF,
279 .irqs = { 81, 81, 81, 81 },
280 .clk = "scif1",
281 }, {
282 .mapbase = 0xffe20000,
283 .flags = UPF_BOOT_AUTOCONF,
284 .type = PORT_SCIF,
285 .irqs = { 82, 82, 82, 82 },
286 .clk = "scif2",
287 }, {
288 .mapbase = 0xffe30000,
289 .flags = UPF_BOOT_AUTOCONF,
290 .type = PORT_SCIF,
291 .irqs = { 83, 83, 83, 83 },
292 .clk = "scif3",
293 }, {
294 .flags = 0,
295 }
296};
297
298static struct platform_device sci_device = {
299 .name = "sh-sci",
300 .id = -1,
301 .dev = {
302 .platform_data = sci_platform_data,
303 },
304};
305
306static struct platform_device *sh7343_devices[] __initdata = { 333static struct platform_device *sh7343_devices[] __initdata = {
334 &scif0_device,
335 &scif1_device,
336 &scif2_device,
337 &scif3_device,
307 &cmt_device, 338 &cmt_device,
308 &tmu0_device, 339 &tmu0_device,
309 &tmu1_device, 340 &tmu1_device,
310 &tmu2_device, 341 &tmu2_device,
311 &iic0_device, 342 &iic0_device,
312 &iic1_device, 343 &iic1_device,
313 &sci_device,
314 &vpu_device, 344 &vpu_device,
315 &veu_device, 345 &veu_device,
316 &jpu_device, 346 &jpu_device,
@@ -328,6 +358,10 @@ static int __init sh7343_devices_setup(void)
328arch_initcall(sh7343_devices_setup); 358arch_initcall(sh7343_devices_setup);
329 359
330static struct platform_device *sh7343_early_devices[] __initdata = { 360static struct platform_device *sh7343_early_devices[] __initdata = {
361 &scif0_device,
362 &scif1_device,
363 &scif2_device,
364 &scif3_device,
331 &cmt_device, 365 &cmt_device,
332 &tmu0_device, 366 &tmu0_device,
333 &tmu1_device, 367 &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 4a9010bf4fd3..c494c193e3b6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -18,6 +18,22 @@
18#include <linux/usb/r8a66597.h> 18#include <linux/usb/r8a66597.h>
19#include <asm/clock.h> 19#include <asm/clock.h>
20 20
21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF,
24 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 },
26 .clk = "scif0",
27};
28
29static struct platform_device scif0_device = {
30 .name = "sh-sci",
31 .id = 0,
32 .dev = {
33 .platform_data = &scif0_platform_data,
34 },
35};
36
21static struct resource iic_resources[] = { 37static struct resource iic_resources[] = {
22 [0] = { 38 [0] = {
23 .name = "IIC", 39 .name = "IIC",
@@ -276,33 +292,13 @@ static struct platform_device tmu2_device = {
276 .num_resources = ARRAY_SIZE(tmu2_resources), 292 .num_resources = ARRAY_SIZE(tmu2_resources),
277}; 293};
278 294
279static struct plat_sci_port sci_platform_data[] = {
280 {
281 .mapbase = 0xffe00000,
282 .flags = UPF_BOOT_AUTOCONF,
283 .type = PORT_SCIF,
284 .irqs = { 80, 80, 80, 80 },
285 .clk = "scif0",
286 }, {
287 .flags = 0,
288 }
289};
290
291static struct platform_device sci_device = {
292 .name = "sh-sci",
293 .id = -1,
294 .dev = {
295 .platform_data = sci_platform_data,
296 },
297};
298
299static struct platform_device *sh7366_devices[] __initdata = { 295static struct platform_device *sh7366_devices[] __initdata = {
296 &scif0_device,
300 &cmt_device, 297 &cmt_device,
301 &tmu0_device, 298 &tmu0_device,
302 &tmu1_device, 299 &tmu1_device,
303 &tmu2_device, 300 &tmu2_device,
304 &iic_device, 301 &iic_device,
305 &sci_device,
306 &usb_host_device, 302 &usb_host_device,
307 &vpu_device, 303 &vpu_device,
308 &veu0_device, 304 &veu0_device,
@@ -321,6 +317,7 @@ static int __init sh7366_devices_setup(void)
321arch_initcall(sh7366_devices_setup); 317arch_initcall(sh7366_devices_setup);
322 318
323static struct platform_device *sh7366_early_devices[] __initdata = { 319static struct platform_device *sh7366_early_devices[] __initdata = {
320 &scif0_device,
324 &cmt_device, 321 &cmt_device,
325 &tmu0_device, 322 &tmu0_device,
326 &tmu1_device, 323 &tmu1_device,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5491b094cf05..fd7e3639e845 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -7,19 +7,216 @@
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10#include <linux/platform_device.h>
11#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/platform_device.h>
12#include <linux/serial.h> 13#include <linux/serial.h>
13#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
14#include <linux/mm.h> 15#include <linux/sh_timer.h>
15#include <linux/uio_driver.h> 16#include <linux/uio_driver.h>
16#include <linux/usb/m66592.h> 17#include <linux/usb/m66592.h>
17#include <linux/sh_timer.h> 18
18#include <asm/clock.h> 19#include <asm/clock.h>
20#include <asm/dmaengine.h>
19#include <asm/mmzone.h> 21#include <asm/mmzone.h>
20#include <asm/dma-sh.h> 22#include <asm/siu.h>
23
24#include <cpu/dma-register.h>
21#include <cpu/sh7722.h> 25#include <cpu/sh7722.h>
22 26
27static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
28 {
29 .slave_id = SHDMA_SLAVE_SCIF0_TX,
30 .addr = 0xffe0000c,
31 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
32 .mid_rid = 0x21,
33 }, {
34 .slave_id = SHDMA_SLAVE_SCIF0_RX,
35 .addr = 0xffe00014,
36 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
37 .mid_rid = 0x22,
38 }, {
39 .slave_id = SHDMA_SLAVE_SCIF1_TX,
40 .addr = 0xffe1000c,
41 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
42 .mid_rid = 0x25,
43 }, {
44 .slave_id = SHDMA_SLAVE_SCIF1_RX,
45 .addr = 0xffe10014,
46 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
47 .mid_rid = 0x26,
48 }, {
49 .slave_id = SHDMA_SLAVE_SCIF2_TX,
50 .addr = 0xffe2000c,
51 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
52 .mid_rid = 0x29,
53 }, {
54 .slave_id = SHDMA_SLAVE_SCIF2_RX,
55 .addr = 0xffe20014,
56 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
57 .mid_rid = 0x2a,
58 }, {
59 .slave_id = SHDMA_SLAVE_SIUA_TX,
60 .addr = 0xa454c098,
61 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
62 .mid_rid = 0xb1,
63 }, {
64 .slave_id = SHDMA_SLAVE_SIUA_RX,
65 .addr = 0xa454c090,
66 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
67 .mid_rid = 0xb2,
68 }, {
69 .slave_id = SHDMA_SLAVE_SIUB_TX,
70 .addr = 0xa454c09c,
71 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
72 .mid_rid = 0xb5,
73 }, {
74 .slave_id = SHDMA_SLAVE_SIUB_RX,
75 .addr = 0xa454c094,
76 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
77 .mid_rid = 0xb6,
78 },
79};
80
81static struct sh_dmae_channel sh7722_dmae_channels[] = {
82 {
83 .offset = 0,
84 .dmars = 0,
85 .dmars_bit = 0,
86 }, {
87 .offset = 0x10,
88 .dmars = 0,
89 .dmars_bit = 8,
90 }, {
91 .offset = 0x20,
92 .dmars = 4,
93 .dmars_bit = 0,
94 }, {
95 .offset = 0x30,
96 .dmars = 4,
97 .dmars_bit = 8,
98 }, {
99 .offset = 0x50,
100 .dmars = 8,
101 .dmars_bit = 0,
102 }, {
103 .offset = 0x60,
104 .dmars = 8,
105 .dmars_bit = 8,
106 }
107};
108
109static unsigned int ts_shift[] = TS_SHIFT;
110
111static struct sh_dmae_pdata dma_platform_data = {
112 .slave = sh7722_dmae_slaves,
113 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
114 .channel = sh7722_dmae_channels,
115 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
116 .ts_low_shift = CHCR_TS_LOW_SHIFT,
117 .ts_low_mask = CHCR_TS_LOW_MASK,
118 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
119 .ts_high_mask = CHCR_TS_HIGH_MASK,
120 .ts_shift = ts_shift,
121 .ts_shift_num = ARRAY_SIZE(ts_shift),
122 .dmaor_init = DMAOR_INIT,
123};
124
125static struct resource sh7722_dmae_resources[] = {
126 [0] = {
127 /* Channel registers and DMAOR */
128 .start = 0xfe008020,
129 .end = 0xfe00808f,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 /* DMARSx */
134 .start = 0xfe009000,
135 .end = 0xfe00900b,
136 .flags = IORESOURCE_MEM,
137 },
138 {
139 /* DMA error IRQ */
140 .start = 78,
141 .end = 78,
142 .flags = IORESOURCE_IRQ,
143 },
144 {
145 /* IRQ for channels 0-3 */
146 .start = 48,
147 .end = 51,
148 .flags = IORESOURCE_IRQ,
149 },
150 {
151 /* IRQ for channels 4-5 */
152 .start = 76,
153 .end = 77,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158struct platform_device dma_device = {
159 .name = "sh-dma-engine",
160 .id = -1,
161 .resource = sh7722_dmae_resources,
162 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
163 .dev = {
164 .platform_data = &dma_platform_data,
165 },
166 .archdata = {
167 .hwblk_id = HWBLK_DMAC,
168 },
169};
170
171/* Serial */
172static struct plat_sci_port scif0_platform_data = {
173 .mapbase = 0xffe00000,
174 .flags = UPF_BOOT_AUTOCONF,
175 .type = PORT_SCIF,
176 .irqs = { 80, 80, 80, 80 },
177 .clk = "scif0",
178};
179
180static struct platform_device scif0_device = {
181 .name = "sh-sci",
182 .id = 0,
183 .dev = {
184 .platform_data = &scif0_platform_data,
185 },
186};
187
188static struct plat_sci_port scif1_platform_data = {
189 .mapbase = 0xffe10000,
190 .flags = UPF_BOOT_AUTOCONF,
191 .type = PORT_SCIF,
192 .irqs = { 81, 81, 81, 81 },
193 .clk = "scif1",
194};
195
196static struct platform_device scif1_device = {
197 .name = "sh-sci",
198 .id = 1,
199 .dev = {
200 .platform_data = &scif1_platform_data,
201 },
202};
203
204static struct plat_sci_port scif2_platform_data = {
205 .mapbase = 0xffe20000,
206 .flags = UPF_BOOT_AUTOCONF,
207 .type = PORT_SCIF,
208 .irqs = { 82, 82, 82, 82 },
209 .clk = "scif2",
210};
211
212static struct platform_device scif2_device = {
213 .name = "sh-sci",
214 .id = 2,
215 .dev = {
216 .platform_data = &scif2_platform_data,
217 },
218};
219
23static struct resource rtc_resources[] = { 220static struct resource rtc_resources[] = {
24 [0] = { 221 [0] = {
25 .start = 0xa465fec0, 222 .start = 0xa465fec0,
@@ -339,54 +536,43 @@ static struct platform_device tmu2_device = {
339 }, 536 },
340}; 537};
341 538
342static struct plat_sci_port sci_platform_data[] = { 539static struct siu_platform siu_platform_data = {
343 { 540 .dma_dev = &dma_device.dev,
344 .mapbase = 0xffe00000, 541 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
345 .flags = UPF_BOOT_AUTOCONF, 542 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
346 .type = PORT_SCIF, 543 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
347 .irqs = { 80, 80, 80, 80 }, 544 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
348 .clk = "scif0",
349 },
350 {
351 .mapbase = 0xffe10000,
352 .flags = UPF_BOOT_AUTOCONF,
353 .type = PORT_SCIF,
354 .irqs = { 81, 81, 81, 81 },
355 .clk = "scif1",
356 },
357 {
358 .mapbase = 0xffe20000,
359 .flags = UPF_BOOT_AUTOCONF,
360 .type = PORT_SCIF,
361 .irqs = { 82, 82, 82, 82 },
362 .clk = "scif2",
363 },
364 {
365 .flags = 0,
366 }
367}; 545};
368 546
369static struct platform_device sci_device = { 547static struct resource siu_resources[] = {
370 .name = "sh-sci", 548 [0] = {
371 .id = -1, 549 .start = 0xa4540000,
372 .dev = { 550 .end = 0xa454c10f,
373 .platform_data = sci_platform_data, 551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = 108,
555 .flags = IORESOURCE_IRQ,
374 }, 556 },
375}; 557};
376 558
377static struct sh_dmae_pdata dma_platform_data = { 559static struct platform_device siu_device = {
378 .mode = 0, 560 .name = "sh_siu",
379};
380
381static struct platform_device dma_device = {
382 .name = "sh-dma-engine",
383 .id = -1, 561 .id = -1,
384 .dev = { 562 .dev = {
385 .platform_data = &dma_platform_data, 563 .platform_data = &siu_platform_data,
564 },
565 .resource = siu_resources,
566 .num_resources = ARRAY_SIZE(siu_resources),
567 .archdata = {
568 .hwblk_id = HWBLK_SIU,
386 }, 569 },
387}; 570};
388 571
389static struct platform_device *sh7722_devices[] __initdata = { 572static struct platform_device *sh7722_devices[] __initdata = {
573 &scif0_device,
574 &scif1_device,
575 &scif2_device,
390 &cmt_device, 576 &cmt_device,
391 &tmu0_device, 577 &tmu0_device,
392 &tmu1_device, 578 &tmu1_device,
@@ -394,10 +580,10 @@ static struct platform_device *sh7722_devices[] __initdata = {
394 &rtc_device, 580 &rtc_device,
395 &usbf_device, 581 &usbf_device,
396 &iic_device, 582 &iic_device,
397 &sci_device,
398 &vpu_device, 583 &vpu_device,
399 &veu_device, 584 &veu_device,
400 &jpu_device, 585 &jpu_device,
586 &siu_device,
401 &dma_device, 587 &dma_device,
402}; 588};
403 589
@@ -413,6 +599,9 @@ static int __init sh7722_devices_setup(void)
413arch_initcall(sh7722_devices_setup); 599arch_initcall(sh7722_devices_setup);
414 600
415static struct platform_device *sh7722_early_devices[] __initdata = { 601static struct platform_device *sh7722_early_devices[] __initdata = {
602 &scif0_device,
603 &scif1_device,
604 &scif2_device,
416 &cmt_device, 605 &cmt_device,
417 &tmu0_device, 606 &tmu0_device,
418 &tmu1_device, 607 &tmu1_device,
@@ -427,6 +616,8 @@ void __init plat_early_device_setup(void)
427 616
428enum { 617enum {
429 UNUSED=0, 618 UNUSED=0,
619 ENABLED,
620 DISABLED,
430 621
431 /* interrupt sources */ 622 /* interrupt sources */
432 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 623 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -442,7 +633,6 @@ enum {
442 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 633 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
443 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 634 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
444 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 635 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
445 SDHI0, SDHI1, SDHI2, SDHI3,
446 CMT, TSIF, SIU, TWODG, 636 CMT, TSIF, SIU, TWODG,
447 TMU0, TMU1, TMU2, 637 TMU0, TMU1, TMU2,
448 IRDA, JPU, LCDC, 638 IRDA, JPU, LCDC,
@@ -475,8 +665,8 @@ static struct intc_vect vectors[] __initdata = {
475 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 665 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
476 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 666 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
477 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 667 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
478 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0), 668 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
479 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0), 669 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
480 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 670 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
481 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 671 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
482 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 672 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -494,7 +684,6 @@ static struct intc_group groups[] __initdata = {
494 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 684 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
495 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 685 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
496 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 686 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
497 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
498}; 687};
499 688
500static struct intc_mask_reg mask_registers[] __initdata = { 689static struct intc_mask_reg mask_registers[] __initdata = {
@@ -516,7 +705,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
516 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 705 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
517 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 706 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
518 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 707 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
519 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } }, 708 { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
520 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 709 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
521 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 710 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
522 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 711 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -554,9 +743,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
554 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 743 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
555}; 744};
556 745
557static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups, 746static struct intc_desc intc_desc __initdata = {
558 mask_registers, prio_registers, sense_registers, 747 .name = "sh7722",
559 ack_registers); 748 .force_enable = ENABLED,
749 .force_disable = DISABLED,
750 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
751 prio_registers, sense_registers, ack_registers),
752};
560 753
561void __init plat_irq_setup(void) 754void __init plat_irq_setup(void)
562{ 755{
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 4caa5a7ca86e..85c61f624702 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -20,6 +20,103 @@
20#include <asm/mmzone.h> 20#include <asm/mmzone.h>
21#include <cpu/sh7723.h> 21#include <cpu/sh7723.h>
22 22
23/* Serial */
24static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000,
26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 },
29 .clk = "scif0",
30};
31
32static struct platform_device scif0_device = {
33 .name = "sh-sci",
34 .id = 0,
35 .dev = {
36 .platform_data = &scif0_platform_data,
37 },
38};
39
40static struct plat_sci_port scif1_platform_data = {
41 .mapbase = 0xffe10000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF,
44 .irqs = { 81, 81, 81, 81 },
45 .clk = "scif1",
46};
47
48static struct platform_device scif1_device = {
49 .name = "sh-sci",
50 .id = 1,
51 .dev = {
52 .platform_data = &scif1_platform_data,
53 },
54};
55
56static struct plat_sci_port scif2_platform_data = {
57 .mapbase = 0xffe20000,
58 .flags = UPF_BOOT_AUTOCONF,
59 .type = PORT_SCIF,
60 .irqs = { 82, 82, 82, 82 },
61 .clk = "scif2",
62};
63
64static struct platform_device scif2_device = {
65 .name = "sh-sci",
66 .id = 2,
67 .dev = {
68 .platform_data = &scif2_platform_data,
69 },
70};
71
72static struct plat_sci_port scif3_platform_data = {
73 .mapbase = 0xa4e30000,
74 .flags = UPF_BOOT_AUTOCONF,
75 .type = PORT_SCIFA,
76 .irqs = { 56, 56, 56, 56 },
77 .clk = "scif3",
78};
79
80static struct platform_device scif3_device = {
81 .name = "sh-sci",
82 .id = 3,
83 .dev = {
84 .platform_data = &scif3_platform_data,
85 },
86};
87
88static struct plat_sci_port scif4_platform_data = {
89 .mapbase = 0xa4e40000,
90 .flags = UPF_BOOT_AUTOCONF,
91 .type = PORT_SCIFA,
92 .irqs = { 88, 88, 88, 88 },
93 .clk = "scif4",
94};
95
96static struct platform_device scif4_device = {
97 .name = "sh-sci",
98 .id = 4,
99 .dev = {
100 .platform_data = &scif4_platform_data,
101 },
102};
103
104static struct plat_sci_port scif5_platform_data = {
105 .mapbase = 0xa4e50000,
106 .flags = UPF_BOOT_AUTOCONF,
107 .type = PORT_SCIFA,
108 .irqs = { 109, 109, 109, 109 },
109 .clk = "scif5",
110};
111
112static struct platform_device scif5_device = {
113 .name = "sh-sci",
114 .id = 5,
115 .dev = {
116 .platform_data = &scif5_platform_data,
117 },
118};
119
23static struct uio_info vpu_platform_data = { 120static struct uio_info vpu_platform_data = {
24 .name = "VPU5", 121 .name = "VPU5",
25 .version = "0", 122 .version = "0",
@@ -348,56 +445,6 @@ static struct platform_device tmu5_device = {
348 }, 445 },
349}; 446};
350 447
351static struct plat_sci_port sci_platform_data[] = {
352 {
353 .mapbase = 0xffe00000,
354 .flags = UPF_BOOT_AUTOCONF,
355 .type = PORT_SCIF,
356 .irqs = { 80, 80, 80, 80 },
357 .clk = "scif0",
358 },{
359 .mapbase = 0xffe10000,
360 .flags = UPF_BOOT_AUTOCONF,
361 .type = PORT_SCIF,
362 .irqs = { 81, 81, 81, 81 },
363 .clk = "scif1",
364 },{
365 .mapbase = 0xffe20000,
366 .flags = UPF_BOOT_AUTOCONF,
367 .type = PORT_SCIF,
368 .irqs = { 82, 82, 82, 82 },
369 .clk = "scif2",
370 },{
371 .mapbase = 0xa4e30000,
372 .flags = UPF_BOOT_AUTOCONF,
373 .type = PORT_SCIFA,
374 .irqs = { 56, 56, 56, 56 },
375 .clk = "scif3",
376 },{
377 .mapbase = 0xa4e40000,
378 .flags = UPF_BOOT_AUTOCONF,
379 .type = PORT_SCIFA,
380 .irqs = { 88, 88, 88, 88 },
381 .clk = "scif4",
382 },{
383 .mapbase = 0xa4e50000,
384 .flags = UPF_BOOT_AUTOCONF,
385 .type = PORT_SCIFA,
386 .irqs = { 109, 109, 109, 109 },
387 .clk = "scif5",
388 }, {
389 .flags = 0,
390 }
391};
392
393static struct platform_device sci_device = {
394 .name = "sh-sci",
395 .id = -1,
396 .dev = {
397 .platform_data = sci_platform_data,
398 },
399};
400
401static struct resource rtc_resources[] = { 448static struct resource rtc_resources[] = {
402 [0] = { 449 [0] = {
403 .start = 0xa465fec0, 450 .start = 0xa465fec0,
@@ -488,6 +535,12 @@ static struct platform_device iic_device = {
488}; 535};
489 536
490static struct platform_device *sh7723_devices[] __initdata = { 537static struct platform_device *sh7723_devices[] __initdata = {
538 &scif0_device,
539 &scif1_device,
540 &scif2_device,
541 &scif3_device,
542 &scif4_device,
543 &scif5_device,
491 &cmt_device, 544 &cmt_device,
492 &tmu0_device, 545 &tmu0_device,
493 &tmu1_device, 546 &tmu1_device,
@@ -495,7 +548,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
495 &tmu3_device, 548 &tmu3_device,
496 &tmu4_device, 549 &tmu4_device,
497 &tmu5_device, 550 &tmu5_device,
498 &sci_device,
499 &rtc_device, 551 &rtc_device,
500 &iic_device, 552 &iic_device,
501 &sh7723_usb_host_device, 553 &sh7723_usb_host_device,
@@ -516,6 +568,12 @@ static int __init sh7723_devices_setup(void)
516arch_initcall(sh7723_devices_setup); 568arch_initcall(sh7723_devices_setup);
517 569
518static struct platform_device *sh7723_early_devices[] __initdata = { 570static struct platform_device *sh7723_early_devices[] __initdata = {
571 &scif0_device,
572 &scif1_device,
573 &scif2_device,
574 &scif3_device,
575 &scif4_device,
576 &scif5_device,
519 &cmt_device, 577 &cmt_device,
520 &tmu0_device, 578 &tmu0_device,
521 &tmu1_device, 579 &tmu1_device,
@@ -534,14 +592,17 @@ void __init plat_early_device_setup(void)
534#define RAMCR_CACHE_L2FC 0x0002 592#define RAMCR_CACHE_L2FC 0x0002
535#define RAMCR_CACHE_L2E 0x0001 593#define RAMCR_CACHE_L2E 0x0001
536#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 594#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
537void __uses_jump_to_uncached l2_cache_init(void) 595
596void l2_cache_init(void)
538{ 597{
539 /* Enable L2 cache */ 598 /* Enable L2 cache */
540 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 599 __raw_writel(L2_CACHE_ENABLE, RAMCR);
541} 600}
542 601
543enum { 602enum {
544 UNUSED=0, 603 UNUSED=0,
604 ENABLED,
605 DISABLED,
545 606
546 /* interrupt sources */ 607 /* interrupt sources */
547 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 608 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -564,7 +625,6 @@ enum {
564 SCIFA_SCIFA1, 625 SCIFA_SCIFA1,
565 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I, 626 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
566 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI, 627 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
567 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
568 CMT_CMTI, 628 CMT_CMTI,
569 TSIF_TSIFI, 629 TSIF_TSIFI,
570 SIU_SIUI, 630 SIU_SIUI,
@@ -572,7 +632,6 @@ enum {
572 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 632 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
573 IRDA_IRDAI, 633 IRDA_IRDAI,
574 ATAPI_ATAPII, 634 ATAPI_ATAPII,
575 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
576 VEU2H1_VEU2HI, 635 VEU2H1_VEU2HI,
577 LCDC_LCDCI, 636 LCDC_LCDCI,
578 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2, 637 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
@@ -643,9 +702,9 @@ static struct intc_vect vectors[] __initdata = {
643 INTC_VECT(I2C_WAITI,0xE40), 702 INTC_VECT(I2C_WAITI,0xE40),
644 INTC_VECT(I2C_DTEI,0xE60), 703 INTC_VECT(I2C_DTEI,0xE60),
645 704
646 INTC_VECT(SDHI0_SDHII0,0xE80), 705 INTC_VECT(SDHI0, 0xE80),
647 INTC_VECT(SDHI0_SDHII1,0xEA0), 706 INTC_VECT(SDHI0, 0xEA0),
648 INTC_VECT(SDHI0_SDHII2,0xEC0), 707 INTC_VECT(SDHI0, 0xEC0),
649 708
650 INTC_VECT(CMT_CMTI,0xF00), 709 INTC_VECT(CMT_CMTI,0xF00),
651 INTC_VECT(TSIF_TSIFI,0xF20), 710 INTC_VECT(TSIF_TSIFI,0xF20),
@@ -659,9 +718,9 @@ static struct intc_vect vectors[] __initdata = {
659 INTC_VECT(IRDA_IRDAI,0x480), 718 INTC_VECT(IRDA_IRDAI,0x480),
660 INTC_VECT(ATAPI_ATAPII,0x4A0), 719 INTC_VECT(ATAPI_ATAPII,0x4A0),
661 720
662 INTC_VECT(SDHI1_SDHII0,0x4E0), 721 INTC_VECT(SDHI1, 0x4E0),
663 INTC_VECT(SDHI1_SDHII1,0x500), 722 INTC_VECT(SDHI1, 0x500),
664 INTC_VECT(SDHI1_SDHII2,0x520), 723 INTC_VECT(SDHI1, 0x520),
665 724
666 INTC_VECT(VEU2H1_VEU2HI,0x560), 725 INTC_VECT(VEU2H1_VEU2HI,0x560),
667 INTC_VECT(LCDC_LCDCI,0x580), 726 INTC_VECT(LCDC_LCDCI,0x580),
@@ -680,15 +739,14 @@ static struct intc_group groups[] __initdata = {
680 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I), 739 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
681 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI), 740 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
682 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI), 741 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
683 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
684 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI), 742 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
685 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR), 743 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
686 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
687}; 744};
688 745
689static struct intc_mask_reg mask_registers[] __initdata = { 746static struct intc_mask_reg mask_registers[] __initdata = {
690 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 747 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
691 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} }, 748 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
749 0, DISABLED, ENABLED, ENABLED } },
692 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 750 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
693 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } }, 751 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
694 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 752 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
@@ -705,7 +763,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
705 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 763 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
706 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 764 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
707 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 765 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
708 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } }, 766 { 0, DISABLED, ENABLED, ENABLED,
767 0, 0, SCIFA_SCIFA2, SIU_SIUI } },
709 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 768 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
710 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } }, 769 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
711 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 770 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -745,9 +804,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
745 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 804 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
746}; 805};
747 806
748static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups, 807static struct intc_desc intc_desc __initdata = {
749 mask_registers, prio_registers, sense_registers, 808 .name = "sh7723",
750 ack_registers); 809 .force_enable = ENABLED,
810 .force_disable = DISABLED,
811 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
812 prio_registers, sense_registers, ack_registers),
813};
751 814
752void __init plat_irq_setup(void) 815void __init plat_irq_setup(void)
753{ 816{
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index f3851fd757ec..e7fa2a92fc1f 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -20,58 +20,287 @@
20#include <linux/uio_driver.h> 20#include <linux/uio_driver.h>
21#include <linux/sh_timer.h> 21#include <linux/sh_timer.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/notifier.h>
24
25#include <asm/suspend.h>
23#include <asm/clock.h> 26#include <asm/clock.h>
27#include <asm/dmaengine.h>
24#include <asm/mmzone.h> 28#include <asm/mmzone.h>
29
30#include <cpu/dma-register.h>
25#include <cpu/sh7724.h> 31#include <cpu/sh7724.h>
26 32
27/* Serial */ 33/* DMA */
28static struct plat_sci_port sci_platform_data[] = { 34static struct sh_dmae_channel sh7724_dmae0_channels[] = {
29 { 35 {
30 .mapbase = 0xffe00000, 36 .offset = 0,
31 .flags = UPF_BOOT_AUTOCONF, 37 .dmars = 0,
32 .type = PORT_SCIF, 38 .dmars_bit = 0,
33 .irqs = { 80, 80, 80, 80 }, 39 }, {
34 .clk = "scif0", 40 .offset = 0x10,
41 .dmars = 0,
42 .dmars_bit = 8,
43 }, {
44 .offset = 0x20,
45 .dmars = 4,
46 .dmars_bit = 0,
47 }, {
48 .offset = 0x30,
49 .dmars = 4,
50 .dmars_bit = 8,
35 }, { 51 }, {
36 .mapbase = 0xffe10000, 52 .offset = 0x50,
37 .flags = UPF_BOOT_AUTOCONF, 53 .dmars = 8,
38 .type = PORT_SCIF, 54 .dmars_bit = 0,
39 .irqs = { 81, 81, 81, 81 }, 55 }, {
40 .clk = "scif1", 56 .offset = 0x60,
57 .dmars = 8,
58 .dmars_bit = 8,
59 }
60};
61
62static struct sh_dmae_channel sh7724_dmae1_channels[] = {
63 {
64 .offset = 0,
65 .dmars = 0,
66 .dmars_bit = 0,
41 }, { 67 }, {
42 .mapbase = 0xffe20000, 68 .offset = 0x10,
43 .flags = UPF_BOOT_AUTOCONF, 69 .dmars = 0,
44 .type = PORT_SCIF, 70 .dmars_bit = 8,
45 .irqs = { 82, 82, 82, 82 },
46 .clk = "scif2",
47 }, { 71 }, {
48 .mapbase = 0xa4e30000, 72 .offset = 0x20,
49 .flags = UPF_BOOT_AUTOCONF, 73 .dmars = 4,
50 .type = PORT_SCIFA, 74 .dmars_bit = 0,
51 .irqs = { 56, 56, 56, 56 },
52 .clk = "scif3",
53 }, { 75 }, {
54 .mapbase = 0xa4e40000, 76 .offset = 0x30,
55 .flags = UPF_BOOT_AUTOCONF, 77 .dmars = 4,
56 .type = PORT_SCIFA, 78 .dmars_bit = 8,
57 .irqs = { 88, 88, 88, 88 },
58 .clk = "scif4",
59 }, { 79 }, {
60 .mapbase = 0xa4e50000, 80 .offset = 0x50,
61 .flags = UPF_BOOT_AUTOCONF, 81 .dmars = 8,
62 .type = PORT_SCIFA, 82 .dmars_bit = 0,
63 .irqs = { 109, 109, 109, 109 },
64 .clk = "scif5",
65 }, { 83 }, {
66 .flags = 0, 84 .offset = 0x60,
85 .dmars = 8,
86 .dmars_bit = 8,
67 } 87 }
68}; 88};
69 89
70static struct platform_device sci_device = { 90static unsigned int ts_shift[] = TS_SHIFT;
91
92static struct sh_dmae_pdata dma0_platform_data = {
93 .channel = sh7724_dmae0_channels,
94 .channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
95 .ts_low_shift = CHCR_TS_LOW_SHIFT,
96 .ts_low_mask = CHCR_TS_LOW_MASK,
97 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
98 .ts_high_mask = CHCR_TS_HIGH_MASK,
99 .ts_shift = ts_shift,
100 .ts_shift_num = ARRAY_SIZE(ts_shift),
101 .dmaor_init = DMAOR_INIT,
102};
103
104static struct sh_dmae_pdata dma1_platform_data = {
105 .channel = sh7724_dmae1_channels,
106 .channel_num = ARRAY_SIZE(sh7724_dmae1_channels),
107 .ts_low_shift = CHCR_TS_LOW_SHIFT,
108 .ts_low_mask = CHCR_TS_LOW_MASK,
109 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
110 .ts_high_mask = CHCR_TS_HIGH_MASK,
111 .ts_shift = ts_shift,
112 .ts_shift_num = ARRAY_SIZE(ts_shift),
113 .dmaor_init = DMAOR_INIT,
114};
115
116/* Resource order important! */
117static struct resource sh7724_dmae0_resources[] = {
118 {
119 /* Channel registers and DMAOR */
120 .start = 0xfe008020,
121 .end = 0xfe00808f,
122 .flags = IORESOURCE_MEM,
123 },
124 {
125 /* DMARSx */
126 .start = 0xfe009000,
127 .end = 0xfe00900b,
128 .flags = IORESOURCE_MEM,
129 },
130 {
131 /* DMA error IRQ */
132 .start = 78,
133 .end = 78,
134 .flags = IORESOURCE_IRQ,
135 },
136 {
137 /* IRQ for channels 0-3 */
138 .start = 48,
139 .end = 51,
140 .flags = IORESOURCE_IRQ,
141 },
142 {
143 /* IRQ for channels 4-5 */
144 .start = 76,
145 .end = 77,
146 .flags = IORESOURCE_IRQ,
147 },
148};
149
150/* Resource order important! */
151static struct resource sh7724_dmae1_resources[] = {
152 {
153 /* Channel registers and DMAOR */
154 .start = 0xfdc08020,
155 .end = 0xfdc0808f,
156 .flags = IORESOURCE_MEM,
157 },
158 {
159 /* DMARSx */
160 .start = 0xfdc09000,
161 .end = 0xfdc0900b,
162 .flags = IORESOURCE_MEM,
163 },
164 {
165 /* DMA error IRQ */
166 .start = 74,
167 .end = 74,
168 .flags = IORESOURCE_IRQ,
169 },
170 {
171 /* IRQ for channels 0-3 */
172 .start = 40,
173 .end = 43,
174 .flags = IORESOURCE_IRQ,
175 },
176 {
177 /* IRQ for channels 4-5 */
178 .start = 72,
179 .end = 73,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct platform_device dma0_device = {
185 .name = "sh-dma-engine",
186 .id = 0,
187 .resource = sh7724_dmae0_resources,
188 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
189 .dev = {
190 .platform_data = &dma0_platform_data,
191 },
192 .archdata = {
193 .hwblk_id = HWBLK_DMAC0,
194 },
195};
196
197static struct platform_device dma1_device = {
198 .name = "sh-dma-engine",
199 .id = 1,
200 .resource = sh7724_dmae1_resources,
201 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
202 .dev = {
203 .platform_data = &dma1_platform_data,
204 },
205 .archdata = {
206 .hwblk_id = HWBLK_DMAC1,
207 },
208};
209
210/* Serial */
211static struct plat_sci_port scif0_platform_data = {
212 .mapbase = 0xffe00000,
213 .flags = UPF_BOOT_AUTOCONF,
214 .type = PORT_SCIF,
215 .irqs = { 80, 80, 80, 80 },
216 .clk = "scif0",
217};
218
219static struct platform_device scif0_device = {
71 .name = "sh-sci", 220 .name = "sh-sci",
72 .id = -1, 221 .id = 0,
222 .dev = {
223 .platform_data = &scif0_platform_data,
224 },
225};
226
227static struct plat_sci_port scif1_platform_data = {
228 .mapbase = 0xffe10000,
229 .flags = UPF_BOOT_AUTOCONF,
230 .type = PORT_SCIF,
231 .irqs = { 81, 81, 81, 81 },
232 .clk = "scif1",
233};
234
235static struct platform_device scif1_device = {
236 .name = "sh-sci",
237 .id = 1,
73 .dev = { 238 .dev = {
74 .platform_data = sci_platform_data, 239 .platform_data = &scif1_platform_data,
240 },
241};
242
243static struct plat_sci_port scif2_platform_data = {
244 .mapbase = 0xffe20000,
245 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF,
247 .irqs = { 82, 82, 82, 82 },
248 .clk = "scif2",
249};
250
251static struct platform_device scif2_device = {
252 .name = "sh-sci",
253 .id = 2,
254 .dev = {
255 .platform_data = &scif2_platform_data,
256 },
257};
258
259static struct plat_sci_port scif3_platform_data = {
260 .mapbase = 0xa4e30000,
261 .flags = UPF_BOOT_AUTOCONF,
262 .type = PORT_SCIFA,
263 .irqs = { 56, 56, 56, 56 },
264 .clk = "scif3",
265};
266
267static struct platform_device scif3_device = {
268 .name = "sh-sci",
269 .id = 3,
270 .dev = {
271 .platform_data = &scif3_platform_data,
272 },
273};
274
275static struct plat_sci_port scif4_platform_data = {
276 .mapbase = 0xa4e40000,
277 .flags = UPF_BOOT_AUTOCONF,
278 .type = PORT_SCIFA,
279 .irqs = { 88, 88, 88, 88 },
280 .clk = "scif4",
281};
282
283static struct platform_device scif4_device = {
284 .name = "sh-sci",
285 .id = 4,
286 .dev = {
287 .platform_data = &scif4_platform_data,
288 },
289};
290
291static struct plat_sci_port scif5_platform_data = {
292 .mapbase = 0xa4e50000,
293 .flags = UPF_BOOT_AUTOCONF,
294 .type = PORT_SCIFA,
295 .irqs = { 109, 109, 109, 109 },
296 .clk = "scif5",
297};
298
299static struct platform_device scif5_device = {
300 .name = "sh-sci",
301 .id = 5,
302 .dev = {
303 .platform_data = &scif5_platform_data,
75 }, 304 },
76}; 305};
77 306
@@ -202,7 +431,7 @@ static struct resource veu0_resources[] = {
202 [0] = { 431 [0] = {
203 .name = "VEU3F0", 432 .name = "VEU3F0",
204 .start = 0xfe920000, 433 .start = 0xfe920000,
205 .end = 0xfe9200cb - 1, 434 .end = 0xfe9200cb,
206 .flags = IORESOURCE_MEM, 435 .flags = IORESOURCE_MEM,
207 }, 436 },
208 [1] = { 437 [1] = {
@@ -234,7 +463,7 @@ static struct resource veu1_resources[] = {
234 [0] = { 463 [0] = {
235 .name = "VEU3F1", 464 .name = "VEU3F1",
236 .start = 0xfe924000, 465 .start = 0xfe924000,
237 .end = 0xfe9240cb - 1, 466 .end = 0xfe9240cb,
238 .flags = IORESOURCE_MEM, 467 .flags = IORESOURCE_MEM,
239 }, 468 },
240 [1] = { 469 [1] = {
@@ -523,7 +752,77 @@ static struct platform_device jpu_device = {
523 }, 752 },
524}; 753};
525 754
755/* SPU2DSP0 */
756static struct uio_info spu0_platform_data = {
757 .name = "SPU2DSP0",
758 .version = "0",
759 .irq = 86,
760};
761
762static struct resource spu0_resources[] = {
763 [0] = {
764 .name = "SPU2DSP0",
765 .start = 0xFE200000,
766 .end = 0xFE2FFFFF,
767 .flags = IORESOURCE_MEM,
768 },
769 [1] = {
770 /* place holder for contiguous memory */
771 },
772};
773
774static struct platform_device spu0_device = {
775 .name = "uio_pdrv_genirq",
776 .id = 4,
777 .dev = {
778 .platform_data = &spu0_platform_data,
779 },
780 .resource = spu0_resources,
781 .num_resources = ARRAY_SIZE(spu0_resources),
782 .archdata = {
783 .hwblk_id = HWBLK_SPU,
784 },
785};
786
787/* SPU2DSP1 */
788static struct uio_info spu1_platform_data = {
789 .name = "SPU2DSP1",
790 .version = "0",
791 .irq = 87,
792};
793
794static struct resource spu1_resources[] = {
795 [0] = {
796 .name = "SPU2DSP1",
797 .start = 0xFE300000,
798 .end = 0xFE3FFFFF,
799 .flags = IORESOURCE_MEM,
800 },
801 [1] = {
802 /* place holder for contiguous memory */
803 },
804};
805
806static struct platform_device spu1_device = {
807 .name = "uio_pdrv_genirq",
808 .id = 5,
809 .dev = {
810 .platform_data = &spu1_platform_data,
811 },
812 .resource = spu1_resources,
813 .num_resources = ARRAY_SIZE(spu1_resources),
814 .archdata = {
815 .hwblk_id = HWBLK_SPU,
816 },
817};
818
526static struct platform_device *sh7724_devices[] __initdata = { 819static struct platform_device *sh7724_devices[] __initdata = {
820 &scif0_device,
821 &scif1_device,
822 &scif2_device,
823 &scif3_device,
824 &scif4_device,
825 &scif5_device,
527 &cmt_device, 826 &cmt_device,
528 &tmu0_device, 827 &tmu0_device,
529 &tmu1_device, 828 &tmu1_device,
@@ -531,7 +830,8 @@ static struct platform_device *sh7724_devices[] __initdata = {
531 &tmu3_device, 830 &tmu3_device,
532 &tmu4_device, 831 &tmu4_device,
533 &tmu5_device, 832 &tmu5_device,
534 &sci_device, 833 &dma0_device,
834 &dma1_device,
535 &rtc_device, 835 &rtc_device,
536 &iic0_device, 836 &iic0_device,
537 &iic1_device, 837 &iic1_device,
@@ -539,6 +839,8 @@ static struct platform_device *sh7724_devices[] __initdata = {
539 &veu0_device, 839 &veu0_device,
540 &veu1_device, 840 &veu1_device,
541 &jpu_device, 841 &jpu_device,
842 &spu0_device,
843 &spu1_device,
542}; 844};
543 845
544static int __init sh7724_devices_setup(void) 846static int __init sh7724_devices_setup(void)
@@ -547,6 +849,8 @@ static int __init sh7724_devices_setup(void)
547 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 849 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
548 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 850 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
549 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 851 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
852 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
853 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
550 854
551 return platform_add_devices(sh7724_devices, 855 return platform_add_devices(sh7724_devices,
552 ARRAY_SIZE(sh7724_devices)); 856 ARRAY_SIZE(sh7724_devices));
@@ -554,6 +858,12 @@ static int __init sh7724_devices_setup(void)
554arch_initcall(sh7724_devices_setup); 858arch_initcall(sh7724_devices_setup);
555 859
556static struct platform_device *sh7724_early_devices[] __initdata = { 860static struct platform_device *sh7724_early_devices[] __initdata = {
861 &scif0_device,
862 &scif1_device,
863 &scif2_device,
864 &scif3_device,
865 &scif4_device,
866 &scif5_device,
557 &cmt_device, 867 &cmt_device,
558 &tmu0_device, 868 &tmu0_device,
559 &tmu1_device, 869 &tmu1_device,
@@ -572,14 +882,17 @@ void __init plat_early_device_setup(void)
572#define RAMCR_CACHE_L2FC 0x0002 882#define RAMCR_CACHE_L2FC 0x0002
573#define RAMCR_CACHE_L2E 0x0001 883#define RAMCR_CACHE_L2E 0x0001
574#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 884#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
575void __uses_jump_to_uncached l2_cache_init(void) 885
886void l2_cache_init(void)
576{ 887{
577 /* Enable L2 cache */ 888 /* Enable L2 cache */
578 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 889 __raw_writel(L2_CACHE_ENABLE, RAMCR);
579} 890}
580 891
581enum { 892enum {
582 UNUSED = 0, 893 UNUSED = 0,
894 ENABLED,
895 DISABLED,
583 896
584 /* interrupt sources */ 897 /* interrupt sources */
585 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 898 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -608,14 +921,12 @@ enum {
608 ETHI, 921 ETHI,
609 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI, 922 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
610 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, 923 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
611 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
612 CMT, 924 CMT,
613 TSIF, 925 TSIF,
614 FSI, 926 FSI,
615 SCIFA5, 927 SCIFA5,
616 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, 928 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
617 IRDA, 929 IRDA,
618 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
619 JPU, 930 JPU,
620 _2DDMAC, 931 _2DDMAC,
621 MMC_MMC2I, MMC_MMC3I, 932 MMC_MMC2I, MMC_MMC3I,
@@ -697,10 +1008,10 @@ static struct intc_vect vectors[] __initdata = {
697 INTC_VECT(I2C0_WAITI, 0xE40), 1008 INTC_VECT(I2C0_WAITI, 0xE40),
698 INTC_VECT(I2C0_DTEI, 0xE60), 1009 INTC_VECT(I2C0_DTEI, 0xE60),
699 1010
700 INTC_VECT(SDHI0_SDHII0, 0xE80), 1011 INTC_VECT(SDHI0, 0xE80),
701 INTC_VECT(SDHI0_SDHII1, 0xEA0), 1012 INTC_VECT(SDHI0, 0xEA0),
702 INTC_VECT(SDHI0_SDHII2, 0xEC0), 1013 INTC_VECT(SDHI0, 0xEC0),
703 INTC_VECT(SDHI0_SDHII3, 0xEE0), 1014 INTC_VECT(SDHI0, 0xEE0),
704 1015
705 INTC_VECT(CMT, 0xF00), 1016 INTC_VECT(CMT, 0xF00),
706 INTC_VECT(TSIF, 0xF20), 1017 INTC_VECT(TSIF, 0xF20),
@@ -713,9 +1024,9 @@ static struct intc_vect vectors[] __initdata = {
713 1024
714 INTC_VECT(IRDA, 0x480), 1025 INTC_VECT(IRDA, 0x480),
715 1026
716 INTC_VECT(SDHI1_SDHII0, 0x4E0), 1027 INTC_VECT(SDHI1, 0x4E0),
717 INTC_VECT(SDHI1_SDHII1, 0x500), 1028 INTC_VECT(SDHI1, 0x500),
718 INTC_VECT(SDHI1_SDHII2, 0x520), 1029 INTC_VECT(SDHI1, 0x520),
719 1030
720 INTC_VECT(JPU, 0x560), 1031 INTC_VECT(JPU, 0x560),
721 INTC_VECT(_2DDMAC, 0x4A0), 1032 INTC_VECT(_2DDMAC, 0x4A0),
@@ -741,8 +1052,6 @@ static struct intc_group groups[] __initdata = {
741 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR), 1052 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
742 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI), 1053 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
743 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI), 1054 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
744 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
745 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
746 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1), 1055 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
747 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I), 1056 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
748}; 1057};
@@ -750,7 +1059,7 @@ static struct intc_group groups[] __initdata = {
750static struct intc_mask_reg mask_registers[] __initdata = { 1059static struct intc_mask_reg mask_registers[] __initdata = {
751 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 1060 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
752 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0, 1061 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
753 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } }, 1062 0, DISABLED, ENABLED, ENABLED } },
754 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 1063 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
755 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0, 1064 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
756 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } }, 1065 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
@@ -772,7 +1081,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
772 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI, 1081 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
773 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } }, 1082 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
774 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 1083 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
775 { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0, 1084 { DISABLED, DISABLED, ENABLED, ENABLED,
776 0, 0, SCIFA5, FSI } }, 1085 0, 0, SCIFA5, FSI } },
777 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 1086 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
778 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } }, 1087 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
@@ -819,11 +1128,205 @@ static struct intc_mask_reg ack_registers[] __initdata = {
819 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 1128 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
820}; 1129};
821 1130
822static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups, 1131static struct intc_desc intc_desc __initdata = {
823 mask_registers, prio_registers, sense_registers, 1132 .name = "sh7724",
824 ack_registers); 1133 .force_enable = ENABLED,
1134 .force_disable = DISABLED,
1135 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1136 prio_registers, sense_registers, ack_registers),
1137};
825 1138
826void __init plat_irq_setup(void) 1139void __init plat_irq_setup(void)
827{ 1140{
828 register_intc_controller(&intc_desc); 1141 register_intc_controller(&intc_desc);
829} 1142}
1143
1144static struct {
1145 /* BSC */
1146 unsigned long mmselr;
1147 unsigned long cs0bcr;
1148 unsigned long cs4bcr;
1149 unsigned long cs5abcr;
1150 unsigned long cs5bbcr;
1151 unsigned long cs6abcr;
1152 unsigned long cs6bbcr;
1153 unsigned long cs4wcr;
1154 unsigned long cs5awcr;
1155 unsigned long cs5bwcr;
1156 unsigned long cs6awcr;
1157 unsigned long cs6bwcr;
1158 /* INTC */
1159 unsigned short ipra;
1160 unsigned short iprb;
1161 unsigned short iprc;
1162 unsigned short iprd;
1163 unsigned short ipre;
1164 unsigned short iprf;
1165 unsigned short iprg;
1166 unsigned short iprh;
1167 unsigned short ipri;
1168 unsigned short iprj;
1169 unsigned short iprk;
1170 unsigned short iprl;
1171 unsigned char imr0;
1172 unsigned char imr1;
1173 unsigned char imr2;
1174 unsigned char imr3;
1175 unsigned char imr4;
1176 unsigned char imr5;
1177 unsigned char imr6;
1178 unsigned char imr7;
1179 unsigned char imr8;
1180 unsigned char imr9;
1181 unsigned char imr10;
1182 unsigned char imr11;
1183 unsigned char imr12;
1184 /* RWDT */
1185 unsigned short rwtcnt;
1186 unsigned short rwtcsr;
1187 /* CPG */
1188 unsigned long irdaclk;
1189 unsigned long spuclk;
1190} sh7724_rstandby_state;
1191
1192static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1193 unsigned long flags, void *unused)
1194{
1195 if (!(flags & SUSP_SH_RSTANDBY))
1196 return NOTIFY_DONE;
1197
1198 /* BCR */
1199 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1200 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1201 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1202 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1203 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1204 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1205 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1206 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1207 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1208 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1209 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1210 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1211 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1212
1213 /* INTC */
1214 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1215 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1216 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1217 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1218 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1219 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1220 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1221 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1222 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1223 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1224 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1225 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1226 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1227 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1228 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1229 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1230 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1231 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1232 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1233 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1234 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1235 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1236 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1237 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1238 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1239
1240 /* RWDT */
1241 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1242 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1243 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1244 sh7724_rstandby_state.rwtcsr |= 0xa500;
1245 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1246
1247 /* CPG */
1248 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1249 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1250
1251 return NOTIFY_DONE;
1252}
1253
1254static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1255 unsigned long flags, void *unused)
1256{
1257 if (!(flags & SUSP_SH_RSTANDBY))
1258 return NOTIFY_DONE;
1259
1260 /* BCR */
1261 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1262 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1263 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1264 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1265 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1266 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1267 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1268 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1269 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1270 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1271 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1272 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1273
1274 /* INTC */
1275 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1276 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1277 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1278 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1279 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1280 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1281 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1282 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1283 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1284 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1285 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1286 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1287 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1288 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1289 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1290 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1291 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1292 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1293 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1294 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1295 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1296 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1297 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1298 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1299 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1300
1301 /* RWDT */
1302 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1303 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1304
1305 /* CPG */
1306 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1307 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1308
1309 return NOTIFY_DONE;
1310}
1311
1312static struct notifier_block sh7724_pre_sleep_notifier = {
1313 .notifier_call = sh7724_pre_sleep_notifier_call,
1314 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1315};
1316
1317static struct notifier_block sh7724_post_sleep_notifier = {
1318 .notifier_call = sh7724_post_sleep_notifier_call,
1319 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1320};
1321
1322static int __init sh7724_sleep_setup(void)
1323{
1324 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1325 &sh7724_pre_sleep_notifier);
1326
1327 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1328 &sh7724_post_sleep_notifier);
1329 return 0;
1330}
1331arch_initcall(sh7724_sleep_setup);
1332
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index c470e15f2e03..e75edf58796a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -17,6 +17,51 @@
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/sh_timer.h> 18#include <linux/sh_timer.h>
19 19
20static struct plat_sci_port scif2_platform_data = {
21 .mapbase = 0xfe4b0000, /* SCIF2 */
22 .flags = UPF_BOOT_AUTOCONF,
23 .type = PORT_SCIF,
24 .irqs = { 40, 40, 40, 40 },
25};
26
27static struct platform_device scif2_device = {
28 .name = "sh-sci",
29 .id = 2,
30 .dev = {
31 .platform_data = &scif2_platform_data,
32 },
33};
34
35static struct plat_sci_port scif3_platform_data = {
36 .mapbase = 0xfe4c0000, /* SCIF3 */
37 .flags = UPF_BOOT_AUTOCONF,
38 .type = PORT_SCIF,
39 .irqs = { 76, 76, 76, 76 },
40};
41
42static struct platform_device scif3_device = {
43 .name = "sh-sci",
44 .id = 3,
45 .dev = {
46 .platform_data = &scif3_platform_data,
47 },
48};
49
50static struct plat_sci_port scif4_platform_data = {
51 .mapbase = 0xfe4d0000, /* SCIF4 */
52 .flags = UPF_BOOT_AUTOCONF,
53 .type = PORT_SCIF,
54 .irqs = { 104, 104, 104, 104 },
55};
56
57static struct platform_device scif4_device = {
58 .name = "sh-sci",
59 .id = 4,
60 .dev = {
61 .platform_data = &scif4_platform_data,
62 },
63};
64
20static struct sh_timer_config tmu0_platform_data = { 65static struct sh_timer_config tmu0_platform_data = {
21 .name = "TMU0", 66 .name = "TMU0",
22 .channel_offset = 0x04, 67 .channel_offset = 0x04,
@@ -79,39 +124,12 @@ static struct platform_device tmu1_device = {
79 .num_resources = ARRAY_SIZE(tmu1_resources), 124 .num_resources = ARRAY_SIZE(tmu1_resources),
80}; 125};
81 126
82static struct plat_sci_port sci_platform_data[] = {
83 {
84 .mapbase = 0xfe4b0000, /* SCIF2 */
85 .flags = UPF_BOOT_AUTOCONF,
86 .type = PORT_SCIF,
87 .irqs = { 40, 40, 40, 40 },
88 }, {
89 .mapbase = 0xfe4c0000, /* SCIF3 */
90 .flags = UPF_BOOT_AUTOCONF,
91 .type = PORT_SCIF,
92 .irqs = { 76, 76, 76, 76 },
93 }, {
94 .mapbase = 0xfe4d0000, /* SCIF4 */
95 .flags = UPF_BOOT_AUTOCONF,
96 .type = PORT_SCIF,
97 .irqs = { 104, 104, 104, 104 },
98 }, {
99 .flags = 0,
100 }
101};
102
103static struct platform_device sci_device = {
104 .name = "sh-sci",
105 .id = -1,
106 .dev = {
107 .platform_data = sci_platform_data,
108 },
109};
110
111static struct platform_device *sh7757_devices[] __initdata = { 127static struct platform_device *sh7757_devices[] __initdata = {
128 &scif2_device,
129 &scif3_device,
130 &scif4_device,
112 &tmu0_device, 131 &tmu0_device,
113 &tmu1_device, 132 &tmu1_device,
114 &sci_device,
115}; 133};
116 134
117static int __init sh7757_devices_setup(void) 135static int __init sh7757_devices_setup(void)
@@ -121,6 +139,20 @@ static int __init sh7757_devices_setup(void)
121} 139}
122arch_initcall(sh7757_devices_setup); 140arch_initcall(sh7757_devices_setup);
123 141
142static struct platform_device *sh7757_early_devices[] __initdata = {
143 &scif2_device,
144 &scif3_device,
145 &scif4_device,
146 &tmu0_device,
147 &tmu1_device,
148};
149
150void __init plat_early_device_setup(void)
151{
152 early_platform_add_devices(sh7757_early_devices,
153 ARRAY_SIZE(sh7757_early_devices));
154}
155
124enum { 156enum {
125 UNUSED = 0, 157 UNUSED = 0,
126 158
@@ -455,17 +487,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
455void __init plat_irq_setup(void) 487void __init plat_irq_setup(void)
456{ 488{
457 /* disable IRQ3-0 + IRQ7-4 */ 489 /* disable IRQ3-0 + IRQ7-4 */
458 ctrl_outl(0xff000000, INTC_INTMSK0); 490 __raw_writel(0xff000000, INTC_INTMSK0);
459 491
460 /* disable IRL3-0 + IRL7-4 */ 492 /* disable IRL3-0 + IRL7-4 */
461 ctrl_outl(0xc0000000, INTC_INTMSK1); 493 __raw_writel(0xc0000000, INTC_INTMSK1);
462 ctrl_outl(0xfffefffe, INTC_INTMSK2); 494 __raw_writel(0xfffefffe, INTC_INTMSK2);
463 495
464 /* select IRL mode for IRL3-0 + IRL7-4 */ 496 /* select IRL mode for IRL3-0 + IRL7-4 */
465 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 497 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
466 498
467 /* disable holding function, ie enable "SH-4 Mode" */ 499 /* disable holding function, ie enable "SH-4 Mode" */
468 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 500 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
469 501
470 register_intc_controller(&intc_desc); 502 register_intc_controller(&intc_desc);
471} 503}
@@ -475,32 +507,32 @@ void __init plat_irq_setup_pins(int mode)
475 switch (mode) { 507 switch (mode) {
476 case IRQ_MODE_IRQ7654: 508 case IRQ_MODE_IRQ7654:
477 /* select IRQ mode for IRL7-4 */ 509 /* select IRQ mode for IRL7-4 */
478 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 510 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
479 register_intc_controller(&intc_desc_irq4567); 511 register_intc_controller(&intc_desc_irq4567);
480 break; 512 break;
481 case IRQ_MODE_IRQ3210: 513 case IRQ_MODE_IRQ3210:
482 /* select IRQ mode for IRL3-0 */ 514 /* select IRQ mode for IRL3-0 */
483 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 515 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
484 register_intc_controller(&intc_desc_irq0123); 516 register_intc_controller(&intc_desc_irq0123);
485 break; 517 break;
486 case IRQ_MODE_IRL7654: 518 case IRQ_MODE_IRL7654:
487 /* enable IRL7-4 but don't provide any masking */ 519 /* enable IRL7-4 but don't provide any masking */
488 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 520 __raw_writel(0x40000000, INTC_INTMSKCLR1);
489 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 521 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
490 break; 522 break;
491 case IRQ_MODE_IRL3210: 523 case IRQ_MODE_IRL3210:
492 /* enable IRL0-3 but don't provide any masking */ 524 /* enable IRL0-3 but don't provide any masking */
493 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 525 __raw_writel(0x80000000, INTC_INTMSKCLR1);
494 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 526 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
495 break; 527 break;
496 case IRQ_MODE_IRL7654_MASK: 528 case IRQ_MODE_IRL7654_MASK:
497 /* enable IRL7-4 and mask using cpu intc controller */ 529 /* enable IRL7-4 and mask using cpu intc controller */
498 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 530 __raw_writel(0x40000000, INTC_INTMSKCLR1);
499 register_intc_controller(&intc_desc_irl4567); 531 register_intc_controller(&intc_desc_irl4567);
500 break; 532 break;
501 case IRQ_MODE_IRL3210_MASK: 533 case IRQ_MODE_IRL3210_MASK:
502 /* enable IRL0-3 and mask using cpu intc controller */ 534 /* enable IRL0-3 and mask using cpu intc controller */
503 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 535 __raw_writel(0x80000000, INTC_INTMSKCLR1);
504 register_intc_controller(&intc_desc_irl0123); 536 register_intc_controller(&intc_desc_irl0123);
505 break; 537 break;
506 default: 538 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 4659fff6b842..7f6b0a5f7f82 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -16,6 +16,51 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/serial_sci.h> 17#include <linux/serial_sci.h>
18 18
19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF,
23 .irqs = { 40, 40, 40, 40 },
24};
25
26static struct platform_device scif0_device = {
27 .name = "sh-sci",
28 .id = 0,
29 .dev = {
30 .platform_data = &scif0_platform_data,
31 },
32};
33
34static struct plat_sci_port scif1_platform_data = {
35 .mapbase = 0xffe08000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 76, 76, 76, 76 },
39};
40
41static struct platform_device scif1_device = {
42 .name = "sh-sci",
43 .id = 1,
44 .dev = {
45 .platform_data = &scif1_platform_data,
46 },
47};
48
49static struct plat_sci_port scif2_platform_data = {
50 .mapbase = 0xffe10000,
51 .flags = UPF_BOOT_AUTOCONF,
52 .type = PORT_SCIF,
53 .irqs = { 104, 104, 104, 104 },
54};
55
56static struct platform_device scif2_device = {
57 .name = "sh-sci",
58 .id = 2,
59 .dev = {
60 .platform_data = &scif2_platform_data,
61 },
62};
63
19static struct resource rtc_resources[] = { 64static struct resource rtc_resources[] = {
20 [0] = { 65 [0] = {
21 .start = 0xffe80000, 66 .start = 0xffe80000,
@@ -36,35 +81,6 @@ static struct platform_device rtc_device = {
36 .resource = rtc_resources, 81 .resource = rtc_resources,
37}; 82};
38 83
39static struct plat_sci_port sci_platform_data[] = {
40 {
41 .mapbase = 0xffe00000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF,
44 .irqs = { 40, 40, 40, 40 },
45 }, {
46 .mapbase = 0xffe08000,
47 .flags = UPF_BOOT_AUTOCONF,
48 .type = PORT_SCIF,
49 .irqs = { 76, 76, 76, 76 },
50 }, {
51 .mapbase = 0xffe10000,
52 .flags = UPF_BOOT_AUTOCONF,
53 .type = PORT_SCIF,
54 .irqs = { 104, 104, 104, 104 },
55 }, {
56 .flags = 0,
57 }
58};
59
60static struct platform_device sci_device = {
61 .name = "sh-sci",
62 .id = -1,
63 .dev = {
64 .platform_data = sci_platform_data,
65 },
66};
67
68static struct resource usb_ohci_resources[] = { 84static struct resource usb_ohci_resources[] = {
69 [0] = { 85 [0] = {
70 .start = 0xffec8000, 86 .start = 0xffec8000,
@@ -297,6 +313,9 @@ static struct platform_device tmu5_device = {
297}; 313};
298 314
299static struct platform_device *sh7763_devices[] __initdata = { 315static struct platform_device *sh7763_devices[] __initdata = {
316 &scif0_device,
317 &scif1_device,
318 &scif2_device,
300 &tmu0_device, 319 &tmu0_device,
301 &tmu1_device, 320 &tmu1_device,
302 &tmu2_device, 321 &tmu2_device,
@@ -304,7 +323,6 @@ static struct platform_device *sh7763_devices[] __initdata = {
304 &tmu4_device, 323 &tmu4_device,
305 &tmu5_device, 324 &tmu5_device,
306 &rtc_device, 325 &rtc_device,
307 &sci_device,
308 &usb_ohci_device, 326 &usb_ohci_device,
309 &usbf_device, 327 &usbf_device,
310}; 328};
@@ -317,6 +335,9 @@ static int __init sh7763_devices_setup(void)
317arch_initcall(sh7763_devices_setup); 335arch_initcall(sh7763_devices_setup);
318 336
319static struct platform_device *sh7763_early_devices[] __initdata = { 337static struct platform_device *sh7763_early_devices[] __initdata = {
338 &scif0_device,
339 &scif1_device,
340 &scif2_device,
320 &tmu0_device, 341 &tmu0_device,
321 &tmu1_device, 342 &tmu1_device,
322 &tmu2_device, 343 &tmu2_device,
@@ -517,11 +538,11 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
517void __init plat_irq_setup(void) 538void __init plat_irq_setup(void)
518{ 539{
519 /* disable IRQ7-0 */ 540 /* disable IRQ7-0 */
520 ctrl_outl(0xff000000, INTC_INTMSK0); 541 __raw_writel(0xff000000, INTC_INTMSK0);
521 542
522 /* disable IRL3-0 + IRL7-4 */ 543 /* disable IRL3-0 + IRL7-4 */
523 ctrl_outl(0xc0000000, INTC_INTMSK1); 544 __raw_writel(0xc0000000, INTC_INTMSK1);
524 ctrl_outl(0xfffefffe, INTC_INTMSK2); 545 __raw_writel(0xfffefffe, INTC_INTMSK2);
525 546
526 register_intc_controller(&intc_desc); 547 register_intc_controller(&intc_desc);
527} 548}
@@ -531,27 +552,27 @@ void __init plat_irq_setup_pins(int mode)
531 switch (mode) { 552 switch (mode) {
532 case IRQ_MODE_IRQ: 553 case IRQ_MODE_IRQ:
533 /* select IRQ mode for IRL3-0 + IRL7-4 */ 554 /* select IRQ mode for IRL3-0 + IRL7-4 */
534 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 555 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
535 register_intc_controller(&intc_irq_desc); 556 register_intc_controller(&intc_irq_desc);
536 break; 557 break;
537 case IRQ_MODE_IRL7654: 558 case IRQ_MODE_IRL7654:
538 /* enable IRL7-4 but don't provide any masking */ 559 /* enable IRL7-4 but don't provide any masking */
539 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 560 __raw_writel(0x40000000, INTC_INTMSKCLR1);
540 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 561 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
541 break; 562 break;
542 case IRQ_MODE_IRL3210: 563 case IRQ_MODE_IRL3210:
543 /* enable IRL0-3 but don't provide any masking */ 564 /* enable IRL0-3 but don't provide any masking */
544 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 565 __raw_writel(0x80000000, INTC_INTMSKCLR1);
545 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 566 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
546 break; 567 break;
547 case IRQ_MODE_IRL7654_MASK: 568 case IRQ_MODE_IRL7654_MASK:
548 /* enable IRL7-4 and mask using cpu intc controller */ 569 /* enable IRL7-4 and mask using cpu intc controller */
549 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 570 __raw_writel(0x40000000, INTC_INTMSKCLR1);
550 register_intc_controller(&intc_irl7654_desc); 571 register_intc_controller(&intc_irl7654_desc);
551 break; 572 break;
552 case IRQ_MODE_IRL3210_MASK: 573 case IRQ_MODE_IRL3210_MASK:
553 /* enable IRL0-3 and mask using cpu intc controller */ 574 /* enable IRL0-3 and mask using cpu intc controller */
554 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 575 __raw_writel(0x80000000, INTC_INTMSKCLR1);
555 register_intc_controller(&intc_irl3210_desc); 576 register_intc_controller(&intc_irl3210_desc);
556 break; 577 break;
557 default: 578 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index eead08d89d32..86d681ecf90e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -14,67 +14,153 @@
14#include <linux/sh_timer.h> 14#include <linux/sh_timer.h>
15#include <linux/io.h> 15#include <linux/io.h>
16 16
17static struct plat_sci_port sci_platform_data[] = { 17static struct plat_sci_port scif0_platform_data = {
18 { 18 .mapbase = 0xff923000,
19 .mapbase = 0xff923000, 19 .flags = UPF_BOOT_AUTOCONF,
20 .flags = UPF_BOOT_AUTOCONF, 20 .type = PORT_SCIF,
21 .type = PORT_SCIF, 21 .irqs = { 61, 61, 61, 61 },
22 .irqs = { 61, 61, 61, 61 }, 22};
23 }, { 23
24 .mapbase = 0xff924000, 24static struct platform_device scif0_device = {
25 .flags = UPF_BOOT_AUTOCONF, 25 .name = "sh-sci",
26 .type = PORT_SCIF, 26 .id = 0,
27 .irqs = { 62, 62, 62, 62 }, 27 .dev = {
28 }, { 28 .platform_data = &scif0_platform_data,
29 .mapbase = 0xff925000, 29 },
30 .flags = UPF_BOOT_AUTOCONF, 30};
31 .type = PORT_SCIF, 31
32 .irqs = { 63, 63, 63, 63 }, 32static struct plat_sci_port scif1_platform_data = {
33 }, { 33 .mapbase = 0xff924000,
34 .mapbase = 0xff926000, 34 .flags = UPF_BOOT_AUTOCONF,
35 .flags = UPF_BOOT_AUTOCONF, 35 .type = PORT_SCIF,
36 .type = PORT_SCIF, 36 .irqs = { 62, 62, 62, 62 },
37 .irqs = { 64, 64, 64, 64 }, 37};
38 }, { 38
39 .mapbase = 0xff927000, 39static struct platform_device scif1_device = {
40 .flags = UPF_BOOT_AUTOCONF, 40 .name = "sh-sci",
41 .type = PORT_SCIF, 41 .id = 1,
42 .irqs = { 65, 65, 65, 65 }, 42 .dev = {
43 }, { 43 .platform_data = &scif1_platform_data,
44 .mapbase = 0xff928000, 44 },
45 .flags = UPF_BOOT_AUTOCONF, 45};
46 .type = PORT_SCIF, 46
47 .irqs = { 66, 66, 66, 66 }, 47static struct plat_sci_port scif2_platform_data = {
48 }, { 48 .mapbase = 0xff925000,
49 .mapbase = 0xff929000, 49 .flags = UPF_BOOT_AUTOCONF,
50 .flags = UPF_BOOT_AUTOCONF, 50 .type = PORT_SCIF,
51 .type = PORT_SCIF, 51 .irqs = { 63, 63, 63, 63 },
52 .irqs = { 67, 67, 67, 67 }, 52};
53 }, { 53
54 .mapbase = 0xff92a000, 54static struct platform_device scif2_device = {
55 .flags = UPF_BOOT_AUTOCONF, 55 .name = "sh-sci",
56 .type = PORT_SCIF, 56 .id = 2,
57 .irqs = { 68, 68, 68, 68 }, 57 .dev = {
58 }, { 58 .platform_data = &scif2_platform_data,
59 .mapbase = 0xff92b000, 59 },
60 .flags = UPF_BOOT_AUTOCONF, 60};
61 .type = PORT_SCIF, 61
62 .irqs = { 69, 69, 69, 69 }, 62static struct plat_sci_port scif3_platform_data = {
63 }, { 63 .mapbase = 0xff926000,
64 .mapbase = 0xff92c000, 64 .flags = UPF_BOOT_AUTOCONF,
65 .flags = UPF_BOOT_AUTOCONF, 65 .type = PORT_SCIF,
66 .type = PORT_SCIF, 66 .irqs = { 64, 64, 64, 64 },
67 .irqs = { 70, 70, 70, 70 }, 67};
68 }, { 68
69 .flags = 0, 69static struct platform_device scif3_device = {
70 } 70 .name = "sh-sci",
71 .id = 3,
72 .dev = {
73 .platform_data = &scif3_platform_data,
74 },
75};
76
77static struct plat_sci_port scif4_platform_data = {
78 .mapbase = 0xff927000,
79 .flags = UPF_BOOT_AUTOCONF,
80 .type = PORT_SCIF,
81 .irqs = { 65, 65, 65, 65 },
82};
83
84static struct platform_device scif4_device = {
85 .name = "sh-sci",
86 .id = 4,
87 .dev = {
88 .platform_data = &scif4_platform_data,
89 },
90};
91
92static struct plat_sci_port scif5_platform_data = {
93 .mapbase = 0xff928000,
94 .flags = UPF_BOOT_AUTOCONF,
95 .type = PORT_SCIF,
96 .irqs = { 66, 66, 66, 66 },
97};
98
99static struct platform_device scif5_device = {
100 .name = "sh-sci",
101 .id = 5,
102 .dev = {
103 .platform_data = &scif5_platform_data,
104 },
105};
106
107static struct plat_sci_port scif6_platform_data = {
108 .mapbase = 0xff929000,
109 .flags = UPF_BOOT_AUTOCONF,
110 .type = PORT_SCIF,
111 .irqs = { 67, 67, 67, 67 },
112};
113
114static struct platform_device scif6_device = {
115 .name = "sh-sci",
116 .id = 6,
117 .dev = {
118 .platform_data = &scif6_platform_data,
119 },
120};
121
122static struct plat_sci_port scif7_platform_data = {
123 .mapbase = 0xff92a000,
124 .flags = UPF_BOOT_AUTOCONF,
125 .type = PORT_SCIF,
126 .irqs = { 68, 68, 68, 68 },
127};
128
129static struct platform_device scif7_device = {
130 .name = "sh-sci",
131 .id = 7,
132 .dev = {
133 .platform_data = &scif7_platform_data,
134 },
135};
136
137static struct plat_sci_port scif8_platform_data = {
138 .mapbase = 0xff92b000,
139 .flags = UPF_BOOT_AUTOCONF,
140 .type = PORT_SCIF,
141 .irqs = { 69, 69, 69, 69 },
142};
143
144static struct platform_device scif8_device = {
145 .name = "sh-sci",
146 .id = 8,
147 .dev = {
148 .platform_data = &scif8_platform_data,
149 },
150};
151
152static struct plat_sci_port scif9_platform_data = {
153 .mapbase = 0xff92c000,
154 .flags = UPF_BOOT_AUTOCONF,
155 .type = PORT_SCIF,
156 .irqs = { 70, 70, 70, 70 },
71}; 157};
72 158
73static struct platform_device sci_device = { 159static struct platform_device scif9_device = {
74 .name = "sh-sci", 160 .name = "sh-sci",
75 .id = -1, 161 .id = 9,
76 .dev = { 162 .dev = {
77 .platform_data = sci_platform_data, 163 .platform_data = &scif9_platform_data,
78 }, 164 },
79}; 165};
80 166
@@ -351,6 +437,16 @@ static struct platform_device tmu8_device = {
351}; 437};
352 438
353static struct platform_device *sh7770_devices[] __initdata = { 439static struct platform_device *sh7770_devices[] __initdata = {
440 &scif0_device,
441 &scif1_device,
442 &scif2_device,
443 &scif3_device,
444 &scif4_device,
445 &scif5_device,
446 &scif6_device,
447 &scif7_device,
448 &scif8_device,
449 &scif9_device,
354 &tmu0_device, 450 &tmu0_device,
355 &tmu1_device, 451 &tmu1_device,
356 &tmu2_device, 452 &tmu2_device,
@@ -360,7 +456,6 @@ static struct platform_device *sh7770_devices[] __initdata = {
360 &tmu6_device, 456 &tmu6_device,
361 &tmu7_device, 457 &tmu7_device,
362 &tmu8_device, 458 &tmu8_device,
363 &sci_device,
364}; 459};
365 460
366static int __init sh7770_devices_setup(void) 461static int __init sh7770_devices_setup(void)
@@ -371,6 +466,16 @@ static int __init sh7770_devices_setup(void)
371arch_initcall(sh7770_devices_setup); 466arch_initcall(sh7770_devices_setup);
372 467
373static struct platform_device *sh7770_early_devices[] __initdata = { 468static struct platform_device *sh7770_early_devices[] __initdata = {
469 &scif0_device,
470 &scif1_device,
471 &scif2_device,
472 &scif3_device,
473 &scif4_device,
474 &scif5_device,
475 &scif6_device,
476 &scif7_device,
477 &scif8_device,
478 &scif9_device,
374 &tmu0_device, 479 &tmu0_device,
375 &tmu1_device, 480 &tmu1_device,
376 &tmu2_device, 481 &tmu2_device,
@@ -589,17 +694,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
589void __init plat_irq_setup(void) 694void __init plat_irq_setup(void)
590{ 695{
591 /* disable IRQ7-0 */ 696 /* disable IRQ7-0 */
592 ctrl_outl(0xff000000, INTC_INTMSK0); 697 __raw_writel(0xff000000, INTC_INTMSK0);
593 698
594 /* disable IRL3-0 + IRL7-4 */ 699 /* disable IRL3-0 + IRL7-4 */
595 ctrl_outl(0xc0000000, INTC_INTMSK1); 700 __raw_writel(0xc0000000, INTC_INTMSK1);
596 ctrl_outl(0xfffefffe, INTC_INTMSK2); 701 __raw_writel(0xfffefffe, INTC_INTMSK2);
597 702
598 /* select IRL mode for IRL3-0 + IRL7-4 */ 703 /* select IRL mode for IRL3-0 + IRL7-4 */
599 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 704 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
600 705
601 /* disable holding function, ie enable "SH-4 Mode" */ 706 /* disable holding function, ie enable "SH-4 Mode" */
602 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 707 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
603 708
604 register_intc_controller(&intc_desc); 709 register_intc_controller(&intc_desc);
605} 710}
@@ -609,27 +714,27 @@ void __init plat_irq_setup_pins(int mode)
609 switch (mode) { 714 switch (mode) {
610 case IRQ_MODE_IRQ: 715 case IRQ_MODE_IRQ:
611 /* select IRQ mode for IRL3-0 + IRL7-4 */ 716 /* select IRQ mode for IRL3-0 + IRL7-4 */
612 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 717 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
613 register_intc_controller(&intc_irq_desc); 718 register_intc_controller(&intc_irq_desc);
614 break; 719 break;
615 case IRQ_MODE_IRL7654: 720 case IRQ_MODE_IRL7654:
616 /* enable IRL7-4 but don't provide any masking */ 721 /* enable IRL7-4 but don't provide any masking */
617 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 722 __raw_writel(0x40000000, INTC_INTMSKCLR1);
618 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 723 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
619 break; 724 break;
620 case IRQ_MODE_IRL3210: 725 case IRQ_MODE_IRL3210:
621 /* enable IRL0-3 but don't provide any masking */ 726 /* enable IRL0-3 but don't provide any masking */
622 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 727 __raw_writel(0x80000000, INTC_INTMSKCLR1);
623 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 728 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
624 break; 729 break;
625 case IRQ_MODE_IRL7654_MASK: 730 case IRQ_MODE_IRL7654_MASK:
626 /* enable IRL7-4 and mask using cpu intc controller */ 731 /* enable IRL7-4 and mask using cpu intc controller */
627 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 732 __raw_writel(0x40000000, INTC_INTMSKCLR1);
628 register_intc_controller(&intc_irl7654_desc); 733 register_intc_controller(&intc_irl7654_desc);
629 break; 734 break;
630 case IRQ_MODE_IRL3210_MASK: 735 case IRQ_MODE_IRL3210_MASK:
631 /* enable IRL0-3 and mask using cpu intc controller */ 736 /* enable IRL0-3 and mask using cpu intc controller */
632 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 737 __raw_writel(0x80000000, INTC_INTMSKCLR1);
633 register_intc_controller(&intc_irl3210_desc); 738 register_intc_controller(&intc_irl3210_desc);
634 break; 739 break;
635 default: 740 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 12ff56f19c5c..02e792c90de6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -13,7 +13,40 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <asm/dma-sh.h> 16
17#include <asm/dmaengine.h>
18
19#include <cpu/dma-register.h>
20
21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF,
24 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 },
26};
27
28static struct platform_device scif0_device = {
29 .name = "sh-sci",
30 .id = 0,
31 .dev = {
32 .platform_data = &scif0_platform_data,
33 },
34};
35
36static struct plat_sci_port scif1_platform_data = {
37 .mapbase = 0xffe10000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .type = PORT_SCIF,
40 .irqs = { 76, 76, 76, 76 },
41};
42
43static struct platform_device scif1_device = {
44 .name = "sh-sci",
45 .id = 1,
46 .dev = {
47 .platform_data = &scif1_platform_data,
48 },
49};
17 50
18static struct sh_timer_config tmu0_platform_data = { 51static struct sh_timer_config tmu0_platform_data = {
19 .name = "TMU0", 52 .name = "TMU0",
@@ -217,43 +250,137 @@ static struct platform_device rtc_device = {
217 .resource = rtc_resources, 250 .resource = rtc_resources,
218}; 251};
219 252
220static struct plat_sci_port sci_platform_data[] = { 253/* DMA */
254static struct sh_dmae_channel sh7780_dmae0_channels[] = {
221 { 255 {
222 .mapbase = 0xffe00000, 256 .offset = 0,
223 .flags = UPF_BOOT_AUTOCONF, 257 .dmars = 0,
224 .type = PORT_SCIF, 258 .dmars_bit = 0,
225 .irqs = { 40, 40, 40, 40 }, 259 }, {
260 .offset = 0x10,
261 .dmars = 0,
262 .dmars_bit = 8,
263 }, {
264 .offset = 0x20,
265 .dmars = 4,
266 .dmars_bit = 0,
267 }, {
268 .offset = 0x30,
269 .dmars = 4,
270 .dmars_bit = 8,
226 }, { 271 }, {
227 .mapbase = 0xffe10000, 272 .offset = 0x50,
228 .flags = UPF_BOOT_AUTOCONF, 273 .dmars = 8,
229 .type = PORT_SCIF, 274 .dmars_bit = 0,
230 .irqs = { 76, 76, 76, 76 },
231 }, { 275 }, {
232 .flags = 0, 276 .offset = 0x60,
277 .dmars = 8,
278 .dmars_bit = 8,
233 } 279 }
234}; 280};
235 281
236static struct platform_device sci_device = { 282static struct sh_dmae_channel sh7780_dmae1_channels[] = {
237 .name = "sh-sci", 283 {
238 .id = -1, 284 .offset = 0,
239 .dev = { 285 }, {
240 .platform_data = sci_platform_data, 286 .offset = 0x10,
287 }, {
288 .offset = 0x20,
289 }, {
290 .offset = 0x30,
291 }, {
292 .offset = 0x50,
293 }, {
294 .offset = 0x60,
295 }
296};
297
298static unsigned int ts_shift[] = TS_SHIFT;
299
300static struct sh_dmae_pdata dma0_platform_data = {
301 .channel = sh7780_dmae0_channels,
302 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
303 .ts_low_shift = CHCR_TS_LOW_SHIFT,
304 .ts_low_mask = CHCR_TS_LOW_MASK,
305 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
306 .ts_high_mask = CHCR_TS_HIGH_MASK,
307 .ts_shift = ts_shift,
308 .ts_shift_num = ARRAY_SIZE(ts_shift),
309 .dmaor_init = DMAOR_INIT,
310};
311
312static struct sh_dmae_pdata dma1_platform_data = {
313 .channel = sh7780_dmae1_channels,
314 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
315 .ts_low_shift = CHCR_TS_LOW_SHIFT,
316 .ts_low_mask = CHCR_TS_LOW_MASK,
317 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
318 .ts_high_mask = CHCR_TS_HIGH_MASK,
319 .ts_shift = ts_shift,
320 .ts_shift_num = ARRAY_SIZE(ts_shift),
321 .dmaor_init = DMAOR_INIT,
322};
323
324static struct resource sh7780_dmae0_resources[] = {
325 [0] = {
326 /* Channel registers and DMAOR */
327 .start = 0xfc808020,
328 .end = 0xfc80808f,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 /* DMARSx */
333 .start = 0xfc809000,
334 .end = 0xfc80900b,
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
339 .start = 34,
340 .end = 34,
341 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
241 }, 342 },
242}; 343};
243 344
244static struct sh_dmae_pdata dma_platform_data = { 345static struct resource sh7780_dmae1_resources[] = {
245 .mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1), 346 [0] = {
347 /* Channel registers and DMAOR */
348 .start = 0xfc818020,
349 .end = 0xfc81808f,
350 .flags = IORESOURCE_MEM,
351 },
352 /* DMAC1 has no DMARS */
353 {
354 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
355 .start = 46,
356 .end = 46,
357 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
358 },
246}; 359};
247 360
248static struct platform_device dma_device = { 361static struct platform_device dma0_device = {
249 .name = "sh-dma-engine", 362 .name = "sh-dma-engine",
250 .id = -1, 363 .id = 0,
364 .resource = sh7780_dmae0_resources,
365 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
251 .dev = { 366 .dev = {
252 .platform_data = &dma_platform_data, 367 .platform_data = &dma0_platform_data,
368 },
369};
370
371static struct platform_device dma1_device = {
372 .name = "sh-dma-engine",
373 .id = 1,
374 .resource = sh7780_dmae1_resources,
375 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
376 .dev = {
377 .platform_data = &dma1_platform_data,
253 }, 378 },
254}; 379};
255 380
256static struct platform_device *sh7780_devices[] __initdata = { 381static struct platform_device *sh7780_devices[] __initdata = {
382 &scif0_device,
383 &scif1_device,
257 &tmu0_device, 384 &tmu0_device,
258 &tmu1_device, 385 &tmu1_device,
259 &tmu2_device, 386 &tmu2_device,
@@ -261,8 +388,8 @@ static struct platform_device *sh7780_devices[] __initdata = {
261 &tmu4_device, 388 &tmu4_device,
262 &tmu5_device, 389 &tmu5_device,
263 &rtc_device, 390 &rtc_device,
264 &sci_device, 391 &dma0_device,
265 &dma_device, 392 &dma1_device,
266}; 393};
267 394
268static int __init sh7780_devices_setup(void) 395static int __init sh7780_devices_setup(void)
@@ -271,8 +398,9 @@ static int __init sh7780_devices_setup(void)
271 ARRAY_SIZE(sh7780_devices)); 398 ARRAY_SIZE(sh7780_devices));
272} 399}
273arch_initcall(sh7780_devices_setup); 400arch_initcall(sh7780_devices_setup);
274
275static struct platform_device *sh7780_early_devices[] __initdata = { 401static struct platform_device *sh7780_early_devices[] __initdata = {
402 &scif0_device,
403 &scif1_device,
276 &tmu0_device, 404 &tmu0_device,
277 &tmu1_device, 405 &tmu1_device,
278 &tmu2_device, 406 &tmu2_device,
@@ -453,17 +581,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
453void __init plat_irq_setup(void) 581void __init plat_irq_setup(void)
454{ 582{
455 /* disable IRQ7-0 */ 583 /* disable IRQ7-0 */
456 ctrl_outl(0xff000000, INTC_INTMSK0); 584 __raw_writel(0xff000000, INTC_INTMSK0);
457 585
458 /* disable IRL3-0 + IRL7-4 */ 586 /* disable IRL3-0 + IRL7-4 */
459 ctrl_outl(0xc0000000, INTC_INTMSK1); 587 __raw_writel(0xc0000000, INTC_INTMSK1);
460 ctrl_outl(0xfffefffe, INTC_INTMSK2); 588 __raw_writel(0xfffefffe, INTC_INTMSK2);
461 589
462 /* select IRL mode for IRL3-0 + IRL7-4 */ 590 /* select IRL mode for IRL3-0 + IRL7-4 */
463 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 591 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
464 592
465 /* disable holding function, ie enable "SH-4 Mode" */ 593 /* disable holding function, ie enable "SH-4 Mode" */
466 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 594 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
467 595
468 register_intc_controller(&intc_desc); 596 register_intc_controller(&intc_desc);
469} 597}
@@ -473,27 +601,27 @@ void __init plat_irq_setup_pins(int mode)
473 switch (mode) { 601 switch (mode) {
474 case IRQ_MODE_IRQ: 602 case IRQ_MODE_IRQ:
475 /* select IRQ mode for IRL3-0 + IRL7-4 */ 603 /* select IRQ mode for IRL3-0 + IRL7-4 */
476 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 604 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
477 register_intc_controller(&intc_irq_desc); 605 register_intc_controller(&intc_irq_desc);
478 break; 606 break;
479 case IRQ_MODE_IRL7654: 607 case IRQ_MODE_IRL7654:
480 /* enable IRL7-4 but don't provide any masking */ 608 /* enable IRL7-4 but don't provide any masking */
481 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 609 __raw_writel(0x40000000, INTC_INTMSKCLR1);
482 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 610 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
483 break; 611 break;
484 case IRQ_MODE_IRL3210: 612 case IRQ_MODE_IRL3210:
485 /* enable IRL0-3 but don't provide any masking */ 613 /* enable IRL0-3 but don't provide any masking */
486 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 614 __raw_writel(0x80000000, INTC_INTMSKCLR1);
487 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 615 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
488 break; 616 break;
489 case IRQ_MODE_IRL7654_MASK: 617 case IRQ_MODE_IRL7654_MASK:
490 /* enable IRL7-4 and mask using cpu intc controller */ 618 /* enable IRL7-4 and mask using cpu intc controller */
491 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 619 __raw_writel(0x40000000, INTC_INTMSKCLR1);
492 register_intc_controller(&intc_irl7654_desc); 620 register_intc_controller(&intc_irl7654_desc);
493 break; 621 break;
494 case IRQ_MODE_IRL3210_MASK: 622 case IRQ_MODE_IRL3210_MASK:
495 /* enable IRL0-3 and mask using cpu intc controller */ 623 /* enable IRL0-3 and mask using cpu intc controller */
496 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 624 __raw_writel(0x80000000, INTC_INTMSKCLR1);
497 register_intc_controller(&intc_irl3210_desc); 625 register_intc_controller(&intc_irl3210_desc);
498 break; 626 break;
499 default: 627 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 7f6c718b6c36..1fcd88b1671e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -14,8 +14,108 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17
18#include <asm/dmaengine.h>
17#include <asm/mmzone.h> 19#include <asm/mmzone.h>
18 20
21#include <cpu/dma-register.h>
22
23static struct plat_sci_port scif0_platform_data = {
24 .mapbase = 0xffea0000,
25 .flags = UPF_BOOT_AUTOCONF,
26 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 },
28 .clk = "scif_fck",
29};
30
31static struct platform_device scif0_device = {
32 .name = "sh-sci",
33 .id = 0,
34 .dev = {
35 .platform_data = &scif0_platform_data,
36 },
37};
38
39static struct plat_sci_port scif1_platform_data = {
40 .mapbase = 0xffeb0000,
41 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF,
43 .irqs = { 44, 44, 44, 44 },
44 .clk = "scif_fck",
45};
46
47static struct platform_device scif1_device = {
48 .name = "sh-sci",
49 .id = 1,
50 .dev = {
51 .platform_data = &scif1_platform_data,
52 },
53};
54
55static struct plat_sci_port scif2_platform_data = {
56 .mapbase = 0xffec0000,
57 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIF,
59 .irqs = { 60, 60, 60, 60 },
60 .clk = "scif_fck",
61};
62
63static struct platform_device scif2_device = {
64 .name = "sh-sci",
65 .id = 2,
66 .dev = {
67 .platform_data = &scif2_platform_data,
68 },
69};
70
71static struct plat_sci_port scif3_platform_data = {
72 .mapbase = 0xffed0000,
73 .flags = UPF_BOOT_AUTOCONF,
74 .type = PORT_SCIF,
75 .irqs = { 61, 61, 61, 61 },
76 .clk = "scif_fck",
77};
78
79static struct platform_device scif3_device = {
80 .name = "sh-sci",
81 .id = 3,
82 .dev = {
83 .platform_data = &scif3_platform_data,
84 },
85};
86
87static struct plat_sci_port scif4_platform_data = {
88 .mapbase = 0xffee0000,
89 .flags = UPF_BOOT_AUTOCONF,
90 .type = PORT_SCIF,
91 .irqs = { 62, 62, 62, 62 },
92 .clk = "scif_fck",
93};
94
95static struct platform_device scif4_device = {
96 .name = "sh-sci",
97 .id = 4,
98 .dev = {
99 .platform_data = &scif4_platform_data,
100 },
101};
102
103static struct plat_sci_port scif5_platform_data = {
104 .mapbase = 0xffef0000,
105 .flags = UPF_BOOT_AUTOCONF,
106 .type = PORT_SCIF,
107 .irqs = { 63, 63, 63, 63 },
108 .clk = "scif_fck",
109};
110
111static struct platform_device scif5_device = {
112 .name = "sh-sci",
113 .id = 5,
114 .dev = {
115 .platform_data = &scif5_platform_data,
116 },
117};
118
19static struct sh_timer_config tmu0_platform_data = { 119static struct sh_timer_config tmu0_platform_data = {
20 .name = "TMU0", 120 .name = "TMU0",
21 .channel_offset = 0x04, 121 .channel_offset = 0x04,
@@ -198,64 +298,149 @@ static struct platform_device tmu5_device = {
198 .num_resources = ARRAY_SIZE(tmu5_resources), 298 .num_resources = ARRAY_SIZE(tmu5_resources),
199}; 299};
200 300
201static struct plat_sci_port sci_platform_data[] = { 301/* DMA */
302static struct sh_dmae_channel sh7785_dmae0_channels[] = {
202 { 303 {
203 .mapbase = 0xffea0000, 304 .offset = 0,
204 .flags = UPF_BOOT_AUTOCONF, 305 .dmars = 0,
205 .type = PORT_SCIF, 306 .dmars_bit = 0,
206 .irqs = { 40, 40, 40, 40 },
207 .clk = "scif_fck",
208 }, { 307 }, {
209 .mapbase = 0xffeb0000, 308 .offset = 0x10,
210 .flags = UPF_BOOT_AUTOCONF, 309 .dmars = 0,
211 .type = PORT_SCIF, 310 .dmars_bit = 8,
212 .irqs = { 44, 44, 44, 44 },
213 .clk = "scif_fck",
214 }, { 311 }, {
215 .mapbase = 0xffec0000, 312 .offset = 0x20,
216 .flags = UPF_BOOT_AUTOCONF, 313 .dmars = 4,
217 .type = PORT_SCIF, 314 .dmars_bit = 0,
218 .irqs = { 60, 60, 60, 60 },
219 .clk = "scif_fck",
220 }, { 315 }, {
221 .mapbase = 0xffed0000, 316 .offset = 0x30,
222 .flags = UPF_BOOT_AUTOCONF, 317 .dmars = 4,
223 .type = PORT_SCIF, 318 .dmars_bit = 8,
224 .irqs = { 61, 61, 61, 61 },
225 .clk = "scif_fck",
226 }, { 319 }, {
227 .mapbase = 0xffee0000, 320 .offset = 0x50,
228 .flags = UPF_BOOT_AUTOCONF, 321 .dmars = 8,
229 .type = PORT_SCIF, 322 .dmars_bit = 0,
230 .irqs = { 62, 62, 62, 62 },
231 .clk = "scif_fck",
232 }, { 323 }, {
233 .mapbase = 0xffef0000, 324 .offset = 0x60,
234 .flags = UPF_BOOT_AUTOCONF, 325 .dmars = 8,
235 .type = PORT_SCIF, 326 .dmars_bit = 8,
236 .irqs = { 63, 63, 63, 63 }, 327 }
237 .clk = "scif_fck", 328};
329
330static struct sh_dmae_channel sh7785_dmae1_channels[] = {
331 {
332 .offset = 0,
238 }, { 333 }, {
239 .flags = 0, 334 .offset = 0x10,
335 }, {
336 .offset = 0x20,
337 }, {
338 .offset = 0x30,
339 }, {
340 .offset = 0x50,
341 }, {
342 .offset = 0x60,
240 } 343 }
241}; 344};
242 345
243static struct platform_device sci_device = { 346static unsigned int ts_shift[] = TS_SHIFT;
244 .name = "sh-sci", 347
245 .id = -1, 348static struct sh_dmae_pdata dma0_platform_data = {
349 .channel = sh7785_dmae0_channels,
350 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
351 .ts_low_shift = CHCR_TS_LOW_SHIFT,
352 .ts_low_mask = CHCR_TS_LOW_MASK,
353 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
354 .ts_high_mask = CHCR_TS_HIGH_MASK,
355 .ts_shift = ts_shift,
356 .ts_shift_num = ARRAY_SIZE(ts_shift),
357 .dmaor_init = DMAOR_INIT,
358};
359
360static struct sh_dmae_pdata dma1_platform_data = {
361 .channel = sh7785_dmae1_channels,
362 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
363 .ts_low_shift = CHCR_TS_LOW_SHIFT,
364 .ts_low_mask = CHCR_TS_LOW_MASK,
365 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
366 .ts_high_mask = CHCR_TS_HIGH_MASK,
367 .ts_shift = ts_shift,
368 .ts_shift_num = ARRAY_SIZE(ts_shift),
369 .dmaor_init = DMAOR_INIT,
370};
371
372static struct resource sh7785_dmae0_resources[] = {
373 [0] = {
374 /* Channel registers and DMAOR */
375 .start = 0xfc808020,
376 .end = 0xfc80808f,
377 .flags = IORESOURCE_MEM,
378 },
379 [1] = {
380 /* DMARSx */
381 .start = 0xfc809000,
382 .end = 0xfc80900b,
383 .flags = IORESOURCE_MEM,
384 },
385 {
386 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
387 .start = 33,
388 .end = 33,
389 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
390 },
391};
392
393static struct resource sh7785_dmae1_resources[] = {
394 [0] = {
395 /* Channel registers and DMAOR */
396 .start = 0xfcc08020,
397 .end = 0xfcc0808f,
398 .flags = IORESOURCE_MEM,
399 },
400 /* DMAC1 has no DMARS */
401 {
402 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
403 .start = 52,
404 .end = 52,
405 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
406 },
407};
408
409static struct platform_device dma0_device = {
410 .name = "sh-dma-engine",
411 .id = 0,
412 .resource = sh7785_dmae0_resources,
413 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
414 .dev = {
415 .platform_data = &dma0_platform_data,
416 },
417};
418
419static struct platform_device dma1_device = {
420 .name = "sh-dma-engine",
421 .id = 1,
422 .resource = sh7785_dmae1_resources,
423 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
246 .dev = { 424 .dev = {
247 .platform_data = sci_platform_data, 425 .platform_data = &dma1_platform_data,
248 }, 426 },
249}; 427};
250 428
251static struct platform_device *sh7785_devices[] __initdata = { 429static struct platform_device *sh7785_devices[] __initdata = {
430 &scif0_device,
431 &scif1_device,
432 &scif2_device,
433 &scif3_device,
434 &scif4_device,
435 &scif5_device,
252 &tmu0_device, 436 &tmu0_device,
253 &tmu1_device, 437 &tmu1_device,
254 &tmu2_device, 438 &tmu2_device,
255 &tmu3_device, 439 &tmu3_device,
256 &tmu4_device, 440 &tmu4_device,
257 &tmu5_device, 441 &tmu5_device,
258 &sci_device, 442 &dma0_device,
443 &dma1_device,
259}; 444};
260 445
261static int __init sh7785_devices_setup(void) 446static int __init sh7785_devices_setup(void)
@@ -266,6 +451,12 @@ static int __init sh7785_devices_setup(void)
266arch_initcall(sh7785_devices_setup); 451arch_initcall(sh7785_devices_setup);
267 452
268static struct platform_device *sh7785_early_devices[] __initdata = { 453static struct platform_device *sh7785_early_devices[] __initdata = {
454 &scif0_device,
455 &scif1_device,
456 &scif2_device,
457 &scif3_device,
458 &scif4_device,
459 &scif5_device,
269 &tmu0_device, 460 &tmu0_device,
270 &tmu1_device, 461 &tmu1_device,
271 &tmu2_device, 462 &tmu2_device,
@@ -470,17 +661,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
470void __init plat_irq_setup(void) 661void __init plat_irq_setup(void)
471{ 662{
472 /* disable IRQ3-0 + IRQ7-4 */ 663 /* disable IRQ3-0 + IRQ7-4 */
473 ctrl_outl(0xff000000, INTC_INTMSK0); 664 __raw_writel(0xff000000, INTC_INTMSK0);
474 665
475 /* disable IRL3-0 + IRL7-4 */ 666 /* disable IRL3-0 + IRL7-4 */
476 ctrl_outl(0xc0000000, INTC_INTMSK1); 667 __raw_writel(0xc0000000, INTC_INTMSK1);
477 ctrl_outl(0xfffefffe, INTC_INTMSK2); 668 __raw_writel(0xfffefffe, INTC_INTMSK2);
478 669
479 /* select IRL mode for IRL3-0 + IRL7-4 */ 670 /* select IRL mode for IRL3-0 + IRL7-4 */
480 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 671 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
481 672
482 /* disable holding function, ie enable "SH-4 Mode" */ 673 /* disable holding function, ie enable "SH-4 Mode" */
483 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 674 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
484 675
485 register_intc_controller(&intc_desc); 676 register_intc_controller(&intc_desc);
486} 677}
@@ -490,32 +681,32 @@ void __init plat_irq_setup_pins(int mode)
490 switch (mode) { 681 switch (mode) {
491 case IRQ_MODE_IRQ7654: 682 case IRQ_MODE_IRQ7654:
492 /* select IRQ mode for IRL7-4 */ 683 /* select IRQ mode for IRL7-4 */
493 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 684 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
494 register_intc_controller(&intc_desc_irq4567); 685 register_intc_controller(&intc_desc_irq4567);
495 break; 686 break;
496 case IRQ_MODE_IRQ3210: 687 case IRQ_MODE_IRQ3210:
497 /* select IRQ mode for IRL3-0 */ 688 /* select IRQ mode for IRL3-0 */
498 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 689 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
499 register_intc_controller(&intc_desc_irq0123); 690 register_intc_controller(&intc_desc_irq0123);
500 break; 691 break;
501 case IRQ_MODE_IRL7654: 692 case IRQ_MODE_IRL7654:
502 /* enable IRL7-4 but don't provide any masking */ 693 /* enable IRL7-4 but don't provide any masking */
503 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 694 __raw_writel(0x40000000, INTC_INTMSKCLR1);
504 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 695 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
505 break; 696 break;
506 case IRQ_MODE_IRL3210: 697 case IRQ_MODE_IRL3210:
507 /* enable IRL0-3 but don't provide any masking */ 698 /* enable IRL0-3 but don't provide any masking */
508 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 699 __raw_writel(0x80000000, INTC_INTMSKCLR1);
509 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 700 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
510 break; 701 break;
511 case IRQ_MODE_IRL7654_MASK: 702 case IRQ_MODE_IRL7654_MASK:
512 /* enable IRL7-4 and mask using cpu intc controller */ 703 /* enable IRL7-4 and mask using cpu intc controller */
513 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 704 __raw_writel(0x40000000, INTC_INTMSKCLR1);
514 register_intc_controller(&intc_desc_irl4567); 705 register_intc_controller(&intc_desc_irl4567);
515 break; 706 break;
516 case IRQ_MODE_IRL3210_MASK: 707 case IRQ_MODE_IRL3210_MASK:
517 /* enable IRL0-3 and mask using cpu intc controller */ 708 /* enable IRL0-3 and mask using cpu intc controller */
518 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 709 __raw_writel(0x80000000, INTC_INTMSKCLR1);
519 register_intc_controller(&intc_desc_irl0123); 710 register_intc_controller(&intc_desc_irl0123);
520 break; 711 break;
521 default: 712 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 0104a8ec5369..7e585320710a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -23,51 +23,96 @@
23#include <linux/sh_timer.h> 23#include <linux/sh_timer.h>
24#include <asm/mmzone.h> 24#include <asm/mmzone.h>
25 25
26static struct plat_sci_port sci_platform_data[] = { 26static struct plat_sci_port scif0_platform_data = {
27 { 27 .mapbase = 0xffea0000,
28 .mapbase = 0xffea0000, 28 .flags = UPF_BOOT_AUTOCONF,
29 .flags = UPF_BOOT_AUTOCONF, 29 .type = PORT_SCIF,
30 .type = PORT_SCIF, 30 .irqs = { 40, 41, 43, 42 },
31 .irqs = { 40, 41, 43, 42 }, 31};
32
33static struct platform_device scif0_device = {
34 .name = "sh-sci",
35 .id = 0,
36 .dev = {
37 .platform_data = &scif0_platform_data,
32 }, 38 },
33 /*
34 * The rest of these all have multiplexed IRQs
35 */
36 {
37 .mapbase = 0xffeb0000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .type = PORT_SCIF,
40 .irqs = { 44, 44, 44, 44 },
41 }, {
42 .mapbase = 0xffec0000,
43 .flags = UPF_BOOT_AUTOCONF,
44 .type = PORT_SCIF,
45 .irqs = { 50, 50, 50, 50 },
46 }, {
47 .mapbase = 0xffed0000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIF,
50 .irqs = { 51, 51, 51, 51 },
51 }, {
52 .mapbase = 0xffee0000,
53 .flags = UPF_BOOT_AUTOCONF,
54 .type = PORT_SCIF,
55 .irqs = { 52, 52, 52, 52 },
56 }, {
57 .mapbase = 0xffef0000,
58 .flags = UPF_BOOT_AUTOCONF,
59 .type = PORT_SCIF,
60 .irqs = { 53, 53, 53, 53 },
61 }, {
62 .flags = 0,
63 }
64}; 39};
65 40
66static struct platform_device sci_device = { 41/*
42 * The rest of these all have multiplexed IRQs
43 */
44static struct plat_sci_port scif1_platform_data = {
45 .mapbase = 0xffeb0000,
46 .flags = UPF_BOOT_AUTOCONF,
47 .type = PORT_SCIF,
48 .irqs = { 44, 44, 44, 44 },
49};
50
51static struct platform_device scif1_device = {
67 .name = "sh-sci", 52 .name = "sh-sci",
68 .id = -1, 53 .id = 1,
54 .dev = {
55 .platform_data = &scif1_platform_data,
56 },
57};
58
59static struct plat_sci_port scif2_platform_data = {
60 .mapbase = 0xffec0000,
61 .flags = UPF_BOOT_AUTOCONF,
62 .type = PORT_SCIF,
63 .irqs = { 50, 50, 50, 50 },
64};
65
66static struct platform_device scif2_device = {
67 .name = "sh-sci",
68 .id = 2,
69 .dev = {
70 .platform_data = &scif2_platform_data,
71 },
72};
73
74static struct plat_sci_port scif3_platform_data = {
75 .mapbase = 0xffed0000,
76 .flags = UPF_BOOT_AUTOCONF,
77 .type = PORT_SCIF,
78 .irqs = { 51, 51, 51, 51 },
79};
80
81static struct platform_device scif3_device = {
82 .name = "sh-sci",
83 .id = 3,
84 .dev = {
85 .platform_data = &scif3_platform_data,
86 },
87};
88
89static struct plat_sci_port scif4_platform_data = {
90 .mapbase = 0xffee0000,
91 .flags = UPF_BOOT_AUTOCONF,
92 .type = PORT_SCIF,
93 .irqs = { 52, 52, 52, 52 },
94};
95
96static struct platform_device scif4_device = {
97 .name = "sh-sci",
98 .id = 4,
99 .dev = {
100 .platform_data = &scif4_platform_data,
101 },
102};
103
104static struct plat_sci_port scif5_platform_data = {
105 .mapbase = 0xffef0000,
106 .flags = UPF_BOOT_AUTOCONF,
107 .type = PORT_SCIF,
108 .irqs = { 53, 53, 53, 53 },
109};
110
111static struct platform_device scif5_device = {
112 .name = "sh-sci",
113 .id = 5,
69 .dev = { 114 .dev = {
70 .platform_data = sci_platform_data, 115 .platform_data = &scif5_platform_data,
71 }, 116 },
72}; 117};
73 118
@@ -459,6 +504,12 @@ static struct platform_device usb_ohci_device = {
459}; 504};
460 505
461static struct platform_device *sh7786_early_devices[] __initdata = { 506static struct platform_device *sh7786_early_devices[] __initdata = {
507 &scif0_device,
508 &scif1_device,
509 &scif2_device,
510 &scif3_device,
511 &scif4_device,
512 &scif5_device,
462 &tmu0_device, 513 &tmu0_device,
463 &tmu1_device, 514 &tmu1_device,
464 &tmu2_device, 515 &tmu2_device,
@@ -474,7 +525,6 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
474}; 525};
475 526
476static struct platform_device *sh7786_devices[] __initdata = { 527static struct platform_device *sh7786_devices[] __initdata = {
477 &sci_device,
478 &usb_ohci_device, 528 &usb_ohci_device,
479}; 529};
480 530
@@ -817,14 +867,14 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
817void __init plat_irq_setup(void) 867void __init plat_irq_setup(void)
818{ 868{
819 /* disable IRQ3-0 + IRQ7-4 */ 869 /* disable IRQ3-0 + IRQ7-4 */
820 ctrl_outl(0xff000000, INTC_INTMSK0); 870 __raw_writel(0xff000000, INTC_INTMSK0);
821 871
822 /* disable IRL3-0 + IRL7-4 */ 872 /* disable IRL3-0 + IRL7-4 */
823 ctrl_outl(0xc0000000, INTC_INTMSK1); 873 __raw_writel(0xc0000000, INTC_INTMSK1);
824 ctrl_outl(0xfffefffe, INTC_INTMSK2); 874 __raw_writel(0xfffefffe, INTC_INTMSK2);
825 875
826 /* select IRL mode for IRL3-0 + IRL7-4 */ 876 /* select IRL mode for IRL3-0 + IRL7-4 */
827 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 877 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
828 878
829 register_intc_controller(&intc_desc); 879 register_intc_controller(&intc_desc);
830} 880}
@@ -834,32 +884,32 @@ void __init plat_irq_setup_pins(int mode)
834 switch (mode) { 884 switch (mode) {
835 case IRQ_MODE_IRQ7654: 885 case IRQ_MODE_IRQ7654:
836 /* select IRQ mode for IRL7-4 */ 886 /* select IRQ mode for IRL7-4 */
837 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 887 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
838 register_intc_controller(&intc_desc_irq4567); 888 register_intc_controller(&intc_desc_irq4567);
839 break; 889 break;
840 case IRQ_MODE_IRQ3210: 890 case IRQ_MODE_IRQ3210:
841 /* select IRQ mode for IRL3-0 */ 891 /* select IRQ mode for IRL3-0 */
842 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 892 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
843 register_intc_controller(&intc_desc_irq0123); 893 register_intc_controller(&intc_desc_irq0123);
844 break; 894 break;
845 case IRQ_MODE_IRL7654: 895 case IRQ_MODE_IRL7654:
846 /* enable IRL7-4 but don't provide any masking */ 896 /* enable IRL7-4 but don't provide any masking */
847 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 897 __raw_writel(0x40000000, INTC_INTMSKCLR1);
848 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 898 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
849 break; 899 break;
850 case IRQ_MODE_IRL3210: 900 case IRQ_MODE_IRL3210:
851 /* enable IRL0-3 but don't provide any masking */ 901 /* enable IRL0-3 but don't provide any masking */
852 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 902 __raw_writel(0x80000000, INTC_INTMSKCLR1);
853 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 903 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
854 break; 904 break;
855 case IRQ_MODE_IRL7654_MASK: 905 case IRQ_MODE_IRL7654_MASK:
856 /* enable IRL7-4 and mask using cpu intc controller */ 906 /* enable IRL7-4 and mask using cpu intc controller */
857 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 907 __raw_writel(0x40000000, INTC_INTMSKCLR1);
858 register_intc_controller(&intc_desc_irl4567); 908 register_intc_controller(&intc_desc_irl4567);
859 break; 909 break;
860 case IRQ_MODE_IRL3210_MASK: 910 case IRQ_MODE_IRL3210_MASK:
861 /* enable IRL0-3 and mask using cpu intc controller */ 911 /* enable IRL0-3 and mask using cpu intc controller */
862 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 912 __raw_writel(0x80000000, INTC_INTMSKCLR1);
863 register_intc_controller(&intc_desc_irl0123); 913 register_intc_controller(&intc_desc_irl0123);
864 break; 914 break;
865 default: 915 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index e848443deeb9..780ba17a5599 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -15,37 +15,57 @@
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <asm/mmzone.h> 16#include <asm/mmzone.h>
17 17
18static struct plat_sci_port sci_platform_data[] = { 18/*
19 { 19 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
20 .mapbase = 0xffc30000, 20 * INTEVT values overlap with the FPU EXPEVT ones, requiring special
21 .flags = UPF_BOOT_AUTOCONF, 21 * demuxing in the exception dispatch path.
22 .type = PORT_SCIF, 22 *
23 .irqs = { 40, 41, 43, 42 }, 23 * As this overlap is something that never should have made it in to
24 }, { 24 * silicon in the first place, we just refuse to deal with the port at
25 .mapbase = 0xffc40000, 25 * all rather than adding infrastructure to hack around it.
26 .flags = UPF_BOOT_AUTOCONF, 26 */
27 .type = PORT_SCIF, 27static struct plat_sci_port scif0_platform_data = {
28 .irqs = { 44, 45, 47, 46 }, 28 .mapbase = 0xffc30000,
29 }, { 29 .flags = UPF_BOOT_AUTOCONF,
30 .mapbase = 0xffc50000, 30 .type = PORT_SCIF,
31 .flags = UPF_BOOT_AUTOCONF, 31 .irqs = { 40, 41, 43, 42 },
32 .type = PORT_SCIF,
33 .irqs = { 48, 49, 51, 50 },
34 }, {
35 .mapbase = 0xffc60000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 52, 53, 55, 54 },
39 }, {
40 .flags = 0,
41 }
42}; 32};
43 33
44static struct platform_device sci_device = { 34static struct platform_device scif0_device = {
45 .name = "sh-sci", 35 .name = "sh-sci",
46 .id = -1, 36 .id = 0,
37 .dev = {
38 .platform_data = &scif0_platform_data,
39 },
40};
41
42static struct plat_sci_port scif1_platform_data = {
43 .mapbase = 0xffc40000,
44 .flags = UPF_BOOT_AUTOCONF,
45 .type = PORT_SCIF,
46 .irqs = { 44, 45, 47, 46 },
47};
48
49static struct platform_device scif1_device = {
50 .name = "sh-sci",
51 .id = 1,
47 .dev = { 52 .dev = {
48 .platform_data = sci_platform_data, 53 .platform_data = &scif1_platform_data,
54 },
55};
56
57static struct plat_sci_port scif2_platform_data = {
58 .mapbase = 0xffc60000,
59 .flags = UPF_BOOT_AUTOCONF,
60 .type = PORT_SCIF,
61 .irqs = { 52, 53, 55, 54 },
62};
63
64static struct platform_device scif2_device = {
65 .name = "sh-sci",
66 .id = 2,
67 .dev = {
68 .platform_data = &scif2_platform_data,
49 }, 69 },
50}; 70};
51 71
@@ -232,6 +252,9 @@ static struct platform_device tmu5_device = {
232}; 252};
233 253
234static struct platform_device *shx3_early_devices[] __initdata = { 254static struct platform_device *shx3_early_devices[] __initdata = {
255 &scif0_device,
256 &scif1_device,
257 &scif2_device,
235 &tmu0_device, 258 &tmu0_device,
236 &tmu1_device, 259 &tmu1_device,
237 &tmu2_device, 260 &tmu2_device,
@@ -240,21 +263,10 @@ static struct platform_device *shx3_early_devices[] __initdata = {
240 &tmu5_device, 263 &tmu5_device,
241}; 264};
242 265
243static struct platform_device *shx3_devices[] __initdata = {
244 &sci_device,
245};
246
247static int __init shx3_devices_setup(void) 266static int __init shx3_devices_setup(void)
248{ 267{
249 int ret; 268 return platform_add_devices(shx3_early_devices,
250
251 ret = platform_add_devices(shx3_early_devices,
252 ARRAY_SIZE(shx3_early_devices)); 269 ARRAY_SIZE(shx3_early_devices));
253 if (unlikely(ret != 0))
254 return ret;
255
256 return platform_add_devices(shx3_devices,
257 ARRAY_SIZE(shx3_devices));
258} 270}
259arch_initcall(shx3_devices_setup); 271arch_initcall(shx3_devices_setup);
260 272
@@ -268,7 +280,11 @@ enum {
268 UNUSED = 0, 280 UNUSED = 0,
269 281
270 /* interrupt sources */ 282 /* interrupt sources */
271 IRL, IRQ0, IRQ1, IRQ2, IRQ3, 283 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
284 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
285 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
286 IRL_HHLL, IRL_HHLH, IRL_HHHL,
287 IRQ0, IRQ1, IRQ2, IRQ3,
272 HUDII, 288 HUDII,
273 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5, 289 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
274 PCII0, PCII1, PCII2, PCII3, PCII4, 290 PCII0, PCII1, PCII2, PCII3, PCII4,
@@ -291,7 +307,7 @@ enum {
291 INTICI4, INTICI5, INTICI6, INTICI7, 307 INTICI4, INTICI5, INTICI6, INTICI7,
292 308
293 /* interrupt groups */ 309 /* interrupt groups */
294 PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, 310 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
295 DMAC0, DMAC1, 311 DMAC0, DMAC1,
296}; 312};
297 313
@@ -309,8 +325,6 @@ static struct intc_vect vectors[] __initdata = {
309 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), 325 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
310 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0), 326 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
311 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0), 327 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
312 INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
313 INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
314 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0), 328 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
315 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0), 329 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
316 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920), 330 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
@@ -344,10 +358,13 @@ static struct intc_vect vectors[] __initdata = {
344}; 358};
345 359
346static struct intc_group groups[] __initdata = { 360static struct intc_group groups[] __initdata = {
361 INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
362 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
363 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
364 IRL_HHLL, IRL_HHLH, IRL_HHHL),
347 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), 365 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
348 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 366 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
349 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 367 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
350 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
351 INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI), 368 INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
352 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, 369 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
353 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), 370 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
@@ -419,14 +436,14 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
419 436
420/* External interrupt pins in IRL mode */ 437/* External interrupt pins in IRL mode */
421static struct intc_vect vectors_irl[] __initdata = { 438static struct intc_vect vectors_irl[] __initdata = {
422 INTC_VECT(IRL, 0x200), INTC_VECT(IRL, 0x220), 439 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
423 INTC_VECT(IRL, 0x240), INTC_VECT(IRL, 0x260), 440 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
424 INTC_VECT(IRL, 0x280), INTC_VECT(IRL, 0x2a0), 441 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
425 INTC_VECT(IRL, 0x2c0), INTC_VECT(IRL, 0x2e0), 442 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
426 INTC_VECT(IRL, 0x300), INTC_VECT(IRL, 0x320), 443 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
427 INTC_VECT(IRL, 0x340), INTC_VECT(IRL, 0x360), 444 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
428 INTC_VECT(IRL, 0x380), INTC_VECT(IRL, 0x3a0), 445 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
429 INTC_VECT(IRL, 0x3c0), 446 INTC_VECT(IRL_HHHL, 0x3c0),
430}; 447};
431 448
432static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, 449static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 185ec3976a25..11bf4c1e25c0 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -14,6 +14,13 @@
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/io.h> 15#include <linux/io.h>
16 16
17#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
18#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
19
20#define STBCR_MSTP 0x00000001
21#define STBCR_RESET 0x00000002
22#define STBCR_LTSLP 0x80000000
23
17static irqreturn_t ipi_interrupt_handler(int irq, void *arg) 24static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
18{ 25{
19 unsigned int message = (unsigned int)(long)arg; 26 unsigned int message = (unsigned int)(long)arg;
@@ -21,9 +28,9 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
21 unsigned int offs = 4 * cpu; 28 unsigned int offs = 4 * cpu;
22 unsigned int x; 29 unsigned int x;
23 30
24 x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ 31 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
25 x &= (1 << (message << 2)); 32 x &= (1 << (message << 2));
26 ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ 33 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
27 34
28 smp_message_recv(message); 35 smp_message_recv(message);
29 36
@@ -37,6 +44,9 @@ void __init plat_smp_setup(void)
37 44
38 init_cpu_possible(cpumask_of(cpu)); 45 init_cpu_possible(cpumask_of(cpu));
39 46
47 /* Enable light sleep for the boot CPU */
48 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
49
40 __cpu_number_map[0] = 0; 50 __cpu_number_map[0] = 0;
41 __cpu_logical_map[0] = 0; 51 __cpu_logical_map[0] = 0;
42 52
@@ -66,32 +76,26 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
66 "IPI", (void *)(long)i); 76 "IPI", (void *)(long)i);
67} 77}
68 78
69#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
70#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
71
72#define STBCR_MSTP 0x00000001
73#define STBCR_RESET 0x00000002
74#define STBCR_LTSLP 0x80000000
75
76#define STBCR_AP_VAL (STBCR_RESET | STBCR_LTSLP)
77
78void plat_start_cpu(unsigned int cpu, unsigned long entry_point) 79void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
79{ 80{
80 ctrl_outl(entry_point, RESET_REG(cpu)); 81 if (__in_29bit_mode())
82 __raw_writel(entry_point, RESET_REG(cpu));
83 else
84 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
81 85
82 if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) 86 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
83 ctrl_outl(STBCR_MSTP, STBCR_REG(cpu)); 87 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
84 88
85 while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) 89 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
86 cpu_relax(); 90 cpu_relax();
87 91
88 /* Start up secondary processor by sending a reset */ 92 /* Start up secondary processor by sending a reset */
89 ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu)); 93 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
90} 94}
91 95
92int plat_smp_processor_id(void) 96int plat_smp_processor_id(void)
93{ 97{
94 return ctrl_inl(0xff000048); /* CPIDR */ 98 return __raw_readl(0xff000048); /* CPIDR */
95} 99}
96 100
97void plat_send_ipi(unsigned int cpu, unsigned int message) 101void plat_send_ipi(unsigned int cpu, unsigned int message)
@@ -100,5 +104,5 @@ void plat_send_ipi(unsigned int cpu, unsigned int message)
100 104
101 BUG_ON(cpu >= 4); 105 BUG_ON(cpu >= 4);
102 106
103 ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ 107 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
104} 108}
diff --git a/arch/sh/kernel/cpu/sh4a/ubc.c b/arch/sh/kernel/cpu/sh4a/ubc.c
new file mode 100644
index 000000000000..efb2745bcb36
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/ubc.c
@@ -0,0 +1,133 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/ubc.c
3 *
4 * On-chip UBC support for SH-4A CPUs.
5 *
6 * Copyright (C) 2009 - 2010 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <asm/hw_breakpoint.h>
17
18#define UBC_CBR(idx) (0xff200000 + (0x20 * idx))
19#define UBC_CRR(idx) (0xff200004 + (0x20 * idx))
20#define UBC_CAR(idx) (0xff200008 + (0x20 * idx))
21#define UBC_CAMR(idx) (0xff20000c + (0x20 * idx))
22
23#define UBC_CCMFR 0xff200600
24#define UBC_CBCR 0xff200620
25
26/* CRR */
27#define UBC_CRR_PCB (1 << 1)
28#define UBC_CRR_BIE (1 << 0)
29
30/* CBR */
31#define UBC_CBR_CE (1 << 0)
32
33static struct sh_ubc sh4a_ubc;
34
35static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx)
36{
37 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
38 __raw_writel(info->address, UBC_CAR(idx));
39}
40
41static void sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx)
42{
43 __raw_writel(0, UBC_CBR(idx));
44 __raw_writel(0, UBC_CAR(idx));
45}
46
47static void sh4a_ubc_enable_all(unsigned long mask)
48{
49 int i;
50
51 for (i = 0; i < sh4a_ubc.num_events; i++)
52 if (mask & (1 << i))
53 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
54 UBC_CBR(i));
55}
56
57static void sh4a_ubc_disable_all(void)
58{
59 int i;
60
61 for (i = 0; i < sh4a_ubc.num_events; i++)
62 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
63 UBC_CBR(i));
64}
65
66static unsigned long sh4a_ubc_active_mask(void)
67{
68 unsigned long active = 0;
69 int i;
70
71 for (i = 0; i < sh4a_ubc.num_events; i++)
72 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE)
73 active |= (1 << i);
74
75 return active;
76}
77
78static unsigned long sh4a_ubc_triggered_mask(void)
79{
80 return __raw_readl(UBC_CCMFR);
81}
82
83static void sh4a_ubc_clear_triggered_mask(unsigned long mask)
84{
85 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
86}
87
88static struct sh_ubc sh4a_ubc = {
89 .name = "SH-4A",
90 .num_events = 2,
91 .trap_nr = 0x1e0,
92 .enable = sh4a_ubc_enable,
93 .disable = sh4a_ubc_disable,
94 .enable_all = sh4a_ubc_enable_all,
95 .disable_all = sh4a_ubc_disable_all,
96 .active_mask = sh4a_ubc_active_mask,
97 .triggered_mask = sh4a_ubc_triggered_mask,
98 .clear_triggered_mask = sh4a_ubc_clear_triggered_mask,
99};
100
101static int __init sh4a_ubc_init(void)
102{
103 struct clk *ubc_iclk = clk_get(NULL, "ubc0");
104 int i;
105
106 /*
107 * The UBC MSTP bit is optional, as not all platforms will have
108 * it. Just ignore it if we can't find it.
109 */
110 if (IS_ERR(ubc_iclk))
111 ubc_iclk = NULL;
112
113 clk_enable(ubc_iclk);
114
115 __raw_writel(0, UBC_CBCR);
116
117 for (i = 0; i < sh4a_ubc.num_events; i++) {
118 __raw_writel(0, UBC_CAMR(i));
119 __raw_writel(0, UBC_CBR(i));
120
121 __raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i));
122
123 /* dummy read for write posting */
124 (void)__raw_readl(UBC_CRR(i));
125 }
126
127 clk_disable(ubc_iclk);
128
129 sh4a_ubc.clk = ubc_iclk;
130
131 return register_sh_ubc(&sh4a_ubc);
132}
133arch_initcall(sh4a_ubc_init);
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 7f864ebc51d3..9cfc19b8dbe4 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -24,7 +24,7 @@ static unsigned long cprc_base;
24 24
25static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
26{ 26{
27 int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007; 27 int idx = (__raw_readl(cprc_base + 0x00) >> 6) & 0x0007;
28 clk->rate *= ifc_table[idx]; 28 clk->rate *= ifc_table[idx];
29} 29}
30 30
@@ -34,7 +34,7 @@ static struct clk_ops sh5_master_clk_ops = {
34 34
35static unsigned long module_clk_recalc(struct clk *clk) 35static unsigned long module_clk_recalc(struct clk *clk)
36{ 36{
37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007; 37 int idx = (__raw_readw(cprc_base) >> 12) & 0x0007;
38 return clk->parent->rate / ifc_table[idx]; 38 return clk->parent->rate / ifc_table[idx];
39} 39}
40 40
@@ -44,7 +44,7 @@ static struct clk_ops sh5_module_clk_ops = {
44 44
45static unsigned long bus_clk_recalc(struct clk *clk) 45static unsigned long bus_clk_recalc(struct clk *clk)
46{ 46{
47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007; 47 int idx = (__raw_readw(cprc_base) >> 3) & 0x0007;
48 return clk->parent->rate / ifc_table[idx]; 48 return clk->parent->rate / ifc_table[idx];
49} 49}
50 50
@@ -54,7 +54,7 @@ static struct clk_ops sh5_bus_clk_ops = {
54 54
55static unsigned long cpu_clk_recalc(struct clk *clk) 55static unsigned long cpu_clk_recalc(struct clk *clk)
56{ 56{
57 int idx = (ctrl_inw(cprc_base) & 0x0007); 57 int idx = (__raw_readw(cprc_base) & 0x0007);
58 return clk->parent->rate / ifc_table[idx]; 58 return clk->parent->rate / ifc_table[idx];
59} 59}
60 60
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index b0aacf675258..6b80295dd7a4 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -187,7 +187,7 @@ trap_jtable:
187 .rept 6 187 .rept 6
188 .long do_exception_error /* 0x880 - 0x920 */ 188 .long do_exception_error /* 0x880 - 0x920 */
189 .endr 189 .endr
190 .long do_software_break_point /* 0x940 */ 190 .long breakpoint_trap_handler /* 0x940 */
191 .long do_exception_error /* 0x960 */ 191 .long do_exception_error /* 0x960 */
192 .long do_single_step /* 0x980 */ 192 .long do_single_step /* 0x980 */
193 193
@@ -933,7 +933,7 @@ ret_with_reschedule:
933 933
934 pta restore_all, tr1 934 pta restore_all, tr1
935 935
936 movi (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), r8 936 movi _TIF_SIGPENDING, r8
937 and r8, r7, r8 937 and r8, r7, r8
938 pta work_notifysig, tr0 938 pta work_notifysig, tr0
939 bne r8, ZERO, tr0 939 bne r8, ZERO, tr0
@@ -1124,7 +1124,7 @@ fpu_error_or_IRQA:
1124 pta its_IRQ, tr0 1124 pta its_IRQ, tr0
1125 beqi/l r4, EVENT_INTERRUPT, tr0 1125 beqi/l r4, EVENT_INTERRUPT, tr0
1126#ifdef CONFIG_SH_FPU 1126#ifdef CONFIG_SH_FPU
1127 movi do_fpu_state_restore, r6 1127 movi fpu_state_restore_trap_handler, r6
1128#else 1128#else
1129 movi do_exception_error, r6 1129 movi do_exception_error, r6
1130#endif 1130#endif
@@ -1135,7 +1135,7 @@ fpu_error_or_IRQB:
1135 pta its_IRQ, tr0 1135 pta its_IRQ, tr0
1136 beqi/l r4, EVENT_INTERRUPT, tr0 1136 beqi/l r4, EVENT_INTERRUPT, tr0
1137#ifdef CONFIG_SH_FPU 1137#ifdef CONFIG_SH_FPU
1138 movi do_fpu_state_restore, r6 1138 movi fpu_state_restore_trap_handler, r6
1139#else 1139#else
1140 movi do_exception_error, r6 1140 movi do_exception_error, r6
1141#endif 1141#endif
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index dd4f51ffb50e..4b3bb35e99f3 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -15,26 +15,8 @@
15#include <linux/sched.h> 15#include <linux/sched.h>
16#include <linux/signal.h> 16#include <linux/signal.h>
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/user.h>
19#include <asm/io.h>
20#include <asm/fpu.h>
21 18
22/* 19void save_fpu(struct task_struct *tsk)
23 * Initially load the FPU with signalling NANS. This bit pattern
24 * has the property that no matter whether considered as single or as
25 * double precision, it still represents a signalling NAN.
26 */
27#define sNAN64 0xFFFFFFFFFFFFFFFFULL
28#define sNAN32 0xFFFFFFFFUL
29
30static union sh_fpu_union init_fpuregs = {
31 .hard = {
32 .fp_regs = { [0 ... 63] = sNAN32 },
33 .fpscr = FPSCR_INIT
34 }
35};
36
37void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
38{ 20{
39 asm volatile("fst.p %0, (0*8), fp0\n\t" 21 asm volatile("fst.p %0, (0*8), fp0\n\t"
40 "fst.p %0, (1*8), fp2\n\t" 22 "fst.p %0, (1*8), fp2\n\t"
@@ -72,12 +54,11 @@ void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
72 "fgetscr fr63\n\t" 54 "fgetscr fr63\n\t"
73 "fst.s %0, (32*8), fr63\n\t" 55 "fst.s %0, (32*8), fr63\n\t"
74 : /* no output */ 56 : /* no output */
75 : "r" (&tsk->thread.fpu.hard) 57 : "r" (&tsk->thread.xstate->hardfpu)
76 : "memory"); 58 : "memory");
77} 59}
78 60
79static inline void 61void restore_fpu(struct task_struct *tsk)
80fpload(struct sh_fpu_hard_struct *fpregs)
81{ 62{
82 asm volatile("fld.p %0, (0*8), fp0\n\t" 63 asm volatile("fld.p %0, (0*8), fp0\n\t"
83 "fld.p %0, (1*8), fp2\n\t" 64 "fld.p %0, (1*8), fp2\n\t"
@@ -116,16 +97,11 @@ fpload(struct sh_fpu_hard_struct *fpregs)
116 97
117 "fld.p %0, (31*8), fp62\n\t" 98 "fld.p %0, (31*8), fp62\n\t"
118 : /* no output */ 99 : /* no output */
119 : "r" (fpregs) ); 100 : "r" (&tsk->thread.xstate->hardfpu)
120} 101 : "memory");
121
122void fpinit(struct sh_fpu_hard_struct *fpregs)
123{
124 *fpregs = init_fpuregs.hard;
125} 102}
126 103
127asmlinkage void 104asmlinkage void do_fpu_error(unsigned long ex, struct pt_regs *regs)
128do_fpu_error(unsigned long ex, struct pt_regs *regs)
129{ 105{
130 struct task_struct *tsk = current; 106 struct task_struct *tsk = current;
131 107
@@ -133,35 +109,6 @@ do_fpu_error(unsigned long ex, struct pt_regs *regs)
133 109
134 tsk->thread.trap_no = 11; 110 tsk->thread.trap_no = 11;
135 tsk->thread.error_code = 0; 111 tsk->thread.error_code = 0;
136 force_sig(SIGFPE, tsk);
137}
138
139
140asmlinkage void
141do_fpu_state_restore(unsigned long ex, struct pt_regs *regs)
142{
143 void die(const char *str, struct pt_regs *regs, long err);
144
145 if (! user_mode(regs))
146 die("FPU used in kernel", regs, ex);
147 112
148 regs->sr &= ~SR_FD; 113 force_sig(SIGFPE, tsk);
149
150 if (last_task_used_math == current)
151 return;
152
153 enable_fpu();
154 if (last_task_used_math != NULL)
155 /* Other processes fpu state, save away */
156 save_fpu(last_task_used_math, regs);
157
158 last_task_used_math = current;
159 if (used_math()) {
160 fpload(&current->thread.fpu.hard);
161 } else {
162 /* First time FPU user. */
163 fpload(&init_fpuregs.hard);
164 set_used_math();
165 }
166 disable_fpu();
167} 114}
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 6a0f82f70032..e7a3c1e4b604 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -16,22 +16,18 @@
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <asm/addrspace.h> 17#include <asm/addrspace.h>
18 18
19static struct plat_sci_port sci_platform_data[] = { 19static struct plat_sci_port scif0_platform_data = {
20 { 20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
21 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, 21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
22 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 22 .type = PORT_SCIF,
23 .type = PORT_SCIF, 23 .irqs = { 39, 40, 42, 0 },
24 .irqs = { 39, 40, 42, 0 },
25 }, {
26 .flags = 0,
27 }
28}; 24};
29 25
30static struct platform_device sci_device = { 26static struct platform_device scif0_device = {
31 .name = "sh-sci", 27 .name = "sh-sci",
32 .id = -1, 28 .id = 0,
33 .dev = { 29 .dev = {
34 .platform_data = sci_platform_data, 30 .platform_data = &scif0_platform_data,
35 }, 31 },
36}; 32};
37 33
@@ -164,13 +160,13 @@ static struct platform_device tmu2_device = {
164}; 160};
165 161
166static struct platform_device *sh5_early_devices[] __initdata = { 162static struct platform_device *sh5_early_devices[] __initdata = {
163 &scif0_device,
167 &tmu0_device, 164 &tmu0_device,
168 &tmu1_device, 165 &tmu1_device,
169 &tmu2_device, 166 &tmu2_device,
170}; 167};
171 168
172static struct platform_device *sh5_devices[] __initdata = { 169static struct platform_device *sh5_devices[] __initdata = {
173 &sci_device,
174 &rtc_device, 170 &rtc_device,
175}; 171};
176 172
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 1c504bd972c3..83972aa319c2 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -87,25 +87,31 @@ void sh_mobile_setup_cpuidle(void)
87 87
88 dev->safe_state = state; 88 dev->safe_state = state;
89 89
90 state = &dev->states[i++]; 90 if (sh_mobile_sleep_supported & SUSP_SH_SF) {
91 snprintf(state->name, CPUIDLE_NAME_LEN, "C1"); 91 state = &dev->states[i++];
92 strncpy(state->desc, "SuperH Sleep Mode [SF]", CPUIDLE_DESC_LEN); 92 snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
93 state->exit_latency = 100; 93 strncpy(state->desc, "SuperH Sleep Mode [SF]",
94 state->target_residency = 1 * 2; 94 CPUIDLE_DESC_LEN);
95 state->power_usage = 1; 95 state->exit_latency = 100;
96 state->flags = 0; 96 state->target_residency = 1 * 2;
97 state->flags |= CPUIDLE_FLAG_TIME_VALID; 97 state->power_usage = 1;
98 state->enter = cpuidle_sleep_enter; 98 state->flags = 0;
99 state->flags |= CPUIDLE_FLAG_TIME_VALID;
100 state->enter = cpuidle_sleep_enter;
101 }
99 102
100 state = &dev->states[i++]; 103 if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) {
101 snprintf(state->name, CPUIDLE_NAME_LEN, "C2"); 104 state = &dev->states[i++];
102 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]", CPUIDLE_DESC_LEN); 105 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
103 state->exit_latency = 2300; 106 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]",
104 state->target_residency = 1 * 2; 107 CPUIDLE_DESC_LEN);
105 state->power_usage = 1; 108 state->exit_latency = 2300;
106 state->flags = 0; 109 state->target_residency = 1 * 2;
107 state->flags |= CPUIDLE_FLAG_TIME_VALID; 110 state->power_usage = 1;
108 state->enter = cpuidle_sleep_enter; 111 state->flags = 0;
112 state->flags |= CPUIDLE_FLAG_TIME_VALID;
113 state->enter = cpuidle_sleep_enter;
114 }
109 115
110 dev->state_count = i; 116 dev->state_count = i;
111 117
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
index ee3c2aaf66fb..e55968712706 100644
--- a/arch/sh/kernel/cpu/shmobile/pm.c
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -15,6 +15,13 @@
15#include <linux/suspend.h> 15#include <linux/suspend.h>
16#include <asm/suspend.h> 16#include <asm/suspend.h>
17#include <asm/uaccess.h> 17#include <asm/uaccess.h>
18#include <asm/cacheflush.h>
19
20/*
21 * Notifier lists for pre/post sleep notification
22 */
23ATOMIC_NOTIFIER_HEAD(sh_mobile_pre_sleep_notifier_list);
24ATOMIC_NOTIFIER_HEAD(sh_mobile_post_sleep_notifier_list);
18 25
19/* 26/*
20 * Sleep modes available on SuperH Mobile: 27 * Sleep modes available on SuperH Mobile:
@@ -26,30 +33,106 @@
26#define SUSP_MODE_SLEEP (SUSP_SH_SLEEP) 33#define SUSP_MODE_SLEEP (SUSP_SH_SLEEP)
27#define SUSP_MODE_SLEEP_SF (SUSP_SH_SLEEP | SUSP_SH_SF) 34#define SUSP_MODE_SLEEP_SF (SUSP_SH_SLEEP | SUSP_SH_SF)
28#define SUSP_MODE_STANDBY_SF (SUSP_SH_STANDBY | SUSP_SH_SF) 35#define SUSP_MODE_STANDBY_SF (SUSP_SH_STANDBY | SUSP_SH_SF)
36#define SUSP_MODE_RSTANDBY_SF \
37 (SUSP_SH_RSTANDBY | SUSP_SH_MMU | SUSP_SH_REGS | SUSP_SH_SF)
38 /*
39 * U-standby mode is unsupported since it needs bootloader hacks
40 */
29 41
30/* 42#ifdef CONFIG_CPU_SUBTYPE_SH7724
31 * The following modes are not there yet: 43#define RAM_BASE 0xfd800000 /* RSMEM */
32 * 44#else
33 * R-standby mode is unsupported, but will be added in the future 45#define RAM_BASE 0xe5200000 /* ILRAM */
34 * U-standby mode is low priority since it needs bootloader hacks 46#endif
35 */
36
37#define ILRAM_BASE 0xe5200000
38
39extern const unsigned char sh_mobile_standby[];
40extern const unsigned int sh_mobile_standby_size;
41 47
42void sh_mobile_call_standby(unsigned long mode) 48void sh_mobile_call_standby(unsigned long mode)
43{ 49{
44 void *onchip_mem = (void *)ILRAM_BASE; 50 void *onchip_mem = (void *)RAM_BASE;
45 void (*standby_onchip_mem)(unsigned long, unsigned long) = onchip_mem; 51 struct sh_sleep_data *sdp = onchip_mem;
52 void (*standby_onchip_mem)(unsigned long, unsigned long);
53
54 /* code located directly after data structure */
55 standby_onchip_mem = (void *)(sdp + 1);
56
57 atomic_notifier_call_chain(&sh_mobile_pre_sleep_notifier_list,
58 mode, NULL);
59
60 /* flush the caches if MMU flag is set */
61 if (mode & SUSP_SH_MMU)
62 flush_cache_all();
46 63
47 /* Let assembly snippet in on-chip memory handle the rest */ 64 /* Let assembly snippet in on-chip memory handle the rest */
48 standby_onchip_mem(mode, ILRAM_BASE); 65 standby_onchip_mem(mode, RAM_BASE);
66
67 atomic_notifier_call_chain(&sh_mobile_post_sleep_notifier_list,
68 mode, NULL);
69}
70
71extern char sh_mobile_sleep_enter_start;
72extern char sh_mobile_sleep_enter_end;
73
74extern char sh_mobile_sleep_resume_start;
75extern char sh_mobile_sleep_resume_end;
76
77unsigned long sh_mobile_sleep_supported = SUSP_SH_SLEEP;
78
79void sh_mobile_register_self_refresh(unsigned long flags,
80 void *pre_start, void *pre_end,
81 void *post_start, void *post_end)
82{
83 void *onchip_mem = (void *)RAM_BASE;
84 void *vp;
85 struct sh_sleep_data *sdp;
86 int n;
87
88 /* part 0: data area */
89 sdp = onchip_mem;
90 sdp->addr.stbcr = 0xa4150020; /* STBCR */
91 sdp->addr.bar = 0xa4150040; /* BAR */
92 sdp->addr.pteh = 0xff000000; /* PTEH */
93 sdp->addr.ptel = 0xff000004; /* PTEL */
94 sdp->addr.ttb = 0xff000008; /* TTB */
95 sdp->addr.tea = 0xff00000c; /* TEA */
96 sdp->addr.mmucr = 0xff000010; /* MMUCR */
97 sdp->addr.ptea = 0xff000034; /* PTEA */
98 sdp->addr.pascr = 0xff000070; /* PASCR */
99 sdp->addr.irmcr = 0xff000078; /* IRMCR */
100 sdp->addr.ccr = 0xff00001c; /* CCR */
101 sdp->addr.ramcr = 0xff000074; /* RAMCR */
102 vp = sdp + 1;
103
104 /* part 1: common code to enter sleep mode */
105 n = &sh_mobile_sleep_enter_end - &sh_mobile_sleep_enter_start;
106 memcpy(vp, &sh_mobile_sleep_enter_start, n);
107 vp += roundup(n, 4);
108
109 /* part 2: board specific code to enter self-refresh mode */
110 n = pre_end - pre_start;
111 memcpy(vp, pre_start, n);
112 sdp->sf_pre = (unsigned long)vp;
113 vp += roundup(n, 4);
114
115 /* part 3: board specific code to resume from self-refresh mode */
116 n = post_end - post_start;
117 memcpy(vp, post_start, n);
118 sdp->sf_post = (unsigned long)vp;
119 vp += roundup(n, 4);
120
121 /* part 4: common code to resume from sleep mode */
122 WARN_ON(vp > (onchip_mem + 0x600));
123 vp = onchip_mem + 0x600; /* located at interrupt vector */
124 n = &sh_mobile_sleep_resume_end - &sh_mobile_sleep_resume_start;
125 memcpy(vp, &sh_mobile_sleep_resume_start, n);
126 sdp->resume = (unsigned long)vp;
127
128 sh_mobile_sleep_supported |= flags;
49} 129}
50 130
51static int sh_pm_enter(suspend_state_t state) 131static int sh_pm_enter(suspend_state_t state)
52{ 132{
133 if (!(sh_mobile_sleep_supported & SUSP_MODE_STANDBY_SF))
134 return -ENXIO;
135
53 local_irq_disable(); 136 local_irq_disable();
54 set_bl_bit(); 137 set_bl_bit();
55 sh_mobile_call_standby(SUSP_MODE_STANDBY_SF); 138 sh_mobile_call_standby(SUSP_MODE_STANDBY_SF);
@@ -65,13 +148,6 @@ static struct platform_suspend_ops sh_pm_ops = {
65 148
66static int __init sh_pm_init(void) 149static int __init sh_pm_init(void)
67{ 150{
68 void *onchip_mem = (void *)ILRAM_BASE;
69
70 /* Copy the assembly snippet to the otherwise ununsed ILRAM */
71 memcpy(onchip_mem, sh_mobile_standby, sh_mobile_standby_size);
72 wmb();
73 ctrl_barrier();
74
75 suspend_set_ops(&sh_pm_ops); 151 suspend_set_ops(&sh_pm_ops);
76 sh_mobile_setup_cpuidle(); 152 sh_mobile_setup_cpuidle();
77 return 0; 153 return 0;
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
index 7c615b17e209..6dcb8166a64d 100644
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -45,12 +45,14 @@ static int __platform_pm_runtime_resume(struct platform_device *pdev)
45 45
46 dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk); 46 dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
47 47
48 if (d->driver && d->driver->pm && d->driver->pm->runtime_resume) { 48 if (d->driver) {
49 hwblk_enable(hwblk_info, hwblk); 49 hwblk_enable(hwblk_info, hwblk);
50 ret = 0; 50 ret = 0;
51 51
52 if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) { 52 if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
53 ret = d->driver->pm->runtime_resume(d); 53 if (d->driver->pm && d->driver->pm->runtime_resume)
54 ret = d->driver->pm->runtime_resume(d);
55
54 if (!ret) 56 if (!ret)
55 clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags); 57 clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
56 else 58 else
@@ -73,12 +75,15 @@ static int __platform_pm_runtime_suspend(struct platform_device *pdev)
73 75
74 dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk); 76 dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
75 77
76 if (d->driver && d->driver->pm && d->driver->pm->runtime_suspend) { 78 if (d->driver) {
77 BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags)); 79 BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
80 ret = 0;
78 81
79 hwblk_enable(hwblk_info, hwblk); 82 if (d->driver->pm && d->driver->pm->runtime_suspend) {
80 ret = d->driver->pm->runtime_suspend(d); 83 hwblk_enable(hwblk_info, hwblk);
81 hwblk_disable(hwblk_info, hwblk); 84 ret = d->driver->pm->runtime_suspend(d);
85 hwblk_disable(hwblk_info, hwblk);
86 }
82 87
83 if (!ret) { 88 if (!ret) {
84 set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags); 89 set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S
index a439e6c7824f..e6aac65f5750 100644
--- a/arch/sh/kernel/cpu/shmobile/sleep.S
+++ b/arch/sh/kernel/cpu/shmobile/sleep.S
@@ -20,79 +20,143 @@
20 * Kernel mode register usage, see entry.S: 20 * Kernel mode register usage, see entry.S:
21 * k0 scratch 21 * k0 scratch
22 * k1 scratch 22 * k1 scratch
23 * k4 scratch
24 */ 23 */
25#define k0 r0 24#define k0 r0
26#define k1 r1 25#define k1 r1
27#define k4 r4
28 26
29/* manage self-refresh and enter standby mode. 27/* manage self-refresh and enter standby mode. must be self-contained.
30 * this code will be copied to on-chip memory and executed from there. 28 * this code will be copied to on-chip memory and executed from there.
31 */ 29 */
30 .balign 4
31ENTRY(sh_mobile_sleep_enter_start)
32 32
33 .balign 4096,0,4096 33 /* save mode flags */
34ENTRY(sh_mobile_standby) 34 mov.l r4, @(SH_SLEEP_MODE, r5)
35 35
36 /* save original vbr */ 36 /* save original vbr */
37 stc vbr, r1 37 stc vbr, r0
38 mova saved_vbr, r0 38 mov.l r0, @(SH_SLEEP_VBR, r5)
39 mov.l r1, @r0
40 39
41 /* point vbr to our on-chip memory page */ 40 /* point vbr to our on-chip memory page */
42 ldc r5, vbr 41 ldc r5, vbr
43 42
44 /* save return address */ 43 /* save return address */
45 mova saved_spc, r0 44 sts pr, r0
46 sts pr, r5 45 mov.l r0, @(SH_SLEEP_SPC, r5)
47 mov.l r5, @r0
48 46
49 /* save sr */ 47 /* save sr */
50 mova saved_sr, r0 48 stc sr, r0
51 stc sr, r5 49 mov.l r0, @(SH_SLEEP_SR, r5)
52 mov.l r5, @r0 50
51 /* save general purpose registers to stack if needed */
52 mov.l @(SH_SLEEP_MODE, r5), r0
53 tst #SUSP_SH_REGS, r0
54 bt skip_regs_save
55
56 sts.l pr, @-r15
57 mov.l r14, @-r15
58 mov.l r13, @-r15
59 mov.l r12, @-r15
60 mov.l r11, @-r15
61 mov.l r10, @-r15
62 mov.l r9, @-r15
63 mov.l r8, @-r15
64
65 /* make sure bank0 is selected, save low registers */
66 mov.l rb_bit, r9
67 not r9, r9
68 bsr set_sr
69 mov #0, r10
70
71 bsr save_low_regs
72 nop
53 73
54 /* save mode flags */ 74 /* switch to bank 1, save low registers */
55 mova saved_mode, r0 75 mov.l rb_bit, r10
56 mov.l r4, @r0 76 bsr set_sr
77 mov #-1, r9
78
79 bsr save_low_regs
80 nop
81
82 /* switch back to bank 0 */
83 mov.l rb_bit, r9
84 not r9, r9
85 bsr set_sr
86 mov #0, r10
87
88skip_regs_save:
89
90 /* save sp, also set to internal ram */
91 mov.l r15, @(SH_SLEEP_SP, r5)
92 mov r5, r15
93
94 /* save stbcr */
95 bsr save_register
96 mov #SH_SLEEP_REG_STBCR, r0
97
98 /* save mmu and cache context if needed */
99 mov.l @(SH_SLEEP_MODE, r5), r0
100 tst #SUSP_SH_MMU, r0
101 bt skip_mmu_save_disable
102
103 /* save mmu state */
104 bsr save_register
105 mov #SH_SLEEP_REG_PTEH, r0
106
107 bsr save_register
108 mov #SH_SLEEP_REG_PTEL, r0
109
110 bsr save_register
111 mov #SH_SLEEP_REG_TTB, r0
112
113 bsr save_register
114 mov #SH_SLEEP_REG_TEA, r0
115
116 bsr save_register
117 mov #SH_SLEEP_REG_MMUCR, r0
118
119 bsr save_register
120 mov #SH_SLEEP_REG_PTEA, r0
121
122 bsr save_register
123 mov #SH_SLEEP_REG_PASCR, r0
57 124
58 /* put mode flags in r0 */ 125 bsr save_register
59 mov r4, r0 126 mov #SH_SLEEP_REG_IRMCR, r0
60 127
128 /* invalidate TLBs and disable the MMU */
129 bsr get_register
130 mov #SH_SLEEP_REG_MMUCR, r0
131 mov #4, r1
132 mov.l r1, @r0
133 icbi @r0
134
135 /* save cache registers and disable caches */
136 bsr save_register
137 mov #SH_SLEEP_REG_CCR, r0
138
139 bsr save_register
140 mov #SH_SLEEP_REG_RAMCR, r0
141
142 bsr get_register
143 mov #SH_SLEEP_REG_CCR, r0
144 mov #0, r1
145 mov.l r1, @r0
146 icbi @r0
147
148skip_mmu_save_disable:
149 /* call self-refresh entering code if needed */
150 mov.l @(SH_SLEEP_MODE, r5), r0
61 tst #SUSP_SH_SF, r0 151 tst #SUSP_SH_SF, r0
62 bt skip_set_sf 152 bt skip_set_sf
63#ifdef CONFIG_CPU_SUBTYPE_SH7724 153
64 /* DBSC: put memory in self-refresh mode */ 154 mov.l @(SH_SLEEP_SF_PRE, r5), r0
65 mov.l dben_reg, r4 155 jsr @r0
66 mov.l dben_data0, r1 156 nop
67 mov.l r1, @r4
68
69 mov.l dbrfpdn0_reg, r4
70 mov.l dbrfpdn0_data0, r1
71 mov.l r1, @r4
72
73 mov.l dbcmdcnt_reg, r4
74 mov.l dbcmdcnt_data0, r1
75 mov.l r1, @r4
76
77 mov.l dbcmdcnt_reg, r4
78 mov.l dbcmdcnt_data1, r1
79 mov.l r1, @r4
80
81 mov.l dbrfpdn0_reg, r4
82 mov.l dbrfpdn0_data1, r1
83 mov.l r1, @r4
84#else
85 /* SBSC: disable power down and put in self-refresh mode */
86 mov.l 1f, r4
87 mov.l 2f, r1
88 mov.l @r4, r2
89 or r1, r2
90 mov.l 3f, r3
91 and r3, r2
92 mov.l r2, @r4
93#endif
94 157
95skip_set_sf: 158skip_set_sf:
159 mov.l @(SH_SLEEP_MODE, r5), r0
96 tst #SUSP_SH_STANDBY, r0 160 tst #SUSP_SH_STANDBY, r0
97 bt test_rstandby 161 bt test_rstandby
98 162
@@ -104,6 +168,12 @@ test_rstandby:
104 tst #SUSP_SH_RSTANDBY, r0 168 tst #SUSP_SH_RSTANDBY, r0
105 bt test_ustandby 169 bt test_ustandby
106 170
171 /* setup BAR register */
172 bsr get_register
173 mov #SH_SLEEP_REG_BAR, r0
174 mov.l @(SH_SLEEP_RESUME, r5), r1
175 mov.l r1, @r0
176
107 /* set mode to "r-standby mode" */ 177 /* set mode to "r-standby mode" */
108 bra do_sleep 178 bra do_sleep
109 mov #0x20, r1 179 mov #0x20, r1
@@ -123,124 +193,213 @@ force_sleep:
123 193
124do_sleep: 194do_sleep:
125 /* setup and enter selected standby mode */ 195 /* setup and enter selected standby mode */
126 mov.l 5f, r4 196 bsr get_register
127 mov.l r1, @r4 197 mov #SH_SLEEP_REG_STBCR, r0
198 mov.l r1, @r0
128again: 199again:
129 sleep 200 sleep
130 bra again 201 bra again
131 nop 202 nop
132 203
133restore_jump_vbr: 204save_register:
205 add #SH_SLEEP_BASE_ADDR, r0
206 mov.l @(r0, r5), r1
207 add #-SH_SLEEP_BASE_ADDR, r0
208 mov.l @r1, r1
209 add #SH_SLEEP_BASE_DATA, r0
210 mov.l r1, @(r0, r5)
211 add #-SH_SLEEP_BASE_DATA, r0
212 rts
213 nop
214
215get_register:
216 add #SH_SLEEP_BASE_ADDR, r0
217 mov.l @(r0, r5), r0
218 rts
219 nop
220
221set_sr:
222 stc sr, r8
223 and r9, r8
224 or r10, r8
225 ldc r8, sr
226 rts
227 nop
228
229save_low_regs:
230 mov.l r7, @-r15
231 mov.l r6, @-r15
232 mov.l r5, @-r15
233 mov.l r4, @-r15
234 mov.l r3, @-r15
235 mov.l r2, @-r15
236 mov.l r1, @-r15
237 rts
238 mov.l r0, @-r15
239
240 .balign 4
241rb_bit: .long 0x20000000 ! RB=1
242
243ENTRY(sh_mobile_sleep_enter_end)
244
245 .balign 4
246ENTRY(sh_mobile_sleep_resume_start)
247
248 /* figure out start address */
249 bsr 0f
250 nop
2510:
252 sts pr, k1
253 mov.l 1f, k0
254 and k0, k1
255
256 /* store pointer to data area in VBR */
257 ldc k1, vbr
258
259 /* setup sr with saved sr */
260 mov.l @(SH_SLEEP_SR, k1), k0
261 ldc k0, sr
262
263 /* now: user register set! */
264 stc vbr, r5
265
134 /* setup spc with return address to c code */ 266 /* setup spc with return address to c code */
135 mov.l saved_spc, k0 267 mov.l @(SH_SLEEP_SPC, r5), r0
136 ldc k0, spc 268 ldc r0, spc
137 269
138 /* restore vbr */ 270 /* restore vbr */
139 mov.l saved_vbr, k0 271 mov.l @(SH_SLEEP_VBR, r5), r0
140 ldc k0, vbr 272 ldc r0, vbr
141 273
142 /* setup ssr with saved sr */ 274 /* setup ssr with saved sr */
143 mov.l saved_sr, k0 275 mov.l @(SH_SLEEP_SR, r5), r0
144 ldc k0, ssr 276 ldc r0, ssr
145 277
146 /* get mode flags */ 278 /* restore sp */
147 mov.l saved_mode, k0 279 mov.l @(SH_SLEEP_SP, r5), r15
148 280
149done_sleep: 281 /* restore sleep mode register */
150 /* reset standby mode to sleep mode */ 282 bsr restore_register
151 mov.l 5f, k4 283 mov #SH_SLEEP_REG_STBCR, r0
152 mov #0x00, k1
153 mov.l k1, @k4
154 284
155 tst #SUSP_SH_SF, k0 285 /* call self-refresh resume code if needed */
286 mov.l @(SH_SLEEP_MODE, r5), r0
287 tst #SUSP_SH_SF, r0
156 bt skip_restore_sf 288 bt skip_restore_sf
157 289
158#ifdef CONFIG_CPU_SUBTYPE_SH7724 290 mov.l @(SH_SLEEP_SF_POST, r5), r0
159 /* DBSC: put memory in auto-refresh mode */ 291 jsr @r0
160 mov.l dbrfpdn0_reg, k4 292 nop
161 mov.l dbrfpdn0_data0, k1 293
162 mov.l k1, @k4
163
164 nop /* sleep 140 ns */
165 nop
166 nop
167 nop
168
169 mov.l dbcmdcnt_reg, k4
170 mov.l dbcmdcnt_data0, k1
171 mov.l k1, @k4
172
173 mov.l dbcmdcnt_reg, k4
174 mov.l dbcmdcnt_data1, k1
175 mov.l k1, @k4
176
177 mov.l dben_reg, k4
178 mov.l dben_data1, k1
179 mov.l k1, @k4
180
181 mov.l dbrfpdn0_reg, k4
182 mov.l dbrfpdn0_data2, k1
183 mov.l k1, @k4
184#else
185 /* SBSC: set auto-refresh mode */
186 mov.l 1f, k4
187 mov.l @k4, k0
188 mov.l 4f, k1
189 and k1, k0
190 mov.l k0, @k4
191 mov.l 6f, k4
192 mov.l 8f, k0
193 mov.l @k4, k1
194 mov #-1, k4
195 add k4, k1
196 or k1, k0
197 mov.l 7f, k1
198 mov.l k0, @k1
199#endif
200skip_restore_sf: 294skip_restore_sf:
201 /* jump to vbr vector */ 295 /* restore mmu and cache state if needed */
202 mov.l saved_vbr, k0 296 mov.l @(SH_SLEEP_MODE, r5), r0
203 mov.l offset_vbr, k4 297 tst #SUSP_SH_MMU, r0
204 add k4, k0 298 bt skip_restore_mmu
205 jmp @k0 299
300 /* restore mmu state */
301 bsr restore_register
302 mov #SH_SLEEP_REG_PTEH, r0
303
304 bsr restore_register
305 mov #SH_SLEEP_REG_PTEL, r0
306
307 bsr restore_register
308 mov #SH_SLEEP_REG_TTB, r0
309
310 bsr restore_register
311 mov #SH_SLEEP_REG_TEA, r0
312
313 bsr restore_register
314 mov #SH_SLEEP_REG_PTEA, r0
315
316 bsr restore_register
317 mov #SH_SLEEP_REG_PASCR, r0
318
319 bsr restore_register
320 mov #SH_SLEEP_REG_IRMCR, r0
321
322 bsr restore_register
323 mov #SH_SLEEP_REG_MMUCR, r0
324 icbi @r0
325
326 /* restore cache settings */
327 bsr restore_register
328 mov #SH_SLEEP_REG_RAMCR, r0
329 icbi @r0
330
331 bsr restore_register
332 mov #SH_SLEEP_REG_CCR, r0
333 icbi @r0
334
335skip_restore_mmu:
336
337 /* restore general purpose registers if needed */
338 mov.l @(SH_SLEEP_MODE, r5), r0
339 tst #SUSP_SH_REGS, r0
340 bt skip_restore_regs
341
342 /* switch to bank 1, restore low registers */
343 mov.l _rb_bit, r10
344 bsr _set_sr
345 mov #-1, r9
346
347 bsr restore_low_regs
206 nop 348 nop
207 349
208 .balign 4 350 /* switch to bank0, restore low registers */
209saved_mode: .long 0 351 mov.l _rb_bit, r9
210saved_spc: .long 0 352 not r9, r9
211saved_sr: .long 0 353 bsr _set_sr
212saved_vbr: .long 0 354 mov #0, r10
213offset_vbr: .long 0x600 355
214#ifdef CONFIG_CPU_SUBTYPE_SH7724 356 bsr restore_low_regs
215dben_reg: .long 0xfd000010 /* DBEN */
216dben_data0: .long 0
217dben_data1: .long 1
218dbrfpdn0_reg: .long 0xfd000040 /* DBRFPDN0 */
219dbrfpdn0_data0: .long 0
220dbrfpdn0_data1: .long 1
221dbrfpdn0_data2: .long 0x00010000
222dbcmdcnt_reg: .long 0xfd000014 /* DBCMDCNT */
223dbcmdcnt_data0: .long 2
224dbcmdcnt_data1: .long 4
225#else
2261: .long 0xfe400008 /* SDCR0 */
2272: .long 0x00000400
2283: .long 0xffff7fff
2294: .long 0xfffffbff
230#endif
2315: .long 0xa4150020 /* STBCR */
2326: .long 0xfe40001c /* RTCOR */
2337: .long 0xfe400018 /* RTCNT */
2348: .long 0xa55a0000
235
236
237/* interrupt vector @ 0x600 */
238 .balign 0x400,0,0x400
239 .long 0xdeadbeef
240 .balign 0x200,0,0x200
241 bra restore_jump_vbr
242 nop 357 nop
243sh_mobile_standby_end:
244 358
245ENTRY(sh_mobile_standby_size) 359 /* restore the rest of the registers */
246 .long sh_mobile_standby_end - sh_mobile_standby 360 mov.l @r15+, r8
361 mov.l @r15+, r9
362 mov.l @r15+, r10
363 mov.l @r15+, r11
364 mov.l @r15+, r12
365 mov.l @r15+, r13
366 mov.l @r15+, r14
367 lds.l @r15+, pr
368
369skip_restore_regs:
370 rte
371 nop
372
373restore_register:
374 add #SH_SLEEP_BASE_DATA, r0
375 mov.l @(r0, r5), r1
376 add #-SH_SLEEP_BASE_DATA, r0
377 add #SH_SLEEP_BASE_ADDR, r0
378 mov.l @(r0, r5), r0
379 mov.l r1, @r0
380 rts
381 nop
382
383_set_sr:
384 stc sr, r8
385 and r9, r8
386 or r10, r8
387 ldc r8, sr
388 rts
389 nop
390
391restore_low_regs:
392 mov.l @r15+, r0
393 mov.l @r15+, r1
394 mov.l @r15+, r2
395 mov.l @r15+, r3
396 mov.l @r15+, r4
397 mov.l @r15+, r5
398 mov.l @r15+, r6
399 rts
400 mov.l @r15+, r7
401
402 .balign 4
403_rb_bit: .long 0x20000000 ! RB=1
4041: .long ~0x7ff
405ENTRY(sh_mobile_sleep_resume_end)
diff --git a/arch/sh/kernel/cpu/ubc.S b/arch/sh/kernel/cpu/ubc.S
deleted file mode 100644
index 81923079fa12..000000000000
--- a/arch/sh/kernel/cpu/ubc.S
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/ubc.S
3 *
4 * Set of management routines for the User Break Controller (UBC)
5 *
6 * Copyright (C) 2002 Paul Mundt
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/linkage.h>
14#include <asm/ubc.h>
15
16#define STBCR2 0xffc00010
17
18ENTRY(ubc_sleep)
19 mov #0, r0
20
21 mov.l 1f, r1 ! Zero out UBC_BBRA ..
22 mov.w r0, @r1
23
24 mov.l 2f, r1 ! .. same for BBRB ..
25 mov.w r0, @r1
26
27 mov.l 3f, r1 ! .. and again for BRCR.
28 mov.w r0, @r1
29
30 mov.w @r1, r0 ! Dummy read BRCR
31
32 mov.l 4f, r1 ! Set MSTP5 in STBCR2
33 mov.b @r1, r0
34 or #0x01, r0
35 mov.b r0, @r1
36
37 mov.b @r1, r0 ! Two dummy reads ..
38 mov.b @r1, r0
39
40 rts
41 nop
42
43ENTRY(ubc_wakeup)
44 mov.l 4f, r1 ! Clear MSTP5
45 mov.b @r1, r0
46 and #0xfe, r0
47 mov.b r0, @r1
48
49 mov.b @r1, r0 ! Two more dummy reads ..
50 mov.b @r1, r0
51
52 rts
53 nop
54
551: .long UBC_BBRA
562: .long UBC_BBRB
573: .long UBC_BRCR
584: .long STBCR2
59
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-24 11:02:59 -0400