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-rw-r--r--arch/ppc/platforms/85xx/Kconfig10
-rw-r--r--arch/ppc/platforms/85xx/Makefile1
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c5
-rw-r--r--arch/ppc/platforms/85xx/mpc8560_ads.c1
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_ads_common.c37
-rw-r--r--arch/ppc/platforms/85xx/mpc85xx_cds_common.c96
-rw-r--r--arch/ppc/platforms/85xx/sbc8560.c5
-rw-r--r--arch/ppc/platforms/85xx/sbc85xx.c37
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c37
9 files changed, 67 insertions, 162 deletions
diff --git a/arch/ppc/platforms/85xx/Kconfig b/arch/ppc/platforms/85xx/Kconfig
index ff92e38e7da1..c5bc2821d991 100644
--- a/arch/ppc/platforms/85xx/Kconfig
+++ b/arch/ppc/platforms/85xx/Kconfig
@@ -21,6 +21,11 @@ config MPC8540_ADS
21 help 21 help
22 This option enables support for the MPC 8540 ADS evaluation board. 22 This option enables support for the MPC 8540 ADS evaluation board.
23 23
24config MPC8548_CDS
25 bool "Freescale MPC8548 CDS"
26 help
27 This option enablese support for the MPC8548 CDS evaluation board.
28
24config MPC8555_CDS 29config MPC8555_CDS
25 bool "Freescale MPC8555 CDS" 30 bool "Freescale MPC8555 CDS"
26 help 31 help
@@ -53,6 +58,11 @@ config MPC8540
53 depends on MPC8540_ADS 58 depends on MPC8540_ADS
54 default y 59 default y
55 60
61config MPC8548
62 bool
63 depends on MPC8548_CDS
64 default y
65
56config MPC8555 66config MPC8555
57 bool 67 bool
58 depends on MPC8555_CDS 68 depends on MPC8555_CDS
diff --git a/arch/ppc/platforms/85xx/Makefile b/arch/ppc/platforms/85xx/Makefile
index 854fbd298ba2..efdf813108f2 100644
--- a/arch/ppc/platforms/85xx/Makefile
+++ b/arch/ppc/platforms/85xx/Makefile
@@ -2,6 +2,7 @@
2# Makefile for the PowerPC 85xx linux kernel. 2# Makefile for the PowerPC 85xx linux kernel.
3# 3#
4obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads_common.o mpc8540_ads.o 4obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads_common.o mpc8540_ads.o
5obj-$(CONFIG_MPC8548_CDS) += mpc85xx_cds_common.o
5obj-$(CONFIG_MPC8555_CDS) += mpc85xx_cds_common.o 6obj-$(CONFIG_MPC8555_CDS) += mpc85xx_cds_common.o
6obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o 7obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads_common.o mpc8560_ads.o
7obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o 8obj-$(CONFIG_SBC8560) += sbc85xx.o sbc8560.o
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
index 583838ab02d8..a2ed611cd936 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -41,7 +41,6 @@
41#include <asm/time.h> 41#include <asm/time.h>
42#include <asm/io.h> 42#include <asm/io.h>
43#include <asm/machdep.h> 43#include <asm/machdep.h>
44#include <asm/prom.h>
45#include <asm/open_pic.h> 44#include <asm/open_pic.h>
46#include <asm/bootinfo.h> 45#include <asm/bootinfo.h>
47#include <asm/pci-bridge.h> 46#include <asm/pci-bridge.h>
@@ -88,7 +87,7 @@ mpc8540ads_setup_arch(void)
88#ifdef CONFIG_SERIAL_TEXT_DEBUG 87#ifdef CONFIG_SERIAL_TEXT_DEBUG
89 /* Invalidate the entry we stole earlier the serial ports 88 /* Invalidate the entry we stole earlier the serial ports
90 * should be properly mapped */ 89 * should be properly mapped */
91 invalidate_tlbcam_entry(NUM_TLBCAMS - 1); 90 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
92#endif 91#endif
93 92
94 /* setup the board related information for the enet controllers */ 93 /* setup the board related information for the enet controllers */
@@ -150,7 +149,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
150 struct uart_port p; 149 struct uart_port p;
151 150
152 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ 151 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
153 settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base, 152 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
154 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); 153 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
155 154
156 memset(&p, 0, sizeof (p)); 155 memset(&p, 0, sizeof (p));
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index 761b8c7b25d2..d87dfd5ce0a2 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -41,7 +41,6 @@
41#include <asm/time.h> 41#include <asm/time.h>
42#include <asm/io.h> 42#include <asm/io.h>
43#include <asm/machdep.h> 43#include <asm/machdep.h>
44#include <asm/prom.h>
45#include <asm/open_pic.h> 44#include <asm/open_pic.h>
46#include <asm/bootinfo.h> 45#include <asm/bootinfo.h>
47#include <asm/pci-bridge.h> 46#include <asm/pci-bridge.h>
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
index ba9f9f562c45..18e952d1767c 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
@@ -36,7 +36,6 @@
36#include <asm/time.h> 36#include <asm/time.h>
37#include <asm/io.h> 37#include <asm/io.h>
38#include <asm/machdep.h> 38#include <asm/machdep.h>
39#include <asm/prom.h>
40#include <asm/open_pic.h> 39#include <asm/open_pic.h>
41#include <asm/bootinfo.h> 40#include <asm/bootinfo.h>
42#include <asm/pci-bridge.h> 41#include <asm/pci-bridge.h>
@@ -59,40 +58,8 @@ extern unsigned long total_memory; /* in mm/init */
59unsigned char __res[sizeof (bd_t)]; 58unsigned char __res[sizeof (bd_t)];
60 59
61/* Internal interrupts are all Level Sensitive, and Positive Polarity */ 60/* Internal interrupts are all Level Sensitive, and Positive Polarity */
62
63static u_char mpc85xx_ads_openpic_initsenses[] __initdata = { 61static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ 62 MPC85XX_INTERNAL_IRQ_SENSES,
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
96 0x0, /* External 0: */ 63 0x0, /* External 0: */
97#if defined(CONFIG_PCI) 64#if defined(CONFIG_PCI)
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */ 65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
@@ -159,7 +126,7 @@ mpc85xx_ads_init_IRQ(void)
159 /* Skip reserved space and internal sources */ 126 /* Skip reserved space and internal sources */
160 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); 127 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
161 /* Map PIC IRQs 0-11 */ 128 /* Map PIC IRQs 0-11 */
162 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); 129 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
163 130
164 /* we let openpic interrupts starting from an offset, to 131 /* we let openpic interrupts starting from an offset, to
165 * leave space for cascading interrupts underneath. 132 * leave space for cascading interrupts underneath.
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index e7cfa498568c..203b2ca61df8 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -42,7 +42,6 @@
42#include <asm/todc.h> 42#include <asm/todc.h>
43#include <asm/io.h> 43#include <asm/io.h>
44#include <asm/machdep.h> 44#include <asm/machdep.h>
45#include <asm/prom.h>
46#include <asm/open_pic.h> 45#include <asm/open_pic.h>
47#include <asm/i8259.h> 46#include <asm/i8259.h>
48#include <asm/bootinfo.h> 47#include <asm/bootinfo.h>
@@ -73,40 +72,8 @@ static int cds_pci_slot = 2;
73static volatile u8 * cadmus; 72static volatile u8 * cadmus;
74 73
75/* Internal interrupts are all Level Sensitive, and Positive Polarity */ 74/* Internal interrupts are all Level Sensitive, and Positive Polarity */
76
77static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { 75static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ 76 MPC85XX_INTERNAL_IRQ_SENSES,
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
107 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
110#if defined(CONFIG_PCI) 77#if defined(CONFIG_PCI)
111 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */ 78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
112 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */ 79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
@@ -182,7 +149,6 @@ void __init
182mpc85xx_cds_init_IRQ(void) 149mpc85xx_cds_init_IRQ(void)
183{ 150{
184 bd_t *binfo = (bd_t *) __res; 151 bd_t *binfo = (bd_t *) __res;
185 int i;
186 152
187 /* Determine the Physical Address of the OpenPIC regs */ 153 /* Determine the Physical Address of the OpenPIC regs */
188 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; 154 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
@@ -191,9 +157,13 @@ mpc85xx_cds_init_IRQ(void)
191 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses); 157 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
192 158
193 /* Skip reserved space and internal sources */ 159 /* Skip reserved space and internal sources */
160#ifdef CONFIG_MPC8548
161 openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
162#else
194 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); 163 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
164#endif
195 /* Map PIC IRQs 0-11 */ 165 /* Map PIC IRQs 0-11 */
196 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); 166 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
197 167
198 /* we let openpic interrupts starting from an offset, to 168 /* we let openpic interrupts starting from an offset, to
199 * leave space for cascading interrupts underneath. 169 * leave space for cascading interrupts underneath.
@@ -475,26 +445,52 @@ mpc85xx_cds_setup_arch(void)
475#ifdef CONFIG_SERIAL_TEXT_DEBUG 445#ifdef CONFIG_SERIAL_TEXT_DEBUG
476 /* Invalidate the entry we stole earlier the serial ports 446 /* Invalidate the entry we stole earlier the serial ports
477 * should be properly mapped */ 447 * should be properly mapped */
478 invalidate_tlbcam_entry(NUM_TLBCAMS - 1); 448 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
479#endif 449#endif
480 450
481 /* setup the board related information for the enet controllers */ 451 /* setup the board related information for the enet controllers */
482 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 452 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
483 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 453 if (pdata) {
484 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 454 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
485 pdata->phyid = 0; 455 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
486 /* fixup phy address */ 456 pdata->phyid = 0;
487 pdata->phy_reg_addr += binfo->bi_immr_base; 457 /* fixup phy address */
488 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 458 pdata->phy_reg_addr += binfo->bi_immr_base;
459 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
460 }
489 461
490 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 462 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
491 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 463 if (pdata) {
492 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 464 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
493 pdata->phyid = 1; 465 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
494 /* fixup phy address */ 466 pdata->phyid = 1;
495 pdata->phy_reg_addr += binfo->bi_immr_base; 467 /* fixup phy address */
496 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 468 pdata->phy_reg_addr += binfo->bi_immr_base;
469 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
470 }
471
472 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
473 if (pdata) {
474 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
475 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
476 pdata->phyid = 0;
477 /* fixup phy address */
478 pdata->phy_reg_addr += binfo->bi_immr_base;
479 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
480 }
481
482 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
483 if (pdata) {
484 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
485 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
486 pdata->phyid = 1;
487 /* fixup phy address */
488 pdata->phy_reg_addr += binfo->bi_immr_base;
489 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
490 }
497 491
492 ppc_sys_device_remove(MPC85xx_eTSEC3);
493 ppc_sys_device_remove(MPC85xx_eTSEC4);
498 494
499#ifdef CONFIG_BLK_DEV_INITRD 495#ifdef CONFIG_BLK_DEV_INITRD
500 if (initrd_start) 496 if (initrd_start)
@@ -531,7 +527,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
531 struct uart_port p; 527 struct uart_port p;
532 528
533 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ 529 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
534 settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base, 530 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
535 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); 531 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
536 532
537 memset(&p, 0, sizeof (p)); 533 memset(&p, 0, sizeof (p));
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
index 7b9e1543e175..3dbdd73618eb 100644
--- a/arch/ppc/platforms/85xx/sbc8560.c
+++ b/arch/ppc/platforms/85xx/sbc8560.c
@@ -41,7 +41,6 @@
41#include <asm/time.h> 41#include <asm/time.h>
42#include <asm/io.h> 42#include <asm/io.h>
43#include <asm/machdep.h> 43#include <asm/machdep.h>
44#include <asm/prom.h>
45#include <asm/open_pic.h> 44#include <asm/open_pic.h>
46#include <asm/bootinfo.h> 45#include <asm/bootinfo.h>
47#include <asm/pci-bridge.h> 46#include <asm/pci-bridge.h>
@@ -125,7 +124,7 @@ sbc8560_setup_arch(void)
125#ifdef CONFIG_SERIAL_TEXT_DEBUG 124#ifdef CONFIG_SERIAL_TEXT_DEBUG
126 /* Invalidate the entry we stole earlier the serial ports 125 /* Invalidate the entry we stole earlier the serial ports
127 * should be properly mapped */ 126 * should be properly mapped */
128 invalidate_tlbcam_entry(NUM_TLBCAMS - 1); 127 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
129#endif 128#endif
130 129
131 /* setup the board related information for the enet controllers */ 130 /* setup the board related information for the enet controllers */
@@ -176,7 +175,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
176 175
177#ifdef CONFIG_SERIAL_TEXT_DEBUG 176#ifdef CONFIG_SERIAL_TEXT_DEBUG
178 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ 177 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
179 settlbcam(NUM_TLBCAMS - 1, UARTA_ADDR, 178 settlbcam(num_tlbcam_entries - 1, UARTA_ADDR,
180 UARTA_ADDR, 0x1000, _PAGE_IO, 0); 179 UARTA_ADDR, 0x1000, _PAGE_IO, 0);
181#endif 180#endif
182 181
diff --git a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c
index 2d638c1c1bd6..4f6d1ddd6fb8 100644
--- a/arch/ppc/platforms/85xx/sbc85xx.c
+++ b/arch/ppc/platforms/85xx/sbc85xx.c
@@ -35,7 +35,6 @@
35#include <asm/time.h> 35#include <asm/time.h>
36#include <asm/io.h> 36#include <asm/io.h>
37#include <asm/machdep.h> 37#include <asm/machdep.h>
38#include <asm/prom.h>
39#include <asm/open_pic.h> 38#include <asm/open_pic.h>
40#include <asm/bootinfo.h> 39#include <asm/bootinfo.h>
41#include <asm/pci-bridge.h> 40#include <asm/pci-bridge.h>
@@ -59,40 +58,8 @@ unsigned long pci_dram_offset = 0;
59extern unsigned long total_memory; /* in mm/init */ 58extern unsigned long total_memory; /* in mm/init */
60 59
61/* Internal interrupts are all Level Sensitive, and Positive Polarity */ 60/* Internal interrupts are all Level Sensitive, and Positive Polarity */
62
63static u_char sbc8560_openpic_initsenses[] __initdata = { 61static u_char sbc8560_openpic_initsenses[] __initdata = {
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ 62 MPC85XX_INTERNAL_IRQ_SENSES,
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
96 0x0, /* External 0: */ 63 0x0, /* External 0: */
97 0x0, /* External 1: */ 64 0x0, /* External 1: */
98#if defined(CONFIG_PCI) 65#if defined(CONFIG_PCI)
@@ -159,7 +126,7 @@ sbc8560_init_IRQ(void)
159 /* Skip reserved space and internal sources */ 126 /* Skip reserved space and internal sources */
160 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); 127 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
161 /* Map PIC IRQs 0-11 */ 128 /* Map PIC IRQs 0-11 */
162 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); 129 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
163 130
164 /* we let openpic interrupts starting from an offset, to 131 /* we let openpic interrupts starting from an offset, to
165 * leave space for cascading interrupts underneath. 132 * leave space for cascading interrupts underneath.
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index bc95836e417c..9455bb6b45e9 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -46,7 +46,6 @@
46#include <asm/time.h> 46#include <asm/time.h>
47#include <asm/io.h> 47#include <asm/io.h>
48#include <asm/machdep.h> 48#include <asm/machdep.h>
49#include <asm/prom.h>
50#include <asm/open_pic.h> 49#include <asm/open_pic.h>
51#include <asm/bootinfo.h> 50#include <asm/bootinfo.h>
52#include <asm/pci-bridge.h> 51#include <asm/pci-bridge.h>
@@ -72,38 +71,7 @@ unsigned long pci_dram_offset = 0;
72 71
73/* Internal interrupts are all Level Sensitive, and Positive Polarity */ 72/* Internal interrupts are all Level Sensitive, and Positive Polarity */
74static u8 gp3_openpic_initsenses[] __initdata = { 73static u8 gp3_openpic_initsenses[] __initdata = {
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ 74 MPC85XX_INTERNAL_IRQ_SENSES,
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
107 0x0, /* External 0: */ 75 0x0, /* External 0: */
108#if defined(CONFIG_PCI) 76#if defined(CONFIG_PCI)
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */ 77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
@@ -200,7 +168,6 @@ static struct irqaction cpm2_irqaction = {
200static void __init 168static void __init
201gp3_init_IRQ(void) 169gp3_init_IRQ(void)
202{ 170{
203 int i;
204 bd_t *binfo = (bd_t *) __res; 171 bd_t *binfo = (bd_t *) __res;
205 172
206 /* 173 /*
@@ -218,7 +185,7 @@ gp3_init_IRQ(void)
218 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); 185 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
219 186
220 /* Map PIC IRQs 0-11 */ 187 /* Map PIC IRQs 0-11 */
221 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); 188 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
222 189
223 /* 190 /*
224 * Let openpic interrupts starting from an offset, to 191 * Let openpic interrupts starting from an offset, to
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 00:30:25 -0500