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Diffstat (limited to 'arch/ppc/platforms/85xx/stx_gp3.c')
-rw-r--r--arch/ppc/platforms/85xx/stx_gp3.c37
1 files changed, 2 insertions, 35 deletions
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index bc95836e417c..9455bb6b45e9 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -46,7 +46,6 @@
46#include <asm/time.h> 46#include <asm/time.h>
47#include <asm/io.h> 47#include <asm/io.h>
48#include <asm/machdep.h> 48#include <asm/machdep.h>
49#include <asm/prom.h>
50#include <asm/open_pic.h> 49#include <asm/open_pic.h>
51#include <asm/bootinfo.h> 50#include <asm/bootinfo.h>
52#include <asm/pci-bridge.h> 51#include <asm/pci-bridge.h>
@@ -72,38 +71,7 @@ unsigned long pci_dram_offset = 0;
72 71
73/* Internal interrupts are all Level Sensitive, and Positive Polarity */ 72/* Internal interrupts are all Level Sensitive, and Positive Polarity */
74static u8 gp3_openpic_initsenses[] __initdata = { 73static u8 gp3_openpic_initsenses[] __initdata = {
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */ 74 MPC85XX_INTERNAL_IRQ_SENSES,
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
100 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
101 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
102 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
103 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
104 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
105 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
106 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
107 0x0, /* External 0: */ 75 0x0, /* External 0: */
108#if defined(CONFIG_PCI) 76#if defined(CONFIG_PCI)
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */ 77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
@@ -200,7 +168,6 @@ static struct irqaction cpm2_irqaction = {
200static void __init 168static void __init
201gp3_init_IRQ(void) 169gp3_init_IRQ(void)
202{ 170{
203 int i;
204 bd_t *binfo = (bd_t *) __res; 171 bd_t *binfo = (bd_t *) __res;
205 172
206 /* 173 /*
@@ -218,7 +185,7 @@ gp3_init_IRQ(void)
218 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); 185 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
219 186
220 /* Map PIC IRQs 0-11 */ 187 /* Map PIC IRQs 0-11 */
221 openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000); 188 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
222 189
223 /* 190 /*
224 * Let openpic interrupts starting from an offset, to 191 * Let openpic interrupts starting from an offset, to