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-rw-r--r--arch/ppc/boot/simple/rw4/ppc_40x.h664
-rw-r--r--arch/ppc/boot/simple/rw4/rw4_init.S78
-rw-r--r--arch/ppc/boot/simple/rw4/rw4_init_brd.S1125
-rw-r--r--arch/ppc/boot/simple/rw4/stb.h239
4 files changed, 0 insertions, 2106 deletions
diff --git a/arch/ppc/boot/simple/rw4/ppc_40x.h b/arch/ppc/boot/simple/rw4/ppc_40x.h
deleted file mode 100644
index 561fb26f5a93..000000000000
--- a/arch/ppc/boot/simple/rw4/ppc_40x.h
+++ /dev/null
@@ -1,664 +0,0 @@
1/*----------------------------------------------------------------------------+
2| This source code has been made available to you by IBM on an AS-IS
3| basis. Anyone receiving this source is licensed under IBM
4| copyrights to use it in any way he or she deems fit, including
5| copying it, modifying it, compiling it, and redistributing it either
6| with or without modifications. No license under IBM patents or
7| patent applications is to be implied by the copyright license.
8|
9| Any user of this software should understand that IBM cannot provide
10| technical support for this software and will not be responsible for
11| any consequences resulting from the use of this software.
12|
13| Any person who transfers this source code or any derivative work
14| must include the IBM copyright notice, this paragraph, and the
15| preceding two paragraphs in the transferred software.
16|
17| COPYRIGHT I B M CORPORATION 1997
18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
19+----------------------------------------------------------------------------*/
20/*----------------------------------------------------------------------------+
21| Author: Tony J. Cerreto
22| Component: Assembler include file.
23| File: ppc_40x.h
24| Purpose: Include file containing PPC DCR defines.
25|
26| Changes:
27| Date Author Comment
28| --------- ------ --------------------------------------------------------
29| 01-Mar-00 tjc Created
30+----------------------------------------------------------------------------*/
31/* added by linguohui*/
32#define MW
33/*----------------------------------------------------------------------------+
34| PPC Special purpose registers Numbers
35+----------------------------------------------------------------------------*/
36#define ccr0 0x3b3 /* core configuration reg */
37#define ctr 0x009 /* count register */
38#define ctrreg 0x009 /* count register */
39#define dbcr0 0x3f2 /* debug control register 0 */
40#define dbcr1 0x3bd /* debug control register 1 */
41#define dbsr 0x3f0 /* debug status register */
42#define dccr 0x3fa /* data cache control reg. */
43#define dcwr 0x3ba /* data cache write-thru reg */
44#define dear 0x3d5 /* data exception address reg */
45#define esr 0x3d4 /* exception syndrome register */
46#define evpr 0x3d6 /* exception vector prefix reg */
47#define iccr 0x3fb /* instruction cache cntrl re */
48#define icdbdr 0x3d3 /* instr cache dbug data reg */
49#define lrreg 0x008 /* link register */
50#define pid 0x3b1 /* process id reg */
51#define pit 0x3db /* programmable interval time */
52#define pvr 0x11f /* processor version register */
53#define sgr 0x3b9 /* storage guarded reg */
54#define sler 0x3bb /* storage little endian reg */
55#define sprg0 0x110 /* special general purpose 0 */
56#define sprg1 0x111 /* special general purpose 1 */
57#define sprg2 0x112 /* special general purpose 2 */
58#define sprg3 0x113 /* special general purpose 3 */
59#define sprg4 0x114 /* special general purpose 4 */
60#define sprg5 0x115 /* special general purpose 5 */
61#define sprg6 0x116 /* special general purpose 6 */
62#define sprg7 0x117 /* special general purpose 7 */
63#define srr0 0x01a /* save/restore register 0 */
64#define srr1 0x01b /* save/restore register 1 */
65#define srr2 0x3de /* save/restore register 2 */
66#define srr3 0x3df /* save/restore register 3 */
67#define tbhi 0x11D
68#define tblo 0x11C
69#define tcr 0x3da /* timer control register */
70#define tsr 0x3d8 /* timer status register */
71#define xerreg 0x001 /* fixed point exception */
72#define xer 0x001 /* fixed point exception */
73#define zpr 0x3b0 /* zone protection reg */
74
75/*----------------------------------------------------------------------------+
76| Decompression Controller
77+----------------------------------------------------------------------------*/
78#define kiar 0x014 /* Decompression cntl addr reg */
79#define kidr 0x015 /* Decompression cntl data reg */
80#define kitor0 0x00 /* index table origin Reg 0 */
81#define kitor1 0x01 /* index table origin Reg 1 */
82#define kitor2 0x02 /* index table origin Reg 2 */
83#define kitor3 0x03 /* index table origin Reg 3 */
84#define kaddr0 0x04 /* addr decode Definition Reg 0 */
85#define kaddr1 0x05 /* addr decode Definition Reg 1 */
86#define kconf 0x40 /* Decompression cntl config reg */
87#define kid 0x41 /* Decompression cntl id reg */
88#define kver 0x42 /* Decompression cntl ver number */
89#define kpear 0x50 /* bus error addr reg (PLB) */
90#define kbear 0x51 /* bus error addr reg (DCP-EBC) */
91#define kesr0 0x52 /* bus error status reg 0 */
92
93/*----------------------------------------------------------------------------+
94| Romeo Specific Device Control Register Numbers.
95+----------------------------------------------------------------------------*/
96#ifndef VESTA
97#define cdbcr 0x3d7 /* cache debug cntrl reg */
98
99#define a_latcnt 0x1a9 /* PLB Latency count */
100#define a_tgval 0x1ac /* tone generation value */
101#define a_plb_pr 0x1bf /* PLB priority */
102
103#define cic_sel1 0x031 /* select register 1 */
104#define cic_sel2 0x032 /* select register 2 */
105
106#define clkgcrst 0x122 /* chip reset register */
107
108#define cp_cpmsr 0x100 /*rstatus register */
109#define cp_cpmer 0x101 /* enable register */
110
111#define dcp_kiar 0x190 /* indirect address register */
112#define dcp_kidr 0x191 /* indirect data register */
113
114#define hsmc_mcgr 0x1c0 /* HSMC global register */
115#define hsmc_mcbesr 0x1c1 /* bus error status register */
116#define hsmc_mcbear 0x1c2 /* bus error address register*/
117#define hsmc_mcbr0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */
118#define hsmc_mccr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */
119#define hsmc_mcbr1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */
120#define hsmc_mccr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */
121#define hsmc_sysr 0x1d1 /* system register */
122#define hsmc_data 0x1d2 /* data register */
123#define hsmc_mccrr 0x1d3 /* refresh register */
124
125#define ocm_pbar 0x1E0 /* base address register */
126
127#define plb0_pacr0 0x057 /* PLB arbiter control reg */
128#define plb1_pacr1 0x067 /* PLB arbiter control reg */
129
130#define v_displb 0x157 /* set left border of display*/
131#define v_disptb 0x158 /* top border of display */
132#define v_osd_la 0x159 /* first link address for OSD*/
133#define v_ptsdlta 0x15E /* PTS delta register */
134#define v_v0base 0x16C /* base mem add for VBI-0 */
135#define v_v1base 0x16D /* base mem add for VBI-1 */
136#define v_osbase 0x16E /* base mem add for OSD data */
137#endif
138
139/*----------------------------------------------------------------------------+
140| Vesta Device Control Register Numbers.
141+----------------------------------------------------------------------------*/
142/*----------------------------------------------------------------------------+
143| Cross bar switch.
144+----------------------------------------------------------------------------*/
145#define cbs0_cr 0x010 /* CBS configuration register */
146
147/*----------------------------------------------------------------------------+
148| DCR external master (DCRX).
149+----------------------------------------------------------------------------*/
150#define dcrx0_icr 0x020 /* internal control register */
151#define dcrx0_isr 0x021 /* internal status register */
152#define dcrx0_ecr 0x022 /* external control register */
153#define dcrx0_esr 0x023 /* external status register */
154#define dcrx0_tar 0x024 /* target address register */
155#define dcrx0_tdr 0x025 /* target data register */
156#define dcrx0_igr 0x026 /* interrupt generation register */
157#define dcrx0_bcr 0x027 /* buffer control register */
158
159/*----------------------------------------------------------------------------+
160| Chip interconnect configuration.
161+----------------------------------------------------------------------------*/
162#define cic0_cr 0x030 /* CIC control register */
163#define cic0_vcr 0x033 /* video macro control reg */
164#define cic0_sel3 0x035 /* select register 3 */
165
166/*----------------------------------------------------------------------------+
167| Chip interconnect configuration.
168+----------------------------------------------------------------------------*/
169#define sgpo0_sgpO 0x036 /* simplified GPIO output */
170#define sgpo0_gpod 0x037 /* simplified GPIO open drain */
171#define sgpo0_gptc 0x038 /* simplified GPIO tristate cntl */
172#define sgpo0_gpi 0x039 /* simplified GPIO input */
173
174/*----------------------------------------------------------------------------+
175| Universal interrupt controller.
176+----------------------------------------------------------------------------*/
177#define uic0_sr 0x040 /* status register */
178#define uic0_srs 0x041 /* status register set */
179#define uic0_er 0x042 /* enable register */
180#define uic0_cr 0x043 /* critical register */
181#define uic0_pr 0x044 /* parity register */
182#define uic0_tr 0x045 /* triggering register */
183#define uic0_msr 0x046 /* masked status register */
184#define uic0_vr 0x047 /* vector register */
185#define uic0_vcr 0x048 /* enable config register */
186
187/*----------------------------------------------------------------------------+
188| PLB 0 and 1.
189+----------------------------------------------------------------------------*/
190#define pb0_pesr 0x054 /* PLB error status reg 0 */
191#define pb0_pesrs 0x055 /* PLB error status reg 0 set */
192#define pb0_pear 0x056 /* PLB error address reg */
193
194#define pb1_pesr 0x064 /* PLB error status reg 1 */
195#define pb1_pesrs 0x065 /* PLB error status reg 1 set */
196#define pb1_pear 0x066 /* PLB error address reg */
197
198/*----------------------------------------------------------------------------+
199| EBIU DCR registers.
200+----------------------------------------------------------------------------*/
201#define ebiu0_brcrh0 0x070 /* bus region register 0 high */
202#define ebiu0_brcrh1 0x071 /* bus region register 1 high */
203#define ebiu0_brcrh2 0x072 /* bus region register 2 high */
204#define ebiu0_brcrh3 0x073 /* bus region register 3 high */
205#define ebiu0_brcrh4 0x074 /* bus region register 4 high */
206#define ebiu0_brcrh5 0x075 /* bus region register 5 high */
207#define ebiu0_brcrh6 0x076 /* bus region register 6 high */
208#define ebiu0_brcrh7 0x077 /* bus region register 7 high */
209#define ebiu0_brcr0 0x080 /* bus region register 0 */
210#define ebiu0_brcr1 0x081 /* bus region register 1 */
211#define ebiu0_brcr2 0x082 /* bus region register 2 */
212#define ebiu0_brcr3 0x083 /* bus region register 3 */
213#define ebiu0_brcr4 0x084 /* bus region register 4 */
214#define ebiu0_brcr5 0x085 /* bus region register 5 */
215#define ebiu0_brcr6 0x086 /* bus region register 6 */
216#define ebiu0_brcr7 0x087 /* bus region register 7 */
217#define ebiu0_bear 0x090 /* bus error address register */
218#define ebiu0_besr 0x091 /* bus error syndrome reg */
219#define ebiu0_besr0s 0x093 /* bus error syndrome reg */
220#define ebiu0_biucr 0x09a /* bus interface control reg */
221
222/*----------------------------------------------------------------------------+
223| OPB bridge.
224+----------------------------------------------------------------------------*/
225#define opbw0_gesr 0x0b0 /* error status reg */
226#define opbw0_gesrs 0x0b1 /* error status reg */
227#define opbw0_gear 0x0b2 /* error address reg */
228
229/*----------------------------------------------------------------------------+
230| DMA.
231+----------------------------------------------------------------------------*/
232#define dma0_cr0 0x0c0 /* DMA channel control reg 0 */
233#define dma0_ct0 0x0c1 /* DMA count register 0 */
234#define dma0_da0 0x0c2 /* DMA destination addr reg 0 */
235#define dma0_sa0 0x0c3 /* DMA source addr register 0 */
236#define dma0_cc0 0x0c4 /* DMA chained count 0 */
237#define dma0_cr1 0x0c8 /* DMA channel control reg 1 */
238#define dma0_ct1 0x0c9 /* DMA count register 1 */
239#define dma0_da1 0x0ca /* DMA destination addr reg 1 */
240#define dma0_sa1 0x0cb /* DMA source addr register 1 */
241#define dma0_cc1 0x0cc /* DMA chained count 1 */
242#define dma0_cr2 0x0d0 /* DMA channel control reg 2 */
243#define dma0_ct2 0x0d1 /* DMA count register 2 */
244#define dma0_da2 0x0d2 /* DMA destination addr reg 2 */
245#define dma0_sa2 0x0d3 /* DMA source addr register 2 */
246#define dma0_cc2 0x0d4 /* DMA chained count 2 */
247#define dma0_cr3 0x0d8 /* DMA channel control reg 3 */
248#define dma0_ct3 0x0d9 /* DMA count register 3 */
249#define dma0_da3 0x0da /* DMA destination addr reg 3 */
250#define dma0_sa3 0x0db /* DMA source addr register 3 */
251#define dma0_cc3 0x0dc /* DMA chained count 3 */
252#define dma0_sr 0x0e0 /* DMA status register */
253#define dma0_srs 0x0e1 /* DMA status register */
254#define dma0_s1 0x031 /* DMA select1 register */
255#define dma0_s2 0x032 /* DMA select2 register */
256
257/*---------------------------------------------------------------------------+
258| Clock and power management.
259+----------------------------------------------------------------------------*/
260#define cpm0_fr 0x102 /* force register */
261
262/*----------------------------------------------------------------------------+
263| Serial Clock Control.
264+----------------------------------------------------------------------------*/
265#define ser0_ccr 0x120 /* serial clock control register */
266
267/*----------------------------------------------------------------------------+
268| Audio Clock Control.
269+----------------------------------------------------------------------------*/
270#define aud0_apcr 0x121 /* audio clock ctrl register */
271
272/*----------------------------------------------------------------------------+
273| DENC.
274+----------------------------------------------------------------------------*/
275#define denc0_idr 0x130 /* DENC ID register */
276#define denc0_cr1 0x131 /* control register 1 */
277#define denc0_rr1 0x132 /* microvision 1 (reserved 1) */
278#define denc0_cr2 0x133 /* control register 2 */
279#define denc0_rr2 0x134 /* microvision 2 (reserved 2) */
280#define denc0_rr3 0x135 /* microvision 3 (reserved 3) */
281#define denc0_rr4 0x136 /* microvision 4 (reserved 4) */
282#define denc0_rr5 0x137 /* microvision 5 (reserved 5) */
283#define denc0_ccdr 0x138 /* closed caption data */
284#define denc0_cccr 0x139 /* closed caption control */
285#define denc0_trr 0x13A /* teletext request register */
286#define denc0_tosr 0x13B /* teletext odd field line se */
287#define denc0_tesr 0x13C /* teletext even field line s */
288#define denc0_rlsr 0x13D /* RGB rhift left register */
289#define denc0_vlsr 0x13E /* video level shift register */
290#define denc0_vsr 0x13F /* video scaling register */
291
292/*----------------------------------------------------------------------------+
293| Video decoder. Suspect 0x179, 0x169, 0x16a, 0x152 (rc).
294+----------------------------------------------------------------------------*/
295#define vid0_ccntl 0x140 /* control decoder operation */
296#define vid0_cmode 0x141 /* video operational mode */
297#define vid0_sstc0 0x142 /* STC high order bits 31:0 */
298#define vid0_sstc1 0x143 /* STC low order bit 32 */
299#define vid0_spts0 0x144 /* PTS high order bits 31:0 */
300#define vid0_spts1 0x145 /* PTS low order bit 32 */
301#define vid0_fifo 0x146 /* FIFO data port */
302#define vid0_fifos 0x147 /* FIFO status */
303#define vid0_cmd 0x148 /* send command to decoder */
304#define vid0_cmdd 0x149 /* port for command params */
305#define vid0_cmdst 0x14A /* command status */
306#define vid0_cmdad 0x14B /* command address */
307#define vid0_procia 0x14C /* instruction store */
308#define vid0_procid 0x14D /* data port for I_Store */
309#define vid0_osdm 0x151 /* OSD mode control */
310#define vid0_hosti 0x152 /* base interrupt register */
311#define vid0_mask 0x153 /* interrupt mask register */
312#define vid0_dispm 0x154 /* operational mode for Disp */
313#define vid0_dispd 0x155 /* setting for 'Sync' delay */
314#define vid0_vbctl 0x156 /* VBI */
315#define vid0_ttxctl 0x157 /* teletext control */
316#define vid0_disptb 0x158 /* display left/top border */
317#define vid0_osdgla 0x159 /* Graphics plane link addr */
318#define vid0_osdila 0x15A /* Image plane link addr */
319#define vid0_rbthr 0x15B /* rate buffer threshold */
320#define vid0_osdcla 0x15C /* Cursor link addr */
321#define vid0_stcca 0x15D /* STC common address */
322#define vid0_ptsctl 0x15F /* PTS Control */
323#define vid0_wprot 0x165 /* write protect for I_Store */
324#define vid0_vcqa 0x167 /* video clip queued block Ad */
325#define vid0_vcql 0x168 /* video clip queued block Le */
326#define vid0_blksz 0x169 /* block size bytes for copy op */
327#define vid0_srcad 0x16a /* copy source address bits 6-31 */
328#define vid0_udbas 0x16B /* base mem add for user data */
329#define vid0_vbibas 0x16C /* base mem add for VBI 0/1 */
330#define vid0_osdibas 0x16D /* Image plane base address */
331#define vid0_osdgbas 0x16E /* Graphic plane base address */
332#define vid0_rbbase 0x16F /* base mem add for video buf */
333#define vid0_dramad 0x170 /* DRAM address */
334#define vid0_dramdt 0x171 /* data port for DRAM access */
335#define vid0_dramcs 0x172 /* DRAM command and statusa */
336#define vid0_vcwa 0x173 /* v clip work address */
337#define vid0_vcwl 0x174 /* v clip work length */
338#define vid0_mseg0 0x175 /* segment address 0 */
339#define vid0_mseg1 0x176 /* segment address 1 */
340#define vid0_mseg2 0x177 /* segment address 2 */
341#define vid0_mseg3 0x178 /* segment address 3 */
342#define vid0_fbbase 0x179 /* frame buffer base memory */
343#define vid0_osdcbas 0x17A /* Cursor base addr */
344#define vid0_lboxtb 0x17B /* top left border */
345#define vid0_trdly 0x17C /* transparency gate delay */
346#define vid0_sbord 0x17D /* left/top small pict. bord. */
347#define vid0_zoffs 0x17E /* hor/ver zoom window */
348#define vid0_rbsz 0x17F /* rate buffer size read */
349
350/*----------------------------------------------------------------------------+
351| Transport demultiplexer.
352+----------------------------------------------------------------------------*/
353#define xpt0_lr 0x180 /* demux location register */
354#define xpt0_data 0x181 /* demux data register */
355#define xpt0_ir 0x182 /* demux interrupt register */
356
357#define xpt0_config1 0x0000 /* configuration 1 */
358#define xpt0_control1 0x0001 /* control 1 */
359#define xpt0_festat 0x0002 /* Front-end status */
360#define xpt0_feimask 0x0003 /* Front_end interrupt Mask */
361#define xpt0_ocmcnfg 0x0004 /* OCM Address */
362#define xpt0_settapi 0x0005 /* Set TAP Interrupt */
363
364#define xpt0_pcrhi 0x0010 /* PCR High */
365#define xpt0_pcrlow 0x0011 /* PCR Low */
366#define xpt0_lstchi 0x0012 /* Latched STC High */
367#define xpt0_lstclow 0x0013 /* Latched STC Low */
368#define xpt0_stchi 0x0014 /* STC High */
369#define xpt0_stclow 0x0015 /* STC Low */
370#define xpt0_pwm 0x0016 /* PWM */
371#define xpt0_pcrstct 0x0017 /* PCR-STC Threshold */
372#define xpt0_pcrstcd 0x0018 /* PCR-STC Delta */
373#define xpt0_stccomp 0x0019 /* STC Compare */
374#define xpt0_stccmpd 0x001a /* STC Compare Disarm */
375
376#define xpt0_dsstat 0x0048 /* Descrambler Status */
377#define xpt0_dsimask 0x0049 /* Descrambler Interrupt Mask */
378
379#define xpt0_vcchng 0x01f0 /* Video Channel Change */
380#define xpt0_acchng 0x01f1 /* Audio Channel Change */
381#define xpt0_axenable 0x01fe /* Aux PID Enables */
382#define xpt0_pcrpid 0x01ff /* PCR PID */
383
384#define xpt0_config2 0x1000 /* Configuration 2 */
385#define xpt0_pbuflvl 0x1002 /* Packet Buffer Level */
386#define xpt0_intmask 0x1003 /* Interrupt Mask */
387#define xpt0_plbcnfg 0x1004 /* PLB Configuration */
388
389#define xpt0_qint 0x1010 /* Queues Interrupts */
390#define xpt0_qintmsk 0x1011 /* Queues Interrupts Mask */
391#define xpt0_astatus 0x1012 /* Audio Status */
392#define xpt0_aintmask 0x1013 /* Audio Interrupt Mask */
393#define xpt0_vstatus 0x1014 /* Video Status */
394#define xpt0_vintmask 0x1015 /* Video Interrupt Mask */
395
396#define xpt0_qbase 0x1020 /* Queue Base */
397#define xpt0_bucketq 0x1021 /* Bucket Queue */
398#define xpt0_qstops 0x1024 /* Queue Stops */
399#define xpt0_qresets 0x1025 /* Queue Resets */
400#define xpt0_sfchng 0x1026 /* Section Filter Change */
401
402/*----------------------------------------------------------------------------+
403| Audio decoder. Suspect 0x1ad, 0x1b4, 0x1a3, 0x1a5 (read/write status)
404+----------------------------------------------------------------------------*/
405#define aud0_ctrl0 0x1a0 /* control 0 */
406#define aud0_ctrl1 0x1a1 /* control 1 */
407#define aud0_ctrl2 0x1a2 /* control 2 */
408#define aud0_cmd 0x1a3 /* command register */
409#define aud0_isr 0x1a4 /* interrupt status register */
410#define aud0_imr 0x1a5 /* interrupt mask register */
411#define aud0_dsr 0x1a6 /* decoder status register */
412#define aud0_stc 0x1a7 /* system time clock */
413#define aud0_csr 0x1a8 /* channel status register */
414#define aud0_lcnt 0x1a9 /* queued address register 2 */
415#define aud0_pts 0x1aa /* presentation time stamp */
416#define aud0_tgctrl 0x1ab /* tone generation control */
417#define aud0_qlr2 0x1ac /* queued length register 2 */
418#define aud0_auxd 0x1ad /* aux data */
419#define aud0_strmid 0x1ae /* stream ID */
420#define aud0_qar 0x1af /* queued address register */
421#define aud0_dsps 0x1b0 /* DSP status */
422#define aud0_qlr 0x1b1 /* queued len address */
423#define aud0_dspc 0x1b2 /* DSP control */
424#define aud0_wlr2 0x1b3 /* working length register 2 */
425#define aud0_instd 0x1b4 /* instruction download */
426#define aud0_war 0x1b5 /* working address register */
427#define aud0_seg1 0x1b6 /* segment 1 base register */
428#define aud0_seg2 0x1b7 /* segment 2 base register */
429#define aud0_avf 0x1b9 /* audio att value front */
430#define aud0_avr 0x1ba /* audio att value rear */
431#define aud0_avc 0x1bb /* audio att value center */
432#define aud0_seg3 0x1bc /* segment 3 base register */
433#define aud0_offset 0x1bd /* offset address */
434#define aud0_wrl 0x1be /* working length register */
435#define aud0_war2 0x1bf /* working address register 2 */
436
437/*----------------------------------------------------------------------------+
438| High speed memory controller 0 and 1.
439+----------------------------------------------------------------------------*/
440#define hsmc0_gr 0x1e0 /* HSMC global register */
441#define hsmc0_besr 0x1e1 /* bus error status register */
442#define hsmc0_bear 0x1e2 /* bus error address register */
443#define hsmc0_br0 0x1e4 /* SDRAM sub-ctrl bank reg 0 */
444#define hsmc0_cr0 0x1e5 /* SDRAM sub-ctrl ctrl reg 0 */
445#define hsmc0_br1 0x1e7 /* SDRAM sub-ctrl bank reg 1 */
446#define hsmc0_cr1 0x1e8 /* SDRAM sub-ctrl ctrl reg 1 */
447#define hsmc0_sysr 0x1f1 /* system register */
448#define hsmc0_data 0x1f2 /* data register */
449#define hsmc0_crr 0x1f3 /* refresh register */
450
451#define hsmc1_gr 0x1c0 /* HSMC global register */
452#define hsmc1_besr 0x1c1 /* bus error status register */
453#define hsmc1_bear 0x1c2 /* bus error address register */
454#define hsmc1_br0 0x1c4 /* SDRAM sub-ctrl bank reg 0 */
455#define hsmc1_cr0 0x1c5 /* SDRAM sub-ctrl ctrl reg 0 */
456#define hsmc1_br1 0x1c7 /* SDRAM sub-ctrl bank reg 1 */
457#define hsmc1_cr1 0x1c8 /* SDRAM sub-ctrl ctrl reg 1 */
458#define hsmc1_sysr 0x1d1 /* system register */
459#define hsmc1_data 0x1d2 /* data register */
460#define hsmc1_crr 0x1d3 /* refresh register */
461
462/*----------------------------------------------------------------------------+
463| Machine State Register bit definitions.
464+----------------------------------------------------------------------------*/
465#define msr_ape 0x00100000
466#define msr_apa 0x00080000
467#define msr_we 0x00040000
468#define msr_ce 0x00020000
469#define msr_ile 0x00010000
470#define msr_ee 0x00008000
471#define msr_pr 0x00004000
472#define msr_me 0x00001000
473#define msr_de 0x00000200
474#define msr_ir 0x00000020
475#define msr_dr 0x00000010
476#define msr_le 0x00000001
477
478/*----------------------------------------------------------------------------+
479| Used during interrupt processing.
480+----------------------------------------------------------------------------*/
481#define stack_reg_image_size 160
482
483/*----------------------------------------------------------------------------+
484| Function prolog definition and other Metaware (EABI) defines.
485+----------------------------------------------------------------------------*/
486#ifdef MW
487
488#define r0 0
489#define r1 1
490#define r2 2
491#define r3 3
492#define r4 4
493#define r5 5
494#define r6 6
495#define r7 7
496#define r8 8
497#define r9 9
498#define r10 10
499#define r11 11
500#define r12 12
501#define r13 13
502#define r14 14
503#define r15 15
504#define r16 16
505#define r17 17
506#define r18 18
507#define r19 19
508#define r20 20
509#define r21 21
510#define r22 22
511#define r23 23
512#define r24 24
513#define r25 25
514#define r26 26
515#define r27 27
516#define r28 28
517#define r29 29
518#define r30 30
519#define r31 31
520
521#define cr0 0
522#define cr1 1
523#define cr2 2
524#define cr3 3
525#define cr4 4
526#define cr5 5
527#define cr6 6
528#define cr7 7
529
530#define function_prolog(func_name) .text; \
531 .align 2; \
532 .globl func_name; \
533 func_name:
534#define function_epilog(func_name) .type func_name,@function; \
535 .size func_name,.-func_name
536
537#define function_call(func_name) bl func_name
538
539#define stack_frame_min 8
540#define stack_frame_bc 0
541#define stack_frame_lr 4
542#define stack_neg_off 0
543
544#endif
545
546/*----------------------------------------------------------------------------+
547| Function prolog definition and other DIAB (Elf) defines.
548+----------------------------------------------------------------------------*/
549#ifdef ELF_DIAB
550
551fprolog: macro f_name
552 .text
553 .align 2
554 .globl f_name
555f_name:
556 endm
557
558fepilog: macro f_name
559 .type f_name,@function
560 .size f_name,.-f_name
561 endm
562
563#define function_prolog(func_name) fprolog func_name
564#define function_epilog(func_name) fepilog func_name
565#define function_call(func_name) bl func_name
566
567#define stack_frame_min 8
568#define stack_frame_bc 0
569#define stack_frame_lr 4
570#define stack_neg_off 0
571
572#endif
573
574/*----------------------------------------------------------------------------+
575| Function prolog definition and other Xlc (XCOFF) defines.
576+----------------------------------------------------------------------------*/
577#ifdef XCOFF
578
579.machine "403ga"
580
581#define r0 0
582#define r1 1
583#define r2 2
584#define r3 3
585#define r4 4
586#define r5 5
587#define r6 6
588#define r7 7
589#define r8 8
590#define r9 9
591#define r10 10
592#define r11 11
593#define r12 12
594#define r13 13
595#define r14 14
596#define r15 15
597#define r16 16
598#define r17 17
599#define r18 18
600#define r19 19
601#define r20 20
602#define r21 21
603#define r22 22
604#define r23 23
605#define r24 24
606#define r25 25
607#define r26 26
608#define r27 27
609#define r28 28
610#define r29 29
611#define r30 30
612#define r31 31
613
614#define cr0 0
615#define cr1 1
616#define cr2 2
617#define cr3 3
618#define cr4 4
619#define cr5 5
620#define cr6 6
621#define cr7 7
622
623#define function_prolog(func_name) .csect .func_name[PR]; \
624 .globl .func_name[PR]; \
625 func_name:
626
627#define function_epilog(func_name) .toc; \
628 .csect func_name[DS]; \
629 .globl func_name[DS]; \
630 .long .func_name[PR]; \
631 .long TOC[tc0]
632
633#define function_call(func_name) .extern .func_name[PR]; \
634 stw r2,stack_frame_toc(r1); \
635 mfspr r2,sprg0; \
636 bl .func_name[PR]; \
637 lwz r2,stack_frame_toc(r1)
638
639#define stack_frame_min 56
640#define stack_frame_bc 0
641#define stack_frame_lr 8
642#define stack_frame_toc 20
643#define stack_neg_off 276
644
645#endif
646#define function_prolog(func_name) .text; \
647 .align 2; \
648 .globl func_name; \
649 func_name:
650#define function_epilog(func_name) .type func_name,@function; \
651 .size func_name,.-func_name
652
653#define function_call(func_name) bl func_name
654
655/*----------------------------------------------------------------------------+
656| Function prolog definition for GNU
657+----------------------------------------------------------------------------*/
658#ifdef _GNU_TOOL
659
660#define function_prolog(func_name) .globl func_name; \
661 func_name:
662#define function_epilog(func_name)
663
664#endif
diff --git a/arch/ppc/boot/simple/rw4/rw4_init.S b/arch/ppc/boot/simple/rw4/rw4_init.S
deleted file mode 100644
index b1061962e46b..000000000000
--- a/arch/ppc/boot/simple/rw4/rw4_init.S
+++ /dev/null
@@ -1,78 +0,0 @@
1#define VESTA
2#include "ppc_40x.h"
3#
4 .align 2
5 .text
6#
7# added by linguohui
8 .extern initb_ebiu0, initb_config, hdw_init_finish
9 .extern initb_hsmc0, initb_hsmc1, initb_cache
10# end added
11 .globl HdwInit
12#
13HdwInit:
14#
15#-----------------------------------------------------------------------*
16# If we are not executing from the FLASH get out *
17#-----------------------------------------------------------------------*
18# SAW keep this or comment out a la Hawthorne?
19# r3 contains NIP when used with Linux
20# rlwinm r28, r3, 8, 24, 31 # if MSB == 0xFF -> FLASH address
21# cmpwi r28, 0xff
22# bne locn01
23#
24#
25#------------------------------------------------------------------------
26# Init_cpu. Bank registers are setup for the IBM STB.
27#------------------------------------------------------------------------
28#
29# Setup processor core clock to be driven off chip. This is GPI4 bit
30# twenty. Setup Open Drain, Output Select, Three-State Control, and
31# Three-State Select registers.
32#
33
34
35 pb0pesr = 0x054
36 pb0pear = 0x056
37
38 mflr r30
39
40#-----------------------------------------------------------------------------
41# Vectors will be at 0x1F000000
42# Dummy Machine check handler just does RFI before true handler gets installed
43#-----------------------------------------------------------------------------
44#if 1 /* xuwentao added*/
45#ifdef SDRAM16MB
46 lis r10,0x0000
47 addi r10,r10,0x0000
48#else
49 lis r10,0x1F00
50 addi r10,r10,0x0000
51#endif
52
53 mtspr evpr,r10 #EVPR: 0x0 or 0x1f000000 depending
54 isync # on SDRAM memory model used.
55
56 lis r10,0xFFFF # clear PB0_PESR because some
57 ori r10,r10,0xFFFF # transitions from flash,changed by linguohui
58 mtdcr pb0pesr,r10 # to load RAM image via RiscWatch
59 lis r10,0x0000 # cause PB0_PESR machine checks
60 mtdcr pb0pear,r10
61 addis r10,r10,0x0000 # clear the
62 mtxer r10 # XER just in case...
63#endif /* xuwentao*/
64
65 bl initb_ebiu0 # init EBIU
66
67 bl initb_config # config PPC and board
68
69
70
71
72#------------------------------------------------------------------------
73# EVPR setup moved to top of this function.
74#------------------------------------------------------------------------
75#
76 mtlr r30
77 blr
78 .end
diff --git a/arch/ppc/boot/simple/rw4/rw4_init_brd.S b/arch/ppc/boot/simple/rw4/rw4_init_brd.S
deleted file mode 100644
index 386afdaad6c7..000000000000
--- a/arch/ppc/boot/simple/rw4/rw4_init_brd.S
+++ /dev/null
@@ -1,1125 +0,0 @@
1/*----------------------------------------------------------------------------+
2| This source code has been made available to you by IBM on an AS-IS
3| basis. Anyone receiving this source is licensed under IBM
4| copyrights to use it in any way he or she deems fit, including
5| copying it, modifying it, compiling it, and redistributing it either
6| with or without modifications. No license under IBM patents or
7| patent applications is to be implied by the copyright license.
8|
9| Any user of this software should understand that IBM cannot provide
10| technical support for this software and will not be responsible for
11| any consequences resulting from the use of this software.
12|
13| Any person who transfers this source code or any derivative work
14| must include the IBM copyright notice, this paragraph, and the
15| preceding two paragraphs in the transferred software.
16|
17| COPYRIGHT I B M CORPORATION 1997
18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
19+----------------------------------------------------------------------------*/
20/*----------------------------------------------------------------------------+
21| Author: Tony J. Cerreto
22| Component: BSPS
23| File: init_brd.s
24| Purpose: Vesta Evaluation Board initialization subroutines. The following
25| routines are available:
26| 1. INITB_EBIU0: Initialize EBIU0.
27| 2. INITB_CONFIG: Configure board.
28| 3. INITB_HSMC0: Initialize HSMC0 (SDRAM).
29| 4. INITB_HSMC1: Initialize HSMC1 (SDRAM).
30| 5. INITB_CACHE: Initialize Data and Instruction Cache.
31| 6. INITB_DCACHE: Initialize Data Cache.
32| 7. INITB_ICACHE: Initialize Instruction Cache.
33| 8. INITB_GET_CSPD: Get CPU Speed (Bus Speed and Processor Speed)
34|
35| Changes:
36| Date: Author Comment:
37| --------- ------ --------
38| 01-Mar-00 tjc Created
39| 04-Mar-00 jfh Modified CIC_SEL3_VAL to support 1284 (Mux3 & GPIO 21-28)
40| 04-Mar-00 jfh Modified XILINIX Reg 0 to support 1284 (Mux3 & GPIO 21-28)
41| 04-Mar-00 jfh Modified XILINIX Reg 1 to support 1284 (Mux3 & GPIO 21-28)
42| 04-Mar-00 jfh Modified XILINIX Reg 4 to support 1284 (Mux3 & GPIO 21-28)
43| 19-May-00 rlb Relcoated HSMC0 to 0x1F000000 to support 32MB of contiguous
44| SDRAM space. Changed cache ctl regs to reflect this.
45| 22-May-00 tjc Changed initb_get_cspd interface and eliminated
46| initb_get_bspd routines.
47| 26-May-00 tjc Added two nop instructions after all mtxxx/mfxxx
48| instructions due to PPC405 bug.
49+----------------------------------------------------------------------------*/
50#define VESTA
51#include "ppc_40x.h"
52#include "stb.h"
53
54/*----------------------------------------------------------------------------+
55| BOARD CONFIGURATION DEFINES
56+----------------------------------------------------------------------------*/
57#define CBS0_CR_VAL 0x00000002 /* CBS control reg value */
58#define CIC0_CR_VAL 0xD0800448 /* CIC control reg value */
59#define CIC0_SEL3_VAL 0x11500000 /* CIC select 3 reg value */
60#define CIC0_VCR_VAL 0x00631700 /* CIC video cntl reg value */
61
62/*----------------------------------------------------------------------------+
63| EBIU0 BANK REGISTERS DEFINES
64+----------------------------------------------------------------------------*/
65#define EBIU0_BRCRH0_VAL 0x00000000 /* BR High 0 (Extension Reg)*/
66#define EBIU0_BRCRH1_VAL 0x00000000 /* BR High 1 (Extension Reg)*/
67#define EBIU0_BRCRH2_VAL 0x40000000 /* BR High 2 (Extension Reg)*/
68#define EBIU0_BRCRH3_VAL 0x40000000 /* BR High 3 (Extension Reg)*/
69#define EBIU0_BRCRH4_VAL 0x00000000 /* BR High 4 (Extension Reg)*/
70#define EBIU0_BRCRH5_VAL 0x00000000 /* BR High 5 (Extension Reg)*/
71#define EBIU0_BRCRH6_VAL 0x00000000 /* BR High 6 (Extension Reg)*/
72#define EBIU0_BRCRH7_VAL 0x40000000 /* BR High 7 (Extension Reg)*/
73
74#define EBIU0_BRCR0_VAL 0xFC58BFFE /* BR 0: 16 bit Flash 4 MB */
75#define EBIU0_BRCR1_VAL 0xFF00BFFE /* BR 1: Ext Connector 1 MB */
76#if 1
77#define EBIU0_BRCR2_VAL 0x207CFFBE /* BR 2: Xilinx 8 MB */
78 /* twt == 0x3f */
79#else
80#define EBIU0_BRCR2_VAL 0x207CCFBE /* BR 2: Xilinx 8 MB */
81 /* twt == 0x0f */
82#endif
83#define EBIU0_BRCR3_VAL 0x407CBFBE /* BR 3: IDE Drive 8 MB */
84#define EBIU0_BRCR4_VAL 0xFF00BFFF /* BR 4: Disabled. 0 MB */
85#define EBIU0_BRCR5_VAL 0xFF00BFFF /* BR 5: Disabled. 0 MB */
86#define EBIU0_BRCR6_VAL 0xFF00BFFF /* BR 6: Disabled. 0 MB */
87#define EBIU0_BRCR7_VAL 0xCE3F0003 /* BR 7: Line Mode DMA 2 MB */
88
89/*----------------------------------------------------------------------------+
90| GPIO DEFINES
91+----------------------------------------------------------------------------*/
92#define STB_GPIO0_OUTPUT (STB_GPIO0_BASE_ADDRESS+ 0x00)
93#define STB_GPIO0_TC (STB_GPIO0_BASE_ADDRESS+ 0x04)
94#define STB_GPIO0_OS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x08)
95#define STB_GPIO0_OS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x0C)
96#define STB_GPIO0_TS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x10)
97#define STB_GPIO0_TS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x14)
98#define STB_GPIO0_OD (STB_GPIO0_BASE_ADDRESS+ 0x18)
99#define STB_GPIO0_INPUT (STB_GPIO0_BASE_ADDRESS+ 0x1C)
100#define STB_GPIO0_R1 (STB_GPIO0_BASE_ADDRESS+ 0x20)
101#define STB_GPIO0_R2 (STB_GPIO0_BASE_ADDRESS+ 0x24)
102#define STB_GPIO0_R3 (STB_GPIO0_BASE_ADDRESS+ 0x28)
103#define STB_GPIO0_IS_1_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x30)
104#define STB_GPIO0_IS_1_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x34)
105#define STB_GPIO0_IS_2_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x38)
106#define STB_GPIO0_IS_2_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x3C)
107#define STB_GPIO0_IS_3_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x40)
108#define STB_GPIO0_IS_3_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x44)
109#define STB_GPIO0_SS_1 (STB_GPIO0_BASE_ADDRESS+ 0x50)
110#define STB_GPIO0_SS_2 (STB_GPIO0_BASE_ADDRESS+ 0x54)
111#define STB_GPIO0_SS_3 (STB_GPIO0_BASE_ADDRESS+ 0x58)
112
113#define GPIO0_TC_VAL 0x0C020004 /* three-state control val */
114#define GPIO0_OS_0_31_VAL 0x51A00004 /* output select 0-31 val */
115#define GPIO0_OS_32_63_VAL 0x0000002F /* output select 32-63 val */
116#define GPIO0_TS_0_31_VAL 0x51A00000 /* three-state sel 0-31 val*/
117#define GPIO0_TS_32_63_VAL 0x0000000F /* three-state sel 32-63 val*/
118#define GPIO0_OD_VAL 0xC0000004 /* open drain val */
119#define GPIO0_IS_1_0_31_VAL 0x50000151 /* input select 1 0-31 val */
120#define GPIO0_IS_1_32_63_VAL 0x00000000 /* input select 1 32-63 val */
121#define GPIO0_IS_2_0_31_VAL 0x00000000 /* input select 2 0-31 val */
122#define GPIO0_IS_2_32_63_VAL 0x00000000 /* input select 2 32-63 val */
123#define GPIO0_IS_3_0_31_VAL 0x00000440 /* input select 3 0-31 val */
124#define GPIO0_IS_3_32_63_VAL 0x00000000 /* input select 3 32-63 val */
125#define GPIO0_SS_1_VAL 0x00000000 /* sync select 1 val */
126#define GPIO0_SS_2_VAL 0x00000000 /* sync select 2 val */
127#define GPIO0_SS_3_VAL 0x00000000 /* sync select 3 val */
128
129/*----------------------------------------------------------------------------+
130| XILINX DEFINES
131+----------------------------------------------------------------------------*/
132#define STB_XILINX_LED (STB_FPGA_BASE_ADDRESS+ 0x0100)
133#define STB_XILINX1_REG0 (STB_FPGA_BASE_ADDRESS+ 0x40000)
134#define STB_XILINX1_REG1 (STB_FPGA_BASE_ADDRESS+ 0x40002)
135#define STB_XILINX1_REG2 (STB_FPGA_BASE_ADDRESS+ 0x40004)
136#define STB_XILINX1_REG3 (STB_FPGA_BASE_ADDRESS+ 0x40006)
137#define STB_XILINX1_REG4 (STB_FPGA_BASE_ADDRESS+ 0x40008)
138#define STB_XILINX1_REG5 (STB_FPGA_BASE_ADDRESS+ 0x4000A)
139#define STB_XILINX1_REG6 (STB_FPGA_BASE_ADDRESS+ 0x4000C)
140#define STB_XILINX1_ID (STB_FPGA_BASE_ADDRESS+ 0x4000E)
141#define STB_XILINX1_FLUSH (STB_FPGA_BASE_ADDRESS+ 0x4000E)
142#define STB_XILINX2_REG0 (STB_FPGA_BASE_ADDRESS+ 0x80000)
143#define STB_XILINX2_REG1 (STB_FPGA_BASE_ADDRESS+ 0x80002)
144#define STB_XILINX2_REG2 (STB_FPGA_BASE_ADDRESS+ 0x80004)
145
146#define XILINX1_R0_VAL 0x2440 /* Xilinx 1 Register 0 Val */
147#define XILINX1_R1_VAL 0x0025 /* Xilinx 1 Register 1 Val */
148#define XILINX1_R2_VAL 0x0441 /* Xilinx 1 Register 2 Val */
149#define XILINX1_R3_VAL 0x0008 /* Xilinx 1 Register 3 Val */
150#define XILINX1_R4_VAL 0x0100 /* Xilinx 1 Register 4 Val */
151#define XILINX1_R5_VAL 0x6810 /* Xilinx 1 Register 5 Val */
152#define XILINX1_R6_VAL 0x0000 /* Xilinx 1 Register 6 Val */
153#if 0
154#define XILINX2_R0_VAL 0x0008 /* Xilinx 2 Register 0 Val */
155#define XILINX2_R1_VAL 0x0000 /* Xilinx 2 Register 1 Val */
156#else
157#define XILINX2_R0_VAL 0x0018 /* disable IBM IrDA RxD */
158#define XILINX2_R1_VAL 0x0008 /* enable SICC MAX chip */
159#endif
160#define XILINX2_R2_VAL 0x0000 /* Xilinx 2 Register 2 Val */
161
162/*----------------------------------------------------------------------------+
163| HSMC BANK REGISTERS DEFINES
164+----------------------------------------------------------------------------*/
165#ifdef SDRAM16MB
166#define HSMC0_BR0_VAL 0x000D2D55 /* 0x1F000000-007FFFFF R/W */
167#define HSMC0_BR1_VAL 0x008D2D55 /* 0x1F800000-1FFFFFFF R/W */
168#else
169#define HSMC0_BR0_VAL 0x1F0D2D55 /* 0x1F000000-007FFFFF R/W */
170#define HSMC0_BR1_VAL 0x1F8D2D55 /* 0x1F800000-1FFFFFFF R/W */
171#endif
172#define HSMC1_BR0_VAL 0xA00D2D55 /* 0xA0000000-A07FFFFF R/W */
173#define HSMC1_BR1_VAL 0xA08D2D55 /* 0xA0800000-A0FFFFFF R/W */
174
175/*----------------------------------------------------------------------------+
176| CACHE DEFINES
177+----------------------------------------------------------------------------*/
178#define DCACHE_NLINES 128 /* no. D-cache lines */
179#define DCACHE_NBYTES 32 /* no. bytes/ D-cache line */
180#define ICACHE_NLINES 256 /* no. I-cache lines */
181#define ICACHE_NBYTES 32 /* no. bytes/ I-cache line */
182#ifdef SDRAM16MB
183#define DCACHE_ENABLE 0x80000000 /* D-cache regions to enable*/
184#define ICACHE_ENABLE 0x80000001 /* I-cache regions to enable*/
185#else
186#define DCACHE_ENABLE 0x18000000 /* D-cache regions to enable*/
187#define ICACHE_ENABLE 0x18000001 /* I-cache regions to enable*/
188#endif
189
190/*----------------------------------------------------------------------------+
191| CPU CORE SPEED CALCULATION DEFINES
192+----------------------------------------------------------------------------*/
193#define GCS_LCNT 500000 /* CPU speed loop count */
194#define GCS_TROW_BYTES 8 /* no. bytes in table row */
195#define GCS_CTICK_TOL 100 /* allowable clock tick tol */
196#define GCS_NMULT 4 /* no. of core speed mults */
197
198 /*--------------------------------------------------------------------+
199 | No. 13.5Mhz
200 | Clock Ticks
201 | based on a
202 | loop count Bus
203 | of 100,000 Speed
204 +--------------------------------------------------------------------*/
205gcs_lookup_table:
206 .int 50000, 54000000 /* 54.0 Mhz */
207 .int 66667, 40500000 /* 40.5 Mhz */
208 .int 54545, 49500000 /* 49.5 Mhz */
209 .int 46154, 58500000 /* 58.5 Mhz */
210 .int 0, 0 /* end of table flag */
211
212
213/*****************************************************************************+
214| XXXXXXX XXX XXX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX
215| XX X XX XX X XX X XX X XX XX XXX XX XXXX XX
216| XX X XXX XX XX X XX XX XXXX XX XX XX XX
217| XXXX X XX XXXX XXXXX XX XXXX XX XX XX
218| XX X XXX XX XX X XX XX XX XXX XXXXXX XX
219| XX X XX XX XX XX X XX XX XX XX XX XX XX XX
220| XXXXXXX XXX XXX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX
221+*****************************************************************************/
222/******************************************************************************
223|
224| Routine: INITB_EBIU0.
225|
226| Purpose: Initialize all the EBIU0 Bank Registers
227| Parameters: None.
228| Returns: None.
229|
230******************************************************************************/
231 function_prolog(initb_ebiu0)
232 /*--------------------------------------------------------------------+
233 | Set EBIU0 Bank 0
234 +--------------------------------------------------------------------*/
235 lis r10,EBIU0_BRCR0_VAL@h
236 ori r10,r10,EBIU0_BRCR0_VAL@l
237 mtdcr ebiu0_brcr0,r10
238 lis r10,EBIU0_BRCRH0_VAL@h
239 ori r10,r10,EBIU0_BRCRH0_VAL@l
240 mtdcr ebiu0_brcrh0,r10
241
242 /*--------------------------------------------------------------------+
243 | Set EBIU0 Bank 1
244 +--------------------------------------------------------------------*/
245 lis r10,EBIU0_BRCR1_VAL@h
246 ori r10,r10,EBIU0_BRCR1_VAL@l
247 mtdcr ebiu0_brcr1,r10
248 lis r10,EBIU0_BRCRH1_VAL@h
249 ori r10,r10,EBIU0_BRCRH1_VAL@l
250 mtdcr ebiu0_brcrh1,r10
251
252 /*--------------------------------------------------------------------+
253 | Set EBIU0 Bank 2
254 +--------------------------------------------------------------------*/
255 lis r10,EBIU0_BRCR2_VAL@h
256 ori r10,r10,EBIU0_BRCR2_VAL@l
257 mtdcr ebiu0_brcr2,r10
258 lis r10,EBIU0_BRCRH2_VAL@h
259 ori r10,r10,EBIU0_BRCRH2_VAL@l
260 mtdcr ebiu0_brcrh2,r10
261
262 /*--------------------------------------------------------------------+
263 | Set EBIU0 Bank 3
264 +--------------------------------------------------------------------*/
265 lis r10,EBIU0_BRCR3_VAL@h
266 ori r10,r10,EBIU0_BRCR3_VAL@l
267 mtdcr ebiu0_brcr3,r10
268 lis r10,EBIU0_BRCRH3_VAL@h
269 ori r10,r10,EBIU0_BRCRH3_VAL@l
270 mtdcr ebiu0_brcrh3,r10
271
272 /*--------------------------------------------------------------------+
273 | Set EBIU0 Bank 4
274 +--------------------------------------------------------------------*/
275 lis r10,EBIU0_BRCR4_VAL@h
276 ori r10,r10,EBIU0_BRCR4_VAL@l
277 mtdcr ebiu0_brcr4,r10
278 lis r10,EBIU0_BRCRH4_VAL@h
279 ori r10,r10,EBIU0_BRCRH4_VAL@l
280 mtdcr ebiu0_brcrh4,r10
281
282 /*--------------------------------------------------------------------+
283 | Set EBIU0 Bank 5
284 +--------------------------------------------------------------------*/
285 lis r10,EBIU0_BRCR5_VAL@h
286 ori r10,r10,EBIU0_BRCR5_VAL@l
287 mtdcr ebiu0_brcr5,r10
288 lis r10,EBIU0_BRCRH5_VAL@h
289 ori r10,r10,EBIU0_BRCRH5_VAL@l
290 mtdcr ebiu0_brcrh5,r10
291
292 /*--------------------------------------------------------------------+
293 | Set EBIU0 Bank 6
294 +--------------------------------------------------------------------*/
295 lis r10,EBIU0_BRCR6_VAL@h
296 ori r10,r10,EBIU0_BRCR6_VAL@l
297 mtdcr ebiu0_brcr6,r10
298 lis r10,EBIU0_BRCRH6_VAL@h
299 ori r10,r10,EBIU0_BRCRH6_VAL@l
300 mtdcr ebiu0_brcrh6,r10
301
302 /*--------------------------------------------------------------------+
303 | Set EBIU0 Bank 7
304 +--------------------------------------------------------------------*/
305 lis r10,EBIU0_BRCR7_VAL@h
306 ori r10,r10,EBIU0_BRCR7_VAL@l
307 mtdcr ebiu0_brcr7,r10
308 lis r10,EBIU0_BRCRH7_VAL@h
309 ori r10,r10,EBIU0_BRCRH7_VAL@l
310 mtdcr ebiu0_brcrh7,r10
311
312 blr
313 function_epilog(initb_ebiu0)
314
315
316/******************************************************************************
317|
318| Routine: INITB_CONFIG
319|
320| Purpose: Configure the Vesta Evaluation Board. The following items
321| will be configured:
322| 1. Cross-Bar Switch.
323| 2. Chip Interconnect.
324| 3. Clear/reset key PPC registers.
325| 4. Xilinx and GPIO Registers.
326|
327| Returns: None.
328|
329******************************************************************************/
330 function_prolog(initb_config)
331 /*--------------------------------------------------------------------+
332 | Init CROSS-BAR SWITCH
333 +--------------------------------------------------------------------*/
334 lis r10,CBS0_CR_VAL@h /* r10 <- CBS Cntl Reg val */
335 ori r10,r10,CBS0_CR_VAL@l
336 mtdcr cbs0_cr,r10
337
338 /*--------------------------------------------------------------------+
339 | Init Chip-Interconnect (CIC) Registers
340 +--------------------------------------------------------------------*/
341 lis r10,CIC0_CR_VAL@h /* r10 <- CIC Cntl Reg val */
342 ori r10,r10,CIC0_CR_VAL@l
343 mtdcr cic0_cr,r10
344
345 lis r10,CIC0_SEL3_VAL@h /* r10 <- CIC SEL3 Reg val */
346 ori r10,r10,CIC0_SEL3_VAL@l
347 mtdcr cic0_sel3,r10
348
349 lis r10,CIC0_VCR_VAL@h /* r10 <- CIC Vid C-Reg val */
350 ori r10,r10,CIC0_VCR_VAL@l
351 mtdcr cic0_vcr,r10
352
353 /*--------------------------------------------------------------------+
354 | Clear SGR and DCWR
355 +--------------------------------------------------------------------*/
356 li r10,0x0000
357 mtspr sgr,r10
358 mtspr dcwr,r10
359
360 /*--------------------------------------------------------------------+
361 | Clear/set up some machine state registers.
362 +--------------------------------------------------------------------*/
363 li r10,0x0000 /* r10 <- 0 */
364 mtdcr ebiu0_besr,r10 /* clr Bus Err Syndrome Reg */
365 mtspr esr,r10 /* clr Exceptn Syndrome Reg */
366 mttcr r10 /* timer control register */
367
368 mtdcr uic0_er,r10 /* disable all interrupts */
369
370 /* UIC_IIC0 | UIC_IIC1 | UIC_U0 | UIC_IR_RCV | UIC_IR_XMIT */
371 lis r10, 0x00600e00@h
372 ori r10,r10,0x00600e00@l
373 mtdcr uic0_pr,r10
374
375 li r10,0x00000020 /* UIC_EIR1 */
376 mtdcr uic0_tr,r10
377
378 lis r10,0xFFFF /* r10 <- 0xFFFFFFFF */
379 ori r10,r10,0xFFFF /* */
380 mtdbsr r10 /* clear/reset the dbsr */
381 mtdcr uic0_sr,r10 /* clear pending interrupts */
382
383 li r10,0x1000 /* set Machine Exception bit*/
384 oris r10,r10,0x2 /* set Criticl Exception bit*/
385 mtmsr r10 /* change MSR */
386
387 /*--------------------------------------------------------------------+
388 | Clear XER.
389 +--------------------------------------------------------------------*/
390 li r10,0x0000
391 mtxer r10
392
393 /*--------------------------------------------------------------------+
394 | Init GPIO0 Registers
395 +--------------------------------------------------------------------*/
396 lis r10, STB_GPIO0_TC@h /* Three-state control */
397 ori r10,r10,STB_GPIO0_TC@l
398 lis r11, GPIO0_TC_VAL@h
399 ori r11,r11,GPIO0_TC_VAL@l
400 stw r11,0(r10)
401
402 lis r10, STB_GPIO0_OS_0_31@h /* output select 0-31 */
403 ori r10,r10,STB_GPIO0_OS_0_31@l
404 lis r11, GPIO0_OS_0_31_VAL@h
405 ori r11,r11,GPIO0_OS_0_31_VAL@l
406 stw r11,0(r10)
407
408 lis r10, STB_GPIO0_OS_32_63@h /* output select 32-63 */
409 ori r10,r10,STB_GPIO0_OS_32_63@l
410 lis r11, GPIO0_OS_32_63_VAL@h
411 ori r11,r11,GPIO0_OS_32_63_VAL@l
412 stw r11,0(r10)
413
414 lis r10, STB_GPIO0_TS_0_31@h /* three-state select 0-31 */
415 ori r10,r10,STB_GPIO0_TS_0_31@l
416 lis r11, GPIO0_TS_0_31_VAL@h
417 ori r11,r11,GPIO0_TS_0_31_VAL@l
418 stw r11,0(r10)
419
420 lis r10, STB_GPIO0_TS_32_63@h /* three-state select 32-63 */
421 ori r10,r10,STB_GPIO0_TS_32_63@l
422 lis r11, GPIO0_TS_32_63_VAL@h
423 ori r11,r11,GPIO0_TS_32_63_VAL@l
424 stw r11,0(r10)
425
426 lis r10, STB_GPIO0_OD@h /* open drain */
427 ori r10,r10,STB_GPIO0_OD@l
428 lis r11, GPIO0_OD_VAL@h
429 ori r11,r11,GPIO0_OD_VAL@l
430 stw r11,0(r10)
431
432 lis r10, STB_GPIO0_IS_1_0_31@h /* input select 1, 0-31 */
433 ori r10,r10,STB_GPIO0_IS_1_0_31@l
434 lis r11, GPIO0_IS_1_0_31_VAL@h
435 ori r11,r11,GPIO0_IS_1_0_31_VAL@l
436 stw r11,0(r10)
437
438 lis r10, STB_GPIO0_IS_1_32_63@h /* input select 1, 32-63 */
439 ori r10,r10,STB_GPIO0_IS_1_32_63@l
440 lis r11, GPIO0_IS_1_32_63_VAL@h
441 ori r11,r11,GPIO0_IS_1_32_63_VAL@l
442 stw r11,0(r10)
443
444 lis r10, STB_GPIO0_IS_2_0_31@h /* input select 2, 0-31 */
445 ori r10,r10,STB_GPIO0_IS_2_0_31@l
446 lis r11, GPIO0_IS_2_0_31_VAL@h
447 ori r11,r11,GPIO0_IS_2_0_31_VAL@l
448 stw r11,0(r10)
449
450 lis r10, STB_GPIO0_IS_2_32_63@h /* input select 2, 32-63 */
451 ori r10,r10,STB_GPIO0_IS_2_32_63@l
452 lis r11, GPIO0_IS_2_32_63_VAL@h
453 ori r11,r11,GPIO0_IS_2_32_63_VAL@l
454 stw r11,0(r10)
455
456 lis r10, STB_GPIO0_IS_3_0_31@h /* input select 3, 0-31 */
457 ori r10,r10,STB_GPIO0_IS_3_0_31@l
458 lis r11, GPIO0_IS_3_0_31_VAL@h
459 ori r11,r11,GPIO0_IS_3_0_31_VAL@l
460 stw r11,0(r10)
461
462 lis r10, STB_GPIO0_IS_3_32_63@h /* input select 3, 32-63 */
463 ori r10,r10,STB_GPIO0_IS_3_32_63@l
464 lis r11, GPIO0_IS_3_32_63_VAL@h
465 ori r11,r11,GPIO0_IS_3_32_63_VAL@l
466 stw r11,0(r10)
467
468 lis r10, STB_GPIO0_SS_1@h /* sync select 1 */
469 ori r10,r10,STB_GPIO0_SS_1@l
470 lis r11, GPIO0_SS_1_VAL@h
471 ori r11,r11,GPIO0_SS_1_VAL@l
472 stw r11,0(r10)
473
474 lis r10, STB_GPIO0_SS_2@h /* sync select 2 */
475 ori r10,r10,STB_GPIO0_SS_2@l
476 lis r11, GPIO0_SS_2_VAL@h
477 ori r11,r11,GPIO0_SS_2_VAL@l
478 stw r11,0(r10)
479
480 lis r10, STB_GPIO0_SS_3@h /* sync select 3 */
481 ori r10,r10,STB_GPIO0_SS_3@l
482 lis r11, GPIO0_SS_3_VAL@h
483 ori r11,r11,GPIO0_SS_3_VAL@l
484 stw r11,0(r10)
485
486 /*--------------------------------------------------------------------+
487 | Init Xilinx #1 Registers
488 +--------------------------------------------------------------------*/
489 lis r10, STB_XILINX1_REG0@h /* init Xilinx1 Reg 0 */
490 ori r10,r10,STB_XILINX1_REG0@l
491 li r11,XILINX1_R0_VAL
492 sth r11,0(r10)
493
494 lis r10, STB_XILINX1_REG1@h /* init Xilinx1 Reg 1 */
495 ori r10,r10,STB_XILINX1_REG1@l
496 li r11,XILINX1_R1_VAL
497 sth r11,0(r10)
498
499 lis r10, STB_XILINX1_REG2@h /* init Xilinx1 Reg 2 */
500 ori r10,r10,STB_XILINX1_REG2@l
501 li r11,XILINX1_R2_VAL
502 sth r11,0(r10)
503
504 lis r10, STB_XILINX1_REG3@h /* init Xilinx1 Reg 3 */
505 ori r10,r10,STB_XILINX1_REG3@l
506 li r11,XILINX1_R3_VAL
507 sth r11,0(r10)
508
509 lis r10, STB_XILINX1_REG4@h /* init Xilinx1 Reg 4 */
510 ori r10,r10,STB_XILINX1_REG4@l
511 li r11,XILINX1_R4_VAL
512 sth r11,0(r10)
513
514 lis r10, STB_XILINX1_REG5@h /* init Xilinx1 Reg 5 */
515 ori r10,r10,STB_XILINX1_REG5@l
516 li r11,XILINX1_R5_VAL
517 sth r11,0(r10)
518
519 lis r10, STB_XILINX1_REG6@h /* init Xilinx1 Reg 6 */
520 ori r10,r10,STB_XILINX1_REG6@l
521 li r11,XILINX1_R6_VAL
522 sth r11,0(r10)
523
524 lis r10, STB_XILINX1_FLUSH@h /* latch registers in Xilinx*/
525 ori r10,r10,STB_XILINX1_FLUSH@l
526 li r11,0x0000
527 sth r11,0(r10)
528
529 /*--------------------------------------------------------------------+
530 | Init Xilinx #2 Registers
531 +--------------------------------------------------------------------*/
532 lis r10, STB_XILINX2_REG0@h /* init Xilinx2 Reg 0 */
533 ori r10,r10,STB_XILINX2_REG0@l
534 li r11,XILINX2_R0_VAL
535 sth r11,0(r10)
536
537 lis r10, STB_XILINX2_REG1@h /* init Xilinx2 Reg 1 */
538 ori r10,r10,STB_XILINX2_REG1@l
539 li r11,XILINX2_R1_VAL
540 sth r11,0(r10)
541
542 lis r10, STB_XILINX2_REG2@h /* init Xilinx2 Reg 2 */
543 ori r10,r10,STB_XILINX2_REG2@l
544 li r11,XILINX2_R2_VAL
545 sth r11,0(r10)
546
547 blr
548 function_epilog(initb_config)
549
550
551/******************************************************************************
552|
553| Routine: INITB_HSMC0.
554|
555| Purpose: Initialize the HSMC0 Registers for SDRAM
556| Parameters: None.
557| Returns: R3 = 0: Successful
558| = -1: Unsuccessful, SDRAM did not reset properly.
559|
560******************************************************************************/
561 function_prolog(initb_hsmc0)
562 mflr r0 /* Save return addr */
563
564 /*--------------------------------------------------------------------+
565 | Set Global SDRAM Controller to recommended default
566 +--------------------------------------------------------------------*/
567 lis r10,0x6C00
568 ori r10,r10,0x0000
569 mtdcr hsmc0_gr,r10
570
571 /*--------------------------------------------------------------------+
572 | Set HSMC0 Data Register to recommended default
573 +--------------------------------------------------------------------*/
574 lis r10,0x0037
575 ori r10,r10,0x0000
576 mtdcr hsmc0_data,r10
577
578 /*--------------------------------------------------------------------+
579 | Init HSMC0 Bank Register 0
580 +--------------------------------------------------------------------*/
581 lis r10,HSMC0_BR0_VAL@h
582 ori r10,r10,HSMC0_BR0_VAL@l
583 mtdcr hsmc0_br0,r10
584
585 /*--------------------------------------------------------------------+
586 | Init HSMC0 Bank Register 1
587 +--------------------------------------------------------------------*/
588 lis r10,HSMC0_BR1_VAL@h
589 ori r10,r10,HSMC0_BR1_VAL@l
590 mtdcr hsmc0_br1,r10
591
592 /*--------------------------------------------------------------------+
593 | Set HSMC0 Control Reg 0
594 +--------------------------------------------------------------------*/
595 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
596 ori r10,r10,0x0000
597 mtdcr hsmc0_cr0,r10
598 li r3,0x0000
599 bl hsmc_cr_wait /* wait for op completion */
600 cmpwi cr0,r3,0x0000
601 bne cr0,hsmc0_err
602
603 lis r10,0x8078 /* AUTO-REFRESH */
604 ori r10,r10,0x0000
605 mtdcr hsmc0_cr0,r10
606 li r3,0x0000
607 bl hsmc_cr_wait /* wait for op completion */
608 cmpwi cr0,r3,0x0000
609 bne cr0,hsmc0_err
610
611 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
612 ori r10,r10,0x8000
613 mtdcr hsmc0_cr0,r10
614 li r3,0x0000
615 bl hsmc_cr_wait /* wait for op completion */
616 cmpwi cr0,r3,0x0000
617 bne hsmc0_err
618
619 /*--------------------------------------------------------------------+
620 | Set HSMC0 Control Reg 1
621 +--------------------------------------------------------------------*/
622 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
623 ori r10,r10,0x0000
624 mtdcr hsmc0_cr1,r10
625 li r3,0x0001
626 bl hsmc_cr_wait /* wait for op completion */
627 cmpwi cr0,r3,0x0000
628 bne cr0,hsmc0_err
629
630 lis r10,0x8078 /* AUTO-REFRESH */
631 ori r10,r10,0x0000
632 mtdcr hsmc0_cr1,r10
633 li r3,0x0001
634 bl hsmc_cr_wait /* wait for op completion */
635 cmpwi cr0,r3,0x0000
636 bne cr0,hsmc0_err
637
638 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
639 ori r10,r10,0x8000
640 mtdcr hsmc0_cr1,r10
641 li r3,0x0001
642 bl hsmc_cr_wait /* wait for op completion */
643 cmpwi cr0,r3,0x0000
644 bne cr0,hsmc0_err
645
646 /*--------------------------------------------------------------------+
647 | Set HSMC0 Refresh Register
648 +--------------------------------------------------------------------*/
649 lis r10,0x0FE1
650 ori r10,r10,0x0000
651 mtdcr hsmc0_crr,r10
652 li r3,0
653
654hsmc0_err:
655 mtlr r0
656 blr
657 function_epilog(initb_hsmc0)
658
659
660/******************************************************************************
661|
662| Routine: INITB_HSMC1.
663|
664| Purpose: Initialize the HSMC1 Registers for SDRAM
665| Parameters: None.
666| Returns: R3 = 0: Successful
667| = -1: Unsuccessful, SDRAM did not reset properly.
668|
669******************************************************************************/
670 function_prolog(initb_hsmc1)
671 mflr r0 /* Save return addr */
672
673 /*--------------------------------------------------------------------+
674 | Set Global SDRAM Controller to recommended default
675 +--------------------------------------------------------------------*/
676 lis r10,0x6C00
677 ori r10,r10,0x0000
678 mtdcr hsmc1_gr,r10
679
680 /*--------------------------------------------------------------------+
681 | Set HSMC1 Data Register to recommended default
682 +--------------------------------------------------------------------*/
683 lis r10,0x0037
684 ori r10,r10,0x0000
685 mtdcr hsmc1_data,r10
686
687 /*--------------------------------------------------------------------+
688 | Init HSMC1 Bank Register 0
689 +--------------------------------------------------------------------*/
690 lis r10,HSMC1_BR0_VAL@h
691 ori r10,r10,HSMC1_BR0_VAL@l
692 mtdcr hsmc1_br0,r10
693
694 /*--------------------------------------------------------------------+
695 | Init HSMC1 Bank Register 1
696 +--------------------------------------------------------------------*/
697 lis r10,HSMC1_BR1_VAL@h
698 ori r10,r10,HSMC1_BR1_VAL@l
699 mtdcr hsmc1_br1,r10
700
701 /*--------------------------------------------------------------------+
702 | Set HSMC1 Control Reg 0
703 +--------------------------------------------------------------------*/
704 lis r10,0x8077 /* PRECHARGE ALL DEVICE BANKS */
705 ori r10,r10,0x0000
706 mtdcr hsmc1_cr0,r10
707 li r3,0x0002
708 bl hsmc_cr_wait /* wait for operation completion */
709 cmpwi cr0,r3,0x0000
710 bne hsmc1_err
711
712 lis r10,0x8078 /* AUTO-REFRESH */
713 ori r10,r10,0x0000
714 mtdcr hsmc1_cr0,r10
715 li r3,0x0002
716 bl hsmc_cr_wait /* wait for operation completion */
717 cmpwi cr0,r3,0x0000
718 bne hsmc1_err
719
720 lis r10,0x8070 /* PROGRAM MODE W/DATA REG VALUE */
721 ori r10,r10,0x8000
722 mtdcr hsmc1_cr0,r10
723 li r3,0x0002
724 bl hsmc_cr_wait /* wait for operation completion */
725 cmpwi cr0,r3,0x0000
726 bne hsmc1_err
727
728 /*--------------------------------------------------------------------+
729 | Set HSMC1 Control Reg 1
730 +--------------------------------------------------------------------*/
731 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */
732 ori r10,r10,0x0000
733 mtdcr hsmc1_cr1,r10
734 li r3,0x0003
735 bl hsmc_cr_wait /* wait for op completion */
736 cmpwi cr0,r3,0x0000
737 bne hsmc1_err
738
739 lis r10,0x8078 /* AUTO-REFRESH */
740 ori r10,r10,0x0000
741 mtdcr hsmc1_cr1,r10
742 li r3,0x0003
743 bl hsmc_cr_wait /* wait for op completion */
744 cmpwi cr0,r3,0x0000
745 bne hsmc1_err
746
747 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */
748 ori r10,r10,0x8000
749 mtdcr hsmc1_cr1,r10
750 li r3,0x0003
751 bl hsmc_cr_wait /* wait for op completion */
752 cmpwi cr0,r3,0x0000
753 bne hsmc1_err
754
755 /*--------------------------------------------------------------------+
756 | Set HSMC1 Refresh Register
757 +--------------------------------------------------------------------*/
758 lis r10,0x0FE1
759 ori r10,r10,0x0000
760 mtdcr hsmc1_crr,r10
761 xor r3,r3,r3
762
763hsmc1_err:
764 mtlr r0
765 blr
766 function_epilog(initb_hsmc1)
767
768
769/******************************************************************************
770|
771| Routine: INITB_CACHE
772|
773| Purpose: This routine will enable Data and Instruction Cache.
774| The Data Cache is an 8K two-way set associative and the
775| Instruction Cache is an 16K two-way set associative cache.
776|
777| Parameters: None.
778|
779| Returns: None.
780|
781******************************************************************************/
782 function_prolog(initb_cache)
783 mflr r0 /* Save return addr */
784
785 bl initb_Dcache /* enable D-Cache */
786 bl initb_Icache /* enable I-Cache */
787
788 mtlr r0
789 blr
790 function_epilog(initb_cache)
791
792
793/******************************************************************************
794|
795| Routine: INITB_DCACHE
796|
797| Purpose: This routine will invalidate all data in the Data Cache and
798| then enable D-Cache. If cache is enabled already, the D-Cache
799| will be flushed before the data is invalidated.
800|
801| Parameters: None.
802|
803| Returns: None.
804|
805******************************************************************************/
806 function_prolog(initb_Dcache)
807 /*--------------------------------------------------------------------+
808 | Flush Data Cache if enabled
809 +--------------------------------------------------------------------*/
810 mfdccr r10 /* r10 <- DCCR */
811 isync /* ensure prev insts done */
812 cmpwi r10,0x00
813 beq ic_dcinv /* D-cache off, invalidate */
814
815 /*--------------------------------------------------------------------+
816 | Data Cache enabled, force known memory addresses to be Cached
817 +--------------------------------------------------------------------*/
818 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */
819 andis. r10,r10,0xFFF0
820 li r11,DCACHE_NLINES /* r11 <- # A-way addresses */
821 addi r11,r11,DCACHE_NLINES /* r11 <- # B-way addresses */
822 mtctr r11 /* set loop counter */
823
824ic_dcload:
825 lwz r12,0(r10) /* force cache of address */
826 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */
827 bdnz ic_dcload
828 sync /* ensure prev insts done */
829 isync
830
831 /*--------------------------------------------------------------------+
832 | Flush the known memory addresses from Cache
833 +--------------------------------------------------------------------*/
834 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */
835 andis. r10,r10,0xFFF0
836 mtctr r11 /* set loop counter */
837
838ic_dcflush:
839 dcbf 0,r10 /* flush D-cache line */
840 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */
841 bdnz ic_dcflush
842 sync /* ensure prev insts done */
843 isync
844
845 /*--------------------------------------------------------------------+
846 | Disable then invalidate Data Cache
847 +--------------------------------------------------------------------*/
848 li r10,0 /* r10 <- 0 */
849 mtdccr r10 /* disable the D-Cache */
850 isync /* ensure prev insts done */
851
852ic_dcinv:
853 li r10,0 /* r10 <- line address */
854 li r11,DCACHE_NLINES /* r11 <- # lines in cache */
855 mtctr r11 /* set loop counter */
856
857ic_dcloop:
858 dccci 0,r10 /* invalidate A/B cache lns */
859 addi r10,r10,DCACHE_NBYTES /* bump to next line */
860 bdnz ic_dcloop
861 sync /* ensure prev insts done */
862 isync
863
864 /*--------------------------------------------------------------------+
865 | Enable Data Cache
866 +--------------------------------------------------------------------*/
867 lis r10,DCACHE_ENABLE@h /* r10 <- D-cache enable msk*/
868 ori r10,r10,DCACHE_ENABLE@l
869 mtdccr r10
870 sync /* ensure prev insts done */
871 isync
872
873 blr
874 function_epilog(initb_Dcache)
875
876
877/******************************************************************************
878|
879| Routine: INITB_ICACHE
880|
881| Purpose: This routine will invalidate all data in the Instruction
882| Cache then enable I-Cache.
883|
884| Parameters: None.
885|
886| Returns: None.
887|
888******************************************************************************/
889 function_prolog(initb_Icache)
890 /*--------------------------------------------------------------------+
891 | Invalidate Instruction Cache
892 +--------------------------------------------------------------------*/
893 li r10,0 /* r10 <- lines address */
894 iccci 0,r10 /* invalidate all I-cache */
895 sync /* ensure prev insts done */
896 isync
897
898 /*--------------------------------------------------------------------+
899 | Enable Instruction Cache
900 +--------------------------------------------------------------------*/
901 lis r10,ICACHE_ENABLE@h /* r10 <- I-cache enable msk*/
902 ori r10,r10,ICACHE_ENABLE@l
903 mticcr r10
904 sync /* ensure prev insts done */
905 isync
906
907 blr
908 function_epilog(initb_Icache)
909
910#if 0
911/******************************************************************************
912|
913| Routine: INITB_GET_CSPD
914|
915| Purpose: Determine the CPU Core Speed. The 13.5 Mhz Time Base
916| Counter (TBC) is used to measure a conditional branch
917| instruction.
918|
919| Parameters: R3 = Address of Bus Speed
920| R4 = Address of Core Speed
921|
922| Returns: (R3) = >0: Bus Speed.
923| 0: Bus Speed not found in Look-Up Table.
924| (R4) = >0: Core Speed.
925| 0: Core Speed not found in Look-Up Table.
926|
927| Note: 1. This routine assumes the bdnz branch instruction takes
928| two instruction cycles to complete.
929| 2. This routine must be called before interrupts are enabled.
930|
931******************************************************************************/
932 function_prolog(initb_get_cspd)
933 mflr r0 /* Save return address */
934 /*--------------------------------------------------------------------+
935 | Set-up timed loop
936 +--------------------------------------------------------------------*/
937 lis r9,gcs_time_loop@h /* r9 <- addr loop instr */
938 ori r9,r9,gcs_time_loop@l
939 lis r10,GCS_LCNT@h /* r10 <- loop count */
940 ori r10,r10,GCS_LCNT@l
941 mtctr r10 /* ctr <- loop count */
942 lis r11,STB_TIMERS_TBC@h /* r11 <- TBC register addr */
943 ori r11,r11,STB_TIMERS_TBC@l
944 li r12,0 /* r12 <- 0 */
945
946 /*--------------------------------------------------------------------+
947 | Cache timed-loop instruction
948 +--------------------------------------------------------------------*/
949 icbt 0,r9
950 sync
951 isync
952
953 /*--------------------------------------------------------------------+
954 | Get number of 13.5 Mhz cycles to execute time-loop
955 +--------------------------------------------------------------------*/
956 stw r12,0(r11) /* reset TBC */
957gcs_time_loop:
958 bdnz+ gcs_time_loop /* force branch pred taken */
959 lwz r5,0(r11) /* r5 <- num 13.5 Mhz ticks */
960 li r6,5 /* LUT based on 1/5th the...*/
961 divw r5,r5,r6 /*..loop count used */
962 sync
963 isync
964
965 /*--------------------------------------------------------------------+
966 | Look-up core speed based on TBC value
967 +--------------------------------------------------------------------*/
968 lis r6,gcs_lookup_table@h /* r6 <- pts at core spd LUT*/
969 ori r6,r6,gcs_lookup_table@l
970 bl gcs_cspd_lookup /* find core speed in LUT */
971
972 mtlr r0 /* set return address */
973 blr
974 function_epilog(initb_get_cspd)
975
976#endif
977/*****************************************************************************+
978| XXXX XX XX XXXXXX XXXXXXX XXXXXX XX XX XX XXXX
979| XX XXX XX X XX X XX X XX XX XXX XX XXXX XX
980| XX XXXX XX XX XX X XX XX XXXX XX XX XX XX
981| XX XX XXXX XX XXXX XXXXX XX XXXX XX XX XX
982| XX XX XXX XX XX X XX XX XX XXX XXXXXX XX
983| XX XX XX XX XX X XX XX XX XX XX XX XX XX
984| XXXX XX XX XXXX XXXXXXX XXX XX XX XX XX XX XXXXXXX
985+*****************************************************************************/
986/******************************************************************************
987|
988| Routine: HSMC_CR_WAIT
989|
990| Purpose: Wait for the HSMC Control Register (bits 12-16) to be reset
991| after an auto-refresh, pre-charge or program mode register
992| command execution.
993|
994| Parameters: R3 = HSMC Control Register ID.
995| 0: HSMC0 CR0
996| 1: HSMC0 CR1
997| 2: HSMC1 CR0
998| 3: HSMC1 CR1
999|
1000| Returns: R3 = 0: Successful
1001| -1: Unsuccessful
1002|
1003******************************************************************************/
1004hsmc_cr_wait:
1005
1006 li r11,10 /* r11 <- retry counter */
1007 mtctr r11 /* set retry counter */
1008 mr r11,r3 /* r11 <- HSMC CR reg id */
1009
1010hsmc_cr_rep:
1011 bdz hsmc_cr_err /* branch if max retries hit*/
1012
1013 /*--------------------------------------------------------------------+
1014 | GET HSMCx_CRx value based on HSMC Control Register ID
1015 +--------------------------------------------------------------------*/
1016try_hsmc0_cr0: /* CHECK IF ID=HSMC0 CR0 REG*/
1017 cmpwi cr0,r11,0x0000
1018 bne cr0,try_hsmc0_cr1
1019 mfdcr r10,hsmc0_cr0 /* r11 <- HSMC0 CR0 value */
1020 b hsmc_cr_read
1021
1022try_hsmc0_cr1: /* CHECK IF ID=HSMC0 CR1 REG*/
1023 cmpwi cr0,r11,0x0001
1024 bne cr0,try_hsmc1_cr0
1025 mfdcr r10,hsmc0_cr1 /* r10 <- HSMC0 CR1 value */
1026 b hsmc_cr_read
1027
1028try_hsmc1_cr0: /* CHECK IF ID=HSMC1 CR0 REG*/
1029 cmpwi cr0,r11,0x0002
1030 bne cr0,try_hsmc1_cr1
1031 mfdcr r10,hsmc1_cr0 /* r10 <- HSMC1 CR0 value */
1032 b hsmc_cr_read
1033
1034try_hsmc1_cr1: /* CHECK IF ID=HSMC1 CR1 REG*/
1035 cmpwi cr0,r11,0x0003
1036 bne cr0,hsmc_cr_err
1037 mfdcr r10,hsmc1_cr1 /* r10 <- HSMC1 CR1 value */
1038
1039 /*--------------------------------------------------------------------+
1040 | Check if HSMC CR register was reset after command execution
1041 +--------------------------------------------------------------------*/
1042hsmc_cr_read:
1043 lis r12,0x000F /* create "AND" mask */
1044 ori r12,r12,0x8000
1045 and. r10,r10,r12 /* r10 <- HSMC CR bits 12-16*/
1046 bne cr0,hsmc_cr_rep /* wait for bits to reset */
1047 li r3,0 /* set return code = success*/
1048 b hsmc_cr_done
1049
1050hsmc_cr_err: /* ERROR: SDRAM didn't reset*/
1051 li r3,-1 /* set RC=unsuccessful */
1052
1053hsmc_cr_done:
1054 blr
1055
1056#if 0
1057/******************************************************************************
1058|
1059| Routine: GCS_CSPD_LOOKUP
1060|
1061| Purpose: Uses the number of 13.5 Mhz clock ticks found after executing
1062| the branch instruction time loop to look-up the CPU Core Speed
1063| in the Core Speed Look-up Table.
1064|
1065| Parameters: R3 = Address of Bus Speed
1066| R4 = Address of Core Speed
1067| R5 = Number of 13.5 Mhz clock ticks found in time loop.
1068| R6 = Pointer to Core-Speed Look-Up Table
1069|
1070| Returns: (R3) = >0: Bus Speed.
1071| 0: Bus Speed not found in Look-Up Table.
1072| (R4) = >0: Core Speed.
1073| 0: Core Speed not found in Look-Up Table.
1074|
1075| Note: Core Speed = Bus Speed * Mult Factor (1-4x).
1076|
1077******************************************************************************/
1078gcs_cspd_lookup:
1079
1080 li r9,1 /* r9 <- core speed mult */
1081 /*--------------------------------------------------------------------+
1082 | Get theoritical number 13.5 Mhz ticks for a given Bus Speed from
1083 | Look-up Table. Check all mult factors to determine if calculated
1084 | value matches theoretical value (within a tolerance).
1085 +--------------------------------------------------------------------*/
1086gcs_cspd_loop:
1087 lwz r10,0(r6) /* r10 <- no. ticks from LUT*/
1088 divw r10,r10,r9 /* r10 <- div mult (1-4x) */
1089 subi r11,r10,GCS_CTICK_TOL /* r11 <- no. tks low range */
1090 addi r12,r10,GCS_CTICK_TOL /* r12 <- no. tks high range*/
1091
1092 cmpw cr0,r5,r11 /* calc value within range? */
1093 blt gcs_cspd_retry /* less than low range */
1094 cmpw cr0,r5,r12
1095 bgt gcs_cspd_retry /* greater than high range */
1096 b gcs_cspd_fnd /* calc value within range */
1097
1098 /*--------------------------------------------------------------------+
1099 | SO FAR CORE SPEED NOT FOUND: Check next mult factor
1100 +--------------------------------------------------------------------*/
1101gcs_cspd_retry:
1102 addi r9,r9,1 /* bump mult factor (1-4x) */
1103 cmpwi cr0,r9,GCS_NMULT
1104 ble gcs_cspd_loop
1105
1106 /*--------------------------------------------------------------------+
1107 | SO FAR CORE SPEED NOT FOUND: Point at next Bus Speed in LUT
1108 +--------------------------------------------------------------------*/
1109 li r9,1 /* reset mult factor */
1110 addi r6,r6,GCS_TROW_BYTES /* point at next table entry*/
1111 lwz r10,0(r6)
1112 cmpwi cr0,r10,0 /* check for EOT flag */
1113 bne gcs_cspd_loop
1114
1115 /*--------------------------------------------------------------------+
1116 | COMPUTE CORE SPEED AND GET BUS SPEED FROM LOOK-UP TABLE
1117 +--------------------------------------------------------------------*/
1118gcs_cspd_fnd:
1119 lwz r5,4(r6) /* r5 <- Bus Speed in LUT */
1120 mullw r6,r5,r9 /* r6 <- Core speed */
1121 stw r5,0(r3) /* (r3) <- Bus Speed */
1122 stw r6,0(r4) /* (r4) <- Core Speed */
1123
1124 blr
1125#endif
diff --git a/arch/ppc/boot/simple/rw4/stb.h b/arch/ppc/boot/simple/rw4/stb.h
deleted file mode 100644
index 9afa5ab24d26..000000000000
--- a/arch/ppc/boot/simple/rw4/stb.h
+++ /dev/null
@@ -1,239 +0,0 @@
1/*----------------------------------------------------------------------------+
2| This source code has been made available to you by IBM on an AS-IS
3| basis. Anyone receiving this source is licensed under IBM
4| copyrights to use it in any way he or she deems fit, including
5| copying it, modifying it, compiling it, and redistributing it either
6| with or without modifications. No license under IBM patents or
7| patent applications is to be implied by the copyright license.
8|
9| Any user of this software should understand that IBM cannot provide
10| technical support for this software and will not be responsible for
11| any consequences resulting from the use of this software.
12|
13| Any person who transfers this source code or any derivative work
14| must include the IBM copyright notice, this paragraph, and the
15| preceding two paragraphs in the transferred software.
16|
17| COPYRIGHT I B M CORPORATION 1999
18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
19+----------------------------------------------------------------------------*/
20/*----------------------------------------------------------------------------+
21| Author: Maciej P. Tyrlik
22| Component: Include file.
23| File: stb.h
24| Purpose: Common Set-tob-box definitions.
25| Changes:
26| Date: Comment:
27| ----- --------
28| 14-Jan-97 Created for ElPaso pass 1 MPT
29| 13-May-97 Added function prototype and global variables MPT
30| 08-Dec-98 Added RAW IR task information MPT
31| 19-Jan-99 Port to Romeo MPT
32| 19-May-00 Changed SDRAM to 32MB contiguous 0x1F000000 - 0x20FFFFFF RLB
33+----------------------------------------------------------------------------*/
34
35#ifndef _stb_h_
36#define _stb_h_
37
38/*----------------------------------------------------------------------------+
39| Read/write from I/O macros.
40+----------------------------------------------------------------------------*/
41#define inbyte(port) (*((unsigned char volatile *)(port)))
42#define outbyte(port,data) *(unsigned char volatile *)(port)=\
43 (unsigned char)(data)
44
45#define inshort(port) (*((unsigned short volatile *)(port)))
46#define outshort(port,data) *(unsigned short volatile *)(port)=\
47 (unsigned short)(data)
48
49#define inword(port) (*((unsigned long volatile *)(port)))
50#define outword(port,data) *(unsigned long volatile *)(port)=\
51 (unsigned long)(data)
52
53/*----------------------------------------------------------------------------+
54| STB interrupts.
55+----------------------------------------------------------------------------*/
56#define STB_XP_TP_INT 0
57#define STB_XP_APP_INT 1
58#define STB_AUD_INT 2
59#define STB_VID_INT 3
60#define STB_DMA0_INT 4
61#define STB_DMA1_INT 5
62#define STB_DMA2_INT 6
63#define STB_DMA3_INT 7
64#define STB_SCI_INT 8
65#define STB_I2C1_INT 9
66#define STB_I2C2_INT 10
67#define STB_GPT_PWM0 11
68#define STB_GPT_PWM1 12
69#define STB_SCP_INT 13
70#define STB_SSP_INT 14
71#define STB_GPT_PWM2 15
72#define STB_EXT5_INT 16
73#define STB_EXT6_INT 17
74#define STB_EXT7_INT 18
75#define STB_EXT8_INT 19
76#define STB_SCC_INT 20
77#define STB_SICC_RECV_INT 21
78#define STB_SICC_TRAN_INT 22
79#define STB_PPU_INT 23
80#define STB_DCRX_INT 24
81#define STB_EXT0_INT 25
82#define STB_EXT1_INT 26
83#define STB_EXT2_INT 27
84#define STB_EXT3_INT 28
85#define STB_EXT4_INT 29
86#define STB_REDWOOD_ENET_INT STB_EXT1_INT
87
88/*----------------------------------------------------------------------------+
89| STB tasks, task stack sizes, and task priorities. The actual task priority
90| is 1 more than the specified number since priority 0 is reserved (system
91| internally adds 1 to supplied priority number).
92+----------------------------------------------------------------------------*/
93#define STB_IDLE_TASK_SS (5* 1024)
94#define STB_IDLE_TASK_PRIO 0
95#define STB_LEDTEST_SS (2* 1024)
96#define STB_LEDTEST_PRIO 0
97#define STB_CURSOR_TASK_SS (10* 1024)
98#define STB_CURSOR_TASK_PRIO 7
99#define STB_MPEG_TASK_SS (10* 1024)
100#define STB_MPEG_TASK_PRIO 9
101#define STB_DEMUX_TASK_SS (10* 1024)
102#define STB_DEMUX_TASK_PRIO 20
103#define RAW_STB_IR_TASK_SS (10* 1024)
104#define RAW_STB_IR_TASK_PRIO 20
105
106#define STB_SERIAL_ER_TASK_SS (10* 1024)
107#define STB_SERIAL_ER_TASK_PRIO 1
108#define STB_CA_TASK_SS (10* 1024)
109#define STB_CA_TASK_PRIO 8
110
111#define INIT_DEFAULT_VIDEO_SS (10* 1024)
112#define INIT_DEFAULT_VIDEO_PRIO 8
113#define INIT_DEFAULT_SERVI_SS (10* 1024)
114#define INIT_DEFAULT_SERVI_PRIO 8
115#define INIT_DEFAULT_POST_SS (10* 1024)
116#define INIT_DEFAULT_POST_PRIO 8
117#define INIT_DEFAULT_INTER_SS (10* 1024)
118#define INIT_DEFAULT_INTER_PRIO 8
119#define INIT_DEFAULT_BR_SS (10* 1024)
120#define INIT_DEFAULT_BR_PRIO 8
121#define INITIAL_TASK_STACK_SIZE (32* 1024)
122
123#ifdef VESTA
124/*----------------------------------------------------------------------------+
125| Vesta Overall Address Map (all addresses are double mapped, bit 0 of the
126| address is not decoded. Numbers below are dependent on board configuration.
127| FLASH, SDRAM, DRAM numbers can be affected by actual board setup.
128|
129| FFE0,0000 - FFFF,FFFF FLASH
130| F200,0000 - F210,FFFF FPGA logic
131| Ethernet = F200,0000
132| LED Display = F200,0100
133| Xilinx #1 Regs = F204,0000
134| Xilinx #2 Regs = F208,0000
135| Spare = F20C,0000
136| IDE CS0 = F210,0000
137| F410,0000 - F410,FFFF IDE CS1
138| C000,0000 - C7FF,FFFF OBP
139| C000,0000 - C000,0014 SICC (16550 + infra red)
140| C001,0000 - C001,0018 PPU (Parallel Port)
141| C002,0000 - C002,001B SC0 (Smart Card 0)
142| C003,0000 - C003,000F I2C0
143| C004,0000 - C004,0009 SCC (16550 UART)
144| C005,0000 - C005,0124 GPT (Timers)
145| C006,0000 - C006,0058 GPIO0
146| C007,0000 - C007,001b SC1 (Smart Card 1)
147| C008,0000 - C008,FFFF Unused
148| C009,0000 - C009,FFFF Unused
149| C00A,0000 - C00A,FFFF Unused
150| C00B,0000 - C00B,000F I2C1
151| C00C,0000 - C00C,0006 SCP
152| C00D,0000 - C00D,0010 SSP
153| A000,0000 - A0FF,FFFF SDRAM1 (16M)
154| 0000,0000 - 00FF,FFFF SDRAM0 (16M)
155+----------------------------------------------------------------------------*/
156#define STB_FLASH_BASE_ADDRESS 0xFFE00000
157#define STB_FPGA_BASE_ADDRESS 0xF2000000
158#define STB_SICC_BASE_ADDRESS 0xC0000000
159#define STB_PPU_BASE_ADDR 0xC0010000
160#define STB_SC0_BASE_ADDRESS 0xC0020000
161#define STB_I2C1_BASE_ADDRESS 0xC0030000
162#define STB_SCC_BASE_ADDRESS 0xC0040000
163#define STB_TIMERS_BASE_ADDRESS 0xC0050000
164#define STB_GPIO0_BASE_ADDRESS 0xC0060000
165#define STB_SC1_BASE_ADDRESS 0xC0070000
166#define STB_I2C2_BASE_ADDRESS 0xC00B0000
167#define STB_SCP_BASE_ADDRESS 0xC00C0000
168#define STB_SSP_BASE_ADDRESS 0xC00D0000
169/*----------------------------------------------------------------------------+
170|The following are used by the IBM RTOS SW.
171|15-May-00 Changed these values to reflect movement of base addresses in
172|order to support 32MB of contiguous SDRAM space.
173|Points to the cacheable region since these values are used in IBM RTOS
174|to establish the vector address.
175+----------------------------------------------------------------------------*/
176#define STB_SDRAM1_BASE_ADDRESS 0x20000000
177#define STB_SDRAM1_SIZE 0x01000000
178#define STB_SDRAM0_BASE_ADDRESS 0x1F000000
179#define STB_SDRAM0_SIZE 0x01000000
180
181#else
182/*----------------------------------------------------------------------------+
183| ElPaso Overall Address Map (all addresses are double mapped, bit 0 of the
184| address is not decoded. Numbers below are dependent on board configuration.
185| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. OPB
186| devices are inside the ElPaso chip.
187| FFE0,0000 - FFFF,FFFF FLASH
188| F144,0000 - F104,FFFF FPGA logic
189| F140,0000 - F100,0000 ethernet (through FPGA logic)
190| C000,0000 - C7FF,FFFF OBP
191| C000,0000 - C000,0014 SICC (16550+ infra red)
192| C001,0000 - C001,0016 PPU (parallel port)
193| C002,0000 - C002,001B SC (smart card)
194| C003,0000 - C003,000F I2C 1
195| C004,0000 - C004,0009 SCC (16550 UART)
196| C005,0000 - C005,0124 Timers
197| C006,0000 - C006,0058 GPIO0
198| C007,0000 - C007,0058 GPIO1
199| C008,0000 - C008,0058 GPIO2
200| C009,0000 - C009,0058 GPIO3
201| C00A,0000 - C00A,0058 GPIO4
202| C00B,0000 - C00B,000F I2C 2
203| C00C,0000 - C00C,0006 SCP
204| C00D,0000 - C00D,0006 SSP
205| A000,0000 - A0FF,FFFF SDRAM 16M
206| 0000,0000 - 00FF,FFFF DRAM 16M
207+----------------------------------------------------------------------------*/
208#define STB_FLASH_BASE_ADDRESS 0xFFE00000
209#define STB_FPGA_BASE_ADDRESS 0xF1440000
210#define STB_ENET_BASE_ADDRESS 0xF1400000
211#define STB_SICC_BASE_ADDRESS 0xC0000000
212#define STB_PPU_BASE_ADDR 0xC0010000
213#define STB_SC_BASE_ADDRESS 0xC0020000
214#define STB_I2C1_BASE_ADDRESS 0xC0030000
215#define STB_SCC_BASE_ADDRESS 0xC0040000
216#define STB_TIMERS_BASE_ADDRESS 0xC0050000
217#define STB_GPIO0_BASE_ADDRESS 0xC0060000
218#define STB_GPIO1_BASE_ADDRESS 0xC0070000
219#define STB_GPIO2_BASE_ADDRESS 0xC0080000
220#define STB_GPIO3_BASE_ADDRESS 0xC0090000
221#define STB_GPIO4_BASE_ADDRESS 0xC00A0000
222#define STB_I2C2_BASE_ADDRESS 0xC00B0000
223#define STB_SCP_BASE_ADDRESS 0xC00C0000
224#define STB_SSP_BASE_ADDRESS 0xC00D0000
225#define STB_SDRAM_BASE_ADDRESS 0xA0000000
226#endif
227
228/*----------------------------------------------------------------------------+
229| Other common defines.
230+----------------------------------------------------------------------------*/
231#ifndef TRUE
232#define TRUE 1
233#endif
234
235#ifndef FALSE
236#define FALSE 0
237#endif
238
239#endif /* _stb_h_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 18:11:02 -0500