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1/*----------------------------------------------------------------------------+
2| This source code has been made available to you by IBM on an AS-IS
3| basis. Anyone receiving this source is licensed under IBM
4| copyrights to use it in any way he or she deems fit, including
5| copying it, modifying it, compiling it, and redistributing it either
6| with or without modifications. No license under IBM patents or
7| patent applications is to be implied by the copyright license.
8|
9| Any user of this software should understand that IBM cannot provide
10| technical support for this software and will not be responsible for
11| any consequences resulting from the use of this software.
12|
13| Any person who transfers this source code or any derivative work
14| must include the IBM copyright notice, this paragraph, and the
15| preceding two paragraphs in the transferred software.
16|
17| COPYRIGHT I B M CORPORATION 1999
18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
19+----------------------------------------------------------------------------*/
20/*----------------------------------------------------------------------------+
21| Author: Maciej P. Tyrlik
22| Component: Include file.
23| File: stb.h
24| Purpose: Common Set-tob-box definitions.
25| Changes:
26| Date: Comment:
27| ----- --------
28| 14-Jan-97 Created for ElPaso pass 1 MPT
29| 13-May-97 Added function prototype and global variables MPT
30| 08-Dec-98 Added RAW IR task information MPT
31| 19-Jan-99 Port to Romeo MPT
32| 19-May-00 Changed SDRAM to 32MB contiguous 0x1F000000 - 0x20FFFFFF RLB
33+----------------------------------------------------------------------------*/
34
35#ifndef _stb_h_
36#define _stb_h_
37
38/*----------------------------------------------------------------------------+
39| Read/write from I/O macros.
40+----------------------------------------------------------------------------*/
41#define inbyte(port) (*((unsigned char volatile *)(port)))
42#define outbyte(port,data) *(unsigned char volatile *)(port)=\
43 (unsigned char)(data)
44
45#define inshort(port) (*((unsigned short volatile *)(port)))
46#define outshort(port,data) *(unsigned short volatile *)(port)=\
47 (unsigned short)(data)
48
49#define inword(port) (*((unsigned long volatile *)(port)))
50#define outword(port,data) *(unsigned long volatile *)(port)=\
51 (unsigned long)(data)
52
53/*----------------------------------------------------------------------------+
54| STB interrupts.
55+----------------------------------------------------------------------------*/
56#define STB_XP_TP_INT 0
57#define STB_XP_APP_INT 1
58#define STB_AUD_INT 2
59#define STB_VID_INT 3
60#define STB_DMA0_INT 4
61#define STB_DMA1_INT 5
62#define STB_DMA2_INT 6
63#define STB_DMA3_INT 7
64#define STB_SCI_INT 8
65#define STB_I2C1_INT 9
66#define STB_I2C2_INT 10
67#define STB_GPT_PWM0 11
68#define STB_GPT_PWM1 12
69#define STB_SCP_INT 13
70#define STB_SSP_INT 14
71#define STB_GPT_PWM2 15
72#define STB_EXT5_INT 16
73#define STB_EXT6_INT 17
74#define STB_EXT7_INT 18
75#define STB_EXT8_INT 19
76#define STB_SCC_INT 20
77#define STB_SICC_RECV_INT 21
78#define STB_SICC_TRAN_INT 22
79#define STB_PPU_INT 23
80#define STB_DCRX_INT 24
81#define STB_EXT0_INT 25
82#define STB_EXT1_INT 26
83#define STB_EXT2_INT 27
84#define STB_EXT3_INT 28
85#define STB_EXT4_INT 29
86#define STB_REDWOOD_ENET_INT STB_EXT1_INT
87
88/*----------------------------------------------------------------------------+
89| STB tasks, task stack sizes, and task priorities. The actual task priority
90| is 1 more than the specified number since priority 0 is reserved (system
91| internally adds 1 to supplied priority number).
92+----------------------------------------------------------------------------*/
93#define STB_IDLE_TASK_SS (5* 1024)
94#define STB_IDLE_TASK_PRIO 0
95#define STB_LEDTEST_SS (2* 1024)
96#define STB_LEDTEST_PRIO 0
97#define STB_CURSOR_TASK_SS (10* 1024)
98#define STB_CURSOR_TASK_PRIO 7
99#define STB_MPEG_TASK_SS (10* 1024)
100#define STB_MPEG_TASK_PRIO 9
101#define STB_DEMUX_TASK_SS (10* 1024)
102#define STB_DEMUX_TASK_PRIO 20
103#define RAW_STB_IR_TASK_SS (10* 1024)
104#define RAW_STB_IR_TASK_PRIO 20
105
106#define STB_SERIAL_ER_TASK_SS (10* 1024)
107#define STB_SERIAL_ER_TASK_PRIO 1
108#define STB_CA_TASK_SS (10* 1024)
109#define STB_CA_TASK_PRIO 8
110
111#define INIT_DEFAULT_VIDEO_SS (10* 1024)
112#define INIT_DEFAULT_VIDEO_PRIO 8
113#define INIT_DEFAULT_SERVI_SS (10* 1024)
114#define INIT_DEFAULT_SERVI_PRIO 8
115#define INIT_DEFAULT_POST_SS (10* 1024)
116#define INIT_DEFAULT_POST_PRIO 8
117#define INIT_DEFAULT_INTER_SS (10* 1024)
118#define INIT_DEFAULT_INTER_PRIO 8
119#define INIT_DEFAULT_BR_SS (10* 1024)
120#define INIT_DEFAULT_BR_PRIO 8
121#define INITIAL_TASK_STACK_SIZE (32* 1024)
122
123#ifdef VESTA
124/*----------------------------------------------------------------------------+
125| Vesta Overall Address Map (all addresses are double mapped, bit 0 of the
126| address is not decoded. Numbers below are dependent on board configuration.
127| FLASH, SDRAM, DRAM numbers can be affected by actual board setup.
128|
129| FFE0,0000 - FFFF,FFFF FLASH
130| F200,0000 - F210,FFFF FPGA logic
131| Ethernet = F200,0000
132| LED Display = F200,0100
133| Xilinx #1 Regs = F204,0000
134| Xilinx #2 Regs = F208,0000
135| Spare = F20C,0000
136| IDE CS0 = F210,0000
137| F410,0000 - F410,FFFF IDE CS1
138| C000,0000 - C7FF,FFFF OBP
139| C000,0000 - C000,0014 SICC (16550 + infra red)
140| C001,0000 - C001,0018 PPU (Parallel Port)
141| C002,0000 - C002,001B SC0 (Smart Card 0)
142| C003,0000 - C003,000F I2C0
143| C004,0000 - C004,0009 SCC (16550 UART)
144| C005,0000 - C005,0124 GPT (Timers)
145| C006,0000 - C006,0058 GPIO0
146| C007,0000 - C007,001b SC1 (Smart Card 1)
147| C008,0000 - C008,FFFF Unused
148| C009,0000 - C009,FFFF Unused
149| C00A,0000 - C00A,FFFF Unused
150| C00B,0000 - C00B,000F I2C1
151| C00C,0000 - C00C,0006 SCP
152| C00D,0000 - C00D,0010 SSP
153| A000,0000 - A0FF,FFFF SDRAM1 (16M)
154| 0000,0000 - 00FF,FFFF SDRAM0 (16M)
155+----------------------------------------------------------------------------*/
156#define STB_FLASH_BASE_ADDRESS 0xFFE00000
157#define STB_FPGA_BASE_ADDRESS 0xF2000000
158#define STB_SICC_BASE_ADDRESS 0xC0000000
159#define STB_PPU_BASE_ADDR 0xC0010000
160#define STB_SC0_BASE_ADDRESS 0xC0020000
161#define STB_I2C1_BASE_ADDRESS 0xC0030000
162#define STB_SCC_BASE_ADDRESS 0xC0040000
163#define STB_TIMERS_BASE_ADDRESS 0xC0050000
164#define STB_GPIO0_BASE_ADDRESS 0xC0060000
165#define STB_SC1_BASE_ADDRESS 0xC0070000
166#define STB_I2C2_BASE_ADDRESS 0xC00B0000
167#define STB_SCP_BASE_ADDRESS 0xC00C0000
168#define STB_SSP_BASE_ADDRESS 0xC00D0000
169/*----------------------------------------------------------------------------+
170|The following are used by the IBM RTOS SW.
171|15-May-00 Changed these values to reflect movement of base addresses in
172|order to support 32MB of contiguous SDRAM space.
173|Points to the cacheable region since these values are used in IBM RTOS
174|to establish the vector address.
175+----------------------------------------------------------------------------*/
176#define STB_SDRAM1_BASE_ADDRESS 0x20000000
177#define STB_SDRAM1_SIZE 0x01000000
178#define STB_SDRAM0_BASE_ADDRESS 0x1F000000
179#define STB_SDRAM0_SIZE 0x01000000
180
181#else
182/*----------------------------------------------------------------------------+
183| ElPaso Overall Address Map (all addresses are double mapped, bit 0 of the
184| address is not decoded. Numbers below are dependent on board configuration.
185| FLASH, SDRAM, DRAM numbers can be affected by actual board setup. OPB
186| devices are inside the ElPaso chip.
187| FFE0,0000 - FFFF,FFFF FLASH
188| F144,0000 - F104,FFFF FPGA logic
189| F140,0000 - F100,0000 ethernet (through FPGA logic)
190| C000,0000 - C7FF,FFFF OBP
191| C000,0000 - C000,0014 SICC (16550+ infra red)
192| C001,0000 - C001,0016 PPU (parallel port)
193| C002,0000 - C002,001B SC (smart card)
194| C003,0000 - C003,000F I2C 1
195| C004,0000 - C004,0009 SCC (16550 UART)
196| C005,0000 - C005,0124 Timers
197| C006,0000 - C006,0058 GPIO0
198| C007,0000 - C007,0058 GPIO1
199| C008,0000 - C008,0058 GPIO2
200| C009,0000 - C009,0058 GPIO3
201| C00A,0000 - C00A,0058 GPIO4
202| C00B,0000 - C00B,000F I2C 2
203| C00C,0000 - C00C,0006 SCP
204| C00D,0000 - C00D,0006 SSP
205| A000,0000 - A0FF,FFFF SDRAM 16M
206| 0000,0000 - 00FF,FFFF DRAM 16M
207+----------------------------------------------------------------------------*/
208#define STB_FLASH_BASE_ADDRESS 0xFFE00000
209#define STB_FPGA_BASE_ADDRESS 0xF1440000
210#define STB_ENET_BASE_ADDRESS 0xF1400000
211#define STB_SICC_BASE_ADDRESS 0xC0000000
212#define STB_PPU_BASE_ADDR 0xC0010000
213#define STB_SC_BASE_ADDRESS 0xC0020000
214#define STB_I2C1_BASE_ADDRESS 0xC0030000
215#define STB_SCC_BASE_ADDRESS 0xC0040000
216#define STB_TIMERS_BASE_ADDRESS 0xC0050000
217#define STB_GPIO0_BASE_ADDRESS 0xC0060000
218#define STB_GPIO1_BASE_ADDRESS 0xC0070000
219#define STB_GPIO2_BASE_ADDRESS 0xC0080000
220#define STB_GPIO3_BASE_ADDRESS 0xC0090000
221#define STB_GPIO4_BASE_ADDRESS 0xC00A0000
222#define STB_I2C2_BASE_ADDRESS 0xC00B0000
223#define STB_SCP_BASE_ADDRESS 0xC00C0000
224#define STB_SSP_BASE_ADDRESS 0xC00D0000
225#define STB_SDRAM_BASE_ADDRESS 0xA0000000
226#endif
227
228/*----------------------------------------------------------------------------+
229| Other common defines.
230+----------------------------------------------------------------------------*/
231#ifndef TRUE
232#define TRUE 1
233#endif
234
235#ifndef FALSE
236#define FALSE 0
237#endif
238
239#endif /* _stb_h_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 23:23:19 -0400