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-rw-r--r--arch/powerpc/include/asm/asm-compat.h5
-rw-r--r--arch/powerpc/include/asm/atomic.h48
-rw-r--r--arch/powerpc/include/asm/bitops.h56
-rw-r--r--arch/powerpc/include/asm/cputable.h4
-rw-r--r--arch/powerpc/include/asm/cputime.h7
-rw-r--r--arch/powerpc/include/asm/feature-fixups.h2
-rw-r--r--arch/powerpc/include/asm/futex.h6
-rw-r--r--arch/powerpc/include/asm/hardirq.h30
-rw-r--r--arch/powerpc/include/asm/local.h12
-rw-r--r--arch/powerpc/include/asm/mpc5121.h24
-rw-r--r--arch/powerpc/include/asm/mpc52xx_psc.h4
-rw-r--r--arch/powerpc/include/asm/mpic.h2
-rw-r--r--arch/powerpc/include/asm/mutex.h6
-rw-r--r--arch/powerpc/include/asm/param.h23
-rw-r--r--arch/powerpc/include/asm/pgtable.h2
-rw-r--r--arch/powerpc/include/asm/pmac_feature.h2
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h18
-rw-r--r--arch/powerpc/include/asm/ppc-pci.h5
-rw-r--r--arch/powerpc/include/asm/processor.h36
-rw-r--r--arch/powerpc/include/asm/prom.h18
-rw-r--r--arch/powerpc/include/asm/ptrace.h77
-rw-r--r--arch/powerpc/include/asm/reg_booke.h96
-rw-r--r--arch/powerpc/include/asm/spinlock.h32
-rw-r--r--arch/powerpc/include/asm/synch.h12
-rw-r--r--arch/powerpc/include/asm/system.h21
-rw-r--r--arch/powerpc/include/asm/topology.h48
26 files changed, 430 insertions, 166 deletions
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
index 8f0fe7971949..c1b475a941eb 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -2,6 +2,7 @@
2#define _ASM_POWERPC_ASM_COMPAT_H 2#define _ASM_POWERPC_ASM_COMPAT_H
3 3
4#include <asm/types.h> 4#include <asm/types.h>
5#include <asm/ppc-opcode.h>
5 6
6#ifdef __ASSEMBLY__ 7#ifdef __ASSEMBLY__
7# define stringify_in_c(...) __VA_ARGS__ 8# define stringify_in_c(...) __VA_ARGS__
@@ -24,7 +25,7 @@
24#define PPC_LONG stringify_in_c(.llong) 25#define PPC_LONG stringify_in_c(.llong)
25#define PPC_LONG_ALIGN stringify_in_c(.balign 8) 26#define PPC_LONG_ALIGN stringify_in_c(.balign 8)
26#define PPC_TLNEI stringify_in_c(tdnei) 27#define PPC_TLNEI stringify_in_c(tdnei)
27#define PPC_LLARX stringify_in_c(ldarx) 28#define PPC_LLARX(t, a, b, eh) PPC_LDARX(t, a, b, eh)
28#define PPC_STLCX stringify_in_c(stdcx.) 29#define PPC_STLCX stringify_in_c(stdcx.)
29#define PPC_CNTLZL stringify_in_c(cntlzd) 30#define PPC_CNTLZL stringify_in_c(cntlzd)
30 31
@@ -46,7 +47,7 @@
46#define PPC_LONG stringify_in_c(.long) 47#define PPC_LONG stringify_in_c(.long)
47#define PPC_LONG_ALIGN stringify_in_c(.balign 4) 48#define PPC_LONG_ALIGN stringify_in_c(.balign 4)
48#define PPC_TLNEI stringify_in_c(twnei) 49#define PPC_TLNEI stringify_in_c(twnei)
49#define PPC_LLARX stringify_in_c(lwarx) 50#define PPC_LLARX(t, a, b, eh) PPC_LWARX(t, a, b, eh)
50#define PPC_STLCX stringify_in_c(stwcx.) 51#define PPC_STLCX stringify_in_c(stwcx.)
51#define PPC_CNTLZL stringify_in_c(cntlzw) 52#define PPC_CNTLZL stringify_in_c(cntlzw)
52#define PPC_MTOCRF stringify_in_c(mtcrf) 53#define PPC_MTOCRF stringify_in_c(mtcrf)
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index 4012483b1899..b8f152ece025 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -49,13 +49,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
49 int t; 49 int t;
50 50
51 __asm__ __volatile__( 51 __asm__ __volatile__(
52 LWSYNC_ON_SMP 52 PPC_RELEASE_BARRIER
53"1: lwarx %0,0,%2 # atomic_add_return\n\ 53"1: lwarx %0,0,%2 # atomic_add_return\n\
54 add %0,%1,%0\n" 54 add %0,%1,%0\n"
55 PPC405_ERR77(0,%2) 55 PPC405_ERR77(0,%2)
56" stwcx. %0,0,%2 \n\ 56" stwcx. %0,0,%2 \n\
57 bne- 1b" 57 bne- 1b"
58 ISYNC_ON_SMP 58 PPC_ACQUIRE_BARRIER
59 : "=&r" (t) 59 : "=&r" (t)
60 : "r" (a), "r" (&v->counter) 60 : "r" (a), "r" (&v->counter)
61 : "cc", "memory"); 61 : "cc", "memory");
@@ -85,13 +85,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
85 int t; 85 int t;
86 86
87 __asm__ __volatile__( 87 __asm__ __volatile__(
88 LWSYNC_ON_SMP 88 PPC_RELEASE_BARRIER
89"1: lwarx %0,0,%2 # atomic_sub_return\n\ 89"1: lwarx %0,0,%2 # atomic_sub_return\n\
90 subf %0,%1,%0\n" 90 subf %0,%1,%0\n"
91 PPC405_ERR77(0,%2) 91 PPC405_ERR77(0,%2)
92" stwcx. %0,0,%2 \n\ 92" stwcx. %0,0,%2 \n\
93 bne- 1b" 93 bne- 1b"
94 ISYNC_ON_SMP 94 PPC_ACQUIRE_BARRIER
95 : "=&r" (t) 95 : "=&r" (t)
96 : "r" (a), "r" (&v->counter) 96 : "r" (a), "r" (&v->counter)
97 : "cc", "memory"); 97 : "cc", "memory");
@@ -119,13 +119,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
119 int t; 119 int t;
120 120
121 __asm__ __volatile__( 121 __asm__ __volatile__(
122 LWSYNC_ON_SMP 122 PPC_RELEASE_BARRIER
123"1: lwarx %0,0,%1 # atomic_inc_return\n\ 123"1: lwarx %0,0,%1 # atomic_inc_return\n\
124 addic %0,%0,1\n" 124 addic %0,%0,1\n"
125 PPC405_ERR77(0,%1) 125 PPC405_ERR77(0,%1)
126" stwcx. %0,0,%1 \n\ 126" stwcx. %0,0,%1 \n\
127 bne- 1b" 127 bne- 1b"
128 ISYNC_ON_SMP 128 PPC_ACQUIRE_BARRIER
129 : "=&r" (t) 129 : "=&r" (t)
130 : "r" (&v->counter) 130 : "r" (&v->counter)
131 : "cc", "xer", "memory"); 131 : "cc", "xer", "memory");
@@ -163,13 +163,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
163 int t; 163 int t;
164 164
165 __asm__ __volatile__( 165 __asm__ __volatile__(
166 LWSYNC_ON_SMP 166 PPC_RELEASE_BARRIER
167"1: lwarx %0,0,%1 # atomic_dec_return\n\ 167"1: lwarx %0,0,%1 # atomic_dec_return\n\
168 addic %0,%0,-1\n" 168 addic %0,%0,-1\n"
169 PPC405_ERR77(0,%1) 169 PPC405_ERR77(0,%1)
170" stwcx. %0,0,%1\n\ 170" stwcx. %0,0,%1\n\
171 bne- 1b" 171 bne- 1b"
172 ISYNC_ON_SMP 172 PPC_ACQUIRE_BARRIER
173 : "=&r" (t) 173 : "=&r" (t)
174 : "r" (&v->counter) 174 : "r" (&v->counter)
175 : "cc", "xer", "memory"); 175 : "cc", "xer", "memory");
@@ -194,7 +194,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
194 int t; 194 int t;
195 195
196 __asm__ __volatile__ ( 196 __asm__ __volatile__ (
197 LWSYNC_ON_SMP 197 PPC_RELEASE_BARRIER
198"1: lwarx %0,0,%1 # atomic_add_unless\n\ 198"1: lwarx %0,0,%1 # atomic_add_unless\n\
199 cmpw 0,%0,%3 \n\ 199 cmpw 0,%0,%3 \n\
200 beq- 2f \n\ 200 beq- 2f \n\
@@ -202,7 +202,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
202 PPC405_ERR77(0,%2) 202 PPC405_ERR77(0,%2)
203" stwcx. %0,0,%1 \n\ 203" stwcx. %0,0,%1 \n\
204 bne- 1b \n" 204 bne- 1b \n"
205 ISYNC_ON_SMP 205 PPC_ACQUIRE_BARRIER
206" subf %0,%2,%0 \n\ 206" subf %0,%2,%0 \n\
2072:" 2072:"
208 : "=&r" (t) 208 : "=&r" (t)
@@ -227,7 +227,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
227 int t; 227 int t;
228 228
229 __asm__ __volatile__( 229 __asm__ __volatile__(
230 LWSYNC_ON_SMP 230 PPC_RELEASE_BARRIER
231"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\ 231"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
232 cmpwi %0,1\n\ 232 cmpwi %0,1\n\
233 addi %0,%0,-1\n\ 233 addi %0,%0,-1\n\
@@ -235,7 +235,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
235 PPC405_ERR77(0,%1) 235 PPC405_ERR77(0,%1)
236" stwcx. %0,0,%1\n\ 236" stwcx. %0,0,%1\n\
237 bne- 1b" 237 bne- 1b"
238 ISYNC_ON_SMP 238 PPC_ACQUIRE_BARRIER
239 "\n\ 239 "\n\
2402:" : "=&b" (t) 2402:" : "=&b" (t)
241 : "r" (&v->counter) 241 : "r" (&v->counter)
@@ -286,12 +286,12 @@ static __inline__ long atomic64_add_return(long a, atomic64_t *v)
286 long t; 286 long t;
287 287
288 __asm__ __volatile__( 288 __asm__ __volatile__(
289 LWSYNC_ON_SMP 289 PPC_RELEASE_BARRIER
290"1: ldarx %0,0,%2 # atomic64_add_return\n\ 290"1: ldarx %0,0,%2 # atomic64_add_return\n\
291 add %0,%1,%0\n\ 291 add %0,%1,%0\n\
292 stdcx. %0,0,%2 \n\ 292 stdcx. %0,0,%2 \n\
293 bne- 1b" 293 bne- 1b"
294 ISYNC_ON_SMP 294 PPC_ACQUIRE_BARRIER
295 : "=&r" (t) 295 : "=&r" (t)
296 : "r" (a), "r" (&v->counter) 296 : "r" (a), "r" (&v->counter)
297 : "cc", "memory"); 297 : "cc", "memory");
@@ -320,12 +320,12 @@ static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
320 long t; 320 long t;
321 321
322 __asm__ __volatile__( 322 __asm__ __volatile__(
323 LWSYNC_ON_SMP 323 PPC_RELEASE_BARRIER
324"1: ldarx %0,0,%2 # atomic64_sub_return\n\ 324"1: ldarx %0,0,%2 # atomic64_sub_return\n\
325 subf %0,%1,%0\n\ 325 subf %0,%1,%0\n\
326 stdcx. %0,0,%2 \n\ 326 stdcx. %0,0,%2 \n\
327 bne- 1b" 327 bne- 1b"
328 ISYNC_ON_SMP 328 PPC_ACQUIRE_BARRIER
329 : "=&r" (t) 329 : "=&r" (t)
330 : "r" (a), "r" (&v->counter) 330 : "r" (a), "r" (&v->counter)
331 : "cc", "memory"); 331 : "cc", "memory");
@@ -352,12 +352,12 @@ static __inline__ long atomic64_inc_return(atomic64_t *v)
352 long t; 352 long t;
353 353
354 __asm__ __volatile__( 354 __asm__ __volatile__(
355 LWSYNC_ON_SMP 355 PPC_RELEASE_BARRIER
356"1: ldarx %0,0,%1 # atomic64_inc_return\n\ 356"1: ldarx %0,0,%1 # atomic64_inc_return\n\
357 addic %0,%0,1\n\ 357 addic %0,%0,1\n\
358 stdcx. %0,0,%1 \n\ 358 stdcx. %0,0,%1 \n\
359 bne- 1b" 359 bne- 1b"
360 ISYNC_ON_SMP 360 PPC_ACQUIRE_BARRIER
361 : "=&r" (t) 361 : "=&r" (t)
362 : "r" (&v->counter) 362 : "r" (&v->counter)
363 : "cc", "xer", "memory"); 363 : "cc", "xer", "memory");
@@ -394,12 +394,12 @@ static __inline__ long atomic64_dec_return(atomic64_t *v)
394 long t; 394 long t;
395 395
396 __asm__ __volatile__( 396 __asm__ __volatile__(
397 LWSYNC_ON_SMP 397 PPC_RELEASE_BARRIER
398"1: ldarx %0,0,%1 # atomic64_dec_return\n\ 398"1: ldarx %0,0,%1 # atomic64_dec_return\n\
399 addic %0,%0,-1\n\ 399 addic %0,%0,-1\n\
400 stdcx. %0,0,%1\n\ 400 stdcx. %0,0,%1\n\
401 bne- 1b" 401 bne- 1b"
402 ISYNC_ON_SMP 402 PPC_ACQUIRE_BARRIER
403 : "=&r" (t) 403 : "=&r" (t)
404 : "r" (&v->counter) 404 : "r" (&v->counter)
405 : "cc", "xer", "memory"); 405 : "cc", "xer", "memory");
@@ -419,13 +419,13 @@ static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
419 long t; 419 long t;
420 420
421 __asm__ __volatile__( 421 __asm__ __volatile__(
422 LWSYNC_ON_SMP 422 PPC_RELEASE_BARRIER
423"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\ 423"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
424 addic. %0,%0,-1\n\ 424 addic. %0,%0,-1\n\
425 blt- 2f\n\ 425 blt- 2f\n\
426 stdcx. %0,0,%1\n\ 426 stdcx. %0,0,%1\n\
427 bne- 1b" 427 bne- 1b"
428 ISYNC_ON_SMP 428 PPC_ACQUIRE_BARRIER
429 "\n\ 429 "\n\
4302:" : "=&r" (t) 4302:" : "=&r" (t)
431 : "r" (&v->counter) 431 : "r" (&v->counter)
@@ -451,14 +451,14 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
451 long t; 451 long t;
452 452
453 __asm__ __volatile__ ( 453 __asm__ __volatile__ (
454 LWSYNC_ON_SMP 454 PPC_RELEASE_BARRIER
455"1: ldarx %0,0,%1 # atomic_add_unless\n\ 455"1: ldarx %0,0,%1 # atomic_add_unless\n\
456 cmpd 0,%0,%3 \n\ 456 cmpd 0,%0,%3 \n\
457 beq- 2f \n\ 457 beq- 2f \n\
458 add %0,%2,%0 \n" 458 add %0,%2,%0 \n"
459" stdcx. %0,0,%1 \n\ 459" stdcx. %0,0,%1 \n\
460 bne- 1b \n" 460 bne- 1b \n"
461 ISYNC_ON_SMP 461 PPC_ACQUIRE_BARRIER
462" subf %0,%2,%0 \n\ 462" subf %0,%2,%0 \n\
4632:" 4632:"
464 : "=&r" (t) 464 : "=&r" (t)
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 56f2f2ea5631..30964ae2d096 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -65,7 +65,7 @@ static __inline__ void fn(unsigned long mask, \
65 unsigned long *p = (unsigned long *)_p; \ 65 unsigned long *p = (unsigned long *)_p; \
66 __asm__ __volatile__ ( \ 66 __asm__ __volatile__ ( \
67 prefix \ 67 prefix \
68"1:" PPC_LLARX "%0,0,%3\n" \ 68"1:" PPC_LLARX(%0,0,%3,0) "\n" \
69 stringify_in_c(op) "%0,%0,%2\n" \ 69 stringify_in_c(op) "%0,%0,%2\n" \
70 PPC405_ERR77(0,%3) \ 70 PPC405_ERR77(0,%3) \
71 PPC_STLCX "%0,0,%3\n" \ 71 PPC_STLCX "%0,0,%3\n" \
@@ -78,7 +78,7 @@ static __inline__ void fn(unsigned long mask, \
78 78
79DEFINE_BITOP(set_bits, or, "", "") 79DEFINE_BITOP(set_bits, or, "", "")
80DEFINE_BITOP(clear_bits, andc, "", "") 80DEFINE_BITOP(clear_bits, andc, "", "")
81DEFINE_BITOP(clear_bits_unlock, andc, LWSYNC_ON_SMP, "") 81DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER, "")
82DEFINE_BITOP(change_bits, xor, "", "") 82DEFINE_BITOP(change_bits, xor, "", "")
83 83
84static __inline__ void set_bit(int nr, volatile unsigned long *addr) 84static __inline__ void set_bit(int nr, volatile unsigned long *addr)
@@ -103,31 +103,35 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr)
103 103
104/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output 104/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
105 * operands. */ 105 * operands. */
106#define DEFINE_TESTOP(fn, op, prefix, postfix) \ 106#define DEFINE_TESTOP(fn, op, prefix, postfix, eh) \
107static __inline__ unsigned long fn( \ 107static __inline__ unsigned long fn( \
108 unsigned long mask, \ 108 unsigned long mask, \
109 volatile unsigned long *_p) \ 109 volatile unsigned long *_p) \
110{ \ 110{ \
111 unsigned long old, t; \ 111 unsigned long old, t; \
112 unsigned long *p = (unsigned long *)_p; \ 112 unsigned long *p = (unsigned long *)_p; \
113 __asm__ __volatile__ ( \ 113 __asm__ __volatile__ ( \
114 prefix \ 114 prefix \
115"1:" PPC_LLARX "%0,0,%3\n" \ 115"1:" PPC_LLARX(%0,0,%3,eh) "\n" \
116 stringify_in_c(op) "%1,%0,%2\n" \ 116 stringify_in_c(op) "%1,%0,%2\n" \
117 PPC405_ERR77(0,%3) \ 117 PPC405_ERR77(0,%3) \
118 PPC_STLCX "%1,0,%3\n" \ 118 PPC_STLCX "%1,0,%3\n" \
119 "bne- 1b\n" \ 119 "bne- 1b\n" \
120 postfix \ 120 postfix \
121 : "=&r" (old), "=&r" (t) \ 121 : "=&r" (old), "=&r" (t) \
122 : "r" (mask), "r" (p) \ 122 : "r" (mask), "r" (p) \
123 : "cc", "memory"); \ 123 : "cc", "memory"); \
124 return (old & mask); \ 124 return (old & mask); \
125} 125}
126 126
127DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP) 127DEFINE_TESTOP(test_and_set_bits, or, PPC_RELEASE_BARRIER,
128DEFINE_TESTOP(test_and_set_bits_lock, or, "", ISYNC_ON_SMP) 128 PPC_ACQUIRE_BARRIER, 0)
129DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP) 129DEFINE_TESTOP(test_and_set_bits_lock, or, "",
130DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP) 130 PPC_ACQUIRE_BARRIER, 1)
131DEFINE_TESTOP(test_and_clear_bits, andc, PPC_RELEASE_BARRIER,
132 PPC_ACQUIRE_BARRIER, 0)
133DEFINE_TESTOP(test_and_change_bits, xor, PPC_RELEASE_BARRIER,
134 PPC_ACQUIRE_BARRIER, 0)
131 135
132static __inline__ int test_and_set_bit(unsigned long nr, 136static __inline__ int test_and_set_bit(unsigned long nr,
133 volatile unsigned long *addr) 137 volatile unsigned long *addr)
@@ -158,7 +162,7 @@ static __inline__ int test_and_change_bit(unsigned long nr,
158 162
159static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr) 163static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
160{ 164{
161 __asm__ __volatile__(LWSYNC_ON_SMP "" ::: "memory"); 165 __asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
162 __clear_bit(nr, addr); 166 __clear_bit(nr, addr);
163} 167}
164 168
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 80f315e8a421..abb833b0e58f 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -381,9 +381,9 @@ extern const char *powerpc_base_platform;
381#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 381#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
382 382
383/* 64-bit CPUs */ 383/* 64-bit CPUs */
384#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 384#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
385 CPU_FTR_IABR | CPU_FTR_PPC_LE) 385 CPU_FTR_IABR | CPU_FTR_PPC_LE)
386#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 386#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
387 CPU_FTR_IABR | \ 387 CPU_FTR_IABR | \
388 CPU_FTR_MMCRA | CPU_FTR_CTRL) 388 CPU_FTR_MMCRA | CPU_FTR_CTRL)
389#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 389#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index fa19f3fe05ff..8bdc6a9e5773 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -73,10 +73,9 @@ static inline unsigned long cputime_to_jiffies(const cputime_t ct)
73static inline cputime_t cputime_to_scaled(const cputime_t ct) 73static inline cputime_t cputime_to_scaled(const cputime_t ct)
74{ 74{
75 if (cpu_has_feature(CPU_FTR_SPURR) && 75 if (cpu_has_feature(CPU_FTR_SPURR) &&
76 per_cpu(cputime_last_delta, smp_processor_id())) 76 __get_cpu_var(cputime_last_delta))
77 return ct * 77 return ct * __get_cpu_var(cputime_scaled_last_delta) /
78 per_cpu(cputime_scaled_last_delta, smp_processor_id())/ 78 __get_cpu_var(cputime_last_delta);
79 per_cpu(cputime_last_delta, smp_processor_id());
80 return ct; 79 return ct;
81} 80}
82 81
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
index cbd4dfa4bce2..96a7d067fbb2 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -165,7 +165,7 @@ label##2: \
165 .pushsection sect,"a"; \ 165 .pushsection sect,"a"; \
166 .align 2; \ 166 .align 2; \
167label##3: \ 167label##3: \
168 .long label##1b-label##3b; \ 168 FTR_ENTRY_OFFSET label##1b-label##3b; \
169 .popsection; 169 .popsection;
170 170
171#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */ 171#endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */
diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
index 9696cc36d2dc..7c589ef81fb0 100644
--- a/arch/powerpc/include/asm/futex.h
+++ b/arch/powerpc/include/asm/futex.h
@@ -11,7 +11,7 @@
11 11
12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
13 __asm__ __volatile ( \ 13 __asm__ __volatile ( \
14 LWSYNC_ON_SMP \ 14 PPC_RELEASE_BARRIER \
15"1: lwarx %0,0,%2\n" \ 15"1: lwarx %0,0,%2\n" \
16 insn \ 16 insn \
17 PPC405_ERR77(0, %2) \ 17 PPC405_ERR77(0, %2) \
@@ -90,14 +90,14 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
90 return -EFAULT; 90 return -EFAULT;
91 91
92 __asm__ __volatile__ ( 92 __asm__ __volatile__ (
93 LWSYNC_ON_SMP 93 PPC_RELEASE_BARRIER
94"1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\ 94"1: lwarx %0,0,%2 # futex_atomic_cmpxchg_inatomic\n\
95 cmpw 0,%0,%3\n\ 95 cmpw 0,%0,%3\n\
96 bne- 3f\n" 96 bne- 3f\n"
97 PPC405_ERR77(0,%2) 97 PPC405_ERR77(0,%2)
98"2: stwcx. %4,0,%2\n\ 98"2: stwcx. %4,0,%2\n\
99 bne- 1b\n" 99 bne- 1b\n"
100 ISYNC_ON_SMP 100 PPC_ACQUIRE_BARRIER
101"3: .section .fixup,\"ax\"\n\ 101"3: .section .fixup,\"ax\"\n\
1024: li %0,%5\n\ 1024: li %0,%5\n\
103 b 3b\n\ 103 b 3b\n\
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index fb3c05a0cbbf..3147a2970125 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -1 +1,29 @@
1#include <asm-generic/hardirq.h> 1#ifndef _ASM_POWERPC_HARDIRQ_H
2#define _ASM_POWERPC_HARDIRQ_H
3
4#include <linux/threads.h>
5#include <linux/irq.h>
6
7typedef struct {
8 unsigned int __softirq_pending;
9 unsigned int timer_irqs;
10 unsigned int pmu_irqs;
11 unsigned int mce_exceptions;
12 unsigned int spurious_irqs;
13} ____cacheline_aligned irq_cpustat_t;
14
15DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
16
17#define __ARCH_IRQ_STAT
18
19#define local_softirq_pending() __get_cpu_var(irq_stat).__softirq_pending
20
21static inline void ack_bad_irq(unsigned int irq)
22{
23 printk(KERN_CRIT "unexpected IRQ trap at vector %02x\n", irq);
24}
25
26extern u64 arch_irq_stat_cpu(unsigned int cpu);
27#define arch_irq_stat_cpu arch_irq_stat_cpu
28
29#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/arch/powerpc/include/asm/local.h b/arch/powerpc/include/asm/local.h
index 84b457a3c1bc..ce58c80e1bcf 100644
--- a/arch/powerpc/include/asm/local.h
+++ b/arch/powerpc/include/asm/local.h
@@ -24,7 +24,7 @@ static __inline__ long local_add_return(long a, local_t *l)
24 long t; 24 long t;
25 25
26 __asm__ __volatile__( 26 __asm__ __volatile__(
27"1:" PPC_LLARX "%0,0,%2 # local_add_return\n\ 27"1:" PPC_LLARX(%0,0,%2,0) " # local_add_return\n\
28 add %0,%1,%0\n" 28 add %0,%1,%0\n"
29 PPC405_ERR77(0,%2) 29 PPC405_ERR77(0,%2)
30 PPC_STLCX "%0,0,%2 \n\ 30 PPC_STLCX "%0,0,%2 \n\
@@ -43,7 +43,7 @@ static __inline__ long local_sub_return(long a, local_t *l)
43 long t; 43 long t;
44 44
45 __asm__ __volatile__( 45 __asm__ __volatile__(
46"1:" PPC_LLARX "%0,0,%2 # local_sub_return\n\ 46"1:" PPC_LLARX(%0,0,%2,0) " # local_sub_return\n\
47 subf %0,%1,%0\n" 47 subf %0,%1,%0\n"
48 PPC405_ERR77(0,%2) 48 PPC405_ERR77(0,%2)
49 PPC_STLCX "%0,0,%2 \n\ 49 PPC_STLCX "%0,0,%2 \n\
@@ -60,7 +60,7 @@ static __inline__ long local_inc_return(local_t *l)
60 long t; 60 long t;
61 61
62 __asm__ __volatile__( 62 __asm__ __volatile__(
63"1:" PPC_LLARX "%0,0,%1 # local_inc_return\n\ 63"1:" PPC_LLARX(%0,0,%1,0) " # local_inc_return\n\
64 addic %0,%0,1\n" 64 addic %0,%0,1\n"
65 PPC405_ERR77(0,%1) 65 PPC405_ERR77(0,%1)
66 PPC_STLCX "%0,0,%1 \n\ 66 PPC_STLCX "%0,0,%1 \n\
@@ -87,7 +87,7 @@ static __inline__ long local_dec_return(local_t *l)
87 long t; 87 long t;
88 88
89 __asm__ __volatile__( 89 __asm__ __volatile__(
90"1:" PPC_LLARX "%0,0,%1 # local_dec_return\n\ 90"1:" PPC_LLARX(%0,0,%1,0) " # local_dec_return\n\
91 addic %0,%0,-1\n" 91 addic %0,%0,-1\n"
92 PPC405_ERR77(0,%1) 92 PPC405_ERR77(0,%1)
93 PPC_STLCX "%0,0,%1\n\ 93 PPC_STLCX "%0,0,%1\n\
@@ -117,7 +117,7 @@ static __inline__ int local_add_unless(local_t *l, long a, long u)
117 long t; 117 long t;
118 118
119 __asm__ __volatile__ ( 119 __asm__ __volatile__ (
120"1:" PPC_LLARX "%0,0,%1 # local_add_unless\n\ 120"1:" PPC_LLARX(%0,0,%1,0) " # local_add_unless\n\
121 cmpw 0,%0,%3 \n\ 121 cmpw 0,%0,%3 \n\
122 beq- 2f \n\ 122 beq- 2f \n\
123 add %0,%2,%0 \n" 123 add %0,%2,%0 \n"
@@ -147,7 +147,7 @@ static __inline__ long local_dec_if_positive(local_t *l)
147 long t; 147 long t;
148 148
149 __asm__ __volatile__( 149 __asm__ __volatile__(
150"1:" PPC_LLARX "%0,0,%1 # local_dec_if_positive\n\ 150"1:" PPC_LLARX(%0,0,%1,0) " # local_dec_if_positive\n\
151 cmpwi %0,1\n\ 151 cmpwi %0,1\n\
152 addi %0,%0,-1\n\ 152 addi %0,%0,-1\n\
153 blt- 2f\n" 153 blt- 2f\n"
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
new file mode 100644
index 000000000000..e6a30bb1d16a
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -0,0 +1,24 @@
1/*
2 * MPC5121 Prototypes and definitions
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2.
6 */
7
8#ifndef __ASM_POWERPC_MPC5121_H__
9#define __ASM_POWERPC_MPC5121_H__
10
11/* MPC512x Reset module registers */
12struct mpc512x_reset_module {
13 u32 rcwlr; /* Reset Configuration Word Low Register */
14 u32 rcwhr; /* Reset Configuration Word High Register */
15 u32 reserved1;
16 u32 reserved2;
17 u32 rsr; /* Reset Status Register */
18 u32 rmr; /* Reset Mode Register */
19 u32 rpr; /* Reset Protection Register */
20 u32 rcr; /* Reset Control Register */
21 u32 rcer; /* Reset Control Enable Register */
22};
23
24#endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
index fb8412057450..42561f4f032d 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -25,7 +25,11 @@
25#include <asm/types.h> 25#include <asm/types.h>
26 26
27/* Max number of PSCs */ 27/* Max number of PSCs */
28#ifdef CONFIG_PPC_MPC512x
29#define MPC52xx_PSC_MAXNUM 12
30#else
28#define MPC52xx_PSC_MAXNUM 6 31#define MPC52xx_PSC_MAXNUM 6
32#endif
29 33
30/* Programmable Serial Controller (PSC) status register bits */ 34/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_UNEX_RX 0x0001 35#define MPC52xx_PSC_SR_UNEX_RX 0x0001
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index a002682f3a6d..61913d9a21a0 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -289,7 +289,7 @@ struct mpic
289#ifdef CONFIG_MPIC_U3_HT_IRQS 289#ifdef CONFIG_MPIC_U3_HT_IRQS
290 /* The fixup table */ 290 /* The fixup table */
291 struct mpic_irq_fixup *fixups; 291 struct mpic_irq_fixup *fixups;
292 spinlock_t fixup_lock; 292 raw_spinlock_t fixup_lock;
293#endif 293#endif
294 294
295 /* Register access method */ 295 /* Register access method */
diff --git a/arch/powerpc/include/asm/mutex.h b/arch/powerpc/include/asm/mutex.h
index dabc01c727b8..5399f7e18102 100644
--- a/arch/powerpc/include/asm/mutex.h
+++ b/arch/powerpc/include/asm/mutex.h
@@ -15,7 +15,7 @@ static inline int __mutex_cmpxchg_lock(atomic_t *v, int old, int new)
15 PPC405_ERR77(0,%1) 15 PPC405_ERR77(0,%1)
16" stwcx. %3,0,%1\n\ 16" stwcx. %3,0,%1\n\
17 bne- 1b" 17 bne- 1b"
18 ISYNC_ON_SMP 18 PPC_ACQUIRE_BARRIER
19 "\n\ 19 "\n\
202:" 202:"
21 : "=&r" (t) 21 : "=&r" (t)
@@ -35,7 +35,7 @@ static inline int __mutex_dec_return_lock(atomic_t *v)
35 PPC405_ERR77(0,%1) 35 PPC405_ERR77(0,%1)
36" stwcx. %0,0,%1\n\ 36" stwcx. %0,0,%1\n\
37 bne- 1b" 37 bne- 1b"
38 ISYNC_ON_SMP 38 PPC_ACQUIRE_BARRIER
39 : "=&r" (t) 39 : "=&r" (t)
40 : "r" (&v->counter) 40 : "r" (&v->counter)
41 : "cc", "memory"); 41 : "cc", "memory");
@@ -48,7 +48,7 @@ static inline int __mutex_inc_return_unlock(atomic_t *v)
48 int t; 48 int t;
49 49
50 __asm__ __volatile__( 50 __asm__ __volatile__(
51 LWSYNC_ON_SMP 51 PPC_RELEASE_BARRIER
52"1: lwarx %0,0,%1 # mutex unlock\n\ 52"1: lwarx %0,0,%1 # mutex unlock\n\
53 addic %0,%0,1\n" 53 addic %0,%0,1\n"
54 PPC405_ERR77(0,%1) 54 PPC405_ERR77(0,%1)
diff --git a/arch/powerpc/include/asm/param.h b/arch/powerpc/include/asm/param.h
index 094f63d4d5ca..965d45427975 100644
--- a/arch/powerpc/include/asm/param.h
+++ b/arch/powerpc/include/asm/param.h
@@ -1,22 +1 @@
1#ifndef _ASM_POWERPC_PARAM_H #include <asm-generic/param.h>
2#define _ASM_POWERPC_PARAM_H
3
4#ifdef __KERNEL__
5#define HZ CONFIG_HZ /* internal kernel timer frequency */
6#define USER_HZ 100 /* for user interfaces in "ticks" */
7#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
8#endif /* __KERNEL__ */
9
10#ifndef HZ
11#define HZ 100
12#endif
13
14#define EXEC_PAGESIZE 4096
15
16#ifndef NOGROUP
17#define NOGROUP (-1)
18#endif
19
20#define MAXHOSTNAMELEN 64 /* max length of hostname */
21
22#endif /* _ASM_POWERPC_PARAM_H */
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 21207e54825b..89f158731ce3 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -209,7 +209,7 @@ extern void paging_init(void);
209 * corresponding HPTE into the hash table ahead of time, instead of 209 * corresponding HPTE into the hash table ahead of time, instead of
210 * waiting for the inevitable extra hash-table miss exception. 210 * waiting for the inevitable extra hash-table miss exception.
211 */ 211 */
212extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); 212extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
213 213
214extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr, 214extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
215 unsigned long end, int write, struct page **pages, int *nr); 215 unsigned long end, int write, struct page **pages, int *nr);
diff --git a/arch/powerpc/include/asm/pmac_feature.h b/arch/powerpc/include/asm/pmac_feature.h
index 877c35a4356e..00eedc5a4e61 100644
--- a/arch/powerpc/include/asm/pmac_feature.h
+++ b/arch/powerpc/include/asm/pmac_feature.h
@@ -378,7 +378,7 @@ extern struct macio_chip* macio_find(struct device_node* child, int type);
378 * Those are exported by pmac feature for internal use by arch code 378 * Those are exported by pmac feature for internal use by arch code
379 * only like the platform function callbacks, do not use directly in drivers 379 * only like the platform function callbacks, do not use directly in drivers
380 */ 380 */
381extern spinlock_t feature_lock; 381extern raw_spinlock_t feature_lock;
382extern struct device_node *uninorth_node; 382extern struct device_node *uninorth_node;
383extern u32 __iomem *uninorth_base; 383extern u32 __iomem *uninorth_base;
384 384
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index ef9aa84cac5a..aea714797590 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -22,8 +22,10 @@
22#define PPC_INST_DCBZL 0x7c2007ec 22#define PPC_INST_DCBZL 0x7c2007ec
23#define PPC_INST_ISEL 0x7c00001e 23#define PPC_INST_ISEL 0x7c00001e
24#define PPC_INST_ISEL_MASK 0xfc00003e 24#define PPC_INST_ISEL_MASK 0xfc00003e
25#define PPC_INST_LDARX 0x7c0000a8
25#define PPC_INST_LSWI 0x7c0004aa 26#define PPC_INST_LSWI 0x7c0004aa
26#define PPC_INST_LSWX 0x7c00042a 27#define PPC_INST_LSWX 0x7c00042a
28#define PPC_INST_LWARX 0x7c000029
27#define PPC_INST_LWSYNC 0x7c2004ac 29#define PPC_INST_LWSYNC 0x7c2004ac
28#define PPC_INST_LXVD2X 0x7c000698 30#define PPC_INST_LXVD2X 0x7c000698
29#define PPC_INST_MCRXR 0x7c000400 31#define PPC_INST_MCRXR 0x7c000400
@@ -55,15 +57,31 @@
55#define __PPC_RA(a) (((a) & 0x1f) << 16) 57#define __PPC_RA(a) (((a) & 0x1f) << 16)
56#define __PPC_RB(b) (((b) & 0x1f) << 11) 58#define __PPC_RB(b) (((b) & 0x1f) << 11)
57#define __PPC_RS(s) (((s) & 0x1f) << 21) 59#define __PPC_RS(s) (((s) & 0x1f) << 21)
60#define __PPC_RT(s) __PPC_RS(s)
58#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) 61#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
59#define __PPC_T_TLB(t) (((t) & 0x3) << 21) 62#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
60#define __PPC_WC(w) (((w) & 0x3) << 21) 63#define __PPC_WC(w) (((w) & 0x3) << 21)
64/*
65 * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have
66 * any side effects on all 32bit processors, we can do this all the time.
67 */
68#ifdef CONFIG_PPC64
69#define __PPC_EH(eh) (((eh) & 0x1) << 0)
70#else
71#define __PPC_EH(eh) 0
72#endif
61 73
62/* Deal with instructions that older assemblers aren't aware of */ 74/* Deal with instructions that older assemblers aren't aware of */
63#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ 75#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
64 __PPC_RA(a) | __PPC_RB(b)) 76 __PPC_RA(a) | __PPC_RB(b))
65#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ 77#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
66 __PPC_RA(a) | __PPC_RB(b)) 78 __PPC_RA(a) | __PPC_RB(b))
79#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
80 __PPC_RT(t) | __PPC_RA(a) | \
81 __PPC_RB(b) | __PPC_EH(eh))
82#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
83 __PPC_RT(t) | __PPC_RA(a) | \
84 __PPC_RB(b) | __PPC_EH(eh))
67#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 85#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
68 __PPC_RB(b)) 86 __PPC_RB(b))
69#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) 87#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index 2828f9d0f66d..42fdff0e4b32 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -137,6 +137,11 @@ struct device_node * find_device_pe(struct device_node *dn);
137void eeh_sysfs_add_device(struct pci_dev *pdev); 137void eeh_sysfs_add_device(struct pci_dev *pdev);
138void eeh_sysfs_remove_device(struct pci_dev *pdev); 138void eeh_sysfs_remove_device(struct pci_dev *pdev);
139 139
140static inline const char *eeh_pci_name(struct pci_dev *pdev)
141{
142 return pdev ? pci_name(pdev) : "<null>";
143}
144
140#endif /* CONFIG_EEH */ 145#endif /* CONFIG_EEH */
141 146
142#else /* CONFIG_PCI */ 147#else /* CONFIG_PCI */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 9eed29eee604..221ba6240464 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -161,9 +161,41 @@ struct thread_struct {
161#ifdef CONFIG_PPC32 161#ifdef CONFIG_PPC32
162 void *pgdir; /* root of page-table tree */ 162 void *pgdir; /* root of page-table tree */
163#endif 163#endif
164#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE) 164#ifdef CONFIG_PPC_ADV_DEBUG_REGS
165 unsigned long dbcr0; /* debug control register values */ 165 /*
166 * The following help to manage the use of Debug Control Registers
167 * om the BookE platforms.
168 */
169 unsigned long dbcr0;
166 unsigned long dbcr1; 170 unsigned long dbcr1;
171#ifdef CONFIG_BOOKE
172 unsigned long dbcr2;
173#endif
174 /*
175 * The stored value of the DBSR register will be the value at the
176 * last debug interrupt. This register can only be read from the
177 * user (will never be written to) and has value while helping to
178 * describe the reason for the last debug trap. Torez
179 */
180 unsigned long dbsr;
181 /*
182 * The following will contain addresses used by debug applications
183 * to help trace and trap on particular address locations.
184 * The bits in the Debug Control Registers above help define which
185 * of the following registers will contain valid data and/or addresses.
186 */
187 unsigned long iac1;
188 unsigned long iac2;
189#if CONFIG_PPC_ADV_DEBUG_IACS > 2
190 unsigned long iac3;
191 unsigned long iac4;
192#endif
193 unsigned long dac1;
194 unsigned long dac2;
195#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
196 unsigned long dvc1;
197 unsigned long dvc2;
198#endif
167#endif 199#endif
168 /* FP and VSX 0-31 register set */ 200 /* FP and VSX 0-31 register set */
169 double fpr[32][TS_FPRWIDTH]; 201 double fpr[32][TS_FPRWIDTH];
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 2ab9cbd98826..ddd408a93b5a 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -23,21 +23,8 @@
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <asm/atomic.h> 24#include <asm/atomic.h>
25 25
26#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1
27#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
28
29#define of_compat_cmp(s1, s2, l) strcasecmp((s1), (s2))
30#define of_prop_cmp(s1, s2) strcmp((s1), (s2))
31#define of_node_cmp(s1, s2) strcasecmp((s1), (s2))
32
33extern struct device_node *of_chosen;
34
35#define HAVE_ARCH_DEVTREE_FIXUPS 26#define HAVE_ARCH_DEVTREE_FIXUPS
36 27
37/* For updating the device tree at runtime */
38extern void of_attach_node(struct device_node *);
39extern void of_detach_node(struct device_node *);
40
41#ifdef CONFIG_PPC32 28#ifdef CONFIG_PPC32
42/* 29/*
43 * PCI <-> OF matching functions 30 * PCI <-> OF matching functions
@@ -52,11 +39,6 @@ extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
52extern void pci_create_OF_bus_map(void); 39extern void pci_create_OF_bus_map(void);
53#endif 40#endif
54 41
55extern struct resource *request_OF_resource(struct device_node* node,
56 int index, const char* name_postfix);
57extern int release_OF_resource(struct device_node* node, int index);
58
59
60/* 42/*
61 * OF address retreival & translation 43 * OF address retreival & translation
62 */ 44 */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index cbd759e3cd78..b45108126562 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -24,6 +24,12 @@
24 * 2 of the License, or (at your option) any later version. 24 * 2 of the License, or (at your option) any later version.
25 */ 25 */
26 26
27#ifdef __KERNEL__
28#include <linux/types.h>
29#else
30#include <stdint.h>
31#endif
32
27#ifndef __ASSEMBLY__ 33#ifndef __ASSEMBLY__
28 34
29struct pt_regs { 35struct pt_regs {
@@ -294,4 +300,75 @@ extern void user_disable_single_step(struct task_struct *);
294 300
295#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 301#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
296 302
303#define PPC_PTRACE_GETHWDBGINFO 0x89
304#define PPC_PTRACE_SETHWDEBUG 0x88
305#define PPC_PTRACE_DELHWDEBUG 0x87
306
307#ifndef __ASSEMBLY__
308
309struct ppc_debug_info {
310 uint32_t version; /* Only version 1 exists to date */
311 uint32_t num_instruction_bps;
312 uint32_t num_data_bps;
313 uint32_t num_condition_regs;
314 uint32_t data_bp_alignment;
315 uint32_t sizeof_condition; /* size of the DVC register */
316 uint64_t features;
317};
318
319#endif /* __ASSEMBLY__ */
320
321/*
322 * features will have bits indication whether there is support for:
323 */
324#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
325#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
326#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
327#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
328
329#ifndef __ASSEMBLY__
330
331struct ppc_hw_breakpoint {
332 uint32_t version; /* currently, version must be 1 */
333 uint32_t trigger_type; /* only some combinations allowed */
334 uint32_t addr_mode; /* address match mode */
335 uint32_t condition_mode; /* break/watchpoint condition flags */
336 uint64_t addr; /* break/watchpoint address */
337 uint64_t addr2; /* range end or mask */
338 uint64_t condition_value; /* contents of the DVC register */
339};
340
341#endif /* __ASSEMBLY__ */
342
343/*
344 * Trigger Type
345 */
346#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
347#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
348#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
349#define PPC_BREAKPOINT_TRIGGER_RW \
350 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
351
352/*
353 * Address Mode
354 */
355#define PPC_BREAKPOINT_MODE_EXACT 0x00000000
356#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
357#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
358#define PPC_BREAKPOINT_MODE_MASK 0x00000003
359
360/*
361 * Condition Mode
362 */
363#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
364#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
365#define PPC_BREAKPOINT_CONDITION_AND 0x00000001
366#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
367#define PPC_BREAKPOINT_CONDITION_OR 0x00000002
368#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
369#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
370#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
371#define PPC_BREAKPOINT_CONDITION_BE(n) \
372 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
373
297#endif /* _ASM_POWERPC_PTRACE_H */ 374#endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 3bf783505528..8808d307fe7e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -248,6 +248,8 @@
248#define DBSR_RET 0x00008000 /* Return Debug Event */ 248#define DBSR_RET 0x00008000 /* Return Debug Event */
249#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */ 249#define DBSR_CIRPT 0x00000040 /* Critical Interrupt Taken Event */
250#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */ 250#define DBSR_CRET 0x00000020 /* Critical Return Debug Event */
251#define DBSR_IAC12ATS 0x00000002 /* Instr Address Compare 1/2 Toggle */
252#define DBSR_IAC34ATS 0x00000001 /* Instr Address Compare 3/4 Toggle */
251#endif 253#endif
252#ifdef CONFIG_40x 254#ifdef CONFIG_40x
253#define DBSR_IC 0x80000000 /* Instruction Completion */ 255#define DBSR_IC 0x80000000 /* Instruction Completion */
@@ -313,6 +315,38 @@
313#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ 315#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
314#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ 316#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
315#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 317#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
318
319#define dbcr_iac_range(task) ((task)->thread.dbcr0)
320#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */
321#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
322#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
323#define DBCR_IAC34I DBCR0_IA34 /* Range Inclusive */
324#define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X) /* Range Exclusive */
325#define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X) /* IAC 3-4 Mode Bits */
326
327/* Bit definitions related to the DBCR1. */
328#define DBCR1_DAC1R 0x80000000 /* DAC1 Read Debug Event */
329#define DBCR1_DAC2R 0x40000000 /* DAC2 Read Debug Event */
330#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */
331#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */
332
333#define dbcr_dac(task) ((task)->thread.dbcr1)
334#define DBCR_DAC1R DBCR1_DAC1R
335#define DBCR_DAC1W DBCR1_DAC1W
336#define DBCR_DAC2R DBCR1_DAC2R
337#define DBCR_DAC2W DBCR1_DAC2W
338
339/*
340 * Are there any active Debug Events represented in the
341 * Debug Control Registers?
342 */
343#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
344 DBCR0_IAC3 | DBCR0_IAC4)
345#define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \
346 DBCR1_DAC1W | DBCR1_DAC2W)
347#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
348 ((dbcr1) & DBCR1_ACTIVE_EVENTS))
349
316#elif defined(CONFIG_BOOKE) 350#elif defined(CONFIG_BOOKE)
317#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 351#define DBCR0_EDM 0x80000000 /* External Debug Mode */
318#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 352#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
@@ -342,19 +376,79 @@
342#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ 376#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
343#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 377#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
344 378
379#define dbcr_dac(task) ((task)->thread.dbcr0)
380#define DBCR_DAC1R DBCR0_DAC1R
381#define DBCR_DAC1W DBCR0_DAC1W
382#define DBCR_DAC2R DBCR0_DAC2R
383#define DBCR_DAC2W DBCR0_DAC2W
384
345/* Bit definitions related to the DBCR1. */ 385/* Bit definitions related to the DBCR1. */
386#define DBCR1_IAC1US 0xC0000000 /* Instr Addr Cmp 1 Sup/User */
387#define DBCR1_IAC1ER 0x30000000 /* Instr Addr Cmp 1 Eff/Real */
388#define DBCR1_IAC1ER_01 0x10000000 /* reserved */
389#define DBCR1_IAC1ER_10 0x20000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
390#define DBCR1_IAC1ER_11 0x30000000 /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
391#define DBCR1_IAC2US 0x0C000000 /* Instr Addr Cmp 2 Sup/User */
392#define DBCR1_IAC2ER 0x03000000 /* Instr Addr Cmp 2 Eff/Real */
393#define DBCR1_IAC2ER_01 0x01000000 /* reserved */
394#define DBCR1_IAC2ER_10 0x02000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
395#define DBCR1_IAC2ER_11 0x03000000 /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
346#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */ 396#define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
347#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */ 397#define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
348#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */ 398#define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
399#define DBCR1_IAC3US 0x0000C000 /* Instr Addr Cmp 3 Sup/User */
400#define DBCR1_IAC3ER 0x00003000 /* Instr Addr Cmp 3 Eff/Real */
401#define DBCR1_IAC3ER_01 0x00001000 /* reserved */
402#define DBCR1_IAC3ER_10 0x00002000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
403#define DBCR1_IAC3ER_11 0x00003000 /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
404#define DBCR1_IAC4US 0x00000C00 /* Instr Addr Cmp 4 Sup/User */
405#define DBCR1_IAC4ER 0x00000300 /* Instr Addr Cmp 4 Eff/Real */
406#define DBCR1_IAC4ER_01 0x00000100 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
407#define DBCR1_IAC4ER_10 0x00000200 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
408#define DBCR1_IAC4ER_11 0x00000300 /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
349#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */ 409#define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
350#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ 410#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
351#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ 411#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
352 412
413#define dbcr_iac_range(task) ((task)->thread.dbcr1)
414#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */
415#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */
416#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
417#define DBCR_IAC34I DBCR1_IAC34M /* Range Inclusive */
418#define DBCR_IAC34X DBCR1_IAC34MX /* Range Exclusive */
419#define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
420
353/* Bit definitions related to the DBCR2. */ 421/* Bit definitions related to the DBCR2. */
422#define DBCR2_DAC1US 0xC0000000 /* Data Addr Cmp 1 Sup/User */
423#define DBCR2_DAC1ER 0x30000000 /* Data Addr Cmp 1 Eff/Real */
424#define DBCR2_DAC2US 0x00000000 /* Data Addr Cmp 2 Sup/User */
425#define DBCR2_DAC2ER 0x00000000 /* Data Addr Cmp 2 Eff/Real */
354#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */ 426#define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
427#define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
355#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */ 428#define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
429#define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
356#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */ 430#define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
357#endif 431#define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */
432#define DBCR2_DVC1M_SHIFT 18 /* # of bits to shift DBCR2_DVC1M */
433#define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */
434#define DBCR2_DVC2M_SHIFT 16 /* # of bits to shift DBCR2_DVC2M */
435#define DBCR2_DVC1BE 0x00000F00 /* Data Value Comp 1 Byte */
436#define DBCR2_DVC1BE_SHIFT 8 /* # of bits to shift DBCR2_DVC1BE */
437#define DBCR2_DVC2BE 0x0000000F /* Data Value Comp 2 Byte */
438#define DBCR2_DVC2BE_SHIFT 0 /* # of bits to shift DBCR2_DVC2BE */
439
440/*
441 * Are there any active Debug Events represented in the
442 * Debug Control Registers?
443 */
444#define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
445 DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
446 DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)
447#define DBCR1_ACTIVE_EVENTS 0
448
449#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
450 ((dbcr1) & DBCR1_ACTIVE_EVENTS))
451#endif /* #elif defined(CONFIG_BOOKE) */
358 452
359/* Bit definitions related to the TCR. */ 453/* Bit definitions related to the TCR. */
360#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ 454#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index 764094cff681..f9611bd69ed2 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -27,6 +27,7 @@
27#endif 27#endif
28#include <asm/asm-compat.h> 28#include <asm/asm-compat.h>
29#include <asm/synch.h> 29#include <asm/synch.h>
30#include <asm/ppc-opcode.h>
30 31
31#define arch_spin_is_locked(x) ((x)->slock != 0) 32#define arch_spin_is_locked(x) ((x)->slock != 0)
32 33
@@ -60,13 +61,14 @@ static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
60 61
61 token = LOCK_TOKEN; 62 token = LOCK_TOKEN;
62 __asm__ __volatile__( 63 __asm__ __volatile__(
63"1: lwarx %0,0,%2\n\ 64"1: " PPC_LWARX(%0,0,%2,1) "\n\
64 cmpwi 0,%0,0\n\ 65 cmpwi 0,%0,0\n\
65 bne- 2f\n\ 66 bne- 2f\n\
66 stwcx. %1,0,%2\n\ 67 stwcx. %1,0,%2\n\
67 bne- 1b\n\ 68 bne- 1b\n"
68 isync\n\ 69 PPC_ACQUIRE_BARRIER
692:" : "=&r" (tmp) 70"2:"
71 : "=&r" (tmp)
70 : "r" (token), "r" (&lock->slock) 72 : "r" (token), "r" (&lock->slock)
71 : "cr0", "memory"); 73 : "cr0", "memory");
72 74
@@ -144,7 +146,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
144{ 146{
145 SYNC_IO; 147 SYNC_IO;
146 __asm__ __volatile__("# arch_spin_unlock\n\t" 148 __asm__ __volatile__("# arch_spin_unlock\n\t"
147 LWSYNC_ON_SMP: : :"memory"); 149 PPC_RELEASE_BARRIER: : :"memory");
148 lock->slock = 0; 150 lock->slock = 0;
149} 151}
150 152
@@ -186,15 +188,15 @@ static inline long __arch_read_trylock(arch_rwlock_t *rw)
186 long tmp; 188 long tmp;
187 189
188 __asm__ __volatile__( 190 __asm__ __volatile__(
189"1: lwarx %0,0,%1\n" 191"1: " PPC_LWARX(%0,0,%1,1) "\n"
190 __DO_SIGN_EXTEND 192 __DO_SIGN_EXTEND
191" addic. %0,%0,1\n\ 193" addic. %0,%0,1\n\
192 ble- 2f\n" 194 ble- 2f\n"
193 PPC405_ERR77(0,%1) 195 PPC405_ERR77(0,%1)
194" stwcx. %0,0,%1\n\ 196" stwcx. %0,0,%1\n\
195 bne- 1b\n\ 197 bne- 1b\n"
196 isync\n\ 198 PPC_ACQUIRE_BARRIER
1972:" : "=&r" (tmp) 199"2:" : "=&r" (tmp)
198 : "r" (&rw->lock) 200 : "r" (&rw->lock)
199 : "cr0", "xer", "memory"); 201 : "cr0", "xer", "memory");
200 202
@@ -211,14 +213,14 @@ static inline long __arch_write_trylock(arch_rwlock_t *rw)
211 213
212 token = WRLOCK_TOKEN; 214 token = WRLOCK_TOKEN;
213 __asm__ __volatile__( 215 __asm__ __volatile__(
214"1: lwarx %0,0,%2\n\ 216"1: " PPC_LWARX(%0,0,%2,1) "\n\
215 cmpwi 0,%0,0\n\ 217 cmpwi 0,%0,0\n\
216 bne- 2f\n" 218 bne- 2f\n"
217 PPC405_ERR77(0,%1) 219 PPC405_ERR77(0,%1)
218" stwcx. %1,0,%2\n\ 220" stwcx. %1,0,%2\n\
219 bne- 1b\n\ 221 bne- 1b\n"
220 isync\n\ 222 PPC_ACQUIRE_BARRIER
2212:" : "=&r" (tmp) 223"2:" : "=&r" (tmp)
222 : "r" (token), "r" (&rw->lock) 224 : "r" (token), "r" (&rw->lock)
223 : "cr0", "memory"); 225 : "cr0", "memory");
224 226
@@ -269,7 +271,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
269 271
270 __asm__ __volatile__( 272 __asm__ __volatile__(
271 "# read_unlock\n\t" 273 "# read_unlock\n\t"
272 LWSYNC_ON_SMP 274 PPC_RELEASE_BARRIER
273"1: lwarx %0,0,%1\n\ 275"1: lwarx %0,0,%1\n\
274 addic %0,%0,-1\n" 276 addic %0,%0,-1\n"
275 PPC405_ERR77(0,%1) 277 PPC405_ERR77(0,%1)
@@ -283,7 +285,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
283static inline void arch_write_unlock(arch_rwlock_t *rw) 285static inline void arch_write_unlock(arch_rwlock_t *rw)
284{ 286{
285 __asm__ __volatile__("# write_unlock\n\t" 287 __asm__ __volatile__("# write_unlock\n\t"
286 LWSYNC_ON_SMP: : :"memory"); 288 PPC_RELEASE_BARRIER: : :"memory");
287 rw->lock = 0; 289 rw->lock = 0;
288} 290}
289 291
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
index 28f6ddbff4cf..d7cab44643c5 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch.h
@@ -37,11 +37,15 @@ static inline void isync(void)
37#endif 37#endif
38 38
39#ifdef CONFIG_SMP 39#ifdef CONFIG_SMP
40#define ISYNC_ON_SMP "\n\tisync\n" 40#define __PPC_ACQUIRE_BARRIER \
41#define LWSYNC_ON_SMP stringify_in_c(LWSYNC) "\n" 41 START_LWSYNC_SECTION(97); \
42 isync; \
43 MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
44#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
45#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
42#else 46#else
43#define ISYNC_ON_SMP 47#define PPC_ACQUIRE_BARRIER
44#define LWSYNC_ON_SMP 48#define PPC_RELEASE_BARRIER
45#endif 49#endif
46 50
47#endif /* __KERNEL__ */ 51#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index bb8e006a47c6..a6297c67c3d6 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -112,8 +112,13 @@ static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
112#endif 112#endif
113 113
114extern int set_dabr(unsigned long dabr); 114extern int set_dabr(unsigned long dabr);
115#ifdef CONFIG_PPC_ADV_DEBUG_REGS
116extern void do_send_trap(struct pt_regs *regs, unsigned long address,
117 unsigned long error_code, int signal_code, int brkpt);
118#else
115extern void do_dabr(struct pt_regs *regs, unsigned long address, 119extern void do_dabr(struct pt_regs *regs, unsigned long address,
116 unsigned long error_code); 120 unsigned long error_code);
121#endif
117extern void print_backtrace(unsigned long *); 122extern void print_backtrace(unsigned long *);
118extern void show_regs(struct pt_regs * regs); 123extern void show_regs(struct pt_regs * regs);
119extern void flush_instruction_cache(void); 124extern void flush_instruction_cache(void);
@@ -232,12 +237,12 @@ __xchg_u32(volatile void *p, unsigned long val)
232 unsigned long prev; 237 unsigned long prev;
233 238
234 __asm__ __volatile__( 239 __asm__ __volatile__(
235 LWSYNC_ON_SMP 240 PPC_RELEASE_BARRIER
236"1: lwarx %0,0,%2 \n" 241"1: lwarx %0,0,%2 \n"
237 PPC405_ERR77(0,%2) 242 PPC405_ERR77(0,%2)
238" stwcx. %3,0,%2 \n\ 243" stwcx. %3,0,%2 \n\
239 bne- 1b" 244 bne- 1b"
240 ISYNC_ON_SMP 245 PPC_ACQUIRE_BARRIER
241 : "=&r" (prev), "+m" (*(volatile unsigned int *)p) 246 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
242 : "r" (p), "r" (val) 247 : "r" (p), "r" (val)
243 : "cc", "memory"); 248 : "cc", "memory");
@@ -275,12 +280,12 @@ __xchg_u64(volatile void *p, unsigned long val)
275 unsigned long prev; 280 unsigned long prev;
276 281
277 __asm__ __volatile__( 282 __asm__ __volatile__(
278 LWSYNC_ON_SMP 283 PPC_RELEASE_BARRIER
279"1: ldarx %0,0,%2 \n" 284"1: ldarx %0,0,%2 \n"
280 PPC405_ERR77(0,%2) 285 PPC405_ERR77(0,%2)
281" stdcx. %3,0,%2 \n\ 286" stdcx. %3,0,%2 \n\
282 bne- 1b" 287 bne- 1b"
283 ISYNC_ON_SMP 288 PPC_ACQUIRE_BARRIER
284 : "=&r" (prev), "+m" (*(volatile unsigned long *)p) 289 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
285 : "r" (p), "r" (val) 290 : "r" (p), "r" (val)
286 : "cc", "memory"); 291 : "cc", "memory");
@@ -366,14 +371,14 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
366 unsigned int prev; 371 unsigned int prev;
367 372
368 __asm__ __volatile__ ( 373 __asm__ __volatile__ (
369 LWSYNC_ON_SMP 374 PPC_RELEASE_BARRIER
370"1: lwarx %0,0,%2 # __cmpxchg_u32\n\ 375"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
371 cmpw 0,%0,%3\n\ 376 cmpw 0,%0,%3\n\
372 bne- 2f\n" 377 bne- 2f\n"
373 PPC405_ERR77(0,%2) 378 PPC405_ERR77(0,%2)
374" stwcx. %4,0,%2\n\ 379" stwcx. %4,0,%2\n\
375 bne- 1b" 380 bne- 1b"
376 ISYNC_ON_SMP 381 PPC_ACQUIRE_BARRIER
377 "\n\ 382 "\n\
3782:" 3832:"
379 : "=&r" (prev), "+m" (*p) 384 : "=&r" (prev), "+m" (*p)
@@ -412,13 +417,13 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
412 unsigned long prev; 417 unsigned long prev;
413 418
414 __asm__ __volatile__ ( 419 __asm__ __volatile__ (
415 LWSYNC_ON_SMP 420 PPC_RELEASE_BARRIER
416"1: ldarx %0,0,%2 # __cmpxchg_u64\n\ 421"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
417 cmpd 0,%0,%3\n\ 422 cmpd 0,%0,%3\n\
418 bne- 2f\n\ 423 bne- 2f\n\
419 stdcx. %4,0,%2\n\ 424 stdcx. %4,0,%2\n\
420 bne- 1b" 425 bne- 1b"
421 ISYNC_ON_SMP 426 PPC_ACQUIRE_BARRIER
422 "\n\ 427 "\n\
4232:" 4282:"
424 : "=&r" (prev), "+m" (*p) 429 : "=&r" (prev), "+m" (*p)
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index bbf89701d7a4..8eaec310a25b 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -38,27 +38,33 @@ static inline int pcibus_to_node(struct pci_bus *bus)
38 cpumask_of_node(pcibus_to_node(bus))) 38 cpumask_of_node(pcibus_to_node(bus)))
39 39
40/* sched_domains SD_NODE_INIT for PPC64 machines */ 40/* sched_domains SD_NODE_INIT for PPC64 machines */
41#define SD_NODE_INIT (struct sched_domain) { \ 41#define SD_NODE_INIT (struct sched_domain) { \
42 .parent = NULL, \ 42 .min_interval = 8, \
43 .child = NULL, \ 43 .max_interval = 32, \
44 .groups = NULL, \ 44 .busy_factor = 32, \
45 .min_interval = 8, \ 45 .imbalance_pct = 125, \
46 .max_interval = 32, \ 46 .cache_nice_tries = 1, \
47 .busy_factor = 32, \ 47 .busy_idx = 3, \
48 .imbalance_pct = 125, \ 48 .idle_idx = 1, \
49 .cache_nice_tries = 1, \ 49 .newidle_idx = 0, \
50 .busy_idx = 3, \ 50 .wake_idx = 0, \
51 .idle_idx = 1, \ 51 .forkexec_idx = 0, \
52 .newidle_idx = 0, \ 52 \
53 .wake_idx = 0, \ 53 .flags = 1*SD_LOAD_BALANCE \
54 .flags = SD_LOAD_BALANCE \ 54 | 1*SD_BALANCE_NEWIDLE \
55 | SD_BALANCE_EXEC \ 55 | 1*SD_BALANCE_EXEC \
56 | SD_BALANCE_FORK \ 56 | 1*SD_BALANCE_FORK \
57 | SD_BALANCE_NEWIDLE \ 57 | 0*SD_BALANCE_WAKE \
58 | SD_SERIALIZE, \ 58 | 0*SD_WAKE_AFFINE \
59 .last_balance = jiffies, \ 59 | 0*SD_PREFER_LOCAL \
60 .balance_interval = 1, \ 60 | 0*SD_SHARE_CPUPOWER \
61 .nr_balance_failed = 0, \ 61 | 0*SD_POWERSAVINGS_BALANCE \
62 | 0*SD_SHARE_PKG_RESOURCES \
63 | 1*SD_SERIALIZE \
64 | 0*SD_PREFER_SIBLING \
65 , \
66 .last_balance = jiffies, \
67 .balance_interval = 1, \
62} 68}
63 69
64extern void __init dump_numa_cpu_topology(void); 70extern void __init dump_numa_cpu_topology(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 17:25:09 -0400