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Diffstat (limited to 'arch/powerpc/boot/dts/uc101.dts')
-rw-r--r--arch/powerpc/boot/dts/uc101.dts160
1 files changed, 33 insertions, 127 deletions
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
index e00441a3e5a7..ba83d5488ec6 100644
--- a/arch/powerpc/boot/dts/uc101.dts
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -11,79 +11,24 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "manroland,uc101"; 17 model = "manroland,uc101";
18 compatible = "manroland,uc101"; 18 compatible = "manroland,uc101";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44 19
45 soc5200@f0000000 { 20 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // General Purpose Timer in GPIO mode 21 gpt0: timer@600 { // General Purpose Timer in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller; 22 gpio-controller;
72 #gpio-cells = <2>; 23 #gpio-cells = <2>;
73 }; 24 };
74 25
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode 26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller; 27 gpio-controller;
80 #gpio-cells = <2>; 28 #gpio-cells = <2>;
81 }; 29 };
82 30
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode 31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller; 32 gpio-controller;
88 #gpio-cells = <2>; 33 #gpio-cells = <2>;
89 }; 34 };
@@ -97,118 +42,85 @@
97 }; 42 };
98 43
99 gpt4: timer@640 { // General Purpose Timer in GPIO mode 44 gpt4: timer@640 { // General Purpose Timer in GPIO mode
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 reg = <0x640 0x10>;
102 interrupts = <1 13 0>;
103 gpio-controller; 45 gpio-controller;
104 #gpio-cells = <2>; 46 #gpio-cells = <2>;
105 }; 47 };
106 48
107 gpt5: timer@650 { // General Purpose Timer in GPIO mode 49 gpt5: timer@650 { // General Purpose Timer in GPIO mode
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 gpio-controller; 50 gpio-controller;
112 #gpio-cells = <2>; 51 #gpio-cells = <2>;
113 }; 52 };
114 53
115 gpt6: timer@660 { // General Purpose Timer in GPIO mode 54 gpt6: timer@660 { // General Purpose Timer in GPIO mode
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x660 0x10>;
118 interrupts = <1 15 0>;
119 gpio-controller; 55 gpio-controller;
120 #gpio-cells = <2>; 56 #gpio-cells = <2>;
121 }; 57 };
122 58
123 gpt7: timer@670 { // General Purpose Timer in GPIO mode 59 gpt7: timer@670 { // General Purpose Timer in GPIO mode
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 reg = <0x670 0x10>;
126 interrupts = <1 16 0>;
127 gpio-controller; 60 gpio-controller;
128 #gpio-cells = <2>; 61 #gpio-cells = <2>;
129 }; 62 };
130 63
131 gpio_simple: gpio@b00 { 64 rtc@800 {
132 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 65 status = "disabled";
133 reg = <0xb00 0x40>;
134 interrupts = <1 7 0>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 }; 66 };
138 67
139 gpio_wkup: gpio@c00 { 68 can@900 {
140 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 69 status = "disabled";
141 reg = <0xc00 0x40>; 70 };
142 interrupts = <1 8 0 0 3 0>; 71
143 gpio-controller; 72 can@980 {
144 #gpio-cells = <2>; 73 status = "disabled";
145 }; 74 };
146 75
147 dma-controller@1200 { 76 spi@f00 {
148 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 77 status = "disabled";
149 reg = <0x1200 0x80>;
150 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
151 3 4 0 3 5 0 3 6 0 3 7 0
152 3 8 0 3 9 0 3 10 0 3 11 0
153 3 12 0 3 13 0 3 14 0 3 15 0>;
154 }; 78 };
155 79
156 xlb@1f00 { 80 usb@1000 {
157 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 81 status = "disabled";
158 reg = <0x1f00 0x100>;
159 }; 82 };
160 83
161 psc@2000 { /* PSC1 in UART mode */ 84 psc@2000 { // PSC1
162 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 85 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
163 reg = <0x2000 0x100>;
164 interrupts = <2 1 0>;
165 }; 86 };
166 87
167 psc@2200 { /* PSC2 in UART mode */ 88 psc@2200 { // PSC2
168 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 89 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
169 reg = <0x2200 0x100>;
170 interrupts = <2 2 0>;
171 }; 90 };
172 91
173 psc@2c00 { /* PSC6 in UART mode */ 92 psc@2400 { // PSC3
93 status = "disabled";
94 };
95
96 psc@2600 { // PSC4
97 status = "disabled";
98 };
99
100 psc@2800 { // PSC5
101 status = "disabled";
102 };
103
104 psc@2c00 { // PSC6
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 105 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 reg = <0x2c00 0x100>;
176 interrupts = <2 4 0>;
177 }; 106 };
178 107
179 ethernet@3000 { 108 ethernet@3000 {
180 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
181 reg = <0x3000 0x400>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <2 5 0>;
184 phy-handle = <&phy0>; 109 phy-handle = <&phy0>;
185 }; 110 };
186 111
187 mdio@3000 { 112 mdio@3000 {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
191 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
192 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
193
194 phy0: ethernet-phy@0 { 113 phy0: ethernet-phy@0 {
195 compatible = "intel,lxt971"; 114 compatible = "intel,lxt971";
196 reg = <0>; 115 reg = <0>;
197 }; 116 };
198 }; 117 };
199 118
200 ata@3a00 { 119 i2c@3d00 {
201 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 120 status = "disabled";
202 reg = <0x3a00 0x100>;
203 interrupts = <2 7 0>;
204 }; 121 };
205 122
206 i2c@3d40 { 123 i2c@3d40 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
210 reg = <0x3d40 0x40>;
211 interrupts = <2 16 0>;
212 fsl,preserve-clocking; 124 fsl,preserve-clocking;
213 clock-frequency = <400000>; 125 clock-frequency = <400000>;
214 126
@@ -221,19 +133,13 @@
221 reg = <0x51>; 133 reg = <0x51>;
222 }; 134 };
223 }; 135 };
136 };
224 137
225 sram@8000 { 138 pci@f0000d00 {
226 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 139 status = "disabled";
227 reg = <0x8000 0x4000>;
228 };
229 }; 140 };
230 141
231 localbus { 142 localbus {
232 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
233
234 #address-cells = <2>;
235 #size-cells = <1>;
236
237 ranges = <0 0 0xff800000 0x00800000 143 ranges = <0 0 0xff800000 0x00800000
238 1 0 0x80000000 0x00800000 144 1 0 0x80000000 0x00800000
239 3 0 0x80000000 0x00800000>; 145 3 0 0x80000000 0x00800000>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 21:59:22 -0500