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-rw-r--r--arch/powerpc/boot/dts/cm5200.dts192
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts173
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts217
-rw-r--r--arch/powerpc/boot/dts/media5200.dts210
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts190
-rw-r--r--arch/powerpc/boot/dts/mpc5200b.dtsi275
-rw-r--r--arch/powerpc/boot/dts/mucmc52.dts174
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts187
-rw-r--r--arch/powerpc/boot/dts/pcm032.dts231
-rw-r--r--arch/powerpc/boot/dts/uc101.dts160
10 files changed, 506 insertions, 1503 deletions
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 22f7233414ba..ad3a4f4a2b04 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -10,226 +10,82 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "schindler,cm5200"; 16 model = "schindler,cm5200";
17 compatible = "schindler,cm5200"; 17 compatible = "schindler,cm5200";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x04000000>; // 64MB
42 };
43 18
44 soc5200@f0000000 { 19 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 20 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 21 fsl,has-wdt;
71 }; 22 };
72 23
73 timer@610 { // General Purpose Timer 24 can@900 {
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 25 status = "disabled";
75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
107 };
108
109 timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
113 };
114
115 rtc@800 { // Real time clock
116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117 reg = <0x800 0x100>;
118 interrupts = <1 5 0 1 6 0>;
119 }; 26 };
120 27
121 gpio_simple: gpio@b00 { 28 can@980 {
122 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 29 status = "disabled";
123 reg = <0xb00 0x40>;
124 interrupts = <1 7 0>;
125 gpio-controller;
126 #gpio-cells = <2>;
127 };
128
129 gpio_wkup: gpio@c00 {
130 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
131 reg = <0xc00 0x40>;
132 interrupts = <1 8 0 0 3 0>;
133 gpio-controller;
134 #gpio-cells = <2>;
135 };
136
137 spi@f00 {
138 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
139 reg = <0xf00 0x20>;
140 interrupts = <2 13 0 2 14 0>;
141 };
142
143 usb@1000 {
144 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
145 reg = <0x1000 0xff>;
146 interrupts = <2 6 0>;
147 };
148
149 dma-controller@1200 {
150 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
151 reg = <0x1200 0x80>;
152 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
153 3 4 0 3 5 0 3 6 0 3 7 0
154 3 8 0 3 9 0 3 10 0 3 11 0
155 3 12 0 3 13 0 3 14 0 3 15 0>;
156 };
157
158 xlb@1f00 {
159 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
160 reg = <0x1f00 0x100>;
161 }; 30 };
162 31
163 psc@2000 { // PSC1 32 psc@2000 { // PSC1
164 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 33 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
165 reg = <0x2000 0x100>;
166 interrupts = <2 1 0>;
167 }; 34 };
168 35
169 psc@2200 { // PSC2 36 psc@2200 { // PSC2
170 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 37 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
171 reg = <0x2200 0x100>;
172 interrupts = <2 2 0>;
173 }; 38 };
174 39
175 psc@2400 { // PSC3 40 psc@2400 { // PSC3
176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 41 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
177 reg = <0x2400 0x100>; 42 };
178 interrupts = <2 3 0>; 43
44 psc@2600 { // PSC4
45 status = "disabled";
46 };
47
48 psc@2800 { // PSC5
49 status = "disabled";
179 }; 50 };
180 51
181 psc@2c00 { // PSC6 52 psc@2c00 { // PSC6
182 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 53 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183 reg = <0x2c00 0x100>;
184 interrupts = <2 4 0>;
185 }; 54 };
186 55
187 ethernet@3000 { 56 ethernet@3000 {
188 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
189 reg = <0x3000 0x400>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <2 5 0>;
192 phy-handle = <&phy0>; 57 phy-handle = <&phy0>;
193 }; 58 };
194 59
195 mdio@3000 { 60 mdio@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
199 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
200 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
201
202 phy0: ethernet-phy@0 { 61 phy0: ethernet-phy@0 {
203 reg = <0>; 62 reg = <0>;
204 }; 63 };
205 }; 64 };
206 65
207 i2c@3d40 { 66 ata@3a00 {
208 #address-cells = <1>; 67 status = "disabled";
209 #size-cells = <0>;
210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
211 reg = <0x3d40 0x40>;
212 interrupts = <2 16 0>;
213 }; 68 };
214 69
215 sram@8000 { 70 i2c@3d00 {
216 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 71 status = "disabled";
217 reg = <0x8000 0x4000>;
218 }; 72 };
73
219 }; 74 };
220 75
221 localbus { 76 pci@f0000d00 {
222 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; 77 status = "disabled";
223 #address-cells = <2>; 78 };
224 #size-cells = <1>;
225 ranges = <0 0 0xfc000000 0x2000000>;
226 79
80 localbus {
227 // 16-bit flash device at LocalPlus Bus CS0 81 // 16-bit flash device at LocalPlus Bus CS0
228 flash@0,0 { 82 flash@0,0 {
229 compatible = "cfi-flash"; 83 compatible = "cfi-flash";
230 reg = <0 0 0x2000000>; 84 reg = <0 0 0x2000000>;
231 bank-width = <2>; 85 bank-width = <2>;
232 device-width = <2>; 86 device-width = <2>;
87 #size-cells = <1>;
88 #address-cells = <1>;
233 }; 89 };
234 }; 90 };
235}; 91};
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index 3147b9894205..27bd267d631c 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -11,195 +11,68 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "intercontrol,digsy-mtc"; 17 model = "intercontrol,digsy-mtc";
18 compatible = "intercontrol,digsy-mtc"; 18 compatible = "intercontrol,digsy-mtc";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39 19
40 memory { 20 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x02000000>; // 32MB 21 reg = <0x00000000 0x02000000>; // 32MB
43 }; 22 };
44 23
45 soc5200@f0000000 { 24 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer 25 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt; 26 fsl,has-wdt;
72 }; 27 };
73 28
74 timer@610 { // General Purpose Timer 29 rtc@800 {
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 30 status = "disabled";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 };
85
86 timer@630 { // General Purpose Timer
87 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
88 reg = <0x630 0x10>;
89 interrupts = <1 12 0>;
90 };
91
92 timer@640 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 reg = <0x640 0x10>;
95 interrupts = <1 13 0>;
96 };
97
98 timer@650 { // General Purpose Timer
99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 reg = <0x650 0x10>;
101 interrupts = <1 14 0>;
102 };
103
104 timer@660 { // General Purpose Timer
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 };
109
110 timer@670 { // General Purpose Timer
111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
112 reg = <0x670 0x10>;
113 interrupts = <1 16 0>;
114 };
115
116 gpio_simple: gpio@b00 {
117 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
118 reg = <0xb00 0x40>;
119 interrupts = <1 7 0>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 }; 31 };
123 32
124 gpio_wkup: gpio@c00 { 33 can@900 {
125 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 34 status = "disabled";
126 reg = <0xc00 0x40>;
127 interrupts = <1 8 0 0 3 0>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 }; 35 };
131 36
132 spi@f00 { 37 can@980 {
133 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 38 status = "disabled";
134 reg = <0xf00 0x20>;
135 interrupts = <2 13 0 2 14 0>;
136 }; 39 };
137 40
138 usb@1000 { 41 psc@2000 { // PSC1
139 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 42 status = "disabled";
140 reg = <0x1000 0xff>;
141 interrupts = <2 6 0>;
142 }; 43 };
143 44
144 dma-controller@1200 { 45 psc@2200 { // PSC2
145 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 46 status = "disabled";
146 reg = <0x1200 0x80>;
147 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
148 3 4 0 3 5 0 3 6 0 3 7 0
149 3 8 0 3 9 0 3 10 0 3 11 0
150 3 12 0 3 13 0 3 14 0 3 15 0>;
151 }; 47 };
152 48
153 xlb@1f00 { 49 psc@2400 { // PSC3
154 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 50 status = "disabled";
155 reg = <0x1f00 0x100>;
156 }; 51 };
157 52
158 psc@2600 { // PSC4 53 psc@2600 { // PSC4
159 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
160 reg = <0x2600 0x100>;
161 interrupts = <2 11 0>;
162 }; 55 };
163 56
164 psc@2800 { // PSC5 57 psc@2800 { // PSC5
165 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
166 reg = <0x2800 0x100>; 59 };
167 interrupts = <2 12 0>; 60
61 psc@2c00 { // PSC6
62 status = "disabled";
168 }; 63 };
169 64
170 ethernet@3000 { 65 ethernet@3000 {
171 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
172 reg = <0x3000 0x400>;
173 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupts = <2 5 0>;
175 phy-handle = <&phy0>; 66 phy-handle = <&phy0>;
176 }; 67 };
177 68
178 mdio@3000 { 69 mdio@3000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
182 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
183 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
184
185 phy0: ethernet-phy@0 { 70 phy0: ethernet-phy@0 {
186 reg = <0>; 71 reg = <0>;
187 }; 72 };
188 }; 73 };
189 74
190 ata@3a00 {
191 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
192 reg = <0x3a00 0x100>;
193 interrupts = <2 7 0>;
194 };
195
196 i2c@3d00 { 75 i2c@3d00 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
200 reg = <0x3d00 0x40>;
201 interrupts = <2 15 0>;
202
203 rtc@50 { 76 rtc@50 {
204 compatible = "at,24c08"; 77 compatible = "at,24c08";
205 reg = <0x50>; 78 reg = <0x50>;
@@ -211,16 +84,16 @@
211 }; 84 };
212 }; 85 };
213 86
214 sram@8000 { 87 i2c@3d40 {
215 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 88 status = "disabled";
216 reg = <0x8000 0x4000>;
217 }; 89 };
218 }; 90 };
219 91
92 pci@f0000d00 {
93 status = "disabled";
94 };
95
220 localbus { 96 localbus {
221 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
222 #address-cells = <2>;
223 #size-cells = <1>;
224 ranges = <0 0 0xff000000 0x1000000>; 97 ranges = <0 0 0xff000000 0x1000000>;
225 98
226 // 16-bit flash device at LocalPlus Bus CS0 99 // 16-bit flash device at LocalPlus Bus CS0
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index c0a4e4592baa..fb288bb882b6 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -10,253 +10,75 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "fsl,lite5200b"; 16 model = "fsl,lite5200b";
17 compatible = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38 18
39 memory { 19 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x10000000>; // 256MB 20 reg = <0x00000000 0x10000000>; // 256MB
42 }; 21 };
43 22
44 soc5200@f0000000 { 23 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 24 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 25 fsl,has-wdt;
71 }; 26 };
72 27
73 timer@610 { // General Purpose Timer 28 psc@2000 { // PSC1
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 29 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
75 reg = <0x610 0x10>; 30 cell-index = <0>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
107 };
108
109 timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
113 };
114
115 rtc@800 { // Real time clock
116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117 reg = <0x800 0x100>;
118 interrupts = <1 5 0 1 6 0>;
119 };
120
121 can@900 {
122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
123 interrupts = <2 17 0>;
124 reg = <0x900 0x80>;
125 };
126
127 can@980 {
128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
129 interrupts = <2 18 0>;
130 reg = <0x980 0x80>;
131 };
132
133 gpio_simple: gpio@b00 {
134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
135 reg = <0xb00 0x40>;
136 interrupts = <1 7 0>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 gpio_wkup: gpio@c00 {
142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
143 reg = <0xc00 0x40>;
144 interrupts = <1 8 0 0 3 0>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 }; 31 };
148 32
149 spi@f00 { 33 psc@2200 { // PSC2
150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 34 status = "disabled";
151 reg = <0xf00 0x20>;
152 interrupts = <2 13 0 2 14 0>;
153 }; 35 };
154 36
155 usb@1000 { 37 psc@2400 { // PSC3
156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 38 status = "disabled";
157 reg = <0x1000 0xff>;
158 interrupts = <2 6 0>;
159 }; 39 };
160 40
161 dma-controller@1200 { 41 psc@2600 { // PSC4
162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 42 status = "disabled";
163 reg = <0x1200 0x80>;
164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
165 3 4 0 3 5 0 3 6 0 3 7 0
166 3 8 0 3 9 0 3 10 0 3 11 0
167 3 12 0 3 13 0 3 14 0 3 15 0>;
168 }; 43 };
169 44
170 xlb@1f00 { 45 psc@2800 { // PSC5
171 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 46 status = "disabled";
172 reg = <0x1f00 0x100>;
173 }; 47 };
174 48
175 psc@2000 { // PSC1 49 psc@2c00 { // PSC6
176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 50 status = "disabled";
177 reg = <0x2000 0x100>;
178 interrupts = <2 1 0>;
179 }; 51 };
180 52
181 // PSC2 in ac97 mode example 53 // PSC2 in ac97 mode example
182 //ac97@2200 { // PSC2 54 //ac97@2200 { // PSC2
183 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 55 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
184 // cell-index = <1>; 56 // cell-index = <1>;
185 // reg = <0x2200 0x100>;
186 // interrupts = <2 2 0>;
187 //}; 57 //};
188 58
189 // PSC3 in CODEC mode example 59 // PSC3 in CODEC mode example
190 //i2s@2400 { // PSC3 60 //i2s@2400 { // PSC3
191 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible 61 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
192 // cell-index = <2>; 62 // cell-index = <2>;
193 // reg = <0x2400 0x100>;
194 // interrupts = <2 3 0>;
195 //};
196
197 // PSC4 in uart mode example
198 //serial@2600 { // PSC4
199 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
200 // reg = <0x2600 0x100>;
201 // interrupts = <2 11 0>;
202 //};
203
204 // PSC5 in uart mode example
205 //serial@2800 { // PSC5
206 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
207 // reg = <0x2800 0x100>;
208 // interrupts = <2 12 0>;
209 //}; 63 //};
210 64
211 // PSC6 in spi mode example 65 // PSC6 in spi mode example
212 //spi@2c00 { // PSC6 66 //spi@2c00 { // PSC6
213 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 67 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
214 // cell-index = <5>; 68 // cell-index = <5>;
215 // reg = <0x2c00 0x100>;
216 // interrupts = <2 4 0>;
217 //}; 69 //};
218 70
219 ethernet@3000 { 71 ethernet@3000 {
220 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
221 reg = <0x3000 0x400>;
222 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <2 5 0>;
224 phy-handle = <&phy0>; 72 phy-handle = <&phy0>;
225 }; 73 };
226 74
227 mdio@3000 { 75 mdio@3000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
231 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
232 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
233
234 phy0: ethernet-phy@0 { 76 phy0: ethernet-phy@0 {
235 reg = <0>; 77 reg = <0>;
236 }; 78 };
237 }; 79 };
238 80
239 ata@3a00 {
240 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
241 reg = <0x3a00 0x100>;
242 interrupts = <2 7 0>;
243 };
244
245 i2c@3d00 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
249 reg = <0x3d00 0x40>;
250 interrupts = <2 15 0>;
251 };
252
253 i2c@3d40 { 81 i2c@3d40 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
257 reg = <0x3d40 0x40>;
258 interrupts = <2 16 0>;
259
260 eeprom@50 { 82 eeprom@50 {
261 compatible = "atmel,24c02"; 83 compatible = "atmel,24c02";
262 reg = <0x50>; 84 reg = <0x50>;
@@ -270,12 +92,6 @@
270 }; 92 };
271 93
272 pci@f0000d00 { 94 pci@f0000d00 {
273 #interrupt-cells = <1>;
274 #size-cells = <2>;
275 #address-cells = <3>;
276 device_type = "pci";
277 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
278 reg = <0xf0000d00 0x100>;
279 interrupt-map-mask = <0xf800 0 0 7>; 95 interrupt-map-mask = <0xf800 0 0 7>;
280 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 96 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
281 0xc000 0 0 2 &mpc5200_pic 1 1 3 97 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -295,11 +111,6 @@
295 }; 111 };
296 112
297 localbus { 113 localbus {
298 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
299
300 #address-cells = <2>;
301 #size-cells = <1>;
302
303 ranges = <0 0 0xfe000000 0x02000000>; 114 ranges = <0 0 0xfe000000 0x02000000>;
304 115
305 flash@0,0 { 116 flash@0,0 {
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index 861f09ff3a7f..48d72f38e5ed 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -11,14 +11,11 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "fsl,media5200"; 17 model = "fsl,media5200";
18 compatible = "fsl,media5200"; 18 compatible = "fsl,media5200";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22 19
23 aliases { 20 aliases {
24 console = &console; 21 console = &console;
@@ -30,16 +27,7 @@
30 }; 27 };
31 28
32 cpus { 29 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5200@0 { 30 PowerPC,5200@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <0x4000>; // L1, 16K
42 i-cache-size = <0x4000>; // L1, 16K
43 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot 31 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
44 bus-frequency = <132000000>; // 132 MHz 32 bus-frequency = <132000000>; // 132 MHz
45 clock-frequency = <396000000>; // 396 MHz 33 clock-frequency = <396000000>; // 396 MHz
@@ -47,203 +35,57 @@
47 }; 35 };
48 36
49 memory { 37 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x08000000>; // 128MB RAM 38 reg = <0x00000000 0x08000000>; // 128MB RAM
52 }; 39 };
53 40
54 soc@f0000000 { 41 soc5200@f0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "fsl,mpc5200b-immr";
58 ranges = <0 0xf0000000 0x0000c000>;
59 reg = <0xf0000000 0x00000100>;
60 bus-frequency = <132000000>;// 132 MHz 42 bus-frequency = <132000000>;// 132 MHz
61 system-frequency = <0>; // from bootloader
62
63 cdm@200 {
64 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
65 reg = <0x200 0x38>;
66 };
67
68 mpc5200_pic: interrupt-controller@500 {
69 // 5200 interrupts are encoded into two levels;
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
73 reg = <0x500 0x80>;
74 };
75 43
76 timer@600 { // General Purpose Timer 44 timer@600 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 reg = <0x600 0x10>;
79 interrupts = <1 9 0>;
80 fsl,has-wdt; 45 fsl,has-wdt;
81 }; 46 };
82 47
83 timer@610 { // General Purpose Timer 48 psc@2000 { // PSC1
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 49 status = "disabled";
85 reg = <0x610 0x10>;
86 interrupts = <1 10 0>;
87 };
88
89 timer@620 { // General Purpose Timer
90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 reg = <0x620 0x10>;
92 interrupts = <1 11 0>;
93 };
94
95 timer@630 { // General Purpose Timer
96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97 reg = <0x630 0x10>;
98 interrupts = <1 12 0>;
99 };
100
101 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x640 0x10>;
104 interrupts = <1 13 0>;
105 };
106
107 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 };
112
113 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 reg = <0x660 0x10>;
116 interrupts = <1 15 0>;
117 };
118
119 timer@670 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 reg = <0x670 0x10>;
122 interrupts = <1 16 0>;
123 };
124
125 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>;
129 };
130
131 can@900 {
132 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
133 interrupts = <2 17 0>;
134 reg = <0x900 0x80>;
135 }; 50 };
136 51
137 can@980 { 52 psc@2200 { // PSC2
138 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 53 status = "disabled";
139 interrupts = <2 18 0>;
140 reg = <0x980 0x80>;
141 }; 54 };
142 55
143 gpio_simple: gpio@b00 { 56 psc@2400 { // PSC3
144 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 57 status = "disabled";
145 reg = <0xb00 0x40>;
146 interrupts = <1 7 0>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 }; 58 };
150 59
151 gpio_wkup: gpio@c00 { 60 psc@2600 { // PSC4
152 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 61 status = "disabled";
153 reg = <0xc00 0x40>;
154 interrupts = <1 8 0 0 3 0>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 }; 62 };
158 63
159 spi@f00 { 64 psc@2800 { // PSC5
160 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 65 status = "disabled";
161 reg = <0xf00 0x20>;
162 interrupts = <2 13 0 2 14 0>;
163 };
164
165 usb@1000 {
166 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
167 reg = <0x1000 0x100>;
168 interrupts = <2 6 0>;
169 };
170
171 dma-controller@1200 {
172 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
173 reg = <0x1200 0x80>;
174 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
175 3 4 0 3 5 0 3 6 0 3 7 0
176 3 8 0 3 9 0 3 10 0 3 11 0
177 3 12 0 3 13 0 3 14 0 3 15 0>;
178 };
179
180 xlb@1f00 {
181 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
182 reg = <0x1f00 0x100>;
183 }; 66 };
184 67
185 // PSC6 in uart mode 68 // PSC6 in uart mode
186 console: psc@2c00 { // PSC6 69 console: psc@2c00 { // PSC6
187 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
188 reg = <0x2c00 0x100>;
189 interrupts = <2 4 0>;
190 }; 71 };
191 72
192 eth0: ethernet@3000 { 73 ethernet@3000 {
193 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
194 reg = <0x3000 0x400>;
195 local-mac-address = [ 00 00 00 00 00 00 ];
196 interrupts = <2 5 0>;
197 phy-handle = <&phy0>; 74 phy-handle = <&phy0>;
198 }; 75 };
199 76
200 mdio@3000 { 77 mdio@3000 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
204 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
205 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
206
207 phy0: ethernet-phy@0 { 78 phy0: ethernet-phy@0 {
208 reg = <0>; 79 reg = <0>;
209 }; 80 };
210 }; 81 };
211 82
212 ata@3a00 { 83 usb@1000 {
213 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 84 reg = <0x1000 0x100>;
214 reg = <0x3a00 0x100>;
215 interrupts = <2 7 0>;
216 };
217
218 i2c@3d00 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
222 reg = <0x3d00 0x40>;
223 interrupts = <2 15 0>;
224 };
225
226 i2c@3d40 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
230 reg = <0x3d40 0x40>;
231 interrupts = <2 16 0>;
232 };
233
234 sram@8000 {
235 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
236 reg = <0x8000 0x4000>;
237 }; 85 };
238 }; 86 };
239 87
240 pci@f0000d00 { 88 pci@f0000d00 {
241 #interrupt-cells = <1>;
242 #size-cells = <2>;
243 #address-cells = <3>;
244 device_type = "pci";
245 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
246 reg = <0xf0000d00 0x100>;
247 interrupt-map-mask = <0xf800 0 0 7>; 89 interrupt-map-mask = <0xf800 0 0 7>;
248 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot 90 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
249 0xc000 0 0 2 &media5200_fpga 0 3 91 0xc000 0 0 2 &media5200_fpga 0 3
@@ -260,37 +102,29 @@
260 102
261 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP 103 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
262 >; 104 >;
263 clock-frequency = <0>; // From boot loader
264 interrupts = <2 8 0 2 9 0 2 10 0>;
265 interrupt-parent = <&mpc5200_pic>;
266 bus-range = <0 0>;
267 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 105 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
268 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 106 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
269 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 107 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
108 interrupt-parent = <&mpc5200_pic>;
270 }; 109 };
271 110
272 localbus { 111 localbus {
273 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
274 #address-cells = <2>;
275 #size-cells = <1>;
276
277 ranges = < 0 0 0xfc000000 0x02000000 112 ranges = < 0 0 0xfc000000 0x02000000
278 1 0 0xfe000000 0x02000000 113 1 0 0xfe000000 0x02000000
279 2 0 0xf0010000 0x00010000 114 2 0 0xf0010000 0x00010000
280 3 0 0xf0020000 0x00010000 >; 115 3 0 0xf0020000 0x00010000 >;
281
282 flash@0,0 { 116 flash@0,0 {
283 compatible = "amd,am29lv28ml", "cfi-flash"; 117 compatible = "amd,am29lv28ml", "cfi-flash";
284 reg = <0 0x0 0x2000000>; // 32 MB 118 reg = <0 0x0 0x2000000>; // 32 MB
285 bank-width = <4>; // Width in bytes of the flash bank 119 bank-width = <4>; // Width in bytes of the flash bank
286 device-width = <2>; // Two devices on each bank 120 device-width = <2>; // Two devices on each bank
287 }; 121 };
288 122
289 flash@1,0 { 123 flash@1,0 {
290 compatible = "amd,am29lv28ml", "cfi-flash"; 124 compatible = "amd,am29lv28ml", "cfi-flash";
291 reg = <1 0 0x2000000>; // 32 MB 125 reg = <1 0 0x2000000>; // 32 MB
292 bank-width = <4>; // Width in bytes of the flash bank 126 bank-width = <4>; // Width in bytes of the flash bank
293 device-width = <2>; // Two devices on each bank 127 device-width = <2>; // Two devices on each bank
294 }; 128 };
295 129
296 media5200_fpga: fpga@2,0 { 130 media5200_fpga: fpga@2,0 {
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 97cb08598a4a..0b78e89ac69b 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,219 +10,73 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "promess,motionpro"; 16 model = "promess,motionpro";
17 compatible = "promess,motionpro"; 17 compatible = "promess,motionpro";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x04000000>; // 64MB
42 };
43 18
44 soc5200@f0000000 { 19 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 20 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 21 fsl,has-wdt;
71 }; 22 };
72 23
73 timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // Motion-PRO status LED 24 timer@660 { // Motion-PRO status LED
104 compatible = "promess,motionpro-led"; 25 compatible = "promess,motionpro-led";
105 label = "motionpro-statusled"; 26 label = "motionpro-statusled";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 blink-delay = <100>; // 100 msec 27 blink-delay = <100>; // 100 msec
109 }; 28 };
110 29
111 timer@670 { // Motion-PRO ready LED 30 timer@670 { // Motion-PRO ready LED
112 compatible = "promess,motionpro-led"; 31 compatible = "promess,motionpro-led";
113 label = "motionpro-readyled"; 32 label = "motionpro-readyled";
114 reg = <0x670 0x10>;
115 interrupts = <1 16 0>;
116 };
117
118 rtc@800 { // Real time clock
119 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
120 reg = <0x800 0x100>;
121 interrupts = <1 5 0 1 6 0>;
122 };
123
124 can@980 {
125 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
126 interrupts = <2 18 0>;
127 reg = <0x980 0x80>;
128 }; 33 };
129 34
130 gpio_simple: gpio@b00 { 35 can@900 {
131 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 36 status = "disabled";
132 reg = <0xb00 0x40>;
133 interrupts = <1 7 0>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 };
137
138 gpio_wkup: gpio@c00 {
139 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
140 reg = <0xc00 0x40>;
141 interrupts = <1 8 0 0 3 0>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
146 spi@f00 {
147 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
148 reg = <0xf00 0x20>;
149 interrupts = <2 13 0 2 14 0>;
150 };
151
152 usb@1000 {
153 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
154 reg = <0x1000 0xff>;
155 interrupts = <2 6 0>;
156 };
157
158 dma-controller@1200 {
159 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
160 reg = <0x1200 0x80>;
161 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
162 3 4 0 3 5 0 3 6 0 3 7 0
163 3 8 0 3 9 0 3 10 0 3 11 0
164 3 12 0 3 13 0 3 14 0 3 15 0>;
165 };
166
167 xlb@1f00 {
168 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
169 reg = <0x1f00 0x100>;
170 }; 37 };
171 38
172 psc@2000 { // PSC1 39 psc@2000 { // PSC1
173 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 40 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
174 reg = <0x2000 0x100>;
175 interrupts = <2 1 0>;
176 }; 41 };
177 42
178 // PSC2 in spi master mode 43 // PSC2 in spi master mode
179 psc@2200 { // PSC2 44 psc@2200 { // PSC2
180 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 45 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
181 cell-index = <1>; 46 cell-index = <1>;
182 reg = <0x2200 0x100>;
183 interrupts = <2 2 0>;
184 }; 47 };
185 48
186 // PSC5 in uart mode 49 psc@2400 { // PSC3
50 status = "disabled";
51 };
52
53 psc@2600 { // PSC4
54 status = "disabled";
55 };
56
187 psc@2800 { // PSC5 57 psc@2800 { // PSC5
188 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
189 reg = <0x2800 0x100>; 59 };
190 interrupts = <2 12 0>; 60
61 psc@2c00 { // PSC6
62 status = "disabled";
191 }; 63 };
192 64
193 ethernet@3000 { 65 ethernet@3000 {
194 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
195 reg = <0x3000 0x400>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <2 5 0>;
198 phy-handle = <&phy0>; 66 phy-handle = <&phy0>;
199 }; 67 };
200 68
201 mdio@3000 { 69 mdio@3000 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
205 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
206 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
207
208 phy0: ethernet-phy@2 { 70 phy0: ethernet-phy@2 {
209 reg = <2>; 71 reg = <2>;
210 }; 72 };
211 }; 73 };
212 74
213 ata@3a00 { 75 i2c@3d00 {
214 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 76 status = "disabled";
215 reg = <0x3a00 0x100>;
216 interrupts = <2 7 0>;
217 }; 77 };
218 78
219 i2c@3d40 { 79 i2c@3d40 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
223 reg = <0x3d40 0x40>;
224 interrupts = <2 16 0>;
225
226 rtc@68 { 80 rtc@68 {
227 compatible = "dallas,ds1339"; 81 compatible = "dallas,ds1339";
228 reg = <0x68>; 82 reg = <0x68>;
@@ -235,10 +89,11 @@
235 }; 89 };
236 }; 90 };
237 91
92 pci@f0000d00 {
93 status = "disabled";
94 };
95
238 localbus { 96 localbus {
239 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
240 #address-cells = <2>;
241 #size-cells = <1>;
242 ranges = <0 0 0xff000000 0x01000000 97 ranges = <0 0 0xff000000 0x01000000
243 1 0 0x50000000 0x00010000 98 1 0 0x50000000 0x00010000
244 2 0 0x50010000 0x00010000 99 2 0 0x50010000 0x00010000
@@ -277,6 +132,9 @@
277 reg = <0 0 0x01000000>; 132 reg = <0 0 0x01000000>;
278 bank-width = <2>; 133 bank-width = <2>;
279 device-width = <2>; 134 device-width = <2>;
135 #size-cells = <1>;
136 #address-cells = <1>;
280 }; 137 };
138
281 }; 139 };
282}; 140};
diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
new file mode 100644
index 000000000000..bc27548e895d
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
@@ -0,0 +1,275 @@
1/*
2 * base MPC5200b Device Tree Source
3 *
4 * Copyright (C) 2010 SecretLab
5 * Grant Likely <grant@secretlab.ca>
6 * John Bonesio <bones@secretlab.ca>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "fsl,mpc5200b";
18 compatible = "fsl,mpc5200b";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 powerpc: PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory: memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44
45 soc: soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 };
72
73 timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
107 };
108
109 timer@670 { // General Purpose Timer
110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
113 };
114
115 rtc@800 { // Real time clock
116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
117 reg = <0x800 0x100>;
118 interrupts = <1 5 0 1 6 0>;
119 };
120
121 can@900 {
122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
123 interrupts = <2 17 0>;
124 reg = <0x900 0x80>;
125 };
126
127 can@980 {
128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
129 interrupts = <2 18 0>;
130 reg = <0x980 0x80>;
131 };
132
133 gpio_simple: gpio@b00 {
134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
135 reg = <0xb00 0x40>;
136 interrupts = <1 7 0>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 gpio_wkup: gpio@c00 {
142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
143 reg = <0xc00 0x40>;
144 interrupts = <1 8 0 0 3 0>;
145 gpio-controller;
146 #gpio-cells = <2>;
147 };
148
149 spi@f00 {
150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
151 reg = <0xf00 0x20>;
152 interrupts = <2 13 0 2 14 0>;
153 };
154
155 usb: usb@1000 {
156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
157 reg = <0x1000 0xff>;
158 interrupts = <2 6 0>;
159 };
160
161 dma-controller@1200 {
162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
163 reg = <0x1200 0x80>;
164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
165 3 4 0 3 5 0 3 6 0 3 7 0
166 3 8 0 3 9 0 3 10 0 3 11 0
167 3 12 0 3 13 0 3 14 0 3 15 0>;
168 };
169
170 xlb@1f00 {
171 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
172 reg = <0x1f00 0x100>;
173 };
174
175 psc1: psc@2000 { // PSC1
176 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
177 reg = <0x2000 0x100>;
178 interrupts = <2 1 0>;
179 };
180
181 psc2: psc@2200 { // PSC2
182 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
183 reg = <0x2200 0x100>;
184 interrupts = <2 2 0>;
185 };
186
187 psc3: psc@2400 { // PSC3
188 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
189 reg = <0x2400 0x100>;
190 interrupts = <2 3 0>;
191 };
192
193 psc4: psc@2600 { // PSC4
194 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
195 reg = <0x2600 0x100>;
196 interrupts = <2 11 0>;
197 };
198
199 psc5: psc@2800 { // PSC5
200 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
201 reg = <0x2800 0x100>;
202 interrupts = <2 12 0>;
203 };
204
205 psc6: psc@2c00 { // PSC6
206 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
207 reg = <0x2c00 0x100>;
208 interrupts = <2 4 0>;
209 };
210
211 eth0: ethernet@3000 {
212 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
213 reg = <0x3000 0x400>;
214 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <2 5 0>;
216 };
217
218 mdio@3000 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
222 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
224 };
225
226 ata@3a00 {
227 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
228 reg = <0x3a00 0x100>;
229 interrupts = <2 7 0>;
230 };
231
232 i2c@3d00 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
236 reg = <0x3d00 0x40>;
237 interrupts = <2 15 0>;
238 };
239
240 i2c@3d40 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
244 reg = <0x3d40 0x40>;
245 interrupts = <2 16 0>;
246 };
247
248 sram@8000 {
249 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
250 reg = <0x8000 0x4000>;
251 };
252 };
253
254 pci: pci@f0000d00 {
255 #interrupt-cells = <1>;
256 #size-cells = <2>;
257 #address-cells = <3>;
258 device_type = "pci";
259 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
260 reg = <0xf0000d00 0x100>;
261 // interrupt-map-mask = need to add
262 // interrupt-map = need to add
263 clock-frequency = <0>; // From boot loader
264 interrupts = <2 8 0 2 9 0 2 10 0>;
265 bus-range = <0 0>;
266 // ranges = need to add
267 };
268
269 localbus: localbus {
270 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
271 #address-cells = <2>;
272 #size-cells = <1>;
273 ranges = <0 0 0xfc000000 0x2000000>;
274 };
275};
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
index 8dc212d9238b..21d34720fcc9 100644
--- a/arch/powerpc/boot/dts/mucmc52.dts
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -11,172 +11,109 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "manroland,mucmc52"; 17 model = "manroland,mucmc52";
18 compatible = "manroland,mucmc52"; 18 compatible = "manroland,mucmc52";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44 19
45 soc5200@f0000000 { 20 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // GPT 0 in GPIO mode 21 gpt0: timer@600 { // GPT 0 in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller; 22 gpio-controller;
72 #gpio-cells = <2>; 23 #gpio-cells = <2>;
73 }; 24 };
74 25
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode 26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller; 27 gpio-controller;
80 #gpio-cells = <2>; 28 #gpio-cells = <2>;
81 }; 29 };
82 30
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode 31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller; 32 gpio-controller;
88 #gpio-cells = <2>; 33 #gpio-cells = <2>;
89 }; 34 };
90 35
91 gpt3: timer@630 { // General Purpose Timer in GPIO mode 36 gpt3: timer@630 { // General Purpose Timer in GPIO mode
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x630 0x10>;
94 interrupts = <1 12 0>;
95 gpio-controller; 37 gpio-controller;
96 #gpio-cells = <2>; 38 #gpio-cells = <2>;
97 }; 39 };
98 40
99 gpio_simple: gpio@b00 { 41 timer@640 {
100 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 42 status = "disabled";
101 reg = <0xb00 0x40>;
102 interrupts = <1 7 0>;
103 gpio-controller;
104 #gpio-cells = <2>;
105 }; 43 };
106 44
107 gpio_wkup: gpio@c00 { 45 timer@650 {
108 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 46 status = "disabled";
109 reg = <0xc00 0x40>; 47 };
110 interrupts = <1 8 0 0 3 0>; 48
111 gpio-controller; 49 timer@660 {
112 #gpio-cells = <2>; 50 status = "disabled";
51 };
52
53 timer@670 {
54 status = "disabled";
113 }; 55 };
114 56
115 dma-controller@1200 { 57 rtc@800 {
116 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 58 status = "disabled";
117 reg = <0x1200 0x80>;
118 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
119 3 4 0 3 5 0 3 6 0 3 7 0
120 3 8 0 3 9 0 3 10 0 3 11 0
121 3 12 0 3 13 0 3 14 0 3 15 0>;
122 }; 59 };
123 60
124 xlb@1f00 { 61 can@900 {
125 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 62 status = "disabled";
126 reg = <0x1f00 0x100>;
127 }; 63 };
128 64
129 psc@2000 { /* PSC1 in UART mode */ 65 can@980 {
66 status = "disabled";
67 };
68
69 spi@f00 {
70 status = "disabled";
71 };
72
73 usb@1000 {
74 status = "disabled";
75 };
76
77 psc@2000 { // PSC1
130 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 78 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
131 reg = <0x2000 0x100>;
132 interrupts = <2 1 0>;
133 }; 79 };
134 80
135 psc@2200 { /* PSC2 in UART mode */ 81 psc@2200 { // PSC2
136 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 82 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
137 reg = <0x2200 0x100>;
138 interrupts = <2 2 0>;
139 }; 83 };
140 84
141 psc@2c00 { /* PSC6 in UART mode */ 85 psc@2400 { // PSC3
86 status = "disabled";
87 };
88
89 psc@2600 { // PSC4
90 status = "disabled";
91 };
92
93 psc@2800 { // PSC5
94 status = "disabled";
95 };
96
97 psc@2c00 { // PSC6
142 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 98 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
143 reg = <0x2c00 0x100>;
144 interrupts = <2 4 0>;
145 }; 99 };
146 100
147 ethernet@3000 { 101 ethernet@3000 {
148 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
149 reg = <0x3000 0x400>;
150 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupts = <2 5 0>;
152 phy-handle = <&phy0>; 102 phy-handle = <&phy0>;
153 }; 103 };
154 104
155 mdio@3000 { 105 mdio@3000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
159 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
160 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
161
162 phy0: ethernet-phy@0 { 106 phy0: ethernet-phy@0 {
163 compatible = "intel,lxt971"; 107 compatible = "intel,lxt971";
164 reg = <0>; 108 reg = <0>;
165 }; 109 };
166 }; 110 };
167 111
168 ata@3a00 { 112 i2c@3d00 {
169 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 113 status = "disabled";
170 reg = <0x3a00 0x100>;
171 interrupts = <2 7 0>;
172 }; 114 };
173 115
174 i2c@3d40 { 116 i2c@3d40 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>;
180 hwmon@2c { 117 hwmon@2c {
181 compatible = "ad,adm9240"; 118 compatible = "ad,adm9240";
182 reg = <0x2c>; 119 reg = <0x2c>;
@@ -186,20 +123,9 @@
186 reg = <0x51>; 123 reg = <0x51>;
187 }; 124 };
188 }; 125 };
189
190 sram@8000 {
191 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
192 reg = <0x8000 0x4000>;
193 };
194 }; 126 };
195 127
196 pci@f0000d00 { 128 pci@f0000d00 {
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 device_type = "pci";
201 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
202 reg = <0xf0000d00 0x100>;
203 interrupt-map-mask = <0xf800 0 0 7>; 129 interrupt-map-mask = <0xf800 0 0 7>;
204 interrupt-map = < 130 interrupt-map = <
205 /* IDSEL 0x10 */ 131 /* IDSEL 0x10 */
@@ -208,20 +134,12 @@
208 0x8000 0 0 3 &mpc5200_pic 0 2 3 134 0x8000 0 0 3 &mpc5200_pic 0 2 3
209 0x8000 0 0 4 &mpc5200_pic 0 1 3 135 0x8000 0 0 4 &mpc5200_pic 0 1 3
210 >; 136 >;
211 clock-frequency = <0>; // From boot loader
212 interrupts = <2 8 0 2 9 0 2 10 0>;
213 bus-range = <0 0>;
214 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000 137 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
215 0x02000000 0 0x90000000 0x90000000 0 0x10000000 138 0x02000000 0 0x90000000 0x90000000 0 0x10000000
216 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; 139 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
217 }; 140 };
218 141
219 localbus { 142 localbus {
220 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
221
222 #address-cells = <2>;
223 #size-cells = <1>;
224
225 ranges = <0 0 0xff800000 0x00800000 143 ranges = <0 0 0xff800000 0x00800000
226 1 0 0x80000000 0x00800000 144 1 0 0x80000000 0x00800000
227 3 0 0x80000000 0x00800000>; 145 3 0 0x80000000 0x00800000>;
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 28d77758d8be..9e354997eb7e 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -12,244 +12,92 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15/dts-v1/; 15/include/ "mpc5200b.dtsi"
16 16
17/ { 17/ {
18 model = "phytec,pcm030"; 18 model = "phytec,pcm030";
19 compatible = "phytec,pcm030"; 19 compatible = "phytec,pcm030";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5200@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <0x4000>; // L1, 16K
34 i-cache-size = <0x4000>; // L1, 16K
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x04000000>; // 64MB
44 };
45 20
46 soc5200@f0000000 { 21 soc5200@f0000000 {
47 #address-cells = <1>; 22 timer@600 { // General Purpose Timer
48 #size-cells = <1>;
49 compatible = "fsl,mpc5200b-immr";
50 ranges = <0 0xf0000000 0x0000c000>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt; 23 fsl,has-wdt;
72 }; 24 };
73 25
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 gpt2: timer@620 { // General Purpose Timer in GPIO mode 26 gpt2: timer@620 { // General Purpose Timer in GPIO mode
81 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 27 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 gpio-controller; 28 gpio-controller;
85 #gpio-cells = <2>; 29 #gpio-cells = <2>;
86 }; 30 };
87 31
88 gpt3: timer@630 { // General Purpose Timer in GPIO mode 32 gpt3: timer@630 { // General Purpose Timer in GPIO mode
89 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 33 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
90 reg = <0x630 0x10>;
91 interrupts = <1 12 0>;
92 gpio-controller; 34 gpio-controller;
93 #gpio-cells = <2>; 35 #gpio-cells = <2>;
94 }; 36 };
95 37
96 gpt4: timer@640 { // General Purpose Timer in GPIO mode 38 gpt4: timer@640 { // General Purpose Timer in GPIO mode
97 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 39 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
98 reg = <0x640 0x10>;
99 interrupts = <1 13 0>;
100 gpio-controller; 40 gpio-controller;
101 #gpio-cells = <2>; 41 #gpio-cells = <2>;
102 }; 42 };
103 43
104 gpt5: timer@650 { // General Purpose Timer in GPIO mode 44 gpt5: timer@650 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 45 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 reg = <0x650 0x10>;
107 interrupts = <1 14 0>;
108 gpio-controller; 46 gpio-controller;
109 #gpio-cells = <2>; 47 #gpio-cells = <2>;
110 }; 48 };
111 49
112 gpt6: timer@660 { // General Purpose Timer in GPIO mode 50 gpt6: timer@660 { // General Purpose Timer in GPIO mode
113 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 51 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
114 reg = <0x660 0x10>;
115 interrupts = <1 15 0>;
116 gpio-controller; 52 gpio-controller;
117 #gpio-cells = <2>; 53 #gpio-cells = <2>;
118 }; 54 };
119 55
120 gpt7: timer@670 { // General Purpose Timer in GPIO mode 56 gpt7: timer@670 { // General Purpose Timer in GPIO mode
121 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 57 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
122 reg = <0x670 0x10>;
123 interrupts = <1 16 0>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 };
127
128 rtc@800 { // Real time clock
129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
130 reg = <0x800 0x100>;
131 interrupts = <1 5 0 1 6 0>;
132 };
133
134 can@900 {
135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
136 interrupts = <2 17 0>;
137 reg = <0x900 0x80>;
138 };
139
140 can@980 {
141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
142 interrupts = <2 18 0>;
143 reg = <0x980 0x80>;
144 };
145
146 gpio_simple: gpio@b00 {
147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
148 reg = <0xb00 0x40>;
149 interrupts = <1 7 0>;
150 gpio-controller; 58 gpio-controller;
151 #gpio-cells = <2>; 59 #gpio-cells = <2>;
152 }; 60 };
153 61
154 gpio_wkup: gpio@c00 {
155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
156 reg = <0xc00 0x40>;
157 interrupts = <1 8 0 0 3 0>;
158 gpio-controller;
159 #gpio-cells = <2>;
160 };
161
162 spi@f00 {
163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
164 reg = <0xf00 0x20>;
165 interrupts = <2 13 0 2 14 0>;
166 };
167
168 usb@1000 {
169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
170 reg = <0x1000 0xff>;
171 interrupts = <2 6 0>;
172 };
173
174 dma-controller@1200 {
175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
176 reg = <0x1200 0x80>;
177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
178 3 4 0 3 5 0 3 6 0 3 7 0
179 3 8 0 3 9 0 3 10 0 3 11 0
180 3 12 0 3 13 0 3 14 0 3 15 0>;
181 };
182
183 xlb@1f00 {
184 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
185 reg = <0x1f00 0x100>;
186 };
187
188 psc@2000 { /* PSC1 in ac97 mode */ 62 psc@2000 { /* PSC1 in ac97 mode */
189 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 63 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
190 cell-index = <0>; 64 cell-index = <0>;
191 reg = <0x2000 0x100>;
192 interrupts = <2 1 0>;
193 }; 65 };
194 66
195 /* PSC2 port is used by CAN1/2 */ 67 /* PSC2 port is used by CAN1/2 */
68 psc@2200 {
69 status = "disabled";
70 };
196 71
197 psc@2400 { /* PSC3 in UART mode */ 72 psc@2400 { /* PSC3 in UART mode */
198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 73 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
199 reg = <0x2400 0x100>;
200 interrupts = <2 3 0>;
201 }; 74 };
202 75
203 /* PSC4 is ??? */ 76 /* PSC4 is ??? */
77 psc@2600 {
78 status = "disabled";
79 };
204 80
205 /* PSC5 is ??? */ 81 /* PSC5 is ??? */
82 psc@2800 {
83 status = "disabled";
84 };
206 85
207 psc@2c00 { /* PSC6 in UART mode */ 86 psc@2c00 { /* PSC6 in UART mode */
208 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 87 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
209 reg = <0x2c00 0x100>;
210 interrupts = <2 4 0>;
211 }; 88 };
212 89
213 ethernet@3000 { 90 ethernet@3000 {
214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
215 reg = <0x3000 0x400>;
216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <2 5 0>;
218 phy-handle = <&phy0>; 91 phy-handle = <&phy0>;
219 }; 92 };
220 93
221 mdio@3000 { 94 mdio@3000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
225 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
226 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
227
228 phy0: ethernet-phy@0 { 95 phy0: ethernet-phy@0 {
229 reg = <0>; 96 reg = <0>;
230 }; 97 };
231 }; 98 };
232 99
233 ata@3a00 {
234 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
235 reg = <0x3a00 0x100>;
236 interrupts = <2 7 0>;
237 };
238
239 i2c@3d00 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
243 reg = <0x3d00 0x40>;
244 interrupts = <2 15 0>;
245 };
246
247 i2c@3d40 { 100 i2c@3d40 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
251 reg = <0x3d40 0x40>;
252 interrupts = <2 16 0>;
253 rtc@51 { 101 rtc@51 {
254 compatible = "nxp,pcf8563"; 102 compatible = "nxp,pcf8563";
255 reg = <0x51>; 103 reg = <0x51>;
@@ -268,12 +116,6 @@
268 }; 116 };
269 117
270 pci@f0000d00 { 118 pci@f0000d00 {
271 #interrupt-cells = <1>;
272 #size-cells = <2>;
273 #address-cells = <3>;
274 device_type = "pci";
275 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
276 reg = <0xf0000d00 0x100>;
277 interrupt-map-mask = <0xf800 0 0 7>; 119 interrupt-map-mask = <0xf800 0 0 7>;
278 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 120 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
279 0xc000 0 0 2 &mpc5200_pic 1 1 3 121 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -284,11 +126,12 @@
284 0xc800 0 0 2 &mpc5200_pic 1 2 3 126 0xc800 0 0 2 &mpc5200_pic 1 2 3
285 0xc800 0 0 3 &mpc5200_pic 1 3 3 127 0xc800 0 0 3 &mpc5200_pic 1 3 3
286 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 128 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
287 clock-frequency = <0>; // From boot loader
288 interrupts = <2 8 0 2 9 0 2 10 0>;
289 bus-range = <0 0>;
290 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 129 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
291 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 130 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
292 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 131 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
293 }; 132 };
133
134 localbus {
135 status = "disabled";
136 };
294}; 137};
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 9dee52b67477..1dd478bfff96 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -12,99 +12,37 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14 14
15/dts-v1/; 15/include/ "mpc5200b.dtsi"
16 16
17/ { 17/ {
18 model = "phytec,pcm032"; 18 model = "phytec,pcm032";
19 compatible = "phytec,pcm032"; 19 compatible = "phytec,pcm032";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,5200@0 {
29 device_type = "cpu";
30 reg = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <0x4000>; // L1, 16K
34 i-cache-size = <0x4000>; // L1, 16K
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
38 };
39 };
40 20
41 memory { 21 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x08000000>; // 128MB 22 reg = <0x00000000 0x08000000>; // 128MB
44 }; 23 };
45 24
46 soc5200@f0000000 { 25 soc5200@f0000000 {
47 #address-cells = <1>; 26 timer@600 { // General Purpose Timer
48 #size-cells = <1>;
49 compatible = "fsl,mpc5200b-immr";
50 ranges = <0 0xf0000000 0x0000c000>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt; 27 fsl,has-wdt;
72 }; 28 };
73 29
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 gpt2: timer@620 { // General Purpose Timer in GPIO mode 30 gpt2: timer@620 { // General Purpose Timer in GPIO mode
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 gpio-controller; 31 gpio-controller;
85 #gpio-cells = <2>; 32 #gpio-cells = <2>;
86 }; 33 };
87 34
88 gpt3: timer@630 { // General Purpose Timer in GPIO mode 35 gpt3: timer@630 { // General Purpose Timer in GPIO mode
89 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
90 reg = <0x630 0x10>;
91 interrupts = <1 12 0>;
92 gpio-controller; 36 gpio-controller;
93 #gpio-cells = <2>; 37 #gpio-cells = <2>;
94 }; 38 };
95 39
96 gpt4: timer@640 { // General Purpose Timer in GPIO mode 40 gpt4: timer@640 { // General Purpose Timer in GPIO mode
97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
98 reg = <0x640 0x10>;
99 interrupts = <1 13 0>;
100 gpio-controller; 41 gpio-controller;
101 #gpio-cells = <2>; 42 #gpio-cells = <2>;
102 }; 43 };
103 44
104 gpt5: timer@650 { // General Purpose Timer in GPIO mode 45 gpt5: timer@650 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x650 0x10>;
107 interrupts = <1 14 0>;
108 gpio-controller; 46 gpio-controller;
109 #gpio-cells = <2>; 47 #gpio-cells = <2>;
110 }; 48 };
@@ -118,138 +56,49 @@
118 }; 56 };
119 57
120 gpt7: timer@670 { // General Purpose Timer in GPIO mode 58 gpt7: timer@670 { // General Purpose Timer in GPIO mode
121 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
122 reg = <0x670 0x10>;
123 interrupts = <1 16 0>;
124 gpio-controller; 59 gpio-controller;
125 #gpio-cells = <2>; 60 #gpio-cells = <2>;
126 }; 61 };
127 62
128 rtc@800 { // Real time clock
129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
130 reg = <0x800 0x100>;
131 interrupts = <1 5 0 1 6 0>;
132 };
133
134 can@900 {
135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
136 interrupts = <2 17 0>;
137 reg = <0x900 0x80>;
138 };
139
140 can@980 {
141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
142 interrupts = <2 18 0>;
143 reg = <0x980 0x80>;
144 };
145
146 gpio_simple: gpio@b00 {
147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
148 reg = <0xb00 0x40>;
149 interrupts = <1 7 0>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 gpio_wkup: gpio@c00 {
155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
156 reg = <0xc00 0x40>;
157 interrupts = <1 8 0 0 3 0>;
158 gpio-controller;
159 #gpio-cells = <2>;
160 };
161
162 spi@f00 {
163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
164 reg = <0xf00 0x20>;
165 interrupts = <2 13 0 2 14 0>;
166 };
167
168 usb@1000 {
169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
170 reg = <0x1000 0xff>;
171 interrupts = <2 6 0>;
172 };
173
174 dma-controller@1200 {
175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
176 reg = <0x1200 0x80>;
177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
178 3 4 0 3 5 0 3 6 0 3 7 0
179 3 8 0 3 9 0 3 10 0 3 11 0
180 3 12 0 3 13 0 3 14 0 3 15 0>;
181 };
182
183 xlb@1f00 {
184 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
185 reg = <0x1f00 0x100>;
186 };
187
188 psc@2000 { /* PSC1 is ac97 */ 63 psc@2000 { /* PSC1 is ac97 */
189 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 64 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
190 cell-index = <0>; 65 cell-index = <0>;
191 reg = <0x2000 0x100>;
192 interrupts = <2 1 0>;
193 }; 66 };
194 67
195 /* PSC2 port is used by CAN1/2 */ 68 /* PSC2 port is used by CAN1/2 */
69 psc@2200 {
70 status = "disabled";
71 };
196 72
197 psc@2400 { /* PSC3 in UART mode */ 73 psc@2400 { /* PSC3 in UART mode */
198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 74 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
199 reg = <0x2400 0x100>;
200 interrupts = <2 3 0>;
201 }; 75 };
202 76
203 /* PSC4 is ??? */ 77 /* PSC4 is ??? */
78 psc@2600 {
79 status = "disabled";
80 };
204 81
205 /* PSC5 is ??? */ 82 /* PSC5 is ??? */
83 psc@2800 {
84 status = "disabled";
85 };
206 86
207 psc@2c00 { /* PSC6 in UART mode */ 87 psc@2c00 { /* PSC6 in UART mode */
208 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 88 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
209 reg = <0x2c00 0x100>;
210 interrupts = <2 4 0>;
211 }; 89 };
212 90
213 ethernet@3000 { 91 ethernet@3000 {
214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
215 reg = <0x3000 0x400>;
216 local-mac-address = [ 00 00 00 00 00 00 ];
217 interrupts = <2 5 0>;
218 phy-handle = <&phy0>; 92 phy-handle = <&phy0>;
219 }; 93 };
220 94
221 mdio@3000 { 95 mdio@3000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
225 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
226 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
227
228 phy0: ethernet-phy@0 { 96 phy0: ethernet-phy@0 {
229 reg = <0>; 97 reg = <0>;
230 }; 98 };
231 }; 99 };
232 100
233 ata@3a00 {
234 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
235 reg = <0x3a00 0x100>;
236 interrupts = <2 7 0>;
237 };
238
239 i2c@3d00 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
243 reg = <0x3d00 0x40>;
244 interrupts = <2 15 0>;
245 };
246
247 i2c@3d40 { 101 i2c@3d40 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
251 reg = <0x3d40 0x40>;
252 interrupts = <2 16 0>;
253 rtc@51 { 102 rtc@51 {
254 compatible = "nxp,pcf8563"; 103 compatible = "nxp,pcf8563";
255 reg = <0x51>; 104 reg = <0x51>;
@@ -260,20 +109,9 @@
260 pagesize = <32>; 109 pagesize = <32>;
261 }; 110 };
262 }; 111 };
263
264 sram@8000 {
265 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
266 reg = <0x8000 0x4000>;
267 };
268 }; 112 };
269 113
270 pci@f0000d00 { 114 pci@f0000d00 {
271 #interrupt-cells = <1>;
272 #size-cells = <2>;
273 #address-cells = <3>;
274 device_type = "pci";
275 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
276 reg = <0xf0000d00 0x100>;
277 interrupt-map-mask = <0xf800 0 0 7>; 115 interrupt-map-mask = <0xf800 0 0 7>;
278 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 116 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
279 0xc000 0 0 2 &mpc5200_pic 1 1 3 117 0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -284,20 +122,12 @@
284 0xc800 0 0 2 &mpc5200_pic 1 2 3 122 0xc800 0 0 2 &mpc5200_pic 1 2 3
285 0xc800 0 0 3 &mpc5200_pic 1 3 3 123 0xc800 0 0 3 &mpc5200_pic 1 3 3
286 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 124 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
287 clock-frequency = <0>; // From boot loader
288 interrupts = <2 8 0 2 9 0 2 10 0>;
289 bus-range = <0 0>;
290 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 125 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
291 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 126 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
292 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; 127 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
293 }; 128 };
294 129
295 localbus { 130 localbus {
296 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
297
298 #address-cells = <2>;
299 #size-cells = <1>;
300
301 ranges = <0 0 0xfe000000 0x02000000 131 ranges = <0 0 0xfe000000 0x02000000
302 1 0 0xfc000000 0x02000000 132 1 0 0xfc000000 0x02000000
303 2 0 0xfbe00000 0x00200000 133 2 0 0xfbe00000 0x00200000
@@ -350,40 +180,39 @@
350 bank-width = <2>; 180 bank-width = <2>;
351 }; 181 };
352 182
353 /* 183 /*
354 * example snippets for FPGA 184 * example snippets for FPGA
355 * 185 *
356 * fpga@3,0 { 186 * fpga@3,0 {
357 * compatible = "fpga_driver"; 187 * compatible = "fpga_driver";
358 * reg = <3 0 0x02000000>; 188 * reg = <3 0 0x02000000>;
359 * bank-width = <4>; 189 * bank-width = <4>;
360 * }; 190 * };
361 * 191 *
362 * fpga@4,0 { 192 * fpga@4,0 {
363 * compatible = "fpga_driver"; 193 * compatible = "fpga_driver";
364 * reg = <4 0 0x02000000>; 194 * reg = <4 0 0x02000000>;
365 * bank-width = <4>; 195 * bank-width = <4>;
366 * }; 196 * };
367 */ 197 */
368 198
369 /* 199 /*
370 * example snippets for free chipselects 200 * example snippets for free chipselects
371 * 201 *
372 * device@5,0 { 202 * device@5,0 {
373 * compatible = "custom_driver"; 203 * compatible = "custom_driver";
374 * reg = <5 0 0x02000000>; 204 * reg = <5 0 0x02000000>;
375 * }; 205 * };
376 * 206 *
377 * device@6,0 { 207 * device@6,0 {
378 * compatible = "custom_driver"; 208 * compatible = "custom_driver";
379 * reg = <6 0 0x02000000>; 209 * reg = <6 0 0x02000000>;
380 * }; 210 * };
381 * 211 *
382 * device@7,0 { 212 * device@7,0 {
383 * compatible = "custom_driver"; 213 * compatible = "custom_driver";
384 * reg = <7 0 0x02000000>; 214 * reg = <7 0 0x02000000>;
385 * }; 215 * };
386 */ 216 */
387 }; 217 };
388}; 218};
389
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
index e00441a3e5a7..ba83d5488ec6 100644
--- a/arch/powerpc/boot/dts/uc101.dts
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -11,79 +11,24 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14/dts-v1/; 14/include/ "mpc5200b.dtsi"
15 15
16/ { 16/ {
17 model = "manroland,uc101"; 17 model = "manroland,uc101";
18 compatible = "manroland,uc101"; 18 compatible = "manroland,uc101";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; // 64MB
43 };
44 19
45 soc5200@f0000000 { 20 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 gpt0: timer@600 { // General Purpose Timer in GPIO mode 21 gpt0: timer@600 { // General Purpose Timer in GPIO mode
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 gpio-controller; 22 gpio-controller;
72 #gpio-cells = <2>; 23 #gpio-cells = <2>;
73 }; 24 };
74 25
75 gpt1: timer@610 { // General Purpose Timer in GPIO mode 26 gpt1: timer@610 { // General Purpose Timer in GPIO mode
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 reg = <0x610 0x10>;
78 interrupts = <1 10 0>;
79 gpio-controller; 27 gpio-controller;
80 #gpio-cells = <2>; 28 #gpio-cells = <2>;
81 }; 29 };
82 30
83 gpt2: timer@620 { // General Purpose Timer in GPIO mode 31 gpt2: timer@620 { // General Purpose Timer in GPIO mode
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x620 0x10>;
86 interrupts = <1 11 0>;
87 gpio-controller; 32 gpio-controller;
88 #gpio-cells = <2>; 33 #gpio-cells = <2>;
89 }; 34 };
@@ -97,118 +42,85 @@
97 }; 42 };
98 43
99 gpt4: timer@640 { // General Purpose Timer in GPIO mode 44 gpt4: timer@640 { // General Purpose Timer in GPIO mode
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 reg = <0x640 0x10>;
102 interrupts = <1 13 0>;
103 gpio-controller; 45 gpio-controller;
104 #gpio-cells = <2>; 46 #gpio-cells = <2>;
105 }; 47 };
106 48
107 gpt5: timer@650 { // General Purpose Timer in GPIO mode 49 gpt5: timer@650 { // General Purpose Timer in GPIO mode
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 gpio-controller; 50 gpio-controller;
112 #gpio-cells = <2>; 51 #gpio-cells = <2>;
113 }; 52 };
114 53
115 gpt6: timer@660 { // General Purpose Timer in GPIO mode 54 gpt6: timer@660 { // General Purpose Timer in GPIO mode
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x660 0x10>;
118 interrupts = <1 15 0>;
119 gpio-controller; 55 gpio-controller;
120 #gpio-cells = <2>; 56 #gpio-cells = <2>;
121 }; 57 };
122 58
123 gpt7: timer@670 { // General Purpose Timer in GPIO mode 59 gpt7: timer@670 { // General Purpose Timer in GPIO mode
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 reg = <0x670 0x10>;
126 interrupts = <1 16 0>;
127 gpio-controller; 60 gpio-controller;
128 #gpio-cells = <2>; 61 #gpio-cells = <2>;
129 }; 62 };
130 63
131 gpio_simple: gpio@b00 { 64 rtc@800 {
132 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 65 status = "disabled";
133 reg = <0xb00 0x40>;
134 interrupts = <1 7 0>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 }; 66 };
138 67
139 gpio_wkup: gpio@c00 { 68 can@900 {
140 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 69 status = "disabled";
141 reg = <0xc00 0x40>; 70 };
142 interrupts = <1 8 0 0 3 0>; 71
143 gpio-controller; 72 can@980 {
144 #gpio-cells = <2>; 73 status = "disabled";
145 }; 74 };
146 75
147 dma-controller@1200 { 76 spi@f00 {
148 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 77 status = "disabled";
149 reg = <0x1200 0x80>;
150 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
151 3 4 0 3 5 0 3 6 0 3 7 0
152 3 8 0 3 9 0 3 10 0 3 11 0
153 3 12 0 3 13 0 3 14 0 3 15 0>;
154 }; 78 };
155 79
156 xlb@1f00 { 80 usb@1000 {
157 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 81 status = "disabled";
158 reg = <0x1f00 0x100>;
159 }; 82 };
160 83
161 psc@2000 { /* PSC1 in UART mode */ 84 psc@2000 { // PSC1
162 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 85 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
163 reg = <0x2000 0x100>;
164 interrupts = <2 1 0>;
165 }; 86 };
166 87
167 psc@2200 { /* PSC2 in UART mode */ 88 psc@2200 { // PSC2
168 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 89 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
169 reg = <0x2200 0x100>;
170 interrupts = <2 2 0>;
171 }; 90 };
172 91
173 psc@2c00 { /* PSC6 in UART mode */ 92 psc@2400 { // PSC3
93 status = "disabled";
94 };
95
96 psc@2600 { // PSC4
97 status = "disabled";
98 };
99
100 psc@2800 { // PSC5
101 status = "disabled";
102 };
103
104 psc@2c00 { // PSC6
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 105 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 reg = <0x2c00 0x100>;
176 interrupts = <2 4 0>;
177 }; 106 };
178 107
179 ethernet@3000 { 108 ethernet@3000 {
180 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
181 reg = <0x3000 0x400>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <2 5 0>;
184 phy-handle = <&phy0>; 109 phy-handle = <&phy0>;
185 }; 110 };
186 111
187 mdio@3000 { 112 mdio@3000 {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
191 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
192 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
193
194 phy0: ethernet-phy@0 { 113 phy0: ethernet-phy@0 {
195 compatible = "intel,lxt971"; 114 compatible = "intel,lxt971";
196 reg = <0>; 115 reg = <0>;
197 }; 116 };
198 }; 117 };
199 118
200 ata@3a00 { 119 i2c@3d00 {
201 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 120 status = "disabled";
202 reg = <0x3a00 0x100>;
203 interrupts = <2 7 0>;
204 }; 121 };
205 122
206 i2c@3d40 { 123 i2c@3d40 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
210 reg = <0x3d40 0x40>;
211 interrupts = <2 16 0>;
212 fsl,preserve-clocking; 124 fsl,preserve-clocking;
213 clock-frequency = <400000>; 125 clock-frequency = <400000>;
214 126
@@ -221,19 +133,13 @@
221 reg = <0x51>; 133 reg = <0x51>;
222 }; 134 };
223 }; 135 };
136 };
224 137
225 sram@8000 { 138 pci@f0000d00 {
226 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 139 status = "disabled";
227 reg = <0x8000 0x4000>;
228 };
229 }; 140 };
230 141
231 localbus { 142 localbus {
232 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
233
234 #address-cells = <2>;
235 #size-cells = <1>;
236
237 ranges = <0 0 0xff800000 0x00800000 143 ranges = <0 0 0xff800000 0x00800000
238 1 0 0x80000000 0x00800000 144 1 0 0x80000000 0x00800000
239 3 0 0x80000000 0x00800000>; 145 3 0 0x80000000 0x00800000>;
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-25 17:33:34 -0400