1 files changed, 104 insertions, 10 deletions
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
index b71051f506c1..f20c01ab2473 100644
--- a/arch/powerpc/boot/dts/p4080si.dtsi
+++ b/arch/powerpc/boot/dts/p4080si.dtsi
@@ -42,6 +42,7 @@
        aliases {
                ccsr = &soc;
+                dcsr = &dcsr;
                serial0 = &serial0;
                serial1 = &serial1;
@@ -77,7 +78,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
-                cpu0: PowerPC,4080@0 {
+                cpu0: PowerPC,e500mc@0 {
                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2_0>;
@@ -85,7 +86,7 @@
                                next-level-cache = <&cpc>;
                        };
                };
-                cpu1: PowerPC,4080@1 {
+                cpu1: PowerPC,e500mc@1 {
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2_1>;
@@ -93,7 +94,7 @@
                                next-level-cache = <&cpc>;
                        };
                };
-                cpu2: PowerPC,4080@2 {
+                cpu2: PowerPC,e500mc@2 {
                        device_type = "cpu";
                        reg = <2>;
                        next-level-cache = <&L2_2>;
@@ -101,7 +102,7 @@
                                next-level-cache = <&cpc>;
                        };
                };
-                cpu3: PowerPC,4080@3 {
+                cpu3: PowerPC,e500mc@3 {
                        device_type = "cpu";
                        reg = <3>;
                        next-level-cache = <&L2_3>;
@@ -109,7 +110,7 @@
                                next-level-cache = <&cpc>;
                        };
                };
-                cpu4: PowerPC,4080@4 {
+                cpu4: PowerPC,e500mc@4 {
                        device_type = "cpu";
                        reg = <4>;
                        next-level-cache = <&L2_4>;
@@ -117,7 +118,7 @@
                                next-level-cache = <&cpc>;
                        };
                };
-                cpu5: PowerPC,4080@5 {
+                cpu5: PowerPC,e500mc@5 {
                        device_type = "cpu";
                        reg = <5>;
                        next-level-cache = <&L2_5>;
@@ -125,7 +126,7 @@
                                next-level-cache = <&cpc>;
                        };
                };
-                cpu6: PowerPC,4080@6 {
+                cpu6: PowerPC,e500mc@6 {
                        device_type = "cpu";
                        reg = <6>;
                        next-level-cache = <&L2_6>;
@@ -133,7 +134,7 @@
                                next-level-cache = <&cpc>;
                        };
                };
-                cpu7: PowerPC,4080@7 {
+                cpu7: PowerPC,e500mc@7 {
                        device_type = "cpu";
                        reg = <7>;
                        next-level-cache = <&L2_7>;
@@ -143,6 +144,99 @@
                };
        };
+        dcsr: dcsr@f00000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,dcsr", "simple-bus";
+                dcsr-epu@0 {
+                        compatible = "fsl,dcsr-epu";
+                        interrupts = <52 2 0 0
+                                      84 2 0 0
+                                      85 2 0 0>;
+                        interrupt-parent = <&mpic>;
+                        reg = <0x0 0x1000>;
+                };
+                dcsr-npc {
+                        compatible = "fsl,dcsr-npc";
+                        reg = <0x1000 0x1000 0x1000000 0x8000>;
+                };
+                dcsr-nxc@2000 {
+                        compatible = "fsl,dcsr-nxc";
+                        reg = <0x2000 0x1000>;
+                };
+                dcsr-corenet {
+                        compatible = "fsl,dcsr-corenet";
+                        reg = <0x8000 0x1000 0xB0000 0x1000>;
+                };
+                dcsr-dpaa@9000 {
+                        compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
+                        reg = <0x9000 0x1000>;
+                };
+                dcsr-ocn@11000 {
+                        compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
+                        reg = <0x11000 0x1000>;
+                };
+                dcsr-ddr@12000 {
+                        compatible = "fsl,dcsr-ddr";
+                        dev-handle = <&ddr1>;
+                        reg = <0x12000 0x1000>;
+                };
+                dcsr-ddr@13000 {
+                        compatible = "fsl,dcsr-ddr";
+                        dev-handle = <&ddr2>;
+                        reg = <0x13000 0x1000>;
+                };
+                dcsr-nal@18000 {
+                        compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
+                        reg = <0x18000 0x1000>;
+                };
+                dcsr-rcpm@22000 {
+                        compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
+                        reg = <0x22000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@40000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu0>;
+                        reg = <0x40000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@41000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu1>;
+                        reg = <0x41000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@42000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu2>;
+                        reg = <0x42000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@43000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu3>;
+                        reg = <0x43000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@44000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu4>;
+                        reg = <0x44000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@45000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu5>;
+                        reg = <0x45000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@46000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu6>;
+                        reg = <0x46000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@47000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu7>;
+                        reg = <0x47000 0x1000>;
+                };
+        };
        soc: soc@ffe000000 {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -162,13 +256,13 @@
                        fsl,num-laws = <32>;
                };
-                memory-controller@8000 {
+                ddr1: memory-controller@8000 {
                        compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
                        reg = <0x8000 0x1000>;
                        interrupts = <16 2 1 23>;
                };
-                memory-controller@9000 {
+                ddr2: memory-controller@9000 {
                        compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
                        reg = <0x9000 0x1000>;
                        interrupts = <16 2 1 22>;

diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi index b71051f506c1..f20c01ab2473 100644 --- a/arch/powerpc/boot/dts/p4080si.dtsi +++ b/arch/powerpc/boot/dts/p4080si.dtsi
@@ -42,6 +42,7 @@
42		42
43	aliases {	43	aliases {
44	ccsr = &soc;	44	ccsr = &soc;
		45	dcsr = &dcsr;
45		46
46	serial0 = &serial0;	47	serial0 = &serial0;
47	serial1 = &serial1;	48	serial1 = &serial1;
@@ -77,7 +78,7 @@
77	#address-cells = <1>;	78	#address-cells = <1>;
78	#size-cells = <0>;	79	#size-cells = <0>;
79		80
80	cpu0: PowerPC,4080@0 {	81	cpu0: PowerPC,e500mc@0 {
81	device_type = "cpu";	82	device_type = "cpu";
82	reg = <0>;	83	reg = <0>;
83	next-level-cache = <&L2_0>;	84	next-level-cache = <&L2_0>;
@@ -85,7 +86,7 @@
85	next-level-cache = <&cpc>;	86	next-level-cache = <&cpc>;
86	};	87	};
87	};	88	};
88	cpu1: PowerPC,4080@1 {	89	cpu1: PowerPC,e500mc@1 {
89	device_type = "cpu";	90	device_type = "cpu";
90	reg = <1>;	91	reg = <1>;
91	next-level-cache = <&L2_1>;	92	next-level-cache = <&L2_1>;
@@ -93,7 +94,7 @@
93	next-level-cache = <&cpc>;	94	next-level-cache = <&cpc>;
94	};	95	};
95	};	96	};
96	cpu2: PowerPC,4080@2 {	97	cpu2: PowerPC,e500mc@2 {
97	device_type = "cpu";	98	device_type = "cpu";
98	reg = <2>;	99	reg = <2>;
99	next-level-cache = <&L2_2>;	100	next-level-cache = <&L2_2>;
@@ -101,7 +102,7 @@
101	next-level-cache = <&cpc>;	102	next-level-cache = <&cpc>;
102	};	103	};
103	};	104	};
104	cpu3: PowerPC,4080@3 {	105	cpu3: PowerPC,e500mc@3 {
105	device_type = "cpu";	106	device_type = "cpu";
106	reg = <3>;	107	reg = <3>;
107	next-level-cache = <&L2_3>;	108	next-level-cache = <&L2_3>;
@@ -109,7 +110,7 @@
109	next-level-cache = <&cpc>;	110	next-level-cache = <&cpc>;
110	};	111	};
111	};	112	};
112	cpu4: PowerPC,4080@4 {	113	cpu4: PowerPC,e500mc@4 {
113	device_type = "cpu";	114	device_type = "cpu";
114	reg = <4>;	115	reg = <4>;
115	next-level-cache = <&L2_4>;	116	next-level-cache = <&L2_4>;
@@ -117,7 +118,7 @@
117	next-level-cache = <&cpc>;	118	next-level-cache = <&cpc>;
118	};	119	};
119	};	120	};
120	cpu5: PowerPC,4080@5 {	121	cpu5: PowerPC,e500mc@5 {
121	device_type = "cpu";	122	device_type = "cpu";
122	reg = <5>;	123	reg = <5>;
123	next-level-cache = <&L2_5>;	124	next-level-cache = <&L2_5>;
@@ -125,7 +126,7 @@
125	next-level-cache = <&cpc>;	126	next-level-cache = <&cpc>;
126	};	127	};
127	};	128	};
128	cpu6: PowerPC,4080@6 {	129	cpu6: PowerPC,e500mc@6 {
129	device_type = "cpu";	130	device_type = "cpu";
130	reg = <6>;	131	reg = <6>;
131	next-level-cache = <&L2_6>;	132	next-level-cache = <&L2_6>;
@@ -133,7 +134,7 @@
133	next-level-cache = <&cpc>;	134	next-level-cache = <&cpc>;
134	};	135	};
135	};	136	};
136	cpu7: PowerPC,4080@7 {	137	cpu7: PowerPC,e500mc@7 {
137	device_type = "cpu";	138	device_type = "cpu";
138	reg = <7>;	139	reg = <7>;
139	next-level-cache = <&L2_7>;	140	next-level-cache = <&L2_7>;
@@ -143,6 +144,99 @@
143	};	144	};
144	};	145	};
145		146
		147	dcsr: dcsr@f00000000 {
		148	#address-cells = <1>;
		149	#size-cells = <1>;
		150	compatible = "fsl,dcsr", "simple-bus";
		151
		152	dcsr-epu@0 {
		153	compatible = "fsl,dcsr-epu";
		154	interrupts = <52 2 0 0
		155	84 2 0 0
		156	85 2 0 0>;
		157	interrupt-parent = <&mpic>;
		158	reg = <0x0 0x1000>;
		159	};
		160	dcsr-npc {
		161	compatible = "fsl,dcsr-npc";
		162	reg = <0x1000 0x1000 0x1000000 0x8000>;
		163	};
		164	dcsr-nxc@2000 {
		165	compatible = "fsl,dcsr-nxc";
		166	reg = <0x2000 0x1000>;
		167	};
		168	dcsr-corenet {
		169	compatible = "fsl,dcsr-corenet";
		170	reg = <0x8000 0x1000 0xB0000 0x1000>;
		171	};
		172	dcsr-dpaa@9000 {
		173	compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
		174	reg = <0x9000 0x1000>;
		175	};
		176	dcsr-ocn@11000 {
		177	compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
		178	reg = <0x11000 0x1000>;
		179	};
		180	dcsr-ddr@12000 {
		181	compatible = "fsl,dcsr-ddr";
		182	dev-handle = <&ddr1>;
		183	reg = <0x12000 0x1000>;
		184	};
		185	dcsr-ddr@13000 {
		186	compatible = "fsl,dcsr-ddr";
		187	dev-handle = <&ddr2>;
		188	reg = <0x13000 0x1000>;
		189	};
		190	dcsr-nal@18000 {
		191	compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
		192	reg = <0x18000 0x1000>;
		193	};
		194	dcsr-rcpm@22000 {
		195	compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
		196	reg = <0x22000 0x1000>;
		197	};
		198	dcsr-cpu-sb-proxy@40000 {
		199	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		200	cpu-handle = <&cpu0>;
		201	reg = <0x40000 0x1000>;
		202	};
		203	dcsr-cpu-sb-proxy@41000 {
		204	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		205	cpu-handle = <&cpu1>;
		206	reg = <0x41000 0x1000>;
		207	};
		208	dcsr-cpu-sb-proxy@42000 {
		209	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		210	cpu-handle = <&cpu2>;
		211	reg = <0x42000 0x1000>;
		212	};
		213	dcsr-cpu-sb-proxy@43000 {
		214	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		215	cpu-handle = <&cpu3>;
		216	reg = <0x43000 0x1000>;
		217	};
		218	dcsr-cpu-sb-proxy@44000 {
		219	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		220	cpu-handle = <&cpu4>;
		221	reg = <0x44000 0x1000>;
		222	};
		223	dcsr-cpu-sb-proxy@45000 {
		224	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		225	cpu-handle = <&cpu5>;
		226	reg = <0x45000 0x1000>;
		227	};
		228	dcsr-cpu-sb-proxy@46000 {
		229	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		230	cpu-handle = <&cpu6>;
		231	reg = <0x46000 0x1000>;
		232	};
		233	dcsr-cpu-sb-proxy@47000 {
		234	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
		235	cpu-handle = <&cpu7>;
		236	reg = <0x47000 0x1000>;
		237	};
		238	};
		239
146	soc: soc@ffe000000 {	240	soc: soc@ffe000000 {
147	#address-cells = <1>;	241	#address-cells = <1>;
148	#size-cells = <1>;	242	#size-cells = <1>;
@@ -162,13 +256,13 @@
162	fsl,num-laws = <32>;	256	fsl,num-laws = <32>;
163	};	257	};
164		258
165	memory-controller@8000 {	259	ddr1: memory-controller@8000 {
166	compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";	260	compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
167	reg = <0x8000 0x1000>;	261	reg = <0x8000 0x1000>;
168	interrupts = <16 2 1 23>;	262	interrupts = <16 2 1 23>;
169	};	263	};
170		264
171	memory-controller@9000 {	265	ddr2: memory-controller@9000 {
172	compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";	266	compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
173	reg = <0x9000 0x1000>;	267	reg = <0x9000 0x1000>;
174	interrupts = <16 2 1 22>;	268	interrupts = <16 2 1 22>;