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diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
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1/*
2 * P2041RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "p2041si.dtsi"
36
37/ {
38 model = "fsl,P2041RDB";
39 compatible = "fsl,P2041RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 dcsr: dcsr@f00000000 {
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
50 };
51
52 soc: soc@ffe000000 {
53 spi@110000 {
54 flash@0 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "spansion,s25sl12801";
58 reg = <0>;
59 spi-max-frequency = <40000000>; /* input clock */
60 partition@u-boot {
61 label = "u-boot";
62 reg = <0x00000000 0x00100000>;
63 read-only;
64 };
65 partition@kernel {
66 label = "kernel";
67 reg = <0x00100000 0x00500000>;
68 read-only;
69 };
70 partition@dtb {
71 label = "dtb";
72 reg = <0x00600000 0x00100000>;
73 read-only;
74 };
75 partition@fs {
76 label = "file system";
77 reg = <0x00700000 0x00900000>;
78 };
79 };
80 };
81
82 i2c@118000 {
83 lm75b@48 {
84 compatible = "nxp,lm75a";
85 reg = <0x48>;
86 };
87 eeprom@50 {
88 compatible = "at24,24c256";
89 reg = <0x50>;
90 };
91 rtc@68 {
92 compatible = "pericom,pt7c4338";
93 reg = <0x68>;
94 };
95 };
96
97 i2c@118100 {
98 eeprom@50 {
99 compatible = "at24,24c256";
100 reg = <0x50>;
101 };
102 };
103
104 usb1: usb@211000 {
105 dr_mode = "host";
106 };
107 };
108
109 localbus@ffe124000 {
110 reg = <0xf 0xfe124000 0 0x1000>;
111 ranges = <0 0 0xf 0xe8000000 0x08000000>;
112
113 flash@0,0 {
114 compatible = "cfi-flash";
115 reg = <0 0 0x08000000>;
116 bank-width = <2>;
117 device-width = <2>;
118 };
119 };
120
121 pci0: pcie@ffe200000 {
122 reg = <0xf 0xfe200000 0 0x1000>;
123 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
124 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
125 pcie@0 {
126 ranges = <0x02000000 0 0xe0000000
127 0x02000000 0 0xe0000000
128 0 0x20000000
129
130 0x01000000 0 0x00000000
131 0x01000000 0 0x00000000
132 0 0x00010000>;
133 };
134 };
135
136 pci1: pcie@ffe201000 {
137 reg = <0xf 0xfe201000 0 0x1000>;
138 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
139 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
140 pcie@0 {
141 ranges = <0x02000000 0 0xe0000000
142 0x02000000 0 0xe0000000
143 0 0x20000000
144
145 0x01000000 0 0x00000000
146 0x01000000 0 0x00000000
147 0 0x00010000>;
148 };
149 };
150
151 pci2: pcie@ffe202000 {
152 reg = <0xf 0xfe202000 0 0x1000>;
153 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
154 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
155 pcie@0 {
156 ranges = <0x02000000 0 0xe0000000
157 0x02000000 0 0xe0000000
158 0 0x20000000
159
160 0x01000000 0 0x00000000
161 0x01000000 0 0x00000000
162 0 0x00010000>;
163 };
164 };
165};