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-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c63
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c66
2 files changed, 12 insertions, 117 deletions
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index 47e3fa32b075..bb11fef08472 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -66,48 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
66} 66}
67 67
68/* 68/*
69 * Enables the IRQ in the FPGA
70 */
71static void enable_cpci_irq(unsigned int irq)
72{
73 unmask_cpci_irq(irq);
74}
75
76/*
77 * Initialize the IRQ in the FPGA
78 */
79static unsigned int startup_cpci_irq(unsigned int irq)
80{
81 unmask_cpci_irq(irq);
82 return 0;
83}
84
85/*
86 * Disables the IRQ in the FPGA
87 */
88static void disable_cpci_irq(unsigned int irq)
89{
90 mask_cpci_irq(irq);
91}
92
93/*
94 * Masks and ACKs an IRQ
95 */
96static void mask_and_ack_cpci_irq(unsigned int irq)
97{
98 mask_cpci_irq(irq);
99}
100
101/*
102 * End IRQ processing
103 */
104static void end_cpci_irq(unsigned int irq)
105{
106 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
107 unmask_cpci_irq(irq);
108}
109
110/*
111 * Interrupt handler for interrupts coming from the FPGA chip. 69 * Interrupt handler for interrupts coming from the FPGA chip.
112 * It could be built in ethernet ports etc... 70 * It could be built in ethernet ports etc...
113 */ 71 */
@@ -125,27 +83,18 @@ void ll_cpci_irq(void)
125 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE); 83 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
126} 84}
127 85
128#define shutdown_cpci_irq disable_cpci_irq
129
130struct irq_chip cpci_irq_type = { 86struct irq_chip cpci_irq_type = {
131 .typename = "CPCI/FPGA", 87 .typename = "CPCI/FPGA",
132 .startup = startup_cpci_irq, 88 .ack = mask_cpci_irq,
133 .shutdown = shutdown_cpci_irq, 89 .mask = mask_cpci_irq,
134 .enable = enable_cpci_irq, 90 .mask_ack = mask_cpci_irq,
135 .disable = disable_cpci_irq, 91 .unmask = unmask_cpci_irq,
136 .ack = mask_and_ack_cpci_irq,
137 .end = end_cpci_irq,
138}; 92};
139 93
140void cpci_irq_init(void) 94void cpci_irq_init(void)
141{ 95{
142 int i; 96 int i;
143 97
144 /* Reset irq handlers pointers to NULL */ 98 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
145 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { 99 set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
146 irq_desc[i].status = IRQ_DISABLED;
147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 2;
149 irq_desc[i].chip = &cpci_irq_type;
150 }
151} 100}
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 510257dc205a..a7a80c0da569 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -60,48 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq)
60} 60}
61 61
62/* 62/*
63 * Enables the IRQ in the FPGA
64 */
65static void enable_uart_irq(unsigned int irq)
66{
67 unmask_uart_irq(irq);
68}
69
70/*
71 * Initialize the IRQ in the FPGA
72 */
73static unsigned int startup_uart_irq(unsigned int irq)
74{
75 unmask_uart_irq(irq);
76 return 0;
77}
78
79/*
80 * Disables the IRQ in the FPGA
81 */
82static void disable_uart_irq(unsigned int irq)
83{
84 mask_uart_irq(irq);
85}
86
87/*
88 * Masks and ACKs an IRQ
89 */
90static void mask_and_ack_uart_irq(unsigned int irq)
91{
92 mask_uart_irq(irq);
93}
94
95/*
96 * End IRQ processing
97 */
98static void end_uart_irq(unsigned int irq)
99{
100 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
101 unmask_uart_irq(irq);
102}
103
104/*
105 * Interrupt handler for interrupts coming from the FPGA chip. 63 * Interrupt handler for interrupts coming from the FPGA chip.
106 */ 64 */
107void ll_uart_irq(void) 65void ll_uart_irq(void)
@@ -118,28 +76,16 @@ void ll_uart_irq(void)
118 do_IRQ(ls1bit8(irq_src) + 74); 76 do_IRQ(ls1bit8(irq_src) + 74);
119} 77}
120 78
121#define shutdown_uart_irq disable_uart_irq
122
123struct irq_chip uart_irq_type = { 79struct irq_chip uart_irq_type = {
124 .typename = "UART/FPGA", 80 .typename = "UART/FPGA",
125 .startup = startup_uart_irq, 81 .ack = mask_uart_irq,
126 .shutdown = shutdown_uart_irq, 82 .mask = mask_uart_irq,
127 .enable = enable_uart_irq, 83 .mask_ack = mask_uart_irq,
128 .disable = disable_uart_irq, 84 .unmask = unmask_uart_irq,
129 .ack = mask_and_ack_uart_irq,
130 .end = end_uart_irq,
131}; 85};
132 86
133void uart_irq_init(void) 87void uart_irq_init(void)
134{ 88{
135 /* Reset irq handlers pointers to NULL */ 89 set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
136 irq_desc[80].status = IRQ_DISABLED; 90 set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
137 irq_desc[80].action = 0;
138 irq_desc[80].depth = 2;
139 irq_desc[80].chip = &uart_irq_type;
140
141 irq_desc[81].status = IRQ_DISABLED;
142 irq_desc[81].action = 0;
143 irq_desc[81].depth = 2;
144 irq_desc[81].chip = &uart_irq_type;
145} 91}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 11:46:55 -0500