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-rw-r--r--arch/mips/kernel/r4k_switch.S33
1 files changed, 0 insertions, 33 deletions
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index abacac7c33ef..547c522964de 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -87,18 +87,6 @@
87 87
88 PTR_ADDU t0, $28, _THREAD_SIZE - 32 88 PTR_ADDU t0, $28, _THREAD_SIZE - 32
89 set_saved_sp t0, t1, t2 89 set_saved_sp t0, t1, t2
90#ifdef CONFIG_MIPS_MT_SMTC
91 /* Read-modify-writes of Status must be atomic on a VPE */
92 mfc0 t2, CP0_TCSTATUS
93 ori t1, t2, TCSTATUS_IXMT
94 mtc0 t1, CP0_TCSTATUS
95 andi t2, t2, TCSTATUS_IXMT
96 _ehb
97 DMT 8 # dmt t0
98 move t1,ra
99 jal mips_ihb
100 move ra,t1
101#endif /* CONFIG_MIPS_MT_SMTC */
102 mfc0 t1, CP0_STATUS /* Do we really need this? */ 90 mfc0 t1, CP0_STATUS /* Do we really need this? */
103 li a3, 0xff01 91 li a3, 0xff01
104 and t1, a3 92 and t1, a3
@@ -107,18 +95,6 @@
107 and a2, a3 95 and a2, a3
108 or a2, t1 96 or a2, t1
109 mtc0 a2, CP0_STATUS 97 mtc0 a2, CP0_STATUS
110#ifdef CONFIG_MIPS_MT_SMTC
111 _ehb
112 andi t0, t0, VPECONTROL_TE
113 beqz t0, 1f
114 emt
1151:
116 mfc0 t1, CP0_TCSTATUS
117 xori t1, t1, TCSTATUS_IXMT
118 or t1, t1, t2
119 mtc0 t1, CP0_TCSTATUS
120 _ehb
121#endif /* CONFIG_MIPS_MT_SMTC */
122 move v0, a0 98 move v0, a0
123 jr ra 99 jr ra
124 END(resume) 100 END(resume)
@@ -176,19 +152,10 @@ LEAF(_restore_msa)
176#define FPU_DEFAULT 0x00000000 152#define FPU_DEFAULT 0x00000000
177 153
178LEAF(_init_fpu) 154LEAF(_init_fpu)
179#ifdef CONFIG_MIPS_MT_SMTC
180 /* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
181 mfc0 t0, CP0_TCSTATUS
182 /* Bit position is the same for Status, TCStatus */
183 li t1, ST0_CU1
184 or t0, t1
185 mtc0 t0, CP0_TCSTATUS
186#else /* Normal MIPS CU1 enable */
187 mfc0 t0, CP0_STATUS 155 mfc0 t0, CP0_STATUS
188 li t1, ST0_CU1 156 li t1, ST0_CU1
189 or t0, t1 157 or t0, t1
190 mtc0 t0, CP0_STATUS 158 mtc0 t0, CP0_STATUS
191#endif /* CONFIG_MIPS_MT_SMTC */
192 enable_fpu_hazard 159 enable_fpu_hazard
193 160
194 li t1, FPU_DEFAULT 161 li t1, FPU_DEFAULT