8 files changed, 365 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
new file mode 100644
index 000000000000..107104c3cd12
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
@@ -0,0 +1,48 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Basler eXcite has an RM9122 processor.
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_icache_snoops_remote_store  0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
new file mode 100644
index 000000000000..4c29ba44992c
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/excite.h
@@ -0,0 +1,154 @@
+#ifndef __EXCITE_H__
+#define __EXCITE_H__
+
+#include <linux/init.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+
+#define EXCITE_CPU_EXT_CLOCK 100000000
+
+#if !defined(__ASSEMBLY__)
+void __init excite_kgdb_init(void);
+void excite_procfs_init(void);
+extern unsigned long memsize;
+extern char modetty[];
+extern u32 unit_id;
+#endif
+
+/* Base name for XICAP devices */
+#define XICAP_NAME      "xicap_gpi"
+
+/* OCD register offsets */
+#define LKB0            0x0038
+#define LKB5            0x0128
+#define LKM5            0x012C
+#define LKB7            0x0138
+#define LKM7            0x013c
+#define LKB8            0x0140
+#define LKM8            0x0144
+#define LKB9            0x0148
+#define LKM9            0x014c
+#define LKB10           0x0150
+#define LKM10           0x0154
+#define LKB11           0x0158
+#define LKM11           0x015c
+#define LKB12           0x0160
+#define LKM12           0x0164
+#define LKB13           0x0168
+#define LKM13           0x016c
+#define LDP0            0x0200
+#define LDP1            0x0210
+#define LDP2            0x0220
+#define LDP3            0x0230
+#define INTPIN0         0x0A40
+#define INTPIN1         0x0A44
+#define INTPIN2         0x0A48
+#define INTPIN3         0x0A4C
+#define INTPIN4         0x0A50
+#define INTPIN5         0x0A54
+#define INTPIN6         0x0A58
+#define INTPIN7         0x0A5C
+
+
+
+
+/* TITAN register offsets */
+#define CPRR            0x0004
+#define CPDSR           0x0008
+#define CPTC0R          0x000c
+#define CPTC1R          0x0010
+#define CPCFG0          0x0020
+#define CPCFG1          0x0024
+#define CPDST0A         0x0028
+#define CPDST0B         0x002c
+#define CPDST1A         0x0030
+#define CPDST1B         0x0034
+#define CPXDSTA         0x0038
+#define CPXDSTB         0x003c
+#define CPXCISRA        0x0048
+#define CPXCISRB        0x004c
+#define CPGIG0ER        0x0050
+#define CPGIG1ER        0x0054
+#define CPGRWL          0x0068
+#define CPURSLMT        0x00f8
+#define UACFG           0x0200
+#define UAINTS          0x0204
+#define SDRXFCIE        0x4828
+#define SDTXFCIE        0x4928
+#define INTP0Status0    0x1B00
+#define INTP0Mask0      0x1B04
+#define INTP0Set0       0x1B08
+#define INTP0Clear0     0x1B0C
+#define GXCFG           0x5000
+#define GXDMADRPFX      0x5018
+#define GXDMA_DESCADR   0x501c
+#define GXCH0TDESSTRT   0x5054
+
+/* IRQ definitions */
+#define NMICONFIG               0xac0
+#define TITAN_MSGINT    0xc4
+#define TITAN_IRQ       ((TITAN_MSGINT / 0x20) + 2)
+#define FPGA0_MSGINT    0x5a
+#define FPGA0_IRQ       ((FPGA0_MSGINT / 0x20) + 2)
+#define FPGA1_MSGINT    0x7b
+#define FPGA1_IRQ       ((FPGA1_MSGINT / 0x20) + 2)
+#define PHY_MSGINT      0x9c
+#define PHY_IRQ         ((PHY_MSGINT   / 0x20) + 2)
+
+#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
+/* Pre-release units used interrupt pin #9 */
+#define USB_IRQ         11
+#else
+/* Re-designed units use interrupt pin #1 */
+#define USB_MSGINT      0x39
+#define USB_IRQ         ((USB_MSGINT / 0x20) + 2)
+#endif
+#define TIMER_IRQ       12
+
+
+/* Device address ranges */
+#define EXCITE_OFFS_OCD         0x1fffc000
+#define EXCITE_SIZE_OCD         (16 * 1024)
+#define EXCITE_PHYS_OCD         CPHYSADDR(EXCITE_OFFS_OCD)
+#define EXCITE_ADDR_OCD         CKSEG1ADDR(EXCITE_OFFS_OCD)
+
+#define EXCITE_OFFS_SCRAM       0x1fffa000
+#define EXCITE_SIZE_SCRAM       (8 << 10)
+#define EXCITE_PHYS_SCRAM       CPHYSADDR(EXCITE_OFFS_SCRAM)
+#define EXCITE_ADDR_SCRAM       CKSEG1ADDR(EXCITE_OFFS_SCRAM)
+
+#define EXCITE_OFFS_PCI_IO      0x1fff8000
+#define EXCITE_SIZE_PCI_IO      (8 << 10)
+#define EXCITE_PHYS_PCI_IO      CPHYSADDR(EXCITE_OFFS_PCI_IO)
+#define EXCITE_ADDR_PCI_IO      CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
+
+#define EXCITE_OFFS_TITAN       0x1fff0000
+#define EXCITE_SIZE_TITAN       (32 << 10)
+#define EXCITE_PHYS_TITAN       CPHYSADDR(EXCITE_OFFS_TITAN)
+#define EXCITE_ADDR_TITAN       CKSEG1ADDR(EXCITE_OFFS_TITAN)
+
+#define EXCITE_OFFS_PCI_MEM     0x1ffe0000
+#define EXCITE_SIZE_PCI_MEM     (64 << 10)
+#define EXCITE_PHYS_PCI_MEM     CPHYSADDR(EXCITE_OFFS_PCI_MEM)
+#define EXCITE_ADDR_PCI_MEM     CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
+
+#define EXCITE_OFFS_FPGA        0x1ffdc000
+#define EXCITE_SIZE_FPGA        (16 << 10)
+#define EXCITE_PHYS_FPGA        CPHYSADDR(EXCITE_OFFS_FPGA)
+#define EXCITE_ADDR_FPGA        CKSEG1ADDR(EXCITE_OFFS_FPGA)
+
+#define EXCITE_OFFS_NAND        0x1ffd8000
+#define EXCITE_SIZE_NAND        (16 << 10)
+#define EXCITE_PHYS_NAND        CPHYSADDR(EXCITE_OFFS_NAND)
+#define EXCITE_ADDR_NAND        CKSEG1ADDR(EXCITE_OFFS_NAND)
+
+#define EXCITE_OFFS_BOOTROM     0x1f000000
+#define EXCITE_SIZE_BOOTROM     (8 << 20)
+#define EXCITE_PHYS_BOOTROM     CPHYSADDR(EXCITE_OFFS_BOOTROM)
+#define EXCITE_ADDR_BOOTROM     CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
+
+/* FPGA address offsets */
+#define EXCITE_FPGA_DPR         0x0104  /* dual-ported ram */
+#define EXCITE_FPGA_SYSCTL      0x0200  /* system control register block */
+
+#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
new file mode 100644
index 000000000000..0a1ef69bece7
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/excite_fpga.h
@@ -0,0 +1,80 @@
+#ifndef EXCITE_FPGA_H_INCLUDED
+#define EXCITE_FPGA_H_INCLUDED
+
+
+/**
+ * Address alignment of the individual FPGA bytes.
+ * The address arrangement of the individual bytes of the FPGA is two
+ * byte aligned at the embedded MK2 platform.
+ */
+#ifdef EXCITE_CCI_FPGA_MK2
+typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
+#else
+typedef unsigned char excite_cci_fpga_align_t;
+#endif
+
+
+/**
+ * Size of Dual Ported RAM.
+ */
+#define EXCITE_DPR_SIZE 263
+
+
+/**
+ * Size of Reserved Status Fields in Dual Ported RAM.
+ */
+#define EXCITE_DPR_STATUS_SIZE 7
+
+
+
+/**
+ * FPGA.
+ * Hardware register layout of the FPGA interface. The FPGA must accessed
+ * byte wise solely.
+ * @see EXCITE_CCI_DPR_MK2
+ */
+typedef struct excite_fpga {
+
+        /**
+         * Dual Ported RAM.
+         */
+        excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
+
+        /**
+         * Status.
+         */
+        excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
+
+#ifdef EXCITE_CCI_FPGA_MK2
+        /**
+         * RM9000 Interrupt.
+         * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
+         */
+        excite_cci_fpga_align_t rm9k_int;
+#else
+        /**
+         * MK2 Interrupt.
+         * Write access initiates interrupt at the ARM processor of the MK2.
+         */
+        excite_cci_fpga_align_t mk2_int;
+
+        excite_cci_fpga_align_t gap[0x1000-0x10f];
+
+        /**
+         * IRQ Source/Acknowledge.
+         */
+        excite_cci_fpga_align_t rm9k_irq_src;
+
+        /**
+         * IRQ Mask.
+         * Set bits enable the related interrupt.
+         */
+        excite_cci_fpga_align_t rm9k_irq_mask;
+#endif
+
+
+} excite_fpga;
+
+
+
+#endif  /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
new file mode 100644
index 000000000000..c4cf6140622e
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/excite_nandflash.h
@@ -0,0 +1,7 @@
+#ifndef __EXCITE_NANDFLASH_H__
+#define __EXCITE_NANDFLASH_H__
+
+/* Resource names */
+#define EXCITE_NANDFLASH_RESOURCE_REGS  "excite_nandflash_regs"
+
+#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
new file mode 100644
index 000000000000..94705a46f72e
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/rm9k_eth.h
@@ -0,0 +1,23 @@
+#if !defined(__RM9K_ETH_H__)
+#define __RM9K_ETH_H__
+
+#define RM9K_GE_NAME                    "rm9k_ge"
+
+/* Resource names */
+#define RM9K_GE_RESOURCE_MAC            "rm9k_ge_mac"
+#define RM9K_GE_RESOURCE_MSTAT          "rm9k_ge_mstat"
+#define RM9K_GE_RESOURCE_PKTPROC        "rm9k_ge_pktproc"
+#define RM9K_GE_RESOURCE_XDMA           "rm9k_ge_xdma"
+#define RM9K_GE_RESOURCE_FIFO_RX        "rm9k_ge_fifo_rx"
+#define RM9K_GE_RESOURCE_FIFO_TX        "rm9k_ge_fifo_tx"
+#define RM9K_GE_RESOURCE_FIFOMEM_RX     "rm9k_ge_fifo_memory_rx"
+#define RM9K_GE_RESOURCE_FIFOMEM_TX     "rm9k_ge_fifo_memory_tx"
+#define RM9K_GE_RESOURCE_PHY            "rm9k_ge_phy"
+#define RM9K_GE_RESOURCE_DMADESC_RX     "rm9k_ge_dmadesc_rx"
+#define RM9K_GE_RESOURCE_DMADESC_TX     "rm9k_ge_dmadesc_tx"
+#define RM9K_GE_RESOURCE_IRQ_MAIN       "rm9k_ge_irq_main"
+#define RM9K_GE_RESOURCE_IRQ_PHY        "rm9k_ge_irq_phy"
+#define RM9K_GE_RESOURCE_GPI_SLICE      "rm9k_ge_gpi_slice"
+#define RM9K_GE_RESOURCE_MDIO_CHANNEL   "rm9k_ge_mdio_channel"
+
+#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
new file mode 100644
index 000000000000..3fa3c08d2da7
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
@@ -0,0 +1,12 @@
+#ifndef __RM9K_WDT_H__
+#define __RM9K_WDT_H__
+
+/* Device name */
+#define WDT_NAME                "wdt_gpi"
+
+/* Resource names */
+#define WDT_RESOURCE_REGS       "excite_watchdog_regs"
+#define WDT_RESOURCE_IRQ        "excite_watchdog_irq"
+#define WDT_RESOURCE_COUNTER    "excite_watchdog_counter"
+
+#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
new file mode 100644
index 000000000000..009577734a8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
@@ -0,0 +1,16 @@
+#ifndef __EXCITE_XICAP_H__
+#define __EXCITE_XICAP_H__
+
+
+/* Resource names */
+#define XICAP_RESOURCE_FIFO_RX          "xicap_fifo_rx"
+#define XICAP_RESOURCE_FIFO_TX          "xicap_fifo_tx"
+#define XICAP_RESOURCE_XDMA             "xicap_xdma"
+#define XICAP_RESOURCE_DMADESC          "xicap_dmadesc"
+#define XICAP_RESOURCE_PKTPROC          "xicap_pktproc"
+#define XICAP_RESOURCE_IRQ              "xicap_irq"
+#define XICAP_RESOURCE_GPI_SLICE        "xicap_gpi_slice"
+#define XICAP_RESOURCE_FIFO_BLK         "xicap_fifo_blocks"
+#define XICAP_RESOURCE_PKT_STREAM       "xicap_pkt_stream"
+
+#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-excite/war.h
new file mode 100644
index 000000000000..1f82180c1598
--- /dev/null
+++ b/arch/mips/include/asm/mach-excite/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
+#define __ASM_MIPS_MACH_EXCITE_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             1
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */