diff options
Diffstat (limited to 'arch/mips/include/asm/dec/kn05.h')
-rw-r--r-- | arch/mips/include/asm/dec/kn05.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/mips/include/asm/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h index 56d22dc8803a..8e14f677e5ef 100644 --- a/arch/mips/include/asm/dec/kn05.h +++ b/arch/mips/include/asm/dec/kn05.h | |||
@@ -49,12 +49,20 @@ | |||
49 | #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ | 49 | #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ |
50 | 50 | ||
51 | /* | 51 | /* |
52 | * MB ASIC interrupt bits. | ||
53 | */ | ||
54 | #define KN4K_MB_INR_MB 4 /* ??? */ | ||
55 | #define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */ | ||
56 | #define KN4K_MB_INR_RES_2 2 /* unused */ | ||
57 | #define KN4K_MB_INR_RTC 1 /* RTC */ | ||
58 | #define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */ | ||
59 | |||
60 | /* | ||
52 | * Bits for the MB interrupt register. | 61 | * Bits for the MB interrupt register. |
53 | * The register appears read-only. | 62 | * The register appears read-only. |
54 | */ | 63 | */ |
55 | #define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ | 64 | #define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */ |
56 | #define KN4K_MB_INT_RTC (1<<1) /* RTC? */ | 65 | #define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */ |
57 | #define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ | ||
58 | 66 | ||
59 | /* | 67 | /* |
60 | * Bits for the MB control & status register. | 68 | * Bits for the MB control & status register. |
@@ -70,6 +78,7 @@ | |||
70 | #define KN4K_MB_CSR_NC (1<<14) /* ??? */ | 78 | #define KN4K_MB_CSR_NC (1<<14) /* ??? */ |
71 | #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ | 79 | #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ |
72 | #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ | 80 | #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ |
81 | #define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */ | ||
73 | #define KN4K_MB_CSR_FW (1<<21) /* ??? */ | 82 | #define KN4K_MB_CSR_FW (1<<21) /* ??? */ |
74 | #define KN4K_MB_CSR_W (1<<31) /* ??? */ | 83 | #define KN4K_MB_CSR_W (1<<31) /* ??? */ |
75 | 84 | ||