diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-09 21:10:34 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-09 21:10:34 -0400 |
commit | 82abb273d838318424644d8f02825db0fbbd400a (patch) | |
tree | e1ea8a92db4ba68f347249986ffe3a25ffbf8219 /arch/mips/include/asm/dec/kn05.h | |
parent | 9b651cc2277b5e4883012ebab0fea2bcda4cbafa (diff) | |
parent | f8647b506d7116a1a3accd8d618184096e85f50b (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
- three fixes for 3.15 that didn't make it in time
- limited Octeon 3 support.
- paravirtualization support
- improvment to platform support for Netlogix SOCs.
- add support for powering down the Malta eval board in software
- add many instructions to the in-kernel microassembler.
- add support for the BPF JIT.
- minor cleanups of the BCM47xx code.
- large cleanup of math emu code resulting in significant code size
reduction, better readability of the code and more accurate
emulation.
- improvments to the MIPS CPS code.
- support C3 power status for the R4k count/compare clock device.
- improvments to the GIO support for older SGI workstations.
- increase number of supported CPUs to 256; this can be reached on
certain embedded multithreaded ccNUMA configurations.
- various small cleanups, updates and fixes
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (173 commits)
MIPS: IP22/IP28: Improve GIO support
MIPS: Octeon: Add twsi interrupt initialization for OCTEON 3XXX, 5XXX, 63XX
DEC: Document the R4k MB ASIC mini interrupt controller
DEC: Add self as the maintainer
MIPS: Add microMIPS MSA support.
MIPS: Replace calls to obsolete strict_strto call with kstrto* equivalents.
MIPS: Replace obsolete strict_strto call with kstrto
MIPS: BFP: Simplify code slightly.
MIPS: Call find_vma with the mmap_sem held
MIPS: Fix 'write_msa_##' inline macro.
MIPS: Fix MSA toolchain support detection.
mips: Update the email address of Geert Uytterhoeven
MIPS: Add minimal defconfig for mips_paravirt
MIPS: Enable build for new system 'paravirt'
MIPS: paravirt: Add pci controller for virtio
MIPS: Add code for new system 'paravirt'
MIPS: Add functions for hypervisor call
MIPS: OCTEON: Add OCTEON3 to __get_cpu_type
MIPS: Add function get_ebase_cpunum
MIPS: Add minimal support for OCTEON3 to c-r4k.c
...
Diffstat (limited to 'arch/mips/include/asm/dec/kn05.h')
-rw-r--r-- | arch/mips/include/asm/dec/kn05.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/mips/include/asm/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h index 56d22dc8803a..8e14f677e5ef 100644 --- a/arch/mips/include/asm/dec/kn05.h +++ b/arch/mips/include/asm/dec/kn05.h | |||
@@ -49,12 +49,20 @@ | |||
49 | #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ | 49 | #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ |
50 | 50 | ||
51 | /* | 51 | /* |
52 | * MB ASIC interrupt bits. | ||
53 | */ | ||
54 | #define KN4K_MB_INR_MB 4 /* ??? */ | ||
55 | #define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */ | ||
56 | #define KN4K_MB_INR_RES_2 2 /* unused */ | ||
57 | #define KN4K_MB_INR_RTC 1 /* RTC */ | ||
58 | #define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */ | ||
59 | |||
60 | /* | ||
52 | * Bits for the MB interrupt register. | 61 | * Bits for the MB interrupt register. |
53 | * The register appears read-only. | 62 | * The register appears read-only. |
54 | */ | 63 | */ |
55 | #define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ | 64 | #define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */ |
56 | #define KN4K_MB_INT_RTC (1<<1) /* RTC? */ | 65 | #define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */ |
57 | #define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ | ||
58 | 66 | ||
59 | /* | 67 | /* |
60 | * Bits for the MB control & status register. | 68 | * Bits for the MB control & status register. |
@@ -70,6 +78,7 @@ | |||
70 | #define KN4K_MB_CSR_NC (1<<14) /* ??? */ | 78 | #define KN4K_MB_CSR_NC (1<<14) /* ??? */ |
71 | #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ | 79 | #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ |
72 | #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ | 80 | #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ |
81 | #define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */ | ||
73 | #define KN4K_MB_CSR_FW (1<<21) /* ??? */ | 82 | #define KN4K_MB_CSR_FW (1<<21) /* ??? */ |
74 | #define KN4K_MB_CSR_W (1<<31) /* ??? */ | 83 | #define KN4K_MB_CSR_W (1<<31) /* ??? */ |
75 | 84 | ||