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-rw-r--r--arch/mips/dec/Makefile4
-rw-r--r--arch/mips/dec/ecc-berr.c48
-rw-r--r--arch/mips/dec/int-handler.S18
-rw-r--r--arch/mips/dec/kn01-berr.c201
-rw-r--r--arch/mips/dec/kn02-irq.c13
-rw-r--r--arch/mips/dec/kn02xa-berr.c139
-rw-r--r--arch/mips/dec/prom/identify.c28
-rw-r--r--arch/mips/dec/prom/init.c16
-rw-r--r--arch/mips/dec/prom/memory.c14
-rw-r--r--arch/mips/dec/reset.c2
-rw-r--r--arch/mips/dec/setup.c57
11 files changed, 460 insertions, 80 deletions
diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile
index 688757a97cb8..ed181fdc3ac9 100644
--- a/arch/mips/dec/Makefile
+++ b/arch/mips/dec/Makefile
@@ -2,8 +2,8 @@
2# Makefile for the DECstation family specific parts of the kernel 2# Makefile for the DECstation family specific parts of the kernel
3# 3#
4 4
5obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \ 5obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
6 setup.o time.o 6 kn02-irq.o kn02xa-berr.o reset.o setup.o time.o
7 7
8obj-$(CONFIG_PROM_CONSOLE) += promcon.o 8obj-$(CONFIG_PROM_CONSOLE) += promcon.o
9obj-$(CONFIG_CPU_HAS_WB) += wbflush.o 9obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 6dbce92eb068..cc24c5ed0c05 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -6,7 +6,7 @@
6 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03), 6 * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
7 * 5900/260 (KN05) systems. 7 * 5900/260 (KN05) systems.
8 * 8 *
9 * Copyright (c) 2003 Maciej W. Rozycki 9 * Copyright (c) 2003, 2005 Maciej W. Rozycki
10 * 10 *
11 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License 12 * modify it under the terms of the GNU General Public License
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/interrupt.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/spinlock.h> 21#include <linux/spinlock.h>
@@ -57,7 +58,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
57 58
58 const char *kind, *agent, *cycle, *event; 59 const char *kind, *agent, *cycle, *event;
59 const char *status = "", *xbit = "", *fmt = ""; 60 const char *status = "", *xbit = "", *fmt = "";
60 dma_addr_t address; 61 unsigned long address;
61 u16 syn = 0, sngl; 62 u16 syn = 0, sngl;
62 63
63 int i = 0; 64 int i = 0;
@@ -66,7 +67,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66 u32 chksyn = *kn0x_chksyn; 67 u32 chksyn = *kn0x_chksyn;
67 int action = MIPS_BE_FATAL; 68 int action = MIPS_BE_FATAL;
68 69
69 /* For non-ECC ack ASAP, so any subsequent errors get caught. */ 70 /* For non-ECC ack ASAP, so that any subsequent errors get caught. */
70 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID) 71 if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
71 dec_ecc_be_ack(); 72 dec_ecc_be_ack();
72 73
@@ -74,7 +75,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
74 75
75 if (!(erraddr & KN0X_EAR_VALID)) { 76 if (!(erraddr & KN0X_EAR_VALID)) {
76 /* No idea what happened. */ 77 /* No idea what happened. */
77 printk(KERN_ALERT "Unidentified bus error %s.\n", kind); 78 printk(KERN_ALERT "Unidentified bus error %s\n", kind);
78 return action; 79 return action;
79 } 80 }
80 81
@@ -126,7 +127,7 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
126 /* Ack now, no rewrite will happen. */ 127 /* Ack now, no rewrite will happen. */
127 dec_ecc_be_ack(); 128 dec_ecc_be_ack();
128 129
129 fmt = KERN_ALERT "%s" "invalid.\n"; 130 fmt = KERN_ALERT "%s" "invalid\n";
130 } else { 131 } else {
131 sngl = syn & KN0X_ESR_SNGLO; 132 sngl = syn & KN0X_ESR_SNGLO;
132 syn &= KN0X_ESR_SYNLO; 133 syn &= KN0X_ESR_SYNLO;
@@ -144,7 +145,8 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
144 } else if (!sngl) { 145 } else if (!sngl) {
145 status = dbestr; 146 status = dbestr;
146 } else { 147 } else {
147 volatile u32 *ptr = (void *)KSEG1ADDR(address); 148 volatile u32 *ptr =
149 (void *)CKSEG1ADDR(address);
148 150
149 *ptr = *ptr; /* Rewrite. */ 151 *ptr = *ptr; /* Rewrite. */
150 iob(); 152 iob();
@@ -160,12 +162,12 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
160 if (syn == 0x01) { 162 if (syn == 0x01) {
161 fmt = KERN_ALERT "%s" 163 fmt = KERN_ALERT "%s"
162 "%#04x -- %s bit error " 164 "%#04x -- %s bit error "
163 "at check bit C%s.\n"; 165 "at check bit C%s\n";
164 xbit = "X"; 166 xbit = "X";
165 } else { 167 } else {
166 fmt = KERN_ALERT "%s" 168 fmt = KERN_ALERT "%s"
167 "%#04x -- %s bit error " 169 "%#04x -- %s bit error "
168 "at check bit C%s%u.\n"; 170 "at check bit C%s%u\n";
169 } 171 }
170 i = syn >> 2; 172 i = syn >> 2;
171 } else { 173 } else {
@@ -175,16 +177,16 @@ static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
175 if (i < 32) 177 if (i < 32)
176 fmt = KERN_ALERT "%s" 178 fmt = KERN_ALERT "%s"
177 "%#04x -- %s bit error " 179 "%#04x -- %s bit error "
178 "at data bit D%s%u.\n"; 180 "at data bit D%s%u\n";
179 else 181 else
180 fmt = KERN_ALERT "%s" 182 fmt = KERN_ALERT "%s"
181 "%#04x -- %s bit error.\n"; 183 "%#04x -- %s bit error\n";
182 } 184 }
183 } 185 }
184 } 186 }
185 187
186 if (action != MIPS_BE_FIXUP) 188 if (action != MIPS_BE_FIXUP)
187 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n", 189 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
188 kind, agent, cycle, event, address); 190 kind, agent, cycle, event, address);
189 191
190 if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR) 192 if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
@@ -203,11 +205,11 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
203 int action = dec_ecc_be_backend(regs, 0, 1); 205 int action = dec_ecc_be_backend(regs, 0, 1);
204 206
205 if (action == MIPS_BE_DISCARD) 207 if (action == MIPS_BE_DISCARD)
206 return IRQ_NONE; 208 return IRQ_HANDLED;
207 209
208 /* 210 /*
209 * FIXME: Find affected processes and kill them, otherwise we 211 * FIXME: Find the affected processes and kill them, otherwise
210 * must die. 212 * we must die.
211 * 213 *
212 * The interrupt is asynchronously delivered thus EPC and RA 214 * The interrupt is asynchronously delivered thus EPC and RA
213 * may be irrelevant, but are printed for a reference. 215 * may be irrelevant, but are printed for a reference.
@@ -225,16 +227,16 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs)
225 */ 227 */
226static inline void dec_kn02_be_init(void) 228static inline void dec_kn02_be_init(void)
227{ 229{
228 volatile u32 *csr = (void *)KN02_CSR_BASE; 230 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
229 unsigned long flags; 231 unsigned long flags;
230 232
231 kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR); 233 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
232 kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN); 234 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
233 235
234 spin_lock_irqsave(&kn02_lock, flags); 236 spin_lock_irqsave(&kn02_lock, flags);
235 237
236 /* Preset write-only bits of the Control Register cache. */ 238 /* Preset write-only bits of the Control Register cache. */
237 cached_kn02_csr = *csr | KN03_CSR_LEDS; 239 cached_kn02_csr = *csr | KN02_CSR_LEDS;
238 240
239 /* Set normal ECC detection and generation. */ 241 /* Set normal ECC detection and generation. */
240 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN); 242 cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
@@ -248,11 +250,11 @@ static inline void dec_kn02_be_init(void)
248 250
249static inline void dec_kn03_be_init(void) 251static inline void dec_kn03_be_init(void)
250{ 252{
251 volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); 253 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
252 volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR); 254 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
253 255
254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); 256 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); 257 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
256 258
257 /* 259 /*
258 * Set normal ECC detection and generation, enable ECC correction. 260 * Set normal ECC detection and generation, enable ECC correction.
@@ -264,7 +266,7 @@ static inline void dec_kn03_be_init(void)
264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | 266 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
265 KN03_MCR_CORRECT; 267 KN03_MCR_CORRECT;
266 if (current_cpu_data.cputype == CPU_R4400SC) 268 if (current_cpu_data.cputype == CPU_R4400SC)
267 *mbcs |= KN05_MB_CSR_EE; 269 *mbcs |= KN4K_MB_CSR_EE;
268 fast_iob(); 270 fast_iob();
269} 271}
270 272
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index c89768d5c4e5..41fa372007bf 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -2,9 +2,9 @@
2 * arch/mips/dec/int-handler.S 2 * arch/mips/dec/int-handler.S
3 * 3 *
4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen 4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen
5 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki 5 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
6 * 6 *
7 * Written by Ralf Baechle and Andreas Busse, modified for DECStation 7 * Written by Ralf Baechle and Andreas Busse, modified for DECstation
8 * support by Paul Antoine and Harald Koerfgen. 8 * support by Paul Antoine and Harald Koerfgen.
9 * 9 *
10 * completly rewritten: 10 * completly rewritten:
@@ -14,11 +14,12 @@
14 * by Maciej W. Rozycki. 14 * by Maciej W. Rozycki.
15 */ 15 */
16#include <linux/config.h> 16#include <linux/config.h>
17
18#include <asm/addrspace.h>
17#include <asm/asm.h> 19#include <asm/asm.h>
18#include <asm/regdef.h>
19#include <asm/mipsregs.h> 20#include <asm/mipsregs.h>
21#include <asm/regdef.h>
20#include <asm/stackframe.h> 22#include <asm/stackframe.h>
21#include <asm/addrspace.h>
22 23
23#include <asm/dec/interrupts.h> 24#include <asm/dec/interrupts.h>
24#include <asm/dec/ioasic_addrs.h> 25#include <asm/dec/ioasic_addrs.h>
@@ -28,11 +29,14 @@
28#include <asm/dec/kn02xa.h> 29#include <asm/dec/kn02xa.h>
29#include <asm/dec/kn03.h> 30#include <asm/dec/kn03.h>
30 31
32#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
33#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
34#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
31 35
32 .text 36 .text
33 .set noreorder 37 .set noreorder
34/* 38/*
35 * decstation_handle_int: Interrupt handler for DECStations 39 * decstation_handle_int: Interrupt handler for DECstations
36 * 40 *
37 * We follow the model in the Indy interrupt code by David Miller, where he 41 * We follow the model in the Indy interrupt code by David Miller, where he
38 * says: a lot of complication here is taken away because: 42 * says: a lot of complication here is taken away because:
@@ -48,7 +52,7 @@
48 * 3) Linux only thinks in terms of all IRQs on or all IRQs 52 * 3) Linux only thinks in terms of all IRQs on or all IRQs
49 * off, nothing in between like BSD spl() brain-damage. 53 * off, nothing in between like BSD spl() brain-damage.
50 * 54 *
51 * Furthermore, the IRQs on the DECStations look basically (barring 55 * Furthermore, the IRQs on the DECstations look basically (barring
52 * software IRQs which we don't use at all) like... 56 * software IRQs which we don't use at all) like...
53 * 57 *
54 * DS2100/3100's, aka kn01, aka Pmax: 58 * DS2100/3100's, aka kn01, aka Pmax:
@@ -61,7 +65,7 @@
61 * 3 Lance Ethernet 65 * 3 Lance Ethernet
62 * 4 DZ11 serial 66 * 4 DZ11 serial
63 * 5 RTC 67 * 5 RTC
64 * 6 Memory Controller 68 * 6 Memory Controller & Video
65 * 7 FPU 69 * 7 FPU
66 * 70 *
67 * DS5000/200, aka kn02, aka 3max: 71 * DS5000/200, aka kn02, aka 3max:
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
new file mode 100644
index 000000000000..b9271db9bc76
--- /dev/null
+++ b/arch/mips/dec/kn01-berr.c
@@ -0,0 +1,201 @@
1/*
2 * linux/arch/mips/dec/kn01-berr.c
3 *
4 * Bus error event handling code for DECstation/DECsystem 3100
5 * and 2100 (KN01) systems equipped with parity error detection
6 * logic.
7 *
8 * Copyright (c) 2005 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/spinlock.h>
20#include <linux/types.h>
21
22#include <asm/inst.h>
23#include <asm/mipsregs.h>
24#include <asm/page.h>
25#include <asm/system.h>
26#include <asm/traps.h>
27#include <asm/uaccess.h>
28
29#include <asm/dec/kn01.h>
30
31
32/* CP0 hazard avoidance. */
33#define BARRIER \
34 __asm__ __volatile__( \
35 ".set push\n\t" \
36 ".set noreorder\n\t" \
37 "nop\n\t" \
38 ".set pop\n\t")
39
40/*
41 * Bits 7:0 of the Control Register are write-only -- the
42 * corresponding bits of the Status Register have a different
43 * meaning. Hence we use a cache. It speeds up things a bit
44 * as well.
45 *
46 * There is no default value -- it has to be initialized.
47 */
48u16 cached_kn01_csr;
49DEFINE_SPINLOCK(kn01_lock);
50
51
52static inline void dec_kn01_be_ack(void)
53{
54 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
55 unsigned long flags;
56
57 spin_lock_irqsave(&kn01_lock, flags);
58
59 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
60 iob();
61
62 spin_unlock_irqrestore(&kn01_lock, flags);
63}
64
65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66{
67 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
68 KN01_ERRADDR);
69
70 static const char excstr[] = "exception";
71 static const char intstr[] = "interrupt";
72 static const char cpustr[] = "CPU";
73 static const char mreadstr[] = "memory read";
74 static const char readstr[] = "read";
75 static const char writestr[] = "write";
76 static const char timestr[] = "timeout";
77 static const char paritystr[] = "parity error";
78
79 int data = regs->cp0_cause & 4;
80 unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
81 ((regs->cp0_cause & CAUSEF_BD) != 0);
82 union mips_instruction insn;
83 unsigned long entrylo, offset;
84 long asid, entryhi, vaddr;
85
86 const char *kind, *agent, *cycle, *event;
87 unsigned long address;
88
89 u32 erraddr = *kn01_erraddr;
90 int action = MIPS_BE_FATAL;
91
92 /* Ack ASAP, so that any subsequent errors get caught. */
93 dec_kn01_be_ack();
94
95 kind = invoker ? intstr : excstr;
96
97 agent = cpustr;
98
99 if (invoker)
100 address = erraddr;
101 else {
102 /* Bloody hardware doesn't record the address for reads... */
103 if (data) {
104 /* This never faults. */
105 __get_user(insn.word, pc);
106 vaddr = regs->regs[insn.i_format.rs] +
107 insn.i_format.simmediate;
108 } else
109 vaddr = (long)pc;
110 if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
111 address = CPHYSADDR(vaddr);
112 else {
113 /* Peek at what physical address the CPU used. */
114 asid = read_c0_entryhi();
115 entryhi = asid & (PAGE_SIZE - 1);
116 entryhi |= vaddr & ~(PAGE_SIZE - 1);
117 write_c0_entryhi(entryhi);
118 BARRIER;
119 tlb_probe();
120 /* No need to check for presence. */
121 tlb_read();
122 entrylo = read_c0_entrylo0();
123 write_c0_entryhi(asid);
124 offset = vaddr & (PAGE_SIZE - 1);
125 address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
126 }
127 }
128
129 /* Treat low 256MB as memory, high -- as I/O. */
130 if (address < 0x10000000) {
131 cycle = mreadstr;
132 event = paritystr;
133 } else {
134 cycle = invoker ? writestr : readstr;
135 event = timestr;
136 }
137
138 if (is_fixup)
139 action = MIPS_BE_FIXUP;
140
141 if (action != MIPS_BE_FIXUP)
142 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
143 kind, agent, cycle, event, address);
144
145 return action;
146}
147
148int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
149{
150 return dec_kn01_be_backend(regs, is_fixup, 0);
151}
152
153irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
154 struct pt_regs *regs)
155{
156 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
157 int action;
158
159 if (!(*csr & KN01_CSR_MEMERR))
160 return IRQ_NONE; /* Must have been video. */
161
162 action = dec_kn01_be_backend(regs, 0, 1);
163
164 if (action == MIPS_BE_DISCARD)
165 return IRQ_HANDLED;
166
167 /*
168 * FIXME: Find the affected processes and kill them, otherwise
169 * we must die.
170 *
171 * The interrupt is asynchronously delivered thus EPC and RA
172 * may be irrelevant, but are printed for a reference.
173 */
174 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
175 regs->cp0_epc, regs->regs[31]);
176 die("Unrecoverable bus error", regs);
177}
178
179
180void __init dec_kn01_be_init(void)
181{
182 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
183 unsigned long flags;
184
185 spin_lock_irqsave(&kn01_lock, flags);
186
187 /* Preset write-only bits of the Control Register cache. */
188 cached_kn01_csr = *csr;
189 cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
190 cached_kn01_csr |= KN01_CSR_LEDS;
191
192 /* Enable parity error detection. */
193 cached_kn01_csr &= ~KN01_CSR_PARDIS;
194 *csr = cached_kn01_csr;
195 iob();
196
197 spin_unlock_irqrestore(&kn01_lock, flags);
198
199 /* Clear any leftover errors from the firmware. */
200 dec_kn01_be_ack();
201}
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index e0bfcd1521e2..898bed502a34 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -4,7 +4,7 @@
4 * DECstation 5000/200 (KN02) Control and Status Register 4 * DECstation 5000/200 (KN02) Control and Status Register
5 * interrupts. 5 * interrupts.
6 * 6 *
7 * Copyright (c) 2002, 2003 Maciej W. Rozycki 7 * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
@@ -37,7 +37,8 @@ static int kn02_irq_base;
37 37
38static inline void unmask_kn02_irq(unsigned int irq) 38static inline void unmask_kn02_irq(unsigned int irq)
39{ 39{
40 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 40 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
41 KN02_CSR);
41 42
42 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); 43 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
43 *csr = cached_kn02_csr; 44 *csr = cached_kn02_csr;
@@ -45,7 +46,8 @@ static inline void unmask_kn02_irq(unsigned int irq)
45 46
46static inline void mask_kn02_irq(unsigned int irq) 47static inline void mask_kn02_irq(unsigned int irq)
47{ 48{
48 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 49 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
50 KN02_CSR);
49 51
50 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); 52 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
51 *csr = cached_kn02_csr; 53 *csr = cached_kn02_csr;
@@ -105,13 +107,14 @@ static struct hw_interrupt_type kn02_irq_type = {
105 107
106void __init init_kn02_irqs(int base) 108void __init init_kn02_irqs(int base)
107{ 109{
108 volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; 110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR);
109 unsigned long flags; 112 unsigned long flags;
110 int i; 113 int i;
111 114
112 /* Mask interrupts. */ 115 /* Mask interrupts. */
113 spin_lock_irqsave(&kn02_lock, flags); 116 spin_lock_irqsave(&kn02_lock, flags);
114 cached_kn02_csr &= ~KN03_CSR_IOINTEN; 117 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
115 *csr = cached_kn02_csr; 118 *csr = cached_kn02_csr;
116 iob(); 119 iob();
117 spin_unlock_irqrestore(&kn02_lock, flags); 120 spin_unlock_irqrestore(&kn02_lock, flags);
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
new file mode 100644
index 000000000000..6cd3f94f79fe
--- /dev/null
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -0,0 +1,139 @@
1/*
2 * linux/arch/mips/dec/kn02xa-berr.c
3 *
4 * Bus error event handling code for 5000-series systems equipped
5 * with parity error detection logic, i.e. DECstation/DECsystem
6 * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
7 * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
8 * (KN04-CA) systems.
9 *
10 * Copyright (c) 2005 Maciej W. Rozycki
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/kernel.h>
21#include <linux/types.h>
22
23#include <asm/addrspace.h>
24#include <asm/system.h>
25#include <asm/traps.h>
26
27#include <asm/dec/kn02ca.h>
28#include <asm/dec/kn02xa.h>
29#include <asm/dec/kn05.h>
30
31static inline void dec_kn02xa_be_ack(void)
32{
33 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
34 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
35
36 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
37 *mem_intr = 0; /* Any write clears the bus IRQ. */
38 iob();
39}
40
41static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
42 int invoker)
43{
44 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
45 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
46
47 static const char excstr[] = "exception";
48 static const char intstr[] = "interrupt";
49 static const char cpustr[] = "CPU";
50 static const char mreadstr[] = "memory read";
51 static const char readstr[] = "read";
52 static const char writestr[] = "write";
53 static const char timestr[] = "timeout";
54 static const char paritystr[] = "parity error";
55 static const char lanestat[][4] = { " OK", "BAD" };
56
57 const char *kind, *agent, *cycle, *event;
58 unsigned long address;
59
60 u32 mer = *kn02xa_mer;
61 u32 ear = *kn02xa_ear;
62 int action = MIPS_BE_FATAL;
63
64 /* Ack ASAP, so that any subsequent errors get caught. */
65 dec_kn02xa_be_ack();
66
67 kind = invoker ? intstr : excstr;
68
69 /* No DMA errors? */
70 agent = cpustr;
71
72 address = ear & KN02XA_EAR_ADDRESS;
73
74 /* Low 256MB is decoded as memory, high -- as TC. */
75 if (address < 0x10000000) {
76 cycle = mreadstr;
77 event = paritystr;
78 } else {
79 cycle = invoker ? writestr : readstr;
80 event = timestr;
81 }
82
83 if (is_fixup)
84 action = MIPS_BE_FIXUP;
85
86 if (action != MIPS_BE_FIXUP)
87 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
88 kind, agent, cycle, event, address);
89
90 if (action != MIPS_BE_FIXUP && address < 0x10000000)
91 printk(KERN_ALERT " Byte lane status %#3x -- "
92 "#3: %s, #2: %s, #1: %s, #0: %s\n",
93 (mer & KN02XA_MER_BYTERR) >> 8,
94 lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
95 lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
96 lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
97 lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
98
99 return action;
100}
101
102int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
103{
104 return dec_kn02xa_be_backend(regs, is_fixup, 0);
105}
106
107irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
108 struct pt_regs *regs)
109{
110 int action = dec_kn02xa_be_backend(regs, 0, 1);
111
112 if (action == MIPS_BE_DISCARD)
113 return IRQ_HANDLED;
114
115 /*
116 * FIXME: Find the affected processes and kill them, otherwise
117 * we must die.
118 *
119 * The interrupt is asynchronously delivered thus EPC and RA
120 * may be irrelevant, but are printed for a reference.
121 */
122 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
123 regs->cp0_epc, regs->regs[31]);
124 die("Unrecoverable bus error", regs);
125}
126
127
128void __init dec_kn02xa_be_init(void)
129{
130 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
131
132 /* For KN04 we need to make sure EE (?) is enabled in the MB. */
133 if (current_cpu_data.cputype == CPU_R4000SC)
134 *mbcs |= KN4K_MB_CSR_EE;
135 fast_iob();
136
137 /* Clear any leftover errors from the firmware. */
138 dec_kn02xa_be_ack();
139}
diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c
index 9380588cb15c..81d5e878ddce 100644
--- a/arch/mips/dec/prom/identify.c
+++ b/arch/mips/dec/prom/identify.c
@@ -2,7 +2,7 @@
2 * identify.c: machine identification code. 2 * identify.c: machine identification code.
3 * 3 *
4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine 4 * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine
5 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki 5 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
6 */ 6 */
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/kernel.h> 8#include <linux/kernel.h>
@@ -12,6 +12,7 @@
12#include <linux/types.h> 12#include <linux/types.h>
13 13
14#include <asm/bootinfo.h> 14#include <asm/bootinfo.h>
15
15#include <asm/dec/ioasic.h> 16#include <asm/dec/ioasic.h>
16#include <asm/dec/ioasic_addrs.h> 17#include <asm/dec/ioasic_addrs.h>
17#include <asm/dec/kn01.h> 18#include <asm/dec/kn01.h>
@@ -21,6 +22,7 @@
21#include <asm/dec/kn03.h> 22#include <asm/dec/kn03.h>
22#include <asm/dec/kn230.h> 23#include <asm/dec/kn230.h>
23#include <asm/dec/prom.h> 24#include <asm/dec/prom.h>
25#include <asm/dec/system.h>
24 26
25#include "dectypes.h" 27#include "dectypes.h"
26 28
@@ -68,34 +70,44 @@ EXPORT_SYMBOL(dec_rtc_base);
68 70
69static inline void prom_init_kn01(void) 71static inline void prom_init_kn01(void)
70{ 72{
71 dec_rtc_base = (void *)KN01_RTC_BASE; 73 dec_kn_slot_base = KN01_SLOT_BASE;
72 dec_kn_slot_size = KN01_SLOT_SIZE; 74 dec_kn_slot_size = KN01_SLOT_SIZE;
75
76 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
73} 77}
74 78
75static inline void prom_init_kn230(void) 79static inline void prom_init_kn230(void)
76{ 80{
77 dec_rtc_base = (void *)KN01_RTC_BASE; 81 dec_kn_slot_base = KN01_SLOT_BASE;
78 dec_kn_slot_size = KN01_SLOT_SIZE; 82 dec_kn_slot_size = KN01_SLOT_SIZE;
83
84 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
79} 85}
80 86
81static inline void prom_init_kn02(void) 87static inline void prom_init_kn02(void)
82{ 88{
83 dec_rtc_base = (void *)KN02_RTC_BASE; 89 dec_kn_slot_base = KN02_SLOT_BASE;
84 dec_kn_slot_size = KN02_SLOT_SIZE; 90 dec_kn_slot_size = KN02_SLOT_SIZE;
91
92 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
85} 93}
86 94
87static inline void prom_init_kn02xa(void) 95static inline void prom_init_kn02xa(void)
88{ 96{
89 ioasic_base = (void *)KN02XA_IOASIC_BASE; 97 dec_kn_slot_base = KN02XA_SLOT_BASE;
90 dec_rtc_base = (void *)KN02XA_RTC_BASE;
91 dec_kn_slot_size = IOASIC_SLOT_SIZE; 98 dec_kn_slot_size = IOASIC_SLOT_SIZE;
99
100 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
101 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
92} 102}
93 103
94static inline void prom_init_kn03(void) 104static inline void prom_init_kn03(void)
95{ 105{
96 ioasic_base = (void *)KN03_IOASIC_BASE; 106 dec_kn_slot_base = KN03_SLOT_BASE;
97 dec_rtc_base = (void *)KN03_RTC_BASE;
98 dec_kn_slot_size = IOASIC_SLOT_SIZE; 107 dec_kn_slot_size = IOASIC_SLOT_SIZE;
108
109 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
110 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
99} 111}
100 112
101 113
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index 60f74256e689..32a7cc7e4c65 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -6,6 +6,8 @@
6 */ 6 */
7#include <linux/config.h> 7#include <linux/config.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/linkage.h>
9#include <linux/smp.h> 11#include <linux/smp.h>
10#include <linux/string.h> 12#include <linux/string.h>
11#include <linux/types.h> 13#include <linux/types.h>
@@ -85,17 +87,13 @@ void __init which_prom(s32 magic, s32 *prom_vec)
85 87
86void __init prom_init(void) 88void __init prom_init(void)
87{ 89{
88 extern void dec_machine_halt(void); 90 extern void ATTRIB_NORET dec_machine_halt(void);
89 static char cpu_msg[] __initdata = 91 static char cpu_msg[] __initdata =
90 "Sorry, this kernel is compiled for a wrong CPU type!\n"; 92 "Sorry, this kernel is compiled for a wrong CPU type!\n";
91 static char r3k_msg[] __initdata =
92 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
93 static char r4k_msg[] __initdata =
94 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
95 s32 argc = fw_arg0; 93 s32 argc = fw_arg0;
96 s32 argv = fw_arg1; 94 s32 *argv = (void *)fw_arg1;
97 u32 magic = fw_arg2; 95 u32 magic = fw_arg2;
98 s32 prom_vec = fw_arg3; 96 s32 *prom_vec = (void *)fw_arg3;
99 97
100 /* 98 /*
101 * Determine which PROM we have 99 * Determine which PROM we have
@@ -113,6 +111,8 @@ void __init prom_init(void)
113#if defined(CONFIG_CPU_R3000) 111#if defined(CONFIG_CPU_R3000)
114 if ((current_cpu_data.cputype == CPU_R4000SC) || 112 if ((current_cpu_data.cputype == CPU_R4000SC) ||
115 (current_cpu_data.cputype == CPU_R4400SC)) { 113 (current_cpu_data.cputype == CPU_R4400SC)) {
114 static char r4k_msg[] __initdata =
115 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
116 printk(cpu_msg); 116 printk(cpu_msg);
117 printk(r4k_msg); 117 printk(r4k_msg);
118 dec_machine_halt(); 118 dec_machine_halt();
@@ -122,6 +122,8 @@ void __init prom_init(void)
122#if defined(CONFIG_CPU_R4X00) 122#if defined(CONFIG_CPU_R4X00)
123 if ((current_cpu_data.cputype == CPU_R3000) || 123 if ((current_cpu_data.cputype == CPU_R3000) ||
124 (current_cpu_data.cputype == CPU_R3000A)) { 124 (current_cpu_data.cputype == CPU_R3000A)) {
125 static char r3k_msg[] __initdata =
126 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
125 printk(cpu_msg); 127 printk(cpu_msg);
126 printk(r3k_msg); 128 printk(r3k_msg);
127 dec_machine_halt(); 129 dec_machine_halt();
diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index e4f6f26425ea..83d4556c3cb5 100644
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -35,22 +35,22 @@ static inline void pmax_setup_memory_region(void)
35 extern char genexcept_early; 35 extern char genexcept_early;
36 36
37 /* Install exception handler */ 37 /* Install exception handler */
38 memcpy(&old_handler, (void *)(KSEG0 + 0x80), 0x80); 38 memcpy(&old_handler, (void *)(CKSEG0 + 0x80), 0x80);
39 memcpy((void *)(KSEG0 + 0x80), &genexcept_early, 0x80); 39 memcpy((void *)(CKSEG0 + 0x80), &genexcept_early, 0x80);
40 40
41 /* read unmapped and uncached (KSEG1) 41 /* read unmapped and uncached (KSEG1)
42 * DECstations have at least 4MB RAM 42 * DECstations have at least 4MB RAM
43 * Assume less than 480MB of RAM, as this is max for 5000/2xx 43 * Assume less than 480MB of RAM, as this is max for 5000/2xx
44 * FIXME this should be replaced by the first free page! 44 * FIXME this should be replaced by the first free page!
45 */ 45 */
46 for (memory_page = (unsigned char *) KSEG1 + CHUNK_SIZE; 46 for (memory_page = (unsigned char *)CKSEG1 + CHUNK_SIZE;
47 (mem_err== 0) && (memory_page < ((unsigned char *) KSEG1+0x1E000000)); 47 mem_err == 0 && memory_page < (unsigned char *)CKSEG1 + 0x1e00000;
48 memory_page += CHUNK_SIZE) { 48 memory_page += CHUNK_SIZE) {
49 dummy = *memory_page; 49 dummy = *memory_page;
50 } 50 }
51 memcpy((void *)(KSEG0 + 0x80), &old_handler, 0x80); 51 memcpy((void *)(CKSEG0 + 0x80), &old_handler, 0x80);
52 52
53 add_memory_region(0, (unsigned long)memory_page - KSEG1 - CHUNK_SIZE, 53 add_memory_region(0, (unsigned long)memory_page - CKSEG1 - CHUNK_SIZE,
54 BOOT_MEM_RAM); 54 BOOT_MEM_RAM);
55} 55}
56 56
@@ -65,7 +65,7 @@ static inline void rex_setup_memory_region(void)
65 memmap *bm; 65 memmap *bm;
66 66
67 /* some free 64k */ 67 /* some free 64k */
68 bm = (memmap *)KSEG0ADDR(0x28000); 68 bm = (memmap *)CKSEG0ADDR(0x28000);
69 69
70 bitmap_size = rex_getbitmap(bm); 70 bitmap_size = rex_getbitmap(bm);
71 71
diff --git a/arch/mips/dec/reset.c b/arch/mips/dec/reset.c
index 7e4d34d0573d..f78c6da47921 100644
--- a/arch/mips/dec/reset.c
+++ b/arch/mips/dec/reset.c
@@ -14,7 +14,7 @@ typedef void ATTRIB_NORET (* noret_func_t)(void);
14 14
15static inline void ATTRIB_NORET back_to_prom(void) 15static inline void ATTRIB_NORET back_to_prom(void)
16{ 16{
17 noret_func_t func = (void *) KSEG1ADDR(0x1fc00000); 17 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000);
18 18
19 func(); 19 func();
20} 20}
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 6a69309baf40..9ef54fe1feaa 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -1,19 +1,20 @@
1/* 1/*
2 * Setup the interrupt stuff. 2 * System-specific setup, especially interrupts.
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1998 Harald Koerfgen 8 * Copyright (C) 1998 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
10 */ 10 */
11#include <linux/sched.h>
12#include <linux/interrupt.h>
13#include <linux/param.h>
14#include <linux/console.h> 11#include <linux/console.h>
15#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/ioport.h>
16#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/param.h>
17#include <linux/sched.h>
17#include <linux/spinlock.h> 18#include <linux/spinlock.h>
18#include <linux/types.h> 19#include <linux/types.h>
19 20
@@ -38,6 +39,7 @@
38#include <asm/dec/kn02ca.h> 39#include <asm/dec/kn02ca.h>
39#include <asm/dec/kn03.h> 40#include <asm/dec/kn03.h>
40#include <asm/dec/kn230.h> 41#include <asm/dec/kn230.h>
42#include <asm/dec/system.h>
41 43
42 44
43extern void dec_machine_restart(char *command); 45extern void dec_machine_restart(char *command);
@@ -47,10 +49,16 @@ extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
47 49
48extern asmlinkage void decstation_handle_int(void); 50extern asmlinkage void decstation_handle_int(void);
49 51
52unsigned long dec_kn_slot_base, dec_kn_slot_size;
53
54EXPORT_SYMBOL(dec_kn_slot_base);
55EXPORT_SYMBOL(dec_kn_slot_size);
56
50spinlock_t ioasic_ssr_lock; 57spinlock_t ioasic_ssr_lock;
51 58
52volatile u32 *ioasic_base; 59volatile u32 *ioasic_base;
53unsigned long dec_kn_slot_size; 60
61EXPORT_SYMBOL(ioasic_base);
54 62
55/* 63/*
56 * IRQ routing and priority tables. Priorites are set as follows: 64 * IRQ routing and priority tables. Priorites are set as follows:
@@ -77,6 +85,9 @@ unsigned long dec_kn_slot_size;
77int dec_interrupt[DEC_NR_INTS] = { 85int dec_interrupt[DEC_NR_INTS] = {
78 [0 ... DEC_NR_INTS - 1] = -1 86 [0 ... DEC_NR_INTS - 1] = -1
79}; 87};
88
89EXPORT_SYMBOL(dec_interrupt);
90
80int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 91int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
81 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 92 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
82}; 93};
@@ -108,11 +119,20 @@ static struct irqaction haltirq = {
108/* 119/*
109 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. 120 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
110 */ 121 */
111void __init dec_be_init(void) 122static void __init dec_be_init(void)
112{ 123{
113 switch (mips_machtype) { 124 switch (mips_machtype) {
114 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 125 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
126 board_be_handler = dec_kn01_be_handler;
127 busirq.handler = dec_kn01_be_interrupt;
115 busirq.flags |= SA_SHIRQ; 128 busirq.flags |= SA_SHIRQ;
129 dec_kn01_be_init();
130 break;
131 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
132 case MACH_DS5000_XX: /* DS5000/xx Maxine */
133 board_be_handler = dec_kn02xa_be_handler;
134 busirq.handler = dec_kn02xa_be_interrupt;
135 dec_kn02xa_be_init();
116 break; 136 break;
117 case MACH_DS5000_200: /* DS5000/200 3max */ 137 case MACH_DS5000_200: /* DS5000/200 3max */
118 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 138 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
@@ -128,7 +148,7 @@ void __init dec_be_init(void)
128extern void dec_time_init(void); 148extern void dec_time_init(void);
129extern void dec_timer_setup(struct irqaction *); 149extern void dec_timer_setup(struct irqaction *);
130 150
131static void __init decstation_setup(void) 151void __init plat_setup(void)
132{ 152{
133 board_be_init = dec_be_init; 153 board_be_init = dec_be_init;
134 board_time_init = dec_time_init; 154 board_time_init = dec_time_init;
@@ -139,9 +159,10 @@ static void __init decstation_setup(void)
139 _machine_restart = dec_machine_restart; 159 _machine_restart = dec_machine_restart;
140 _machine_halt = dec_machine_halt; 160 _machine_halt = dec_machine_halt;
141 _machine_power_off = dec_machine_power_off; 161 _machine_power_off = dec_machine_power_off;
142}
143 162
144early_initcall(decstation_setup); 163 ioport_resource.start = ~0UL;
164 ioport_resource.end = 0UL;
165}
145 166
146/* 167/*
147 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) 168 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
@@ -206,7 +227,7 @@ static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
206 { .p = cpu_all_int } }, 227 { .p = cpu_all_int } },
207}; 228};
208 229
209void __init dec_init_kn01(void) 230static void __init dec_init_kn01(void)
210{ 231{
211 /* IRQ routing. */ 232 /* IRQ routing. */
212 memcpy(&dec_interrupt, &kn01_interrupt, 233 memcpy(&dec_interrupt, &kn01_interrupt,
@@ -281,7 +302,7 @@ static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
281 { .p = cpu_all_int } }, 302 { .p = cpu_all_int } },
282}; 303};
283 304
284void __init dec_init_kn230(void) 305static void __init dec_init_kn230(void)
285{ 306{
286 /* IRQ routing. */ 307 /* IRQ routing. */
287 memcpy(&dec_interrupt, &kn230_interrupt, 308 memcpy(&dec_interrupt, &kn230_interrupt,
@@ -371,7 +392,7 @@ static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
371 { .p = kn02_all_int } }, 392 { .p = kn02_all_int } },
372}; 393};
373 394
374void __init dec_init_kn02(void) 395static void __init dec_init_kn02(void)
375{ 396{
376 /* IRQ routing. */ 397 /* IRQ routing. */
377 memcpy(&dec_interrupt, &kn02_interrupt, 398 memcpy(&dec_interrupt, &kn02_interrupt,
@@ -472,7 +493,7 @@ static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
472 { .p = asic_all_int } }, 493 { .p = asic_all_int } },
473}; 494};
474 495
475void __init dec_init_kn02ba(void) 496static void __init dec_init_kn02ba(void)
476{ 497{
477 /* IRQ routing. */ 498 /* IRQ routing. */
478 memcpy(&dec_interrupt, &kn02ba_interrupt, 499 memcpy(&dec_interrupt, &kn02ba_interrupt,
@@ -569,7 +590,7 @@ static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
569 { .p = asic_all_int } }, 590 { .p = asic_all_int } },
570}; 591};
571 592
572void __init dec_init_kn02ca(void) 593static void __init dec_init_kn02ca(void)
573{ 594{
574 /* IRQ routing. */ 595 /* IRQ routing. */
575 memcpy(&dec_interrupt, &kn02ca_interrupt, 596 memcpy(&dec_interrupt, &kn02ca_interrupt,
@@ -670,7 +691,7 @@ static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
670 { .p = asic_all_int } }, 691 { .p = asic_all_int } },
671}; 692};
672 693
673void __init dec_init_kn03(void) 694static void __init dec_init_kn03(void)
674{ 695{
675 /* IRQ routing. */ 696 /* IRQ routing. */
676 memcpy(&dec_interrupt, &kn03_interrupt, 697 memcpy(&dec_interrupt, &kn03_interrupt,
@@ -744,7 +765,3 @@ void __init arch_init_irq(void)
744 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 765 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
745 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 766 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
746} 767}
747
748EXPORT_SYMBOL(ioasic_base);
749EXPORT_SYMBOL(dec_kn_slot_size);
750EXPORT_SYMBOL(dec_interrupt);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 01:34:20 -0500