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-rw-r--r--arch/mips/ddb5xxx/ddb5074/Makefile2
-rw-r--r--arch/mips/ddb5xxx/ddb5074/int-handler.S120
-rw-r--r--arch/mips/ddb5xxx/ddb5074/irq.c26
3 files changed, 19 insertions, 129 deletions
diff --git a/arch/mips/ddb5xxx/ddb5074/Makefile b/arch/mips/ddb5xxx/ddb5074/Makefile
index 488206b8d94e..304c02107b46 100644
--- a/arch/mips/ddb5xxx/ddb5074/Makefile
+++ b/arch/mips/ddb5xxx/ddb5074/Makefile
@@ -3,6 +3,6 @@
3# under Linux. 3# under Linux.
4# 4#
5 5
6obj-y += setup.o irq.o int-handler.o nile4_pic.o 6obj-y += setup.o irq.o nile4_pic.o
7 7
8EXTRA_AFLAGS := $(CFLAGS) 8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/ddb5xxx/ddb5074/int-handler.S b/arch/mips/ddb5xxx/ddb5074/int-handler.S
deleted file mode 100644
index a78644150b37..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/int-handler.S
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler
3 *
4 * Based on arch/mips/sgi/kernel/indyIRQ.S
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 *
8 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
9 * Sony Software Development Center Europe (SDCE), Brussels
10 */
11#include <asm/asm.h>
12#include <asm/mipsregs.h>
13#include <asm/regdef.h>
14#include <asm/stackframe.h>
15
16/* A lot of complication here is taken away because:
17 *
18 * 1) We handle one interrupt and return, sitting in a loop and moving across
19 * all the pending IRQ bits in the cause register is _NOT_ the answer, the
20 * common case is one pending IRQ so optimize in that direction.
21 *
22 * 2) We need not check against bits in the status register IRQ mask, that
23 * would make this routine slow as hell.
24 *
25 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
26 * between like BSD spl() brain-damage.
27 *
28 * Furthermore, the IRQs on the INDY look basically (barring software IRQs
29 * which we don't use at all) like:
30 *
31 * MIPS IRQ Source
32 * -------- ------
33 * 0 Software (ignored)
34 * 1 Software (ignored)
35 * 2 Local IRQ level zero
36 * 3 Local IRQ level one
37 * 4 8254 Timer zero
38 * 5 8254 Timer one
39 * 6 Bus Error
40 * 7 R4k timer (what we use)
41 *
42 * We handle the IRQ according to _our_ priority which is:
43 *
44 * Highest ---- R4k Timer
45 * Local IRQ zero
46 * Local IRQ one
47 * Bus Error
48 * 8254 Timer zero
49 * Lowest ---- 8254 Timer one
50 *
51 * then we just return, if multiple IRQs are pending then we will just take
52 * another exception, big deal.
53 */
54
55 .text
56 .set noreorder
57 .set noat
58 .align 5
59 NESTED(ddbIRQ, PT_SIZE, sp)
60 SAVE_ALL
61 CLI
62 .set at
63 mfc0 s0, CP0_CAUSE # get irq mask
64
65#if 1
66 mfc0 t2,CP0_STATUS # get enabled interrupts
67 and s0,t2 # isolate allowed ones
68#endif
69 /* First we check for r4k counter/timer IRQ. */
70 andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero
71 beq a0, zero, 1f
72 andi a0, s0, CAUSEF_IP3 # delay slot, check local level one
73
74 /* Wheee, local level zero interrupt. */
75 jal ddb_local0_irqdispatch
76 move a0, sp # delay slot
77
78 j ret_from_irq
79 nop # delay slot
80
811:
82 beq a0, zero, 1f
83 andi a0, s0, CAUSEF_IP6 # delay slot, check bus error
84
85 /* Wheee, local level one interrupt. */
86 move a0, sp
87 jal ddb_local1_irqdispatch
88 nop
89
90 j ret_from_irq
91 nop
92
931:
94 beq a0, zero, 1f
95 nop
96
97 /* Wheee, an asynchronous bus error... */
98 move a0, sp
99 jal ddb_buserror_irq
100 nop
101
102 j ret_from_irq
103 nop
104
1051:
106 /* Here by mistake? This is possible, what can happen
107 * is that by the time we take the exception the IRQ
108 * pin goes low, so just leave if this is the case.
109 */
110 andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
111 beq a0, zero, 1f
112
113 /* Must be one of the 8254 timers... */
114 move a0, sp
115 jal ddb_8254timer_irq
116 nop
1171:
118 j ret_from_irq
119 nop
120 END(ddbIRQ)
diff --git a/arch/mips/ddb5xxx/ddb5074/irq.c b/arch/mips/ddb5xxx/ddb5074/irq.c
index 45088a1be414..60c087b7738c 100644
--- a/arch/mips/ddb5xxx/ddb5074/irq.c
+++ b/arch/mips/ddb5xxx/ddb5074/irq.c
@@ -21,8 +21,6 @@
21#include <asm/ddb5xxx/ddb5074.h> 21#include <asm/ddb5xxx/ddb5074.h>
22 22
23 23
24extern asmlinkage void ddbIRQ(void);
25
26static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; 24static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
27 25
28#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ 26#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
@@ -90,7 +88,7 @@ static void m1543_irq_setup(void)
90 88
91} 89}
92 90
93void ddb_local0_irqdispatch(struct pt_regs *regs) 91static void ddb_local0_irqdispatch(struct pt_regs *regs)
94{ 92{
95 u32 mask; 93 u32 mask;
96 int nile4_irq; 94 int nile4_irq;
@@ -118,29 +116,41 @@ void ddb_local0_irqdispatch(struct pt_regs *regs)
118 } 116 }
119} 117}
120 118
121void ddb_local1_irqdispatch(void) 119static void ddb_local1_irqdispatch(void)
122{ 120{
123 printk("ddb_local1_irqdispatch called\n"); 121 printk("ddb_local1_irqdispatch called\n");
124} 122}
125 123
126void ddb_buserror_irq(void) 124static void ddb_buserror_irq(void)
127{ 125{
128 printk("ddb_buserror_irq called\n"); 126 printk("ddb_buserror_irq called\n");
129} 127}
130 128
131void ddb_8254timer_irq(void) 129static void ddb_8254timer_irq(void)
132{ 130{
133 printk("ddb_8254timer_irq called\n"); 131 printk("ddb_8254timer_irq called\n");
134} 132}
135 133
134asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
135{
136 unsigned int pending = read_c0_cause() & read_c0_status();
137
138 if (pending & CAUSEF_IP2)
139 ddb_local0_irqdispatch(regs);
140 else if (pending & CAUSEF_IP3)
141 ddb_local1_irqdispatch();
142 else if (pending & CAUSEF_IP6)
143 ddb_buserror_irq();
144 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
145 ddb_8254timer_irq();
146}
147
136void __init arch_init_irq(void) 148void __init arch_init_irq(void)
137{ 149{
138 /* setup cascade interrupts */ 150 /* setup cascade interrupts */
139 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade); 151 setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
140 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade); 152 setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
141 153
142 set_except_vector(0, ddbIRQ);
143
144 nile4_irq_setup(NILE4_IRQ_BASE); 154 nile4_irq_setup(NILE4_IRQ_BASE);
145 m1543_irq_setup(); 155 m1543_irq_setup();
146 init_i8259_irqs(); 156 init_i8259_irqs();
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 16:21:55 -0400