1 files changed, 0 insertions, 120 deletions
diff --git a/arch/mips/ddb5xxx/ddb5074/int-handler.S b/arch/mips/ddb5xxx/ddb5074/int-handler.S
deleted file mode 100644
index a78644150b37..000000000000
--- a/arch/mips/ddb5xxx/ddb5074/int-handler.S
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- *  arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler
- *
- *  Based on arch/mips/sgi/kernel/indyIRQ.S
- *
- *  Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- */
-#include <asm/asm.h>
-#include <asm/mipsregs.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-/* A lot of complication here is taken away because:
- *
- * 1) We handle one interrupt and return, sitting in a loop and moving across
- *    all the pending IRQ bits in the cause register is _NOT_ the answer, the
- *    common case is one pending IRQ so optimize in that direction.
- *
- * 2) We need not check against bits in the status register IRQ mask, that
- *    would make this routine slow as hell.
- *
- * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
- *    between like BSD spl() brain-damage.
- *
- * Furthermore, the IRQs on the INDY look basically (barring software IRQs
- * which we don't use at all) like:
- *
- *      MIPS IRQ        Source
- *      --------        ------
- *             0        Software (ignored)
- *             1        Software (ignored)
- *             2        Local IRQ level zero
- *             3        Local IRQ level one
- *             4        8254 Timer zero
- *             5        8254 Timer one
- *             6        Bus Error
- *             7        R4k timer (what we use)
- *
- * We handle the IRQ according to _our_ priority which is:
- *
- * Highest ----     R4k Timer
- *                  Local IRQ zero
- *                  Local IRQ one
- *                  Bus Error
- *                  8254 Timer zero
- * Lowest  ----     8254 Timer one
- *
- * then we just return, if multiple IRQs are pending then we will just take
- * another exception, big deal.
- */
-        .text
-        .set    noreorder
-        .set    noat
-        .align  5
-        NESTED(ddbIRQ, PT_SIZE, sp)
-        SAVE_ALL
-        CLI
-        .set    at
-        mfc0    s0, CP0_CAUSE           # get irq mask
-#if 1
-        mfc0    t2,CP0_STATUS           # get enabled interrupts
-        and     s0,t2                   # isolate allowed ones
-#endif
-        /* First we check for r4k counter/timer IRQ. */
-        andi    a0, s0, CAUSEF_IP2      # delay slot, check local level zero
-        beq     a0, zero, 1f
-         andi   a0, s0, CAUSEF_IP3      # delay slot, check local level one
-        /* Wheee, local level zero interrupt. */
-        jal     ddb_local0_irqdispatch
-         move   a0, sp                  # delay slot
-        j       ret_from_irq
-         nop                            # delay slot
-1:
-        beq     a0, zero, 1f
-         andi   a0, s0, CAUSEF_IP6      # delay slot, check bus error
-        /* Wheee, local level one interrupt. */
-        move    a0, sp
-        jal     ddb_local1_irqdispatch
-         nop
-        j       ret_from_irq
-         nop
-1:
-        beq     a0, zero, 1f
-         nop
-        /* Wheee, an asynchronous bus error... */
-        move    a0, sp
-        jal     ddb_buserror_irq
-         nop
-        j       ret_from_irq
-         nop
-1:
-        /* Here by mistake?  This is possible, what can happen
-         * is that by the time we take the exception the IRQ
-         * pin goes low, so just leave if this is the case.
-         */
-        andi    a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
-        beq     a0, zero, 1f
-        /* Must be one of the 8254 timers... */
-        move    a0, sp
-        jal     ddb_8254timer_irq
-         nop
-1:
-        j       ret_from_irq
-         nop
-        END(ddbIRQ)

diff --git a/arch/mips/ddb5xxx/ddb5074/int-handler.S b/arch/mips/ddb5xxx/ddb5074/int-handler.S deleted file mode 100644 index a78644150b37..000000000000 --- a/arch/mips/ddb5xxx/ddb5074/int-handler.S +++ /dev/null
@@ -1,120 +0,0 @@
1	/*
2	* arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler
3	*
4	* Based on arch/mips/sgi/kernel/indyIRQ.S
5	*
6	* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7	*
8	* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
9	* Sony Software Development Center Europe (SDCE), Brussels
10	*/
11	#include <asm/asm.h>
12	#include <asm/mipsregs.h>
13	#include <asm/regdef.h>
14	#include <asm/stackframe.h>
15
16	/* A lot of complication here is taken away because:
17	*
18	* 1) We handle one interrupt and return, sitting in a loop and moving across
19	* all the pending IRQ bits in the cause register is _NOT_ the answer, the
20	* common case is one pending IRQ so optimize in that direction.
21	*
22	* 2) We need not check against bits in the status register IRQ mask, that
23	* would make this routine slow as hell.
24	*
25	* 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
26	* between like BSD spl() brain-damage.
27	*
28	* Furthermore, the IRQs on the INDY look basically (barring software IRQs
29	* which we don't use at all) like:
30	*
31	* MIPS IRQ Source
32	* -------- ------
33	* 0 Software (ignored)
34	* 1 Software (ignored)
35	* 2 Local IRQ level zero
36	* 3 Local IRQ level one
37	* 4 8254 Timer zero
38	* 5 8254 Timer one
39	* 6 Bus Error
40	* 7 R4k timer (what we use)
41	*
42	* We handle the IRQ according to _our_ priority which is:
43	*
44	* Highest ---- R4k Timer
45	* Local IRQ zero
46	* Local IRQ one
47	* Bus Error
48	* 8254 Timer zero
49	* Lowest ---- 8254 Timer one
50	*
51	* then we just return, if multiple IRQs are pending then we will just take
52	* another exception, big deal.
53	*/
54
55	.text
56	.set noreorder
57	.set noat
58	.align 5
59	NESTED(ddbIRQ, PT_SIZE, sp)
60	SAVE_ALL
61	CLI
62	.set at
63	mfc0 s0, CP0_CAUSE # get irq mask
64
65	#if 1
66	mfc0 t2,CP0_STATUS # get enabled interrupts
67	and s0,t2 # isolate allowed ones
68	#endif
69	/* First we check for r4k counter/timer IRQ. */
70	andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero
71	beq a0, zero, 1f
72	andi a0, s0, CAUSEF_IP3 # delay slot, check local level one
73
74	/* Wheee, local level zero interrupt. */
75	jal ddb_local0_irqdispatch
76	move a0, sp # delay slot
77
78	j ret_from_irq
79	nop # delay slot
80
81	1:
82	beq a0, zero, 1f
83	andi a0, s0, CAUSEF_IP6 # delay slot, check bus error
84
85	/* Wheee, local level one interrupt. */
86	move a0, sp
87	jal ddb_local1_irqdispatch
88	nop
89
90	j ret_from_irq
91	nop
92
93	1:
94	beq a0, zero, 1f
95	nop
96
97	/* Wheee, an asynchronous bus error... */
98	move a0, sp
99	jal ddb_buserror_irq
100	nop
101
102	j ret_from_irq
103	nop
104
105	1:
106	/* Here by mistake? This is possible, what can happen
107	* is that by the time we take the exception the IRQ
108	* pin goes low, so just leave if this is the case.
109	*/
110	andi a0, s0, (CAUSEF_IP4 \| CAUSEF_IP5)
111	beq a0, zero, 1f
112
113	/* Must be one of the 8254 timers... */
114	move a0, sp
115	jal ddb_8254timer_irq
116	nop
117	1:
118	j ret_from_irq
119	nop
120	END(ddbIRQ)