diff options
Diffstat (limited to 'arch/m68k/include')
308 files changed, 31193 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild new file mode 100644 index 000000000000..1a922fad76f7 --- /dev/null +++ b/arch/m68k/include/asm/Kbuild | |||
| @@ -0,0 +1,2 @@ | |||
| 1 | include include/asm-generic/Kbuild.asm | ||
| 2 | header-y += cachectl.h | ||
diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h new file mode 100644 index 000000000000..a337e56d09bf --- /dev/null +++ b/arch/m68k/include/asm/MC68328.h | |||
| @@ -0,0 +1,1266 @@ | |||
| 1 | |||
| 2 | /* include/asm-m68knommu/MC68328.h: '328 control registers | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> | ||
| 5 | * Bear & Hare Software, Inc. | ||
| 6 | * | ||
| 7 | * Based on include/asm-m68knommu/MC68332.h | ||
| 8 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _MC68328_H_ | ||
| 13 | #define _MC68328_H_ | ||
| 14 | |||
| 15 | #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) | ||
| 16 | #define WORD_REF(addr) (*((volatile unsigned short*)addr)) | ||
| 17 | #define LONG_REF(addr) (*((volatile unsigned long*)addr)) | ||
| 18 | |||
| 19 | #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) | ||
| 20 | #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) | ||
| 21 | |||
| 22 | /********** | ||
| 23 | * | ||
| 24 | * 0xFFFFF0xx -- System Control | ||
| 25 | * | ||
| 26 | **********/ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * System Control Register (SCR) | ||
| 30 | */ | ||
| 31 | #define SCR_ADDR 0xfffff000 | ||
| 32 | #define SCR BYTE_REF(SCR_ADDR) | ||
| 33 | |||
| 34 | #define SCR_WDTH8 0x01 /* 8-Bit Width Select */ | ||
| 35 | #define SCR_DMAP 0x04 /* Double Map */ | ||
| 36 | #define SCR_SO 0x08 /* Supervisor Only */ | ||
| 37 | #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ | ||
| 38 | #define SCR_PRV 0x20 /* Privilege Violation */ | ||
| 39 | #define SCR_WPV 0x40 /* Write Protect Violation */ | ||
| 40 | #define SCR_BETO 0x80 /* Bus-Error TimeOut */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Mask Revision Register | ||
| 44 | */ | ||
| 45 | #define MRR_ADDR 0xfffff004 | ||
| 46 | #define MRR LONG_REF(MRR_ADDR) | ||
| 47 | |||
| 48 | /********** | ||
| 49 | * | ||
| 50 | * 0xFFFFF1xx -- Chip-Select logic | ||
| 51 | * | ||
| 52 | **********/ | ||
| 53 | |||
| 54 | /********** | ||
| 55 | * | ||
| 56 | * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control | ||
| 57 | * | ||
| 58 | **********/ | ||
| 59 | |||
| 60 | /* | ||
| 61 | * Group Base Address Registers | ||
| 62 | */ | ||
| 63 | #define GRPBASEA_ADDR 0xfffff100 | ||
| 64 | #define GRPBASEB_ADDR 0xfffff102 | ||
| 65 | #define GRPBASEC_ADDR 0xfffff104 | ||
| 66 | #define GRPBASED_ADDR 0xfffff106 | ||
| 67 | |||
| 68 | #define GRPBASEA WORD_REF(GRPBASEA_ADDR) | ||
| 69 | #define GRPBASEB WORD_REF(GRPBASEB_ADDR) | ||
| 70 | #define GRPBASEC WORD_REF(GRPBASEC_ADDR) | ||
| 71 | #define GRPBASED WORD_REF(GRPBASED_ADDR) | ||
| 72 | |||
| 73 | #define GRPBASE_V 0x0001 /* Valid */ | ||
| 74 | #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */ | ||
| 75 | |||
| 76 | /* | ||
| 77 | * Group Base Address Mask Registers | ||
| 78 | */ | ||
| 79 | #define GRPMASKA_ADDR 0xfffff108 | ||
| 80 | #define GRPMASKB_ADDR 0xfffff10a | ||
| 81 | #define GRPMASKC_ADDR 0xfffff10c | ||
| 82 | #define GRPMASKD_ADDR 0xfffff10e | ||
| 83 | |||
| 84 | #define GRPMASKA WORD_REF(GRPMASKA_ADDR) | ||
| 85 | #define GRPMASKB WORD_REF(GRPMASKB_ADDR) | ||
| 86 | #define GRPMASKC WORD_REF(GRPMASKC_ADDR) | ||
| 87 | #define GRPMASKD WORD_REF(GRPMASKD_ADDR) | ||
| 88 | |||
| 89 | #define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */ | ||
| 90 | |||
| 91 | /* | ||
| 92 | * Chip-Select Option Registers (group A) | ||
| 93 | */ | ||
| 94 | #define CSA0_ADDR 0xfffff110 | ||
| 95 | #define CSA1_ADDR 0xfffff114 | ||
| 96 | #define CSA2_ADDR 0xfffff118 | ||
| 97 | #define CSA3_ADDR 0xfffff11c | ||
| 98 | |||
| 99 | #define CSA0 LONG_REF(CSA0_ADDR) | ||
| 100 | #define CSA1 LONG_REF(CSA1_ADDR) | ||
| 101 | #define CSA2 LONG_REF(CSA2_ADDR) | ||
| 102 | #define CSA3 LONG_REF(CSA3_ADDR) | ||
| 103 | |||
| 104 | #define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */ | ||
| 105 | #define CSA_WAIT_SHIFT 0 | ||
| 106 | #define CSA_RO 0x00000008 /* Read-Only */ | ||
| 107 | #define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ | ||
| 108 | #define CSA_AM_SHIFT 8 | ||
| 109 | #define CSA_BUSW 0x00010000 /* Bus Width Select */ | ||
| 110 | #define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ | ||
| 111 | #define CSA_AC_SHIFT 24 | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Chip-Select Option Registers (group B) | ||
| 115 | */ | ||
| 116 | #define CSB0_ADDR 0xfffff120 | ||
| 117 | #define CSB1_ADDR 0xfffff124 | ||
| 118 | #define CSB2_ADDR 0xfffff128 | ||
| 119 | #define CSB3_ADDR 0xfffff12c | ||
| 120 | |||
| 121 | #define CSB0 LONG_REF(CSB0_ADDR) | ||
| 122 | #define CSB1 LONG_REF(CSB1_ADDR) | ||
| 123 | #define CSB2 LONG_REF(CSB2_ADDR) | ||
| 124 | #define CSB3 LONG_REF(CSB3_ADDR) | ||
| 125 | |||
| 126 | #define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */ | ||
| 127 | #define CSB_WAIT_SHIFT 0 | ||
| 128 | #define CSB_RO 0x00000008 /* Read-Only */ | ||
| 129 | #define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ | ||
| 130 | #define CSB_AM_SHIFT 8 | ||
| 131 | #define CSB_BUSW 0x00010000 /* Bus Width Select */ | ||
| 132 | #define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ | ||
| 133 | #define CSB_AC_SHIFT 24 | ||
| 134 | |||
| 135 | /* | ||
| 136 | * Chip-Select Option Registers (group C) | ||
| 137 | */ | ||
| 138 | #define CSC0_ADDR 0xfffff130 | ||
| 139 | #define CSC1_ADDR 0xfffff134 | ||
| 140 | #define CSC2_ADDR 0xfffff138 | ||
| 141 | #define CSC3_ADDR 0xfffff13c | ||
| 142 | |||
| 143 | #define CSC0 LONG_REF(CSC0_ADDR) | ||
| 144 | #define CSC1 LONG_REF(CSC1_ADDR) | ||
| 145 | #define CSC2 LONG_REF(CSC2_ADDR) | ||
| 146 | #define CSC3 LONG_REF(CSC3_ADDR) | ||
| 147 | |||
| 148 | #define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */ | ||
| 149 | #define CSC_WAIT_SHIFT 0 | ||
| 150 | #define CSC_RO 0x00000008 /* Read-Only */ | ||
| 151 | #define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ | ||
| 152 | #define CSC_AM_SHIFT 4 | ||
| 153 | #define CSC_BUSW 0x00010000 /* Bus Width Select */ | ||
| 154 | #define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ | ||
| 155 | #define CSC_AC_SHIFT 20 | ||
| 156 | |||
| 157 | /* | ||
| 158 | * Chip-Select Option Registers (group D) | ||
| 159 | */ | ||
| 160 | #define CSD0_ADDR 0xfffff140 | ||
| 161 | #define CSD1_ADDR 0xfffff144 | ||
| 162 | #define CSD2_ADDR 0xfffff148 | ||
| 163 | #define CSD3_ADDR 0xfffff14c | ||
| 164 | |||
| 165 | #define CSD0 LONG_REF(CSD0_ADDR) | ||
| 166 | #define CSD1 LONG_REF(CSD1_ADDR) | ||
| 167 | #define CSD2 LONG_REF(CSD2_ADDR) | ||
| 168 | #define CSD3 LONG_REF(CSD3_ADDR) | ||
| 169 | |||
| 170 | #define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */ | ||
| 171 | #define CSD_WAIT_SHIFT 0 | ||
| 172 | #define CSD_RO 0x00000008 /* Read-Only */ | ||
| 173 | #define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ | ||
| 174 | #define CSD_AM_SHIFT 4 | ||
| 175 | #define CSD_BUSW 0x00010000 /* Bus Width Select */ | ||
| 176 | #define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ | ||
| 177 | #define CSD_AC_SHIFT 20 | ||
| 178 | |||
| 179 | /********** | ||
| 180 | * | ||
| 181 | * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control | ||
| 182 | * | ||
| 183 | **********/ | ||
| 184 | |||
| 185 | /* | ||
| 186 | * PLL Control Register | ||
| 187 | */ | ||
| 188 | #define PLLCR_ADDR 0xfffff200 | ||
| 189 | #define PLLCR WORD_REF(PLLCR_ADDR) | ||
| 190 | |||
| 191 | #define PLLCR_DISPLL 0x0008 /* Disable PLL */ | ||
| 192 | #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ | ||
| 193 | #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ | ||
| 194 | #define PLLCR_SYSCLK_SEL_SHIFT 8 | ||
| 195 | #define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ | ||
| 196 | #define PLLCR_PIXCLK_SEL_SHIFT 11 | ||
| 197 | |||
| 198 | /* 'EZ328-compatible definitions */ | ||
| 199 | #define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK | ||
| 200 | #define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT | ||
| 201 | |||
| 202 | /* | ||
| 203 | * PLL Frequency Select Register | ||
| 204 | */ | ||
| 205 | #define PLLFSR_ADDR 0xfffff202 | ||
| 206 | #define PLLFSR WORD_REF(PLLFSR_ADDR) | ||
| 207 | |||
| 208 | #define PLLFSR_PC_MASK 0x00ff /* P Count */ | ||
| 209 | #define PLLFSR_PC_SHIFT 0 | ||
| 210 | #define PLLFSR_QC_MASK 0x0f00 /* Q Count */ | ||
| 211 | #define PLLFSR_QC_SHIFT 8 | ||
| 212 | #define PLLFSR_PROT 0x4000 /* Protect P & Q */ | ||
| 213 | #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ | ||
| 214 | |||
| 215 | /* | ||
| 216 | * Power Control Register | ||
| 217 | */ | ||
| 218 | #define PCTRL_ADDR 0xfffff207 | ||
| 219 | #define PCTRL BYTE_REF(PCTRL_ADDR) | ||
| 220 | |||
| 221 | #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ | ||
| 222 | #define PCTRL_WIDTH_SHIFT 0 | ||
| 223 | #define PCTRL_STOP 0x40 /* Enter power-save mode immediately */ | ||
| 224 | #define PCTRL_PCEN 0x80 /* Power Control Enable */ | ||
| 225 | |||
| 226 | /********** | ||
| 227 | * | ||
| 228 | * 0xFFFFF3xx -- Interrupt Controller | ||
| 229 | * | ||
| 230 | **********/ | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Interrupt Vector Register | ||
| 234 | */ | ||
| 235 | #define IVR_ADDR 0xfffff300 | ||
| 236 | #define IVR BYTE_REF(IVR_ADDR) | ||
| 237 | |||
| 238 | #define IVR_VECTOR_MASK 0xF8 | ||
| 239 | |||
| 240 | /* | ||
| 241 | * Interrupt control Register | ||
| 242 | */ | ||
| 243 | #define ICR_ADRR 0xfffff302 | ||
| 244 | #define ICR WORD_REF(ICR_ADDR) | ||
| 245 | |||
| 246 | #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ | ||
| 247 | #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ | ||
| 248 | #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ | ||
| 249 | #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ | ||
| 250 | #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ | ||
| 251 | #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ | ||
| 252 | #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ | ||
| 253 | #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ | ||
| 254 | |||
| 255 | /* | ||
| 256 | * Interrupt Mask Register | ||
| 257 | */ | ||
| 258 | #define IMR_ADDR 0xfffff304 | ||
| 259 | #define IMR LONG_REF(IMR_ADDR) | ||
| 260 | |||
| 261 | /* | ||
| 262 | * Define the names for bit positions first. This is useful for | ||
| 263 | * request_irq | ||
| 264 | */ | ||
| 265 | #define SPIM_IRQ_NUM 0 /* SPI Master interrupt */ | ||
| 266 | #define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */ | ||
| 267 | #define UART_IRQ_NUM 2 /* UART interrupt */ | ||
| 268 | #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ | ||
| 269 | #define RTC_IRQ_NUM 4 /* RTC interrupt */ | ||
| 270 | #define KB_IRQ_NUM 6 /* Keyboard Interrupt */ | ||
| 271 | #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ | ||
| 272 | #define INT0_IRQ_NUM 8 /* External INT0 */ | ||
| 273 | #define INT1_IRQ_NUM 9 /* External INT1 */ | ||
| 274 | #define INT2_IRQ_NUM 10 /* External INT2 */ | ||
| 275 | #define INT3_IRQ_NUM 11 /* External INT3 */ | ||
| 276 | #define INT4_IRQ_NUM 12 /* External INT4 */ | ||
| 277 | #define INT5_IRQ_NUM 13 /* External INT5 */ | ||
| 278 | #define INT6_IRQ_NUM 14 /* External INT6 */ | ||
| 279 | #define INT7_IRQ_NUM 15 /* External INT7 */ | ||
| 280 | #define IRQ1_IRQ_NUM 16 /* IRQ1 */ | ||
| 281 | #define IRQ2_IRQ_NUM 17 /* IRQ2 */ | ||
| 282 | #define IRQ3_IRQ_NUM 18 /* IRQ3 */ | ||
| 283 | #define IRQ6_IRQ_NUM 19 /* IRQ6 */ | ||
| 284 | #define PEN_IRQ_NUM 20 /* Pen Interrupt */ | ||
| 285 | #define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */ | ||
| 286 | #define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */ | ||
| 287 | #define IRQ7_IRQ_NUM 23 /* IRQ7 */ | ||
| 288 | |||
| 289 | /* '328-compatible definitions */ | ||
| 290 | #define SPI_IRQ_NUM SPIM_IRQ_NUM | ||
| 291 | #define TMR_IRQ_NUM TMR1_IRQ_NUM | ||
| 292 | |||
| 293 | /* | ||
| 294 | * Here go the bitmasks themselves | ||
| 295 | */ | ||
| 296 | #define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */ | ||
| 297 | #define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ | ||
| 298 | #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ | ||
| 299 | #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ | ||
| 300 | #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ | ||
| 301 | #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ | ||
| 302 | #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ | ||
| 303 | #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ | ||
| 304 | #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ | ||
| 305 | #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ | ||
| 306 | #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ | ||
| 307 | #define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */ | ||
| 308 | #define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */ | ||
| 309 | #define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */ | ||
| 310 | #define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */ | ||
| 311 | #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ | ||
| 312 | #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ | ||
| 313 | #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ | ||
| 314 | #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ | ||
| 315 | #define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */ | ||
| 316 | #define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */ | ||
| 317 | #define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */ | ||
| 318 | #define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */ | ||
| 319 | |||
| 320 | /* 'EZ328-compatible definitions */ | ||
| 321 | #define IMR_MSPI IMR_MSPIM | ||
| 322 | #define IMR_MTMR IMR_MTMR1 | ||
| 323 | |||
| 324 | /* | ||
| 325 | * Interrupt Wake-Up Enable Register | ||
| 326 | */ | ||
| 327 | #define IWR_ADDR 0xfffff308 | ||
| 328 | #define IWR LONG_REF(IWR_ADDR) | ||
| 329 | |||
| 330 | #define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ | ||
| 331 | #define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ | ||
| 332 | #define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | ||
| 333 | #define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | ||
| 334 | #define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | ||
| 335 | #define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | ||
| 336 | #define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ | ||
| 337 | #define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | ||
| 338 | #define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | ||
| 339 | #define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | ||
| 340 | #define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | ||
| 341 | #define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ | ||
| 342 | #define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ | ||
| 343 | #define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ | ||
| 344 | #define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ | ||
| 345 | #define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | ||
| 346 | #define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | ||
| 347 | #define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | ||
| 348 | #define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | ||
| 349 | #define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ | ||
| 350 | #define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ | ||
| 351 | #define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ | ||
| 352 | #define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ | ||
| 353 | |||
| 354 | /* | ||
| 355 | * Interrupt Status Register | ||
| 356 | */ | ||
| 357 | #define ISR_ADDR 0xfffff30c | ||
| 358 | #define ISR LONG_REF(ISR_ADDR) | ||
| 359 | |||
| 360 | #define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ | ||
| 361 | #define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ | ||
| 362 | #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | ||
| 363 | #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | ||
| 364 | #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | ||
| 365 | #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | ||
| 366 | #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ | ||
| 367 | #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | ||
| 368 | #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | ||
| 369 | #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | ||
| 370 | #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | ||
| 371 | #define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ | ||
| 372 | #define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ | ||
| 373 | #define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ | ||
| 374 | #define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ | ||
| 375 | #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | ||
| 376 | #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | ||
| 377 | #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | ||
| 378 | #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | ||
| 379 | #define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ | ||
| 380 | #define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ | ||
| 381 | #define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ | ||
| 382 | #define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ | ||
| 383 | |||
| 384 | /* 'EZ328-compatible definitions */ | ||
| 385 | #define ISR_SPI ISR_SPIM | ||
| 386 | #define ISR_TMR ISR_TMR1 | ||
| 387 | |||
| 388 | /* | ||
| 389 | * Interrupt Pending Register | ||
| 390 | */ | ||
| 391 | #define IPR_ADDR 0xfffff310 | ||
| 392 | #define IPR LONG_REF(IPR_ADDR) | ||
| 393 | |||
| 394 | #define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ | ||
| 395 | #define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ | ||
| 396 | #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | ||
| 397 | #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | ||
| 398 | #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | ||
| 399 | #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | ||
| 400 | #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ | ||
| 401 | #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | ||
| 402 | #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | ||
| 403 | #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | ||
| 404 | #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | ||
| 405 | #define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ | ||
| 406 | #define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ | ||
| 407 | #define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ | ||
| 408 | #define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ | ||
| 409 | #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | ||
| 410 | #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | ||
| 411 | #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | ||
| 412 | #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | ||
| 413 | #define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ | ||
| 414 | #define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ | ||
| 415 | #define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ | ||
| 416 | #define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ | ||
| 417 | |||
| 418 | /* 'EZ328-compatible definitions */ | ||
| 419 | #define IPR_SPI IPR_SPIM | ||
| 420 | #define IPR_TMR IPR_TMR1 | ||
| 421 | |||
| 422 | /********** | ||
| 423 | * | ||
| 424 | * 0xFFFFF4xx -- Parallel Ports | ||
| 425 | * | ||
| 426 | **********/ | ||
| 427 | |||
| 428 | /* | ||
| 429 | * Port A | ||
| 430 | */ | ||
| 431 | #define PADIR_ADDR 0xfffff400 /* Port A direction reg */ | ||
| 432 | #define PADATA_ADDR 0xfffff401 /* Port A data register */ | ||
| 433 | #define PASEL_ADDR 0xfffff403 /* Port A Select register */ | ||
| 434 | |||
| 435 | #define PADIR BYTE_REF(PADIR_ADDR) | ||
| 436 | #define PADATA BYTE_REF(PADATA_ADDR) | ||
| 437 | #define PASEL BYTE_REF(PASEL_ADDR) | ||
| 438 | |||
| 439 | #define PA(x) (1 << (x)) | ||
| 440 | #define PA_A(x) PA((x) - 16) /* This is specific to PA only! */ | ||
| 441 | |||
| 442 | #define PA_A16 PA(0) /* Use A16 as PA(0) */ | ||
| 443 | #define PA_A17 PA(1) /* Use A17 as PA(1) */ | ||
| 444 | #define PA_A18 PA(2) /* Use A18 as PA(2) */ | ||
| 445 | #define PA_A19 PA(3) /* Use A19 as PA(3) */ | ||
| 446 | #define PA_A20 PA(4) /* Use A20 as PA(4) */ | ||
| 447 | #define PA_A21 PA(5) /* Use A21 as PA(5) */ | ||
| 448 | #define PA_A22 PA(6) /* Use A22 as PA(6) */ | ||
| 449 | #define PA_A23 PA(7) /* Use A23 as PA(7) */ | ||
| 450 | |||
| 451 | /* | ||
| 452 | * Port B | ||
| 453 | */ | ||
| 454 | #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ | ||
| 455 | #define PBDATA_ADDR 0xfffff409 /* Port B data register */ | ||
| 456 | #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ | ||
| 457 | |||
| 458 | #define PBDIR BYTE_REF(PBDIR_ADDR) | ||
| 459 | #define PBDATA BYTE_REF(PBDATA_ADDR) | ||
| 460 | #define PBSEL BYTE_REF(PBSEL_ADDR) | ||
| 461 | |||
| 462 | #define PB(x) (1 << (x)) | ||
| 463 | #define PB_D(x) PB(x) /* This is specific to port B only */ | ||
| 464 | |||
| 465 | #define PB_D0 PB(0) /* Use D0 as PB(0) */ | ||
| 466 | #define PB_D1 PB(1) /* Use D1 as PB(1) */ | ||
| 467 | #define PB_D2 PB(2) /* Use D2 as PB(2) */ | ||
| 468 | #define PB_D3 PB(3) /* Use D3 as PB(3) */ | ||
| 469 | #define PB_D4 PB(4) /* Use D4 as PB(4) */ | ||
| 470 | #define PB_D5 PB(5) /* Use D5 as PB(5) */ | ||
| 471 | #define PB_D6 PB(6) /* Use D6 as PB(6) */ | ||
| 472 | #define PB_D7 PB(7) /* Use D7 as PB(7) */ | ||
| 473 | |||
| 474 | /* | ||
| 475 | * Port C | ||
| 476 | */ | ||
| 477 | #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ | ||
| 478 | #define PCDATA_ADDR 0xfffff411 /* Port C data register */ | ||
| 479 | #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ | ||
| 480 | |||
| 481 | #define PCDIR BYTE_REF(PCDIR_ADDR) | ||
| 482 | #define PCDATA BYTE_REF(PCDATA_ADDR) | ||
| 483 | #define PCSEL BYTE_REF(PCSEL_ADDR) | ||
| 484 | |||
| 485 | #define PC(x) (1 << (x)) | ||
| 486 | |||
| 487 | #define PC_WE PC(6) /* Use WE as PC(6) */ | ||
| 488 | #define PC_DTACK PC(5) /* Use DTACK as PC(5) */ | ||
| 489 | #define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */ | ||
| 490 | #define PC_LDS PC(2) /* Use LDS as PC(2) */ | ||
| 491 | #define PC_UDS PC(1) /* Use UDS as PC(1) */ | ||
| 492 | #define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */ | ||
| 493 | |||
| 494 | /* | ||
| 495 | * Port D | ||
| 496 | */ | ||
| 497 | #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ | ||
| 498 | #define PDDATA_ADDR 0xfffff419 /* Port D data register */ | ||
| 499 | #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ | ||
| 500 | #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ | ||
| 501 | #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ | ||
| 502 | #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ | ||
| 503 | |||
| 504 | #define PDDIR BYTE_REF(PDDIR_ADDR) | ||
| 505 | #define PDDATA BYTE_REF(PDDATA_ADDR) | ||
| 506 | #define PDPUEN BYTE_REF(PDPUEN_ADDR) | ||
| 507 | #define PDPOL BYTE_REF(PDPOL_ADDR) | ||
| 508 | #define PDIRQEN BYTE_REF(PDIRQEN_ADDR) | ||
| 509 | #define PDIQEG BYTE_REF(PDIQEG_ADDR) | ||
| 510 | |||
| 511 | #define PD(x) (1 << (x)) | ||
| 512 | #define PD_KB(x) PD(x) /* This is specific for Port D only */ | ||
| 513 | |||
| 514 | #define PD_KB0 PD(0) /* Use KB0 as PD(0) */ | ||
| 515 | #define PD_KB1 PD(1) /* Use KB1 as PD(1) */ | ||
| 516 | #define PD_KB2 PD(2) /* Use KB2 as PD(2) */ | ||
| 517 | #define PD_KB3 PD(3) /* Use KB3 as PD(3) */ | ||
| 518 | #define PD_KB4 PD(4) /* Use KB4 as PD(4) */ | ||
| 519 | #define PD_KB5 PD(5) /* Use KB5 as PD(5) */ | ||
| 520 | #define PD_KB6 PD(6) /* Use KB6 as PD(6) */ | ||
| 521 | #define PD_KB7 PD(7) /* Use KB7 as PD(7) */ | ||
| 522 | |||
| 523 | /* | ||
| 524 | * Port E | ||
| 525 | */ | ||
| 526 | #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ | ||
| 527 | #define PEDATA_ADDR 0xfffff421 /* Port E data register */ | ||
| 528 | #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ | ||
| 529 | #define PESEL_ADDR 0xfffff423 /* Port E Select Register */ | ||
| 530 | |||
| 531 | #define PEDIR BYTE_REF(PEDIR_ADDR) | ||
| 532 | #define PEDATA BYTE_REF(PEDATA_ADDR) | ||
| 533 | #define PEPUEN BYTE_REF(PEPUEN_ADDR) | ||
| 534 | #define PESEL BYTE_REF(PESEL_ADDR) | ||
| 535 | |||
| 536 | #define PE(x) (1 << (x)) | ||
| 537 | |||
| 538 | #define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */ | ||
| 539 | #define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */ | ||
| 540 | #define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */ | ||
| 541 | #define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */ | ||
| 542 | #define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */ | ||
| 543 | #define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */ | ||
| 544 | #define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */ | ||
| 545 | |||
| 546 | /* | ||
| 547 | * Port F | ||
| 548 | */ | ||
| 549 | #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ | ||
| 550 | #define PFDATA_ADDR 0xfffff429 /* Port F data register */ | ||
| 551 | #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ | ||
| 552 | #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ | ||
| 553 | |||
| 554 | #define PFDIR BYTE_REF(PFDIR_ADDR) | ||
| 555 | #define PFDATA BYTE_REF(PFDATA_ADDR) | ||
| 556 | #define PFPUEN BYTE_REF(PFPUEN_ADDR) | ||
| 557 | #define PFSEL BYTE_REF(PFSEL_ADDR) | ||
| 558 | |||
| 559 | #define PF(x) (1 << (x)) | ||
| 560 | #define PF_A(x) PF((x) - 24) /* This is Port F specific only */ | ||
| 561 | |||
| 562 | #define PF_A24 PF(0) /* Use A24 as PF(0) */ | ||
| 563 | #define PF_A25 PF(1) /* Use A25 as PF(1) */ | ||
| 564 | #define PF_A26 PF(2) /* Use A26 as PF(2) */ | ||
| 565 | #define PF_A27 PF(3) /* Use A27 as PF(3) */ | ||
| 566 | #define PF_A28 PF(4) /* Use A28 as PF(4) */ | ||
| 567 | #define PF_A29 PF(5) /* Use A29 as PF(5) */ | ||
| 568 | #define PF_A30 PF(6) /* Use A30 as PF(6) */ | ||
| 569 | #define PF_A31 PF(7) /* Use A31 as PF(7) */ | ||
| 570 | |||
| 571 | /* | ||
| 572 | * Port G | ||
| 573 | */ | ||
| 574 | #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ | ||
| 575 | #define PGDATA_ADDR 0xfffff431 /* Port G data register */ | ||
| 576 | #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ | ||
| 577 | #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ | ||
| 578 | |||
| 579 | #define PGDIR BYTE_REF(PGDIR_ADDR) | ||
| 580 | #define PGDATA BYTE_REF(PGDATA_ADDR) | ||
| 581 | #define PGPUEN BYTE_REF(PGPUEN_ADDR) | ||
| 582 | #define PGSEL BYTE_REF(PGSEL_ADDR) | ||
| 583 | |||
| 584 | #define PG(x) (1 << (x)) | ||
| 585 | |||
| 586 | #define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */ | ||
| 587 | #define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */ | ||
| 588 | #define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */ | ||
| 589 | #define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */ | ||
| 590 | #define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */ | ||
| 591 | #define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */ | ||
| 592 | #define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */ | ||
| 593 | #define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */ | ||
| 594 | |||
| 595 | /* | ||
| 596 | * Port J | ||
| 597 | */ | ||
| 598 | #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ | ||
| 599 | #define PJDATA_ADDR 0xfffff439 /* Port J data register */ | ||
| 600 | #define PJSEL_ADDR 0xfffff43b /* Port J Select Register */ | ||
| 601 | |||
| 602 | #define PJDIR BYTE_REF(PJDIR_ADDR) | ||
| 603 | #define PJDATA BYTE_REF(PJDATA_ADDR) | ||
| 604 | #define PJSEL BYTE_REF(PJSEL_ADDR) | ||
| 605 | |||
| 606 | #define PJ(x) (1 << (x)) | ||
| 607 | |||
| 608 | #define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */ | ||
| 609 | |||
| 610 | /* | ||
| 611 | * Port K | ||
| 612 | */ | ||
| 613 | #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */ | ||
| 614 | #define PKDATA_ADDR 0xfffff441 /* Port K data register */ | ||
| 615 | #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */ | ||
| 616 | #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */ | ||
| 617 | |||
| 618 | #define PKDIR BYTE_REF(PKDIR_ADDR) | ||
| 619 | #define PKDATA BYTE_REF(PKDATA_ADDR) | ||
| 620 | #define PKPUEN BYTE_REF(PKPUEN_ADDR) | ||
| 621 | #define PKSEL BYTE_REF(PKSEL_ADDR) | ||
| 622 | |||
| 623 | #define PK(x) (1 << (x)) | ||
| 624 | |||
| 625 | /* | ||
| 626 | * Port M | ||
| 627 | */ | ||
| 628 | #define PMDIR_ADDR 0xfffff438 /* Port M direction reg */ | ||
| 629 | #define PMDATA_ADDR 0xfffff439 /* Port M data register */ | ||
| 630 | #define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */ | ||
| 631 | #define PMSEL_ADDR 0xfffff43b /* Port M Select Register */ | ||
| 632 | |||
| 633 | #define PMDIR BYTE_REF(PMDIR_ADDR) | ||
| 634 | #define PMDATA BYTE_REF(PMDATA_ADDR) | ||
| 635 | #define PMPUEN BYTE_REF(PMPUEN_ADDR) | ||
| 636 | #define PMSEL BYTE_REF(PMSEL_ADDR) | ||
| 637 | |||
| 638 | #define PM(x) (1 << (x)) | ||
| 639 | |||
| 640 | /********** | ||
| 641 | * | ||
| 642 | * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) | ||
| 643 | * | ||
| 644 | **********/ | ||
| 645 | |||
| 646 | /* | ||
| 647 | * PWM Control Register | ||
| 648 | */ | ||
| 649 | #define PWMC_ADDR 0xfffff500 | ||
| 650 | #define PWMC WORD_REF(PWMC_ADDR) | ||
| 651 | |||
| 652 | #define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */ | ||
| 653 | #define PWMC_CLKSEL_SHIFT 0 | ||
| 654 | #define PWMC_PWMEN 0x0010 /* Enable PWM */ | ||
| 655 | #define PMNC_POL 0x0020 /* PWM Output Bit Polarity */ | ||
| 656 | #define PWMC_PIN 0x0080 /* Current PWM output pin status */ | ||
| 657 | #define PWMC_LOAD 0x0100 /* Force a new period */ | ||
| 658 | #define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */ | ||
| 659 | #define PWMC_CLKSRC 0x8000 /* Clock Source Select */ | ||
| 660 | |||
| 661 | /* 'EZ328-compatible definitions */ | ||
| 662 | #define PWMC_EN PWMC_PWMEN | ||
| 663 | |||
| 664 | /* | ||
| 665 | * PWM Period Register | ||
| 666 | */ | ||
| 667 | #define PWMP_ADDR 0xfffff502 | ||
| 668 | #define PWMP WORD_REF(PWMP_ADDR) | ||
| 669 | |||
| 670 | /* | ||
| 671 | * PWM Width Register | ||
| 672 | */ | ||
| 673 | #define PWMW_ADDR 0xfffff504 | ||
| 674 | #define PWMW WORD_REF(PWMW_ADDR) | ||
| 675 | |||
| 676 | /* | ||
| 677 | * PWM Counter Register | ||
| 678 | */ | ||
| 679 | #define PWMCNT_ADDR 0xfffff506 | ||
| 680 | #define PWMCNT WORD_REF(PWMCNT_ADDR) | ||
| 681 | |||
| 682 | /********** | ||
| 683 | * | ||
| 684 | * 0xFFFFF6xx -- General-Purpose Timers | ||
| 685 | * | ||
| 686 | **********/ | ||
| 687 | |||
| 688 | /* | ||
| 689 | * Timer Unit 1 and 2 Control Registers | ||
| 690 | */ | ||
| 691 | #define TCTL1_ADDR 0xfffff600 | ||
| 692 | #define TCTL1 WORD_REF(TCTL1_ADDR) | ||
| 693 | #define TCTL2_ADDR 0xfffff60c | ||
| 694 | #define TCTL2 WORD_REF(TCTL2_ADDR) | ||
| 695 | |||
| 696 | #define TCTL_TEN 0x0001 /* Timer Enable */ | ||
| 697 | #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ | ||
| 698 | #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ | ||
| 699 | #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ | ||
| 700 | #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ | ||
| 701 | #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ | ||
| 702 | #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ | ||
| 703 | #define TCTL_IRQEN 0x0010 /* IRQ Enable */ | ||
| 704 | #define TCTL_OM 0x0020 /* Output Mode */ | ||
| 705 | #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ | ||
| 706 | #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ | ||
| 707 | #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ | ||
| 708 | #define TCTL_FRR 0x0010 /* Free-Run Mode */ | ||
| 709 | |||
| 710 | /* 'EZ328-compatible definitions */ | ||
| 711 | #define TCTL_ADDR TCTL1_ADDR | ||
| 712 | #define TCTL TCTL1 | ||
| 713 | |||
| 714 | /* | ||
| 715 | * Timer Unit 1 and 2 Prescaler Registers | ||
| 716 | */ | ||
| 717 | #define TPRER1_ADDR 0xfffff602 | ||
| 718 | #define TPRER1 WORD_REF(TPRER1_ADDR) | ||
| 719 | #define TPRER2_ADDR 0xfffff60e | ||
| 720 | #define TPRER2 WORD_REF(TPRER2_ADDR) | ||
| 721 | |||
| 722 | /* 'EZ328-compatible definitions */ | ||
| 723 | #define TPRER_ADDR TPRER1_ADDR | ||
| 724 | #define TPRER TPRER1 | ||
| 725 | |||
| 726 | /* | ||
| 727 | * Timer Unit 1 and 2 Compare Registers | ||
| 728 | */ | ||
| 729 | #define TCMP1_ADDR 0xfffff604 | ||
| 730 | #define TCMP1 WORD_REF(TCMP1_ADDR) | ||
| 731 | #define TCMP2_ADDR 0xfffff610 | ||
| 732 | #define TCMP2 WORD_REF(TCMP2_ADDR) | ||
| 733 | |||
| 734 | /* 'EZ328-compatible definitions */ | ||
| 735 | #define TCMP_ADDR TCMP1_ADDR | ||
| 736 | #define TCMP TCMP1 | ||
| 737 | |||
| 738 | /* | ||
| 739 | * Timer Unit 1 and 2 Capture Registers | ||
| 740 | */ | ||
| 741 | #define TCR1_ADDR 0xfffff606 | ||
| 742 | #define TCR1 WORD_REF(TCR1_ADDR) | ||
| 743 | #define TCR2_ADDR 0xfffff612 | ||
| 744 | #define TCR2 WORD_REF(TCR2_ADDR) | ||
| 745 | |||
| 746 | /* 'EZ328-compatible definitions */ | ||
| 747 | #define TCR_ADDR TCR1_ADDR | ||
| 748 | #define TCR TCR1 | ||
| 749 | |||
| 750 | /* | ||
| 751 | * Timer Unit 1 and 2 Counter Registers | ||
| 752 | */ | ||
| 753 | #define TCN1_ADDR 0xfffff608 | ||
| 754 | #define TCN1 WORD_REF(TCN1_ADDR) | ||
| 755 | #define TCN2_ADDR 0xfffff614 | ||
| 756 | #define TCN2 WORD_REF(TCN2_ADDR) | ||
| 757 | |||
| 758 | /* 'EZ328-compatible definitions */ | ||
| 759 | #define TCN_ADDR TCN1_ADDR | ||
| 760 | #define TCN TCN | ||
| 761 | |||
| 762 | /* | ||
| 763 | * Timer Unit 1 and 2 Status Registers | ||
| 764 | */ | ||
| 765 | #define TSTAT1_ADDR 0xfffff60a | ||
| 766 | #define TSTAT1 WORD_REF(TSTAT1_ADDR) | ||
| 767 | #define TSTAT2_ADDR 0xfffff616 | ||
| 768 | #define TSTAT2 WORD_REF(TSTAT2_ADDR) | ||
| 769 | |||
| 770 | #define TSTAT_COMP 0x0001 /* Compare Event occurred */ | ||
| 771 | #define TSTAT_CAPT 0x0001 /* Capture Event occurred */ | ||
| 772 | |||
| 773 | /* 'EZ328-compatible definitions */ | ||
| 774 | #define TSTAT_ADDR TSTAT1_ADDR | ||
| 775 | #define TSTAT TSTAT1 | ||
| 776 | |||
| 777 | /* | ||
| 778 | * Watchdog Compare Register | ||
| 779 | */ | ||
| 780 | #define WRR_ADDR 0xfffff61a | ||
| 781 | #define WRR WORD_REF(WRR_ADDR) | ||
| 782 | |||
| 783 | /* | ||
| 784 | * Watchdog Counter Register | ||
| 785 | */ | ||
| 786 | #define WCN_ADDR 0xfffff61c | ||
| 787 | #define WCN WORD_REF(WCN_ADDR) | ||
| 788 | |||
| 789 | /* | ||
| 790 | * Watchdog Control and Status Register | ||
| 791 | */ | ||
| 792 | #define WCSR_ADDR 0xfffff618 | ||
| 793 | #define WCSR WORD_REF(WCSR_ADDR) | ||
| 794 | |||
| 795 | #define WCSR_WDEN 0x0001 /* Watchdog Enable */ | ||
| 796 | #define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/ | ||
| 797 | #define WCSR_WRST 0x0004 /* Watchdog Reset */ | ||
| 798 | |||
| 799 | /********** | ||
| 800 | * | ||
| 801 | * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS) | ||
| 802 | * | ||
| 803 | **********/ | ||
| 804 | |||
| 805 | /* | ||
| 806 | * SPI Slave Register | ||
| 807 | */ | ||
| 808 | #define SPISR_ADDR 0xfffff700 | ||
| 809 | #define SPISR WORD_REF(SPISR_ADDR) | ||
| 810 | |||
| 811 | #define SPISR_DATA_ADDR 0xfffff701 | ||
| 812 | #define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR) | ||
| 813 | |||
| 814 | #define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */ | ||
| 815 | #define SPISR_DATA_SHIFT 0 | ||
| 816 | #define SPISR_SPISEN 0x0100 /* SPIS module enable */ | ||
| 817 | #define SPISR_POL 0x0200 /* SPSCLK polarity control */ | ||
| 818 | #define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */ | ||
| 819 | #define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */ | ||
| 820 | #define SPISR_DATARDY 0x1000 /* Data ready */ | ||
| 821 | #define SPISR_ENPOL 0x2000 /* Enable Polarity */ | ||
| 822 | #define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */ | ||
| 823 | #define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */ | ||
| 824 | |||
| 825 | /********** | ||
| 826 | * | ||
| 827 | * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) | ||
| 828 | * | ||
| 829 | **********/ | ||
| 830 | |||
| 831 | /* | ||
| 832 | * SPIM Data Register | ||
| 833 | */ | ||
| 834 | #define SPIMDATA_ADDR 0xfffff800 | ||
| 835 | #define SPIMDATA WORD_REF(SPIMDATA_ADDR) | ||
| 836 | |||
| 837 | /* | ||
| 838 | * SPIM Control/Status Register | ||
| 839 | */ | ||
| 840 | #define SPIMCONT_ADDR 0xfffff802 | ||
| 841 | #define SPIMCONT WORD_REF(SPIMCONT_ADDR) | ||
| 842 | |||
| 843 | #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ | ||
| 844 | #define SPIMCONT_BIT_COUNT_SHIFT 0 | ||
| 845 | #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ | ||
| 846 | #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ | ||
| 847 | #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ | ||
| 848 | #define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */ | ||
| 849 | #define SPIMCONT_XCH 0x0100 /* Exchange */ | ||
| 850 | #define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */ | ||
| 851 | #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ | ||
| 852 | #define SPIMCONT_DATA_RATE_SHIFT 13 | ||
| 853 | |||
| 854 | /* 'EZ328-compatible definitions */ | ||
| 855 | #define SPIMCONT_IRQ SPIMCONT_SPIMIRQ | ||
| 856 | #define SPIMCONT_ENABLE SPIMCONT_SPIMEN | ||
| 857 | /********** | ||
| 858 | * | ||
| 859 | * 0xFFFFF9xx -- UART | ||
| 860 | * | ||
| 861 | **********/ | ||
| 862 | |||
| 863 | /* | ||
| 864 | * UART Status/Control Register | ||
| 865 | */ | ||
| 866 | #define USTCNT_ADDR 0xfffff900 | ||
| 867 | #define USTCNT WORD_REF(USTCNT_ADDR) | ||
| 868 | |||
| 869 | #define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */ | ||
| 870 | #define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */ | ||
| 871 | #define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */ | ||
| 872 | #define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */ | ||
| 873 | #define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */ | ||
| 874 | #define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */ | ||
| 875 | #define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */ | ||
| 876 | #define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */ | ||
| 877 | #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ | ||
| 878 | #define USTCNT_STOP 0x0200 /* Stop bit transmission */ | ||
| 879 | #define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */ | ||
| 880 | #define USTCNT_PARITYEN 0x0800 /* Parity Enable */ | ||
| 881 | #define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */ | ||
| 882 | #define USTCNT_TXEN 0x2000 /* Transmitter Enable */ | ||
| 883 | #define USTCNT_RXEN 0x4000 /* Receiver Enable */ | ||
| 884 | #define USTCNT_UARTEN 0x8000 /* UART Enable */ | ||
| 885 | |||
| 886 | /* 'EZ328-compatible definitions */ | ||
| 887 | #define USTCNT_TXAE USTCNT_TXAVAILEN | ||
| 888 | #define USTCNT_TXHE USTCNT_TXHALFEN | ||
| 889 | #define USTCNT_TXEE USTCNT_TXEMPTYEN | ||
| 890 | #define USTCNT_RXRE USTCNT_RXREADYEN | ||
| 891 | #define USTCNT_RXHE USTCNT_RXHALFEN | ||
| 892 | #define USTCNT_RXFE USTCNT_RXFULLEN | ||
| 893 | #define USTCNT_CTSD USTCNT_CTSDELTAEN | ||
| 894 | #define USTCNT_ODD USTCNT_ODD_EVEN | ||
| 895 | #define USTCNT_PEN USTCNT_PARITYEN | ||
| 896 | #define USTCNT_CLKM USTCNT_CLKMODE | ||
| 897 | #define USTCNT_UEN USTCNT_UARTEN | ||
| 898 | |||
| 899 | /* | ||
| 900 | * UART Baud Control Register | ||
| 901 | */ | ||
| 902 | #define UBAUD_ADDR 0xfffff902 | ||
| 903 | #define UBAUD WORD_REF(UBAUD_ADDR) | ||
| 904 | |||
| 905 | #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ | ||
| 906 | #define UBAUD_PRESCALER_SHIFT 0 | ||
| 907 | #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ | ||
| 908 | #define UBAUD_DIVIDE_SHIFT 8 | ||
| 909 | #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ | ||
| 910 | #define UBAUD_GPIOSRC 0x1000 /* GPIO source */ | ||
| 911 | #define UBAUD_GPIODIR 0x2000 /* GPIO Direction */ | ||
| 912 | #define UBAUD_GPIO 0x4000 /* Current GPIO pin status */ | ||
| 913 | #define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */ | ||
| 914 | |||
| 915 | /* | ||
| 916 | * UART Receiver Register | ||
| 917 | */ | ||
| 918 | #define URX_ADDR 0xfffff904 | ||
| 919 | #define URX WORD_REF(URX_ADDR) | ||
| 920 | |||
| 921 | #define URX_RXDATA_ADDR 0xfffff905 | ||
| 922 | #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) | ||
| 923 | |||
| 924 | #define URX_RXDATA_MASK 0x00ff /* Received data */ | ||
| 925 | #define URX_RXDATA_SHIFT 0 | ||
| 926 | #define URX_PARITY_ERROR 0x0100 /* Parity Error */ | ||
| 927 | #define URX_BREAK 0x0200 /* Break Detected */ | ||
| 928 | #define URX_FRAME_ERROR 0x0400 /* Framing Error */ | ||
| 929 | #define URX_OVRUN 0x0800 /* Serial Overrun */ | ||
| 930 | #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ | ||
| 931 | #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ | ||
| 932 | #define URX_FIFO_FULL 0x8000 /* FIFO is Full */ | ||
| 933 | |||
| 934 | /* | ||
| 935 | * UART Transmitter Register | ||
| 936 | */ | ||
| 937 | #define UTX_ADDR 0xfffff906 | ||
| 938 | #define UTX WORD_REF(UTX_ADDR) | ||
| 939 | |||
| 940 | #define UTX_TXDATA_ADDR 0xfffff907 | ||
| 941 | #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) | ||
| 942 | |||
| 943 | #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ | ||
| 944 | #define UTX_TXDATA_SHIFT 0 | ||
| 945 | #define UTX_CTS_DELTA 0x0100 /* CTS changed */ | ||
| 946 | #define UTX_CTS_STATUS 0x0200 /* CTS State */ | ||
| 947 | #define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */ | ||
| 948 | #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ | ||
| 949 | #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ | ||
| 950 | #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ | ||
| 951 | #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ | ||
| 952 | |||
| 953 | /* 'EZ328-compatible definitions */ | ||
| 954 | #define UTX_CTS_STAT UTX_CTS_STATUS | ||
| 955 | #define UTX_NOCTS UTX_IGNORE_CTS | ||
| 956 | |||
| 957 | /* | ||
| 958 | * UART Miscellaneous Register | ||
| 959 | */ | ||
| 960 | #define UMISC_ADDR 0xfffff908 | ||
| 961 | #define UMISC WORD_REF(UMISC_ADDR) | ||
| 962 | |||
| 963 | #define UMISC_TX_POL 0x0004 /* Transmit Polarity */ | ||
| 964 | #define UMISC_RX_POL 0x0008 /* Receive Polarity */ | ||
| 965 | #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ | ||
| 966 | #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ | ||
| 967 | #define UMISC_RTS 0x0040 /* Set RTS status */ | ||
| 968 | #define UMISC_RTSCONT 0x0080 /* Choose RTS control */ | ||
| 969 | #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ | ||
| 970 | #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ | ||
| 971 | #define UMISC_CLKSRC 0x4000 /* Clock Source */ | ||
| 972 | |||
| 973 | |||
| 974 | /* generalization of uart control registers to support multiple ports: */ | ||
| 975 | typedef volatile struct { | ||
| 976 | volatile unsigned short int ustcnt; | ||
| 977 | volatile unsigned short int ubaud; | ||
| 978 | union { | ||
| 979 | volatile unsigned short int w; | ||
| 980 | struct { | ||
| 981 | volatile unsigned char status; | ||
| 982 | volatile unsigned char rxdata; | ||
| 983 | } b; | ||
| 984 | } urx; | ||
| 985 | union { | ||
| 986 | volatile unsigned short int w; | ||
| 987 | struct { | ||
| 988 | volatile unsigned char status; | ||
| 989 | volatile unsigned char txdata; | ||
| 990 | } b; | ||
| 991 | } utx; | ||
| 992 | volatile unsigned short int umisc; | ||
| 993 | volatile unsigned short int pad1; | ||
| 994 | volatile unsigned short int pad2; | ||
| 995 | volatile unsigned short int pad3; | ||
| 996 | } __attribute__((packed)) m68328_uart; | ||
| 997 | |||
| 998 | |||
| 999 | /********** | ||
| 1000 | * | ||
| 1001 | * 0xFFFFFAxx -- LCD Controller | ||
| 1002 | * | ||
| 1003 | **********/ | ||
| 1004 | |||
| 1005 | /* | ||
| 1006 | * LCD Screen Starting Address Register | ||
| 1007 | */ | ||
| 1008 | #define LSSA_ADDR 0xfffffa00 | ||
| 1009 | #define LSSA LONG_REF(LSSA_ADDR) | ||
| 1010 | |||
| 1011 | #define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */ | ||
| 1012 | |||
| 1013 | /* | ||
| 1014 | * LCD Virtual Page Width Register | ||
| 1015 | */ | ||
| 1016 | #define LVPW_ADDR 0xfffffa05 | ||
| 1017 | #define LVPW BYTE_REF(LVPW_ADDR) | ||
| 1018 | |||
| 1019 | /* | ||
| 1020 | * LCD Screen Width Register (not compatible with 'EZ328 !!!) | ||
| 1021 | */ | ||
| 1022 | #define LXMAX_ADDR 0xfffffa08 | ||
| 1023 | #define LXMAX WORD_REF(LXMAX_ADDR) | ||
| 1024 | |||
| 1025 | #define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */ | ||
| 1026 | |||
| 1027 | /* | ||
| 1028 | * LCD Screen Height Register | ||
| 1029 | */ | ||
| 1030 | #define LYMAX_ADDR 0xfffffa0a | ||
| 1031 | #define LYMAX WORD_REF(LYMAX_ADDR) | ||
| 1032 | |||
| 1033 | #define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */ | ||
| 1034 | |||
| 1035 | /* | ||
| 1036 | * LCD Cursor X Position Register | ||
| 1037 | */ | ||
| 1038 | #define LCXP_ADDR 0xfffffa18 | ||
| 1039 | #define LCXP WORD_REF(LCXP_ADDR) | ||
| 1040 | |||
| 1041 | #define LCXP_CC_MASK 0xc000 /* Cursor Control */ | ||
| 1042 | #define LCXP_CC_TRAMSPARENT 0x0000 | ||
| 1043 | #define LCXP_CC_BLACK 0x4000 | ||
| 1044 | #define LCXP_CC_REVERSED 0x8000 | ||
| 1045 | #define LCXP_CC_WHITE 0xc000 | ||
| 1046 | #define LCXP_CXP_MASK 0x02ff /* Cursor X position */ | ||
| 1047 | |||
| 1048 | /* | ||
| 1049 | * LCD Cursor Y Position Register | ||
| 1050 | */ | ||
| 1051 | #define LCYP_ADDR 0xfffffa1a | ||
| 1052 | #define LCYP WORD_REF(LCYP_ADDR) | ||
| 1053 | |||
| 1054 | #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ | ||
| 1055 | |||
| 1056 | /* | ||
| 1057 | * LCD Cursor Width and Heigth Register | ||
| 1058 | */ | ||
| 1059 | #define LCWCH_ADDR 0xfffffa1c | ||
| 1060 | #define LCWCH WORD_REF(LCWCH_ADDR) | ||
| 1061 | |||
| 1062 | #define LCWCH_CH_MASK 0x001f /* Cursor Height */ | ||
| 1063 | #define LCWCH_CH_SHIFT 0 | ||
| 1064 | #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ | ||
| 1065 | #define LCWCH_CW_SHIFT 8 | ||
| 1066 | |||
| 1067 | /* | ||
| 1068 | * LCD Blink Control Register | ||
| 1069 | */ | ||
| 1070 | #define LBLKC_ADDR 0xfffffa1f | ||
| 1071 | #define LBLKC BYTE_REF(LBLKC_ADDR) | ||
| 1072 | |||
| 1073 | #define LBLKC_BD_MASK 0x7f /* Blink Divisor */ | ||
| 1074 | #define LBLKC_BD_SHIFT 0 | ||
| 1075 | #define LBLKC_BKEN 0x80 /* Blink Enabled */ | ||
| 1076 | |||
| 1077 | /* | ||
| 1078 | * LCD Panel Interface Configuration Register | ||
| 1079 | */ | ||
| 1080 | #define LPICF_ADDR 0xfffffa20 | ||
| 1081 | #define LPICF BYTE_REF(LPICF_ADDR) | ||
| 1082 | |||
| 1083 | #define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */ | ||
| 1084 | #define LPICF_GS_BW 0x00 | ||
| 1085 | #define LPICF_GS_GRAY_4 0x01 | ||
| 1086 | #define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */ | ||
| 1087 | #define LPICF_PBSIZ_1 0x00 | ||
| 1088 | #define LPICF_PBSIZ_2 0x02 | ||
| 1089 | #define LPICF_PBSIZ_4 0x04 | ||
| 1090 | |||
| 1091 | /* | ||
| 1092 | * LCD Polarity Configuration Register | ||
| 1093 | */ | ||
| 1094 | #define LPOLCF_ADDR 0xfffffa21 | ||
| 1095 | #define LPOLCF BYTE_REF(LPOLCF_ADDR) | ||
| 1096 | |||
| 1097 | #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ | ||
| 1098 | #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ | ||
| 1099 | #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ | ||
| 1100 | #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ | ||
| 1101 | |||
| 1102 | /* | ||
| 1103 | * LACD (LCD Alternate Crystal Direction) Rate Control Register | ||
| 1104 | */ | ||
| 1105 | #define LACDRC_ADDR 0xfffffa23 | ||
| 1106 | #define LACDRC BYTE_REF(LACDRC_ADDR) | ||
| 1107 | |||
| 1108 | #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ | ||
| 1109 | #define LACDRC_ACD_SHIFT 0 | ||
| 1110 | |||
| 1111 | /* | ||
| 1112 | * LCD Pixel Clock Divider Register | ||
| 1113 | */ | ||
| 1114 | #define LPXCD_ADDR 0xfffffa25 | ||
| 1115 | #define LPXCD BYTE_REF(LPXCD_ADDR) | ||
| 1116 | |||
| 1117 | #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ | ||
| 1118 | #define LPXCD_PCD_SHIFT 0 | ||
| 1119 | |||
| 1120 | /* | ||
| 1121 | * LCD Clocking Control Register | ||
| 1122 | */ | ||
| 1123 | #define LCKCON_ADDR 0xfffffa27 | ||
| 1124 | #define LCKCON BYTE_REF(LCKCON_ADDR) | ||
| 1125 | |||
| 1126 | #define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */ | ||
| 1127 | #define LCKCON_DWIDTH 0x02 /* Display Memory Width */ | ||
| 1128 | #define LCKCON_DWS_MASK 0x3c /* Display Wait-State */ | ||
| 1129 | #define LCKCON_DWS_SHIFT 2 | ||
| 1130 | #define LCKCON_DMA16 0x40 /* DMA burst length */ | ||
| 1131 | #define LCKCON_LCDON 0x80 /* Enable LCD Controller */ | ||
| 1132 | |||
| 1133 | /* 'EZ328-compatible definitions */ | ||
| 1134 | #define LCKCON_DW_MASK LCKCON_DWS_MASK | ||
| 1135 | #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT | ||
| 1136 | |||
| 1137 | /* | ||
| 1138 | * LCD Last Buffer Address Register | ||
| 1139 | */ | ||
| 1140 | #define LLBAR_ADDR 0xfffffa29 | ||
| 1141 | #define LLBAR BYTE_REF(LLBAR_ADDR) | ||
| 1142 | |||
| 1143 | #define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */ | ||
| 1144 | #define LLBAR_LBAR_SHIFT 0 | ||
| 1145 | |||
| 1146 | /* | ||
| 1147 | * LCD Octet Terminal Count Register | ||
| 1148 | */ | ||
| 1149 | #define LOTCR_ADDR 0xfffffa2b | ||
| 1150 | #define LOTCR BYTE_REF(LOTCR_ADDR) | ||
| 1151 | |||
| 1152 | /* | ||
| 1153 | * LCD Panning Offset Register | ||
| 1154 | */ | ||
| 1155 | #define LPOSR_ADDR 0xfffffa2d | ||
| 1156 | #define LPOSR BYTE_REF(LPOSR_ADDR) | ||
| 1157 | |||
| 1158 | #define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */ | ||
| 1159 | #define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */ | ||
| 1160 | #define LPOSR_POS_SHIFT 0 | ||
| 1161 | |||
| 1162 | /* | ||
| 1163 | * LCD Frame Rate Control Modulation Register | ||
| 1164 | */ | ||
| 1165 | #define LFRCM_ADDR 0xfffffa31 | ||
| 1166 | #define LFRCM BYTE_REF(LFRCM_ADDR) | ||
| 1167 | |||
| 1168 | #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ | ||
| 1169 | #define LFRCM_YMOD_SHIFT 0 | ||
| 1170 | #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ | ||
| 1171 | #define LFRCM_XMOD_SHIFT 4 | ||
| 1172 | |||
| 1173 | /* | ||
| 1174 | * LCD Gray Palette Mapping Register | ||
| 1175 | */ | ||
| 1176 | #define LGPMR_ADDR 0xfffffa32 | ||
| 1177 | #define LGPMR WORD_REF(LGPMR_ADDR) | ||
| 1178 | |||
| 1179 | #define LGPMR_GLEVEL3_MASK 0x000f | ||
| 1180 | #define LGPMR_GLEVEL3_SHIFT 0 | ||
| 1181 | #define LGPMR_GLEVEL2_MASK 0x00f0 | ||
| 1182 | #define LGPMR_GLEVEL2_SHIFT 4 | ||
| 1183 | #define LGPMR_GLEVEL0_MASK 0x0f00 | ||
| 1184 | #define LGPMR_GLEVEL0_SHIFT 8 | ||
| 1185 | #define LGPMR_GLEVEL1_MASK 0xf000 | ||
| 1186 | #define LGPMR_GLEVEL1_SHIFT 12 | ||
| 1187 | |||
| 1188 | /********** | ||
| 1189 | * | ||
| 1190 | * 0xFFFFFBxx -- Real-Time Clock (RTC) | ||
| 1191 | * | ||
| 1192 | **********/ | ||
| 1193 | |||
| 1194 | /* | ||
| 1195 | * RTC Hours Minutes and Seconds Register | ||
| 1196 | */ | ||
| 1197 | #define RTCTIME_ADDR 0xfffffb00 | ||
| 1198 | #define RTCTIME LONG_REF(RTCTIME_ADDR) | ||
| 1199 | |||
| 1200 | #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ | ||
| 1201 | #define RTCTIME_SECONDS_SHIFT 0 | ||
| 1202 | #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ | ||
| 1203 | #define RTCTIME_MINUTES_SHIFT 16 | ||
| 1204 | #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ | ||
| 1205 | #define RTCTIME_HOURS_SHIFT 24 | ||
| 1206 | |||
| 1207 | /* | ||
| 1208 | * RTC Alarm Register | ||
| 1209 | */ | ||
| 1210 | #define RTCALRM_ADDR 0xfffffb04 | ||
| 1211 | #define RTCALRM LONG_REF(RTCALRM_ADDR) | ||
| 1212 | |||
| 1213 | #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ | ||
| 1214 | #define RTCALRM_SECONDS_SHIFT 0 | ||
| 1215 | #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ | ||
| 1216 | #define RTCALRM_MINUTES_SHIFT 16 | ||
| 1217 | #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ | ||
| 1218 | #define RTCALRM_HOURS_SHIFT 24 | ||
| 1219 | |||
| 1220 | /* | ||
| 1221 | * RTC Control Register | ||
| 1222 | */ | ||
| 1223 | #define RTCCTL_ADDR 0xfffffb0c | ||
| 1224 | #define RTCCTL WORD_REF(RTCCTL_ADDR) | ||
| 1225 | |||
| 1226 | #define RTCCTL_384 0x0020 /* Crystal Selection */ | ||
| 1227 | #define RTCCTL_ENABLE 0x0080 /* RTC Enable */ | ||
| 1228 | |||
| 1229 | /* 'EZ328-compatible definitions */ | ||
| 1230 | #define RTCCTL_XTL RTCCTL_384 | ||
| 1231 | #define RTCCTL_EN RTCCTL_ENABLE | ||
| 1232 | |||
| 1233 | /* | ||
| 1234 | * RTC Interrupt Status Register | ||
| 1235 | */ | ||
| 1236 | #define RTCISR_ADDR 0xfffffb0e | ||
| 1237 | #define RTCISR WORD_REF(RTCISR_ADDR) | ||
| 1238 | |||
| 1239 | #define RTCISR_SW 0x0001 /* Stopwatch timed out */ | ||
| 1240 | #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ | ||
| 1241 | #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ | ||
| 1242 | #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ | ||
| 1243 | #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ | ||
| 1244 | |||
| 1245 | /* | ||
| 1246 | * RTC Interrupt Enable Register | ||
| 1247 | */ | ||
| 1248 | #define RTCIENR_ADDR 0xfffffb10 | ||
| 1249 | #define RTCIENR WORD_REF(RTCIENR_ADDR) | ||
| 1250 | |||
| 1251 | #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ | ||
| 1252 | #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ | ||
| 1253 | #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ | ||
| 1254 | #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ | ||
| 1255 | #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ | ||
| 1256 | |||
| 1257 | /* | ||
| 1258 | * Stopwatch Minutes Register | ||
| 1259 | */ | ||
| 1260 | #define STPWCH_ADDR 0xfffffb12 | ||
| 1261 | #define STPWCH WORD_REF(STPWCH) | ||
| 1262 | |||
| 1263 | #define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */ | ||
| 1264 | #define SPTWCH_CNT_SHIFT 0 | ||
| 1265 | |||
| 1266 | #endif /* _MC68328_H_ */ | ||
diff --git a/arch/m68k/include/asm/MC68332.h b/arch/m68k/include/asm/MC68332.h new file mode 100644 index 000000000000..6bb8f02685a2 --- /dev/null +++ b/arch/m68k/include/asm/MC68332.h | |||
| @@ -0,0 +1,152 @@ | |||
| 1 | |||
| 2 | /* include/asm-m68knommu/MC68332.h: '332 control registers | ||
| 3 | * | ||
| 4 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, | ||
| 5 | * | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _MC68332_H_ | ||
| 9 | #define _MC68332_H_ | ||
| 10 | |||
| 11 | #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) | ||
| 12 | #define WORD_REF(addr) (*((volatile unsigned short*)addr)) | ||
| 13 | |||
| 14 | #define PORTE_ADDR 0xfffa11 | ||
| 15 | #define PORTE BYTE_REF(PORTE_ADDR) | ||
| 16 | #define DDRE_ADDR 0xfffa15 | ||
| 17 | #define DDRE BYTE_REF(DDRE_ADDR) | ||
| 18 | #define PEPAR_ADDR 0xfffa17 | ||
| 19 | #define PEPAR BYTE_REF(PEPAR_ADDR) | ||
| 20 | |||
| 21 | #define PORTF_ADDR 0xfffa19 | ||
| 22 | #define PORTF BYTE_REF(PORTF_ADDR) | ||
| 23 | #define DDRF_ADDR 0xfffa1d | ||
| 24 | #define DDRF BYTE_REF(DDRF_ADDR) | ||
| 25 | #define PFPAR_ADDR 0xfffa1f | ||
| 26 | #define PFPAR BYTE_REF(PFPAR_ADDR) | ||
| 27 | |||
| 28 | #define PORTQS_ADDR 0xfffc15 | ||
| 29 | #define PORTQS BYTE_REF(PORTQS_ADDR) | ||
| 30 | #define DDRQS_ADDR 0xfffc17 | ||
| 31 | #define DDRQS BYTE_REF(DDRQS_ADDR) | ||
| 32 | #define PQSPAR_ADDR 0xfffc16 | ||
| 33 | #define PQSPAR BYTE_REF(PQSPAR_ADDR) | ||
| 34 | |||
| 35 | #define CSPAR0_ADDR 0xFFFA44 | ||
| 36 | #define CSPAR0 WORD_REF(CSPAR0_ADDR) | ||
| 37 | #define CSPAR1_ADDR 0xFFFA46 | ||
| 38 | #define CSPAR1 WORD_REF(CSPAR1_ADDR) | ||
| 39 | #define CSARBT_ADDR 0xFFFA48 | ||
| 40 | #define CSARBT WORD_REF(CSARBT_ADDR) | ||
| 41 | #define CSOPBT_ADDR 0xFFFA4A | ||
| 42 | #define CSOPBT WORD_REF(CSOPBT_ADDR) | ||
| 43 | #define CSBAR0_ADDR 0xFFFA4C | ||
| 44 | #define CSBAR0 WORD_REF(CSBAR0_ADDR) | ||
| 45 | #define CSOR0_ADDR 0xFFFA4E | ||
| 46 | #define CSOR0 WORD_REF(CSOR0_ADDR) | ||
| 47 | #define CSBAR1_ADDR 0xFFFA50 | ||
| 48 | #define CSBAR1 WORD_REF(CSBAR1_ADDR) | ||
| 49 | #define CSOR1_ADDR 0xFFFA52 | ||
| 50 | #define CSOR1 WORD_REF(CSOR1_ADDR) | ||
| 51 | #define CSBAR2_ADDR 0xFFFA54 | ||
| 52 | #define CSBAR2 WORD_REF(CSBAR2_ADDR) | ||
| 53 | #define CSOR2_ADDR 0xFFFA56 | ||
| 54 | #define CSOR2 WORD_REF(CSOR2_ADDR) | ||
| 55 | #define CSBAR3_ADDR 0xFFFA58 | ||
| 56 | #define CSBAR3 WORD_REF(CSBAR3_ADDR) | ||
| 57 | #define CSOR3_ADDR 0xFFFA5A | ||
| 58 | #define CSOR3 WORD_REF(CSOR3_ADDR) | ||
| 59 | #define CSBAR4_ADDR 0xFFFA5C | ||
| 60 | #define CSBAR4 WORD_REF(CSBAR4_ADDR) | ||
| 61 | #define CSOR4_ADDR 0xFFFA5E | ||
| 62 | #define CSOR4 WORD_REF(CSOR4_ADDR) | ||
| 63 | #define CSBAR5_ADDR 0xFFFA60 | ||
| 64 | #define CSBAR5 WORD_REF(CSBAR5_ADDR) | ||
| 65 | #define CSOR5_ADDR 0xFFFA62 | ||
| 66 | #define CSOR5 WORD_REF(CSOR5_ADDR) | ||
| 67 | #define CSBAR6_ADDR 0xFFFA64 | ||
| 68 | #define CSBAR6 WORD_REF(CSBAR6_ADDR) | ||
| 69 | #define CSOR6_ADDR 0xFFFA66 | ||
| 70 | #define CSOR6 WORD_REF(CSOR6_ADDR) | ||
| 71 | #define CSBAR7_ADDR 0xFFFA68 | ||
| 72 | #define CSBAR7 WORD_REF(CSBAR7_ADDR) | ||
| 73 | #define CSOR7_ADDR 0xFFFA6A | ||
| 74 | #define CSOR7 WORD_REF(CSOR7_ADDR) | ||
| 75 | #define CSBAR8_ADDR 0xFFFA6C | ||
| 76 | #define CSBAR8 WORD_REF(CSBAR8_ADDR) | ||
| 77 | #define CSOR8_ADDR 0xFFFA6E | ||
| 78 | #define CSOR8 WORD_REF(CSOR8_ADDR) | ||
| 79 | #define CSBAR9_ADDR 0xFFFA70 | ||
| 80 | #define CSBAR9 WORD_REF(CSBAR9_ADDR) | ||
| 81 | #define CSOR9_ADDR 0xFFFA72 | ||
| 82 | #define CSOR9 WORD_REF(CSOR9_ADDR) | ||
| 83 | #define CSBAR10_ADDR 0xFFFA74 | ||
| 84 | #define CSBAR10 WORD_REF(CSBAR10_ADDR) | ||
| 85 | #define CSOR10_ADDR 0xFFFA76 | ||
| 86 | #define CSOR10 WORD_REF(CSOR10_ADDR) | ||
| 87 | |||
| 88 | #define CSOR_MODE_ASYNC 0x0000 | ||
| 89 | #define CSOR_MODE_SYNC 0x8000 | ||
| 90 | #define CSOR_MODE_MASK 0x8000 | ||
| 91 | #define CSOR_BYTE_DISABLE 0x0000 | ||
| 92 | #define CSOR_BYTE_UPPER 0x4000 | ||
| 93 | #define CSOR_BYTE_LOWER 0x2000 | ||
| 94 | #define CSOR_BYTE_BOTH 0x6000 | ||
| 95 | #define CSOR_BYTE_MASK 0x6000 | ||
| 96 | #define CSOR_RW_RSVD 0x0000 | ||
| 97 | #define CSOR_RW_READ 0x0800 | ||
| 98 | #define CSOR_RW_WRITE 0x1000 | ||
| 99 | #define CSOR_RW_BOTH 0x1800 | ||
| 100 | #define CSOR_RW_MASK 0x1800 | ||
| 101 | #define CSOR_STROBE_DS 0x0400 | ||
| 102 | #define CSOR_STROBE_AS 0x0000 | ||
| 103 | #define CSOR_STROBE_MASK 0x0400 | ||
| 104 | #define CSOR_DSACK_WAIT(x) (wait << 6) | ||
| 105 | #define CSOR_DSACK_FTERM (14 << 6) | ||
| 106 | #define CSOR_DSACK_EXTERNAL (15 << 6) | ||
| 107 | #define CSOR_DSACK_MASK 0x03c0 | ||
| 108 | #define CSOR_SPACE_CPU 0x0000 | ||
| 109 | #define CSOR_SPACE_USER 0x0010 | ||
| 110 | #define CSOR_SPACE_SU 0x0020 | ||
| 111 | #define CSOR_SPACE_BOTH 0x0030 | ||
| 112 | #define CSOR_SPACE_MASK 0x0030 | ||
| 113 | #define CSOR_IPL_ALL 0x0000 | ||
| 114 | #define CSOR_IPL_PRIORITY(x) (x << 1) | ||
| 115 | #define CSOR_IPL_MASK 0x000e | ||
| 116 | #define CSOR_AVEC_ON 0x0001 | ||
| 117 | #define CSOR_AVEC_OFF 0x0000 | ||
| 118 | #define CSOR_AVEC_MASK 0x0001 | ||
| 119 | |||
| 120 | #define CSBAR_ADDR(x) ((addr >> 11) << 3) | ||
| 121 | #define CSBAR_ADDR_MASK 0xfff8 | ||
| 122 | #define CSBAR_BLKSIZE_2K 0x0000 | ||
| 123 | #define CSBAR_BLKSIZE_8K 0x0001 | ||
| 124 | #define CSBAR_BLKSIZE_16K 0x0002 | ||
| 125 | #define CSBAR_BLKSIZE_64K 0x0003 | ||
| 126 | #define CSBAR_BLKSIZE_128K 0x0004 | ||
| 127 | #define CSBAR_BLKSIZE_256K 0x0005 | ||
| 128 | #define CSBAR_BLKSIZE_512K 0x0006 | ||
| 129 | #define CSBAR_BLKSIZE_1M 0x0007 | ||
| 130 | #define CSBAR_BLKSIZE_MASK 0x0007 | ||
| 131 | |||
| 132 | #define CSPAR_DISC 0 | ||
| 133 | #define CSPAR_ALT 1 | ||
| 134 | #define CSPAR_CS8 2 | ||
| 135 | #define CSPAR_CS16 3 | ||
| 136 | #define CSPAR_MASK 3 | ||
| 137 | |||
| 138 | #define CSPAR0_CSBOOT(x) (x << 0) | ||
| 139 | #define CSPAR0_CS0(x) (x << 2) | ||
| 140 | #define CSPAR0_CS1(x) (x << 4) | ||
| 141 | #define CSPAR0_CS2(x) (x << 6) | ||
| 142 | #define CSPAR0_CS3(x) (x << 8) | ||
| 143 | #define CSPAR0_CS4(x) (x << 10) | ||
| 144 | #define CSPAR0_CS5(x) (x << 12) | ||
| 145 | |||
| 146 | #define CSPAR1_CS6(x) (x << 0) | ||
| 147 | #define CSPAR1_CS7(x) (x << 2) | ||
| 148 | #define CSPAR1_CS8(x) (x << 4) | ||
| 149 | #define CSPAR1_CS9(x) (x << 6) | ||
| 150 | #define CSPAR1_CS10(x) (x << 8) | ||
| 151 | |||
| 152 | #endif | ||
diff --git a/arch/m68k/include/asm/MC68EZ328.h b/arch/m68k/include/asm/MC68EZ328.h new file mode 100644 index 000000000000..69b7f9139e5e --- /dev/null +++ b/arch/m68k/include/asm/MC68EZ328.h | |||
| @@ -0,0 +1,1253 @@ | |||
| 1 | |||
| 2 | /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> | ||
| 5 | * Bear & Hare Software, Inc. | ||
| 6 | * | ||
| 7 | * Based on include/asm-m68knommu/MC68332.h | ||
| 8 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, | ||
| 9 | * The Silver Hammer Group, Ltd. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _MC68EZ328_H_ | ||
| 14 | #define _MC68EZ328_H_ | ||
| 15 | |||
| 16 | #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) | ||
| 17 | #define WORD_REF(addr) (*((volatile unsigned short*)addr)) | ||
| 18 | #define LONG_REF(addr) (*((volatile unsigned long*)addr)) | ||
| 19 | |||
| 20 | #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) | ||
| 21 | #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) | ||
| 22 | |||
| 23 | /********** | ||
| 24 | * | ||
| 25 | * 0xFFFFF0xx -- System Control | ||
| 26 | * | ||
| 27 | **********/ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * System Control Register (SCR) | ||
| 31 | */ | ||
| 32 | #define SCR_ADDR 0xfffff000 | ||
| 33 | #define SCR BYTE_REF(SCR_ADDR) | ||
| 34 | |||
| 35 | #define SCR_WDTH8 0x01 /* 8-Bit Width Select */ | ||
| 36 | #define SCR_DMAP 0x04 /* Double Map */ | ||
| 37 | #define SCR_SO 0x08 /* Supervisor Only */ | ||
| 38 | #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ | ||
| 39 | #define SCR_PRV 0x20 /* Privilege Violation */ | ||
| 40 | #define SCR_WPV 0x40 /* Write Protect Violation */ | ||
| 41 | #define SCR_BETO 0x80 /* Bus-Error TimeOut */ | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) | ||
| 45 | */ | ||
| 46 | #define MRR_ADDR 0xfffff004 | ||
| 47 | #define MRR LONG_REF(MRR_ADDR) | ||
| 48 | |||
| 49 | /********** | ||
| 50 | * | ||
| 51 | * 0xFFFFF1xx -- Chip-Select logic | ||
| 52 | * | ||
| 53 | **********/ | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Chip Select Group Base Registers | ||
| 57 | */ | ||
| 58 | #define CSGBA_ADDR 0xfffff100 | ||
| 59 | #define CSGBB_ADDR 0xfffff102 | ||
| 60 | |||
| 61 | #define CSGBC_ADDR 0xfffff104 | ||
| 62 | #define CSGBD_ADDR 0xfffff106 | ||
| 63 | |||
| 64 | #define CSGBA WORD_REF(CSGBA_ADDR) | ||
| 65 | #define CSGBB WORD_REF(CSGBB_ADDR) | ||
| 66 | #define CSGBC WORD_REF(CSGBC_ADDR) | ||
| 67 | #define CSGBD WORD_REF(CSGBD_ADDR) | ||
| 68 | |||
| 69 | /* | ||
| 70 | * Chip Select Registers | ||
| 71 | */ | ||
| 72 | #define CSA_ADDR 0xfffff110 | ||
| 73 | #define CSB_ADDR 0xfffff112 | ||
| 74 | #define CSC_ADDR 0xfffff114 | ||
| 75 | #define CSD_ADDR 0xfffff116 | ||
| 76 | |||
| 77 | #define CSA WORD_REF(CSA_ADDR) | ||
| 78 | #define CSB WORD_REF(CSB_ADDR) | ||
| 79 | #define CSC WORD_REF(CSC_ADDR) | ||
| 80 | #define CSD WORD_REF(CSD_ADDR) | ||
| 81 | |||
| 82 | #define CSA_EN 0x0001 /* Chip-Select Enable */ | ||
| 83 | #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 84 | #define CSA_SIZ_SHIFT 1 | ||
| 85 | #define CSA_WS_MASK 0x0070 /* Wait State */ | ||
| 86 | #define CSA_WS_SHIFT 4 | ||
| 87 | #define CSA_BSW 0x0080 /* Data Bus Width */ | ||
| 88 | #define CSA_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 89 | #define CSA_RO 0x8000 /* Read-Only */ | ||
| 90 | |||
| 91 | #define CSB_EN 0x0001 /* Chip-Select Enable */ | ||
| 92 | #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 93 | #define CSB_SIZ_SHIFT 1 | ||
| 94 | #define CSB_WS_MASK 0x0070 /* Wait State */ | ||
| 95 | #define CSB_WS_SHIFT 4 | ||
| 96 | #define CSB_BSW 0x0080 /* Data Bus Width */ | ||
| 97 | #define CSB_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 98 | #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | ||
| 99 | #define CSB_UPSIZ_SHIFT 11 | ||
| 100 | #define CSB_ROP 0x2000 /* Readonly if protected */ | ||
| 101 | #define CSB_SOP 0x4000 /* Supervisor only if protected */ | ||
| 102 | #define CSB_RO 0x8000 /* Read-Only */ | ||
| 103 | |||
| 104 | #define CSC_EN 0x0001 /* Chip-Select Enable */ | ||
| 105 | #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 106 | #define CSC_SIZ_SHIFT 1 | ||
| 107 | #define CSC_WS_MASK 0x0070 /* Wait State */ | ||
| 108 | #define CSC_WS_SHIFT 4 | ||
| 109 | #define CSC_BSW 0x0080 /* Data Bus Width */ | ||
| 110 | #define CSC_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 111 | #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | ||
| 112 | #define CSC_UPSIZ_SHIFT 11 | ||
| 113 | #define CSC_ROP 0x2000 /* Readonly if protected */ | ||
| 114 | #define CSC_SOP 0x4000 /* Supervisor only if protected */ | ||
| 115 | #define CSC_RO 0x8000 /* Read-Only */ | ||
| 116 | |||
| 117 | #define CSD_EN 0x0001 /* Chip-Select Enable */ | ||
| 118 | #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 119 | #define CSD_SIZ_SHIFT 1 | ||
| 120 | #define CSD_WS_MASK 0x0070 /* Wait State */ | ||
| 121 | #define CSD_WS_SHIFT 4 | ||
| 122 | #define CSD_BSW 0x0080 /* Data Bus Width */ | ||
| 123 | #define CSD_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 124 | #define CSD_DRAM 0x0200 /* Dram Selection */ | ||
| 125 | #define CSD_COMB 0x0400 /* Combining */ | ||
| 126 | #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | ||
| 127 | #define CSD_UPSIZ_SHIFT 11 | ||
| 128 | #define CSD_ROP 0x2000 /* Readonly if protected */ | ||
| 129 | #define CSD_SOP 0x4000 /* Supervisor only if protected */ | ||
| 130 | #define CSD_RO 0x8000 /* Read-Only */ | ||
| 131 | |||
| 132 | /* | ||
| 133 | * Emulation Chip-Select Register | ||
| 134 | */ | ||
| 135 | #define EMUCS_ADDR 0xfffff118 | ||
| 136 | #define EMUCS WORD_REF(EMUCS_ADDR) | ||
| 137 | |||
| 138 | #define EMUCS_WS_MASK 0x0070 | ||
| 139 | #define EMUCS_WS_SHIFT 4 | ||
| 140 | |||
| 141 | /********** | ||
| 142 | * | ||
| 143 | * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control | ||
| 144 | * | ||
| 145 | **********/ | ||
| 146 | |||
| 147 | /* | ||
| 148 | * PLL Control Register | ||
| 149 | */ | ||
| 150 | #define PLLCR_ADDR 0xfffff200 | ||
| 151 | #define PLLCR WORD_REF(PLLCR_ADDR) | ||
| 152 | |||
| 153 | #define PLLCR_DISPLL 0x0008 /* Disable PLL */ | ||
| 154 | #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ | ||
| 155 | #define PLLCR_PRESC 0x0020 /* VCO prescaler */ | ||
| 156 | #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ | ||
| 157 | #define PLLCR_SYSCLK_SEL_SHIFT 8 | ||
| 158 | #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ | ||
| 159 | #define PLLCR_LCDCLK_SEL_SHIFT 11 | ||
| 160 | |||
| 161 | /* '328-compatible definitions */ | ||
| 162 | #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK | ||
| 163 | #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT | ||
| 164 | |||
| 165 | /* | ||
| 166 | * PLL Frequency Select Register | ||
| 167 | */ | ||
| 168 | #define PLLFSR_ADDR 0xfffff202 | ||
| 169 | #define PLLFSR WORD_REF(PLLFSR_ADDR) | ||
| 170 | |||
| 171 | #define PLLFSR_PC_MASK 0x00ff /* P Count */ | ||
| 172 | #define PLLFSR_PC_SHIFT 0 | ||
| 173 | #define PLLFSR_QC_MASK 0x0f00 /* Q Count */ | ||
| 174 | #define PLLFSR_QC_SHIFT 8 | ||
| 175 | #define PLLFSR_PROT 0x4000 /* Protect P & Q */ | ||
| 176 | #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ | ||
| 177 | |||
| 178 | /* | ||
| 179 | * Power Control Register | ||
| 180 | */ | ||
| 181 | #define PCTRL_ADDR 0xfffff207 | ||
| 182 | #define PCTRL BYTE_REF(PCTRL_ADDR) | ||
| 183 | |||
| 184 | #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ | ||
| 185 | #define PCTRL_WIDTH_SHIFT 0 | ||
| 186 | #define PCTRL_PCEN 0x80 /* Power Control Enable */ | ||
| 187 | |||
| 188 | /********** | ||
| 189 | * | ||
| 190 | * 0xFFFFF3xx -- Interrupt Controller | ||
| 191 | * | ||
| 192 | **********/ | ||
| 193 | |||
| 194 | /* | ||
| 195 | * Interrupt Vector Register | ||
| 196 | */ | ||
| 197 | #define IVR_ADDR 0xfffff300 | ||
| 198 | #define IVR BYTE_REF(IVR_ADDR) | ||
| 199 | |||
| 200 | #define IVR_VECTOR_MASK 0xF8 | ||
| 201 | |||
| 202 | /* | ||
| 203 | * Interrupt control Register | ||
| 204 | */ | ||
| 205 | #define ICR_ADDR 0xfffff302 | ||
| 206 | #define ICR WORD_REF(ICR_ADDR) | ||
| 207 | |||
| 208 | #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ | ||
| 209 | #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ | ||
| 210 | #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ | ||
| 211 | #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ | ||
| 212 | #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ | ||
| 213 | #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ | ||
| 214 | #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ | ||
| 215 | #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ | ||
| 216 | #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ | ||
| 217 | |||
| 218 | /* | ||
| 219 | * Interrupt Mask Register | ||
| 220 | */ | ||
| 221 | #define IMR_ADDR 0xfffff304 | ||
| 222 | #define IMR LONG_REF(IMR_ADDR) | ||
| 223 | |||
| 224 | /* | ||
| 225 | * Define the names for bit positions first. This is useful for | ||
| 226 | * request_irq | ||
| 227 | */ | ||
| 228 | #define SPI_IRQ_NUM 0 /* SPI interrupt */ | ||
| 229 | #define TMR_IRQ_NUM 1 /* Timer interrupt */ | ||
| 230 | #define UART_IRQ_NUM 2 /* UART interrupt */ | ||
| 231 | #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ | ||
| 232 | #define RTC_IRQ_NUM 4 /* RTC interrupt */ | ||
| 233 | #define KB_IRQ_NUM 6 /* Keyboard Interrupt */ | ||
| 234 | #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ | ||
| 235 | #define INT0_IRQ_NUM 8 /* External INT0 */ | ||
| 236 | #define INT1_IRQ_NUM 9 /* External INT1 */ | ||
| 237 | #define INT2_IRQ_NUM 10 /* External INT2 */ | ||
| 238 | #define INT3_IRQ_NUM 11 /* External INT3 */ | ||
| 239 | #define IRQ1_IRQ_NUM 16 /* IRQ1 */ | ||
| 240 | #define IRQ2_IRQ_NUM 17 /* IRQ2 */ | ||
| 241 | #define IRQ3_IRQ_NUM 18 /* IRQ3 */ | ||
| 242 | #define IRQ6_IRQ_NUM 19 /* IRQ6 */ | ||
| 243 | #define IRQ5_IRQ_NUM 20 /* IRQ5 */ | ||
| 244 | #define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ | ||
| 245 | #define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ | ||
| 246 | |||
| 247 | /* '328-compatible definitions */ | ||
| 248 | #define SPIM_IRQ_NUM SPI_IRQ_NUM | ||
| 249 | #define TMR1_IRQ_NUM TMR_IRQ_NUM | ||
| 250 | |||
| 251 | /* | ||
| 252 | * Here go the bitmasks themselves | ||
| 253 | */ | ||
| 254 | #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ | ||
| 255 | #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ | ||
| 256 | #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ | ||
| 257 | #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ | ||
| 258 | #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ | ||
| 259 | #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ | ||
| 260 | #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ | ||
| 261 | #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ | ||
| 262 | #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ | ||
| 263 | #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ | ||
| 264 | #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ | ||
| 265 | #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ | ||
| 266 | #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ | ||
| 267 | #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ | ||
| 268 | #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ | ||
| 269 | #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ | ||
| 270 | #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ | ||
| 271 | #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ | ||
| 272 | |||
| 273 | /* '328-compatible definitions */ | ||
| 274 | #define IMR_MSPIM IMR_MSPI | ||
| 275 | #define IMR_MTMR1 IMR_MTMR | ||
| 276 | |||
| 277 | /* | ||
| 278 | * Interrupt Status Register | ||
| 279 | */ | ||
| 280 | #define ISR_ADDR 0xfffff30c | ||
| 281 | #define ISR LONG_REF(ISR_ADDR) | ||
| 282 | |||
| 283 | #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ | ||
| 284 | #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ | ||
| 285 | #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | ||
| 286 | #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | ||
| 287 | #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | ||
| 288 | #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | ||
| 289 | #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ | ||
| 290 | #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | ||
| 291 | #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | ||
| 292 | #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | ||
| 293 | #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | ||
| 294 | #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | ||
| 295 | #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | ||
| 296 | #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | ||
| 297 | #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | ||
| 298 | #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ | ||
| 299 | #define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ | ||
| 300 | #define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ | ||
| 301 | |||
| 302 | /* '328-compatible definitions */ | ||
| 303 | #define ISR_SPIM ISR_SPI | ||
| 304 | #define ISR_TMR1 ISR_TMR | ||
| 305 | |||
| 306 | /* | ||
| 307 | * Interrupt Pending Register | ||
| 308 | */ | ||
| 309 | #define IPR_ADDR 0xfffff30c | ||
| 310 | #define IPR LONG_REF(IPR_ADDR) | ||
| 311 | |||
| 312 | #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ | ||
| 313 | #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ | ||
| 314 | #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | ||
| 315 | #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | ||
| 316 | #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | ||
| 317 | #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | ||
| 318 | #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ | ||
| 319 | #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | ||
| 320 | #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | ||
| 321 | #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | ||
| 322 | #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | ||
| 323 | #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | ||
| 324 | #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | ||
| 325 | #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | ||
| 326 | #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | ||
| 327 | #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ | ||
| 328 | #define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ | ||
| 329 | #define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ | ||
| 330 | |||
| 331 | /* '328-compatible definitions */ | ||
| 332 | #define IPR_SPIM IPR_SPI | ||
| 333 | #define IPR_TMR1 IPR_TMR | ||
| 334 | |||
| 335 | /********** | ||
| 336 | * | ||
| 337 | * 0xFFFFF4xx -- Parallel Ports | ||
| 338 | * | ||
| 339 | **********/ | ||
| 340 | |||
| 341 | /* | ||
| 342 | * Port A | ||
| 343 | */ | ||
| 344 | #define PADIR_ADDR 0xfffff400 /* Port A direction reg */ | ||
| 345 | #define PADATA_ADDR 0xfffff401 /* Port A data register */ | ||
| 346 | #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ | ||
| 347 | |||
| 348 | #define PADIR BYTE_REF(PADIR_ADDR) | ||
| 349 | #define PADATA BYTE_REF(PADATA_ADDR) | ||
| 350 | #define PAPUEN BYTE_REF(PAPUEN_ADDR) | ||
| 351 | |||
| 352 | #define PA(x) (1 << (x)) | ||
| 353 | |||
| 354 | /* | ||
| 355 | * Port B | ||
| 356 | */ | ||
| 357 | #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ | ||
| 358 | #define PBDATA_ADDR 0xfffff409 /* Port B data register */ | ||
| 359 | #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ | ||
| 360 | #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ | ||
| 361 | |||
| 362 | #define PBDIR BYTE_REF(PBDIR_ADDR) | ||
| 363 | #define PBDATA BYTE_REF(PBDATA_ADDR) | ||
| 364 | #define PBPUEN BYTE_REF(PBPUEN_ADDR) | ||
| 365 | #define PBSEL BYTE_REF(PBSEL_ADDR) | ||
| 366 | |||
| 367 | #define PB(x) (1 << (x)) | ||
| 368 | |||
| 369 | #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ | ||
| 370 | #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ | ||
| 371 | #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ | ||
| 372 | #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ | ||
| 373 | #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ | ||
| 374 | #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ | ||
| 375 | #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ | ||
| 376 | #define PB_PWMO 0x80 /* Use PWMO as PB[7] */ | ||
| 377 | |||
| 378 | /* | ||
| 379 | * Port C | ||
| 380 | */ | ||
| 381 | #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ | ||
| 382 | #define PCDATA_ADDR 0xfffff411 /* Port C data register */ | ||
| 383 | #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ | ||
| 384 | #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ | ||
| 385 | |||
| 386 | #define PCDIR BYTE_REF(PCDIR_ADDR) | ||
| 387 | #define PCDATA BYTE_REF(PCDATA_ADDR) | ||
| 388 | #define PCPDEN BYTE_REF(PCPDEN_ADDR) | ||
| 389 | #define PCSEL BYTE_REF(PCSEL_ADDR) | ||
| 390 | |||
| 391 | #define PC(x) (1 << (x)) | ||
| 392 | |||
| 393 | #define PC_LD0 0x01 /* Use LD0 as PC[0] */ | ||
| 394 | #define PC_LD1 0x02 /* Use LD1 as PC[1] */ | ||
| 395 | #define PC_LD2 0x04 /* Use LD2 as PC[2] */ | ||
| 396 | #define PC_LD3 0x08 /* Use LD3 as PC[3] */ | ||
| 397 | #define PC_LFLM 0x10 /* Use LFLM as PC[4] */ | ||
| 398 | #define PC_LLP 0x20 /* Use LLP as PC[5] */ | ||
| 399 | #define PC_LCLK 0x40 /* Use LCLK as PC[6] */ | ||
| 400 | #define PC_LACD 0x80 /* Use LACD as PC[7] */ | ||
| 401 | |||
| 402 | /* | ||
| 403 | * Port D | ||
| 404 | */ | ||
| 405 | #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ | ||
| 406 | #define PDDATA_ADDR 0xfffff419 /* Port D data register */ | ||
| 407 | #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ | ||
| 408 | #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ | ||
| 409 | #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ | ||
| 410 | #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ | ||
| 411 | #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ | ||
| 412 | #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ | ||
| 413 | |||
| 414 | #define PDDIR BYTE_REF(PDDIR_ADDR) | ||
| 415 | #define PDDATA BYTE_REF(PDDATA_ADDR) | ||
| 416 | #define PDPUEN BYTE_REF(PDPUEN_ADDR) | ||
| 417 | #define PDSEL BYTE_REF(PDSEL_ADDR) | ||
| 418 | #define PDPOL BYTE_REF(PDPOL_ADDR) | ||
| 419 | #define PDIRQEN BYTE_REF(PDIRQEN_ADDR) | ||
| 420 | #define PDKBEN BYTE_REF(PDKBEN_ADDR) | ||
| 421 | #define PDIQEG BYTE_REF(PDIQEG_ADDR) | ||
| 422 | |||
| 423 | #define PD(x) (1 << (x)) | ||
| 424 | |||
| 425 | #define PD_INT0 0x01 /* Use INT0 as PD[0] */ | ||
| 426 | #define PD_INT1 0x02 /* Use INT1 as PD[1] */ | ||
| 427 | #define PD_INT2 0x04 /* Use INT2 as PD[2] */ | ||
| 428 | #define PD_INT3 0x08 /* Use INT3 as PD[3] */ | ||
| 429 | #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ | ||
| 430 | #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ | ||
| 431 | #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ | ||
| 432 | #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ | ||
| 433 | |||
| 434 | /* | ||
| 435 | * Port E | ||
| 436 | */ | ||
| 437 | #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ | ||
| 438 | #define PEDATA_ADDR 0xfffff421 /* Port E data register */ | ||
| 439 | #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ | ||
| 440 | #define PESEL_ADDR 0xfffff423 /* Port E Select Register */ | ||
| 441 | |||
| 442 | #define PEDIR BYTE_REF(PEDIR_ADDR) | ||
| 443 | #define PEDATA BYTE_REF(PEDATA_ADDR) | ||
| 444 | #define PEPUEN BYTE_REF(PEPUEN_ADDR) | ||
| 445 | #define PESEL BYTE_REF(PESEL_ADDR) | ||
| 446 | |||
| 447 | #define PE(x) (1 << (x)) | ||
| 448 | |||
| 449 | #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ | ||
| 450 | #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ | ||
| 451 | #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ | ||
| 452 | #define PE_DWE 0x08 /* Use DWE as PE[3] */ | ||
| 453 | #define PE_RXD 0x10 /* Use RXD as PE[4] */ | ||
| 454 | #define PE_TXD 0x20 /* Use TXD as PE[5] */ | ||
| 455 | #define PE_RTS 0x40 /* Use RTS as PE[6] */ | ||
| 456 | #define PE_CTS 0x80 /* Use CTS as PE[7] */ | ||
| 457 | |||
| 458 | /* | ||
| 459 | * Port F | ||
| 460 | */ | ||
| 461 | #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ | ||
| 462 | #define PFDATA_ADDR 0xfffff429 /* Port F data register */ | ||
| 463 | #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ | ||
| 464 | #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ | ||
| 465 | |||
| 466 | #define PFDIR BYTE_REF(PFDIR_ADDR) | ||
| 467 | #define PFDATA BYTE_REF(PFDATA_ADDR) | ||
| 468 | #define PFPUEN BYTE_REF(PFPUEN_ADDR) | ||
| 469 | #define PFSEL BYTE_REF(PFSEL_ADDR) | ||
| 470 | |||
| 471 | #define PF(x) (1 << (x)) | ||
| 472 | |||
| 473 | #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ | ||
| 474 | #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ | ||
| 475 | #define PF_CLKO 0x04 /* Use CLKO as PF[2] */ | ||
| 476 | #define PF_A20 0x08 /* Use A20 as PF[3] */ | ||
| 477 | #define PF_A21 0x10 /* Use A21 as PF[4] */ | ||
| 478 | #define PF_A22 0x20 /* Use A22 as PF[5] */ | ||
| 479 | #define PF_A23 0x40 /* Use A23 as PF[6] */ | ||
| 480 | #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ | ||
| 481 | |||
| 482 | /* | ||
| 483 | * Port G | ||
| 484 | */ | ||
| 485 | #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ | ||
| 486 | #define PGDATA_ADDR 0xfffff431 /* Port G data register */ | ||
| 487 | #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ | ||
| 488 | #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ | ||
| 489 | |||
| 490 | #define PGDIR BYTE_REF(PGDIR_ADDR) | ||
| 491 | #define PGDATA BYTE_REF(PGDATA_ADDR) | ||
| 492 | #define PGPUEN BYTE_REF(PGPUEN_ADDR) | ||
| 493 | #define PGSEL BYTE_REF(PGSEL_ADDR) | ||
| 494 | |||
| 495 | #define PG(x) (1 << (x)) | ||
| 496 | |||
| 497 | #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ | ||
| 498 | #define PG_A0 0x02 /* Use A0 as PG[1] */ | ||
| 499 | #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ | ||
| 500 | #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ | ||
| 501 | #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ | ||
| 502 | #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ | ||
| 503 | |||
| 504 | /********** | ||
| 505 | * | ||
| 506 | * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) | ||
| 507 | * | ||
| 508 | **********/ | ||
| 509 | |||
| 510 | /* | ||
| 511 | * PWM Control Register | ||
| 512 | */ | ||
| 513 | #define PWMC_ADDR 0xfffff500 | ||
| 514 | #define PWMC WORD_REF(PWMC_ADDR) | ||
| 515 | |||
| 516 | #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ | ||
| 517 | #define PWMC_CLKSEL_SHIFT 0 | ||
| 518 | #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ | ||
| 519 | #define PWMC_REPEAT_SHIFT 2 | ||
| 520 | #define PWMC_EN 0x0010 /* Enable PWM */ | ||
| 521 | #define PMNC_FIFOAV 0x0020 /* FIFO Available */ | ||
| 522 | #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ | ||
| 523 | #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ | ||
| 524 | #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ | ||
| 525 | #define PWMC_PRESCALER_SHIFT 8 | ||
| 526 | #define PWMC_CLKSRC 0x8000 /* Clock Source Select */ | ||
| 527 | |||
| 528 | /* '328-compatible definitions */ | ||
| 529 | #define PWMC_PWMEN PWMC_EN | ||
| 530 | |||
| 531 | /* | ||
| 532 | * PWM Sample Register | ||
| 533 | */ | ||
| 534 | #define PWMS_ADDR 0xfffff502 | ||
| 535 | #define PWMS WORD_REF(PWMS_ADDR) | ||
| 536 | |||
| 537 | /* | ||
| 538 | * PWM Period Register | ||
| 539 | */ | ||
| 540 | #define PWMP_ADDR 0xfffff504 | ||
| 541 | #define PWMP BYTE_REF(PWMP_ADDR) | ||
| 542 | |||
| 543 | /* | ||
| 544 | * PWM Counter Register | ||
| 545 | */ | ||
| 546 | #define PWMCNT_ADDR 0xfffff505 | ||
| 547 | #define PWMCNT BYTE_REF(PWMCNT_ADDR) | ||
| 548 | |||
| 549 | /********** | ||
| 550 | * | ||
| 551 | * 0xFFFFF6xx -- General-Purpose Timer | ||
| 552 | * | ||
| 553 | **********/ | ||
| 554 | |||
| 555 | /* | ||
| 556 | * Timer Control register | ||
| 557 | */ | ||
| 558 | #define TCTL_ADDR 0xfffff600 | ||
| 559 | #define TCTL WORD_REF(TCTL_ADDR) | ||
| 560 | |||
| 561 | #define TCTL_TEN 0x0001 /* Timer Enable */ | ||
| 562 | #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ | ||
| 563 | #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ | ||
| 564 | #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ | ||
| 565 | #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ | ||
| 566 | #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ | ||
| 567 | #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ | ||
| 568 | #define TCTL_IRQEN 0x0010 /* IRQ Enable */ | ||
| 569 | #define TCTL_OM 0x0020 /* Output Mode */ | ||
| 570 | #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ | ||
| 571 | #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ | ||
| 572 | #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ | ||
| 573 | #define TCTL_FRR 0x0010 /* Free-Run Mode */ | ||
| 574 | |||
| 575 | /* '328-compatible definitions */ | ||
| 576 | #define TCTL1_ADDR TCTL_ADDR | ||
| 577 | #define TCTL1 TCTL | ||
| 578 | |||
| 579 | /* | ||
| 580 | * Timer Prescaler Register | ||
| 581 | */ | ||
| 582 | #define TPRER_ADDR 0xfffff602 | ||
| 583 | #define TPRER WORD_REF(TPRER_ADDR) | ||
| 584 | |||
| 585 | /* '328-compatible definitions */ | ||
| 586 | #define TPRER1_ADDR TPRER_ADDR | ||
| 587 | #define TPRER1 TPRER | ||
| 588 | |||
| 589 | /* | ||
| 590 | * Timer Compare Register | ||
| 591 | */ | ||
| 592 | #define TCMP_ADDR 0xfffff604 | ||
| 593 | #define TCMP WORD_REF(TCMP_ADDR) | ||
| 594 | |||
| 595 | /* '328-compatible definitions */ | ||
| 596 | #define TCMP1_ADDR TCMP_ADDR | ||
| 597 | #define TCMP1 TCMP | ||
| 598 | |||
| 599 | /* | ||
| 600 | * Timer Capture register | ||
| 601 | */ | ||
| 602 | #define TCR_ADDR 0xfffff606 | ||
| 603 | #define TCR WORD_REF(TCR_ADDR) | ||
| 604 | |||
| 605 | /* '328-compatible definitions */ | ||
| 606 | #define TCR1_ADDR TCR_ADDR | ||
| 607 | #define TCR1 TCR | ||
| 608 | |||
| 609 | /* | ||
| 610 | * Timer Counter Register | ||
| 611 | */ | ||
| 612 | #define TCN_ADDR 0xfffff608 | ||
| 613 | #define TCN WORD_REF(TCN_ADDR) | ||
| 614 | |||
| 615 | /* '328-compatible definitions */ | ||
| 616 | #define TCN1_ADDR TCN_ADDR | ||
| 617 | #define TCN1 TCN | ||
| 618 | |||
| 619 | /* | ||
| 620 | * Timer Status Register | ||
| 621 | */ | ||
| 622 | #define TSTAT_ADDR 0xfffff60a | ||
| 623 | #define TSTAT WORD_REF(TSTAT_ADDR) | ||
| 624 | |||
| 625 | #define TSTAT_COMP 0x0001 /* Compare Event occurred */ | ||
| 626 | #define TSTAT_CAPT 0x0001 /* Capture Event occurred */ | ||
| 627 | |||
| 628 | /* '328-compatible definitions */ | ||
| 629 | #define TSTAT1_ADDR TSTAT_ADDR | ||
| 630 | #define TSTAT1 TSTAT | ||
| 631 | |||
| 632 | /********** | ||
| 633 | * | ||
| 634 | * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) | ||
| 635 | * | ||
| 636 | **********/ | ||
| 637 | |||
| 638 | /* | ||
| 639 | * SPIM Data Register | ||
| 640 | */ | ||
| 641 | #define SPIMDATA_ADDR 0xfffff800 | ||
| 642 | #define SPIMDATA WORD_REF(SPIMDATA_ADDR) | ||
| 643 | |||
| 644 | /* | ||
| 645 | * SPIM Control/Status Register | ||
| 646 | */ | ||
| 647 | #define SPIMCONT_ADDR 0xfffff802 | ||
| 648 | #define SPIMCONT WORD_REF(SPIMCONT_ADDR) | ||
| 649 | |||
| 650 | #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ | ||
| 651 | #define SPIMCONT_BIT_COUNT_SHIFT 0 | ||
| 652 | #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ | ||
| 653 | #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ | ||
| 654 | #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ | ||
| 655 | #define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ | ||
| 656 | #define SPIMCONT_XCH 0x0100 /* Exchange */ | ||
| 657 | #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ | ||
| 658 | #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ | ||
| 659 | #define SPIMCONT_DATA_RATE_SHIFT 13 | ||
| 660 | |||
| 661 | /* '328-compatible definitions */ | ||
| 662 | #define SPIMCONT_SPIMIRQ SPIMCONT_IRQ | ||
| 663 | #define SPIMCONT_SPIMEN SPIMCONT_ENABLE | ||
| 664 | |||
| 665 | /********** | ||
| 666 | * | ||
| 667 | * 0xFFFFF9xx -- UART | ||
| 668 | * | ||
| 669 | **********/ | ||
| 670 | |||
| 671 | /* | ||
| 672 | * UART Status/Control Register | ||
| 673 | */ | ||
| 674 | #define USTCNT_ADDR 0xfffff900 | ||
| 675 | #define USTCNT WORD_REF(USTCNT_ADDR) | ||
| 676 | |||
| 677 | #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ | ||
| 678 | #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ | ||
| 679 | #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ | ||
| 680 | #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ | ||
| 681 | #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ | ||
| 682 | #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ | ||
| 683 | #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ | ||
| 684 | #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ | ||
| 685 | #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ | ||
| 686 | #define USTCNT_STOP 0x0200 /* Stop bit transmission */ | ||
| 687 | #define USTCNT_ODD 0x0400 /* Odd Parity */ | ||
| 688 | #define USTCNT_PEN 0x0800 /* Parity Enable */ | ||
| 689 | #define USTCNT_CLKM 0x1000 /* Clock Mode Select */ | ||
| 690 | #define USTCNT_TXEN 0x2000 /* Transmitter Enable */ | ||
| 691 | #define USTCNT_RXEN 0x4000 /* Receiver Enable */ | ||
| 692 | #define USTCNT_UEN 0x8000 /* UART Enable */ | ||
| 693 | |||
| 694 | /* '328-compatible definitions */ | ||
| 695 | #define USTCNT_TXAVAILEN USTCNT_TXAE | ||
| 696 | #define USTCNT_TXHALFEN USTCNT_TXHE | ||
| 697 | #define USTCNT_TXEMPTYEN USTCNT_TXEE | ||
| 698 | #define USTCNT_RXREADYEN USTCNT_RXRE | ||
| 699 | #define USTCNT_RXHALFEN USTCNT_RXHE | ||
| 700 | #define USTCNT_RXFULLEN USTCNT_RXFE | ||
| 701 | #define USTCNT_CTSDELTAEN USTCNT_CTSD | ||
| 702 | #define USTCNT_ODD_EVEN USTCNT_ODD | ||
| 703 | #define USTCNT_PARITYEN USTCNT_PEN | ||
| 704 | #define USTCNT_CLKMODE USTCNT_CLKM | ||
| 705 | #define USTCNT_UARTEN USTCNT_UEN | ||
| 706 | |||
| 707 | /* | ||
| 708 | * UART Baud Control Register | ||
| 709 | */ | ||
| 710 | #define UBAUD_ADDR 0xfffff902 | ||
| 711 | #define UBAUD WORD_REF(UBAUD_ADDR) | ||
| 712 | |||
| 713 | #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ | ||
| 714 | #define UBAUD_PRESCALER_SHIFT 0 | ||
| 715 | #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ | ||
| 716 | #define UBAUD_DIVIDE_SHIFT 8 | ||
| 717 | #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ | ||
| 718 | #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ | ||
| 719 | |||
| 720 | /* | ||
| 721 | * UART Receiver Register | ||
| 722 | */ | ||
| 723 | #define URX_ADDR 0xfffff904 | ||
| 724 | #define URX WORD_REF(URX_ADDR) | ||
| 725 | |||
| 726 | #define URX_RXDATA_ADDR 0xfffff905 | ||
| 727 | #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) | ||
| 728 | |||
| 729 | #define URX_RXDATA_MASK 0x00ff /* Received data */ | ||
| 730 | #define URX_RXDATA_SHIFT 0 | ||
| 731 | #define URX_PARITY_ERROR 0x0100 /* Parity Error */ | ||
| 732 | #define URX_BREAK 0x0200 /* Break Detected */ | ||
| 733 | #define URX_FRAME_ERROR 0x0400 /* Framing Error */ | ||
| 734 | #define URX_OVRUN 0x0800 /* Serial Overrun */ | ||
| 735 | #define URX_OLD_DATA 0x1000 /* Old data in FIFO */ | ||
| 736 | #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ | ||
| 737 | #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ | ||
| 738 | #define URX_FIFO_FULL 0x8000 /* FIFO is Full */ | ||
| 739 | |||
| 740 | /* | ||
| 741 | * UART Transmitter Register | ||
| 742 | */ | ||
| 743 | #define UTX_ADDR 0xfffff906 | ||
| 744 | #define UTX WORD_REF(UTX_ADDR) | ||
| 745 | |||
| 746 | #define UTX_TXDATA_ADDR 0xfffff907 | ||
| 747 | #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) | ||
| 748 | |||
| 749 | #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ | ||
| 750 | #define UTX_TXDATA_SHIFT 0 | ||
| 751 | #define UTX_CTS_DELTA 0x0100 /* CTS changed */ | ||
| 752 | #define UTX_CTS_STAT 0x0200 /* CTS State */ | ||
| 753 | #define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ | ||
| 754 | #define UTX_NOCTS 0x0800 /* Ignore CTS */ | ||
| 755 | #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ | ||
| 756 | #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ | ||
| 757 | #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ | ||
| 758 | #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ | ||
| 759 | |||
| 760 | /* '328-compatible definitions */ | ||
| 761 | #define UTX_CTS_STATUS UTX_CTS_STAT | ||
| 762 | #define UTX_IGNORE_CTS UTX_NOCTS | ||
| 763 | |||
| 764 | /* | ||
| 765 | * UART Miscellaneous Register | ||
| 766 | */ | ||
| 767 | #define UMISC_ADDR 0xfffff908 | ||
| 768 | #define UMISC WORD_REF(UMISC_ADDR) | ||
| 769 | |||
| 770 | #define UMISC_TX_POL 0x0004 /* Transmit Polarity */ | ||
| 771 | #define UMISC_RX_POL 0x0008 /* Receive Polarity */ | ||
| 772 | #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ | ||
| 773 | #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ | ||
| 774 | #define UMISC_RTS 0x0040 /* Set RTS status */ | ||
| 775 | #define UMISC_RTSCONT 0x0080 /* Choose RTS control */ | ||
| 776 | #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ | ||
| 777 | #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ | ||
| 778 | #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ | ||
| 779 | #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ | ||
| 780 | #define UMISC_CLKSRC 0x4000 /* Clock Source */ | ||
| 781 | #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ | ||
| 782 | |||
| 783 | /* | ||
| 784 | * UART Non-integer Prescaler Register | ||
| 785 | */ | ||
| 786 | #define NIPR_ADDR 0xfffff90a | ||
| 787 | #define NIPR WORD_REF(NIPR_ADDR) | ||
| 788 | |||
| 789 | #define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ | ||
| 790 | #define NIPR_STEP_VALUE_SHIFT 0 | ||
| 791 | #define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ | ||
| 792 | #define NIPR_SELECT_SHIFT 8 | ||
| 793 | #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ | ||
| 794 | |||
| 795 | |||
| 796 | /* generalization of uart control registers to support multiple ports: */ | ||
| 797 | typedef volatile struct { | ||
| 798 | volatile unsigned short int ustcnt; | ||
| 799 | volatile unsigned short int ubaud; | ||
| 800 | union { | ||
| 801 | volatile unsigned short int w; | ||
| 802 | struct { | ||
| 803 | volatile unsigned char status; | ||
| 804 | volatile unsigned char rxdata; | ||
| 805 | } b; | ||
| 806 | } urx; | ||
| 807 | union { | ||
| 808 | volatile unsigned short int w; | ||
| 809 | struct { | ||
| 810 | volatile unsigned char status; | ||
| 811 | volatile unsigned char txdata; | ||
| 812 | } b; | ||
| 813 | } utx; | ||
| 814 | volatile unsigned short int umisc; | ||
| 815 | volatile unsigned short int nipr; | ||
| 816 | volatile unsigned short int pad1; | ||
| 817 | volatile unsigned short int pad2; | ||
| 818 | } __attribute__((packed)) m68328_uart; | ||
| 819 | |||
| 820 | |||
| 821 | /********** | ||
| 822 | * | ||
| 823 | * 0xFFFFFAxx -- LCD Controller | ||
| 824 | * | ||
| 825 | **********/ | ||
| 826 | |||
| 827 | /* | ||
| 828 | * LCD Screen Starting Address Register | ||
| 829 | */ | ||
| 830 | #define LSSA_ADDR 0xfffffa00 | ||
| 831 | #define LSSA LONG_REF(LSSA_ADDR) | ||
| 832 | |||
| 833 | #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ | ||
| 834 | |||
| 835 | /* | ||
| 836 | * LCD Virtual Page Width Register | ||
| 837 | */ | ||
| 838 | #define LVPW_ADDR 0xfffffa05 | ||
| 839 | #define LVPW BYTE_REF(LVPW_ADDR) | ||
| 840 | |||
| 841 | /* | ||
| 842 | * LCD Screen Width Register (not compatible with '328 !!!) | ||
| 843 | */ | ||
| 844 | #define LXMAX_ADDR 0xfffffa08 | ||
| 845 | #define LXMAX WORD_REF(LXMAX_ADDR) | ||
| 846 | |||
| 847 | #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ | ||
| 848 | |||
| 849 | /* | ||
| 850 | * LCD Screen Height Register | ||
| 851 | */ | ||
| 852 | #define LYMAX_ADDR 0xfffffa0a | ||
| 853 | #define LYMAX WORD_REF(LYMAX_ADDR) | ||
| 854 | |||
| 855 | #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ | ||
| 856 | |||
| 857 | /* | ||
| 858 | * LCD Cursor X Position Register | ||
| 859 | */ | ||
| 860 | #define LCXP_ADDR 0xfffffa18 | ||
| 861 | #define LCXP WORD_REF(LCXP_ADDR) | ||
| 862 | |||
| 863 | #define LCXP_CC_MASK 0xc000 /* Cursor Control */ | ||
| 864 | #define LCXP_CC_TRAMSPARENT 0x0000 | ||
| 865 | #define LCXP_CC_BLACK 0x4000 | ||
| 866 | #define LCXP_CC_REVERSED 0x8000 | ||
| 867 | #define LCXP_CC_WHITE 0xc000 | ||
| 868 | #define LCXP_CXP_MASK 0x02ff /* Cursor X position */ | ||
| 869 | |||
| 870 | /* | ||
| 871 | * LCD Cursor Y Position Register | ||
| 872 | */ | ||
| 873 | #define LCYP_ADDR 0xfffffa1a | ||
| 874 | #define LCYP WORD_REF(LCYP_ADDR) | ||
| 875 | |||
| 876 | #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ | ||
| 877 | |||
| 878 | /* | ||
| 879 | * LCD Cursor Width and Heigth Register | ||
| 880 | */ | ||
| 881 | #define LCWCH_ADDR 0xfffffa1c | ||
| 882 | #define LCWCH WORD_REF(LCWCH_ADDR) | ||
| 883 | |||
| 884 | #define LCWCH_CH_MASK 0x001f /* Cursor Height */ | ||
| 885 | #define LCWCH_CH_SHIFT 0 | ||
| 886 | #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ | ||
| 887 | #define LCWCH_CW_SHIFT 8 | ||
| 888 | |||
| 889 | /* | ||
| 890 | * LCD Blink Control Register | ||
| 891 | */ | ||
| 892 | #define LBLKC_ADDR 0xfffffa1f | ||
| 893 | #define LBLKC BYTE_REF(LBLKC_ADDR) | ||
| 894 | |||
| 895 | #define LBLKC_BD_MASK 0x7f /* Blink Divisor */ | ||
| 896 | #define LBLKC_BD_SHIFT 0 | ||
| 897 | #define LBLKC_BKEN 0x80 /* Blink Enabled */ | ||
| 898 | |||
| 899 | /* | ||
| 900 | * LCD Panel Interface Configuration Register | ||
| 901 | */ | ||
| 902 | #define LPICF_ADDR 0xfffffa20 | ||
| 903 | #define LPICF BYTE_REF(LPICF_ADDR) | ||
| 904 | |||
| 905 | #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ | ||
| 906 | #define LPICF_GS_BW 0x00 | ||
| 907 | #define LPICF_GS_GRAY_4 0x01 | ||
| 908 | #define LPICF_GS_GRAY_16 0x02 | ||
| 909 | #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ | ||
| 910 | #define LPICF_PBSIZ_1 0x00 | ||
| 911 | #define LPICF_PBSIZ_2 0x04 | ||
| 912 | #define LPICF_PBSIZ_4 0x08 | ||
| 913 | |||
| 914 | /* | ||
| 915 | * LCD Polarity Configuration Register | ||
| 916 | */ | ||
| 917 | #define LPOLCF_ADDR 0xfffffa21 | ||
| 918 | #define LPOLCF BYTE_REF(LPOLCF_ADDR) | ||
| 919 | |||
| 920 | #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ | ||
| 921 | #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ | ||
| 922 | #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ | ||
| 923 | #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ | ||
| 924 | |||
| 925 | /* | ||
| 926 | * LACD (LCD Alternate Crystal Direction) Rate Control Register | ||
| 927 | */ | ||
| 928 | #define LACDRC_ADDR 0xfffffa23 | ||
| 929 | #define LACDRC BYTE_REF(LACDRC_ADDR) | ||
| 930 | |||
| 931 | #define LACDRC_ACDSLT 0x80 /* Signal Source Select */ | ||
| 932 | #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ | ||
| 933 | #define LACDRC_ACD_SHIFT 0 | ||
| 934 | |||
| 935 | /* | ||
| 936 | * LCD Pixel Clock Divider Register | ||
| 937 | */ | ||
| 938 | #define LPXCD_ADDR 0xfffffa25 | ||
| 939 | #define LPXCD BYTE_REF(LPXCD_ADDR) | ||
| 940 | |||
| 941 | #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ | ||
| 942 | #define LPXCD_PCD_SHIFT 0 | ||
| 943 | |||
| 944 | /* | ||
| 945 | * LCD Clocking Control Register | ||
| 946 | */ | ||
| 947 | #define LCKCON_ADDR 0xfffffa27 | ||
| 948 | #define LCKCON BYTE_REF(LCKCON_ADDR) | ||
| 949 | |||
| 950 | #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ | ||
| 951 | #define LCKCON_DWS_SHIFT 0 | ||
| 952 | #define LCKCON_DWIDTH 0x40 /* Display Memory Width */ | ||
| 953 | #define LCKCON_LCDON 0x80 /* Enable LCD Controller */ | ||
| 954 | |||
| 955 | /* '328-compatible definitions */ | ||
| 956 | #define LCKCON_DW_MASK LCKCON_DWS_MASK | ||
| 957 | #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT | ||
| 958 | |||
| 959 | /* | ||
| 960 | * LCD Refresh Rate Adjustment Register | ||
| 961 | */ | ||
| 962 | #define LRRA_ADDR 0xfffffa29 | ||
| 963 | #define LRRA BYTE_REF(LRRA_ADDR) | ||
| 964 | |||
| 965 | /* | ||
| 966 | * LCD Panning Offset Register | ||
| 967 | */ | ||
| 968 | #define LPOSR_ADDR 0xfffffa2d | ||
| 969 | #define LPOSR BYTE_REF(LPOSR_ADDR) | ||
| 970 | |||
| 971 | #define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ | ||
| 972 | #define LPOSR_POS_SHIFT 0 | ||
| 973 | |||
| 974 | /* | ||
| 975 | * LCD Frame Rate Control Modulation Register | ||
| 976 | */ | ||
| 977 | #define LFRCM_ADDR 0xfffffa31 | ||
| 978 | #define LFRCM BYTE_REF(LFRCM_ADDR) | ||
| 979 | |||
| 980 | #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ | ||
| 981 | #define LFRCM_YMOD_SHIFT 0 | ||
| 982 | #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ | ||
| 983 | #define LFRCM_XMOD_SHIFT 4 | ||
| 984 | |||
| 985 | /* | ||
| 986 | * LCD Gray Palette Mapping Register | ||
| 987 | */ | ||
| 988 | #define LGPMR_ADDR 0xfffffa33 | ||
| 989 | #define LGPMR BYTE_REF(LGPMR_ADDR) | ||
| 990 | |||
| 991 | #define LGPMR_G1_MASK 0x0f | ||
| 992 | #define LGPMR_G1_SHIFT 0 | ||
| 993 | #define LGPMR_G2_MASK 0xf0 | ||
| 994 | #define LGPMR_G2_SHIFT 4 | ||
| 995 | |||
| 996 | /* | ||
| 997 | * PWM Contrast Control Register | ||
| 998 | */ | ||
| 999 | #define PWMR_ADDR 0xfffffa36 | ||
| 1000 | #define PWMR WORD_REF(PWMR_ADDR) | ||
| 1001 | |||
| 1002 | #define PWMR_PW_MASK 0x00ff /* Pulse Width */ | ||
| 1003 | #define PWMR_PW_SHIFT 0 | ||
| 1004 | #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ | ||
| 1005 | #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ | ||
| 1006 | #define PWMR_SRC_LINE 0x0000 /* Line Pulse */ | ||
| 1007 | #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ | ||
| 1008 | #define PWMR_SRC_LCD 0x4000 /* LCD clock */ | ||
| 1009 | |||
| 1010 | /********** | ||
| 1011 | * | ||
| 1012 | * 0xFFFFFBxx -- Real-Time Clock (RTC) | ||
| 1013 | * | ||
| 1014 | **********/ | ||
| 1015 | |||
| 1016 | /* | ||
| 1017 | * RTC Hours Minutes and Seconds Register | ||
| 1018 | */ | ||
| 1019 | #define RTCTIME_ADDR 0xfffffb00 | ||
| 1020 | #define RTCTIME LONG_REF(RTCTIME_ADDR) | ||
| 1021 | |||
| 1022 | #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ | ||
| 1023 | #define RTCTIME_SECONDS_SHIFT 0 | ||
| 1024 | #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ | ||
| 1025 | #define RTCTIME_MINUTES_SHIFT 16 | ||
| 1026 | #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ | ||
| 1027 | #define RTCTIME_HOURS_SHIFT 24 | ||
| 1028 | |||
| 1029 | /* | ||
| 1030 | * RTC Alarm Register | ||
| 1031 | */ | ||
| 1032 | #define RTCALRM_ADDR 0xfffffb04 | ||
| 1033 | #define RTCALRM LONG_REF(RTCALRM_ADDR) | ||
| 1034 | |||
| 1035 | #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ | ||
| 1036 | #define RTCALRM_SECONDS_SHIFT 0 | ||
| 1037 | #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ | ||
| 1038 | #define RTCALRM_MINUTES_SHIFT 16 | ||
| 1039 | #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ | ||
| 1040 | #define RTCALRM_HOURS_SHIFT 24 | ||
| 1041 | |||
| 1042 | /* | ||
| 1043 | * Watchdog Timer Register | ||
| 1044 | */ | ||
| 1045 | #define WATCHDOG_ADDR 0xfffffb0a | ||
| 1046 | #define WATCHDOG WORD_REF(WATCHDOG_ADDR) | ||
| 1047 | |||
| 1048 | #define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ | ||
| 1049 | #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ | ||
| 1050 | #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */ | ||
| 1051 | #define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ | ||
| 1052 | #define WATCHDOG_CNT_SHIFT 8 | ||
| 1053 | |||
| 1054 | /* | ||
| 1055 | * RTC Control Register | ||
| 1056 | */ | ||
| 1057 | #define RTCCTL_ADDR 0xfffffb0c | ||
| 1058 | #define RTCCTL WORD_REF(RTCCTL_ADDR) | ||
| 1059 | |||
| 1060 | #define RTCCTL_XTL 0x0020 /* Crystal Selection */ | ||
| 1061 | #define RTCCTL_EN 0x0080 /* RTC Enable */ | ||
| 1062 | |||
| 1063 | /* '328-compatible definitions */ | ||
| 1064 | #define RTCCTL_384 RTCCTL_XTL | ||
| 1065 | #define RTCCTL_ENABLE RTCCTL_EN | ||
| 1066 | |||
| 1067 | /* | ||
| 1068 | * RTC Interrupt Status Register | ||
| 1069 | */ | ||
| 1070 | #define RTCISR_ADDR 0xfffffb0e | ||
| 1071 | #define RTCISR WORD_REF(RTCISR_ADDR) | ||
| 1072 | |||
| 1073 | #define RTCISR_SW 0x0001 /* Stopwatch timed out */ | ||
| 1074 | #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ | ||
| 1075 | #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ | ||
| 1076 | #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ | ||
| 1077 | #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ | ||
| 1078 | #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ | ||
| 1079 | #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ | ||
| 1080 | #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ | ||
| 1081 | #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ | ||
| 1082 | #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ | ||
| 1083 | #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ | ||
| 1084 | #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ | ||
| 1085 | #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ | ||
| 1086 | #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ | ||
| 1087 | |||
| 1088 | /* | ||
| 1089 | * RTC Interrupt Enable Register | ||
| 1090 | */ | ||
| 1091 | #define RTCIENR_ADDR 0xfffffb10 | ||
| 1092 | #define RTCIENR WORD_REF(RTCIENR_ADDR) | ||
| 1093 | |||
| 1094 | #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ | ||
| 1095 | #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ | ||
| 1096 | #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ | ||
| 1097 | #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ | ||
| 1098 | #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ | ||
| 1099 | #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ | ||
| 1100 | #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ | ||
| 1101 | #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ | ||
| 1102 | #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ | ||
| 1103 | #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ | ||
| 1104 | #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ | ||
| 1105 | #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ | ||
| 1106 | #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ | ||
| 1107 | #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ | ||
| 1108 | |||
| 1109 | /* | ||
| 1110 | * Stopwatch Minutes Register | ||
| 1111 | */ | ||
| 1112 | #define STPWCH_ADDR 0xfffffb12 | ||
| 1113 | #define STPWCH WORD_REF(STPWCH) | ||
| 1114 | |||
| 1115 | #define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ | ||
| 1116 | #define SPTWCH_CNT_SHIFT 0 | ||
| 1117 | |||
| 1118 | /* | ||
| 1119 | * RTC Day Count Register | ||
| 1120 | */ | ||
| 1121 | #define DAYR_ADDR 0xfffffb1a | ||
| 1122 | #define DAYR WORD_REF(DAYR_ADDR) | ||
| 1123 | |||
| 1124 | #define DAYR_DAYS_MASK 0x1ff /* Day Setting */ | ||
| 1125 | #define DAYR_DAYS_SHIFT 0 | ||
| 1126 | |||
| 1127 | /* | ||
| 1128 | * RTC Day Alarm Register | ||
| 1129 | */ | ||
| 1130 | #define DAYALARM_ADDR 0xfffffb1c | ||
| 1131 | #define DAYALARM WORD_REF(DAYALARM_ADDR) | ||
| 1132 | |||
| 1133 | #define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ | ||
| 1134 | #define DAYALARM_DAYSAL_SHIFT 0 | ||
| 1135 | |||
| 1136 | /********** | ||
| 1137 | * | ||
| 1138 | * 0xFFFFFCxx -- DRAM Controller | ||
| 1139 | * | ||
| 1140 | **********/ | ||
| 1141 | |||
| 1142 | /* | ||
| 1143 | * DRAM Memory Configuration Register | ||
| 1144 | */ | ||
| 1145 | #define DRAMMC_ADDR 0xfffffc00 | ||
| 1146 | #define DRAMMC WORD_REF(DRAMMC_ADDR) | ||
| 1147 | |||
| 1148 | #define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ | ||
| 1149 | #define DRAMMC_ROW12_PA10 0x0000 | ||
| 1150 | #define DRAMMC_ROW12_PA21 0x4000 | ||
| 1151 | #define DRAMMC_ROW12_PA23 0x8000 | ||
| 1152 | #define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ | ||
| 1153 | #define DRAMMC_ROW0_PA11 0x0000 | ||
| 1154 | #define DRAMMC_ROW0_PA22 0x1000 | ||
| 1155 | #define DRAMMC_ROW0_PA23 0x2000 | ||
| 1156 | #define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ | ||
| 1157 | #define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ | ||
| 1158 | #define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ | ||
| 1159 | #define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ | ||
| 1160 | #define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ | ||
| 1161 | #define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ | ||
| 1162 | #define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ | ||
| 1163 | #define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ | ||
| 1164 | #define DRAMMC_REF_SHIFT 0 | ||
| 1165 | |||
| 1166 | /* | ||
| 1167 | * DRAM Control Register | ||
| 1168 | */ | ||
| 1169 | #define DRAMC_ADDR 0xfffffc02 | ||
| 1170 | #define DRAMC WORD_REF(DRAMC_ADDR) | ||
| 1171 | |||
| 1172 | #define DRAMC_DWE 0x0001 /* DRAM Write Enable */ | ||
| 1173 | #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ | ||
| 1174 | #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ | ||
| 1175 | #define DRAMC_SLW 0x0008 /* Slow RAM */ | ||
| 1176 | #define DRAMC_LSP 0x0010 /* Light Sleep */ | ||
| 1177 | #define DRAMC_MSW 0x0020 /* Slow Multiplexing */ | ||
| 1178 | #define DRAMC_WS_MASK 0x00c0 /* Wait-states */ | ||
| 1179 | #define DRAMC_WS_SHIFT 6 | ||
| 1180 | #define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ | ||
| 1181 | #define DRAMC_PGSZ_SHIFT 8 | ||
| 1182 | #define DRAMC_PGSZ_256K 0x0000 | ||
| 1183 | #define DRAMC_PGSZ_512K 0x0100 | ||
| 1184 | #define DRAMC_PGSZ_1024K 0x0200 | ||
| 1185 | #define DRAMC_PGSZ_2048K 0x0300 | ||
| 1186 | #define DRAMC_EDO 0x0400 /* EDO DRAM */ | ||
| 1187 | #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ | ||
| 1188 | #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ | ||
| 1189 | #define DRAMC_BC_SHIFT 12 | ||
| 1190 | #define DRAMC_RM 0x4000 /* Refresh Mode */ | ||
| 1191 | #define DRAMC_EN 0x8000 /* DRAM Controller enable */ | ||
| 1192 | |||
| 1193 | |||
| 1194 | /********** | ||
| 1195 | * | ||
| 1196 | * 0xFFFFFDxx -- In-Circuit Emulation (ICE) | ||
| 1197 | * | ||
| 1198 | **********/ | ||
| 1199 | |||
| 1200 | /* | ||
| 1201 | * ICE Module Address Compare Register | ||
| 1202 | */ | ||
| 1203 | #define ICEMACR_ADDR 0xfffffd00 | ||
| 1204 | #define ICEMACR LONG_REF(ICEMACR_ADDR) | ||
| 1205 | |||
| 1206 | /* | ||
| 1207 | * ICE Module Address Mask Register | ||
| 1208 | */ | ||
| 1209 | #define ICEMAMR_ADDR 0xfffffd04 | ||
| 1210 | #define ICEMAMR LONG_REF(ICEMAMR_ADDR) | ||
| 1211 | |||
| 1212 | /* | ||
| 1213 | * ICE Module Control Compare Register | ||
| 1214 | */ | ||
| 1215 | #define ICEMCCR_ADDR 0xfffffd08 | ||
| 1216 | #define ICEMCCR WORD_REF(ICEMCCR_ADDR) | ||
| 1217 | |||
| 1218 | #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ | ||
| 1219 | #define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ | ||
| 1220 | |||
| 1221 | /* | ||
| 1222 | * ICE Module Control Mask Register | ||
| 1223 | */ | ||
| 1224 | #define ICEMCMR_ADDR 0xfffffd0a | ||
| 1225 | #define ICEMCMR WORD_REF(ICEMCMR_ADDR) | ||
| 1226 | |||
| 1227 | #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ | ||
| 1228 | #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ | ||
| 1229 | |||
| 1230 | /* | ||
| 1231 | * ICE Module Control Register | ||
| 1232 | */ | ||
| 1233 | #define ICEMCR_ADDR 0xfffffd0c | ||
| 1234 | #define ICEMCR WORD_REF(ICEMCR_ADDR) | ||
| 1235 | |||
| 1236 | #define ICEMCR_CEN 0x0001 /* Compare Enable */ | ||
| 1237 | #define ICEMCR_PBEN 0x0002 /* Program Break Enable */ | ||
| 1238 | #define ICEMCR_SB 0x0004 /* Single Breakpoint */ | ||
| 1239 | #define ICEMCR_HMDIS 0x0008 /* HardMap disable */ | ||
| 1240 | #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ | ||
| 1241 | |||
| 1242 | /* | ||
| 1243 | * ICE Module Status Register | ||
| 1244 | */ | ||
| 1245 | #define ICEMSR_ADDR 0xfffffd0e | ||
| 1246 | #define ICEMSR WORD_REF(ICEMSR_ADDR) | ||
| 1247 | |||
| 1248 | #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ | ||
| 1249 | #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ | ||
| 1250 | #define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ | ||
| 1251 | #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ | ||
| 1252 | |||
| 1253 | #endif /* _MC68EZ328_H_ */ | ||
diff --git a/arch/m68k/include/asm/MC68VZ328.h b/arch/m68k/include/asm/MC68VZ328.h new file mode 100644 index 000000000000..2b9bf626a0a5 --- /dev/null +++ b/arch/m68k/include/asm/MC68VZ328.h | |||
| @@ -0,0 +1,1349 @@ | |||
| 1 | |||
| 2 | /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers | ||
| 3 | * | ||
| 4 | * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com> | ||
| 5 | * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca> | ||
| 6 | * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> | ||
| 7 | * Bare & Hare Software, Inc. | ||
| 8 | * Based on include/asm-m68knommu/MC68332.h | ||
| 9 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, | ||
| 10 | * The Silver Hammer Group, Ltd. | ||
| 11 | * | ||
| 12 | * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com> | ||
| 13 | * vz multiport fixes by Michael Leslie <mleslie@lineo.com> | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _MC68VZ328_H_ | ||
| 17 | #define _MC68VZ328_H_ | ||
| 18 | |||
| 19 | #define BYTE_REF(addr) (*((volatile unsigned char*)addr)) | ||
| 20 | #define WORD_REF(addr) (*((volatile unsigned short*)addr)) | ||
| 21 | #define LONG_REF(addr) (*((volatile unsigned long*)addr)) | ||
| 22 | |||
| 23 | #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) | ||
| 24 | #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) | ||
| 25 | |||
| 26 | /********** | ||
| 27 | * | ||
| 28 | * 0xFFFFF0xx -- System Control | ||
| 29 | * | ||
| 30 | **********/ | ||
| 31 | |||
| 32 | /* | ||
| 33 | * System Control Register (SCR) | ||
| 34 | */ | ||
| 35 | #define SCR_ADDR 0xfffff000 | ||
| 36 | #define SCR BYTE_REF(SCR_ADDR) | ||
| 37 | |||
| 38 | #define SCR_WDTH8 0x01 /* 8-Bit Width Select */ | ||
| 39 | #define SCR_DMAP 0x04 /* Double Map */ | ||
| 40 | #define SCR_SO 0x08 /* Supervisor Only */ | ||
| 41 | #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ | ||
| 42 | #define SCR_PRV 0x20 /* Privilege Violation */ | ||
| 43 | #define SCR_WPV 0x40 /* Write Protect Violation */ | ||
| 44 | #define SCR_BETO 0x80 /* Bus-Error TimeOut */ | ||
| 45 | |||
| 46 | /* | ||
| 47 | * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) | ||
| 48 | */ | ||
| 49 | #define MRR_ADDR 0xfffff004 | ||
| 50 | #define MRR LONG_REF(MRR_ADDR) | ||
| 51 | |||
| 52 | /********** | ||
| 53 | * | ||
| 54 | * 0xFFFFF1xx -- Chip-Select logic | ||
| 55 | * | ||
| 56 | **********/ | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Chip Select Group Base Registers | ||
| 60 | */ | ||
| 61 | #define CSGBA_ADDR 0xfffff100 | ||
| 62 | #define CSGBB_ADDR 0xfffff102 | ||
| 63 | |||
| 64 | #define CSGBC_ADDR 0xfffff104 | ||
| 65 | #define CSGBD_ADDR 0xfffff106 | ||
| 66 | |||
| 67 | #define CSGBA WORD_REF(CSGBA_ADDR) | ||
| 68 | #define CSGBB WORD_REF(CSGBB_ADDR) | ||
| 69 | #define CSGBC WORD_REF(CSGBC_ADDR) | ||
| 70 | #define CSGBD WORD_REF(CSGBD_ADDR) | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Chip Select Registers | ||
| 74 | */ | ||
| 75 | #define CSA_ADDR 0xfffff110 | ||
| 76 | #define CSB_ADDR 0xfffff112 | ||
| 77 | #define CSC_ADDR 0xfffff114 | ||
| 78 | #define CSD_ADDR 0xfffff116 | ||
| 79 | |||
| 80 | #define CSA WORD_REF(CSA_ADDR) | ||
| 81 | #define CSB WORD_REF(CSB_ADDR) | ||
| 82 | #define CSC WORD_REF(CSC_ADDR) | ||
| 83 | #define CSD WORD_REF(CSD_ADDR) | ||
| 84 | |||
| 85 | #define CSA_EN 0x0001 /* Chip-Select Enable */ | ||
| 86 | #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 87 | #define CSA_SIZ_SHIFT 1 | ||
| 88 | #define CSA_WS_MASK 0x0070 /* Wait State */ | ||
| 89 | #define CSA_WS_SHIFT 4 | ||
| 90 | #define CSA_BSW 0x0080 /* Data Bus Width */ | ||
| 91 | #define CSA_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 92 | #define CSA_RO 0x8000 /* Read-Only */ | ||
| 93 | |||
| 94 | #define CSB_EN 0x0001 /* Chip-Select Enable */ | ||
| 95 | #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 96 | #define CSB_SIZ_SHIFT 1 | ||
| 97 | #define CSB_WS_MASK 0x0070 /* Wait State */ | ||
| 98 | #define CSB_WS_SHIFT 4 | ||
| 99 | #define CSB_BSW 0x0080 /* Data Bus Width */ | ||
| 100 | #define CSB_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 101 | #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | ||
| 102 | #define CSB_UPSIZ_SHIFT 11 | ||
| 103 | #define CSB_ROP 0x2000 /* Readonly if protected */ | ||
| 104 | #define CSB_SOP 0x4000 /* Supervisor only if protected */ | ||
| 105 | #define CSB_RO 0x8000 /* Read-Only */ | ||
| 106 | |||
| 107 | #define CSC_EN 0x0001 /* Chip-Select Enable */ | ||
| 108 | #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 109 | #define CSC_SIZ_SHIFT 1 | ||
| 110 | #define CSC_WS_MASK 0x0070 /* Wait State */ | ||
| 111 | #define CSC_WS_SHIFT 4 | ||
| 112 | #define CSC_BSW 0x0080 /* Data Bus Width */ | ||
| 113 | #define CSC_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 114 | #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | ||
| 115 | #define CSC_UPSIZ_SHIFT 11 | ||
| 116 | #define CSC_ROP 0x2000 /* Readonly if protected */ | ||
| 117 | #define CSC_SOP 0x4000 /* Supervisor only if protected */ | ||
| 118 | #define CSC_RO 0x8000 /* Read-Only */ | ||
| 119 | |||
| 120 | #define CSD_EN 0x0001 /* Chip-Select Enable */ | ||
| 121 | #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ | ||
| 122 | #define CSD_SIZ_SHIFT 1 | ||
| 123 | #define CSD_WS_MASK 0x0070 /* Wait State */ | ||
| 124 | #define CSD_WS_SHIFT 4 | ||
| 125 | #define CSD_BSW 0x0080 /* Data Bus Width */ | ||
| 126 | #define CSD_FLASH 0x0100 /* FLASH Memory Support */ | ||
| 127 | #define CSD_DRAM 0x0200 /* Dram Selection */ | ||
| 128 | #define CSD_COMB 0x0400 /* Combining */ | ||
| 129 | #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ | ||
| 130 | #define CSD_UPSIZ_SHIFT 11 | ||
| 131 | #define CSD_ROP 0x2000 /* Readonly if protected */ | ||
| 132 | #define CSD_SOP 0x4000 /* Supervisor only if protected */ | ||
| 133 | #define CSD_RO 0x8000 /* Read-Only */ | ||
| 134 | |||
| 135 | /* | ||
| 136 | * Emulation Chip-Select Register | ||
| 137 | */ | ||
| 138 | #define EMUCS_ADDR 0xfffff118 | ||
| 139 | #define EMUCS WORD_REF(EMUCS_ADDR) | ||
| 140 | |||
| 141 | #define EMUCS_WS_MASK 0x0070 | ||
| 142 | #define EMUCS_WS_SHIFT 4 | ||
| 143 | |||
| 144 | /********** | ||
| 145 | * | ||
| 146 | * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control | ||
| 147 | * | ||
| 148 | **********/ | ||
| 149 | |||
| 150 | /* | ||
| 151 | * PLL Control Register | ||
| 152 | */ | ||
| 153 | #define PLLCR_ADDR 0xfffff200 | ||
| 154 | #define PLLCR WORD_REF(PLLCR_ADDR) | ||
| 155 | |||
| 156 | #define PLLCR_DISPLL 0x0008 /* Disable PLL */ | ||
| 157 | #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ | ||
| 158 | #define PLLCR_PRESC 0x0020 /* VCO prescaler */ | ||
| 159 | #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ | ||
| 160 | #define PLLCR_SYSCLK_SEL_SHIFT 8 | ||
| 161 | #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ | ||
| 162 | #define PLLCR_LCDCLK_SEL_SHIFT 11 | ||
| 163 | |||
| 164 | /* '328-compatible definitions */ | ||
| 165 | #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK | ||
| 166 | #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT | ||
| 167 | |||
| 168 | /* | ||
| 169 | * PLL Frequency Select Register | ||
| 170 | */ | ||
| 171 | #define PLLFSR_ADDR 0xfffff202 | ||
| 172 | #define PLLFSR WORD_REF(PLLFSR_ADDR) | ||
| 173 | |||
| 174 | #define PLLFSR_PC_MASK 0x00ff /* P Count */ | ||
| 175 | #define PLLFSR_PC_SHIFT 0 | ||
| 176 | #define PLLFSR_QC_MASK 0x0f00 /* Q Count */ | ||
| 177 | #define PLLFSR_QC_SHIFT 8 | ||
| 178 | #define PLLFSR_PROT 0x4000 /* Protect P & Q */ | ||
| 179 | #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ | ||
| 180 | |||
| 181 | /* | ||
| 182 | * Power Control Register | ||
| 183 | */ | ||
| 184 | #define PCTRL_ADDR 0xfffff207 | ||
| 185 | #define PCTRL BYTE_REF(PCTRL_ADDR) | ||
| 186 | |||
| 187 | #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ | ||
| 188 | #define PCTRL_WIDTH_SHIFT 0 | ||
| 189 | #define PCTRL_PCEN 0x80 /* Power Control Enable */ | ||
| 190 | |||
| 191 | /********** | ||
| 192 | * | ||
| 193 | * 0xFFFFF3xx -- Interrupt Controller | ||
| 194 | * | ||
| 195 | **********/ | ||
| 196 | |||
| 197 | /* | ||
| 198 | * Interrupt Vector Register | ||
| 199 | */ | ||
| 200 | #define IVR_ADDR 0xfffff300 | ||
| 201 | #define IVR BYTE_REF(IVR_ADDR) | ||
| 202 | |||
| 203 | #define IVR_VECTOR_MASK 0xF8 | ||
| 204 | |||
| 205 | /* | ||
| 206 | * Interrupt control Register | ||
| 207 | */ | ||
| 208 | #define ICR_ADDR 0xfffff302 | ||
| 209 | #define ICR WORD_REF(ICR_ADDR) | ||
| 210 | |||
| 211 | #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ | ||
| 212 | #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ | ||
| 213 | #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ | ||
| 214 | #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ | ||
| 215 | #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ | ||
| 216 | #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ | ||
| 217 | #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ | ||
| 218 | #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ | ||
| 219 | #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ | ||
| 220 | |||
| 221 | /* | ||
| 222 | * Interrupt Mask Register | ||
| 223 | */ | ||
| 224 | #define IMR_ADDR 0xfffff304 | ||
| 225 | #define IMR LONG_REF(IMR_ADDR) | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Define the names for bit positions first. This is useful for | ||
| 229 | * request_irq | ||
| 230 | */ | ||
| 231 | #define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */ | ||
| 232 | #define TMR_IRQ_NUM 1 /* Timer 1 interrupt */ | ||
| 233 | #define UART1_IRQ_NUM 2 /* UART 1 interrupt */ | ||
| 234 | #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ | ||
| 235 | #define RTC_IRQ_NUM 4 /* RTC interrupt */ | ||
| 236 | #define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */ | ||
| 237 | #define KB_IRQ_NUM 6 /* Keyboard Interrupt */ | ||
| 238 | #define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */ | ||
| 239 | #define INT0_IRQ_NUM 8 /* External INT0 */ | ||
| 240 | #define INT1_IRQ_NUM 9 /* External INT1 */ | ||
| 241 | #define INT2_IRQ_NUM 10 /* External INT2 */ | ||
| 242 | #define INT3_IRQ_NUM 11 /* External INT3 */ | ||
| 243 | #define UART2_IRQ_NUM 12 /* UART 2 interrupt */ | ||
| 244 | #define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */ | ||
| 245 | #define IRQ1_IRQ_NUM 16 /* IRQ1 */ | ||
| 246 | #define IRQ2_IRQ_NUM 17 /* IRQ2 */ | ||
| 247 | #define IRQ3_IRQ_NUM 18 /* IRQ3 */ | ||
| 248 | #define IRQ6_IRQ_NUM 19 /* IRQ6 */ | ||
| 249 | #define IRQ5_IRQ_NUM 20 /* IRQ5 */ | ||
| 250 | #define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */ | ||
| 251 | #define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ | ||
| 252 | #define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ | ||
| 253 | |||
| 254 | #define SPI_IRQ_NUM SPI2_IRQ_NUM | ||
| 255 | |||
| 256 | /* '328-compatible definitions */ | ||
| 257 | #define SPIM_IRQ_NUM SPI_IRQ_NUM | ||
| 258 | #define TMR1_IRQ_NUM TMR_IRQ_NUM | ||
| 259 | #define UART_IRQ_NUM UART1_IRQ_NUM | ||
| 260 | |||
| 261 | /* | ||
| 262 | * Here go the bitmasks themselves | ||
| 263 | */ | ||
| 264 | #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ | ||
| 265 | #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ | ||
| 266 | #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ | ||
| 267 | #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ | ||
| 268 | #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ | ||
| 269 | #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ | ||
| 270 | #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ | ||
| 271 | #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ | ||
| 272 | #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ | ||
| 273 | #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ | ||
| 274 | #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ | ||
| 275 | #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ | ||
| 276 | #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ | ||
| 277 | #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ | ||
| 278 | #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ | ||
| 279 | #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ | ||
| 280 | #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ | ||
| 281 | #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ | ||
| 282 | |||
| 283 | /* '328-compatible definitions */ | ||
| 284 | #define IMR_MSPIM IMR_MSPI | ||
| 285 | #define IMR_MTMR1 IMR_MTMR | ||
| 286 | |||
| 287 | /* | ||
| 288 | * Interrupt Status Register | ||
| 289 | */ | ||
| 290 | #define ISR_ADDR 0xfffff30c | ||
| 291 | #define ISR LONG_REF(ISR_ADDR) | ||
| 292 | |||
| 293 | #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ | ||
| 294 | #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ | ||
| 295 | #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | ||
| 296 | #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | ||
| 297 | #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | ||
| 298 | #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | ||
| 299 | #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ | ||
| 300 | #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | ||
| 301 | #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | ||
| 302 | #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | ||
| 303 | #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | ||
| 304 | #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | ||
| 305 | #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | ||
| 306 | #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | ||
| 307 | #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | ||
| 308 | #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ | ||
| 309 | #define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ | ||
| 310 | #define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ | ||
| 311 | |||
| 312 | /* '328-compatible definitions */ | ||
| 313 | #define ISR_SPIM ISR_SPI | ||
| 314 | #define ISR_TMR1 ISR_TMR | ||
| 315 | |||
| 316 | /* | ||
| 317 | * Interrupt Pending Register | ||
| 318 | */ | ||
| 319 | #define IPR_ADDR 0xfffff30c | ||
| 320 | #define IPR LONG_REF(IPR_ADDR) | ||
| 321 | |||
| 322 | #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ | ||
| 323 | #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ | ||
| 324 | #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ | ||
| 325 | #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ | ||
| 326 | #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ | ||
| 327 | #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ | ||
| 328 | #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ | ||
| 329 | #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ | ||
| 330 | #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ | ||
| 331 | #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ | ||
| 332 | #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ | ||
| 333 | #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ | ||
| 334 | #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ | ||
| 335 | #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ | ||
| 336 | #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ | ||
| 337 | #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ | ||
| 338 | #define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ | ||
| 339 | #define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ | ||
| 340 | |||
| 341 | /* '328-compatible definitions */ | ||
| 342 | #define IPR_SPIM IPR_SPI | ||
| 343 | #define IPR_TMR1 IPR_TMR | ||
| 344 | |||
| 345 | /********** | ||
| 346 | * | ||
| 347 | * 0xFFFFF4xx -- Parallel Ports | ||
| 348 | * | ||
| 349 | **********/ | ||
| 350 | |||
| 351 | /* | ||
| 352 | * Port A | ||
| 353 | */ | ||
| 354 | #define PADIR_ADDR 0xfffff400 /* Port A direction reg */ | ||
| 355 | #define PADATA_ADDR 0xfffff401 /* Port A data register */ | ||
| 356 | #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ | ||
| 357 | |||
| 358 | #define PADIR BYTE_REF(PADIR_ADDR) | ||
| 359 | #define PADATA BYTE_REF(PADATA_ADDR) | ||
| 360 | #define PAPUEN BYTE_REF(PAPUEN_ADDR) | ||
| 361 | |||
| 362 | #define PA(x) (1 << (x)) | ||
| 363 | |||
| 364 | /* | ||
| 365 | * Port B | ||
| 366 | */ | ||
| 367 | #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ | ||
| 368 | #define PBDATA_ADDR 0xfffff409 /* Port B data register */ | ||
| 369 | #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ | ||
| 370 | #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ | ||
| 371 | |||
| 372 | #define PBDIR BYTE_REF(PBDIR_ADDR) | ||
| 373 | #define PBDATA BYTE_REF(PBDATA_ADDR) | ||
| 374 | #define PBPUEN BYTE_REF(PBPUEN_ADDR) | ||
| 375 | #define PBSEL BYTE_REF(PBSEL_ADDR) | ||
| 376 | |||
| 377 | #define PB(x) (1 << (x)) | ||
| 378 | |||
| 379 | #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ | ||
| 380 | #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ | ||
| 381 | #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ | ||
| 382 | #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ | ||
| 383 | #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ | ||
| 384 | #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ | ||
| 385 | #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ | ||
| 386 | #define PB_PWMO 0x80 /* Use PWMO as PB[7] */ | ||
| 387 | |||
| 388 | /* | ||
| 389 | * Port C | ||
| 390 | */ | ||
| 391 | #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ | ||
| 392 | #define PCDATA_ADDR 0xfffff411 /* Port C data register */ | ||
| 393 | #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ | ||
| 394 | #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ | ||
| 395 | |||
| 396 | #define PCDIR BYTE_REF(PCDIR_ADDR) | ||
| 397 | #define PCDATA BYTE_REF(PCDATA_ADDR) | ||
| 398 | #define PCPDEN BYTE_REF(PCPDEN_ADDR) | ||
| 399 | #define PCSEL BYTE_REF(PCSEL_ADDR) | ||
| 400 | |||
| 401 | #define PC(x) (1 << (x)) | ||
| 402 | |||
| 403 | #define PC_LD0 0x01 /* Use LD0 as PC[0] */ | ||
| 404 | #define PC_LD1 0x02 /* Use LD1 as PC[1] */ | ||
| 405 | #define PC_LD2 0x04 /* Use LD2 as PC[2] */ | ||
| 406 | #define PC_LD3 0x08 /* Use LD3 as PC[3] */ | ||
| 407 | #define PC_LFLM 0x10 /* Use LFLM as PC[4] */ | ||
| 408 | #define PC_LLP 0x20 /* Use LLP as PC[5] */ | ||
| 409 | #define PC_LCLK 0x40 /* Use LCLK as PC[6] */ | ||
| 410 | #define PC_LACD 0x80 /* Use LACD as PC[7] */ | ||
| 411 | |||
| 412 | /* | ||
| 413 | * Port D | ||
| 414 | */ | ||
| 415 | #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ | ||
| 416 | #define PDDATA_ADDR 0xfffff419 /* Port D data register */ | ||
| 417 | #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ | ||
| 418 | #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ | ||
| 419 | #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ | ||
| 420 | #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ | ||
| 421 | #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ | ||
| 422 | #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ | ||
| 423 | |||
| 424 | #define PDDIR BYTE_REF(PDDIR_ADDR) | ||
| 425 | #define PDDATA BYTE_REF(PDDATA_ADDR) | ||
| 426 | #define PDPUEN BYTE_REF(PDPUEN_ADDR) | ||
| 427 | #define PDSEL BYTE_REF(PDSEL_ADDR) | ||
| 428 | #define PDPOL BYTE_REF(PDPOL_ADDR) | ||
| 429 | #define PDIRQEN BYTE_REF(PDIRQEN_ADDR) | ||
| 430 | #define PDKBEN BYTE_REF(PDKBEN_ADDR) | ||
| 431 | #define PDIQEG BYTE_REF(PDIQEG_ADDR) | ||
| 432 | |||
| 433 | #define PD(x) (1 << (x)) | ||
| 434 | |||
| 435 | #define PD_INT0 0x01 /* Use INT0 as PD[0] */ | ||
| 436 | #define PD_INT1 0x02 /* Use INT1 as PD[1] */ | ||
| 437 | #define PD_INT2 0x04 /* Use INT2 as PD[2] */ | ||
| 438 | #define PD_INT3 0x08 /* Use INT3 as PD[3] */ | ||
| 439 | #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ | ||
| 440 | #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ | ||
| 441 | #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ | ||
| 442 | #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ | ||
| 443 | |||
| 444 | /* | ||
| 445 | * Port E | ||
| 446 | */ | ||
| 447 | #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ | ||
| 448 | #define PEDATA_ADDR 0xfffff421 /* Port E data register */ | ||
| 449 | #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ | ||
| 450 | #define PESEL_ADDR 0xfffff423 /* Port E Select Register */ | ||
| 451 | |||
| 452 | #define PEDIR BYTE_REF(PEDIR_ADDR) | ||
| 453 | #define PEDATA BYTE_REF(PEDATA_ADDR) | ||
| 454 | #define PEPUEN BYTE_REF(PEPUEN_ADDR) | ||
| 455 | #define PESEL BYTE_REF(PESEL_ADDR) | ||
| 456 | |||
| 457 | #define PE(x) (1 << (x)) | ||
| 458 | |||
| 459 | #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ | ||
| 460 | #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ | ||
| 461 | #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ | ||
| 462 | #define PE_DWE 0x08 /* Use DWE as PE[3] */ | ||
| 463 | #define PE_RXD 0x10 /* Use RXD as PE[4] */ | ||
| 464 | #define PE_TXD 0x20 /* Use TXD as PE[5] */ | ||
| 465 | #define PE_RTS 0x40 /* Use RTS as PE[6] */ | ||
| 466 | #define PE_CTS 0x80 /* Use CTS as PE[7] */ | ||
| 467 | |||
| 468 | /* | ||
| 469 | * Port F | ||
| 470 | */ | ||
| 471 | #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ | ||
| 472 | #define PFDATA_ADDR 0xfffff429 /* Port F data register */ | ||
| 473 | #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ | ||
| 474 | #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ | ||
| 475 | |||
| 476 | #define PFDIR BYTE_REF(PFDIR_ADDR) | ||
| 477 | #define PFDATA BYTE_REF(PFDATA_ADDR) | ||
| 478 | #define PFPUEN BYTE_REF(PFPUEN_ADDR) | ||
| 479 | #define PFSEL BYTE_REF(PFSEL_ADDR) | ||
| 480 | |||
| 481 | #define PF(x) (1 << (x)) | ||
| 482 | |||
| 483 | #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ | ||
| 484 | #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ | ||
| 485 | #define PF_CLKO 0x04 /* Use CLKO as PF[2] */ | ||
| 486 | #define PF_A20 0x08 /* Use A20 as PF[3] */ | ||
| 487 | #define PF_A21 0x10 /* Use A21 as PF[4] */ | ||
| 488 | #define PF_A22 0x20 /* Use A22 as PF[5] */ | ||
| 489 | #define PF_A23 0x40 /* Use A23 as PF[6] */ | ||
| 490 | #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ | ||
| 491 | |||
| 492 | /* | ||
| 493 | * Port G | ||
| 494 | */ | ||
| 495 | #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ | ||
| 496 | #define PGDATA_ADDR 0xfffff431 /* Port G data register */ | ||
| 497 | #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ | ||
| 498 | #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ | ||
| 499 | |||
| 500 | #define PGDIR BYTE_REF(PGDIR_ADDR) | ||
| 501 | #define PGDATA BYTE_REF(PGDATA_ADDR) | ||
| 502 | #define PGPUEN BYTE_REF(PGPUEN_ADDR) | ||
| 503 | #define PGSEL BYTE_REF(PGSEL_ADDR) | ||
| 504 | |||
| 505 | #define PG(x) (1 << (x)) | ||
| 506 | |||
| 507 | #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ | ||
| 508 | #define PG_A0 0x02 /* Use A0 as PG[1] */ | ||
| 509 | #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ | ||
| 510 | #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ | ||
| 511 | #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ | ||
| 512 | #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ | ||
| 513 | |||
| 514 | /* | ||
| 515 | * Port J | ||
| 516 | */ | ||
| 517 | #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ | ||
| 518 | #define PJDATA_ADDR 0xfffff439 /* Port J data register */ | ||
| 519 | #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */ | ||
| 520 | #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ | ||
| 521 | |||
| 522 | #define PJDIR BYTE_REF(PJDIR_ADDR) | ||
| 523 | #define PJDATA BYTE_REF(PJDATA_ADDR) | ||
| 524 | #define PJPUEN BYTE_REF(PJPUEN_ADDR) | ||
| 525 | #define PJSEL BYTE_REF(PJSEL_ADDR) | ||
| 526 | |||
| 527 | #define PJ(x) (1 << (x)) | ||
| 528 | |||
| 529 | /* | ||
| 530 | * Port K | ||
| 531 | */ | ||
| 532 | #define PKDIR_ADDR 0xfffff440 /* Port K direction reg */ | ||
| 533 | #define PKDATA_ADDR 0xfffff441 /* Port K data register */ | ||
| 534 | #define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */ | ||
| 535 | #define PKSEL_ADDR 0xfffff443 /* Port K Select Register */ | ||
| 536 | |||
| 537 | #define PKDIR BYTE_REF(PKDIR_ADDR) | ||
| 538 | #define PKDATA BYTE_REF(PKDATA_ADDR) | ||
| 539 | #define PKPUEN BYTE_REF(PKPUEN_ADDR) | ||
| 540 | #define PKSEL BYTE_REF(PKSEL_ADDR) | ||
| 541 | |||
| 542 | #define PK(x) (1 << (x)) | ||
| 543 | |||
| 544 | #define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */ | ||
| 545 | #define PK_PWM2 0x01 /* Use PWM2 as PK[0] */ | ||
| 546 | #define PK_R_W 0x02 /* Use R/W as PK[1] */ | ||
| 547 | #define PK_LDS 0x04 /* Use /LDS as PK[2] */ | ||
| 548 | #define PK_UDS 0x08 /* Use /UDS as PK[3] */ | ||
| 549 | #define PK_LD4 0x10 /* Use LD4 as PK[4] */ | ||
| 550 | #define PK_LD5 0x20 /* Use LD5 as PK[5] */ | ||
| 551 | #define PK_LD6 0x40 /* Use LD6 as PK[6] */ | ||
| 552 | #define PK_LD7 0x80 /* Use LD7 as PK[7] */ | ||
| 553 | |||
| 554 | #define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ | ||
| 555 | #define PJDATA_ADDR 0xfffff439 /* Port J data register */ | ||
| 556 | #define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */ | ||
| 557 | #define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ | ||
| 558 | |||
| 559 | #define PJDIR BYTE_REF(PJDIR_ADDR) | ||
| 560 | #define PJDATA BYTE_REF(PJDATA_ADDR) | ||
| 561 | #define PJPUEN BYTE_REF(PJPUEN_ADDR) | ||
| 562 | #define PJSEL BYTE_REF(PJSEL_ADDR) | ||
| 563 | |||
| 564 | #define PJ(x) (1 << (x)) | ||
| 565 | |||
| 566 | #define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */ | ||
| 567 | #define PJ_MISO 0x02 /* Use MISO as PJ[1] */ | ||
| 568 | #define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */ | ||
| 569 | #define PJ_SS 0x08 /* Use SS as PJ[3] */ | ||
| 570 | #define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */ | ||
| 571 | #define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */ | ||
| 572 | #define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */ | ||
| 573 | #define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */ | ||
| 574 | |||
| 575 | /* | ||
| 576 | * Port M | ||
| 577 | */ | ||
| 578 | #define PMDIR_ADDR 0xfffff448 /* Port M direction reg */ | ||
| 579 | #define PMDATA_ADDR 0xfffff449 /* Port M data register */ | ||
| 580 | #define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */ | ||
| 581 | #define PMSEL_ADDR 0xfffff44b /* Port M Select Register */ | ||
| 582 | |||
| 583 | #define PMDIR BYTE_REF(PMDIR_ADDR) | ||
| 584 | #define PMDATA BYTE_REF(PMDATA_ADDR) | ||
| 585 | #define PMPUEN BYTE_REF(PMPUEN_ADDR) | ||
| 586 | #define PMSEL BYTE_REF(PMSEL_ADDR) | ||
| 587 | |||
| 588 | #define PM(x) (1 << (x)) | ||
| 589 | |||
| 590 | #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */ | ||
| 591 | #define PM_SDCE 0x02 /* Use SDCE as PM[1] */ | ||
| 592 | #define PM_DQMH 0x04 /* Use DQMH as PM[2] */ | ||
| 593 | #define PM_DQML 0x08 /* Use DQML as PM[3] */ | ||
| 594 | #define PM_SDA10 0x10 /* Use SDA10 as PM[4] */ | ||
| 595 | #define PM_DMOE 0x20 /* Use DMOE as PM[5] */ | ||
| 596 | |||
| 597 | /********** | ||
| 598 | * | ||
| 599 | * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) | ||
| 600 | * | ||
| 601 | **********/ | ||
| 602 | |||
| 603 | /* | ||
| 604 | * PWM Control Register | ||
| 605 | */ | ||
| 606 | #define PWMC_ADDR 0xfffff500 | ||
| 607 | #define PWMC WORD_REF(PWMC_ADDR) | ||
| 608 | |||
| 609 | #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ | ||
| 610 | #define PWMC_CLKSEL_SHIFT 0 | ||
| 611 | #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ | ||
| 612 | #define PWMC_REPEAT_SHIFT 2 | ||
| 613 | #define PWMC_EN 0x0010 /* Enable PWM */ | ||
| 614 | #define PMNC_FIFOAV 0x0020 /* FIFO Available */ | ||
| 615 | #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ | ||
| 616 | #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ | ||
| 617 | #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ | ||
| 618 | #define PWMC_PRESCALER_SHIFT 8 | ||
| 619 | #define PWMC_CLKSRC 0x8000 /* Clock Source Select */ | ||
| 620 | |||
| 621 | /* '328-compatible definitions */ | ||
| 622 | #define PWMC_PWMEN PWMC_EN | ||
| 623 | |||
| 624 | /* | ||
| 625 | * PWM Sample Register | ||
| 626 | */ | ||
| 627 | #define PWMS_ADDR 0xfffff502 | ||
| 628 | #define PWMS WORD_REF(PWMS_ADDR) | ||
| 629 | |||
| 630 | /* | ||
| 631 | * PWM Period Register | ||
| 632 | */ | ||
| 633 | #define PWMP_ADDR 0xfffff504 | ||
| 634 | #define PWMP BYTE_REF(PWMP_ADDR) | ||
| 635 | |||
| 636 | /* | ||
| 637 | * PWM Counter Register | ||
| 638 | */ | ||
| 639 | #define PWMCNT_ADDR 0xfffff505 | ||
| 640 | #define PWMCNT BYTE_REF(PWMCNT_ADDR) | ||
| 641 | |||
| 642 | /********** | ||
| 643 | * | ||
| 644 | * 0xFFFFF6xx -- General-Purpose Timer | ||
| 645 | * | ||
| 646 | **********/ | ||
| 647 | |||
| 648 | /* | ||
| 649 | * Timer Control register | ||
| 650 | */ | ||
| 651 | #define TCTL_ADDR 0xfffff600 | ||
| 652 | #define TCTL WORD_REF(TCTL_ADDR) | ||
| 653 | |||
| 654 | #define TCTL_TEN 0x0001 /* Timer Enable */ | ||
| 655 | #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ | ||
| 656 | #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ | ||
| 657 | #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ | ||
| 658 | #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ | ||
| 659 | #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ | ||
| 660 | #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ | ||
| 661 | #define TCTL_IRQEN 0x0010 /* IRQ Enable */ | ||
| 662 | #define TCTL_OM 0x0020 /* Output Mode */ | ||
| 663 | #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ | ||
| 664 | #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ | ||
| 665 | #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ | ||
| 666 | #define TCTL_FRR 0x0010 /* Free-Run Mode */ | ||
| 667 | |||
| 668 | /* '328-compatible definitions */ | ||
| 669 | #define TCTL1_ADDR TCTL_ADDR | ||
| 670 | #define TCTL1 TCTL | ||
| 671 | |||
| 672 | /* | ||
| 673 | * Timer Prescaler Register | ||
| 674 | */ | ||
| 675 | #define TPRER_ADDR 0xfffff602 | ||
| 676 | #define TPRER WORD_REF(TPRER_ADDR) | ||
| 677 | |||
| 678 | /* '328-compatible definitions */ | ||
| 679 | #define TPRER1_ADDR TPRER_ADDR | ||
| 680 | #define TPRER1 TPRER | ||
| 681 | |||
| 682 | /* | ||
| 683 | * Timer Compare Register | ||
| 684 | */ | ||
| 685 | #define TCMP_ADDR 0xfffff604 | ||
| 686 | #define TCMP WORD_REF(TCMP_ADDR) | ||
| 687 | |||
| 688 | /* '328-compatible definitions */ | ||
| 689 | #define TCMP1_ADDR TCMP_ADDR | ||
| 690 | #define TCMP1 TCMP | ||
| 691 | |||
| 692 | /* | ||
| 693 | * Timer Capture register | ||
| 694 | */ | ||
| 695 | #define TCR_ADDR 0xfffff606 | ||
| 696 | #define TCR WORD_REF(TCR_ADDR) | ||
| 697 | |||
| 698 | /* '328-compatible definitions */ | ||
| 699 | #define TCR1_ADDR TCR_ADDR | ||
| 700 | #define TCR1 TCR | ||
| 701 | |||
| 702 | /* | ||
| 703 | * Timer Counter Register | ||
| 704 | */ | ||
| 705 | #define TCN_ADDR 0xfffff608 | ||
| 706 | #define TCN WORD_REF(TCN_ADDR) | ||
| 707 | |||
| 708 | /* '328-compatible definitions */ | ||
| 709 | #define TCN1_ADDR TCN_ADDR | ||
| 710 | #define TCN1 TCN | ||
| 711 | |||
| 712 | /* | ||
| 713 | * Timer Status Register | ||
| 714 | */ | ||
| 715 | #define TSTAT_ADDR 0xfffff60a | ||
| 716 | #define TSTAT WORD_REF(TSTAT_ADDR) | ||
| 717 | |||
| 718 | #define TSTAT_COMP 0x0001 /* Compare Event occurred */ | ||
| 719 | #define TSTAT_CAPT 0x0001 /* Capture Event occurred */ | ||
| 720 | |||
| 721 | /* '328-compatible definitions */ | ||
| 722 | #define TSTAT1_ADDR TSTAT_ADDR | ||
| 723 | #define TSTAT1 TSTAT | ||
| 724 | |||
| 725 | /********** | ||
| 726 | * | ||
| 727 | * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) | ||
| 728 | * | ||
| 729 | **********/ | ||
| 730 | |||
| 731 | /* | ||
| 732 | * SPIM Data Register | ||
| 733 | */ | ||
| 734 | #define SPIMDATA_ADDR 0xfffff800 | ||
| 735 | #define SPIMDATA WORD_REF(SPIMDATA_ADDR) | ||
| 736 | |||
| 737 | /* | ||
| 738 | * SPIM Control/Status Register | ||
| 739 | */ | ||
| 740 | #define SPIMCONT_ADDR 0xfffff802 | ||
| 741 | #define SPIMCONT WORD_REF(SPIMCONT_ADDR) | ||
| 742 | |||
| 743 | #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ | ||
| 744 | #define SPIMCONT_BIT_COUNT_SHIFT 0 | ||
| 745 | #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ | ||
| 746 | #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ | ||
| 747 | #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ | ||
| 748 | #define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ | ||
| 749 | #define SPIMCONT_XCH 0x0100 /* Exchange */ | ||
| 750 | #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ | ||
| 751 | #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ | ||
| 752 | #define SPIMCONT_DATA_RATE_SHIFT 13 | ||
| 753 | |||
| 754 | /* '328-compatible definitions */ | ||
| 755 | #define SPIMCONT_SPIMIRQ SPIMCONT_IRQ | ||
| 756 | #define SPIMCONT_SPIMEN SPIMCONT_ENABLE | ||
| 757 | |||
| 758 | /********** | ||
| 759 | * | ||
| 760 | * 0xFFFFF9xx -- UART | ||
| 761 | * | ||
| 762 | **********/ | ||
| 763 | |||
| 764 | /* | ||
| 765 | * UART Status/Control Register | ||
| 766 | */ | ||
| 767 | |||
| 768 | #define USTCNT_ADDR 0xfffff900 | ||
| 769 | #define USTCNT WORD_REF(USTCNT_ADDR) | ||
| 770 | |||
| 771 | #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ | ||
| 772 | #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ | ||
| 773 | #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ | ||
| 774 | #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ | ||
| 775 | #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ | ||
| 776 | #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ | ||
| 777 | #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ | ||
| 778 | #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ | ||
| 779 | #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ | ||
| 780 | #define USTCNT_STOP 0x0200 /* Stop bit transmission */ | ||
| 781 | #define USTCNT_ODD 0x0400 /* Odd Parity */ | ||
| 782 | #define USTCNT_PEN 0x0800 /* Parity Enable */ | ||
| 783 | #define USTCNT_CLKM 0x1000 /* Clock Mode Select */ | ||
| 784 | #define USTCNT_TXEN 0x2000 /* Transmitter Enable */ | ||
| 785 | #define USTCNT_RXEN 0x4000 /* Receiver Enable */ | ||
| 786 | #define USTCNT_UEN 0x8000 /* UART Enable */ | ||
| 787 | |||
| 788 | /* '328-compatible definitions */ | ||
| 789 | #define USTCNT_TXAVAILEN USTCNT_TXAE | ||
| 790 | #define USTCNT_TXHALFEN USTCNT_TXHE | ||
| 791 | #define USTCNT_TXEMPTYEN USTCNT_TXEE | ||
| 792 | #define USTCNT_RXREADYEN USTCNT_RXRE | ||
| 793 | #define USTCNT_RXHALFEN USTCNT_RXHE | ||
| 794 | #define USTCNT_RXFULLEN USTCNT_RXFE | ||
| 795 | #define USTCNT_CTSDELTAEN USTCNT_CTSD | ||
| 796 | #define USTCNT_ODD_EVEN USTCNT_ODD | ||
| 797 | #define USTCNT_PARITYEN USTCNT_PEN | ||
| 798 | #define USTCNT_CLKMODE USTCNT_CLKM | ||
| 799 | #define USTCNT_UARTEN USTCNT_UEN | ||
| 800 | |||
| 801 | /* | ||
| 802 | * UART Baud Control Register | ||
| 803 | */ | ||
| 804 | #define UBAUD_ADDR 0xfffff902 | ||
| 805 | #define UBAUD WORD_REF(UBAUD_ADDR) | ||
| 806 | |||
| 807 | #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ | ||
| 808 | #define UBAUD_PRESCALER_SHIFT 0 | ||
| 809 | #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ | ||
| 810 | #define UBAUD_DIVIDE_SHIFT 8 | ||
| 811 | #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ | ||
| 812 | #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ | ||
| 813 | |||
| 814 | /* | ||
| 815 | * UART Receiver Register | ||
| 816 | */ | ||
| 817 | #define URX_ADDR 0xfffff904 | ||
| 818 | #define URX WORD_REF(URX_ADDR) | ||
| 819 | |||
| 820 | #define URX_RXDATA_ADDR 0xfffff905 | ||
| 821 | #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) | ||
| 822 | |||
| 823 | #define URX_RXDATA_MASK 0x00ff /* Received data */ | ||
| 824 | #define URX_RXDATA_SHIFT 0 | ||
| 825 | #define URX_PARITY_ERROR 0x0100 /* Parity Error */ | ||
| 826 | #define URX_BREAK 0x0200 /* Break Detected */ | ||
| 827 | #define URX_FRAME_ERROR 0x0400 /* Framing Error */ | ||
| 828 | #define URX_OVRUN 0x0800 /* Serial Overrun */ | ||
| 829 | #define URX_OLD_DATA 0x1000 /* Old data in FIFO */ | ||
| 830 | #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ | ||
| 831 | #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ | ||
| 832 | #define URX_FIFO_FULL 0x8000 /* FIFO is Full */ | ||
| 833 | |||
| 834 | /* | ||
| 835 | * UART Transmitter Register | ||
| 836 | */ | ||
| 837 | #define UTX_ADDR 0xfffff906 | ||
| 838 | #define UTX WORD_REF(UTX_ADDR) | ||
| 839 | |||
| 840 | #define UTX_TXDATA_ADDR 0xfffff907 | ||
| 841 | #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) | ||
| 842 | |||
| 843 | #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ | ||
| 844 | #define UTX_TXDATA_SHIFT 0 | ||
| 845 | #define UTX_CTS_DELTA 0x0100 /* CTS changed */ | ||
| 846 | #define UTX_CTS_STAT 0x0200 /* CTS State */ | ||
| 847 | #define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ | ||
| 848 | #define UTX_NOCTS 0x0800 /* Ignore CTS */ | ||
| 849 | #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ | ||
| 850 | #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ | ||
| 851 | #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ | ||
| 852 | #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ | ||
| 853 | |||
| 854 | /* '328-compatible definitions */ | ||
| 855 | #define UTX_CTS_STATUS UTX_CTS_STAT | ||
| 856 | #define UTX_IGNORE_CTS UTX_NOCTS | ||
| 857 | |||
| 858 | /* | ||
| 859 | * UART Miscellaneous Register | ||
| 860 | */ | ||
| 861 | #define UMISC_ADDR 0xfffff908 | ||
| 862 | #define UMISC WORD_REF(UMISC_ADDR) | ||
| 863 | |||
| 864 | #define UMISC_TX_POL 0x0004 /* Transmit Polarity */ | ||
| 865 | #define UMISC_RX_POL 0x0008 /* Receive Polarity */ | ||
| 866 | #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ | ||
| 867 | #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ | ||
| 868 | #define UMISC_RTS 0x0040 /* Set RTS status */ | ||
| 869 | #define UMISC_RTSCONT 0x0080 /* Choose RTS control */ | ||
| 870 | #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ | ||
| 871 | #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ | ||
| 872 | #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ | ||
| 873 | #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ | ||
| 874 | #define UMISC_CLKSRC 0x4000 /* Clock Source */ | ||
| 875 | #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ | ||
| 876 | |||
| 877 | /* | ||
| 878 | * UART Non-integer Prescaler Register | ||
| 879 | */ | ||
| 880 | #define NIPR_ADDR 0xfffff90a | ||
| 881 | #define NIPR WORD_REF(NIPR_ADDR) | ||
| 882 | |||
| 883 | #define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ | ||
| 884 | #define NIPR_STEP_VALUE_SHIFT 0 | ||
| 885 | #define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ | ||
| 886 | #define NIPR_SELECT_SHIFT 8 | ||
| 887 | #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ | ||
| 888 | |||
| 889 | |||
| 890 | /* generalization of uart control registers to support multiple ports: */ | ||
| 891 | typedef struct { | ||
| 892 | volatile unsigned short int ustcnt; | ||
| 893 | volatile unsigned short int ubaud; | ||
| 894 | union { | ||
| 895 | volatile unsigned short int w; | ||
| 896 | struct { | ||
| 897 | volatile unsigned char status; | ||
| 898 | volatile unsigned char rxdata; | ||
| 899 | } b; | ||
| 900 | } urx; | ||
| 901 | union { | ||
| 902 | volatile unsigned short int w; | ||
| 903 | struct { | ||
| 904 | volatile unsigned char status; | ||
| 905 | volatile unsigned char txdata; | ||
| 906 | } b; | ||
| 907 | } utx; | ||
| 908 | volatile unsigned short int umisc; | ||
| 909 | volatile unsigned short int nipr; | ||
| 910 | volatile unsigned short int hmark; | ||
| 911 | volatile unsigned short int unused; | ||
| 912 | } __attribute__((packed)) m68328_uart; | ||
| 913 | |||
| 914 | |||
| 915 | |||
| 916 | |||
| 917 | /********** | ||
| 918 | * | ||
| 919 | * 0xFFFFFAxx -- LCD Controller | ||
| 920 | * | ||
| 921 | **********/ | ||
| 922 | |||
| 923 | /* | ||
| 924 | * LCD Screen Starting Address Register | ||
| 925 | */ | ||
| 926 | #define LSSA_ADDR 0xfffffa00 | ||
| 927 | #define LSSA LONG_REF(LSSA_ADDR) | ||
| 928 | |||
| 929 | #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ | ||
| 930 | |||
| 931 | /* | ||
| 932 | * LCD Virtual Page Width Register | ||
| 933 | */ | ||
| 934 | #define LVPW_ADDR 0xfffffa05 | ||
| 935 | #define LVPW BYTE_REF(LVPW_ADDR) | ||
| 936 | |||
| 937 | /* | ||
| 938 | * LCD Screen Width Register (not compatible with '328 !!!) | ||
| 939 | */ | ||
| 940 | #define LXMAX_ADDR 0xfffffa08 | ||
| 941 | #define LXMAX WORD_REF(LXMAX_ADDR) | ||
| 942 | |||
| 943 | #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ | ||
| 944 | |||
| 945 | /* | ||
| 946 | * LCD Screen Height Register | ||
| 947 | */ | ||
| 948 | #define LYMAX_ADDR 0xfffffa0a | ||
| 949 | #define LYMAX WORD_REF(LYMAX_ADDR) | ||
| 950 | |||
| 951 | #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ | ||
| 952 | |||
| 953 | /* | ||
| 954 | * LCD Cursor X Position Register | ||
| 955 | */ | ||
| 956 | #define LCXP_ADDR 0xfffffa18 | ||
| 957 | #define LCXP WORD_REF(LCXP_ADDR) | ||
| 958 | |||
| 959 | #define LCXP_CC_MASK 0xc000 /* Cursor Control */ | ||
| 960 | #define LCXP_CC_TRAMSPARENT 0x0000 | ||
| 961 | #define LCXP_CC_BLACK 0x4000 | ||
| 962 | #define LCXP_CC_REVERSED 0x8000 | ||
| 963 | #define LCXP_CC_WHITE 0xc000 | ||
| 964 | #define LCXP_CXP_MASK 0x02ff /* Cursor X position */ | ||
| 965 | |||
| 966 | /* | ||
| 967 | * LCD Cursor Y Position Register | ||
| 968 | */ | ||
| 969 | #define LCYP_ADDR 0xfffffa1a | ||
| 970 | #define LCYP WORD_REF(LCYP_ADDR) | ||
| 971 | |||
| 972 | #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ | ||
| 973 | |||
| 974 | /* | ||
| 975 | * LCD Cursor Width and Heigth Register | ||
| 976 | */ | ||
| 977 | #define LCWCH_ADDR 0xfffffa1c | ||
| 978 | #define LCWCH WORD_REF(LCWCH_ADDR) | ||
| 979 | |||
| 980 | #define LCWCH_CH_MASK 0x001f /* Cursor Height */ | ||
| 981 | #define LCWCH_CH_SHIFT 0 | ||
| 982 | #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ | ||
| 983 | #define LCWCH_CW_SHIFT 8 | ||
| 984 | |||
| 985 | /* | ||
| 986 | * LCD Blink Control Register | ||
| 987 | */ | ||
| 988 | #define LBLKC_ADDR 0xfffffa1f | ||
| 989 | #define LBLKC BYTE_REF(LBLKC_ADDR) | ||
| 990 | |||
| 991 | #define LBLKC_BD_MASK 0x7f /* Blink Divisor */ | ||
| 992 | #define LBLKC_BD_SHIFT 0 | ||
| 993 | #define LBLKC_BKEN 0x80 /* Blink Enabled */ | ||
| 994 | |||
| 995 | /* | ||
| 996 | * LCD Panel Interface Configuration Register | ||
| 997 | */ | ||
| 998 | #define LPICF_ADDR 0xfffffa20 | ||
| 999 | #define LPICF BYTE_REF(LPICF_ADDR) | ||
| 1000 | |||
| 1001 | #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ | ||
| 1002 | #define LPICF_GS_BW 0x00 | ||
| 1003 | #define LPICF_GS_GRAY_4 0x01 | ||
| 1004 | #define LPICF_GS_GRAY_16 0x02 | ||
| 1005 | #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ | ||
| 1006 | #define LPICF_PBSIZ_1 0x00 | ||
| 1007 | #define LPICF_PBSIZ_2 0x04 | ||
| 1008 | #define LPICF_PBSIZ_4 0x08 | ||
| 1009 | |||
| 1010 | /* | ||
| 1011 | * LCD Polarity Configuration Register | ||
| 1012 | */ | ||
| 1013 | #define LPOLCF_ADDR 0xfffffa21 | ||
| 1014 | #define LPOLCF BYTE_REF(LPOLCF_ADDR) | ||
| 1015 | |||
| 1016 | #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ | ||
| 1017 | #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ | ||
| 1018 | #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ | ||
| 1019 | #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ | ||
| 1020 | |||
| 1021 | /* | ||
| 1022 | * LACD (LCD Alternate Crystal Direction) Rate Control Register | ||
| 1023 | */ | ||
| 1024 | #define LACDRC_ADDR 0xfffffa23 | ||
| 1025 | #define LACDRC BYTE_REF(LACDRC_ADDR) | ||
| 1026 | |||
| 1027 | #define LACDRC_ACDSLT 0x80 /* Signal Source Select */ | ||
| 1028 | #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ | ||
| 1029 | #define LACDRC_ACD_SHIFT 0 | ||
| 1030 | |||
| 1031 | /* | ||
| 1032 | * LCD Pixel Clock Divider Register | ||
| 1033 | */ | ||
| 1034 | #define LPXCD_ADDR 0xfffffa25 | ||
| 1035 | #define LPXCD BYTE_REF(LPXCD_ADDR) | ||
| 1036 | |||
| 1037 | #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ | ||
| 1038 | #define LPXCD_PCD_SHIFT 0 | ||
| 1039 | |||
| 1040 | /* | ||
| 1041 | * LCD Clocking Control Register | ||
| 1042 | */ | ||
| 1043 | #define LCKCON_ADDR 0xfffffa27 | ||
| 1044 | #define LCKCON BYTE_REF(LCKCON_ADDR) | ||
| 1045 | |||
| 1046 | #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ | ||
| 1047 | #define LCKCON_DWS_SHIFT 0 | ||
| 1048 | #define LCKCON_DWIDTH 0x40 /* Display Memory Width */ | ||
| 1049 | #define LCKCON_LCDON 0x80 /* Enable LCD Controller */ | ||
| 1050 | |||
| 1051 | /* '328-compatible definitions */ | ||
| 1052 | #define LCKCON_DW_MASK LCKCON_DWS_MASK | ||
| 1053 | #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT | ||
| 1054 | |||
| 1055 | /* | ||
| 1056 | * LCD Refresh Rate Adjustment Register | ||
| 1057 | */ | ||
| 1058 | #define LRRA_ADDR 0xfffffa29 | ||
| 1059 | #define LRRA BYTE_REF(LRRA_ADDR) | ||
| 1060 | |||
| 1061 | /* | ||
| 1062 | * LCD Panning Offset Register | ||
| 1063 | */ | ||
| 1064 | #define LPOSR_ADDR 0xfffffa2d | ||
| 1065 | #define LPOSR BYTE_REF(LPOSR_ADDR) | ||
| 1066 | |||
| 1067 | #define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ | ||
| 1068 | #define LPOSR_POS_SHIFT 0 | ||
| 1069 | |||
| 1070 | /* | ||
| 1071 | * LCD Frame Rate Control Modulation Register | ||
| 1072 | */ | ||
| 1073 | #define LFRCM_ADDR 0xfffffa31 | ||
| 1074 | #define LFRCM BYTE_REF(LFRCM_ADDR) | ||
| 1075 | |||
| 1076 | #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ | ||
| 1077 | #define LFRCM_YMOD_SHIFT 0 | ||
| 1078 | #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ | ||
| 1079 | #define LFRCM_XMOD_SHIFT 4 | ||
| 1080 | |||
| 1081 | /* | ||
| 1082 | * LCD Gray Palette Mapping Register | ||
| 1083 | */ | ||
| 1084 | #define LGPMR_ADDR 0xfffffa33 | ||
| 1085 | #define LGPMR BYTE_REF(LGPMR_ADDR) | ||
| 1086 | |||
| 1087 | #define LGPMR_G1_MASK 0x0f | ||
| 1088 | #define LGPMR_G1_SHIFT 0 | ||
| 1089 | #define LGPMR_G2_MASK 0xf0 | ||
| 1090 | #define LGPMR_G2_SHIFT 4 | ||
| 1091 | |||
| 1092 | /* | ||
| 1093 | * PWM Contrast Control Register | ||
| 1094 | */ | ||
| 1095 | #define PWMR_ADDR 0xfffffa36 | ||
| 1096 | #define PWMR WORD_REF(PWMR_ADDR) | ||
| 1097 | |||
| 1098 | #define PWMR_PW_MASK 0x00ff /* Pulse Width */ | ||
| 1099 | #define PWMR_PW_SHIFT 0 | ||
| 1100 | #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ | ||
| 1101 | #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ | ||
| 1102 | #define PWMR_SRC_LINE 0x0000 /* Line Pulse */ | ||
| 1103 | #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ | ||
| 1104 | #define PWMR_SRC_LCD 0x4000 /* LCD clock */ | ||
| 1105 | |||
| 1106 | /********** | ||
| 1107 | * | ||
| 1108 | * 0xFFFFFBxx -- Real-Time Clock (RTC) | ||
| 1109 | * | ||
| 1110 | **********/ | ||
| 1111 | |||
| 1112 | /* | ||
| 1113 | * RTC Hours Minutes and Seconds Register | ||
| 1114 | */ | ||
| 1115 | #define RTCTIME_ADDR 0xfffffb00 | ||
| 1116 | #define RTCTIME LONG_REF(RTCTIME_ADDR) | ||
| 1117 | |||
| 1118 | #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ | ||
| 1119 | #define RTCTIME_SECONDS_SHIFT 0 | ||
| 1120 | #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ | ||
| 1121 | #define RTCTIME_MINUTES_SHIFT 16 | ||
| 1122 | #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ | ||
| 1123 | #define RTCTIME_HOURS_SHIFT 24 | ||
| 1124 | |||
| 1125 | /* | ||
| 1126 | * RTC Alarm Register | ||
| 1127 | */ | ||
| 1128 | #define RTCALRM_ADDR 0xfffffb04 | ||
| 1129 | #define RTCALRM LONG_REF(RTCALRM_ADDR) | ||
| 1130 | |||
| 1131 | #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ | ||
| 1132 | #define RTCALRM_SECONDS_SHIFT 0 | ||
| 1133 | #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ | ||
| 1134 | #define RTCALRM_MINUTES_SHIFT 16 | ||
| 1135 | #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ | ||
| 1136 | #define RTCALRM_HOURS_SHIFT 24 | ||
| 1137 | |||
| 1138 | /* | ||
| 1139 | * Watchdog Timer Register | ||
| 1140 | */ | ||
| 1141 | #define WATCHDOG_ADDR 0xfffffb0a | ||
| 1142 | #define WATCHDOG WORD_REF(WATCHDOG_ADDR) | ||
| 1143 | |||
| 1144 | #define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ | ||
| 1145 | #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ | ||
| 1146 | #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */ | ||
| 1147 | #define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ | ||
| 1148 | #define WATCHDOG_CNT_SHIFT 8 | ||
| 1149 | |||
| 1150 | /* | ||
| 1151 | * RTC Control Register | ||
| 1152 | */ | ||
| 1153 | #define RTCCTL_ADDR 0xfffffb0c | ||
| 1154 | #define RTCCTL WORD_REF(RTCCTL_ADDR) | ||
| 1155 | |||
| 1156 | #define RTCCTL_XTL 0x0020 /* Crystal Selection */ | ||
| 1157 | #define RTCCTL_EN 0x0080 /* RTC Enable */ | ||
| 1158 | |||
| 1159 | /* '328-compatible definitions */ | ||
| 1160 | #define RTCCTL_384 RTCCTL_XTL | ||
| 1161 | #define RTCCTL_ENABLE RTCCTL_EN | ||
| 1162 | |||
| 1163 | /* | ||
| 1164 | * RTC Interrupt Status Register | ||
| 1165 | */ | ||
| 1166 | #define RTCISR_ADDR 0xfffffb0e | ||
| 1167 | #define RTCISR WORD_REF(RTCISR_ADDR) | ||
| 1168 | |||
| 1169 | #define RTCISR_SW 0x0001 /* Stopwatch timed out */ | ||
| 1170 | #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ | ||
| 1171 | #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ | ||
| 1172 | #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ | ||
| 1173 | #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ | ||
| 1174 | #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ | ||
| 1175 | #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ | ||
| 1176 | #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ | ||
| 1177 | #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ | ||
| 1178 | #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ | ||
| 1179 | #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ | ||
| 1180 | #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ | ||
| 1181 | #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ | ||
| 1182 | #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ | ||
| 1183 | |||
| 1184 | /* | ||
| 1185 | * RTC Interrupt Enable Register | ||
| 1186 | */ | ||
| 1187 | #define RTCIENR_ADDR 0xfffffb10 | ||
| 1188 | #define RTCIENR WORD_REF(RTCIENR_ADDR) | ||
| 1189 | |||
| 1190 | #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ | ||
| 1191 | #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ | ||
| 1192 | #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ | ||
| 1193 | #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ | ||
| 1194 | #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ | ||
| 1195 | #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ | ||
| 1196 | #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ | ||
| 1197 | #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ | ||
| 1198 | #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ | ||
| 1199 | #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ | ||
| 1200 | #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ | ||
| 1201 | #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ | ||
| 1202 | #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ | ||
| 1203 | #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ | ||
| 1204 | |||
| 1205 | /* | ||
| 1206 | * Stopwatch Minutes Register | ||
| 1207 | */ | ||
| 1208 | #define STPWCH_ADDR 0xfffffb12 | ||
| 1209 | #define STPWCH WORD_REF(STPWCH_ADDR) | ||
| 1210 | |||
| 1211 | #define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ | ||
| 1212 | #define SPTWCH_CNT_SHIFT 0 | ||
| 1213 | |||
| 1214 | /* | ||
| 1215 | * RTC Day Count Register | ||
| 1216 | */ | ||
| 1217 | #define DAYR_ADDR 0xfffffb1a | ||
| 1218 | #define DAYR WORD_REF(DAYR_ADDR) | ||
| 1219 | |||
| 1220 | #define DAYR_DAYS_MASK 0x1ff /* Day Setting */ | ||
| 1221 | #define DAYR_DAYS_SHIFT 0 | ||
| 1222 | |||
| 1223 | /* | ||
| 1224 | * RTC Day Alarm Register | ||
| 1225 | */ | ||
| 1226 | #define DAYALARM_ADDR 0xfffffb1c | ||
| 1227 | #define DAYALARM WORD_REF(DAYALARM_ADDR) | ||
| 1228 | |||
| 1229 | #define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ | ||
| 1230 | #define DAYALARM_DAYSAL_SHIFT 0 | ||
| 1231 | |||
| 1232 | /********** | ||
| 1233 | * | ||
| 1234 | * 0xFFFFFCxx -- DRAM Controller | ||
| 1235 | * | ||
| 1236 | **********/ | ||
| 1237 | |||
| 1238 | /* | ||
| 1239 | * DRAM Memory Configuration Register | ||
| 1240 | */ | ||
| 1241 | #define DRAMMC_ADDR 0xfffffc00 | ||
| 1242 | #define DRAMMC WORD_REF(DRAMMC_ADDR) | ||
| 1243 | |||
| 1244 | #define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ | ||
| 1245 | #define DRAMMC_ROW12_PA10 0x0000 | ||
| 1246 | #define DRAMMC_ROW12_PA21 0x4000 | ||
| 1247 | #define DRAMMC_ROW12_PA23 0x8000 | ||
| 1248 | #define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ | ||
| 1249 | #define DRAMMC_ROW0_PA11 0x0000 | ||
| 1250 | #define DRAMMC_ROW0_PA22 0x1000 | ||
| 1251 | #define DRAMMC_ROW0_PA23 0x2000 | ||
| 1252 | #define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ | ||
| 1253 | #define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ | ||
| 1254 | #define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ | ||
| 1255 | #define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ | ||
| 1256 | #define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ | ||
| 1257 | #define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ | ||
| 1258 | #define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ | ||
| 1259 | #define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ | ||
| 1260 | #define DRAMMC_REF_SHIFT 0 | ||
| 1261 | |||
| 1262 | /* | ||
| 1263 | * DRAM Control Register | ||
| 1264 | */ | ||
| 1265 | #define DRAMC_ADDR 0xfffffc02 | ||
| 1266 | #define DRAMC WORD_REF(DRAMC_ADDR) | ||
| 1267 | |||
| 1268 | #define DRAMC_DWE 0x0001 /* DRAM Write Enable */ | ||
| 1269 | #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ | ||
| 1270 | #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ | ||
| 1271 | #define DRAMC_SLW 0x0008 /* Slow RAM */ | ||
| 1272 | #define DRAMC_LSP 0x0010 /* Light Sleep */ | ||
| 1273 | #define DRAMC_MSW 0x0020 /* Slow Multiplexing */ | ||
| 1274 | #define DRAMC_WS_MASK 0x00c0 /* Wait-states */ | ||
| 1275 | #define DRAMC_WS_SHIFT 6 | ||
| 1276 | #define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ | ||
| 1277 | #define DRAMC_PGSZ_SHIFT 8 | ||
| 1278 | #define DRAMC_PGSZ_256K 0x0000 | ||
| 1279 | #define DRAMC_PGSZ_512K 0x0100 | ||
| 1280 | #define DRAMC_PGSZ_1024K 0x0200 | ||
| 1281 | #define DRAMC_PGSZ_2048K 0x0300 | ||
| 1282 | #define DRAMC_EDO 0x0400 /* EDO DRAM */ | ||
| 1283 | #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ | ||
| 1284 | #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ | ||
| 1285 | #define DRAMC_BC_SHIFT 12 | ||
| 1286 | #define DRAMC_RM 0x4000 /* Refresh Mode */ | ||
| 1287 | #define DRAMC_EN 0x8000 /* DRAM Controller enable */ | ||
| 1288 | |||
| 1289 | |||
| 1290 | /********** | ||
| 1291 | * | ||
| 1292 | * 0xFFFFFDxx -- In-Circuit Emulation (ICE) | ||
| 1293 | * | ||
| 1294 | **********/ | ||
| 1295 | |||
| 1296 | /* | ||
| 1297 | * ICE Module Address Compare Register | ||
| 1298 | */ | ||
| 1299 | #define ICEMACR_ADDR 0xfffffd00 | ||
| 1300 | #define ICEMACR LONG_REF(ICEMACR_ADDR) | ||
| 1301 | |||
| 1302 | /* | ||
| 1303 | * ICE Module Address Mask Register | ||
| 1304 | */ | ||
| 1305 | #define ICEMAMR_ADDR 0xfffffd04 | ||
| 1306 | #define ICEMAMR LONG_REF(ICEMAMR_ADDR) | ||
| 1307 | |||
| 1308 | /* | ||
| 1309 | * ICE Module Control Compare Register | ||
| 1310 | */ | ||
| 1311 | #define ICEMCCR_ADDR 0xfffffd08 | ||
| 1312 | #define ICEMCCR WORD_REF(ICEMCCR_ADDR) | ||
| 1313 | |||
| 1314 | #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ | ||
| 1315 | #define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ | ||
| 1316 | |||
| 1317 | /* | ||
| 1318 | * ICE Module Control Mask Register | ||
| 1319 | */ | ||
| 1320 | #define ICEMCMR_ADDR 0xfffffd0a | ||
| 1321 | #define ICEMCMR WORD_REF(ICEMCMR_ADDR) | ||
| 1322 | |||
| 1323 | #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ | ||
| 1324 | #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ | ||
| 1325 | |||
| 1326 | /* | ||
| 1327 | * ICE Module Control Register | ||
| 1328 | */ | ||
| 1329 | #define ICEMCR_ADDR 0xfffffd0c | ||
| 1330 | #define ICEMCR WORD_REF(ICEMCR_ADDR) | ||
| 1331 | |||
| 1332 | #define ICEMCR_CEN 0x0001 /* Compare Enable */ | ||
| 1333 | #define ICEMCR_PBEN 0x0002 /* Program Break Enable */ | ||
| 1334 | #define ICEMCR_SB 0x0004 /* Single Breakpoint */ | ||
| 1335 | #define ICEMCR_HMDIS 0x0008 /* HardMap disable */ | ||
| 1336 | #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ | ||
| 1337 | |||
| 1338 | /* | ||
| 1339 | * ICE Module Status Register | ||
| 1340 | */ | ||
| 1341 | #define ICEMSR_ADDR 0xfffffd0e | ||
| 1342 | #define ICEMSR WORD_REF(ICEMSR_ADDR) | ||
| 1343 | |||
| 1344 | #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ | ||
| 1345 | #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ | ||
| 1346 | #define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ | ||
| 1347 | #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ | ||
| 1348 | |||
| 1349 | #endif /* _MC68VZ328_H_ */ | ||
diff --git a/arch/m68k/include/asm/a.out-core.h b/arch/m68k/include/asm/a.out-core.h new file mode 100644 index 000000000000..f6bfc1d63ff6 --- /dev/null +++ b/arch/m68k/include/asm/a.out-core.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* a.out coredump register dumper | ||
| 2 | * | ||
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
| 4 | * Written by David Howells (dhowells@redhat.com) | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public Licence | ||
| 8 | * as published by the Free Software Foundation; either version | ||
| 9 | * 2 of the Licence, or (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_A_OUT_CORE_H | ||
| 13 | #define _ASM_A_OUT_CORE_H | ||
| 14 | |||
| 15 | #ifdef __KERNEL__ | ||
| 16 | |||
| 17 | #include <linux/user.h> | ||
| 18 | #include <linux/elfcore.h> | ||
| 19 | |||
| 20 | /* | ||
| 21 | * fill in the user structure for an a.out core dump | ||
| 22 | */ | ||
| 23 | static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) | ||
| 24 | { | ||
| 25 | struct switch_stack *sw; | ||
| 26 | |||
| 27 | /* changed the size calculations - should hopefully work better. lbt */ | ||
| 28 | dump->magic = CMAGIC; | ||
| 29 | dump->start_code = 0; | ||
| 30 | dump->start_stack = rdusp() & ~(PAGE_SIZE - 1); | ||
| 31 | dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT; | ||
| 32 | dump->u_dsize = ((unsigned long) (current->mm->brk + | ||
| 33 | (PAGE_SIZE-1))) >> PAGE_SHIFT; | ||
| 34 | dump->u_dsize -= dump->u_tsize; | ||
| 35 | dump->u_ssize = 0; | ||
| 36 | |||
| 37 | if (dump->start_stack < TASK_SIZE) | ||
| 38 | dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT; | ||
| 39 | |||
| 40 | dump->u_ar0 = offsetof(struct user, regs); | ||
| 41 | sw = ((struct switch_stack *)regs) - 1; | ||
| 42 | dump->regs.d1 = regs->d1; | ||
| 43 | dump->regs.d2 = regs->d2; | ||
| 44 | dump->regs.d3 = regs->d3; | ||
| 45 | dump->regs.d4 = regs->d4; | ||
| 46 | dump->regs.d5 = regs->d5; | ||
| 47 | dump->regs.d6 = sw->d6; | ||
| 48 | dump->regs.d7 = sw->d7; | ||
| 49 | dump->regs.a0 = regs->a0; | ||
| 50 | dump->regs.a1 = regs->a1; | ||
| 51 | dump->regs.a2 = regs->a2; | ||
| 52 | dump->regs.a3 = sw->a3; | ||
| 53 | dump->regs.a4 = sw->a4; | ||
| 54 | dump->regs.a5 = sw->a5; | ||
| 55 | dump->regs.a6 = sw->a6; | ||
| 56 | dump->regs.d0 = regs->d0; | ||
| 57 | dump->regs.orig_d0 = regs->orig_d0; | ||
| 58 | dump->regs.stkadj = regs->stkadj; | ||
| 59 | dump->regs.sr = regs->sr; | ||
| 60 | dump->regs.pc = regs->pc; | ||
| 61 | dump->regs.fmtvec = (regs->format << 12) | regs->vector; | ||
| 62 | /* dump floating point stuff */ | ||
| 63 | dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp); | ||
| 64 | } | ||
| 65 | |||
| 66 | #endif /* __KERNEL__ */ | ||
| 67 | #endif /* _ASM_A_OUT_CORE_H */ | ||
diff --git a/arch/m68k/include/asm/a.out.h b/arch/m68k/include/asm/a.out.h new file mode 100644 index 000000000000..3885fe43432a --- /dev/null +++ b/arch/m68k/include/asm/a.out.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | #ifndef __M68K_A_OUT_H__ | ||
| 2 | #define __M68K_A_OUT_H__ | ||
| 3 | |||
| 4 | struct exec | ||
| 5 | { | ||
| 6 | unsigned long a_info; /* Use macros N_MAGIC, etc for access */ | ||
| 7 | unsigned a_text; /* length of text, in bytes */ | ||
| 8 | unsigned a_data; /* length of data, in bytes */ | ||
| 9 | unsigned a_bss; /* length of uninitialized data area for file, in bytes */ | ||
| 10 | unsigned a_syms; /* length of symbol table data in file, in bytes */ | ||
| 11 | unsigned a_entry; /* start address */ | ||
| 12 | unsigned a_trsize; /* length of relocation info for text, in bytes */ | ||
| 13 | unsigned a_drsize; /* length of relocation info for data, in bytes */ | ||
| 14 | }; | ||
| 15 | |||
| 16 | #define N_TRSIZE(a) ((a).a_trsize) | ||
| 17 | #define N_DRSIZE(a) ((a).a_drsize) | ||
| 18 | #define N_SYMSIZE(a) ((a).a_syms) | ||
| 19 | |||
| 20 | #endif /* __M68K_A_OUT_H__ */ | ||
diff --git a/arch/m68k/include/asm/adb_iop.h b/arch/m68k/include/asm/adb_iop.h new file mode 100644 index 000000000000..8a48e56f2d62 --- /dev/null +++ b/arch/m68k/include/asm/adb_iop.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * ADB through the IOP | ||
| 3 | * Written by Joshua M. Thompson | ||
| 4 | */ | ||
| 5 | |||
| 6 | /* IOP number and channel number for ADB */ | ||
| 7 | |||
| 8 | #define ADB_IOP IOP_NUM_ISM | ||
| 9 | #define ADB_CHAN 2 | ||
| 10 | |||
| 11 | /* From the A/UX headers...maybe important, maybe not */ | ||
| 12 | |||
| 13 | #define ADB_IOP_LISTEN 0x01 | ||
| 14 | #define ADB_IOP_TALK 0x02 | ||
| 15 | #define ADB_IOP_EXISTS 0x04 | ||
| 16 | #define ADB_IOP_FLUSH 0x08 | ||
| 17 | #define ADB_IOP_RESET 0x10 | ||
| 18 | #define ADB_IOP_INT 0x20 | ||
| 19 | #define ADB_IOP_POLL 0x40 | ||
| 20 | #define ADB_IOP_UNINT 0x80 | ||
| 21 | |||
| 22 | #define AIF_RESET 0x00 | ||
| 23 | #define AIF_FLUSH 0x01 | ||
| 24 | #define AIF_LISTEN 0x08 | ||
| 25 | #define AIF_TALK 0x0C | ||
| 26 | |||
| 27 | /* Flag bits in struct adb_iopmsg */ | ||
| 28 | |||
| 29 | #define ADB_IOP_EXPLICIT 0x80 /* nonzero if explicit command */ | ||
| 30 | #define ADB_IOP_AUTOPOLL 0x40 /* auto/SRQ polling enabled */ | ||
| 31 | #define ADB_IOP_SRQ 0x04 /* SRQ detected */ | ||
| 32 | #define ADB_IOP_TIMEOUT 0x02 /* nonzero if timeout */ | ||
| 33 | |||
| 34 | #ifndef __ASSEMBLY__ | ||
| 35 | |||
| 36 | struct adb_iopmsg { | ||
| 37 | __u8 flags; /* ADB flags */ | ||
| 38 | __u8 count; /* no. of data bytes */ | ||
| 39 | __u8 cmd; /* ADB command */ | ||
| 40 | __u8 data[8]; /* ADB data */ | ||
| 41 | __u8 spare[21]; /* spare */ | ||
| 42 | }; | ||
| 43 | |||
| 44 | #endif /* __ASSEMBLY__ */ | ||
diff --git a/arch/m68k/include/asm/amigahw.h b/arch/m68k/include/asm/amigahw.h new file mode 100644 index 000000000000..5ca5dd951a4a --- /dev/null +++ b/arch/m68k/include/asm/amigahw.h | |||
| @@ -0,0 +1,350 @@ | |||
| 1 | /* | ||
| 2 | ** asm-m68k/amigahw.h -- This header defines some macros and pointers for | ||
| 3 | ** the various Amiga custom hardware registers. | ||
| 4 | ** The naming conventions used here conform to those | ||
| 5 | ** used in the Amiga Hardware Reference Manual, 3rd Edition | ||
| 6 | ** | ||
| 7 | ** Copyright 1992 by Greg Harp | ||
| 8 | ** | ||
| 9 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 10 | ** License. See the file COPYING in the main directory of this archive | ||
| 11 | ** for more details. | ||
| 12 | ** | ||
| 13 | ** Created: 9/24/92 by Greg Harp | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _M68K_AMIGAHW_H | ||
| 17 | #define _M68K_AMIGAHW_H | ||
| 18 | |||
| 19 | #include <linux/ioport.h> | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Different Amiga models | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define AMI_UNKNOWN (0) | ||
| 26 | #define AMI_500 (1) | ||
| 27 | #define AMI_500PLUS (2) | ||
| 28 | #define AMI_600 (3) | ||
| 29 | #define AMI_1000 (4) | ||
| 30 | #define AMI_1200 (5) | ||
| 31 | #define AMI_2000 (6) | ||
| 32 | #define AMI_2500 (7) | ||
| 33 | #define AMI_3000 (8) | ||
| 34 | #define AMI_3000T (9) | ||
| 35 | #define AMI_3000PLUS (10) | ||
| 36 | #define AMI_4000 (11) | ||
| 37 | #define AMI_4000T (12) | ||
| 38 | #define AMI_CDTV (13) | ||
| 39 | #define AMI_CD32 (14) | ||
| 40 | #define AMI_DRACO (15) | ||
| 41 | |||
| 42 | |||
| 43 | /* | ||
| 44 | * Chipsets | ||
| 45 | */ | ||
| 46 | |||
| 47 | extern unsigned long amiga_chipset; | ||
| 48 | |||
| 49 | #define CS_STONEAGE (0) | ||
| 50 | #define CS_OCS (1) | ||
| 51 | #define CS_ECS (2) | ||
| 52 | #define CS_AGA (3) | ||
| 53 | |||
| 54 | |||
| 55 | /* | ||
| 56 | * Miscellaneous | ||
| 57 | */ | ||
| 58 | |||
| 59 | extern unsigned long amiga_eclock; /* 700 kHz E Peripheral Clock */ | ||
| 60 | extern unsigned long amiga_colorclock; /* 3.5 MHz Color Clock */ | ||
| 61 | extern unsigned long amiga_chip_size; /* Chip RAM Size (bytes) */ | ||
| 62 | extern unsigned char amiga_vblank; /* VBLANK Frequency */ | ||
| 63 | |||
| 64 | |||
| 65 | #define AMIGAHW_DECLARE(name) unsigned name : 1 | ||
| 66 | #define AMIGAHW_SET(name) (amiga_hw_present.name = 1) | ||
| 67 | #define AMIGAHW_PRESENT(name) (amiga_hw_present.name) | ||
| 68 | |||
| 69 | struct amiga_hw_present { | ||
| 70 | /* video hardware */ | ||
| 71 | AMIGAHW_DECLARE(AMI_VIDEO); /* Amiga Video */ | ||
| 72 | AMIGAHW_DECLARE(AMI_BLITTER); /* Amiga Blitter */ | ||
| 73 | AMIGAHW_DECLARE(AMBER_FF); /* Amber Flicker Fixer */ | ||
| 74 | /* sound hardware */ | ||
| 75 | AMIGAHW_DECLARE(AMI_AUDIO); /* Amiga Audio */ | ||
| 76 | /* disk storage interfaces */ | ||
| 77 | AMIGAHW_DECLARE(AMI_FLOPPY); /* Amiga Floppy */ | ||
| 78 | AMIGAHW_DECLARE(A3000_SCSI); /* SCSI (wd33c93, A3000 alike) */ | ||
| 79 | AMIGAHW_DECLARE(A4000_SCSI); /* SCSI (ncr53c710, A4000T alike) */ | ||
| 80 | AMIGAHW_DECLARE(A1200_IDE); /* IDE (A1200 alike) */ | ||
| 81 | AMIGAHW_DECLARE(A4000_IDE); /* IDE (A4000 alike) */ | ||
| 82 | AMIGAHW_DECLARE(CD_ROM); /* CD ROM drive */ | ||
| 83 | /* other I/O hardware */ | ||
| 84 | AMIGAHW_DECLARE(AMI_KEYBOARD); /* Amiga Keyboard */ | ||
| 85 | AMIGAHW_DECLARE(AMI_MOUSE); /* Amiga Mouse */ | ||
| 86 | AMIGAHW_DECLARE(AMI_SERIAL); /* Amiga Serial */ | ||
| 87 | AMIGAHW_DECLARE(AMI_PARALLEL); /* Amiga Parallel */ | ||
| 88 | /* real time clocks */ | ||
| 89 | AMIGAHW_DECLARE(A2000_CLK); /* Hardware Clock (A2000 alike) */ | ||
| 90 | AMIGAHW_DECLARE(A3000_CLK); /* Hardware Clock (A3000 alike) */ | ||
| 91 | /* supporting hardware */ | ||
| 92 | AMIGAHW_DECLARE(CHIP_RAM); /* Chip RAM */ | ||
| 93 | AMIGAHW_DECLARE(PAULA); /* Paula (8364) */ | ||
| 94 | AMIGAHW_DECLARE(DENISE); /* Denise (8362) */ | ||
| 95 | AMIGAHW_DECLARE(DENISE_HR); /* Denise (8373) */ | ||
| 96 | AMIGAHW_DECLARE(LISA); /* Lisa (8375) */ | ||
| 97 | AMIGAHW_DECLARE(AGNUS_PAL); /* Normal/Fat PAL Agnus (8367/8371) */ | ||
| 98 | AMIGAHW_DECLARE(AGNUS_NTSC); /* Normal/Fat NTSC Agnus (8361/8370) */ | ||
| 99 | AMIGAHW_DECLARE(AGNUS_HR_PAL); /* Fat Hires PAL Agnus (8372) */ | ||
| 100 | AMIGAHW_DECLARE(AGNUS_HR_NTSC); /* Fat Hires NTSC Agnus (8372) */ | ||
| 101 | AMIGAHW_DECLARE(ALICE_PAL); /* PAL Alice (8374) */ | ||
| 102 | AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */ | ||
| 103 | AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */ | ||
| 104 | AMIGAHW_DECLARE(PCMCIA); /* PCMCIA Slot */ | ||
| 105 | AMIGAHW_DECLARE(GG2_ISA); /* GG2 Zorro2ISA Bridge */ | ||
| 106 | AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */ | ||
| 107 | AMIGAHW_DECLARE(ZORRO3); /* Zorro III */ | ||
| 108 | }; | ||
| 109 | |||
| 110 | extern struct amiga_hw_present amiga_hw_present; | ||
| 111 | |||
| 112 | struct CUSTOM { | ||
| 113 | unsigned short bltddat; | ||
| 114 | unsigned short dmaconr; | ||
| 115 | unsigned short vposr; | ||
| 116 | unsigned short vhposr; | ||
| 117 | unsigned short dskdatr; | ||
| 118 | unsigned short joy0dat; | ||
| 119 | unsigned short joy1dat; | ||
| 120 | unsigned short clxdat; | ||
| 121 | unsigned short adkconr; | ||
| 122 | unsigned short pot0dat; | ||
| 123 | unsigned short pot1dat; | ||
| 124 | unsigned short potgor; | ||
| 125 | unsigned short serdatr; | ||
| 126 | unsigned short dskbytr; | ||
| 127 | unsigned short intenar; | ||
| 128 | unsigned short intreqr; | ||
| 129 | unsigned char *dskptr; | ||
| 130 | unsigned short dsklen; | ||
| 131 | unsigned short dskdat; | ||
| 132 | unsigned short refptr; | ||
| 133 | unsigned short vposw; | ||
| 134 | unsigned short vhposw; | ||
| 135 | unsigned short copcon; | ||
| 136 | unsigned short serdat; | ||
| 137 | unsigned short serper; | ||
| 138 | unsigned short potgo; | ||
| 139 | unsigned short joytest; | ||
| 140 | unsigned short strequ; | ||
| 141 | unsigned short strvbl; | ||
| 142 | unsigned short strhor; | ||
| 143 | unsigned short strlong; | ||
| 144 | unsigned short bltcon0; | ||
| 145 | unsigned short bltcon1; | ||
| 146 | unsigned short bltafwm; | ||
| 147 | unsigned short bltalwm; | ||
| 148 | unsigned char *bltcpt; | ||
| 149 | unsigned char *bltbpt; | ||
| 150 | unsigned char *bltapt; | ||
| 151 | unsigned char *bltdpt; | ||
| 152 | unsigned short bltsize; | ||
| 153 | unsigned char pad2d; | ||
| 154 | unsigned char bltcon0l; | ||
| 155 | unsigned short bltsizv; | ||
| 156 | unsigned short bltsizh; | ||
| 157 | unsigned short bltcmod; | ||
| 158 | unsigned short bltbmod; | ||
| 159 | unsigned short bltamod; | ||
| 160 | unsigned short bltdmod; | ||
| 161 | unsigned short spare2[4]; | ||
| 162 | unsigned short bltcdat; | ||
| 163 | unsigned short bltbdat; | ||
| 164 | unsigned short bltadat; | ||
| 165 | unsigned short spare3[3]; | ||
| 166 | unsigned short deniseid; | ||
| 167 | unsigned short dsksync; | ||
| 168 | unsigned short *cop1lc; | ||
| 169 | unsigned short *cop2lc; | ||
| 170 | unsigned short copjmp1; | ||
| 171 | unsigned short copjmp2; | ||
| 172 | unsigned short copins; | ||
| 173 | unsigned short diwstrt; | ||
| 174 | unsigned short diwstop; | ||
| 175 | unsigned short ddfstrt; | ||
| 176 | unsigned short ddfstop; | ||
| 177 | unsigned short dmacon; | ||
| 178 | unsigned short clxcon; | ||
| 179 | unsigned short intena; | ||
| 180 | unsigned short intreq; | ||
| 181 | unsigned short adkcon; | ||
| 182 | struct { | ||
| 183 | unsigned short *audlc; | ||
| 184 | unsigned short audlen; | ||
| 185 | unsigned short audper; | ||
| 186 | unsigned short audvol; | ||
| 187 | unsigned short auddat; | ||
| 188 | unsigned short audspare[2]; | ||
| 189 | } aud[4]; | ||
| 190 | unsigned char *bplpt[8]; | ||
| 191 | unsigned short bplcon0; | ||
| 192 | unsigned short bplcon1; | ||
| 193 | unsigned short bplcon2; | ||
| 194 | unsigned short bplcon3; | ||
| 195 | unsigned short bpl1mod; | ||
| 196 | unsigned short bpl2mod; | ||
| 197 | unsigned short bplcon4; | ||
| 198 | unsigned short clxcon2; | ||
| 199 | unsigned short bpldat[8]; | ||
| 200 | unsigned char *sprpt[8]; | ||
| 201 | struct { | ||
| 202 | unsigned short pos; | ||
| 203 | unsigned short ctl; | ||
| 204 | unsigned short dataa; | ||
| 205 | unsigned short datab; | ||
| 206 | } spr[8]; | ||
| 207 | unsigned short color[32]; | ||
| 208 | unsigned short htotal; | ||
| 209 | unsigned short hsstop; | ||
| 210 | unsigned short hbstrt; | ||
| 211 | unsigned short hbstop; | ||
| 212 | unsigned short vtotal; | ||
| 213 | unsigned short vsstop; | ||
| 214 | unsigned short vbstrt; | ||
| 215 | unsigned short vbstop; | ||
| 216 | unsigned short sprhstrt; | ||
| 217 | unsigned short sprhstop; | ||
| 218 | unsigned short bplhstrt; | ||
| 219 | unsigned short bplhstop; | ||
| 220 | unsigned short hhposw; | ||
| 221 | unsigned short hhposr; | ||
| 222 | unsigned short beamcon0; | ||
| 223 | unsigned short hsstrt; | ||
| 224 | unsigned short vsstrt; | ||
| 225 | unsigned short hcenter; | ||
| 226 | unsigned short diwhigh; | ||
| 227 | unsigned short spare4[11]; | ||
| 228 | unsigned short fmode; | ||
| 229 | }; | ||
| 230 | |||
| 231 | /* | ||
| 232 | * DMA register bits | ||
| 233 | */ | ||
| 234 | #define DMAF_SETCLR (0x8000) | ||
| 235 | #define DMAF_AUD0 (0x0001) | ||
| 236 | #define DMAF_AUD1 (0x0002) | ||
| 237 | #define DMAF_AUD2 (0x0004) | ||
| 238 | #define DMAF_AUD3 (0x0008) | ||
| 239 | #define DMAF_DISK (0x0010) | ||
| 240 | #define DMAF_SPRITE (0x0020) | ||
| 241 | #define DMAF_BLITTER (0x0040) | ||
| 242 | #define DMAF_COPPER (0x0080) | ||
| 243 | #define DMAF_RASTER (0x0100) | ||
| 244 | #define DMAF_MASTER (0x0200) | ||
| 245 | #define DMAF_BLITHOG (0x0400) | ||
| 246 | #define DMAF_BLTNZERO (0x2000) | ||
| 247 | #define DMAF_BLTDONE (0x4000) | ||
| 248 | #define DMAF_ALL (0x01FF) | ||
| 249 | |||
| 250 | struct CIA { | ||
| 251 | unsigned char pra; char pad0[0xff]; | ||
| 252 | unsigned char prb; char pad1[0xff]; | ||
| 253 | unsigned char ddra; char pad2[0xff]; | ||
| 254 | unsigned char ddrb; char pad3[0xff]; | ||
| 255 | unsigned char talo; char pad4[0xff]; | ||
| 256 | unsigned char tahi; char pad5[0xff]; | ||
| 257 | unsigned char tblo; char pad6[0xff]; | ||
| 258 | unsigned char tbhi; char pad7[0xff]; | ||
| 259 | unsigned char todlo; char pad8[0xff]; | ||
| 260 | unsigned char todmid; char pad9[0xff]; | ||
| 261 | unsigned char todhi; char pada[0x1ff]; | ||
| 262 | unsigned char sdr; char padb[0xff]; | ||
| 263 | unsigned char icr; char padc[0xff]; | ||
| 264 | unsigned char cra; char padd[0xff]; | ||
| 265 | unsigned char crb; char pade[0xff]; | ||
| 266 | }; | ||
| 267 | |||
| 268 | #define zTwoBase (0x80000000) | ||
| 269 | #define ZTWO_PADDR(x) (((unsigned long)(x))-zTwoBase) | ||
| 270 | #define ZTWO_VADDR(x) (((unsigned long)(x))+zTwoBase) | ||
| 271 | |||
| 272 | #define CUSTOM_PHYSADDR (0xdff000) | ||
| 273 | #define amiga_custom ((*(volatile struct CUSTOM *)(zTwoBase+CUSTOM_PHYSADDR))) | ||
| 274 | |||
| 275 | #define CIAA_PHYSADDR (0xbfe001) | ||
| 276 | #define CIAB_PHYSADDR (0xbfd000) | ||
| 277 | #define ciaa ((*(volatile struct CIA *)(zTwoBase + CIAA_PHYSADDR))) | ||
| 278 | #define ciab ((*(volatile struct CIA *)(zTwoBase + CIAB_PHYSADDR))) | ||
| 279 | |||
| 280 | #define CHIP_PHYSADDR (0x000000) | ||
| 281 | |||
| 282 | void amiga_chip_init (void); | ||
| 283 | void *amiga_chip_alloc(unsigned long size, const char *name); | ||
| 284 | void *amiga_chip_alloc_res(unsigned long size, struct resource *res); | ||
| 285 | void amiga_chip_free(void *ptr); | ||
| 286 | unsigned long amiga_chip_avail( void ); /*MILAN*/ | ||
| 287 | extern volatile unsigned short amiga_audio_min_period; | ||
| 288 | |||
| 289 | static inline void amifb_video_off(void) | ||
| 290 | { | ||
| 291 | if (amiga_chipset == CS_ECS || amiga_chipset == CS_AGA) { | ||
| 292 | /* program Denise/Lisa for a higher maximum play rate */ | ||
| 293 | amiga_custom.htotal = 113; /* 31 kHz */ | ||
| 294 | amiga_custom.vtotal = 223; /* 70 Hz */ | ||
| 295 | amiga_custom.beamcon0 = 0x4390; /* HARDDIS, VAR{BEAM,VSY,HSY,CSY}EN */ | ||
| 296 | /* suspend the monitor */ | ||
| 297 | amiga_custom.hsstrt = amiga_custom.hsstop = 116; | ||
| 298 | amiga_custom.vsstrt = amiga_custom.vsstop = 226; | ||
| 299 | amiga_audio_min_period = 57; | ||
| 300 | } | ||
| 301 | } | ||
| 302 | |||
| 303 | struct tod3000 { | ||
| 304 | unsigned int :28, second2:4; /* lower digit */ | ||
| 305 | unsigned int :28, second1:4; /* upper digit */ | ||
| 306 | unsigned int :28, minute2:4; /* lower digit */ | ||
| 307 | unsigned int :28, minute1:4; /* upper digit */ | ||
| 308 | unsigned int :28, hour2:4; /* lower digit */ | ||
| 309 | unsigned int :28, hour1:4; /* upper digit */ | ||
| 310 | unsigned int :28, weekday:4; | ||
| 311 | unsigned int :28, day2:4; /* lower digit */ | ||
| 312 | unsigned int :28, day1:4; /* upper digit */ | ||
| 313 | unsigned int :28, month2:4; /* lower digit */ | ||
| 314 | unsigned int :28, month1:4; /* upper digit */ | ||
| 315 | unsigned int :28, year2:4; /* lower digit */ | ||
| 316 | unsigned int :28, year1:4; /* upper digit */ | ||
| 317 | unsigned int :28, cntrl1:4; /* control-byte 1 */ | ||
| 318 | unsigned int :28, cntrl2:4; /* control-byte 2 */ | ||
| 319 | unsigned int :28, cntrl3:4; /* control-byte 3 */ | ||
| 320 | }; | ||
| 321 | #define TOD3000_CNTRL1_HOLD 0 | ||
| 322 | #define TOD3000_CNTRL1_FREE 9 | ||
| 323 | #define tod_3000 ((*(volatile struct tod3000 *)(zTwoBase+0xDC0000))) | ||
| 324 | |||
| 325 | struct tod2000 { | ||
| 326 | unsigned int :28, second2:4; /* lower digit */ | ||
| 327 | unsigned int :28, second1:4; /* upper digit */ | ||
| 328 | unsigned int :28, minute2:4; /* lower digit */ | ||
| 329 | unsigned int :28, minute1:4; /* upper digit */ | ||
| 330 | unsigned int :28, hour2:4; /* lower digit */ | ||
| 331 | unsigned int :28, hour1:4; /* upper digit */ | ||
| 332 | unsigned int :28, day2:4; /* lower digit */ | ||
| 333 | unsigned int :28, day1:4; /* upper digit */ | ||
| 334 | unsigned int :28, month2:4; /* lower digit */ | ||
| 335 | unsigned int :28, month1:4; /* upper digit */ | ||
| 336 | unsigned int :28, year2:4; /* lower digit */ | ||
| 337 | unsigned int :28, year1:4; /* upper digit */ | ||
| 338 | unsigned int :28, weekday:4; | ||
| 339 | unsigned int :28, cntrl1:4; /* control-byte 1 */ | ||
| 340 | unsigned int :28, cntrl2:4; /* control-byte 2 */ | ||
| 341 | unsigned int :28, cntrl3:4; /* control-byte 3 */ | ||
| 342 | }; | ||
| 343 | |||
| 344 | #define TOD2000_CNTRL1_HOLD (1<<0) | ||
| 345 | #define TOD2000_CNTRL1_BUSY (1<<1) | ||
| 346 | #define TOD2000_CNTRL3_24HMODE (1<<2) | ||
| 347 | #define TOD2000_HOUR1_PM (1<<2) | ||
| 348 | #define tod_2000 ((*(volatile struct tod2000 *)(zTwoBase+0xDC0000))) | ||
| 349 | |||
| 350 | #endif /* _M68K_AMIGAHW_H */ | ||
diff --git a/arch/m68k/include/asm/amigaints.h b/arch/m68k/include/asm/amigaints.h new file mode 100644 index 000000000000..b1bcdb835ab9 --- /dev/null +++ b/arch/m68k/include/asm/amigaints.h | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | /* | ||
| 2 | ** amigaints.h -- Amiga Linux interrupt handling structs and prototypes | ||
| 3 | ** | ||
| 4 | ** Copyright 1992 by Greg Harp | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | ** Created 10/2/92 by Greg Harp | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _ASMm68k_AMIGAINTS_H_ | ||
| 14 | #define _ASMm68k_AMIGAINTS_H_ | ||
| 15 | |||
| 16 | #include <asm/irq.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | ** Amiga Interrupt sources. | ||
| 20 | ** | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define AUTO_IRQS (8) | ||
| 24 | #define AMI_STD_IRQS (14) | ||
| 25 | #define CIA_IRQS (5) | ||
| 26 | #define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */ | ||
| 27 | |||
| 28 | /* builtin serial port interrupts */ | ||
| 29 | #define IRQ_AMIGA_TBE (IRQ_USER+0) | ||
| 30 | #define IRQ_AMIGA_RBF (IRQ_USER+11) | ||
| 31 | |||
| 32 | /* floppy disk interrupts */ | ||
| 33 | #define IRQ_AMIGA_DSKBLK (IRQ_USER+1) | ||
| 34 | #define IRQ_AMIGA_DSKSYN (IRQ_USER+12) | ||
| 35 | |||
| 36 | /* software interrupts */ | ||
| 37 | #define IRQ_AMIGA_SOFT (IRQ_USER+2) | ||
| 38 | |||
| 39 | /* interrupts from external hardware */ | ||
| 40 | #define IRQ_AMIGA_PORTS IRQ_AUTO_2 | ||
| 41 | #define IRQ_AMIGA_EXTER IRQ_AUTO_6 | ||
| 42 | |||
| 43 | /* copper interrupt */ | ||
| 44 | #define IRQ_AMIGA_COPPER (IRQ_USER+4) | ||
| 45 | |||
| 46 | /* vertical blanking interrupt */ | ||
| 47 | #define IRQ_AMIGA_VERTB (IRQ_USER+5) | ||
| 48 | |||
| 49 | /* Blitter done interrupt */ | ||
| 50 | #define IRQ_AMIGA_BLIT (IRQ_USER+6) | ||
| 51 | |||
| 52 | /* Audio interrupts */ | ||
| 53 | #define IRQ_AMIGA_AUD0 (IRQ_USER+7) | ||
| 54 | #define IRQ_AMIGA_AUD1 (IRQ_USER+8) | ||
| 55 | #define IRQ_AMIGA_AUD2 (IRQ_USER+9) | ||
| 56 | #define IRQ_AMIGA_AUD3 (IRQ_USER+10) | ||
| 57 | |||
| 58 | /* CIA interrupt sources */ | ||
| 59 | #define IRQ_AMIGA_CIAA (IRQ_USER+14) | ||
| 60 | #define IRQ_AMIGA_CIAA_TA (IRQ_USER+14) | ||
| 61 | #define IRQ_AMIGA_CIAA_TB (IRQ_USER+15) | ||
| 62 | #define IRQ_AMIGA_CIAA_ALRM (IRQ_USER+16) | ||
| 63 | #define IRQ_AMIGA_CIAA_SP (IRQ_USER+17) | ||
| 64 | #define IRQ_AMIGA_CIAA_FLG (IRQ_USER+18) | ||
| 65 | #define IRQ_AMIGA_CIAB (IRQ_USER+19) | ||
| 66 | #define IRQ_AMIGA_CIAB_TA (IRQ_USER+19) | ||
| 67 | #define IRQ_AMIGA_CIAB_TB (IRQ_USER+20) | ||
| 68 | #define IRQ_AMIGA_CIAB_ALRM (IRQ_USER+21) | ||
| 69 | #define IRQ_AMIGA_CIAB_SP (IRQ_USER+22) | ||
| 70 | #define IRQ_AMIGA_CIAB_FLG (IRQ_USER+23) | ||
| 71 | |||
| 72 | |||
| 73 | /* INTREQR masks */ | ||
| 74 | #define IF_SETCLR 0x8000 /* set/clr bit */ | ||
| 75 | #define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */ | ||
| 76 | #define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */ | ||
| 77 | #define IF_DSKSYN 0x1000 /* disk sync interrupt */ | ||
| 78 | #define IF_RBF 0x0800 /* serial receive buffer full interrupt */ | ||
| 79 | #define IF_AUD3 0x0400 /* audio channel 3 done interrupt */ | ||
| 80 | #define IF_AUD2 0x0200 /* audio channel 2 done interrupt */ | ||
| 81 | #define IF_AUD1 0x0100 /* audio channel 1 done interrupt */ | ||
| 82 | #define IF_AUD0 0x0080 /* audio channel 0 done interrupt */ | ||
| 83 | #define IF_BLIT 0x0040 /* blitter done interrupt */ | ||
| 84 | #define IF_VERTB 0x0020 /* vertical blanking interrupt */ | ||
| 85 | #define IF_COPER 0x0010 /* copper interrupt */ | ||
| 86 | #define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */ | ||
| 87 | #define IF_SOFT 0x0004 /* software initiated interrupt */ | ||
| 88 | #define IF_DSKBLK 0x0002 /* diskblock DMA finished */ | ||
| 89 | #define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */ | ||
| 90 | |||
| 91 | /* CIA interrupt control register bits */ | ||
| 92 | |||
| 93 | #define CIA_ICR_TA 0x01 | ||
| 94 | #define CIA_ICR_TB 0x02 | ||
| 95 | #define CIA_ICR_ALRM 0x04 | ||
| 96 | #define CIA_ICR_SP 0x08 | ||
| 97 | #define CIA_ICR_FLG 0x10 | ||
| 98 | #define CIA_ICR_ALL 0x1f | ||
| 99 | #define CIA_ICR_SETCLR 0x80 | ||
| 100 | |||
| 101 | extern void amiga_init_IRQ(void); | ||
| 102 | |||
| 103 | /* to access the interrupt control registers of CIA's use only | ||
| 104 | ** these functions, they behave exactly like the amiga os routines | ||
| 105 | */ | ||
| 106 | |||
| 107 | extern struct ciabase ciaa_base, ciab_base; | ||
| 108 | |||
| 109 | extern void cia_init_IRQ(struct ciabase *base); | ||
| 110 | extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask); | ||
| 111 | extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask); | ||
| 112 | |||
| 113 | #endif /* asm-m68k/amigaints.h */ | ||
diff --git a/arch/m68k/include/asm/amigayle.h b/arch/m68k/include/asm/amigayle.h new file mode 100644 index 000000000000..bb5a6aa329f3 --- /dev/null +++ b/arch/m68k/include/asm/amigayle.h | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* | ||
| 2 | ** asm-m68k/amigayle.h -- This header defines the registers of the gayle chip | ||
| 3 | ** found on the Amiga 1200 | ||
| 4 | ** This information was found by disassembling card.resource, | ||
| 5 | ** so the definitions may not be 100% correct | ||
| 6 | ** anyone has an official doc ? | ||
| 7 | ** | ||
| 8 | ** Copyright 1997 by Alain Malek | ||
| 9 | ** | ||
| 10 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 11 | ** License. See the file COPYING in the main directory of this archive | ||
| 12 | ** for more details. | ||
| 13 | ** | ||
| 14 | ** Created: 11/28/97 by Alain Malek | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef _M68K_AMIGAYLE_H_ | ||
| 18 | #define _M68K_AMIGAYLE_H_ | ||
| 19 | |||
| 20 | #include <linux/types.h> | ||
| 21 | #include <asm/amigahw.h> | ||
| 22 | |||
| 23 | /* memory layout */ | ||
| 24 | |||
| 25 | #define GAYLE_RAM (0x600000+zTwoBase) | ||
| 26 | #define GAYLE_RAMSIZE (0x400000) | ||
| 27 | #define GAYLE_ATTRIBUTE (0xa00000+zTwoBase) | ||
| 28 | #define GAYLE_ATTRIBUTESIZE (0x020000) | ||
| 29 | #define GAYLE_IO (0xa20000+zTwoBase) /* 16bit and even 8bit registers */ | ||
| 30 | #define GAYLE_IOSIZE (0x010000) | ||
| 31 | #define GAYLE_IO_8BITODD (0xa30000+zTwoBase) /* odd 8bit registers */ | ||
| 32 | |||
| 33 | /* offset for accessing odd IO registers */ | ||
| 34 | #define GAYLE_ODD (GAYLE_IO_8BITODD-GAYLE_IO-1) | ||
| 35 | |||
| 36 | /* GAYLE registers */ | ||
| 37 | |||
| 38 | struct GAYLE { | ||
| 39 | u_char cardstatus; | ||
| 40 | u_char pad0[0x1000-1]; | ||
| 41 | |||
| 42 | u_char intreq; | ||
| 43 | u_char pad1[0x1000-1]; | ||
| 44 | |||
| 45 | u_char inten; | ||
| 46 | u_char pad2[0x1000-1]; | ||
| 47 | |||
| 48 | u_char config; | ||
| 49 | u_char pad3[0x1000-1]; | ||
| 50 | }; | ||
| 51 | |||
| 52 | #define GAYLE_ADDRESS (0xda8000) /* gayle main registers base address */ | ||
| 53 | |||
| 54 | #define GAYLE_RESET (0xa40000) /* write 0x00 to start reset, | ||
| 55 | read 1 byte to stop reset */ | ||
| 56 | |||
| 57 | #define gayle (*(volatile struct GAYLE *)(zTwoBase+GAYLE_ADDRESS)) | ||
| 58 | #define gayle_reset (*(volatile u_char *)(zTwoBase+GAYLE_RESET)) | ||
| 59 | |||
| 60 | #define gayle_attribute ((volatile u_char *)(GAYLE_ATTRIBUTE)) | ||
| 61 | |||
| 62 | #if 0 | ||
| 63 | #define gayle_inb(a) readb( GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) ) | ||
| 64 | #define gayle_outb(v,a) writeb( v, GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) ) | ||
| 65 | |||
| 66 | #define gayle_inw(a) readw( GAYLE_IO+(a) ) | ||
| 67 | #define gayle_outw(v,a) writew( v, GAYLE_IO+(a) ) | ||
| 68 | #endif | ||
| 69 | |||
| 70 | /* GAYLE_CARDSTATUS bit def */ | ||
| 71 | |||
| 72 | #define GAYLE_CS_CCDET 0x40 /* credit card detect */ | ||
| 73 | #define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */ | ||
| 74 | #define GAYLE_CS_SC 0x20 /* credit card status change */ | ||
| 75 | #define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */ | ||
| 76 | #define GAYLE_CS_DA 0x10 /* digital audio */ | ||
| 77 | #define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */ | ||
| 78 | #define GAYLE_CS_BSY 0x04 /* credit card busy */ | ||
| 79 | #define GAYLE_CS_IRQ 0x04 /* interrupt request */ | ||
| 80 | |||
| 81 | /* GAYLE_IRQ bit def */ | ||
| 82 | |||
| 83 | #define GAYLE_IRQ_IDE 0x80 | ||
| 84 | #define GAYLE_IRQ_CCDET 0x40 | ||
| 85 | #define GAYLE_IRQ_BVD1 0x20 | ||
| 86 | #define GAYLE_IRQ_SC 0x20 | ||
| 87 | #define GAYLE_IRQ_BVD2 0x10 | ||
| 88 | #define GAYLE_IRQ_DA 0x10 | ||
| 89 | #define GAYLE_IRQ_WR 0x08 | ||
| 90 | #define GAYLE_IRQ_BSY 0x04 | ||
| 91 | #define GAYLE_IRQ_IRQ 0x04 | ||
| 92 | #define GAYLE_IRQ_IDEACK1 0x02 | ||
| 93 | #define GAYLE_IRQ_IDEACK0 0x01 | ||
| 94 | |||
| 95 | /* GAYLE_CONFIG bit def | ||
| 96 | (bit 0-1 for program voltage, bit 2-3 for access speed */ | ||
| 97 | |||
| 98 | #define GAYLE_CFG_0V 0x00 | ||
| 99 | #define GAYLE_CFG_5V 0x01 | ||
| 100 | #define GAYLE_CFG_12V 0x02 | ||
| 101 | |||
| 102 | #define GAYLE_CFG_100NS 0x08 | ||
| 103 | #define GAYLE_CFG_150NS 0x04 | ||
| 104 | #define GAYLE_CFG_250NS 0x00 | ||
| 105 | #define GAYLE_CFG_720NS 0x0c | ||
| 106 | |||
| 107 | #endif /* asm-m68k/amigayle.h */ | ||
diff --git a/arch/m68k/include/asm/amipcmcia.h b/arch/m68k/include/asm/amipcmcia.h new file mode 100644 index 000000000000..6f1ec1887d82 --- /dev/null +++ b/arch/m68k/include/asm/amipcmcia.h | |||
| @@ -0,0 +1,110 @@ | |||
| 1 | /* | ||
| 2 | ** asm-m68k/pcmcia.h -- Amiga Linux PCMCIA Definitions | ||
| 3 | ** | ||
| 4 | ** Copyright 1997 by Alain Malek | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | ** Created: 12/10/97 by Alain Malek | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __AMIGA_PCMCIA_H__ | ||
| 14 | #define __AMIGA_PCMCIA_H__ | ||
| 15 | |||
| 16 | #include <asm/amigayle.h> | ||
| 17 | |||
| 18 | /* prototypes */ | ||
| 19 | |||
| 20 | void pcmcia_reset(void); | ||
| 21 | int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len); | ||
| 22 | void pcmcia_program_voltage(int voltage); | ||
| 23 | void pcmcia_access_speed(int speed); | ||
| 24 | void pcmcia_write_enable(void); | ||
| 25 | void pcmcia_write_disable(void); | ||
| 26 | |||
| 27 | static inline u_char pcmcia_read_status(void) | ||
| 28 | { | ||
| 29 | return (gayle.cardstatus & 0x7c); | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline u_char pcmcia_get_intreq(void) | ||
| 33 | { | ||
| 34 | return (gayle.intreq); | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline void pcmcia_ack_int(u_char intreq) | ||
| 38 | { | ||
| 39 | gayle.intreq = 0xf8; | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline void pcmcia_enable_irq(void) | ||
| 43 | { | ||
| 44 | gayle.inten |= GAYLE_IRQ_IRQ; | ||
| 45 | } | ||
| 46 | |||
| 47 | static inline void pcmcia_disable_irq(void) | ||
| 48 | { | ||
| 49 | gayle.inten &= ~GAYLE_IRQ_IRQ; | ||
| 50 | } | ||
| 51 | |||
| 52 | #define PCMCIA_INSERTED (gayle.cardstatus & GAYLE_CS_CCDET) | ||
| 53 | |||
| 54 | /* valid voltages for pcmcia_ProgramVoltage */ | ||
| 55 | |||
| 56 | #define PCMCIA_0V 0 | ||
| 57 | #define PCMCIA_5V 5 | ||
| 58 | #define PCMCIA_12V 12 | ||
| 59 | |||
| 60 | /* valid speeds for pcmcia_AccessSpeed */ | ||
| 61 | |||
| 62 | #define PCMCIA_SPEED_100NS 100 | ||
| 63 | #define PCMCIA_SPEED_150NS 150 | ||
| 64 | #define PCMCIA_SPEED_250NS 250 | ||
| 65 | #define PCMCIA_SPEED_720NS 720 | ||
| 66 | |||
| 67 | /* PCMCIA Tuple codes */ | ||
| 68 | |||
| 69 | #define CISTPL_NULL 0x00 | ||
| 70 | #define CISTPL_DEVICE 0x01 | ||
| 71 | #define CISTPL_LONGLINK_CB 0x02 | ||
| 72 | #define CISTPL_CONFIG_CB 0x04 | ||
| 73 | #define CISTPL_CFTABLE_ENTRY_CB 0x05 | ||
| 74 | #define CISTPL_LONGLINK_MFC 0x06 | ||
| 75 | #define CISTPL_BAR 0x07 | ||
| 76 | #define CISTPL_CHECKSUM 0x10 | ||
| 77 | #define CISTPL_LONGLINK_A 0x11 | ||
| 78 | #define CISTPL_LONGLINK_C 0x12 | ||
| 79 | #define CISTPL_LINKTARGET 0x13 | ||
| 80 | #define CISTPL_NO_LINK 0x14 | ||
| 81 | #define CISTPL_VERS_1 0x15 | ||
| 82 | #define CISTPL_ALTSTR 0x16 | ||
| 83 | #define CISTPL_DEVICE_A 0x17 | ||
| 84 | #define CISTPL_JEDEC_C 0x18 | ||
| 85 | #define CISTPL_JEDEC_A 0x19 | ||
| 86 | #define CISTPL_CONFIG 0x1a | ||
| 87 | #define CISTPL_CFTABLE_ENTRY 0x1b | ||
| 88 | #define CISTPL_DEVICE_OC 0x1c | ||
| 89 | #define CISTPL_DEVICE_OA 0x1d | ||
| 90 | #define CISTPL_DEVICE_GEO 0x1e | ||
| 91 | #define CISTPL_DEVICE_GEO_A 0x1f | ||
| 92 | #define CISTPL_MANFID 0x20 | ||
| 93 | #define CISTPL_FUNCID 0x21 | ||
| 94 | #define CISTPL_FUNCE 0x22 | ||
| 95 | #define CISTPL_SWIL 0x23 | ||
| 96 | #define CISTPL_END 0xff | ||
| 97 | |||
| 98 | /* FUNCID */ | ||
| 99 | |||
| 100 | #define CISTPL_FUNCID_MULTI 0x00 | ||
| 101 | #define CISTPL_FUNCID_MEMORY 0x01 | ||
| 102 | #define CISTPL_FUNCID_SERIAL 0x02 | ||
| 103 | #define CISTPL_FUNCID_PARALLEL 0x03 | ||
| 104 | #define CISTPL_FUNCID_FIXED 0x04 | ||
| 105 | #define CISTPL_FUNCID_VIDEO 0x05 | ||
| 106 | #define CISTPL_FUNCID_NETWORK 0x06 | ||
| 107 | #define CISTPL_FUNCID_AIMS 0x07 | ||
| 108 | #define CISTPL_FUNCID_SCSI 0x08 | ||
| 109 | |||
| 110 | #endif | ||
diff --git a/arch/m68k/include/asm/anchor.h b/arch/m68k/include/asm/anchor.h new file mode 100644 index 000000000000..871c0d5cfc3d --- /dev/null +++ b/arch/m68k/include/asm/anchor.h | |||
| @@ -0,0 +1,112 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * anchor.h -- Anchor CO-MEM Lite PCI host bridge part. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2000, Moreton Bay (www.moreton.com.au) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef anchor_h | ||
| 11 | #define anchor_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Define basic addressing info. | ||
| 16 | */ | ||
| 17 | #if defined(CONFIG_M5407C3) | ||
| 18 | #define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */ | ||
| 19 | #define COMEM_IRQ 25 /* IRQ of anchor part */ | ||
| 20 | #else | ||
| 21 | #define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */ | ||
| 22 | #define COMEM_IRQ 25 /* IRQ of anchor part */ | ||
| 23 | #endif | ||
| 24 | |||
| 25 | /****************************************************************************/ | ||
| 26 | |||
| 27 | /* | ||
| 28 | * 4-byte registers of CO-MEM, so adjust register addresses for | ||
| 29 | * easy access. Handy macro for word access too. | ||
| 30 | */ | ||
| 31 | #define LREG(a) ((a) >> 2) | ||
| 32 | #define WREG(a) ((a) >> 1) | ||
| 33 | |||
| 34 | |||
| 35 | /* | ||
| 36 | * Define base addresses within CO-MEM Lite register address space. | ||
| 37 | */ | ||
| 38 | #define COMEM_I2O 0x0000 /* I2O registers */ | ||
| 39 | #define COMEM_OPREGS 0x0400 /* Operation registers */ | ||
| 40 | #define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */ | ||
| 41 | #define COMEM_SHMEM 0x4000 /* Shared memory region */ | ||
| 42 | |||
| 43 | #define COMEM_SHMEMSIZE 0x4000 /* Size of shared memory */ | ||
| 44 | |||
| 45 | |||
| 46 | /* | ||
| 47 | * Define CO-MEM Registers. | ||
| 48 | */ | ||
| 49 | #define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */ | ||
| 50 | #define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */ | ||
| 51 | #define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */ | ||
| 52 | #define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */ | ||
| 53 | #define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */ | ||
| 54 | #define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */ | ||
| 55 | #define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */ | ||
| 56 | #define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */ | ||
| 57 | |||
| 58 | #define COMEM_DAHBASE 0x0460 /* Direct access base address */ | ||
| 59 | |||
| 60 | #define COMEM_NVCMD 0x04a0 /* I2C serial command */ | ||
| 61 | #define COMEM_NVREAD 0x04a4 /* I2C serial read */ | ||
| 62 | #define COMEM_NVSTAT 0x04a8 /* I2C status */ | ||
| 63 | |||
| 64 | #define COMEM_DMALBASE 0x04b0 /* DMA local base address */ | ||
| 65 | #define COMEM_DMAHBASE 0x04b4 /* DMA host base address */ | ||
| 66 | #define COMEM_DMASIZE 0x04b8 /* DMA size */ | ||
| 67 | #define COMEM_DMACTL 0x04bc /* DMA control */ | ||
| 68 | |||
| 69 | #define COMEM_HCTL 0x04e0 /* Host control */ | ||
| 70 | #define COMEM_HINT 0x04e4 /* Host interrupt control/status */ | ||
| 71 | #define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */ | ||
| 72 | #define COMEM_LINT 0x04f4 /* Local interrupt contole status */ | ||
| 73 | #define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */ | ||
| 74 | |||
| 75 | #define COMEM_LBUSCFG 0x04fc /* Local bus configuration */ | ||
| 76 | |||
| 77 | |||
| 78 | /* | ||
| 79 | * Commands and flags for use with Direct Access Register. | ||
| 80 | */ | ||
| 81 | #define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */ | ||
| 82 | #define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */ | ||
| 83 | #define COMEM_DA_MEMRD 0x00000004 /* Memory read cycle */ | ||
| 84 | #define COMEM_DA_MEMWR 0x00000004 /* Memory write cycle */ | ||
| 85 | #define COMEM_DA_IORD 0x00000002 /* I/O read cycle */ | ||
| 86 | #define COMEM_DA_IOWR 0x00000002 /* I/O write cycle */ | ||
| 87 | #define COMEM_DA_CFGRD 0x00000006 /* Configuration read cycle */ | ||
| 88 | #define COMEM_DA_CFGWR 0x00000006 /* Configuration write cycle */ | ||
| 89 | |||
| 90 | #define COMEM_DA_ADDR(a) ((a) & 0xffffe000) | ||
| 91 | |||
| 92 | #define COMEM_DA_OFFSET(a) ((a) & 0x00001fff) | ||
| 93 | |||
| 94 | |||
| 95 | /* | ||
| 96 | * The PCI bus will be limited in what slots will actually be used. | ||
| 97 | * Define valid device numbers for different boards. | ||
| 98 | */ | ||
| 99 | #if defined(CONFIG_M5407C3) | ||
| 100 | #define COMEM_MINDEV 14 /* Minimum valid DEVICE */ | ||
| 101 | #define COMEM_MAXDEV 14 /* Maximum valid DEVICE */ | ||
| 102 | #define COMEM_BRIDGEDEV 15 /* Slot bridge is in */ | ||
| 103 | #else | ||
| 104 | #define COMEM_MINDEV 0 /* Minimum valid DEVICE */ | ||
| 105 | #define COMEM_MAXDEV 3 /* Maximum valid DEVICE */ | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */ | ||
| 109 | |||
| 110 | |||
| 111 | /****************************************************************************/ | ||
| 112 | #endif /* anchor_h */ | ||
diff --git a/arch/m68k/include/asm/apollodma.h b/arch/m68k/include/asm/apollodma.h new file mode 100644 index 000000000000..954adc851adb --- /dev/null +++ b/arch/m68k/include/asm/apollodma.h | |||
| @@ -0,0 +1,248 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm/dma.h: Defines for using and allocating dma channels. | ||
| 3 | * Written by Hennus Bergman, 1992. | ||
| 4 | * High DMA channel support & info by Hannu Savolainen | ||
| 5 | * and John Boyd, Nov. 1992. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _ASM_APOLLO_DMA_H | ||
| 9 | #define _ASM_APOLLO_DMA_H | ||
| 10 | |||
| 11 | #include <asm/apollohw.h> /* need byte IO */ | ||
| 12 | #include <linux/spinlock.h> /* And spinlocks */ | ||
| 13 | #include <linux/delay.h> | ||
| 14 | |||
| 15 | |||
| 16 | #define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val)) | ||
| 17 | #define dma_inb(addr) (*((volatile unsigned char *)(addr+IO_BASE))) | ||
| 18 | |||
| 19 | /* | ||
| 20 | * NOTES about DMA transfers: | ||
| 21 | * | ||
| 22 | * controller 1: channels 0-3, byte operations, ports 00-1F | ||
| 23 | * controller 2: channels 4-7, word operations, ports C0-DF | ||
| 24 | * | ||
| 25 | * - ALL registers are 8 bits only, regardless of transfer size | ||
| 26 | * - channel 4 is not used - cascades 1 into 2. | ||
| 27 | * - channels 0-3 are byte - addresses/counts are for physical bytes | ||
| 28 | * - channels 5-7 are word - addresses/counts are for physical words | ||
| 29 | * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries | ||
| 30 | * - transfer count loaded to registers is 1 less than actual count | ||
| 31 | * - controller 2 offsets are all even (2x offsets for controller 1) | ||
| 32 | * - page registers for 5-7 don't use data bit 0, represent 128K pages | ||
| 33 | * - page registers for 0-3 use bit 0, represent 64K pages | ||
| 34 | * | ||
| 35 | * DMA transfers are limited to the lower 16MB of _physical_ memory. | ||
| 36 | * Note that addresses loaded into registers must be _physical_ addresses, | ||
| 37 | * not logical addresses (which may differ if paging is active). | ||
| 38 | * | ||
| 39 | * Address mapping for channels 0-3: | ||
| 40 | * | ||
| 41 | * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) | ||
| 42 | * | ... | | ... | | ... | | ||
| 43 | * | ... | | ... | | ... | | ||
| 44 | * | ... | | ... | | ... | | ||
| 45 | * P7 ... P0 A7 ... A0 A7 ... A0 | ||
| 46 | * | Page | Addr MSB | Addr LSB | (DMA registers) | ||
| 47 | * | ||
| 48 | * Address mapping for channels 5-7: | ||
| 49 | * | ||
| 50 | * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) | ||
| 51 | * | ... | \ \ ... \ \ \ ... \ \ | ||
| 52 | * | ... | \ \ ... \ \ \ ... \ (not used) | ||
| 53 | * | ... | \ \ ... \ \ \ ... \ | ||
| 54 | * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 | ||
| 55 | * | Page | Addr MSB | Addr LSB | (DMA registers) | ||
| 56 | * | ||
| 57 | * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses | ||
| 58 | * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at | ||
| 59 | * the hardware level, so odd-byte transfers aren't possible). | ||
| 60 | * | ||
| 61 | * Transfer count (_not # bytes_) is limited to 64K, represented as actual | ||
| 62 | * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, | ||
| 63 | * and up to 128K bytes may be transferred on channels 5-7 in one operation. | ||
| 64 | * | ||
| 65 | */ | ||
| 66 | |||
| 67 | #define MAX_DMA_CHANNELS 8 | ||
| 68 | |||
| 69 | /* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000) | ||
| 70 | |||
| 71 | /* 8237 DMA controllers */ | ||
| 72 | #define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */ | ||
| 73 | #define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */ | ||
| 74 | |||
| 75 | /* DMA controller registers */ | ||
| 76 | #define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */ | ||
| 77 | #define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */ | ||
| 78 | #define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */ | ||
| 79 | #define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */ | ||
| 80 | #define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */ | ||
| 81 | #define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */ | ||
| 82 | #define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */ | ||
| 83 | #define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */ | ||
| 84 | #define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */ | ||
| 85 | #define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */ | ||
| 86 | |||
| 87 | #define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */ | ||
| 88 | #define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */ | ||
| 89 | #define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */ | ||
| 90 | #define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */ | ||
| 91 | #define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */ | ||
| 92 | #define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */ | ||
| 93 | #define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */ | ||
| 94 | #define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */ | ||
| 95 | #define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */ | ||
| 96 | #define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */ | ||
| 97 | |||
| 98 | #define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */ | ||
| 99 | #define DMA_ADDR_1 (IO_DMA1_BASE+0x02) | ||
| 100 | #define DMA_ADDR_2 (IO_DMA1_BASE+0x04) | ||
| 101 | #define DMA_ADDR_3 (IO_DMA1_BASE+0x06) | ||
| 102 | #define DMA_ADDR_4 (IO_DMA2_BASE+0x00) | ||
| 103 | #define DMA_ADDR_5 (IO_DMA2_BASE+0x04) | ||
| 104 | #define DMA_ADDR_6 (IO_DMA2_BASE+0x08) | ||
| 105 | #define DMA_ADDR_7 (IO_DMA2_BASE+0x0C) | ||
| 106 | |||
| 107 | #define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */ | ||
| 108 | #define DMA_CNT_1 (IO_DMA1_BASE+0x03) | ||
| 109 | #define DMA_CNT_2 (IO_DMA1_BASE+0x05) | ||
| 110 | #define DMA_CNT_3 (IO_DMA1_BASE+0x07) | ||
| 111 | #define DMA_CNT_4 (IO_DMA2_BASE+0x02) | ||
| 112 | #define DMA_CNT_5 (IO_DMA2_BASE+0x06) | ||
| 113 | #define DMA_CNT_6 (IO_DMA2_BASE+0x0A) | ||
| 114 | #define DMA_CNT_7 (IO_DMA2_BASE+0x0E) | ||
| 115 | |||
| 116 | #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ | ||
| 117 | #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ | ||
| 118 | #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ | ||
| 119 | |||
| 120 | #define DMA_AUTOINIT 0x10 | ||
| 121 | |||
| 122 | #define DMA_8BIT 0 | ||
| 123 | #define DMA_16BIT 1 | ||
| 124 | #define DMA_BUSMASTER 2 | ||
| 125 | |||
| 126 | extern spinlock_t dma_spin_lock; | ||
| 127 | |||
| 128 | static __inline__ unsigned long claim_dma_lock(void) | ||
| 129 | { | ||
| 130 | unsigned long flags; | ||
| 131 | spin_lock_irqsave(&dma_spin_lock, flags); | ||
| 132 | return flags; | ||
| 133 | } | ||
| 134 | |||
| 135 | static __inline__ void release_dma_lock(unsigned long flags) | ||
| 136 | { | ||
| 137 | spin_unlock_irqrestore(&dma_spin_lock, flags); | ||
| 138 | } | ||
| 139 | |||
| 140 | /* enable/disable a specific DMA channel */ | ||
| 141 | static __inline__ void enable_dma(unsigned int dmanr) | ||
| 142 | { | ||
| 143 | if (dmanr<=3) | ||
| 144 | dma_outb(dmanr, DMA1_MASK_REG); | ||
| 145 | else | ||
| 146 | dma_outb(dmanr & 3, DMA2_MASK_REG); | ||
| 147 | } | ||
| 148 | |||
| 149 | static __inline__ void disable_dma(unsigned int dmanr) | ||
| 150 | { | ||
| 151 | if (dmanr<=3) | ||
| 152 | dma_outb(dmanr | 4, DMA1_MASK_REG); | ||
| 153 | else | ||
| 154 | dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); | ||
| 155 | } | ||
| 156 | |||
| 157 | /* Clear the 'DMA Pointer Flip Flop'. | ||
| 158 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | ||
| 159 | * Use this once to initialize the FF to a known state. | ||
| 160 | * After that, keep track of it. :-) | ||
| 161 | * --- In order to do that, the DMA routines below should --- | ||
| 162 | * --- only be used while holding the DMA lock ! --- | ||
| 163 | */ | ||
| 164 | static __inline__ void clear_dma_ff(unsigned int dmanr) | ||
| 165 | { | ||
| 166 | if (dmanr<=3) | ||
| 167 | dma_outb(0, DMA1_CLEAR_FF_REG); | ||
| 168 | else | ||
| 169 | dma_outb(0, DMA2_CLEAR_FF_REG); | ||
| 170 | } | ||
| 171 | |||
| 172 | /* set mode (above) for a specific DMA channel */ | ||
| 173 | static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | ||
| 174 | { | ||
| 175 | if (dmanr<=3) | ||
| 176 | dma_outb(mode | dmanr, DMA1_MODE_REG); | ||
| 177 | else | ||
| 178 | dma_outb(mode | (dmanr&3), DMA2_MODE_REG); | ||
| 179 | } | ||
| 180 | |||
| 181 | /* Set transfer address & page bits for specific DMA channel. | ||
| 182 | * Assumes dma flipflop is clear. | ||
| 183 | */ | ||
| 184 | static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) | ||
| 185 | { | ||
| 186 | if (dmanr <= 3) { | ||
| 187 | dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); | ||
| 188 | dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); | ||
| 189 | } else { | ||
| 190 | dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); | ||
| 191 | dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); | ||
| 192 | } | ||
| 193 | } | ||
| 194 | |||
| 195 | |||
| 196 | /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for | ||
| 197 | * a specific DMA channel. | ||
| 198 | * You must ensure the parameters are valid. | ||
| 199 | * NOTE: from a manual: "the number of transfers is one more | ||
| 200 | * than the initial word count"! This is taken into account. | ||
| 201 | * Assumes dma flip-flop is clear. | ||
| 202 | * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. | ||
| 203 | */ | ||
| 204 | static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) | ||
| 205 | { | ||
| 206 | count--; | ||
| 207 | if (dmanr <= 3) { | ||
| 208 | dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); | ||
| 209 | dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); | ||
| 210 | } else { | ||
| 211 | dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); | ||
| 212 | dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); | ||
| 213 | } | ||
| 214 | } | ||
| 215 | |||
| 216 | |||
| 217 | /* Get DMA residue count. After a DMA transfer, this | ||
| 218 | * should return zero. Reading this while a DMA transfer is | ||
| 219 | * still in progress will return unpredictable results. | ||
| 220 | * If called before the channel has been used, it may return 1. | ||
| 221 | * Otherwise, it returns the number of _bytes_ left to transfer. | ||
| 222 | * | ||
| 223 | * Assumes DMA flip-flop is clear. | ||
| 224 | */ | ||
| 225 | static __inline__ int get_dma_residue(unsigned int dmanr) | ||
| 226 | { | ||
| 227 | unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE | ||
| 228 | : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; | ||
| 229 | |||
| 230 | /* using short to get 16-bit wrap around */ | ||
| 231 | unsigned short count; | ||
| 232 | |||
| 233 | count = 1 + dma_inb(io_port); | ||
| 234 | count += dma_inb(io_port) << 8; | ||
| 235 | |||
| 236 | return (dmanr<=3)? count : (count<<1); | ||
| 237 | } | ||
| 238 | |||
| 239 | |||
| 240 | /* These are in kernel/dma.c: */ | ||
| 241 | extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ | ||
| 242 | extern void free_dma(unsigned int dmanr); /* release it again */ | ||
| 243 | |||
| 244 | /* These are in arch/m68k/apollo/dma.c: */ | ||
| 245 | extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type); | ||
| 246 | extern void dma_unmap_page(unsigned short dma_addr); | ||
| 247 | |||
| 248 | #endif /* _ASM_APOLLO_DMA_H */ | ||
diff --git a/arch/m68k/include/asm/apollohw.h b/arch/m68k/include/asm/apollohw.h new file mode 100644 index 000000000000..a1373b9aa281 --- /dev/null +++ b/arch/m68k/include/asm/apollohw.h | |||
| @@ -0,0 +1,108 @@ | |||
| 1 | /* apollohw.h : some structures to access apollo HW */ | ||
| 2 | |||
| 3 | #ifndef _ASMm68k_APOLLOHW_H_ | ||
| 4 | #define _ASMm68k_APOLLOHW_H_ | ||
| 5 | |||
| 6 | #include <linux/types.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | apollo models | ||
| 10 | */ | ||
| 11 | |||
| 12 | extern u_long apollo_model; | ||
| 13 | |||
| 14 | #define APOLLO_UNKNOWN (0) | ||
| 15 | #define APOLLO_DN3000 (1) | ||
| 16 | #define APOLLO_DN3010 (2) | ||
| 17 | #define APOLLO_DN3500 (3) | ||
| 18 | #define APOLLO_DN4000 (4) | ||
| 19 | #define APOLLO_DN4500 (5) | ||
| 20 | |||
| 21 | /* | ||
| 22 | see scn2681 data sheet for more info. | ||
| 23 | member names are read_write. | ||
| 24 | */ | ||
| 25 | |||
| 26 | #define DECLARE_2681_FIELD(x) unsigned char x; unsigned char dummy##x | ||
| 27 | |||
| 28 | struct SCN2681 { | ||
| 29 | |||
| 30 | DECLARE_2681_FIELD(mra); | ||
| 31 | DECLARE_2681_FIELD(sra_csra); | ||
| 32 | DECLARE_2681_FIELD(BRGtest_cra); | ||
| 33 | DECLARE_2681_FIELD(rhra_thra); | ||
| 34 | DECLARE_2681_FIELD(ipcr_acr); | ||
| 35 | DECLARE_2681_FIELD(isr_imr); | ||
| 36 | DECLARE_2681_FIELD(ctu_ctur); | ||
| 37 | DECLARE_2681_FIELD(ctl_ctlr); | ||
| 38 | DECLARE_2681_FIELD(mrb); | ||
| 39 | DECLARE_2681_FIELD(srb_csrb); | ||
| 40 | DECLARE_2681_FIELD(tst_crb); | ||
| 41 | DECLARE_2681_FIELD(rhrb_thrb); | ||
| 42 | DECLARE_2681_FIELD(reserved); | ||
| 43 | DECLARE_2681_FIELD(ip_opcr); | ||
| 44 | DECLARE_2681_FIELD(startCnt_setOutBit); | ||
| 45 | DECLARE_2681_FIELD(stopCnt_resetOutBit); | ||
| 46 | |||
| 47 | }; | ||
| 48 | |||
| 49 | #if 0 | ||
| 50 | struct mc146818 { | ||
| 51 | |||
| 52 | unsigned int second1:4, second2:4, alarm_second1:4, alarm_second2:4, | ||
| 53 | minute1:4, minute2:4, alarm_minute1:4, alarm_minute2:4; | ||
| 54 | unsigned int hours1:4, hours2:4, alarm_hours1:4, alarm_hours2:4, | ||
| 55 | day_of_week1:4, day_of_week2:4, day_of_month1:4, day_of_month2:4; | ||
| 56 | unsigned int month1:4, month2:4, year1:4, year2:4, :16; | ||
| 57 | |||
| 58 | }; | ||
| 59 | #endif | ||
| 60 | |||
| 61 | struct mc146818 { | ||
| 62 | unsigned char second, alarm_second; | ||
| 63 | unsigned char minute, alarm_minute; | ||
| 64 | unsigned char hours, alarm_hours; | ||
| 65 | unsigned char day_of_week, day_of_month; | ||
| 66 | unsigned char month, year; | ||
| 67 | }; | ||
| 68 | |||
| 69 | |||
| 70 | #define IO_BASE 0x80000000 | ||
| 71 | |||
| 72 | extern u_long sio01_physaddr; | ||
| 73 | extern u_long sio23_physaddr; | ||
| 74 | extern u_long rtc_physaddr; | ||
| 75 | extern u_long pica_physaddr; | ||
| 76 | extern u_long picb_physaddr; | ||
| 77 | extern u_long cpuctrl_physaddr; | ||
| 78 | extern u_long timer_physaddr; | ||
| 79 | |||
| 80 | #define SAU7_SIO01_PHYSADDR 0x10400 | ||
| 81 | #define SAU7_SIO23_PHYSADDR 0x10500 | ||
| 82 | #define SAU7_RTC_PHYSADDR 0x10900 | ||
| 83 | #define SAU7_PICA 0x11000 | ||
| 84 | #define SAU7_PICB 0x11100 | ||
| 85 | #define SAU7_CPUCTRL 0x10100 | ||
| 86 | #define SAU7_TIMER 0x010800 | ||
| 87 | |||
| 88 | #define SAU8_SIO01_PHYSADDR 0x8400 | ||
| 89 | #define SAU8_RTC_PHYSADDR 0x8900 | ||
| 90 | #define SAU8_PICA 0x9400 | ||
| 91 | #define SAU8_PICB 0x9500 | ||
| 92 | #define SAU8_CPUCTRL 0x8100 | ||
| 93 | #define SAU8_TIMER 0x8800 | ||
| 94 | |||
| 95 | #define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr))) | ||
| 96 | #define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr))) | ||
| 97 | #define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr))) | ||
| 98 | #define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr)) | ||
| 99 | #define pica (IO_BASE + pica_physaddr) | ||
| 100 | #define picb (IO_BASE + picb_physaddr) | ||
| 101 | #define timer (IO_BASE + timer_physaddr) | ||
| 102 | #define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000)) | ||
| 103 | |||
| 104 | #define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE) | ||
| 105 | |||
| 106 | #define IRQ_APOLLO IRQ_USER | ||
| 107 | |||
| 108 | #endif | ||
diff --git a/arch/m68k/include/asm/atafd.h b/arch/m68k/include/asm/atafd.h new file mode 100644 index 000000000000..8456889ee7da --- /dev/null +++ b/arch/m68k/include/asm/atafd.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef _ASM_M68K_FD_H | ||
| 2 | #define _ASM_M68K_FD_H | ||
| 3 | |||
| 4 | /* Definitions for the Atari Floppy driver */ | ||
| 5 | |||
| 6 | struct atari_format_descr { | ||
| 7 | int track; /* to be formatted */ | ||
| 8 | int head; /* "" "" */ | ||
| 9 | int sect_offset; /* offset of first sector */ | ||
| 10 | }; | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/arch/m68k/include/asm/atafdreg.h b/arch/m68k/include/asm/atafdreg.h new file mode 100644 index 000000000000..bbf80949fd9f --- /dev/null +++ b/arch/m68k/include/asm/atafdreg.h | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | #ifndef _LINUX_FDREG_H | ||
| 2 | #define _LINUX_FDREG_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | ** WD1772 stuff | ||
| 6 | */ | ||
| 7 | |||
| 8 | /* register codes */ | ||
| 9 | |||
| 10 | #define FDCSELREG_STP (0x80) /* command/status register */ | ||
| 11 | #define FDCSELREG_TRA (0x82) /* track register */ | ||
| 12 | #define FDCSELREG_SEC (0x84) /* sector register */ | ||
| 13 | #define FDCSELREG_DTA (0x86) /* data register */ | ||
| 14 | |||
| 15 | /* register names for FDC_READ/WRITE macros */ | ||
| 16 | |||
| 17 | #define FDCREG_CMD 0 | ||
| 18 | #define FDCREG_STATUS 0 | ||
| 19 | #define FDCREG_TRACK 2 | ||
| 20 | #define FDCREG_SECTOR 4 | ||
| 21 | #define FDCREG_DATA 6 | ||
| 22 | |||
| 23 | /* command opcodes */ | ||
| 24 | |||
| 25 | #define FDCCMD_RESTORE (0x00) /* - */ | ||
| 26 | #define FDCCMD_SEEK (0x10) /* | */ | ||
| 27 | #define FDCCMD_STEP (0x20) /* | TYP 1 Commands */ | ||
| 28 | #define FDCCMD_STIN (0x40) /* | */ | ||
| 29 | #define FDCCMD_STOT (0x60) /* - */ | ||
| 30 | #define FDCCMD_RDSEC (0x80) /* - TYP 2 Commands */ | ||
| 31 | #define FDCCMD_WRSEC (0xa0) /* - " */ | ||
| 32 | #define FDCCMD_RDADR (0xc0) /* - */ | ||
| 33 | #define FDCCMD_RDTRA (0xe0) /* | TYP 3 Commands */ | ||
| 34 | #define FDCCMD_WRTRA (0xf0) /* - */ | ||
| 35 | #define FDCCMD_FORCI (0xd0) /* - TYP 4 Command */ | ||
| 36 | |||
| 37 | /* command modifier bits */ | ||
| 38 | |||
| 39 | #define FDCCMDADD_SR6 (0x00) /* step rate settings */ | ||
| 40 | #define FDCCMDADD_SR12 (0x01) | ||
| 41 | #define FDCCMDADD_SR2 (0x02) | ||
| 42 | #define FDCCMDADD_SR3 (0x03) | ||
| 43 | #define FDCCMDADD_V (0x04) /* verify */ | ||
| 44 | #define FDCCMDADD_H (0x08) /* wait for spin-up */ | ||
| 45 | #define FDCCMDADD_U (0x10) /* update track register */ | ||
| 46 | #define FDCCMDADD_M (0x10) /* multiple sector access */ | ||
| 47 | #define FDCCMDADD_E (0x04) /* head settling flag */ | ||
| 48 | #define FDCCMDADD_P (0x02) /* precompensation off */ | ||
| 49 | #define FDCCMDADD_A0 (0x01) /* DAM flag */ | ||
| 50 | |||
| 51 | /* status register bits */ | ||
| 52 | |||
| 53 | #define FDCSTAT_MOTORON (0x80) /* motor on */ | ||
| 54 | #define FDCSTAT_WPROT (0x40) /* write protected (FDCCMD_WR*) */ | ||
| 55 | #define FDCSTAT_SPINUP (0x20) /* motor speed stable (Type I) */ | ||
| 56 | #define FDCSTAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */ | ||
| 57 | #define FDCSTAT_RECNF (0x10) /* record not found */ | ||
| 58 | #define FDCSTAT_CRC (0x08) /* CRC error */ | ||
| 59 | #define FDCSTAT_TR00 (0x04) /* Track 00 flag (Type I) */ | ||
| 60 | #define FDCSTAT_LOST (0x04) /* Lost Data (Type II+III) */ | ||
| 61 | #define FDCSTAT_IDX (0x02) /* Index status (Type I) */ | ||
| 62 | #define FDCSTAT_DRQ (0x02) /* DRQ status (Type II+III) */ | ||
| 63 | #define FDCSTAT_BUSY (0x01) /* FDC is busy */ | ||
| 64 | |||
| 65 | |||
| 66 | /* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */ | ||
| 67 | #define DSKSIDE (0x01) | ||
| 68 | |||
| 69 | #define DSKDRVNONE (0x06) | ||
| 70 | #define DSKDRV0 (0x02) | ||
| 71 | #define DSKDRV1 (0x04) | ||
| 72 | |||
| 73 | /* step rates */ | ||
| 74 | #define FDCSTEP_6 0x00 | ||
| 75 | #define FDCSTEP_12 0x01 | ||
| 76 | #define FDCSTEP_2 0x02 | ||
| 77 | #define FDCSTEP_3 0x03 | ||
| 78 | |||
| 79 | #endif | ||
diff --git a/arch/m68k/include/asm/atari_joystick.h b/arch/m68k/include/asm/atari_joystick.h new file mode 100644 index 000000000000..93be7da9f2c7 --- /dev/null +++ b/arch/m68k/include/asm/atari_joystick.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | #ifndef _LINUX_ATARI_JOYSTICK_H | ||
| 2 | #define _LINUX_ATARI_JOYSTICK_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * linux/include/linux/atari_joystick.h | ||
| 6 | * header file for Atari Joystick driver | ||
| 7 | * by Robert de Vries (robert@and.nl) on 19Jul93 | ||
| 8 | */ | ||
| 9 | |||
| 10 | void atari_joystick_interrupt(char*); | ||
| 11 | int atari_joystick_init(void); | ||
| 12 | extern int atari_mouse_buttons; | ||
| 13 | |||
| 14 | struct joystick_status { | ||
| 15 | char fire; | ||
| 16 | char dir; | ||
| 17 | int ready; | ||
| 18 | int active; | ||
| 19 | wait_queue_head_t wait; | ||
| 20 | }; | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/arch/m68k/include/asm/atari_stdma.h b/arch/m68k/include/asm/atari_stdma.h new file mode 100644 index 000000000000..8e389b7fa70c --- /dev/null +++ b/arch/m68k/include/asm/atari_stdma.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | |||
| 2 | #ifndef _atari_stdma_h | ||
| 3 | #define _atari_stdma_h | ||
| 4 | |||
| 5 | |||
| 6 | #include <linux/interrupt.h> | ||
| 7 | |||
| 8 | |||
| 9 | /***************************** Prototypes *****************************/ | ||
| 10 | |||
| 11 | void stdma_lock(irq_handler_t handler, void *data); | ||
| 12 | void stdma_release( void ); | ||
| 13 | int stdma_others_waiting( void ); | ||
| 14 | int stdma_islocked( void ); | ||
| 15 | void *stdma_locked_by( void ); | ||
| 16 | void stdma_init( void ); | ||
| 17 | |||
| 18 | /************************* End of Prototypes **************************/ | ||
| 19 | |||
| 20 | |||
| 21 | |||
| 22 | #endif /* _atari_stdma_h */ | ||
diff --git a/arch/m68k/include/asm/atari_stram.h b/arch/m68k/include/asm/atari_stram.h new file mode 100644 index 000000000000..7546d13963be --- /dev/null +++ b/arch/m68k/include/asm/atari_stram.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | #ifndef _M68K_ATARI_STRAM_H | ||
| 2 | #define _M68K_ATARI_STRAM_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Functions for Atari ST-RAM management | ||
| 6 | */ | ||
| 7 | |||
| 8 | /* public interface */ | ||
| 9 | void *atari_stram_alloc(long size, const char *owner); | ||
| 10 | void atari_stram_free(void *); | ||
| 11 | |||
| 12 | /* functions called internally by other parts of the kernel */ | ||
| 13 | void atari_stram_init(void); | ||
| 14 | void atari_stram_reserve_pages(void *start_mem); | ||
| 15 | void atari_stram_mem_init_hook (void); | ||
| 16 | |||
| 17 | #endif /*_M68K_ATARI_STRAM_H */ | ||
diff --git a/arch/m68k/include/asm/atarihw.h b/arch/m68k/include/asm/atarihw.h new file mode 100644 index 000000000000..1412b4ab202f --- /dev/null +++ b/arch/m68k/include/asm/atarihw.h | |||
| @@ -0,0 +1,807 @@ | |||
| 1 | /* | ||
| 2 | ** linux/atarihw.h -- This header defines some macros and pointers for | ||
| 3 | ** the various Atari custom hardware registers. | ||
| 4 | ** | ||
| 5 | ** Copyright 1994 by Björn Brauel | ||
| 6 | ** | ||
| 7 | ** 5/1/94 Roman Hodek: | ||
| 8 | ** Added definitions for TT specific chips. | ||
| 9 | ** | ||
| 10 | ** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>: | ||
| 11 | ** Finally added definitions for the matrix/codec and the DSP56001 host | ||
| 12 | ** interface. | ||
| 13 | ** | ||
| 14 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 15 | ** License. See the file COPYING in the main directory of this archive | ||
| 16 | ** for more details. | ||
| 17 | ** | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _LINUX_ATARIHW_H_ | ||
| 21 | #define _LINUX_ATARIHW_H_ | ||
| 22 | |||
| 23 | #include <linux/types.h> | ||
| 24 | #include <asm/bootinfo.h> | ||
| 25 | #include <asm/raw_io.h> | ||
| 26 | |||
| 27 | extern u_long atari_mch_cookie; | ||
| 28 | extern u_long atari_mch_type; | ||
| 29 | extern u_long atari_switches; | ||
| 30 | extern int atari_rtc_year_offset; | ||
| 31 | extern int atari_dont_touch_floppy_select; | ||
| 32 | |||
| 33 | /* convenience macros for testing machine type */ | ||
| 34 | #define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) | ||
| 35 | #define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ | ||
| 36 | (atari_mch_cookie & 0xffff) == 0) | ||
| 37 | #define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ | ||
| 38 | (atari_mch_cookie & 0xffff) == 0x10) | ||
| 39 | #define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT) | ||
| 40 | #define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON) | ||
| 41 | #define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA) | ||
| 42 | #define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40) | ||
| 43 | |||
| 44 | /* values for atari_switches */ | ||
| 45 | #define ATARI_SWITCH_IKBD 0x01 | ||
| 46 | #define ATARI_SWITCH_MIDI 0x02 | ||
| 47 | #define ATARI_SWITCH_SND6 0x04 | ||
| 48 | #define ATARI_SWITCH_SND7 0x08 | ||
| 49 | #define ATARI_SWITCH_OVSC_SHIFT 16 | ||
| 50 | #define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT) | ||
| 51 | #define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT) | ||
| 52 | #define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT) | ||
| 53 | #define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT) | ||
| 54 | #define ATARI_SWITCH_OVSC_MASK 0xffff0000 | ||
| 55 | |||
| 56 | /* | ||
| 57 | * Define several Hardware-Chips for indication so that for the ATARI we do | ||
| 58 | * no longer decide whether it is a Falcon or other machine . It's just | ||
| 59 | * important what hardware the machine uses | ||
| 60 | */ | ||
| 61 | |||
| 62 | /* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */ | ||
| 63 | |||
| 64 | #define ATARIHW_DECLARE(name) unsigned name : 1 | ||
| 65 | #define ATARIHW_SET(name) (atari_hw_present.name = 1) | ||
| 66 | #define ATARIHW_PRESENT(name) (atari_hw_present.name) | ||
| 67 | |||
| 68 | struct atari_hw_present { | ||
| 69 | /* video hardware */ | ||
| 70 | ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */ | ||
| 71 | ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */ | ||
| 72 | ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */ | ||
| 73 | ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */ | ||
| 74 | /* sound hardware */ | ||
| 75 | ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */ | ||
| 76 | ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */ | ||
| 77 | ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */ | ||
| 78 | /* disk storage interfaces */ | ||
| 79 | ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */ | ||
| 80 | ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */ | ||
| 81 | ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */ | ||
| 82 | ATARIHW_DECLARE(IDE); /* IDE Interface */ | ||
| 83 | ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */ | ||
| 84 | /* other I/O hardware */ | ||
| 85 | ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari | ||
| 86 | without it... but who knows?) */ | ||
| 87 | ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */ | ||
| 88 | ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */ | ||
| 89 | ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */ | ||
| 90 | ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe | ||
| 91 | and Falcon */ | ||
| 92 | ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */ | ||
| 93 | /* DMA */ | ||
| 94 | ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */ | ||
| 95 | ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */ | ||
| 96 | ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */ | ||
| 97 | ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */ | ||
| 98 | /* real time clocks */ | ||
| 99 | ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */ | ||
| 100 | ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */ | ||
| 101 | /* supporting hardware */ | ||
| 102 | ATARIHW_DECLARE(SCU); /* System Control Unit */ | ||
| 103 | ATARIHW_DECLARE(BLITTER); /* Blitter */ | ||
| 104 | ATARIHW_DECLARE(VME); /* VME Bus */ | ||
| 105 | ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */ | ||
| 106 | }; | ||
| 107 | |||
| 108 | extern struct atari_hw_present atari_hw_present; | ||
| 109 | |||
| 110 | |||
| 111 | /* Reading the MFP port register gives a machine independent delay, since the | ||
| 112 | * MFP always has a 8 MHz clock. This avoids problems with the varying length | ||
| 113 | * of nops on various machines. Somebody claimed that the tstb takes 600 ns. | ||
| 114 | */ | ||
| 115 | #define MFPDELAY() \ | ||
| 116 | __asm__ __volatile__ ( "tstb %0" : : "m" (mfp.par_dt_reg) : "cc" ); | ||
| 117 | |||
| 118 | /* Do cache push/invalidate for DMA read/write. This function obeys the | ||
| 119 | * snooping on some machines (Medusa) and processors: The Medusa itself can | ||
| 120 | * snoop, but only the '040 can source data from its cache to DMA writes i.e., | ||
| 121 | * reads from memory). Both '040 and '060 invalidate cache entries on snooped | ||
| 122 | * DMA reads (i.e., writes to memory). | ||
| 123 | */ | ||
| 124 | |||
| 125 | |||
| 126 | #define atari_readb raw_inb | ||
| 127 | #define atari_writeb raw_outb | ||
| 128 | |||
| 129 | #define atari_inb_p raw_inb | ||
| 130 | #define atari_outb_p raw_outb | ||
| 131 | |||
| 132 | |||
| 133 | |||
| 134 | #include <linux/mm.h> | ||
| 135 | #include <asm/cacheflush.h> | ||
| 136 | |||
| 137 | static inline void dma_cache_maintenance( unsigned long paddr, | ||
| 138 | unsigned long len, | ||
| 139 | int writeflag ) | ||
| 140 | |||
| 141 | { | ||
| 142 | if (writeflag) { | ||
| 143 | if (!MACH_IS_MEDUSA || CPU_IS_060) | ||
| 144 | cache_push( paddr, len ); | ||
| 145 | } | ||
| 146 | else { | ||
| 147 | if (!MACH_IS_MEDUSA) | ||
| 148 | cache_clear( paddr, len ); | ||
| 149 | } | ||
| 150 | } | ||
| 151 | |||
| 152 | |||
| 153 | /* | ||
| 154 | ** Shifter | ||
| 155 | */ | ||
| 156 | #define ST_LOW 0 | ||
| 157 | #define ST_MID 1 | ||
| 158 | #define ST_HIGH 2 | ||
| 159 | #define TT_LOW 7 | ||
| 160 | #define TT_MID 4 | ||
| 161 | #define TT_HIGH 6 | ||
| 162 | |||
| 163 | #define SHF_BAS (0xffff8200) | ||
| 164 | struct SHIFTER | ||
| 165 | { | ||
| 166 | u_char pad1; | ||
| 167 | u_char bas_hi; | ||
| 168 | u_char pad2; | ||
| 169 | u_char bas_md; | ||
| 170 | u_char pad3; | ||
| 171 | u_char volatile vcounthi; | ||
| 172 | u_char pad4; | ||
| 173 | u_char volatile vcountmid; | ||
| 174 | u_char pad5; | ||
| 175 | u_char volatile vcountlow; | ||
| 176 | u_char volatile syncmode; | ||
| 177 | u_char pad6; | ||
| 178 | u_char pad7; | ||
| 179 | u_char bas_lo; | ||
| 180 | }; | ||
| 181 | # define shifter ((*(volatile struct SHIFTER *)SHF_BAS)) | ||
| 182 | |||
| 183 | #define SHF_FBAS (0xffff820e) | ||
| 184 | struct SHIFTER_F030 | ||
| 185 | { | ||
| 186 | u_short off_next; | ||
| 187 | u_short scn_width; | ||
| 188 | }; | ||
| 189 | # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS)) | ||
| 190 | |||
| 191 | |||
| 192 | #define SHF_TBAS (0xffff8200) | ||
| 193 | struct SHIFTER_TT { | ||
| 194 | u_char char_dummy0; | ||
| 195 | u_char bas_hi; /* video mem base addr, high and mid byte */ | ||
| 196 | u_char char_dummy1; | ||
| 197 | u_char bas_md; | ||
| 198 | u_char char_dummy2; | ||
| 199 | u_char vcount_hi; /* pointer to currently displayed byte */ | ||
| 200 | u_char char_dummy3; | ||
| 201 | u_char vcount_md; | ||
| 202 | u_char char_dummy4; | ||
| 203 | u_char vcount_lo; | ||
| 204 | u_short st_sync; /* ST compatible sync mode register, unused */ | ||
| 205 | u_char char_dummy5; | ||
| 206 | u_char bas_lo; /* video mem addr, low byte */ | ||
| 207 | u_char char_dummy6[2+3*16]; | ||
| 208 | /* $ffff8240: */ | ||
| 209 | u_short color_reg[16]; /* 16 color registers */ | ||
| 210 | u_char st_shiftmode; /* ST compatible shift mode register, unused */ | ||
| 211 | u_char char_dummy7; | ||
| 212 | u_short tt_shiftmode; /* TT shift mode register */ | ||
| 213 | |||
| 214 | |||
| 215 | }; | ||
| 216 | #define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS)) | ||
| 217 | |||
| 218 | /* values for shifter_tt->tt_shiftmode */ | ||
| 219 | #define TT_SHIFTER_STLOW 0x0000 | ||
| 220 | #define TT_SHIFTER_STMID 0x0100 | ||
| 221 | #define TT_SHIFTER_STHIGH 0x0200 | ||
| 222 | #define TT_SHIFTER_TTLOW 0x0700 | ||
| 223 | #define TT_SHIFTER_TTMID 0x0400 | ||
| 224 | #define TT_SHIFTER_TTHIGH 0x0600 | ||
| 225 | #define TT_SHIFTER_MODEMASK 0x0700 | ||
| 226 | #define TT_SHIFTER_NUMMODE 0x0008 | ||
| 227 | #define TT_SHIFTER_PALETTE_MASK 0x000f | ||
| 228 | #define TT_SHIFTER_GRAYMODE 0x1000 | ||
| 229 | |||
| 230 | /* 256 TT palette registers */ | ||
| 231 | #define TT_PALETTE_BASE (0xffff8400) | ||
| 232 | #define tt_palette ((volatile u_short *)TT_PALETTE_BASE) | ||
| 233 | |||
| 234 | #define TT_PALETTE_RED_MASK 0x0f00 | ||
| 235 | #define TT_PALETTE_GREEN_MASK 0x00f0 | ||
| 236 | #define TT_PALETTE_BLUE_MASK 0x000f | ||
| 237 | |||
| 238 | /* | ||
| 239 | ** Falcon030 VIDEL Video Controller | ||
| 240 | ** for description see File 'linux\tools\atari\hardware.txt | ||
| 241 | */ | ||
| 242 | #define f030_col ((u_long *) 0xffff9800) | ||
| 243 | #define f030_xreg ((u_short*) 0xffff8282) | ||
| 244 | #define f030_yreg ((u_short*) 0xffff82a2) | ||
| 245 | #define f030_creg ((u_short*) 0xffff82c0) | ||
| 246 | #define f030_sreg ((u_short*) 0xffff8260) | ||
| 247 | #define f030_mreg ((u_short*) 0xffff820a) | ||
| 248 | #define f030_linewidth ((u_short*) 0xffff820e) | ||
| 249 | #define f030_hscroll ((u_char*) 0xffff8265) | ||
| 250 | |||
| 251 | #define VIDEL_BAS (0xffff8260) | ||
| 252 | struct VIDEL { | ||
| 253 | u_short st_shift; | ||
| 254 | u_short pad1; | ||
| 255 | u_char xoffset_s; | ||
| 256 | u_char xoffset; | ||
| 257 | u_short f_shift; | ||
| 258 | u_char pad2[0x1a]; | ||
| 259 | u_short hht; | ||
| 260 | u_short hbb; | ||
| 261 | u_short hbe; | ||
| 262 | u_short hdb; | ||
| 263 | u_short hde; | ||
| 264 | u_short hss; | ||
| 265 | u_char pad3[0x14]; | ||
| 266 | u_short vft; | ||
| 267 | u_short vbb; | ||
| 268 | u_short vbe; | ||
| 269 | u_short vdb; | ||
| 270 | u_short vde; | ||
| 271 | u_short vss; | ||
| 272 | u_char pad4[0x12]; | ||
| 273 | u_short control; | ||
| 274 | u_short mode; | ||
| 275 | }; | ||
| 276 | #define videl ((*(volatile struct VIDEL *)VIDEL_BAS)) | ||
| 277 | |||
| 278 | /* | ||
| 279 | ** DMA/WD1772 Disk Controller | ||
| 280 | */ | ||
| 281 | |||
| 282 | #define FWD_BAS (0xffff8604) | ||
| 283 | struct DMA_WD | ||
| 284 | { | ||
| 285 | u_short fdc_acces_seccount; | ||
| 286 | u_short dma_mode_status; | ||
| 287 | u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */ | ||
| 288 | u_char dma_hi; | ||
| 289 | u_char char_dummy2; | ||
| 290 | u_char dma_md; | ||
| 291 | u_char char_dummy3; | ||
| 292 | u_char dma_lo; | ||
| 293 | u_short fdc_speed; | ||
| 294 | }; | ||
| 295 | # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS)) | ||
| 296 | /* alias */ | ||
| 297 | #define st_dma dma_wd | ||
| 298 | /* The two highest bytes of an extended DMA as a short; this is a must | ||
| 299 | * for the Medusa. | ||
| 300 | */ | ||
| 301 | #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608)) | ||
| 302 | |||
| 303 | /* | ||
| 304 | ** YM2149 Sound Chip | ||
| 305 | ** access in bytes | ||
| 306 | */ | ||
| 307 | |||
| 308 | #define YM_BAS (0xffff8800) | ||
| 309 | struct SOUND_YM | ||
| 310 | { | ||
| 311 | u_char rd_data_reg_sel; | ||
| 312 | u_char char_dummy1; | ||
| 313 | u_char wd_data; | ||
| 314 | }; | ||
| 315 | #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS)) | ||
| 316 | |||
| 317 | /* TT SCSI DMA */ | ||
| 318 | |||
| 319 | #define TT_SCSI_DMA_BAS (0xffff8700) | ||
| 320 | struct TT_DMA { | ||
| 321 | u_char char_dummy0; | ||
| 322 | u_char dma_addr_hi; | ||
| 323 | u_char char_dummy1; | ||
| 324 | u_char dma_addr_hmd; | ||
| 325 | u_char char_dummy2; | ||
| 326 | u_char dma_addr_lmd; | ||
| 327 | u_char char_dummy3; | ||
| 328 | u_char dma_addr_lo; | ||
| 329 | u_char char_dummy4; | ||
| 330 | u_char dma_cnt_hi; | ||
| 331 | u_char char_dummy5; | ||
| 332 | u_char dma_cnt_hmd; | ||
| 333 | u_char char_dummy6; | ||
| 334 | u_char dma_cnt_lmd; | ||
| 335 | u_char char_dummy7; | ||
| 336 | u_char dma_cnt_lo; | ||
| 337 | u_long dma_restdata; | ||
| 338 | u_short dma_ctrl; | ||
| 339 | }; | ||
| 340 | #define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS)) | ||
| 341 | |||
| 342 | /* TT SCSI Controller 5380 */ | ||
| 343 | |||
| 344 | #define TT_5380_BAS (0xffff8781) | ||
| 345 | struct TT_5380 { | ||
| 346 | u_char scsi_data; | ||
| 347 | u_char char_dummy1; | ||
| 348 | u_char scsi_icr; | ||
| 349 | u_char char_dummy2; | ||
| 350 | u_char scsi_mode; | ||
| 351 | u_char char_dummy3; | ||
| 352 | u_char scsi_tcr; | ||
| 353 | u_char char_dummy4; | ||
| 354 | u_char scsi_idstat; | ||
| 355 | u_char char_dummy5; | ||
| 356 | u_char scsi_dmastat; | ||
| 357 | u_char char_dummy6; | ||
| 358 | u_char scsi_targrcv; | ||
| 359 | u_char char_dummy7; | ||
| 360 | u_char scsi_inircv; | ||
| 361 | }; | ||
| 362 | #define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS)) | ||
| 363 | #define tt_scsi_regp ((volatile char *)TT_5380_BAS) | ||
| 364 | |||
| 365 | |||
| 366 | /* | ||
| 367 | ** Falcon DMA Sound Subsystem | ||
| 368 | */ | ||
| 369 | |||
| 370 | #define MATRIX_BASE (0xffff8930) | ||
| 371 | struct MATRIX | ||
| 372 | { | ||
| 373 | u_short source; | ||
| 374 | u_short destination; | ||
| 375 | u_char external_frequency_divider; | ||
| 376 | u_char internal_frequency_divider; | ||
| 377 | }; | ||
| 378 | #define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE) | ||
| 379 | |||
| 380 | #define CODEC_BASE (0xffff8936) | ||
| 381 | struct CODEC | ||
| 382 | { | ||
| 383 | u_char tracks; | ||
| 384 | u_char input_source; | ||
| 385 | #define CODEC_SOURCE_ADC 1 | ||
| 386 | #define CODEC_SOURCE_MATRIX 2 | ||
| 387 | u_char adc_source; | ||
| 388 | #define ADC_SOURCE_RIGHT_PSG 1 | ||
| 389 | #define ADC_SOURCE_LEFT_PSG 2 | ||
| 390 | u_char gain; | ||
| 391 | #define CODEC_GAIN_RIGHT 0x0f | ||
| 392 | #define CODEC_GAIN_LEFT 0xf0 | ||
| 393 | u_char attenuation; | ||
| 394 | #define CODEC_ATTENUATION_RIGHT 0x0f | ||
| 395 | #define CODEC_ATTENUATION_LEFT 0xf0 | ||
| 396 | u_char unused1; | ||
| 397 | u_char status; | ||
| 398 | #define CODEC_OVERFLOW_RIGHT 1 | ||
| 399 | #define CODEC_OVERFLOW_LEFT 2 | ||
| 400 | u_char unused2, unused3, unused4, unused5; | ||
| 401 | u_char gpio_directions; | ||
| 402 | #define GPIO_IN 0 | ||
| 403 | #define GPIO_OUT 1 | ||
| 404 | u_char unused6; | ||
| 405 | u_char gpio_data; | ||
| 406 | }; | ||
| 407 | #define falcon_codec (*(volatile struct CODEC *)CODEC_BASE) | ||
| 408 | |||
| 409 | /* | ||
| 410 | ** Falcon Blitter | ||
| 411 | */ | ||
| 412 | |||
| 413 | #define BLT_BAS (0xffff8a00) | ||
| 414 | |||
| 415 | struct BLITTER | ||
| 416 | { | ||
| 417 | u_short halftone[16]; | ||
| 418 | u_short src_x_inc; | ||
| 419 | u_short src_y_inc; | ||
| 420 | u_long src_address; | ||
| 421 | u_short endmask1; | ||
| 422 | u_short endmask2; | ||
| 423 | u_short endmask3; | ||
| 424 | u_short dst_x_inc; | ||
| 425 | u_short dst_y_inc; | ||
| 426 | u_long dst_address; | ||
| 427 | u_short wd_per_line; | ||
| 428 | u_short ln_per_bb; | ||
| 429 | u_short hlf_op_reg; | ||
| 430 | u_short log_op_reg; | ||
| 431 | u_short lin_nm_reg; | ||
| 432 | u_short skew_reg; | ||
| 433 | }; | ||
| 434 | # define blitter ((*(volatile struct BLITTER *)BLT_BAS)) | ||
| 435 | |||
| 436 | |||
| 437 | /* | ||
| 438 | ** SCC Z8530 | ||
| 439 | */ | ||
| 440 | |||
| 441 | #define SCC_BAS (0xffff8c81) | ||
| 442 | struct SCC | ||
| 443 | { | ||
| 444 | u_char cha_a_ctrl; | ||
| 445 | u_char char_dummy1; | ||
| 446 | u_char cha_a_data; | ||
| 447 | u_char char_dummy2; | ||
| 448 | u_char cha_b_ctrl; | ||
| 449 | u_char char_dummy3; | ||
| 450 | u_char cha_b_data; | ||
| 451 | }; | ||
| 452 | # define scc ((*(volatile struct SCC*)SCC_BAS)) | ||
| 453 | |||
| 454 | /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */ | ||
| 455 | # define st_escc ((*(volatile struct SCC*)0xfffffa31)) | ||
| 456 | # define st_escc_dsr ((*(volatile char *)0xfffffa39)) | ||
| 457 | |||
| 458 | /* TT SCC DMA Controller (same chip as SCSI DMA) */ | ||
| 459 | |||
| 460 | #define TT_SCC_DMA_BAS (0xffff8c00) | ||
| 461 | #define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS)) | ||
| 462 | |||
| 463 | /* | ||
| 464 | ** VIDEL Palette Register | ||
| 465 | */ | ||
| 466 | |||
| 467 | #define FPL_BAS (0xffff9800) | ||
| 468 | struct VIDEL_PALETTE | ||
| 469 | { | ||
| 470 | u_long reg[256]; | ||
| 471 | }; | ||
| 472 | # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS)) | ||
| 473 | |||
| 474 | |||
| 475 | /* | ||
| 476 | ** Falcon DSP Host Interface | ||
| 477 | */ | ||
| 478 | |||
| 479 | #define DSP56K_HOST_INTERFACE_BASE (0xffffa200) | ||
| 480 | struct DSP56K_HOST_INTERFACE { | ||
| 481 | u_char icr; | ||
| 482 | #define DSP56K_ICR_RREQ 0x01 | ||
| 483 | #define DSP56K_ICR_TREQ 0x02 | ||
| 484 | #define DSP56K_ICR_HF0 0x08 | ||
| 485 | #define DSP56K_ICR_HF1 0x10 | ||
| 486 | #define DSP56K_ICR_HM0 0x20 | ||
| 487 | #define DSP56K_ICR_HM1 0x40 | ||
| 488 | #define DSP56K_ICR_INIT 0x80 | ||
| 489 | |||
| 490 | u_char cvr; | ||
| 491 | #define DSP56K_CVR_HV_MASK 0x1f | ||
| 492 | #define DSP56K_CVR_HC 0x80 | ||
| 493 | |||
| 494 | u_char isr; | ||
| 495 | #define DSP56K_ISR_RXDF 0x01 | ||
| 496 | #define DSP56K_ISR_TXDE 0x02 | ||
| 497 | #define DSP56K_ISR_TRDY 0x04 | ||
| 498 | #define DSP56K_ISR_HF2 0x08 | ||
| 499 | #define DSP56K_ISR_HF3 0x10 | ||
| 500 | #define DSP56K_ISR_DMA 0x40 | ||
| 501 | #define DSP56K_ISR_HREQ 0x80 | ||
| 502 | |||
| 503 | u_char ivr; | ||
| 504 | |||
| 505 | union { | ||
| 506 | u_char b[4]; | ||
| 507 | u_short w[2]; | ||
| 508 | u_long l; | ||
| 509 | } data; | ||
| 510 | }; | ||
| 511 | #define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE)) | ||
| 512 | |||
| 513 | /* | ||
| 514 | ** MFP 68901 | ||
| 515 | */ | ||
| 516 | |||
| 517 | #define MFP_BAS (0xfffffa01) | ||
| 518 | struct MFP | ||
| 519 | { | ||
| 520 | u_char par_dt_reg; | ||
| 521 | u_char char_dummy1; | ||
| 522 | u_char active_edge; | ||
| 523 | u_char char_dummy2; | ||
| 524 | u_char data_dir; | ||
| 525 | u_char char_dummy3; | ||
| 526 | u_char int_en_a; | ||
| 527 | u_char char_dummy4; | ||
| 528 | u_char int_en_b; | ||
| 529 | u_char char_dummy5; | ||
| 530 | u_char int_pn_a; | ||
| 531 | u_char char_dummy6; | ||
| 532 | u_char int_pn_b; | ||
| 533 | u_char char_dummy7; | ||
| 534 | u_char int_sv_a; | ||
| 535 | u_char char_dummy8; | ||
| 536 | u_char int_sv_b; | ||
| 537 | u_char char_dummy9; | ||
| 538 | u_char int_mk_a; | ||
| 539 | u_char char_dummy10; | ||
| 540 | u_char int_mk_b; | ||
| 541 | u_char char_dummy11; | ||
| 542 | u_char vec_adr; | ||
| 543 | u_char char_dummy12; | ||
| 544 | u_char tim_ct_a; | ||
| 545 | u_char char_dummy13; | ||
| 546 | u_char tim_ct_b; | ||
| 547 | u_char char_dummy14; | ||
| 548 | u_char tim_ct_cd; | ||
| 549 | u_char char_dummy15; | ||
| 550 | u_char tim_dt_a; | ||
| 551 | u_char char_dummy16; | ||
| 552 | u_char tim_dt_b; | ||
| 553 | u_char char_dummy17; | ||
| 554 | u_char tim_dt_c; | ||
| 555 | u_char char_dummy18; | ||
| 556 | u_char tim_dt_d; | ||
| 557 | u_char char_dummy19; | ||
| 558 | u_char sync_char; | ||
| 559 | u_char char_dummy20; | ||
| 560 | u_char usart_ctr; | ||
| 561 | u_char char_dummy21; | ||
| 562 | u_char rcv_stat; | ||
| 563 | u_char char_dummy22; | ||
| 564 | u_char trn_stat; | ||
| 565 | u_char char_dummy23; | ||
| 566 | u_char usart_dta; | ||
| 567 | }; | ||
| 568 | # define mfp ((*(volatile struct MFP*)MFP_BAS)) | ||
| 569 | |||
| 570 | /* TT's second MFP */ | ||
| 571 | |||
| 572 | #define TT_MFP_BAS (0xfffffa81) | ||
| 573 | # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS)) | ||
| 574 | |||
| 575 | |||
| 576 | /* TT System Control Unit */ | ||
| 577 | |||
| 578 | #define TT_SCU_BAS (0xffff8e01) | ||
| 579 | struct TT_SCU { | ||
| 580 | u_char sys_mask; | ||
| 581 | u_char char_dummy1; | ||
| 582 | u_char sys_stat; | ||
| 583 | u_char char_dummy2; | ||
| 584 | u_char softint; | ||
| 585 | u_char char_dummy3; | ||
| 586 | u_char vmeint; | ||
| 587 | u_char char_dummy4; | ||
| 588 | u_char gp_reg1; | ||
| 589 | u_char char_dummy5; | ||
| 590 | u_char gp_reg2; | ||
| 591 | u_char char_dummy6; | ||
| 592 | u_char vme_mask; | ||
| 593 | u_char char_dummy7; | ||
| 594 | u_char vme_stat; | ||
| 595 | }; | ||
| 596 | #define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS)) | ||
| 597 | |||
| 598 | /* TT real time clock */ | ||
| 599 | |||
| 600 | #define TT_RTC_BAS (0xffff8961) | ||
| 601 | struct TT_RTC { | ||
| 602 | u_char regsel; | ||
| 603 | u_char dummy; | ||
| 604 | u_char data; | ||
| 605 | }; | ||
| 606 | #define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS)) | ||
| 607 | |||
| 608 | |||
| 609 | /* | ||
| 610 | ** ACIA 6850 | ||
| 611 | */ | ||
| 612 | /* constants for the ACIA registers */ | ||
| 613 | |||
| 614 | /* baudrate selection and reset (Baudrate = clock/factor) */ | ||
| 615 | #define ACIA_DIV1 0 | ||
| 616 | #define ACIA_DIV16 1 | ||
| 617 | #define ACIA_DIV64 2 | ||
| 618 | #define ACIA_RESET 3 | ||
| 619 | |||
| 620 | /* character format */ | ||
| 621 | #define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */ | ||
| 622 | #define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */ | ||
| 623 | #define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */ | ||
| 624 | #define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */ | ||
| 625 | #define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */ | ||
| 626 | #define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */ | ||
| 627 | #define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */ | ||
| 628 | #define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */ | ||
| 629 | |||
| 630 | /* transmit control */ | ||
| 631 | #define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */ | ||
| 632 | #define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */ | ||
| 633 | #define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */ | ||
| 634 | #define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */ | ||
| 635 | |||
| 636 | /* receive control */ | ||
| 637 | #define ACIA_RID (0<<7) /* RxINT disabled */ | ||
| 638 | #define ACIA_RIE (1<<7) /* RxINT enabled */ | ||
| 639 | |||
| 640 | /* status fields of the ACIA */ | ||
| 641 | #define ACIA_RDRF 1 /* Receive Data Register Full */ | ||
| 642 | #define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */ | ||
| 643 | #define ACIA_DCD (1<<2) /* Data Carrier Detect */ | ||
| 644 | #define ACIA_CTS (1<<3) /* Clear To Send */ | ||
| 645 | #define ACIA_FE (1<<4) /* Framing Error */ | ||
| 646 | #define ACIA_OVRN (1<<5) /* Receiver Overrun */ | ||
| 647 | #define ACIA_PE (1<<6) /* Parity Error */ | ||
| 648 | #define ACIA_IRQ (1<<7) /* Interrupt Request */ | ||
| 649 | |||
| 650 | #define ACIA_BAS (0xfffffc00) | ||
| 651 | struct ACIA | ||
| 652 | { | ||
| 653 | u_char key_ctrl; | ||
| 654 | u_char char_dummy1; | ||
| 655 | u_char key_data; | ||
| 656 | u_char char_dummy2; | ||
| 657 | u_char mid_ctrl; | ||
| 658 | u_char char_dummy3; | ||
| 659 | u_char mid_data; | ||
| 660 | }; | ||
| 661 | # define acia ((*(volatile struct ACIA*)ACIA_BAS)) | ||
| 662 | |||
| 663 | #define TT_DMASND_BAS (0xffff8900) | ||
| 664 | struct TT_DMASND { | ||
| 665 | u_char int_ctrl; /* Falcon: Interrupt control */ | ||
| 666 | u_char ctrl; | ||
| 667 | u_char pad2; | ||
| 668 | u_char bas_hi; | ||
| 669 | u_char pad3; | ||
| 670 | u_char bas_mid; | ||
| 671 | u_char pad4; | ||
| 672 | u_char bas_low; | ||
| 673 | u_char pad5; | ||
| 674 | u_char addr_hi; | ||
| 675 | u_char pad6; | ||
| 676 | u_char addr_mid; | ||
| 677 | u_char pad7; | ||
| 678 | u_char addr_low; | ||
| 679 | u_char pad8; | ||
| 680 | u_char end_hi; | ||
| 681 | u_char pad9; | ||
| 682 | u_char end_mid; | ||
| 683 | u_char pad10; | ||
| 684 | u_char end_low; | ||
| 685 | u_char pad11[12]; | ||
| 686 | u_char track_select; /* Falcon */ | ||
| 687 | u_char mode; | ||
| 688 | u_char pad12[14]; | ||
| 689 | /* Falcon only: */ | ||
| 690 | u_short cbar_src; | ||
| 691 | u_short cbar_dst; | ||
| 692 | u_char ext_div; | ||
| 693 | u_char int_div; | ||
| 694 | u_char rec_track_select; | ||
| 695 | u_char dac_src; | ||
| 696 | u_char adc_src; | ||
| 697 | u_char input_gain; | ||
| 698 | u_short output_atten; | ||
| 699 | }; | ||
| 700 | # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS)) | ||
| 701 | |||
| 702 | #define DMASND_MFP_INT_REPLAY 0x01 | ||
| 703 | #define DMASND_MFP_INT_RECORD 0x02 | ||
| 704 | #define DMASND_TIMERA_INT_REPLAY 0x04 | ||
| 705 | #define DMASND_TIMERA_INT_RECORD 0x08 | ||
| 706 | |||
| 707 | #define DMASND_CTRL_OFF 0x00 | ||
| 708 | #define DMASND_CTRL_ON 0x01 | ||
| 709 | #define DMASND_CTRL_REPEAT 0x02 | ||
| 710 | #define DMASND_CTRL_RECORD_ON 0x10 | ||
| 711 | #define DMASND_CTRL_RECORD_OFF 0x00 | ||
| 712 | #define DMASND_CTRL_RECORD_REPEAT 0x20 | ||
| 713 | #define DMASND_CTRL_SELECT_REPLAY 0x00 | ||
| 714 | #define DMASND_CTRL_SELECT_RECORD 0x80 | ||
| 715 | #define DMASND_MODE_MONO 0x80 | ||
| 716 | #define DMASND_MODE_STEREO 0x00 | ||
| 717 | #define DMASND_MODE_8BIT 0x00 | ||
| 718 | #define DMASND_MODE_16BIT 0x40 /* Falcon only */ | ||
| 719 | #define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */ | ||
| 720 | #define DMASND_MODE_12KHZ 0x01 | ||
| 721 | #define DMASND_MODE_25KHZ 0x02 | ||
| 722 | #define DMASND_MODE_50KHZ 0x03 | ||
| 723 | |||
| 724 | |||
| 725 | #define DMASNDSetBase(bufstart) \ | ||
| 726 | do { \ | ||
| 727 | tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \ | ||
| 728 | tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \ | ||
| 729 | tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \ | ||
| 730 | } while( 0 ) | ||
| 731 | |||
| 732 | #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \ | ||
| 733 | (tt_dmasnd.addr_mid << 8) + \ | ||
| 734 | (tt_dmasnd.addr_low)) | ||
| 735 | |||
| 736 | #define DMASNDSetEnd(bufend) \ | ||
| 737 | do { \ | ||
| 738 | tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \ | ||
| 739 | tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \ | ||
| 740 | tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \ | ||
| 741 | } while( 0 ) | ||
| 742 | |||
| 743 | |||
| 744 | #define TT_MICROWIRE_BAS (0xffff8922) | ||
| 745 | struct TT_MICROWIRE { | ||
| 746 | u_short data; | ||
| 747 | u_short mask; | ||
| 748 | }; | ||
| 749 | # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS)) | ||
| 750 | |||
| 751 | #define MW_LM1992_ADDR 0x0400 | ||
| 752 | |||
| 753 | #define MW_LM1992_VOLUME(dB) \ | ||
| 754 | (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2))) | ||
| 755 | #define MW_LM1992_BALLEFT(dB) \ | ||
| 756 | (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) | ||
| 757 | #define MW_LM1992_BALRIGHT(dB) \ | ||
| 758 | (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) | ||
| 759 | #define MW_LM1992_TREBLE(dB) \ | ||
| 760 | (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) | ||
| 761 | #define MW_LM1992_BASS(dB) \ | ||
| 762 | (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) | ||
| 763 | |||
| 764 | #define MW_LM1992_PSG_LOW 0x000 | ||
| 765 | #define MW_LM1992_PSG_HIGH 0x001 | ||
| 766 | #define MW_LM1992_PSG_OFF 0x002 | ||
| 767 | |||
| 768 | #define MSTE_RTC_BAS (0xfffffc21) | ||
| 769 | |||
| 770 | struct MSTE_RTC { | ||
| 771 | u_char sec_ones; | ||
| 772 | u_char dummy1; | ||
| 773 | u_char sec_tens; | ||
| 774 | u_char dummy2; | ||
| 775 | u_char min_ones; | ||
| 776 | u_char dummy3; | ||
| 777 | u_char min_tens; | ||
| 778 | u_char dummy4; | ||
| 779 | u_char hr_ones; | ||
| 780 | u_char dummy5; | ||
| 781 | u_char hr_tens; | ||
| 782 | u_char dummy6; | ||
| 783 | u_char weekday; | ||
| 784 | u_char dummy7; | ||
| 785 | u_char day_ones; | ||
| 786 | u_char dummy8; | ||
| 787 | u_char day_tens; | ||
| 788 | u_char dummy9; | ||
| 789 | u_char mon_ones; | ||
| 790 | u_char dummy10; | ||
| 791 | u_char mon_tens; | ||
| 792 | u_char dummy11; | ||
| 793 | u_char year_ones; | ||
| 794 | u_char dummy12; | ||
| 795 | u_char year_tens; | ||
| 796 | u_char dummy13; | ||
| 797 | u_char mode; | ||
| 798 | u_char dummy14; | ||
| 799 | u_char test; | ||
| 800 | u_char dummy15; | ||
| 801 | u_char reset; | ||
| 802 | }; | ||
| 803 | |||
| 804 | #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS)) | ||
| 805 | |||
| 806 | #endif /* linux/atarihw.h */ | ||
| 807 | |||
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h new file mode 100644 index 000000000000..5748e99f4e26 --- /dev/null +++ b/arch/m68k/include/asm/atariints.h | |||
| @@ -0,0 +1,204 @@ | |||
| 1 | /* | ||
| 2 | ** atariints.h -- Atari Linux interrupt handling structs and prototypes | ||
| 3 | ** | ||
| 4 | ** Copyright 1994 by Björn Brauel | ||
| 5 | ** | ||
| 6 | ** 5/2/94 Roman Hodek: | ||
| 7 | ** TT interrupt definitions added. | ||
| 8 | ** | ||
| 9 | ** 12/02/96: (Roman) | ||
| 10 | ** Adapted to new int handling scheme (see ataints.c); revised numbering | ||
| 11 | ** | ||
| 12 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 13 | ** License. See the file COPYING in the main directory of this archive | ||
| 14 | ** for more details. | ||
| 15 | ** | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef _LINUX_ATARIINTS_H_ | ||
| 19 | #define _LINUX_ATARIINTS_H_ | ||
| 20 | |||
| 21 | #include <asm/irq.h> | ||
| 22 | #include <asm/atarihw.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | ** Atari Interrupt sources. | ||
| 26 | ** | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define STMFP_SOURCE_BASE 8 | ||
| 30 | #define TTMFP_SOURCE_BASE 24 | ||
| 31 | #define SCC_SOURCE_BASE 40 | ||
| 32 | #define VME_SOURCE_BASE 56 | ||
| 33 | #define VME_MAX_SOURCES 16 | ||
| 34 | |||
| 35 | #define NUM_ATARI_SOURCES (VME_SOURCE_BASE+VME_MAX_SOURCES-STMFP_SOURCE_BASE) | ||
| 36 | |||
| 37 | /* convert vector number to int source number */ | ||
| 38 | #define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8))) | ||
| 39 | |||
| 40 | /* convert irq_handler index to vector number */ | ||
| 41 | #define IRQ_SOURCE_TO_VECTOR(i) ((i) + ((i) < 8 ? 0x18 : (0x40-8))) | ||
| 42 | |||
| 43 | /* interrupt service types */ | ||
| 44 | #define IRQ_TYPE_SLOW 0 | ||
| 45 | #define IRQ_TYPE_FAST 1 | ||
| 46 | #define IRQ_TYPE_PRIO 2 | ||
| 47 | |||
| 48 | /* ST-MFP interrupts */ | ||
| 49 | #define IRQ_MFP_BUSY (8) | ||
| 50 | #define IRQ_MFP_DCD (9) | ||
| 51 | #define IRQ_MFP_CTS (10) | ||
| 52 | #define IRQ_MFP_GPU (11) | ||
| 53 | #define IRQ_MFP_TIMD (12) | ||
| 54 | #define IRQ_MFP_TIMC (13) | ||
| 55 | #define IRQ_MFP_ACIA (14) | ||
| 56 | #define IRQ_MFP_FDC (15) | ||
| 57 | #define IRQ_MFP_ACSI IRQ_MFP_FDC | ||
| 58 | #define IRQ_MFP_FSCSI IRQ_MFP_FDC | ||
| 59 | #define IRQ_MFP_IDE IRQ_MFP_FDC | ||
| 60 | #define IRQ_MFP_TIMB (16) | ||
| 61 | #define IRQ_MFP_SERERR (17) | ||
| 62 | #define IRQ_MFP_SEREMPT (18) | ||
| 63 | #define IRQ_MFP_RECERR (19) | ||
| 64 | #define IRQ_MFP_RECFULL (20) | ||
| 65 | #define IRQ_MFP_TIMA (21) | ||
| 66 | #define IRQ_MFP_RI (22) | ||
| 67 | #define IRQ_MFP_MMD (23) | ||
| 68 | |||
| 69 | /* TT-MFP interrupts */ | ||
| 70 | #define IRQ_TT_MFP_IO0 (24) | ||
| 71 | #define IRQ_TT_MFP_IO1 (25) | ||
| 72 | #define IRQ_TT_MFP_SCC (26) | ||
| 73 | #define IRQ_TT_MFP_RI (27) | ||
| 74 | #define IRQ_TT_MFP_TIMD (28) | ||
| 75 | #define IRQ_TT_MFP_TIMC (29) | ||
| 76 | #define IRQ_TT_MFP_DRVRDY (30) | ||
| 77 | #define IRQ_TT_MFP_SCSIDMA (31) | ||
| 78 | #define IRQ_TT_MFP_TIMB (32) | ||
| 79 | #define IRQ_TT_MFP_SERERR (33) | ||
| 80 | #define IRQ_TT_MFP_SEREMPT (34) | ||
| 81 | #define IRQ_TT_MFP_RECERR (35) | ||
| 82 | #define IRQ_TT_MFP_RECFULL (36) | ||
| 83 | #define IRQ_TT_MFP_TIMA (37) | ||
| 84 | #define IRQ_TT_MFP_RTC (38) | ||
| 85 | #define IRQ_TT_MFP_SCSI (39) | ||
| 86 | |||
| 87 | /* SCC interrupts */ | ||
| 88 | #define IRQ_SCCB_TX (40) | ||
| 89 | #define IRQ_SCCB_STAT (42) | ||
| 90 | #define IRQ_SCCB_RX (44) | ||
| 91 | #define IRQ_SCCB_SPCOND (46) | ||
| 92 | #define IRQ_SCCA_TX (48) | ||
| 93 | #define IRQ_SCCA_STAT (50) | ||
| 94 | #define IRQ_SCCA_RX (52) | ||
| 95 | #define IRQ_SCCA_SPCOND (54) | ||
| 96 | |||
| 97 | |||
| 98 | #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */ | ||
| 99 | #define INT_TICKS 246 /* to make sched_time = 99.902... HZ */ | ||
| 100 | |||
| 101 | |||
| 102 | #define MFP_ENABLE 0 | ||
| 103 | #define MFP_PENDING 1 | ||
| 104 | #define MFP_SERVICE 2 | ||
| 105 | #define MFP_MASK 3 | ||
| 106 | |||
| 107 | /* Utility functions for setting/clearing bits in the interrupt registers of | ||
| 108 | * the MFP. 'type' should be constant, if 'irq' is constant, too, code size is | ||
| 109 | * reduced. set_mfp_bit() is nonsense for PENDING and SERVICE registers. */ | ||
| 110 | |||
| 111 | static inline int get_mfp_bit( unsigned irq, int type ) | ||
| 112 | |||
| 113 | { unsigned char mask, *reg; | ||
| 114 | |||
| 115 | mask = 1 << (irq & 7); | ||
| 116 | reg = (unsigned char *)&mfp.int_en_a + type*4 + | ||
| 117 | ((irq & 8) >> 2) + (((irq-8) & 16) << 3); | ||
| 118 | return( *reg & mask ); | ||
| 119 | } | ||
| 120 | |||
| 121 | static inline void set_mfp_bit( unsigned irq, int type ) | ||
| 122 | |||
| 123 | { unsigned char mask, *reg; | ||
| 124 | |||
| 125 | mask = 1 << (irq & 7); | ||
| 126 | reg = (unsigned char *)&mfp.int_en_a + type*4 + | ||
| 127 | ((irq & 8) >> 2) + (((irq-8) & 16) << 3); | ||
| 128 | __asm__ __volatile__ ( "orb %0,%1" | ||
| 129 | : : "di" (mask), "m" (*reg) : "memory" ); | ||
| 130 | } | ||
| 131 | |||
| 132 | static inline void clear_mfp_bit( unsigned irq, int type ) | ||
| 133 | |||
| 134 | { unsigned char mask, *reg; | ||
| 135 | |||
| 136 | mask = ~(1 << (irq & 7)); | ||
| 137 | reg = (unsigned char *)&mfp.int_en_a + type*4 + | ||
| 138 | ((irq & 8) >> 2) + (((irq-8) & 16) << 3); | ||
| 139 | if (type == MFP_PENDING || type == MFP_SERVICE) | ||
| 140 | __asm__ __volatile__ ( "moveb %0,%1" | ||
| 141 | : : "di" (mask), "m" (*reg) : "memory" ); | ||
| 142 | else | ||
| 143 | __asm__ __volatile__ ( "andb %0,%1" | ||
| 144 | : : "di" (mask), "m" (*reg) : "memory" ); | ||
| 145 | } | ||
| 146 | |||
| 147 | /* | ||
| 148 | * {en,dis}able_irq have the usual semantics of temporary blocking the | ||
| 149 | * interrupt, but not loosing requests that happen between disabling and | ||
| 150 | * enabling. This is done with the MFP mask registers. | ||
| 151 | */ | ||
| 152 | |||
| 153 | static inline void atari_enable_irq( unsigned irq ) | ||
| 154 | |||
| 155 | { | ||
| 156 | if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return; | ||
| 157 | set_mfp_bit( irq, MFP_MASK ); | ||
| 158 | } | ||
| 159 | |||
| 160 | static inline void atari_disable_irq( unsigned irq ) | ||
| 161 | |||
| 162 | { | ||
| 163 | if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return; | ||
| 164 | clear_mfp_bit( irq, MFP_MASK ); | ||
| 165 | } | ||
| 166 | |||
| 167 | /* | ||
| 168 | * In opposite to {en,dis}able_irq, requests between turn{off,on}_irq are not | ||
| 169 | * "stored" | ||
| 170 | */ | ||
| 171 | |||
| 172 | static inline void atari_turnon_irq( unsigned irq ) | ||
| 173 | |||
| 174 | { | ||
| 175 | if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return; | ||
| 176 | set_mfp_bit( irq, MFP_ENABLE ); | ||
| 177 | } | ||
| 178 | |||
| 179 | static inline void atari_turnoff_irq( unsigned irq ) | ||
| 180 | |||
| 181 | { | ||
| 182 | if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return; | ||
| 183 | clear_mfp_bit( irq, MFP_ENABLE ); | ||
| 184 | clear_mfp_bit( irq, MFP_PENDING ); | ||
| 185 | } | ||
| 186 | |||
| 187 | static inline void atari_clear_pending_irq( unsigned irq ) | ||
| 188 | |||
| 189 | { | ||
| 190 | if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return; | ||
| 191 | clear_mfp_bit( irq, MFP_PENDING ); | ||
| 192 | } | ||
| 193 | |||
| 194 | static inline int atari_irq_pending( unsigned irq ) | ||
| 195 | |||
| 196 | { | ||
| 197 | if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return( 0 ); | ||
| 198 | return( get_mfp_bit( irq, MFP_PENDING ) ); | ||
| 199 | } | ||
| 200 | |||
| 201 | unsigned long atari_register_vme_int( void ); | ||
| 202 | void atari_unregister_vme_int( unsigned long ); | ||
| 203 | |||
| 204 | #endif /* linux/atariints.h */ | ||
diff --git a/arch/m68k/include/asm/atarikb.h b/arch/m68k/include/asm/atarikb.h new file mode 100644 index 000000000000..546e7da5804f --- /dev/null +++ b/arch/m68k/include/asm/atarikb.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* | ||
| 2 | ** atarikb.h -- This header contains the prototypes of functions of | ||
| 3 | ** the intelligent keyboard of the Atari needed by the | ||
| 4 | ** mouse and joystick drivers. | ||
| 5 | ** | ||
| 6 | ** Copyright 1994 by Robert de Vries | ||
| 7 | ** | ||
| 8 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 9 | ** License. See the file COPYING in the main directory of this archive | ||
| 10 | ** for more details. | ||
| 11 | ** | ||
| 12 | ** Created: 20 Feb 1994 by Robert de Vries | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef _LINUX_ATARIKB_H | ||
| 16 | #define _LINUX_ATARIKB_H | ||
| 17 | |||
| 18 | void ikbd_write(const char *, int); | ||
| 19 | void ikbd_mouse_button_action(int mode); | ||
| 20 | void ikbd_mouse_rel_pos(void); | ||
| 21 | void ikbd_mouse_abs_pos(int xmax, int ymax); | ||
| 22 | void ikbd_mouse_kbd_mode(int dx, int dy); | ||
| 23 | void ikbd_mouse_thresh(int x, int y); | ||
| 24 | void ikbd_mouse_scale(int x, int y); | ||
| 25 | void ikbd_mouse_pos_get(int *x, int *y); | ||
| 26 | void ikbd_mouse_pos_set(int x, int y); | ||
| 27 | void ikbd_mouse_y0_bot(void); | ||
| 28 | void ikbd_mouse_y0_top(void); | ||
| 29 | void ikbd_mouse_disable(void); | ||
| 30 | void ikbd_joystick_event_on(void); | ||
| 31 | void ikbd_joystick_event_off(void); | ||
| 32 | void ikbd_joystick_get_state(void); | ||
| 33 | void ikbd_joystick_disable(void); | ||
| 34 | |||
| 35 | /* Hook for MIDI serial driver */ | ||
| 36 | extern void (*atari_MIDI_interrupt_hook) (void); | ||
| 37 | /* Hook for mouse driver */ | ||
| 38 | extern void (*atari_mouse_interrupt_hook) (char *); | ||
| 39 | /* Hook for keyboard inputdev driver */ | ||
| 40 | extern void (*atari_input_keyboard_interrupt_hook) (unsigned char, char); | ||
| 41 | /* Hook for mouse inputdev driver */ | ||
| 42 | extern void (*atari_input_mouse_interrupt_hook) (char *); | ||
| 43 | |||
| 44 | int atari_keyb_init(void); | ||
| 45 | |||
| 46 | #endif /* _LINUX_ATARIKB_H */ | ||
diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h new file mode 100644 index 000000000000..8d29145ebb27 --- /dev/null +++ b/arch/m68k/include/asm/atomic.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "atomic_no.h" | ||
| 3 | #else | ||
| 4 | #include "atomic_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/atomic_mm.h b/arch/m68k/include/asm/atomic_mm.h new file mode 100644 index 000000000000..eb0ab9d4ee77 --- /dev/null +++ b/arch/m68k/include/asm/atomic_mm.h | |||
| @@ -0,0 +1,196 @@ | |||
| 1 | #ifndef __ARCH_M68K_ATOMIC__ | ||
| 2 | #define __ARCH_M68K_ATOMIC__ | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | #include <asm/system.h> | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Atomic operations that C can't guarantee us. Useful for | ||
| 9 | * resource counting etc.. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * We do not have SMP m68k systems, so we don't have to deal with that. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define ATOMIC_INIT(i) { (i) } | ||
| 17 | |||
| 18 | #define atomic_read(v) ((v)->counter) | ||
| 19 | #define atomic_set(v, i) (((v)->counter) = i) | ||
| 20 | |||
| 21 | static inline void atomic_add(int i, atomic_t *v) | ||
| 22 | { | ||
| 23 | __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i)); | ||
| 24 | } | ||
| 25 | |||
| 26 | static inline void atomic_sub(int i, atomic_t *v) | ||
| 27 | { | ||
| 28 | __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i)); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline void atomic_inc(atomic_t *v) | ||
| 32 | { | ||
| 33 | __asm__ __volatile__("addql #1,%0" : "+m" (*v)); | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void atomic_dec(atomic_t *v) | ||
| 37 | { | ||
| 38 | __asm__ __volatile__("subql #1,%0" : "+m" (*v)); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline int atomic_dec_and_test(atomic_t *v) | ||
| 42 | { | ||
| 43 | char c; | ||
| 44 | __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | ||
| 45 | return c != 0; | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline int atomic_inc_and_test(atomic_t *v) | ||
| 49 | { | ||
| 50 | char c; | ||
| 51 | __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | ||
| 52 | return c != 0; | ||
| 53 | } | ||
| 54 | |||
| 55 | #ifdef CONFIG_RMW_INSNS | ||
| 56 | |||
| 57 | static inline int atomic_add_return(int i, atomic_t *v) | ||
| 58 | { | ||
| 59 | int t, tmp; | ||
| 60 | |||
| 61 | __asm__ __volatile__( | ||
| 62 | "1: movel %2,%1\n" | ||
| 63 | " addl %3,%1\n" | ||
| 64 | " casl %2,%1,%0\n" | ||
| 65 | " jne 1b" | ||
| 66 | : "+m" (*v), "=&d" (t), "=&d" (tmp) | ||
| 67 | : "g" (i), "2" (atomic_read(v))); | ||
| 68 | return t; | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline int atomic_sub_return(int i, atomic_t *v) | ||
| 72 | { | ||
| 73 | int t, tmp; | ||
| 74 | |||
| 75 | __asm__ __volatile__( | ||
| 76 | "1: movel %2,%1\n" | ||
| 77 | " subl %3,%1\n" | ||
| 78 | " casl %2,%1,%0\n" | ||
| 79 | " jne 1b" | ||
| 80 | : "+m" (*v), "=&d" (t), "=&d" (tmp) | ||
| 81 | : "g" (i), "2" (atomic_read(v))); | ||
| 82 | return t; | ||
| 83 | } | ||
| 84 | |||
| 85 | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) | ||
| 86 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | ||
| 87 | |||
| 88 | #else /* !CONFIG_RMW_INSNS */ | ||
| 89 | |||
| 90 | static inline int atomic_add_return(int i, atomic_t * v) | ||
| 91 | { | ||
| 92 | unsigned long flags; | ||
| 93 | int t; | ||
| 94 | |||
| 95 | local_irq_save(flags); | ||
| 96 | t = atomic_read(v); | ||
| 97 | t += i; | ||
| 98 | atomic_set(v, t); | ||
| 99 | local_irq_restore(flags); | ||
| 100 | |||
| 101 | return t; | ||
| 102 | } | ||
| 103 | |||
| 104 | static inline int atomic_sub_return(int i, atomic_t * v) | ||
| 105 | { | ||
| 106 | unsigned long flags; | ||
| 107 | int t; | ||
| 108 | |||
| 109 | local_irq_save(flags); | ||
| 110 | t = atomic_read(v); | ||
| 111 | t -= i; | ||
| 112 | atomic_set(v, t); | ||
| 113 | local_irq_restore(flags); | ||
| 114 | |||
| 115 | return t; | ||
| 116 | } | ||
| 117 | |||
| 118 | static inline int atomic_cmpxchg(atomic_t *v, int old, int new) | ||
| 119 | { | ||
| 120 | unsigned long flags; | ||
| 121 | int prev; | ||
| 122 | |||
| 123 | local_irq_save(flags); | ||
| 124 | prev = atomic_read(v); | ||
| 125 | if (prev == old) | ||
| 126 | atomic_set(v, new); | ||
| 127 | local_irq_restore(flags); | ||
| 128 | return prev; | ||
| 129 | } | ||
| 130 | |||
| 131 | static inline int atomic_xchg(atomic_t *v, int new) | ||
| 132 | { | ||
| 133 | unsigned long flags; | ||
| 134 | int prev; | ||
| 135 | |||
| 136 | local_irq_save(flags); | ||
| 137 | prev = atomic_read(v); | ||
| 138 | atomic_set(v, new); | ||
| 139 | local_irq_restore(flags); | ||
| 140 | return prev; | ||
| 141 | } | ||
| 142 | |||
| 143 | #endif /* !CONFIG_RMW_INSNS */ | ||
| 144 | |||
| 145 | #define atomic_dec_return(v) atomic_sub_return(1, (v)) | ||
| 146 | #define atomic_inc_return(v) atomic_add_return(1, (v)) | ||
| 147 | |||
| 148 | static inline int atomic_sub_and_test(int i, atomic_t *v) | ||
| 149 | { | ||
| 150 | char c; | ||
| 151 | __asm__ __volatile__("subl %2,%1; seq %0" : "=d" (c), "+m" (*v): "g" (i)); | ||
| 152 | return c != 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | static inline int atomic_add_negative(int i, atomic_t *v) | ||
| 156 | { | ||
| 157 | char c; | ||
| 158 | __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v): "g" (i)); | ||
| 159 | return c != 0; | ||
| 160 | } | ||
| 161 | |||
| 162 | static inline void atomic_clear_mask(unsigned long mask, unsigned long *v) | ||
| 163 | { | ||
| 164 | __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); | ||
| 165 | } | ||
| 166 | |||
| 167 | static inline void atomic_set_mask(unsigned long mask, unsigned long *v) | ||
| 168 | { | ||
| 169 | __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); | ||
| 170 | } | ||
| 171 | |||
| 172 | static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) | ||
| 173 | { | ||
| 174 | int c, old; | ||
| 175 | c = atomic_read(v); | ||
| 176 | for (;;) { | ||
| 177 | if (unlikely(c == (u))) | ||
| 178 | break; | ||
| 179 | old = atomic_cmpxchg((v), c, c + (a)); | ||
| 180 | if (likely(old == c)) | ||
| 181 | break; | ||
| 182 | c = old; | ||
| 183 | } | ||
| 184 | return c != (u); | ||
| 185 | } | ||
| 186 | |||
| 187 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
| 188 | |||
| 189 | /* Atomic operations are already serializing */ | ||
| 190 | #define smp_mb__before_atomic_dec() barrier() | ||
| 191 | #define smp_mb__after_atomic_dec() barrier() | ||
| 192 | #define smp_mb__before_atomic_inc() barrier() | ||
| 193 | #define smp_mb__after_atomic_inc() barrier() | ||
| 194 | |||
| 195 | #include <asm-generic/atomic.h> | ||
| 196 | #endif /* __ARCH_M68K_ATOMIC __ */ | ||
diff --git a/arch/m68k/include/asm/atomic_no.h b/arch/m68k/include/asm/atomic_no.h new file mode 100644 index 000000000000..6bb674855a3f --- /dev/null +++ b/arch/m68k/include/asm/atomic_no.h | |||
| @@ -0,0 +1,155 @@ | |||
| 1 | #ifndef __ARCH_M68KNOMMU_ATOMIC__ | ||
| 2 | #define __ARCH_M68KNOMMU_ATOMIC__ | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | #include <asm/system.h> | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Atomic operations that C can't guarantee us. Useful for | ||
| 9 | * resource counting etc.. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * We do not have SMP m68k systems, so we don't have to deal with that. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define ATOMIC_INIT(i) { (i) } | ||
| 17 | |||
| 18 | #define atomic_read(v) ((v)->counter) | ||
| 19 | #define atomic_set(v, i) (((v)->counter) = i) | ||
| 20 | |||
| 21 | static __inline__ void atomic_add(int i, atomic_t *v) | ||
| 22 | { | ||
| 23 | #ifdef CONFIG_COLDFIRE | ||
| 24 | __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "d" (i)); | ||
| 25 | #else | ||
| 26 | __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "di" (i)); | ||
| 27 | #endif | ||
| 28 | } | ||
| 29 | |||
| 30 | static __inline__ void atomic_sub(int i, atomic_t *v) | ||
| 31 | { | ||
| 32 | #ifdef CONFIG_COLDFIRE | ||
| 33 | __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "d" (i)); | ||
| 34 | #else | ||
| 35 | __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "di" (i)); | ||
| 36 | #endif | ||
| 37 | } | ||
| 38 | |||
| 39 | static __inline__ int atomic_sub_and_test(int i, atomic_t * v) | ||
| 40 | { | ||
| 41 | char c; | ||
| 42 | #ifdef CONFIG_COLDFIRE | ||
| 43 | __asm__ __volatile__("subl %2,%1; seq %0" | ||
| 44 | : "=d" (c), "+m" (*v) | ||
| 45 | : "d" (i)); | ||
| 46 | #else | ||
| 47 | __asm__ __volatile__("subl %2,%1; seq %0" | ||
| 48 | : "=d" (c), "+m" (*v) | ||
| 49 | : "di" (i)); | ||
| 50 | #endif | ||
| 51 | return c != 0; | ||
| 52 | } | ||
| 53 | |||
| 54 | static __inline__ void atomic_inc(volatile atomic_t *v) | ||
| 55 | { | ||
| 56 | __asm__ __volatile__("addql #1,%0" : "+m" (*v)); | ||
| 57 | } | ||
| 58 | |||
| 59 | /* | ||
| 60 | * atomic_inc_and_test - increment and test | ||
| 61 | * @v: pointer of type atomic_t | ||
| 62 | * | ||
| 63 | * Atomically increments @v by 1 | ||
| 64 | * and returns true if the result is zero, or false for all | ||
| 65 | * other cases. | ||
| 66 | */ | ||
| 67 | |||
| 68 | static __inline__ int atomic_inc_and_test(volatile atomic_t *v) | ||
| 69 | { | ||
| 70 | char c; | ||
| 71 | __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | ||
| 72 | return c != 0; | ||
| 73 | } | ||
| 74 | |||
| 75 | static __inline__ void atomic_dec(volatile atomic_t *v) | ||
| 76 | { | ||
| 77 | __asm__ __volatile__("subql #1,%0" : "+m" (*v)); | ||
| 78 | } | ||
| 79 | |||
| 80 | static __inline__ int atomic_dec_and_test(volatile atomic_t *v) | ||
| 81 | { | ||
| 82 | char c; | ||
| 83 | __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | ||
| 84 | return c != 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v) | ||
| 88 | { | ||
| 89 | __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); | ||
| 90 | } | ||
| 91 | |||
| 92 | static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v) | ||
| 93 | { | ||
| 94 | __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); | ||
| 95 | } | ||
| 96 | |||
| 97 | /* Atomic operations are already serializing */ | ||
| 98 | #define smp_mb__before_atomic_dec() barrier() | ||
| 99 | #define smp_mb__after_atomic_dec() barrier() | ||
| 100 | #define smp_mb__before_atomic_inc() barrier() | ||
| 101 | #define smp_mb__after_atomic_inc() barrier() | ||
| 102 | |||
| 103 | static inline int atomic_add_return(int i, atomic_t * v) | ||
| 104 | { | ||
| 105 | unsigned long temp, flags; | ||
| 106 | |||
| 107 | local_irq_save(flags); | ||
| 108 | temp = *(long *)v; | ||
| 109 | temp += i; | ||
| 110 | *(long *)v = temp; | ||
| 111 | local_irq_restore(flags); | ||
| 112 | |||
| 113 | return temp; | ||
| 114 | } | ||
| 115 | |||
| 116 | #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) | ||
| 117 | |||
| 118 | static inline int atomic_sub_return(int i, atomic_t * v) | ||
| 119 | { | ||
| 120 | unsigned long temp, flags; | ||
| 121 | |||
| 122 | local_irq_save(flags); | ||
| 123 | temp = *(long *)v; | ||
| 124 | temp -= i; | ||
| 125 | *(long *)v = temp; | ||
| 126 | local_irq_restore(flags); | ||
| 127 | |||
| 128 | return temp; | ||
| 129 | } | ||
| 130 | |||
| 131 | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) | ||
| 132 | #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) | ||
| 133 | |||
| 134 | static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) | ||
| 135 | { | ||
| 136 | int c, old; | ||
| 137 | c = atomic_read(v); | ||
| 138 | for (;;) { | ||
| 139 | if (unlikely(c == (u))) | ||
| 140 | break; | ||
| 141 | old = atomic_cmpxchg((v), c, c + (a)); | ||
| 142 | if (likely(old == c)) | ||
| 143 | break; | ||
| 144 | c = old; | ||
| 145 | } | ||
| 146 | return c != (u); | ||
| 147 | } | ||
| 148 | |||
| 149 | #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) | ||
| 150 | |||
| 151 | #define atomic_dec_return(v) atomic_sub_return(1,(v)) | ||
| 152 | #define atomic_inc_return(v) atomic_add_return(1,(v)) | ||
| 153 | |||
| 154 | #include <asm-generic/atomic.h> | ||
| 155 | #endif /* __ARCH_M68KNOMMU_ATOMIC __ */ | ||
diff --git a/arch/m68k/include/asm/auxvec.h b/arch/m68k/include/asm/auxvec.h new file mode 100644 index 000000000000..844d6d52204b --- /dev/null +++ b/arch/m68k/include/asm/auxvec.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef __ASMm68k_AUXVEC_H | ||
| 2 | #define __ASMm68k_AUXVEC_H | ||
| 3 | |||
| 4 | #endif | ||
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h new file mode 100644 index 000000000000..ce163abddaba --- /dev/null +++ b/arch/m68k/include/asm/bitops.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "bitops_no.h" | ||
| 3 | #else | ||
| 4 | #include "bitops_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h new file mode 100644 index 000000000000..9bde784e7bad --- /dev/null +++ b/arch/m68k/include/asm/bitops_mm.h | |||
| @@ -0,0 +1,464 @@ | |||
| 1 | #ifndef _M68K_BITOPS_H | ||
| 2 | #define _M68K_BITOPS_H | ||
| 3 | /* | ||
| 4 | * Copyright 1992, Linus Torvalds. | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef _LINUX_BITOPS_H | ||
| 12 | #error only <linux/bitops.h> can be included directly | ||
| 13 | #endif | ||
| 14 | |||
| 15 | #include <linux/compiler.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Require 68020 or better. | ||
| 19 | * | ||
| 20 | * They use the standard big-endian m680x0 bit ordering. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define test_and_set_bit(nr,vaddr) \ | ||
| 24 | (__builtin_constant_p(nr) ? \ | ||
| 25 | __constant_test_and_set_bit(nr, vaddr) : \ | ||
| 26 | __generic_test_and_set_bit(nr, vaddr)) | ||
| 27 | |||
| 28 | #define __test_and_set_bit(nr,vaddr) test_and_set_bit(nr,vaddr) | ||
| 29 | |||
| 30 | static inline int __constant_test_and_set_bit(int nr, unsigned long *vaddr) | ||
| 31 | { | ||
| 32 | char *p = (char *)vaddr + (nr ^ 31) / 8; | ||
| 33 | char retval; | ||
| 34 | |||
| 35 | __asm__ __volatile__ ("bset %2,%1; sne %0" | ||
| 36 | : "=d" (retval), "+m" (*p) | ||
| 37 | : "di" (nr & 7)); | ||
| 38 | |||
| 39 | return retval; | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline int __generic_test_and_set_bit(int nr, unsigned long *vaddr) | ||
| 43 | { | ||
| 44 | char retval; | ||
| 45 | |||
| 46 | __asm__ __volatile__ ("bfset %2{%1:#1}; sne %0" | ||
| 47 | : "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory"); | ||
| 48 | |||
| 49 | return retval; | ||
| 50 | } | ||
| 51 | |||
| 52 | #define set_bit(nr,vaddr) \ | ||
| 53 | (__builtin_constant_p(nr) ? \ | ||
| 54 | __constant_set_bit(nr, vaddr) : \ | ||
| 55 | __generic_set_bit(nr, vaddr)) | ||
| 56 | |||
| 57 | #define __set_bit(nr,vaddr) set_bit(nr,vaddr) | ||
| 58 | |||
| 59 | static inline void __constant_set_bit(int nr, volatile unsigned long *vaddr) | ||
| 60 | { | ||
| 61 | char *p = (char *)vaddr + (nr ^ 31) / 8; | ||
| 62 | __asm__ __volatile__ ("bset %1,%0" | ||
| 63 | : "+m" (*p) : "di" (nr & 7)); | ||
| 64 | } | ||
| 65 | |||
| 66 | static inline void __generic_set_bit(int nr, volatile unsigned long *vaddr) | ||
| 67 | { | ||
| 68 | __asm__ __volatile__ ("bfset %1{%0:#1}" | ||
| 69 | : : "d" (nr^31), "o" (*vaddr) : "memory"); | ||
| 70 | } | ||
| 71 | |||
| 72 | #define test_and_clear_bit(nr,vaddr) \ | ||
| 73 | (__builtin_constant_p(nr) ? \ | ||
| 74 | __constant_test_and_clear_bit(nr, vaddr) : \ | ||
| 75 | __generic_test_and_clear_bit(nr, vaddr)) | ||
| 76 | |||
| 77 | #define __test_and_clear_bit(nr,vaddr) test_and_clear_bit(nr,vaddr) | ||
| 78 | |||
| 79 | static inline int __constant_test_and_clear_bit(int nr, unsigned long *vaddr) | ||
| 80 | { | ||
| 81 | char *p = (char *)vaddr + (nr ^ 31) / 8; | ||
| 82 | char retval; | ||
| 83 | |||
| 84 | __asm__ __volatile__ ("bclr %2,%1; sne %0" | ||
| 85 | : "=d" (retval), "+m" (*p) | ||
| 86 | : "di" (nr & 7)); | ||
| 87 | |||
| 88 | return retval; | ||
| 89 | } | ||
| 90 | |||
| 91 | static inline int __generic_test_and_clear_bit(int nr, unsigned long *vaddr) | ||
| 92 | { | ||
| 93 | char retval; | ||
| 94 | |||
| 95 | __asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0" | ||
| 96 | : "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory"); | ||
| 97 | |||
| 98 | return retval; | ||
| 99 | } | ||
| 100 | |||
| 101 | /* | ||
| 102 | * clear_bit() doesn't provide any barrier for the compiler. | ||
| 103 | */ | ||
| 104 | #define smp_mb__before_clear_bit() barrier() | ||
| 105 | #define smp_mb__after_clear_bit() barrier() | ||
| 106 | |||
| 107 | #define clear_bit(nr,vaddr) \ | ||
| 108 | (__builtin_constant_p(nr) ? \ | ||
| 109 | __constant_clear_bit(nr, vaddr) : \ | ||
| 110 | __generic_clear_bit(nr, vaddr)) | ||
| 111 | #define __clear_bit(nr,vaddr) clear_bit(nr,vaddr) | ||
| 112 | |||
| 113 | static inline void __constant_clear_bit(int nr, volatile unsigned long *vaddr) | ||
| 114 | { | ||
| 115 | char *p = (char *)vaddr + (nr ^ 31) / 8; | ||
| 116 | __asm__ __volatile__ ("bclr %1,%0" | ||
| 117 | : "+m" (*p) : "di" (nr & 7)); | ||
| 118 | } | ||
| 119 | |||
| 120 | static inline void __generic_clear_bit(int nr, volatile unsigned long *vaddr) | ||
| 121 | { | ||
| 122 | __asm__ __volatile__ ("bfclr %1{%0:#1}" | ||
| 123 | : : "d" (nr^31), "o" (*vaddr) : "memory"); | ||
| 124 | } | ||
| 125 | |||
| 126 | #define test_and_change_bit(nr,vaddr) \ | ||
| 127 | (__builtin_constant_p(nr) ? \ | ||
| 128 | __constant_test_and_change_bit(nr, vaddr) : \ | ||
| 129 | __generic_test_and_change_bit(nr, vaddr)) | ||
| 130 | |||
| 131 | #define __test_and_change_bit(nr,vaddr) test_and_change_bit(nr,vaddr) | ||
| 132 | #define __change_bit(nr,vaddr) change_bit(nr,vaddr) | ||
| 133 | |||
| 134 | static inline int __constant_test_and_change_bit(int nr, unsigned long *vaddr) | ||
| 135 | { | ||
| 136 | char *p = (char *)vaddr + (nr ^ 31) / 8; | ||
| 137 | char retval; | ||
| 138 | |||
| 139 | __asm__ __volatile__ ("bchg %2,%1; sne %0" | ||
| 140 | : "=d" (retval), "+m" (*p) | ||
| 141 | : "di" (nr & 7)); | ||
| 142 | |||
| 143 | return retval; | ||
| 144 | } | ||
| 145 | |||
| 146 | static inline int __generic_test_and_change_bit(int nr, unsigned long *vaddr) | ||
| 147 | { | ||
| 148 | char retval; | ||
| 149 | |||
| 150 | __asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0" | ||
| 151 | : "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory"); | ||
| 152 | |||
| 153 | return retval; | ||
| 154 | } | ||
| 155 | |||
| 156 | #define change_bit(nr,vaddr) \ | ||
| 157 | (__builtin_constant_p(nr) ? \ | ||
| 158 | __constant_change_bit(nr, vaddr) : \ | ||
| 159 | __generic_change_bit(nr, vaddr)) | ||
| 160 | |||
| 161 | static inline void __constant_change_bit(int nr, unsigned long *vaddr) | ||
| 162 | { | ||
| 163 | char *p = (char *)vaddr + (nr ^ 31) / 8; | ||
| 164 | __asm__ __volatile__ ("bchg %1,%0" | ||
| 165 | : "+m" (*p) : "di" (nr & 7)); | ||
| 166 | } | ||
| 167 | |||
| 168 | static inline void __generic_change_bit(int nr, unsigned long *vaddr) | ||
| 169 | { | ||
| 170 | __asm__ __volatile__ ("bfchg %1{%0:#1}" | ||
| 171 | : : "d" (nr^31), "o" (*vaddr) : "memory"); | ||
| 172 | } | ||
| 173 | |||
| 174 | static inline int test_bit(int nr, const unsigned long *vaddr) | ||
| 175 | { | ||
| 176 | return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0; | ||
| 177 | } | ||
| 178 | |||
| 179 | static inline int find_first_zero_bit(const unsigned long *vaddr, | ||
| 180 | unsigned size) | ||
| 181 | { | ||
| 182 | const unsigned long *p = vaddr; | ||
| 183 | int res = 32; | ||
| 184 | unsigned long num; | ||
| 185 | |||
| 186 | if (!size) | ||
| 187 | return 0; | ||
| 188 | |||
| 189 | size = (size + 31) >> 5; | ||
| 190 | while (!(num = ~*p++)) { | ||
| 191 | if (!--size) | ||
| 192 | goto out; | ||
| 193 | } | ||
| 194 | |||
| 195 | __asm__ __volatile__ ("bfffo %1{#0,#0},%0" | ||
| 196 | : "=d" (res) : "d" (num & -num)); | ||
| 197 | res ^= 31; | ||
| 198 | out: | ||
| 199 | return ((long)p - (long)vaddr - 4) * 8 + res; | ||
| 200 | } | ||
| 201 | |||
| 202 | static inline int find_next_zero_bit(const unsigned long *vaddr, int size, | ||
| 203 | int offset) | ||
| 204 | { | ||
| 205 | const unsigned long *p = vaddr + (offset >> 5); | ||
| 206 | int bit = offset & 31UL, res; | ||
| 207 | |||
| 208 | if (offset >= size) | ||
| 209 | return size; | ||
| 210 | |||
| 211 | if (bit) { | ||
| 212 | unsigned long num = ~*p++ & (~0UL << bit); | ||
| 213 | offset -= bit; | ||
| 214 | |||
| 215 | /* Look for zero in first longword */ | ||
| 216 | __asm__ __volatile__ ("bfffo %1{#0,#0},%0" | ||
| 217 | : "=d" (res) : "d" (num & -num)); | ||
| 218 | if (res < 32) | ||
| 219 | return offset + (res ^ 31); | ||
| 220 | offset += 32; | ||
| 221 | } | ||
| 222 | /* No zero yet, search remaining full bytes for a zero */ | ||
| 223 | res = find_first_zero_bit(p, size - ((long)p - (long)vaddr) * 8); | ||
| 224 | return offset + res; | ||
| 225 | } | ||
| 226 | |||
| 227 | static inline int find_first_bit(const unsigned long *vaddr, unsigned size) | ||
| 228 | { | ||
| 229 | const unsigned long *p = vaddr; | ||
| 230 | int res = 32; | ||
| 231 | unsigned long num; | ||
| 232 | |||
| 233 | if (!size) | ||
| 234 | return 0; | ||
| 235 | |||
| 236 | size = (size + 31) >> 5; | ||
| 237 | while (!(num = *p++)) { | ||
| 238 | if (!--size) | ||
| 239 | goto out; | ||
| 240 | } | ||
| 241 | |||
| 242 | __asm__ __volatile__ ("bfffo %1{#0,#0},%0" | ||
| 243 | : "=d" (res) : "d" (num & -num)); | ||
| 244 | res ^= 31; | ||
| 245 | out: | ||
| 246 | return ((long)p - (long)vaddr - 4) * 8 + res; | ||
| 247 | } | ||
| 248 | |||
| 249 | static inline int find_next_bit(const unsigned long *vaddr, int size, | ||
| 250 | int offset) | ||
| 251 | { | ||
| 252 | const unsigned long *p = vaddr + (offset >> 5); | ||
| 253 | int bit = offset & 31UL, res; | ||
| 254 | |||
| 255 | if (offset >= size) | ||
| 256 | return size; | ||
| 257 | |||
| 258 | if (bit) { | ||
| 259 | unsigned long num = *p++ & (~0UL << bit); | ||
| 260 | offset -= bit; | ||
| 261 | |||
| 262 | /* Look for one in first longword */ | ||
| 263 | __asm__ __volatile__ ("bfffo %1{#0,#0},%0" | ||
| 264 | : "=d" (res) : "d" (num & -num)); | ||
| 265 | if (res < 32) | ||
| 266 | return offset + (res ^ 31); | ||
| 267 | offset += 32; | ||
| 268 | } | ||
| 269 | /* No one yet, search remaining full bytes for a one */ | ||
| 270 | res = find_first_bit(p, size - ((long)p - (long)vaddr) * 8); | ||
| 271 | return offset + res; | ||
| 272 | } | ||
| 273 | |||
| 274 | /* | ||
| 275 | * ffz = Find First Zero in word. Undefined if no zero exists, | ||
| 276 | * so code should check against ~0UL first.. | ||
| 277 | */ | ||
| 278 | static inline unsigned long ffz(unsigned long word) | ||
| 279 | { | ||
| 280 | int res; | ||
| 281 | |||
| 282 | __asm__ __volatile__ ("bfffo %1{#0,#0},%0" | ||
| 283 | : "=d" (res) : "d" (~word & -~word)); | ||
| 284 | return res ^ 31; | ||
| 285 | } | ||
| 286 | |||
| 287 | #ifdef __KERNEL__ | ||
| 288 | |||
| 289 | /* | ||
| 290 | * ffs: find first bit set. This is defined the same way as | ||
| 291 | * the libc and compiler builtin ffs routines, therefore | ||
| 292 | * differs in spirit from the above ffz (man ffs). | ||
| 293 | */ | ||
| 294 | |||
| 295 | static inline int ffs(int x) | ||
| 296 | { | ||
| 297 | int cnt; | ||
| 298 | |||
| 299 | asm ("bfffo %1{#0:#0},%0" : "=d" (cnt) : "dm" (x & -x)); | ||
| 300 | |||
| 301 | return 32 - cnt; | ||
| 302 | } | ||
| 303 | #define __ffs(x) (ffs(x) - 1) | ||
| 304 | |||
| 305 | /* | ||
| 306 | * fls: find last bit set. | ||
| 307 | */ | ||
| 308 | |||
| 309 | static inline int fls(int x) | ||
| 310 | { | ||
| 311 | int cnt; | ||
| 312 | |||
| 313 | asm ("bfffo %1{#0,#0},%0" : "=d" (cnt) : "dm" (x)); | ||
| 314 | |||
| 315 | return 32 - cnt; | ||
| 316 | } | ||
| 317 | |||
| 318 | static inline int __fls(int x) | ||
| 319 | { | ||
| 320 | return fls(x) - 1; | ||
| 321 | } | ||
| 322 | |||
| 323 | #include <asm-generic/bitops/fls64.h> | ||
| 324 | #include <asm-generic/bitops/sched.h> | ||
| 325 | #include <asm-generic/bitops/hweight.h> | ||
| 326 | #include <asm-generic/bitops/lock.h> | ||
| 327 | |||
| 328 | /* Bitmap functions for the minix filesystem */ | ||
| 329 | |||
| 330 | static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size) | ||
| 331 | { | ||
| 332 | const unsigned short *p = vaddr, *addr = vaddr; | ||
| 333 | int res; | ||
| 334 | unsigned short num; | ||
| 335 | |||
| 336 | if (!size) | ||
| 337 | return 0; | ||
| 338 | |||
| 339 | size = (size >> 4) + ((size & 15) > 0); | ||
| 340 | while (*p++ == 0xffff) | ||
| 341 | { | ||
| 342 | if (--size == 0) | ||
| 343 | return (p - addr) << 4; | ||
| 344 | } | ||
| 345 | |||
| 346 | num = ~*--p; | ||
| 347 | __asm__ __volatile__ ("bfffo %1{#16,#16},%0" | ||
| 348 | : "=d" (res) : "d" (num & -num)); | ||
| 349 | return ((p - addr) << 4) + (res ^ 31); | ||
| 350 | } | ||
| 351 | |||
| 352 | #define minix_test_and_set_bit(nr, addr) __test_and_set_bit((nr) ^ 16, (unsigned long *)(addr)) | ||
| 353 | #define minix_set_bit(nr,addr) __set_bit((nr) ^ 16, (unsigned long *)(addr)) | ||
| 354 | #define minix_test_and_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr)) | ||
| 355 | |||
| 356 | static inline int minix_test_bit(int nr, const void *vaddr) | ||
| 357 | { | ||
| 358 | const unsigned short *p = vaddr; | ||
| 359 | return (p[nr >> 4] & (1U << (nr & 15))) != 0; | ||
| 360 | } | ||
| 361 | |||
| 362 | /* Bitmap functions for the ext2 filesystem. */ | ||
| 363 | |||
| 364 | #define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) | ||
| 365 | #define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, (unsigned long *)(addr)) | ||
| 366 | #define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) | ||
| 367 | #define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, (unsigned long *)(addr)) | ||
| 368 | |||
| 369 | static inline int ext2_test_bit(int nr, const void *vaddr) | ||
| 370 | { | ||
| 371 | const unsigned char *p = vaddr; | ||
| 372 | return (p[nr >> 3] & (1U << (nr & 7))) != 0; | ||
| 373 | } | ||
| 374 | |||
| 375 | static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size) | ||
| 376 | { | ||
| 377 | const unsigned long *p = vaddr, *addr = vaddr; | ||
| 378 | int res; | ||
| 379 | |||
| 380 | if (!size) | ||
| 381 | return 0; | ||
| 382 | |||
| 383 | size = (size >> 5) + ((size & 31) > 0); | ||
| 384 | while (*p++ == ~0UL) | ||
| 385 | { | ||
| 386 | if (--size == 0) | ||
| 387 | return (p - addr) << 5; | ||
| 388 | } | ||
| 389 | |||
| 390 | --p; | ||
| 391 | for (res = 0; res < 32; res++) | ||
| 392 | if (!ext2_test_bit (res, p)) | ||
| 393 | break; | ||
| 394 | return (p - addr) * 32 + res; | ||
| 395 | } | ||
| 396 | |||
| 397 | static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size, | ||
| 398 | unsigned offset) | ||
| 399 | { | ||
| 400 | const unsigned long *addr = vaddr; | ||
| 401 | const unsigned long *p = addr + (offset >> 5); | ||
| 402 | int bit = offset & 31UL, res; | ||
| 403 | |||
| 404 | if (offset >= size) | ||
| 405 | return size; | ||
| 406 | |||
| 407 | if (bit) { | ||
| 408 | /* Look for zero in first longword */ | ||
| 409 | for (res = bit; res < 32; res++) | ||
| 410 | if (!ext2_test_bit (res, p)) | ||
| 411 | return (p - addr) * 32 + res; | ||
| 412 | p++; | ||
| 413 | } | ||
| 414 | /* No zero yet, search remaining full bytes for a zero */ | ||
| 415 | res = ext2_find_first_zero_bit (p, size - 32 * (p - addr)); | ||
| 416 | return (p - addr) * 32 + res; | ||
| 417 | } | ||
| 418 | |||
| 419 | static inline int ext2_find_first_bit(const void *vaddr, unsigned size) | ||
| 420 | { | ||
| 421 | const unsigned long *p = vaddr, *addr = vaddr; | ||
| 422 | int res; | ||
| 423 | |||
| 424 | if (!size) | ||
| 425 | return 0; | ||
| 426 | |||
| 427 | size = (size >> 5) + ((size & 31) > 0); | ||
| 428 | while (*p++ == 0UL) { | ||
| 429 | if (--size == 0) | ||
| 430 | return (p - addr) << 5; | ||
| 431 | } | ||
| 432 | |||
| 433 | --p; | ||
| 434 | for (res = 0; res < 32; res++) | ||
| 435 | if (ext2_test_bit(res, p)) | ||
| 436 | break; | ||
| 437 | return (p - addr) * 32 + res; | ||
| 438 | } | ||
| 439 | |||
| 440 | static inline int ext2_find_next_bit(const void *vaddr, unsigned size, | ||
| 441 | unsigned offset) | ||
| 442 | { | ||
| 443 | const unsigned long *addr = vaddr; | ||
| 444 | const unsigned long *p = addr + (offset >> 5); | ||
| 445 | int bit = offset & 31UL, res; | ||
| 446 | |||
| 447 | if (offset >= size) | ||
| 448 | return size; | ||
| 449 | |||
| 450 | if (bit) { | ||
| 451 | /* Look for one in first longword */ | ||
| 452 | for (res = bit; res < 32; res++) | ||
| 453 | if (ext2_test_bit(res, p)) | ||
| 454 | return (p - addr) * 32 + res; | ||
| 455 | p++; | ||
| 456 | } | ||
| 457 | /* No set bit yet, search remaining full bytes for a set bit */ | ||
| 458 | res = ext2_find_first_bit(p, size - 32 * (p - addr)); | ||
| 459 | return (p - addr) * 32 + res; | ||
| 460 | } | ||
| 461 | |||
| 462 | #endif /* __KERNEL__ */ | ||
| 463 | |||
| 464 | #endif /* _M68K_BITOPS_H */ | ||
diff --git a/arch/m68k/include/asm/bitops_no.h b/arch/m68k/include/asm/bitops_no.h new file mode 100644 index 000000000000..9d3cbe5fad1e --- /dev/null +++ b/arch/m68k/include/asm/bitops_no.h | |||
| @@ -0,0 +1,337 @@ | |||
| 1 | #ifndef _M68KNOMMU_BITOPS_H | ||
| 2 | #define _M68KNOMMU_BITOPS_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Copyright 1992, Linus Torvalds. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <asm/byteorder.h> /* swab32 */ | ||
| 10 | |||
| 11 | #ifdef __KERNEL__ | ||
| 12 | |||
| 13 | #ifndef _LINUX_BITOPS_H | ||
| 14 | #error only <linux/bitops.h> can be included directly | ||
| 15 | #endif | ||
| 16 | |||
| 17 | #if defined (__mcfisaaplus__) || defined (__mcfisac__) | ||
| 18 | static inline int ffs(unsigned int val) | ||
| 19 | { | ||
| 20 | if (!val) | ||
| 21 | return 0; | ||
| 22 | |||
| 23 | asm volatile( | ||
| 24 | "bitrev %0\n\t" | ||
| 25 | "ff1 %0\n\t" | ||
| 26 | : "=d" (val) | ||
| 27 | : "0" (val) | ||
| 28 | ); | ||
| 29 | val++; | ||
| 30 | return val; | ||
| 31 | } | ||
| 32 | |||
| 33 | static inline int __ffs(unsigned int val) | ||
| 34 | { | ||
| 35 | asm volatile( | ||
| 36 | "bitrev %0\n\t" | ||
| 37 | "ff1 %0\n\t" | ||
| 38 | : "=d" (val) | ||
| 39 | : "0" (val) | ||
| 40 | ); | ||
| 41 | return val; | ||
| 42 | } | ||
| 43 | |||
| 44 | #else | ||
| 45 | #include <asm-generic/bitops/ffs.h> | ||
| 46 | #include <asm-generic/bitops/__ffs.h> | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #include <asm-generic/bitops/sched.h> | ||
| 50 | #include <asm-generic/bitops/ffz.h> | ||
| 51 | |||
| 52 | static __inline__ void set_bit(int nr, volatile unsigned long * addr) | ||
| 53 | { | ||
| 54 | #ifdef CONFIG_COLDFIRE | ||
| 55 | __asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)" | ||
| 56 | : "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 57 | : "d" (nr) | ||
| 58 | : "%a0", "cc"); | ||
| 59 | #else | ||
| 60 | __asm__ __volatile__ ("bset %1,%0" | ||
| 61 | : "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 62 | : "di" (nr) | ||
| 63 | : "cc"); | ||
| 64 | #endif | ||
| 65 | } | ||
| 66 | |||
| 67 | #define __set_bit(nr, addr) set_bit(nr, addr) | ||
| 68 | |||
| 69 | /* | ||
| 70 | * clear_bit() doesn't provide any barrier for the compiler. | ||
| 71 | */ | ||
| 72 | #define smp_mb__before_clear_bit() barrier() | ||
| 73 | #define smp_mb__after_clear_bit() barrier() | ||
| 74 | |||
| 75 | static __inline__ void clear_bit(int nr, volatile unsigned long * addr) | ||
| 76 | { | ||
| 77 | #ifdef CONFIG_COLDFIRE | ||
| 78 | __asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)" | ||
| 79 | : "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 80 | : "d" (nr) | ||
| 81 | : "%a0", "cc"); | ||
| 82 | #else | ||
| 83 | __asm__ __volatile__ ("bclr %1,%0" | ||
| 84 | : "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 85 | : "di" (nr) | ||
| 86 | : "cc"); | ||
| 87 | #endif | ||
| 88 | } | ||
| 89 | |||
| 90 | #define __clear_bit(nr, addr) clear_bit(nr, addr) | ||
| 91 | |||
| 92 | static __inline__ void change_bit(int nr, volatile unsigned long * addr) | ||
| 93 | { | ||
| 94 | #ifdef CONFIG_COLDFIRE | ||
| 95 | __asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)" | ||
| 96 | : "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 97 | : "d" (nr) | ||
| 98 | : "%a0", "cc"); | ||
| 99 | #else | ||
| 100 | __asm__ __volatile__ ("bchg %1,%0" | ||
| 101 | : "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 102 | : "di" (nr) | ||
| 103 | : "cc"); | ||
| 104 | #endif | ||
| 105 | } | ||
| 106 | |||
| 107 | #define __change_bit(nr, addr) change_bit(nr, addr) | ||
| 108 | |||
| 109 | static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr) | ||
| 110 | { | ||
| 111 | char retval; | ||
| 112 | |||
| 113 | #ifdef CONFIG_COLDFIRE | ||
| 114 | __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" | ||
| 115 | : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 116 | : "d" (nr) | ||
| 117 | : "%a0"); | ||
| 118 | #else | ||
| 119 | __asm__ __volatile__ ("bset %2,%1; sne %0" | ||
| 120 | : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 121 | : "di" (nr) | ||
| 122 | /* No clobber */); | ||
| 123 | #endif | ||
| 124 | |||
| 125 | return retval; | ||
| 126 | } | ||
| 127 | |||
| 128 | #define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) | ||
| 129 | |||
| 130 | static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr) | ||
| 131 | { | ||
| 132 | char retval; | ||
| 133 | |||
| 134 | #ifdef CONFIG_COLDFIRE | ||
| 135 | __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" | ||
| 136 | : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 137 | : "d" (nr) | ||
| 138 | : "%a0"); | ||
| 139 | #else | ||
| 140 | __asm__ __volatile__ ("bclr %2,%1; sne %0" | ||
| 141 | : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 142 | : "di" (nr) | ||
| 143 | /* No clobber */); | ||
| 144 | #endif | ||
| 145 | |||
| 146 | return retval; | ||
| 147 | } | ||
| 148 | |||
| 149 | #define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) | ||
| 150 | |||
| 151 | static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr) | ||
| 152 | { | ||
| 153 | char retval; | ||
| 154 | |||
| 155 | #ifdef CONFIG_COLDFIRE | ||
| 156 | __asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0" | ||
| 157 | : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 158 | : "d" (nr) | ||
| 159 | : "%a0"); | ||
| 160 | #else | ||
| 161 | __asm__ __volatile__ ("bchg %2,%1; sne %0" | ||
| 162 | : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) | ||
| 163 | : "di" (nr) | ||
| 164 | /* No clobber */); | ||
| 165 | #endif | ||
| 166 | |||
| 167 | return retval; | ||
| 168 | } | ||
| 169 | |||
| 170 | #define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr) | ||
| 171 | |||
| 172 | /* | ||
| 173 | * This routine doesn't need to be atomic. | ||
| 174 | */ | ||
| 175 | static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr) | ||
| 176 | { | ||
| 177 | return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; | ||
| 178 | } | ||
| 179 | |||
| 180 | static __inline__ int __test_bit(int nr, const volatile unsigned long * addr) | ||
| 181 | { | ||
| 182 | int * a = (int *) addr; | ||
| 183 | int mask; | ||
| 184 | |||
| 185 | a += nr >> 5; | ||
| 186 | mask = 1 << (nr & 0x1f); | ||
| 187 | return ((mask & *a) != 0); | ||
| 188 | } | ||
| 189 | |||
| 190 | #define test_bit(nr,addr) \ | ||
| 191 | (__builtin_constant_p(nr) ? \ | ||
| 192 | __constant_test_bit((nr),(addr)) : \ | ||
| 193 | __test_bit((nr),(addr))) | ||
| 194 | |||
| 195 | #include <asm-generic/bitops/find.h> | ||
| 196 | #include <asm-generic/bitops/hweight.h> | ||
| 197 | #include <asm-generic/bitops/lock.h> | ||
| 198 | |||
| 199 | static __inline__ int ext2_set_bit(int nr, volatile void * addr) | ||
| 200 | { | ||
| 201 | char retval; | ||
| 202 | |||
| 203 | #ifdef CONFIG_COLDFIRE | ||
| 204 | __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" | ||
| 205 | : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) | ||
| 206 | : "d" (nr) | ||
| 207 | : "%a0"); | ||
| 208 | #else | ||
| 209 | __asm__ __volatile__ ("bset %2,%1; sne %0" | ||
| 210 | : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) | ||
| 211 | : "di" (nr) | ||
| 212 | /* No clobber */); | ||
| 213 | #endif | ||
| 214 | |||
| 215 | return retval; | ||
| 216 | } | ||
| 217 | |||
| 218 | static __inline__ int ext2_clear_bit(int nr, volatile void * addr) | ||
| 219 | { | ||
| 220 | char retval; | ||
| 221 | |||
| 222 | #ifdef CONFIG_COLDFIRE | ||
| 223 | __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" | ||
| 224 | : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) | ||
| 225 | : "d" (nr) | ||
| 226 | : "%a0"); | ||
| 227 | #else | ||
| 228 | __asm__ __volatile__ ("bclr %2,%1; sne %0" | ||
| 229 | : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) | ||
| 230 | : "di" (nr) | ||
| 231 | /* No clobber */); | ||
| 232 | #endif | ||
| 233 | |||
| 234 | return retval; | ||
| 235 | } | ||
| 236 | |||
| 237 | #define ext2_set_bit_atomic(lock, nr, addr) \ | ||
| 238 | ({ \ | ||
| 239 | int ret; \ | ||
| 240 | spin_lock(lock); \ | ||
| 241 | ret = ext2_set_bit((nr), (addr)); \ | ||
| 242 | spin_unlock(lock); \ | ||
| 243 | ret; \ | ||
| 244 | }) | ||
| 245 | |||
| 246 | #define ext2_clear_bit_atomic(lock, nr, addr) \ | ||
| 247 | ({ \ | ||
| 248 | int ret; \ | ||
| 249 | spin_lock(lock); \ | ||
| 250 | ret = ext2_clear_bit((nr), (addr)); \ | ||
| 251 | spin_unlock(lock); \ | ||
| 252 | ret; \ | ||
| 253 | }) | ||
| 254 | |||
| 255 | static __inline__ int ext2_test_bit(int nr, const volatile void * addr) | ||
| 256 | { | ||
| 257 | char retval; | ||
| 258 | |||
| 259 | #ifdef CONFIG_COLDFIRE | ||
| 260 | __asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0" | ||
| 261 | : "=d" (retval) | ||
| 262 | : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr) | ||
| 263 | : "%a0"); | ||
| 264 | #else | ||
| 265 | __asm__ __volatile__ ("btst %2,%1; sne %0" | ||
| 266 | : "=d" (retval) | ||
| 267 | : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr) | ||
| 268 | /* No clobber */); | ||
| 269 | #endif | ||
| 270 | |||
| 271 | return retval; | ||
| 272 | } | ||
| 273 | |||
| 274 | #define ext2_find_first_zero_bit(addr, size) \ | ||
| 275 | ext2_find_next_zero_bit((addr), (size), 0) | ||
| 276 | |||
| 277 | static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) | ||
| 278 | { | ||
| 279 | unsigned long *p = ((unsigned long *) addr) + (offset >> 5); | ||
| 280 | unsigned long result = offset & ~31UL; | ||
| 281 | unsigned long tmp; | ||
| 282 | |||
| 283 | if (offset >= size) | ||
| 284 | return size; | ||
| 285 | size -= result; | ||
| 286 | offset &= 31UL; | ||
| 287 | if(offset) { | ||
| 288 | /* We hold the little endian value in tmp, but then the | ||
| 289 | * shift is illegal. So we could keep a big endian value | ||
| 290 | * in tmp, like this: | ||
| 291 | * | ||
| 292 | * tmp = __swab32(*(p++)); | ||
| 293 | * tmp |= ~0UL >> (32-offset); | ||
| 294 | * | ||
| 295 | * but this would decrease performance, so we change the | ||
| 296 | * shift: | ||
| 297 | */ | ||
| 298 | tmp = *(p++); | ||
| 299 | tmp |= __swab32(~0UL >> (32-offset)); | ||
| 300 | if(size < 32) | ||
| 301 | goto found_first; | ||
| 302 | if(~tmp) | ||
| 303 | goto found_middle; | ||
| 304 | size -= 32; | ||
| 305 | result += 32; | ||
| 306 | } | ||
| 307 | while(size & ~31UL) { | ||
| 308 | if(~(tmp = *(p++))) | ||
| 309 | goto found_middle; | ||
| 310 | result += 32; | ||
| 311 | size -= 32; | ||
| 312 | } | ||
| 313 | if(!size) | ||
| 314 | return result; | ||
| 315 | tmp = *p; | ||
| 316 | |||
| 317 | found_first: | ||
| 318 | /* tmp is little endian, so we would have to swab the shift, | ||
| 319 | * see above. But then we have to swab tmp below for ffz, so | ||
| 320 | * we might as well do this here. | ||
| 321 | */ | ||
| 322 | return result + ffz(__swab32(tmp) | (~0UL << size)); | ||
| 323 | found_middle: | ||
| 324 | return result + ffz(__swab32(tmp)); | ||
| 325 | } | ||
| 326 | |||
| 327 | #define ext2_find_next_bit(addr, size, off) \ | ||
| 328 | generic_find_next_le_bit((unsigned long *)(addr), (size), (off)) | ||
| 329 | #include <asm-generic/bitops/minix.h> | ||
| 330 | |||
| 331 | #endif /* __KERNEL__ */ | ||
| 332 | |||
| 333 | #include <asm-generic/bitops/fls.h> | ||
| 334 | #include <asm-generic/bitops/__fls.h> | ||
| 335 | #include <asm-generic/bitops/fls64.h> | ||
| 336 | |||
| 337 | #endif /* _M68KNOMMU_BITOPS_H */ | ||
diff --git a/arch/m68k/include/asm/blinken.h b/arch/m68k/include/asm/blinken.h new file mode 100644 index 000000000000..1a749cf7b06d --- /dev/null +++ b/arch/m68k/include/asm/blinken.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | ** asm/blinken.h -- m68k blinkenlights support (currently hp300 only) | ||
| 3 | ** | ||
| 4 | ** (c) 1998 Phil Blundell <philb@gnu.org> | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _M68K_BLINKEN_H | ||
| 13 | #define _M68K_BLINKEN_H | ||
| 14 | |||
| 15 | #include <asm/setup.h> | ||
| 16 | #include <asm/io.h> | ||
| 17 | |||
| 18 | #define HP300_LEDS 0xf001ffff | ||
| 19 | |||
| 20 | extern unsigned char ledstate; | ||
| 21 | |||
| 22 | static __inline__ void blinken_leds(int on, int off) | ||
| 23 | { | ||
| 24 | if (MACH_IS_HP300) | ||
| 25 | { | ||
| 26 | ledstate |= on; | ||
| 27 | ledstate &= ~off; | ||
| 28 | out_8(HP300_LEDS, ~ledstate); | ||
| 29 | } | ||
| 30 | } | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/arch/m68k/include/asm/bootinfo.h b/arch/m68k/include/asm/bootinfo.h new file mode 100644 index 000000000000..fedf3e326121 --- /dev/null +++ b/arch/m68k/include/asm/bootinfo.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "bootinfo_no.h" | ||
| 3 | #else | ||
| 4 | #include "bootinfo_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/bootinfo_mm.h b/arch/m68k/include/asm/bootinfo_mm.h new file mode 100644 index 000000000000..fb8a06b9ab6a --- /dev/null +++ b/arch/m68k/include/asm/bootinfo_mm.h | |||
| @@ -0,0 +1,378 @@ | |||
| 1 | /* | ||
| 2 | ** asm/bootinfo.h -- Definition of the Linux/m68k boot information structure | ||
| 3 | ** | ||
| 4 | ** Copyright 1992 by Greg Harp | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | ** Created 09/29/92 by Greg Harp | ||
| 11 | ** | ||
| 12 | ** 5/2/94 Roman Hodek: | ||
| 13 | ** Added bi_atari part of the machine dependent union bi_un; for now it | ||
| 14 | ** contains just a model field to distinguish between TT and Falcon. | ||
| 15 | ** 26/7/96 Roman Zippel: | ||
| 16 | ** Renamed to setup.h; added some useful macros to allow gcc some | ||
| 17 | ** optimizations if possible. | ||
| 18 | ** 5/10/96 Geert Uytterhoeven: | ||
| 19 | ** Redesign of the boot information structure; renamed to bootinfo.h again | ||
| 20 | ** 27/11/96 Geert Uytterhoeven: | ||
| 21 | ** Backwards compatibility with bootinfo interface version 1.0 | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef _M68K_BOOTINFO_H | ||
| 25 | #define _M68K_BOOTINFO_H | ||
| 26 | |||
| 27 | |||
| 28 | /* | ||
| 29 | * Bootinfo definitions | ||
| 30 | * | ||
| 31 | * This is an easily parsable and extendable structure containing all | ||
| 32 | * information to be passed from the bootstrap to the kernel. | ||
| 33 | * | ||
| 34 | * This way I hope to keep all future changes back/forewards compatible. | ||
| 35 | * Thus, keep your fingers crossed... | ||
| 36 | * | ||
| 37 | * This structure is copied right after the kernel bss by the bootstrap | ||
| 38 | * routine. | ||
| 39 | */ | ||
| 40 | |||
| 41 | #ifndef __ASSEMBLY__ | ||
| 42 | |||
| 43 | struct bi_record { | ||
| 44 | unsigned short tag; /* tag ID */ | ||
| 45 | unsigned short size; /* size of record (in bytes) */ | ||
| 46 | unsigned long data[0]; /* data */ | ||
| 47 | }; | ||
| 48 | |||
| 49 | #endif /* __ASSEMBLY__ */ | ||
| 50 | |||
| 51 | |||
| 52 | /* | ||
| 53 | * Tag Definitions | ||
| 54 | * | ||
| 55 | * Machine independent tags start counting from 0x0000 | ||
| 56 | * Machine dependent tags start counting from 0x8000 | ||
| 57 | */ | ||
| 58 | |||
| 59 | #define BI_LAST 0x0000 /* last record (sentinel) */ | ||
| 60 | #define BI_MACHTYPE 0x0001 /* machine type (u_long) */ | ||
| 61 | #define BI_CPUTYPE 0x0002 /* cpu type (u_long) */ | ||
| 62 | #define BI_FPUTYPE 0x0003 /* fpu type (u_long) */ | ||
| 63 | #define BI_MMUTYPE 0x0004 /* mmu type (u_long) */ | ||
| 64 | #define BI_MEMCHUNK 0x0005 /* memory chunk address and size */ | ||
| 65 | /* (struct mem_info) */ | ||
| 66 | #define BI_RAMDISK 0x0006 /* ramdisk address and size */ | ||
| 67 | /* (struct mem_info) */ | ||
| 68 | #define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */ | ||
| 69 | /* (string) */ | ||
| 70 | |||
| 71 | /* | ||
| 72 | * Amiga-specific tags | ||
| 73 | */ | ||
| 74 | |||
| 75 | #define BI_AMIGA_MODEL 0x8000 /* model (u_long) */ | ||
| 76 | #define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */ | ||
| 77 | /* (struct ConfigDev) */ | ||
| 78 | #define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */ | ||
| 79 | #define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */ | ||
| 80 | #define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */ | ||
| 81 | #define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */ | ||
| 82 | #define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */ | ||
| 83 | #define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */ | ||
| 84 | |||
| 85 | /* | ||
| 86 | * Atari-specific tags | ||
| 87 | */ | ||
| 88 | |||
| 89 | #define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */ | ||
| 90 | #define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */ | ||
| 91 | /* (values are ATARI_MACH_* defines */ | ||
| 92 | |||
| 93 | /* mch_cookie values (upper word) */ | ||
| 94 | #define ATARI_MCH_ST 0 | ||
| 95 | #define ATARI_MCH_STE 1 | ||
| 96 | #define ATARI_MCH_TT 2 | ||
| 97 | #define ATARI_MCH_FALCON 3 | ||
| 98 | |||
| 99 | /* mch_type values */ | ||
| 100 | #define ATARI_MACH_NORMAL 0 /* no special machine type */ | ||
| 101 | #define ATARI_MACH_MEDUSA 1 /* Medusa 040 */ | ||
| 102 | #define ATARI_MACH_HADES 2 /* Hades 040 or 060 */ | ||
| 103 | #define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */ | ||
| 104 | |||
| 105 | /* | ||
| 106 | * VME-specific tags | ||
| 107 | */ | ||
| 108 | |||
| 109 | #define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */ | ||
| 110 | #define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */ | ||
| 111 | |||
| 112 | /* BI_VME_TYPE codes */ | ||
| 113 | #define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */ | ||
| 114 | #define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */ | ||
| 115 | #define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */ | ||
| 116 | #define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */ | ||
| 117 | #define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */ | ||
| 118 | #define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */ | ||
| 119 | #define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */ | ||
| 120 | #define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */ | ||
| 121 | #define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */ | ||
| 122 | |||
| 123 | /* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on | ||
| 124 | * Motorola VME boards. Contains board number, Bug version, board | ||
| 125 | * configuration options, etc. See include/asm/mvme16xhw.h for details. | ||
| 126 | */ | ||
| 127 | |||
| 128 | |||
| 129 | /* | ||
| 130 | * Macintosh-specific tags (all u_long) | ||
| 131 | */ | ||
| 132 | |||
| 133 | #define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */ | ||
| 134 | #define BI_MAC_VADDR 0x8001 /* Mac video base address */ | ||
| 135 | #define BI_MAC_VDEPTH 0x8002 /* Mac video depth */ | ||
| 136 | #define BI_MAC_VROW 0x8003 /* Mac video rowbytes */ | ||
| 137 | #define BI_MAC_VDIM 0x8004 /* Mac video dimensions */ | ||
| 138 | #define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */ | ||
| 139 | #define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */ | ||
| 140 | #define BI_MAC_BTIME 0x8007 /* Mac boot time */ | ||
| 141 | #define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */ | ||
| 142 | #define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */ | ||
| 143 | #define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */ | ||
| 144 | #define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */ | ||
| 145 | |||
| 146 | /* | ||
| 147 | * Macintosh hardware profile data - unused, see macintosh.h for | ||
| 148 | * resonable type values | ||
| 149 | */ | ||
| 150 | |||
| 151 | #define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */ | ||
| 152 | #define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */ | ||
| 153 | #define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */ | ||
| 154 | #define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */ | ||
| 155 | #define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */ | ||
| 156 | #define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */ | ||
| 157 | #define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */ | ||
| 158 | #define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */ | ||
| 159 | #define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */ | ||
| 160 | #define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */ | ||
| 161 | #define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */ | ||
| 162 | #define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */ | ||
| 163 | #define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */ | ||
| 164 | #define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */ | ||
| 165 | #define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */ | ||
| 166 | #define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */ | ||
| 167 | #define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */ | ||
| 168 | #define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */ | ||
| 169 | |||
| 170 | /* | ||
| 171 | * Mac: compatibility with old booter data format (temporarily) | ||
| 172 | * Fields unused with the new bootinfo can be deleted now; instead of | ||
| 173 | * adding new fields the struct might be splitted into a hardware address | ||
| 174 | * part and a hardware type part | ||
| 175 | */ | ||
| 176 | |||
| 177 | #ifndef __ASSEMBLY__ | ||
| 178 | |||
| 179 | struct mac_booter_data | ||
| 180 | { | ||
| 181 | unsigned long videoaddr; | ||
| 182 | unsigned long videorow; | ||
| 183 | unsigned long videodepth; | ||
| 184 | unsigned long dimensions; | ||
| 185 | unsigned long args; | ||
| 186 | unsigned long boottime; | ||
| 187 | unsigned long gmtbias; | ||
| 188 | unsigned long bootver; | ||
| 189 | unsigned long videological; | ||
| 190 | unsigned long sccbase; | ||
| 191 | unsigned long id; | ||
| 192 | unsigned long memsize; | ||
| 193 | unsigned long serialmf; | ||
| 194 | unsigned long serialhsk; | ||
| 195 | unsigned long serialgpi; | ||
| 196 | unsigned long printmf; | ||
| 197 | unsigned long printhsk; | ||
| 198 | unsigned long printgpi; | ||
| 199 | unsigned long cpuid; | ||
| 200 | unsigned long rombase; | ||
| 201 | unsigned long adbdelay; | ||
| 202 | unsigned long timedbra; | ||
| 203 | }; | ||
| 204 | |||
| 205 | extern struct mac_booter_data | ||
| 206 | mac_bi_data; | ||
| 207 | |||
| 208 | #endif | ||
| 209 | |||
| 210 | /* | ||
| 211 | * Apollo-specific tags | ||
| 212 | */ | ||
| 213 | |||
| 214 | #define BI_APOLLO_MODEL 0x8000 /* model (u_long) */ | ||
| 215 | |||
| 216 | /* | ||
| 217 | * HP300-specific tags | ||
| 218 | */ | ||
| 219 | |||
| 220 | #define BI_HP300_MODEL 0x8000 /* model (u_long) */ | ||
| 221 | #define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */ | ||
| 222 | #define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */ | ||
| 223 | |||
| 224 | /* | ||
| 225 | * Stuff for bootinfo interface versioning | ||
| 226 | * | ||
| 227 | * At the start of kernel code, a 'struct bootversion' is located. | ||
| 228 | * bootstrap checks for a matching version of the interface before booting | ||
| 229 | * a kernel, to avoid user confusion if kernel and bootstrap don't work | ||
| 230 | * together :-) | ||
| 231 | * | ||
| 232 | * If incompatible changes are made to the bootinfo interface, the major | ||
| 233 | * number below should be stepped (and the minor reset to 0) for the | ||
| 234 | * appropriate machine. If a change is backward-compatible, the minor | ||
| 235 | * should be stepped. "Backwards-compatible" means that booting will work, | ||
| 236 | * but certain features may not. | ||
| 237 | */ | ||
| 238 | |||
| 239 | #define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */ | ||
| 240 | #define MK_BI_VERSION(major,minor) (((major)<<16)+(minor)) | ||
| 241 | #define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff) | ||
| 242 | #define BI_VERSION_MINOR(v) ((v) & 0xffff) | ||
| 243 | |||
| 244 | #ifndef __ASSEMBLY__ | ||
| 245 | |||
| 246 | struct bootversion { | ||
| 247 | unsigned short branch; | ||
| 248 | unsigned long magic; | ||
| 249 | struct { | ||
| 250 | unsigned long machtype; | ||
| 251 | unsigned long version; | ||
| 252 | } machversions[0]; | ||
| 253 | }; | ||
| 254 | |||
| 255 | #endif /* __ASSEMBLY__ */ | ||
| 256 | |||
| 257 | #define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) | ||
| 258 | #define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 ) | ||
| 259 | #define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) | ||
| 260 | #define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) | ||
| 261 | #define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) | ||
| 262 | #define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) | ||
| 263 | #define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) | ||
| 264 | #define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) | ||
| 265 | |||
| 266 | #ifdef BOOTINFO_COMPAT_1_0 | ||
| 267 | |||
| 268 | /* | ||
| 269 | * Backwards compatibility with bootinfo interface version 1.0 | ||
| 270 | */ | ||
| 271 | |||
| 272 | #define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) | ||
| 273 | #define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) | ||
| 274 | #define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) | ||
| 275 | |||
| 276 | #include <linux/zorro.h> | ||
| 277 | |||
| 278 | #define COMPAT_NUM_AUTO 16 | ||
| 279 | |||
| 280 | struct compat_bi_Amiga { | ||
| 281 | int model; | ||
| 282 | int num_autocon; | ||
| 283 | struct ConfigDev autocon[COMPAT_NUM_AUTO]; | ||
| 284 | unsigned long chip_size; | ||
| 285 | unsigned char vblank; | ||
| 286 | unsigned char psfreq; | ||
| 287 | unsigned long eclock; | ||
| 288 | unsigned long chipset; | ||
| 289 | unsigned long hw_present; | ||
| 290 | }; | ||
| 291 | |||
| 292 | struct compat_bi_Atari { | ||
| 293 | unsigned long hw_present; | ||
| 294 | unsigned long mch_cookie; | ||
| 295 | }; | ||
| 296 | |||
| 297 | #ifndef __ASSEMBLY__ | ||
| 298 | |||
| 299 | struct compat_bi_Macintosh | ||
| 300 | { | ||
| 301 | unsigned long videoaddr; | ||
| 302 | unsigned long videorow; | ||
| 303 | unsigned long videodepth; | ||
| 304 | unsigned long dimensions; | ||
| 305 | unsigned long args; | ||
| 306 | unsigned long boottime; | ||
| 307 | unsigned long gmtbias; | ||
| 308 | unsigned long bootver; | ||
| 309 | unsigned long videological; | ||
| 310 | unsigned long sccbase; | ||
| 311 | unsigned long id; | ||
| 312 | unsigned long memsize; | ||
| 313 | unsigned long serialmf; | ||
| 314 | unsigned long serialhsk; | ||
| 315 | unsigned long serialgpi; | ||
| 316 | unsigned long printmf; | ||
| 317 | unsigned long printhsk; | ||
| 318 | unsigned long printgpi; | ||
| 319 | unsigned long cpuid; | ||
| 320 | unsigned long rombase; | ||
| 321 | unsigned long adbdelay; | ||
| 322 | unsigned long timedbra; | ||
| 323 | }; | ||
| 324 | |||
| 325 | #endif | ||
| 326 | |||
| 327 | struct compat_mem_info { | ||
| 328 | unsigned long addr; | ||
| 329 | unsigned long size; | ||
| 330 | }; | ||
| 331 | |||
| 332 | #define COMPAT_NUM_MEMINFO 4 | ||
| 333 | |||
| 334 | #define COMPAT_CPUB_68020 0 | ||
| 335 | #define COMPAT_CPUB_68030 1 | ||
| 336 | #define COMPAT_CPUB_68040 2 | ||
| 337 | #define COMPAT_CPUB_68060 3 | ||
| 338 | #define COMPAT_FPUB_68881 5 | ||
| 339 | #define COMPAT_FPUB_68882 6 | ||
| 340 | #define COMPAT_FPUB_68040 7 | ||
| 341 | #define COMPAT_FPUB_68060 8 | ||
| 342 | |||
| 343 | #define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020) | ||
| 344 | #define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030) | ||
| 345 | #define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040) | ||
| 346 | #define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060) | ||
| 347 | #define COMPAT_CPU_MASK (31) | ||
| 348 | #define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881) | ||
| 349 | #define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882) | ||
| 350 | #define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040) | ||
| 351 | #define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060) | ||
| 352 | #define COMPAT_FPU_MASK (0xfe0) | ||
| 353 | |||
| 354 | #define COMPAT_CL_SIZE (256) | ||
| 355 | |||
| 356 | struct compat_bootinfo { | ||
| 357 | unsigned long machtype; | ||
| 358 | unsigned long cputype; | ||
| 359 | struct compat_mem_info memory[COMPAT_NUM_MEMINFO]; | ||
| 360 | int num_memory; | ||
| 361 | unsigned long ramdisk_size; | ||
| 362 | unsigned long ramdisk_addr; | ||
| 363 | char command_line[COMPAT_CL_SIZE]; | ||
| 364 | union { | ||
| 365 | struct compat_bi_Amiga bi_ami; | ||
| 366 | struct compat_bi_Atari bi_ata; | ||
| 367 | struct compat_bi_Macintosh bi_mac; | ||
| 368 | } bi_un; | ||
| 369 | }; | ||
| 370 | |||
| 371 | #define bi_amiga bi_un.bi_ami | ||
| 372 | #define bi_atari bi_un.bi_ata | ||
| 373 | #define bi_mac bi_un.bi_mac | ||
| 374 | |||
| 375 | #endif /* BOOTINFO_COMPAT_1_0 */ | ||
| 376 | |||
| 377 | |||
| 378 | #endif /* _M68K_BOOTINFO_H */ | ||
diff --git a/arch/m68k/include/asm/bootinfo_no.h b/arch/m68k/include/asm/bootinfo_no.h new file mode 100644 index 000000000000..c12e526f5189 --- /dev/null +++ b/arch/m68k/include/asm/bootinfo_no.h | |||
| @@ -0,0 +1,2 @@ | |||
| 1 | |||
| 2 | /* Nothing for m68knommu */ | ||
diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h new file mode 100644 index 000000000000..bdc1a4ac4fe9 --- /dev/null +++ b/arch/m68k/include/asm/bootstd.h | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* bootstd.h: Bootloader system call interface | ||
| 2 | * | ||
| 3 | * (c) 1999, Rt-Control, Inc. | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef __BOOTSTD_H__ | ||
| 7 | #define __BOOTSTD_H__ | ||
| 8 | |||
| 9 | #define NR_BSC 21 /* last used bootloader system call */ | ||
| 10 | |||
| 11 | #define __BN_reset 0 /* reset and start the bootloader */ | ||
| 12 | #define __BN_test 1 /* tests the system call interface */ | ||
| 13 | #define __BN_exec 2 /* executes a bootloader image */ | ||
| 14 | #define __BN_exit 3 /* terminates a bootloader image */ | ||
| 15 | #define __BN_program 4 /* program FLASH from a chain */ | ||
| 16 | #define __BN_erase 5 /* erase sector(s) of FLASH */ | ||
| 17 | #define __BN_open 6 | ||
| 18 | #define __BN_write 7 | ||
| 19 | #define __BN_read 8 | ||
| 20 | #define __BN_close 9 | ||
| 21 | #define __BN_mmap 10 /* map a file descriptor into memory */ | ||
| 22 | #define __BN_munmap 11 /* remove a file to memory mapping */ | ||
| 23 | #define __BN_gethwaddr 12 /* get the hardware address of my interfaces */ | ||
| 24 | #define __BN_getserialnum 13 /* get the serial number of this board */ | ||
| 25 | #define __BN_getbenv 14 /* get a bootloader envvar */ | ||
| 26 | #define __BN_setbenv 15 /* get a bootloader envvar */ | ||
| 27 | #define __BN_setpmask 16 /* set the protection mask */ | ||
| 28 | #define __BN_readenv 17 /* read environment variables */ | ||
| 29 | #define __BN_flash_chattr_range 18 | ||
| 30 | #define __BN_flash_erase_range 19 | ||
| 31 | #define __BN_flash_write_range 20 | ||
| 32 | |||
| 33 | /* Calling conventions compatible to (uC)linux/68k | ||
| 34 | * We use simmilar macros to call into the bootloader as for uClinux | ||
| 35 | */ | ||
| 36 | |||
| 37 | #define __bsc_return(type, res) \ | ||
| 38 | do { \ | ||
| 39 | if ((unsigned long)(res) >= (unsigned long)(-64)) { \ | ||
| 40 | /* let errno be a function, preserve res in %d0 */ \ | ||
| 41 | int __err = -(res); \ | ||
| 42 | errno = __err; \ | ||
| 43 | res = -1; \ | ||
| 44 | } \ | ||
| 45 | return (type)(res); \ | ||
| 46 | } while (0) | ||
| 47 | |||
| 48 | #define _bsc0(type,name) \ | ||
| 49 | type name(void) \ | ||
| 50 | { \ | ||
| 51 | register long __res __asm__ ("%d0") = __BN_##name; \ | ||
| 52 | __asm__ __volatile__ ("trap #2" \ | ||
| 53 | : "=g" (__res) \ | ||
| 54 | : "0" (__res) \ | ||
| 55 | ); \ | ||
| 56 | __bsc_return(type,__res); \ | ||
| 57 | } | ||
| 58 | |||
| 59 | #define _bsc1(type,name,atype,a) \ | ||
| 60 | type name(atype a) \ | ||
| 61 | { \ | ||
| 62 | register long __res __asm__ ("%d0") = __BN_##name; \ | ||
| 63 | register long __a __asm__ ("%d1") = (long)a; \ | ||
| 64 | __asm__ __volatile__ ("trap #2" \ | ||
| 65 | : "=g" (__res) \ | ||
| 66 | : "0" (__res), "d" (__a) \ | ||
| 67 | ); \ | ||
| 68 | __bsc_return(type,__res); \ | ||
| 69 | } | ||
| 70 | |||
| 71 | #define _bsc2(type,name,atype,a,btype,b) \ | ||
| 72 | type name(atype a, btype b) \ | ||
| 73 | { \ | ||
| 74 | register long __res __asm__ ("%d0") = __BN_##name; \ | ||
| 75 | register long __a __asm__ ("%d1") = (long)a; \ | ||
| 76 | register long __b __asm__ ("%d2") = (long)b; \ | ||
| 77 | __asm__ __volatile__ ("trap #2" \ | ||
| 78 | : "=g" (__res) \ | ||
| 79 | : "0" (__res), "d" (__a), "d" (__b) \ | ||
| 80 | ); \ | ||
| 81 | __bsc_return(type,__res); \ | ||
| 82 | } | ||
| 83 | |||
| 84 | #define _bsc3(type,name,atype,a,btype,b,ctype,c) \ | ||
| 85 | type name(atype a, btype b, ctype c) \ | ||
| 86 | { \ | ||
| 87 | register long __res __asm__ ("%d0") = __BN_##name; \ | ||
| 88 | register long __a __asm__ ("%d1") = (long)a; \ | ||
| 89 | register long __b __asm__ ("%d2") = (long)b; \ | ||
| 90 | register long __c __asm__ ("%d3") = (long)c; \ | ||
| 91 | __asm__ __volatile__ ("trap #2" \ | ||
| 92 | : "=g" (__res) \ | ||
| 93 | : "0" (__res), "d" (__a), "d" (__b), \ | ||
| 94 | "d" (__c) \ | ||
| 95 | ); \ | ||
| 96 | __bsc_return(type,__res); \ | ||
| 97 | } | ||
| 98 | |||
| 99 | #define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ | ||
| 100 | type name(atype a, btype b, ctype c, dtype d) \ | ||
| 101 | { \ | ||
| 102 | register long __res __asm__ ("%d0") = __BN_##name; \ | ||
| 103 | register long __a __asm__ ("%d1") = (long)a; \ | ||
| 104 | register long __b __asm__ ("%d2") = (long)b; \ | ||
| 105 | register long __c __asm__ ("%d3") = (long)c; \ | ||
| 106 | register long __d __asm__ ("%d4") = (long)d; \ | ||
| 107 | __asm__ __volatile__ ("trap #2" \ | ||
| 108 | : "=g" (__res) \ | ||
| 109 | : "0" (__res), "d" (__a), "d" (__b), \ | ||
| 110 | "d" (__c), "d" (__d) \ | ||
| 111 | ); \ | ||
| 112 | __bsc_return(type,__res); \ | ||
| 113 | } | ||
| 114 | |||
| 115 | #define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ | ||
| 116 | type name(atype a, btype b, ctype c, dtype d, etype e) \ | ||
| 117 | { \ | ||
| 118 | register long __res __asm__ ("%d0") = __BN_##name; \ | ||
| 119 | register long __a __asm__ ("%d1") = (long)a; \ | ||
| 120 | register long __b __asm__ ("%d2") = (long)b; \ | ||
| 121 | register long __c __asm__ ("%d3") = (long)c; \ | ||
| 122 | register long __d __asm__ ("%d4") = (long)d; \ | ||
| 123 | register long __e __asm__ ("%d5") = (long)e; \ | ||
| 124 | __asm__ __volatile__ ("trap #2" \ | ||
| 125 | : "=g" (__res) \ | ||
| 126 | : "0" (__res), "d" (__a), "d" (__b), \ | ||
| 127 | "d" (__c), "d" (__d), "d" (__e) \ | ||
| 128 | ); \ | ||
| 129 | __bsc_return(type,__res); \ | ||
| 130 | } | ||
| 131 | |||
| 132 | #endif /* __BOOTSTD_H__ */ | ||
diff --git a/arch/m68k/include/asm/bug.h b/arch/m68k/include/asm/bug.h new file mode 100644 index 000000000000..997e0944ebc1 --- /dev/null +++ b/arch/m68k/include/asm/bug.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "bug_no.h" | ||
| 3 | #else | ||
| 4 | #include "bug_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/bug_mm.h b/arch/m68k/include/asm/bug_mm.h new file mode 100644 index 000000000000..e5b528deb8a8 --- /dev/null +++ b/arch/m68k/include/asm/bug_mm.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #ifndef _M68K_BUG_H | ||
| 2 | #define _M68K_BUG_H | ||
| 3 | |||
| 4 | |||
| 5 | #ifdef CONFIG_BUG | ||
| 6 | #ifdef CONFIG_DEBUG_BUGVERBOSE | ||
| 7 | #ifndef CONFIG_SUN3 | ||
| 8 | #define BUG() do { \ | ||
| 9 | printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ | ||
| 10 | __builtin_trap(); \ | ||
| 11 | } while (0) | ||
| 12 | #else | ||
| 13 | #define BUG() do { \ | ||
| 14 | printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ | ||
| 15 | panic("BUG!"); \ | ||
| 16 | } while (0) | ||
| 17 | #endif | ||
| 18 | #else | ||
| 19 | #define BUG() do { \ | ||
| 20 | __builtin_trap(); \ | ||
| 21 | } while (0) | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #define HAVE_ARCH_BUG | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #include <asm-generic/bug.h> | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/arch/m68k/include/asm/bug_no.h b/arch/m68k/include/asm/bug_no.h new file mode 100644 index 000000000000..70e7dc0af21a --- /dev/null +++ b/arch/m68k/include/asm/bug_no.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef _M68KNOMMU_BUG_H | ||
| 2 | #define _M68KNOMMU_BUG_H | ||
| 3 | #include <asm-generic/bug.h> | ||
| 4 | #endif | ||
diff --git a/arch/m68k/include/asm/bugs.h b/arch/m68k/include/asm/bugs.h new file mode 100644 index 000000000000..01f047d784ec --- /dev/null +++ b/arch/m68k/include/asm/bugs.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "bugs_no.h" | ||
| 3 | #else | ||
| 4 | #include "bugs_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/bugs_mm.h b/arch/m68k/include/asm/bugs_mm.h new file mode 100644 index 000000000000..d01935592410 --- /dev/null +++ b/arch/m68k/include/asm/bugs_mm.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68k/bugs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1994 Linus Torvalds | ||
| 5 | */ | ||
| 6 | |||
| 7 | /* | ||
| 8 | * This is included by init/main.c to check for architecture-dependent bugs. | ||
| 9 | * | ||
| 10 | * Needs: | ||
| 11 | * void check_bugs(void); | ||
| 12 | */ | ||
| 13 | |||
| 14 | extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */ | ||
diff --git a/arch/m68k/include/asm/bugs_no.h b/arch/m68k/include/asm/bugs_no.h new file mode 100644 index 000000000000..5f382dac3a60 --- /dev/null +++ b/arch/m68k/include/asm/bugs_no.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68k/bugs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1994 Linus Torvalds | ||
| 5 | */ | ||
| 6 | |||
| 7 | /* | ||
| 8 | * This is included by init/main.c to check for architecture-dependent bugs. | ||
| 9 | * | ||
| 10 | * Needs: | ||
| 11 | * void check_bugs(void); | ||
| 12 | */ | ||
| 13 | |||
| 14 | static void check_bugs(void) | ||
| 15 | { | ||
| 16 | } | ||
diff --git a/arch/m68k/include/asm/bvme6000hw.h b/arch/m68k/include/asm/bvme6000hw.h new file mode 100644 index 000000000000..f40d2f8510ee --- /dev/null +++ b/arch/m68k/include/asm/bvme6000hw.h | |||
| @@ -0,0 +1,150 @@ | |||
| 1 | #ifndef _M68K_BVME6000HW_H_ | ||
| 2 | #define _M68K_BVME6000HW_H_ | ||
| 3 | |||
| 4 | #include <asm/irq.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * PIT structure | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define BVME_PIT_BASE 0xffa00000 | ||
| 11 | |||
| 12 | typedef struct { | ||
| 13 | unsigned char | ||
| 14 | pad_a[3], pgcr, | ||
| 15 | pad_b[3], psrr, | ||
| 16 | pad_c[3], paddr, | ||
| 17 | pad_d[3], pbddr, | ||
| 18 | pad_e[3], pcddr, | ||
| 19 | pad_f[3], pivr, | ||
| 20 | pad_g[3], pacr, | ||
| 21 | pad_h[3], pbcr, | ||
| 22 | pad_i[3], padr, | ||
| 23 | pad_j[3], pbdr, | ||
| 24 | pad_k[3], paar, | ||
| 25 | pad_l[3], pbar, | ||
| 26 | pad_m[3], pcdr, | ||
| 27 | pad_n[3], psr, | ||
| 28 | pad_o[3], res1, | ||
| 29 | pad_p[3], res2, | ||
| 30 | pad_q[3], tcr, | ||
| 31 | pad_r[3], tivr, | ||
| 32 | pad_s[3], res3, | ||
| 33 | pad_t[3], cprh, | ||
| 34 | pad_u[3], cprm, | ||
| 35 | pad_v[3], cprl, | ||
| 36 | pad_w[3], res4, | ||
| 37 | pad_x[3], crh, | ||
| 38 | pad_y[3], crm, | ||
| 39 | pad_z[3], crl, | ||
| 40 | pad_A[3], tsr, | ||
| 41 | pad_B[3], res5; | ||
| 42 | } PitRegs_t, *PitRegsPtr; | ||
| 43 | |||
| 44 | #define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE))) | ||
| 45 | |||
| 46 | #define BVME_RTC_BASE 0xff900000 | ||
| 47 | |||
| 48 | typedef struct { | ||
| 49 | unsigned char | ||
| 50 | pad_a[3], msr, | ||
| 51 | pad_b[3], t0cr_rtmr, | ||
| 52 | pad_c[3], t1cr_omr, | ||
| 53 | pad_d[3], pfr_icr0, | ||
| 54 | pad_e[3], irr_icr1, | ||
| 55 | pad_f[3], bcd_tenms, | ||
| 56 | pad_g[3], bcd_sec, | ||
| 57 | pad_h[3], bcd_min, | ||
| 58 | pad_i[3], bcd_hr, | ||
| 59 | pad_j[3], bcd_dom, | ||
| 60 | pad_k[3], bcd_mth, | ||
| 61 | pad_l[3], bcd_year, | ||
| 62 | pad_m[3], bcd_ujcc, | ||
| 63 | pad_n[3], bcd_hjcc, | ||
| 64 | pad_o[3], bcd_dow, | ||
| 65 | pad_p[3], t0lsb, | ||
| 66 | pad_q[3], t0msb, | ||
| 67 | pad_r[3], t1lsb, | ||
| 68 | pad_s[3], t1msb, | ||
| 69 | pad_t[3], cmp_sec, | ||
| 70 | pad_u[3], cmp_min, | ||
| 71 | pad_v[3], cmp_hr, | ||
| 72 | pad_w[3], cmp_dom, | ||
| 73 | pad_x[3], cmp_mth, | ||
| 74 | pad_y[3], cmp_dow, | ||
| 75 | pad_z[3], sav_sec, | ||
| 76 | pad_A[3], sav_min, | ||
| 77 | pad_B[3], sav_hr, | ||
| 78 | pad_C[3], sav_dom, | ||
| 79 | pad_D[3], sav_mth, | ||
| 80 | pad_E[3], ram, | ||
| 81 | pad_F[3], test; | ||
| 82 | } RtcRegs_t, *RtcPtr_t; | ||
| 83 | |||
| 84 | |||
| 85 | #define BVME_I596_BASE 0xff100000 | ||
| 86 | |||
| 87 | #define BVME_ETHIRQ_REG 0xff20000b | ||
| 88 | |||
| 89 | #define BVME_LOCAL_IRQ_STAT 0xff20000f | ||
| 90 | |||
| 91 | #define BVME_ETHERR 0x02 | ||
| 92 | #define BVME_ABORT_STATUS 0x08 | ||
| 93 | |||
| 94 | #define BVME_NCR53C710_BASE 0xff000000 | ||
| 95 | |||
| 96 | #define BVME_SCC_A_ADDR 0xffb0000b | ||
| 97 | #define BVME_SCC_B_ADDR 0xffb00003 | ||
| 98 | #define BVME_SCC_RTxC 7372800 | ||
| 99 | |||
| 100 | #define BVME_CONFIG_REG 0xff500003 | ||
| 101 | |||
| 102 | #define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG | ||
| 103 | |||
| 104 | #define BVME_CONFIG_SW1 0x08 | ||
| 105 | #define BVME_CONFIG_SW2 0x04 | ||
| 106 | #define BVME_CONFIG_SW3 0x02 | ||
| 107 | #define BVME_CONFIG_SW4 0x01 | ||
| 108 | |||
| 109 | |||
| 110 | #define BVME_IRQ_TYPE_PRIO 0 | ||
| 111 | |||
| 112 | #define BVME_IRQ_PRN (IRQ_USER+20) | ||
| 113 | #define BVME_IRQ_TIMER (IRQ_USER+25) | ||
| 114 | #define BVME_IRQ_I596 IRQ_AUTO_2 | ||
| 115 | #define BVME_IRQ_SCSI IRQ_AUTO_3 | ||
| 116 | #define BVME_IRQ_RTC IRQ_AUTO_6 | ||
| 117 | #define BVME_IRQ_ABORT IRQ_AUTO_7 | ||
| 118 | |||
| 119 | /* SCC interrupts */ | ||
| 120 | #define BVME_IRQ_SCC_BASE IRQ_USER | ||
| 121 | #define BVME_IRQ_SCCB_TX IRQ_USER | ||
| 122 | #define BVME_IRQ_SCCB_STAT (IRQ_USER+2) | ||
| 123 | #define BVME_IRQ_SCCB_RX (IRQ_USER+4) | ||
| 124 | #define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6) | ||
| 125 | #define BVME_IRQ_SCCA_TX (IRQ_USER+8) | ||
| 126 | #define BVME_IRQ_SCCA_STAT (IRQ_USER+10) | ||
| 127 | #define BVME_IRQ_SCCA_RX (IRQ_USER+12) | ||
| 128 | #define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14) | ||
| 129 | |||
| 130 | /* Address control registers */ | ||
| 131 | |||
| 132 | #define BVME_ACR_A32VBA 0xff400003 | ||
| 133 | #define BVME_ACR_A32MSK 0xff410003 | ||
| 134 | #define BVME_ACR_A24VBA 0xff420003 | ||
| 135 | #define BVME_ACR_A24MSK 0xff430003 | ||
| 136 | #define BVME_ACR_A16VBA 0xff440003 | ||
| 137 | #define BVME_ACR_A32LBA 0xff450003 | ||
| 138 | #define BVME_ACR_A24LBA 0xff460003 | ||
| 139 | #define BVME_ACR_ADDRCTL 0xff470003 | ||
| 140 | |||
| 141 | #define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA | ||
| 142 | #define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK | ||
| 143 | #define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA | ||
| 144 | #define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK | ||
| 145 | #define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA | ||
| 146 | #define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA | ||
| 147 | #define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA | ||
| 148 | #define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL | ||
| 149 | |||
| 150 | #endif | ||
diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h new file mode 100644 index 000000000000..f20502a001f5 --- /dev/null +++ b/arch/m68k/include/asm/byteorder.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "byteorder_no.h" | ||
| 3 | #else | ||
| 4 | #include "byteorder_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/byteorder_mm.h b/arch/m68k/include/asm/byteorder_mm.h new file mode 100644 index 000000000000..31b260a88803 --- /dev/null +++ b/arch/m68k/include/asm/byteorder_mm.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68K_BYTEORDER_H | ||
| 2 | #define _M68K_BYTEORDER_H | ||
| 3 | |||
| 4 | #include <linux/byteorder/big_endian.h> | ||
| 5 | |||
| 6 | #endif /* _M68K_BYTEORDER_H */ | ||
diff --git a/arch/m68k/include/asm/byteorder_no.h b/arch/m68k/include/asm/byteorder_no.h new file mode 100644 index 000000000000..9c6c76a15041 --- /dev/null +++ b/arch/m68k/include/asm/byteorder_no.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68KNOMMU_BYTEORDER_H | ||
| 2 | #define _M68KNOMMU_BYTEORDER_H | ||
| 3 | |||
| 4 | #include <linux/byteorder/big_endian.h> | ||
| 5 | |||
| 6 | #endif /* _M68KNOMMU_BYTEORDER_H */ | ||
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h new file mode 100644 index 000000000000..599c29bc8f40 --- /dev/null +++ b/arch/m68k/include/asm/cache.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "cache_no.h" | ||
| 3 | #else | ||
| 4 | #include "cache_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/cache_mm.h b/arch/m68k/include/asm/cache_mm.h new file mode 100644 index 000000000000..fed3fd30de7e --- /dev/null +++ b/arch/m68k/include/asm/cache_mm.h | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68k/cache.h | ||
| 3 | */ | ||
| 4 | #ifndef __ARCH_M68K_CACHE_H | ||
| 5 | #define __ARCH_M68K_CACHE_H | ||
| 6 | |||
| 7 | /* bytes per L1 cache line */ | ||
| 8 | #define L1_CACHE_SHIFT 4 | ||
| 9 | #define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT) | ||
| 10 | |||
| 11 | #endif | ||
diff --git a/arch/m68k/include/asm/cache_no.h b/arch/m68k/include/asm/cache_no.h new file mode 100644 index 000000000000..24e9eace5f8c --- /dev/null +++ b/arch/m68k/include/asm/cache_no.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef __ARCH_M68KNOMMU_CACHE_H | ||
| 2 | #define __ARCH_M68KNOMMU_CACHE_H | ||
| 3 | |||
| 4 | /* bytes per L1 cache line */ | ||
| 5 | #define L1_CACHE_BYTES 16 /* this need to be at least 1 */ | ||
| 6 | |||
| 7 | /* m68k-elf-gcc 2.95.2 doesn't like these */ | ||
| 8 | |||
| 9 | #define __cacheline_aligned | ||
| 10 | #define ____cacheline_aligned | ||
| 11 | |||
| 12 | #endif | ||
diff --git a/arch/m68k/include/asm/cachectl.h b/arch/m68k/include/asm/cachectl.h new file mode 100644 index 000000000000..525978e959e3 --- /dev/null +++ b/arch/m68k/include/asm/cachectl.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | #ifndef _M68K_CACHECTL_H | ||
| 2 | #define _M68K_CACHECTL_H | ||
| 3 | |||
| 4 | /* Definitions for the cacheflush system call. */ | ||
| 5 | |||
| 6 | #define FLUSH_SCOPE_LINE 1 /* Flush a cache line */ | ||
| 7 | #define FLUSH_SCOPE_PAGE 2 /* Flush a page */ | ||
| 8 | #define FLUSH_SCOPE_ALL 3 /* Flush the whole cache -- superuser only */ | ||
| 9 | |||
| 10 | #define FLUSH_CACHE_DATA 1 /* Writeback and flush data cache */ | ||
| 11 | #define FLUSH_CACHE_INSN 2 /* Flush instruction cache */ | ||
| 12 | #define FLUSH_CACHE_BOTH 3 /* Flush both caches */ | ||
| 13 | |||
| 14 | #endif /* _M68K_CACHECTL_H */ | ||
diff --git a/arch/m68k/include/asm/cacheflush.h b/arch/m68k/include/asm/cacheflush.h new file mode 100644 index 000000000000..a70d7319630a --- /dev/null +++ b/arch/m68k/include/asm/cacheflush.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "cacheflush_no.h" | ||
| 3 | #else | ||
| 4 | #include "cacheflush_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h new file mode 100644 index 000000000000..16bf375fdbe1 --- /dev/null +++ b/arch/m68k/include/asm/cacheflush_mm.h | |||
| @@ -0,0 +1,156 @@ | |||
| 1 | #ifndef _M68K_CACHEFLUSH_H | ||
| 2 | #define _M68K_CACHEFLUSH_H | ||
| 3 | |||
| 4 | #include <linux/mm.h> | ||
| 5 | |||
| 6 | /* cache code */ | ||
| 7 | #define FLUSH_I_AND_D (0x00000808) | ||
| 8 | #define FLUSH_I (0x00000008) | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Cache handling functions | ||
| 12 | */ | ||
| 13 | |||
| 14 | static inline void flush_icache(void) | ||
| 15 | { | ||
| 16 | if (CPU_IS_040_OR_060) | ||
| 17 | asm volatile ( "nop\n" | ||
| 18 | " .chip 68040\n" | ||
| 19 | " cpusha %bc\n" | ||
| 20 | " .chip 68k"); | ||
| 21 | else { | ||
| 22 | unsigned long tmp; | ||
| 23 | asm volatile ( "movec %%cacr,%0\n" | ||
| 24 | " or.w %1,%0\n" | ||
| 25 | " movec %0,%%cacr" | ||
| 26 | : "=&d" (tmp) | ||
| 27 | : "id" (FLUSH_I)); | ||
| 28 | } | ||
| 29 | } | ||
| 30 | |||
| 31 | /* | ||
| 32 | * invalidate the cache for the specified memory range. | ||
| 33 | * It starts at the physical address specified for | ||
| 34 | * the given number of bytes. | ||
| 35 | */ | ||
| 36 | extern void cache_clear(unsigned long paddr, int len); | ||
| 37 | /* | ||
| 38 | * push any dirty cache in the specified memory range. | ||
| 39 | * It starts at the physical address specified for | ||
| 40 | * the given number of bytes. | ||
| 41 | */ | ||
| 42 | extern void cache_push(unsigned long paddr, int len); | ||
| 43 | |||
| 44 | /* | ||
| 45 | * push and invalidate pages in the specified user virtual | ||
| 46 | * memory range. | ||
| 47 | */ | ||
| 48 | extern void cache_push_v(unsigned long vaddr, int len); | ||
| 49 | |||
| 50 | /* This is needed whenever the virtual mapping of the current | ||
| 51 | process changes. */ | ||
| 52 | #define __flush_cache_all() \ | ||
| 53 | ({ \ | ||
| 54 | if (CPU_IS_040_OR_060) \ | ||
| 55 | __asm__ __volatile__("nop\n\t" \ | ||
| 56 | ".chip 68040\n\t" \ | ||
| 57 | "cpusha %dc\n\t" \ | ||
| 58 | ".chip 68k"); \ | ||
| 59 | else { \ | ||
| 60 | unsigned long _tmp; \ | ||
| 61 | __asm__ __volatile__("movec %%cacr,%0\n\t" \ | ||
| 62 | "orw %1,%0\n\t" \ | ||
| 63 | "movec %0,%%cacr" \ | ||
| 64 | : "=&d" (_tmp) \ | ||
| 65 | : "di" (FLUSH_I_AND_D)); \ | ||
| 66 | } \ | ||
| 67 | }) | ||
| 68 | |||
| 69 | #define __flush_cache_030() \ | ||
| 70 | ({ \ | ||
| 71 | if (CPU_IS_020_OR_030) { \ | ||
| 72 | unsigned long _tmp; \ | ||
| 73 | __asm__ __volatile__("movec %%cacr,%0\n\t" \ | ||
| 74 | "orw %1,%0\n\t" \ | ||
| 75 | "movec %0,%%cacr" \ | ||
| 76 | : "=&d" (_tmp) \ | ||
| 77 | : "di" (FLUSH_I_AND_D)); \ | ||
| 78 | } \ | ||
| 79 | }) | ||
| 80 | |||
| 81 | #define flush_cache_all() __flush_cache_all() | ||
| 82 | |||
| 83 | #define flush_cache_vmap(start, end) flush_cache_all() | ||
| 84 | #define flush_cache_vunmap(start, end) flush_cache_all() | ||
| 85 | |||
| 86 | static inline void flush_cache_mm(struct mm_struct *mm) | ||
| 87 | { | ||
| 88 | if (mm == current->mm) | ||
| 89 | __flush_cache_030(); | ||
| 90 | } | ||
| 91 | |||
| 92 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) | ||
| 93 | |||
| 94 | /* flush_cache_range/flush_cache_page must be macros to avoid | ||
| 95 | a dependency on linux/mm.h, which includes this file... */ | ||
| 96 | static inline void flush_cache_range(struct vm_area_struct *vma, | ||
| 97 | unsigned long start, | ||
| 98 | unsigned long end) | ||
| 99 | { | ||
| 100 | if (vma->vm_mm == current->mm) | ||
| 101 | __flush_cache_030(); | ||
| 102 | } | ||
| 103 | |||
| 104 | static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn) | ||
| 105 | { | ||
| 106 | if (vma->vm_mm == current->mm) | ||
| 107 | __flush_cache_030(); | ||
| 108 | } | ||
| 109 | |||
| 110 | |||
| 111 | /* Push the page at kernel virtual address and clear the icache */ | ||
| 112 | /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ | ||
| 113 | static inline void __flush_page_to_ram(void *vaddr) | ||
| 114 | { | ||
| 115 | if (CPU_IS_040_OR_060) { | ||
| 116 | __asm__ __volatile__("nop\n\t" | ||
| 117 | ".chip 68040\n\t" | ||
| 118 | "cpushp %%bc,(%0)\n\t" | ||
| 119 | ".chip 68k" | ||
| 120 | : : "a" (__pa(vaddr))); | ||
| 121 | } else { | ||
| 122 | unsigned long _tmp; | ||
| 123 | __asm__ __volatile__("movec %%cacr,%0\n\t" | ||
| 124 | "orw %1,%0\n\t" | ||
| 125 | "movec %0,%%cacr" | ||
| 126 | : "=&d" (_tmp) | ||
| 127 | : "di" (FLUSH_I)); | ||
| 128 | } | ||
| 129 | } | ||
| 130 | |||
| 131 | #define flush_dcache_page(page) __flush_page_to_ram(page_address(page)) | ||
| 132 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
| 133 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
| 134 | #define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page)) | ||
| 135 | |||
| 136 | extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, | ||
| 137 | unsigned long addr, int len); | ||
| 138 | extern void flush_icache_range(unsigned long address, unsigned long endaddr); | ||
| 139 | |||
| 140 | static inline void copy_to_user_page(struct vm_area_struct *vma, | ||
| 141 | struct page *page, unsigned long vaddr, | ||
| 142 | void *dst, void *src, int len) | ||
| 143 | { | ||
| 144 | flush_cache_page(vma, vaddr, page_to_pfn(page)); | ||
| 145 | memcpy(dst, src, len); | ||
| 146 | flush_icache_user_range(vma, page, vaddr, len); | ||
| 147 | } | ||
| 148 | static inline void copy_from_user_page(struct vm_area_struct *vma, | ||
| 149 | struct page *page, unsigned long vaddr, | ||
| 150 | void *dst, void *src, int len) | ||
| 151 | { | ||
| 152 | flush_cache_page(vma, vaddr, page_to_pfn(page)); | ||
| 153 | memcpy(dst, src, len); | ||
| 154 | } | ||
| 155 | |||
| 156 | #endif /* _M68K_CACHEFLUSH_H */ | ||
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h new file mode 100644 index 000000000000..87e5dc0413b4 --- /dev/null +++ b/arch/m68k/include/asm/cacheflush_no.h | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | #ifndef _M68KNOMMU_CACHEFLUSH_H | ||
| 2 | #define _M68KNOMMU_CACHEFLUSH_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com> | ||
| 6 | */ | ||
| 7 | #include <linux/mm.h> | ||
| 8 | |||
| 9 | #define flush_cache_all() __flush_cache_all() | ||
| 10 | #define flush_cache_mm(mm) do { } while (0) | ||
| 11 | #define flush_cache_dup_mm(mm) do { } while (0) | ||
| 12 | #define flush_cache_range(vma, start, end) __flush_cache_all() | ||
| 13 | #define flush_cache_page(vma, vmaddr) do { } while (0) | ||
| 14 | #define flush_dcache_range(start,len) __flush_cache_all() | ||
| 15 | #define flush_dcache_page(page) do { } while (0) | ||
| 16 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
| 17 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
| 18 | #define flush_icache_range(start,len) __flush_cache_all() | ||
| 19 | #define flush_icache_page(vma,pg) do { } while (0) | ||
| 20 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) | ||
| 21 | #define flush_cache_vmap(start, end) do { } while (0) | ||
| 22 | #define flush_cache_vunmap(start, end) do { } while (0) | ||
| 23 | |||
| 24 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 25 | memcpy(dst, src, len) | ||
| 26 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | ||
| 27 | memcpy(dst, src, len) | ||
| 28 | |||
| 29 | static inline void __flush_cache_all(void) | ||
| 30 | { | ||
| 31 | #ifdef CONFIG_M5407 | ||
| 32 | /* | ||
| 33 | * Use cpushl to push and invalidate all cache lines. | ||
| 34 | * Gas doesn't seem to know how to generate the ColdFire | ||
| 35 | * cpushl instruction... Oh well, bit stuff it for now. | ||
| 36 | */ | ||
| 37 | __asm__ __volatile__ ( | ||
| 38 | "nop\n\t" | ||
| 39 | "clrl %%d0\n\t" | ||
| 40 | "1:\n\t" | ||
| 41 | "movel %%d0,%%a0\n\t" | ||
| 42 | "2:\n\t" | ||
| 43 | ".word 0xf468\n\t" | ||
| 44 | "addl #0x10,%%a0\n\t" | ||
| 45 | "cmpl #0x00000800,%%a0\n\t" | ||
| 46 | "blt 2b\n\t" | ||
| 47 | "addql #1,%%d0\n\t" | ||
| 48 | "cmpil #4,%%d0\n\t" | ||
| 49 | "bne 1b\n\t" | ||
| 50 | "movel #0xb6088500,%%d0\n\t" | ||
| 51 | "movec %%d0,%%CACR\n\t" | ||
| 52 | : : : "d0", "a0" ); | ||
| 53 | #endif /* CONFIG_M5407 */ | ||
| 54 | #if defined(CONFIG_M527x) || defined(CONFIG_M528x) | ||
| 55 | __asm__ __volatile__ ( | ||
| 56 | "movel #0x81000200, %%d0\n\t" | ||
| 57 | "movec %%d0, %%CACR\n\t" | ||
| 58 | "nop\n\t" | ||
| 59 | : : : "d0" ); | ||
| 60 | #endif /* CONFIG_M527x || CONFIG_M528x */ | ||
| 61 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) | ||
| 62 | __asm__ __volatile__ ( | ||
| 63 | "movel #0x81000100, %%d0\n\t" | ||
| 64 | "movec %%d0, %%CACR\n\t" | ||
| 65 | "nop\n\t" | ||
| 66 | : : : "d0" ); | ||
| 67 | #endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ | ||
| 68 | #ifdef CONFIG_M5249 | ||
| 69 | __asm__ __volatile__ ( | ||
| 70 | "movel #0xa1000200, %%d0\n\t" | ||
| 71 | "movec %%d0, %%CACR\n\t" | ||
| 72 | "nop\n\t" | ||
| 73 | : : : "d0" ); | ||
| 74 | #endif /* CONFIG_M5249 */ | ||
| 75 | #ifdef CONFIG_M532x | ||
| 76 | __asm__ __volatile__ ( | ||
| 77 | "movel #0x81000200, %%d0\n\t" | ||
| 78 | "movec %%d0, %%CACR\n\t" | ||
| 79 | "nop\n\t" | ||
| 80 | : : : "d0" ); | ||
| 81 | #endif /* CONFIG_M532x */ | ||
| 82 | } | ||
| 83 | |||
| 84 | #endif /* _M68KNOMMU_CACHEFLUSH_H */ | ||
diff --git a/arch/m68k/include/asm/checksum.h b/arch/m68k/include/asm/checksum.h new file mode 100644 index 000000000000..1cf544767453 --- /dev/null +++ b/arch/m68k/include/asm/checksum.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "checksum_no.h" | ||
| 3 | #else | ||
| 4 | #include "checksum_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/checksum_mm.h b/arch/m68k/include/asm/checksum_mm.h new file mode 100644 index 000000000000..494f9aec37ea --- /dev/null +++ b/arch/m68k/include/asm/checksum_mm.h | |||
| @@ -0,0 +1,148 @@ | |||
| 1 | #ifndef _M68K_CHECKSUM_H | ||
| 2 | #define _M68K_CHECKSUM_H | ||
| 3 | |||
| 4 | #include <linux/in6.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * computes the checksum of a memory block at buff, length len, | ||
| 8 | * and adds in "sum" (32-bit) | ||
| 9 | * | ||
| 10 | * returns a 32-bit number suitable for feeding into itself | ||
| 11 | * or csum_tcpudp_magic | ||
| 12 | * | ||
| 13 | * this function must be called with even lengths, except | ||
| 14 | * for the last fragment, which may be odd | ||
| 15 | * | ||
| 16 | * it's best to have buff aligned on a 32-bit boundary | ||
| 17 | */ | ||
| 18 | __wsum csum_partial(const void *buff, int len, __wsum sum); | ||
| 19 | |||
| 20 | /* | ||
| 21 | * the same as csum_partial, but copies from src while it | ||
| 22 | * checksums | ||
| 23 | * | ||
| 24 | * here even more important to align src and dst on a 32-bit (or even | ||
| 25 | * better 64-bit) boundary | ||
| 26 | */ | ||
| 27 | |||
| 28 | extern __wsum csum_partial_copy_from_user(const void __user *src, | ||
| 29 | void *dst, | ||
| 30 | int len, __wsum sum, | ||
| 31 | int *csum_err); | ||
| 32 | |||
| 33 | extern __wsum csum_partial_copy_nocheck(const void *src, | ||
| 34 | void *dst, int len, | ||
| 35 | __wsum sum); | ||
| 36 | |||
| 37 | /* | ||
| 38 | * This is a version of ip_compute_csum() optimized for IP headers, | ||
| 39 | * which always checksum on 4 octet boundaries. | ||
| 40 | * | ||
| 41 | */ | ||
| 42 | static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) | ||
| 43 | { | ||
| 44 | unsigned int sum = 0; | ||
| 45 | unsigned long tmp; | ||
| 46 | |||
| 47 | __asm__ ("subqw #1,%2\n" | ||
| 48 | "1:\t" | ||
| 49 | "movel %1@+,%3\n\t" | ||
| 50 | "addxl %3,%0\n\t" | ||
| 51 | "dbra %2,1b\n\t" | ||
| 52 | "movel %0,%3\n\t" | ||
| 53 | "swap %3\n\t" | ||
| 54 | "addxw %3,%0\n\t" | ||
| 55 | "clrw %3\n\t" | ||
| 56 | "addxw %3,%0\n\t" | ||
| 57 | : "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp) | ||
| 58 | : "0" (sum), "1" (iph), "2" (ihl) | ||
| 59 | : "memory"); | ||
| 60 | return (__force __sum16)~sum; | ||
| 61 | } | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Fold a partial checksum | ||
| 65 | */ | ||
| 66 | |||
| 67 | static inline __sum16 csum_fold(__wsum sum) | ||
| 68 | { | ||
| 69 | unsigned int tmp = (__force u32)sum; | ||
| 70 | __asm__("swap %1\n\t" | ||
| 71 | "addw %1, %0\n\t" | ||
| 72 | "clrw %1\n\t" | ||
| 73 | "addxw %1, %0" | ||
| 74 | : "=&d" (sum), "=&d" (tmp) | ||
| 75 | : "0" (sum), "1" (tmp)); | ||
| 76 | return (__force __sum16)~sum; | ||
| 77 | } | ||
| 78 | |||
| 79 | |||
| 80 | static inline __wsum | ||
| 81 | csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, | ||
| 82 | unsigned short proto, __wsum sum) | ||
| 83 | { | ||
| 84 | __asm__ ("addl %2,%0\n\t" | ||
| 85 | "addxl %3,%0\n\t" | ||
| 86 | "addxl %4,%0\n\t" | ||
| 87 | "clrl %1\n\t" | ||
| 88 | "addxl %1,%0" | ||
| 89 | : "=&d" (sum), "=d" (saddr) | ||
| 90 | : "g" (daddr), "1" (saddr), "d" (len + proto), | ||
| 91 | "0" (sum)); | ||
| 92 | return sum; | ||
| 93 | } | ||
| 94 | |||
| 95 | |||
| 96 | /* | ||
| 97 | * computes the checksum of the TCP/UDP pseudo-header | ||
| 98 | * returns a 16-bit checksum, already complemented | ||
| 99 | */ | ||
| 100 | static inline __sum16 | ||
| 101 | csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, | ||
| 102 | unsigned short proto, __wsum sum) | ||
| 103 | { | ||
| 104 | return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); | ||
| 105 | } | ||
| 106 | |||
| 107 | /* | ||
| 108 | * this routine is used for miscellaneous IP-like checksums, mainly | ||
| 109 | * in icmp.c | ||
| 110 | */ | ||
| 111 | |||
| 112 | static inline __sum16 ip_compute_csum(const void *buff, int len) | ||
| 113 | { | ||
| 114 | return csum_fold (csum_partial(buff, len, 0)); | ||
| 115 | } | ||
| 116 | |||
| 117 | #define _HAVE_ARCH_IPV6_CSUM | ||
| 118 | static __inline__ __sum16 | ||
| 119 | csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, | ||
| 120 | __u32 len, unsigned short proto, __wsum sum) | ||
| 121 | { | ||
| 122 | register unsigned long tmp; | ||
| 123 | __asm__("addl %2@,%0\n\t" | ||
| 124 | "movel %2@(4),%1\n\t" | ||
| 125 | "addxl %1,%0\n\t" | ||
| 126 | "movel %2@(8),%1\n\t" | ||
| 127 | "addxl %1,%0\n\t" | ||
| 128 | "movel %2@(12),%1\n\t" | ||
| 129 | "addxl %1,%0\n\t" | ||
| 130 | "movel %3@,%1\n\t" | ||
| 131 | "addxl %1,%0\n\t" | ||
| 132 | "movel %3@(4),%1\n\t" | ||
| 133 | "addxl %1,%0\n\t" | ||
| 134 | "movel %3@(8),%1\n\t" | ||
| 135 | "addxl %1,%0\n\t" | ||
| 136 | "movel %3@(12),%1\n\t" | ||
| 137 | "addxl %1,%0\n\t" | ||
| 138 | "addxl %4,%0\n\t" | ||
| 139 | "clrl %1\n\t" | ||
| 140 | "addxl %1,%0" | ||
| 141 | : "=&d" (sum), "=&d" (tmp) | ||
| 142 | : "a" (saddr), "a" (daddr), "d" (len + proto), | ||
| 143 | "0" (sum)); | ||
| 144 | |||
| 145 | return csum_fold(sum); | ||
| 146 | } | ||
| 147 | |||
| 148 | #endif /* _M68K_CHECKSUM_H */ | ||
diff --git a/arch/m68k/include/asm/checksum_no.h b/arch/m68k/include/asm/checksum_no.h new file mode 100644 index 000000000000..81883482ffb1 --- /dev/null +++ b/arch/m68k/include/asm/checksum_no.h | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | #ifndef _M68K_CHECKSUM_H | ||
| 2 | #define _M68K_CHECKSUM_H | ||
| 3 | |||
| 4 | #include <linux/in6.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * computes the checksum of a memory block at buff, length len, | ||
| 8 | * and adds in "sum" (32-bit) | ||
| 9 | * | ||
| 10 | * returns a 32-bit number suitable for feeding into itself | ||
| 11 | * or csum_tcpudp_magic | ||
| 12 | * | ||
| 13 | * this function must be called with even lengths, except | ||
| 14 | * for the last fragment, which may be odd | ||
| 15 | * | ||
| 16 | * it's best to have buff aligned on a 32-bit boundary | ||
| 17 | */ | ||
| 18 | __wsum csum_partial(const void *buff, int len, __wsum sum); | ||
| 19 | |||
| 20 | /* | ||
| 21 | * the same as csum_partial, but copies from src while it | ||
| 22 | * checksums | ||
| 23 | * | ||
| 24 | * here even more important to align src and dst on a 32-bit (or even | ||
| 25 | * better 64-bit) boundary | ||
| 26 | */ | ||
| 27 | |||
| 28 | __wsum csum_partial_copy_nocheck(const void *src, void *dst, | ||
| 29 | int len, __wsum sum); | ||
| 30 | |||
| 31 | |||
| 32 | /* | ||
| 33 | * the same as csum_partial_copy, but copies from user space. | ||
| 34 | * | ||
| 35 | * here even more important to align src and dst on a 32-bit (or even | ||
| 36 | * better 64-bit) boundary | ||
| 37 | */ | ||
| 38 | |||
| 39 | extern __wsum csum_partial_copy_from_user(const void __user *src, | ||
| 40 | void *dst, int len, __wsum sum, int *csum_err); | ||
| 41 | |||
| 42 | __sum16 ip_fast_csum(const void *iph, unsigned int ihl); | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Fold a partial checksum | ||
| 46 | */ | ||
| 47 | |||
| 48 | static inline __sum16 csum_fold(__wsum sum) | ||
| 49 | { | ||
| 50 | unsigned int tmp = (__force u32)sum; | ||
| 51 | #ifdef CONFIG_COLDFIRE | ||
| 52 | tmp = (tmp & 0xffff) + (tmp >> 16); | ||
| 53 | tmp = (tmp & 0xffff) + (tmp >> 16); | ||
| 54 | return (__force __sum16)~tmp; | ||
| 55 | #else | ||
| 56 | __asm__("swap %1\n\t" | ||
| 57 | "addw %1, %0\n\t" | ||
| 58 | "clrw %1\n\t" | ||
| 59 | "addxw %1, %0" | ||
| 60 | : "=&d" (sum), "=&d" (tmp) | ||
| 61 | : "0" (sum), "1" (sum)); | ||
| 62 | return (__force __sum16)~sum; | ||
| 63 | #endif | ||
| 64 | } | ||
| 65 | |||
| 66 | |||
| 67 | /* | ||
| 68 | * computes the checksum of the TCP/UDP pseudo-header | ||
| 69 | * returns a 16-bit checksum, already complemented | ||
| 70 | */ | ||
| 71 | |||
| 72 | static inline __wsum | ||
| 73 | csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, | ||
| 74 | unsigned short proto, __wsum sum) | ||
| 75 | { | ||
| 76 | __asm__ ("addl %1,%0\n\t" | ||
| 77 | "addxl %4,%0\n\t" | ||
| 78 | "addxl %5,%0\n\t" | ||
| 79 | "clrl %1\n\t" | ||
| 80 | "addxl %1,%0" | ||
| 81 | : "=&d" (sum), "=&d" (saddr) | ||
| 82 | : "0" (daddr), "1" (saddr), "d" (len + proto), | ||
| 83 | "d"(sum)); | ||
| 84 | return sum; | ||
| 85 | } | ||
| 86 | |||
| 87 | static inline __sum16 | ||
| 88 | csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, | ||
| 89 | unsigned short proto, __wsum sum) | ||
| 90 | { | ||
| 91 | return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); | ||
| 92 | } | ||
| 93 | |||
| 94 | /* | ||
| 95 | * this routine is used for miscellaneous IP-like checksums, mainly | ||
| 96 | * in icmp.c | ||
| 97 | */ | ||
| 98 | |||
| 99 | extern __sum16 ip_compute_csum(const void *buff, int len); | ||
| 100 | |||
| 101 | #define _HAVE_ARCH_IPV6_CSUM | ||
| 102 | static __inline__ __sum16 | ||
| 103 | csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, | ||
| 104 | __u32 len, unsigned short proto, __wsum sum) | ||
| 105 | { | ||
| 106 | register unsigned long tmp; | ||
| 107 | __asm__("addl %2@,%0\n\t" | ||
| 108 | "movel %2@(4),%1\n\t" | ||
| 109 | "addxl %1,%0\n\t" | ||
| 110 | "movel %2@(8),%1\n\t" | ||
| 111 | "addxl %1,%0\n\t" | ||
| 112 | "movel %2@(12),%1\n\t" | ||
| 113 | "addxl %1,%0\n\t" | ||
| 114 | "movel %3@,%1\n\t" | ||
| 115 | "addxl %1,%0\n\t" | ||
| 116 | "movel %3@(4),%1\n\t" | ||
| 117 | "addxl %1,%0\n\t" | ||
| 118 | "movel %3@(8),%1\n\t" | ||
| 119 | "addxl %1,%0\n\t" | ||
| 120 | "movel %3@(12),%1\n\t" | ||
| 121 | "addxl %1,%0\n\t" | ||
| 122 | "addxl %4,%0\n\t" | ||
| 123 | "clrl %1\n\t" | ||
| 124 | "addxl %1,%0" | ||
| 125 | : "=&d" (sum), "=&d" (tmp) | ||
| 126 | : "a" (saddr), "a" (daddr), "d" (len + proto), | ||
| 127 | "0" (sum)); | ||
| 128 | |||
| 129 | return csum_fold(sum); | ||
| 130 | } | ||
| 131 | |||
| 132 | #endif /* _M68K_CHECKSUM_H */ | ||
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h new file mode 100644 index 000000000000..83a9fa4e618a --- /dev/null +++ b/arch/m68k/include/asm/coldfire.h | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * coldfire.h -- Motorola ColdFire CPU sepecific defines | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef coldfire_h | ||
| 12 | #define coldfire_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * Define master clock frequency. This is essentially done at config | ||
| 18 | * time now. No point enumerating dozens of possible clock options | ||
| 19 | * here. Also the peripheral clock (bus clock) divide ratio is set | ||
| 20 | * at config time too. | ||
| 21 | */ | ||
| 22 | #ifdef CONFIG_CLOCK_SET | ||
| 23 | #define MCF_CLK CONFIG_CLOCK_FREQ | ||
| 24 | #define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV) | ||
| 25 | #else | ||
| 26 | #error "Don't know what your ColdFire CPU clock frequency is??" | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Define the processor support peripherals base address. | ||
| 31 | * This is generally setup by the boards start up code. | ||
| 32 | */ | ||
| 33 | #define MCF_MBAR 0x10000000 | ||
| 34 | #define MCF_MBAR2 0x80000000 | ||
| 35 | #if defined(CONFIG_M520x) | ||
| 36 | #define MCF_IPSBAR 0xFC000000 | ||
| 37 | #else | ||
| 38 | #define MCF_IPSBAR 0x40000000 | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ | ||
| 42 | defined(CONFIG_M520x) | ||
| 43 | #undef MCF_MBAR | ||
| 44 | #define MCF_MBAR MCF_IPSBAR | ||
| 45 | #elif defined(CONFIG_M532x) | ||
| 46 | #undef MCF_MBAR | ||
| 47 | #define MCF_MBAR 0x00000000 | ||
| 48 | #endif | ||
| 49 | |||
| 50 | /****************************************************************************/ | ||
| 51 | #endif /* coldfire_h */ | ||
diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h new file mode 100644 index 000000000000..edf5eb6c08d2 --- /dev/null +++ b/arch/m68k/include/asm/commproc.h | |||
| @@ -0,0 +1,703 @@ | |||
| 1 | |||
| 2 | /* | ||
| 3 | * 68360 Communication Processor Module. | ||
| 4 | * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after: | ||
| 5 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx) | ||
| 6 | * | ||
| 7 | * This file contains structures and information for the communication | ||
| 8 | * processor channels. Some CPM control and status is available | ||
| 9 | * through the 68360 internal memory map. See include/asm/360_immap.h for details. | ||
| 10 | * This file is not a complete map of all of the 360 QUICC's capabilities | ||
| 11 | * | ||
| 12 | * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 | ||
| 13 | * bytes of the DP RAM and relocates the I2C parameter area to the | ||
| 14 | * IDMA1 space. The remaining DP RAM is available for buffer descriptors | ||
| 15 | * or other use. | ||
| 16 | */ | ||
| 17 | #ifndef __CPM_360__ | ||
| 18 | #define __CPM_360__ | ||
| 19 | |||
| 20 | |||
| 21 | /* CPM Command register masks: */ | ||
| 22 | #define CPM_CR_RST ((ushort)0x8000) | ||
| 23 | #define CPM_CR_OPCODE ((ushort)0x0f00) | ||
| 24 | #define CPM_CR_CHAN ((ushort)0x00f0) | ||
| 25 | #define CPM_CR_FLG ((ushort)0x0001) | ||
| 26 | |||
| 27 | /* CPM Command set (opcodes): */ | ||
| 28 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | ||
| 29 | #define CPM_CR_INIT_RX ((ushort)0x0001) | ||
| 30 | #define CPM_CR_INIT_TX ((ushort)0x0002) | ||
| 31 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | ||
| 32 | #define CPM_CR_STOP_TX ((ushort)0x0004) | ||
| 33 | #define CPM_CR_GRSTOP_TX ((ushort)0x0005) | ||
| 34 | #define CPM_CR_RESTART_TX ((ushort)0x0006) | ||
| 35 | #define CPM_CR_CLOSE_RXBD ((ushort)0x0007) | ||
| 36 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | ||
| 37 | #define CPM_CR_GCI_TIMEOUT ((ushort)0x0009) | ||
| 38 | #define CPM_CR_GCI_ABORT ((ushort)0x000a) | ||
| 39 | #define CPM_CR_RESET_BCS ((ushort)0x000a) | ||
| 40 | |||
| 41 | /* CPM Channel numbers. */ | ||
| 42 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) | ||
| 43 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) | ||
| 44 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */ | ||
| 45 | #define CPM_CR_CH_TMR ((ushort)0x0005) | ||
| 46 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) | ||
| 47 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */ | ||
| 48 | #define CPM_CR_CH_IDMA1 ((ushort)0x0009) | ||
| 49 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) | ||
| 50 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */ | ||
| 51 | #define CPM_CR_CH_IDMA2 ((ushort)0x000d) | ||
| 52 | |||
| 53 | |||
| 54 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) | ||
| 55 | |||
| 56 | #if 1 /* mleslie: I dinna think we have any such restrictions on | ||
| 57 | * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */ | ||
| 58 | |||
| 59 | /* The dual ported RAM is multi-functional. Some areas can be (and are | ||
| 60 | * being) used for microcode. There is an area that can only be used | ||
| 61 | * as data ram for buffer descriptors, which is all we use right now. | ||
| 62 | * Currently the first 512 and last 256 bytes are used for microcode. | ||
| 63 | */ | ||
| 64 | /* mleslie: The uCquicc board is using no extra microcode in DPRAM */ | ||
| 65 | #define CPM_DATAONLY_BASE ((uint)0x0000) | ||
| 66 | #define CPM_DATAONLY_SIZE ((uint)0x0800) | ||
| 67 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | ||
| 68 | |||
| 69 | #endif | ||
| 70 | |||
| 71 | |||
| 72 | /* Export the base address of the communication processor registers | ||
| 73 | * and dual port ram. */ | ||
| 74 | /* extern cpm360_t *cpmp; */ /* Pointer to comm processor */ | ||
| 75 | extern QUICC *pquicc; | ||
| 76 | uint m360_cpm_dpalloc(uint size); | ||
| 77 | /* void *m360_cpm_hostalloc(uint size); */ | ||
| 78 | void m360_cpm_setbrg(uint brg, uint rate); | ||
| 79 | |||
| 80 | #if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */ | ||
| 81 | /* Buffer descriptors used by many of the CPM protocols. */ | ||
| 82 | typedef struct cpm_buf_desc { | ||
| 83 | ushort cbd_sc; /* Status and Control */ | ||
| 84 | ushort cbd_datlen; /* Data length in buffer */ | ||
| 85 | uint cbd_bufaddr; /* Buffer address in host memory */ | ||
| 86 | } cbd_t; | ||
| 87 | #endif | ||
| 88 | |||
| 89 | |||
| 90 | /* rx bd status/control bits */ | ||
| 91 | #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ | ||
| 92 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ | ||
| 93 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | ||
| 94 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ | ||
| 95 | |||
| 96 | #define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ | ||
| 97 | #define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ | ||
| 98 | |||
| 99 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | ||
| 100 | #define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ | ||
| 101 | |||
| 102 | #define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ | ||
| 103 | #define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */ | ||
| 104 | |||
| 105 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | ||
| 106 | #define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */ | ||
| 107 | |||
| 108 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | ||
| 109 | #define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */ | ||
| 110 | |||
| 111 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | ||
| 112 | #define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */ | ||
| 113 | |||
| 114 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | ||
| 115 | #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ | ||
| 116 | |||
| 117 | /* tx bd status/control bits (as differ from rx bd) */ | ||
| 118 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | ||
| 119 | #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ | ||
| 120 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | ||
| 121 | #define BD_SC_UN ((ushort)0x0002) /* Underrun */ | ||
| 122 | |||
| 123 | |||
| 124 | |||
| 125 | |||
| 126 | /* Parameter RAM offsets. */ | ||
| 127 | |||
| 128 | |||
| 129 | |||
| 130 | /* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM. | ||
| 131 | * In 2.0, we use a more structured C struct map of DPRAM, and so | ||
| 132 | * instead, we need only a parameter ram `slot' */ | ||
| 133 | |||
| 134 | #define PRSLOT_SCC1 0 | ||
| 135 | #define PRSLOT_SCC2 1 | ||
| 136 | #define PRSLOT_SCC3 2 | ||
| 137 | #define PRSLOT_SMC1 2 | ||
| 138 | #define PRSLOT_SCC4 3 | ||
| 139 | #define PRSLOT_SMC2 3 | ||
| 140 | |||
| 141 | |||
| 142 | /* #define PROFF_SCC1 ((uint)0x0000) */ | ||
| 143 | /* #define PROFF_SCC2 ((uint)0x0100) */ | ||
| 144 | /* #define PROFF_SCC3 ((uint)0x0200) */ | ||
| 145 | /* #define PROFF_SMC1 ((uint)0x0280) */ | ||
| 146 | /* #define PROFF_SCC4 ((uint)0x0300) */ | ||
| 147 | /* #define PROFF_SMC2 ((uint)0x0380) */ | ||
| 148 | |||
| 149 | |||
| 150 | /* Define enough so I can at least use the serial port as a UART. | ||
| 151 | * The MBX uses SMC1 as the host serial port. | ||
| 152 | */ | ||
| 153 | typedef struct smc_uart { | ||
| 154 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | ||
| 155 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | ||
| 156 | u_char smc_rfcr; /* Rx function code */ | ||
| 157 | u_char smc_tfcr; /* Tx function code */ | ||
| 158 | ushort smc_mrblr; /* Max receive buffer length */ | ||
| 159 | uint smc_rstate; /* Internal */ | ||
| 160 | uint smc_idp; /* Internal */ | ||
| 161 | ushort smc_rbptr; /* Internal */ | ||
| 162 | ushort smc_ibc; /* Internal */ | ||
| 163 | uint smc_rxtmp; /* Internal */ | ||
| 164 | uint smc_tstate; /* Internal */ | ||
| 165 | uint smc_tdp; /* Internal */ | ||
| 166 | ushort smc_tbptr; /* Internal */ | ||
| 167 | ushort smc_tbc; /* Internal */ | ||
| 168 | uint smc_txtmp; /* Internal */ | ||
| 169 | ushort smc_maxidl; /* Maximum idle characters */ | ||
| 170 | ushort smc_tmpidl; /* Temporary idle counter */ | ||
| 171 | ushort smc_brklen; /* Last received break length */ | ||
| 172 | ushort smc_brkec; /* rcv'd break condition counter */ | ||
| 173 | ushort smc_brkcr; /* xmt break count register */ | ||
| 174 | ushort smc_rmask; /* Temporary bit mask */ | ||
| 175 | } smc_uart_t; | ||
| 176 | |||
| 177 | /* Function code bits. | ||
| 178 | */ | ||
| 179 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ | ||
| 180 | |||
| 181 | /* SMC uart mode register. | ||
| 182 | */ | ||
| 183 | #define SMCMR_REN ((ushort)0x0001) | ||
| 184 | #define SMCMR_TEN ((ushort)0x0002) | ||
| 185 | #define SMCMR_DM ((ushort)0x000c) | ||
| 186 | #define SMCMR_SM_GCI ((ushort)0x0000) | ||
| 187 | #define SMCMR_SM_UART ((ushort)0x0020) | ||
| 188 | #define SMCMR_SM_TRANS ((ushort)0x0030) | ||
| 189 | #define SMCMR_SM_MASK ((ushort)0x0030) | ||
| 190 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | ||
| 191 | #define SMCMR_REVD SMCMR_PM_EVEN | ||
| 192 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | ||
| 193 | #define SMCMR_BS SMCMR_PEN | ||
| 194 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | ||
| 195 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | ||
| 196 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | ||
| 197 | |||
| 198 | /* SMC2 as Centronics parallel printer. It is half duplex, in that | ||
| 199 | * it can only receive or transmit. The parameter ram values for | ||
| 200 | * each direction are either unique or properly overlap, so we can | ||
| 201 | * include them in one structure. | ||
| 202 | */ | ||
| 203 | typedef struct smc_centronics { | ||
| 204 | ushort scent_rbase; | ||
| 205 | ushort scent_tbase; | ||
| 206 | u_char scent_cfcr; | ||
| 207 | u_char scent_smask; | ||
| 208 | ushort scent_mrblr; | ||
| 209 | uint scent_rstate; | ||
| 210 | uint scent_r_ptr; | ||
| 211 | ushort scent_rbptr; | ||
| 212 | ushort scent_r_cnt; | ||
| 213 | uint scent_rtemp; | ||
| 214 | uint scent_tstate; | ||
| 215 | uint scent_t_ptr; | ||
| 216 | ushort scent_tbptr; | ||
| 217 | ushort scent_t_cnt; | ||
| 218 | uint scent_ttemp; | ||
| 219 | ushort scent_max_sl; | ||
| 220 | ushort scent_sl_cnt; | ||
| 221 | ushort scent_character1; | ||
| 222 | ushort scent_character2; | ||
| 223 | ushort scent_character3; | ||
| 224 | ushort scent_character4; | ||
| 225 | ushort scent_character5; | ||
| 226 | ushort scent_character6; | ||
| 227 | ushort scent_character7; | ||
| 228 | ushort scent_character8; | ||
| 229 | ushort scent_rccm; | ||
| 230 | ushort scent_rccr; | ||
| 231 | } smc_cent_t; | ||
| 232 | |||
| 233 | /* Centronics Status Mask Register. | ||
| 234 | */ | ||
| 235 | #define SMC_CENT_F ((u_char)0x08) | ||
| 236 | #define SMC_CENT_PE ((u_char)0x04) | ||
| 237 | #define SMC_CENT_S ((u_char)0x02) | ||
| 238 | |||
| 239 | /* SMC Event and Mask register. | ||
| 240 | */ | ||
| 241 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | ||
| 242 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | ||
| 243 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ | ||
| 244 | #define SMCM_BSY ((unsigned char)0x04) | ||
| 245 | #define SMCM_TX ((unsigned char)0x02) | ||
| 246 | #define SMCM_RX ((unsigned char)0x01) | ||
| 247 | |||
| 248 | /* Baud rate generators. | ||
| 249 | */ | ||
| 250 | #define CPM_BRG_RST ((uint)0x00020000) | ||
| 251 | #define CPM_BRG_EN ((uint)0x00010000) | ||
| 252 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | ||
| 253 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) | ||
| 254 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) | ||
| 255 | #define CPM_BRG_ATB ((uint)0x00002000) | ||
| 256 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | ||
| 257 | #define CPM_BRG_DIV16 ((uint)0x00000001) | ||
| 258 | |||
| 259 | /* SCCs. | ||
| 260 | */ | ||
| 261 | #define SCC_GSMRH_IRP ((uint)0x00040000) | ||
| 262 | #define SCC_GSMRH_GDE ((uint)0x00010000) | ||
| 263 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | ||
| 264 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | ||
| 265 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | ||
| 266 | #define SCC_GSMRH_REVD ((uint)0x00002000) | ||
| 267 | #define SCC_GSMRH_TRX ((uint)0x00001000) | ||
| 268 | #define SCC_GSMRH_TTX ((uint)0x00000800) | ||
| 269 | #define SCC_GSMRH_CDP ((uint)0x00000400) | ||
| 270 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | ||
| 271 | #define SCC_GSMRH_CDS ((uint)0x00000100) | ||
| 272 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | ||
| 273 | #define SCC_GSMRH_TFL ((uint)0x00000040) | ||
| 274 | #define SCC_GSMRH_RFW ((uint)0x00000020) | ||
| 275 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | ||
| 276 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | ||
| 277 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | ||
| 278 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | ||
| 279 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | ||
| 280 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | ||
| 281 | |||
| 282 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | ||
| 283 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | ||
| 284 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | ||
| 285 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | ||
| 286 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | ||
| 287 | #define SCC_GSMRL_TCI ((uint)0x10000000) | ||
| 288 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | ||
| 289 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | ||
| 290 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | ||
| 291 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | ||
| 292 | #define SCC_GSMRL_RINV ((uint)0x02000000) | ||
| 293 | #define SCC_GSMRL_TINV ((uint)0x01000000) | ||
| 294 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | ||
| 295 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | ||
| 296 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | ||
| 297 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | ||
| 298 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | ||
| 299 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | ||
| 300 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | ||
| 301 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | ||
| 302 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | ||
| 303 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | ||
| 304 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | ||
| 305 | #define SCC_GSMRL_TEND ((uint)0x00040000) | ||
| 306 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | ||
| 307 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | ||
| 308 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | ||
| 309 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | ||
| 310 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | ||
| 311 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | ||
| 312 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | ||
| 313 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | ||
| 314 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | ||
| 315 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | ||
| 316 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | ||
| 317 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | ||
| 318 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | ||
| 319 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | ||
| 320 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | ||
| 321 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | ||
| 322 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | ||
| 323 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | ||
| 324 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | ||
| 325 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | ||
| 326 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | ||
| 327 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | ||
| 328 | #define SCC_GSMRL_ENR ((uint)0x00000020) | ||
| 329 | #define SCC_GSMRL_ENT ((uint)0x00000010) | ||
| 330 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | ||
| 331 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | ||
| 332 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | ||
| 333 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | ||
| 334 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | ||
| 335 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | ||
| 336 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | ||
| 337 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | ||
| 338 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | ||
| 339 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | ||
| 340 | |||
| 341 | #define SCC_TODR_TOD ((ushort)0x8000) | ||
| 342 | |||
| 343 | /* SCC Event and Mask register. | ||
| 344 | */ | ||
| 345 | #define SCCM_TXE ((unsigned char)0x10) | ||
| 346 | #define SCCM_BSY ((unsigned char)0x04) | ||
| 347 | #define SCCM_TX ((unsigned char)0x02) | ||
| 348 | #define SCCM_RX ((unsigned char)0x01) | ||
| 349 | |||
| 350 | typedef struct scc_param { | ||
| 351 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | ||
| 352 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | ||
| 353 | u_char scc_rfcr; /* Rx function code */ | ||
| 354 | u_char scc_tfcr; /* Tx function code */ | ||
| 355 | ushort scc_mrblr; /* Max receive buffer length */ | ||
| 356 | uint scc_rstate; /* Internal */ | ||
| 357 | uint scc_idp; /* Internal */ | ||
| 358 | ushort scc_rbptr; /* Internal */ | ||
| 359 | ushort scc_ibc; /* Internal */ | ||
| 360 | uint scc_rxtmp; /* Internal */ | ||
| 361 | uint scc_tstate; /* Internal */ | ||
| 362 | uint scc_tdp; /* Internal */ | ||
| 363 | ushort scc_tbptr; /* Internal */ | ||
| 364 | ushort scc_tbc; /* Internal */ | ||
| 365 | uint scc_txtmp; /* Internal */ | ||
| 366 | uint scc_rcrc; /* Internal */ | ||
| 367 | uint scc_tcrc; /* Internal */ | ||
| 368 | } sccp_t; | ||
| 369 | |||
| 370 | |||
| 371 | /* Function code bits. | ||
| 372 | */ | ||
| 373 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ | ||
| 374 | #define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */ | ||
| 375 | |||
| 376 | /* CPM Ethernet through SCC1. | ||
| 377 | */ | ||
| 378 | typedef struct scc_enet { | ||
| 379 | sccp_t sen_genscc; | ||
| 380 | uint sen_cpres; /* Preset CRC */ | ||
| 381 | uint sen_cmask; /* Constant mask for CRC */ | ||
| 382 | uint sen_crcec; /* CRC Error counter */ | ||
| 383 | uint sen_alec; /* alignment error counter */ | ||
| 384 | uint sen_disfc; /* discard frame counter */ | ||
| 385 | ushort sen_pads; /* Tx short frame pad character */ | ||
| 386 | ushort sen_retlim; /* Retry limit threshold */ | ||
| 387 | ushort sen_retcnt; /* Retry limit counter */ | ||
| 388 | ushort sen_maxflr; /* maximum frame length register */ | ||
| 389 | ushort sen_minflr; /* minimum frame length register */ | ||
| 390 | ushort sen_maxd1; /* maximum DMA1 length */ | ||
| 391 | ushort sen_maxd2; /* maximum DMA2 length */ | ||
| 392 | ushort sen_maxd; /* Rx max DMA */ | ||
| 393 | ushort sen_dmacnt; /* Rx DMA counter */ | ||
| 394 | ushort sen_maxb; /* Max BD byte count */ | ||
| 395 | ushort sen_gaddr1; /* Group address filter */ | ||
| 396 | ushort sen_gaddr2; | ||
| 397 | ushort sen_gaddr3; | ||
| 398 | ushort sen_gaddr4; | ||
| 399 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | ||
| 400 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | ||
| 401 | uint sen_tbuf0rba; /* Internal */ | ||
| 402 | uint sen_tbuf0crc; /* Internal */ | ||
| 403 | ushort sen_tbuf0bcnt; /* Internal */ | ||
| 404 | ushort sen_paddrh; /* physical address (MSB) */ | ||
| 405 | ushort sen_paddrm; | ||
| 406 | ushort sen_paddrl; /* physical address (LSB) */ | ||
| 407 | ushort sen_pper; /* persistence */ | ||
| 408 | ushort sen_rfbdptr; /* Rx first BD pointer */ | ||
| 409 | ushort sen_tfbdptr; /* Tx first BD pointer */ | ||
| 410 | ushort sen_tlbdptr; /* Tx last BD pointer */ | ||
| 411 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | ||
| 412 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | ||
| 413 | uint sen_tbuf1rba; /* Internal */ | ||
| 414 | uint sen_tbuf1crc; /* Internal */ | ||
| 415 | ushort sen_tbuf1bcnt; /* Internal */ | ||
| 416 | ushort sen_txlen; /* Tx Frame length counter */ | ||
| 417 | ushort sen_iaddr1; /* Individual address filter */ | ||
| 418 | ushort sen_iaddr2; | ||
| 419 | ushort sen_iaddr3; | ||
| 420 | ushort sen_iaddr4; | ||
| 421 | ushort sen_boffcnt; /* Backoff counter */ | ||
| 422 | |||
| 423 | /* NOTE: Some versions of the manual have the following items | ||
| 424 | * incorrectly documented. Below is the proper order. | ||
| 425 | */ | ||
| 426 | ushort sen_taddrh; /* temp address (MSB) */ | ||
| 427 | ushort sen_taddrm; | ||
| 428 | ushort sen_taddrl; /* temp address (LSB) */ | ||
| 429 | } scc_enet_t; | ||
| 430 | |||
| 431 | |||
| 432 | |||
| 433 | #if defined (CONFIG_UCQUICC) | ||
| 434 | /* uCquicc has the following signals connected to Ethernet: | ||
| 435 | * 68360 - lxt905 | ||
| 436 | * PA0/RXD1 - rxd | ||
| 437 | * PA1/TXD1 - txd | ||
| 438 | * PA8/CLK1 - tclk | ||
| 439 | * PA9/CLK2 - rclk | ||
| 440 | * PC0/!RTS1 - t_en | ||
| 441 | * PC1/!CTS1 - col | ||
| 442 | * PC5/!CD1 - cd | ||
| 443 | */ | ||
| 444 | #define PA_ENET_RXD PA_RXD1 | ||
| 445 | #define PA_ENET_TXD PA_TXD1 | ||
| 446 | #define PA_ENET_TCLK PA_CLK1 | ||
| 447 | #define PA_ENET_RCLK PA_CLK2 | ||
| 448 | #define PC_ENET_TENA PC_RTS1 | ||
| 449 | #define PC_ENET_CLSN PC_CTS1 | ||
| 450 | #define PC_ENET_RENA PC_CD1 | ||
| 451 | |||
| 452 | /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to | ||
| 453 | * SCC1. | ||
| 454 | */ | ||
| 455 | #define SICR_ENET_MASK ((uint)0x000000ff) | ||
| 456 | #define SICR_ENET_CLKRT ((uint)0x0000002c) | ||
| 457 | |||
| 458 | #endif /* config_ucquicc */ | ||
| 459 | |||
| 460 | |||
| 461 | #ifdef MBX | ||
| 462 | /* Bits in parallel I/O port registers that have to be set/cleared | ||
| 463 | * to configure the pins for SCC1 use. The TCLK and RCLK seem unique | ||
| 464 | * to the MBX860 board. Any two of the four available clocks could be | ||
| 465 | * used, and the MPC860 cookbook manual has an example using different | ||
| 466 | * clock pins. | ||
| 467 | */ | ||
| 468 | #define PA_ENET_RXD ((ushort)0x0001) | ||
| 469 | #define PA_ENET_TXD ((ushort)0x0002) | ||
| 470 | #define PA_ENET_TCLK ((ushort)0x0200) | ||
| 471 | #define PA_ENET_RCLK ((ushort)0x0800) | ||
| 472 | #define PC_ENET_TENA ((ushort)0x0001) | ||
| 473 | #define PC_ENET_CLSN ((ushort)0x0010) | ||
| 474 | #define PC_ENET_RENA ((ushort)0x0020) | ||
| 475 | |||
| 476 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to | ||
| 477 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. | ||
| 478 | */ | ||
| 479 | #define SICR_ENET_MASK ((uint)0x000000ff) | ||
| 480 | #define SICR_ENET_CLKRT ((uint)0x0000003d) | ||
| 481 | #endif | ||
| 482 | |||
| 483 | #ifdef CONFIG_RPXLITE | ||
| 484 | /* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of | ||
| 485 | * this may be unique to the RPX-Lite configuration. | ||
| 486 | * Note TENA is on Port B. | ||
| 487 | */ | ||
| 488 | #define PA_ENET_RXD ((ushort)0x0004) | ||
| 489 | #define PA_ENET_TXD ((ushort)0x0008) | ||
| 490 | #define PA_ENET_TCLK ((ushort)0x0200) | ||
| 491 | #define PA_ENET_RCLK ((ushort)0x0800) | ||
| 492 | #define PB_ENET_TENA ((uint)0x00002000) | ||
| 493 | #define PC_ENET_CLSN ((ushort)0x0040) | ||
| 494 | #define PC_ENET_RENA ((ushort)0x0080) | ||
| 495 | |||
| 496 | #define SICR_ENET_MASK ((uint)0x0000ff00) | ||
| 497 | #define SICR_ENET_CLKRT ((uint)0x00003d00) | ||
| 498 | #endif | ||
| 499 | |||
| 500 | #ifdef CONFIG_BSEIP | ||
| 501 | /* This ENET stuff is for the MPC823 with ethernet on SCC2. | ||
| 502 | * This is unique to the BSE ip-Engine board. | ||
| 503 | */ | ||
| 504 | #define PA_ENET_RXD ((ushort)0x0004) | ||
| 505 | #define PA_ENET_TXD ((ushort)0x0008) | ||
| 506 | #define PA_ENET_TCLK ((ushort)0x0100) | ||
| 507 | #define PA_ENET_RCLK ((ushort)0x0200) | ||
| 508 | #define PB_ENET_TENA ((uint)0x00002000) | ||
| 509 | #define PC_ENET_CLSN ((ushort)0x0040) | ||
| 510 | #define PC_ENET_RENA ((ushort)0x0080) | ||
| 511 | |||
| 512 | /* BSE uses port B and C bits for PHY control also. | ||
| 513 | */ | ||
| 514 | #define PB_BSE_POWERUP ((uint)0x00000004) | ||
| 515 | #define PB_BSE_FDXDIS ((uint)0x00008000) | ||
| 516 | #define PC_BSE_LOOPBACK ((ushort)0x0800) | ||
| 517 | |||
| 518 | #define SICR_ENET_MASK ((uint)0x0000ff00) | ||
| 519 | #define SICR_ENET_CLKRT ((uint)0x00002c00) | ||
| 520 | #endif | ||
| 521 | |||
| 522 | /* SCC Event register as used by Ethernet. | ||
| 523 | */ | ||
| 524 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | ||
| 525 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | ||
| 526 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | ||
| 527 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | ||
| 528 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | ||
| 529 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | ||
| 530 | |||
| 531 | /* SCC Mode Register (PMSR) as used by Ethernet. | ||
| 532 | */ | ||
| 533 | #define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */ | ||
| 534 | #define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */ | ||
| 535 | #define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */ | ||
| 536 | #define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */ | ||
| 537 | #define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | ||
| 538 | #define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */ | ||
| 539 | #define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | ||
| 540 | #define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */ | ||
| 541 | #define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */ | ||
| 542 | #define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */ | ||
| 543 | #define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */ | ||
| 544 | #define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */ | ||
| 545 | #define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */ | ||
| 546 | |||
| 547 | /* Buffer descriptor control/status used by Ethernet receive. | ||
| 548 | */ | ||
| 549 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | ||
| 550 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | ||
| 551 | #define BD_ENET_RX_INTR ((ushort)0x1000) | ||
| 552 | #define BD_ENET_RX_LAST ((ushort)0x0800) | ||
| 553 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | ||
| 554 | #define BD_ENET_RX_MISS ((ushort)0x0100) | ||
| 555 | #define BD_ENET_RX_LG ((ushort)0x0020) | ||
| 556 | #define BD_ENET_RX_NO ((ushort)0x0010) | ||
| 557 | #define BD_ENET_RX_SH ((ushort)0x0008) | ||
| 558 | #define BD_ENET_RX_CR ((ushort)0x0004) | ||
| 559 | #define BD_ENET_RX_OV ((ushort)0x0002) | ||
| 560 | #define BD_ENET_RX_CL ((ushort)0x0001) | ||
| 561 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | ||
| 562 | |||
| 563 | /* Buffer descriptor control/status used by Ethernet transmit. | ||
| 564 | */ | ||
| 565 | #define BD_ENET_TX_READY ((ushort)0x8000) | ||
| 566 | #define BD_ENET_TX_PAD ((ushort)0x4000) | ||
| 567 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | ||
| 568 | #define BD_ENET_TX_INTR ((ushort)0x1000) | ||
| 569 | #define BD_ENET_TX_LAST ((ushort)0x0800) | ||
| 570 | #define BD_ENET_TX_TC ((ushort)0x0400) | ||
| 571 | #define BD_ENET_TX_DEF ((ushort)0x0200) | ||
| 572 | #define BD_ENET_TX_HB ((ushort)0x0100) | ||
| 573 | #define BD_ENET_TX_LC ((ushort)0x0080) | ||
| 574 | #define BD_ENET_TX_RL ((ushort)0x0040) | ||
| 575 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | ||
| 576 | #define BD_ENET_TX_UN ((ushort)0x0002) | ||
| 577 | #define BD_ENET_TX_CSL ((ushort)0x0001) | ||
| 578 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | ||
| 579 | |||
| 580 | /* SCC as UART | ||
| 581 | */ | ||
| 582 | typedef struct scc_uart { | ||
| 583 | sccp_t scc_genscc; | ||
| 584 | uint scc_res1; /* Reserved */ | ||
| 585 | uint scc_res2; /* Reserved */ | ||
| 586 | ushort scc_maxidl; /* Maximum idle chars */ | ||
| 587 | ushort scc_idlc; /* temp idle counter */ | ||
| 588 | ushort scc_brkcr; /* Break count register */ | ||
| 589 | ushort scc_parec; /* receive parity error counter */ | ||
| 590 | ushort scc_frmec; /* receive framing error counter */ | ||
| 591 | ushort scc_nosec; /* receive noise counter */ | ||
| 592 | ushort scc_brkec; /* receive break condition counter */ | ||
| 593 | ushort scc_brkln; /* last received break length */ | ||
| 594 | ushort scc_uaddr1; /* UART address character 1 */ | ||
| 595 | ushort scc_uaddr2; /* UART address character 2 */ | ||
| 596 | ushort scc_rtemp; /* Temp storage */ | ||
| 597 | ushort scc_toseq; /* Transmit out of sequence char */ | ||
| 598 | ushort scc_char1; /* control character 1 */ | ||
| 599 | ushort scc_char2; /* control character 2 */ | ||
| 600 | ushort scc_char3; /* control character 3 */ | ||
| 601 | ushort scc_char4; /* control character 4 */ | ||
| 602 | ushort scc_char5; /* control character 5 */ | ||
| 603 | ushort scc_char6; /* control character 6 */ | ||
| 604 | ushort scc_char7; /* control character 7 */ | ||
| 605 | ushort scc_char8; /* control character 8 */ | ||
| 606 | ushort scc_rccm; /* receive control character mask */ | ||
| 607 | ushort scc_rccr; /* receive control character register */ | ||
| 608 | ushort scc_rlbc; /* receive last break character */ | ||
| 609 | } scc_uart_t; | ||
| 610 | |||
| 611 | /* SCC Event and Mask registers when it is used as a UART. | ||
| 612 | */ | ||
| 613 | #define UART_SCCM_GLR ((ushort)0x1000) | ||
| 614 | #define UART_SCCM_GLT ((ushort)0x0800) | ||
| 615 | #define UART_SCCM_AB ((ushort)0x0200) | ||
| 616 | #define UART_SCCM_IDL ((ushort)0x0100) | ||
| 617 | #define UART_SCCM_GRA ((ushort)0x0080) | ||
| 618 | #define UART_SCCM_BRKE ((ushort)0x0040) | ||
| 619 | #define UART_SCCM_BRKS ((ushort)0x0020) | ||
| 620 | #define UART_SCCM_CCR ((ushort)0x0008) | ||
| 621 | #define UART_SCCM_BSY ((ushort)0x0004) | ||
| 622 | #define UART_SCCM_TX ((ushort)0x0002) | ||
| 623 | #define UART_SCCM_RX ((ushort)0x0001) | ||
| 624 | |||
| 625 | /* The SCC PMSR when used as a UART. | ||
| 626 | */ | ||
| 627 | #define SCU_PMSR_FLC ((ushort)0x8000) | ||
| 628 | #define SCU_PMSR_SL ((ushort)0x4000) | ||
| 629 | #define SCU_PMSR_CL ((ushort)0x3000) | ||
| 630 | #define SCU_PMSR_UM ((ushort)0x0c00) | ||
| 631 | #define SCU_PMSR_FRZ ((ushort)0x0200) | ||
| 632 | #define SCU_PMSR_RZS ((ushort)0x0100) | ||
| 633 | #define SCU_PMSR_SYN ((ushort)0x0080) | ||
| 634 | #define SCU_PMSR_DRT ((ushort)0x0040) | ||
| 635 | #define SCU_PMSR_PEN ((ushort)0x0010) | ||
| 636 | #define SCU_PMSR_RPM ((ushort)0x000c) | ||
| 637 | #define SCU_PMSR_REVP ((ushort)0x0008) | ||
| 638 | #define SCU_PMSR_TPM ((ushort)0x0003) | ||
| 639 | #define SCU_PMSR_TEVP ((ushort)0x0003) | ||
| 640 | |||
| 641 | /* CPM Transparent mode SCC. | ||
| 642 | */ | ||
| 643 | typedef struct scc_trans { | ||
| 644 | sccp_t st_genscc; | ||
| 645 | uint st_cpres; /* Preset CRC */ | ||
| 646 | uint st_cmask; /* Constant mask for CRC */ | ||
| 647 | } scc_trans_t; | ||
| 648 | |||
| 649 | #define BD_SCC_TX_LAST ((ushort)0x0800) | ||
| 650 | |||
| 651 | |||
| 652 | |||
| 653 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM | ||
| 654 | * channels or devices. All of these are presented to the PPC core | ||
| 655 | * as a single interrupt. The CPM interrupt handler dispatches its | ||
| 656 | * own handlers, in a similar fashion to the PPC core handler. We | ||
| 657 | * use the table as defined in the manuals (i.e. no special high | ||
| 658 | * priority and SCC1 == SCCa, etc...). | ||
| 659 | */ | ||
| 660 | /* #define CPMVEC_NR 32 */ | ||
| 661 | /* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */ | ||
| 662 | /* #define CPMVEC_SCC1 ((ushort)0x1e) */ | ||
| 663 | /* #define CPMVEC_SCC2 ((ushort)0x1d) */ | ||
| 664 | /* #define CPMVEC_SCC3 ((ushort)0x1c) */ | ||
| 665 | /* #define CPMVEC_SCC4 ((ushort)0x1b) */ | ||
| 666 | /* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */ | ||
| 667 | /* #define CPMVEC_TIMER1 ((ushort)0x19) */ | ||
| 668 | /* #define CPMVEC_PIO_PC13 ((ushort)0x18) */ | ||
| 669 | /* #define CPMVEC_PIO_PC12 ((ushort)0x17) */ | ||
| 670 | /* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ | ||
| 671 | /* #define CPMVEC_IDMA1 ((ushort)0x15) */ | ||
| 672 | /* #define CPMVEC_IDMA2 ((ushort)0x14) */ | ||
| 673 | /* #define CPMVEC_TIMER2 ((ushort)0x12) */ | ||
| 674 | /* #define CPMVEC_RISCTIMER ((ushort)0x11) */ | ||
| 675 | /* #define CPMVEC_I2C ((ushort)0x10) */ | ||
| 676 | /* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */ | ||
| 677 | /* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */ | ||
| 678 | /* #define CPMVEC_TIMER3 ((ushort)0x0c) */ | ||
| 679 | /* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */ | ||
| 680 | /* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */ | ||
| 681 | /* #define CPMVEC_PIO_PC7 ((ushort)0x09) */ | ||
| 682 | /* #define CPMVEC_TIMER4 ((ushort)0x07) */ | ||
| 683 | /* #define CPMVEC_PIO_PC6 ((ushort)0x06) */ | ||
| 684 | /* #define CPMVEC_SPI ((ushort)0x05) */ | ||
| 685 | /* #define CPMVEC_SMC1 ((ushort)0x04) */ | ||
| 686 | /* #define CPMVEC_SMC2 ((ushort)0x03) */ | ||
| 687 | /* #define CPMVEC_PIO_PC5 ((ushort)0x02) */ | ||
| 688 | /* #define CPMVEC_PIO_PC4 ((ushort)0x01) */ | ||
| 689 | /* #define CPMVEC_ERROR ((ushort)0x00) */ | ||
| 690 | |||
| 691 | extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); | ||
| 692 | |||
| 693 | /* CPM interrupt configuration vector. | ||
| 694 | */ | ||
| 695 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | ||
| 696 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | ||
| 697 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | ||
| 698 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | ||
| 699 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ | ||
| 700 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ | ||
| 701 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | ||
| 702 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | ||
| 703 | #endif /* __CPM_360__ */ | ||
diff --git a/arch/m68k/include/asm/contregs.h b/arch/m68k/include/asm/contregs.h new file mode 100644 index 000000000000..d1ea750bddfe --- /dev/null +++ b/arch/m68k/include/asm/contregs.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | #ifndef _M68K_CONTREGS_H | ||
| 2 | #define _M68K_CONTREGS_H | ||
| 3 | |||
| 4 | /* contregs.h: Addresses of registers in the ASI_CONTROL alternate address | ||
| 5 | * space. These are for the mmu's context register, etc. | ||
| 6 | * | ||
| 7 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /* 3=sun3 | ||
| 11 | 4=sun4 (as in sun4 sysmaint student book) | ||
| 12 | c=sun4c (according to davem) */ | ||
| 13 | |||
| 14 | #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */ | ||
| 15 | #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */ | ||
| 16 | #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */ | ||
| 17 | #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */ | ||
| 18 | #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/ | ||
| 19 | #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */ | ||
| 20 | #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */ | ||
| 21 | #define AC_SYNC_ERR 0x60000000 /* c fault type */ | ||
| 22 | #define AC_SYNC_VA 0x60000004 /* c fault virtual address */ | ||
| 23 | #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */ | ||
| 24 | #define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */ | ||
| 25 | #define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */ | ||
| 26 | #define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */ | ||
| 27 | #define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */ | ||
| 28 | #define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */ | ||
| 29 | #define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */ | ||
| 30 | #define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/ | ||
| 31 | |||
| 32 | /* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */ | ||
| 33 | #define AC_M_PCR 0x0000 /* shv Processor Control Reg */ | ||
| 34 | #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */ | ||
| 35 | #define AC_M_CXR 0x0200 /* shv Context Register */ | ||
| 36 | #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */ | ||
| 37 | #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */ | ||
| 38 | #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */ | ||
| 39 | #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */ | ||
| 40 | #define AC_M_RESET 0x0700 /* hv Reset Reg */ | ||
| 41 | #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */ | ||
| 42 | #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */ | ||
| 43 | #define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */ | ||
| 44 | #define AC_M_DAPTP 0x1200 /* hv Data Access PTP */ | ||
| 45 | #define AC_M_ITR 0x1300 /* hv Index Tag Register */ | ||
| 46 | #define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */ | ||
| 47 | #define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */ | ||
| 48 | #define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */ | ||
| 49 | #define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */ | ||
| 50 | #define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */ | ||
| 51 | #define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */ | ||
| 52 | |||
| 53 | #endif /* _M68K_CONTREGS_H */ | ||
diff --git a/arch/m68k/include/asm/cputime.h b/arch/m68k/include/asm/cputime.h new file mode 100644 index 000000000000..c79c5e892305 --- /dev/null +++ b/arch/m68k/include/asm/cputime.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef __M68K_CPUTIME_H | ||
| 2 | #define __M68K_CPUTIME_H | ||
| 3 | |||
| 4 | #include <asm-generic/cputime.h> | ||
| 5 | |||
| 6 | #endif /* __M68K_CPUTIME_H */ | ||
diff --git a/arch/m68k/include/asm/current.h b/arch/m68k/include/asm/current.h new file mode 100644 index 000000000000..51b056dfaedd --- /dev/null +++ b/arch/m68k/include/asm/current.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "current_no.h" | ||
| 3 | #else | ||
| 4 | #include "current_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/current_mm.h b/arch/m68k/include/asm/current_mm.h new file mode 100644 index 000000000000..8de8f8ceda61 --- /dev/null +++ b/arch/m68k/include/asm/current_mm.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68K_CURRENT_H | ||
| 2 | #define _M68K_CURRENT_H | ||
| 3 | |||
| 4 | register struct task_struct *current __asm__("%a2"); | ||
| 5 | |||
| 6 | #endif /* !(_M68K_CURRENT_H) */ | ||
diff --git a/arch/m68k/include/asm/current_no.h b/arch/m68k/include/asm/current_no.h new file mode 100644 index 000000000000..53ee0f9f7cef --- /dev/null +++ b/arch/m68k/include/asm/current_no.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | #ifndef _M68KNOMMU_CURRENT_H | ||
| 2 | #define _M68KNOMMU_CURRENT_H | ||
| 3 | /* | ||
| 4 | * current.h | ||
| 5 | * (C) Copyright 2000, Lineo, David McCullough <davidm@uclinux.org> | ||
| 6 | * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * | ||
| 8 | * rather than dedicate a register (as the m68k source does), we | ||
| 9 | * just keep a global, we should probably just change it all to be | ||
| 10 | * current and lose _current_task. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/thread_info.h> | ||
| 14 | |||
| 15 | struct task_struct; | ||
| 16 | |||
| 17 | static inline struct task_struct *get_current(void) | ||
| 18 | { | ||
| 19 | return(current_thread_info()->task); | ||
| 20 | } | ||
| 21 | |||
| 22 | #define current get_current() | ||
| 23 | |||
| 24 | #endif /* _M68KNOMMU_CURRENT_H */ | ||
diff --git a/arch/m68k/include/asm/dbg.h b/arch/m68k/include/asm/dbg.h new file mode 100644 index 000000000000..27af3270f671 --- /dev/null +++ b/arch/m68k/include/asm/dbg.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #define DEBUG 1 | ||
| 2 | #ifdef CONFIG_COLDFIRE | ||
| 3 | #define BREAK asm volatile ("halt") | ||
| 4 | #else | ||
| 5 | #define BREAK *(volatile unsigned char *)0xdeadbee0 = 0 | ||
| 6 | #endif | ||
diff --git a/arch/m68k/include/asm/delay.h b/arch/m68k/include/asm/delay.h new file mode 100644 index 000000000000..d2598e3dd7b2 --- /dev/null +++ b/arch/m68k/include/asm/delay.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "delay_no.h" | ||
| 3 | #else | ||
| 4 | #include "delay_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/delay_mm.h b/arch/m68k/include/asm/delay_mm.h new file mode 100644 index 000000000000..5ed92851bc6f --- /dev/null +++ b/arch/m68k/include/asm/delay_mm.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | #ifndef _M68K_DELAY_H | ||
| 2 | #define _M68K_DELAY_H | ||
| 3 | |||
| 4 | #include <asm/param.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Copyright (C) 1994 Hamish Macdonald | ||
| 8 | * | ||
| 9 | * Delay routines, using a pre-computed "loops_per_jiffy" value. | ||
| 10 | */ | ||
| 11 | |||
| 12 | static inline void __delay(unsigned long loops) | ||
| 13 | { | ||
| 14 | __asm__ __volatile__ ("1: subql #1,%0; jcc 1b" | ||
| 15 | : "=d" (loops) : "0" (loops)); | ||
| 16 | } | ||
| 17 | |||
| 18 | extern void __bad_udelay(void); | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Use only for very small delays ( < 1 msec). Should probably use a | ||
| 22 | * lookup table, really, as the multiplications take much too long with | ||
| 23 | * short delays. This is a "reasonable" implementation, though (and the | ||
| 24 | * first constant multiplications gets optimized away if the delay is | ||
| 25 | * a constant) | ||
| 26 | */ | ||
| 27 | static inline void __const_udelay(unsigned long xloops) | ||
| 28 | { | ||
| 29 | unsigned long tmp; | ||
| 30 | |||
| 31 | __asm__ ("mulul %2,%0:%1" | ||
| 32 | : "=d" (xloops), "=d" (tmp) | ||
| 33 | : "d" (xloops), "1" (loops_per_jiffy)); | ||
| 34 | __delay(xloops * HZ); | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline void __udelay(unsigned long usecs) | ||
| 38 | { | ||
| 39 | __const_udelay(usecs * 4295); /* 2**32 / 1000000 */ | ||
| 40 | } | ||
| 41 | |||
| 42 | #define udelay(n) (__builtin_constant_p(n) ? \ | ||
| 43 | ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 4295)) : \ | ||
| 44 | __udelay(n)) | ||
| 45 | |||
| 46 | static inline unsigned long muldiv(unsigned long a, unsigned long b, | ||
| 47 | unsigned long c) | ||
| 48 | { | ||
| 49 | unsigned long tmp; | ||
| 50 | |||
| 51 | __asm__ ("mulul %2,%0:%1; divul %3,%0:%1" | ||
| 52 | : "=d" (tmp), "=d" (a) | ||
| 53 | : "d" (b), "d" (c), "1" (a)); | ||
| 54 | return a; | ||
| 55 | } | ||
| 56 | |||
| 57 | #endif /* defined(_M68K_DELAY_H) */ | ||
diff --git a/arch/m68k/include/asm/delay_no.h b/arch/m68k/include/asm/delay_no.h new file mode 100644 index 000000000000..55cbd6294ab6 --- /dev/null +++ b/arch/m68k/include/asm/delay_no.h | |||
| @@ -0,0 +1,76 @@ | |||
| 1 | #ifndef _M68KNOMMU_DELAY_H | ||
| 2 | #define _M68KNOMMU_DELAY_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Copyright (C) 1994 Hamish Macdonald | ||
| 6 | * Copyright (C) 2004 Greg Ungerer <gerg@snapgear.com> | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/param.h> | ||
| 10 | |||
| 11 | static inline void __delay(unsigned long loops) | ||
| 12 | { | ||
| 13 | #if defined(CONFIG_COLDFIRE) | ||
| 14 | /* The coldfire runs this loop at significantly different speeds | ||
| 15 | * depending upon long word alignment or not. We'll pad it to | ||
| 16 | * long word alignment which is the faster version. | ||
| 17 | * The 0x4a8e is of course a 'tstl %fp' instruction. This is better | ||
| 18 | * than using a NOP (0x4e71) instruction because it executes in one | ||
| 19 | * cycle not three and doesn't allow for an arbitary delay waiting | ||
| 20 | * for bus cycles to finish. Also fp/a6 isn't likely to cause a | ||
| 21 | * stall waiting for the register to become valid if such is added | ||
| 22 | * to the coldfire at some stage. | ||
| 23 | */ | ||
| 24 | __asm__ __volatile__ ( ".balignw 4, 0x4a8e\n\t" | ||
| 25 | "1: subql #1, %0\n\t" | ||
| 26 | "jcc 1b" | ||
| 27 | : "=d" (loops) : "0" (loops)); | ||
| 28 | #else | ||
| 29 | __asm__ __volatile__ ( "1: subql #1, %0\n\t" | ||
| 30 | "jcc 1b" | ||
| 31 | : "=d" (loops) : "0" (loops)); | ||
| 32 | #endif | ||
| 33 | } | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Ideally we use a 32*32->64 multiply to calculate the number of | ||
| 37 | * loop iterations, but the older standard 68k and ColdFire do not | ||
| 38 | * have this instruction. So for them we have a clsoe approximation | ||
| 39 | * loop using 32*32->32 multiplies only. This calculation based on | ||
| 40 | * the ARM version of delay. | ||
| 41 | * | ||
| 42 | * We want to implement: | ||
| 43 | * | ||
| 44 | * loops = (usecs * 0x10c6 * HZ * loops_per_jiffy) / 2^32 | ||
| 45 | */ | ||
| 46 | |||
| 47 | #define HZSCALE (268435456 / (1000000/HZ)) | ||
| 48 | |||
| 49 | extern unsigned long loops_per_jiffy; | ||
| 50 | |||
| 51 | static inline void _udelay(unsigned long usecs) | ||
| 52 | { | ||
| 53 | #if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \ | ||
| 54 | defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \ | ||
| 55 | defined(CONFIG_COLDFIRE) | ||
| 56 | __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6); | ||
| 57 | #else | ||
| 58 | unsigned long tmp; | ||
| 59 | |||
| 60 | usecs *= 4295; /* 2**32 / 1000000 */ | ||
| 61 | __asm__ ("mulul %2,%0:%1" | ||
| 62 | : "=d" (usecs), "=d" (tmp) | ||
| 63 | : "d" (usecs), "1" (loops_per_jiffy*HZ)); | ||
| 64 | __delay(usecs); | ||
| 65 | #endif | ||
| 66 | } | ||
| 67 | |||
| 68 | /* | ||
| 69 | * Moved the udelay() function into library code, no longer inlined. | ||
| 70 | * I had to change the algorithm because we are overflowing now on | ||
| 71 | * the faster ColdFire parts. The code is a little bigger, so it makes | ||
| 72 | * sense to library it. | ||
| 73 | */ | ||
| 74 | extern void udelay(unsigned long usecs); | ||
| 75 | |||
| 76 | #endif /* defined(_M68KNOMMU_DELAY_H) */ | ||
diff --git a/arch/m68k/include/asm/device.h b/arch/m68k/include/asm/device.h new file mode 100644 index 000000000000..d8f9872b0e2d --- /dev/null +++ b/arch/m68k/include/asm/device.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | /* | ||
| 2 | * Arch specific extensions to struct device | ||
| 3 | * | ||
| 4 | * This file is released under the GPLv2 | ||
| 5 | */ | ||
| 6 | #include <asm-generic/device.h> | ||
| 7 | |||
diff --git a/arch/m68k/include/asm/div64.h b/arch/m68k/include/asm/div64.h new file mode 100644 index 000000000000..d211d9f54276 --- /dev/null +++ b/arch/m68k/include/asm/div64.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "div64_no.h" | ||
| 3 | #else | ||
| 4 | #include "div64_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/div64_mm.h b/arch/m68k/include/asm/div64_mm.h new file mode 100644 index 000000000000..8243c931b5c0 --- /dev/null +++ b/arch/m68k/include/asm/div64_mm.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | #ifndef _M68K_DIV64_H | ||
| 2 | #define _M68K_DIV64_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* n = n / base; return rem; */ | ||
| 7 | |||
| 8 | #define do_div(n, base) ({ \ | ||
| 9 | union { \ | ||
| 10 | unsigned long n32[2]; \ | ||
| 11 | unsigned long long n64; \ | ||
| 12 | } __n; \ | ||
| 13 | unsigned long __rem, __upper; \ | ||
| 14 | \ | ||
| 15 | __n.n64 = (n); \ | ||
| 16 | if ((__upper = __n.n32[0])) { \ | ||
| 17 | asm ("divul.l %2,%1:%0" \ | ||
| 18 | : "=d" (__n.n32[0]), "=d" (__upper) \ | ||
| 19 | : "d" (base), "0" (__n.n32[0])); \ | ||
| 20 | } \ | ||
| 21 | asm ("divu.l %2,%1:%0" \ | ||
| 22 | : "=d" (__n.n32[1]), "=d" (__rem) \ | ||
| 23 | : "d" (base), "1" (__upper), "0" (__n.n32[1])); \ | ||
| 24 | (n) = __n.n64; \ | ||
| 25 | __rem; \ | ||
| 26 | }) | ||
| 27 | |||
| 28 | #endif /* _M68K_DIV64_H */ | ||
diff --git a/arch/m68k/include/asm/div64_no.h b/arch/m68k/include/asm/div64_no.h new file mode 100644 index 000000000000..6cd978cefb28 --- /dev/null +++ b/arch/m68k/include/asm/div64_no.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/div64.h> | |||
diff --git a/arch/m68k/include/asm/dma-mapping.h b/arch/m68k/include/asm/dma-mapping.h new file mode 100644 index 000000000000..f4a4c7638f89 --- /dev/null +++ b/arch/m68k/include/asm/dma-mapping.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "dma-mapping_no.h" | ||
| 3 | #else | ||
| 4 | #include "dma-mapping_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/dma-mapping_mm.h b/arch/m68k/include/asm/dma-mapping_mm.h new file mode 100644 index 000000000000..26f505488c11 --- /dev/null +++ b/arch/m68k/include/asm/dma-mapping_mm.h | |||
| @@ -0,0 +1,112 @@ | |||
| 1 | #ifndef _M68K_DMA_MAPPING_H | ||
| 2 | #define _M68K_DMA_MAPPING_H | ||
| 3 | |||
| 4 | #include <asm/cache.h> | ||
| 5 | |||
| 6 | struct scatterlist; | ||
| 7 | |||
| 8 | #ifndef CONFIG_MMU_SUN3 | ||
| 9 | static inline int dma_supported(struct device *dev, u64 mask) | ||
| 10 | { | ||
| 11 | return 1; | ||
| 12 | } | ||
| 13 | |||
| 14 | static inline int dma_set_mask(struct device *dev, u64 mask) | ||
| 15 | { | ||
| 16 | return 0; | ||
| 17 | } | ||
| 18 | |||
| 19 | static inline int dma_get_cache_alignment(void) | ||
| 20 | { | ||
| 21 | return 1 << L1_CACHE_SHIFT; | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr) | ||
| 25 | { | ||
| 26 | return 0; | ||
| 27 | } | ||
| 28 | |||
| 29 | extern void *dma_alloc_coherent(struct device *, size_t, | ||
| 30 | dma_addr_t *, gfp_t); | ||
| 31 | extern void dma_free_coherent(struct device *, size_t, | ||
| 32 | void *, dma_addr_t); | ||
| 33 | |||
| 34 | static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, | ||
| 35 | dma_addr_t *handle, gfp_t flag) | ||
| 36 | { | ||
| 37 | return dma_alloc_coherent(dev, size, handle, flag); | ||
| 38 | } | ||
| 39 | static inline void dma_free_noncoherent(struct device *dev, size_t size, | ||
| 40 | void *addr, dma_addr_t handle) | ||
| 41 | { | ||
| 42 | dma_free_coherent(dev, size, addr, handle); | ||
| 43 | } | ||
| 44 | static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, | ||
| 45 | enum dma_data_direction dir) | ||
| 46 | { | ||
| 47 | /* we use coherent allocation, so not much to do here. */ | ||
| 48 | } | ||
| 49 | |||
| 50 | extern dma_addr_t dma_map_single(struct device *, void *, size_t, | ||
| 51 | enum dma_data_direction); | ||
| 52 | static inline void dma_unmap_single(struct device *dev, dma_addr_t addr, | ||
| 53 | size_t size, enum dma_data_direction dir) | ||
| 54 | { | ||
| 55 | } | ||
| 56 | |||
| 57 | extern dma_addr_t dma_map_page(struct device *, struct page *, | ||
| 58 | unsigned long, size_t size, | ||
| 59 | enum dma_data_direction); | ||
| 60 | static inline void dma_unmap_page(struct device *dev, dma_addr_t address, | ||
| 61 | size_t size, enum dma_data_direction dir) | ||
| 62 | { | ||
| 63 | } | ||
| 64 | |||
| 65 | extern int dma_map_sg(struct device *, struct scatterlist *, int, | ||
| 66 | enum dma_data_direction); | ||
| 67 | static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg, | ||
| 68 | int nhwentries, enum dma_data_direction dir) | ||
| 69 | { | ||
| 70 | } | ||
| 71 | |||
| 72 | extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t, | ||
| 73 | enum dma_data_direction); | ||
| 74 | extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int, | ||
| 75 | enum dma_data_direction); | ||
| 76 | |||
| 77 | static inline void dma_sync_single_range_for_device(struct device *dev, | ||
| 78 | dma_addr_t dma_handle, unsigned long offset, size_t size, | ||
| 79 | enum dma_data_direction direction) | ||
| 80 | { | ||
| 81 | /* just sync everything for now */ | ||
| 82 | dma_sync_single_for_device(dev, dma_handle, offset + size, direction); | ||
| 83 | } | ||
| 84 | |||
| 85 | static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, | ||
| 86 | size_t size, enum dma_data_direction dir) | ||
| 87 | { | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | ||
| 91 | int nents, enum dma_data_direction dir) | ||
| 92 | { | ||
| 93 | } | ||
| 94 | |||
| 95 | static inline void dma_sync_single_range_for_cpu(struct device *dev, | ||
| 96 | dma_addr_t dma_handle, unsigned long offset, size_t size, | ||
| 97 | enum dma_data_direction direction) | ||
| 98 | { | ||
| 99 | /* just sync everything for now */ | ||
| 100 | dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction); | ||
| 101 | } | ||
| 102 | |||
| 103 | static inline int dma_mapping_error(struct device *dev, dma_addr_t handle) | ||
| 104 | { | ||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | #else | ||
| 109 | #include <asm-generic/dma-mapping-broken.h> | ||
| 110 | #endif | ||
| 111 | |||
| 112 | #endif /* _M68K_DMA_MAPPING_H */ | ||
diff --git a/arch/m68k/include/asm/dma-mapping_no.h b/arch/m68k/include/asm/dma-mapping_no.h new file mode 100644 index 000000000000..6aeab18e58bd --- /dev/null +++ b/arch/m68k/include/asm/dma-mapping_no.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | #ifndef _M68KNOMMU_DMA_MAPPING_H | ||
| 2 | #define _M68KNOMMU_DMA_MAPPING_H | ||
| 3 | |||
| 4 | #ifdef CONFIG_PCI | ||
| 5 | #include <asm-generic/dma-mapping.h> | ||
| 6 | #else | ||
| 7 | #include <asm-generic/dma-mapping-broken.h> | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #endif /* _M68KNOMMU_DMA_MAPPING_H */ | ||
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h new file mode 100644 index 000000000000..b82e660cf1c2 --- /dev/null +++ b/arch/m68k/include/asm/dma.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "dma_no.h" | ||
| 3 | #else | ||
| 4 | #include "dma_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/dma_mm.h b/arch/m68k/include/asm/dma_mm.h new file mode 100644 index 000000000000..4240fbc946f8 --- /dev/null +++ b/arch/m68k/include/asm/dma_mm.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | #ifndef _M68K_DMA_H | ||
| 2 | #define _M68K_DMA_H 1 | ||
| 3 | |||
| 4 | |||
| 5 | /* it's useless on the m68k, but unfortunately needed by the new | ||
| 6 | bootmem allocator (but this should do it for this) */ | ||
| 7 | #define MAX_DMA_ADDRESS PAGE_OFFSET | ||
| 8 | |||
| 9 | #define MAX_DMA_CHANNELS 8 | ||
| 10 | |||
| 11 | extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ | ||
| 12 | extern void free_dma(unsigned int dmanr); /* release it again */ | ||
| 13 | |||
| 14 | #define isa_dma_bridge_buggy (0) | ||
| 15 | |||
| 16 | #endif /* _M68K_DMA_H */ | ||
diff --git a/arch/m68k/include/asm/dma_no.h b/arch/m68k/include/asm/dma_no.h new file mode 100644 index 000000000000..939a02056217 --- /dev/null +++ b/arch/m68k/include/asm/dma_no.h | |||
| @@ -0,0 +1,494 @@ | |||
| 1 | #ifndef _M68K_DMA_H | ||
| 2 | #define _M68K_DMA_H 1 | ||
| 3 | |||
| 4 | //#define DMA_DEBUG 1 | ||
| 5 | |||
| 6 | |||
| 7 | #ifdef CONFIG_COLDFIRE | ||
| 8 | /* | ||
| 9 | * ColdFire DMA Model: | ||
| 10 | * ColdFire DMA supports two forms of DMA: Single and Dual address. Single | ||
| 11 | * address mode emits a source address, and expects that the device will either | ||
| 12 | * pick up the data (DMA READ) or source data (DMA WRITE). This implies that | ||
| 13 | * the device will place data on the correct byte(s) of the data bus, as the | ||
| 14 | * memory transactions are always 32 bits. This implies that only 32 bit | ||
| 15 | * devices will find single mode transfers useful. Dual address DMA mode | ||
| 16 | * performs two cycles: source read and destination write. ColdFire will | ||
| 17 | * align the data so that the device will always get the correct bytes, thus | ||
| 18 | * is useful for 8 and 16 bit devices. This is the mode that is supported | ||
| 19 | * below. | ||
| 20 | * | ||
| 21 | * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000 | ||
| 22 | * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) | ||
| 23 | * | ||
| 24 | * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000 | ||
| 25 | * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) | ||
| 26 | * | ||
| 27 | * APR/18/2002 : added proper support for MCF5272 DMA controller. | ||
| 28 | * Arthur Shipkowski (art@videon-central.com) | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <asm/coldfire.h> | ||
| 32 | #include <asm/mcfsim.h> | ||
| 33 | #include <asm/mcfdma.h> | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Set number of channels of DMA on ColdFire for different implementations. | ||
| 37 | */ | ||
| 38 | #if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ | ||
| 39 | defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) | ||
| 40 | #define MAX_M68K_DMA_CHANNELS 4 | ||
| 41 | #elif defined(CONFIG_M5272) | ||
| 42 | #define MAX_M68K_DMA_CHANNELS 1 | ||
| 43 | #elif defined(CONFIG_M532x) | ||
| 44 | #define MAX_M68K_DMA_CHANNELS 0 | ||
| 45 | #else | ||
| 46 | #define MAX_M68K_DMA_CHANNELS 2 | ||
| 47 | #endif | ||
| 48 | |||
| 49 | extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS]; | ||
| 50 | extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS]; | ||
| 51 | |||
| 52 | #if !defined(CONFIG_M5272) | ||
| 53 | #define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */ | ||
| 54 | #define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */ | ||
| 55 | #define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */ | ||
| 56 | #define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */ | ||
| 57 | |||
| 58 | /* I/O to memory, 8 bits, mode */ | ||
| 59 | #define DMA_MODE_READ 0 | ||
| 60 | /* memory to I/O, 8 bits, mode */ | ||
| 61 | #define DMA_MODE_WRITE 1 | ||
| 62 | /* I/O to memory, 16 bits, mode */ | ||
| 63 | #define DMA_MODE_READ_WORD 2 | ||
| 64 | /* memory to I/O, 16 bits, mode */ | ||
| 65 | #define DMA_MODE_WRITE_WORD 3 | ||
| 66 | /* I/O to memory, 32 bits, mode */ | ||
| 67 | #define DMA_MODE_READ_LONG 4 | ||
| 68 | /* memory to I/O, 32 bits, mode */ | ||
| 69 | #define DMA_MODE_WRITE_LONG 5 | ||
| 70 | /* I/O to memory, 8 bits, single-address-mode */ | ||
| 71 | #define DMA_MODE_READ_SINGLE 8 | ||
| 72 | /* memory to I/O, 8 bits, single-address-mode */ | ||
| 73 | #define DMA_MODE_WRITE_SINGLE 9 | ||
| 74 | /* I/O to memory, 16 bits, single-address-mode */ | ||
| 75 | #define DMA_MODE_READ_WORD_SINGLE 10 | ||
| 76 | /* memory to I/O, 16 bits, single-address-mode */ | ||
| 77 | #define DMA_MODE_WRITE_WORD_SINGLE 11 | ||
| 78 | /* I/O to memory, 32 bits, single-address-mode */ | ||
| 79 | #define DMA_MODE_READ_LONG_SINGLE 12 | ||
| 80 | /* memory to I/O, 32 bits, single-address-mode */ | ||
| 81 | #define DMA_MODE_WRITE_LONG_SINGLE 13 | ||
| 82 | |||
| 83 | #else /* CONFIG_M5272 is defined */ | ||
| 84 | |||
| 85 | /* Source static-address mode */ | ||
| 86 | #define DMA_MODE_SRC_SA_BIT 0x01 | ||
| 87 | /* Two bits to select between all four modes */ | ||
| 88 | #define DMA_MODE_SSIZE_MASK 0x06 | ||
| 89 | /* Offset to shift bits in */ | ||
| 90 | #define DMA_MODE_SSIZE_OFF 0x01 | ||
| 91 | /* Destination static-address mode */ | ||
| 92 | #define DMA_MODE_DES_SA_BIT 0x10 | ||
| 93 | /* Two bits to select between all four modes */ | ||
| 94 | #define DMA_MODE_DSIZE_MASK 0x60 | ||
| 95 | /* Offset to shift bits in */ | ||
| 96 | #define DMA_MODE_DSIZE_OFF 0x05 | ||
| 97 | /* Size modifiers */ | ||
| 98 | #define DMA_MODE_SIZE_LONG 0x00 | ||
| 99 | #define DMA_MODE_SIZE_BYTE 0x01 | ||
| 100 | #define DMA_MODE_SIZE_WORD 0x02 | ||
| 101 | #define DMA_MODE_SIZE_LINE 0x03 | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Aliases to help speed quick ports; these may be suboptimal, however. They | ||
| 105 | * do not include the SINGLE mode modifiers since the MCF5272 does not have a | ||
| 106 | * mode where the device is in control of its addressing. | ||
| 107 | */ | ||
| 108 | |||
| 109 | /* I/O to memory, 8 bits, mode */ | ||
| 110 | #define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) | ||
| 111 | /* memory to I/O, 8 bits, mode */ | ||
| 112 | #define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) | ||
| 113 | /* I/O to memory, 16 bits, mode */ | ||
| 114 | #define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) | ||
| 115 | /* memory to I/O, 16 bits, mode */ | ||
| 116 | #define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) | ||
| 117 | /* I/O to memory, 32 bits, mode */ | ||
| 118 | #define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) | ||
| 119 | /* memory to I/O, 32 bits, mode */ | ||
| 120 | #define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) | ||
| 121 | |||
| 122 | #endif /* !defined(CONFIG_M5272) */ | ||
| 123 | |||
| 124 | #if !defined(CONFIG_M5272) | ||
| 125 | /* enable/disable a specific DMA channel */ | ||
| 126 | static __inline__ void enable_dma(unsigned int dmanr) | ||
| 127 | { | ||
| 128 | volatile unsigned short *dmawp; | ||
| 129 | |||
| 130 | #ifdef DMA_DEBUG | ||
| 131 | printk("enable_dma(dmanr=%d)\n", dmanr); | ||
| 132 | #endif | ||
| 133 | |||
| 134 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | ||
| 135 | dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT; | ||
| 136 | } | ||
| 137 | |||
| 138 | static __inline__ void disable_dma(unsigned int dmanr) | ||
| 139 | { | ||
| 140 | volatile unsigned short *dmawp; | ||
| 141 | volatile unsigned char *dmapb; | ||
| 142 | |||
| 143 | #ifdef DMA_DEBUG | ||
| 144 | printk("disable_dma(dmanr=%d)\n", dmanr); | ||
| 145 | #endif | ||
| 146 | |||
| 147 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | ||
| 148 | dmapb = (unsigned char *) dma_base_addr[dmanr]; | ||
| 149 | |||
| 150 | /* Turn off external requests, and stop any DMA in progress */ | ||
| 151 | dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT; | ||
| 152 | dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE; | ||
| 153 | } | ||
| 154 | |||
| 155 | /* | ||
| 156 | * Clear the 'DMA Pointer Flip Flop'. | ||
| 157 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | ||
| 158 | * Use this once to initialize the FF to a known state. | ||
| 159 | * After that, keep track of it. :-) | ||
| 160 | * --- In order to do that, the DMA routines below should --- | ||
| 161 | * --- only be used while interrupts are disabled! --- | ||
| 162 | * | ||
| 163 | * This is a NOP for ColdFire. Provide a stub for compatibility. | ||
| 164 | */ | ||
| 165 | static __inline__ void clear_dma_ff(unsigned int dmanr) | ||
| 166 | { | ||
| 167 | } | ||
| 168 | |||
| 169 | /* set mode (above) for a specific DMA channel */ | ||
| 170 | static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | ||
| 171 | { | ||
| 172 | |||
| 173 | volatile unsigned char *dmabp; | ||
| 174 | volatile unsigned short *dmawp; | ||
| 175 | |||
| 176 | #ifdef DMA_DEBUG | ||
| 177 | printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode); | ||
| 178 | #endif | ||
| 179 | |||
| 180 | dmabp = (unsigned char *) dma_base_addr[dmanr]; | ||
| 181 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | ||
| 182 | |||
| 183 | // Clear config errors | ||
| 184 | dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE; | ||
| 185 | |||
| 186 | // Set command register | ||
| 187 | dmawp[MCFDMA_DCR] = | ||
| 188 | MCFDMA_DCR_INT | // Enable completion irq | ||
| 189 | MCFDMA_DCR_CS | // Force one xfer per request | ||
| 190 | MCFDMA_DCR_AA | // Enable auto alignment | ||
| 191 | // single-address-mode | ||
| 192 | ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) | | ||
| 193 | // sets s_rw (-> r/w) high if Memory to I/0 | ||
| 194 | ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) | | ||
| 195 | // Memory to I/O or I/O to Memory | ||
| 196 | ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) | | ||
| 197 | // 32 bit, 16 bit or 8 bit transfers | ||
| 198 | ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD : | ||
| 199 | ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG : | ||
| 200 | MCFDMA_DCR_SSIZE_BYTE)) | | ||
| 201 | ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD : | ||
| 202 | ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG : | ||
| 203 | MCFDMA_DCR_DSIZE_BYTE)); | ||
| 204 | |||
| 205 | #ifdef DEBUG_DMA | ||
| 206 | printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__, | ||
| 207 | dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR], | ||
| 208 | (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]); | ||
| 209 | #endif | ||
| 210 | } | ||
| 211 | |||
| 212 | /* Set transfer address for specific DMA channel */ | ||
| 213 | static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) | ||
| 214 | { | ||
| 215 | volatile unsigned short *dmawp; | ||
| 216 | volatile unsigned int *dmalp; | ||
| 217 | |||
| 218 | #ifdef DMA_DEBUG | ||
| 219 | printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a); | ||
| 220 | #endif | ||
| 221 | |||
| 222 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | ||
| 223 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | ||
| 224 | |||
| 225 | // Determine which address registers are used for memory/device accesses | ||
| 226 | if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) { | ||
| 227 | // Source incrementing, must be memory | ||
| 228 | dmalp[MCFDMA_SAR] = a; | ||
| 229 | // Set dest address, must be device | ||
| 230 | dmalp[MCFDMA_DAR] = dma_device_address[dmanr]; | ||
| 231 | } else { | ||
| 232 | // Destination incrementing, must be memory | ||
| 233 | dmalp[MCFDMA_DAR] = a; | ||
| 234 | // Set source address, must be device | ||
| 235 | dmalp[MCFDMA_SAR] = dma_device_address[dmanr]; | ||
| 236 | } | ||
| 237 | |||
| 238 | #ifdef DEBUG_DMA | ||
| 239 | printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n", | ||
| 240 | __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR], | ||
| 241 | (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR], | ||
| 242 | (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]); | ||
| 243 | #endif | ||
| 244 | } | ||
| 245 | |||
| 246 | /* | ||
| 247 | * Specific for Coldfire - sets device address. | ||
| 248 | * Should be called after the mode set call, and before set DMA address. | ||
| 249 | */ | ||
| 250 | static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a) | ||
| 251 | { | ||
| 252 | #ifdef DMA_DEBUG | ||
| 253 | printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a); | ||
| 254 | #endif | ||
| 255 | |||
| 256 | dma_device_address[dmanr] = a; | ||
| 257 | } | ||
| 258 | |||
| 259 | /* | ||
| 260 | * NOTE 2: "count" represents _bytes_. | ||
| 261 | */ | ||
| 262 | static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) | ||
| 263 | { | ||
| 264 | volatile unsigned short *dmawp; | ||
| 265 | |||
| 266 | #ifdef DMA_DEBUG | ||
| 267 | printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count); | ||
| 268 | #endif | ||
| 269 | |||
| 270 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | ||
| 271 | dmawp[MCFDMA_BCR] = (unsigned short)count; | ||
| 272 | } | ||
| 273 | |||
| 274 | /* | ||
| 275 | * Get DMA residue count. After a DMA transfer, this | ||
| 276 | * should return zero. Reading this while a DMA transfer is | ||
| 277 | * still in progress will return unpredictable results. | ||
| 278 | * Otherwise, it returns the number of _bytes_ left to transfer. | ||
| 279 | */ | ||
| 280 | static __inline__ int get_dma_residue(unsigned int dmanr) | ||
| 281 | { | ||
| 282 | volatile unsigned short *dmawp; | ||
| 283 | unsigned short count; | ||
| 284 | |||
| 285 | #ifdef DMA_DEBUG | ||
| 286 | printk("get_dma_residue(dmanr=%d)\n", dmanr); | ||
| 287 | #endif | ||
| 288 | |||
| 289 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | ||
| 290 | count = dmawp[MCFDMA_BCR]; | ||
| 291 | return((int) count); | ||
| 292 | } | ||
| 293 | #else /* CONFIG_M5272 is defined */ | ||
| 294 | |||
| 295 | /* | ||
| 296 | * The MCF5272 DMA controller is very different than the controller defined above | ||
| 297 | * in terms of register mapping. For instance, with the exception of the 16-bit | ||
| 298 | * interrupt register (IRQ#85, for reference), all of the registers are 32-bit. | ||
| 299 | * | ||
| 300 | * The big difference, however, is the lack of device-requested DMA. All modes | ||
| 301 | * are dual address transfer, and there is no 'device' setup or direction bit. | ||
| 302 | * You can DMA between a device and memory, between memory and memory, or even between | ||
| 303 | * two devices directly, with any combination of incrementing and non-incrementing | ||
| 304 | * addresses you choose. This puts a crimp in distinguishing between the 'device | ||
| 305 | * address' set up by set_dma_device_addr. | ||
| 306 | * | ||
| 307 | * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr, | ||
| 308 | * which will act exactly as above in -- it will look to see if the source is set to | ||
| 309 | * autoincrement, and if so it will make the source use the set_dma_addr value and the | ||
| 310 | * destination the set_dma_device_addr value. Otherwise the source will be set to the | ||
| 311 | * set_dma_device_addr value and the destination will get the set_dma_addr value. | ||
| 312 | * | ||
| 313 | * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions | ||
| 314 | * and make it explicit. Depending on what you're doing, one of these two should work | ||
| 315 | * for you, but don't mix them in the same transfer setup. | ||
| 316 | */ | ||
| 317 | |||
| 318 | /* enable/disable a specific DMA channel */ | ||
| 319 | static __inline__ void enable_dma(unsigned int dmanr) | ||
| 320 | { | ||
| 321 | volatile unsigned int *dmalp; | ||
| 322 | |||
| 323 | #ifdef DMA_DEBUG | ||
| 324 | printk("enable_dma(dmanr=%d)\n", dmanr); | ||
| 325 | #endif | ||
| 326 | |||
| 327 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | ||
| 328 | dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN; | ||
| 329 | } | ||
| 330 | |||
| 331 | static __inline__ void disable_dma(unsigned int dmanr) | ||
| 332 | { | ||
| 333 | volatile unsigned int *dmalp; | ||
| 334 | |||
| 335 | #ifdef DMA_DEBUG | ||
| 336 | printk("disable_dma(dmanr=%d)\n", dmanr); | ||
| 337 | #endif | ||
| 338 | |||
| 339 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | ||
| 340 | |||
| 341 | /* Turn off external requests, and stop any DMA in progress */ | ||
| 342 | dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN; | ||
| 343 | dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; | ||
| 344 | } | ||
| 345 | |||
| 346 | /* | ||
| 347 | * Clear the 'DMA Pointer Flip Flop'. | ||
| 348 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | ||
| 349 | * Use this once to initialize the FF to a known state. | ||
| 350 | * After that, keep track of it. :-) | ||
| 351 | * --- In order to do that, the DMA routines below should --- | ||
| 352 | * --- only be used while interrupts are disabled! --- | ||
| 353 | * | ||
| 354 | * This is a NOP for ColdFire. Provide a stub for compatibility. | ||
| 355 | */ | ||
| 356 | static __inline__ void clear_dma_ff(unsigned int dmanr) | ||
| 357 | { | ||
| 358 | } | ||
| 359 | |||
| 360 | /* set mode (above) for a specific DMA channel */ | ||
| 361 | static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | ||
| 362 | { | ||
| 363 | |||
| 364 | volatile unsigned int *dmalp; | ||
| 365 | volatile unsigned short *dmawp; | ||
| 366 | |||
| 367 | #ifdef DMA_DEBUG | ||
| 368 | printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode); | ||
| 369 | #endif | ||
| 370 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | ||
| 371 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | ||
| 372 | |||
| 373 | // Clear config errors | ||
| 374 | dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; | ||
| 375 | |||
| 376 | // Set command register | ||
| 377 | dmalp[MCFDMA_DMR] = | ||
| 378 | MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting | ||
| 379 | MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data. | ||
| 380 | MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data. | ||
| 381 | // source static-address-mode | ||
| 382 | ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) | | ||
| 383 | // dest static-address-mode | ||
| 384 | ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) | | ||
| 385 | // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 | ||
| 386 | (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) | | ||
| 387 | (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF); | ||
| 388 | |||
| 389 | dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */ | ||
| 390 | |||
| 391 | #ifdef DEBUG_DMA | ||
| 392 | printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__, | ||
| 393 | dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR], | ||
| 394 | (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]); | ||
| 395 | #endif | ||
| 396 | } | ||
| 397 | |||
| 398 | /* Set transfer address for specific DMA channel */ | ||
| 399 | static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) | ||
| 400 | { | ||
| 401 | volatile unsigned int *dmalp; | ||
| 402 | |||
| 403 | #ifdef DMA_DEBUG | ||
| 404 | printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a); | ||
| 405 | #endif | ||
| 406 | |||
| 407 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | ||
| 408 | |||
| 409 | // Determine which address registers are used for memory/device accesses | ||
| 410 | if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) { | ||
| 411 | // Source incrementing, must be memory | ||
| 412 | dmalp[MCFDMA_DSAR] = a; | ||
| 413 | // Set dest address, must be device | ||
| 414 | dmalp[MCFDMA_DDAR] = dma_device_address[dmanr]; | ||
| 415 | } else { | ||
| 416 | // Destination incrementing, must be memory | ||
| 417 | dmalp[MCFDMA_DDAR] = a; | ||
| 418 | // Set source address, must be device | ||
| 419 | dmalp[MCFDMA_DSAR] = dma_device_address[dmanr]; | ||
| 420 | } | ||
| 421 | |||
| 422 | #ifdef DEBUG_DMA | ||
| 423 | printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n", | ||
| 424 | __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR], | ||
| 425 | (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR], | ||
| 426 | (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]); | ||
| 427 | #endif | ||
| 428 | } | ||
| 429 | |||
| 430 | /* | ||
| 431 | * Specific for Coldfire - sets device address. | ||
| 432 | * Should be called after the mode set call, and before set DMA address. | ||
| 433 | */ | ||
| 434 | static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a) | ||
| 435 | { | ||
| 436 | #ifdef DMA_DEBUG | ||
| 437 | printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a); | ||
| 438 | #endif | ||
| 439 | |||
| 440 | dma_device_address[dmanr] = a; | ||
| 441 | } | ||
| 442 | |||
| 443 | /* | ||
| 444 | * NOTE 2: "count" represents _bytes_. | ||
| 445 | * | ||
| 446 | * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value. | ||
| 447 | */ | ||
| 448 | static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) | ||
| 449 | { | ||
| 450 | volatile unsigned int *dmalp; | ||
| 451 | |||
| 452 | #ifdef DMA_DEBUG | ||
| 453 | printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count); | ||
| 454 | #endif | ||
| 455 | |||
| 456 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | ||
| 457 | dmalp[MCFDMA_DBCR] = count; | ||
| 458 | } | ||
| 459 | |||
| 460 | /* | ||
| 461 | * Get DMA residue count. After a DMA transfer, this | ||
| 462 | * should return zero. Reading this while a DMA transfer is | ||
| 463 | * still in progress will return unpredictable results. | ||
| 464 | * Otherwise, it returns the number of _bytes_ left to transfer. | ||
| 465 | */ | ||
| 466 | static __inline__ int get_dma_residue(unsigned int dmanr) | ||
| 467 | { | ||
| 468 | volatile unsigned int *dmalp; | ||
| 469 | unsigned int count; | ||
| 470 | |||
| 471 | #ifdef DMA_DEBUG | ||
| 472 | printk("get_dma_residue(dmanr=%d)\n", dmanr); | ||
| 473 | #endif | ||
| 474 | |||
| 475 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | ||
| 476 | count = dmalp[MCFDMA_DBCR]; | ||
| 477 | return(count); | ||
| 478 | } | ||
| 479 | |||
| 480 | #endif /* !defined(CONFIG_M5272) */ | ||
| 481 | #endif /* CONFIG_COLDFIRE */ | ||
| 482 | |||
| 483 | #define MAX_DMA_CHANNELS 8 | ||
| 484 | |||
| 485 | /* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any | ||
| 486 | occurrence should be flagged as an error. */ | ||
| 487 | /* under 2.4 it is actually needed by the new bootmem allocator */ | ||
| 488 | #define MAX_DMA_ADDRESS PAGE_OFFSET | ||
| 489 | |||
| 490 | /* These are in kernel/dma.c: */ | ||
| 491 | extern int request_dma(unsigned int dmanr, const char *device_id); /* reserve a DMA channel */ | ||
| 492 | extern void free_dma(unsigned int dmanr); /* release it again */ | ||
| 493 | |||
| 494 | #endif /* _M68K_DMA_H */ | ||
diff --git a/arch/m68k/include/asm/dsp56k.h b/arch/m68k/include/asm/dsp56k.h new file mode 100644 index 000000000000..2d8c0c9f794b --- /dev/null +++ b/arch/m68k/include/asm/dsp56k.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-m68k/dsp56k.h - defines and declarations for | ||
| 3 | * DSP56k device driver | ||
| 4 | * | ||
| 5 | * Copyright (C) 1996,1997 Fredrik Noring, lars brinkhoff & Tomas Berndtsson | ||
| 6 | * | ||
| 7 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 8 | * License. See the file COPYING in the main directory of this archive | ||
| 9 | * for more details. | ||
| 10 | */ | ||
| 11 | |||
| 12 | |||
| 13 | /* Used for uploading DSP binary code */ | ||
| 14 | struct dsp56k_upload { | ||
| 15 | int len; | ||
| 16 | char __user *bin; | ||
| 17 | }; | ||
| 18 | |||
| 19 | /* For the DSP host flags */ | ||
| 20 | struct dsp56k_host_flags { | ||
| 21 | int dir; /* Bit field. 1 = write output bit, 0 = do nothing. | ||
| 22 | * 0x0000 means reading only, 0x0011 means | ||
| 23 | * writing the bits stored in `out' on HF0 and HF1. | ||
| 24 | * Note that HF2 and HF3 can only be read. | ||
| 25 | */ | ||
| 26 | int out; /* Bit field like above. */ | ||
| 27 | int status; /* Host register's current state is returned */ | ||
| 28 | }; | ||
| 29 | |||
| 30 | /* ioctl command codes */ | ||
| 31 | #define DSP56K_UPLOAD 1 /* Upload DSP binary program */ | ||
| 32 | #define DSP56K_SET_TX_WSIZE 2 /* Host transmit word size (1-4) */ | ||
| 33 | #define DSP56K_SET_RX_WSIZE 3 /* Host receive word size (1-4) */ | ||
| 34 | #define DSP56K_HOST_FLAGS 4 /* Host flag registers */ | ||
| 35 | #define DSP56K_HOST_CMD 5 /* Trig Host Command (0-31) */ | ||
diff --git a/arch/m68k/include/asm/dvma.h b/arch/m68k/include/asm/dvma.h new file mode 100644 index 000000000000..890bbf7e7758 --- /dev/null +++ b/arch/m68k/include/asm/dvma.h | |||
| @@ -0,0 +1,240 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68k/dma.h | ||
| 3 | * | ||
| 4 | * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu) | ||
| 5 | * | ||
| 6 | * Hacked to fit Sun3x needs by Thomas Bogendoerfer | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __M68K_DVMA_H | ||
| 10 | #define __M68K_DVMA_H | ||
| 11 | |||
| 12 | |||
| 13 | #define DVMA_PAGE_SHIFT 13 | ||
| 14 | #define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT) | ||
| 15 | #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1)) | ||
| 16 | #define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE) | ||
| 17 | |||
| 18 | extern void dvma_init(void); | ||
| 19 | extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr, | ||
| 20 | int len); | ||
| 21 | |||
| 22 | #define dvma_malloc(x) dvma_malloc_align(x, 0) | ||
| 23 | #define dvma_map(x, y) dvma_map_align(x, y, 0) | ||
| 24 | #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff) | ||
| 25 | #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff) | ||
| 26 | extern unsigned long dvma_map_align(unsigned long kaddr, int len, | ||
| 27 | int align); | ||
| 28 | extern void *dvma_malloc_align(unsigned long len, unsigned long align); | ||
| 29 | |||
| 30 | extern void dvma_unmap(void *baddr); | ||
| 31 | extern void dvma_free(void *vaddr); | ||
| 32 | |||
| 33 | |||
| 34 | #ifdef CONFIG_SUN3 | ||
| 35 | /* sun3 dvma page support */ | ||
| 36 | |||
| 37 | /* memory and pmegs potentially reserved for dvma */ | ||
| 38 | #define DVMA_PMEG_START 10 | ||
| 39 | #define DVMA_PMEG_END 16 | ||
| 40 | #define DVMA_START 0xf00000 | ||
| 41 | #define DVMA_END 0xfe0000 | ||
| 42 | #define DVMA_SIZE (DVMA_END-DVMA_START) | ||
| 43 | #define IOMMU_TOTAL_ENTRIES 128 | ||
| 44 | #define IOMMU_ENTRIES 120 | ||
| 45 | |||
| 46 | /* empirical kludge -- dvma regions only seem to work right on 0x10000 | ||
| 47 | byte boundaries */ | ||
| 48 | #define DVMA_REGION_SIZE 0x10000 | ||
| 49 | #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \ | ||
| 50 | ~(DVMA_REGION_SIZE-1)) | ||
| 51 | |||
| 52 | /* virt <-> phys conversions */ | ||
| 53 | #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff) | ||
| 54 | #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000) | ||
| 55 | #define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff) | ||
| 56 | #define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000) | ||
| 57 | #define dvma_vtob(x) dvma_vtop(x) | ||
| 58 | #define dvma_btov(x) dvma_ptov(x) | ||
| 59 | |||
| 60 | static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, | ||
| 61 | int len) | ||
| 62 | { | ||
| 63 | return 0; | ||
| 64 | } | ||
| 65 | |||
| 66 | #else /* Sun3x */ | ||
| 67 | |||
| 68 | /* sun3x dvma page support */ | ||
| 69 | |||
| 70 | #define DVMA_START 0x0 | ||
| 71 | #define DVMA_END 0xf00000 | ||
| 72 | #define DVMA_SIZE (DVMA_END-DVMA_START) | ||
| 73 | #define IOMMU_TOTAL_ENTRIES 2048 | ||
| 74 | /* the prom takes the top meg */ | ||
| 75 | #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80) | ||
| 76 | |||
| 77 | #define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff) | ||
| 78 | #define dvma_btov(x) ((unsigned long)(x) | 0xff000000) | ||
| 79 | |||
| 80 | extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len); | ||
| 81 | |||
| 82 | |||
| 83 | |||
| 84 | /* everything below this line is specific to dma used for the onboard | ||
| 85 | ESP scsi on sun3x */ | ||
| 86 | |||
| 87 | /* Structure to describe the current status of DMA registers on the Sparc */ | ||
| 88 | struct sparc_dma_registers { | ||
| 89 | __volatile__ unsigned long cond_reg; /* DMA condition register */ | ||
| 90 | __volatile__ unsigned long st_addr; /* Start address of this transfer */ | ||
| 91 | __volatile__ unsigned long cnt; /* How many bytes to transfer */ | ||
| 92 | __volatile__ unsigned long dma_test; /* DMA test register */ | ||
| 93 | }; | ||
| 94 | |||
| 95 | /* DVMA chip revisions */ | ||
| 96 | enum dvma_rev { | ||
| 97 | dvmarev0, | ||
| 98 | dvmaesc1, | ||
| 99 | dvmarev1, | ||
| 100 | dvmarev2, | ||
| 101 | dvmarev3, | ||
| 102 | dvmarevplus, | ||
| 103 | dvmahme | ||
| 104 | }; | ||
| 105 | |||
| 106 | #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) | ||
| 107 | |||
| 108 | /* Linux DMA information structure, filled during probe. */ | ||
| 109 | struct Linux_SBus_DMA { | ||
| 110 | struct Linux_SBus_DMA *next; | ||
| 111 | struct linux_sbus_device *SBus_dev; | ||
| 112 | struct sparc_dma_registers *regs; | ||
| 113 | |||
| 114 | /* Status, misc info */ | ||
| 115 | int node; /* Prom node for this DMA device */ | ||
| 116 | int running; /* Are we doing DMA now? */ | ||
| 117 | int allocated; /* Are we "owned" by anyone yet? */ | ||
| 118 | |||
| 119 | /* Transfer information. */ | ||
| 120 | unsigned long addr; /* Start address of current transfer */ | ||
| 121 | int nbytes; /* Size of current transfer */ | ||
| 122 | int realbytes; /* For splitting up large transfers, etc. */ | ||
| 123 | |||
| 124 | /* DMA revision */ | ||
| 125 | enum dvma_rev revision; | ||
| 126 | }; | ||
| 127 | |||
| 128 | extern struct Linux_SBus_DMA *dma_chain; | ||
| 129 | |||
| 130 | /* Broken hardware... */ | ||
| 131 | #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1) | ||
| 132 | #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) | ||
| 133 | |||
| 134 | /* Fields in the cond_reg register */ | ||
| 135 | /* First, the version identification bits */ | ||
| 136 | #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ | ||
| 137 | #define DMA_VERS0 0x00000000 /* Sunray DMA version */ | ||
| 138 | #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ | ||
| 139 | #define DMA_VERS1 0x80000000 /* DMA rev 1 */ | ||
| 140 | #define DMA_VERS2 0xa0000000 /* DMA rev 2 */ | ||
| 141 | #define DMA_VERHME 0xb0000000 /* DMA hme gate array */ | ||
| 142 | #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ | ||
| 143 | |||
| 144 | #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ | ||
| 145 | #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ | ||
| 146 | #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ | ||
| 147 | #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ | ||
| 148 | #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ | ||
| 149 | #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ | ||
| 150 | #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ | ||
| 151 | #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ | ||
| 152 | #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ | ||
| 153 | #define DMA_ST_WRITE 0x00000100 /* write from device to memory */ | ||
| 154 | #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ | ||
| 155 | #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ | ||
| 156 | #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ | ||
| 157 | #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ | ||
| 158 | #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ | ||
| 159 | #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ | ||
| 160 | #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ | ||
| 161 | #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ | ||
| 162 | #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ | ||
| 163 | #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ | ||
| 164 | #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ | ||
| 165 | #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */ | ||
| 166 | #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ | ||
| 167 | #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ | ||
| 168 | #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */ | ||
| 169 | #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */ | ||
| 170 | #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ | ||
| 171 | #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ | ||
| 172 | #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ | ||
| 173 | #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ | ||
| 174 | #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ | ||
| 175 | #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ | ||
| 176 | #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ | ||
| 177 | #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ | ||
| 178 | #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ | ||
| 179 | #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ | ||
| 180 | #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ | ||
| 181 | |||
| 182 | /* Values describing the burst-size property from the PROM */ | ||
| 183 | #define DMA_BURST1 0x01 | ||
| 184 | #define DMA_BURST2 0x02 | ||
| 185 | #define DMA_BURST4 0x04 | ||
| 186 | #define DMA_BURST8 0x08 | ||
| 187 | #define DMA_BURST16 0x10 | ||
| 188 | #define DMA_BURST32 0x20 | ||
| 189 | #define DMA_BURST64 0x40 | ||
| 190 | #define DMA_BURSTBITS 0x7f | ||
| 191 | |||
| 192 | /* Determine highest possible final transfer address given a base */ | ||
| 193 | #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) | ||
| 194 | |||
| 195 | /* Yes, I hack a lot of elisp in my spare time... */ | ||
| 196 | #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR)) | ||
| 197 | #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))) | ||
| 198 | #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE)) | ||
| 199 | #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE))) | ||
| 200 | #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB))) | ||
| 201 | #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB))) | ||
| 202 | #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV)) | ||
| 203 | #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr)) | ||
| 204 | #define DMA_BEGINDMA_W(regs) \ | ||
| 205 | ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB)))) | ||
| 206 | #define DMA_BEGINDMA_R(regs) \ | ||
| 207 | ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE))))) | ||
| 208 | |||
| 209 | /* For certain DMA chips, we need to disable ints upon irq entry | ||
| 210 | * and turn them back on when we are done. So in any ESP interrupt | ||
| 211 | * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT | ||
| 212 | * when leaving the handler. You have been warned... | ||
| 213 | */ | ||
| 214 | #define DMA_IRQ_ENTRY(dma, dregs) do { \ | ||
| 215 | if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ | ||
| 216 | } while (0) | ||
| 217 | |||
| 218 | #define DMA_IRQ_EXIT(dma, dregs) do { \ | ||
| 219 | if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ | ||
| 220 | } while(0) | ||
| 221 | |||
| 222 | /* Reset the friggin' thing... */ | ||
| 223 | #define DMA_RESET(dma) do { \ | ||
| 224 | struct sparc_dma_registers *regs = dma->regs; \ | ||
| 225 | /* Let the current FIFO drain itself */ \ | ||
| 226 | sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \ | ||
| 227 | /* Reset the logic */ \ | ||
| 228 | regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \ | ||
| 229 | __delay(400); /* let the bits set ;) */ \ | ||
| 230 | regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \ | ||
| 231 | sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \ | ||
| 232 | /* Enable FAST transfers if available */ \ | ||
| 233 | if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \ | ||
| 234 | dma->running = 0; \ | ||
| 235 | } while(0) | ||
| 236 | |||
| 237 | |||
| 238 | #endif /* !CONFIG_SUN3 */ | ||
| 239 | |||
| 240 | #endif /* !(__M68K_DVMA_H) */ | ||
diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h new file mode 100644 index 000000000000..04ce488bc63f --- /dev/null +++ b/arch/m68k/include/asm/elf.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "elf_no.h" | ||
| 3 | #else | ||
| 4 | #include "elf_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/elf_mm.h b/arch/m68k/include/asm/elf_mm.h new file mode 100644 index 000000000000..0b0f49eb876b --- /dev/null +++ b/arch/m68k/include/asm/elf_mm.h | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | #ifndef __ASMm68k_ELF_H | ||
| 2 | #define __ASMm68k_ELF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * ELF register definitions.. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <asm/ptrace.h> | ||
| 9 | #include <asm/user.h> | ||
| 10 | |||
| 11 | /* | ||
| 12 | * 68k ELF relocation types | ||
| 13 | */ | ||
| 14 | #define R_68K_NONE 0 | ||
| 15 | #define R_68K_32 1 | ||
| 16 | #define R_68K_16 2 | ||
| 17 | #define R_68K_8 3 | ||
| 18 | #define R_68K_PC32 4 | ||
| 19 | #define R_68K_PC16 5 | ||
| 20 | #define R_68K_PC8 6 | ||
| 21 | #define R_68K_GOT32 7 | ||
| 22 | #define R_68K_GOT16 8 | ||
| 23 | #define R_68K_GOT8 9 | ||
| 24 | #define R_68K_GOT32O 10 | ||
| 25 | #define R_68K_GOT16O 11 | ||
| 26 | #define R_68K_GOT8O 12 | ||
| 27 | #define R_68K_PLT32 13 | ||
| 28 | #define R_68K_PLT16 14 | ||
| 29 | #define R_68K_PLT8 15 | ||
| 30 | #define R_68K_PLT32O 16 | ||
| 31 | #define R_68K_PLT16O 17 | ||
| 32 | #define R_68K_PLT8O 18 | ||
| 33 | #define R_68K_COPY 19 | ||
| 34 | #define R_68K_GLOB_DAT 20 | ||
| 35 | #define R_68K_JMP_SLOT 21 | ||
| 36 | #define R_68K_RELATIVE 22 | ||
| 37 | |||
| 38 | typedef unsigned long elf_greg_t; | ||
| 39 | |||
| 40 | #define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) | ||
| 41 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | ||
| 42 | |||
| 43 | typedef struct user_m68kfp_struct elf_fpregset_t; | ||
| 44 | |||
| 45 | /* | ||
| 46 | * This is used to ensure we don't load something for the wrong architecture. | ||
| 47 | */ | ||
| 48 | #define elf_check_arch(x) ((x)->e_machine == EM_68K) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * These are used to set parameters in the core dumps. | ||
| 52 | */ | ||
| 53 | #define ELF_CLASS ELFCLASS32 | ||
| 54 | #define ELF_DATA ELFDATA2MSB | ||
| 55 | #define ELF_ARCH EM_68K | ||
| 56 | |||
| 57 | /* For SVR4/m68k the function pointer to be registered with `atexit' is | ||
| 58 | passed in %a1. Although my copy of the ABI has no such statement, it | ||
| 59 | is actually used on ASV. */ | ||
| 60 | #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 | ||
| 61 | |||
| 62 | #define USE_ELF_CORE_DUMP | ||
| 63 | #ifndef CONFIG_SUN3 | ||
| 64 | #define ELF_EXEC_PAGESIZE 4096 | ||
| 65 | #else | ||
| 66 | #define ELF_EXEC_PAGESIZE 8192 | ||
| 67 | #endif | ||
| 68 | |||
| 69 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | ||
| 70 | use of this is to invoke "./ld.so someprog" to test out a new version of | ||
| 71 | the loader. We need to make sure that it is out of the way of the program | ||
| 72 | that it will "exec", and that there is sufficient room for the brk. */ | ||
| 73 | |||
| 74 | #ifndef CONFIG_SUN3 | ||
| 75 | #define ELF_ET_DYN_BASE 0xD0000000UL | ||
| 76 | #else | ||
| 77 | #define ELF_ET_DYN_BASE 0x0D800000UL | ||
| 78 | #endif | ||
| 79 | |||
| 80 | #define ELF_CORE_COPY_REGS(pr_reg, regs) \ | ||
| 81 | /* Bleech. */ \ | ||
| 82 | pr_reg[0] = regs->d1; \ | ||
| 83 | pr_reg[1] = regs->d2; \ | ||
| 84 | pr_reg[2] = regs->d3; \ | ||
| 85 | pr_reg[3] = regs->d4; \ | ||
| 86 | pr_reg[4] = regs->d5; \ | ||
| 87 | pr_reg[7] = regs->a0; \ | ||
| 88 | pr_reg[8] = regs->a1; \ | ||
| 89 | pr_reg[9] = regs->a2; \ | ||
| 90 | pr_reg[14] = regs->d0; \ | ||
| 91 | pr_reg[15] = rdusp(); \ | ||
| 92 | pr_reg[16] = regs->orig_d0; \ | ||
| 93 | pr_reg[17] = regs->sr; \ | ||
| 94 | pr_reg[18] = regs->pc; \ | ||
| 95 | pr_reg[19] = (regs->format << 12) | regs->vector; \ | ||
| 96 | { \ | ||
| 97 | struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \ | ||
| 98 | pr_reg[5] = sw->d6; \ | ||
| 99 | pr_reg[6] = sw->d7; \ | ||
| 100 | pr_reg[10] = sw->a3; \ | ||
| 101 | pr_reg[11] = sw->a4; \ | ||
| 102 | pr_reg[12] = sw->a5; \ | ||
| 103 | pr_reg[13] = sw->a6; \ | ||
| 104 | } | ||
| 105 | |||
| 106 | /* This yields a mask that user programs can use to figure out what | ||
| 107 | instruction set this cpu supports. */ | ||
| 108 | |||
| 109 | #define ELF_HWCAP (0) | ||
| 110 | |||
| 111 | /* This yields a string that ld.so will use to load implementation | ||
| 112 | specific libraries for optimization. This is more specific in | ||
| 113 | intent than poking at uname or /proc/cpuinfo. */ | ||
| 114 | |||
| 115 | #define ELF_PLATFORM (NULL) | ||
| 116 | |||
| 117 | #define SET_PERSONALITY(ex) set_personality(PER_LINUX) | ||
| 118 | |||
| 119 | #endif | ||
diff --git a/arch/m68k/include/asm/elf_no.h b/arch/m68k/include/asm/elf_no.h new file mode 100644 index 000000000000..b8046837f384 --- /dev/null +++ b/arch/m68k/include/asm/elf_no.h | |||
| @@ -0,0 +1,110 @@ | |||
| 1 | #ifndef __ASMm68k_ELF_H | ||
| 2 | #define __ASMm68k_ELF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * ELF register definitions.. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <asm/ptrace.h> | ||
| 9 | #include <asm/user.h> | ||
| 10 | |||
| 11 | /* | ||
| 12 | * 68k ELF relocation types | ||
| 13 | */ | ||
| 14 | #define R_68K_NONE 0 | ||
| 15 | #define R_68K_32 1 | ||
| 16 | #define R_68K_16 2 | ||
| 17 | #define R_68K_8 3 | ||
| 18 | #define R_68K_PC32 4 | ||
| 19 | #define R_68K_PC16 5 | ||
| 20 | #define R_68K_PC8 6 | ||
| 21 | #define R_68K_GOT32 7 | ||
| 22 | #define R_68K_GOT16 8 | ||
| 23 | #define R_68K_GOT8 9 | ||
| 24 | #define R_68K_GOT32O 10 | ||
| 25 | #define R_68K_GOT16O 11 | ||
| 26 | #define R_68K_GOT8O 12 | ||
| 27 | #define R_68K_PLT32 13 | ||
| 28 | #define R_68K_PLT16 14 | ||
| 29 | #define R_68K_PLT8 15 | ||
| 30 | #define R_68K_PLT32O 16 | ||
| 31 | #define R_68K_PLT16O 17 | ||
| 32 | #define R_68K_PLT8O 18 | ||
| 33 | #define R_68K_COPY 19 | ||
| 34 | #define R_68K_GLOB_DAT 20 | ||
| 35 | #define R_68K_JMP_SLOT 21 | ||
| 36 | #define R_68K_RELATIVE 22 | ||
| 37 | |||
| 38 | typedef unsigned long elf_greg_t; | ||
| 39 | |||
| 40 | #define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) | ||
| 41 | typedef elf_greg_t elf_gregset_t[ELF_NGREG]; | ||
| 42 | |||
| 43 | typedef struct user_m68kfp_struct elf_fpregset_t; | ||
| 44 | |||
| 45 | /* | ||
| 46 | * This is used to ensure we don't load something for the wrong architecture. | ||
| 47 | */ | ||
| 48 | #define elf_check_arch(x) ((x)->e_machine == EM_68K) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * These are used to set parameters in the core dumps. | ||
| 52 | */ | ||
| 53 | #define ELF_CLASS ELFCLASS32 | ||
| 54 | #define ELF_DATA ELFDATA2MSB | ||
| 55 | #define ELF_ARCH EM_68K | ||
| 56 | |||
| 57 | /* For SVR4/m68k the function pointer to be registered with `atexit' is | ||
| 58 | passed in %a1. Although my copy of the ABI has no such statement, it | ||
| 59 | is actually used on ASV. */ | ||
| 60 | #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 | ||
| 61 | |||
| 62 | #define USE_ELF_CORE_DUMP | ||
| 63 | #define ELF_EXEC_PAGESIZE 4096 | ||
| 64 | |||
| 65 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | ||
| 66 | use of this is to invoke "./ld.so someprog" to test out a new version of | ||
| 67 | the loader. We need to make sure that it is out of the way of the program | ||
| 68 | that it will "exec", and that there is sufficient room for the brk. */ | ||
| 69 | |||
| 70 | #define ELF_ET_DYN_BASE 0xD0000000UL | ||
| 71 | |||
| 72 | #define ELF_CORE_COPY_REGS(pr_reg, regs) \ | ||
| 73 | /* Bleech. */ \ | ||
| 74 | pr_reg[0] = regs->d1; \ | ||
| 75 | pr_reg[1] = regs->d2; \ | ||
| 76 | pr_reg[2] = regs->d3; \ | ||
| 77 | pr_reg[3] = regs->d4; \ | ||
| 78 | pr_reg[4] = regs->d5; \ | ||
| 79 | pr_reg[7] = regs->a0; \ | ||
| 80 | pr_reg[8] = regs->a1; \ | ||
| 81 | pr_reg[14] = regs->d0; \ | ||
| 82 | pr_reg[15] = rdusp(); \ | ||
| 83 | pr_reg[16] = 0 /* regs->orig_d0 */; \ | ||
| 84 | pr_reg[17] = regs->sr; \ | ||
| 85 | pr_reg[18] = regs->pc; \ | ||
| 86 | /* pr_reg[19] = (regs->format << 12) | regs->vector; */ \ | ||
| 87 | { \ | ||
| 88 | struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \ | ||
| 89 | pr_reg[5] = sw->d6; \ | ||
| 90 | pr_reg[6] = sw->d7; \ | ||
| 91 | pr_reg[10] = sw->a3; \ | ||
| 92 | pr_reg[11] = sw->a4; \ | ||
| 93 | pr_reg[12] = sw->a5; \ | ||
| 94 | pr_reg[13] = sw->a6; \ | ||
| 95 | } | ||
| 96 | |||
| 97 | /* This yields a mask that user programs can use to figure out what | ||
| 98 | instruction set this cpu supports. */ | ||
| 99 | |||
| 100 | #define ELF_HWCAP (0) | ||
| 101 | |||
| 102 | /* This yields a string that ld.so will use to load implementation | ||
| 103 | specific libraries for optimization. This is more specific in | ||
| 104 | intent than poking at uname or /proc/cpuinfo. */ | ||
| 105 | |||
| 106 | #define ELF_PLATFORM (NULL) | ||
| 107 | |||
| 108 | #define SET_PERSONALITY(ex) set_personality(PER_LINUX) | ||
| 109 | |||
| 110 | #endif | ||
diff --git a/arch/m68k/include/asm/elia.h b/arch/m68k/include/asm/elia.h new file mode 100644 index 000000000000..e037d4e2de33 --- /dev/null +++ b/arch/m68k/include/asm/elia.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * elia.h -- Lineo (formerly Moreton Bay) eLIA platform support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au) | ||
| 7 | * (C) Copyright 1999-2000, Lineo (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef elia_h | ||
| 12 | #define elia_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | #include <asm/coldfire.h> | ||
| 16 | |||
| 17 | #ifdef CONFIG_eLIA | ||
| 18 | |||
| 19 | /* | ||
| 20 | * The serial port DTR and DCD lines are also on the Parallel I/O | ||
| 21 | * as well, so define those too. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #define eLIA_DCD1 0x0001 | ||
| 25 | #define eLIA_DCD0 0x0002 | ||
| 26 | #define eLIA_DTR1 0x0004 | ||
| 27 | #define eLIA_DTR0 0x0008 | ||
| 28 | |||
| 29 | #define eLIA_PCIRESET 0x0020 | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Kernel macros to set and unset the LEDs. | ||
| 33 | */ | ||
| 34 | #ifndef __ASSEMBLY__ | ||
| 35 | extern unsigned short ppdata; | ||
| 36 | #endif /* __ASSEMBLY__ */ | ||
| 37 | |||
| 38 | #endif /* CONFIG_eLIA */ | ||
| 39 | |||
| 40 | /****************************************************************************/ | ||
| 41 | #endif /* elia_h */ | ||
diff --git a/arch/m68k/include/asm/emergency-restart.h b/arch/m68k/include/asm/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/arch/m68k/include/asm/emergency-restart.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_EMERGENCY_RESTART_H | ||
| 2 | #define _ASM_EMERGENCY_RESTART_H | ||
| 3 | |||
| 4 | #include <asm-generic/emergency-restart.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_EMERGENCY_RESTART_H */ | ||
diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h new file mode 100644 index 000000000000..876eec6f2b52 --- /dev/null +++ b/arch/m68k/include/asm/entry.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "entry_no.h" | ||
| 3 | #else | ||
| 4 | #include "entry_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/entry_mm.h b/arch/m68k/include/asm/entry_mm.h new file mode 100644 index 000000000000..5202f5a5b420 --- /dev/null +++ b/arch/m68k/include/asm/entry_mm.h | |||
| @@ -0,0 +1,137 @@ | |||
| 1 | #ifndef __M68K_ENTRY_H | ||
| 2 | #define __M68K_ENTRY_H | ||
| 3 | |||
| 4 | #include <asm/setup.h> | ||
| 5 | #include <asm/page.h> | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Stack layout in 'ret_from_exception': | ||
| 9 | * | ||
| 10 | * This allows access to the syscall arguments in registers d1-d5 | ||
| 11 | * | ||
| 12 | * 0(sp) - d1 | ||
| 13 | * 4(sp) - d2 | ||
| 14 | * 8(sp) - d3 | ||
| 15 | * C(sp) - d4 | ||
| 16 | * 10(sp) - d5 | ||
| 17 | * 14(sp) - a0 | ||
| 18 | * 18(sp) - a1 | ||
| 19 | * 1C(sp) - a2 | ||
| 20 | * 20(sp) - d0 | ||
| 21 | * 24(sp) - orig_d0 | ||
| 22 | * 28(sp) - stack adjustment | ||
| 23 | * 2C(sp) - sr | ||
| 24 | * 2E(sp) - pc | ||
| 25 | * 32(sp) - format & vector | ||
| 26 | */ | ||
| 27 | |||
| 28 | /* | ||
| 29 | * 97/05/14 Andreas: Register %a2 is now set to the current task throughout | ||
| 30 | * the whole kernel. | ||
| 31 | */ | ||
| 32 | |||
| 33 | /* the following macro is used when enabling interrupts */ | ||
| 34 | #if defined(MACH_ATARI_ONLY) | ||
| 35 | /* block out HSYNC on the atari */ | ||
| 36 | #define ALLOWINT (~0x400) | ||
| 37 | #define MAX_NOINT_IPL 3 | ||
| 38 | #else | ||
| 39 | /* portable version */ | ||
| 40 | #define ALLOWINT (~0x700) | ||
| 41 | #define MAX_NOINT_IPL 0 | ||
| 42 | #endif /* machine compilation types */ | ||
| 43 | |||
| 44 | #ifdef __ASSEMBLY__ | ||
| 45 | |||
| 46 | #define curptr a2 | ||
| 47 | |||
| 48 | LFLUSH_I_AND_D = 0x00000808 | ||
| 49 | LSIGTRAP = 5 | ||
| 50 | |||
| 51 | /* process bits for task_struct.ptrace */ | ||
| 52 | PT_TRACESYS_OFF = 3 | ||
| 53 | PT_TRACESYS_BIT = 1 | ||
| 54 | PT_PTRACED_OFF = 3 | ||
| 55 | PT_PTRACED_BIT = 0 | ||
| 56 | PT_DTRACE_OFF = 3 | ||
| 57 | PT_DTRACE_BIT = 2 | ||
| 58 | |||
| 59 | #define SAVE_ALL_INT save_all_int | ||
| 60 | #define SAVE_ALL_SYS save_all_sys | ||
| 61 | #define RESTORE_ALL restore_all | ||
| 62 | /* | ||
| 63 | * This defines the normal kernel pt-regs layout. | ||
| 64 | * | ||
| 65 | * regs a3-a6 and d6-d7 are preserved by C code | ||
| 66 | * the kernel doesn't mess with usp unless it needs to | ||
| 67 | */ | ||
| 68 | |||
| 69 | /* | ||
| 70 | * a -1 in the orig_d0 field signifies | ||
| 71 | * that the stack frame is NOT for syscall | ||
| 72 | */ | ||
| 73 | .macro save_all_int | ||
| 74 | clrl %sp@- | stk_adj | ||
| 75 | pea -1:w | orig d0 | ||
| 76 | movel %d0,%sp@- | d0 | ||
| 77 | moveml %d1-%d5/%a0-%a1/%curptr,%sp@- | ||
| 78 | .endm | ||
| 79 | |||
| 80 | .macro save_all_sys | ||
| 81 | clrl %sp@- | stk_adj | ||
| 82 | movel %d0,%sp@- | orig d0 | ||
| 83 | movel %d0,%sp@- | d0 | ||
| 84 | moveml %d1-%d5/%a0-%a1/%curptr,%sp@- | ||
| 85 | .endm | ||
| 86 | |||
| 87 | .macro restore_all | ||
| 88 | moveml %sp@+,%a0-%a1/%curptr/%d1-%d5 | ||
| 89 | movel %sp@+,%d0 | ||
| 90 | addql #4,%sp | orig d0 | ||
| 91 | addl %sp@+,%sp | stk adj | ||
| 92 | rte | ||
| 93 | .endm | ||
| 94 | |||
| 95 | #define SWITCH_STACK_SIZE (6*4+4) /* includes return address */ | ||
| 96 | |||
| 97 | #define SAVE_SWITCH_STACK save_switch_stack | ||
| 98 | #define RESTORE_SWITCH_STACK restore_switch_stack | ||
| 99 | #define GET_CURRENT(tmp) get_current tmp | ||
| 100 | |||
| 101 | .macro save_switch_stack | ||
| 102 | moveml %a3-%a6/%d6-%d7,%sp@- | ||
| 103 | .endm | ||
| 104 | |||
| 105 | .macro restore_switch_stack | ||
| 106 | moveml %sp@+,%a3-%a6/%d6-%d7 | ||
| 107 | .endm | ||
| 108 | |||
| 109 | .macro get_current reg=%d0 | ||
| 110 | movel %sp,\reg | ||
| 111 | andw #-THREAD_SIZE,\reg | ||
| 112 | movel \reg,%curptr | ||
| 113 | movel %curptr@,%curptr | ||
| 114 | .endm | ||
| 115 | |||
| 116 | #else /* C source */ | ||
| 117 | |||
| 118 | #define STR(X) STR1(X) | ||
| 119 | #define STR1(X) #X | ||
| 120 | |||
| 121 | #define PT_OFF_ORIG_D0 0x24 | ||
| 122 | #define PT_OFF_FORMATVEC 0x32 | ||
| 123 | #define PT_OFF_SR 0x2C | ||
| 124 | #define SAVE_ALL_INT \ | ||
| 125 | "clrl %%sp@-;" /* stk_adj */ \ | ||
| 126 | "pea -1:w;" /* orig d0 = -1 */ \ | ||
| 127 | "movel %%d0,%%sp@-;" /* d0 */ \ | ||
| 128 | "moveml %%d1-%%d5/%%a0-%%a2,%%sp@-" | ||
| 129 | #define GET_CURRENT(tmp) \ | ||
| 130 | "movel %%sp,"#tmp"\n\t" \ | ||
| 131 | "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \ | ||
| 132 | "movel "#tmp",%%a2\n\t" \ | ||
| 133 | "movel %%a2@,%%a2" | ||
| 134 | |||
| 135 | #endif | ||
| 136 | |||
| 137 | #endif /* __M68K_ENTRY_H */ | ||
diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h new file mode 100644 index 000000000000..c2553d26273d --- /dev/null +++ b/arch/m68k/include/asm/entry_no.h | |||
| @@ -0,0 +1,182 @@ | |||
| 1 | #ifndef __M68KNOMMU_ENTRY_H | ||
| 2 | #define __M68KNOMMU_ENTRY_H | ||
| 3 | |||
| 4 | #include <asm/setup.h> | ||
| 5 | #include <asm/page.h> | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Stack layout in 'ret_from_exception': | ||
| 9 | * | ||
| 10 | * This allows access to the syscall arguments in registers d1-d5 | ||
| 11 | * | ||
| 12 | * 0(sp) - d1 | ||
| 13 | * 4(sp) - d2 | ||
| 14 | * 8(sp) - d3 | ||
| 15 | * C(sp) - d4 | ||
| 16 | * 10(sp) - d5 | ||
| 17 | * 14(sp) - a0 | ||
| 18 | * 18(sp) - a1 | ||
| 19 | * 1C(sp) - a2 | ||
| 20 | * 20(sp) - d0 | ||
| 21 | * 24(sp) - orig_d0 | ||
| 22 | * 28(sp) - stack adjustment | ||
| 23 | * 2C(sp) - [ sr ] [ format & vector ] | ||
| 24 | * 2E(sp) - [ pc-hiword ] [ sr ] | ||
| 25 | * 30(sp) - [ pc-loword ] [ pc-hiword ] | ||
| 26 | * 32(sp) - [ format & vector ] [ pc-loword ] | ||
| 27 | * ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^ | ||
| 28 | * M68K COLDFIRE | ||
| 29 | */ | ||
| 30 | |||
| 31 | #define ALLOWINT 0xf8ff | ||
| 32 | |||
| 33 | #ifdef __ASSEMBLY__ | ||
| 34 | |||
| 35 | /* process bits for task_struct.flags */ | ||
| 36 | PF_TRACESYS_OFF = 3 | ||
| 37 | PF_TRACESYS_BIT = 5 | ||
| 38 | PF_PTRACED_OFF = 3 | ||
| 39 | PF_PTRACED_BIT = 4 | ||
| 40 | PF_DTRACE_OFF = 1 | ||
| 41 | PF_DTRACE_BIT = 5 | ||
| 42 | |||
| 43 | LENOSYS = 38 | ||
| 44 | |||
| 45 | #define SWITCH_STACK_SIZE (6*4+4) /* Includes return address */ | ||
| 46 | |||
| 47 | /* | ||
| 48 | * This defines the normal kernel pt-regs layout. | ||
| 49 | * | ||
| 50 | * regs are a2-a6 and d6-d7 preserved by C code | ||
| 51 | * the kernel doesn't mess with usp unless it needs to | ||
| 52 | */ | ||
| 53 | |||
| 54 | #ifdef CONFIG_COLDFIRE | ||
| 55 | /* | ||
| 56 | * This is made a little more tricky on the ColdFire. There is no | ||
| 57 | * separate kernel and user stack pointers. Need to artificially | ||
| 58 | * construct a usp in software... When doing this we need to disable | ||
| 59 | * interrupts, otherwise bad things could happen. | ||
| 60 | */ | ||
| 61 | .macro SAVE_ALL | ||
| 62 | move #0x2700,%sr /* disable intrs */ | ||
| 63 | btst #5,%sp@(2) /* from user? */ | ||
| 64 | bnes 6f /* no, skip */ | ||
| 65 | movel %sp,sw_usp /* save user sp */ | ||
| 66 | addql #8,sw_usp /* remove exception */ | ||
| 67 | movel sw_ksp,%sp /* kernel sp */ | ||
| 68 | subql #8,%sp /* room for exception */ | ||
| 69 | clrl %sp@- /* stkadj */ | ||
| 70 | movel %d0,%sp@- /* orig d0 */ | ||
| 71 | movel %d0,%sp@- /* d0 */ | ||
| 72 | lea %sp@(-32),%sp /* space for 8 regs */ | ||
| 73 | moveml %d1-%d5/%a0-%a2,%sp@ | ||
| 74 | movel sw_usp,%a0 /* get usp */ | ||
| 75 | movel %a0@-,%sp@(PT_PC) /* copy exception program counter */ | ||
| 76 | movel %a0@-,%sp@(PT_FORMATVEC)/* copy exception format/vector/sr */ | ||
| 77 | bra 7f | ||
| 78 | 6: | ||
| 79 | clrl %sp@- /* stkadj */ | ||
| 80 | movel %d0,%sp@- /* orig d0 */ | ||
| 81 | movel %d0,%sp@- /* d0 */ | ||
| 82 | lea %sp@(-32),%sp /* space for 8 regs */ | ||
| 83 | moveml %d1-%d5/%a0-%a2,%sp@ | ||
| 84 | 7: | ||
| 85 | .endm | ||
| 86 | |||
| 87 | .macro RESTORE_ALL | ||
| 88 | btst #5,%sp@(PT_SR) /* going user? */ | ||
| 89 | bnes 8f /* no, skip */ | ||
| 90 | move #0x2700,%sr /* disable intrs */ | ||
| 91 | movel sw_usp,%a0 /* get usp */ | ||
| 92 | movel %sp@(PT_PC),%a0@- /* copy exception program counter */ | ||
| 93 | movel %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */ | ||
| 94 | moveml %sp@,%d1-%d5/%a0-%a2 | ||
| 95 | lea %sp@(32),%sp /* space for 8 regs */ | ||
| 96 | movel %sp@+,%d0 | ||
| 97 | addql #4,%sp /* orig d0 */ | ||
| 98 | addl %sp@+,%sp /* stkadj */ | ||
| 99 | addql #8,%sp /* remove exception */ | ||
| 100 | movel %sp,sw_ksp /* save ksp */ | ||
| 101 | subql #8,sw_usp /* set exception */ | ||
| 102 | movel sw_usp,%sp /* restore usp */ | ||
| 103 | rte | ||
| 104 | 8: | ||
| 105 | moveml %sp@,%d1-%d5/%a0-%a2 | ||
| 106 | lea %sp@(32),%sp /* space for 8 regs */ | ||
| 107 | movel %sp@+,%d0 | ||
| 108 | addql #4,%sp /* orig d0 */ | ||
| 109 | addl %sp@+,%sp /* stkadj */ | ||
| 110 | rte | ||
| 111 | .endm | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Quick exception save, use current stack only. | ||
| 115 | */ | ||
| 116 | .macro SAVE_LOCAL | ||
| 117 | move #0x2700,%sr /* disable intrs */ | ||
| 118 | clrl %sp@- /* stkadj */ | ||
| 119 | movel %d0,%sp@- /* orig d0 */ | ||
| 120 | movel %d0,%sp@- /* d0 */ | ||
| 121 | lea %sp@(-32),%sp /* space for 8 regs */ | ||
| 122 | moveml %d1-%d5/%a0-%a2,%sp@ | ||
| 123 | .endm | ||
| 124 | |||
| 125 | .macro RESTORE_LOCAL | ||
| 126 | moveml %sp@,%d1-%d5/%a0-%a2 | ||
| 127 | lea %sp@(32),%sp /* space for 8 regs */ | ||
| 128 | movel %sp@+,%d0 | ||
| 129 | addql #4,%sp /* orig d0 */ | ||
| 130 | addl %sp@+,%sp /* stkadj */ | ||
| 131 | rte | ||
| 132 | .endm | ||
| 133 | |||
| 134 | .macro SAVE_SWITCH_STACK | ||
| 135 | lea %sp@(-24),%sp /* 6 regs */ | ||
| 136 | moveml %a3-%a6/%d6-%d7,%sp@ | ||
| 137 | .endm | ||
| 138 | |||
| 139 | .macro RESTORE_SWITCH_STACK | ||
| 140 | moveml %sp@,%a3-%a6/%d6-%d7 | ||
| 141 | lea %sp@(24),%sp /* 6 regs */ | ||
| 142 | .endm | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Software copy of the user and kernel stack pointers... Ugh... | ||
| 146 | * Need these to get around ColdFire not having separate kernel | ||
| 147 | * and user stack pointers. | ||
| 148 | */ | ||
| 149 | .globl sw_usp | ||
| 150 | .globl sw_ksp | ||
| 151 | |||
| 152 | #else /* !CONFIG_COLDFIRE */ | ||
| 153 | |||
| 154 | /* | ||
| 155 | * Standard 68k interrupt entry and exit macros. | ||
| 156 | */ | ||
| 157 | .macro SAVE_ALL | ||
| 158 | clrl %sp@- /* stkadj */ | ||
| 159 | movel %d0,%sp@- /* orig d0 */ | ||
| 160 | movel %d0,%sp@- /* d0 */ | ||
| 161 | moveml %d1-%d5/%a0-%a2,%sp@- | ||
| 162 | .endm | ||
| 163 | |||
| 164 | .macro RESTORE_ALL | ||
| 165 | moveml %sp@+,%a0-%a2/%d1-%d5 | ||
| 166 | movel %sp@+,%d0 | ||
| 167 | addql #4,%sp /* orig d0 */ | ||
| 168 | addl %sp@+,%sp /* stkadj */ | ||
| 169 | rte | ||
| 170 | .endm | ||
| 171 | |||
| 172 | .macro SAVE_SWITCH_STACK | ||
| 173 | moveml %a3-%a6/%d6-%d7,%sp@- | ||
| 174 | .endm | ||
| 175 | |||
| 176 | .macro RESTORE_SWITCH_STACK | ||
| 177 | moveml %sp@+,%a3-%a6/%d6-%d7 | ||
| 178 | .endm | ||
| 179 | |||
| 180 | #endif /* !CONFIG_COLDFIRE */ | ||
| 181 | #endif /* __ASSEMBLY__ */ | ||
| 182 | #endif /* __M68KNOMMU_ENTRY_H */ | ||
diff --git a/arch/m68k/include/asm/errno.h b/arch/m68k/include/asm/errno.h new file mode 100644 index 000000000000..0d4e188d6ef6 --- /dev/null +++ b/arch/m68k/include/asm/errno.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68K_ERRNO_H | ||
| 2 | #define _M68K_ERRNO_H | ||
| 3 | |||
| 4 | #include <asm-generic/errno.h> | ||
| 5 | |||
| 6 | #endif /* _M68K_ERRNO_H */ | ||
diff --git a/arch/m68k/include/asm/fb.h b/arch/m68k/include/asm/fb.h new file mode 100644 index 000000000000..97bcaefd2064 --- /dev/null +++ b/arch/m68k/include/asm/fb.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "fb_no.h" | ||
| 3 | #else | ||
| 4 | #include "fb_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/fb_mm.h b/arch/m68k/include/asm/fb_mm.h new file mode 100644 index 000000000000..380b97ae8157 --- /dev/null +++ b/arch/m68k/include/asm/fb_mm.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | #ifndef _ASM_FB_H_ | ||
| 2 | #define _ASM_FB_H_ | ||
| 3 | |||
| 4 | #include <linux/fb.h> | ||
| 5 | #include <linux/fs.h> | ||
| 6 | #include <asm/page.h> | ||
| 7 | #include <asm/setup.h> | ||
| 8 | |||
| 9 | #ifdef CONFIG_SUN3 | ||
| 10 | static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, | ||
| 11 | unsigned long off) | ||
| 12 | { | ||
| 13 | pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE; | ||
| 14 | } | ||
| 15 | #else | ||
| 16 | static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma, | ||
| 17 | unsigned long off) | ||
| 18 | { | ||
| 19 | if (CPU_IS_020_OR_030) | ||
| 20 | pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030; | ||
| 21 | if (CPU_IS_040_OR_060) { | ||
| 22 | pgprot_val(vma->vm_page_prot) &= _CACHEMASK040; | ||
| 23 | /* Use no-cache mode, serialized */ | ||
| 24 | pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S; | ||
| 25 | } | ||
| 26 | } | ||
| 27 | #endif /* CONFIG_SUN3 */ | ||
| 28 | |||
| 29 | static inline int fb_is_primary_device(struct fb_info *info) | ||
| 30 | { | ||
| 31 | return 0; | ||
| 32 | } | ||
| 33 | |||
| 34 | #endif /* _ASM_FB_H_ */ | ||
diff --git a/arch/m68k/include/asm/fb_no.h b/arch/m68k/include/asm/fb_no.h new file mode 100644 index 000000000000..c7df38030992 --- /dev/null +++ b/arch/m68k/include/asm/fb_no.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef _ASM_FB_H_ | ||
| 2 | #define _ASM_FB_H_ | ||
| 3 | #include <linux/fb.h> | ||
| 4 | |||
| 5 | #define fb_pgprotect(...) do {} while (0) | ||
| 6 | |||
| 7 | static inline int fb_is_primary_device(struct fb_info *info) | ||
| 8 | { | ||
| 9 | return 0; | ||
| 10 | } | ||
| 11 | |||
| 12 | #endif /* _ASM_FB_H_ */ | ||
diff --git a/arch/m68k/include/asm/fbio.h b/arch/m68k/include/asm/fbio.h new file mode 100644 index 000000000000..b9215a0907d3 --- /dev/null +++ b/arch/m68k/include/asm/fbio.h | |||
| @@ -0,0 +1,330 @@ | |||
| 1 | #ifndef __LINUX_FBIO_H | ||
| 2 | #define __LINUX_FBIO_H | ||
| 3 | |||
| 4 | #include <linux/compiler.h> | ||
| 5 | #include <linux/types.h> | ||
| 6 | |||
| 7 | /* Constants used for fbio SunOS compatibility */ | ||
| 8 | /* (C) 1996 Miguel de Icaza */ | ||
| 9 | |||
| 10 | /* Frame buffer types */ | ||
| 11 | #define FBTYPE_NOTYPE -1 | ||
| 12 | #define FBTYPE_SUN1BW 0 /* mono */ | ||
| 13 | #define FBTYPE_SUN1COLOR 1 | ||
| 14 | #define FBTYPE_SUN2BW 2 | ||
| 15 | #define FBTYPE_SUN2COLOR 3 | ||
| 16 | #define FBTYPE_SUN2GP 4 | ||
| 17 | #define FBTYPE_SUN5COLOR 5 | ||
| 18 | #define FBTYPE_SUN3COLOR 6 | ||
| 19 | #define FBTYPE_MEMCOLOR 7 | ||
| 20 | #define FBTYPE_SUN4COLOR 8 | ||
| 21 | |||
| 22 | #define FBTYPE_NOTSUN1 9 | ||
| 23 | #define FBTYPE_NOTSUN2 10 | ||
| 24 | #define FBTYPE_NOTSUN3 11 | ||
| 25 | |||
| 26 | #define FBTYPE_SUNFAST_COLOR 12 /* cg6 */ | ||
| 27 | #define FBTYPE_SUNROP_COLOR 13 | ||
| 28 | #define FBTYPE_SUNFB_VIDEO 14 | ||
| 29 | #define FBTYPE_SUNGIFB 15 | ||
| 30 | #define FBTYPE_SUNGPLAS 16 | ||
| 31 | #define FBTYPE_SUNGP3 17 | ||
| 32 | #define FBTYPE_SUNGT 18 | ||
| 33 | #define FBTYPE_SUNLEO 19 /* zx Leo card */ | ||
| 34 | #define FBTYPE_MDICOLOR 20 /* cg14 */ | ||
| 35 | #define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */ | ||
| 36 | |||
| 37 | #define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */ | ||
| 38 | |||
| 39 | /* Does not seem to be listed in the Sun file either */ | ||
| 40 | #define FBTYPE_CREATOR 22 | ||
| 41 | #define FBTYPE_PCI_IGA1682 23 | ||
| 42 | #define FBTYPE_P9100COLOR 24 | ||
| 43 | |||
| 44 | #define FBTYPE_PCI_GENERIC 1000 | ||
| 45 | #define FBTYPE_PCI_MACH64 1001 | ||
| 46 | |||
| 47 | /* fbio ioctls */ | ||
| 48 | /* Returned by FBIOGTYPE */ | ||
| 49 | struct fbtype { | ||
| 50 | int fb_type; /* fb type, see above */ | ||
| 51 | int fb_height; /* pixels */ | ||
| 52 | int fb_width; /* pixels */ | ||
| 53 | int fb_depth; | ||
| 54 | int fb_cmsize; /* color map entries */ | ||
| 55 | int fb_size; /* fb size in bytes */ | ||
| 56 | }; | ||
| 57 | #define FBIOGTYPE _IOR('F', 0, struct fbtype) | ||
| 58 | |||
| 59 | struct fbcmap { | ||
| 60 | int index; /* first element (0 origin) */ | ||
| 61 | int count; | ||
| 62 | unsigned char __user *red; | ||
| 63 | unsigned char __user *green; | ||
| 64 | unsigned char __user *blue; | ||
| 65 | }; | ||
| 66 | |||
| 67 | #ifdef __KERNEL__ | ||
| 68 | #define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap) | ||
| 69 | #define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap) | ||
| 70 | #else | ||
| 71 | #define FBIOPUTCMAP _IOW('F', 3, struct fbcmap) | ||
| 72 | #define FBIOGETCMAP _IOW('F', 4, struct fbcmap) | ||
| 73 | #endif | ||
| 74 | |||
| 75 | /* # of device specific values */ | ||
| 76 | #define FB_ATTR_NDEVSPECIFIC 8 | ||
| 77 | /* # of possible emulations */ | ||
| 78 | #define FB_ATTR_NEMUTYPES 4 | ||
| 79 | |||
| 80 | struct fbsattr { | ||
| 81 | int flags; | ||
| 82 | int emu_type; /* -1 if none */ | ||
| 83 | int dev_specific[FB_ATTR_NDEVSPECIFIC]; | ||
| 84 | }; | ||
| 85 | |||
| 86 | struct fbgattr { | ||
| 87 | int real_type; /* real frame buffer type */ | ||
| 88 | int owner; /* unknown */ | ||
| 89 | struct fbtype fbtype; /* real frame buffer fbtype */ | ||
| 90 | struct fbsattr sattr; | ||
| 91 | int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */ | ||
| 92 | }; | ||
| 93 | #define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */ | ||
| 94 | #define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */ | ||
| 95 | |||
| 96 | #define FBIOSVIDEO _IOW('F', 7, int) | ||
| 97 | #define FBIOGVIDEO _IOR('F', 8, int) | ||
| 98 | |||
| 99 | struct fbcursor { | ||
| 100 | short set; /* what to set, choose from the list above */ | ||
| 101 | short enable; /* cursor on/off */ | ||
| 102 | struct fbcurpos pos; /* cursor position */ | ||
| 103 | struct fbcurpos hot; /* cursor hot spot */ | ||
| 104 | struct fbcmap cmap; /* color map info */ | ||
| 105 | struct fbcurpos size; /* cursor bit map size */ | ||
| 106 | char __user *image; /* cursor image bits */ | ||
| 107 | char __user *mask; /* cursor mask bits */ | ||
| 108 | }; | ||
| 109 | |||
| 110 | /* set/get cursor attributes/shape */ | ||
| 111 | #define FBIOSCURSOR _IOW('F', 24, struct fbcursor) | ||
| 112 | #define FBIOGCURSOR _IOWR('F', 25, struct fbcursor) | ||
| 113 | |||
| 114 | /* set/get cursor position */ | ||
| 115 | #define FBIOSCURPOS _IOW('F', 26, struct fbcurpos) | ||
| 116 | #define FBIOGCURPOS _IOW('F', 27, struct fbcurpos) | ||
| 117 | |||
| 118 | /* get max cursor size */ | ||
| 119 | #define FBIOGCURMAX _IOR('F', 28, struct fbcurpos) | ||
| 120 | |||
| 121 | /* wid manipulation */ | ||
| 122 | struct fb_wid_alloc { | ||
| 123 | #define FB_WID_SHARED_8 0 | ||
| 124 | #define FB_WID_SHARED_24 1 | ||
| 125 | #define FB_WID_DBL_8 2 | ||
| 126 | #define FB_WID_DBL_24 3 | ||
| 127 | __u32 wa_type; | ||
| 128 | __s32 wa_index; /* Set on return */ | ||
| 129 | __u32 wa_count; | ||
| 130 | }; | ||
| 131 | struct fb_wid_item { | ||
| 132 | __u32 wi_type; | ||
| 133 | __s32 wi_index; | ||
| 134 | __u32 wi_attrs; | ||
| 135 | __u32 wi_values[32]; | ||
| 136 | }; | ||
| 137 | struct fb_wid_list { | ||
| 138 | __u32 wl_flags; | ||
| 139 | __u32 wl_count; | ||
| 140 | struct fb_wid_item *wl_list; | ||
| 141 | }; | ||
| 142 | |||
| 143 | #define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc) | ||
| 144 | #define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc) | ||
| 145 | #define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list) | ||
| 146 | #define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list) | ||
| 147 | |||
| 148 | /* Creator ioctls */ | ||
| 149 | #define FFB_IOCTL ('F'<<8) | ||
| 150 | #define FFB_SYS_INFO (FFB_IOCTL|80) | ||
| 151 | #define FFB_CLUTREAD (FFB_IOCTL|81) | ||
| 152 | #define FFB_CLUTPOST (FFB_IOCTL|82) | ||
| 153 | #define FFB_SETDIAGMODE (FFB_IOCTL|83) | ||
| 154 | #define FFB_GETMONITORID (FFB_IOCTL|84) | ||
| 155 | #define FFB_GETVIDEOMODE (FFB_IOCTL|85) | ||
| 156 | #define FFB_SETVIDEOMODE (FFB_IOCTL|86) | ||
| 157 | #define FFB_SETSERVER (FFB_IOCTL|87) | ||
| 158 | #define FFB_SETOVCTL (FFB_IOCTL|88) | ||
| 159 | #define FFB_GETOVCTL (FFB_IOCTL|89) | ||
| 160 | #define FFB_GETSAXNUM (FFB_IOCTL|90) | ||
| 161 | #define FFB_FBDEBUG (FFB_IOCTL|91) | ||
| 162 | |||
| 163 | /* Cg14 ioctls */ | ||
| 164 | #define MDI_IOCTL ('M'<<8) | ||
| 165 | #define MDI_RESET (MDI_IOCTL|1) | ||
| 166 | #define MDI_GET_CFGINFO (MDI_IOCTL|2) | ||
| 167 | #define MDI_SET_PIXELMODE (MDI_IOCTL|3) | ||
| 168 | # define MDI_32_PIX 32 | ||
| 169 | # define MDI_16_PIX 16 | ||
| 170 | # define MDI_8_PIX 8 | ||
| 171 | |||
| 172 | struct mdi_cfginfo { | ||
| 173 | int mdi_ncluts; /* Number of implemented CLUTs in this MDI */ | ||
| 174 | int mdi_type; /* FBTYPE name */ | ||
| 175 | int mdi_height; /* height */ | ||
| 176 | int mdi_width; /* widht */ | ||
| 177 | int mdi_size; /* available ram */ | ||
| 178 | int mdi_mode; /* 8bpp, 16bpp or 32bpp */ | ||
| 179 | int mdi_pixfreq; /* pixel clock (from PROM) */ | ||
| 180 | }; | ||
| 181 | |||
| 182 | /* SparcLinux specific ioctl for the MDI, should be replaced for | ||
| 183 | * the SET_XLUT/SET_CLUTn ioctls instead | ||
| 184 | */ | ||
| 185 | #define MDI_CLEAR_XLUT (MDI_IOCTL|9) | ||
| 186 | |||
| 187 | /* leo & ffb ioctls */ | ||
| 188 | struct fb_clut_alloc { | ||
| 189 | __u32 clutid; /* Set on return */ | ||
| 190 | __u32 flag; | ||
| 191 | __u32 index; | ||
| 192 | }; | ||
| 193 | |||
| 194 | struct fb_clut { | ||
| 195 | #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */ | ||
| 196 | __u32 flag; | ||
| 197 | __u32 clutid; | ||
| 198 | __u32 offset; | ||
| 199 | __u32 count; | ||
| 200 | char * red; | ||
| 201 | char * green; | ||
| 202 | char * blue; | ||
| 203 | }; | ||
| 204 | |||
| 205 | struct fb_clut32 { | ||
| 206 | __u32 flag; | ||
| 207 | __u32 clutid; | ||
| 208 | __u32 offset; | ||
| 209 | __u32 count; | ||
| 210 | __u32 red; | ||
| 211 | __u32 green; | ||
| 212 | __u32 blue; | ||
| 213 | }; | ||
| 214 | |||
| 215 | #define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc) | ||
| 216 | #define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc) | ||
| 217 | #define LEO_CLUTREAD _IOW('L', 55, struct fb_clut) | ||
| 218 | #define LEO_CLUTPOST _IOW('L', 56, struct fb_clut) | ||
| 219 | #define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */ | ||
| 220 | #define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */ | ||
| 221 | |||
| 222 | #ifdef __KERNEL__ | ||
| 223 | /* Addresses on the fd of a cgsix that are mappable */ | ||
| 224 | #define CG6_FBC 0x70000000 | ||
| 225 | #define CG6_TEC 0x70001000 | ||
| 226 | #define CG6_BTREGS 0x70002000 | ||
| 227 | #define CG6_FHC 0x70004000 | ||
| 228 | #define CG6_THC 0x70005000 | ||
| 229 | #define CG6_ROM 0x70006000 | ||
| 230 | #define CG6_RAM 0x70016000 | ||
| 231 | #define CG6_DHC 0x80000000 | ||
| 232 | |||
| 233 | #define CG3_MMAP_OFFSET 0x4000000 | ||
| 234 | |||
| 235 | /* Addresses on the fd of a tcx that are mappable */ | ||
| 236 | #define TCX_RAM8BIT 0x00000000 | ||
| 237 | #define TCX_RAM24BIT 0x01000000 | ||
| 238 | #define TCX_UNK3 0x10000000 | ||
| 239 | #define TCX_UNK4 0x20000000 | ||
| 240 | #define TCX_CONTROLPLANE 0x28000000 | ||
| 241 | #define TCX_UNK6 0x30000000 | ||
| 242 | #define TCX_UNK7 0x38000000 | ||
| 243 | #define TCX_TEC 0x70000000 | ||
| 244 | #define TCX_BTREGS 0x70002000 | ||
| 245 | #define TCX_THC 0x70004000 | ||
| 246 | #define TCX_DHC 0x70008000 | ||
| 247 | #define TCX_ALT 0x7000a000 | ||
| 248 | #define TCX_SYNC 0x7000e000 | ||
| 249 | #define TCX_UNK2 0x70010000 | ||
| 250 | |||
| 251 | /* CG14 definitions */ | ||
| 252 | |||
| 253 | /* Offsets into the OBIO space: */ | ||
| 254 | #define CG14_REGS 0 /* registers */ | ||
| 255 | #define CG14_CURSORREGS 0x1000 /* cursor registers */ | ||
| 256 | #define CG14_DACREGS 0x2000 /* DAC registers */ | ||
| 257 | #define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */ | ||
| 258 | #define CG14_CLUT1 0x4000 /* Color Look Up Table */ | ||
| 259 | #define CG14_CLUT2 0x5000 /* Color Look Up Table */ | ||
| 260 | #define CG14_CLUT3 0x6000 /* Color Look Up Table */ | ||
| 261 | #define CG14_AUTO 0xf000 | ||
| 262 | |||
| 263 | #endif /* KERNEL */ | ||
| 264 | |||
| 265 | /* These are exported to userland for applications to use */ | ||
| 266 | /* Mappable offsets for the cg14: control registers */ | ||
| 267 | #define MDI_DIRECT_MAP 0x10000000 | ||
| 268 | #define MDI_CTLREG_MAP 0x20000000 | ||
| 269 | #define MDI_CURSOR_MAP 0x30000000 | ||
| 270 | #define MDI_SHDW_VRT_MAP 0x40000000 | ||
| 271 | |||
| 272 | /* Mappable offsets for the cg14: frame buffer resolutions */ | ||
| 273 | /* 32 bits */ | ||
| 274 | #define MDI_CHUNKY_XBGR_MAP 0x50000000 | ||
| 275 | #define MDI_CHUNKY_BGR_MAP 0x60000000 | ||
| 276 | |||
| 277 | /* 16 bits */ | ||
| 278 | #define MDI_PLANAR_X16_MAP 0x70000000 | ||
| 279 | #define MDI_PLANAR_C16_MAP 0x80000000 | ||
| 280 | |||
| 281 | /* 8 bit is done as CG3 MMAP offset */ | ||
| 282 | /* 32 bits, planar */ | ||
| 283 | #define MDI_PLANAR_X32_MAP 0x90000000 | ||
| 284 | #define MDI_PLANAR_B32_MAP 0xa0000000 | ||
| 285 | #define MDI_PLANAR_G32_MAP 0xb0000000 | ||
| 286 | #define MDI_PLANAR_R32_MAP 0xc0000000 | ||
| 287 | |||
| 288 | /* Mappable offsets on leo */ | ||
| 289 | #define LEO_SS0_MAP 0x00000000 | ||
| 290 | #define LEO_LC_SS0_USR_MAP 0x00800000 | ||
| 291 | #define LEO_LD_SS0_MAP 0x00801000 | ||
| 292 | #define LEO_LX_CURSOR_MAP 0x00802000 | ||
| 293 | #define LEO_SS1_MAP 0x00803000 | ||
| 294 | #define LEO_LC_SS1_USR_MAP 0x01003000 | ||
| 295 | #define LEO_LD_SS1_MAP 0x01004000 | ||
| 296 | #define LEO_UNK_MAP 0x01005000 | ||
| 297 | #define LEO_LX_KRN_MAP 0x01006000 | ||
| 298 | #define LEO_LC_SS0_KRN_MAP 0x01007000 | ||
| 299 | #define LEO_LC_SS1_KRN_MAP 0x01008000 | ||
| 300 | #define LEO_LD_GBL_MAP 0x01009000 | ||
| 301 | #define LEO_UNK2_MAP 0x0100a000 | ||
| 302 | |||
| 303 | #ifdef __KERNEL__ | ||
| 304 | struct fbcmap32 { | ||
| 305 | int index; /* first element (0 origin) */ | ||
| 306 | int count; | ||
| 307 | u32 red; | ||
| 308 | u32 green; | ||
| 309 | u32 blue; | ||
| 310 | }; | ||
| 311 | |||
| 312 | #define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32) | ||
| 313 | #define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32) | ||
| 314 | |||
| 315 | struct fbcursor32 { | ||
| 316 | short set; /* what to set, choose from the list above */ | ||
| 317 | short enable; /* cursor on/off */ | ||
| 318 | struct fbcurpos pos; /* cursor position */ | ||
| 319 | struct fbcurpos hot; /* cursor hot spot */ | ||
| 320 | struct fbcmap32 cmap; /* color map info */ | ||
| 321 | struct fbcurpos size; /* cursor bit map size */ | ||
| 322 | u32 image; /* cursor image bits */ | ||
| 323 | u32 mask; /* cursor mask bits */ | ||
| 324 | }; | ||
| 325 | |||
| 326 | #define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32) | ||
| 327 | #define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32) | ||
| 328 | #endif | ||
| 329 | |||
| 330 | #endif /* __LINUX_FBIO_H */ | ||
diff --git a/arch/m68k/include/asm/fcntl.h b/arch/m68k/include/asm/fcntl.h new file mode 100644 index 000000000000..1c369b20dc45 --- /dev/null +++ b/arch/m68k/include/asm/fcntl.h | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | #ifndef _M68K_FCNTL_H | ||
| 2 | #define _M68K_FCNTL_H | ||
| 3 | |||
| 4 | #define O_DIRECTORY 040000 /* must be a directory */ | ||
| 5 | #define O_NOFOLLOW 0100000 /* don't follow links */ | ||
| 6 | #define O_DIRECT 0200000 /* direct disk access hint - currently ignored */ | ||
| 7 | #define O_LARGEFILE 0400000 | ||
| 8 | |||
| 9 | #include <asm-generic/fcntl.h> | ||
| 10 | |||
| 11 | #endif /* _M68K_FCNTL_H */ | ||
diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h new file mode 100644 index 000000000000..814b5174a8e0 --- /dev/null +++ b/arch/m68k/include/asm/flat.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68knommu/flat.h -- uClinux flat-format executables | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __M68KNOMMU_FLAT_H__ | ||
| 6 | #define __M68KNOMMU_FLAT_H__ | ||
| 7 | |||
| 8 | #define flat_stack_align(sp) /* nothing needed */ | ||
| 9 | #define flat_argvp_envp_on_stack() 1 | ||
| 10 | #define flat_old_ram_flag(flags) (flags) | ||
| 11 | #define flat_reloc_valid(reloc, size) ((reloc) <= (size)) | ||
| 12 | #define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) | ||
| 13 | #define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) | ||
| 14 | #define flat_get_relocate_addr(rel) (rel) | ||
| 15 | #define flat_set_persistent(relval, p) 0 | ||
| 16 | |||
| 17 | #endif /* __M68KNOMMU_FLAT_H__ */ | ||
diff --git a/arch/m68k/include/asm/floppy.h b/arch/m68k/include/asm/floppy.h new file mode 100644 index 000000000000..697d50393dd0 --- /dev/null +++ b/arch/m68k/include/asm/floppy.h | |||
| @@ -0,0 +1,254 @@ | |||
| 1 | /* | ||
| 2 | * Implementation independent bits of the Floppy driver. | ||
| 3 | * | ||
| 4 | * much of this file is derived from what was originally the Q40 floppy driver. | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file "COPYING" in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | * | ||
| 10 | * Copyright (C) 1999, 2000, 2001 | ||
| 11 | * | ||
| 12 | * Sun3x support added 2/4/2000 Sam Creasey (sammy@sammy.net) | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <asm/io.h> | ||
| 17 | |||
| 18 | #include <linux/vmalloc.h> | ||
| 19 | |||
| 20 | asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id); | ||
| 21 | |||
| 22 | /* constants... */ | ||
| 23 | |||
| 24 | #undef MAX_DMA_ADDRESS | ||
| 25 | #define MAX_DMA_ADDRESS 0x00 /* nothing like that */ | ||
| 26 | |||
| 27 | |||
| 28 | /* | ||
| 29 | * Again, the CMOS information doesn't work on m68k.. | ||
| 30 | */ | ||
| 31 | #define FLOPPY0_TYPE (MACH_IS_Q40 ? 6 : 4) | ||
| 32 | #define FLOPPY1_TYPE 0 | ||
| 33 | |||
| 34 | /* basically PC init + set use_virtual_dma */ | ||
| 35 | #define FDC1 m68k_floppy_init() | ||
| 36 | |||
| 37 | #define N_FDC 1 | ||
| 38 | #define N_DRIVE 8 | ||
| 39 | |||
| 40 | |||
| 41 | /* vdma globals adapted from asm-i386/floppy.h */ | ||
| 42 | |||
| 43 | static int virtual_dma_count=0; | ||
| 44 | static int virtual_dma_residue=0; | ||
| 45 | static char *virtual_dma_addr=NULL; | ||
| 46 | static int virtual_dma_mode=0; | ||
| 47 | static int doing_pdma=0; | ||
| 48 | |||
| 49 | #include <asm/sun3xflop.h> | ||
| 50 | |||
| 51 | extern spinlock_t dma_spin_lock; | ||
| 52 | |||
| 53 | static __inline__ unsigned long claim_dma_lock(void) | ||
| 54 | { | ||
| 55 | unsigned long flags; | ||
| 56 | spin_lock_irqsave(&dma_spin_lock, flags); | ||
| 57 | return flags; | ||
| 58 | } | ||
| 59 | |||
| 60 | static __inline__ void release_dma_lock(unsigned long flags) | ||
| 61 | { | ||
| 62 | spin_unlock_irqrestore(&dma_spin_lock, flags); | ||
| 63 | } | ||
| 64 | |||
| 65 | |||
| 66 | static __inline__ unsigned char fd_inb(int port) | ||
| 67 | { | ||
| 68 | if(MACH_IS_Q40) | ||
| 69 | return inb_p(port); | ||
| 70 | else if(MACH_IS_SUN3X) | ||
| 71 | return sun3x_82072_fd_inb(port); | ||
| 72 | return 0; | ||
| 73 | } | ||
| 74 | |||
| 75 | static __inline__ void fd_outb(unsigned char value, int port) | ||
| 76 | { | ||
| 77 | if(MACH_IS_Q40) | ||
| 78 | outb_p(value, port); | ||
| 79 | else if(MACH_IS_SUN3X) | ||
| 80 | sun3x_82072_fd_outb(value, port); | ||
| 81 | } | ||
| 82 | |||
| 83 | |||
| 84 | static int fd_request_irq(void) | ||
| 85 | { | ||
| 86 | if(MACH_IS_Q40) | ||
| 87 | return request_irq(FLOPPY_IRQ, floppy_hardint, | ||
| 88 | IRQF_DISABLED, "floppy", floppy_hardint); | ||
| 89 | else if(MACH_IS_SUN3X) | ||
| 90 | return sun3xflop_request_irq(); | ||
| 91 | return -ENXIO; | ||
| 92 | } | ||
| 93 | |||
| 94 | static void fd_free_irq(void) | ||
| 95 | { | ||
| 96 | if(MACH_IS_Q40) | ||
| 97 | free_irq(FLOPPY_IRQ, floppy_hardint); | ||
| 98 | } | ||
| 99 | |||
| 100 | #define fd_request_dma() vdma_request_dma(FLOPPY_DMA,"floppy") | ||
| 101 | #define fd_get_dma_residue() vdma_get_dma_residue(FLOPPY_DMA) | ||
| 102 | #define fd_dma_mem_alloc(size) vdma_mem_alloc(size) | ||
| 103 | #define fd_dma_setup(addr, size, mode, io) vdma_dma_setup(addr, size, mode, io) | ||
| 104 | |||
| 105 | #define fd_enable_irq() /* nothing... */ | ||
| 106 | #define fd_disable_irq() /* nothing... */ | ||
| 107 | |||
| 108 | #define fd_free_dma() /* nothing */ | ||
| 109 | |||
| 110 | /* No 64k boundary crossing problems on Q40 - no DMA at all */ | ||
| 111 | #define CROSS_64KB(a,s) (0) | ||
| 112 | |||
| 113 | #define DMA_MODE_READ 0x44 /* i386 look-alike */ | ||
| 114 | #define DMA_MODE_WRITE 0x48 | ||
| 115 | |||
| 116 | |||
| 117 | static int m68k_floppy_init(void) | ||
| 118 | { | ||
| 119 | use_virtual_dma =1; | ||
| 120 | can_use_virtual_dma = 1; | ||
| 121 | |||
| 122 | |||
| 123 | if (MACH_IS_Q40) | ||
| 124 | return 0x3f0; | ||
| 125 | else if(MACH_IS_SUN3X) | ||
| 126 | return sun3xflop_init(); | ||
| 127 | else | ||
| 128 | return -1; | ||
| 129 | } | ||
| 130 | |||
| 131 | |||
| 132 | static int vdma_request_dma(unsigned int dmanr, const char * device_id) | ||
| 133 | { | ||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | |||
| 138 | static int vdma_get_dma_residue(unsigned int dummy) | ||
| 139 | { | ||
| 140 | return virtual_dma_count + virtual_dma_residue; | ||
| 141 | } | ||
| 142 | |||
| 143 | |||
| 144 | static unsigned long vdma_mem_alloc(unsigned long size) | ||
| 145 | { | ||
| 146 | return (unsigned long) vmalloc(size); | ||
| 147 | |||
| 148 | } | ||
| 149 | |||
| 150 | static void _fd_dma_mem_free(unsigned long addr, unsigned long size) | ||
| 151 | { | ||
| 152 | vfree((void *)addr); | ||
| 153 | } | ||
| 154 | #define fd_dma_mem_free(addr,size) _fd_dma_mem_free(addr, size) | ||
| 155 | |||
| 156 | |||
| 157 | /* choose_dma_mode ???*/ | ||
| 158 | |||
| 159 | static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) | ||
| 160 | { | ||
| 161 | doing_pdma = 1; | ||
| 162 | virtual_dma_port = (MACH_IS_Q40 ? io : 0); | ||
| 163 | virtual_dma_mode = (mode == DMA_MODE_WRITE); | ||
| 164 | virtual_dma_addr = addr; | ||
| 165 | virtual_dma_count = size; | ||
| 166 | virtual_dma_residue = 0; | ||
| 167 | return 0; | ||
| 168 | } | ||
| 169 | |||
| 170 | |||
| 171 | |||
| 172 | static void fd_disable_dma(void) | ||
| 173 | { | ||
| 174 | doing_pdma = 0; | ||
| 175 | virtual_dma_residue += virtual_dma_count; | ||
| 176 | virtual_dma_count=0; | ||
| 177 | } | ||
| 178 | |||
| 179 | |||
| 180 | |||
| 181 | /* this is the only truly Q40 specific function */ | ||
| 182 | |||
| 183 | asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id) | ||
| 184 | { | ||
| 185 | register unsigned char st; | ||
| 186 | |||
| 187 | #undef TRACE_FLPY_INT | ||
| 188 | #define NO_FLOPPY_ASSEMBLER | ||
| 189 | |||
| 190 | #ifdef TRACE_FLPY_INT | ||
| 191 | static int calls=0; | ||
| 192 | static int bytes=0; | ||
| 193 | static int dma_wait=0; | ||
| 194 | #endif | ||
| 195 | if(!doing_pdma) { | ||
| 196 | floppy_interrupt(irq, dev_id); | ||
| 197 | return IRQ_HANDLED; | ||
| 198 | } | ||
| 199 | |||
| 200 | #ifdef TRACE_FLPY_INT | ||
| 201 | if(!calls) | ||
| 202 | bytes = virtual_dma_count; | ||
| 203 | #endif | ||
| 204 | |||
| 205 | { | ||
| 206 | register int lcount; | ||
| 207 | register char *lptr; | ||
| 208 | |||
| 209 | /* serve 1st byte fast: */ | ||
| 210 | |||
| 211 | st=1; | ||
| 212 | for(lcount=virtual_dma_count, lptr=virtual_dma_addr; | ||
| 213 | lcount; lcount--, lptr++) { | ||
| 214 | st=inb(virtual_dma_port+4) & 0xa0 ; | ||
| 215 | if(st != 0xa0) | ||
| 216 | break; | ||
| 217 | if(virtual_dma_mode) | ||
| 218 | outb_p(*lptr, virtual_dma_port+5); | ||
| 219 | else | ||
| 220 | *lptr = inb_p(virtual_dma_port+5); | ||
| 221 | } | ||
| 222 | |||
| 223 | virtual_dma_count = lcount; | ||
| 224 | virtual_dma_addr = lptr; | ||
| 225 | st = inb(virtual_dma_port+4); | ||
| 226 | } | ||
| 227 | |||
| 228 | #ifdef TRACE_FLPY_INT | ||
| 229 | calls++; | ||
| 230 | #endif | ||
| 231 | if(st == 0x20) | ||
| 232 | return IRQ_HANDLED; | ||
| 233 | if(!(st & 0x20)) { | ||
| 234 | virtual_dma_residue += virtual_dma_count; | ||
| 235 | virtual_dma_count=0; | ||
| 236 | #ifdef TRACE_FLPY_INT | ||
| 237 | printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n", | ||
| 238 | virtual_dma_count, virtual_dma_residue, calls, bytes, | ||
| 239 | dma_wait); | ||
| 240 | calls = 0; | ||
| 241 | dma_wait=0; | ||
| 242 | #endif | ||
| 243 | doing_pdma = 0; | ||
| 244 | floppy_interrupt(irq, dev_id); | ||
| 245 | return IRQ_HANDLED; | ||
| 246 | } | ||
| 247 | #ifdef TRACE_FLPY_INT | ||
| 248 | if(!virtual_dma_count) | ||
| 249 | dma_wait++; | ||
| 250 | #endif | ||
| 251 | return IRQ_HANDLED; | ||
| 252 | } | ||
| 253 | |||
| 254 | #define EXTRA_FLOPPY_PARAMS | ||
diff --git a/arch/m68k/include/asm/fpu.h b/arch/m68k/include/asm/fpu.h new file mode 100644 index 000000000000..e19bc5ed9c37 --- /dev/null +++ b/arch/m68k/include/asm/fpu.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "fpu_no.h" | ||
| 3 | #else | ||
| 4 | #include "fpu_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/fpu_mm.h b/arch/m68k/include/asm/fpu_mm.h new file mode 100644 index 000000000000..ffb6b8cfc6d5 --- /dev/null +++ b/arch/m68k/include/asm/fpu_mm.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | #ifndef __M68K_FPU_H | ||
| 2 | #define __M68K_FPU_H | ||
| 3 | |||
| 4 | |||
| 5 | /* | ||
| 6 | * MAX floating point unit state size (FSAVE/FRESTORE) | ||
| 7 | */ | ||
| 8 | |||
| 9 | #if defined(CONFIG_M68020) || defined(CONFIG_M68030) | ||
| 10 | #define FPSTATESIZE (216) | ||
| 11 | #elif defined(CONFIG_M68040) | ||
| 12 | #define FPSTATESIZE (96) | ||
| 13 | #elif defined(CONFIG_M68KFPU_EMU) | ||
| 14 | #define FPSTATESIZE (28) | ||
| 15 | #elif defined(CONFIG_M68060) | ||
| 16 | #define FPSTATESIZE (12) | ||
| 17 | #else | ||
| 18 | #define FPSTATESIZE (0) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #endif /* __M68K_FPU_H */ | ||
diff --git a/arch/m68k/include/asm/fpu_no.h b/arch/m68k/include/asm/fpu_no.h new file mode 100644 index 000000000000..b16b2e4fca2a --- /dev/null +++ b/arch/m68k/include/asm/fpu_no.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | #ifndef __M68KNOMMU_FPU_H | ||
| 2 | #define __M68KNOMMU_FPU_H | ||
| 3 | |||
| 4 | |||
| 5 | /* | ||
| 6 | * MAX floating point unit state size (FSAVE/FRESTORE) | ||
| 7 | */ | ||
| 8 | #if defined(CONFIG_M68020) || defined(CONFIG_M68030) | ||
| 9 | #define FPSTATESIZE (216/sizeof(unsigned char)) | ||
| 10 | #elif defined(CONFIG_M68040) | ||
| 11 | #define FPSTATESIZE (96/sizeof(unsigned char)) | ||
| 12 | #elif defined(CONFIG_M68KFPU_EMU) | ||
| 13 | #define FPSTATESIZE (28/sizeof(unsigned char)) | ||
| 14 | #elif defined(CONFIG_M68060) | ||
| 15 | #define FPSTATESIZE (12/sizeof(unsigned char)) | ||
| 16 | #else | ||
| 17 | /* Assume no FP unit present then... */ | ||
| 18 | #define FPSTATESIZE (2) /* dummy size */ | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #endif /* __M68K_FPU_H */ | ||
diff --git a/arch/m68k/include/asm/futex.h b/arch/m68k/include/asm/futex.h new file mode 100644 index 000000000000..6a332a9f099c --- /dev/null +++ b/arch/m68k/include/asm/futex.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_FUTEX_H | ||
| 2 | #define _ASM_FUTEX_H | ||
| 3 | |||
| 4 | #include <asm-generic/futex.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/m68k/include/asm/hardirq.h b/arch/m68k/include/asm/hardirq.h new file mode 100644 index 000000000000..56d0d5db231c --- /dev/null +++ b/arch/m68k/include/asm/hardirq.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "hardirq_no.h" | ||
| 3 | #else | ||
| 4 | #include "hardirq_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/hardirq_mm.h b/arch/m68k/include/asm/hardirq_mm.h new file mode 100644 index 000000000000..394ee946015c --- /dev/null +++ b/arch/m68k/include/asm/hardirq_mm.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | #ifndef __M68K_HARDIRQ_H | ||
| 2 | #define __M68K_HARDIRQ_H | ||
| 3 | |||
| 4 | #include <linux/threads.h> | ||
| 5 | #include <linux/cache.h> | ||
| 6 | |||
| 7 | /* entry.S is sensitive to the offsets of these fields */ | ||
| 8 | typedef struct { | ||
| 9 | unsigned int __softirq_pending; | ||
| 10 | } ____cacheline_aligned irq_cpustat_t; | ||
| 11 | |||
| 12 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
| 13 | |||
| 14 | #define HARDIRQ_BITS 8 | ||
| 15 | |||
| 16 | #endif | ||
diff --git a/arch/m68k/include/asm/hardirq_no.h b/arch/m68k/include/asm/hardirq_no.h new file mode 100644 index 000000000000..bfad28149a49 --- /dev/null +++ b/arch/m68k/include/asm/hardirq_no.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | #ifndef __M68K_HARDIRQ_H | ||
| 2 | #define __M68K_HARDIRQ_H | ||
| 3 | |||
| 4 | #include <linux/cache.h> | ||
| 5 | #include <linux/threads.h> | ||
| 6 | #include <asm/irq.h> | ||
| 7 | |||
| 8 | typedef struct { | ||
| 9 | unsigned int __softirq_pending; | ||
| 10 | } ____cacheline_aligned irq_cpustat_t; | ||
| 11 | |||
| 12 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | ||
| 13 | |||
| 14 | #define HARDIRQ_BITS 8 | ||
| 15 | |||
| 16 | /* | ||
| 17 | * The hardirq mask has to be large enough to have | ||
| 18 | * space for potentially all IRQ sources in the system | ||
| 19 | * nesting on a single CPU: | ||
| 20 | */ | ||
| 21 | #if (1 << HARDIRQ_BITS) < NR_IRQS | ||
| 22 | # error HARDIRQ_BITS is too low! | ||
| 23 | #endif | ||
| 24 | |||
| 25 | void ack_bad_irq(unsigned int irq); | ||
| 26 | |||
| 27 | #endif /* __M68K_HARDIRQ_H */ | ||
diff --git a/arch/m68k/include/asm/hp300hw.h b/arch/m68k/include/asm/hp300hw.h new file mode 100644 index 000000000000..d998ea67c19c --- /dev/null +++ b/arch/m68k/include/asm/hp300hw.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | #ifndef _M68K_HP300HW_H | ||
| 2 | #define _M68K_HP300HW_H | ||
| 3 | |||
| 4 | extern unsigned long hp300_model; | ||
| 5 | |||
| 6 | /* This information was taken from NetBSD */ | ||
| 7 | #define HP_320 (0) /* 16MHz 68020+HP MMU+16K external cache */ | ||
| 8 | #define HP_330 (1) /* 16MHz 68020+68851 MMU */ | ||
| 9 | #define HP_340 (2) /* 16MHz 68030 */ | ||
| 10 | #define HP_345 (3) /* 50MHz 68030+32K external cache */ | ||
| 11 | #define HP_350 (4) /* 25MHz 68020+HP MMU+32K external cache */ | ||
| 12 | #define HP_360 (5) /* 25MHz 68030 */ | ||
| 13 | #define HP_370 (6) /* 33MHz 68030+64K external cache */ | ||
| 14 | #define HP_375 (7) /* 50MHz 68030+32K external cache */ | ||
| 15 | #define HP_380 (8) /* 25MHz 68040 */ | ||
| 16 | #define HP_385 (9) /* 33MHz 68040 */ | ||
| 17 | |||
| 18 | #define HP_400 (10) /* 50MHz 68030+32K external cache */ | ||
| 19 | #define HP_425T (11) /* 25MHz 68040 - model 425t */ | ||
| 20 | #define HP_425S (12) /* 25MHz 68040 - model 425s */ | ||
| 21 | #define HP_425E (13) /* 25MHz 68040 - model 425e */ | ||
| 22 | #define HP_433T (14) /* 33MHz 68040 - model 433t */ | ||
| 23 | #define HP_433S (15) /* 33MHz 68040 - model 433s */ | ||
| 24 | |||
| 25 | #endif /* _M68K_HP300HW_H */ | ||
diff --git a/arch/m68k/include/asm/hw_irq.h b/arch/m68k/include/asm/hw_irq.h new file mode 100644 index 000000000000..e19526015890 --- /dev/null +++ b/arch/m68k/include/asm/hw_irq.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "hw_irq_no.h" | ||
| 3 | #else | ||
| 4 | #include "hw_irq_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/hw_irq_mm.h b/arch/m68k/include/asm/hw_irq_mm.h new file mode 100644 index 000000000000..eacef0951fbf --- /dev/null +++ b/arch/m68k/include/asm/hw_irq_mm.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef __ASM_M68K_HW_IRQ_H | ||
| 2 | #define __ASM_M68K_HW_IRQ_H | ||
| 3 | |||
| 4 | /* Dummy include. */ | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/m68k/include/asm/hw_irq_no.h b/arch/m68k/include/asm/hw_irq_no.h new file mode 100644 index 000000000000..f3ec9e5ae049 --- /dev/null +++ b/arch/m68k/include/asm/hw_irq_no.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef __M68KNOMMU_HW_IRQ_H__ | ||
| 2 | #define __M68KNOMMU_HW_IRQ_H__ | ||
| 3 | |||
| 4 | #endif /* __M68KNOMMU_HW_IRQ_H__ */ | ||
diff --git a/arch/m68k/include/asm/hwtest.h b/arch/m68k/include/asm/hwtest.h new file mode 100644 index 000000000000..402c8a4401fe --- /dev/null +++ b/arch/m68k/include/asm/hwtest.h | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | /* Routines to test for presence/absence of hardware registers: | ||
| 2 | * see arch/m68k/mm/hwtest.c. | ||
| 3 | * -- PMM <pmaydell@chiark.greenend.org.uk> 05/1998 | ||
| 4 | * | ||
| 5 | * Removed __init from decls. We might want them in modules, and | ||
| 6 | * the code is tiny anyway. 16/5/98 pb | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_HWTEST_H | ||
| 10 | #define __ASM_HWTEST_H | ||
| 11 | |||
| 12 | extern int hwreg_present(volatile void *regp); | ||
| 13 | extern int hwreg_write(volatile void *regp, unsigned short val); | ||
| 14 | |||
| 15 | #endif | ||
diff --git a/arch/m68k/include/asm/ide.h b/arch/m68k/include/asm/ide.h new file mode 100644 index 000000000000..b996a3c8cff5 --- /dev/null +++ b/arch/m68k/include/asm/ide.h | |||
| @@ -0,0 +1,130 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-m68k/ide.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1994-1996 Linus Torvalds & authors | ||
| 5 | */ | ||
| 6 | |||
| 7 | /* Copyright(c) 1996 Kars de Jong */ | ||
| 8 | /* Based on the ide driver from 1.2.13pl8 */ | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Credits (alphabetical): | ||
| 12 | * | ||
| 13 | * - Bjoern Brauel | ||
| 14 | * - Kars de Jong | ||
| 15 | * - Torsten Ebeling | ||
| 16 | * - Dwight Engen | ||
| 17 | * - Thorsten Floeck | ||
| 18 | * - Roman Hodek | ||
| 19 | * - Guenther Kelleter | ||
| 20 | * - Chris Lawrence | ||
| 21 | * - Michael Rausch | ||
| 22 | * - Christian Sauer | ||
| 23 | * - Michael Schmitz | ||
| 24 | * - Jes Soerensen | ||
| 25 | * - Michael Thurm | ||
| 26 | * - Geert Uytterhoeven | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef _M68K_IDE_H | ||
| 30 | #define _M68K_IDE_H | ||
| 31 | |||
| 32 | #ifdef __KERNEL__ | ||
| 33 | |||
| 34 | |||
| 35 | #include <asm/setup.h> | ||
| 36 | #include <asm/io.h> | ||
| 37 | #include <asm/irq.h> | ||
| 38 | |||
| 39 | #ifdef CONFIG_ATARI | ||
| 40 | #include <linux/interrupt.h> | ||
| 41 | #include <asm/atari_stdma.h> | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #ifdef CONFIG_MAC | ||
| 45 | #include <asm/macints.h> | ||
| 46 | #endif | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Get rid of defs from io.h - ide has its private and conflicting versions | ||
| 50 | * Since so far no single m68k platform uses ISA/PCI I/O space for IDE, we | ||
| 51 | * always use the `raw' MMIO versions | ||
| 52 | */ | ||
| 53 | #undef inb | ||
| 54 | #undef inw | ||
| 55 | #undef insw | ||
| 56 | #undef inl | ||
| 57 | #undef insl | ||
| 58 | #undef outb | ||
| 59 | #undef outw | ||
| 60 | #undef outsw | ||
| 61 | #undef outl | ||
| 62 | #undef outsl | ||
| 63 | #undef readb | ||
| 64 | #undef readw | ||
| 65 | #undef readl | ||
| 66 | #undef writeb | ||
| 67 | #undef writew | ||
| 68 | #undef writel | ||
| 69 | |||
| 70 | #define inb in_8 | ||
| 71 | #define inw in_be16 | ||
| 72 | #define insw(port, addr, n) raw_insw((u16 *)port, addr, n) | ||
| 73 | #define inl in_be32 | ||
| 74 | #define insl(port, addr, n) raw_insl((u32 *)port, addr, n) | ||
| 75 | #define outb(val, port) out_8(port, val) | ||
| 76 | #define outw(val, port) out_be16(port, val) | ||
| 77 | #define outsw(port, addr, n) raw_outsw((u16 *)port, addr, n) | ||
| 78 | #define outl(val, port) out_be32(port, val) | ||
| 79 | #define outsl(port, addr, n) raw_outsl((u32 *)port, addr, n) | ||
| 80 | #define readb in_8 | ||
| 81 | #define readw in_be16 | ||
| 82 | #define __ide_mm_insw(port, addr, n) raw_insw((u16 *)port, addr, n) | ||
| 83 | #define readl in_be32 | ||
| 84 | #define __ide_mm_insl(port, addr, n) raw_insl((u32 *)port, addr, n) | ||
| 85 | #define writeb(val, port) out_8(port, val) | ||
| 86 | #define writew(val, port) out_be16(port, val) | ||
| 87 | #define __ide_mm_outsw(port, addr, n) raw_outsw((u16 *)port, addr, n) | ||
| 88 | #define writel(val, port) out_be32(port, val) | ||
| 89 | #define __ide_mm_outsl(port, addr, n) raw_outsl((u32 *)port, addr, n) | ||
| 90 | #if defined(CONFIG_ATARI) || defined(CONFIG_Q40) | ||
| 91 | #define insw_swapw(port, addr, n) raw_insw_swapw((u16 *)port, addr, n) | ||
| 92 | #define outsw_swapw(port, addr, n) raw_outsw_swapw((u16 *)port, addr, n) | ||
| 93 | #endif | ||
| 94 | |||
| 95 | #ifdef CONFIG_BLK_DEV_FALCON_IDE | ||
| 96 | #define IDE_ARCH_LOCK | ||
| 97 | |||
| 98 | extern int falconide_intr_lock; | ||
| 99 | |||
| 100 | static __inline__ void ide_release_lock (void) | ||
| 101 | { | ||
| 102 | if (MACH_IS_ATARI) { | ||
| 103 | if (falconide_intr_lock == 0) { | ||
| 104 | printk("ide_release_lock: bug\n"); | ||
| 105 | return; | ||
| 106 | } | ||
| 107 | falconide_intr_lock = 0; | ||
| 108 | stdma_release(); | ||
| 109 | } | ||
| 110 | } | ||
| 111 | |||
| 112 | static __inline__ void | ||
| 113 | ide_get_lock(irq_handler_t handler, void *data) | ||
| 114 | { | ||
| 115 | if (MACH_IS_ATARI) { | ||
| 116 | if (falconide_intr_lock == 0) { | ||
| 117 | if (in_interrupt() > 0) | ||
| 118 | panic( "Falcon IDE hasn't ST-DMA lock in interrupt" ); | ||
| 119 | stdma_lock(handler, data); | ||
| 120 | falconide_intr_lock = 1; | ||
| 121 | } | ||
| 122 | } | ||
| 123 | } | ||
| 124 | #endif /* CONFIG_BLK_DEV_FALCON_IDE */ | ||
| 125 | |||
| 126 | #define IDE_ARCH_ACK_INTR | ||
| 127 | #define ide_ack_intr(hwif) ((hwif)->ack_intr ? (hwif)->ack_intr(hwif) : 1) | ||
| 128 | |||
| 129 | #endif /* __KERNEL__ */ | ||
| 130 | #endif /* _M68K_IDE_H */ | ||
diff --git a/arch/m68k/include/asm/idprom.h b/arch/m68k/include/asm/idprom.h new file mode 100644 index 000000000000..160616a89e05 --- /dev/null +++ b/arch/m68k/include/asm/idprom.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | #ifndef _M68K_IDPROM_H | ||
| 2 | #define _M68K_IDPROM_H | ||
| 3 | /* | ||
| 4 | * idprom.h: Macros and defines for idprom routines | ||
| 5 | * | ||
| 6 | * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/types.h> | ||
| 10 | |||
| 11 | struct idprom { | ||
| 12 | u8 id_format; /* Format identifier (always 0x01) */ | ||
| 13 | u8 id_machtype; /* Machine type */ | ||
| 14 | u8 id_ethaddr[6]; /* Hardware ethernet address */ | ||
| 15 | s32 id_date; /* Date of manufacture */ | ||
| 16 | u32 id_sernum:24; /* Unique serial number */ | ||
| 17 | u8 id_cksum; /* Checksum - xor of the data bytes */ | ||
| 18 | u8 reserved[16]; | ||
| 19 | }; | ||
| 20 | |||
| 21 | extern struct idprom *idprom; | ||
| 22 | extern void idprom_init(void); | ||
| 23 | |||
| 24 | /* Sun3: in control space */ | ||
| 25 | #define SUN3_IDPROM_BASE 0x00000000 | ||
| 26 | |||
| 27 | #endif /* !(_M68K_IDPROM_H) */ | ||
diff --git a/arch/m68k/include/asm/intersil.h b/arch/m68k/include/asm/intersil.h new file mode 100644 index 000000000000..f482902cac8a --- /dev/null +++ b/arch/m68k/include/asm/intersil.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | #ifndef _SUN3_INTERSIL_H | ||
| 2 | #define _SUN3_INTERSIL_H | ||
| 3 | /* bits 0 and 1 */ | ||
| 4 | #define INTERSIL_FREQ_32K 0x00 | ||
| 5 | #define INTERSIL_FREQ_1M 0x01 | ||
| 6 | #define INTERSIL_FREQ_2M 0x02 | ||
| 7 | #define INTERSIL_FREQ_4M 0x03 | ||
| 8 | |||
| 9 | /* bit 2 */ | ||
| 10 | #define INTERSIL_12H_MODE 0x00 | ||
| 11 | #define INTERSIL_24H_MODE 0x04 | ||
| 12 | |||
| 13 | /* bit 3 */ | ||
| 14 | #define INTERSIL_STOP 0x00 | ||
| 15 | #define INTERSIL_RUN 0x08 | ||
| 16 | |||
| 17 | /* bit 4 */ | ||
| 18 | #define INTERSIL_INT_ENABLE 0x10 | ||
| 19 | #define INTERSIL_INT_DISABLE 0x00 | ||
| 20 | |||
| 21 | /* bit 5 */ | ||
| 22 | #define INTERSIL_MODE_NORMAL 0x00 | ||
| 23 | #define INTERSIL_MODE_TEST 0x20 | ||
| 24 | |||
| 25 | #define INTERSIL_HZ_100_MASK 0x02 | ||
| 26 | |||
| 27 | struct intersil_dt { | ||
| 28 | unsigned char csec; | ||
| 29 | unsigned char hour; | ||
| 30 | unsigned char minute; | ||
| 31 | unsigned char second; | ||
| 32 | unsigned char month; | ||
| 33 | unsigned char day; | ||
| 34 | unsigned char year; | ||
| 35 | unsigned char weekday; | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct intersil_7170 { | ||
| 39 | struct intersil_dt counter; | ||
| 40 | struct intersil_dt alarm; | ||
| 41 | unsigned char int_reg; | ||
| 42 | unsigned char cmd_reg; | ||
| 43 | }; | ||
| 44 | |||
| 45 | extern volatile char* clock_va; | ||
| 46 | #define intersil_clock ((volatile struct intersil_7170 *) clock_va) | ||
| 47 | #define intersil_clear() (void)intersil_clock->int_reg | ||
| 48 | #endif | ||
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h new file mode 100644 index 000000000000..c7210ba184ea --- /dev/null +++ b/arch/m68k/include/asm/io.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "io_no.h" | ||
| 3 | #else | ||
| 4 | #include "io_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h new file mode 100644 index 000000000000..9e673e3bd434 --- /dev/null +++ b/arch/m68k/include/asm/io_mm.h | |||
| @@ -0,0 +1,369 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-m68k/io.h | ||
| 3 | * | ||
| 4 | * 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other | ||
| 5 | * IO access | ||
| 6 | * - added Q40 support | ||
| 7 | * - added skeleton for GG-II and Amiga PCMCIA | ||
| 8 | * 2/3/01 RZ: - moved a few more defs into raw_io.h | ||
| 9 | * | ||
| 10 | * inX/outX should not be used by any driver unless it does | ||
| 11 | * ISA access. Other drivers should use function defined in raw_io.h | ||
| 12 | * or define its own macros on top of these. | ||
| 13 | * | ||
| 14 | * inX(),outX() are for ISA I/O | ||
| 15 | * isa_readX(),isa_writeX() are for ISA memory | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef _IO_H | ||
| 19 | #define _IO_H | ||
| 20 | |||
| 21 | #ifdef __KERNEL__ | ||
| 22 | |||
| 23 | #include <linux/compiler.h> | ||
| 24 | #include <asm/raw_io.h> | ||
| 25 | #include <asm/virtconvert.h> | ||
| 26 | |||
| 27 | #include <asm-generic/iomap.h> | ||
| 28 | |||
| 29 | #ifdef CONFIG_ATARI | ||
| 30 | #include <asm/atarihw.h> | ||
| 31 | #endif | ||
| 32 | |||
| 33 | |||
| 34 | /* | ||
| 35 | * IO/MEM definitions for various ISA bridges | ||
| 36 | */ | ||
| 37 | |||
| 38 | |||
| 39 | #ifdef CONFIG_Q40 | ||
| 40 | |||
| 41 | #define q40_isa_io_base 0xff400000 | ||
| 42 | #define q40_isa_mem_base 0xff800000 | ||
| 43 | |||
| 44 | #define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr))) | ||
| 45 | #define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr))) | ||
| 46 | #define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr))) | ||
| 47 | #define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr))) | ||
| 48 | |||
| 49 | #define MULTI_ISA 0 | ||
| 50 | #endif /* Q40 */ | ||
| 51 | |||
| 52 | /* GG-II Zorro to ISA bridge */ | ||
| 53 | #ifdef CONFIG_GG2 | ||
| 54 | |||
| 55 | extern unsigned long gg2_isa_base; | ||
| 56 | #define GG2_ISA_IO_B(ioaddr) (gg2_isa_base+1+((unsigned long)(ioaddr)*4)) | ||
| 57 | #define GG2_ISA_IO_W(ioaddr) (gg2_isa_base+ ((unsigned long)(ioaddr)*4)) | ||
| 58 | #define GG2_ISA_MEM_B(madr) (gg2_isa_base+1+(((unsigned long)(madr)*4) & 0xfffff)) | ||
| 59 | #define GG2_ISA_MEM_W(madr) (gg2_isa_base+ (((unsigned long)(madr)*4) & 0xfffff)) | ||
| 60 | |||
| 61 | #ifndef MULTI_ISA | ||
| 62 | #define MULTI_ISA 0 | ||
| 63 | #else | ||
| 64 | #undef MULTI_ISA | ||
| 65 | #define MULTI_ISA 1 | ||
| 66 | #endif | ||
| 67 | #endif /* GG2 */ | ||
| 68 | |||
| 69 | #ifdef CONFIG_AMIGA_PCMCIA | ||
| 70 | #include <asm/amigayle.h> | ||
| 71 | |||
| 72 | #define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) ) | ||
| 73 | #define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) ) | ||
| 74 | |||
| 75 | #ifndef MULTI_ISA | ||
| 76 | #define MULTI_ISA 0 | ||
| 77 | #else | ||
| 78 | #undef MULTI_ISA | ||
| 79 | #define MULTI_ISA 1 | ||
| 80 | #endif | ||
| 81 | #endif /* AMIGA_PCMCIA */ | ||
| 82 | |||
| 83 | |||
| 84 | |||
| 85 | #ifdef CONFIG_ISA | ||
| 86 | |||
| 87 | #if MULTI_ISA == 0 | ||
| 88 | #undef MULTI_ISA | ||
| 89 | #endif | ||
| 90 | |||
| 91 | #define ISA_TYPE_Q40 (1) | ||
| 92 | #define ISA_TYPE_GG2 (2) | ||
| 93 | #define ISA_TYPE_AG (3) | ||
| 94 | |||
| 95 | #if defined(CONFIG_Q40) && !defined(MULTI_ISA) | ||
| 96 | #define ISA_TYPE ISA_TYPE_Q40 | ||
| 97 | #define ISA_SEX 0 | ||
| 98 | #endif | ||
| 99 | #if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA) | ||
| 100 | #define ISA_TYPE ISA_TYPE_AG | ||
| 101 | #define ISA_SEX 1 | ||
| 102 | #endif | ||
| 103 | #if defined(CONFIG_GG2) && !defined(MULTI_ISA) | ||
| 104 | #define ISA_TYPE ISA_TYPE_GG2 | ||
| 105 | #define ISA_SEX 0 | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #ifdef MULTI_ISA | ||
| 109 | extern int isa_type; | ||
| 110 | extern int isa_sex; | ||
| 111 | |||
| 112 | #define ISA_TYPE isa_type | ||
| 113 | #define ISA_SEX isa_sex | ||
| 114 | #endif | ||
| 115 | |||
| 116 | /* | ||
| 117 | * define inline addr translation functions. Normally only one variant will | ||
| 118 | * be compiled in so the case statement will be optimised away | ||
| 119 | */ | ||
| 120 | |||
| 121 | static inline u8 __iomem *isa_itb(unsigned long addr) | ||
| 122 | { | ||
| 123 | switch(ISA_TYPE) | ||
| 124 | { | ||
| 125 | #ifdef CONFIG_Q40 | ||
| 126 | case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr); | ||
| 127 | #endif | ||
| 128 | #ifdef CONFIG_GG2 | ||
| 129 | case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_IO_B(addr); | ||
| 130 | #endif | ||
| 131 | #ifdef CONFIG_AMIGA_PCMCIA | ||
| 132 | case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr); | ||
| 133 | #endif | ||
| 134 | default: return NULL; /* avoid warnings, just in case */ | ||
| 135 | } | ||
| 136 | } | ||
| 137 | static inline u16 __iomem *isa_itw(unsigned long addr) | ||
| 138 | { | ||
| 139 | switch(ISA_TYPE) | ||
| 140 | { | ||
| 141 | #ifdef CONFIG_Q40 | ||
| 142 | case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr); | ||
| 143 | #endif | ||
| 144 | #ifdef CONFIG_GG2 | ||
| 145 | case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_IO_W(addr); | ||
| 146 | #endif | ||
| 147 | #ifdef CONFIG_AMIGA_PCMCIA | ||
| 148 | case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr); | ||
| 149 | #endif | ||
| 150 | default: return NULL; /* avoid warnings, just in case */ | ||
| 151 | } | ||
| 152 | } | ||
| 153 | static inline u32 __iomem *isa_itl(unsigned long addr) | ||
| 154 | { | ||
| 155 | switch(ISA_TYPE) | ||
| 156 | { | ||
| 157 | #ifdef CONFIG_AMIGA_PCMCIA | ||
| 158 | case ISA_TYPE_AG: return (u32 __iomem *)AG_ISA_IO_W(addr); | ||
| 159 | #endif | ||
| 160 | default: return 0; /* avoid warnings, just in case */ | ||
| 161 | } | ||
| 162 | } | ||
| 163 | static inline u8 __iomem *isa_mtb(unsigned long addr) | ||
| 164 | { | ||
| 165 | switch(ISA_TYPE) | ||
| 166 | { | ||
| 167 | #ifdef CONFIG_Q40 | ||
| 168 | case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr); | ||
| 169 | #endif | ||
| 170 | #ifdef CONFIG_GG2 | ||
| 171 | case ISA_TYPE_GG2: return (u8 __iomem *)GG2_ISA_MEM_B(addr); | ||
| 172 | #endif | ||
| 173 | #ifdef CONFIG_AMIGA_PCMCIA | ||
| 174 | case ISA_TYPE_AG: return (u8 __iomem *)addr; | ||
| 175 | #endif | ||
| 176 | default: return NULL; /* avoid warnings, just in case */ | ||
| 177 | } | ||
| 178 | } | ||
| 179 | static inline u16 __iomem *isa_mtw(unsigned long addr) | ||
| 180 | { | ||
| 181 | switch(ISA_TYPE) | ||
| 182 | { | ||
| 183 | #ifdef CONFIG_Q40 | ||
| 184 | case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr); | ||
| 185 | #endif | ||
| 186 | #ifdef CONFIG_GG2 | ||
| 187 | case ISA_TYPE_GG2: return (u16 __iomem *)GG2_ISA_MEM_W(addr); | ||
| 188 | #endif | ||
| 189 | #ifdef CONFIG_AMIGA_PCMCIA | ||
| 190 | case ISA_TYPE_AG: return (u16 __iomem *)addr; | ||
| 191 | #endif | ||
| 192 | default: return NULL; /* avoid warnings, just in case */ | ||
| 193 | } | ||
| 194 | } | ||
| 195 | |||
| 196 | |||
| 197 | #define isa_inb(port) in_8(isa_itb(port)) | ||
| 198 | #define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port))) | ||
| 199 | #define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port))) | ||
| 200 | #define isa_outb(val,port) out_8(isa_itb(port),(val)) | ||
| 201 | #define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val))) | ||
| 202 | #define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val))) | ||
| 203 | |||
| 204 | #define isa_readb(p) in_8(isa_mtb((unsigned long)(p))) | ||
| 205 | #define isa_readw(p) \ | ||
| 206 | (ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \ | ||
| 207 | : in_le16(isa_mtw((unsigned long)(p)))) | ||
| 208 | #define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val)) | ||
| 209 | #define isa_writew(val,p) \ | ||
| 210 | (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \ | ||
| 211 | : out_le16(isa_mtw((unsigned long)(p)),(val))) | ||
| 212 | |||
| 213 | static inline void isa_delay(void) | ||
| 214 | { | ||
| 215 | switch(ISA_TYPE) | ||
| 216 | { | ||
| 217 | #ifdef CONFIG_Q40 | ||
| 218 | case ISA_TYPE_Q40: isa_outb(0,0x80); break; | ||
| 219 | #endif | ||
| 220 | #ifdef CONFIG_GG2 | ||
| 221 | case ISA_TYPE_GG2: break; | ||
| 222 | #endif | ||
| 223 | #ifdef CONFIG_AMIGA_PCMCIA | ||
| 224 | case ISA_TYPE_AG: break; | ||
| 225 | #endif | ||
| 226 | default: break; /* avoid warnings */ | ||
| 227 | } | ||
| 228 | } | ||
| 229 | |||
| 230 | #define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;}) | ||
| 231 | #define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();}) | ||
| 232 | #define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;}) | ||
| 233 | #define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();}) | ||
| 234 | #define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;}) | ||
| 235 | #define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();}) | ||
| 236 | |||
| 237 | #define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr)) | ||
| 238 | #define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr)) | ||
| 239 | |||
| 240 | #define isa_insw(port, buf, nr) \ | ||
| 241 | (ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) : \ | ||
| 242 | raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr))) | ||
| 243 | |||
| 244 | #define isa_outsw(port, buf, nr) \ | ||
| 245 | (ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \ | ||
| 246 | raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr))) | ||
| 247 | |||
| 248 | #define isa_insl(port, buf, nr) \ | ||
| 249 | (ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \ | ||
| 250 | raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1)) | ||
| 251 | |||
| 252 | #define isa_outsl(port, buf, nr) \ | ||
| 253 | (ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \ | ||
| 254 | raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1)) | ||
| 255 | |||
| 256 | |||
| 257 | #define inb isa_inb | ||
| 258 | #define inb_p isa_inb_p | ||
| 259 | #define outb isa_outb | ||
| 260 | #define outb_p isa_outb_p | ||
| 261 | #define inw isa_inw | ||
| 262 | #define inw_p isa_inw_p | ||
| 263 | #define outw isa_outw | ||
| 264 | #define outw_p isa_outw_p | ||
| 265 | #define inl isa_inl | ||
| 266 | #define inl_p isa_inl_p | ||
| 267 | #define outl isa_outl | ||
| 268 | #define outl_p isa_outl_p | ||
| 269 | #define insb isa_insb | ||
| 270 | #define insw isa_insw | ||
| 271 | #define insl isa_insl | ||
| 272 | #define outsb isa_outsb | ||
| 273 | #define outsw isa_outsw | ||
| 274 | #define outsl isa_outsl | ||
| 275 | #define readb isa_readb | ||
| 276 | #define readw isa_readw | ||
| 277 | #define writeb isa_writeb | ||
| 278 | #define writew isa_writew | ||
| 279 | |||
| 280 | #else /* CONFIG_ISA */ | ||
| 281 | |||
| 282 | /* | ||
| 283 | * We need to define dummy functions for GENERIC_IOMAP support. | ||
| 284 | */ | ||
| 285 | #define inb(port) 0xff | ||
| 286 | #define inb_p(port) 0xff | ||
| 287 | #define outb(val,port) ((void)0) | ||
| 288 | #define outb_p(val,port) ((void)0) | ||
| 289 | #define inw(port) 0xffff | ||
| 290 | #define outw(val,port) ((void)0) | ||
| 291 | #define inl(port) 0xffffffffUL | ||
| 292 | #define outl(val,port) ((void)0) | ||
| 293 | |||
| 294 | #define insb(port,buf,nr) ((void)0) | ||
| 295 | #define outsb(port,buf,nr) ((void)0) | ||
| 296 | #define insw(port,buf,nr) ((void)0) | ||
| 297 | #define outsw(port,buf,nr) ((void)0) | ||
| 298 | #define insl(port,buf,nr) ((void)0) | ||
| 299 | #define outsl(port,buf,nr) ((void)0) | ||
| 300 | |||
| 301 | /* | ||
| 302 | * These should be valid on any ioremap()ed region | ||
| 303 | */ | ||
| 304 | #define readb(addr) in_8(addr) | ||
| 305 | #define writeb(val,addr) out_8((addr),(val)) | ||
| 306 | #define readw(addr) in_le16(addr) | ||
| 307 | #define writew(val,addr) out_le16((addr),(val)) | ||
| 308 | |||
| 309 | #endif /* CONFIG_ISA */ | ||
| 310 | |||
| 311 | #define readl(addr) in_le32(addr) | ||
| 312 | #define writel(val,addr) out_le32((addr),(val)) | ||
| 313 | |||
| 314 | #define mmiowb() | ||
| 315 | |||
| 316 | static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size) | ||
| 317 | { | ||
| 318 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
| 319 | } | ||
| 320 | static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size) | ||
| 321 | { | ||
| 322 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
| 323 | } | ||
| 324 | static inline void __iomem *ioremap_writethrough(unsigned long physaddr, | ||
| 325 | unsigned long size) | ||
| 326 | { | ||
| 327 | return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); | ||
| 328 | } | ||
| 329 | static inline void __iomem *ioremap_fullcache(unsigned long physaddr, | ||
| 330 | unsigned long size) | ||
| 331 | { | ||
| 332 | return __ioremap(physaddr, size, IOMAP_FULL_CACHING); | ||
| 333 | } | ||
| 334 | |||
| 335 | static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) | ||
| 336 | { | ||
| 337 | __builtin_memset((void __force *) addr, val, count); | ||
| 338 | } | ||
| 339 | static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) | ||
| 340 | { | ||
| 341 | __builtin_memcpy(dst, (void __force *) src, count); | ||
| 342 | } | ||
| 343 | static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) | ||
| 344 | { | ||
| 345 | __builtin_memcpy((void __force *) dst, src, count); | ||
| 346 | } | ||
| 347 | |||
| 348 | #ifndef CONFIG_SUN3 | ||
| 349 | #define IO_SPACE_LIMIT 0xffff | ||
| 350 | #else | ||
| 351 | #define IO_SPACE_LIMIT 0x0fffffff | ||
| 352 | #endif | ||
| 353 | |||
| 354 | #endif /* __KERNEL__ */ | ||
| 355 | |||
| 356 | #define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1 | ||
| 357 | |||
| 358 | /* | ||
| 359 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
| 360 | * access | ||
| 361 | */ | ||
| 362 | #define xlate_dev_mem_ptr(p) __va(p) | ||
| 363 | |||
| 364 | /* | ||
| 365 | * Convert a virtual cached pointer to an uncached pointer | ||
| 366 | */ | ||
| 367 | #define xlate_dev_kmem_ptr(p) p | ||
| 368 | |||
| 369 | #endif /* _IO_H */ | ||
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h new file mode 100644 index 000000000000..6adef1ee2082 --- /dev/null +++ b/arch/m68k/include/asm/io_no.h | |||
| @@ -0,0 +1,194 @@ | |||
| 1 | #ifndef _M68KNOMMU_IO_H | ||
| 2 | #define _M68KNOMMU_IO_H | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ | ||
| 5 | |||
| 6 | |||
| 7 | /* | ||
| 8 | * These are for ISA/PCI shared memory _only_ and should never be used | ||
| 9 | * on any other type of memory, including Zorro memory. They are meant to | ||
| 10 | * access the bus in the bus byte order which is little-endian!. | ||
| 11 | * | ||
| 12 | * readX/writeX() are used to access memory mapped devices. On some | ||
| 13 | * architectures the memory mapped IO stuff needs to be accessed | ||
| 14 | * differently. On the m68k architecture, we just read/write the | ||
| 15 | * memory location directly. | ||
| 16 | */ | ||
| 17 | /* ++roman: The assignments to temp. vars avoid that gcc sometimes generates | ||
| 18 | * two accesses to memory, which may be undesireable for some devices. | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * swap functions are sometimes needed to interface little-endian hardware | ||
| 23 | */ | ||
| 24 | static inline unsigned short _swapw(volatile unsigned short v) | ||
| 25 | { | ||
| 26 | return ((v << 8) | (v >> 8)); | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline unsigned int _swapl(volatile unsigned long v) | ||
| 30 | { | ||
| 31 | return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24)); | ||
| 32 | } | ||
| 33 | |||
| 34 | #define readb(addr) \ | ||
| 35 | ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) | ||
| 36 | #define readw(addr) \ | ||
| 37 | ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) | ||
| 38 | #define readl(addr) \ | ||
| 39 | ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) | ||
| 40 | |||
| 41 | #define readb_relaxed(addr) readb(addr) | ||
| 42 | #define readw_relaxed(addr) readw(addr) | ||
| 43 | #define readl_relaxed(addr) readl(addr) | ||
| 44 | |||
| 45 | #define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) | ||
| 46 | #define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) | ||
| 47 | #define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) | ||
| 48 | |||
| 49 | #define __raw_readb readb | ||
| 50 | #define __raw_readw readw | ||
| 51 | #define __raw_readl readl | ||
| 52 | #define __raw_writeb writeb | ||
| 53 | #define __raw_writew writew | ||
| 54 | #define __raw_writel writel | ||
| 55 | |||
| 56 | static inline void io_outsb(unsigned int addr, void *buf, int len) | ||
| 57 | { | ||
| 58 | volatile unsigned char *ap = (volatile unsigned char *) addr; | ||
| 59 | unsigned char *bp = (unsigned char *) buf; | ||
| 60 | while (len--) | ||
| 61 | *ap = *bp++; | ||
| 62 | } | ||
| 63 | |||
| 64 | static inline void io_outsw(unsigned int addr, void *buf, int len) | ||
| 65 | { | ||
| 66 | volatile unsigned short *ap = (volatile unsigned short *) addr; | ||
| 67 | unsigned short *bp = (unsigned short *) buf; | ||
| 68 | while (len--) | ||
| 69 | *ap = _swapw(*bp++); | ||
| 70 | } | ||
| 71 | |||
| 72 | static inline void io_outsl(unsigned int addr, void *buf, int len) | ||
| 73 | { | ||
| 74 | volatile unsigned int *ap = (volatile unsigned int *) addr; | ||
| 75 | unsigned int *bp = (unsigned int *) buf; | ||
| 76 | while (len--) | ||
| 77 | *ap = _swapl(*bp++); | ||
| 78 | } | ||
| 79 | |||
| 80 | static inline void io_insb(unsigned int addr, void *buf, int len) | ||
| 81 | { | ||
| 82 | volatile unsigned char *ap = (volatile unsigned char *) addr; | ||
| 83 | unsigned char *bp = (unsigned char *) buf; | ||
| 84 | while (len--) | ||
| 85 | *bp++ = *ap; | ||
| 86 | } | ||
| 87 | |||
| 88 | static inline void io_insw(unsigned int addr, void *buf, int len) | ||
| 89 | { | ||
| 90 | volatile unsigned short *ap = (volatile unsigned short *) addr; | ||
| 91 | unsigned short *bp = (unsigned short *) buf; | ||
| 92 | while (len--) | ||
| 93 | *bp++ = _swapw(*ap); | ||
| 94 | } | ||
| 95 | |||
| 96 | static inline void io_insl(unsigned int addr, void *buf, int len) | ||
| 97 | { | ||
| 98 | volatile unsigned int *ap = (volatile unsigned int *) addr; | ||
| 99 | unsigned int *bp = (unsigned int *) buf; | ||
| 100 | while (len--) | ||
| 101 | *bp++ = _swapl(*ap); | ||
| 102 | } | ||
| 103 | |||
| 104 | #define mmiowb() | ||
| 105 | |||
| 106 | /* | ||
| 107 | * make the short names macros so specific devices | ||
| 108 | * can override them as required | ||
| 109 | */ | ||
| 110 | |||
| 111 | #define memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
| 112 | #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
| 113 | #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
| 114 | |||
| 115 | #define inb(addr) readb(addr) | ||
| 116 | #define inw(addr) readw(addr) | ||
| 117 | #define inl(addr) readl(addr) | ||
| 118 | #define outb(x,addr) ((void) writeb(x,addr)) | ||
| 119 | #define outw(x,addr) ((void) writew(x,addr)) | ||
| 120 | #define outl(x,addr) ((void) writel(x,addr)) | ||
| 121 | |||
| 122 | #define inb_p(addr) inb(addr) | ||
| 123 | #define inw_p(addr) inw(addr) | ||
| 124 | #define inl_p(addr) inl(addr) | ||
| 125 | #define outb_p(x,addr) outb(x,addr) | ||
| 126 | #define outw_p(x,addr) outw(x,addr) | ||
| 127 | #define outl_p(x,addr) outl(x,addr) | ||
| 128 | |||
| 129 | #define outsb(a,b,l) io_outsb(a,b,l) | ||
| 130 | #define outsw(a,b,l) io_outsw(a,b,l) | ||
| 131 | #define outsl(a,b,l) io_outsl(a,b,l) | ||
| 132 | |||
| 133 | #define insb(a,b,l) io_insb(a,b,l) | ||
| 134 | #define insw(a,b,l) io_insw(a,b,l) | ||
| 135 | #define insl(a,b,l) io_insl(a,b,l) | ||
| 136 | |||
| 137 | #define IO_SPACE_LIMIT 0xffff | ||
| 138 | |||
| 139 | |||
| 140 | /* Values for nocacheflag and cmode */ | ||
| 141 | #define IOMAP_FULL_CACHING 0 | ||
| 142 | #define IOMAP_NOCACHE_SER 1 | ||
| 143 | #define IOMAP_NOCACHE_NONSER 2 | ||
| 144 | #define IOMAP_WRITETHROUGH 3 | ||
| 145 | |||
| 146 | extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); | ||
| 147 | extern void __iounmap(void *addr, unsigned long size); | ||
| 148 | |||
| 149 | static inline void *ioremap(unsigned long physaddr, unsigned long size) | ||
| 150 | { | ||
| 151 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
| 152 | } | ||
| 153 | static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) | ||
| 154 | { | ||
| 155 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
| 156 | } | ||
| 157 | static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) | ||
| 158 | { | ||
| 159 | return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); | ||
| 160 | } | ||
| 161 | static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) | ||
| 162 | { | ||
| 163 | return __ioremap(physaddr, size, IOMAP_FULL_CACHING); | ||
| 164 | } | ||
| 165 | |||
| 166 | extern void iounmap(void *addr); | ||
| 167 | |||
| 168 | /* Pages to physical address... */ | ||
| 169 | #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) | ||
| 170 | #define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) | ||
| 171 | |||
| 172 | /* | ||
| 173 | * Macros used for converting between virtual and physical mappings. | ||
| 174 | */ | ||
| 175 | #define phys_to_virt(vaddr) ((void *) (vaddr)) | ||
| 176 | #define virt_to_phys(vaddr) ((unsigned long) (vaddr)) | ||
| 177 | |||
| 178 | #define virt_to_bus virt_to_phys | ||
| 179 | #define bus_to_virt phys_to_virt | ||
| 180 | |||
| 181 | /* | ||
| 182 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | ||
| 183 | * access | ||
| 184 | */ | ||
| 185 | #define xlate_dev_mem_ptr(p) __va(p) | ||
| 186 | |||
| 187 | /* | ||
| 188 | * Convert a virtual cached pointer to an uncached pointer | ||
| 189 | */ | ||
| 190 | #define xlate_dev_kmem_ptr(p) p | ||
| 191 | |||
| 192 | #endif /* __KERNEL__ */ | ||
| 193 | |||
| 194 | #endif /* _M68KNOMMU_IO_H */ | ||
diff --git a/arch/m68k/include/asm/ioctl.h b/arch/m68k/include/asm/ioctl.h new file mode 100644 index 000000000000..b279fe06dfe5 --- /dev/null +++ b/arch/m68k/include/asm/ioctl.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/ioctl.h> | |||
diff --git a/arch/m68k/include/asm/ioctls.h b/arch/m68k/include/asm/ioctls.h new file mode 100644 index 000000000000..b8d2f4be7fd7 --- /dev/null +++ b/arch/m68k/include/asm/ioctls.h | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | #ifndef __ARCH_M68K_IOCTLS_H__ | ||
| 2 | #define __ARCH_M68K_IOCTLS_H__ | ||
| 3 | |||
| 4 | #include <asm/ioctl.h> | ||
| 5 | |||
| 6 | /* 0x54 is just a magic number to make these relatively unique ('T') */ | ||
| 7 | |||
| 8 | #define TCGETS 0x5401 | ||
| 9 | #define TCSETS 0x5402 | ||
| 10 | #define TCSETSW 0x5403 | ||
| 11 | #define TCSETSF 0x5404 | ||
| 12 | #define TCGETA 0x5405 | ||
| 13 | #define TCSETA 0x5406 | ||
| 14 | #define TCSETAW 0x5407 | ||
| 15 | #define TCSETAF 0x5408 | ||
| 16 | #define TCSBRK 0x5409 | ||
| 17 | #define TCXONC 0x540A | ||
| 18 | #define TCFLSH 0x540B | ||
| 19 | #define TIOCEXCL 0x540C | ||
| 20 | #define TIOCNXCL 0x540D | ||
| 21 | #define TIOCSCTTY 0x540E | ||
| 22 | #define TIOCGPGRP 0x540F | ||
| 23 | #define TIOCSPGRP 0x5410 | ||
| 24 | #define TIOCOUTQ 0x5411 | ||
| 25 | #define TIOCSTI 0x5412 | ||
| 26 | #define TIOCGWINSZ 0x5413 | ||
| 27 | #define TIOCSWINSZ 0x5414 | ||
| 28 | #define TIOCMGET 0x5415 | ||
| 29 | #define TIOCMBIS 0x5416 | ||
| 30 | #define TIOCMBIC 0x5417 | ||
| 31 | #define TIOCMSET 0x5418 | ||
| 32 | #define TIOCGSOFTCAR 0x5419 | ||
| 33 | #define TIOCSSOFTCAR 0x541A | ||
| 34 | #define FIONREAD 0x541B | ||
| 35 | #define TIOCINQ FIONREAD | ||
| 36 | #define TIOCLINUX 0x541C | ||
| 37 | #define TIOCCONS 0x541D | ||
| 38 | #define TIOCGSERIAL 0x541E | ||
| 39 | #define TIOCSSERIAL 0x541F | ||
| 40 | #define TIOCPKT 0x5420 | ||
| 41 | #define FIONBIO 0x5421 | ||
| 42 | #define TIOCNOTTY 0x5422 | ||
| 43 | #define TIOCSETD 0x5423 | ||
| 44 | #define TIOCGETD 0x5424 | ||
| 45 | #define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */ | ||
| 46 | #define TIOCSBRK 0x5427 /* BSD compatibility */ | ||
| 47 | #define TIOCCBRK 0x5428 /* BSD compatibility */ | ||
| 48 | #define TIOCGSID 0x5429 /* Return the session ID of FD */ | ||
| 49 | #define TCGETS2 _IOR('T',0x2A, struct termios2) | ||
| 50 | #define TCSETS2 _IOW('T',0x2B, struct termios2) | ||
| 51 | #define TCSETSW2 _IOW('T',0x2C, struct termios2) | ||
| 52 | #define TCSETSF2 _IOW('T',0x2D, struct termios2) | ||
| 53 | #define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ | ||
| 54 | #define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ | ||
| 55 | |||
| 56 | #define FIONCLEX 0x5450 /* these numbers need to be adjusted. */ | ||
| 57 | #define FIOCLEX 0x5451 | ||
| 58 | #define FIOASYNC 0x5452 | ||
| 59 | #define TIOCSERCONFIG 0x5453 | ||
| 60 | #define TIOCSERGWILD 0x5454 | ||
| 61 | #define TIOCSERSWILD 0x5455 | ||
| 62 | #define TIOCGLCKTRMIOS 0x5456 | ||
| 63 | #define TIOCSLCKTRMIOS 0x5457 | ||
| 64 | #define TIOCSERGSTRUCT 0x5458 /* For debugging only */ | ||
| 65 | #define TIOCSERGETLSR 0x5459 /* Get line status register */ | ||
| 66 | #define TIOCSERGETMULTI 0x545A /* Get multiport config */ | ||
| 67 | #define TIOCSERSETMULTI 0x545B /* Set multiport config */ | ||
| 68 | |||
| 69 | #define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */ | ||
| 70 | #define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */ | ||
| 71 | #define FIOQSIZE 0x545E | ||
| 72 | |||
| 73 | /* Used for packet mode */ | ||
| 74 | #define TIOCPKT_DATA 0 | ||
| 75 | #define TIOCPKT_FLUSHREAD 1 | ||
| 76 | #define TIOCPKT_FLUSHWRITE 2 | ||
| 77 | #define TIOCPKT_STOP 4 | ||
| 78 | #define TIOCPKT_START 8 | ||
| 79 | #define TIOCPKT_NOSTOP 16 | ||
| 80 | #define TIOCPKT_DOSTOP 32 | ||
| 81 | |||
| 82 | #define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ | ||
| 83 | |||
| 84 | #endif /* __ARCH_M68K_IOCTLS_H__ */ | ||
diff --git a/arch/m68k/include/asm/ipcbuf.h b/arch/m68k/include/asm/ipcbuf.h new file mode 100644 index 000000000000..a623ea3f0955 --- /dev/null +++ b/arch/m68k/include/asm/ipcbuf.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #ifndef __m68k_IPCBUF_H__ | ||
| 2 | #define __m68k_IPCBUF_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The user_ipc_perm structure for m68k architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 32-bit mode_t and seq | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct ipc64_perm | ||
| 15 | { | ||
| 16 | __kernel_key_t key; | ||
| 17 | __kernel_uid32_t uid; | ||
| 18 | __kernel_gid32_t gid; | ||
| 19 | __kernel_uid32_t cuid; | ||
| 20 | __kernel_gid32_t cgid; | ||
| 21 | __kernel_mode_t mode; | ||
| 22 | unsigned short __pad1; | ||
| 23 | unsigned short seq; | ||
| 24 | unsigned short __pad2; | ||
| 25 | unsigned long __unused1; | ||
| 26 | unsigned long __unused2; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #endif /* __m68k_IPCBUF_H__ */ | ||
diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h new file mode 100644 index 000000000000..d031416595b2 --- /dev/null +++ b/arch/m68k/include/asm/irq.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "irq_no.h" | ||
| 3 | #else | ||
| 4 | #include "irq_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/irq_mm.h b/arch/m68k/include/asm/irq_mm.h new file mode 100644 index 000000000000..226bfc0f21b1 --- /dev/null +++ b/arch/m68k/include/asm/irq_mm.h | |||
| @@ -0,0 +1,125 @@ | |||
| 1 | #ifndef _M68K_IRQ_H_ | ||
| 2 | #define _M68K_IRQ_H_ | ||
| 3 | |||
| 4 | #include <linux/linkage.h> | ||
| 5 | #include <linux/hardirq.h> | ||
| 6 | #include <linux/spinlock_types.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * This should be the same as the max(NUM_X_SOURCES) for all the | ||
| 10 | * different m68k hosts compiled into the kernel. | ||
| 11 | * Currently the Atari has 72 and the Amiga 24, but if both are | ||
| 12 | * supported in the kernel it is better to make room for 72. | ||
| 13 | */ | ||
| 14 | #if defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X) | ||
| 15 | #define NR_IRQS 200 | ||
| 16 | #elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) | ||
| 17 | #define NR_IRQS 72 | ||
| 18 | #elif defined(CONFIG_Q40) | ||
| 19 | #define NR_IRQS 43 | ||
| 20 | #elif defined(CONFIG_AMIGA) | ||
| 21 | #define NR_IRQS 32 | ||
| 22 | #elif defined(CONFIG_APOLLO) | ||
| 23 | #define NR_IRQS 24 | ||
| 24 | #elif defined(CONFIG_HP300) | ||
| 25 | #define NR_IRQS 8 | ||
| 26 | #else | ||
| 27 | #define NR_IRQS 0 | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* | ||
| 31 | * The hardirq mask has to be large enough to have | ||
| 32 | * space for potentially all IRQ sources in the system | ||
| 33 | * nesting on a single CPU: | ||
| 34 | */ | ||
| 35 | #if (1 << HARDIRQ_BITS) < NR_IRQS | ||
| 36 | # error HARDIRQ_BITS is too low! | ||
| 37 | #endif | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Interrupt source definitions | ||
| 41 | * General interrupt sources are the level 1-7. | ||
| 42 | * Adding an interrupt service routine for one of these sources | ||
| 43 | * results in the addition of that routine to a chain of routines. | ||
| 44 | * Each one is called in succession. Each individual interrupt | ||
| 45 | * service routine should determine if the device associated with | ||
| 46 | * that routine requires service. | ||
| 47 | */ | ||
| 48 | |||
| 49 | #define IRQ_SPURIOUS 0 | ||
| 50 | |||
| 51 | #define IRQ_AUTO_1 1 /* level 1 interrupt */ | ||
| 52 | #define IRQ_AUTO_2 2 /* level 2 interrupt */ | ||
| 53 | #define IRQ_AUTO_3 3 /* level 3 interrupt */ | ||
| 54 | #define IRQ_AUTO_4 4 /* level 4 interrupt */ | ||
| 55 | #define IRQ_AUTO_5 5 /* level 5 interrupt */ | ||
| 56 | #define IRQ_AUTO_6 6 /* level 6 interrupt */ | ||
| 57 | #define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */ | ||
| 58 | |||
| 59 | #define IRQ_USER 8 | ||
| 60 | |||
| 61 | extern unsigned int irq_canonicalize(unsigned int irq); | ||
| 62 | |||
| 63 | struct pt_regs; | ||
| 64 | |||
| 65 | /* | ||
| 66 | * various flags for request_irq() - the Amiga now uses the standard | ||
| 67 | * mechanism like all other architectures - IRQF_DISABLED and | ||
| 68 | * IRQF_SHARED are your friends. | ||
| 69 | */ | ||
| 70 | #ifndef MACH_AMIGA_ONLY | ||
| 71 | #define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */ | ||
| 72 | #define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */ | ||
| 73 | #define IRQ_FLG_FAST (0x0004) | ||
| 74 | #define IRQ_FLG_SLOW (0x0008) | ||
| 75 | #define IRQ_FLG_STD (0x8000) /* internally used */ | ||
| 76 | #endif | ||
| 77 | |||
| 78 | /* | ||
| 79 | * This structure is used to chain together the ISRs for a particular | ||
| 80 | * interrupt source (if it supports chaining). | ||
| 81 | */ | ||
| 82 | typedef struct irq_node { | ||
| 83 | int (*handler)(int, void *); | ||
| 84 | void *dev_id; | ||
| 85 | struct irq_node *next; | ||
| 86 | unsigned long flags; | ||
| 87 | const char *devname; | ||
| 88 | } irq_node_t; | ||
| 89 | |||
| 90 | /* | ||
| 91 | * This structure has only 4 elements for speed reasons | ||
| 92 | */ | ||
| 93 | struct irq_handler { | ||
| 94 | int (*handler)(int, void *); | ||
| 95 | unsigned long flags; | ||
| 96 | void *dev_id; | ||
| 97 | const char *devname; | ||
| 98 | }; | ||
| 99 | |||
| 100 | struct irq_controller { | ||
| 101 | const char *name; | ||
| 102 | spinlock_t lock; | ||
| 103 | int (*startup)(unsigned int irq); | ||
| 104 | void (*shutdown)(unsigned int irq); | ||
| 105 | void (*enable)(unsigned int irq); | ||
| 106 | void (*disable)(unsigned int irq); | ||
| 107 | }; | ||
| 108 | |||
| 109 | extern int m68k_irq_startup(unsigned int); | ||
| 110 | extern void m68k_irq_shutdown(unsigned int); | ||
| 111 | |||
| 112 | /* | ||
| 113 | * This function returns a new irq_node_t | ||
| 114 | */ | ||
| 115 | extern irq_node_t *new_irq_node(void); | ||
| 116 | |||
| 117 | extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int, struct pt_regs *)); | ||
| 118 | extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt, | ||
| 119 | void (*handler)(unsigned int, struct pt_regs *)); | ||
| 120 | extern void m68k_setup_irq_controller(struct irq_controller *, unsigned int, unsigned int); | ||
| 121 | |||
| 122 | asmlinkage void m68k_handle_int(unsigned int); | ||
| 123 | asmlinkage void __m68k_handle_int(unsigned int, struct pt_regs *); | ||
| 124 | |||
| 125 | #endif /* _M68K_IRQ_H_ */ | ||
diff --git a/arch/m68k/include/asm/irq_no.h b/arch/m68k/include/asm/irq_no.h new file mode 100644 index 000000000000..9373c31ac87d --- /dev/null +++ b/arch/m68k/include/asm/irq_no.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | #ifndef _M68KNOMMU_IRQ_H_ | ||
| 2 | #define _M68KNOMMU_IRQ_H_ | ||
| 3 | |||
| 4 | #ifdef CONFIG_COLDFIRE | ||
| 5 | /* | ||
| 6 | * On the ColdFire we keep track of all vectors. That way drivers | ||
| 7 | * can register whatever vector number they wish, and we can deal | ||
| 8 | * with it. | ||
| 9 | */ | ||
| 10 | #define SYS_IRQS 256 | ||
| 11 | #define NR_IRQS SYS_IRQS | ||
| 12 | |||
| 13 | #else | ||
| 14 | |||
| 15 | /* | ||
| 16 | * # of m68k interrupts | ||
| 17 | */ | ||
| 18 | #define SYS_IRQS 8 | ||
| 19 | #define NR_IRQS (24 + SYS_IRQS) | ||
| 20 | |||
| 21 | #endif /* CONFIG_COLDFIRE */ | ||
| 22 | |||
| 23 | |||
| 24 | #define irq_canonicalize(irq) (irq) | ||
| 25 | |||
| 26 | #endif /* _M68KNOMMU_IRQ_H_ */ | ||
diff --git a/arch/m68k/include/asm/irq_regs.h b/arch/m68k/include/asm/irq_regs.h new file mode 100644 index 000000000000..3dd9c0b70270 --- /dev/null +++ b/arch/m68k/include/asm/irq_regs.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/irq_regs.h> | |||
diff --git a/arch/m68k/include/asm/kdebug.h b/arch/m68k/include/asm/kdebug.h new file mode 100644 index 000000000000..6ece1b037665 --- /dev/null +++ b/arch/m68k/include/asm/kdebug.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/kdebug.h> | |||
diff --git a/arch/m68k/include/asm/kmap_types.h b/arch/m68k/include/asm/kmap_types.h new file mode 100644 index 000000000000..045d9fd122a2 --- /dev/null +++ b/arch/m68k/include/asm/kmap_types.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "kmap_types_no.h" | ||
| 3 | #else | ||
| 4 | #include "kmap_types_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/kmap_types_mm.h b/arch/m68k/include/asm/kmap_types_mm.h new file mode 100644 index 000000000000..c843c63d3801 --- /dev/null +++ b/arch/m68k/include/asm/kmap_types_mm.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | #ifndef __ASM_M68K_KMAP_TYPES_H | ||
| 2 | #define __ASM_M68K_KMAP_TYPES_H | ||
| 3 | |||
| 4 | enum km_type { | ||
| 5 | KM_BOUNCE_READ, | ||
| 6 | KM_SKB_SUNRPC_DATA, | ||
| 7 | KM_SKB_DATA_SOFTIRQ, | ||
| 8 | KM_USER0, | ||
| 9 | KM_USER1, | ||
| 10 | KM_BIO_SRC_IRQ, | ||
| 11 | KM_BIO_DST_IRQ, | ||
| 12 | KM_PTE0, | ||
| 13 | KM_PTE1, | ||
| 14 | KM_IRQ0, | ||
| 15 | KM_IRQ1, | ||
| 16 | KM_SOFTIRQ0, | ||
| 17 | KM_SOFTIRQ1, | ||
| 18 | KM_TYPE_NR | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif /* __ASM_M68K_KMAP_TYPES_H */ | ||
diff --git a/arch/m68k/include/asm/kmap_types_no.h b/arch/m68k/include/asm/kmap_types_no.h new file mode 100644 index 000000000000..bfb6707575d1 --- /dev/null +++ b/arch/m68k/include/asm/kmap_types_no.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | #ifndef __ASM_M68K_KMAP_TYPES_H | ||
| 2 | #define __ASM_M68K_KMAP_TYPES_H | ||
| 3 | |||
| 4 | enum km_type { | ||
| 5 | KM_BOUNCE_READ, | ||
| 6 | KM_SKB_SUNRPC_DATA, | ||
| 7 | KM_SKB_DATA_SOFTIRQ, | ||
| 8 | KM_USER0, | ||
| 9 | KM_USER1, | ||
| 10 | KM_BIO_SRC_IRQ, | ||
| 11 | KM_BIO_DST_IRQ, | ||
| 12 | KM_PTE0, | ||
| 13 | KM_PTE1, | ||
| 14 | KM_IRQ0, | ||
| 15 | KM_IRQ1, | ||
| 16 | KM_SOFTIRQ0, | ||
| 17 | KM_SOFTIRQ1, | ||
| 18 | KM_TYPE_NR | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/m68k/include/asm/linkage.h b/arch/m68k/include/asm/linkage.h new file mode 100644 index 000000000000..5a822bb790f7 --- /dev/null +++ b/arch/m68k/include/asm/linkage.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __ASM_LINKAGE_H | ||
| 2 | #define __ASM_LINKAGE_H | ||
| 3 | |||
| 4 | #define __ALIGN .align 4 | ||
| 5 | #define __ALIGN_STR ".align 4" | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/arch/m68k/include/asm/local.h b/arch/m68k/include/asm/local.h new file mode 100644 index 000000000000..6c259263e1f0 --- /dev/null +++ b/arch/m68k/include/asm/local.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_M68K_LOCAL_H | ||
| 2 | #define _ASM_M68K_LOCAL_H | ||
| 3 | |||
| 4 | #include <asm-generic/local.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_M68K_LOCAL_H */ | ||
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h new file mode 100644 index 000000000000..7e3594dea88b --- /dev/null +++ b/arch/m68k/include/asm/m5206sim.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m5206sim.h -- ColdFire 5206 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef m5206sim_h | ||
| 12 | #define m5206sim_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * Define the 5206 SIM register set addresses. | ||
| 18 | */ | ||
| 19 | #define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */ | ||
| 20 | #define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */ | ||
| 21 | #define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */ | ||
| 22 | #define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */ | ||
| 23 | #define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */ | ||
| 24 | #define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */ | ||
| 25 | #define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */ | ||
| 26 | #define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */ | ||
| 27 | #define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */ | ||
| 28 | #define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */ | ||
| 29 | #define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */ | ||
| 30 | #define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */ | ||
| 31 | #define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */ | ||
| 32 | #define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */ | ||
| 33 | #ifdef CONFIG_M5206e | ||
| 34 | #define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */ | ||
| 35 | #define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */ | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */ | ||
| 39 | #define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */ | ||
| 40 | |||
| 41 | #define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ | ||
| 42 | #define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ | ||
| 43 | |||
| 44 | #define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ | ||
| 45 | #define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ | ||
| 46 | |||
| 47 | #define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ | ||
| 48 | #define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ | ||
| 49 | #define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */ | ||
| 50 | #define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ | ||
| 51 | #define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */ | ||
| 52 | #define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */ | ||
| 53 | #define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */ | ||
| 54 | #define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */ | ||
| 55 | |||
| 56 | #define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ | ||
| 57 | #define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ | ||
| 58 | #define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */ | ||
| 59 | #define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */ | ||
| 60 | #define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */ | ||
| 61 | #define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */ | ||
| 62 | #define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */ | ||
| 63 | #define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */ | ||
| 64 | #define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */ | ||
| 65 | #define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */ | ||
| 66 | #define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */ | ||
| 67 | #define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */ | ||
| 68 | #define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */ | ||
| 69 | #define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */ | ||
| 70 | #define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */ | ||
| 71 | #define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */ | ||
| 72 | #define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */ | ||
| 73 | #define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */ | ||
| 74 | #define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */ | ||
| 75 | #define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */ | ||
| 76 | #define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */ | ||
| 77 | #define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */ | ||
| 78 | #define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */ | ||
| 79 | #define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */ | ||
| 80 | #define MCFSIM_DMCR 0xc6 /* Default control */ | ||
| 81 | |||
| 82 | #ifdef CONFIG_M5206e | ||
| 83 | #define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */ | ||
| 84 | #else | ||
| 85 | #define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ | ||
| 86 | #endif | ||
| 87 | |||
| 88 | #define MCFSIM_PADDR 0x1c5 /* Parallel Direction (r/w) */ | ||
| 89 | #define MCFSIM_PADAT 0x1c9 /* Parallel Port Value (r/w) */ | ||
| 90 | |||
| 91 | /* | ||
| 92 | * Some symbol defines for the Parallel Port Pin Assignment Register | ||
| 93 | */ | ||
| 94 | #ifdef CONFIG_M5206e | ||
| 95 | #define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */ | ||
| 96 | /* Clear to select T0 input */ | ||
| 97 | #define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */ | ||
| 98 | /* Clear to select T0 output */ | ||
| 99 | #endif | ||
| 100 | |||
| 101 | /* | ||
| 102 | * Some symbol defines for the Interrupt Control Register | ||
| 103 | */ | ||
| 104 | #define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */ | ||
| 105 | #define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */ | ||
| 106 | #define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */ | ||
| 107 | #define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ | ||
| 108 | #define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */ | ||
| 109 | #ifdef CONFIG_M5206e | ||
| 110 | #define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */ | ||
| 111 | #define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if defined(CONFIG_M5206e) | ||
| 115 | #define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */ | ||
| 116 | #endif | ||
| 117 | |||
| 118 | /* | ||
| 119 | * Macro to get and set IMR register. It is 16 bits on the 5206. | ||
| 120 | */ | ||
| 121 | #define mcf_getimr() \ | ||
| 122 | *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) | ||
| 123 | |||
| 124 | #define mcf_setimr(imr) \ | ||
| 125 | *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr) | ||
| 126 | |||
| 127 | #define mcf_getipr() \ | ||
| 128 | *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR)) | ||
| 129 | |||
| 130 | /****************************************************************************/ | ||
| 131 | #endif /* m5206sim_h */ | ||
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h new file mode 100644 index 000000000000..49d016e6391a --- /dev/null +++ b/arch/m68k/include/asm/m520xsim.h | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef m520xsim_h | ||
| 11 | #define m520xsim_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Define the 5282 SIM register set addresses. | ||
| 17 | */ | ||
| 18 | #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ | ||
| 19 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ | ||
| 20 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | ||
| 21 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | ||
| 22 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | ||
| 23 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | ||
| 24 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | ||
| 25 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | ||
| 26 | |||
| 27 | #define MCFINT_VECBASE 64 | ||
| 28 | #define MCFINT_UART0 26 /* Interrupt number for UART0 */ | ||
| 29 | #define MCFINT_UART1 27 /* Interrupt number for UART1 */ | ||
| 30 | #define MCFINT_UART2 28 /* Interrupt number for UART2 */ | ||
| 31 | #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ | ||
| 32 | #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ | ||
| 33 | |||
| 34 | /* | ||
| 35 | * SDRAM configuration registers. | ||
| 36 | */ | ||
| 37 | #define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ | ||
| 38 | #define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ | ||
| 39 | #define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ | ||
| 40 | #define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ | ||
| 41 | #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ | ||
| 42 | #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ | ||
| 43 | |||
| 44 | |||
| 45 | #define MCF_GPIO_PAR_UART (0xA4036) | ||
| 46 | #define MCF_GPIO_PAR_FECI2C (0xA4033) | ||
| 47 | #define MCF_GPIO_PAR_FEC (0xA4038) | ||
| 48 | |||
| 49 | #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) | ||
| 50 | #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) | ||
| 51 | |||
| 52 | #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) | ||
| 53 | #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) | ||
| 54 | |||
| 55 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) | ||
| 56 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) | ||
| 57 | |||
| 58 | #define ICR_INTRCONF 0x05 | ||
| 59 | #define MCFPIT_IMR MCFINTC_IMRL | ||
| 60 | #define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) | ||
| 61 | |||
| 62 | /****************************************************************************/ | ||
| 63 | #endif /* m520xsim_h */ | ||
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h new file mode 100644 index 000000000000..bf397313e93f --- /dev/null +++ b/arch/m68k/include/asm/m523xsim.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m523xsim.h -- ColdFire 523x System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef m523xsim_h | ||
| 11 | #define m523xsim_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Define the 523x SIM register set addresses. | ||
| 17 | */ | ||
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ | ||
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ | ||
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ | ||
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | ||
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | ||
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | ||
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | ||
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | ||
| 26 | #define MCFINTC_IRLR 0x18 /* */ | ||
| 27 | #define MCFINTC_IACKL 0x19 /* */ | ||
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | ||
| 29 | |||
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ | ||
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | ||
| 32 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ | ||
| 33 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ | ||
| 34 | |||
| 35 | /* | ||
| 36 | * SDRAM configuration registers. | ||
| 37 | */ | ||
| 38 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | ||
| 39 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | ||
| 40 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | ||
| 41 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | ||
| 42 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | ||
| 43 | |||
| 44 | /****************************************************************************/ | ||
| 45 | #endif /* m523xsim_h */ | ||
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h new file mode 100644 index 000000000000..366eb8602d2f --- /dev/null +++ b/arch/m68k/include/asm/m5249sim.h | |||
| @@ -0,0 +1,209 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m5249sim.h -- ColdFire 5249 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef m5249sim_h | ||
| 11 | #define m5249sim_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Define the 5249 SIM register set addresses. | ||
| 16 | */ | ||
| 17 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ | ||
| 18 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ | ||
| 19 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ | ||
| 20 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ | ||
| 21 | #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ | ||
| 22 | #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ | ||
| 23 | #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ | ||
| 24 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ | ||
| 25 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ | ||
| 26 | #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ | ||
| 27 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ | ||
| 28 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ | ||
| 29 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ | ||
| 30 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ | ||
| 31 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ | ||
| 32 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ | ||
| 33 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ | ||
| 34 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ | ||
| 35 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ | ||
| 36 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ | ||
| 37 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ | ||
| 38 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ | ||
| 39 | |||
| 40 | #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ | ||
| 41 | #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ | ||
| 42 | #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ | ||
| 43 | #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ | ||
| 44 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ | ||
| 45 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ | ||
| 46 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ | ||
| 47 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ | ||
| 48 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | ||
| 49 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ | ||
| 50 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ | ||
| 51 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | ||
| 52 | |||
| 53 | #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ | ||
| 54 | #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ | ||
| 55 | #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ | ||
| 56 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ | ||
| 57 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ | ||
| 58 | |||
| 59 | |||
| 60 | /* | ||
| 61 | * Some symbol defines for the above... | ||
| 62 | */ | ||
| 63 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ | ||
| 64 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ | ||
| 65 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ | ||
| 66 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ | ||
| 67 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ | ||
| 68 | #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ | ||
| 69 | #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ | ||
| 70 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ | ||
| 71 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ | ||
| 72 | |||
| 73 | /* | ||
| 74 | * General purpose IO registers (in MBAR2). | ||
| 75 | */ | ||
| 76 | #define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */ | ||
| 77 | #define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */ | ||
| 78 | #define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */ | ||
| 79 | #define MCFSIM2_GPIOFUNC 0xc /* GPIO function */ | ||
| 80 | #define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */ | ||
| 81 | #define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */ | ||
| 82 | #define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */ | ||
| 83 | #define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */ | ||
| 84 | |||
| 85 | #define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ | ||
| 86 | #define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ | ||
| 87 | #define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ | ||
| 88 | |||
| 89 | #define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ | ||
| 90 | #define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ | ||
| 91 | #define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ | ||
| 92 | #define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ | ||
| 93 | #define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ | ||
| 94 | #define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ | ||
| 95 | #define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ | ||
| 96 | #define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ | ||
| 97 | |||
| 98 | #define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ | ||
| 99 | |||
| 100 | #define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ | ||
| 101 | #define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ | ||
| 102 | |||
| 103 | |||
| 104 | /* | ||
| 105 | * Macro to set IMR register. It is 32 bits on the 5249. | ||
| 106 | */ | ||
| 107 | #define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */ | ||
| 108 | |||
| 109 | #define mcf_getimr() \ | ||
| 110 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) | ||
| 111 | |||
| 112 | #define mcf_setimr(imr) \ | ||
| 113 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); | ||
| 114 | |||
| 115 | #define mcf_getipr() \ | ||
| 116 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) | ||
| 117 | |||
| 118 | /****************************************************************************/ | ||
| 119 | |||
| 120 | #ifdef __ASSEMBLER__ | ||
| 121 | |||
| 122 | /* | ||
| 123 | * The M5249C3 board needs a little help getting all its SIM devices | ||
| 124 | * initialized at kernel start time. dBUG doesn't set much up, so | ||
| 125 | * we need to do it manually. | ||
| 126 | */ | ||
| 127 | .macro m5249c3_setup | ||
| 128 | /* | ||
| 129 | * Set MBAR1 and MBAR2, just incase they are not set. | ||
| 130 | */ | ||
| 131 | movel #0x10000001,%a0 | ||
| 132 | movec %a0,%MBAR /* map MBAR region */ | ||
| 133 | subql #1,%a0 /* get MBAR address in a0 */ | ||
| 134 | |||
| 135 | movel #0x80000001,%a1 | ||
| 136 | movec %a1,#3086 /* map MBAR2 region */ | ||
| 137 | subql #1,%a1 /* get MBAR2 address in a1 */ | ||
| 138 | |||
| 139 | /* | ||
| 140 | * Move secondary interrupts to base at 128. | ||
| 141 | */ | ||
| 142 | moveb #0x80,%d0 | ||
| 143 | moveb %d0,0x16b(%a1) /* interrupt base register */ | ||
| 144 | |||
| 145 | /* | ||
| 146 | * Work around broken CSMR0/DRAM vector problem. | ||
| 147 | */ | ||
| 148 | movel #0x001F0021,%d0 /* disable C/I bit */ | ||
| 149 | movel %d0,0x84(%a0) /* set CSMR0 */ | ||
| 150 | |||
| 151 | /* | ||
| 152 | * Disable the PLL firstly. (Who knows what state it is | ||
| 153 | * in here!). | ||
| 154 | */ | ||
| 155 | movel 0x180(%a1),%d0 /* get current PLL value */ | ||
| 156 | andl #0xfffffffe,%d0 /* PLL bypass first */ | ||
| 157 | movel %d0,0x180(%a1) /* set PLL register */ | ||
| 158 | nop | ||
| 159 | |||
| 160 | #if CONFIG_CLOCK_FREQ == 140000000 | ||
| 161 | /* | ||
| 162 | * Set initial clock frequency. This assumes M5249C3 board | ||
| 163 | * is fitted with 11.2896MHz crystal. It will program the | ||
| 164 | * PLL for 140MHz. Lets go fast :-) | ||
| 165 | */ | ||
| 166 | movel #0x125a40f0,%d0 /* set for 140MHz */ | ||
| 167 | movel %d0,0x180(%a1) /* set PLL register */ | ||
| 168 | orl #0x1,%d0 | ||
| 169 | movel %d0,0x180(%a1) /* set PLL register */ | ||
| 170 | #endif | ||
| 171 | |||
| 172 | /* | ||
| 173 | * Setup CS1 for ethernet controller. | ||
| 174 | * (Setup as per M5249C3 doco). | ||
| 175 | */ | ||
| 176 | movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ | ||
| 177 | movel %d0,0x8c(%a0) | ||
| 178 | movel #0x001f0021,%d0 /* CS1 size of 1Mb */ | ||
| 179 | movel %d0,0x90(%a0) | ||
| 180 | movew #0x0080,%d0 /* CS1 = 16bit port, AA */ | ||
| 181 | movew %d0,0x96(%a0) | ||
| 182 | |||
| 183 | /* | ||
| 184 | * Setup CS2 for IDE interface. | ||
| 185 | */ | ||
| 186 | movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ | ||
| 187 | movel %d0,0x98(%a0) | ||
| 188 | movel #0x001f0001,%d0 /* CS2 size of 1MB */ | ||
| 189 | movel %d0,0x9c(%a0) | ||
| 190 | movew #0x0080,%d0 /* CS2 = 16bit, TA */ | ||
| 191 | movew %d0,0xa2(%a0) | ||
| 192 | |||
| 193 | movel #0x00107000,%d0 /* IDEconfig1 */ | ||
| 194 | movel %d0,0x18c(%a1) | ||
| 195 | movel #0x000c0400,%d0 /* IDEconfig2 */ | ||
| 196 | movel %d0,0x190(%a1) | ||
| 197 | |||
| 198 | movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ | ||
| 199 | orl %d0,0xc(%a1) /* function GPIO19 */ | ||
| 200 | orl %d0,0x8(%a1) /* enable GPIO19 as output */ | ||
| 201 | orl %d0,0x4(%a1) /* de-assert IDE reset */ | ||
| 202 | .endm | ||
| 203 | |||
| 204 | #define PLATFORM_SETUP m5249c3_setup | ||
| 205 | |||
| 206 | #endif /* __ASSEMBLER__ */ | ||
| 207 | |||
| 208 | /****************************************************************************/ | ||
| 209 | #endif /* m5249sim_h */ | ||
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h new file mode 100644 index 000000000000..6217edc21139 --- /dev/null +++ b/arch/m68k/include/asm/m5272sim.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m5272sim.h -- ColdFire 5272 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef m5272sim_h | ||
| 12 | #define m5272sim_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * Define the 5272 SIM register set addresses. | ||
| 18 | */ | ||
| 19 | #define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ | ||
| 20 | #define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ | ||
| 21 | #define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ | ||
| 22 | #define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ | ||
| 23 | #define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ | ||
| 24 | |||
| 25 | #define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ | ||
| 26 | #define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ | ||
| 27 | #define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ | ||
| 28 | #define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ | ||
| 29 | |||
| 30 | #define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ | ||
| 31 | #define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ | ||
| 32 | #define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ | ||
| 33 | #define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ | ||
| 34 | |||
| 35 | #define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ | ||
| 36 | #define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ | ||
| 37 | #define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ | ||
| 38 | #define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ | ||
| 39 | |||
| 40 | #define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ | ||
| 41 | #define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ | ||
| 42 | #define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ | ||
| 43 | #define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ | ||
| 44 | #define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ | ||
| 45 | #define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ | ||
| 46 | #define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ | ||
| 47 | #define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ | ||
| 48 | #define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ | ||
| 49 | #define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ | ||
| 50 | #define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ | ||
| 51 | #define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ | ||
| 52 | #define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ | ||
| 53 | #define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ | ||
| 54 | #define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ | ||
| 55 | #define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ | ||
| 56 | |||
| 57 | #define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ | ||
| 58 | #define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ | ||
| 59 | #define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ | ||
| 60 | #define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ | ||
| 61 | #define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ | ||
| 62 | #define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ | ||
| 63 | #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ | ||
| 64 | #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ | ||
| 65 | |||
| 66 | #define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ | ||
| 67 | #define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ | ||
| 68 | #define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ | ||
| 69 | #define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ | ||
| 70 | #define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ | ||
| 71 | #define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ | ||
| 72 | #define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ | ||
| 73 | #define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ | ||
| 74 | #define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ | ||
| 75 | |||
| 76 | |||
| 77 | /****************************************************************************/ | ||
| 78 | #endif /* m5272sim_h */ | ||
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h new file mode 100644 index 000000000000..1f63ab3fb3e6 --- /dev/null +++ b/arch/m68k/include/asm/m527xsim.h | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef m527xsim_h | ||
| 11 | #define m527xsim_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Define the 5270/5271 SIM register set addresses. | ||
| 17 | */ | ||
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ | ||
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ | ||
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ | ||
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | ||
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | ||
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | ||
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | ||
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | ||
| 26 | #define MCFINTC_IRLR 0x18 /* */ | ||
| 27 | #define MCFINTC_IACKL 0x19 /* */ | ||
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | ||
| 29 | |||
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ | ||
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | ||
| 32 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ | ||
| 33 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | ||
| 34 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ | ||
| 35 | |||
| 36 | /* | ||
| 37 | * SDRAM configuration registers. | ||
| 38 | */ | ||
| 39 | #ifdef CONFIG_M5271 | ||
| 40 | #define MCFSIM_DCR 0x40 /* SDRAM control */ | ||
| 41 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | ||
| 42 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | ||
| 43 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | ||
| 44 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | ||
| 45 | #endif | ||
| 46 | #ifdef CONFIG_M5275 | ||
| 47 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ | ||
| 48 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | ||
| 49 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ | ||
| 50 | #define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ | ||
| 51 | #define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ | ||
| 52 | #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ | ||
| 53 | #define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ | ||
| 54 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ | ||
| 55 | #endif | ||
| 56 | |||
| 57 | /* | ||
| 58 | * GPIO pins setups to enable the UARTs. | ||
| 59 | */ | ||
| 60 | #ifdef CONFIG_M5271 | ||
| 61 | #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ | ||
| 62 | #define UART0_ENABLE_MASK 0x000f | ||
| 63 | #define UART1_ENABLE_MASK 0x0ff0 | ||
| 64 | #define UART2_ENABLE_MASK 0x3000 | ||
| 65 | #endif | ||
| 66 | #ifdef CONFIG_M5275 | ||
| 67 | #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ | ||
| 68 | #define UART0_ENABLE_MASK 0x000f | ||
| 69 | #define UART1_ENABLE_MASK 0x00f0 | ||
| 70 | #define UART2_ENABLE_MASK 0x3f00 | ||
| 71 | #endif | ||
| 72 | |||
| 73 | /****************************************************************************/ | ||
| 74 | #endif /* m527xsim_h */ | ||
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h new file mode 100644 index 000000000000..28bf783a5d6d --- /dev/null +++ b/arch/m68k/include/asm/m528xsim.h | |||
| @@ -0,0 +1,159 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef m528xsim_h | ||
| 11 | #define m528xsim_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Define the 5280/5282 SIM register set addresses. | ||
| 17 | */ | ||
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ | ||
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ | ||
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ | ||
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | ||
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | ||
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | ||
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | ||
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | ||
| 26 | #define MCFINTC_IRLR 0x18 /* */ | ||
| 27 | #define MCFINTC_IACKL 0x19 /* */ | ||
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | ||
| 29 | |||
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ | ||
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | ||
| 32 | #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ | ||
| 33 | |||
| 34 | /* | ||
| 35 | * SDRAM configuration registers. | ||
| 36 | */ | ||
| 37 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | ||
| 38 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | ||
| 39 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | ||
| 40 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | ||
| 41 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Derek Cheung - 6 Feb 2005 | ||
| 45 | * add I2C and QSPI register definition using Freescale's MCF5282 | ||
| 46 | */ | ||
| 47 | /* set Port AS pin for I2C or UART */ | ||
| 48 | #define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056) | ||
| 49 | |||
| 50 | /* Port UA Pin Assignment Register (8 Bit) */ | ||
| 51 | #define MCF5282_GPIO_PUAPAR 0x10005C | ||
| 52 | |||
| 53 | /* Interrupt Mask Register Register Low */ | ||
| 54 | #define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C) | ||
| 55 | /* Interrupt Control Register 7 */ | ||
| 56 | #define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51) | ||
| 57 | |||
| 58 | |||
| 59 | |||
| 60 | /********************************************************************* | ||
| 61 | * | ||
| 62 | * Inter-IC (I2C) Module | ||
| 63 | * | ||
| 64 | *********************************************************************/ | ||
| 65 | /* Read/Write access macros for general use */ | ||
| 66 | #define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address | ||
| 67 | #define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider | ||
| 68 | #define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control | ||
| 69 | #define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status | ||
| 70 | #define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O | ||
| 71 | |||
| 72 | /* Bit level definitions and macros */ | ||
| 73 | #define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) | ||
| 74 | |||
| 75 | #define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) | ||
| 76 | |||
| 77 | #define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable | ||
| 78 | #define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable | ||
| 79 | #define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode | ||
| 80 | #define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode | ||
| 81 | #define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable | ||
| 82 | #define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start | ||
| 83 | |||
| 84 | #define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit | ||
| 85 | #define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave | ||
| 86 | #define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy | ||
| 87 | #define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost | ||
| 88 | #define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write | ||
| 89 | #define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt | ||
| 90 | #define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge | ||
| 91 | |||
| 92 | |||
| 93 | |||
| 94 | /********************************************************************* | ||
| 95 | * | ||
| 96 | * Queued Serial Peripheral Interface (QSPI) Module | ||
| 97 | * | ||
| 98 | *********************************************************************/ | ||
| 99 | /* Derek - 21 Feb 2005 */ | ||
| 100 | /* change to the format used in I2C */ | ||
| 101 | /* Read/Write access macros for general use */ | ||
| 102 | #define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340 | ||
| 103 | #define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344 | ||
| 104 | #define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348 | ||
| 105 | #define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C | ||
| 106 | #define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350 | ||
| 107 | #define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354 | ||
| 108 | #define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354 | ||
| 109 | |||
| 110 | /* Bit level definitions and macros */ | ||
| 111 | #define MCF5282_QSPI_QMR_MSTR (0x8000) | ||
| 112 | #define MCF5282_QSPI_QMR_DOHIE (0x4000) | ||
| 113 | #define MCF5282_QSPI_QMR_BITS_16 (0x0000) | ||
| 114 | #define MCF5282_QSPI_QMR_BITS_8 (0x2000) | ||
| 115 | #define MCF5282_QSPI_QMR_BITS_9 (0x2400) | ||
| 116 | #define MCF5282_QSPI_QMR_BITS_10 (0x2800) | ||
| 117 | #define MCF5282_QSPI_QMR_BITS_11 (0x2C00) | ||
| 118 | #define MCF5282_QSPI_QMR_BITS_12 (0x3000) | ||
| 119 | #define MCF5282_QSPI_QMR_BITS_13 (0x3400) | ||
| 120 | #define MCF5282_QSPI_QMR_BITS_14 (0x3800) | ||
| 121 | #define MCF5282_QSPI_QMR_BITS_15 (0x3C00) | ||
| 122 | #define MCF5282_QSPI_QMR_CPOL (0x0200) | ||
| 123 | #define MCF5282_QSPI_QMR_CPHA (0x0100) | ||
| 124 | #define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) | ||
| 125 | |||
| 126 | #define MCF5282_QSPI_QDLYR_SPE (0x80) | ||
| 127 | #define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) | ||
| 128 | #define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) | ||
| 129 | |||
| 130 | #define MCF5282_QSPI_QWR_HALT (0x8000) | ||
| 131 | #define MCF5282_QSPI_QWR_WREN (0x4000) | ||
| 132 | #define MCF5282_QSPI_QWR_WRTO (0x2000) | ||
| 133 | #define MCF5282_QSPI_QWR_CSIV (0x1000) | ||
| 134 | #define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) | ||
| 135 | #define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) | ||
| 136 | #define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) | ||
| 137 | |||
| 138 | #define MCF5282_QSPI_QIR_WCEFB (0x8000) | ||
| 139 | #define MCF5282_QSPI_QIR_ABRTB (0x4000) | ||
| 140 | #define MCF5282_QSPI_QIR_ABRTL (0x1000) | ||
| 141 | #define MCF5282_QSPI_QIR_WCEFE (0x0800) | ||
| 142 | #define MCF5282_QSPI_QIR_ABRTE (0x0400) | ||
| 143 | #define MCF5282_QSPI_QIR_SPIFE (0x0100) | ||
| 144 | #define MCF5282_QSPI_QIR_WCEF (0x0008) | ||
| 145 | #define MCF5282_QSPI_QIR_ABRT (0x0004) | ||
| 146 | #define MCF5282_QSPI_QIR_SPIF (0x0001) | ||
| 147 | |||
| 148 | #define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) | ||
| 149 | |||
| 150 | #define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) | ||
| 151 | #define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) | ||
| 152 | #define MCF5282_QSPI_QCR_CONT (0x8000) | ||
| 153 | #define MCF5282_QSPI_QCR_BITSE (0x4000) | ||
| 154 | #define MCF5282_QSPI_QCR_DT (0x2000) | ||
| 155 | #define MCF5282_QSPI_QCR_DSCK (0x1000) | ||
| 156 | #define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8) | ||
| 157 | |||
| 158 | /****************************************************************************/ | ||
| 159 | #endif /* m528xsim_h */ | ||
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h new file mode 100644 index 000000000000..5886728409c0 --- /dev/null +++ b/arch/m68k/include/asm/m5307sim.h | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m5307sim.h -- ColdFire 5307 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. | ||
| 7 | * (C) Copyright 1999, Lineo (www.lineo.com) | ||
| 8 | * | ||
| 9 | * Modified by David W. Miller for the MCF5307 Eval Board. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /****************************************************************************/ | ||
| 13 | #ifndef m5307sim_h | ||
| 14 | #define m5307sim_h | ||
| 15 | /****************************************************************************/ | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Define the 5307 SIM register set addresses. | ||
| 19 | */ | ||
| 20 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ | ||
| 21 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ | ||
| 22 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ | ||
| 23 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ | ||
| 24 | #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ | ||
| 25 | #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ | ||
| 26 | #define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ | ||
| 27 | #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ | ||
| 28 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ | ||
| 29 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ | ||
| 30 | #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ | ||
| 31 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ | ||
| 32 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ | ||
| 33 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ | ||
| 34 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ | ||
| 35 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ | ||
| 36 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ | ||
| 37 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ | ||
| 38 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ | ||
| 39 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ | ||
| 40 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ | ||
| 41 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ | ||
| 42 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ | ||
| 43 | |||
| 44 | #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ | ||
| 45 | #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ | ||
| 46 | #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ | ||
| 47 | #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ | ||
| 48 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ | ||
| 49 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ | ||
| 50 | |||
| 51 | #ifdef CONFIG_OLDMASK | ||
| 52 | #define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */ | ||
| 53 | #define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */ | ||
| 54 | #define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */ | ||
| 55 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | ||
| 56 | #define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */ | ||
| 57 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | ||
| 58 | #define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */ | ||
| 59 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | ||
| 60 | #define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */ | ||
| 61 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | ||
| 62 | #define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */ | ||
| 63 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | ||
| 64 | #define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ | ||
| 65 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | ||
| 66 | #else | ||
| 67 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ | ||
| 68 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ | ||
| 69 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | ||
| 70 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ | ||
| 71 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ | ||
| 72 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | ||
| 73 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ | ||
| 74 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ | ||
| 75 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | ||
| 76 | #define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ | ||
| 77 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ | ||
| 78 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | ||
| 79 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ | ||
| 80 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ | ||
| 81 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | ||
| 82 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ | ||
| 83 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ | ||
| 84 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | ||
| 85 | #endif /* CONFIG_OLDMASK */ | ||
| 86 | |||
| 87 | #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ | ||
| 88 | #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ | ||
| 89 | #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ | ||
| 90 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ | ||
| 91 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ | ||
| 92 | |||
| 93 | #define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ | ||
| 94 | #define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ | ||
| 95 | |||
| 96 | |||
| 97 | /* Definition offset address for CS2-7 -- old mask 5307 */ | ||
| 98 | |||
| 99 | #define MCF5307_CS2 (0x400000) | ||
| 100 | #define MCF5307_CS3 (0x600000) | ||
| 101 | #define MCF5307_CS4 (0x800000) | ||
| 102 | #define MCF5307_CS5 (0xA00000) | ||
| 103 | #define MCF5307_CS6 (0xC00000) | ||
| 104 | #define MCF5307_CS7 (0xE00000) | ||
| 105 | |||
| 106 | |||
| 107 | /* | ||
| 108 | * Some symbol defines for the above... | ||
| 109 | */ | ||
| 110 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ | ||
| 111 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ | ||
| 112 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ | ||
| 113 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ | ||
| 114 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ | ||
| 115 | #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ | ||
| 116 | #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ | ||
| 117 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ | ||
| 118 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ | ||
| 119 | |||
| 120 | #if defined(CONFIG_M5307) | ||
| 121 | #define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */ | ||
| 122 | #endif | ||
| 123 | |||
| 124 | /* | ||
| 125 | * Macro to set IMR register. It is 32 bits on the 5307. | ||
| 126 | */ | ||
| 127 | #define mcf_getimr() \ | ||
| 128 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) | ||
| 129 | |||
| 130 | #define mcf_setimr(imr) \ | ||
| 131 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); | ||
| 132 | |||
| 133 | #define mcf_getipr() \ | ||
| 134 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) | ||
| 135 | |||
| 136 | |||
| 137 | /* | ||
| 138 | * Some symbol defines for the Parallel Port Pin Assignment Register | ||
| 139 | */ | ||
| 140 | #define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ | ||
| 141 | /* Clear to select par I/O */ | ||
| 142 | #define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ | ||
| 143 | /* Clear to select par I/O */ | ||
| 144 | |||
| 145 | /* | ||
| 146 | * Defines for the IRQPAR Register | ||
| 147 | */ | ||
| 148 | #define IRQ5_LEVEL4 0x80 | ||
| 149 | #define IRQ3_LEVEL6 0x40 | ||
| 150 | #define IRQ1_LEVEL2 0x20 | ||
| 151 | |||
| 152 | |||
| 153 | /* | ||
| 154 | * Define the Cache register flags. | ||
| 155 | */ | ||
| 156 | #define CACR_EC (1<<31) | ||
| 157 | #define CACR_ESB (1<<29) | ||
| 158 | #define CACR_DPI (1<<28) | ||
| 159 | #define CACR_HLCK (1<<27) | ||
| 160 | #define CACR_CINVA (1<<24) | ||
| 161 | #define CACR_DNFB (1<<10) | ||
| 162 | #define CACR_DCM_WTHRU (0<<8) | ||
| 163 | #define CACR_DCM_WBACK (1<<8) | ||
| 164 | #define CACR_DCM_OFF_PRE (2<<8) | ||
| 165 | #define CACR_DCM_OFF_IMP (3<<8) | ||
| 166 | #define CACR_DW (1<<5) | ||
| 167 | |||
| 168 | #define ACR_BASE_POS 24 | ||
| 169 | #define ACR_MASK_POS 16 | ||
| 170 | #define ACR_ENABLE (1<<15) | ||
| 171 | #define ACR_USER (0<<13) | ||
| 172 | #define ACR_SUPER (1<<13) | ||
| 173 | #define ACR_ANY (2<<13) | ||
| 174 | #define ACR_CM_WTHRU (0<<5) | ||
| 175 | #define ACR_CM_WBACK (1<<5) | ||
| 176 | #define ACR_CM_OFF_PRE (2<<5) | ||
| 177 | #define ACR_CM_OFF_IMP (3<<5) | ||
| 178 | #define ACR_WPROTECT (1<<2) | ||
| 179 | |||
| 180 | /****************************************************************************/ | ||
| 181 | #endif /* m5307sim_h */ | ||
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h new file mode 100644 index 000000000000..1835fd20a82c --- /dev/null +++ b/arch/m68k/include/asm/m532xsim.h | |||
| @@ -0,0 +1,2238 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m532xsim.h -- ColdFire 5329 registers | ||
| 5 | */ | ||
| 6 | |||
| 7 | /****************************************************************************/ | ||
| 8 | #ifndef m532xsim_h | ||
| 9 | #define m532xsim_h | ||
| 10 | /****************************************************************************/ | ||
| 11 | |||
| 12 | #define MCF_REG32(x) (*(volatile unsigned long *)(x)) | ||
| 13 | #define MCF_REG16(x) (*(volatile unsigned short *)(x)) | ||
| 14 | #define MCF_REG08(x) (*(volatile unsigned char *)(x)) | ||
| 15 | |||
| 16 | #define MCFINT_VECBASE 64 | ||
| 17 | #define MCFINT_UART0 26 /* Interrupt number for UART0 */ | ||
| 18 | #define MCFINT_UART1 27 /* Interrupt number for UART1 */ | ||
| 19 | |||
| 20 | #define MCF_WTM_WCR MCF_REG16(0xFC098000) | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Define the 532x SIM register set addresses. | ||
| 24 | */ | ||
| 25 | #define MCFSIM_IPRL 0xFC048004 | ||
| 26 | #define MCFSIM_IPRH 0xFC048000 | ||
| 27 | #define MCFSIM_IPR MCFSIM_IPRL | ||
| 28 | #define MCFSIM_IMRL 0xFC04800C | ||
| 29 | #define MCFSIM_IMRH 0xFC048008 | ||
| 30 | #define MCFSIM_IMR MCFSIM_IMRL | ||
| 31 | #define MCFSIM_ICR0 0xFC048040 | ||
| 32 | #define MCFSIM_ICR1 0xFC048041 | ||
| 33 | #define MCFSIM_ICR2 0xFC048042 | ||
| 34 | #define MCFSIM_ICR3 0xFC048043 | ||
| 35 | #define MCFSIM_ICR4 0xFC048044 | ||
| 36 | #define MCFSIM_ICR5 0xFC048045 | ||
| 37 | #define MCFSIM_ICR6 0xFC048046 | ||
| 38 | #define MCFSIM_ICR7 0xFC048047 | ||
| 39 | #define MCFSIM_ICR8 0xFC048048 | ||
| 40 | #define MCFSIM_ICR9 0xFC048049 | ||
| 41 | #define MCFSIM_ICR10 0xFC04804A | ||
| 42 | #define MCFSIM_ICR11 0xFC04804B | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Some symbol defines for the above... | ||
| 46 | */ | ||
| 47 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ | ||
| 48 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ | ||
| 49 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ | ||
| 50 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ | ||
| 51 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ | ||
| 52 | #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ | ||
| 53 | #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ | ||
| 54 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ | ||
| 55 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ | ||
| 56 | |||
| 57 | |||
| 58 | #define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */ | ||
| 59 | |||
| 60 | #define MCFSIM_IMR_SIMR0 0xFC04801C | ||
| 61 | #define MCFSIM_IMR_SIMR1 0xFC04C01C | ||
| 62 | #define MCFSIM_IMR_CIMR0 0xFC04801D | ||
| 63 | #define MCFSIM_IMR_CIMR1 0xFC04C01D | ||
| 64 | |||
| 65 | #define MCFSIM_ICR_TIMER1 (0xFC048040+32) | ||
| 66 | #define MCFSIM_ICR_TIMER2 (0xFC048040+33) | ||
| 67 | |||
| 68 | |||
| 69 | /* | ||
| 70 | * Macro to set IMR register. It is 32 bits on the 5307. | ||
| 71 | */ | ||
| 72 | #define mcf_getimr() \ | ||
| 73 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) | ||
| 74 | |||
| 75 | #define mcf_setimr(imr) \ | ||
| 76 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); | ||
| 77 | |||
| 78 | #define mcf_getipr() \ | ||
| 79 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) | ||
| 80 | |||
| 81 | #define mcf_getiprl() \ | ||
| 82 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL)) | ||
| 83 | |||
| 84 | #define mcf_getiprh() \ | ||
| 85 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH)) | ||
| 86 | |||
| 87 | |||
| 88 | #define mcf_enable_irq0(irq) \ | ||
| 89 | *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq); | ||
| 90 | |||
| 91 | #define mcf_enable_irq1(irq) \ | ||
| 92 | *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq); | ||
| 93 | |||
| 94 | #define mcf_disable_irq0(irq) \ | ||
| 95 | *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq); | ||
| 96 | |||
| 97 | #define mcf_disable_irq1(irq) \ | ||
| 98 | *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq); | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Define the Cache register flags. | ||
| 102 | */ | ||
| 103 | #define CACR_EC (1<<31) | ||
| 104 | #define CACR_ESB (1<<29) | ||
| 105 | #define CACR_DPI (1<<28) | ||
| 106 | #define CACR_HLCK (1<<27) | ||
| 107 | #define CACR_CINVA (1<<24) | ||
| 108 | #define CACR_DNFB (1<<10) | ||
| 109 | #define CACR_DCM_WTHRU (0<<8) | ||
| 110 | #define CACR_DCM_WBACK (1<<8) | ||
| 111 | #define CACR_DCM_OFF_PRE (2<<8) | ||
| 112 | #define CACR_DCM_OFF_IMP (3<<8) | ||
| 113 | #define CACR_DW (1<<5) | ||
| 114 | |||
| 115 | #define ACR_BASE_POS 24 | ||
| 116 | #define ACR_MASK_POS 16 | ||
| 117 | #define ACR_ENABLE (1<<15) | ||
| 118 | #define ACR_USER (0<<13) | ||
| 119 | #define ACR_SUPER (1<<13) | ||
| 120 | #define ACR_ANY (2<<13) | ||
| 121 | #define ACR_CM_WTHRU (0<<5) | ||
| 122 | #define ACR_CM_WBACK (1<<5) | ||
| 123 | #define ACR_CM_OFF_PRE (2<<5) | ||
| 124 | #define ACR_CM_OFF_IMP (3<<5) | ||
| 125 | #define ACR_WPROTECT (1<<2) | ||
| 126 | |||
| 127 | /********************************************************************* | ||
| 128 | * | ||
| 129 | * Inter-IC (I2C) Module | ||
| 130 | * | ||
| 131 | *********************************************************************/ | ||
| 132 | |||
| 133 | /* Read/Write access macros for general use */ | ||
| 134 | #define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address | ||
| 135 | #define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider | ||
| 136 | #define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control | ||
| 137 | #define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status | ||
| 138 | #define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O | ||
| 139 | |||
| 140 | /* Bit level definitions and macros */ | ||
| 141 | #define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) | ||
| 142 | |||
| 143 | #define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F)) | ||
| 144 | |||
| 145 | #define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable | ||
| 146 | #define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable | ||
| 147 | #define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode | ||
| 148 | #define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode | ||
| 149 | #define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable | ||
| 150 | #define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start | ||
| 151 | |||
| 152 | #define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit | ||
| 153 | #define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave | ||
| 154 | #define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy | ||
| 155 | #define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost | ||
| 156 | #define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write | ||
| 157 | #define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt | ||
| 158 | #define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge | ||
| 159 | |||
| 160 | #define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053) | ||
| 161 | |||
| 162 | |||
| 163 | /* | ||
| 164 | * The M5329EVB board needs a help getting its devices initialized | ||
| 165 | * at kernel start time if dBUG doesn't set it up (for example | ||
| 166 | * it is not used), so we need to do it manually. | ||
| 167 | */ | ||
| 168 | #ifdef __ASSEMBLER__ | ||
| 169 | .macro m5329EVB_setup | ||
| 170 | movel #0xFC098000, %a7 | ||
| 171 | movel #0x0, (%a7) | ||
| 172 | #define CORE_SRAM 0x80000000 | ||
| 173 | #define CORE_SRAM_SIZE 0x8000 | ||
| 174 | movel #CORE_SRAM, %d0 | ||
| 175 | addl #0x221, %d0 | ||
| 176 | movec %d0,%RAMBAR1 | ||
| 177 | movel #CORE_SRAM, %sp | ||
| 178 | addl #CORE_SRAM_SIZE, %sp | ||
| 179 | jsr sysinit | ||
| 180 | .endm | ||
| 181 | #define PLATFORM_SETUP m5329EVB_setup | ||
| 182 | |||
| 183 | #endif /* __ASSEMBLER__ */ | ||
| 184 | |||
| 185 | /********************************************************************* | ||
| 186 | * | ||
| 187 | * Chip Configuration Module (CCM) | ||
| 188 | * | ||
| 189 | *********************************************************************/ | ||
| 190 | |||
| 191 | /* Register read/write macros */ | ||
| 192 | #define MCF_CCM_CCR MCF_REG16(0xFC0A0004) | ||
| 193 | #define MCF_CCM_RCON MCF_REG16(0xFC0A0008) | ||
| 194 | #define MCF_CCM_CIR MCF_REG16(0xFC0A000A) | ||
| 195 | #define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) | ||
| 196 | #define MCF_CCM_CDR MCF_REG16(0xFC0A0012) | ||
| 197 | #define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014) | ||
| 198 | #define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016) | ||
| 199 | |||
| 200 | /* Bit definitions and macros for MCF_CCM_CCR */ | ||
| 201 | #define MCF_CCM_CCR_RESERVED (0x0001) | ||
| 202 | #define MCF_CCM_CCR_PLL_MODE (0x0003) | ||
| 203 | #define MCF_CCM_CCR_OSC_MODE (0x0005) | ||
| 204 | #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) | ||
| 205 | #define MCF_CCM_CCR_LOAD (0x0021) | ||
| 206 | #define MCF_CCM_CCR_LIMP (0x0041) | ||
| 207 | #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) | ||
| 208 | |||
| 209 | /* Bit definitions and macros for MCF_CCM_RCON */ | ||
| 210 | #define MCF_CCM_RCON_RESERVED (0x0001) | ||
| 211 | #define MCF_CCM_RCON_PLL_MODE (0x0003) | ||
| 212 | #define MCF_CCM_RCON_OSC_MODE (0x0005) | ||
| 213 | #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) | ||
| 214 | #define MCF_CCM_RCON_LOAD (0x0021) | ||
| 215 | #define MCF_CCM_RCON_LIMP (0x0041) | ||
| 216 | #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) | ||
| 217 | |||
| 218 | /* Bit definitions and macros for MCF_CCM_CIR */ | ||
| 219 | #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) | ||
| 220 | #define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) | ||
| 221 | |||
| 222 | /* Bit definitions and macros for MCF_CCM_MISCCR */ | ||
| 223 | #define MCF_CCM_MISCCR_USBSRC (0x0001) | ||
| 224 | #define MCF_CCM_MISCCR_USBDIV (0x0002) | ||
| 225 | #define MCF_CCM_MISCCR_SSI_SRC (0x0010) | ||
| 226 | #define MCF_CCM_MISCCR_TIM_DMA (0x0020) | ||
| 227 | #define MCF_CCM_MISCCR_SSI_PUS (0x0040) | ||
| 228 | #define MCF_CCM_MISCCR_SSI_PUE (0x0080) | ||
| 229 | #define MCF_CCM_MISCCR_LCD_CHEN (0x0100) | ||
| 230 | #define MCF_CCM_MISCCR_LIMP (0x1000) | ||
| 231 | #define MCF_CCM_MISCCR_PLL_LOCK (0x2000) | ||
| 232 | |||
| 233 | /* Bit definitions and macros for MCF_CCM_CDR */ | ||
| 234 | #define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0) | ||
| 235 | #define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) | ||
| 236 | |||
| 237 | /* Bit definitions and macros for MCF_CCM_UHCSR */ | ||
| 238 | #define MCF_CCM_UHCSR_XPDE (0x0001) | ||
| 239 | #define MCF_CCM_UHCSR_UHMIE (0x0002) | ||
| 240 | #define MCF_CCM_UHCSR_WKUP (0x0004) | ||
| 241 | #define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) | ||
| 242 | |||
| 243 | /* Bit definitions and macros for MCF_CCM_UOCSR */ | ||
| 244 | #define MCF_CCM_UOCSR_XPDE (0x0001) | ||
| 245 | #define MCF_CCM_UOCSR_UOMIE (0x0002) | ||
| 246 | #define MCF_CCM_UOCSR_WKUP (0x0004) | ||
| 247 | #define MCF_CCM_UOCSR_PWRFLT (0x0008) | ||
| 248 | #define MCF_CCM_UOCSR_SEND (0x0010) | ||
| 249 | #define MCF_CCM_UOCSR_VVLD (0x0020) | ||
| 250 | #define MCF_CCM_UOCSR_BVLD (0x0040) | ||
| 251 | #define MCF_CCM_UOCSR_AVLD (0x0080) | ||
| 252 | #define MCF_CCM_UOCSR_DPPU (0x0100) | ||
| 253 | #define MCF_CCM_UOCSR_DCR_VBUS (0x0200) | ||
| 254 | #define MCF_CCM_UOCSR_CRG_VBUS (0x0400) | ||
| 255 | #define MCF_CCM_UOCSR_DRV_VBUS (0x0800) | ||
| 256 | #define MCF_CCM_UOCSR_DMPD (0x1000) | ||
| 257 | #define MCF_CCM_UOCSR_DPPD (0x2000) | ||
| 258 | #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) | ||
| 259 | |||
| 260 | /********************************************************************* | ||
| 261 | * | ||
| 262 | * DMA Timers (DTIM) | ||
| 263 | * | ||
| 264 | *********************************************************************/ | ||
| 265 | |||
| 266 | /* Register read/write macros */ | ||
| 267 | #define MCF_DTIM0_DTMR MCF_REG16(0xFC070000) | ||
| 268 | #define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002) | ||
| 269 | #define MCF_DTIM0_DTER MCF_REG08(0xFC070003) | ||
| 270 | #define MCF_DTIM0_DTRR MCF_REG32(0xFC070004) | ||
| 271 | #define MCF_DTIM0_DTCR MCF_REG32(0xFC070008) | ||
| 272 | #define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C) | ||
| 273 | #define MCF_DTIM1_DTMR MCF_REG16(0xFC074000) | ||
| 274 | #define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002) | ||
| 275 | #define MCF_DTIM1_DTER MCF_REG08(0xFC074003) | ||
| 276 | #define MCF_DTIM1_DTRR MCF_REG32(0xFC074004) | ||
| 277 | #define MCF_DTIM1_DTCR MCF_REG32(0xFC074008) | ||
| 278 | #define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C) | ||
| 279 | #define MCF_DTIM2_DTMR MCF_REG16(0xFC078000) | ||
| 280 | #define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002) | ||
| 281 | #define MCF_DTIM2_DTER MCF_REG08(0xFC078003) | ||
| 282 | #define MCF_DTIM2_DTRR MCF_REG32(0xFC078004) | ||
| 283 | #define MCF_DTIM2_DTCR MCF_REG32(0xFC078008) | ||
| 284 | #define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C) | ||
| 285 | #define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000) | ||
| 286 | #define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002) | ||
| 287 | #define MCF_DTIM3_DTER MCF_REG08(0xFC07C003) | ||
| 288 | #define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004) | ||
| 289 | #define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008) | ||
| 290 | #define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C) | ||
| 291 | #define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000)) | ||
| 292 | #define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000)) | ||
| 293 | #define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000)) | ||
| 294 | #define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000)) | ||
| 295 | #define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000)) | ||
| 296 | #define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000)) | ||
| 297 | |||
| 298 | /* Bit definitions and macros for MCF_DTIM_DTMR */ | ||
| 299 | #define MCF_DTIM_DTMR_RST (0x0001) | ||
| 300 | #define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) | ||
| 301 | #define MCF_DTIM_DTMR_FRR (0x0008) | ||
| 302 | #define MCF_DTIM_DTMR_ORRI (0x0010) | ||
| 303 | #define MCF_DTIM_DTMR_OM (0x0020) | ||
| 304 | #define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) | ||
| 305 | #define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) | ||
| 306 | #define MCF_DTIM_DTMR_CE_ANY (0x00C0) | ||
| 307 | #define MCF_DTIM_DTMR_CE_FALL (0x0080) | ||
| 308 | #define MCF_DTIM_DTMR_CE_RISE (0x0040) | ||
| 309 | #define MCF_DTIM_DTMR_CE_NONE (0x0000) | ||
| 310 | #define MCF_DTIM_DTMR_CLK_DTIN (0x0006) | ||
| 311 | #define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) | ||
| 312 | #define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) | ||
| 313 | #define MCF_DTIM_DTMR_CLK_STOP (0x0000) | ||
| 314 | |||
| 315 | /* Bit definitions and macros for MCF_DTIM_DTXMR */ | ||
| 316 | #define MCF_DTIM_DTXMR_MODE16 (0x01) | ||
| 317 | #define MCF_DTIM_DTXMR_DMAEN (0x80) | ||
| 318 | |||
| 319 | /* Bit definitions and macros for MCF_DTIM_DTER */ | ||
| 320 | #define MCF_DTIM_DTER_CAP (0x01) | ||
| 321 | #define MCF_DTIM_DTER_REF (0x02) | ||
| 322 | |||
| 323 | /* Bit definitions and macros for MCF_DTIM_DTRR */ | ||
| 324 | #define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) | ||
| 325 | |||
| 326 | /* Bit definitions and macros for MCF_DTIM_DTCR */ | ||
| 327 | #define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) | ||
| 328 | |||
| 329 | /* Bit definitions and macros for MCF_DTIM_DTCN */ | ||
| 330 | #define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) | ||
| 331 | |||
| 332 | /********************************************************************* | ||
| 333 | * | ||
| 334 | * FlexBus Chip Selects (FBCS) | ||
| 335 | * | ||
| 336 | *********************************************************************/ | ||
| 337 | |||
| 338 | /* Register read/write macros */ | ||
| 339 | #define MCF_FBCS0_CSAR MCF_REG32(0xFC008000) | ||
| 340 | #define MCF_FBCS0_CSMR MCF_REG32(0xFC008004) | ||
| 341 | #define MCF_FBCS0_CSCR MCF_REG32(0xFC008008) | ||
| 342 | #define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C) | ||
| 343 | #define MCF_FBCS1_CSMR MCF_REG32(0xFC008010) | ||
| 344 | #define MCF_FBCS1_CSCR MCF_REG32(0xFC008014) | ||
| 345 | #define MCF_FBCS2_CSAR MCF_REG32(0xFC008018) | ||
| 346 | #define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C) | ||
| 347 | #define MCF_FBCS2_CSCR MCF_REG32(0xFC008020) | ||
| 348 | #define MCF_FBCS3_CSAR MCF_REG32(0xFC008024) | ||
| 349 | #define MCF_FBCS3_CSMR MCF_REG32(0xFC008028) | ||
| 350 | #define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C) | ||
| 351 | #define MCF_FBCS4_CSAR MCF_REG32(0xFC008030) | ||
| 352 | #define MCF_FBCS4_CSMR MCF_REG32(0xFC008034) | ||
| 353 | #define MCF_FBCS4_CSCR MCF_REG32(0xFC008038) | ||
| 354 | #define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C) | ||
| 355 | #define MCF_FBCS5_CSMR MCF_REG32(0xFC008040) | ||
| 356 | #define MCF_FBCS5_CSCR MCF_REG32(0xFC008044) | ||
| 357 | #define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) | ||
| 358 | #define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) | ||
| 359 | #define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) | ||
| 360 | |||
| 361 | /* Bit definitions and macros for MCF_FBCS_CSAR */ | ||
| 362 | #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) | ||
| 363 | |||
| 364 | /* Bit definitions and macros for MCF_FBCS_CSMR */ | ||
| 365 | #define MCF_FBCS_CSMR_V (0x00000001) | ||
| 366 | #define MCF_FBCS_CSMR_WP (0x00000100) | ||
| 367 | #define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) | ||
| 368 | #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) | ||
| 369 | #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) | ||
| 370 | #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) | ||
| 371 | #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) | ||
| 372 | #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) | ||
| 373 | #define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) | ||
| 374 | #define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) | ||
| 375 | #define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) | ||
| 376 | #define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) | ||
| 377 | #define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) | ||
| 378 | #define MCF_FBCS_CSMR_BAM_8M (0x007F0000) | ||
| 379 | #define MCF_FBCS_CSMR_BAM_4M (0x003F0000) | ||
| 380 | #define MCF_FBCS_CSMR_BAM_2M (0x001F0000) | ||
| 381 | #define MCF_FBCS_CSMR_BAM_1M (0x000F0000) | ||
| 382 | #define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) | ||
| 383 | #define MCF_FBCS_CSMR_BAM_512K (0x00070000) | ||
| 384 | #define MCF_FBCS_CSMR_BAM_256K (0x00030000) | ||
| 385 | #define MCF_FBCS_CSMR_BAM_128K (0x00010000) | ||
| 386 | #define MCF_FBCS_CSMR_BAM_64K (0x00000000) | ||
| 387 | |||
| 388 | /* Bit definitions and macros for MCF_FBCS_CSCR */ | ||
| 389 | #define MCF_FBCS_CSCR_BSTW (0x00000008) | ||
| 390 | #define MCF_FBCS_CSCR_BSTR (0x00000010) | ||
| 391 | #define MCF_FBCS_CSCR_BEM (0x00000020) | ||
| 392 | #define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) | ||
| 393 | #define MCF_FBCS_CSCR_AA (0x00000100) | ||
| 394 | #define MCF_FBCS_CSCR_SBM (0x00000200) | ||
| 395 | #define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) | ||
| 396 | #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) | ||
| 397 | #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) | ||
| 398 | #define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) | ||
| 399 | #define MCF_FBCS_CSCR_SWSEN (0x00800000) | ||
| 400 | #define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) | ||
| 401 | #define MCF_FBCS_CSCR_PS_8 (0x0040) | ||
| 402 | #define MCF_FBCS_CSCR_PS_16 (0x0080) | ||
| 403 | #define MCF_FBCS_CSCR_PS_32 (0x0000) | ||
| 404 | |||
| 405 | /********************************************************************* | ||
| 406 | * | ||
| 407 | * General Purpose I/O (GPIO) | ||
| 408 | * | ||
| 409 | *********************************************************************/ | ||
| 410 | |||
| 411 | /* Register read/write macros */ | ||
| 412 | #define MCF_GPIO_PODR_FECH MCF_REG08(0xFC0A4000) | ||
| 413 | #define MCF_GPIO_PODR_FECL MCF_REG08(0xFC0A4001) | ||
| 414 | #define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) | ||
| 415 | #define MCF_GPIO_PODR_BUSCTL MCF_REG08(0xFC0A4003) | ||
| 416 | #define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) | ||
| 417 | #define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) | ||
| 418 | #define MCF_GPIO_PODR_PWM MCF_REG08(0xFC0A4006) | ||
| 419 | #define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) | ||
| 420 | #define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) | ||
| 421 | #define MCF_GPIO_PODR_QSPI MCF_REG08(0xFC0A400A) | ||
| 422 | #define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) | ||
| 423 | #define MCF_GPIO_PODR_LCDDATAH MCF_REG08(0xFC0A400D) | ||
| 424 | #define MCF_GPIO_PODR_LCDDATAM MCF_REG08(0xFC0A400E) | ||
| 425 | #define MCF_GPIO_PODR_LCDDATAL MCF_REG08(0xFC0A400F) | ||
| 426 | #define MCF_GPIO_PODR_LCDCTLH MCF_REG08(0xFC0A4010) | ||
| 427 | #define MCF_GPIO_PODR_LCDCTLL MCF_REG08(0xFC0A4011) | ||
| 428 | #define MCF_GPIO_PDDR_FECH MCF_REG08(0xFC0A4014) | ||
| 429 | #define MCF_GPIO_PDDR_FECL MCF_REG08(0xFC0A4015) | ||
| 430 | #define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A4016) | ||
| 431 | #define MCF_GPIO_PDDR_BUSCTL MCF_REG08(0xFC0A4017) | ||
| 432 | #define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A4018) | ||
| 433 | #define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A4019) | ||
| 434 | #define MCF_GPIO_PDDR_PWM MCF_REG08(0xFC0A401A) | ||
| 435 | #define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401B) | ||
| 436 | #define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A401C) | ||
| 437 | #define MCF_GPIO_PDDR_QSPI MCF_REG08(0xFC0A401E) | ||
| 438 | #define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A401F) | ||
| 439 | #define MCF_GPIO_PDDR_LCDDATAH MCF_REG08(0xFC0A4021) | ||
| 440 | #define MCF_GPIO_PDDR_LCDDATAM MCF_REG08(0xFC0A4022) | ||
| 441 | #define MCF_GPIO_PDDR_LCDDATAL MCF_REG08(0xFC0A4023) | ||
| 442 | #define MCF_GPIO_PDDR_LCDCTLH MCF_REG08(0xFC0A4024) | ||
| 443 | #define MCF_GPIO_PDDR_LCDCTLL MCF_REG08(0xFC0A4025) | ||
| 444 | #define MCF_GPIO_PPDSDR_FECH MCF_REG08(0xFC0A4028) | ||
| 445 | #define MCF_GPIO_PPDSDR_FECL MCF_REG08(0xFC0A4029) | ||
| 446 | #define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A402A) | ||
| 447 | #define MCF_GPIO_PPDSDR_BUSCTL MCF_REG08(0xFC0A402B) | ||
| 448 | #define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A402C) | ||
| 449 | #define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A402D) | ||
| 450 | #define MCF_GPIO_PPDSDR_PWM MCF_REG08(0xFC0A402E) | ||
| 451 | #define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A402F) | ||
| 452 | #define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4031) | ||
| 453 | #define MCF_GPIO_PPDSDR_QSPI MCF_REG08(0xFC0A4032) | ||
| 454 | #define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A4033) | ||
| 455 | #define MCF_GPIO_PPDSDR_LCDDATAH MCF_REG08(0xFC0A4035) | ||
| 456 | #define MCF_GPIO_PPDSDR_LCDDATAM MCF_REG08(0xFC0A4036) | ||
| 457 | #define MCF_GPIO_PPDSDR_LCDDATAL MCF_REG08(0xFC0A4037) | ||
| 458 | #define MCF_GPIO_PPDSDR_LCDCTLH MCF_REG08(0xFC0A4038) | ||
| 459 | #define MCF_GPIO_PPDSDR_LCDCTLL MCF_REG08(0xFC0A4039) | ||
| 460 | #define MCF_GPIO_PCLRR_FECH MCF_REG08(0xFC0A403C) | ||
| 461 | #define MCF_GPIO_PCLRR_FECL MCF_REG08(0xFC0A403D) | ||
| 462 | #define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A403E) | ||
| 463 | #define MCF_GPIO_PCLRR_BUSCTL MCF_REG08(0xFC0A403F) | ||
| 464 | #define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A4040) | ||
| 465 | #define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A4041) | ||
| 466 | #define MCF_GPIO_PCLRR_PWM MCF_REG08(0xFC0A4042) | ||
| 467 | #define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A4043) | ||
| 468 | #define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4045) | ||
| 469 | #define MCF_GPIO_PCLRR_QSPI MCF_REG08(0xFC0A4046) | ||
| 470 | #define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4047) | ||
| 471 | #define MCF_GPIO_PCLRR_LCDDATAH MCF_REG08(0xFC0A4049) | ||
| 472 | #define MCF_GPIO_PCLRR_LCDDATAM MCF_REG08(0xFC0A404A) | ||
| 473 | #define MCF_GPIO_PCLRR_LCDDATAL MCF_REG08(0xFC0A404B) | ||
| 474 | #define MCF_GPIO_PCLRR_LCDCTLH MCF_REG08(0xFC0A404C) | ||
| 475 | #define MCF_GPIO_PCLRR_LCDCTLL MCF_REG08(0xFC0A404D) | ||
| 476 | #define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) | ||
| 477 | #define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) | ||
| 478 | #define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) | ||
| 479 | #define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) | ||
| 480 | #define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) | ||
| 481 | #define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) | ||
| 482 | #define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) | ||
| 483 | #define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) | ||
| 484 | #define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) | ||
| 485 | #define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) | ||
| 486 | #define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) | ||
| 487 | #define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) | ||
| 488 | #define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) | ||
| 489 | #define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) | ||
| 490 | #define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) | ||
| 491 | #define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) | ||
| 492 | #define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) | ||
| 493 | #define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) | ||
| 494 | #define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) | ||
| 495 | #define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) | ||
| 496 | #define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) | ||
| 497 | #define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) | ||
| 498 | #define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) | ||
| 499 | #define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) | ||
| 500 | #define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) | ||
| 501 | #define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) | ||
| 502 | |||
| 503 | /* Bit definitions and macros for MCF_GPIO_PODR_FECH */ | ||
| 504 | #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) | ||
| 505 | #define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) | ||
| 506 | #define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) | ||
| 507 | #define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) | ||
| 508 | #define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) | ||
| 509 | #define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) | ||
| 510 | #define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) | ||
| 511 | #define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) | ||
| 512 | |||
| 513 | /* Bit definitions and macros for MCF_GPIO_PODR_FECL */ | ||
| 514 | #define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) | ||
| 515 | #define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) | ||
| 516 | #define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) | ||
| 517 | #define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) | ||
| 518 | #define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) | ||
| 519 | #define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) | ||
| 520 | #define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) | ||
| 521 | #define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) | ||
| 522 | |||
| 523 | /* Bit definitions and macros for MCF_GPIO_PODR_SSI */ | ||
| 524 | #define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) | ||
| 525 | #define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) | ||
| 526 | #define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) | ||
| 527 | #define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) | ||
| 528 | #define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) | ||
| 529 | |||
| 530 | /* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ | ||
| 531 | #define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01) | ||
| 532 | #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) | ||
| 533 | #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) | ||
| 534 | #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) | ||
| 535 | |||
| 536 | /* Bit definitions and macros for MCF_GPIO_PODR_BE */ | ||
| 537 | #define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) | ||
| 538 | #define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) | ||
| 539 | #define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) | ||
| 540 | #define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) | ||
| 541 | |||
| 542 | /* Bit definitions and macros for MCF_GPIO_PODR_CS */ | ||
| 543 | #define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) | ||
| 544 | #define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) | ||
| 545 | #define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) | ||
| 546 | #define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) | ||
| 547 | #define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) | ||
| 548 | |||
| 549 | /* Bit definitions and macros for MCF_GPIO_PODR_PWM */ | ||
| 550 | #define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) | ||
| 551 | #define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) | ||
| 552 | #define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) | ||
| 553 | #define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) | ||
| 554 | |||
| 555 | /* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ | ||
| 556 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) | ||
| 557 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) | ||
| 558 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) | ||
| 559 | #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) | ||
| 560 | |||
| 561 | /* Bit definitions and macros for MCF_GPIO_PODR_UART */ | ||
| 562 | #define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) | ||
| 563 | #define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) | ||
| 564 | #define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) | ||
| 565 | #define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) | ||
| 566 | #define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) | ||
| 567 | #define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) | ||
| 568 | #define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) | ||
| 569 | #define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) | ||
| 570 | |||
| 571 | /* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ | ||
| 572 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) | ||
| 573 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) | ||
| 574 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) | ||
| 575 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) | ||
| 576 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) | ||
| 577 | #define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) | ||
| 578 | |||
| 579 | /* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ | ||
| 580 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) | ||
| 581 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) | ||
| 582 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) | ||
| 583 | #define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) | ||
| 584 | |||
| 585 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ | ||
| 586 | #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) | ||
| 587 | #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) | ||
| 588 | |||
| 589 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ | ||
| 590 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) | ||
| 591 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) | ||
| 592 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) | ||
| 593 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) | ||
| 594 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) | ||
| 595 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) | ||
| 596 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) | ||
| 597 | #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) | ||
| 598 | |||
| 599 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ | ||
| 600 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) | ||
| 601 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) | ||
| 602 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) | ||
| 603 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) | ||
| 604 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) | ||
| 605 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) | ||
| 606 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) | ||
| 607 | #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) | ||
| 608 | |||
| 609 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ | ||
| 610 | #define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) | ||
| 611 | |||
| 612 | /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ | ||
| 613 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) | ||
| 614 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) | ||
| 615 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) | ||
| 616 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) | ||
| 617 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) | ||
| 618 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) | ||
| 619 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) | ||
| 620 | #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) | ||
| 621 | |||
| 622 | /* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ | ||
| 623 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) | ||
| 624 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) | ||
| 625 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) | ||
| 626 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) | ||
| 627 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) | ||
| 628 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) | ||
| 629 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) | ||
| 630 | #define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) | ||
| 631 | |||
| 632 | /* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ | ||
| 633 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) | ||
| 634 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) | ||
| 635 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) | ||
| 636 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) | ||
| 637 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) | ||
| 638 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) | ||
| 639 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) | ||
| 640 | #define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) | ||
| 641 | |||
| 642 | /* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ | ||
| 643 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) | ||
| 644 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) | ||
| 645 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) | ||
| 646 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) | ||
| 647 | #define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) | ||
| 648 | |||
| 649 | /* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ | ||
| 650 | #define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01) | ||
| 651 | #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) | ||
| 652 | #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) | ||
| 653 | #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) | ||
| 654 | |||
| 655 | /* Bit definitions and macros for MCF_GPIO_PDDR_BE */ | ||
| 656 | #define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) | ||
| 657 | #define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) | ||
| 658 | #define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) | ||
| 659 | #define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) | ||
| 660 | |||
| 661 | /* Bit definitions and macros for MCF_GPIO_PDDR_CS */ | ||
| 662 | #define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) | ||
| 663 | #define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) | ||
| 664 | #define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) | ||
| 665 | #define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) | ||
| 666 | #define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) | ||
| 667 | |||
| 668 | /* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ | ||
| 669 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) | ||
| 670 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) | ||
| 671 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) | ||
| 672 | #define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) | ||
| 673 | |||
| 674 | /* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ | ||
| 675 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) | ||
| 676 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) | ||
| 677 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) | ||
| 678 | #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) | ||
| 679 | |||
| 680 | /* Bit definitions and macros for MCF_GPIO_PDDR_UART */ | ||
| 681 | #define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) | ||
| 682 | #define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) | ||
| 683 | #define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) | ||
| 684 | #define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) | ||
| 685 | #define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) | ||
| 686 | #define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) | ||
| 687 | #define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) | ||
| 688 | #define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) | ||
| 689 | |||
| 690 | /* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ | ||
| 691 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) | ||
| 692 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) | ||
| 693 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) | ||
| 694 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) | ||
| 695 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) | ||
| 696 | #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) | ||
| 697 | |||
| 698 | /* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ | ||
| 699 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) | ||
| 700 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) | ||
| 701 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) | ||
| 702 | #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) | ||
| 703 | |||
| 704 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ | ||
| 705 | #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) | ||
| 706 | #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) | ||
| 707 | |||
| 708 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ | ||
| 709 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) | ||
| 710 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) | ||
| 711 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) | ||
| 712 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) | ||
| 713 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) | ||
| 714 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) | ||
| 715 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) | ||
| 716 | #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) | ||
| 717 | |||
| 718 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ | ||
| 719 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) | ||
| 720 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) | ||
| 721 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) | ||
| 722 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) | ||
| 723 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) | ||
| 724 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) | ||
| 725 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) | ||
| 726 | #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) | ||
| 727 | |||
| 728 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ | ||
| 729 | #define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) | ||
| 730 | |||
| 731 | /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ | ||
| 732 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) | ||
| 733 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) | ||
| 734 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) | ||
| 735 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) | ||
| 736 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) | ||
| 737 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) | ||
| 738 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) | ||
| 739 | #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) | ||
| 740 | |||
| 741 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ | ||
| 742 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) | ||
| 743 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) | ||
| 744 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) | ||
| 745 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) | ||
| 746 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) | ||
| 747 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) | ||
| 748 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) | ||
| 749 | #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) | ||
| 750 | |||
| 751 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ | ||
| 752 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) | ||
| 753 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) | ||
| 754 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) | ||
| 755 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) | ||
| 756 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) | ||
| 757 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) | ||
| 758 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) | ||
| 759 | #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) | ||
| 760 | |||
| 761 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ | ||
| 762 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) | ||
| 763 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) | ||
| 764 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) | ||
| 765 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) | ||
| 766 | #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) | ||
| 767 | |||
| 768 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ | ||
| 769 | #define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01) | ||
| 770 | #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) | ||
| 771 | #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) | ||
| 772 | #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) | ||
| 773 | |||
| 774 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ | ||
| 775 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) | ||
| 776 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) | ||
| 777 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) | ||
| 778 | #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) | ||
| 779 | |||
| 780 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ | ||
| 781 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) | ||
| 782 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) | ||
| 783 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) | ||
| 784 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) | ||
| 785 | #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) | ||
| 786 | |||
| 787 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ | ||
| 788 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) | ||
| 789 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) | ||
| 790 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) | ||
| 791 | #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) | ||
| 792 | |||
| 793 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ | ||
| 794 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) | ||
| 795 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) | ||
| 796 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) | ||
| 797 | #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) | ||
| 798 | |||
| 799 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ | ||
| 800 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) | ||
| 801 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) | ||
| 802 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) | ||
| 803 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) | ||
| 804 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) | ||
| 805 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) | ||
| 806 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) | ||
| 807 | #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) | ||
| 808 | |||
| 809 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ | ||
| 810 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) | ||
| 811 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) | ||
| 812 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) | ||
| 813 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) | ||
| 814 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) | ||
| 815 | #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) | ||
| 816 | |||
| 817 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ | ||
| 818 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) | ||
| 819 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) | ||
| 820 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) | ||
| 821 | #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) | ||
| 822 | |||
| 823 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ | ||
| 824 | #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) | ||
| 825 | #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) | ||
| 826 | |||
| 827 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ | ||
| 828 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) | ||
| 829 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) | ||
| 830 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) | ||
| 831 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) | ||
| 832 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) | ||
| 833 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) | ||
| 834 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) | ||
| 835 | #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) | ||
| 836 | |||
| 837 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ | ||
| 838 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) | ||
| 839 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) | ||
| 840 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) | ||
| 841 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) | ||
| 842 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) | ||
| 843 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) | ||
| 844 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) | ||
| 845 | #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) | ||
| 846 | |||
| 847 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ | ||
| 848 | #define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) | ||
| 849 | |||
| 850 | /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ | ||
| 851 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) | ||
| 852 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) | ||
| 853 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) | ||
| 854 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) | ||
| 855 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) | ||
| 856 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) | ||
| 857 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) | ||
| 858 | #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) | ||
| 859 | |||
| 860 | /* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ | ||
| 861 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) | ||
| 862 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) | ||
| 863 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) | ||
| 864 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) | ||
| 865 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) | ||
| 866 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) | ||
| 867 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) | ||
| 868 | #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) | ||
| 869 | |||
| 870 | /* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ | ||
| 871 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) | ||
| 872 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) | ||
| 873 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) | ||
| 874 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) | ||
| 875 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) | ||
| 876 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) | ||
| 877 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) | ||
| 878 | #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) | ||
| 879 | |||
| 880 | /* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ | ||
| 881 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) | ||
| 882 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) | ||
| 883 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) | ||
| 884 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) | ||
| 885 | #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) | ||
| 886 | |||
| 887 | /* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ | ||
| 888 | #define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01) | ||
| 889 | #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) | ||
| 890 | #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) | ||
| 891 | #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) | ||
| 892 | |||
| 893 | /* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ | ||
| 894 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) | ||
| 895 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) | ||
| 896 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) | ||
| 897 | #define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) | ||
| 898 | |||
| 899 | /* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ | ||
| 900 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) | ||
| 901 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) | ||
| 902 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) | ||
| 903 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) | ||
| 904 | #define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) | ||
| 905 | |||
| 906 | /* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ | ||
| 907 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) | ||
| 908 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) | ||
| 909 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) | ||
| 910 | #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) | ||
| 911 | |||
| 912 | /* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ | ||
| 913 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) | ||
| 914 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) | ||
| 915 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) | ||
| 916 | #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) | ||
| 917 | |||
| 918 | /* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ | ||
| 919 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) | ||
| 920 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) | ||
| 921 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) | ||
| 922 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) | ||
| 923 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) | ||
| 924 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) | ||
| 925 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) | ||
| 926 | #define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) | ||
| 927 | |||
| 928 | /* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ | ||
| 929 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) | ||
| 930 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) | ||
| 931 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) | ||
| 932 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) | ||
| 933 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) | ||
| 934 | #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) | ||
| 935 | |||
| 936 | /* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ | ||
| 937 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) | ||
| 938 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) | ||
| 939 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) | ||
| 940 | #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) | ||
| 941 | |||
| 942 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ | ||
| 943 | #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) | ||
| 944 | #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) | ||
| 945 | |||
| 946 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ | ||
| 947 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) | ||
| 948 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) | ||
| 949 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) | ||
| 950 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) | ||
| 951 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) | ||
| 952 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) | ||
| 953 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) | ||
| 954 | #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) | ||
| 955 | |||
| 956 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ | ||
| 957 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) | ||
| 958 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) | ||
| 959 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) | ||
| 960 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) | ||
| 961 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) | ||
| 962 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) | ||
| 963 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) | ||
| 964 | #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) | ||
| 965 | |||
| 966 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ | ||
| 967 | #define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) | ||
| 968 | |||
| 969 | /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ | ||
| 970 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) | ||
| 971 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) | ||
| 972 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) | ||
| 973 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) | ||
| 974 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) | ||
| 975 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) | ||
| 976 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) | ||
| 977 | #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) | ||
| 978 | |||
| 979 | /* Bit definitions and macros for MCF_GPIO_PAR_FEC */ | ||
| 980 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) | ||
| 981 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) | ||
| 982 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) | ||
| 983 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) | ||
| 984 | #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) | ||
| 985 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) | ||
| 986 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) | ||
| 987 | #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) | ||
| 988 | |||
| 989 | /* Bit definitions and macros for MCF_GPIO_PAR_PWM */ | ||
| 990 | #define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) | ||
| 991 | #define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) | ||
| 992 | #define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) | ||
| 993 | #define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) | ||
| 994 | |||
| 995 | /* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ | ||
| 996 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) | ||
| 997 | #define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) | ||
| 998 | #define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) | ||
| 999 | #define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) | ||
| 1000 | #define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) | ||
| 1001 | #define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) | ||
| 1002 | #define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) | ||
| 1003 | #define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) | ||
| 1004 | #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) | ||
| 1005 | #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) | ||
| 1006 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) | ||
| 1007 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) | ||
| 1008 | #define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) | ||
| 1009 | |||
| 1010 | /* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ | ||
| 1011 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) | ||
| 1012 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) | ||
| 1013 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) | ||
| 1014 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) | ||
| 1015 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) | ||
| 1016 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) | ||
| 1017 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) | ||
| 1018 | #define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) | ||
| 1019 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) | ||
| 1020 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) | ||
| 1021 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) | ||
| 1022 | #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) | ||
| 1023 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) | ||
| 1024 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) | ||
| 1025 | #define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) | ||
| 1026 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) | ||
| 1027 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) | ||
| 1028 | #define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) | ||
| 1029 | |||
| 1030 | /* Bit definitions and macros for MCF_GPIO_PAR_BE */ | ||
| 1031 | #define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) | ||
| 1032 | #define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) | ||
| 1033 | #define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) | ||
| 1034 | #define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) | ||
| 1035 | |||
| 1036 | /* Bit definitions and macros for MCF_GPIO_PAR_CS */ | ||
| 1037 | #define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) | ||
| 1038 | #define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) | ||
| 1039 | #define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) | ||
| 1040 | #define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) | ||
| 1041 | #define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) | ||
| 1042 | #define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) | ||
| 1043 | #define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) | ||
| 1044 | #define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) | ||
| 1045 | |||
| 1046 | /* Bit definitions and macros for MCF_GPIO_PAR_SSI */ | ||
| 1047 | #define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) | ||
| 1048 | #define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) | ||
| 1049 | #define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) | ||
| 1050 | #define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) | ||
| 1051 | #define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) | ||
| 1052 | |||
| 1053 | /* Bit definitions and macros for MCF_GPIO_PAR_UART */ | ||
| 1054 | #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) | ||
| 1055 | #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) | ||
| 1056 | #define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) | ||
| 1057 | #define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) | ||
| 1058 | #define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) | ||
| 1059 | #define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) | ||
| 1060 | #define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) | ||
| 1061 | #define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) | ||
| 1062 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) | ||
| 1063 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) | ||
| 1064 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) | ||
| 1065 | #define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) | ||
| 1066 | #define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) | ||
| 1067 | #define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) | ||
| 1068 | #define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) | ||
| 1069 | #define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) | ||
| 1070 | #define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) | ||
| 1071 | #define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) | ||
| 1072 | #define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) | ||
| 1073 | #define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) | ||
| 1074 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) | ||
| 1075 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) | ||
| 1076 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) | ||
| 1077 | #define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) | ||
| 1078 | |||
| 1079 | /* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ | ||
| 1080 | #define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) | ||
| 1081 | #define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) | ||
| 1082 | #define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) | ||
| 1083 | #define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) | ||
| 1084 | #define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) | ||
| 1085 | #define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) | ||
| 1086 | |||
| 1087 | /* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ | ||
| 1088 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) | ||
| 1089 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) | ||
| 1090 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) | ||
| 1091 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) | ||
| 1092 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) | ||
| 1093 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) | ||
| 1094 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) | ||
| 1095 | #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) | ||
| 1096 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) | ||
| 1097 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) | ||
| 1098 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) | ||
| 1099 | #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) | ||
| 1100 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) | ||
| 1101 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) | ||
| 1102 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) | ||
| 1103 | #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) | ||
| 1104 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) | ||
| 1105 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) | ||
| 1106 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) | ||
| 1107 | #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) | ||
| 1108 | |||
| 1109 | /* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ | ||
| 1110 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) | ||
| 1111 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) | ||
| 1112 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) | ||
| 1113 | #define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) | ||
| 1114 | |||
| 1115 | /* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ | ||
| 1116 | #define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) | ||
| 1117 | #define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) | ||
| 1118 | #define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) | ||
| 1119 | #define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) | ||
| 1120 | #define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) | ||
| 1121 | #define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) | ||
| 1122 | #define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) | ||
| 1123 | #define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) | ||
| 1124 | #define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) | ||
| 1125 | |||
| 1126 | /* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ | ||
| 1127 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) | ||
| 1128 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) | ||
| 1129 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) | ||
| 1130 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) | ||
| 1131 | #define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) | ||
| 1132 | |||
| 1133 | /* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ | ||
| 1134 | #define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) | ||
| 1135 | #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) | ||
| 1136 | #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) | ||
| 1137 | |||
| 1138 | /* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ | ||
| 1139 | #define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) | ||
| 1140 | #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) | ||
| 1141 | #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) | ||
| 1142 | |||
| 1143 | /* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ | ||
| 1144 | #define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) | ||
| 1145 | |||
| 1146 | /* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ | ||
| 1147 | #define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) | ||
| 1148 | |||
| 1149 | /* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ | ||
| 1150 | #define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) | ||
| 1151 | |||
| 1152 | /* Bit definitions and macros for MCF_GPIO_DSCR_UART */ | ||
| 1153 | #define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) | ||
| 1154 | #define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) | ||
| 1155 | |||
| 1156 | /* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ | ||
| 1157 | #define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) | ||
| 1158 | |||
| 1159 | /* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ | ||
| 1160 | #define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) | ||
| 1161 | |||
| 1162 | /* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ | ||
| 1163 | #define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) | ||
| 1164 | |||
| 1165 | /* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ | ||
| 1166 | #define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) | ||
| 1167 | |||
| 1168 | /* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ | ||
| 1169 | #define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) | ||
| 1170 | |||
| 1171 | /* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ | ||
| 1172 | #define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0) | ||
| 1173 | |||
| 1174 | /* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ | ||
| 1175 | #define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) | ||
| 1176 | |||
| 1177 | /********************************************************************* | ||
| 1178 | * | ||
| 1179 | * Interrupt Controller (INTC) | ||
| 1180 | * | ||
| 1181 | *********************************************************************/ | ||
| 1182 | |||
| 1183 | /* Register read/write macros */ | ||
| 1184 | #define MCF_INTC0_IPRH MCF_REG32(0xFC048000) | ||
| 1185 | #define MCF_INTC0_IPRL MCF_REG32(0xFC048004) | ||
| 1186 | #define MCF_INTC0_IMRH MCF_REG32(0xFC048008) | ||
| 1187 | #define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) | ||
| 1188 | #define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) | ||
| 1189 | #define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) | ||
| 1190 | #define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) | ||
| 1191 | #define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) | ||
| 1192 | #define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) | ||
| 1193 | #define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) | ||
| 1194 | #define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) | ||
| 1195 | #define MCF_INTC0_ICR0 MCF_REG08(0xFC048040) | ||
| 1196 | #define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) | ||
| 1197 | #define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) | ||
| 1198 | #define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) | ||
| 1199 | #define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) | ||
| 1200 | #define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) | ||
| 1201 | #define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) | ||
| 1202 | #define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) | ||
| 1203 | #define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) | ||
| 1204 | #define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) | ||
| 1205 | #define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) | ||
| 1206 | #define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) | ||
| 1207 | #define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) | ||
| 1208 | #define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) | ||
| 1209 | #define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) | ||
| 1210 | #define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) | ||
| 1211 | #define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) | ||
| 1212 | #define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) | ||
| 1213 | #define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) | ||
| 1214 | #define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) | ||
| 1215 | #define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) | ||
| 1216 | #define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) | ||
| 1217 | #define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) | ||
| 1218 | #define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) | ||
| 1219 | #define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) | ||
| 1220 | #define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) | ||
| 1221 | #define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) | ||
| 1222 | #define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) | ||
| 1223 | #define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) | ||
| 1224 | #define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) | ||
| 1225 | #define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) | ||
| 1226 | #define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) | ||
| 1227 | #define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) | ||
| 1228 | #define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) | ||
| 1229 | #define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) | ||
| 1230 | #define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) | ||
| 1231 | #define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) | ||
| 1232 | #define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) | ||
| 1233 | #define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) | ||
| 1234 | #define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) | ||
| 1235 | #define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) | ||
| 1236 | #define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) | ||
| 1237 | #define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) | ||
| 1238 | #define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) | ||
| 1239 | #define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) | ||
| 1240 | #define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) | ||
| 1241 | #define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) | ||
| 1242 | #define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) | ||
| 1243 | #define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) | ||
| 1244 | #define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) | ||
| 1245 | #define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) | ||
| 1246 | #define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) | ||
| 1247 | #define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) | ||
| 1248 | #define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) | ||
| 1249 | #define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) | ||
| 1250 | #define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) | ||
| 1251 | #define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) | ||
| 1252 | #define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) | ||
| 1253 | #define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) | ||
| 1254 | #define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) | ||
| 1255 | #define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) | ||
| 1256 | #define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) | ||
| 1257 | #define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) | ||
| 1258 | #define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) | ||
| 1259 | #define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001)) | ||
| 1260 | #define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) | ||
| 1261 | #define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) | ||
| 1262 | #define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) | ||
| 1263 | #define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) | ||
| 1264 | #define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) | ||
| 1265 | #define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) | ||
| 1266 | #define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) | ||
| 1267 | #define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) | ||
| 1268 | #define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004)) | ||
| 1269 | #define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) | ||
| 1270 | #define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) | ||
| 1271 | #define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) | ||
| 1272 | #define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) | ||
| 1273 | #define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) | ||
| 1274 | #define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) | ||
| 1275 | #define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) | ||
| 1276 | #define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) | ||
| 1277 | #define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) | ||
| 1278 | #define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) | ||
| 1279 | #define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) | ||
| 1280 | #define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040) | ||
| 1281 | #define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) | ||
| 1282 | #define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) | ||
| 1283 | #define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) | ||
| 1284 | #define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) | ||
| 1285 | #define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) | ||
| 1286 | #define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) | ||
| 1287 | #define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) | ||
| 1288 | #define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) | ||
| 1289 | #define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) | ||
| 1290 | #define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) | ||
| 1291 | #define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) | ||
| 1292 | #define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) | ||
| 1293 | #define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) | ||
| 1294 | #define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) | ||
| 1295 | #define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) | ||
| 1296 | #define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) | ||
| 1297 | #define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) | ||
| 1298 | #define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) | ||
| 1299 | #define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) | ||
| 1300 | #define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) | ||
| 1301 | #define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) | ||
| 1302 | #define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) | ||
| 1303 | #define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) | ||
| 1304 | #define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) | ||
| 1305 | #define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) | ||
| 1306 | #define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) | ||
| 1307 | #define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) | ||
| 1308 | #define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) | ||
| 1309 | #define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) | ||
| 1310 | #define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) | ||
| 1311 | #define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) | ||
| 1312 | #define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) | ||
| 1313 | #define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) | ||
| 1314 | #define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) | ||
| 1315 | #define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) | ||
| 1316 | #define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) | ||
| 1317 | #define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) | ||
| 1318 | #define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) | ||
| 1319 | #define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) | ||
| 1320 | #define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) | ||
| 1321 | #define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) | ||
| 1322 | #define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) | ||
| 1323 | #define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) | ||
| 1324 | #define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) | ||
| 1325 | #define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) | ||
| 1326 | #define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) | ||
| 1327 | #define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) | ||
| 1328 | #define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) | ||
| 1329 | #define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) | ||
| 1330 | #define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) | ||
| 1331 | #define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) | ||
| 1332 | #define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) | ||
| 1333 | #define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) | ||
| 1334 | #define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) | ||
| 1335 | #define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) | ||
| 1336 | #define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) | ||
| 1337 | #define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) | ||
| 1338 | #define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) | ||
| 1339 | #define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) | ||
| 1340 | #define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) | ||
| 1341 | #define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) | ||
| 1342 | #define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) | ||
| 1343 | #define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) | ||
| 1344 | #define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001)) | ||
| 1345 | #define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) | ||
| 1346 | #define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) | ||
| 1347 | #define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) | ||
| 1348 | #define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) | ||
| 1349 | #define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) | ||
| 1350 | #define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) | ||
| 1351 | #define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8) | ||
| 1352 | #define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) | ||
| 1353 | #define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004)) | ||
| 1354 | #define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) | ||
| 1355 | #define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) | ||
| 1356 | #define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) | ||
| 1357 | #define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) | ||
| 1358 | #define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) | ||
| 1359 | #define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) | ||
| 1360 | #define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) | ||
| 1361 | #define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) | ||
| 1362 | #define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) | ||
| 1363 | #define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) | ||
| 1364 | #define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) | ||
| 1365 | #define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000)) | ||
| 1366 | #define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) | ||
| 1367 | #define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) | ||
| 1368 | #define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) | ||
| 1369 | #define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) | ||
| 1370 | #define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) | ||
| 1371 | #define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) | ||
| 1372 | #define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) | ||
| 1373 | #define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) | ||
| 1374 | #define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) | ||
| 1375 | #define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) | ||
| 1376 | #define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) | ||
| 1377 | #define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) | ||
| 1378 | #define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) | ||
| 1379 | #define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) | ||
| 1380 | #define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) | ||
| 1381 | #define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) | ||
| 1382 | #define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) | ||
| 1383 | #define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) | ||
| 1384 | #define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) | ||
| 1385 | #define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) | ||
| 1386 | #define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) | ||
| 1387 | #define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) | ||
| 1388 | #define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) | ||
| 1389 | #define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) | ||
| 1390 | #define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) | ||
| 1391 | #define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) | ||
| 1392 | #define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) | ||
| 1393 | #define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) | ||
| 1394 | #define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) | ||
| 1395 | #define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) | ||
| 1396 | #define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) | ||
| 1397 | #define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) | ||
| 1398 | #define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) | ||
| 1399 | #define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) | ||
| 1400 | #define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) | ||
| 1401 | #define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) | ||
| 1402 | #define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) | ||
| 1403 | #define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) | ||
| 1404 | #define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) | ||
| 1405 | #define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) | ||
| 1406 | #define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) | ||
| 1407 | #define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) | ||
| 1408 | #define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) | ||
| 1409 | #define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) | ||
| 1410 | #define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) | ||
| 1411 | #define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) | ||
| 1412 | #define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) | ||
| 1413 | #define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) | ||
| 1414 | #define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) | ||
| 1415 | #define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) | ||
| 1416 | #define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) | ||
| 1417 | #define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) | ||
| 1418 | #define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) | ||
| 1419 | #define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) | ||
| 1420 | #define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) | ||
| 1421 | #define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) | ||
| 1422 | #define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) | ||
| 1423 | #define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) | ||
| 1424 | #define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) | ||
| 1425 | #define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) | ||
| 1426 | #define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) | ||
| 1427 | #define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) | ||
| 1428 | #define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) | ||
| 1429 | #define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) | ||
| 1430 | #define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) | ||
| 1431 | #define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) | ||
| 1432 | #define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) | ||
| 1433 | #define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) | ||
| 1434 | #define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) | ||
| 1435 | #define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) | ||
| 1436 | #define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) | ||
| 1437 | |||
| 1438 | /* Bit definitions and macros for MCF_INTC_IPRH */ | ||
| 1439 | #define MCF_INTC_IPRH_INT32 (0x00000001) | ||
| 1440 | #define MCF_INTC_IPRH_INT33 (0x00000002) | ||
| 1441 | #define MCF_INTC_IPRH_INT34 (0x00000004) | ||
| 1442 | #define MCF_INTC_IPRH_INT35 (0x00000008) | ||
| 1443 | #define MCF_INTC_IPRH_INT36 (0x00000010) | ||
| 1444 | #define MCF_INTC_IPRH_INT37 (0x00000020) | ||
| 1445 | #define MCF_INTC_IPRH_INT38 (0x00000040) | ||
| 1446 | #define MCF_INTC_IPRH_INT39 (0x00000080) | ||
| 1447 | #define MCF_INTC_IPRH_INT40 (0x00000100) | ||
| 1448 | #define MCF_INTC_IPRH_INT41 (0x00000200) | ||
| 1449 | #define MCF_INTC_IPRH_INT42 (0x00000400) | ||
| 1450 | #define MCF_INTC_IPRH_INT43 (0x00000800) | ||
| 1451 | #define MCF_INTC_IPRH_INT44 (0x00001000) | ||
| 1452 | #define MCF_INTC_IPRH_INT45 (0x00002000) | ||
| 1453 | #define MCF_INTC_IPRH_INT46 (0x00004000) | ||
| 1454 | #define MCF_INTC_IPRH_INT47 (0x00008000) | ||
| 1455 | #define MCF_INTC_IPRH_INT48 (0x00010000) | ||
| 1456 | #define MCF_INTC_IPRH_INT49 (0x00020000) | ||
| 1457 | #define MCF_INTC_IPRH_INT50 (0x00040000) | ||
| 1458 | #define MCF_INTC_IPRH_INT51 (0x00080000) | ||
| 1459 | #define MCF_INTC_IPRH_INT52 (0x00100000) | ||
| 1460 | #define MCF_INTC_IPRH_INT53 (0x00200000) | ||
| 1461 | #define MCF_INTC_IPRH_INT54 (0x00400000) | ||
| 1462 | #define MCF_INTC_IPRH_INT55 (0x00800000) | ||
| 1463 | #define MCF_INTC_IPRH_INT56 (0x01000000) | ||
| 1464 | #define MCF_INTC_IPRH_INT57 (0x02000000) | ||
| 1465 | #define MCF_INTC_IPRH_INT58 (0x04000000) | ||
| 1466 | #define MCF_INTC_IPRH_INT59 (0x08000000) | ||
| 1467 | #define MCF_INTC_IPRH_INT60 (0x10000000) | ||
| 1468 | #define MCF_INTC_IPRH_INT61 (0x20000000) | ||
| 1469 | #define MCF_INTC_IPRH_INT62 (0x40000000) | ||
| 1470 | #define MCF_INTC_IPRH_INT63 (0x80000000) | ||
| 1471 | |||
| 1472 | /* Bit definitions and macros for MCF_INTC_IPRL */ | ||
| 1473 | #define MCF_INTC_IPRL_INT0 (0x00000001) | ||
| 1474 | #define MCF_INTC_IPRL_INT1 (0x00000002) | ||
| 1475 | #define MCF_INTC_IPRL_INT2 (0x00000004) | ||
| 1476 | #define MCF_INTC_IPRL_INT3 (0x00000008) | ||
| 1477 | #define MCF_INTC_IPRL_INT4 (0x00000010) | ||
| 1478 | #define MCF_INTC_IPRL_INT5 (0x00000020) | ||
| 1479 | #define MCF_INTC_IPRL_INT6 (0x00000040) | ||
| 1480 | #define MCF_INTC_IPRL_INT7 (0x00000080) | ||
| 1481 | #define MCF_INTC_IPRL_INT8 (0x00000100) | ||
| 1482 | #define MCF_INTC_IPRL_INT9 (0x00000200) | ||
| 1483 | #define MCF_INTC_IPRL_INT10 (0x00000400) | ||
| 1484 | #define MCF_INTC_IPRL_INT11 (0x00000800) | ||
| 1485 | #define MCF_INTC_IPRL_INT12 (0x00001000) | ||
| 1486 | #define MCF_INTC_IPRL_INT13 (0x00002000) | ||
| 1487 | #define MCF_INTC_IPRL_INT14 (0x00004000) | ||
| 1488 | #define MCF_INTC_IPRL_INT15 (0x00008000) | ||
| 1489 | #define MCF_INTC_IPRL_INT16 (0x00010000) | ||
| 1490 | #define MCF_INTC_IPRL_INT17 (0x00020000) | ||
| 1491 | #define MCF_INTC_IPRL_INT18 (0x00040000) | ||
| 1492 | #define MCF_INTC_IPRL_INT19 (0x00080000) | ||
| 1493 | #define MCF_INTC_IPRL_INT20 (0x00100000) | ||
| 1494 | #define MCF_INTC_IPRL_INT21 (0x00200000) | ||
| 1495 | #define MCF_INTC_IPRL_INT22 (0x00400000) | ||
| 1496 | #define MCF_INTC_IPRL_INT23 (0x00800000) | ||
| 1497 | #define MCF_INTC_IPRL_INT24 (0x01000000) | ||
| 1498 | #define MCF_INTC_IPRL_INT25 (0x02000000) | ||
| 1499 | #define MCF_INTC_IPRL_INT26 (0x04000000) | ||
| 1500 | #define MCF_INTC_IPRL_INT27 (0x08000000) | ||
| 1501 | #define MCF_INTC_IPRL_INT28 (0x10000000) | ||
| 1502 | #define MCF_INTC_IPRL_INT29 (0x20000000) | ||
| 1503 | #define MCF_INTC_IPRL_INT30 (0x40000000) | ||
| 1504 | #define MCF_INTC_IPRL_INT31 (0x80000000) | ||
| 1505 | |||
| 1506 | /* Bit definitions and macros for MCF_INTC_IMRH */ | ||
| 1507 | #define MCF_INTC_IMRH_INT_MASK32 (0x00000001) | ||
| 1508 | #define MCF_INTC_IMRH_INT_MASK33 (0x00000002) | ||
| 1509 | #define MCF_INTC_IMRH_INT_MASK34 (0x00000004) | ||
| 1510 | #define MCF_INTC_IMRH_INT_MASK35 (0x00000008) | ||
| 1511 | #define MCF_INTC_IMRH_INT_MASK36 (0x00000010) | ||
| 1512 | #define MCF_INTC_IMRH_INT_MASK37 (0x00000020) | ||
| 1513 | #define MCF_INTC_IMRH_INT_MASK38 (0x00000040) | ||
| 1514 | #define MCF_INTC_IMRH_INT_MASK39 (0x00000080) | ||
| 1515 | #define MCF_INTC_IMRH_INT_MASK40 (0x00000100) | ||
| 1516 | #define MCF_INTC_IMRH_INT_MASK41 (0x00000200) | ||
| 1517 | #define MCF_INTC_IMRH_INT_MASK42 (0x00000400) | ||
| 1518 | #define MCF_INTC_IMRH_INT_MASK43 (0x00000800) | ||
| 1519 | #define MCF_INTC_IMRH_INT_MASK44 (0x00001000) | ||
| 1520 | #define MCF_INTC_IMRH_INT_MASK45 (0x00002000) | ||
| 1521 | #define MCF_INTC_IMRH_INT_MASK46 (0x00004000) | ||
| 1522 | #define MCF_INTC_IMRH_INT_MASK47 (0x00008000) | ||
| 1523 | #define MCF_INTC_IMRH_INT_MASK48 (0x00010000) | ||
| 1524 | #define MCF_INTC_IMRH_INT_MASK49 (0x00020000) | ||
| 1525 | #define MCF_INTC_IMRH_INT_MASK50 (0x00040000) | ||
| 1526 | #define MCF_INTC_IMRH_INT_MASK51 (0x00080000) | ||
| 1527 | #define MCF_INTC_IMRH_INT_MASK52 (0x00100000) | ||
| 1528 | #define MCF_INTC_IMRH_INT_MASK53 (0x00200000) | ||
| 1529 | #define MCF_INTC_IMRH_INT_MASK54 (0x00400000) | ||
| 1530 | #define MCF_INTC_IMRH_INT_MASK55 (0x00800000) | ||
| 1531 | #define MCF_INTC_IMRH_INT_MASK56 (0x01000000) | ||
| 1532 | #define MCF_INTC_IMRH_INT_MASK57 (0x02000000) | ||
| 1533 | #define MCF_INTC_IMRH_INT_MASK58 (0x04000000) | ||
| 1534 | #define MCF_INTC_IMRH_INT_MASK59 (0x08000000) | ||
| 1535 | #define MCF_INTC_IMRH_INT_MASK60 (0x10000000) | ||
| 1536 | #define MCF_INTC_IMRH_INT_MASK61 (0x20000000) | ||
| 1537 | #define MCF_INTC_IMRH_INT_MASK62 (0x40000000) | ||
| 1538 | #define MCF_INTC_IMRH_INT_MASK63 (0x80000000) | ||
| 1539 | |||
| 1540 | /* Bit definitions and macros for MCF_INTC_IMRL */ | ||
| 1541 | #define MCF_INTC_IMRL_INT_MASK0 (0x00000001) | ||
| 1542 | #define MCF_INTC_IMRL_INT_MASK1 (0x00000002) | ||
| 1543 | #define MCF_INTC_IMRL_INT_MASK2 (0x00000004) | ||
| 1544 | #define MCF_INTC_IMRL_INT_MASK3 (0x00000008) | ||
| 1545 | #define MCF_INTC_IMRL_INT_MASK4 (0x00000010) | ||
| 1546 | #define MCF_INTC_IMRL_INT_MASK5 (0x00000020) | ||
| 1547 | #define MCF_INTC_IMRL_INT_MASK6 (0x00000040) | ||
| 1548 | #define MCF_INTC_IMRL_INT_MASK7 (0x00000080) | ||
| 1549 | #define MCF_INTC_IMRL_INT_MASK8 (0x00000100) | ||
| 1550 | #define MCF_INTC_IMRL_INT_MASK9 (0x00000200) | ||
| 1551 | #define MCF_INTC_IMRL_INT_MASK10 (0x00000400) | ||
| 1552 | #define MCF_INTC_IMRL_INT_MASK11 (0x00000800) | ||
| 1553 | #define MCF_INTC_IMRL_INT_MASK12 (0x00001000) | ||
| 1554 | #define MCF_INTC_IMRL_INT_MASK13 (0x00002000) | ||
| 1555 | #define MCF_INTC_IMRL_INT_MASK14 (0x00004000) | ||
| 1556 | #define MCF_INTC_IMRL_INT_MASK15 (0x00008000) | ||
| 1557 | #define MCF_INTC_IMRL_INT_MASK16 (0x00010000) | ||
| 1558 | #define MCF_INTC_IMRL_INT_MASK17 (0x00020000) | ||
| 1559 | #define MCF_INTC_IMRL_INT_MASK18 (0x00040000) | ||
| 1560 | #define MCF_INTC_IMRL_INT_MASK19 (0x00080000) | ||
| 1561 | #define MCF_INTC_IMRL_INT_MASK20 (0x00100000) | ||
| 1562 | #define MCF_INTC_IMRL_INT_MASK21 (0x00200000) | ||
| 1563 | #define MCF_INTC_IMRL_INT_MASK22 (0x00400000) | ||
| 1564 | #define MCF_INTC_IMRL_INT_MASK23 (0x00800000) | ||
| 1565 | #define MCF_INTC_IMRL_INT_MASK24 (0x01000000) | ||
| 1566 | #define MCF_INTC_IMRL_INT_MASK25 (0x02000000) | ||
| 1567 | #define MCF_INTC_IMRL_INT_MASK26 (0x04000000) | ||
| 1568 | #define MCF_INTC_IMRL_INT_MASK27 (0x08000000) | ||
| 1569 | #define MCF_INTC_IMRL_INT_MASK28 (0x10000000) | ||
| 1570 | #define MCF_INTC_IMRL_INT_MASK29 (0x20000000) | ||
| 1571 | #define MCF_INTC_IMRL_INT_MASK30 (0x40000000) | ||
| 1572 | #define MCF_INTC_IMRL_INT_MASK31 (0x80000000) | ||
| 1573 | |||
| 1574 | /* Bit definitions and macros for MCF_INTC_INTFRCH */ | ||
| 1575 | #define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) | ||
| 1576 | #define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) | ||
| 1577 | #define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) | ||
| 1578 | #define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) | ||
| 1579 | #define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) | ||
| 1580 | #define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) | ||
| 1581 | #define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) | ||
| 1582 | #define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) | ||
| 1583 | #define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) | ||
| 1584 | #define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) | ||
| 1585 | #define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) | ||
| 1586 | #define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) | ||
| 1587 | #define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) | ||
| 1588 | #define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) | ||
| 1589 | #define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) | ||
| 1590 | #define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) | ||
| 1591 | #define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) | ||
| 1592 | #define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) | ||
| 1593 | #define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) | ||
| 1594 | #define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) | ||
| 1595 | #define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) | ||
| 1596 | #define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) | ||
| 1597 | #define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) | ||
| 1598 | #define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) | ||
| 1599 | #define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) | ||
| 1600 | #define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) | ||
| 1601 | #define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) | ||
| 1602 | #define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) | ||
| 1603 | #define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) | ||
| 1604 | #define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) | ||
| 1605 | #define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) | ||
| 1606 | #define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) | ||
| 1607 | |||
| 1608 | /* Bit definitions and macros for MCF_INTC_INTFRCL */ | ||
| 1609 | #define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) | ||
| 1610 | #define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) | ||
| 1611 | #define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) | ||
| 1612 | #define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) | ||
| 1613 | #define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) | ||
| 1614 | #define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) | ||
| 1615 | #define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) | ||
| 1616 | #define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) | ||
| 1617 | #define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) | ||
| 1618 | #define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) | ||
| 1619 | #define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) | ||
| 1620 | #define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) | ||
| 1621 | #define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) | ||
| 1622 | #define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) | ||
| 1623 | #define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) | ||
| 1624 | #define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) | ||
| 1625 | #define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) | ||
| 1626 | #define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) | ||
| 1627 | #define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) | ||
| 1628 | #define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) | ||
| 1629 | #define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) | ||
| 1630 | #define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) | ||
| 1631 | #define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) | ||
| 1632 | #define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) | ||
| 1633 | #define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) | ||
| 1634 | #define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) | ||
| 1635 | #define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) | ||
| 1636 | #define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) | ||
| 1637 | #define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) | ||
| 1638 | #define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) | ||
| 1639 | #define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) | ||
| 1640 | #define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) | ||
| 1641 | |||
| 1642 | /* Bit definitions and macros for MCF_INTC_ICONFIG */ | ||
| 1643 | #define MCF_INTC_ICONFIG_EMASK (0x0020) | ||
| 1644 | #define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) | ||
| 1645 | #define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) | ||
| 1646 | #define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) | ||
| 1647 | #define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) | ||
| 1648 | #define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) | ||
| 1649 | #define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) | ||
| 1650 | #define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) | ||
| 1651 | |||
| 1652 | /* Bit definitions and macros for MCF_INTC_SIMR */ | ||
| 1653 | #define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0) | ||
| 1654 | |||
| 1655 | /* Bit definitions and macros for MCF_INTC_CIMR */ | ||
| 1656 | #define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0) | ||
| 1657 | |||
| 1658 | /* Bit definitions and macros for MCF_INTC_CLMASK */ | ||
| 1659 | #define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0) | ||
| 1660 | |||
| 1661 | /* Bit definitions and macros for MCF_INTC_SLMASK */ | ||
| 1662 | #define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0) | ||
| 1663 | |||
| 1664 | /* Bit definitions and macros for MCF_INTC_ICR */ | ||
| 1665 | #define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0) | ||
| 1666 | |||
| 1667 | /* Bit definitions and macros for MCF_INTC_SWIACK */ | ||
| 1668 | #define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) | ||
| 1669 | |||
| 1670 | /* Bit definitions and macros for MCF_INTC_LIACK */ | ||
| 1671 | #define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) | ||
| 1672 | |||
| 1673 | /********************************************************************/ | ||
| 1674 | /********************************************************************* | ||
| 1675 | * | ||
| 1676 | * LCD Controller (LCDC) | ||
| 1677 | * | ||
| 1678 | *********************************************************************/ | ||
| 1679 | |||
| 1680 | /* Register read/write macros */ | ||
| 1681 | #define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000) | ||
| 1682 | #define MCF_LCDC_LSR MCF_REG32(0xFC0AC004) | ||
| 1683 | #define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008) | ||
| 1684 | #define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C) | ||
| 1685 | #define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010) | ||
| 1686 | #define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014) | ||
| 1687 | #define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018) | ||
| 1688 | #define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C) | ||
| 1689 | #define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020) | ||
| 1690 | #define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024) | ||
| 1691 | #define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028) | ||
| 1692 | #define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C) | ||
| 1693 | #define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030) | ||
| 1694 | #define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034) | ||
| 1695 | #define MCF_LCDC_LICR MCF_REG32(0xFC0AC038) | ||
| 1696 | #define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C) | ||
| 1697 | #define MCF_LCDC_LISR MCF_REG32(0xFC0AC040) | ||
| 1698 | #define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050) | ||
| 1699 | #define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054) | ||
| 1700 | #define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058) | ||
| 1701 | #define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C) | ||
| 1702 | #define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060) | ||
| 1703 | #define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064) | ||
| 1704 | #define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068) | ||
| 1705 | #define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800) | ||
| 1706 | #define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00) | ||
| 1707 | |||
| 1708 | /* Bit definitions and macros for MCF_LCDC_LSSAR */ | ||
| 1709 | #define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) | ||
| 1710 | |||
| 1711 | /* Bit definitions and macros for MCF_LCDC_LSR */ | ||
| 1712 | #define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) | ||
| 1713 | #define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) | ||
| 1714 | |||
| 1715 | /* Bit definitions and macros for MCF_LCDC_LVPWR */ | ||
| 1716 | #define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) | ||
| 1717 | |||
| 1718 | /* Bit definitions and macros for MCF_LCDC_LCPR */ | ||
| 1719 | #define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) | ||
| 1720 | #define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) | ||
| 1721 | #define MCF_LCDC_LCPR_OP (0x10000000) | ||
| 1722 | #define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) | ||
| 1723 | #define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000) | ||
| 1724 | #define MCF_LCDC_LCPR_CC_OR (0x40000000) | ||
| 1725 | #define MCF_LCDC_LCPR_CC_XOR (0x80000000) | ||
| 1726 | #define MCF_LCDC_LCPR_CC_AND (0xC0000000) | ||
| 1727 | #define MCF_LCDC_LCPR_OP_ON (0x10000000) | ||
| 1728 | #define MCF_LCDC_LCPR_OP_OFF (0x00000000) | ||
| 1729 | |||
| 1730 | /* Bit definitions and macros for MCF_LCDC_LCWHBR */ | ||
| 1731 | #define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) | ||
| 1732 | #define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) | ||
| 1733 | #define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) | ||
| 1734 | #define MCF_LCDC_LCWHBR_BK_EN (0x80000000) | ||
| 1735 | #define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000) | ||
| 1736 | #define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000) | ||
| 1737 | |||
| 1738 | /* Bit definitions and macros for MCF_LCDC_LCCMR */ | ||
| 1739 | #define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) | ||
| 1740 | #define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) | ||
| 1741 | #define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) | ||
| 1742 | |||
| 1743 | /* Bit definitions and macros for MCF_LCDC_LPCR */ | ||
| 1744 | #define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) | ||
| 1745 | #define MCF_LCDC_LPCR_SHARP (0x00000040) | ||
| 1746 | #define MCF_LCDC_LPCR_SCLKSEL (0x00000080) | ||
| 1747 | #define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) | ||
| 1748 | #define MCF_LCDC_LPCR_ACDSEL (0x00008000) | ||
| 1749 | #define MCF_LCDC_LPCR_REV_VS (0x00010000) | ||
| 1750 | #define MCF_LCDC_LPCR_SWAP_SEL (0x00020000) | ||
| 1751 | #define MCF_LCDC_LPCR_ENDSEL (0x00040000) | ||
| 1752 | #define MCF_LCDC_LPCR_SCLKIDLE (0x00080000) | ||
| 1753 | #define MCF_LCDC_LPCR_OEPOL (0x00100000) | ||
| 1754 | #define MCF_LCDC_LPCR_CLKPOL (0x00200000) | ||
| 1755 | #define MCF_LCDC_LPCR_LPPOL (0x00400000) | ||
| 1756 | #define MCF_LCDC_LPCR_FLM (0x00800000) | ||
| 1757 | #define MCF_LCDC_LPCR_PIXPOL (0x01000000) | ||
| 1758 | #define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) | ||
| 1759 | #define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) | ||
| 1760 | #define MCF_LCDC_LPCR_COLOR (0x40000000) | ||
| 1761 | #define MCF_LCDC_LPCR_TFT (0x80000000) | ||
| 1762 | #define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000) | ||
| 1763 | #define MCF_LCDC_LPCR_MODE_CSTN (0x40000000) | ||
| 1764 | #define MCF_LCDC_LPCR_MODE_TFT (0xC0000000) | ||
| 1765 | #define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000) | ||
| 1766 | #define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000) | ||
| 1767 | #define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000) | ||
| 1768 | #define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000) | ||
| 1769 | #define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000) | ||
| 1770 | #define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000) | ||
| 1771 | #define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000) | ||
| 1772 | #define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000) | ||
| 1773 | #define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000) | ||
| 1774 | #define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000) | ||
| 1775 | #define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000) | ||
| 1776 | |||
| 1777 | #define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) | ||
| 1778 | |||
| 1779 | /* Bit definitions and macros for MCF_LCDC_LHCR */ | ||
| 1780 | #define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) | ||
| 1781 | #define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) | ||
| 1782 | #define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) | ||
| 1783 | |||
| 1784 | /* Bit definitions and macros for MCF_LCDC_LVCR */ | ||
| 1785 | #define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) | ||
| 1786 | #define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) | ||
| 1787 | #define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) | ||
| 1788 | |||
| 1789 | /* Bit definitions and macros for MCF_LCDC_LPOR */ | ||
| 1790 | #define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) | ||
| 1791 | |||
| 1792 | /* Bit definitions and macros for MCF_LCDC_LPCCR */ | ||
| 1793 | #define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) | ||
| 1794 | #define MCF_LCDC_LPCCR_CC_EN (0x00000100) | ||
| 1795 | #define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) | ||
| 1796 | #define MCF_LCDC_LPCCR_LDMSK (0x00008000) | ||
| 1797 | #define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) | ||
| 1798 | #define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000) | ||
| 1799 | #define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000) | ||
| 1800 | #define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) | ||
| 1801 | |||
| 1802 | /* Bit definitions and macros for MCF_LCDC_LDCR */ | ||
| 1803 | #define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) | ||
| 1804 | #define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) | ||
| 1805 | #define MCF_LCDC_LDCR_BURST (0x80000000) | ||
| 1806 | |||
| 1807 | /* Bit definitions and macros for MCF_LCDC_LRMCR */ | ||
| 1808 | #define MCF_LCDC_LRMCR_SEL_REF (0x00000001) | ||
| 1809 | |||
| 1810 | /* Bit definitions and macros for MCF_LCDC_LICR */ | ||
| 1811 | #define MCF_LCDC_LICR_INTCON (0x00000001) | ||
| 1812 | #define MCF_LCDC_LICR_INTSYN (0x00000004) | ||
| 1813 | #define MCF_LCDC_LICR_GW_INT_CON (0x00000010) | ||
| 1814 | |||
| 1815 | /* Bit definitions and macros for MCF_LCDC_LIER */ | ||
| 1816 | #define MCF_LCDC_LIER_BOF_EN (0x00000001) | ||
| 1817 | #define MCF_LCDC_LIER_EOF_EN (0x00000002) | ||
| 1818 | #define MCF_LCDC_LIER_ERR_RES_EN (0x00000004) | ||
| 1819 | #define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008) | ||
| 1820 | #define MCF_LCDC_LIER_GW_BOF_EN (0x00000010) | ||
| 1821 | #define MCF_LCDC_LIER_GW_EOF_EN (0x00000020) | ||
| 1822 | #define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040) | ||
| 1823 | #define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080) | ||
| 1824 | |||
| 1825 | /* Bit definitions and macros for MCF_LCDC_LISR */ | ||
| 1826 | #define MCF_LCDC_LISR_BOF (0x00000001) | ||
| 1827 | #define MCF_LCDC_LISR_EOF (0x00000002) | ||
| 1828 | #define MCF_LCDC_LISR_ERR_RES (0x00000004) | ||
| 1829 | #define MCF_LCDC_LISR_UDR_ERR (0x00000008) | ||
| 1830 | #define MCF_LCDC_LISR_GW_BOF (0x00000010) | ||
| 1831 | #define MCF_LCDC_LISR_GW_EOF (0x00000020) | ||
| 1832 | #define MCF_LCDC_LISR_GW_ERR_RES (0x00000040) | ||
| 1833 | #define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080) | ||
| 1834 | |||
| 1835 | /* Bit definitions and macros for MCF_LCDC_LGWSAR */ | ||
| 1836 | #define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) | ||
| 1837 | |||
| 1838 | /* Bit definitions and macros for MCF_LCDC_LGWSR */ | ||
| 1839 | #define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) | ||
| 1840 | #define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) | ||
| 1841 | |||
| 1842 | /* Bit definitions and macros for MCF_LCDC_LGWVPWR */ | ||
| 1843 | #define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) | ||
| 1844 | |||
| 1845 | /* Bit definitions and macros for MCF_LCDC_LGWPOR */ | ||
| 1846 | #define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) | ||
| 1847 | |||
| 1848 | /* Bit definitions and macros for MCF_LCDC_LGWPR */ | ||
| 1849 | #define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) | ||
| 1850 | #define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) | ||
| 1851 | |||
| 1852 | /* Bit definitions and macros for MCF_LCDC_LGWCR */ | ||
| 1853 | #define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) | ||
| 1854 | #define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) | ||
| 1855 | #define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) | ||
| 1856 | #define MCF_LCDC_LGWCR_GW_RVS (0x00200000) | ||
| 1857 | #define MCF_LCDC_LGWCR_GWE (0x00400000) | ||
| 1858 | #define MCF_LCDC_LGWCR_GWCKE (0x00800000) | ||
| 1859 | #define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) | ||
| 1860 | |||
| 1861 | /* Bit definitions and macros for MCF_LCDC_LGWDCR */ | ||
| 1862 | #define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) | ||
| 1863 | #define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) | ||
| 1864 | #define MCF_LCDC_LGWDCR_GWBT (0x80000000) | ||
| 1865 | |||
| 1866 | /* Bit definitions and macros for MCF_LCDC_LSCR */ | ||
| 1867 | #define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26) | ||
| 1868 | #define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16) | ||
| 1869 | #define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8) | ||
| 1870 | #define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4) | ||
| 1871 | #define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0) | ||
| 1872 | |||
| 1873 | /* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */ | ||
| 1874 | #define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) | ||
| 1875 | |||
| 1876 | /* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */ | ||
| 1877 | #define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) | ||
| 1878 | |||
| 1879 | /********************************************************************* | ||
| 1880 | * | ||
| 1881 | * Phase Locked Loop (PLL) | ||
| 1882 | * | ||
| 1883 | *********************************************************************/ | ||
| 1884 | |||
| 1885 | /* Register read/write macros */ | ||
| 1886 | #define MCF_PLL_PODR MCF_REG08(0xFC0C0000) | ||
| 1887 | #define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004) | ||
| 1888 | #define MCF_PLL_PMDR MCF_REG08(0xFC0C0008) | ||
| 1889 | #define MCF_PLL_PFDR MCF_REG08(0xFC0C000C) | ||
| 1890 | |||
| 1891 | /* Bit definitions and macros for MCF_PLL_PODR */ | ||
| 1892 | #define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) | ||
| 1893 | #define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) | ||
| 1894 | |||
| 1895 | /* Bit definitions and macros for MCF_PLL_PLLCR */ | ||
| 1896 | #define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) | ||
| 1897 | #define MCF_PLL_PLLCR_DITHEN (0x80) | ||
| 1898 | |||
| 1899 | /* Bit definitions and macros for MCF_PLL_PMDR */ | ||
| 1900 | #define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) | ||
| 1901 | |||
| 1902 | /* Bit definitions and macros for MCF_PLL_PFDR */ | ||
| 1903 | #define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) | ||
| 1904 | |||
| 1905 | /********************************************************************* | ||
| 1906 | * | ||
| 1907 | * System Control Module Registers (SCM) | ||
| 1908 | * | ||
| 1909 | *********************************************************************/ | ||
| 1910 | |||
| 1911 | /* Register read/write macros */ | ||
| 1912 | #define MCF_SCM_MPR MCF_REG32(0xFC000000) | ||
| 1913 | #define MCF_SCM_PACRA MCF_REG32(0xFC000020) | ||
| 1914 | #define MCF_SCM_PACRB MCF_REG32(0xFC000024) | ||
| 1915 | #define MCF_SCM_PACRC MCF_REG32(0xFC000028) | ||
| 1916 | #define MCF_SCM_PACRD MCF_REG32(0xFC00002C) | ||
| 1917 | #define MCF_SCM_PACRE MCF_REG32(0xFC000040) | ||
| 1918 | #define MCF_SCM_PACRF MCF_REG32(0xFC000044) | ||
| 1919 | |||
| 1920 | #define MCF_SCM_BCR MCF_REG32(0xFC040024) | ||
| 1921 | |||
| 1922 | /********************************************************************* | ||
| 1923 | * | ||
| 1924 | * SDRAM Controller (SDRAMC) | ||
| 1925 | * | ||
| 1926 | *********************************************************************/ | ||
| 1927 | |||
| 1928 | /* Register read/write macros */ | ||
| 1929 | #define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000) | ||
| 1930 | #define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004) | ||
| 1931 | #define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008) | ||
| 1932 | #define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C) | ||
| 1933 | #define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080) | ||
| 1934 | #define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100) | ||
| 1935 | #define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110) | ||
| 1936 | #define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114) | ||
| 1937 | #define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118) | ||
| 1938 | #define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C) | ||
| 1939 | #define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004)) | ||
| 1940 | |||
| 1941 | /* Bit definitions and macros for MCF_SDRAMC_SDMR */ | ||
| 1942 | #define MCF_SDRAMC_SDMR_CMD (0x00010000) | ||
| 1943 | #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) | ||
| 1944 | #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) | ||
| 1945 | #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) | ||
| 1946 | #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) | ||
| 1947 | |||
| 1948 | /* Bit definitions and macros for MCF_SDRAMC_SDCR */ | ||
| 1949 | #define MCF_SDRAMC_SDCR_IPALL (0x00000002) | ||
| 1950 | #define MCF_SDRAMC_SDCR_IREF (0x00000004) | ||
| 1951 | #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) | ||
| 1952 | #define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) | ||
| 1953 | #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) | ||
| 1954 | #define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) | ||
| 1955 | #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) | ||
| 1956 | #define MCF_SDRAMC_SDCR_REF (0x10000000) | ||
| 1957 | #define MCF_SDRAMC_SDCR_DDR (0x20000000) | ||
| 1958 | #define MCF_SDRAMC_SDCR_CKE (0x40000000) | ||
| 1959 | #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) | ||
| 1960 | #define MCF_SDRAMC_SDCR_PS_16 (0x00002000) | ||
| 1961 | #define MCF_SDRAMC_SDCR_PS_32 (0x00000000) | ||
| 1962 | |||
| 1963 | /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ | ||
| 1964 | #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) | ||
| 1965 | #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) | ||
| 1966 | #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) | ||
| 1967 | #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) | ||
| 1968 | #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) | ||
| 1969 | #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) | ||
| 1970 | #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) | ||
| 1971 | |||
| 1972 | /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ | ||
| 1973 | #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) | ||
| 1974 | #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) | ||
| 1975 | #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) | ||
| 1976 | #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) | ||
| 1977 | |||
| 1978 | /* Device Errata - LIMP mode work around */ | ||
| 1979 | #define MCF_SDRAMC_REFRESH (0x40000000) | ||
| 1980 | |||
| 1981 | /* Bit definitions and macros for MCF_SDRAMC_SDDS */ | ||
| 1982 | #define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) | ||
| 1983 | #define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) | ||
| 1984 | #define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) | ||
| 1985 | #define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) | ||
| 1986 | #define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) | ||
| 1987 | |||
| 1988 | /* Bit definitions and macros for MCF_SDRAMC_SDCS */ | ||
| 1989 | #define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) | ||
| 1990 | #define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) | ||
| 1991 | #define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) | ||
| 1992 | #define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) | ||
| 1993 | #define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) | ||
| 1994 | #define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) | ||
| 1995 | #define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) | ||
| 1996 | #define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) | ||
| 1997 | #define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) | ||
| 1998 | #define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) | ||
| 1999 | #define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) | ||
| 2000 | #define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) | ||
| 2001 | #define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) | ||
| 2002 | #define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) | ||
| 2003 | #define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) | ||
| 2004 | #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) | ||
| 2005 | #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) | ||
| 2006 | |||
| 2007 | /********************************************************************* | ||
| 2008 | * | ||
| 2009 | * FlexCAN module registers | ||
| 2010 | * | ||
| 2011 | *********************************************************************/ | ||
| 2012 | #define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800) | ||
| 2013 | #define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00) | ||
| 2014 | #define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04) | ||
| 2015 | #define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08) | ||
| 2016 | #define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10) | ||
| 2017 | #define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14) | ||
| 2018 | #define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18) | ||
| 2019 | #define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C) | ||
| 2020 | #define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20) | ||
| 2021 | #define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28) | ||
| 2022 | #define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30) | ||
| 2023 | |||
| 2024 | #define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0) | ||
| 2025 | #define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4) | ||
| 2026 | #define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1) | ||
| 2027 | |||
| 2028 | /* | ||
| 2029 | * FlexCAN Module Configuration Register | ||
| 2030 | */ | ||
| 2031 | #define CANMCR_MDIS (0x80000000) | ||
| 2032 | #define CANMCR_FRZ (0x40000000) | ||
| 2033 | #define CANMCR_HALT (0x10000000) | ||
| 2034 | #define CANMCR_SOFTRST (0x02000000) | ||
| 2035 | #define CANMCR_FRZACK (0x01000000) | ||
| 2036 | #define CANMCR_SUPV (0x00800000) | ||
| 2037 | #define CANMCR_MAXMB(x) ((x)&0x0F) | ||
| 2038 | |||
| 2039 | /* | ||
| 2040 | * FlexCAN Control Register | ||
| 2041 | */ | ||
| 2042 | #define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) | ||
| 2043 | #define CANCTRL_RJW(x) (((x)&0x03)<<22) | ||
| 2044 | #define CANCTRL_PSEG1(x) (((x)&0x07)<<19) | ||
| 2045 | #define CANCTRL_PSEG2(x) (((x)&0x07)<<16) | ||
| 2046 | #define CANCTRL_BOFFMSK (0x00008000) | ||
| 2047 | #define CANCTRL_ERRMSK (0x00004000) | ||
| 2048 | #define CANCTRL_CLKSRC (0x00002000) | ||
| 2049 | #define CANCTRL_LPB (0x00001000) | ||
| 2050 | #define CANCTRL_SAMP (0x00000080) | ||
| 2051 | #define CANCTRL_BOFFREC (0x00000040) | ||
| 2052 | #define CANCTRL_TSYNC (0x00000020) | ||
| 2053 | #define CANCTRL_LBUF (0x00000010) | ||
| 2054 | #define CANCTRL_LOM (0x00000008) | ||
| 2055 | #define CANCTRL_PROPSEG(x) ((x)&0x07) | ||
| 2056 | |||
| 2057 | /* | ||
| 2058 | * FlexCAN Error Counter Register | ||
| 2059 | */ | ||
| 2060 | #define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) | ||
| 2061 | #define ERRCNT_TXECTR(x) ((x)&0xFF) | ||
| 2062 | |||
| 2063 | /* | ||
| 2064 | * FlexCAN Error and Status Register | ||
| 2065 | */ | ||
| 2066 | #define ERRSTAT_BITERR(x) (((x)&0x03)<<14) | ||
| 2067 | #define ERRSTAT_ACKERR (0x00002000) | ||
| 2068 | #define ERRSTAT_CRCERR (0x00001000) | ||
| 2069 | #define ERRSTAT_FRMERR (0x00000800) | ||
| 2070 | #define ERRSTAT_STFERR (0x00000400) | ||
| 2071 | #define ERRSTAT_TXWRN (0x00000200) | ||
| 2072 | #define ERRSTAT_RXWRN (0x00000100) | ||
| 2073 | #define ERRSTAT_IDLE (0x00000080) | ||
| 2074 | #define ERRSTAT_TXRX (0x00000040) | ||
| 2075 | #define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) | ||
| 2076 | #define ERRSTAT_BOFFINT (0x00000004) | ||
| 2077 | #define ERRSTAT_ERRINT (0x00000002) | ||
| 2078 | |||
| 2079 | /* | ||
| 2080 | * Interrupt Mask Register | ||
| 2081 | */ | ||
| 2082 | #define IMASK_BUF15M (0x8000) | ||
| 2083 | #define IMASK_BUF14M (0x4000) | ||
| 2084 | #define IMASK_BUF13M (0x2000) | ||
| 2085 | #define IMASK_BUF12M (0x1000) | ||
| 2086 | #define IMASK_BUF11M (0x0800) | ||
| 2087 | #define IMASK_BUF10M (0x0400) | ||
| 2088 | #define IMASK_BUF9M (0x0200) | ||
| 2089 | #define IMASK_BUF8M (0x0100) | ||
| 2090 | #define IMASK_BUF7M (0x0080) | ||
| 2091 | #define IMASK_BUF6M (0x0040) | ||
| 2092 | #define IMASK_BUF5M (0x0020) | ||
| 2093 | #define IMASK_BUF4M (0x0010) | ||
| 2094 | #define IMASK_BUF3M (0x0008) | ||
| 2095 | #define IMASK_BUF2M (0x0004) | ||
| 2096 | #define IMASK_BUF1M (0x0002) | ||
| 2097 | #define IMASK_BUF0M (0x0001) | ||
| 2098 | #define IMASK_BUFnM(x) (0x1<<(x)) | ||
| 2099 | #define IMASK_BUFF_ENABLE_ALL (0x1111) | ||
| 2100 | #define IMASK_BUFF_DISABLE_ALL (0x0000) | ||
| 2101 | |||
| 2102 | /* | ||
| 2103 | * Interrupt Flag Register | ||
| 2104 | */ | ||
| 2105 | #define IFLAG_BUF15M (0x8000) | ||
| 2106 | #define IFLAG_BUF14M (0x4000) | ||
| 2107 | #define IFLAG_BUF13M (0x2000) | ||
| 2108 | #define IFLAG_BUF12M (0x1000) | ||
| 2109 | #define IFLAG_BUF11M (0x0800) | ||
| 2110 | #define IFLAG_BUF10M (0x0400) | ||
| 2111 | #define IFLAG_BUF9M (0x0200) | ||
| 2112 | #define IFLAG_BUF8M (0x0100) | ||
| 2113 | #define IFLAG_BUF7M (0x0080) | ||
| 2114 | #define IFLAG_BUF6M (0x0040) | ||
| 2115 | #define IFLAG_BUF5M (0x0020) | ||
| 2116 | #define IFLAG_BUF4M (0x0010) | ||
| 2117 | #define IFLAG_BUF3M (0x0008) | ||
| 2118 | #define IFLAG_BUF2M (0x0004) | ||
| 2119 | #define IFLAG_BUF1M (0x0002) | ||
| 2120 | #define IFLAG_BUF0M (0x0001) | ||
| 2121 | #define IFLAG_BUFF_SET_ALL (0xFFFF) | ||
| 2122 | #define IFLAG_BUFF_CLEAR_ALL (0x0000) | ||
| 2123 | #define IFLAG_BUFnM(x) (0x1<<(x)) | ||
| 2124 | |||
| 2125 | /* | ||
| 2126 | * Message Buffers | ||
| 2127 | */ | ||
| 2128 | #define MB_CNT_CODE(x) (((x)&0x0F)<<24) | ||
| 2129 | #define MB_CNT_SRR (0x00400000) | ||
| 2130 | #define MB_CNT_IDE (0x00200000) | ||
| 2131 | #define MB_CNT_RTR (0x00100000) | ||
| 2132 | #define MB_CNT_LENGTH(x) (((x)&0x0F)<<16) | ||
| 2133 | #define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) | ||
| 2134 | #define MB_ID_STD(x) (((x)&0x07FF)<<18) | ||
| 2135 | #define MB_ID_EXT(x) ((x)&0x3FFFF) | ||
| 2136 | |||
| 2137 | /********************************************************************* | ||
| 2138 | * | ||
| 2139 | * Edge Port Module (EPORT) | ||
| 2140 | * | ||
| 2141 | *********************************************************************/ | ||
| 2142 | |||
| 2143 | /* Register read/write macros */ | ||
| 2144 | #define MCF_EPORT_EPPAR MCF_REG16(0xFC094000) | ||
| 2145 | #define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) | ||
| 2146 | #define MCF_EPORT_EPIER MCF_REG08(0xFC094003) | ||
| 2147 | #define MCF_EPORT_EPDR MCF_REG08(0xFC094004) | ||
| 2148 | #define MCF_EPORT_EPPDR MCF_REG08(0xFC094005) | ||
| 2149 | #define MCF_EPORT_EPFR MCF_REG08(0xFC094006) | ||
| 2150 | |||
| 2151 | /* Bit definitions and macros for MCF_EPORT_EPPAR */ | ||
| 2152 | #define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) | ||
| 2153 | #define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) | ||
| 2154 | #define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) | ||
| 2155 | #define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) | ||
| 2156 | #define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) | ||
| 2157 | #define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) | ||
| 2158 | #define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) | ||
| 2159 | #define MCF_EPORT_EPPAR_LEVEL (0) | ||
| 2160 | #define MCF_EPORT_EPPAR_RISING (1) | ||
| 2161 | #define MCF_EPORT_EPPAR_FALLING (2) | ||
| 2162 | #define MCF_EPORT_EPPAR_BOTH (3) | ||
| 2163 | #define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) | ||
| 2164 | #define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) | ||
| 2165 | #define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) | ||
| 2166 | #define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) | ||
| 2167 | #define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) | ||
| 2168 | #define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) | ||
| 2169 | #define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) | ||
| 2170 | #define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) | ||
| 2171 | #define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) | ||
| 2172 | #define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) | ||
| 2173 | #define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) | ||
| 2174 | #define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) | ||
| 2175 | #define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) | ||
| 2176 | #define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) | ||
| 2177 | #define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) | ||
| 2178 | #define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) | ||
| 2179 | #define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) | ||
| 2180 | #define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) | ||
| 2181 | #define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) | ||
| 2182 | #define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) | ||
| 2183 | #define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) | ||
| 2184 | #define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) | ||
| 2185 | #define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) | ||
| 2186 | #define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) | ||
| 2187 | #define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) | ||
| 2188 | #define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) | ||
| 2189 | #define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) | ||
| 2190 | #define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) | ||
| 2191 | |||
| 2192 | /* Bit definitions and macros for MCF_EPORT_EPDDR */ | ||
| 2193 | #define MCF_EPORT_EPDDR_EPDD1 (0x02) | ||
| 2194 | #define MCF_EPORT_EPDDR_EPDD2 (0x04) | ||
| 2195 | #define MCF_EPORT_EPDDR_EPDD3 (0x08) | ||
| 2196 | #define MCF_EPORT_EPDDR_EPDD4 (0x10) | ||
| 2197 | #define MCF_EPORT_EPDDR_EPDD5 (0x20) | ||
| 2198 | #define MCF_EPORT_EPDDR_EPDD6 (0x40) | ||
| 2199 | #define MCF_EPORT_EPDDR_EPDD7 (0x80) | ||
| 2200 | |||
| 2201 | /* Bit definitions and macros for MCF_EPORT_EPIER */ | ||
| 2202 | #define MCF_EPORT_EPIER_EPIE1 (0x02) | ||
| 2203 | #define MCF_EPORT_EPIER_EPIE2 (0x04) | ||
| 2204 | #define MCF_EPORT_EPIER_EPIE3 (0x08) | ||
| 2205 | #define MCF_EPORT_EPIER_EPIE4 (0x10) | ||
| 2206 | #define MCF_EPORT_EPIER_EPIE5 (0x20) | ||
| 2207 | #define MCF_EPORT_EPIER_EPIE6 (0x40) | ||
| 2208 | #define MCF_EPORT_EPIER_EPIE7 (0x80) | ||
| 2209 | |||
| 2210 | /* Bit definitions and macros for MCF_EPORT_EPDR */ | ||
| 2211 | #define MCF_EPORT_EPDR_EPD1 (0x02) | ||
| 2212 | #define MCF_EPORT_EPDR_EPD2 (0x04) | ||
| 2213 | #define MCF_EPORT_EPDR_EPD3 (0x08) | ||
| 2214 | #define MCF_EPORT_EPDR_EPD4 (0x10) | ||
| 2215 | #define MCF_EPORT_EPDR_EPD5 (0x20) | ||
| 2216 | #define MCF_EPORT_EPDR_EPD6 (0x40) | ||
| 2217 | #define MCF_EPORT_EPDR_EPD7 (0x80) | ||
| 2218 | |||
| 2219 | /* Bit definitions and macros for MCF_EPORT_EPPDR */ | ||
| 2220 | #define MCF_EPORT_EPPDR_EPPD1 (0x02) | ||
| 2221 | #define MCF_EPORT_EPPDR_EPPD2 (0x04) | ||
| 2222 | #define MCF_EPORT_EPPDR_EPPD3 (0x08) | ||
| 2223 | #define MCF_EPORT_EPPDR_EPPD4 (0x10) | ||
| 2224 | #define MCF_EPORT_EPPDR_EPPD5 (0x20) | ||
| 2225 | #define MCF_EPORT_EPPDR_EPPD6 (0x40) | ||
| 2226 | #define MCF_EPORT_EPPDR_EPPD7 (0x80) | ||
| 2227 | |||
| 2228 | /* Bit definitions and macros for MCF_EPORT_EPFR */ | ||
| 2229 | #define MCF_EPORT_EPFR_EPF1 (0x02) | ||
| 2230 | #define MCF_EPORT_EPFR_EPF2 (0x04) | ||
| 2231 | #define MCF_EPORT_EPFR_EPF3 (0x08) | ||
| 2232 | #define MCF_EPORT_EPFR_EPF4 (0x10) | ||
| 2233 | #define MCF_EPORT_EPFR_EPF5 (0x20) | ||
| 2234 | #define MCF_EPORT_EPFR_EPF6 (0x40) | ||
| 2235 | #define MCF_EPORT_EPFR_EPF7 (0x80) | ||
| 2236 | |||
| 2237 | /********************************************************************/ | ||
| 2238 | #endif /* m532xsim_h */ | ||
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h new file mode 100644 index 000000000000..cc22c4a53005 --- /dev/null +++ b/arch/m68k/include/asm/m5407sim.h | |||
| @@ -0,0 +1,157 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * m5407sim.h -- ColdFire 5407 System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2000, Lineo (www.lineo.com) | ||
| 7 | * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. | ||
| 8 | * | ||
| 9 | * Modified by David W. Miller for the MCF5307 Eval Board. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /****************************************************************************/ | ||
| 13 | #ifndef m5407sim_h | ||
| 14 | #define m5407sim_h | ||
| 15 | /****************************************************************************/ | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Define the 5407 SIM register set addresses. | ||
| 19 | */ | ||
| 20 | #define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ | ||
| 21 | #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ | ||
| 22 | #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ | ||
| 23 | #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ | ||
| 24 | #define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ | ||
| 25 | #define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ | ||
| 26 | #define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ | ||
| 27 | #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ | ||
| 28 | #define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ | ||
| 29 | #define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ | ||
| 30 | #define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ | ||
| 31 | #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ | ||
| 32 | #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ | ||
| 33 | #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ | ||
| 34 | #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ | ||
| 35 | #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ | ||
| 36 | #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ | ||
| 37 | #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ | ||
| 38 | #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ | ||
| 39 | #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ | ||
| 40 | #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ | ||
| 41 | #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ | ||
| 42 | #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ | ||
| 43 | |||
| 44 | #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ | ||
| 45 | #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ | ||
| 46 | #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ | ||
| 47 | #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ | ||
| 48 | #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ | ||
| 49 | #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ | ||
| 50 | |||
| 51 | #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ | ||
| 52 | #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ | ||
| 53 | #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ | ||
| 54 | #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ | ||
| 55 | #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ | ||
| 56 | #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ | ||
| 57 | #define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ | ||
| 58 | #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ | ||
| 59 | #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ | ||
| 60 | #define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ | ||
| 61 | #define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ | ||
| 62 | #define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ | ||
| 63 | #define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ | ||
| 64 | #define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ | ||
| 65 | #define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ | ||
| 66 | #define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ | ||
| 67 | #define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ | ||
| 68 | #define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ | ||
| 69 | |||
| 70 | #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ | ||
| 71 | #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ | ||
| 72 | #define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ | ||
| 73 | #define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ | ||
| 74 | #define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ | ||
| 75 | |||
| 76 | #define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ | ||
| 77 | #define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ | ||
| 78 | |||
| 79 | |||
| 80 | /* | ||
| 81 | * Some symbol defines for the above... | ||
| 82 | */ | ||
| 83 | #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ | ||
| 84 | #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ | ||
| 85 | #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ | ||
| 86 | #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ | ||
| 87 | #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ | ||
| 88 | #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ | ||
| 89 | #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ | ||
| 90 | #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ | ||
| 91 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ | ||
| 92 | |||
| 93 | /* | ||
| 94 | * Macro to set IMR register. It is 32 bits on the 5407. | ||
| 95 | */ | ||
| 96 | #define mcf_getimr() \ | ||
| 97 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) | ||
| 98 | |||
| 99 | #define mcf_setimr(imr) \ | ||
| 100 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); | ||
| 101 | |||
| 102 | #define mcf_getipr() \ | ||
| 103 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) | ||
| 104 | |||
| 105 | |||
| 106 | /* | ||
| 107 | * Some symbol defines for the Parallel Port Pin Assignment Register | ||
| 108 | */ | ||
| 109 | #define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ | ||
| 110 | /* Clear to select par I/O */ | ||
| 111 | #define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ | ||
| 112 | /* Clear to select par I/O */ | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Defines for the IRQPAR Register | ||
| 116 | */ | ||
| 117 | #define IRQ5_LEVEL4 0x80 | ||
| 118 | #define IRQ3_LEVEL6 0x40 | ||
| 119 | #define IRQ1_LEVEL2 0x20 | ||
| 120 | |||
| 121 | |||
| 122 | /* | ||
| 123 | * Define the Cache register flags. | ||
| 124 | */ | ||
| 125 | #define CACR_DEC 0x80000000 /* Enable data cache */ | ||
| 126 | #define CACR_DWP 0x40000000 /* Data write protection */ | ||
| 127 | #define CACR_DESB 0x20000000 /* Enable data store buffer */ | ||
| 128 | #define CACR_DDPI 0x10000000 /* Disable CPUSHL */ | ||
| 129 | #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ | ||
| 130 | #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ | ||
| 131 | #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ | ||
| 132 | #define CACR_DDCM_P 0x04000000 /* No cache, precise */ | ||
| 133 | #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ | ||
| 134 | #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ | ||
| 135 | #define CACR_BEC 0x00080000 /* Enable branch cache */ | ||
| 136 | #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ | ||
| 137 | #define CACR_IEC 0x00008000 /* Enable instruction cache */ | ||
| 138 | #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ | ||
| 139 | #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ | ||
| 140 | #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ | ||
| 141 | #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ | ||
| 142 | #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ | ||
| 143 | |||
| 144 | #define ACR_BASE_POS 24 /* Address Base */ | ||
| 145 | #define ACR_MASK_POS 16 /* Address Mask */ | ||
| 146 | #define ACR_ENABLE 0x00008000 /* Enable address */ | ||
| 147 | #define ACR_USER 0x00000000 /* User mode access only */ | ||
| 148 | #define ACR_SUPER 0x00002000 /* Supervisor mode only */ | ||
| 149 | #define ACR_ANY 0x00004000 /* Match any access mode */ | ||
| 150 | #define ACR_CM_WT 0x00000000 /* Write through mode */ | ||
| 151 | #define ACR_CM_CP 0x00000020 /* Copyback mode */ | ||
| 152 | #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ | ||
| 153 | #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ | ||
| 154 | #define ACR_WPROTECT 0x00000004 /* Write protect */ | ||
| 155 | |||
| 156 | /****************************************************************************/ | ||
| 157 | #endif /* m5407sim_h */ | ||
diff --git a/arch/m68k/include/asm/m68360.h b/arch/m68k/include/asm/m68360.h new file mode 100644 index 000000000000..eb7d39ef2855 --- /dev/null +++ b/arch/m68k/include/asm/m68360.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #include "m68360_regs.h" | ||
| 2 | #include "m68360_pram.h" | ||
| 3 | #include "m68360_quicc.h" | ||
| 4 | #include "m68360_enet.h" | ||
| 5 | |||
| 6 | #ifdef CONFIG_M68360 | ||
| 7 | |||
| 8 | #define CPM_INTERRUPT 4 | ||
| 9 | |||
| 10 | /* see MC68360 User's Manual, p. 7-377 */ | ||
| 11 | #define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */ | ||
| 12 | |||
| 13 | #endif /* CONFIG_M68360 */ | ||
diff --git a/arch/m68k/include/asm/m68360_enet.h b/arch/m68k/include/asm/m68360_enet.h new file mode 100644 index 000000000000..c36f4d059203 --- /dev/null +++ b/arch/m68k/include/asm/m68360_enet.h | |||
| @@ -0,0 +1,177 @@ | |||
| 1 | /*********************************** | ||
| 2 | * $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ | ||
| 3 | *********************************** | ||
| 4 | * | ||
| 5 | *************************************** | ||
| 6 | * Definitions for the ETHERNET controllers | ||
| 7 | *************************************** | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ETHER_H | ||
| 11 | #define __ETHER_H | ||
| 12 | |||
| 13 | #include "quicc_simple.h" | ||
| 14 | |||
| 15 | /* | ||
| 16 | * transmit BD's | ||
| 17 | */ | ||
| 18 | #define T_R 0x8000 /* ready bit */ | ||
| 19 | #define E_T_PAD 0x4000 /* short frame padding */ | ||
| 20 | #define T_W 0x2000 /* wrap bit */ | ||
| 21 | #define T_I 0x1000 /* interrupt on completion */ | ||
| 22 | #define T_L 0x0800 /* last in frame */ | ||
| 23 | #define T_TC 0x0400 /* transmit CRC (when last) */ | ||
| 24 | |||
| 25 | #define T_DEF 0x0200 /* defer indication */ | ||
| 26 | #define T_HB 0x0100 /* heartbeat */ | ||
| 27 | #define T_LC 0x0080 /* error: late collision */ | ||
| 28 | #define T_RL 0x0040 /* error: retransmission limit */ | ||
| 29 | #define T_RC 0x003c /* retry count */ | ||
| 30 | #define T_UN 0x0002 /* error: underrun */ | ||
| 31 | #define T_CSL 0x0001 /* carier sense lost */ | ||
| 32 | #define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL) | ||
| 33 | |||
| 34 | /* | ||
| 35 | * receive BD's | ||
| 36 | */ | ||
| 37 | #define R_E 0x8000 /* buffer empty */ | ||
| 38 | #define R_W 0x2000 /* wrap bit */ | ||
| 39 | #define R_I 0x1000 /* interrupt on reception */ | ||
| 40 | #define R_L 0x0800 /* last BD in frame */ | ||
| 41 | #define R_F 0x0400 /* first BD in frame */ | ||
| 42 | #define R_M 0x0100 /* received because of promisc. mode */ | ||
| 43 | |||
| 44 | #define R_LG 0x0020 /* frame too long */ | ||
| 45 | #define R_NO 0x0010 /* non-octet aligned */ | ||
| 46 | #define R_SH 0x0008 /* short frame */ | ||
| 47 | #define R_CR 0x0004 /* receive CRC error */ | ||
| 48 | #define R_OV 0x0002 /* receive overrun */ | ||
| 49 | #define R_CL 0x0001 /* collision */ | ||
| 50 | #define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL) | ||
| 51 | |||
| 52 | |||
| 53 | /* | ||
| 54 | * ethernet interrupts | ||
| 55 | */ | ||
| 56 | #define ETHERNET_GRA 0x0080 /* graceful stop complete */ | ||
| 57 | #define ETHERNET_TXE 0x0010 /* transmit error */ | ||
| 58 | #define ETHERNET_RXF 0x0008 /* receive frame */ | ||
| 59 | #define ETHERNET_BSY 0x0004 /* busy condition */ | ||
| 60 | #define ETHERNET_TXB 0x0002 /* transmit buffer */ | ||
| 61 | #define ETHERNET_RXB 0x0001 /* receive buffer */ | ||
| 62 | |||
| 63 | /* | ||
| 64 | * ethernet protocol specific mode register (PSMR) | ||
| 65 | */ | ||
| 66 | #define ETHER_HBC 0x8000 /* heartbeat checking */ | ||
| 67 | #define ETHER_FC 0x4000 /* force collision */ | ||
| 68 | #define ETHER_RSH 0x2000 /* receive short frames */ | ||
| 69 | #define ETHER_IAM 0x1000 /* individual address mode */ | ||
| 70 | #define ETHER_CRC_32 (0x2<<10) /* Enable CRC */ | ||
| 71 | #define ETHER_PRO 0x0200 /* promiscuous */ | ||
| 72 | #define ETHER_BRO 0x0100 /* broadcast address */ | ||
| 73 | #define ETHER_SBT 0x0080 /* stop backoff timer */ | ||
| 74 | #define ETHER_LPB 0x0040 /* Loop Back Mode */ | ||
| 75 | #define ETHER_SIP 0x0020 /* sample input pins */ | ||
| 76 | #define ETHER_LCW 0x0010 /* late collision window */ | ||
| 77 | #define ETHER_NIB_13 (0x0<<1) /* # of ignored bits 13 */ | ||
| 78 | #define ETHER_NIB_14 (0x1<<1) /* # of ignored bits 14 */ | ||
| 79 | #define ETHER_NIB_15 (0x2<<1) /* # of ignored bits 15 */ | ||
| 80 | #define ETHER_NIB_16 (0x3<<1) /* # of ignored bits 16 */ | ||
| 81 | #define ETHER_NIB_21 (0x4<<1) /* # of ignored bits 21 */ | ||
| 82 | #define ETHER_NIB_22 (0x5<<1) /* # of ignored bits 22 */ | ||
| 83 | #define ETHER_NIB_23 (0x6<<1) /* # of ignored bits 23 */ | ||
| 84 | #define ETHER_NIB_24 (0x7<<1) /* # of ignored bits 24 */ | ||
| 85 | |||
| 86 | /* | ||
| 87 | * ethernet specific parameters | ||
| 88 | */ | ||
| 89 | #define CRC_WORD 4 /* Length in bytes of CRC */ | ||
| 90 | #define C_PRES 0xffffffff /* preform 32 bit CRC */ | ||
| 91 | #define C_MASK 0xdebb20e3 /* comply with 32 bit CRC */ | ||
| 92 | #define CRCEC 0x00000000 | ||
| 93 | #define ALEC 0x00000000 | ||
| 94 | #define DISFC 0x00000000 | ||
| 95 | #define PADS 0x00000000 | ||
| 96 | #define RET_LIM 0x000f /* retry 15 times to send a frame before interrupt */ | ||
| 97 | #define ETH_MFLR 0x05ee /* 1518 max frame size */ | ||
| 98 | #define MINFLR 0x0040 /* Minimum frame size 64 */ | ||
| 99 | #define MAXD1 0x05ee /* Max dma count 1518 */ | ||
| 100 | #define MAXD2 0x05ee | ||
| 101 | #define GADDR1 0x00000000 /* Clear group address */ | ||
| 102 | #define GADDR2 0x00000000 | ||
| 103 | #define GADDR3 0x00000000 | ||
| 104 | #define GADDR4 0x00000000 | ||
| 105 | #define P_PER 0x00000000 /*not used */ | ||
| 106 | #define IADDR1 0x00000000 /* Individual hash table not used */ | ||
| 107 | #define IADDR2 0x00000000 | ||
| 108 | #define IADDR3 0x00000000 | ||
| 109 | #define IADDR4 0x00000000 | ||
| 110 | #define TADDR_H 0x00000000 /* clear this regs */ | ||
| 111 | #define TADDR_M 0x00000000 | ||
| 112 | #define TADDR_L 0x00000000 | ||
| 113 | |||
| 114 | /* SCC Parameter Ram */ | ||
| 115 | #define RFCR 0x18 /* normal operation */ | ||
| 116 | #define TFCR 0x18 /* normal operation */ | ||
| 117 | #define E_MRBLR 1518 /* Max ethernet frame length */ | ||
| 118 | |||
| 119 | /* | ||
| 120 | * ethernet specific structure | ||
| 121 | */ | ||
| 122 | typedef union { | ||
| 123 | unsigned char b[6]; | ||
| 124 | struct { | ||
| 125 | unsigned short high; | ||
| 126 | unsigned short middl; | ||
| 127 | unsigned short low; | ||
| 128 | } w; | ||
| 129 | } ETHER_ADDR; | ||
| 130 | |||
| 131 | typedef struct { | ||
| 132 | int max_frame_length; | ||
| 133 | int promisc_mode; | ||
| 134 | int reject_broadcast; | ||
| 135 | ETHER_ADDR phys_adr; | ||
| 136 | } ETHER_SPECIFIC; | ||
| 137 | |||
| 138 | typedef struct { | ||
| 139 | ETHER_ADDR dst_addr; | ||
| 140 | ETHER_ADDR src_addr; | ||
| 141 | unsigned short type_or_len; | ||
| 142 | unsigned char data[1]; | ||
| 143 | } ETHER_FRAME; | ||
| 144 | |||
| 145 | #define MAX_DATALEN 1500 | ||
| 146 | typedef struct { | ||
| 147 | ETHER_ADDR dst_addr; | ||
| 148 | ETHER_ADDR src_addr; | ||
| 149 | unsigned short type_or_len; | ||
| 150 | unsigned char data[MAX_DATALEN]; | ||
| 151 | unsigned char fcs[CRC_WORD]; | ||
| 152 | } ETHER_MAX_FRAME; | ||
| 153 | |||
| 154 | |||
| 155 | /* | ||
| 156 | * Internal ethernet function prototypes | ||
| 157 | */ | ||
| 158 | void ether_interrupt(int scc_num); | ||
| 159 | /* mleslie: debug */ | ||
| 160 | /* static void ethernet_rx_internal(int scc_num); */ | ||
| 161 | /* static void ethernet_tx_internal(int scc_num); */ | ||
| 162 | |||
| 163 | /* | ||
| 164 | * User callable routines prototypes (ethernet specific) | ||
| 165 | */ | ||
| 166 | void ethernet_init(int scc_number, | ||
| 167 | alloc_routine *alloc_buffer, | ||
| 168 | free_routine *free_buffer, | ||
| 169 | store_rx_buffer_routine *store_rx_buffer, | ||
| 170 | handle_tx_error_routine *handle_tx_error, | ||
| 171 | handle_rx_error_routine *handle_rx_error, | ||
| 172 | handle_lost_error_routine *handle_lost_error, | ||
| 173 | ETHER_SPECIFIC *ether_spec); | ||
| 174 | int ethernet_tx(int scc_number, void *buf, int length); | ||
| 175 | |||
| 176 | #endif | ||
| 177 | |||
diff --git a/arch/m68k/include/asm/m68360_pram.h b/arch/m68k/include/asm/m68360_pram.h new file mode 100644 index 000000000000..e6088bbce93d --- /dev/null +++ b/arch/m68k/include/asm/m68360_pram.h | |||
| @@ -0,0 +1,431 @@ | |||
| 1 | /*********************************** | ||
| 2 | * $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ | ||
| 3 | *********************************** | ||
| 4 | * | ||
| 5 | *************************************** | ||
| 6 | * Definitions of the parameter area RAM. | ||
| 7 | * Note that different structures are overlaid | ||
| 8 | * at the same offsets for the different modes | ||
| 9 | * of operation. | ||
| 10 | *************************************** | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __PRAM_H | ||
| 14 | #define __PRAM_H | ||
| 15 | |||
| 16 | /* Time slot assignment table */ | ||
| 17 | #define VALID_SLOT 0x8000 | ||
| 18 | #define WRAP_SLOT 0x4000 | ||
| 19 | |||
| 20 | /***************************************************************** | ||
| 21 | Global Multichannel parameter RAM | ||
| 22 | *****************************************************************/ | ||
| 23 | struct global_multi_pram { | ||
| 24 | /* | ||
| 25 | * Global Multichannel parameter RAM | ||
| 26 | */ | ||
| 27 | unsigned long mcbase; /* Multichannel Base pointer */ | ||
| 28 | unsigned short qmcstate; /* Multichannel Controller state */ | ||
| 29 | unsigned short mrblr; /* Maximum Receive Buffer Length */ | ||
| 30 | unsigned short tx_s_ptr; /* TSTATx Pointer */ | ||
| 31 | unsigned short rxptr; /* Current Time slot entry in TSATRx */ | ||
| 32 | unsigned short grfthr; /* Global Receive frame threshold */ | ||
| 33 | unsigned short grfcnt; /* Global Receive Frame Count */ | ||
| 34 | unsigned long intbase; /* Multichannel Base address */ | ||
| 35 | unsigned long iintptr; /* Pointer to interrupt queue */ | ||
| 36 | unsigned short rx_s_ptr; /* TSTARx Pointer */ | ||
| 37 | |||
| 38 | unsigned short txptr; /* Current Time slot entry in TSATTx */ | ||
| 39 | unsigned long c_mask32; /* CRC Constant (debb20e3) */ | ||
| 40 | unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */ | ||
| 41 | unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */ | ||
| 42 | unsigned short c_mask16; /* CRC Constant (f0b8) */ | ||
| 43 | }; | ||
| 44 | |||
| 45 | /***************************************************************** | ||
| 46 | Quicc32 HDLC parameter RAM | ||
| 47 | *****************************************************************/ | ||
| 48 | struct quicc32_pram { | ||
| 49 | |||
| 50 | unsigned short tbase; /* Tx Buffer Descriptors Base Address */ | ||
| 51 | unsigned short chamr; /* Channel Mode Register */ | ||
| 52 | unsigned long tstate; /* Tx Internal State */ | ||
| 53 | unsigned long txintr; /* Tx Internal Data Pointer */ | ||
| 54 | unsigned short tbptr; /* Tx Buffer Descriptor Pointer */ | ||
| 55 | unsigned short txcntr; /* Tx Internal Byte Count */ | ||
| 56 | unsigned long tupack; /* (Tx Temp) */ | ||
| 57 | unsigned long zistate; /* Zero Insertion machine state */ | ||
| 58 | unsigned long tcrc; /* Temp Transmit CRC */ | ||
| 59 | unsigned short intmask; /* Channel's interrupt mask flags */ | ||
| 60 | unsigned short bdflags; | ||
| 61 | unsigned short rbase; /* Rx Buffer Descriptors Base Address */ | ||
| 62 | unsigned short mflr; /* Max Frame Length Register */ | ||
| 63 | unsigned long rstate; /* Rx Internal State */ | ||
| 64 | unsigned long rxintr; /* Rx Internal Data Pointer */ | ||
| 65 | unsigned short rbptr; /* Rx Buffer Descriptor Pointer */ | ||
| 66 | unsigned short rxbyc; /* Rx Internal Byte Count */ | ||
| 67 | unsigned long rpack; /* (Rx Temp) */ | ||
| 68 | unsigned long zdstate; /* Zero Deletion machine state */ | ||
| 69 | unsigned long rcrc; /* Temp Transmit CRC */ | ||
| 70 | unsigned short maxc; /* Max_length counter */ | ||
| 71 | unsigned short tmp_mb; /* Temp */ | ||
| 72 | }; | ||
| 73 | |||
| 74 | |||
| 75 | /***************************************************************** | ||
| 76 | HDLC parameter RAM | ||
| 77 | *****************************************************************/ | ||
| 78 | |||
| 79 | struct hdlc_pram { | ||
| 80 | /* | ||
| 81 | * SCC parameter RAM | ||
| 82 | */ | ||
| 83 | unsigned short rbase; /* RX BD base address */ | ||
| 84 | unsigned short tbase; /* TX BD base address */ | ||
| 85 | unsigned char rfcr; /* Rx function code */ | ||
| 86 | unsigned char tfcr; /* Tx function code */ | ||
| 87 | unsigned short mrblr; /* Rx buffer length */ | ||
| 88 | unsigned long rstate; /* Rx internal state */ | ||
| 89 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 90 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 91 | unsigned short rcount; /* Rx internal byte count */ | ||
| 92 | unsigned long rtemp; /* Rx temp */ | ||
| 93 | unsigned long tstate; /* Tx internal state */ | ||
| 94 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 95 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 96 | unsigned short tcount; /* Tx byte count */ | ||
| 97 | unsigned long ttemp; /* Tx temp */ | ||
| 98 | unsigned long rcrc; /* temp receive CRC */ | ||
| 99 | unsigned long tcrc; /* temp transmit CRC */ | ||
| 100 | |||
| 101 | /* | ||
| 102 | * HDLC specific parameter RAM | ||
| 103 | */ | ||
| 104 | unsigned char RESERVED1[4]; /* Reserved area */ | ||
| 105 | unsigned long c_mask; /* CRC constant */ | ||
| 106 | unsigned long c_pres; /* CRC preset */ | ||
| 107 | unsigned short disfc; /* discarded frame counter */ | ||
| 108 | unsigned short crcec; /* CRC error counter */ | ||
| 109 | unsigned short abtsc; /* abort sequence counter */ | ||
| 110 | unsigned short nmarc; /* nonmatching address rx cnt */ | ||
| 111 | unsigned short retrc; /* frame retransmission cnt */ | ||
| 112 | unsigned short mflr; /* maximum frame length reg */ | ||
| 113 | unsigned short max_cnt; /* maximum length counter */ | ||
| 114 | unsigned short rfthr; /* received frames threshold */ | ||
| 115 | unsigned short rfcnt; /* received frames count */ | ||
| 116 | unsigned short hmask; /* user defined frm addr mask */ | ||
| 117 | unsigned short haddr1; /* user defined frm address 1 */ | ||
| 118 | unsigned short haddr2; /* user defined frm address 2 */ | ||
| 119 | unsigned short haddr3; /* user defined frm address 3 */ | ||
| 120 | unsigned short haddr4; /* user defined frm address 4 */ | ||
| 121 | unsigned short tmp; /* temp */ | ||
| 122 | unsigned short tmp_mb; /* temp */ | ||
| 123 | }; | ||
| 124 | |||
| 125 | |||
| 126 | |||
| 127 | /***************************************************************** | ||
| 128 | UART parameter RAM | ||
| 129 | *****************************************************************/ | ||
| 130 | |||
| 131 | /* | ||
| 132 | * bits in uart control characters table | ||
| 133 | */ | ||
| 134 | #define CC_INVALID 0x8000 /* control character is valid */ | ||
| 135 | #define CC_REJ 0x4000 /* don't store char in buffer */ | ||
| 136 | #define CC_CHAR 0x00ff /* control character */ | ||
| 137 | |||
| 138 | /* UART */ | ||
| 139 | struct uart_pram { | ||
| 140 | /* | ||
| 141 | * SCC parameter RAM | ||
| 142 | */ | ||
| 143 | unsigned short rbase; /* RX BD base address */ | ||
| 144 | unsigned short tbase; /* TX BD base address */ | ||
| 145 | unsigned char rfcr; /* Rx function code */ | ||
| 146 | unsigned char tfcr; /* Tx function code */ | ||
| 147 | unsigned short mrblr; /* Rx buffer length */ | ||
| 148 | unsigned long rstate; /* Rx internal state */ | ||
| 149 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 150 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 151 | unsigned short rcount; /* Rx internal byte count */ | ||
| 152 | unsigned long rx_temp; /* Rx temp */ | ||
| 153 | unsigned long tstate; /* Tx internal state */ | ||
| 154 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 155 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 156 | unsigned short tcount; /* Tx byte count */ | ||
| 157 | unsigned long ttemp; /* Tx temp */ | ||
| 158 | unsigned long rcrc; /* temp receive CRC */ | ||
| 159 | unsigned long tcrc; /* temp transmit CRC */ | ||
| 160 | |||
| 161 | /* | ||
| 162 | * UART specific parameter RAM | ||
| 163 | */ | ||
| 164 | unsigned char RESERVED1[8]; /* Reserved area */ | ||
| 165 | unsigned short max_idl; /* maximum idle characters */ | ||
| 166 | unsigned short idlc; /* rx idle counter (internal) */ | ||
| 167 | unsigned short brkcr; /* break count register */ | ||
| 168 | |||
| 169 | unsigned short parec; /* Rx parity error counter */ | ||
| 170 | unsigned short frmer; /* Rx framing error counter */ | ||
| 171 | unsigned short nosec; /* Rx noise counter */ | ||
| 172 | unsigned short brkec; /* Rx break character counter */ | ||
| 173 | unsigned short brkln; /* Reaceive break length */ | ||
| 174 | |||
| 175 | unsigned short uaddr1; /* address character 1 */ | ||
| 176 | unsigned short uaddr2; /* address character 2 */ | ||
| 177 | unsigned short rtemp; /* temp storage */ | ||
| 178 | unsigned short toseq; /* Tx out of sequence char */ | ||
| 179 | unsigned short cc[8]; /* Rx control characters */ | ||
| 180 | unsigned short rccm; /* Rx control char mask */ | ||
| 181 | unsigned short rccr; /* Rx control char register */ | ||
| 182 | unsigned short rlbc; /* Receive last break char */ | ||
| 183 | }; | ||
| 184 | |||
| 185 | |||
| 186 | |||
| 187 | /***************************************************************** | ||
| 188 | BISYNC parameter RAM | ||
| 189 | *****************************************************************/ | ||
| 190 | |||
| 191 | struct bisync_pram { | ||
| 192 | /* | ||
| 193 | * SCC parameter RAM | ||
| 194 | */ | ||
| 195 | unsigned short rbase; /* RX BD base address */ | ||
| 196 | unsigned short tbase; /* TX BD base address */ | ||
| 197 | unsigned char rfcr; /* Rx function code */ | ||
| 198 | unsigned char tfcr; /* Tx function code */ | ||
| 199 | unsigned short mrblr; /* Rx buffer length */ | ||
| 200 | unsigned long rstate; /* Rx internal state */ | ||
| 201 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 202 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 203 | unsigned short rcount; /* Rx internal byte count */ | ||
| 204 | unsigned long rtemp; /* Rx temp */ | ||
| 205 | unsigned long tstate; /* Tx internal state */ | ||
| 206 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 207 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 208 | unsigned short tcount; /* Tx byte count */ | ||
| 209 | unsigned long ttemp; /* Tx temp */ | ||
| 210 | unsigned long rcrc; /* temp receive CRC */ | ||
| 211 | unsigned long tcrc; /* temp transmit CRC */ | ||
| 212 | |||
| 213 | /* | ||
| 214 | * BISYNC specific parameter RAM | ||
| 215 | */ | ||
| 216 | unsigned char RESERVED1[4]; /* Reserved area */ | ||
| 217 | unsigned long crcc; /* CRC Constant Temp Value */ | ||
| 218 | unsigned short prcrc; /* Preset Receiver CRC-16/LRC */ | ||
| 219 | unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */ | ||
| 220 | unsigned short parec; /* Receive Parity Error Counter */ | ||
| 221 | unsigned short bsync; /* BISYNC SYNC Character */ | ||
| 222 | unsigned short bdle; /* BISYNC DLE Character */ | ||
| 223 | unsigned short cc[8]; /* Rx control characters */ | ||
| 224 | unsigned short rccm; /* Receive Control Character Mask */ | ||
| 225 | }; | ||
| 226 | |||
| 227 | /***************************************************************** | ||
| 228 | IOM2 parameter RAM | ||
| 229 | (overlaid on tx bd[5] of SCC channel[2]) | ||
| 230 | *****************************************************************/ | ||
| 231 | struct iom2_pram { | ||
| 232 | unsigned short ci_data; /* ci data */ | ||
| 233 | unsigned short monitor_data; /* monitor data */ | ||
| 234 | unsigned short tstate; /* transmitter state */ | ||
| 235 | unsigned short rstate; /* receiver state */ | ||
| 236 | }; | ||
| 237 | |||
| 238 | /***************************************************************** | ||
| 239 | SPI/SMC parameter RAM | ||
| 240 | (overlaid on tx bd[6,7] of SCC channel[2]) | ||
| 241 | *****************************************************************/ | ||
| 242 | |||
| 243 | #define SPI_R 0x8000 /* Ready bit in BD */ | ||
| 244 | |||
| 245 | struct spi_pram { | ||
| 246 | unsigned short rbase; /* Rx BD Base Address */ | ||
| 247 | unsigned short tbase; /* Tx BD Base Address */ | ||
| 248 | unsigned char rfcr; /* Rx function code */ | ||
| 249 | unsigned char tfcr; /* Tx function code */ | ||
| 250 | unsigned short mrblr; /* Rx buffer length */ | ||
| 251 | unsigned long rstate; /* Rx internal state */ | ||
| 252 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 253 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 254 | unsigned short rcount; /* Rx internal byte count */ | ||
| 255 | unsigned long rtemp; /* Rx temp */ | ||
| 256 | unsigned long tstate; /* Tx internal state */ | ||
| 257 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 258 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 259 | unsigned short tcount; /* Tx byte count */ | ||
| 260 | unsigned long ttemp; /* Tx temp */ | ||
| 261 | }; | ||
| 262 | |||
| 263 | struct smc_uart_pram { | ||
| 264 | unsigned short rbase; /* Rx BD Base Address */ | ||
| 265 | unsigned short tbase; /* Tx BD Base Address */ | ||
| 266 | unsigned char rfcr; /* Rx function code */ | ||
| 267 | unsigned char tfcr; /* Tx function code */ | ||
| 268 | unsigned short mrblr; /* Rx buffer length */ | ||
| 269 | unsigned long rstate; /* Rx internal state */ | ||
| 270 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 271 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 272 | unsigned short rcount; /* Rx internal byte count */ | ||
| 273 | unsigned long rtemp; /* Rx temp */ | ||
| 274 | unsigned long tstate; /* Tx internal state */ | ||
| 275 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 276 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 277 | unsigned short tcount; /* Tx byte count */ | ||
| 278 | unsigned long ttemp; /* Tx temp */ | ||
| 279 | unsigned short max_idl; /* Maximum IDLE Characters */ | ||
| 280 | unsigned short idlc; /* Temporary IDLE Counter */ | ||
| 281 | unsigned short brkln; /* Last Rx Break Length */ | ||
| 282 | unsigned short brkec; /* Rx Break Condition Counter */ | ||
| 283 | unsigned short brkcr; /* Break Count Register (Tx) */ | ||
| 284 | unsigned short r_mask; /* Temporary bit mask */ | ||
| 285 | }; | ||
| 286 | |||
| 287 | struct smc_trnsp_pram { | ||
| 288 | unsigned short rbase; /* rx BD Base Address */ | ||
| 289 | unsigned short tbase; /* Tx BD Base Address */ | ||
| 290 | unsigned char rfcr; /* Rx function code */ | ||
| 291 | unsigned char tfcr; /* Tx function code */ | ||
| 292 | unsigned short mrblr; /* Rx buffer length */ | ||
| 293 | unsigned long rstate; /* Rx internal state */ | ||
| 294 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 295 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 296 | unsigned short rcount; /* Rx internal byte count */ | ||
| 297 | unsigned long rtemp; /* Rx temp */ | ||
| 298 | unsigned long tstate; /* Tx internal state */ | ||
| 299 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 300 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 301 | unsigned short tcount; /* Tx byte count */ | ||
| 302 | unsigned long ttemp; /* Tx temp */ | ||
| 303 | unsigned short reserved[5]; /* Reserved */ | ||
| 304 | }; | ||
| 305 | |||
| 306 | struct idma_pram { | ||
| 307 | unsigned short ibase; /* IDMA BD Base Address */ | ||
| 308 | unsigned short ibptr; /* IDMA buffer descriptor pointer */ | ||
| 309 | unsigned long istate; /* IDMA internal state */ | ||
| 310 | unsigned long itemp; /* IDMA temp */ | ||
| 311 | }; | ||
| 312 | |||
| 313 | struct ethernet_pram { | ||
| 314 | /* | ||
| 315 | * SCC parameter RAM | ||
| 316 | */ | ||
| 317 | unsigned short rbase; /* RX BD base address */ | ||
| 318 | unsigned short tbase; /* TX BD base address */ | ||
| 319 | unsigned char rfcr; /* Rx function code */ | ||
| 320 | unsigned char tfcr; /* Tx function code */ | ||
| 321 | unsigned short mrblr; /* Rx buffer length */ | ||
| 322 | unsigned long rstate; /* Rx internal state */ | ||
| 323 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 324 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 325 | unsigned short rcount; /* Rx internal byte count */ | ||
| 326 | unsigned long rtemp; /* Rx temp */ | ||
| 327 | unsigned long tstate; /* Tx internal state */ | ||
| 328 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 329 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 330 | unsigned short tcount; /* Tx byte count */ | ||
| 331 | unsigned long ttemp; /* Tx temp */ | ||
| 332 | unsigned long rcrc; /* temp receive CRC */ | ||
| 333 | unsigned long tcrc; /* temp transmit CRC */ | ||
| 334 | |||
| 335 | /* | ||
| 336 | * ETHERNET specific parameter RAM | ||
| 337 | */ | ||
| 338 | unsigned long c_pres; /* preset CRC */ | ||
| 339 | unsigned long c_mask; /* constant mask for CRC */ | ||
| 340 | unsigned long crcec; /* CRC error counter */ | ||
| 341 | unsigned long alec; /* alighnment error counter */ | ||
| 342 | unsigned long disfc; /* discard frame counter */ | ||
| 343 | unsigned short pads; /* short frame PAD characters */ | ||
| 344 | unsigned short ret_lim; /* retry limit threshold */ | ||
| 345 | unsigned short ret_cnt; /* retry limit counter */ | ||
| 346 | unsigned short mflr; /* maximum frame length reg */ | ||
| 347 | unsigned short minflr; /* minimum frame length reg */ | ||
| 348 | unsigned short maxd1; /* maximum DMA1 length reg */ | ||
| 349 | unsigned short maxd2; /* maximum DMA2 length reg */ | ||
| 350 | unsigned short maxd; /* rx max DMA */ | ||
| 351 | unsigned short dma_cnt; /* rx dma counter */ | ||
| 352 | unsigned short max_b; /* max bd byte count */ | ||
| 353 | unsigned short gaddr1; /* group address filter 1 */ | ||
| 354 | unsigned short gaddr2; /* group address filter 2 */ | ||
| 355 | unsigned short gaddr3; /* group address filter 3 */ | ||
| 356 | unsigned short gaddr4; /* group address filter 4 */ | ||
| 357 | unsigned long tbuf0_data0; /* save area 0 - current frm */ | ||
| 358 | unsigned long tbuf0_data1; /* save area 1 - current frm */ | ||
| 359 | unsigned long tbuf0_rba0; | ||
| 360 | unsigned long tbuf0_crc; | ||
| 361 | unsigned short tbuf0_bcnt; | ||
| 362 | union { | ||
| 363 | unsigned char b[6]; | ||
| 364 | struct { | ||
| 365 | unsigned short high; | ||
| 366 | unsigned short middl; | ||
| 367 | unsigned short low; | ||
| 368 | } w; | ||
| 369 | } paddr; | ||
| 370 | unsigned short p_per; /* persistence */ | ||
| 371 | unsigned short rfbd_ptr; /* rx first bd pointer */ | ||
| 372 | unsigned short tfbd_ptr; /* tx first bd pointer */ | ||
| 373 | unsigned short tlbd_ptr; /* tx last bd pointer */ | ||
| 374 | unsigned long tbuf1_data0; /* save area 0 - next frame */ | ||
| 375 | unsigned long tbuf1_data1; /* save area 1 - next frame */ | ||
| 376 | unsigned long tbuf1_rba0; | ||
| 377 | unsigned long tbuf1_crc; | ||
| 378 | unsigned short tbuf1_bcnt; | ||
| 379 | unsigned short tx_len; /* tx frame length counter */ | ||
| 380 | unsigned short iaddr1; /* individual address filter 1*/ | ||
| 381 | unsigned short iaddr2; /* individual address filter 2*/ | ||
| 382 | unsigned short iaddr3; /* individual address filter 3*/ | ||
| 383 | unsigned short iaddr4; /* individual address filter 4*/ | ||
| 384 | unsigned short boff_cnt; /* back-off counter */ | ||
| 385 | unsigned short taddr_h; /* temp address (MSB) */ | ||
| 386 | unsigned short taddr_m; /* temp address */ | ||
| 387 | unsigned short taddr_l; /* temp address (LSB) */ | ||
| 388 | }; | ||
| 389 | |||
| 390 | struct transparent_pram { | ||
| 391 | /* | ||
| 392 | * SCC parameter RAM | ||
| 393 | */ | ||
| 394 | unsigned short rbase; /* RX BD base address */ | ||
| 395 | unsigned short tbase; /* TX BD base address */ | ||
| 396 | unsigned char rfcr; /* Rx function code */ | ||
| 397 | unsigned char tfcr; /* Tx function code */ | ||
| 398 | unsigned short mrblr; /* Rx buffer length */ | ||
| 399 | unsigned long rstate; /* Rx internal state */ | ||
| 400 | unsigned long rptr; /* Rx internal data pointer */ | ||
| 401 | unsigned short rbptr; /* rb BD Pointer */ | ||
| 402 | unsigned short rcount; /* Rx internal byte count */ | ||
| 403 | unsigned long rtemp; /* Rx temp */ | ||
| 404 | unsigned long tstate; /* Tx internal state */ | ||
| 405 | unsigned long tptr; /* Tx internal data pointer */ | ||
| 406 | unsigned short tbptr; /* Tx BD pointer */ | ||
| 407 | unsigned short tcount; /* Tx byte count */ | ||
| 408 | unsigned long ttemp; /* Tx temp */ | ||
| 409 | unsigned long rcrc; /* temp receive CRC */ | ||
| 410 | unsigned long tcrc; /* temp transmit CRC */ | ||
| 411 | |||
| 412 | /* | ||
| 413 | * TRANSPARENT specific parameter RAM | ||
| 414 | */ | ||
| 415 | unsigned long crc_p; /* CRC Preset */ | ||
| 416 | unsigned long crc_c; /* CRC constant */ | ||
| 417 | }; | ||
| 418 | |||
| 419 | struct timer_pram { | ||
| 420 | /* | ||
| 421 | * RISC timers parameter RAM | ||
| 422 | */ | ||
| 423 | unsigned short tm_base; /* RISC timer table base adr */ | ||
| 424 | unsigned short tm_ptr; /* RISC timer table pointer */ | ||
| 425 | unsigned short r_tmr; /* RISC timer mode register */ | ||
| 426 | unsigned short r_tmv; /* RISC timer valid register */ | ||
| 427 | unsigned long tm_cmd; /* RISC timer cmd register */ | ||
| 428 | unsigned long tm_cnt; /* RISC timer internal cnt */ | ||
| 429 | }; | ||
| 430 | |||
| 431 | #endif | ||
diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h new file mode 100644 index 000000000000..6d40f4d18e10 --- /dev/null +++ b/arch/m68k/include/asm/m68360_quicc.h | |||
| @@ -0,0 +1,362 @@ | |||
| 1 | /*********************************** | ||
| 2 | * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ | ||
| 3 | *********************************** | ||
| 4 | * | ||
| 5 | *************************************** | ||
| 6 | * Definitions of QUICC memory structures | ||
| 7 | *************************************** | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __M68360_QUICC_H | ||
| 11 | #define __M68360_QUICC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * include registers and | ||
| 15 | * parameter ram definitions files | ||
| 16 | */ | ||
| 17 | #include <asm/m68360_regs.h> | ||
| 18 | #include <asm/m68360_pram.h> | ||
| 19 | |||
| 20 | |||
| 21 | |||
| 22 | /* Buffer Descriptors */ | ||
| 23 | typedef struct quicc_bd { | ||
| 24 | volatile unsigned short status; | ||
| 25 | volatile unsigned short length; | ||
| 26 | volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */ | ||
| 27 | } QUICC_BD; | ||
| 28 | |||
| 29 | |||
| 30 | #ifdef MOTOROLA_ORIGINAL | ||
| 31 | struct user_data { | ||
| 32 | /* BASE + 0x000: user data memory */ | ||
| 33 | volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ | ||
| 34 | volatile unsigned char udata_bd[0x200]; /*user data Ucode */ | ||
| 35 | volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */ | ||
| 36 | volatile unsigned char RESERVED1[0x500]; /* Reserved area */ | ||
| 37 | }; | ||
| 38 | #else | ||
| 39 | struct user_data { | ||
| 40 | /* BASE + 0x000: user data memory */ | ||
| 41 | volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/ | ||
| 42 | volatile unsigned char udata_bd1[0x200]; /* user, bds */ | ||
| 43 | volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */ | ||
| 44 | volatile unsigned char udata_bd2[0x100]; /* user, bds */ | ||
| 45 | volatile unsigned char RESERVED1[0x400]; /* Reserved area */ | ||
| 46 | }; | ||
| 47 | #endif | ||
| 48 | |||
| 49 | |||
| 50 | /* | ||
| 51 | * internal ram | ||
| 52 | */ | ||
| 53 | typedef struct quicc { | ||
| 54 | union { | ||
| 55 | struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */ | ||
| 56 | struct user_data u; | ||
| 57 | }ch_or_u; /* multipul or user space */ | ||
| 58 | |||
| 59 | /* BASE + 0xc00: PARAMETER RAM */ | ||
| 60 | union { | ||
| 61 | struct scc_pram { | ||
| 62 | union { | ||
| 63 | struct hdlc_pram h; | ||
| 64 | struct uart_pram u; | ||
| 65 | struct bisync_pram b; | ||
| 66 | struct transparent_pram t; | ||
| 67 | unsigned char RESERVED66[0x70]; | ||
| 68 | } pscc; /* scc parameter area (protocol dependent) */ | ||
| 69 | union { | ||
| 70 | struct { | ||
| 71 | unsigned char RESERVED70[0x10]; | ||
| 72 | struct spi_pram spi; | ||
| 73 | unsigned char RESERVED72[0x8]; | ||
| 74 | struct timer_pram timer; | ||
| 75 | } timer_spi; | ||
| 76 | struct { | ||
| 77 | struct idma_pram idma; | ||
| 78 | unsigned char RESERVED67[0x4]; | ||
| 79 | union { | ||
| 80 | struct smc_uart_pram u; | ||
| 81 | struct smc_trnsp_pram t; | ||
| 82 | } psmc; | ||
| 83 | } idma_smc; | ||
| 84 | } pothers; | ||
| 85 | } scc; | ||
| 86 | struct ethernet_pram enet_scc; | ||
| 87 | struct global_multi_pram m; | ||
| 88 | unsigned char pr[0x100]; | ||
| 89 | } pram[4]; | ||
| 90 | |||
| 91 | /* reserved */ | ||
| 92 | |||
| 93 | /* BASE + 0x1000: INTERNAL REGISTERS */ | ||
| 94 | /* SIM */ | ||
| 95 | volatile unsigned long sim_mcr; /* module configuration reg */ | ||
| 96 | volatile unsigned short sim_simtr; /* module test register */ | ||
| 97 | volatile unsigned char RESERVED2[0x2]; /* Reserved area */ | ||
| 98 | volatile unsigned char sim_avr; /* auto vector reg */ | ||
| 99 | volatile unsigned char sim_rsr; /* reset status reg */ | ||
| 100 | volatile unsigned char RESERVED3[0x2]; /* Reserved area */ | ||
| 101 | volatile unsigned char sim_clkocr; /* CLCO control register */ | ||
| 102 | volatile unsigned char RESERVED62[0x3]; /* Reserved area */ | ||
| 103 | volatile unsigned short sim_pllcr; /* PLL control register */ | ||
| 104 | volatile unsigned char RESERVED63[0x2]; /* Reserved area */ | ||
| 105 | volatile unsigned short sim_cdvcr; /* Clock devider control register */ | ||
| 106 | volatile unsigned short sim_pepar; /* Port E pin assignment register */ | ||
| 107 | volatile unsigned char RESERVED64[0xa]; /* Reserved area */ | ||
| 108 | volatile unsigned char sim_sypcr; /* system protection control*/ | ||
| 109 | volatile unsigned char sim_swiv; /* software interrupt vector*/ | ||
| 110 | volatile unsigned char RESERVED6[0x2]; /* Reserved area */ | ||
| 111 | volatile unsigned short sim_picr; /* periodic interrupt control reg */ | ||
| 112 | volatile unsigned char RESERVED7[0x2]; /* Reserved area */ | ||
| 113 | volatile unsigned short sim_pitr; /* periodic interrupt timing reg */ | ||
| 114 | volatile unsigned char RESERVED8[0x3]; /* Reserved area */ | ||
| 115 | volatile unsigned char sim_swsr; /* software service */ | ||
| 116 | volatile unsigned long sim_bkar; /* breakpoint address register*/ | ||
| 117 | volatile unsigned long sim_bkcr; /* breakpoint control register*/ | ||
| 118 | volatile unsigned char RESERVED10[0x8]; /* Reserved area */ | ||
| 119 | /* MEMC */ | ||
| 120 | volatile unsigned long memc_gmr; /* Global memory register */ | ||
| 121 | volatile unsigned short memc_mstat; /* MEMC status register */ | ||
| 122 | volatile unsigned char RESERVED11[0xa]; /* Reserved area */ | ||
| 123 | volatile unsigned long memc_br0; /* base register 0 */ | ||
| 124 | volatile unsigned long memc_or0; /* option register 0 */ | ||
| 125 | volatile unsigned char RESERVED12[0x8]; /* Reserved area */ | ||
| 126 | volatile unsigned long memc_br1; /* base register 1 */ | ||
| 127 | volatile unsigned long memc_or1; /* option register 1 */ | ||
| 128 | volatile unsigned char RESERVED13[0x8]; /* Reserved area */ | ||
| 129 | volatile unsigned long memc_br2; /* base register 2 */ | ||
| 130 | volatile unsigned long memc_or2; /* option register 2 */ | ||
| 131 | volatile unsigned char RESERVED14[0x8]; /* Reserved area */ | ||
| 132 | volatile unsigned long memc_br3; /* base register 3 */ | ||
| 133 | volatile unsigned long memc_or3; /* option register 3 */ | ||
| 134 | volatile unsigned char RESERVED15[0x8]; /* Reserved area */ | ||
| 135 | volatile unsigned long memc_br4; /* base register 3 */ | ||
| 136 | volatile unsigned long memc_or4; /* option register 3 */ | ||
| 137 | volatile unsigned char RESERVED16[0x8]; /* Reserved area */ | ||
| 138 | volatile unsigned long memc_br5; /* base register 3 */ | ||
| 139 | volatile unsigned long memc_or5; /* option register 3 */ | ||
| 140 | volatile unsigned char RESERVED17[0x8]; /* Reserved area */ | ||
| 141 | volatile unsigned long memc_br6; /* base register 3 */ | ||
| 142 | volatile unsigned long memc_or6; /* option register 3 */ | ||
| 143 | volatile unsigned char RESERVED18[0x8]; /* Reserved area */ | ||
| 144 | volatile unsigned long memc_br7; /* base register 3 */ | ||
| 145 | volatile unsigned long memc_or7; /* option register 3 */ | ||
| 146 | volatile unsigned char RESERVED9[0x28]; /* Reserved area */ | ||
| 147 | /* TEST */ | ||
| 148 | volatile unsigned short test_tstmra; /* master shift a */ | ||
| 149 | volatile unsigned short test_tstmrb; /* master shift b */ | ||
| 150 | volatile unsigned short test_tstsc; /* shift count */ | ||
| 151 | volatile unsigned short test_tstrc; /* repetition counter */ | ||
| 152 | volatile unsigned short test_creg; /* control */ | ||
| 153 | volatile unsigned short test_dreg; /* destributed register */ | ||
| 154 | volatile unsigned char RESERVED58[0x404]; /* Reserved area */ | ||
| 155 | /* IDMA1 */ | ||
| 156 | volatile unsigned short idma_iccr; /* channel configuration reg*/ | ||
| 157 | volatile unsigned char RESERVED19[0x2]; /* Reserved area */ | ||
| 158 | volatile unsigned short idma1_cmr; /* dma mode reg */ | ||
| 159 | volatile unsigned char RESERVED68[0x2]; /* Reserved area */ | ||
| 160 | volatile unsigned long idma1_sapr; /* dma source addr ptr */ | ||
| 161 | volatile unsigned long idma1_dapr; /* dma destination addr ptr */ | ||
| 162 | volatile unsigned long idma1_bcr; /* dma byte count reg */ | ||
| 163 | volatile unsigned char idma1_fcr; /* function code reg */ | ||
| 164 | volatile unsigned char RESERVED20; /* Reserved area */ | ||
| 165 | volatile unsigned char idma1_cmar; /* channel mask reg */ | ||
| 166 | volatile unsigned char RESERVED21; /* Reserved area */ | ||
| 167 | volatile unsigned char idma1_csr; /* channel status reg */ | ||
| 168 | volatile unsigned char RESERVED22[0x3]; /* Reserved area */ | ||
| 169 | /* SDMA */ | ||
| 170 | volatile unsigned char sdma_sdsr; /* status reg */ | ||
| 171 | volatile unsigned char RESERVED23; /* Reserved area */ | ||
| 172 | volatile unsigned short sdma_sdcr; /* configuration reg */ | ||
| 173 | volatile unsigned long sdma_sdar; /* address reg */ | ||
| 174 | /* IDMA2 */ | ||
| 175 | volatile unsigned char RESERVED69[0x2]; /* Reserved area */ | ||
| 176 | volatile unsigned short idma2_cmr; /* dma mode reg */ | ||
| 177 | volatile unsigned long idma2_sapr; /* dma source addr ptr */ | ||
| 178 | volatile unsigned long idma2_dapr; /* dma destination addr ptr */ | ||
| 179 | volatile unsigned long idma2_bcr; /* dma byte count reg */ | ||
| 180 | volatile unsigned char idma2_fcr; /* function code reg */ | ||
| 181 | volatile unsigned char RESERVED24; /* Reserved area */ | ||
| 182 | volatile unsigned char idma2_cmar; /* channel mask reg */ | ||
| 183 | volatile unsigned char RESERVED25; /* Reserved area */ | ||
| 184 | volatile unsigned char idma2_csr; /* channel status reg */ | ||
| 185 | volatile unsigned char RESERVED26[0x7]; /* Reserved area */ | ||
| 186 | /* Interrupt Controller */ | ||
| 187 | volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/ | ||
| 188 | volatile unsigned long intr_cipr; /* CP interrupt pending reg */ | ||
| 189 | volatile unsigned long intr_cimr; /* CP interrupt mask reg */ | ||
| 190 | volatile unsigned long intr_cisr; /* CP interrupt in service reg*/ | ||
| 191 | /* Parallel I/O */ | ||
| 192 | volatile unsigned short pio_padir; /* port A data direction reg */ | ||
| 193 | volatile unsigned short pio_papar; /* port A pin assignment reg */ | ||
| 194 | volatile unsigned short pio_paodr; /* port A open drain reg */ | ||
| 195 | volatile unsigned short pio_padat; /* port A data register */ | ||
| 196 | volatile unsigned char RESERVED28[0x8]; /* Reserved area */ | ||
| 197 | volatile unsigned short pio_pcdir; /* port C data direction reg*/ | ||
| 198 | volatile unsigned short pio_pcpar; /* port C pin assignment reg*/ | ||
| 199 | volatile unsigned short pio_pcso; /* port C special options */ | ||
| 200 | volatile unsigned short pio_pcdat; /* port C data register */ | ||
| 201 | volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */ | ||
| 202 | volatile unsigned char RESERVED29[0x16]; /* Reserved area */ | ||
| 203 | /* Timer */ | ||
| 204 | volatile unsigned short timer_tgcr; /* timer global configuration reg */ | ||
| 205 | volatile unsigned char RESERVED30[0xe]; /* Reserved area */ | ||
| 206 | volatile unsigned short timer_tmr1; /* timer 1 mode reg */ | ||
| 207 | volatile unsigned short timer_tmr2; /* timer 2 mode reg */ | ||
| 208 | volatile unsigned short timer_trr1; /* timer 1 referance reg */ | ||
| 209 | volatile unsigned short timer_trr2; /* timer 2 referance reg */ | ||
| 210 | volatile unsigned short timer_tcr1; /* timer 1 capture reg */ | ||
| 211 | volatile unsigned short timer_tcr2; /* timer 2 capture reg */ | ||
| 212 | volatile unsigned short timer_tcn1; /* timer 1 counter reg */ | ||
| 213 | volatile unsigned short timer_tcn2; /* timer 2 counter reg */ | ||
| 214 | volatile unsigned short timer_tmr3; /* timer 3 mode reg */ | ||
| 215 | volatile unsigned short timer_tmr4; /* timer 4 mode reg */ | ||
| 216 | volatile unsigned short timer_trr3; /* timer 3 referance reg */ | ||
| 217 | volatile unsigned short timer_trr4; /* timer 4 referance reg */ | ||
| 218 | volatile unsigned short timer_tcr3; /* timer 3 capture reg */ | ||
| 219 | volatile unsigned short timer_tcr4; /* timer 4 capture reg */ | ||
| 220 | volatile unsigned short timer_tcn3; /* timer 3 counter reg */ | ||
| 221 | volatile unsigned short timer_tcn4; /* timer 4 counter reg */ | ||
| 222 | volatile unsigned short timer_ter1; /* timer 1 event reg */ | ||
| 223 | volatile unsigned short timer_ter2; /* timer 2 event reg */ | ||
| 224 | volatile unsigned short timer_ter3; /* timer 3 event reg */ | ||
| 225 | volatile unsigned short timer_ter4; /* timer 4 event reg */ | ||
| 226 | volatile unsigned char RESERVED34[0x8]; /* Reserved area */ | ||
| 227 | /* CP */ | ||
| 228 | volatile unsigned short cp_cr; /* command register */ | ||
| 229 | volatile unsigned char RESERVED35[0x2]; /* Reserved area */ | ||
| 230 | volatile unsigned short cp_rccr; /* main configuration reg */ | ||
| 231 | volatile unsigned char RESERVED37; /* Reserved area */ | ||
| 232 | volatile unsigned char cp_rmds; /* development support status reg */ | ||
| 233 | volatile unsigned long cp_rmdr; /* development support control reg */ | ||
| 234 | volatile unsigned short cp_rctr1; /* ram break register 1 */ | ||
| 235 | volatile unsigned short cp_rctr2; /* ram break register 2 */ | ||
| 236 | volatile unsigned short cp_rctr3; /* ram break register 3 */ | ||
| 237 | volatile unsigned short cp_rctr4; /* ram break register 4 */ | ||
| 238 | volatile unsigned char RESERVED59[0x2]; /* Reserved area */ | ||
| 239 | volatile unsigned short cp_rter; /* RISC timers event reg */ | ||
| 240 | volatile unsigned char RESERVED38[0x2]; /* Reserved area */ | ||
| 241 | volatile unsigned short cp_rtmr; /* RISC timers mask reg */ | ||
| 242 | volatile unsigned char RESERVED39[0x14]; /* Reserved area */ | ||
| 243 | /* BRG */ | ||
| 244 | union { | ||
| 245 | volatile unsigned long l; | ||
| 246 | struct { | ||
| 247 | volatile unsigned short BRGC_RESERV:14; | ||
| 248 | volatile unsigned short rst:1; | ||
| 249 | volatile unsigned short en:1; | ||
| 250 | volatile unsigned short extc:2; | ||
| 251 | volatile unsigned short atb:1; | ||
| 252 | volatile unsigned short cd:12; | ||
| 253 | volatile unsigned short div16:1; | ||
| 254 | } b; | ||
| 255 | } brgc[4]; /* BRG1-BRG4 configuration regs*/ | ||
| 256 | /* SCC registers */ | ||
| 257 | struct scc_regs { | ||
| 258 | union { | ||
| 259 | struct { | ||
| 260 | /* Low word. */ | ||
| 261 | volatile unsigned short GSMR_RESERV2:1; | ||
| 262 | volatile unsigned short edge:2; | ||
| 263 | volatile unsigned short tci:1; | ||
| 264 | volatile unsigned short tsnc:2; | ||
| 265 | volatile unsigned short rinv:1; | ||
| 266 | volatile unsigned short tinv:1; | ||
| 267 | volatile unsigned short tpl:3; | ||
| 268 | volatile unsigned short tpp:2; | ||
| 269 | volatile unsigned short tend:1; | ||
| 270 | volatile unsigned short tdcr:2; | ||
| 271 | volatile unsigned short rdcr:2; | ||
| 272 | volatile unsigned short renc:3; | ||
| 273 | volatile unsigned short tenc:3; | ||
| 274 | volatile unsigned short diag:2; | ||
| 275 | volatile unsigned short enr:1; | ||
| 276 | volatile unsigned short ent:1; | ||
| 277 | volatile unsigned short mode:4; | ||
| 278 | /* High word. */ | ||
| 279 | volatile unsigned short GSMR_RESERV1:14; | ||
| 280 | volatile unsigned short pri:1; | ||
| 281 | volatile unsigned short gde:1; | ||
| 282 | volatile unsigned short tcrc:2; | ||
| 283 | volatile unsigned short revd:1; | ||
| 284 | volatile unsigned short trx:1; | ||
| 285 | volatile unsigned short ttx:1; | ||
| 286 | volatile unsigned short cdp:1; | ||
| 287 | volatile unsigned short ctsp:1; | ||
| 288 | volatile unsigned short cds:1; | ||
| 289 | volatile unsigned short ctss:1; | ||
| 290 | volatile unsigned short tfl:1; | ||
| 291 | volatile unsigned short rfw:1; | ||
| 292 | volatile unsigned short txsy:1; | ||
| 293 | volatile unsigned short synl:2; | ||
| 294 | volatile unsigned short rtsm:1; | ||
| 295 | volatile unsigned short rsyn:1; | ||
| 296 | } b; | ||
| 297 | struct { | ||
| 298 | volatile unsigned long low; | ||
| 299 | volatile unsigned long high; | ||
| 300 | } w; | ||
| 301 | } scc_gsmr; /* SCC general mode reg */ | ||
| 302 | volatile unsigned short scc_psmr; /* protocol specific mode reg */ | ||
| 303 | volatile unsigned char RESERVED42[0x2]; /* Reserved area */ | ||
| 304 | volatile unsigned short scc_todr; /* SCC transmit on demand */ | ||
| 305 | volatile unsigned short scc_dsr; /* SCC data sync reg */ | ||
| 306 | volatile unsigned short scc_scce; /* SCC event reg */ | ||
| 307 | volatile unsigned char RESERVED43[0x2];/* Reserved area */ | ||
| 308 | volatile unsigned short scc_sccm; /* SCC mask reg */ | ||
| 309 | volatile unsigned char RESERVED44[0x1];/* Reserved area */ | ||
| 310 | volatile unsigned char scc_sccs; /* SCC status reg */ | ||
| 311 | volatile unsigned char RESERVED45[0x8]; /* Reserved area */ | ||
| 312 | } scc_regs[4]; | ||
| 313 | /* SMC */ | ||
| 314 | struct smc_regs { | ||
| 315 | volatile unsigned char RESERVED46[0x2]; /* Reserved area */ | ||
| 316 | volatile unsigned short smc_smcmr; /* SMC mode reg */ | ||
| 317 | volatile unsigned char RESERVED60[0x2]; /* Reserved area */ | ||
| 318 | volatile unsigned char smc_smce; /* SMC event reg */ | ||
| 319 | volatile unsigned char RESERVED47[0x3]; /* Reserved area */ | ||
| 320 | volatile unsigned char smc_smcm; /* SMC mask reg */ | ||
| 321 | volatile unsigned char RESERVED48[0x5]; /* Reserved area */ | ||
| 322 | } smc_regs[2]; | ||
| 323 | /* SPI */ | ||
| 324 | volatile unsigned short spi_spmode; /* SPI mode reg */ | ||
| 325 | volatile unsigned char RESERVED51[0x4]; /* Reserved area */ | ||
| 326 | volatile unsigned char spi_spie; /* SPI event reg */ | ||
| 327 | volatile unsigned char RESERVED52[0x3]; /* Reserved area */ | ||
| 328 | volatile unsigned char spi_spim; /* SPI mask reg */ | ||
| 329 | volatile unsigned char RESERVED53[0x2]; /* Reserved area */ | ||
| 330 | volatile unsigned char spi_spcom; /* SPI command reg */ | ||
| 331 | volatile unsigned char RESERVED54[0x4]; /* Reserved area */ | ||
| 332 | /* PIP */ | ||
| 333 | volatile unsigned short pip_pipc; /* pip configuration reg */ | ||
| 334 | volatile unsigned char RESERVED65[0x2]; /* Reserved area */ | ||
| 335 | volatile unsigned short pip_ptpr; /* pip timing parameters reg */ | ||
| 336 | volatile unsigned long pip_pbdir; /* port b data direction reg */ | ||
| 337 | volatile unsigned long pip_pbpar; /* port b pin assignment reg */ | ||
| 338 | volatile unsigned long pip_pbodr; /* port b open drain reg */ | ||
| 339 | volatile unsigned long pip_pbdat; /* port b data reg */ | ||
| 340 | volatile unsigned char RESERVED71[0x18]; /* Reserved area */ | ||
| 341 | /* Serial Interface */ | ||
| 342 | volatile unsigned long si_simode; /* SI mode register */ | ||
| 343 | volatile unsigned char si_sigmr; /* SI global mode register */ | ||
| 344 | volatile unsigned char RESERVED55; /* Reserved area */ | ||
| 345 | volatile unsigned char si_sistr; /* SI status register */ | ||
| 346 | volatile unsigned char si_sicmr; /* SI command register */ | ||
| 347 | volatile unsigned char RESERVED56[0x4]; /* Reserved area */ | ||
| 348 | volatile unsigned long si_sicr; /* SI clock routing */ | ||
| 349 | volatile unsigned long si_sirp; /* SI ram pointers */ | ||
| 350 | volatile unsigned char RESERVED57[0xc]; /* Reserved area */ | ||
| 351 | volatile unsigned short si_siram[0x80]; /* SI routing ram */ | ||
| 352 | } QUICC; | ||
| 353 | |||
| 354 | #endif | ||
| 355 | |||
| 356 | /* | ||
| 357 | * Local variables: | ||
| 358 | * c-indent-level: 4 | ||
| 359 | * c-basic-offset: 4 | ||
| 360 | * tab-width: 4 | ||
| 361 | * End: | ||
| 362 | */ | ||
diff --git a/arch/m68k/include/asm/m68360_regs.h b/arch/m68k/include/asm/m68360_regs.h new file mode 100644 index 000000000000..d57217ca4f27 --- /dev/null +++ b/arch/m68k/include/asm/m68360_regs.h | |||
| @@ -0,0 +1,408 @@ | |||
| 1 | /*********************************** | ||
| 2 | * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $ | ||
| 3 | *********************************** | ||
| 4 | * | ||
| 5 | *************************************** | ||
| 6 | * Definitions of the QUICC registers | ||
| 7 | *************************************** | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __REGISTERS_H | ||
| 11 | #define __REGISTERS_H | ||
| 12 | |||
| 13 | #define CLEAR_BIT(x, bit) x =bit | ||
| 14 | |||
| 15 | /***************************************************************** | ||
| 16 | Command Register | ||
| 17 | *****************************************************************/ | ||
| 18 | |||
| 19 | /* bit fields within command register */ | ||
| 20 | #define SOFTWARE_RESET 0x8000 | ||
| 21 | #define CMD_OPCODE 0x0f00 | ||
| 22 | #define CMD_CHANNEL 0x00f0 | ||
| 23 | #define CMD_FLAG 0x0001 | ||
| 24 | |||
| 25 | /* general command opcodes */ | ||
| 26 | #define INIT_RXTX_PARAMS 0x0000 | ||
| 27 | #define INIT_RX_PARAMS 0x0100 | ||
| 28 | #define INIT_TX_PARAMS 0x0200 | ||
| 29 | #define ENTER_HUNT_MODE 0x0300 | ||
| 30 | #define STOP_TX 0x0400 | ||
| 31 | #define GR_STOP_TX 0x0500 | ||
| 32 | #define RESTART_TX 0x0600 | ||
| 33 | #define CLOSE_RX_BD 0x0700 | ||
| 34 | #define SET_ENET_GROUP 0x0800 | ||
| 35 | #define RESET_ENET_GROUP 0x0900 | ||
| 36 | |||
| 37 | /* quicc32 CP commands */ | ||
| 38 | #define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */ | ||
| 39 | #define ENTER_HUNT_MODE_32 0x1e00 | ||
| 40 | |||
| 41 | /* quicc32 mask/event SCC register */ | ||
| 42 | #define GOV 0x01 | ||
| 43 | #define GUN 0x02 | ||
| 44 | #define GINT 0x04 | ||
| 45 | #define IQOV 0x08 | ||
| 46 | |||
| 47 | |||
| 48 | /* Timer commands */ | ||
| 49 | #define SET_TIMER 0x0800 | ||
| 50 | |||
| 51 | /* Multi channel Interrupt structure */ | ||
| 52 | #define INTR_VALID 0x8000 /* Valid interrupt entry */ | ||
| 53 | #define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */ | ||
| 54 | #define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */ | ||
| 55 | #define INTR_MASK_BITS 0x383f | ||
| 56 | |||
| 57 | /* | ||
| 58 | * General SCC mode register (GSMR) | ||
| 59 | */ | ||
| 60 | |||
| 61 | #define MODE_HDLC 0x0 | ||
| 62 | #define MODE_APPLE_TALK 0x2 | ||
| 63 | #define MODE_SS7 0x3 | ||
| 64 | #define MODE_UART 0x4 | ||
| 65 | #define MODE_PROFIBUS 0x5 | ||
| 66 | #define MODE_ASYNC_HDLC 0x6 | ||
| 67 | #define MODE_V14 0x7 | ||
| 68 | #define MODE_BISYNC 0x8 | ||
| 69 | #define MODE_DDCMP 0x9 | ||
| 70 | #define MODE_MULTI_CHANNEL 0xa | ||
| 71 | #define MODE_ETHERNET 0xc | ||
| 72 | |||
| 73 | #define DIAG_NORMAL 0x0 | ||
| 74 | #define DIAG_LOCAL_LPB 0x1 | ||
| 75 | #define DIAG_AUTO_ECHO 0x2 | ||
| 76 | #define DIAG_LBP_ECHO 0x3 | ||
| 77 | |||
| 78 | /* For RENC and TENC fields in GSMR */ | ||
| 79 | #define ENC_NRZ 0x0 | ||
| 80 | #define ENC_NRZI 0x1 | ||
| 81 | #define ENC_FM0 0x2 | ||
| 82 | #define ENC_MANCH 0x4 | ||
| 83 | #define ENC_DIFF_MANC 0x6 | ||
| 84 | |||
| 85 | /* For TDCR and RDCR fields in GSMR */ | ||
| 86 | #define CLOCK_RATE_1 0x0 | ||
| 87 | #define CLOCK_RATE_8 0x1 | ||
| 88 | #define CLOCK_RATE_16 0x2 | ||
| 89 | #define CLOCK_RATE_32 0x3 | ||
| 90 | |||
| 91 | #define TPP_00 0x0 | ||
| 92 | #define TPP_10 0x1 | ||
| 93 | #define TPP_01 0x2 | ||
| 94 | #define TPP_11 0x3 | ||
| 95 | |||
| 96 | #define TPL_NO 0x0 | ||
| 97 | #define TPL_8 0x1 | ||
| 98 | #define TPL_16 0x2 | ||
| 99 | #define TPL_32 0x3 | ||
| 100 | #define TPL_48 0x4 | ||
| 101 | #define TPL_64 0x5 | ||
| 102 | #define TPL_128 0x6 | ||
| 103 | |||
| 104 | #define TSNC_INFINITE 0x0 | ||
| 105 | #define TSNC_14_65 0x1 | ||
| 106 | #define TSNC_4_15 0x2 | ||
| 107 | #define TSNC_3_1 0x3 | ||
| 108 | |||
| 109 | #define EDGE_BOTH 0x0 | ||
| 110 | #define EDGE_POS 0x1 | ||
| 111 | #define EDGE_NEG 0x2 | ||
| 112 | #define EDGE_NO 0x3 | ||
| 113 | |||
| 114 | #define SYNL_NO 0x0 | ||
| 115 | #define SYNL_4 0x1 | ||
| 116 | #define SYNL_8 0x2 | ||
| 117 | #define SYNL_16 0x3 | ||
| 118 | |||
| 119 | #define TCRC_CCITT16 0x0 | ||
| 120 | #define TCRC_CRC16 0x1 | ||
| 121 | #define TCRC_CCITT32 0x2 | ||
| 122 | |||
| 123 | |||
| 124 | /***************************************************************** | ||
| 125 | TODR (Transmit on demand) Register | ||
| 126 | *****************************************************************/ | ||
| 127 | #define TODR_TOD 0x8000 /* Transmit on demand */ | ||
| 128 | |||
| 129 | |||
| 130 | /***************************************************************** | ||
| 131 | CICR register settings | ||
| 132 | *****************************************************************/ | ||
| 133 | |||
| 134 | /* note that relative irq priorities of the SCCs can be reordered | ||
| 135 | * if desired - see p. 7-377 of the MC68360UM */ | ||
| 136 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | ||
| 137 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | ||
| 138 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | ||
| 139 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | ||
| 140 | |||
| 141 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ | ||
| 142 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ | ||
| 143 | #define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */ | ||
| 144 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | ||
| 145 | |||
| 146 | |||
| 147 | /***************************************************************** | ||
| 148 | Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379) | ||
| 149 | *****************************************************************/ | ||
| 150 | |||
| 151 | #define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */ | ||
| 152 | #define INTR_SCC1 0x40000000 /* SCC port 1 */ | ||
| 153 | #define INTR_SCC2 0x20000000 /* SCC port 2 */ | ||
| 154 | #define INTR_SCC3 0x10000000 /* SCC port 3 */ | ||
| 155 | #define INTR_SCC4 0x08000000 /* SCC port 4 */ | ||
| 156 | #define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */ | ||
| 157 | #define INTR_TIMER1 0x02000000 /* timer 1 */ | ||
| 158 | #define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */ | ||
| 159 | #define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */ | ||
| 160 | #define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */ | ||
| 161 | #define INTR_DMA1 0x00200000 /* idma 1 */ | ||
| 162 | #define INTR_DMA2 0x00100000 /* idma 2 */ | ||
| 163 | #define INTR_TIMER2 0x00040000 /* timer 2 */ | ||
| 164 | #define INTR_CP_TIMER 0x00020000 /* CP timer */ | ||
| 165 | #define INTR_PIP_STATUS 0x00010000 /* PIP status */ | ||
| 166 | #define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */ | ||
| 167 | #define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */ | ||
| 168 | #define INTR_TIMER3 0x00001000 /* timer 3 */ | ||
| 169 | #define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */ | ||
| 170 | #define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */ | ||
| 171 | #define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */ | ||
| 172 | #define INTR_TIMER4 0x00000080 /* timer 4 */ | ||
| 173 | #define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */ | ||
| 174 | #define INTR_SCP 0x00000020 /* SCP */ | ||
| 175 | #define INTR_SMC1 0x00000010 /* SMC 1 */ | ||
| 176 | #define INTR_SMC2 0x00000008 /* SMC 2 */ | ||
| 177 | #define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */ | ||
| 178 | #define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */ | ||
| 179 | #define INTR_ERR 0x00000001 /* error */ | ||
| 180 | |||
| 181 | |||
| 182 | /***************************************************************** | ||
| 183 | CPM Interrupt vector encodings (MC68360UM p. 7-376) | ||
| 184 | *****************************************************************/ | ||
| 185 | |||
| 186 | #define CPMVEC_NR 32 | ||
| 187 | #define CPMVEC_PIO_PC0 0x1f | ||
| 188 | #define CPMVEC_SCC1 0x1e | ||
| 189 | #define CPMVEC_SCC2 0x1d | ||
| 190 | #define CPMVEC_SCC3 0x1c | ||
| 191 | #define CPMVEC_SCC4 0x1b | ||
| 192 | #define CPMVEC_PIO_PC1 0x1a | ||
| 193 | #define CPMVEC_TIMER1 0x19 | ||
| 194 | #define CPMVEC_PIO_PC2 0x18 | ||
| 195 | #define CPMVEC_PIO_PC3 0x17 | ||
| 196 | #define CPMVEC_SDMA_CB_ERR 0x16 | ||
| 197 | #define CPMVEC_IDMA1 0x15 | ||
| 198 | #define CPMVEC_IDMA2 0x14 | ||
| 199 | #define CPMVEC_RESERVED3 0x13 | ||
| 200 | #define CPMVEC_TIMER2 0x12 | ||
| 201 | #define CPMVEC_RISCTIMER 0x11 | ||
| 202 | #define CPMVEC_RESERVED2 0x10 | ||
| 203 | #define CPMVEC_PIO_PC4 0x0f | ||
| 204 | #define CPMVEC_PIO_PC5 0x0e | ||
| 205 | #define CPMVEC_TIMER3 0x0c | ||
| 206 | #define CPMVEC_PIO_PC6 0x0b | ||
| 207 | #define CPMVEC_PIO_PC7 0x0a | ||
| 208 | #define CPMVEC_PIO_PC8 0x09 | ||
| 209 | #define CPMVEC_RESERVED1 0x08 | ||
| 210 | #define CPMVEC_TIMER4 0x07 | ||
| 211 | #define CPMVEC_PIO_PC9 0x06 | ||
| 212 | #define CPMVEC_SPI 0x05 | ||
| 213 | #define CPMVEC_SMC1 0x04 | ||
| 214 | #define CPMVEC_SMC2 0x03 | ||
| 215 | #define CPMVEC_PIO_PC10 0x02 | ||
| 216 | #define CPMVEC_PIO_PC11 0x01 | ||
| 217 | #define CPMVEC_ERROR 0x00 | ||
| 218 | |||
| 219 | /* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */ | ||
| 220 | /* #define CPMVEC_SCC1 ((ushort)0x1e) */ | ||
| 221 | /* #define CPMVEC_SCC2 ((ushort)0x1d) */ | ||
| 222 | /* #define CPMVEC_SCC3 ((ushort)0x1c) */ | ||
| 223 | /* #define CPMVEC_SCC4 ((ushort)0x1b) */ | ||
| 224 | /* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */ | ||
| 225 | /* #define CPMVEC_TIMER1 ((ushort)0x19) */ | ||
| 226 | /* #define CPMVEC_PIO_PC2 ((ushort)0x18) */ | ||
| 227 | /* #define CPMVEC_PIO_PC3 ((ushort)0x17) */ | ||
| 228 | /* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ | ||
| 229 | /* #define CPMVEC_IDMA1 ((ushort)0x15) */ | ||
| 230 | /* #define CPMVEC_IDMA2 ((ushort)0x14) */ | ||
| 231 | /* #define CPMVEC_RESERVED3 ((ushort)0x13) */ | ||
| 232 | /* #define CPMVEC_TIMER2 ((ushort)0x12) */ | ||
| 233 | /* #define CPMVEC_RISCTIMER ((ushort)0x11) */ | ||
| 234 | /* #define CPMVEC_RESERVED2 ((ushort)0x10) */ | ||
| 235 | /* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */ | ||
| 236 | /* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */ | ||
| 237 | /* #define CPMVEC_TIMER3 ((ushort)0x0c) */ | ||
| 238 | /* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */ | ||
| 239 | /* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */ | ||
| 240 | /* #define CPMVEC_PIO_PC8 ((ushort)0x09) */ | ||
| 241 | /* #define CPMVEC_RESERVED1 ((ushort)0x08) */ | ||
| 242 | /* #define CPMVEC_TIMER4 ((ushort)0x07) */ | ||
| 243 | /* #define CPMVEC_PIO_PC9 ((ushort)0x06) */ | ||
| 244 | /* #define CPMVEC_SPI ((ushort)0x05) */ | ||
| 245 | /* #define CPMVEC_SMC1 ((ushort)0x04) */ | ||
| 246 | /* #define CPMVEC_SMC2 ((ushort)0x03) */ | ||
| 247 | /* #define CPMVEC_PIO_PC10 ((ushort)0x02) */ | ||
| 248 | /* #define CPMVEC_PIO_PC11 ((ushort)0x01) */ | ||
| 249 | /* #define CPMVEC_ERROR ((ushort)0x00) */ | ||
| 250 | |||
| 251 | |||
| 252 | /***************************************************************** | ||
| 253 | * PIO control registers | ||
| 254 | *****************************************************************/ | ||
| 255 | |||
| 256 | /* Port A - See 360UM p. 7-358 | ||
| 257 | * | ||
| 258 | * Note that most of these pins have alternate functions | ||
| 259 | */ | ||
| 260 | |||
| 261 | |||
| 262 | /* The macros are nice, but there are all sorts of references to 1-indexed | ||
| 263 | * facilities on the 68360... */ | ||
| 264 | /* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */ | ||
| 265 | /* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */ | ||
| 266 | |||
| 267 | #define PA_RXD1 ((ushort)0x0001) | ||
| 268 | #define PA_TXD1 ((ushort)0x0002) | ||
| 269 | #define PA_RXD2 ((ushort)0x0004) | ||
| 270 | #define PA_TXD2 ((ushort)0x0008) | ||
| 271 | #define PA_RXD3 ((ushort)0x0010) | ||
| 272 | #define PA_TXD3 ((ushort)0x0020) | ||
| 273 | #define PA_RXD4 ((ushort)0x0040) | ||
| 274 | #define PA_TXD4 ((ushort)0x0080) | ||
| 275 | |||
| 276 | #define PA_CLK1 ((ushort)0x0100) | ||
| 277 | #define PA_CLK2 ((ushort)0x0200) | ||
| 278 | #define PA_CLK3 ((ushort)0x0400) | ||
| 279 | #define PA_CLK4 ((ushort)0x0800) | ||
| 280 | #define PA_CLK5 ((ushort)0x1000) | ||
| 281 | #define PA_CLK6 ((ushort)0x2000) | ||
| 282 | #define PA_CLK7 ((ushort)0x4000) | ||
| 283 | #define PA_CLK8 ((ushort)0x8000) | ||
| 284 | |||
| 285 | |||
| 286 | /* Port B - See 360UM p. 7-362 | ||
| 287 | */ | ||
| 288 | |||
| 289 | |||
| 290 | /* Port C - See 360UM p. 7-365 | ||
| 291 | */ | ||
| 292 | |||
| 293 | #define PC_RTS1 ((ushort)0x0001) | ||
| 294 | #define PC_RTS2 ((ushort)0x0002) | ||
| 295 | #define PC__RTS3 ((ushort)0x0004) /* !RTS3 */ | ||
| 296 | #define PC__RTS4 ((ushort)0x0008) /* !RTS4 */ | ||
| 297 | |||
| 298 | #define PC_CTS1 ((ushort)0x0010) | ||
| 299 | #define PC_CD1 ((ushort)0x0020) | ||
| 300 | #define PC_CTS2 ((ushort)0x0040) | ||
| 301 | #define PC_CD2 ((ushort)0x0080) | ||
| 302 | #define PC_CTS3 ((ushort)0x0100) | ||
| 303 | #define PC_CD3 ((ushort)0x0200) | ||
| 304 | #define PC_CTS4 ((ushort)0x0400) | ||
| 305 | #define PC_CD4 ((ushort)0x0800) | ||
| 306 | |||
| 307 | |||
| 308 | |||
| 309 | /***************************************************************** | ||
| 310 | chip select option register | ||
| 311 | *****************************************************************/ | ||
| 312 | #define DTACK 0xe000 | ||
| 313 | #define ADR_MASK 0x1ffc | ||
| 314 | #define RDWR_MASK 0x0002 | ||
| 315 | #define FC_MASK 0x0001 | ||
| 316 | |||
| 317 | /***************************************************************** | ||
| 318 | tbase and rbase registers | ||
| 319 | *****************************************************************/ | ||
| 320 | #define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \ | ||
| 321 | (quicc->ch_or_u.u.udata_bd_ucode + pram->tbase)) | ||
| 322 | #define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \ | ||
| 323 | (quicc->ch_or_u.u.udata_bd_ucode + pram->rbase)) | ||
| 324 | #define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ | ||
| 325 | (quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr)) | ||
| 326 | #define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ | ||
| 327 | (quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr)) | ||
| 328 | #define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \ | ||
| 329 | ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode))) | ||
| 330 | #define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \ | ||
| 331 | ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode))) | ||
| 332 | #define INCREASE_TBD(bd,quicc,pram) { \ | ||
| 333 | if((bd)->status & T_W) \ | ||
| 334 | (bd) = TBD_ADDR(quicc,pram); \ | ||
| 335 | else \ | ||
| 336 | (bd)++; \ | ||
| 337 | } | ||
| 338 | #define DECREASE_TBD(bd,quicc,pram) { \ | ||
| 339 | if ((bd) == TBD_ADDR(quicc, pram)) \ | ||
| 340 | while (!((bd)->status & T_W)) \ | ||
| 341 | (bd)++; \ | ||
| 342 | else \ | ||
| 343 | (bd)--; \ | ||
| 344 | } | ||
| 345 | #define INCREASE_RBD(bd,quicc,pram) { \ | ||
| 346 | if((bd)->status & R_W) \ | ||
| 347 | (bd) = RBD_ADDR(quicc,pram); \ | ||
| 348 | else \ | ||
| 349 | (bd)++; \ | ||
| 350 | } | ||
| 351 | #define DECREASE_RBD(bd,quicc,pram) { \ | ||
| 352 | if ((bd) == RBD_ADDR(quicc, pram)) \ | ||
| 353 | while (!((bd)->status & T_W)) \ | ||
| 354 | (bd)++; \ | ||
| 355 | else \ | ||
| 356 | (bd)--; \ | ||
| 357 | } | ||
| 358 | |||
| 359 | /***************************************************************** | ||
| 360 | Macros for Multi channel | ||
| 361 | *****************************************************************/ | ||
| 362 | #define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page]) | ||
| 363 | #define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase) | ||
| 364 | #define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \ | ||
| 365 | (&(quicc->ch_or_u.ch_pram_tbl[channel]))) | ||
| 366 | #define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \ | ||
| 367 | (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase))) | ||
| 368 | #define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \ | ||
| 369 | (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase))) | ||
| 370 | #define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \ | ||
| 371 | (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr))) | ||
| 372 | #define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \ | ||
| 373 | (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr))) | ||
| 374 | #define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \ | ||
| 375 | CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \ | ||
| 376 | ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page)))) | ||
| 377 | #define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \ | ||
| 378 | CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \ | ||
| 379 | ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page)))) | ||
| 380 | |||
| 381 | #define INCREASE_TBD_32(bd,quicc,page,channel) { \ | ||
| 382 | if((bd)->status & T_W) \ | ||
| 383 | (bd) = TBD_32_ADDR(quicc,page,channel); \ | ||
| 384 | else \ | ||
| 385 | (bd)++; \ | ||
| 386 | } | ||
| 387 | #define DECREASE_TBD_32(bd,quicc,page,channel) { \ | ||
| 388 | if ((bd) == TBD_32_ADDR(quicc, page,channel)) \ | ||
| 389 | while (!((bd)->status & T_W)) \ | ||
| 390 | (bd)++; \ | ||
| 391 | else \ | ||
| 392 | (bd)--; \ | ||
| 393 | } | ||
| 394 | #define INCREASE_RBD_32(bd,quicc,page,channel) { \ | ||
| 395 | if((bd)->status & R_W) \ | ||
| 396 | (bd) = RBD_32_ADDR(quicc,page,channel); \ | ||
| 397 | else \ | ||
| 398 | (bd)++; \ | ||
| 399 | } | ||
| 400 | #define DECREASE_RBD_32(bd,quicc,page,channel) { \ | ||
| 401 | if ((bd) == RBD_32_ADDR(quicc, page,channel)) \ | ||
| 402 | while (!((bd)->status & T_W)) \ | ||
| 403 | (bd)++; \ | ||
| 404 | else \ | ||
| 405 | (bd)--; \ | ||
| 406 | } | ||
| 407 | |||
| 408 | #endif | ||
diff --git a/arch/m68k/include/asm/mac_asc.h b/arch/m68k/include/asm/mac_asc.h new file mode 100644 index 000000000000..fc2e5467b41e --- /dev/null +++ b/arch/m68k/include/asm/mac_asc.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* | ||
| 2 | * Apple Sound Chip | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_MAC_ASC_H | ||
| 6 | #define __ASM_MAC_ASC_H | ||
| 7 | |||
| 8 | /* | ||
| 9 | * ASC offsets and controls | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define ASC_BUF_BASE 0x00 /* RAM buffer offset */ | ||
| 13 | #define ASC_BUF_SIZE 0x800 | ||
| 14 | |||
| 15 | #define ASC_CONTROL 0x800 | ||
| 16 | #define ASC_CONTROL_OFF 0x00 | ||
| 17 | #define ASC_FREQ(chan,byte) ((0x810)+((chan)<<3)+(byte)) | ||
| 18 | #define ASC_ENABLE 0x801 | ||
| 19 | #define ASC_ENABLE_SAMPLE 0x02 | ||
| 20 | #define ASC_MODE 0x802 | ||
| 21 | #define ASC_MODE_SAMPLE 0x02 | ||
| 22 | |||
| 23 | #define ASC_VOLUME 0x806 | ||
| 24 | #define ASC_CHAN 0x807 /* ??? */ | ||
| 25 | |||
| 26 | |||
| 27 | #endif | ||
diff --git a/arch/m68k/include/asm/mac_baboon.h b/arch/m68k/include/asm/mac_baboon.h new file mode 100644 index 000000000000..c2a042b8c349 --- /dev/null +++ b/arch/m68k/include/asm/mac_baboon.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * Definitions for the "Baboon" custom IC on the PowerBook 190. | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define BABOON_BASE (0x50F1A000) /* same as IDE controller base */ | ||
| 6 | |||
| 7 | #ifndef __ASSEMBLY__ | ||
| 8 | |||
| 9 | struct baboon { | ||
| 10 | char pad1[208]; /* generic IDE registers, not used here */ | ||
| 11 | short mb_control; /* Control register: | ||
| 12 | * bit 5 : slot 2 power control | ||
| 13 | * bit 6 : slot 1 power control | ||
| 14 | */ | ||
| 15 | char pad2[2]; | ||
| 16 | short mb_status; /* (0xD4) media bay status register: | ||
| 17 | * | ||
| 18 | * bit 0: ???? | ||
| 19 | * bit 1: IDE interrupt active? | ||
| 20 | * bit 2: bay status, 0 = full, 1 = empty | ||
| 21 | * bit 3: ???? | ||
| 22 | */ | ||
| 23 | char pad3[2]; /* (0xD6) not used */ | ||
| 24 | short mb_ifr; /* (0xD8) media bay interrupt flags register: | ||
| 25 | * | ||
| 26 | * bit 0: ???? | ||
| 27 | * bit 1: IDE controller interrupt | ||
| 28 | * bit 2: media bay status change interrupt | ||
| 29 | */ | ||
| 30 | }; | ||
| 31 | |||
| 32 | #endif /* __ASSEMBLY **/ | ||
diff --git a/arch/m68k/include/asm/mac_iop.h b/arch/m68k/include/asm/mac_iop.h new file mode 100644 index 000000000000..a2c7e6fcca38 --- /dev/null +++ b/arch/m68k/include/asm/mac_iop.h | |||
| @@ -0,0 +1,162 @@ | |||
| 1 | /* | ||
| 2 | * I/O Processor (IOP) defines and structures, mostly snagged from A/UX | ||
| 3 | * header files. | ||
| 4 | * | ||
| 5 | * The original header from which this was taken is copyrighted. I've done some | ||
| 6 | * rewriting (in fact my changes make this a bit more readable, IMHO) but some | ||
| 7 | * more should be done. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /* | ||
| 11 | * This is the base address of the IOPs. Use this as the address of | ||
| 12 | * a "struct iop" (see below) to see where the actual registers fall. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define SCC_IOP_BASE_IIFX (0x50F04000) | ||
| 16 | #define ISM_IOP_BASE_IIFX (0x50F12000) | ||
| 17 | |||
| 18 | #define SCC_IOP_BASE_QUADRA (0x50F0C000) | ||
| 19 | #define ISM_IOP_BASE_QUADRA (0x50F1E000) | ||
| 20 | |||
| 21 | /* IOP status/control register bits: */ | ||
| 22 | |||
| 23 | #define IOP_BYPASS 0x01 /* bypass-mode hardware access */ | ||
| 24 | #define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */ | ||
| 25 | #define IOP_RUN 0x04 /* set to 0 to reset IOP chip */ | ||
| 26 | #define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */ | ||
| 27 | #define IOP_INT0 0x10 /* intr priority from IOP to host */ | ||
| 28 | #define IOP_INT1 0x20 /* intr priority from IOP to host */ | ||
| 29 | #define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */ | ||
| 30 | #define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */ | ||
| 31 | |||
| 32 | #define NUM_IOPS 2 | ||
| 33 | #define NUM_IOP_CHAN 7 | ||
| 34 | #define NUM_IOP_MSGS NUM_IOP_CHAN*8 | ||
| 35 | #define IOP_MSG_LEN 32 | ||
| 36 | |||
| 37 | /* IOP reference numbers, used by the globally-visible iop_xxx functions */ | ||
| 38 | |||
| 39 | #define IOP_NUM_SCC 0 | ||
| 40 | #define IOP_NUM_ISM 1 | ||
| 41 | |||
| 42 | /* IOP channel states */ | ||
| 43 | |||
| 44 | #define IOP_MSG_IDLE 0 /* idle */ | ||
| 45 | #define IOP_MSG_NEW 1 /* new message sent */ | ||
| 46 | #define IOP_MSG_RCVD 2 /* message received; processing */ | ||
| 47 | #define IOP_MSG_COMPLETE 3 /* message processing complete */ | ||
| 48 | |||
| 49 | /* IOP message status codes */ | ||
| 50 | |||
| 51 | #define IOP_MSGSTATUS_UNUSED 0 /* Unusued message structure */ | ||
| 52 | #define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */ | ||
| 53 | #define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */ | ||
| 54 | #define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */ | ||
| 55 | #define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */ | ||
| 56 | |||
| 57 | /* IOP memory addresses of the members of the mac_iop_kernel structure. */ | ||
| 58 | |||
| 59 | #define IOP_ADDR_MAX_SEND_CHAN 0x0200 | ||
| 60 | #define IOP_ADDR_SEND_STATE 0x0201 | ||
| 61 | #define IOP_ADDR_PATCH_CTRL 0x021F | ||
| 62 | #define IOP_ADDR_SEND_MSG 0x0220 | ||
| 63 | #define IOP_ADDR_MAX_RECV_CHAN 0x0300 | ||
| 64 | #define IOP_ADDR_RECV_STATE 0x0301 | ||
| 65 | #define IOP_ADDR_ALIVE 0x031F | ||
| 66 | #define IOP_ADDR_RECV_MSG 0x0320 | ||
| 67 | |||
| 68 | #ifndef __ASSEMBLY__ | ||
| 69 | |||
| 70 | /* | ||
| 71 | * IOP Control registers, staggered because in usual Apple style they were | ||
| 72 | * too lazy to decode the A0 bit. This structure is assumed to begin at | ||
| 73 | * one of the xxx_IOP_BASE addresses given above. | ||
| 74 | */ | ||
| 75 | |||
| 76 | struct mac_iop { | ||
| 77 | __u8 ram_addr_hi; /* shared RAM address hi byte */ | ||
| 78 | __u8 pad0; | ||
| 79 | __u8 ram_addr_lo; /* shared RAM address lo byte */ | ||
| 80 | __u8 pad1; | ||
| 81 | __u8 status_ctrl; /* status/control register */ | ||
| 82 | __u8 pad2[3]; | ||
| 83 | __u8 ram_data; /* RAM data byte at ramhi/lo */ | ||
| 84 | |||
| 85 | __u8 pad3[23]; | ||
| 86 | |||
| 87 | /* Bypass-mode hardware access registers */ | ||
| 88 | |||
| 89 | union { | ||
| 90 | struct { /* SCC registers */ | ||
| 91 | __u8 sccb_cmd; /* SCC B command reg */ | ||
| 92 | __u8 pad4; | ||
| 93 | __u8 scca_cmd; /* SCC A command reg */ | ||
| 94 | __u8 pad5; | ||
| 95 | __u8 sccb_data; /* SCC B data */ | ||
| 96 | __u8 pad6; | ||
| 97 | __u8 scca_data; /* SCC A data */ | ||
| 98 | } scc_regs; | ||
| 99 | |||
| 100 | struct { /* ISM registers */ | ||
| 101 | __u8 wdata; /* write a data byte */ | ||
| 102 | __u8 pad7; | ||
| 103 | __u8 wmark; /* write a mark byte */ | ||
| 104 | __u8 pad8; | ||
| 105 | __u8 wcrc; /* write 2-byte crc to disk */ | ||
| 106 | __u8 pad9; | ||
| 107 | __u8 wparams; /* write the param regs */ | ||
| 108 | __u8 pad10; | ||
| 109 | __u8 wphase; /* write the phase states & dirs */ | ||
| 110 | __u8 pad11; | ||
| 111 | __u8 wsetup; /* write the setup register */ | ||
| 112 | __u8 pad12; | ||
| 113 | __u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */ | ||
| 114 | __u8 pad13; | ||
| 115 | __u8 wones; /* mode reg: 1's set bits, 0's are x */ | ||
| 116 | __u8 pad14; | ||
| 117 | __u8 rdata; /* read a data byte */ | ||
| 118 | __u8 pad15; | ||
| 119 | __u8 rmark; /* read a mark byte */ | ||
| 120 | __u8 pad16; | ||
| 121 | __u8 rerror; /* read the error register */ | ||
| 122 | __u8 pad17; | ||
| 123 | __u8 rparams; /* read the param regs */ | ||
| 124 | __u8 pad18; | ||
| 125 | __u8 rphase; /* read the phase states & dirs */ | ||
| 126 | __u8 pad19; | ||
| 127 | __u8 rsetup; /* read the setup register */ | ||
| 128 | __u8 pad20; | ||
| 129 | __u8 rmode; /* read the mode register */ | ||
| 130 | __u8 pad21; | ||
| 131 | __u8 rhandshake; /* read the handshake register */ | ||
| 132 | } ism_regs; | ||
| 133 | } b; | ||
| 134 | }; | ||
| 135 | |||
| 136 | /* This structure is used to track IOP messages in the Linux kernel */ | ||
| 137 | |||
| 138 | struct iop_msg { | ||
| 139 | struct iop_msg *next; /* next message in queue or NULL */ | ||
| 140 | uint iop_num; /* IOP number */ | ||
| 141 | uint channel; /* channel number */ | ||
| 142 | void *caller_priv; /* caller private data */ | ||
| 143 | int status; /* status of this message */ | ||
| 144 | __u8 message[IOP_MSG_LEN]; /* the message being sent/received */ | ||
| 145 | __u8 reply[IOP_MSG_LEN]; /* the reply to the message */ | ||
| 146 | void (*handler)(struct iop_msg *); | ||
| 147 | /* function to call when reply recvd */ | ||
| 148 | }; | ||
| 149 | |||
| 150 | extern int iop_scc_present,iop_ism_present; | ||
| 151 | |||
| 152 | extern int iop_listen(uint, uint, | ||
| 153 | void (*handler)(struct iop_msg *), | ||
| 154 | const char *); | ||
| 155 | extern int iop_send_message(uint, uint, void *, uint, __u8 *, | ||
| 156 | void (*)(struct iop_msg *)); | ||
| 157 | extern void iop_complete_message(struct iop_msg *); | ||
| 158 | extern void iop_upload_code(uint, __u8 *, uint, __u16); | ||
| 159 | extern void iop_download_code(uint, __u8 *, uint, __u16); | ||
| 160 | extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16); | ||
| 161 | |||
| 162 | #endif /* __ASSEMBLY__ */ | ||
diff --git a/arch/m68k/include/asm/mac_mouse.h b/arch/m68k/include/asm/mac_mouse.h new file mode 100644 index 000000000000..39a5c292eaee --- /dev/null +++ b/arch/m68k/include/asm/mac_mouse.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef _ASM_MAC_MOUSE_H | ||
| 2 | #define _ASM_MAC_MOUSE_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * linux/include/asm-m68k/mac_mouse.h | ||
| 6 | * header file for Macintosh ADB mouse driver | ||
| 7 | * 27-10-97 Michael Schmitz | ||
| 8 | * copied from: | ||
| 9 | * header file for Atari Mouse driver | ||
| 10 | * by Robert de Vries (robert@and.nl) on 19Jul93 | ||
| 11 | */ | ||
| 12 | |||
| 13 | struct mouse_status { | ||
| 14 | char buttons; | ||
| 15 | short dx; | ||
| 16 | short dy; | ||
| 17 | int ready; | ||
| 18 | int active; | ||
| 19 | wait_queue_head_t wait; | ||
| 20 | struct fasync_struct *fasyncptr; | ||
| 21 | }; | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h new file mode 100644 index 000000000000..7221f7251934 --- /dev/null +++ b/arch/m68k/include/asm/mac_oss.h | |||
| @@ -0,0 +1,94 @@ | |||
| 1 | /* | ||
| 2 | * OSS | ||
| 3 | * | ||
| 4 | * This is used in place of VIA2 on the IIfx. | ||
| 5 | */ | ||
| 6 | |||
| 7 | #define OSS_BASE (0x50f1a000) | ||
| 8 | |||
| 9 | /* | ||
| 10 | * Interrupt level offsets for mac_oss->irq_level | ||
| 11 | */ | ||
| 12 | |||
| 13 | #define OSS_NUBUS0 0 | ||
| 14 | #define OSS_NUBUS1 1 | ||
| 15 | #define OSS_NUBUS2 2 | ||
| 16 | #define OSS_NUBUS3 3 | ||
| 17 | #define OSS_NUBUS4 4 | ||
| 18 | #define OSS_NUBUS5 5 | ||
| 19 | #define OSS_IOPISM 6 | ||
| 20 | #define OSS_IOPSCC 7 | ||
| 21 | #define OSS_SOUND 8 | ||
| 22 | #define OSS_SCSI 9 | ||
| 23 | #define OSS_60HZ 10 | ||
| 24 | #define OSS_VIA1 11 | ||
| 25 | #define OSS_UNUSED1 12 | ||
| 26 | #define OSS_UNUSED2 13 | ||
| 27 | #define OSS_PARITY 14 | ||
| 28 | #define OSS_UNUSED3 15 | ||
| 29 | |||
| 30 | #define OSS_NUM_SOURCES 16 | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Pending interrupt bits in mac_oss->irq_pending | ||
| 34 | */ | ||
| 35 | |||
| 36 | #define OSS_IP_NUBUS0 0x0001 | ||
| 37 | #define OSS_IP_NUBUS1 0x0002 | ||
| 38 | #define OSS_IP_NUBUS2 0x0004 | ||
| 39 | #define OSS_IP_NUBUS3 0x0008 | ||
| 40 | #define OSS_IP_NUBUS4 0x0010 | ||
| 41 | #define OSS_IP_NUBUS5 0x0020 | ||
| 42 | #define OSS_IP_IOPISM 0x0040 | ||
| 43 | #define OSS_IP_IOPSCC 0x0080 | ||
| 44 | #define OSS_IP_SOUND 0x0100 | ||
| 45 | #define OSS_IP_SCSI 0x0200 | ||
| 46 | #define OSS_IP_60HZ 0x0400 | ||
| 47 | #define OSS_IP_VIA1 0x0800 | ||
| 48 | #define OSS_IP_UNUSED1 0x1000 | ||
| 49 | #define OSS_IP_UNUSED2 0x2000 | ||
| 50 | #define OSS_IP_PARITY 0x4000 | ||
| 51 | #define OSS_IP_UNUSED3 0x8000 | ||
| 52 | |||
| 53 | #define OSS_IP_NUBUS (OSS_IP_NUBUS0|OSS_IP_NUBUS1|OSS_IP_NUBUS2|OSS_IP_NUBUS3|OSS_IP_NUBUS4|OSS_IP_NUBUS5) | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Rom Control Register | ||
| 57 | */ | ||
| 58 | |||
| 59 | #define OSS_POWEROFF 0x80 | ||
| 60 | |||
| 61 | /* | ||
| 62 | * OSS Interrupt levels for various sub-systems | ||
| 63 | * | ||
| 64 | * This mapping is layed out with two things in mind: first, we try to keep | ||
| 65 | * things on their own levels to avoid having to do double-dispatches. Second, | ||
| 66 | * the levels match as closely as possible the alternate IRQ mapping mode (aka | ||
| 67 | * "A/UX mode") available on some VIA machines. | ||
| 68 | */ | ||
| 69 | |||
| 70 | #define OSS_IRQLEV_DISABLED 0 | ||
| 71 | #define OSS_IRQLEV_IOPISM 1 /* ADB? */ | ||
| 72 | #define OSS_IRQLEV_SCSI IRQ_AUTO_2 | ||
| 73 | #define OSS_IRQLEV_NUBUS IRQ_AUTO_3 /* keep this on its own level */ | ||
| 74 | #define OSS_IRQLEV_IOPSCC IRQ_AUTO_4 /* matches VIA alternate mapping */ | ||
| 75 | #define OSS_IRQLEV_SOUND IRQ_AUTO_5 /* matches VIA alternate mapping */ | ||
| 76 | #define OSS_IRQLEV_60HZ 6 /* matches VIA alternate mapping */ | ||
| 77 | #define OSS_IRQLEV_VIA1 IRQ_AUTO_6 /* matches VIA alternate mapping */ | ||
| 78 | #define OSS_IRQLEV_PARITY 7 /* matches VIA alternate mapping */ | ||
| 79 | |||
| 80 | #ifndef __ASSEMBLY__ | ||
| 81 | |||
| 82 | struct mac_oss { | ||
| 83 | __u8 irq_level[0x10]; /* [0x000-0x00f] Interrupt levels */ | ||
| 84 | __u8 padding0[0x1F2]; /* [0x010-0x201] IO space filler */ | ||
| 85 | __u16 irq_pending; /* [0x202-0x203] pending interrupts bits */ | ||
| 86 | __u8 rom_ctrl; /* [0x204-0x204] ROM cntl reg (for poweroff) */ | ||
| 87 | __u8 padding1[0x2]; /* [0x205-0x206] currently unused by A/UX */ | ||
| 88 | __u8 ack_60hz; /* [0x207-0x207] 60 Hz ack. */ | ||
| 89 | }; | ||
| 90 | |||
| 91 | extern volatile struct mac_oss *oss; | ||
| 92 | extern int oss_present; | ||
| 93 | |||
| 94 | #endif /* __ASSEMBLY__ */ | ||
diff --git a/arch/m68k/include/asm/mac_psc.h b/arch/m68k/include/asm/mac_psc.h new file mode 100644 index 000000000000..7808bb0b2323 --- /dev/null +++ b/arch/m68k/include/asm/mac_psc.h | |||
| @@ -0,0 +1,248 @@ | |||
| 1 | /* | ||
| 2 | * Apple Peripheral System Controller (PSC) | ||
| 3 | * | ||
| 4 | * The PSC is used on the AV Macs to control IO functions not handled | ||
| 5 | * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA | ||
| 6 | * channels. | ||
| 7 | * | ||
| 8 | * The first seven DMA channels appear to be "one-shot" and are actually | ||
| 9 | * sets of two channels; one member is active while the other is being | ||
| 10 | * configured, and then you flip the active member and start all over again. | ||
| 11 | * The one-shot channels are grouped together and are: | ||
| 12 | * | ||
| 13 | * 1. SCSI | ||
| 14 | * 2. Ethernet Read | ||
| 15 | * 3. Ethernet Write | ||
| 16 | * 4. Floppy Disk Controller | ||
| 17 | * 5. SCC Channel A Receive | ||
| 18 | * 6. SCC Channel B Receive | ||
| 19 | * 7. SCC Channel A Transmit | ||
| 20 | * | ||
| 21 | * The remaining two channels are handled somewhat differently. They appear | ||
| 22 | * to be closely tied and share one set of registers. They also seem to run | ||
| 23 | * continuously, although how you keep the buffer filled in this scenario is | ||
| 24 | * not understood as there seems to be only one input and one output buffer | ||
| 25 | * pointer. | ||
| 26 | * | ||
| 27 | * Much of this was extrapolated from what was known about the Ethernet | ||
| 28 | * registers and subsequently confirmed using MacsBug (ie by pinging the | ||
| 29 | * machine with easy-to-find patterns and looking for them in the DMA | ||
| 30 | * buffers, or by sending a file over the serial ports and finding the | ||
| 31 | * file in the buffers.) | ||
| 32 | * | ||
| 33 | * 1999-05-25 (jmt) | ||
| 34 | */ | ||
| 35 | |||
| 36 | #define PSC_BASE (0x50F31000) | ||
| 37 | |||
| 38 | /* | ||
| 39 | * The IER/IFR registers work like the VIA, except that it has 4 | ||
| 40 | * of them each on different interrupt levels, and each register | ||
| 41 | * set only seems to handle four interrupts instead of seven. | ||
| 42 | * | ||
| 43 | * To access a particular set of registers, add 0xn0 to the base | ||
| 44 | * where n = 3,4,5 or 6. | ||
| 45 | */ | ||
| 46 | |||
| 47 | #define pIFRbase 0x100 | ||
| 48 | #define pIERbase 0x104 | ||
| 49 | |||
| 50 | /* | ||
| 51 | * One-shot DMA control registers | ||
| 52 | */ | ||
| 53 | |||
| 54 | #define PSC_MYSTERY 0x804 | ||
| 55 | |||
| 56 | #define PSC_CTL_BASE 0xC00 | ||
| 57 | |||
| 58 | #define PSC_SCSI_CTL 0xC00 | ||
| 59 | #define PSC_ENETRD_CTL 0xC10 | ||
| 60 | #define PSC_ENETWR_CTL 0xC20 | ||
| 61 | #define PSC_FDC_CTL 0xC30 | ||
| 62 | #define PSC_SCCA_CTL 0xC40 | ||
| 63 | #define PSC_SCCB_CTL 0xC50 | ||
| 64 | #define PSC_SCCATX_CTL 0xC60 | ||
| 65 | |||
| 66 | /* | ||
| 67 | * DMA channels. Add +0x10 for the second channel in the set. | ||
| 68 | * You're supposed to use one channel while the other runs and | ||
| 69 | * then flip channels and do the whole thing again. | ||
| 70 | */ | ||
| 71 | |||
| 72 | #define PSC_ADDR_BASE 0x1000 | ||
| 73 | #define PSC_LEN_BASE 0x1004 | ||
| 74 | #define PSC_CMD_BASE 0x1008 | ||
| 75 | |||
| 76 | #define PSC_SET0 0x00 | ||
| 77 | #define PSC_SET1 0x10 | ||
| 78 | |||
| 79 | #define PSC_SCSI_ADDR 0x1000 /* confirmed */ | ||
| 80 | #define PSC_SCSI_LEN 0x1004 /* confirmed */ | ||
| 81 | #define PSC_SCSI_CMD 0x1008 /* confirmed */ | ||
| 82 | #define PSC_ENETRD_ADDR 0x1020 /* confirmed */ | ||
| 83 | #define PSC_ENETRD_LEN 0x1024 /* confirmed */ | ||
| 84 | #define PSC_ENETRD_CMD 0x1028 /* confirmed */ | ||
| 85 | #define PSC_ENETWR_ADDR 0x1040 /* confirmed */ | ||
| 86 | #define PSC_ENETWR_LEN 0x1044 /* confirmed */ | ||
| 87 | #define PSC_ENETWR_CMD 0x1048 /* confirmed */ | ||
| 88 | #define PSC_FDC_ADDR 0x1060 /* strongly suspected */ | ||
| 89 | #define PSC_FDC_LEN 0x1064 /* strongly suspected */ | ||
| 90 | #define PSC_FDC_CMD 0x1068 /* strongly suspected */ | ||
| 91 | #define PSC_SCCA_ADDR 0x1080 /* confirmed */ | ||
| 92 | #define PSC_SCCA_LEN 0x1084 /* confirmed */ | ||
| 93 | #define PSC_SCCA_CMD 0x1088 /* confirmed */ | ||
| 94 | #define PSC_SCCB_ADDR 0x10A0 /* confirmed */ | ||
| 95 | #define PSC_SCCB_LEN 0x10A4 /* confirmed */ | ||
| 96 | #define PSC_SCCB_CMD 0x10A8 /* confirmed */ | ||
| 97 | #define PSC_SCCATX_ADDR 0x10C0 /* confirmed */ | ||
| 98 | #define PSC_SCCATX_LEN 0x10C4 /* confirmed */ | ||
| 99 | #define PSC_SCCATX_CMD 0x10C8 /* confirmed */ | ||
| 100 | |||
| 101 | /* | ||
| 102 | * Free-running DMA registers. The only part known for sure are the bits in | ||
| 103 | * the control register, the buffer addresses and the buffer length. Everything | ||
| 104 | * else is anybody's guess. | ||
| 105 | * | ||
| 106 | * These registers seem to be mirrored every thirty-two bytes up until offset | ||
| 107 | * 0x300. It's safe to assume then that a new set of registers starts there. | ||
| 108 | */ | ||
| 109 | |||
| 110 | #define PSC_SND_CTL 0x200 /* | ||
| 111 | * [ 16-bit ] | ||
| 112 | * Sound (Singer?) control register. | ||
| 113 | * | ||
| 114 | * bit 0 : ???? | ||
| 115 | * bit 1 : ???? | ||
| 116 | * bit 2 : Set to one to enable sound | ||
| 117 | * output. Possibly a mute flag. | ||
| 118 | * bit 3 : ???? | ||
| 119 | * bit 4 : ???? | ||
| 120 | * bit 5 : ???? | ||
| 121 | * bit 6 : Set to one to enable pass-thru | ||
| 122 | * audio. In this mode the audio data | ||
| 123 | * seems to appear in both the input | ||
| 124 | * buffer and the output buffer. | ||
| 125 | * bit 7 : Set to one to activate the | ||
| 126 | * sound input DMA or zero to | ||
| 127 | * disable it. | ||
| 128 | * bit 8 : Set to one to activate the | ||
| 129 | * sound output DMA or zero to | ||
| 130 | * disable it. | ||
| 131 | * bit 9 : \ | ||
| 132 | * bit 11 : | | ||
| 133 | * These two bits control the sample | ||
| 134 | * rate. Usually set to binary 10 and | ||
| 135 | * MacOS 8.0 says I'm at 48 KHz. Using | ||
| 136 | * a binary value of 01 makes things | ||
| 137 | * sound about 1/2 speed (24 KHz?) and | ||
| 138 | * binary 00 is slower still (22 KHz?) | ||
| 139 | * | ||
| 140 | * Setting this to 0x0000 is a good way to | ||
| 141 | * kill all DMA at boot time so that the | ||
| 142 | * PSC won't overwrite the kernel image | ||
| 143 | * with sound data. | ||
| 144 | */ | ||
| 145 | |||
| 146 | /* | ||
| 147 | * 0x0202 - 0x0203 is unused. Writing there | ||
| 148 | * seems to clobber the control register. | ||
| 149 | */ | ||
| 150 | |||
| 151 | #define PSC_SND_SOURCE 0x204 /* | ||
| 152 | * [ 32-bit ] | ||
| 153 | * Controls input source and volume: | ||
| 154 | * | ||
| 155 | * bits 12-15 : input source volume, 0 - F | ||
| 156 | * bits 16-19 : unknown, always 0x5 | ||
| 157 | * bits 20-23 : input source selection: | ||
| 158 | * 0x3 = CD Audio | ||
| 159 | * 0x4 = External Audio | ||
| 160 | * | ||
| 161 | * The volume is definitely not the general | ||
| 162 | * output volume as it doesn't affect the | ||
| 163 | * alert sound volume. | ||
| 164 | */ | ||
| 165 | #define PSC_SND_STATUS1 0x208 /* | ||
| 166 | * [ 32-bit ] | ||
| 167 | * Appears to be a read-only status register. | ||
| 168 | * The usual value is 0x00400002. | ||
| 169 | */ | ||
| 170 | #define PSC_SND_HUH3 0x20C /* | ||
| 171 | * [ 16-bit ] | ||
| 172 | * Unknown 16-bit value, always 0x0000. | ||
| 173 | */ | ||
| 174 | #define PSC_SND_BITS2GO 0x20E /* | ||
| 175 | * [ 16-bit ] | ||
| 176 | * Counts down to zero from some constant | ||
| 177 | * value. The value appears to be the | ||
| 178 | * number of _bits_ remaining before the | ||
| 179 | * buffer is full, which would make sense | ||
| 180 | * since Apple's docs say the sound DMA | ||
| 181 | * channels are 1 bit wide. | ||
| 182 | */ | ||
| 183 | #define PSC_SND_INADDR 0x210 /* | ||
| 184 | * [ 32-bit ] | ||
| 185 | * Address of the sound input DMA buffer | ||
| 186 | */ | ||
| 187 | #define PSC_SND_OUTADDR 0x214 /* | ||
| 188 | * [ 32-bit ] | ||
| 189 | * Address of the sound output DMA buffer | ||
| 190 | */ | ||
| 191 | #define PSC_SND_LEN 0x218 /* | ||
| 192 | * [ 16-bit ] | ||
| 193 | * Length of both buffers in eight-byte units. | ||
| 194 | */ | ||
| 195 | #define PSC_SND_HUH4 0x21A /* | ||
| 196 | * [ 16-bit ] | ||
| 197 | * Unknown, always 0x0000. | ||
| 198 | */ | ||
| 199 | #define PSC_SND_STATUS2 0x21C /* | ||
| 200 | * [ 16-bit ] | ||
| 201 | * Appears to e a read-only status register. | ||
| 202 | * The usual value is 0x0200. | ||
| 203 | */ | ||
| 204 | #define PSC_SND_HUH5 0x21E /* | ||
| 205 | * [ 16-bit ] | ||
| 206 | * Unknown, always 0x0000. | ||
| 207 | */ | ||
| 208 | |||
| 209 | #ifndef __ASSEMBLY__ | ||
| 210 | |||
| 211 | extern volatile __u8 *psc; | ||
| 212 | extern int psc_present; | ||
| 213 | |||
| 214 | /* | ||
| 215 | * Access functions | ||
| 216 | */ | ||
| 217 | |||
| 218 | static inline void psc_write_byte(int offset, __u8 data) | ||
| 219 | { | ||
| 220 | *((volatile __u8 *)(psc + offset)) = data; | ||
| 221 | } | ||
| 222 | |||
| 223 | static inline void psc_write_word(int offset, __u16 data) | ||
| 224 | { | ||
| 225 | *((volatile __u16 *)(psc + offset)) = data; | ||
| 226 | } | ||
| 227 | |||
| 228 | static inline void psc_write_long(int offset, __u32 data) | ||
| 229 | { | ||
| 230 | *((volatile __u32 *)(psc + offset)) = data; | ||
| 231 | } | ||
| 232 | |||
| 233 | static inline u8 psc_read_byte(int offset) | ||
| 234 | { | ||
| 235 | return *((volatile __u8 *)(psc + offset)); | ||
| 236 | } | ||
| 237 | |||
| 238 | static inline u16 psc_read_word(int offset) | ||
| 239 | { | ||
| 240 | return *((volatile __u16 *)(psc + offset)); | ||
| 241 | } | ||
| 242 | |||
| 243 | static inline u32 psc_read_long(int offset) | ||
| 244 | { | ||
| 245 | return *((volatile __u32 *)(psc + offset)); | ||
| 246 | } | ||
| 247 | |||
| 248 | #endif /* __ASSEMBLY__ */ | ||
diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h new file mode 100644 index 000000000000..39afb438b656 --- /dev/null +++ b/arch/m68k/include/asm/mac_via.h | |||
| @@ -0,0 +1,267 @@ | |||
| 1 | /* | ||
| 2 | * 6522 Versatile Interface Adapter (VIA) | ||
| 3 | * | ||
| 4 | * There are two of these on the Mac II. Some IRQ's are vectored | ||
| 5 | * via them as are assorted bits and bobs - eg rtc, adb. The picture | ||
| 6 | * is a bit incomplete as the Mac documentation doesn't cover this well | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _ASM_MAC_VIA_H_ | ||
| 10 | #define _ASM_MAC_VIA_H_ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Base addresses for the VIAs. There are two in every machine, | ||
| 14 | * although on some machines the second is an RBV or an OSS. | ||
| 15 | * The OSS is different enough that it's handled separately. | ||
| 16 | * | ||
| 17 | * Do not use these values directly; use the via1 and via2 variables | ||
| 18 | * instead (and don't forget to check rbv_present when using via2!) | ||
| 19 | */ | ||
| 20 | |||
| 21 | #define VIA1_BASE (0x50F00000) | ||
| 22 | #define VIA2_BASE (0x50F02000) | ||
| 23 | #define RBV_BASE (0x50F26000) | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Not all of these are true post MacII I think. | ||
| 27 | * CSA: probably the ones CHRP marks as 'unused' change purposes | ||
| 28 | * when the IWM becomes the SWIM. | ||
| 29 | * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html | ||
| 30 | * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf | ||
| 31 | * | ||
| 32 | * also, http://developer.apple.com/technotes/hw/hw_09.html claims the | ||
| 33 | * following changes for IIfx: | ||
| 34 | * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP. | ||
| 35 | * Also, "All of the functionality of VIA2 has been moved to other chips". | ||
| 36 | */ | ||
| 37 | |||
| 38 | #define VIA1A_vSccWrReq 0x80 /* SCC write. (input) | ||
| 39 | * [CHRP] SCC WREQ: Reflects the state of the | ||
| 40 | * Wait/Request pins from the SCC. | ||
| 41 | * [Macintosh Family Hardware] | ||
| 42 | * as CHRP on SE/30,II,IIx,IIcx,IIci. | ||
| 43 | * on IIfx, "0 means an active request" | ||
| 44 | */ | ||
| 45 | #define VIA1A_vRev8 0x40 /* Revision 8 board ??? | ||
| 46 | * [CHRP] En WaitReqB: Lets the WaitReq_L | ||
| 47 | * signal from port B of the SCC appear on | ||
| 48 | * the PA7 input pin. Output. | ||
| 49 | * [Macintosh Family] On the SE/30, this | ||
| 50 | * is the bit to flip screen buffers. | ||
| 51 | * 0=alternate, 1=main. | ||
| 52 | * on II,IIx,IIcx,IIci,IIfx this is a bit | ||
| 53 | * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx | ||
| 54 | */ | ||
| 55 | #define VIA1A_vHeadSel 0x20 /* Head select for IWM. | ||
| 56 | * [CHRP] unused. | ||
| 57 | * [Macintosh Family] "Floppy disk | ||
| 58 | * state-control line SEL" on all but IIfx | ||
| 59 | */ | ||
| 60 | #define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx | ||
| 61 | * this bit enables the "Overlay" address | ||
| 62 | * map in the address decoders as it is on | ||
| 63 | * reset for mapping the ROM over the reset | ||
| 64 | * vector. 1=use overlay map. | ||
| 65 | * On the IIci,IIfx it is another bit of the | ||
| 66 | * CPU ID: 0=normal IIci, 1=IIci with parity | ||
| 67 | * feature or IIfx. | ||
| 68 | * [CHRP] En WaitReqA: Lets the WaitReq_L | ||
| 69 | * signal from port A of the SCC appear | ||
| 70 | * on the PA7 input pin (CHRP). Output. | ||
| 71 | * [MkLinux] "Drive Select" | ||
| 72 | * (with 0x20 being 'disk head select') | ||
| 73 | */ | ||
| 74 | #define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select: | ||
| 75 | * 1: select the external serial clock to | ||
| 76 | * drive the SCC's /RTxCA pin. | ||
| 77 | * 0: Select the 3.6864MHz clock to drive | ||
| 78 | * the SCC cell. | ||
| 79 | * [Macintosh Family] Correct on all but IIfx | ||
| 80 | */ | ||
| 81 | |||
| 82 | /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control | ||
| 83 | * on Macs which had the PWM sound hardware. Reserved on newer models. | ||
| 84 | * On IIci,IIfx, bits 1-2 are the rest of the CPU ID: | ||
| 85 | * bit 2: 1=IIci, 0=IIfx | ||
| 86 | * bit 1: 1 on both IIci and IIfx. | ||
| 87 | * MkLinux sez bit 0 is 'burnin flag' in this case. | ||
| 88 | * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as | ||
| 89 | * inputs, these bits will read 0. | ||
| 90 | */ | ||
| 91 | #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */ | ||
| 92 | #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */ | ||
| 93 | #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ | ||
| 94 | #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ | ||
| 95 | #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ | ||
| 96 | |||
| 97 | /* Info on VIA1B is from Macintosh Family Hardware & MkLinux. | ||
| 98 | * CHRP offers no info. */ | ||
| 99 | #define VIA1B_vSound 0x80 /* Sound enable (for compatibility with | ||
| 100 | * PWM hardware) 0=enabled. | ||
| 101 | * Also, on IIci w/parity, shows parity error | ||
| 102 | * 0=error, 1=OK. */ | ||
| 103 | #define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled | ||
| 104 | * On SE/30, vertical sync interrupt enable. | ||
| 105 | * 0=enabled. This vSync interrupt shows up | ||
| 106 | * as a slot $E interrupt. */ | ||
| 107 | #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */ | ||
| 108 | #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */ | ||
| 109 | #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/ | ||
| 110 | #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */ | ||
| 111 | #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */ | ||
| 112 | #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */ | ||
| 113 | |||
| 114 | /* MkLinux defines the following "VIA1 Register B contents where they | ||
| 115 | * differ from standard VIA1". From the naming scheme, we assume they | ||
| 116 | * correspond to a VIA work-alike named 'EVR'. */ | ||
| 117 | #define EVRB_XCVR 0x08 /* XCVR_SESSION* */ | ||
| 118 | #define EVRB_FULL 0x10 /* VIA_FULL */ | ||
| 119 | #define EVRB_SYSES 0x20 /* SYS_SESSION */ | ||
| 120 | #define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */ | ||
| 121 | #define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */ | ||
| 122 | #define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */ | ||
| 123 | #define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */ | ||
| 124 | |||
| 125 | /* | ||
| 126 | * VIA2 A register is the interrupt lines raised off the nubus | ||
| 127 | * slots. | ||
| 128 | * The below info is from 'Macintosh Family Hardware.' | ||
| 129 | * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.' | ||
| 130 | * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and | ||
| 131 | * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike. | ||
| 132 | * Perhaps OSS uses vRAM1 and vRAM2 for ADB. | ||
| 133 | */ | ||
| 134 | |||
| 135 | #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */ | ||
| 136 | #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */ | ||
| 137 | #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */ | ||
| 138 | #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */ | ||
| 139 | #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */ | ||
| 140 | #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */ | ||
| 141 | #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */ | ||
| 142 | #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */ | ||
| 143 | |||
| 144 | /* RAM size bits decoded as follows: | ||
| 145 | * bit1 bit0 size of ICs in bank A | ||
| 146 | * 0 0 256 kbit | ||
| 147 | * 0 1 1 Mbit | ||
| 148 | * 1 0 4 Mbit | ||
| 149 | * 1 1 16 Mbit | ||
| 150 | */ | ||
| 151 | |||
| 152 | /* | ||
| 153 | * Register B has the fun stuff in it | ||
| 154 | */ | ||
| 155 | |||
| 156 | #define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by | ||
| 157 | * timer T1. | ||
| 158 | * on IIci, parity test: 0=test mode. | ||
| 159 | * [MkLinux] RBV_PARODD: 1=odd,0=even. */ | ||
| 160 | #define VIA2B_vSndJck 0x40 /* External sound jack status. | ||
| 161 | * 0=plug is inserted. On SE/30, always 0 */ | ||
| 162 | #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */ | ||
| 163 | #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */ | ||
| 164 | #define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush | ||
| 165 | * on II, AMU/PMMU control. | ||
| 166 | * if AMU, 0=24bit to 32bit translation | ||
| 167 | * if PMMU, 1=PMMU is accessing page table. | ||
| 168 | * on SE/30 tied low. | ||
| 169 | * on IIx,IIcx,IIfx, unused. | ||
| 170 | * on IIci/RBV, cache control. 0=flush cache. | ||
| 171 | */ | ||
| 172 | #define VIA2B_vPower 0x04 /* Power off, 0=shut off power. | ||
| 173 | * on SE/30 this signal sent to PDS card. */ | ||
| 174 | #define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked. | ||
| 175 | * on SE/30 sent to PDS card. */ | ||
| 176 | #define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card | ||
| 177 | * on others, 0=disable processor's instruction | ||
| 178 | * and data caches. */ | ||
| 179 | |||
| 180 | /* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html | ||
| 181 | * Another example of a valid function that has no ROM support is the use | ||
| 182 | * of the alternate video page for page-flipping animation. Since there | ||
| 183 | * is no ROM call to flip pages, it is necessary to go play with the | ||
| 184 | * right bit in the VIA chip (6522 Versatile Interface Adapter). | ||
| 185 | * [CSA: don't know which one this is, but it's one of 'em!] | ||
| 186 | */ | ||
| 187 | |||
| 188 | /* | ||
| 189 | * 6522 registers - see databook. | ||
| 190 | * CSA: Assignments for VIA1 confirmed from CHRP spec. | ||
| 191 | */ | ||
| 192 | |||
| 193 | /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */ | ||
| 194 | /* Note: 15 VIA regs, 8 RBV regs */ | ||
| 195 | |||
| 196 | #define vBufB 0x0000 /* [VIA/RBV] Register B */ | ||
| 197 | #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */ | ||
| 198 | #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */ | ||
| 199 | #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */ | ||
| 200 | #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */ | ||
| 201 | #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */ | ||
| 202 | #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */ | ||
| 203 | #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */ | ||
| 204 | #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ | ||
| 205 | #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ | ||
| 206 | #define vSR 0x1400 /* [VIA only] Shift register. */ | ||
| 207 | #define vACR 0x1600 /* [VIA only] Auxilary control register. */ | ||
| 208 | #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ | ||
| 209 | /* CHRP sez never ever to *write* this. | ||
| 210 | * Mac family says never to *change* this. | ||
| 211 | * In fact we need to initialize it once at start. */ | ||
| 212 | #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */ | ||
| 213 | #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */ | ||
| 214 | #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */ | ||
| 215 | |||
| 216 | /* The RBV only decodes the bottom eight address lines; the VIA doesn't | ||
| 217 | * decode the bottom eight -- so vBufB | rBufB will always get you BufB */ | ||
| 218 | /* CSA: in fact, only bits 0,1, and 4 seem to be decoded. | ||
| 219 | * BUT note the values for rIER and rIFR, where the top 8 bits *do* seem | ||
| 220 | * to matter. In fact *all* of the top 8 bits seem to matter; | ||
| 221 | * setting rIER=0x1813 and rIFR=0x1803 doesn't work, either. | ||
| 222 | * Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999] | ||
| 223 | */ | ||
| 224 | |||
| 225 | #define rBufB 0x0000 /* [VIA/RBV] Register B */ | ||
| 226 | #define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */ | ||
| 227 | #define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */ | ||
| 228 | #define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */ | ||
| 229 | #define rMonP 0x0010 /* [RBV only] RBV video monitor type. */ | ||
| 230 | #define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */ | ||
| 231 | #define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */ | ||
| 232 | #define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */ | ||
| 233 | #define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */ | ||
| 234 | |||
| 235 | /* | ||
| 236 | * Video monitor parameters, for rMonP: | ||
| 237 | */ | ||
| 238 | #define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */ | ||
| 239 | #define RBV_MONID 0x38 /* monitor type, as below. */ | ||
| 240 | #define RBV_VIDOFF 0x40 /* 1 turns off onboard video */ | ||
| 241 | /* Supported monitor types: */ | ||
| 242 | #define MON_15BW (1<<3) /* 15" BW portrait. */ | ||
| 243 | #define MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */ | ||
| 244 | #define MON_15RGB (5<<3) /* 15" RGB portrait. */ | ||
| 245 | #define MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */ | ||
| 246 | #define MON_NONE (7<<3) /* No monitor attached. */ | ||
| 247 | |||
| 248 | /* To clarify IER manipulations */ | ||
| 249 | #define IER_SET_BIT(b) (0x80 | (1<<(b)) ) | ||
| 250 | #define IER_CLR_BIT(b) (0x7F & (1<<(b)) ) | ||
| 251 | |||
| 252 | #ifndef __ASSEMBLY__ | ||
| 253 | |||
| 254 | extern volatile __u8 *via1,*via2; | ||
| 255 | extern int rbv_present,via_alt_mapping; | ||
| 256 | |||
| 257 | static inline int rbv_set_video_bpp(int bpp) | ||
| 258 | { | ||
| 259 | char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1; | ||
| 260 | if (!rbv_present || val<0) return -1; | ||
| 261 | via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val; | ||
| 262 | return 0; | ||
| 263 | } | ||
| 264 | |||
| 265 | #endif /* __ASSEMBLY__ */ | ||
| 266 | |||
| 267 | #endif /* _ASM_MAC_VIA_H_ */ | ||
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h new file mode 100644 index 000000000000..fc24b6fc5508 --- /dev/null +++ b/arch/m68k/include/asm/machdep.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "machdep_no.h" | ||
| 3 | #else | ||
| 4 | #include "machdep_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/machdep_mm.h b/arch/m68k/include/asm/machdep_mm.h new file mode 100644 index 000000000000..5637dcef314e --- /dev/null +++ b/arch/m68k/include/asm/machdep_mm.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | #ifndef _M68K_MACHDEP_H | ||
| 2 | #define _M68K_MACHDEP_H | ||
| 3 | |||
| 4 | #include <linux/seq_file.h> | ||
| 5 | #include <linux/interrupt.h> | ||
| 6 | |||
| 7 | struct pt_regs; | ||
| 8 | struct mktime; | ||
| 9 | struct rtc_time; | ||
| 10 | struct rtc_pll_info; | ||
| 11 | struct buffer_head; | ||
| 12 | |||
| 13 | extern void (*mach_sched_init) (irq_handler_t handler); | ||
| 14 | /* machine dependent irq functions */ | ||
| 15 | extern void (*mach_init_IRQ) (void); | ||
| 16 | extern void (*mach_get_model) (char *model); | ||
| 17 | extern void (*mach_get_hardware_list) (struct seq_file *m); | ||
| 18 | /* machine dependent timer functions */ | ||
| 19 | extern unsigned long (*mach_gettimeoffset)(void); | ||
| 20 | extern int (*mach_hwclk)(int, struct rtc_time*); | ||
| 21 | extern unsigned int (*mach_get_ss)(void); | ||
| 22 | extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); | ||
| 23 | extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); | ||
| 24 | extern int (*mach_set_clock_mmss)(unsigned long); | ||
| 25 | extern void (*mach_reset)( void ); | ||
| 26 | extern void (*mach_halt)( void ); | ||
| 27 | extern void (*mach_power_off)( void ); | ||
| 28 | extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); | ||
| 29 | extern void (*mach_hd_setup)(char *, int *); | ||
| 30 | extern long mach_max_dma_address; | ||
| 31 | extern void (*mach_heartbeat) (int); | ||
| 32 | extern void (*mach_l2_flush) (int); | ||
| 33 | extern void (*mach_beep) (unsigned int, unsigned int); | ||
| 34 | |||
| 35 | #endif /* _M68K_MACHDEP_H */ | ||
diff --git a/arch/m68k/include/asm/machdep_no.h b/arch/m68k/include/asm/machdep_no.h new file mode 100644 index 000000000000..de9f47a51cc2 --- /dev/null +++ b/arch/m68k/include/asm/machdep_no.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | #ifndef _M68KNOMMU_MACHDEP_H | ||
| 2 | #define _M68KNOMMU_MACHDEP_H | ||
| 3 | |||
| 4 | #include <linux/interrupt.h> | ||
| 5 | |||
| 6 | /* Hardware clock functions */ | ||
| 7 | extern void hw_timer_init(void); | ||
| 8 | extern unsigned long hw_timer_offset(void); | ||
| 9 | |||
| 10 | extern irqreturn_t arch_timer_interrupt(int irq, void *dummy); | ||
| 11 | |||
| 12 | /* Machine dependent time handling */ | ||
| 13 | extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour, | ||
| 14 | int *min, int *sec); | ||
| 15 | extern int (*mach_set_clock_mmss)(unsigned long); | ||
| 16 | |||
| 17 | /* machine dependent power off functions */ | ||
| 18 | extern void (*mach_reset)( void ); | ||
| 19 | extern void (*mach_halt)( void ); | ||
| 20 | extern void (*mach_power_off)( void ); | ||
| 21 | |||
| 22 | extern void config_BSP(char *command, int len); | ||
| 23 | |||
| 24 | extern void do_IRQ(int irq, struct pt_regs *fp); | ||
| 25 | |||
| 26 | #endif /* _M68KNOMMU_MACHDEP_H */ | ||
diff --git a/arch/m68k/include/asm/machines.h b/arch/m68k/include/asm/machines.h new file mode 100644 index 000000000000..be667e84f01b --- /dev/null +++ b/arch/m68k/include/asm/machines.h | |||
| @@ -0,0 +1,85 @@ | |||
| 1 | /* | ||
| 2 | * machines.h: Defines for taking apart the machine type value in the | ||
| 3 | * idprom and determining the kind of machine we are on. | ||
| 4 | * | ||
| 5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
| 6 | * Sun3/3x models added by David Monro (davidm@psrg.cs.usyd.edu.au) | ||
| 7 | */ | ||
| 8 | #ifndef _SPARC_MACHINES_H | ||
| 9 | #define _SPARC_MACHINES_H | ||
| 10 | |||
| 11 | struct Sun_Machine_Models { | ||
| 12 | char *name; | ||
| 13 | unsigned char id_machtype; | ||
| 14 | }; | ||
| 15 | |||
| 16 | /* Current number of machines we know about that has an IDPROM | ||
| 17 | * machtype entry including one entry for the 0x80 OBP machines. | ||
| 18 | */ | ||
| 19 | // reduced along with table in arch/m68k/sun3/idprom.c | ||
| 20 | // sun3 port doesn't need to know about sparc machines. | ||
| 21 | //#define NUM_SUN_MACHINES 23 | ||
| 22 | #define NUM_SUN_MACHINES 8 | ||
| 23 | |||
| 24 | /* The machine type in the idprom area looks like this: | ||
| 25 | * | ||
| 26 | * --------------- | ||
| 27 | * | ARCH | MACH | | ||
| 28 | * --------------- | ||
| 29 | * 7 4 3 0 | ||
| 30 | * | ||
| 31 | * The ARCH field determines the architecture line (sun4, sun4c, etc). | ||
| 32 | * The MACH field determines the machine make within that architecture. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #define SM_ARCH_MASK 0xf0 | ||
| 36 | #define SM_SUN3 0x10 | ||
| 37 | #define SM_SUN4 0x20 | ||
| 38 | #define SM_SUN3X 0x40 | ||
| 39 | #define SM_SUN4C 0x50 | ||
| 40 | #define SM_SUN4M 0x70 | ||
| 41 | #define SM_SUN4M_OBP 0x80 | ||
| 42 | |||
| 43 | #define SM_TYP_MASK 0x0f | ||
| 44 | /* Sun3 machines */ | ||
| 45 | #define SM_3_160 0x01 /* Sun 3/160 series */ | ||
| 46 | #define SM_3_50 0x02 /* Sun 3/50 series */ | ||
| 47 | #define SM_3_260 0x03 /* Sun 3/260 series */ | ||
| 48 | #define SM_3_110 0x04 /* Sun 3/110 series */ | ||
| 49 | #define SM_3_60 0x07 /* Sun 3/60 series */ | ||
| 50 | #define SM_3_E 0x08 /* Sun 3/E series */ | ||
| 51 | |||
| 52 | /* Sun3x machines */ | ||
| 53 | #define SM_3_460 0x01 /* Sun 3/460 (460,470,480) series */ | ||
| 54 | #define SM_3_80 0x02 /* Sun 3/80 series */ | ||
| 55 | |||
| 56 | /* Sun4 machines */ | ||
| 57 | #define SM_4_260 0x01 /* Sun 4/200 series */ | ||
| 58 | #define SM_4_110 0x02 /* Sun 4/100 series */ | ||
| 59 | #define SM_4_330 0x03 /* Sun 4/300 series */ | ||
| 60 | #define SM_4_470 0x04 /* Sun 4/400 series */ | ||
| 61 | |||
| 62 | /* Sun4c machines Full Name - PROM NAME */ | ||
| 63 | #define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */ | ||
| 64 | #define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */ | ||
| 65 | #define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */ | ||
| 66 | #define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */ | ||
| 67 | #define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */ | ||
| 68 | #define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */ | ||
| 69 | #define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */ | ||
| 70 | |||
| 71 | /* Sun4m machines, these predate the OpenBoot. These values only mean | ||
| 72 | * something if the value in the ARCH field is SM_SUN4M, if it is | ||
| 73 | * SM_SUN4M_OBP then you have the following situation: | ||
| 74 | * 1) You either have a sun4d, a sun4e, or a recently made sun4m. | ||
| 75 | * 2) You have to consult OpenBoot to determine which machine this is. | ||
| 76 | */ | ||
| 77 | #define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */ | ||
| 78 | #define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */ | ||
| 79 | #define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */ | ||
| 80 | |||
| 81 | /* Sun4d machines -- N/A */ | ||
| 82 | /* Sun4e machines -- N/A */ | ||
| 83 | /* Sun4u machines -- N/A */ | ||
| 84 | |||
| 85 | #endif /* !(_SPARC_MACHINES_H) */ | ||
diff --git a/arch/m68k/include/asm/machw.h b/arch/m68k/include/asm/machw.h new file mode 100644 index 000000000000..2b4de0c2ce4a --- /dev/null +++ b/arch/m68k/include/asm/machw.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | ** linux/machw.h -- This header defines some macros and pointers for | ||
| 3 | ** the various Macintosh custom hardware registers. | ||
| 4 | ** | ||
| 5 | ** Copyright 1997 by Michael Schmitz | ||
| 6 | ** | ||
| 7 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 8 | ** License. See the file COPYING in the main directory of this archive | ||
| 9 | ** for more details. | ||
| 10 | ** | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _ASM_MACHW_H_ | ||
| 14 | #define _ASM_MACHW_H_ | ||
| 15 | |||
| 16 | /* | ||
| 17 | * head.S maps the videomem to VIDEOMEMBASE | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define VIDEOMEMBASE 0xf0000000 | ||
| 21 | #define VIDEOMEMSIZE (4096*1024) | ||
| 22 | #define VIDEOMEMMASK (-4096*1024) | ||
| 23 | |||
| 24 | #ifndef __ASSEMBLY__ | ||
| 25 | |||
| 26 | #include <linux/types.h> | ||
| 27 | |||
| 28 | #if 0 | ||
| 29 | /* | ||
| 30 | ** SCC Z8530 | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define MAC_SCC_BAS (0x50F04000) | ||
| 34 | struct MAC_SCC | ||
| 35 | { | ||
| 36 | u_char cha_a_ctrl; | ||
| 37 | u_char char_dummy1; | ||
| 38 | u_char cha_a_data; | ||
| 39 | u_char char_dummy2; | ||
| 40 | u_char cha_b_ctrl; | ||
| 41 | u_char char_dummy3; | ||
| 42 | u_char cha_b_data; | ||
| 43 | }; | ||
| 44 | # define mac_scc ((*(volatile struct SCC*)MAC_SCC_BAS)) | ||
| 45 | #endif | ||
| 46 | |||
| 47 | #endif /* __ASSEMBLY__ */ | ||
| 48 | |||
| 49 | #endif /* linux/machw.h */ | ||
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h new file mode 100644 index 000000000000..05309f7e3d06 --- /dev/null +++ b/arch/m68k/include/asm/macintosh.h | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | #ifndef __ASM_MACINTOSH_H | ||
| 2 | #define __ASM_MACINTOSH_H | ||
| 3 | |||
| 4 | #include <linux/seq_file.h> | ||
| 5 | #include <linux/interrupt.h> | ||
| 6 | |||
| 7 | /* | ||
| 8 | * Apple Macintoshisms | ||
| 9 | */ | ||
| 10 | |||
| 11 | extern void mac_reset(void); | ||
| 12 | extern void mac_poweroff(void); | ||
| 13 | extern void mac_init_IRQ(void); | ||
| 14 | extern int mac_irq_pending(unsigned int); | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Floppy driver magic hook - probably shouldnt be here | ||
| 18 | */ | ||
| 19 | |||
| 20 | extern void via1_set_head(int); | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Macintosh Table | ||
| 24 | */ | ||
| 25 | |||
| 26 | struct mac_model | ||
| 27 | { | ||
| 28 | short ident; | ||
| 29 | char *name; | ||
| 30 | char adb_type; | ||
| 31 | char via_type; | ||
| 32 | char scsi_type; | ||
| 33 | char ide_type; | ||
| 34 | char scc_type; | ||
| 35 | char ether_type; | ||
| 36 | char nubus_type; | ||
| 37 | }; | ||
| 38 | |||
| 39 | #define MAC_ADB_NONE 0 | ||
| 40 | #define MAC_ADB_II 1 | ||
| 41 | #define MAC_ADB_IISI 2 | ||
| 42 | #define MAC_ADB_CUDA 3 | ||
| 43 | #define MAC_ADB_PB1 4 | ||
| 44 | #define MAC_ADB_PB2 5 | ||
| 45 | #define MAC_ADB_IOP 6 | ||
| 46 | |||
| 47 | #define MAC_VIA_II 1 | ||
| 48 | #define MAC_VIA_IIci 2 | ||
| 49 | #define MAC_VIA_QUADRA 3 | ||
| 50 | |||
| 51 | #define MAC_SCSI_NONE 0 | ||
| 52 | #define MAC_SCSI_OLD 1 | ||
| 53 | #define MAC_SCSI_QUADRA 2 | ||
| 54 | #define MAC_SCSI_QUADRA2 3 | ||
| 55 | #define MAC_SCSI_QUADRA3 4 | ||
| 56 | |||
| 57 | #define MAC_IDE_NONE 0 | ||
| 58 | #define MAC_IDE_QUADRA 1 | ||
| 59 | #define MAC_IDE_PB 2 | ||
| 60 | #define MAC_IDE_BABOON 3 | ||
| 61 | |||
| 62 | #define MAC_SCC_II 1 | ||
| 63 | #define MAC_SCC_IOP 2 | ||
| 64 | #define MAC_SCC_QUADRA 3 | ||
| 65 | #define MAC_SCC_PSC 4 | ||
| 66 | |||
| 67 | #define MAC_ETHER_NONE 0 | ||
| 68 | #define MAC_ETHER_SONIC 1 | ||
| 69 | #define MAC_ETHER_MACE 2 | ||
| 70 | |||
| 71 | #define MAC_NO_NUBUS 0 | ||
| 72 | #define MAC_NUBUS 1 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Gestalt numbers | ||
| 76 | */ | ||
| 77 | |||
| 78 | #define MAC_MODEL_II 6 | ||
| 79 | #define MAC_MODEL_IIX 7 | ||
| 80 | #define MAC_MODEL_IICX 8 | ||
| 81 | #define MAC_MODEL_SE30 9 | ||
| 82 | #define MAC_MODEL_IICI 11 | ||
| 83 | #define MAC_MODEL_IIFX 13 /* And well numbered it is too */ | ||
| 84 | #define MAC_MODEL_IISI 18 | ||
| 85 | #define MAC_MODEL_LC 19 | ||
| 86 | #define MAC_MODEL_Q900 20 | ||
| 87 | #define MAC_MODEL_PB170 21 | ||
| 88 | #define MAC_MODEL_Q700 22 | ||
| 89 | #define MAC_MODEL_CLII 23 /* aka: P200 */ | ||
| 90 | #define MAC_MODEL_PB140 25 | ||
| 91 | #define MAC_MODEL_Q950 26 /* aka: WGS95 */ | ||
| 92 | #define MAC_MODEL_LCIII 27 /* aka: P450 */ | ||
| 93 | #define MAC_MODEL_PB210 29 | ||
| 94 | #define MAC_MODEL_C650 30 | ||
| 95 | #define MAC_MODEL_PB230 32 | ||
| 96 | #define MAC_MODEL_PB180 33 | ||
| 97 | #define MAC_MODEL_PB160 34 | ||
| 98 | #define MAC_MODEL_Q800 35 /* aka: WGS80 */ | ||
| 99 | #define MAC_MODEL_Q650 36 | ||
| 100 | #define MAC_MODEL_LCII 37 /* aka: P400/405/410/430 */ | ||
| 101 | #define MAC_MODEL_PB250 38 | ||
| 102 | #define MAC_MODEL_IIVI 44 | ||
| 103 | #define MAC_MODEL_P600 45 /* aka: P600CD */ | ||
| 104 | #define MAC_MODEL_IIVX 48 | ||
| 105 | #define MAC_MODEL_CCL 49 /* aka: P250 */ | ||
| 106 | #define MAC_MODEL_PB165C 50 | ||
| 107 | #define MAC_MODEL_C610 52 /* aka: WGS60 */ | ||
| 108 | #define MAC_MODEL_Q610 53 | ||
| 109 | #define MAC_MODEL_PB145 54 /* aka: PB145B */ | ||
| 110 | #define MAC_MODEL_P520 56 /* aka: LC520 */ | ||
| 111 | #define MAC_MODEL_C660 60 | ||
| 112 | #define MAC_MODEL_P460 62 /* aka: LCIII+, P466/P467 */ | ||
| 113 | #define MAC_MODEL_PB180C 71 | ||
| 114 | #define MAC_MODEL_PB520 72 /* aka: PB520C, PB540, PB540C, PB550C */ | ||
| 115 | #define MAC_MODEL_PB270C 77 | ||
| 116 | #define MAC_MODEL_Q840 78 | ||
| 117 | #define MAC_MODEL_P550 80 /* aka: LC550, P560 */ | ||
| 118 | #define MAC_MODEL_CCLII 83 /* aka: P275 */ | ||
| 119 | #define MAC_MODEL_PB165 84 | ||
| 120 | #define MAC_MODEL_PB190 85 /* aka: PB190CS */ | ||
| 121 | #define MAC_MODEL_TV 88 | ||
| 122 | #define MAC_MODEL_P475 89 /* aka: LC475, P476 */ | ||
| 123 | #define MAC_MODEL_P475F 90 /* aka: P475 w/ FPU (no LC040) */ | ||
| 124 | #define MAC_MODEL_P575 92 /* aka: LC575, P577/P578 */ | ||
| 125 | #define MAC_MODEL_Q605 94 | ||
| 126 | #define MAC_MODEL_Q605_ACC 95 /* Q605 accelerated to 33 MHz */ | ||
| 127 | #define MAC_MODEL_Q630 98 /* aka: LC630, P630/631/635/636/637/638/640 */ | ||
| 128 | #define MAC_MODEL_P588 99 /* aka: LC580, P580 */ | ||
| 129 | #define MAC_MODEL_PB280 102 | ||
| 130 | #define MAC_MODEL_PB280C 103 | ||
| 131 | #define MAC_MODEL_PB150 115 | ||
| 132 | |||
| 133 | extern struct mac_model *macintosh_config; | ||
| 134 | |||
| 135 | #endif | ||
diff --git a/arch/m68k/include/asm/macints.h b/arch/m68k/include/asm/macints.h new file mode 100644 index 000000000000..679c48ab4407 --- /dev/null +++ b/arch/m68k/include/asm/macints.h | |||
| @@ -0,0 +1,155 @@ | |||
| 1 | /* | ||
| 2 | ** macints.h -- Macintosh Linux interrupt handling structs and prototypes | ||
| 3 | ** | ||
| 4 | ** Copyright 1997 by Michael Schmitz | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _ASM_MACINTS_H_ | ||
| 13 | #define _ASM_MACINTS_H_ | ||
| 14 | |||
| 15 | #include <asm/irq.h> | ||
| 16 | |||
| 17 | /* Setting this prints debugging info for unclaimed interrupts */ | ||
| 18 | |||
| 19 | #define DEBUG_SPURIOUS | ||
| 20 | |||
| 21 | /* Setting this prints debugging info on each autovector interrupt */ | ||
| 22 | |||
| 23 | /* #define DEBUG_IRQS */ | ||
| 24 | |||
| 25 | /* Setting this prints debugging info on each Nubus interrupt */ | ||
| 26 | |||
| 27 | /* #define DEBUG_NUBUS_INT */ | ||
| 28 | |||
| 29 | /* Setting this prints debugging info on irqs as they enabled and disabled. */ | ||
| 30 | |||
| 31 | /* #define DEBUG_IRQUSE */ | ||
| 32 | |||
| 33 | /* | ||
| 34 | * Base IRQ number for all Mac68K interrupt sources. Each source | ||
| 35 | * has eight indexes (base -> base+7). | ||
| 36 | */ | ||
| 37 | |||
| 38 | #define VIA1_SOURCE_BASE 8 | ||
| 39 | #define VIA2_SOURCE_BASE 16 | ||
| 40 | #define MAC_SCC_SOURCE_BASE 24 | ||
| 41 | #define PSC3_SOURCE_BASE 24 | ||
| 42 | #define PSC4_SOURCE_BASE 32 | ||
| 43 | #define PSC5_SOURCE_BASE 40 | ||
| 44 | #define PSC6_SOURCE_BASE 48 | ||
| 45 | #define NUBUS_SOURCE_BASE 56 | ||
| 46 | #define BABOON_SOURCE_BASE 64 | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Maximum IRQ number is BABOON_SOURCE_BASE + 7, | ||
| 50 | * giving us IRQs up through 71 | ||
| 51 | */ | ||
| 52 | |||
| 53 | #define NUM_MAC_SOURCES 72 | ||
| 54 | |||
| 55 | /* | ||
| 56 | * clean way to separate IRQ into its source and index | ||
| 57 | */ | ||
| 58 | |||
| 59 | #define IRQ_SRC(irq) (irq >> 3) | ||
| 60 | #define IRQ_IDX(irq) (irq & 7) | ||
| 61 | |||
| 62 | /* VIA1 interrupts */ | ||
| 63 | #define IRQ_VIA1_0 (8) /* one second int. */ | ||
| 64 | #define IRQ_VIA1_1 (9) /* VBlank int. */ | ||
| 65 | #define IRQ_MAC_VBL IRQ_VIA1_1 | ||
| 66 | #define IRQ_VIA1_2 (10) /* ADB SR shifts complete */ | ||
| 67 | #define IRQ_MAC_ADB IRQ_VIA1_2 | ||
| 68 | #define IRQ_MAC_ADB_SR IRQ_VIA1_2 | ||
| 69 | #define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */ | ||
| 70 | #define IRQ_MAC_ADB_SD IRQ_VIA1_3 | ||
| 71 | #define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */ | ||
| 72 | #define IRQ_MAC_ADB_CL IRQ_VIA1_4 | ||
| 73 | #define IRQ_VIA1_5 (13) | ||
| 74 | #define IRQ_MAC_TIMER_2 IRQ_VIA1_5 | ||
| 75 | #define IRQ_VIA1_6 (14) | ||
| 76 | #define IRQ_MAC_TIMER_1 IRQ_VIA1_6 | ||
| 77 | #define IRQ_VIA1_7 (15) | ||
| 78 | |||
| 79 | /* VIA2/RBV interrupts */ | ||
| 80 | #define IRQ_VIA2_0 (16) | ||
| 81 | #define IRQ_MAC_SCSIDRQ IRQ_VIA2_0 | ||
| 82 | #define IRQ_VIA2_1 (17) | ||
| 83 | #define IRQ_MAC_NUBUS IRQ_VIA2_1 | ||
| 84 | #define IRQ_VIA2_2 (18) | ||
| 85 | #define IRQ_VIA2_3 (19) | ||
| 86 | #define IRQ_MAC_SCSI IRQ_VIA2_3 | ||
| 87 | #define IRQ_VIA2_4 (20) | ||
| 88 | #define IRQ_VIA2_5 (21) | ||
| 89 | #define IRQ_VIA2_6 (22) | ||
| 90 | #define IRQ_VIA2_7 (23) | ||
| 91 | |||
| 92 | /* Level 3 (PSC, AV Macs only) interrupts */ | ||
| 93 | #define IRQ_PSC3_0 (24) | ||
| 94 | #define IRQ_MAC_MACE IRQ_PSC3_0 | ||
| 95 | #define IRQ_PSC3_1 (25) | ||
| 96 | #define IRQ_PSC3_2 (26) | ||
| 97 | #define IRQ_PSC3_3 (27) | ||
| 98 | |||
| 99 | /* Level 4 (SCC) interrupts */ | ||
| 100 | #define IRQ_SCC (32) | ||
| 101 | #define IRQ_SCCA (33) | ||
| 102 | #define IRQ_SCCB (34) | ||
| 103 | #if 0 /* FIXME: are there multiple interrupt conditions on the SCC ?? */ | ||
| 104 | /* SCC interrupts */ | ||
| 105 | #define IRQ_SCCB_TX (32) | ||
| 106 | #define IRQ_SCCB_STAT (33) | ||
| 107 | #define IRQ_SCCB_RX (34) | ||
| 108 | #define IRQ_SCCB_SPCOND (35) | ||
| 109 | #define IRQ_SCCA_TX (36) | ||
| 110 | #define IRQ_SCCA_STAT (37) | ||
| 111 | #define IRQ_SCCA_RX (38) | ||
| 112 | #define IRQ_SCCA_SPCOND (39) | ||
| 113 | #endif | ||
| 114 | |||
| 115 | /* Level 4 (PSC, AV Macs only) interrupts */ | ||
| 116 | #define IRQ_PSC4_0 (32) | ||
| 117 | #define IRQ_PSC4_1 (33) | ||
| 118 | #define IRQ_PSC4_2 (34) | ||
| 119 | #define IRQ_PSC4_3 (35) | ||
| 120 | #define IRQ_MAC_MACE_DMA IRQ_PSC4_3 | ||
| 121 | |||
| 122 | /* Level 5 (PSC, AV Macs only) interrupts */ | ||
| 123 | #define IRQ_PSC5_0 (40) | ||
| 124 | #define IRQ_PSC5_1 (41) | ||
| 125 | #define IRQ_PSC5_2 (42) | ||
| 126 | #define IRQ_PSC5_3 (43) | ||
| 127 | |||
| 128 | /* Level 6 (PSC, AV Macs only) interrupts */ | ||
| 129 | #define IRQ_PSC6_0 (48) | ||
| 130 | #define IRQ_PSC6_1 (49) | ||
| 131 | #define IRQ_PSC6_2 (50) | ||
| 132 | #define IRQ_PSC6_3 (51) | ||
| 133 | |||
| 134 | /* Nubus interrupts (cascaded to VIA2) */ | ||
| 135 | #define IRQ_NUBUS_9 (56) | ||
| 136 | #define IRQ_NUBUS_A (57) | ||
| 137 | #define IRQ_NUBUS_B (58) | ||
| 138 | #define IRQ_NUBUS_C (59) | ||
| 139 | #define IRQ_NUBUS_D (60) | ||
| 140 | #define IRQ_NUBUS_E (61) | ||
| 141 | #define IRQ_NUBUS_F (62) | ||
| 142 | |||
| 143 | /* Baboon interrupts (cascaded to nubus slot $C) */ | ||
| 144 | #define IRQ_BABOON_0 (64) | ||
| 145 | #define IRQ_BABOON_1 (65) | ||
| 146 | #define IRQ_BABOON_2 (66) | ||
| 147 | #define IRQ_BABOON_3 (67) | ||
| 148 | |||
| 149 | #define SLOT2IRQ(x) (x + 47) | ||
| 150 | #define IRQ2SLOT(x) (x - 47) | ||
| 151 | |||
| 152 | #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */ | ||
| 153 | #define INT_TICKS 246 /* to make sched_time = 99.902... HZ */ | ||
| 154 | |||
| 155 | #endif /* asm/macints.h */ | ||
diff --git a/arch/m68k/include/asm/math-emu.h b/arch/m68k/include/asm/math-emu.h new file mode 100644 index 000000000000..ddfab96403cb --- /dev/null +++ b/arch/m68k/include/asm/math-emu.h | |||
| @@ -0,0 +1,315 @@ | |||
| 1 | #ifndef _ASM_M68K_SETUP_H | ||
| 2 | #define _ASM_M68K_SETUP_H | ||
| 3 | |||
| 4 | #include <asm/setup.h> | ||
| 5 | #include <linux/linkage.h> | ||
| 6 | |||
| 7 | /* Status Register bits */ | ||
| 8 | |||
| 9 | /* accrued exception bits */ | ||
| 10 | #define FPSR_AEXC_INEX 3 | ||
| 11 | #define FPSR_AEXC_DZ 4 | ||
| 12 | #define FPSR_AEXC_UNFL 5 | ||
| 13 | #define FPSR_AEXC_OVFL 6 | ||
| 14 | #define FPSR_AEXC_IOP 7 | ||
| 15 | |||
| 16 | /* exception status bits */ | ||
| 17 | #define FPSR_EXC_INEX1 8 | ||
| 18 | #define FPSR_EXC_INEX2 9 | ||
| 19 | #define FPSR_EXC_DZ 10 | ||
| 20 | #define FPSR_EXC_UNFL 11 | ||
| 21 | #define FPSR_EXC_OVFL 12 | ||
| 22 | #define FPSR_EXC_OPERR 13 | ||
| 23 | #define FPSR_EXC_SNAN 14 | ||
| 24 | #define FPSR_EXC_BSUN 15 | ||
| 25 | |||
| 26 | /* quotient byte, assumes big-endian, of course */ | ||
| 27 | #define FPSR_QUOTIENT(fpsr) (*((signed char *) &(fpsr) + 1)) | ||
| 28 | |||
| 29 | /* condition code bits */ | ||
| 30 | #define FPSR_CC_NAN 24 | ||
| 31 | #define FPSR_CC_INF 25 | ||
| 32 | #define FPSR_CC_Z 26 | ||
| 33 | #define FPSR_CC_NEG 27 | ||
| 34 | |||
| 35 | |||
| 36 | /* Control register bits */ | ||
| 37 | |||
| 38 | /* rounding mode */ | ||
| 39 | #define FPCR_ROUND_RN 0 /* round to nearest/even */ | ||
| 40 | #define FPCR_ROUND_RZ 1 /* round to zero */ | ||
| 41 | #define FPCR_ROUND_RM 2 /* minus infinity */ | ||
| 42 | #define FPCR_ROUND_RP 3 /* plus infinity */ | ||
| 43 | |||
| 44 | /* rounding precision */ | ||
| 45 | #define FPCR_PRECISION_X 0 /* long double */ | ||
| 46 | #define FPCR_PRECISION_S 1 /* double */ | ||
| 47 | #define FPCR_PRECISION_D 2 /* float */ | ||
| 48 | |||
| 49 | |||
| 50 | /* Flags to select the debugging output */ | ||
| 51 | #define PDECODE 0 | ||
| 52 | #define PEXECUTE 1 | ||
| 53 | #define PCONV 2 | ||
| 54 | #define PNORM 3 | ||
| 55 | #define PREGISTER 4 | ||
| 56 | #define PINSTR 5 | ||
| 57 | #define PUNIMPL 6 | ||
| 58 | #define PMOVEM 7 | ||
| 59 | |||
| 60 | #define PMDECODE (1<<PDECODE) | ||
| 61 | #define PMEXECUTE (1<<PEXECUTE) | ||
| 62 | #define PMCONV (1<<PCONV) | ||
| 63 | #define PMNORM (1<<PNORM) | ||
| 64 | #define PMREGISTER (1<<PREGISTER) | ||
| 65 | #define PMINSTR (1<<PINSTR) | ||
| 66 | #define PMUNIMPL (1<<PUNIMPL) | ||
| 67 | #define PMMOVEM (1<<PMOVEM) | ||
| 68 | |||
| 69 | #ifndef __ASSEMBLY__ | ||
| 70 | |||
| 71 | #include <linux/kernel.h> | ||
| 72 | #include <linux/sched.h> | ||
| 73 | |||
| 74 | union fp_mant64 { | ||
| 75 | unsigned long long m64; | ||
| 76 | unsigned long m32[2]; | ||
| 77 | }; | ||
| 78 | |||
| 79 | union fp_mant128 { | ||
| 80 | unsigned long long m64[2]; | ||
| 81 | unsigned long m32[4]; | ||
| 82 | }; | ||
| 83 | |||
| 84 | /* internal representation of extended fp numbers */ | ||
| 85 | struct fp_ext { | ||
| 86 | unsigned char lowmant; | ||
| 87 | unsigned char sign; | ||
| 88 | unsigned short exp; | ||
| 89 | union fp_mant64 mant; | ||
| 90 | }; | ||
| 91 | |||
| 92 | /* C representation of FPU registers */ | ||
| 93 | /* NOTE: if you change this, you have to change the assembler offsets | ||
| 94 | below and the size in <asm/fpu.h>, too */ | ||
| 95 | struct fp_data { | ||
| 96 | struct fp_ext fpreg[8]; | ||
| 97 | unsigned int fpcr; | ||
| 98 | unsigned int fpsr; | ||
| 99 | unsigned int fpiar; | ||
| 100 | unsigned short prec; | ||
| 101 | unsigned short rnd; | ||
| 102 | struct fp_ext temp[2]; | ||
| 103 | }; | ||
| 104 | |||
| 105 | #ifdef FPU_EMU_DEBUG | ||
| 106 | extern unsigned int fp_debugprint; | ||
| 107 | |||
| 108 | #define dprint(bit, fmt, args...) ({ \ | ||
| 109 | if (fp_debugprint & (1 << (bit))) \ | ||
| 110 | printk(fmt, ## args); \ | ||
| 111 | }) | ||
| 112 | #else | ||
| 113 | #define dprint(bit, fmt, args...) | ||
| 114 | #endif | ||
| 115 | |||
| 116 | #define uprint(str) ({ \ | ||
| 117 | static int __count = 3; \ | ||
| 118 | \ | ||
| 119 | if (__count > 0) { \ | ||
| 120 | printk("You just hit an unimplemented " \ | ||
| 121 | "fpu instruction (%s)\n", str); \ | ||
| 122 | printk("Please report this to ....\n"); \ | ||
| 123 | __count--; \ | ||
| 124 | } \ | ||
| 125 | }) | ||
| 126 | |||
| 127 | #define FPDATA ((struct fp_data *)current->thread.fp) | ||
| 128 | |||
| 129 | #else /* __ASSEMBLY__ */ | ||
| 130 | |||
| 131 | #define FPDATA %a2 | ||
| 132 | |||
| 133 | /* offsets from the base register to the floating point data in the task struct */ | ||
| 134 | #define FPD_FPREG (TASK_THREAD+THREAD_FPREG+0) | ||
| 135 | #define FPD_FPCR (TASK_THREAD+THREAD_FPREG+96) | ||
| 136 | #define FPD_FPSR (TASK_THREAD+THREAD_FPREG+100) | ||
| 137 | #define FPD_FPIAR (TASK_THREAD+THREAD_FPREG+104) | ||
| 138 | #define FPD_PREC (TASK_THREAD+THREAD_FPREG+108) | ||
| 139 | #define FPD_RND (TASK_THREAD+THREAD_FPREG+110) | ||
| 140 | #define FPD_TEMPFP1 (TASK_THREAD+THREAD_FPREG+112) | ||
| 141 | #define FPD_TEMPFP2 (TASK_THREAD+THREAD_FPREG+124) | ||
| 142 | #define FPD_SIZEOF (TASK_THREAD+THREAD_FPREG+136) | ||
| 143 | |||
| 144 | /* offsets on the stack to access saved registers, | ||
| 145 | * these are only used during instruction decoding | ||
| 146 | * where we always know how deep we're on the stack. | ||
| 147 | */ | ||
| 148 | #define FPS_DO (PT_D0) | ||
| 149 | #define FPS_D1 (PT_D1) | ||
| 150 | #define FPS_D2 (PT_D2) | ||
| 151 | #define FPS_A0 (PT_A0) | ||
| 152 | #define FPS_A1 (PT_A1) | ||
| 153 | #define FPS_A2 (PT_A2) | ||
| 154 | #define FPS_SR (PT_SR) | ||
| 155 | #define FPS_PC (PT_PC) | ||
| 156 | #define FPS_EA (PT_PC+6) | ||
| 157 | #define FPS_PC2 (PT_PC+10) | ||
| 158 | |||
| 159 | .macro fp_get_fp_reg | ||
| 160 | lea (FPD_FPREG,FPDATA,%d0.w*4),%a0 | ||
| 161 | lea (%a0,%d0.w*8),%a0 | ||
| 162 | .endm | ||
| 163 | |||
| 164 | /* Macros used to get/put the current program counter. | ||
| 165 | * 020/030 use a different stack frame then 040/060, for the | ||
| 166 | * 040/060 the return pc points already to the next location, | ||
| 167 | * so this only needs to be modified for jump instructions. | ||
| 168 | */ | ||
| 169 | .macro fp_get_pc dest | ||
| 170 | move.l (FPS_PC+4,%sp),\dest | ||
| 171 | .endm | ||
| 172 | |||
| 173 | .macro fp_put_pc src,jump=0 | ||
| 174 | move.l \src,(FPS_PC+4,%sp) | ||
| 175 | .endm | ||
| 176 | |||
| 177 | .macro fp_get_instr_data f,s,dest,label | ||
| 178 | getuser \f,%sp@(FPS_PC+4)@(0),\dest,\label,%sp@(FPS_PC+4) | ||
| 179 | addq.l #\s,%sp@(FPS_PC+4) | ||
| 180 | .endm | ||
| 181 | |||
| 182 | .macro fp_get_instr_word dest,label,addr | ||
| 183 | fp_get_instr_data w,2,\dest,\label,\addr | ||
| 184 | .endm | ||
| 185 | |||
| 186 | .macro fp_get_instr_long dest,label,addr | ||
| 187 | fp_get_instr_data l,4,\dest,\label,\addr | ||
| 188 | .endm | ||
| 189 | |||
| 190 | /* These macros are used to read from/write to user space | ||
| 191 | * on error we jump to the fixup section, load the fault | ||
| 192 | * address into %a0 and jump to the exit. | ||
| 193 | * (derived from <asm/uaccess.h>) | ||
| 194 | */ | ||
| 195 | .macro getuser size,src,dest,label,addr | ||
| 196 | | printf ,"[\size<%08x]",1,\addr | ||
| 197 | .Lu1\@: moves\size \src,\dest | ||
| 198 | |||
| 199 | .section .fixup,"ax" | ||
| 200 | .even | ||
| 201 | .Lu2\@: move.l \addr,%a0 | ||
| 202 | jra \label | ||
| 203 | .previous | ||
| 204 | |||
| 205 | .section __ex_table,"a" | ||
| 206 | .align 4 | ||
| 207 | .long .Lu1\@,.Lu2\@ | ||
| 208 | .previous | ||
| 209 | .endm | ||
| 210 | |||
| 211 | .macro putuser size,src,dest,label,addr | ||
| 212 | | printf ,"[\size>%08x]",1,\addr | ||
| 213 | .Lu1\@: moves\size \src,\dest | ||
| 214 | .Lu2\@: | ||
| 215 | |||
| 216 | .section .fixup,"ax" | ||
| 217 | .even | ||
| 218 | .Lu3\@: move.l \addr,%a0 | ||
| 219 | jra \label | ||
| 220 | .previous | ||
| 221 | |||
| 222 | .section __ex_table,"a" | ||
| 223 | .align 4 | ||
| 224 | .long .Lu1\@,.Lu3\@ | ||
| 225 | .long .Lu2\@,.Lu3\@ | ||
| 226 | .previous | ||
| 227 | .endm | ||
| 228 | |||
| 229 | /* work around binutils idiocy */ | ||
| 230 | old_gas=-1 | ||
| 231 | .irp gas_ident.x .x | ||
| 232 | old_gas=old_gas+1 | ||
| 233 | .endr | ||
| 234 | .if !old_gas | ||
| 235 | .irp m b,w,l | ||
| 236 | .macro getuser.\m src,dest,label,addr | ||
| 237 | getuser .\m,\src,\dest,\label,\addr | ||
| 238 | .endm | ||
| 239 | .macro putuser.\m src,dest,label,addr | ||
| 240 | putuser .\m,\src,\dest,\label,\addr | ||
| 241 | .endm | ||
| 242 | .endr | ||
| 243 | .endif | ||
| 244 | |||
| 245 | .macro movestack nr,arg1,arg2,arg3,arg4,arg5 | ||
| 246 | .if \nr | ||
| 247 | movestack (\nr-1),\arg2,\arg3,\arg4,\arg5 | ||
| 248 | move.l \arg1,-(%sp) | ||
| 249 | .endif | ||
| 250 | .endm | ||
| 251 | |||
| 252 | .macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5 | ||
| 253 | #ifdef FPU_EMU_DEBUG | ||
| 254 | .data | ||
| 255 | .Lpdata\@: | ||
| 256 | .string "\string" | ||
| 257 | .previous | ||
| 258 | |||
| 259 | movem.l %d0/%d1/%a0/%a1,-(%sp) | ||
| 260 | .if \bit+1 | ||
| 261 | #if 0 | ||
| 262 | moveq #\bit,%d0 | ||
| 263 | andw #7,%d0 | ||
| 264 | btst %d0,fp_debugprint+((31-\bit)/8) | ||
| 265 | #else | ||
| 266 | btst #\bit,fp_debugprint+((31-\bit)/8) | ||
| 267 | #endif | ||
| 268 | jeq .Lpskip\@ | ||
| 269 | .endif | ||
| 270 | movestack \nr,\arg1,\arg2,\arg3,\arg4,\arg5 | ||
| 271 | pea .Lpdata\@ | ||
| 272 | jsr printk | ||
| 273 | lea ((\nr+1)*4,%sp),%sp | ||
| 274 | .Lpskip\@: | ||
| 275 | movem.l (%sp)+,%d0/%d1/%a0/%a1 | ||
| 276 | #endif | ||
| 277 | .endm | ||
| 278 | |||
| 279 | .macro printx bit,fp | ||
| 280 | #ifdef FPU_EMU_DEBUG | ||
| 281 | movem.l %d0/%a0,-(%sp) | ||
| 282 | lea \fp,%a0 | ||
| 283 | #if 0 | ||
| 284 | moveq #'+',%d0 | ||
| 285 | tst.w (%a0) | ||
| 286 | jeq .Lx1\@ | ||
| 287 | moveq #'-',%d0 | ||
| 288 | .Lx1\@: printf \bit," %c",1,%d0 | ||
| 289 | move.l (4,%a0),%d0 | ||
| 290 | bclr #31,%d0 | ||
| 291 | jne .Lx2\@ | ||
| 292 | printf \bit,"0." | ||
| 293 | jra .Lx3\@ | ||
| 294 | .Lx2\@: printf \bit,"1." | ||
| 295 | .Lx3\@: printf \bit,"%08x%08x",2,%d0,%a0@(8) | ||
| 296 | move.w (2,%a0),%d0 | ||
| 297 | ext.l %d0 | ||
| 298 | printf \bit,"E%04x",1,%d0 | ||
| 299 | #else | ||
| 300 | printf \bit," %08x%08x%08x",3,%a0@,%a0@(4),%a0@(8) | ||
| 301 | #endif | ||
| 302 | movem.l (%sp)+,%d0/%a0 | ||
| 303 | #endif | ||
| 304 | .endm | ||
| 305 | |||
| 306 | .macro debug instr,args | ||
| 307 | #ifdef FPU_EMU_DEBUG | ||
| 308 | \instr \args | ||
| 309 | #endif | ||
| 310 | .endm | ||
| 311 | |||
| 312 | |||
| 313 | #endif /* __ASSEMBLY__ */ | ||
| 314 | |||
| 315 | #endif /* _ASM_M68K_SETUP_H */ | ||
diff --git a/arch/m68k/include/asm/mc146818rtc.h b/arch/m68k/include/asm/mc146818rtc.h new file mode 100644 index 000000000000..fb90dcf78426 --- /dev/null +++ b/arch/m68k/include/asm/mc146818rtc.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "mc146818rtc_no.h" | ||
| 3 | #else | ||
| 4 | #include "mc146818rtc_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/mc146818rtc_mm.h b/arch/m68k/include/asm/mc146818rtc_mm.h new file mode 100644 index 000000000000..9f70a01f73dc --- /dev/null +++ b/arch/m68k/include/asm/mc146818rtc_mm.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Machine dependent access functions for RTC registers. | ||
| 3 | */ | ||
| 4 | #ifndef _ASM_MC146818RTC_H | ||
| 5 | #define _ASM_MC146818RTC_H | ||
| 6 | |||
| 7 | |||
| 8 | #ifdef CONFIG_ATARI | ||
| 9 | /* RTC in Atari machines */ | ||
| 10 | |||
| 11 | #include <asm/atarihw.h> | ||
| 12 | |||
| 13 | #define RTC_PORT(x) (TT_RTC_BAS + 2*(x)) | ||
| 14 | #define RTC_ALWAYS_BCD 0 | ||
| 15 | |||
| 16 | #define CMOS_READ(addr) ({ \ | ||
| 17 | atari_outb_p((addr),RTC_PORT(0)); \ | ||
| 18 | atari_inb_p(RTC_PORT(1)); \ | ||
| 19 | }) | ||
| 20 | #define CMOS_WRITE(val, addr) ({ \ | ||
| 21 | atari_outb_p((addr),RTC_PORT(0)); \ | ||
| 22 | atari_outb_p((val),RTC_PORT(1)); \ | ||
| 23 | }) | ||
| 24 | #endif /* CONFIG_ATARI */ | ||
| 25 | |||
| 26 | #endif /* _ASM_MC146818RTC_H */ | ||
diff --git a/arch/m68k/include/asm/mc146818rtc_no.h b/arch/m68k/include/asm/mc146818rtc_no.h new file mode 100644 index 000000000000..907a0481a140 --- /dev/null +++ b/arch/m68k/include/asm/mc146818rtc_no.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | /* | ||
| 2 | * Machine dependent access functions for RTC registers. | ||
| 3 | */ | ||
| 4 | #ifndef _M68KNOMMU_MC146818RTC_H | ||
| 5 | #define _M68KNOMMU_MC146818RTC_H | ||
| 6 | |||
| 7 | /* empty include file to satisfy the include in genrtc.c/ide-geometry.c */ | ||
| 8 | |||
| 9 | #endif /* _M68KNOMMU_MC146818RTC_H */ | ||
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h new file mode 100644 index 000000000000..c042634fadaa --- /dev/null +++ b/arch/m68k/include/asm/mcfcache.h | |||
| @@ -0,0 +1,150 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfcache.h -- ColdFire CPU cache support code | ||
| 5 | * | ||
| 6 | * (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef __M68KNOMMU_MCFCACHE_H | ||
| 11 | #define __M68KNOMMU_MCFCACHE_H | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * The different ColdFire families have different cache arrangments. | ||
| 17 | * Everything from a small instruction only cache, to configurable | ||
| 18 | * data and/or instruction cache, to unified instruction/data, to | ||
| 19 | * harvard style separate instruction and data caches. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) | ||
| 23 | /* | ||
| 24 | * Simple version 2 core cache. These have instruction cache only, | ||
| 25 | * we just need to invalidate it and enable it. | ||
| 26 | */ | ||
| 27 | .macro CACHE_ENABLE | ||
| 28 | movel #0x01000000,%d0 /* invalidate cache cmd */ | ||
| 29 | movec %d0,%CACR /* do invalidate cache */ | ||
| 30 | movel #0x80000100,%d0 /* setup cache mask */ | ||
| 31 | movec %d0,%CACR /* enable cache */ | ||
| 32 | .endm | ||
| 33 | #endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ | ||
| 34 | |||
| 35 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) | ||
| 36 | /* | ||
| 37 | * New version 2 cores have a configurable split cache arrangement. | ||
| 38 | * For now I am just enabling instruction cache - but ultimately I | ||
| 39 | * think a split instruction/data cache would be better. | ||
| 40 | */ | ||
| 41 | .macro CACHE_ENABLE | ||
| 42 | movel #0x01400000,%d0 | ||
| 43 | movec %d0,%CACR /* invalidate cache */ | ||
| 44 | nop | ||
| 45 | movel #0x0000c000,%d0 /* set SDRAM cached only */ | ||
| 46 | movec %d0,%ACR0 | ||
| 47 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 48 | movec %d0,%ACR1 | ||
| 49 | movel #0x80400100,%d0 /* configure cache */ | ||
| 50 | movec %d0,%CACR /* enable cache */ | ||
| 51 | nop | ||
| 52 | .endm | ||
| 53 | #endif /* CONFIG_M523x || CONFIG_M527x */ | ||
| 54 | |||
| 55 | #if defined(CONFIG_M528x) | ||
| 56 | .macro CACHE_ENABLE | ||
| 57 | nop | ||
| 58 | movel #0x01000000, %d0 | ||
| 59 | movec %d0, %CACR /* Invalidate cache */ | ||
| 60 | nop | ||
| 61 | movel #0x0000c020, %d0 /* Set SDRAM cached only */ | ||
| 62 | movec %d0, %ACR0 | ||
| 63 | movel #0x00000000, %d0 /* No other regions cached */ | ||
| 64 | movec %d0, %ACR1 | ||
| 65 | movel #0x80000200, %d0 /* Setup cache mask */ | ||
| 66 | movec %d0, %CACR /* Enable cache */ | ||
| 67 | nop | ||
| 68 | .endm | ||
| 69 | #endif /* CONFIG_M528x */ | ||
| 70 | |||
| 71 | #if defined(CONFIG_M5249) || defined(CONFIG_M5307) | ||
| 72 | /* | ||
| 73 | * The version 3 core cache. Oddly enough the version 2 core 5249 | ||
| 74 | * has the same SDRAM and cache setup as the version 3 cores. | ||
| 75 | * This is a single unified instruction/data cache. | ||
| 76 | */ | ||
| 77 | .macro CACHE_ENABLE | ||
| 78 | movel #0x01000000,%d0 /* invalidate whole cache */ | ||
| 79 | movec %d0,%CACR | ||
| 80 | nop | ||
| 81 | #if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3) | ||
| 82 | movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ | ||
| 83 | #else | ||
| 84 | movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */ | ||
| 85 | #endif | ||
| 86 | movec %d0,%ACR0 | ||
| 87 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 88 | movec %d0,%ACR1 | ||
| 89 | movel #0xa0000200,%d0 /* enable cache */ | ||
| 90 | movec %d0,%CACR | ||
| 91 | nop | ||
| 92 | .endm | ||
| 93 | #endif /* CONFIG_M5249 || CONFIG_M5307 */ | ||
| 94 | |||
| 95 | #if defined(CONFIG_M532x) | ||
| 96 | .macro CACHE_ENABLE | ||
| 97 | movel #0x01000000,%d0 /* invalidate cache cmd */ | ||
| 98 | movec %d0,%CACR /* do invalidate cache */ | ||
| 99 | nop | ||
| 100 | movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */ | ||
| 101 | movec %d0,%ACR0 | ||
| 102 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 103 | movec %d0,%ACR1 | ||
| 104 | movel #0x80000200,%d0 /* setup cache mask */ | ||
| 105 | movec %d0,%CACR /* enable cache */ | ||
| 106 | nop | ||
| 107 | .endm | ||
| 108 | #endif /* CONFIG_M532x */ | ||
| 109 | |||
| 110 | #if defined(CONFIG_M5407) | ||
| 111 | /* | ||
| 112 | * Version 4 cores have a true harvard style separate instruction | ||
| 113 | * and data cache. Invalidate and enable cache, also enable write | ||
| 114 | * buffers and branch accelerator. | ||
| 115 | */ | ||
| 116 | .macro CACHE_ENABLE | ||
| 117 | movel #0x01040100,%d0 /* invalidate whole cache */ | ||
| 118 | movec %d0,%CACR | ||
| 119 | nop | ||
| 120 | movel #0x000fc000,%d0 /* set SDRAM cached only */ | ||
| 121 | movec %d0, %ACR0 | ||
| 122 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 123 | movec %d0, %ACR1 | ||
| 124 | movel #0x000fc000,%d0 /* set SDRAM cached only */ | ||
| 125 | movec %d0, %ACR2 | ||
| 126 | movel #0x00000000,%d0 /* no other regions cached */ | ||
| 127 | movec %d0, %ACR3 | ||
| 128 | movel #0xb6088400,%d0 /* enable caches */ | ||
| 129 | movec %d0,%CACR | ||
| 130 | nop | ||
| 131 | .endm | ||
| 132 | #endif /* CONFIG_M5407 */ | ||
| 133 | |||
| 134 | #if defined(CONFIG_M520x) | ||
| 135 | .macro CACHE_ENABLE | ||
| 136 | move.l #0x01000000,%d0 /* invalidate whole cache */ | ||
| 137 | movec %d0,%CACR | ||
| 138 | nop | ||
| 139 | move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ | ||
| 140 | movec %d0,%ACR0 | ||
| 141 | move.l #0x00000000,%d0 /* no other regions cached */ | ||
| 142 | movec %d0,%ACR1 | ||
| 143 | move.l #0x80400000,%d0 /* enable 8K instruction cache */ | ||
| 144 | movec %d0,%CACR | ||
| 145 | nop | ||
| 146 | .endm | ||
| 147 | #endif /* CONFIG_M520x */ | ||
| 148 | |||
| 149 | /****************************************************************************/ | ||
| 150 | #endif /* __M68KNOMMU_MCFCACHE_H */ | ||
diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h new file mode 100644 index 000000000000..705c52c79cd8 --- /dev/null +++ b/arch/m68k/include/asm/mcfdma.h | |||
| @@ -0,0 +1,144 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfdma.h -- Coldfire internal DMA support defines. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef mcfdma_h | ||
| 11 | #define mcfdma_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Get address specific defines for this Coldfire member. | ||
| 17 | */ | ||
| 18 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) | ||
| 19 | #define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */ | ||
| 20 | #define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */ | ||
| 21 | #elif defined(CONFIG_M5272) | ||
| 22 | #define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */ | ||
| 23 | #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) | ||
| 24 | /* These are relative to the IPSBAR, not MBAR */ | ||
| 25 | #define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */ | ||
| 26 | #define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */ | ||
| 27 | #define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */ | ||
| 28 | #define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */ | ||
| 29 | #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) | ||
| 30 | #define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */ | ||
| 31 | #define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */ | ||
| 32 | #define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */ | ||
| 33 | #define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */ | ||
| 34 | #endif | ||
| 35 | |||
| 36 | |||
| 37 | #if !defined(CONFIG_M5272) | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Define the DMA register set addresses. | ||
| 41 | * Note: these are longword registers, use unsigned long as data type | ||
| 42 | */ | ||
| 43 | #define MCFDMA_SAR 0x00 /* DMA source address (r/w) */ | ||
| 44 | #define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */ | ||
| 45 | /* these are word registers, use unsigned short data type */ | ||
| 46 | #define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */ | ||
| 47 | #define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */ | ||
| 48 | /* these are byte registers, use unsiged char data type */ | ||
| 49 | #define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */ | ||
| 50 | #define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */ | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Bit definitions for the DMA Control Register (DCR). | ||
| 54 | */ | ||
| 55 | #define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */ | ||
| 56 | #define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */ | ||
| 57 | #define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */ | ||
| 58 | #define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */ | ||
| 59 | #define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */ | ||
| 60 | #define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */ | ||
| 61 | #define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */ | ||
| 62 | #define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */ | ||
| 63 | #define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */ | ||
| 64 | #define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */ | ||
| 65 | #define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */ | ||
| 66 | #define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */ | ||
| 67 | #define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */ | ||
| 68 | #define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */ | ||
| 69 | #define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */ | ||
| 70 | #define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */ | ||
| 71 | #define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */ | ||
| 72 | #define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */ | ||
| 73 | #define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */ | ||
| 74 | #define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */ | ||
| 75 | #define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */ | ||
| 76 | #define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */ | ||
| 77 | #define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */ | ||
| 78 | #define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */ | ||
| 79 | #define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */ | ||
| 80 | #define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */ | ||
| 81 | #define MCFDMA_DCR_START 0x0001 /* Start transfer */ | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Bit definitions for the DMA Status Register (DSR). | ||
| 85 | */ | ||
| 86 | #define MCFDMA_DSR_CE 0x40 /* Config error */ | ||
| 87 | #define MCFDMA_DSR_BES 0x20 /* Bus Error on source */ | ||
| 88 | #define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */ | ||
| 89 | #define MCFDMA_DSR_REQ 0x04 /* Requests remaining */ | ||
| 90 | #define MCFDMA_DSR_BSY 0x02 /* Busy */ | ||
| 91 | #define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */ | ||
| 92 | |||
| 93 | #else /* This is an MCF5272 */ | ||
| 94 | |||
| 95 | #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */ | ||
| 96 | #define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */ | ||
| 97 | #define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */ | ||
| 98 | #define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */ | ||
| 99 | #define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */ | ||
| 100 | |||
| 101 | /* Bit definitions for the DMA Mode Register (DMR) */ | ||
| 102 | #define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */ | ||
| 103 | #define MCFDMA_DMR_EN 0x40000000L /* DMA enable */ | ||
| 104 | #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */ | ||
| 105 | #define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */ | ||
| 106 | #define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */ | ||
| 107 | #define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */ | ||
| 108 | #define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */ | ||
| 109 | #define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */ | ||
| 110 | #define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */ | ||
| 111 | #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */ | ||
| 112 | #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */ | ||
| 113 | #define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */ | ||
| 114 | #define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */ | ||
| 115 | #define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */ | ||
| 116 | #define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */ | ||
| 117 | #define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */ | ||
| 118 | #define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */ | ||
| 119 | #define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */ | ||
| 120 | #define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */ | ||
| 121 | #define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */ | ||
| 122 | #define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */ | ||
| 123 | #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */ | ||
| 124 | #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */ | ||
| 125 | #define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */ | ||
| 126 | #define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */ | ||
| 127 | #define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */ | ||
| 128 | #define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */ | ||
| 129 | #define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */ | ||
| 130 | |||
| 131 | /* Bit definitions for the DMA interrupt register (DIR) */ | ||
| 132 | #define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */ | ||
| 133 | #define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */ | ||
| 134 | #define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */ | ||
| 135 | #define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */ | ||
| 136 | #define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */ | ||
| 137 | #define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */ | ||
| 138 | #define MCFDMA_DIR_TE 0x0002 /* Transfer Error */ | ||
| 139 | #define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */ | ||
| 140 | |||
| 141 | #endif /* !defined(CONFIG_M5272) */ | ||
| 142 | |||
| 143 | /****************************************************************************/ | ||
| 144 | #endif /* mcfdma_h */ | ||
diff --git a/arch/m68k/include/asm/mcfmbus.h b/arch/m68k/include/asm/mcfmbus.h new file mode 100644 index 000000000000..319899c47a2c --- /dev/null +++ b/arch/m68k/include/asm/mcfmbus.h | |||
| @@ -0,0 +1,77 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfmbus.h -- Coldfire MBUS support defines. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | |||
| 11 | |||
| 12 | #ifndef mcfmbus_h | ||
| 13 | #define mcfmbus_h | ||
| 14 | |||
| 15 | |||
| 16 | #define MCFMBUS_BASE 0x280 | ||
| 17 | #define MCFMBUS_IRQ_VECTOR 0x19 | ||
| 18 | #define MCFMBUS_IRQ 0x1 | ||
| 19 | #define MCFMBUS_CLK 0x3f | ||
| 20 | #define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/ | ||
| 21 | #define MCFMBUS_ADDRESS 0x01 | ||
| 22 | |||
| 23 | |||
| 24 | /* | ||
| 25 | * Define the 5307 MBUS register set addresses | ||
| 26 | */ | ||
| 27 | |||
| 28 | #define MCFMBUS_MADR 0x00 | ||
| 29 | #define MCFMBUS_MFDR 0x04 | ||
| 30 | #define MCFMBUS_MBCR 0x08 | ||
| 31 | #define MCFMBUS_MBSR 0x0C | ||
| 32 | #define MCFMBUS_MBDR 0x10 | ||
| 33 | |||
| 34 | |||
| 35 | #define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/ | ||
| 36 | |||
| 37 | #define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/ | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Define bit flags in Control Register | ||
| 41 | */ | ||
| 42 | |||
| 43 | #define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */ | ||
| 44 | #define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ | ||
| 45 | #define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */ | ||
| 46 | #define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */ | ||
| 47 | #define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ | ||
| 48 | #define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */ | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Define bit flags in Status Register | ||
| 52 | */ | ||
| 53 | |||
| 54 | #define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */ | ||
| 55 | #define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */ | ||
| 56 | #define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */ | ||
| 57 | #define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */ | ||
| 58 | #define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */ | ||
| 59 | #define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */ | ||
| 60 | #define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */ | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Define bit flags in DATA I/O Register | ||
| 64 | */ | ||
| 65 | |||
| 66 | #define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */ | ||
| 67 | |||
| 68 | #define MBUSIOCSCLOCK 1 | ||
| 69 | #define MBUSIOCGCLOCK 2 | ||
| 70 | #define MBUSIOCSADDR 3 | ||
| 71 | #define MBUSIOCGADDR 4 | ||
| 72 | #define MBUSIOCSSLADDR 5 | ||
| 73 | #define MBUSIOCGSLADDR 6 | ||
| 74 | #define MBUSIOCSSUBADDR 7 | ||
| 75 | #define MBUSIOCGSUBADDR 8 | ||
| 76 | |||
| 77 | #endif | ||
diff --git a/arch/m68k/include/asm/mcfne.h b/arch/m68k/include/asm/mcfne.h new file mode 100644 index 000000000000..431f63aadd0e --- /dev/null +++ b/arch/m68k/include/asm/mcfne.h | |||
| @@ -0,0 +1,325 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfne.h -- NE2000 in ColdFire eval boards. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo (www.lineo.com) | ||
| 8 | * (C) Copyright 2001, SnapGear (www.snapgear.com) | ||
| 9 | * | ||
| 10 | * 19990409 David W. Miller Converted from m5206ne.h for 5307 eval board | ||
| 11 | * | ||
| 12 | * Hacked support for m5206e Cadre III evaluation board | ||
| 13 | * Fred Stevens (fred.stevens@pemstar.com) 13 April 1999 | ||
| 14 | */ | ||
| 15 | |||
| 16 | /****************************************************************************/ | ||
| 17 | #ifndef mcfne_h | ||
| 18 | #define mcfne_h | ||
| 19 | /****************************************************************************/ | ||
| 20 | |||
| 21 | |||
| 22 | /* | ||
| 23 | * Support for NE2000 clones devices in ColdFire based boards. | ||
| 24 | * Not all boards address these parts the same way, some use a | ||
| 25 | * direct addressing method, others use a side-band address space | ||
| 26 | * to access odd address registers, some require byte swapping | ||
| 27 | * others do not. | ||
| 28 | */ | ||
| 29 | #define BSWAP(w) (((w) << 8) | ((w) >> 8)) | ||
| 30 | #define RSWAP(w) (w) | ||
| 31 | |||
| 32 | |||
| 33 | /* | ||
| 34 | * Define the basic hardware resources of NE2000 boards. | ||
| 35 | */ | ||
| 36 | |||
| 37 | #if defined(CONFIG_ARN5206) | ||
| 38 | #define NE2000_ADDR 0x40000300 | ||
| 39 | #define NE2000_ODDOFFSET 0x00010000 | ||
| 40 | #define NE2000_IRQ_VECTOR 0xf0 | ||
| 41 | #define NE2000_IRQ_PRIORITY 2 | ||
| 42 | #define NE2000_IRQ_LEVEL 4 | ||
| 43 | #define NE2000_BYTE volatile unsigned short | ||
| 44 | #endif | ||
| 45 | |||
| 46 | #if defined(CONFIG_M5206eC3) | ||
| 47 | #define NE2000_ADDR 0x40000300 | ||
| 48 | #define NE2000_ODDOFFSET 0x00010000 | ||
| 49 | #define NE2000_IRQ_VECTOR 0x1c | ||
| 50 | #define NE2000_IRQ_PRIORITY 2 | ||
| 51 | #define NE2000_IRQ_LEVEL 4 | ||
| 52 | #define NE2000_BYTE volatile unsigned short | ||
| 53 | #endif | ||
| 54 | |||
| 55 | #if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) | ||
| 56 | #define NE2000_ADDR 0x30000300 | ||
| 57 | #define NE2000_IRQ_VECTOR 25 | ||
| 58 | #define NE2000_IRQ_PRIORITY 1 | ||
| 59 | #define NE2000_IRQ_LEVEL 3 | ||
| 60 | #define NE2000_BYTE volatile unsigned char | ||
| 61 | #endif | ||
| 62 | |||
| 63 | #if defined(CONFIG_M5307C3) | ||
| 64 | #define NE2000_ADDR 0x40000300 | ||
| 65 | #define NE2000_ODDOFFSET 0x00010000 | ||
| 66 | #define NE2000_IRQ_VECTOR 0x1b | ||
| 67 | #define NE2000_BYTE volatile unsigned short | ||
| 68 | #endif | ||
| 69 | |||
| 70 | #if defined(CONFIG_M5272) && defined(CONFIG_NETtel) | ||
| 71 | #define NE2000_ADDR 0x30600300 | ||
| 72 | #define NE2000_ODDOFFSET 0x00008000 | ||
| 73 | #define NE2000_IRQ_VECTOR 67 | ||
| 74 | #undef BSWAP | ||
| 75 | #define BSWAP(w) (w) | ||
| 76 | #define NE2000_BYTE volatile unsigned short | ||
| 77 | #undef RSWAP | ||
| 78 | #define RSWAP(w) (((w) << 8) | ((w) >> 8)) | ||
| 79 | #endif | ||
| 80 | |||
| 81 | #if defined(CONFIG_M5307) && defined(CONFIG_NETtel) | ||
| 82 | #define NE2000_ADDR0 0x30600300 | ||
| 83 | #define NE2000_ADDR1 0x30800300 | ||
| 84 | #define NE2000_ODDOFFSET 0x00008000 | ||
| 85 | #define NE2000_IRQ_VECTOR0 27 | ||
| 86 | #define NE2000_IRQ_VECTOR1 29 | ||
| 87 | #undef BSWAP | ||
| 88 | #define BSWAP(w) (w) | ||
| 89 | #define NE2000_BYTE volatile unsigned short | ||
| 90 | #undef RSWAP | ||
| 91 | #define RSWAP(w) (((w) << 8) | ((w) >> 8)) | ||
| 92 | #endif | ||
| 93 | |||
| 94 | #if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3) | ||
| 95 | #define NE2000_ADDR 0x30600300 | ||
| 96 | #define NE2000_ODDOFFSET 0x00008000 | ||
| 97 | #define NE2000_IRQ_VECTOR 27 | ||
| 98 | #undef BSWAP | ||
| 99 | #define BSWAP(w) (w) | ||
| 100 | #define NE2000_BYTE volatile unsigned short | ||
| 101 | #undef RSWAP | ||
| 102 | #define RSWAP(w) (((w) << 8) | ((w) >> 8)) | ||
| 103 | #endif | ||
| 104 | |||
| 105 | #if defined(CONFIG_ARN5307) | ||
| 106 | #define NE2000_ADDR 0xfe600300 | ||
| 107 | #define NE2000_ODDOFFSET 0x00010000 | ||
| 108 | #define NE2000_IRQ_VECTOR 0x1b | ||
| 109 | #define NE2000_IRQ_PRIORITY 2 | ||
| 110 | #define NE2000_IRQ_LEVEL 3 | ||
| 111 | #define NE2000_BYTE volatile unsigned short | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if defined(CONFIG_M5407C3) | ||
| 115 | #define NE2000_ADDR 0x40000300 | ||
| 116 | #define NE2000_ODDOFFSET 0x00010000 | ||
| 117 | #define NE2000_IRQ_VECTOR 0x1b | ||
| 118 | #define NE2000_BYTE volatile unsigned short | ||
| 119 | #endif | ||
| 120 | |||
| 121 | /****************************************************************************/ | ||
| 122 | |||
| 123 | /* | ||
| 124 | * Side-band address space for odd address requires re-mapping | ||
| 125 | * many of the standard ISA access functions. | ||
| 126 | */ | ||
| 127 | #ifdef NE2000_ODDOFFSET | ||
| 128 | |||
| 129 | #undef outb | ||
| 130 | #undef outb_p | ||
| 131 | #undef inb | ||
| 132 | #undef inb_p | ||
| 133 | #undef outsb | ||
| 134 | #undef outsw | ||
| 135 | #undef insb | ||
| 136 | #undef insw | ||
| 137 | |||
| 138 | #define outb ne2000_outb | ||
| 139 | #define inb ne2000_inb | ||
| 140 | #define outb_p ne2000_outb | ||
| 141 | #define inb_p ne2000_inb | ||
| 142 | #define outsb ne2000_outsb | ||
| 143 | #define outsw ne2000_outsw | ||
| 144 | #define insb ne2000_insb | ||
| 145 | #define insw ne2000_insw | ||
| 146 | |||
| 147 | |||
| 148 | #ifndef COLDFIRE_NE2000_FUNCS | ||
| 149 | |||
| 150 | void ne2000_outb(unsigned int val, unsigned int addr); | ||
| 151 | int ne2000_inb(unsigned int addr); | ||
| 152 | void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len); | ||
| 153 | void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len); | ||
| 154 | void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len); | ||
| 155 | void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len); | ||
| 156 | |||
| 157 | #else | ||
| 158 | |||
| 159 | /* | ||
| 160 | * This macro converts a conventional register address into the | ||
| 161 | * real memory pointer of the mapped NE2000 device. | ||
| 162 | * On most NE2000 implementations on ColdFire boards the chip is | ||
| 163 | * mapped in kinda funny, due to its ISA heritage. | ||
| 164 | */ | ||
| 165 | #define NE2000_PTR(addr) ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr)) | ||
| 166 | #define NE2000_DATA_PTR(addr) (addr) | ||
| 167 | |||
| 168 | |||
| 169 | void ne2000_outb(unsigned int val, unsigned int addr) | ||
| 170 | { | ||
| 171 | NE2000_BYTE *rp; | ||
| 172 | |||
| 173 | rp = (NE2000_BYTE *) NE2000_PTR(addr); | ||
| 174 | *rp = RSWAP(val); | ||
| 175 | } | ||
| 176 | |||
| 177 | int ne2000_inb(unsigned int addr) | ||
| 178 | { | ||
| 179 | NE2000_BYTE *rp, val; | ||
| 180 | |||
| 181 | rp = (NE2000_BYTE *) NE2000_PTR(addr); | ||
| 182 | val = *rp; | ||
| 183 | return((int) ((NE2000_BYTE) RSWAP(val))); | ||
| 184 | } | ||
| 185 | |||
| 186 | void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len) | ||
| 187 | { | ||
| 188 | NE2000_BYTE *rp, val; | ||
| 189 | unsigned char *buf; | ||
| 190 | |||
| 191 | buf = (unsigned char *) vbuf; | ||
| 192 | rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr); | ||
| 193 | for (; (len > 0); len--) { | ||
| 194 | val = *rp; | ||
| 195 | *buf++ = RSWAP(val); | ||
| 196 | } | ||
| 197 | } | ||
| 198 | |||
| 199 | void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len) | ||
| 200 | { | ||
| 201 | volatile unsigned short *rp; | ||
| 202 | unsigned short w, *buf; | ||
| 203 | |||
| 204 | buf = (unsigned short *) vbuf; | ||
| 205 | rp = (volatile unsigned short *) NE2000_DATA_PTR(addr); | ||
| 206 | for (; (len > 0); len--) { | ||
| 207 | w = *rp; | ||
| 208 | *buf++ = BSWAP(w); | ||
| 209 | } | ||
| 210 | } | ||
| 211 | |||
| 212 | void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len) | ||
| 213 | { | ||
| 214 | NE2000_BYTE *rp, val; | ||
| 215 | unsigned char *buf; | ||
| 216 | |||
| 217 | buf = (unsigned char *) vbuf; | ||
| 218 | rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr); | ||
| 219 | for (; (len > 0); len--) { | ||
| 220 | val = *buf++; | ||
| 221 | *rp = RSWAP(val); | ||
| 222 | } | ||
| 223 | } | ||
| 224 | |||
| 225 | void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len) | ||
| 226 | { | ||
| 227 | volatile unsigned short *rp; | ||
| 228 | unsigned short w, *buf; | ||
| 229 | |||
| 230 | buf = (unsigned short *) vbuf; | ||
| 231 | rp = (volatile unsigned short *) NE2000_DATA_PTR(addr); | ||
| 232 | for (; (len > 0); len--) { | ||
| 233 | w = *buf++; | ||
| 234 | *rp = BSWAP(w); | ||
| 235 | } | ||
| 236 | } | ||
| 237 | |||
| 238 | #endif /* COLDFIRE_NE2000_FUNCS */ | ||
| 239 | #endif /* NE2000_OFFOFFSET */ | ||
| 240 | |||
| 241 | /****************************************************************************/ | ||
| 242 | |||
| 243 | #ifdef COLDFIRE_NE2000_FUNCS | ||
| 244 | |||
| 245 | /* | ||
| 246 | * Lastly the interrupt set up code... | ||
| 247 | * Minor differences between the different board types. | ||
| 248 | */ | ||
| 249 | |||
| 250 | #if defined(CONFIG_ARN5206) | ||
| 251 | void ne2000_irqsetup(int irq) | ||
| 252 | { | ||
| 253 | volatile unsigned char *icrp; | ||
| 254 | |||
| 255 | icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4); | ||
| 256 | *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2; | ||
| 257 | mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4); | ||
| 258 | } | ||
| 259 | #endif | ||
| 260 | |||
| 261 | #if defined(CONFIG_M5206eC3) | ||
| 262 | void ne2000_irqsetup(int irq) | ||
| 263 | { | ||
| 264 | volatile unsigned char *icrp; | ||
| 265 | |||
| 266 | icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4); | ||
| 267 | *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2 | MCFSIM_ICR_AUTOVEC; | ||
| 268 | mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4); | ||
| 269 | } | ||
| 270 | #endif | ||
| 271 | |||
| 272 | #if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) | ||
| 273 | void ne2000_irqsetup(int irq) | ||
| 274 | { | ||
| 275 | mcf_autovector(irq); | ||
| 276 | } | ||
| 277 | #endif | ||
| 278 | |||
| 279 | #if defined(CONFIG_M5272) && defined(CONFIG_NETtel) | ||
| 280 | void ne2000_irqsetup(int irq) | ||
| 281 | { | ||
| 282 | volatile unsigned long *icrp; | ||
| 283 | volatile unsigned long *pitr; | ||
| 284 | |||
| 285 | /* The NE2000 device uses external IRQ3 */ | ||
| 286 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | ||
| 287 | *icrp = (*icrp & 0x77077777) | 0x00d00000; | ||
| 288 | |||
| 289 | pitr = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PITR); | ||
| 290 | *pitr = *pitr | 0x20000000; | ||
| 291 | } | ||
| 292 | |||
| 293 | void ne2000_irqack(int irq) | ||
| 294 | { | ||
| 295 | volatile unsigned long *icrp; | ||
| 296 | |||
| 297 | /* The NE2000 device uses external IRQ3 */ | ||
| 298 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | ||
| 299 | *icrp = (*icrp & 0x77777777) | 0x00800000; | ||
| 300 | } | ||
| 301 | #endif | ||
| 302 | |||
| 303 | #if defined(CONFIG_M5307) || defined(CONFIG_M5407) | ||
| 304 | #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) | ||
| 305 | |||
| 306 | void ne2000_irqsetup(int irq) | ||
| 307 | { | ||
| 308 | mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3); | ||
| 309 | mcf_autovector(irq); | ||
| 310 | } | ||
| 311 | |||
| 312 | #else | ||
| 313 | |||
| 314 | void ne2000_irqsetup(int irq) | ||
| 315 | { | ||
| 316 | mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3); | ||
| 317 | } | ||
| 318 | |||
| 319 | #endif /* ! CONFIG_NETtel || CONFIG_SECUREEDGEMP3 */ | ||
| 320 | #endif /* CONFIG_M5307 || CONFIG_M5407 */ | ||
| 321 | |||
| 322 | #endif /* COLDFIRE_NE2000_FUNCS */ | ||
| 323 | |||
| 324 | /****************************************************************************/ | ||
| 325 | #endif /* mcfne_h */ | ||
diff --git a/arch/m68k/include/asm/mcfpci.h b/arch/m68k/include/asm/mcfpci.h new file mode 100644 index 000000000000..f1507dd06ec6 --- /dev/null +++ b/arch/m68k/include/asm/mcfpci.h | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfpci.h -- PCI bridge on ColdFire eval boards. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2000, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef mcfpci_h | ||
| 12 | #define mcfpci_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | #ifdef CONFIG_PCI | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Address regions in the PCI address space are not mapped into the | ||
| 20 | * normal memory space of the ColdFire. They must be accessed via | ||
| 21 | * handler routines. This is easy for I/O space (inb/outb/etc) but | ||
| 22 | * needs some code changes to support ordinary memory. Interrupts | ||
| 23 | * also need to be vectored through the PCI handler first, then it | ||
| 24 | * will call the actual driver sub-handlers. | ||
| 25 | */ | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Un-define all the standard I/O access routines. | ||
| 29 | */ | ||
| 30 | #undef inb | ||
| 31 | #undef inw | ||
| 32 | #undef inl | ||
| 33 | #undef inb_p | ||
| 34 | #undef inw_p | ||
| 35 | #undef insb | ||
| 36 | #undef insw | ||
| 37 | #undef insl | ||
| 38 | #undef outb | ||
| 39 | #undef outw | ||
| 40 | #undef outl | ||
| 41 | #undef outb_p | ||
| 42 | #undef outw_p | ||
| 43 | #undef outsb | ||
| 44 | #undef outsw | ||
| 45 | #undef outsl | ||
| 46 | |||
| 47 | #undef request_irq | ||
| 48 | #undef free_irq | ||
| 49 | |||
| 50 | #undef bus_to_virt | ||
| 51 | #undef virt_to_bus | ||
| 52 | |||
| 53 | |||
| 54 | /* | ||
| 55 | * Re-direct all I/O memory accesses functions to PCI specific ones. | ||
| 56 | */ | ||
| 57 | #define inb pci_inb | ||
| 58 | #define inw pci_inw | ||
| 59 | #define inl pci_inl | ||
| 60 | #define inb_p pci_inb | ||
| 61 | #define inw_p pci_inw | ||
| 62 | #define insb pci_insb | ||
| 63 | #define insw pci_insw | ||
| 64 | #define insl pci_insl | ||
| 65 | |||
| 66 | #define outb pci_outb | ||
| 67 | #define outw pci_outw | ||
| 68 | #define outl pci_outl | ||
| 69 | #define outb_p pci_outb | ||
| 70 | #define outw_p pci_outw | ||
| 71 | #define outsb pci_outsb | ||
| 72 | #define outsw pci_outsw | ||
| 73 | #define outsl pci_outsl | ||
| 74 | |||
| 75 | #define request_irq pci_request_irq | ||
| 76 | #define free_irq pci_free_irq | ||
| 77 | |||
| 78 | #define virt_to_bus pci_virt_to_bus | ||
| 79 | #define bus_to_virt pci_bus_to_virt | ||
| 80 | |||
| 81 | #define CONFIG_COMEMPCI 1 | ||
| 82 | |||
| 83 | |||
| 84 | /* | ||
| 85 | * Prototypes of the real PCI functions (defined in bios32.c). | ||
| 86 | */ | ||
| 87 | unsigned char pci_inb(unsigned int addr); | ||
| 88 | unsigned short pci_inw(unsigned int addr); | ||
| 89 | unsigned int pci_inl(unsigned int addr); | ||
| 90 | void pci_insb(void *addr, void *buf, int len); | ||
| 91 | void pci_insw(void *addr, void *buf, int len); | ||
| 92 | void pci_insl(void *addr, void *buf, int len); | ||
| 93 | |||
| 94 | void pci_outb(unsigned char val, unsigned int addr); | ||
| 95 | void pci_outw(unsigned short val, unsigned int addr); | ||
| 96 | void pci_outl(unsigned int val, unsigned int addr); | ||
| 97 | void pci_outsb(void *addr, void *buf, int len); | ||
| 98 | void pci_outsw(void *addr, void *buf, int len); | ||
| 99 | void pci_outsl(void *addr, void *buf, int len); | ||
| 100 | |||
| 101 | int pci_request_irq(unsigned int irq, | ||
| 102 | void (*handler)(int, void *, struct pt_regs *), | ||
| 103 | unsigned long flags, | ||
| 104 | const char *device, | ||
| 105 | void *dev_id); | ||
| 106 | void pci_free_irq(unsigned int irq, void *dev_id); | ||
| 107 | |||
| 108 | void *pci_bmalloc(int size); | ||
| 109 | void pci_bmfree(void *bmp, int len); | ||
| 110 | void pci_copytoshmem(unsigned long bmp, void *src, int size); | ||
| 111 | void pci_copyfromshmem(void *dst, unsigned long bmp, int size); | ||
| 112 | unsigned long pci_virt_to_bus(volatile void *address); | ||
| 113 | void *pci_bus_to_virt(unsigned long address); | ||
| 114 | void pci_bmcpyto(void *dst, void *src, int len); | ||
| 115 | void pci_bmcpyfrom(void *dst, void *src, int len); | ||
| 116 | |||
| 117 | #endif /* CONFIG_PCI */ | ||
| 118 | /****************************************************************************/ | ||
| 119 | #endif /* mcfpci_h */ | ||
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h new file mode 100644 index 000000000000..f570cf64fd29 --- /dev/null +++ b/arch/m68k/include/asm/mcfpit.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfpit.h -- ColdFire internal PIT timer support defines. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef mcfpit_h | ||
| 11 | #define mcfpit_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | |||
| 15 | /* | ||
| 16 | * Get address specific defines for the 5270/5271, 5280/5282, and 5208. | ||
| 17 | */ | ||
| 18 | #if defined(CONFIG_M520x) | ||
| 19 | #define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */ | ||
| 20 | #define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */ | ||
| 21 | #else | ||
| 22 | #define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */ | ||
| 23 | #define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */ | ||
| 24 | #define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */ | ||
| 25 | #define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */ | ||
| 26 | #endif | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Define the PIT timer register set addresses. | ||
| 30 | */ | ||
| 31 | #define MCFPIT_PCSR 0x0 /* PIT control register */ | ||
| 32 | #define MCFPIT_PMR 0x2 /* PIT modulus register */ | ||
| 33 | #define MCFPIT_PCNTR 0x4 /* PIT count register */ | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Bit definitions for the PIT Control and Status register. | ||
| 37 | */ | ||
| 38 | #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */ | ||
| 39 | #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */ | ||
| 40 | #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */ | ||
| 41 | #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */ | ||
| 42 | #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */ | ||
| 43 | #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */ | ||
| 44 | #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */ | ||
| 45 | #define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */ | ||
| 46 | #define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */ | ||
| 47 | #define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */ | ||
| 48 | #define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */ | ||
| 49 | #define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */ | ||
| 50 | #define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */ | ||
| 51 | #define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */ | ||
| 52 | #define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */ | ||
| 53 | #define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */ | ||
| 54 | #define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */ | ||
| 55 | #define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */ | ||
| 56 | #define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */ | ||
| 57 | #define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */ | ||
| 58 | #define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */ | ||
| 59 | #define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */ | ||
| 60 | #define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */ | ||
| 61 | #define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */ | ||
| 62 | |||
| 63 | /****************************************************************************/ | ||
| 64 | #endif /* mcfpit_h */ | ||
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h new file mode 100644 index 000000000000..da3f2ceff3a4 --- /dev/null +++ b/arch/m68k/include/asm/mcfsim.h | |||
| @@ -0,0 +1,126 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfsim.h -- ColdFire System Integration Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef mcfsim_h | ||
| 12 | #define mcfsim_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282, | ||
| 18 | * 5307 or 5407 specific addresses. | ||
| 19 | */ | ||
| 20 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) | ||
| 21 | #include <asm/m5206sim.h> | ||
| 22 | #elif defined(CONFIG_M520x) | ||
| 23 | #include <asm/m520xsim.h> | ||
| 24 | #elif defined(CONFIG_M523x) | ||
| 25 | #include <asm/m523xsim.h> | ||
| 26 | #elif defined(CONFIG_M5249) | ||
| 27 | #include <asm/m5249sim.h> | ||
| 28 | #elif defined(CONFIG_M527x) | ||
| 29 | #include <asm/m527xsim.h> | ||
| 30 | #elif defined(CONFIG_M5272) | ||
| 31 | #include <asm/m5272sim.h> | ||
| 32 | #elif defined(CONFIG_M528x) | ||
| 33 | #include <asm/m528xsim.h> | ||
| 34 | #elif defined(CONFIG_M5307) | ||
| 35 | #include <asm/m5307sim.h> | ||
| 36 | #elif defined(CONFIG_M532x) | ||
| 37 | #include <asm/m532xsim.h> | ||
| 38 | #elif defined(CONFIG_M5407) | ||
| 39 | #include <asm/m5407sim.h> | ||
| 40 | #endif | ||
| 41 | |||
| 42 | |||
| 43 | /* | ||
| 44 | * Define the base address of the SIM within the MBAR address space. | ||
| 45 | */ | ||
| 46 | #define MCFSIM_BASE 0x0 /* Base address of SIM */ | ||
| 47 | |||
| 48 | |||
| 49 | /* | ||
| 50 | * Bit definitions for the ICR family of registers. | ||
| 51 | */ | ||
| 52 | #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ | ||
| 53 | #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ | ||
| 54 | #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ | ||
| 55 | #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ | ||
| 56 | #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ | ||
| 57 | #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ | ||
| 58 | #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ | ||
| 59 | #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ | ||
| 60 | #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ | ||
| 61 | |||
| 62 | #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ | ||
| 63 | #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ | ||
| 64 | #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ | ||
| 65 | #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Bit definitions for the Interrupt Mask register (IMR). | ||
| 69 | */ | ||
| 70 | #define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */ | ||
| 71 | #define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */ | ||
| 72 | #define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */ | ||
| 73 | #define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */ | ||
| 74 | #define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */ | ||
| 75 | #define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */ | ||
| 76 | #define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */ | ||
| 77 | |||
| 78 | #define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */ | ||
| 79 | #define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */ | ||
| 80 | #define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */ | ||
| 81 | #define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */ | ||
| 82 | #define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */ | ||
| 83 | #define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */ | ||
| 84 | |||
| 85 | #if defined(CONFIG_M5206e) | ||
| 86 | #define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */ | ||
| 87 | #define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */ | ||
| 88 | #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) | ||
| 89 | #define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */ | ||
| 90 | #define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */ | ||
| 91 | #define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */ | ||
| 92 | #define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */ | ||
| 93 | #endif | ||
| 94 | |||
| 95 | /* | ||
| 96 | * Mask for all of the SIM devices. Some parts have more or less | ||
| 97 | * SIM devices. This is a catchall for the sandard set. | ||
| 98 | */ | ||
| 99 | #ifndef MCFSIM_IMR_MASKALL | ||
| 100 | #define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */ | ||
| 101 | #endif | ||
| 102 | |||
| 103 | |||
| 104 | /* | ||
| 105 | * PIT interrupt settings, if not found in mXXXXsim.h file. | ||
| 106 | */ | ||
| 107 | #ifndef ICR_INTRCONF | ||
| 108 | #define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */ | ||
| 109 | #endif | ||
| 110 | #ifndef MCFPIT_IMR | ||
| 111 | #define MCFPIT_IMR MCFINTC_IMRH | ||
| 112 | #endif | ||
| 113 | #ifndef MCFPIT_IMR_IBIT | ||
| 114 | #define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32)) | ||
| 115 | #endif | ||
| 116 | |||
| 117 | |||
| 118 | #ifndef __ASSEMBLY__ | ||
| 119 | /* | ||
| 120 | * Definition for the interrupt auto-vectoring support. | ||
| 121 | */ | ||
| 122 | extern void mcf_autovector(unsigned int vec); | ||
| 123 | #endif /* __ASSEMBLY__ */ | ||
| 124 | |||
| 125 | /****************************************************************************/ | ||
| 126 | #endif /* mcfsim_h */ | ||
diff --git a/arch/m68k/include/asm/mcfsmc.h b/arch/m68k/include/asm/mcfsmc.h new file mode 100644 index 000000000000..2d7a4dbd9683 --- /dev/null +++ b/arch/m68k/include/asm/mcfsmc.h | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfsmc.h -- SMC ethernet support for ColdFire environments. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef mcfsmc_h | ||
| 12 | #define mcfsmc_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * None of the current ColdFire targets that use the SMC91x111 | ||
| 17 | * allow 8 bit accesses. So this code is 16bit access only. | ||
| 18 | */ | ||
| 19 | |||
| 20 | |||
| 21 | #undef outb | ||
| 22 | #undef inb | ||
| 23 | #undef outw | ||
| 24 | #undef outwd | ||
| 25 | #undef inw | ||
| 26 | #undef outl | ||
| 27 | #undef inl | ||
| 28 | |||
| 29 | #undef outsb | ||
| 30 | #undef outsw | ||
| 31 | #undef outsl | ||
| 32 | #undef insb | ||
| 33 | #undef insw | ||
| 34 | #undef insl | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Re-defines for ColdFire environment... The SMC part is | ||
| 38 | * mapped into memory space, so remap the PC-style in/out | ||
| 39 | * routines to handle that. | ||
| 40 | */ | ||
| 41 | #define outb smc_outb | ||
| 42 | #define inb smc_inb | ||
| 43 | #define outw smc_outw | ||
| 44 | #define outwd smc_outwd | ||
| 45 | #define inw smc_inw | ||
| 46 | #define outl smc_outl | ||
| 47 | #define inl smc_inl | ||
| 48 | |||
| 49 | #define outsb smc_outsb | ||
| 50 | #define outsw smc_outsw | ||
| 51 | #define outsl smc_outsl | ||
| 52 | #define insb smc_insb | ||
| 53 | #define insw smc_insw | ||
| 54 | #define insl smc_insl | ||
| 55 | |||
| 56 | |||
| 57 | static inline int smc_inb(unsigned int addr) | ||
| 58 | { | ||
| 59 | register unsigned short w; | ||
| 60 | w = *((volatile unsigned short *) (addr & ~0x1)); | ||
| 61 | return(((addr & 0x1) ? w : (w >> 8)) & 0xff); | ||
| 62 | } | ||
| 63 | |||
| 64 | static inline void smc_outw(unsigned int val, unsigned int addr) | ||
| 65 | { | ||
| 66 | *((volatile unsigned short *) addr) = (val << 8) | (val >> 8); | ||
| 67 | } | ||
| 68 | |||
| 69 | static inline int smc_inw(unsigned int addr) | ||
| 70 | { | ||
| 71 | register unsigned short w; | ||
| 72 | w = *((volatile unsigned short *) addr); | ||
| 73 | return(((w << 8) | (w >> 8)) & 0xffff); | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline void smc_outl(unsigned long val, unsigned int addr) | ||
| 77 | { | ||
| 78 | *((volatile unsigned long *) addr) = | ||
| 79 | ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) | | ||
| 80 | ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff); | ||
| 81 | } | ||
| 82 | |||
| 83 | static inline void smc_outwd(unsigned int val, unsigned int addr) | ||
| 84 | { | ||
| 85 | *((volatile unsigned short *) addr) = val; | ||
| 86 | } | ||
| 87 | |||
| 88 | |||
| 89 | /* | ||
| 90 | * The rep* functions are used to feed the data port with | ||
| 91 | * raw data. So we do not byte swap them when copying. | ||
| 92 | */ | ||
| 93 | |||
| 94 | static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len) | ||
| 95 | { | ||
| 96 | volatile unsigned short *rp; | ||
| 97 | unsigned short *buf, *ebuf; | ||
| 98 | |||
| 99 | buf = (unsigned short *) vbuf; | ||
| 100 | rp = (volatile unsigned short *) addr; | ||
| 101 | |||
| 102 | /* Copy as words for as long as possible */ | ||
| 103 | for (ebuf = buf + (len >> 1); (buf < ebuf); ) | ||
| 104 | *buf++ = *rp; | ||
| 105 | |||
| 106 | /* Lastly, handle left over byte */ | ||
| 107 | if (len & 0x1) | ||
| 108 | *((unsigned char *) buf) = (*rp >> 8) & 0xff; | ||
| 109 | } | ||
| 110 | |||
| 111 | static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len) | ||
| 112 | { | ||
| 113 | volatile unsigned short *rp; | ||
| 114 | unsigned short *buf, *ebuf; | ||
| 115 | |||
| 116 | buf = (unsigned short *) vbuf; | ||
| 117 | rp = (volatile unsigned short *) addr; | ||
| 118 | for (ebuf = buf + len; (buf < ebuf); ) | ||
| 119 | *buf++ = *rp; | ||
| 120 | } | ||
| 121 | |||
| 122 | static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len) | ||
| 123 | { | ||
| 124 | volatile unsigned long *rp; | ||
| 125 | unsigned long *buf, *ebuf; | ||
| 126 | |||
| 127 | buf = (unsigned long *) vbuf; | ||
| 128 | rp = (volatile unsigned long *) addr; | ||
| 129 | for (ebuf = buf + len; (buf < ebuf); ) | ||
| 130 | *buf++ = *rp; | ||
| 131 | } | ||
| 132 | |||
| 133 | static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len) | ||
| 134 | { | ||
| 135 | volatile unsigned short *rp; | ||
| 136 | unsigned short *buf, *ebuf; | ||
| 137 | |||
| 138 | buf = (unsigned short *) vbuf; | ||
| 139 | rp = (volatile unsigned short *) addr; | ||
| 140 | for (ebuf = buf + len; (buf < ebuf); ) | ||
| 141 | *rp = *buf++; | ||
| 142 | } | ||
| 143 | |||
| 144 | static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len) | ||
| 145 | { | ||
| 146 | volatile unsigned long *rp; | ||
| 147 | unsigned long *buf, *ebuf; | ||
| 148 | |||
| 149 | buf = (unsigned long *) vbuf; | ||
| 150 | rp = (volatile unsigned long *) addr; | ||
| 151 | for (ebuf = buf + len; (buf < ebuf); ) | ||
| 152 | *rp = *buf++; | ||
| 153 | } | ||
| 154 | |||
| 155 | |||
| 156 | #ifdef CONFIG_NETtel | ||
| 157 | /* | ||
| 158 | * Re-map the address space of at least one of the SMC ethernet | ||
| 159 | * parts. Both parts power up decoding the same address, so we | ||
| 160 | * need to move one of them first, before doing enything else. | ||
| 161 | * | ||
| 162 | * We also increase the number of wait states for this part by one. | ||
| 163 | */ | ||
| 164 | |||
| 165 | void smc_remap(unsigned int ioaddr) | ||
| 166 | { | ||
| 167 | static int once = 0; | ||
| 168 | extern unsigned short ppdata; | ||
| 169 | if (once++ == 0) { | ||
| 170 | *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADDR)) = 0x00ec; | ||
| 171 | ppdata |= 0x0080; | ||
| 172 | *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; | ||
| 173 | outw(0x0001, ioaddr + BANK_SELECT); | ||
| 174 | outw(0x0001, ioaddr + BANK_SELECT); | ||
| 175 | outw(0x0067, ioaddr + BASE); | ||
| 176 | |||
| 177 | ppdata &= ~0x0080; | ||
| 178 | *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; | ||
| 179 | } | ||
| 180 | |||
| 181 | *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180; | ||
| 182 | } | ||
| 183 | |||
| 184 | #endif | ||
| 185 | |||
| 186 | /****************************************************************************/ | ||
| 187 | #endif /* mcfsmc_h */ | ||
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h new file mode 100644 index 000000000000..0f90f6d2227a --- /dev/null +++ b/arch/m68k/include/asm/mcftimer.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcftimer.h -- ColdFire internal TIMER support defines. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef mcftimer_h | ||
| 12 | #define mcftimer_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | /* | ||
| 17 | * Get address specific defines for this ColdFire member. | ||
| 18 | */ | ||
| 19 | #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) | ||
| 20 | #define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ | ||
| 21 | #define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ | ||
| 22 | #elif defined(CONFIG_M5272) | ||
| 23 | #define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ | ||
| 24 | #define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ | ||
| 25 | #define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ | ||
| 26 | #define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ | ||
| 27 | #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) | ||
| 28 | #define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ | ||
| 29 | #define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ | ||
| 30 | #elif defined(CONFIG_M532x) | ||
| 31 | #define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */ | ||
| 32 | #define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */ | ||
| 33 | #define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */ | ||
| 34 | #define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */ | ||
| 35 | #endif | ||
| 36 | |||
| 37 | |||
| 38 | /* | ||
| 39 | * Define the TIMER register set addresses. | ||
| 40 | */ | ||
| 41 | #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ | ||
| 42 | #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ | ||
| 43 | #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ | ||
| 44 | #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ | ||
| 45 | #if defined(CONFIG_M532x) | ||
| 46 | #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ | ||
| 47 | #else | ||
| 48 | #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ | ||
| 49 | #endif | ||
| 50 | |||
| 51 | /* | ||
| 52 | * Bit definitions for the Timer Mode Register (TMR). | ||
| 53 | * Register bit flags are common accross ColdFires. | ||
| 54 | */ | ||
| 55 | #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ | ||
| 56 | #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ | ||
| 57 | #define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ | ||
| 58 | #define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ | ||
| 59 | #define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ | ||
| 60 | #define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ | ||
| 61 | #define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ | ||
| 62 | #define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ | ||
| 63 | #define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ | ||
| 64 | #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ | ||
| 65 | #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ | ||
| 66 | #define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ | ||
| 67 | #define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ | ||
| 68 | #define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ | ||
| 69 | #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ | ||
| 70 | #define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ | ||
| 71 | #define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ | ||
| 72 | |||
| 73 | /* | ||
| 74 | * Bit definitions for the Timer Event Registers (TER). | ||
| 75 | */ | ||
| 76 | #define MCFTIMER_TER_CAP 0x01 /* Capture event */ | ||
| 77 | #define MCFTIMER_TER_REF 0x02 /* Refernece event */ | ||
| 78 | |||
| 79 | /****************************************************************************/ | ||
| 80 | #endif /* mcftimer_h */ | ||
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h new file mode 100644 index 000000000000..ef2293873612 --- /dev/null +++ b/arch/m68k/include/asm/mcfuart.h | |||
| @@ -0,0 +1,216 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfuart.h -- ColdFire internal UART support defines. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) | ||
| 7 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) | ||
| 8 | */ | ||
| 9 | |||
| 10 | /****************************************************************************/ | ||
| 11 | #ifndef mcfuart_h | ||
| 12 | #define mcfuart_h | ||
| 13 | /****************************************************************************/ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Define the base address of the UARTS within the MBAR address | ||
| 17 | * space. | ||
| 18 | */ | ||
| 19 | #if defined(CONFIG_M5272) | ||
| 20 | #define MCFUART_BASE1 0x100 /* Base address of UART1 */ | ||
| 21 | #define MCFUART_BASE2 0x140 /* Base address of UART2 */ | ||
| 22 | #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) | ||
| 23 | #if defined(CONFIG_NETtel) | ||
| 24 | #define MCFUART_BASE1 0x180 /* Base address of UART1 */ | ||
| 25 | #define MCFUART_BASE2 0x140 /* Base address of UART2 */ | ||
| 26 | #else | ||
| 27 | #define MCFUART_BASE1 0x140 /* Base address of UART1 */ | ||
| 28 | #define MCFUART_BASE2 0x180 /* Base address of UART2 */ | ||
| 29 | #endif | ||
| 30 | #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) | ||
| 31 | #define MCFUART_BASE1 0x200 /* Base address of UART1 */ | ||
| 32 | #define MCFUART_BASE2 0x240 /* Base address of UART2 */ | ||
| 33 | #define MCFUART_BASE3 0x280 /* Base address of UART3 */ | ||
| 34 | #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) | ||
| 35 | #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) | ||
| 36 | #define MCFUART_BASE1 0x200 /* Base address of UART1 */ | ||
| 37 | #define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ | ||
| 38 | #else | ||
| 39 | #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ | ||
| 40 | #define MCFUART_BASE2 0x200 /* Base address of UART2 */ | ||
| 41 | #endif | ||
| 42 | #elif defined(CONFIG_M520x) | ||
| 43 | #define MCFUART_BASE1 0x60000 /* Base address of UART1 */ | ||
| 44 | #define MCFUART_BASE2 0x64000 /* Base address of UART2 */ | ||
| 45 | #define MCFUART_BASE3 0x68000 /* Base address of UART2 */ | ||
| 46 | #elif defined(CONFIG_M532x) | ||
| 47 | #define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ | ||
| 48 | #define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ | ||
| 49 | #define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ | ||
| 50 | #endif | ||
| 51 | |||
| 52 | |||
| 53 | #include <linux/serial_core.h> | ||
| 54 | #include <linux/platform_device.h> | ||
| 55 | |||
| 56 | struct mcf_platform_uart { | ||
| 57 | unsigned long mapbase; /* Physical address base */ | ||
| 58 | void __iomem *membase; /* Virtual address if mapped */ | ||
| 59 | unsigned int irq; /* Interrupt vector */ | ||
| 60 | unsigned int uartclk; /* UART clock rate */ | ||
| 61 | }; | ||
| 62 | |||
| 63 | /* | ||
| 64 | * Define the ColdFire UART register set addresses. | ||
| 65 | */ | ||
| 66 | #define MCFUART_UMR 0x00 /* Mode register (r/w) */ | ||
| 67 | #define MCFUART_USR 0x04 /* Status register (r) */ | ||
| 68 | #define MCFUART_UCSR 0x04 /* Clock Select (w) */ | ||
| 69 | #define MCFUART_UCR 0x08 /* Command register (w) */ | ||
| 70 | #define MCFUART_URB 0x0c /* Receiver Buffer (r) */ | ||
| 71 | #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ | ||
| 72 | #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ | ||
| 73 | #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ | ||
| 74 | #define MCFUART_UISR 0x14 /* Interrupt Status (r) */ | ||
| 75 | #define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ | ||
| 76 | #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ | ||
| 77 | #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ | ||
| 78 | #ifdef CONFIG_M5272 | ||
| 79 | #define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ | ||
| 80 | #define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ | ||
| 81 | #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ | ||
| 82 | #else | ||
| 83 | #define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ | ||
| 84 | #endif | ||
| 85 | #define MCFUART_UIPR 0x34 /* Input Port (r) */ | ||
| 86 | #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ | ||
| 87 | #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ | ||
| 88 | |||
| 89 | |||
| 90 | /* | ||
| 91 | * Define bit flags in Mode Register 1 (MR1). | ||
| 92 | */ | ||
| 93 | #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ | ||
| 94 | #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ | ||
| 95 | #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ | ||
| 96 | #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ | ||
| 97 | #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ | ||
| 98 | |||
| 99 | #define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ | ||
| 100 | #define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ | ||
| 101 | #define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ | ||
| 102 | #define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ | ||
| 103 | #define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ | ||
| 104 | |||
| 105 | #define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ | ||
| 106 | #define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ | ||
| 107 | #define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ | ||
| 108 | #define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ | ||
| 109 | |||
| 110 | /* | ||
| 111 | * Define bit flags in Mode Register 2 (MR2). | ||
| 112 | */ | ||
| 113 | #define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ | ||
| 114 | #define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ | ||
| 115 | #define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ | ||
| 116 | #define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ | ||
| 117 | #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ | ||
| 118 | |||
| 119 | #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ | ||
| 120 | #define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ | ||
| 121 | #define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ | ||
| 122 | |||
| 123 | /* | ||
| 124 | * Define bit flags in Status Register (USR). | ||
| 125 | */ | ||
| 126 | #define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ | ||
| 127 | #define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ | ||
| 128 | #define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ | ||
| 129 | #define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ | ||
| 130 | #define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ | ||
| 131 | #define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ | ||
| 132 | #define MCFUART_USR_RXFULL 0x02 /* Receiver full */ | ||
| 133 | #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ | ||
| 134 | |||
| 135 | #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ | ||
| 136 | MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) | ||
| 137 | |||
| 138 | /* | ||
| 139 | * Define bit flags in Clock Select Register (UCSR). | ||
| 140 | */ | ||
| 141 | #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ | ||
| 142 | #define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ | ||
| 143 | #define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ | ||
| 144 | |||
| 145 | #define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ | ||
| 146 | #define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ | ||
| 147 | #define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ | ||
| 148 | |||
| 149 | /* | ||
| 150 | * Define bit flags in Command Register (UCR). | ||
| 151 | */ | ||
| 152 | #define MCFUART_UCR_CMDNULL 0x00 /* No command */ | ||
| 153 | #define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ | ||
| 154 | #define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ | ||
| 155 | #define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ | ||
| 156 | #define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ | ||
| 157 | #define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ | ||
| 158 | #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ | ||
| 159 | #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ | ||
| 160 | |||
| 161 | #define MCFUART_UCR_TXNULL 0x00 /* No TX command */ | ||
| 162 | #define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ | ||
| 163 | #define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ | ||
| 164 | #define MCFUART_UCR_RXNULL 0x00 /* No RX command */ | ||
| 165 | #define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ | ||
| 166 | #define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ | ||
| 167 | |||
| 168 | /* | ||
| 169 | * Define bit flags in Input Port Change Register (UIPCR). | ||
| 170 | */ | ||
| 171 | #define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ | ||
| 172 | #define MCFUART_UIPCR_CTS 0x01 /* CTS value */ | ||
| 173 | |||
| 174 | /* | ||
| 175 | * Define bit flags in Input Port Register (UIP). | ||
| 176 | */ | ||
| 177 | #define MCFUART_UIPR_CTS 0x01 /* CTS value */ | ||
| 178 | |||
| 179 | /* | ||
| 180 | * Define bit flags in Output Port Registers (UOP). | ||
| 181 | * Clear bit by writing to UOP0, set by writing to UOP1. | ||
| 182 | */ | ||
| 183 | #define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ | ||
| 184 | |||
| 185 | /* | ||
| 186 | * Define bit flags in the Auxiliary Control Register (UACR). | ||
| 187 | */ | ||
| 188 | #define MCFUART_UACR_IEC 0x01 /* Input enable control */ | ||
| 189 | |||
| 190 | /* | ||
| 191 | * Define bit flags in Interrupt Status Register (UISR). | ||
| 192 | * These same bits are used for the Interrupt Mask Register (UIMR). | ||
| 193 | */ | ||
| 194 | #define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ | ||
| 195 | #define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ | ||
| 196 | #define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ | ||
| 197 | #define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ | ||
| 198 | |||
| 199 | #ifdef CONFIG_M5272 | ||
| 200 | /* | ||
| 201 | * Define bit flags in the Transmitter FIFO Register (UTF). | ||
| 202 | */ | ||
| 203 | #define MCFUART_UTF_TXB 0x1f /* Transmitter data level */ | ||
| 204 | #define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */ | ||
| 205 | #define MCFUART_UTF_TXS 0xc0 /* Transmitter status */ | ||
| 206 | |||
| 207 | /* | ||
| 208 | * Define bit flags in the Receiver FIFO Register (URF). | ||
| 209 | */ | ||
| 210 | #define MCFUART_URF_RXB 0x1f /* Receiver data level */ | ||
| 211 | #define MCFUART_URF_FULL 0x20 /* Receiver fifo full */ | ||
| 212 | #define MCFUART_URF_RXS 0xc0 /* Receiver status */ | ||
| 213 | #endif | ||
| 214 | |||
| 215 | /****************************************************************************/ | ||
| 216 | #endif /* mcfuart_h */ | ||
diff --git a/arch/m68k/include/asm/mcfwdebug.h b/arch/m68k/include/asm/mcfwdebug.h new file mode 100644 index 000000000000..27f70e45d700 --- /dev/null +++ b/arch/m68k/include/asm/mcfwdebug.h | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * mcfdebug.h -- ColdFire Debug Module support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 2001, Lineo Inc. (www.lineo.com) | ||
| 7 | */ | ||
| 8 | |||
| 9 | /****************************************************************************/ | ||
| 10 | #ifndef mcfdebug_h | ||
| 11 | #define mcfdebug_h | ||
| 12 | /****************************************************************************/ | ||
| 13 | |||
| 14 | /* Define the debug module registers */ | ||
| 15 | #define MCFDEBUG_CSR 0x0 /* Configuration status */ | ||
| 16 | #define MCFDEBUG_BAAR 0x5 /* BDM address attribute */ | ||
| 17 | #define MCFDEBUG_AATR 0x6 /* Address attribute trigger */ | ||
| 18 | #define MCFDEBUG_TDR 0x7 /* Trigger definition */ | ||
| 19 | #define MCFDEBUG_PBR 0x8 /* PC breakpoint */ | ||
| 20 | #define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */ | ||
| 21 | #define MCFDEBUG_ABHR 0xc /* High address breakpoint */ | ||
| 22 | #define MCFDEBUG_ABLR 0xd /* Low address breakpoint */ | ||
| 23 | #define MCFDEBUG_DBR 0xe /* Data breakpoint */ | ||
| 24 | #define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */ | ||
| 25 | |||
| 26 | /* Define some handy constants for the trigger definition register */ | ||
| 27 | #define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */ | ||
| 28 | #define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */ | ||
| 29 | #define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */ | ||
| 30 | #define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */ | ||
| 31 | #define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */ | ||
| 32 | #define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */ | ||
| 33 | #define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */ | ||
| 34 | #define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */ | ||
| 35 | #define MCFDEBUG_TDR_EDLW2 0x10000000 | ||
| 36 | #define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */ | ||
| 37 | #define MCFDEBUG_TDR_EDWL2 0x08000000 | ||
| 38 | #define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */ | ||
| 39 | #define MCFDEBUG_TDR_EDWU2 0x04000000 | ||
| 40 | #define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */ | ||
| 41 | #define MCFDEBUG_TDR_EDLL2 0x02000000 | ||
| 42 | #define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */ | ||
| 43 | #define MCFDEBUG_TDR_EDLM2 0x01000000 | ||
| 44 | #define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */ | ||
| 45 | #define MCFDEBUG_TDR_EDUM2 0x00800000 | ||
| 46 | #define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */ | ||
| 47 | #define MCFDEBUG_TDR_EDUU2 0x00400000 | ||
| 48 | #define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */ | ||
| 49 | #define MCFDEBUG_TDR_DI2 0x00200000 | ||
| 50 | #define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */ | ||
| 51 | #define MCFDEBUG_TDR_EAI2 0x00100000 | ||
| 52 | #define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */ | ||
| 53 | #define MCFDEBUG_TDR_EAR2 0x00080000 | ||
| 54 | #define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */ | ||
| 55 | #define MCFDEBUG_TDR_EAL2 0x00040000 | ||
| 56 | #define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */ | ||
| 57 | #define MCFDEBUG_TDR_EPC2 0x00020000 | ||
| 58 | #define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */ | ||
| 59 | #define MCFDEBUG_TDR_PCI2 0x00010000 | ||
| 60 | |||
| 61 | /* Constants for the address attribute trigger register */ | ||
| 62 | #define MCFDEBUG_AAR_RESET 0x00000005 | ||
| 63 | /* Fields not yet implemented */ | ||
| 64 | |||
| 65 | /* And some definitions for the writable sections of the CSR */ | ||
| 66 | #define MCFDEBUG_CSR_RESET 0x00100000 | ||
| 67 | #define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */ | ||
| 68 | #define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */ | ||
| 69 | #define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */ | ||
| 70 | #define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */ | ||
| 71 | #define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */ | ||
| 72 | #define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */ | ||
| 73 | #define MCFDEBUG_CSR_DDC_WRITE 0x00001000 | ||
| 74 | #define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */ | ||
| 75 | #define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */ | ||
| 76 | #define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */ | ||
| 77 | #define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */ | ||
| 78 | #define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */ | ||
| 79 | #define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */ | ||
| 80 | #define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */ | ||
| 81 | |||
| 82 | /* Constants for the BDM address attribute register */ | ||
| 83 | #define MCFDEBUG_BAAR_RESET 0x00000005 | ||
| 84 | /* Fields not yet implemented */ | ||
| 85 | |||
| 86 | |||
| 87 | /* This routine wrappers up the wdebug asm instruction so that the register | ||
| 88 | * and value can be relatively easily specified. The biggest hassle here is | ||
| 89 | * that the debug module instructions (2 longs) must be long word aligned and | ||
| 90 | * some pointer fiddling is performed to ensure this. | ||
| 91 | */ | ||
| 92 | static inline void wdebug(int reg, unsigned long data) { | ||
| 93 | unsigned short dbg_spc[6]; | ||
| 94 | unsigned short *dbg; | ||
| 95 | |||
| 96 | // Force alignment to long word boundary | ||
| 97 | dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc); | ||
| 98 | |||
| 99 | // Build up the debug instruction | ||
| 100 | dbg[0] = 0x2c80 | (reg & 0xf); | ||
| 101 | dbg[1] = (data >> 16) & 0xffff; | ||
| 102 | dbg[2] = data & 0xffff; | ||
| 103 | dbg[3] = 0; | ||
| 104 | |||
| 105 | // Perform the wdebug instruction | ||
| 106 | #if 0 | ||
| 107 | // This strain is for gas which doesn't have the wdebug instructions defined | ||
| 108 | asm( "move.l %0, %%a0\n\t" | ||
| 109 | ".word 0xfbd0\n\t" | ||
| 110 | ".word 0x0003\n\t" | ||
| 111 | :: "g" (dbg) : "a0"); | ||
| 112 | #else | ||
| 113 | // And this is for when it does | ||
| 114 | asm( "wdebug (%0)" :: "a" (dbg)); | ||
| 115 | #endif | ||
| 116 | } | ||
| 117 | |||
| 118 | #endif | ||
diff --git a/arch/m68k/include/asm/md.h b/arch/m68k/include/asm/md.h new file mode 100644 index 000000000000..d2f78f226f3d --- /dev/null +++ b/arch/m68k/include/asm/md.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * md.h: High speed xor_block operation for RAID4/5 | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef __ASM_MD_H | ||
| 7 | #define __ASM_MD_H | ||
| 8 | |||
| 9 | /* #define HAVE_ARCH_XORBLOCK */ | ||
| 10 | |||
| 11 | #define MD_XORBLOCK_ALIGNMENT sizeof(long) | ||
| 12 | |||
| 13 | #endif /* __ASM_MD_H */ | ||
diff --git a/arch/m68k/include/asm/mman.h b/arch/m68k/include/asm/mman.h new file mode 100644 index 000000000000..1626d37f4898 --- /dev/null +++ b/arch/m68k/include/asm/mman.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | #ifndef __M68K_MMAN_H__ | ||
| 2 | #define __M68K_MMAN_H__ | ||
| 3 | |||
| 4 | #include <asm-generic/mman.h> | ||
| 5 | |||
| 6 | #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ | ||
| 7 | #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ | ||
| 8 | #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ | ||
| 9 | #define MAP_LOCKED 0x2000 /* pages are locked */ | ||
| 10 | #define MAP_NORESERVE 0x4000 /* don't check for reservations */ | ||
| 11 | #define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ | ||
| 12 | #define MAP_NONBLOCK 0x10000 /* do not block on IO */ | ||
| 13 | |||
| 14 | #define MCL_CURRENT 1 /* lock all current mappings */ | ||
| 15 | #define MCL_FUTURE 2 /* lock all future mappings */ | ||
| 16 | |||
| 17 | #endif /* __M68K_MMAN_H__ */ | ||
diff --git a/arch/m68k/include/asm/mmu.h b/arch/m68k/include/asm/mmu.h new file mode 100644 index 000000000000..a81d3946675f --- /dev/null +++ b/arch/m68k/include/asm/mmu.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "mmu_no.h" | ||
| 3 | #else | ||
| 4 | #include "mmu_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/mmu_context.h b/arch/m68k/include/asm/mmu_context.h new file mode 100644 index 000000000000..b440928fc6c7 --- /dev/null +++ b/arch/m68k/include/asm/mmu_context.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "mmu_context_no.h" | ||
| 3 | #else | ||
| 4 | #include "mmu_context_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/mmu_context_mm.h b/arch/m68k/include/asm/mmu_context_mm.h new file mode 100644 index 000000000000..894dacbcee14 --- /dev/null +++ b/arch/m68k/include/asm/mmu_context_mm.h | |||
| @@ -0,0 +1,154 @@ | |||
| 1 | #ifndef __M68K_MMU_CONTEXT_H | ||
| 2 | #define __M68K_MMU_CONTEXT_H | ||
| 3 | |||
| 4 | #include <asm-generic/mm_hooks.h> | ||
| 5 | |||
| 6 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | ||
| 7 | { | ||
| 8 | } | ||
| 9 | |||
| 10 | #ifndef CONFIG_SUN3 | ||
| 11 | |||
| 12 | #include <asm/setup.h> | ||
| 13 | #include <asm/page.h> | ||
| 14 | #include <asm/pgalloc.h> | ||
| 15 | |||
| 16 | static inline int init_new_context(struct task_struct *tsk, | ||
| 17 | struct mm_struct *mm) | ||
| 18 | { | ||
| 19 | mm->context = virt_to_phys(mm->pgd); | ||
| 20 | return 0; | ||
| 21 | } | ||
| 22 | |||
| 23 | #define destroy_context(mm) do { } while(0) | ||
| 24 | |||
| 25 | static inline void switch_mm_0230(struct mm_struct *mm) | ||
| 26 | { | ||
| 27 | unsigned long crp[2] = { | ||
| 28 | 0x80000000 | _PAGE_TABLE, mm->context | ||
| 29 | }; | ||
| 30 | unsigned long tmp; | ||
| 31 | |||
| 32 | asm volatile (".chip 68030"); | ||
| 33 | |||
| 34 | /* flush MC68030/MC68020 caches (they are virtually addressed) */ | ||
| 35 | asm volatile ( | ||
| 36 | "movec %%cacr,%0;" | ||
| 37 | "orw %1,%0; " | ||
| 38 | "movec %0,%%cacr" | ||
| 39 | : "=d" (tmp) : "di" (FLUSH_I_AND_D)); | ||
| 40 | |||
| 41 | /* Switch the root pointer. For a 030-only kernel, | ||
| 42 | * avoid flushing the whole ATC, we only need to | ||
| 43 | * flush the user entries. The 68851 does this by | ||
| 44 | * itself. Avoid a runtime check here. | ||
| 45 | */ | ||
| 46 | asm volatile ( | ||
| 47 | #ifdef CPU_M68030_ONLY | ||
| 48 | "pmovefd %0,%%crp; " | ||
| 49 | "pflush #0,#4" | ||
| 50 | #else | ||
| 51 | "pmove %0,%%crp" | ||
| 52 | #endif | ||
| 53 | : : "m" (crp[0])); | ||
| 54 | |||
| 55 | asm volatile (".chip 68k"); | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline void switch_mm_0460(struct mm_struct *mm) | ||
| 59 | { | ||
| 60 | asm volatile (".chip 68040"); | ||
| 61 | |||
| 62 | /* flush address translation cache (user entries) */ | ||
| 63 | asm volatile ("pflushan"); | ||
| 64 | |||
| 65 | /* switch the root pointer */ | ||
| 66 | asm volatile ("movec %0,%%urp" : : "r" (mm->context)); | ||
| 67 | |||
| 68 | if (CPU_IS_060) { | ||
| 69 | unsigned long tmp; | ||
| 70 | |||
| 71 | /* clear user entries in the branch cache */ | ||
| 72 | asm volatile ( | ||
| 73 | "movec %%cacr,%0; " | ||
| 74 | "orl %1,%0; " | ||
| 75 | "movec %0,%%cacr" | ||
| 76 | : "=d" (tmp): "di" (0x00200000)); | ||
| 77 | } | ||
| 78 | |||
| 79 | asm volatile (".chip 68k"); | ||
| 80 | } | ||
| 81 | |||
| 82 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) | ||
| 83 | { | ||
| 84 | if (prev != next) { | ||
| 85 | if (CPU_IS_020_OR_030) | ||
| 86 | switch_mm_0230(next); | ||
| 87 | else | ||
| 88 | switch_mm_0460(next); | ||
| 89 | } | ||
| 90 | } | ||
| 91 | |||
| 92 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
| 93 | |||
| 94 | static inline void activate_mm(struct mm_struct *prev_mm, | ||
| 95 | struct mm_struct *next_mm) | ||
| 96 | { | ||
| 97 | next_mm->context = virt_to_phys(next_mm->pgd); | ||
| 98 | |||
| 99 | if (CPU_IS_020_OR_030) | ||
| 100 | switch_mm_0230(next_mm); | ||
| 101 | else | ||
| 102 | switch_mm_0460(next_mm); | ||
| 103 | } | ||
| 104 | |||
| 105 | #else /* CONFIG_SUN3 */ | ||
| 106 | #include <asm/sun3mmu.h> | ||
| 107 | #include <linux/sched.h> | ||
| 108 | |||
| 109 | extern unsigned long get_free_context(struct mm_struct *mm); | ||
| 110 | extern void clear_context(unsigned long context); | ||
| 111 | |||
| 112 | /* set the context for a new task to unmapped */ | ||
| 113 | static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) | ||
| 114 | { | ||
| 115 | mm->context = SUN3_INVALID_CONTEXT; | ||
| 116 | return 0; | ||
| 117 | } | ||
| 118 | |||
| 119 | /* find the context given to this process, and if it hasn't already | ||
| 120 | got one, go get one for it. */ | ||
| 121 | static inline void get_mmu_context(struct mm_struct *mm) | ||
| 122 | { | ||
| 123 | if(mm->context == SUN3_INVALID_CONTEXT) | ||
| 124 | mm->context = get_free_context(mm); | ||
| 125 | } | ||
| 126 | |||
| 127 | /* flush context if allocated... */ | ||
| 128 | static inline void destroy_context(struct mm_struct *mm) | ||
| 129 | { | ||
| 130 | if(mm->context != SUN3_INVALID_CONTEXT) | ||
| 131 | clear_context(mm->context); | ||
| 132 | } | ||
| 133 | |||
| 134 | static inline void activate_context(struct mm_struct *mm) | ||
| 135 | { | ||
| 136 | get_mmu_context(mm); | ||
| 137 | sun3_put_context(mm->context); | ||
| 138 | } | ||
| 139 | |||
| 140 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) | ||
| 141 | { | ||
| 142 | activate_context(tsk->mm); | ||
| 143 | } | ||
| 144 | |||
| 145 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
| 146 | |||
| 147 | static inline void activate_mm(struct mm_struct *prev_mm, | ||
| 148 | struct mm_struct *next_mm) | ||
| 149 | { | ||
| 150 | activate_context(next_mm); | ||
| 151 | } | ||
| 152 | |||
| 153 | #endif | ||
| 154 | #endif | ||
diff --git a/arch/m68k/include/asm/mmu_context_no.h b/arch/m68k/include/asm/mmu_context_no.h new file mode 100644 index 000000000000..9ccee4278c97 --- /dev/null +++ b/arch/m68k/include/asm/mmu_context_no.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | #ifndef __M68KNOMMU_MMU_CONTEXT_H | ||
| 2 | #define __M68KNOMMU_MMU_CONTEXT_H | ||
| 3 | |||
| 4 | #include <asm/setup.h> | ||
| 5 | #include <asm/page.h> | ||
| 6 | #include <asm/pgalloc.h> | ||
| 7 | #include <asm-generic/mm_hooks.h> | ||
| 8 | |||
| 9 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | ||
| 10 | { | ||
| 11 | } | ||
| 12 | |||
| 13 | static inline int | ||
| 14 | init_new_context(struct task_struct *tsk, struct mm_struct *mm) | ||
| 15 | { | ||
| 16 | // mm->context = virt_to_phys(mm->pgd); | ||
| 17 | return(0); | ||
| 18 | } | ||
| 19 | |||
| 20 | #define destroy_context(mm) do { } while(0) | ||
| 21 | |||
| 22 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) | ||
| 23 | { | ||
| 24 | } | ||
| 25 | |||
| 26 | #define deactivate_mm(tsk,mm) do { } while (0) | ||
| 27 | |||
| 28 | static inline void activate_mm(struct mm_struct *prev_mm, | ||
| 29 | struct mm_struct *next_mm) | ||
| 30 | { | ||
| 31 | } | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/arch/m68k/include/asm/mmu_mm.h b/arch/m68k/include/asm/mmu_mm.h new file mode 100644 index 000000000000..ccd36d26615a --- /dev/null +++ b/arch/m68k/include/asm/mmu_mm.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __MMU_H | ||
| 2 | #define __MMU_H | ||
| 3 | |||
| 4 | /* Default "unsigned long" context */ | ||
| 5 | typedef unsigned long mm_context_t; | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/arch/m68k/include/asm/mmu_no.h b/arch/m68k/include/asm/mmu_no.h new file mode 100644 index 000000000000..e2da1e6f09fe --- /dev/null +++ b/arch/m68k/include/asm/mmu_no.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | #ifndef __M68KNOMMU_MMU_H | ||
| 2 | #define __M68KNOMMU_MMU_H | ||
| 3 | |||
| 4 | /* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */ | ||
| 5 | |||
| 6 | typedef struct { | ||
| 7 | unsigned long end_brk; | ||
| 8 | } mm_context_t; | ||
| 9 | |||
| 10 | #endif /* __M68KNOMMU_MMU_H */ | ||
diff --git a/arch/m68k/include/asm/mmzone.h b/arch/m68k/include/asm/mmzone.h new file mode 100644 index 000000000000..e1f1ec7b7006 --- /dev/null +++ b/arch/m68k/include/asm/mmzone.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | #ifndef _ASM_M68K_MMZONE_H_ | ||
| 2 | #define _ASM_M68K_MMZONE_H_ | ||
| 3 | |||
| 4 | extern pg_data_t pg_data_map[]; | ||
| 5 | |||
| 6 | #define NODE_DATA(nid) (&pg_data_map[nid]) | ||
| 7 | #define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map) | ||
| 8 | |||
| 9 | #endif /* _ASM_M68K_MMZONE_H_ */ | ||
diff --git a/arch/m68k/include/asm/module.h b/arch/m68k/include/asm/module.h new file mode 100644 index 000000000000..79b59d137dd0 --- /dev/null +++ b/arch/m68k/include/asm/module.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "module_no.h" | ||
| 3 | #else | ||
| 4 | #include "module_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/module_mm.h b/arch/m68k/include/asm/module_mm.h new file mode 100644 index 000000000000..382d20a6fc18 --- /dev/null +++ b/arch/m68k/include/asm/module_mm.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | #ifndef _ASM_M68K_MODULE_H | ||
| 2 | #define _ASM_M68K_MODULE_H | ||
| 3 | |||
| 4 | struct mod_arch_specific { | ||
| 5 | struct m68k_fixup_info *fixup_start, *fixup_end; | ||
| 6 | }; | ||
| 7 | |||
| 8 | #define MODULE_ARCH_INIT { \ | ||
| 9 | .fixup_start = __start_fixup, \ | ||
| 10 | .fixup_end = __stop_fixup, \ | ||
| 11 | } | ||
| 12 | |||
| 13 | #define Elf_Shdr Elf32_Shdr | ||
| 14 | #define Elf_Sym Elf32_Sym | ||
| 15 | #define Elf_Ehdr Elf32_Ehdr | ||
| 16 | |||
| 17 | |||
| 18 | enum m68k_fixup_type { | ||
| 19 | m68k_fixup_memoffset, | ||
| 20 | m68k_fixup_vnode_shift, | ||
| 21 | }; | ||
| 22 | |||
| 23 | struct m68k_fixup_info { | ||
| 24 | enum m68k_fixup_type type; | ||
| 25 | void *addr; | ||
| 26 | }; | ||
| 27 | |||
| 28 | #define m68k_fixup(type, addr) \ | ||
| 29 | " .section \".m68k_fixup\",\"aw\"\n" \ | ||
| 30 | " .long " #type "," #addr "\n" \ | ||
| 31 | " .previous\n" | ||
| 32 | |||
| 33 | extern struct m68k_fixup_info __start_fixup[], __stop_fixup[]; | ||
| 34 | |||
| 35 | struct module; | ||
| 36 | extern void module_fixup(struct module *mod, struct m68k_fixup_info *start, | ||
| 37 | struct m68k_fixup_info *end); | ||
| 38 | |||
| 39 | #endif /* _ASM_M68K_MODULE_H */ | ||
diff --git a/arch/m68k/include/asm/module_no.h b/arch/m68k/include/asm/module_no.h new file mode 100644 index 000000000000..2e45ab50b232 --- /dev/null +++ b/arch/m68k/include/asm/module_no.h | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | #ifndef ASM_M68KNOMMU_MODULE_H | ||
| 2 | #define ASM_M68KNOMMU_MODULE_H | ||
| 3 | |||
| 4 | struct mod_arch_specific { | ||
| 5 | }; | ||
| 6 | |||
| 7 | #define Elf_Shdr Elf32_Shdr | ||
| 8 | #define Elf_Sym Elf32_Sym | ||
| 9 | #define Elf_Ehdr Elf32_Ehdr | ||
| 10 | |||
| 11 | #endif /* ASM_M68KNOMMU_MODULE_H */ | ||
diff --git a/arch/m68k/include/asm/motorola_pgalloc.h b/arch/m68k/include/asm/motorola_pgalloc.h new file mode 100644 index 000000000000..d08bf6261df8 --- /dev/null +++ b/arch/m68k/include/asm/motorola_pgalloc.h | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | #ifndef _MOTOROLA_PGALLOC_H | ||
| 2 | #define _MOTOROLA_PGALLOC_H | ||
| 3 | |||
| 4 | #include <asm/tlb.h> | ||
| 5 | #include <asm/tlbflush.h> | ||
| 6 | |||
| 7 | extern pmd_t *get_pointer_table(void); | ||
| 8 | extern int free_pointer_table(pmd_t *); | ||
| 9 | |||
| 10 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) | ||
| 11 | { | ||
| 12 | pte_t *pte; | ||
| 13 | |||
| 14 | pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); | ||
| 15 | if (pte) { | ||
| 16 | __flush_page_to_ram(pte); | ||
| 17 | flush_tlb_kernel_page(pte); | ||
| 18 | nocache_page(pte); | ||
| 19 | } | ||
| 20 | |||
| 21 | return pte; | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | ||
| 25 | { | ||
| 26 | cache_page(pte); | ||
| 27 | free_page((unsigned long) pte); | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) | ||
| 31 | { | ||
| 32 | struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); | ||
| 33 | pte_t *pte; | ||
| 34 | |||
| 35 | if(!page) | ||
| 36 | return NULL; | ||
| 37 | |||
| 38 | pte = kmap(page); | ||
| 39 | if (pte) { | ||
| 40 | __flush_page_to_ram(pte); | ||
| 41 | flush_tlb_kernel_page(pte); | ||
| 42 | nocache_page(pte); | ||
| 43 | } | ||
| 44 | kunmap(pte); | ||
| 45 | pgtable_page_ctor(page); | ||
| 46 | return page; | ||
| 47 | } | ||
| 48 | |||
| 49 | static inline void pte_free(struct mm_struct *mm, pgtable_t page) | ||
| 50 | { | ||
| 51 | pgtable_page_dtor(page); | ||
| 52 | cache_page(kmap(page)); | ||
| 53 | kunmap(page); | ||
| 54 | __free_page(page); | ||
| 55 | } | ||
| 56 | |||
| 57 | static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page) | ||
| 58 | { | ||
| 59 | pgtable_page_dtor(page); | ||
| 60 | cache_page(kmap(page)); | ||
| 61 | kunmap(page); | ||
| 62 | __free_page(page); | ||
| 63 | } | ||
| 64 | |||
| 65 | |||
| 66 | static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address) | ||
| 67 | { | ||
| 68 | return get_pointer_table(); | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline int pmd_free(struct mm_struct *mm, pmd_t *pmd) | ||
| 72 | { | ||
| 73 | return free_pointer_table(pmd); | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline int __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) | ||
| 77 | { | ||
| 78 | return free_pointer_table(pmd); | ||
| 79 | } | ||
| 80 | |||
| 81 | |||
| 82 | static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) | ||
| 83 | { | ||
| 84 | pmd_free(mm, (pmd_t *)pgd); | ||
| 85 | } | ||
| 86 | |||
| 87 | static inline pgd_t *pgd_alloc(struct mm_struct *mm) | ||
| 88 | { | ||
| 89 | return (pgd_t *)get_pointer_table(); | ||
| 90 | } | ||
| 91 | |||
| 92 | |||
| 93 | static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) | ||
| 94 | { | ||
| 95 | pmd_set(pmd, pte); | ||
| 96 | } | ||
| 97 | |||
| 98 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) | ||
| 99 | { | ||
| 100 | pmd_set(pmd, page_address(page)); | ||
| 101 | } | ||
| 102 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 103 | |||
| 104 | static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd) | ||
| 105 | { | ||
| 106 | pgd_set(pgd, pmd); | ||
| 107 | } | ||
| 108 | |||
| 109 | #endif /* _MOTOROLA_PGALLOC_H */ | ||
diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h new file mode 100644 index 000000000000..8e9a8a754dde --- /dev/null +++ b/arch/m68k/include/asm/motorola_pgtable.h | |||
| @@ -0,0 +1,291 @@ | |||
| 1 | #ifndef _MOTOROLA_PGTABLE_H | ||
| 2 | #define _MOTOROLA_PGTABLE_H | ||
| 3 | |||
| 4 | |||
| 5 | /* | ||
| 6 | * Definitions for MMU descriptors | ||
| 7 | */ | ||
| 8 | #define _PAGE_PRESENT 0x001 | ||
| 9 | #define _PAGE_SHORT 0x002 | ||
| 10 | #define _PAGE_RONLY 0x004 | ||
| 11 | #define _PAGE_ACCESSED 0x008 | ||
| 12 | #define _PAGE_DIRTY 0x010 | ||
| 13 | #define _PAGE_SUPER 0x080 /* 68040 supervisor only */ | ||
| 14 | #define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ | ||
| 15 | #define _PAGE_NOCACHE030 0x040 /* 68030 no-cache mode */ | ||
| 16 | #define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */ | ||
| 17 | #define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */ | ||
| 18 | #define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */ | ||
| 19 | #define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */ | ||
| 20 | |||
| 21 | #define _DESCTYPE_MASK 0x003 | ||
| 22 | |||
| 23 | #define _CACHEMASK040 (~0x060) | ||
| 24 | #define _TABLE_MASK (0xfffffe00) | ||
| 25 | |||
| 26 | #define _PAGE_TABLE (_PAGE_SHORT) | ||
| 27 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NOCACHE) | ||
| 28 | |||
| 29 | #define _PAGE_PROTNONE 0x004 | ||
| 30 | #define _PAGE_FILE 0x008 /* pagecache or swap? */ | ||
| 31 | |||
| 32 | #ifndef __ASSEMBLY__ | ||
| 33 | |||
| 34 | /* This is the cache mode to be used for pages containing page descriptors for | ||
| 35 | * processors >= '040. It is in pte_mknocache(), and the variable is defined | ||
| 36 | * and initialized in head.S */ | ||
| 37 | extern int m68k_pgtable_cachemode; | ||
| 38 | |||
| 39 | /* This is the cache mode for normal pages, for supervisor access on | ||
| 40 | * processors >= '040. It is used in pte_mkcache(), and the variable is | ||
| 41 | * defined and initialized in head.S */ | ||
| 42 | |||
| 43 | #if defined(CPU_M68060_ONLY) && defined(CONFIG_060_WRITETHROUGH) | ||
| 44 | #define m68k_supervisor_cachemode _PAGE_CACHE040W | ||
| 45 | #elif defined(CPU_M68040_OR_M68060_ONLY) | ||
| 46 | #define m68k_supervisor_cachemode _PAGE_CACHE040 | ||
| 47 | #elif defined(CPU_M68020_OR_M68030_ONLY) | ||
| 48 | #define m68k_supervisor_cachemode 0 | ||
| 49 | #else | ||
| 50 | extern int m68k_supervisor_cachemode; | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #if defined(CPU_M68040_OR_M68060_ONLY) | ||
| 54 | #define mm_cachebits _PAGE_CACHE040 | ||
| 55 | #elif defined(CPU_M68020_OR_M68030_ONLY) | ||
| 56 | #define mm_cachebits 0 | ||
| 57 | #else | ||
| 58 | extern unsigned long mm_cachebits; | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED | mm_cachebits) | ||
| 62 | #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | mm_cachebits) | ||
| 63 | #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits) | ||
| 64 | #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits) | ||
| 65 | #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | mm_cachebits) | ||
| 66 | |||
| 67 | /* Alternate definitions that are compile time constants, for | ||
| 68 | initializing protection_map. The cachebits are fixed later. */ | ||
| 69 | #define PAGE_NONE_C __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED) | ||
| 70 | #define PAGE_SHARED_C __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) | ||
| 71 | #define PAGE_COPY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED) | ||
| 72 | #define PAGE_READONLY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED) | ||
| 73 | |||
| 74 | /* | ||
| 75 | * The m68k can't do page protection for execute, and considers that the same are read. | ||
| 76 | * Also, write permissions imply read permissions. This is the closest we can get.. | ||
| 77 | */ | ||
| 78 | #define __P000 PAGE_NONE_C | ||
| 79 | #define __P001 PAGE_READONLY_C | ||
| 80 | #define __P010 PAGE_COPY_C | ||
| 81 | #define __P011 PAGE_COPY_C | ||
| 82 | #define __P100 PAGE_READONLY_C | ||
| 83 | #define __P101 PAGE_READONLY_C | ||
| 84 | #define __P110 PAGE_COPY_C | ||
| 85 | #define __P111 PAGE_COPY_C | ||
| 86 | |||
| 87 | #define __S000 PAGE_NONE_C | ||
| 88 | #define __S001 PAGE_READONLY_C | ||
| 89 | #define __S010 PAGE_SHARED_C | ||
| 90 | #define __S011 PAGE_SHARED_C | ||
| 91 | #define __S100 PAGE_READONLY_C | ||
| 92 | #define __S101 PAGE_READONLY_C | ||
| 93 | #define __S110 PAGE_SHARED_C | ||
| 94 | #define __S111 PAGE_SHARED_C | ||
| 95 | |||
| 96 | /* | ||
| 97 | * Conversion functions: convert a page and protection to a page entry, | ||
| 98 | * and a page entry and page directory to the page they refer to. | ||
| 99 | */ | ||
| 100 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | ||
| 101 | |||
| 102 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
| 103 | { | ||
| 104 | pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); | ||
| 105 | return pte; | ||
| 106 | } | ||
| 107 | |||
| 108 | static inline void pmd_set(pmd_t *pmdp, pte_t *ptep) | ||
| 109 | { | ||
| 110 | unsigned long ptbl = virt_to_phys(ptep) | _PAGE_TABLE | _PAGE_ACCESSED; | ||
| 111 | unsigned long *ptr = pmdp->pmd; | ||
| 112 | short i = 16; | ||
| 113 | while (--i >= 0) { | ||
| 114 | *ptr++ = ptbl; | ||
| 115 | ptbl += (sizeof(pte_t)*PTRS_PER_PTE/16); | ||
| 116 | } | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) | ||
| 120 | { | ||
| 121 | pgd_val(*pgdp) = _PAGE_TABLE | _PAGE_ACCESSED | __pa(pmdp); | ||
| 122 | } | ||
| 123 | |||
| 124 | #define __pte_page(pte) ((unsigned long)__va(pte_val(pte) & PAGE_MASK)) | ||
| 125 | #define __pmd_page(pmd) ((unsigned long)__va(pmd_val(pmd) & _TABLE_MASK)) | ||
| 126 | #define __pgd_page(pgd) ((unsigned long)__va(pgd_val(pgd) & _TABLE_MASK)) | ||
| 127 | |||
| 128 | |||
| 129 | #define pte_none(pte) (!pte_val(pte)) | ||
| 130 | #define pte_present(pte) (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROTNONE)) | ||
| 131 | #define pte_clear(mm,addr,ptep) ({ pte_val(*(ptep)) = 0; }) | ||
| 132 | |||
| 133 | #define pte_page(pte) virt_to_page(__va(pte_val(pte))) | ||
| 134 | #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) | ||
| 135 | #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
| 136 | |||
| 137 | #define pmd_none(pmd) (!pmd_val(pmd)) | ||
| 138 | #define pmd_bad(pmd) ((pmd_val(pmd) & _DESCTYPE_MASK) != _PAGE_TABLE) | ||
| 139 | #define pmd_present(pmd) (pmd_val(pmd) & _PAGE_TABLE) | ||
| 140 | #define pmd_clear(pmdp) ({ \ | ||
| 141 | unsigned long *__ptr = pmdp->pmd; \ | ||
| 142 | short __i = 16; \ | ||
| 143 | while (--__i >= 0) \ | ||
| 144 | *__ptr++ = 0; \ | ||
| 145 | }) | ||
| 146 | #define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) | ||
| 147 | |||
| 148 | |||
| 149 | #define pgd_none(pgd) (!pgd_val(pgd)) | ||
| 150 | #define pgd_bad(pgd) ((pgd_val(pgd) & _DESCTYPE_MASK) != _PAGE_TABLE) | ||
| 151 | #define pgd_present(pgd) (pgd_val(pgd) & _PAGE_TABLE) | ||
| 152 | #define pgd_clear(pgdp) ({ pgd_val(*pgdp) = 0; }) | ||
| 153 | #define pgd_page(pgd) (mem_map + ((unsigned long)(__va(pgd_val(pgd)) - PAGE_OFFSET) >> PAGE_SHIFT)) | ||
| 154 | |||
| 155 | #define pte_ERROR(e) \ | ||
| 156 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | ||
| 157 | #define pmd_ERROR(e) \ | ||
| 158 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | ||
| 159 | #define pgd_ERROR(e) \ | ||
| 160 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | ||
| 161 | |||
| 162 | |||
| 163 | /* | ||
| 164 | * The following only work if pte_present() is true. | ||
| 165 | * Undefined behaviour if not.. | ||
| 166 | */ | ||
| 167 | static inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_RONLY); } | ||
| 168 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } | ||
| 169 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } | ||
| 170 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } | ||
| 171 | static inline int pte_special(pte_t pte) { return 0; } | ||
| 172 | |||
| 173 | static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_RONLY; return pte; } | ||
| 174 | static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } | ||
| 175 | static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } | ||
| 176 | static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_RONLY; return pte; } | ||
| 177 | static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } | ||
| 178 | static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } | ||
| 179 | static inline pte_t pte_mknocache(pte_t pte) | ||
| 180 | { | ||
| 181 | pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_pgtable_cachemode; | ||
| 182 | return pte; | ||
| 183 | } | ||
| 184 | static inline pte_t pte_mkcache(pte_t pte) | ||
| 185 | { | ||
| 186 | pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_supervisor_cachemode; | ||
| 187 | return pte; | ||
| 188 | } | ||
| 189 | static inline pte_t pte_mkspecial(pte_t pte) { return pte; } | ||
| 190 | |||
| 191 | #define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address)) | ||
| 192 | |||
| 193 | #define pgd_index(address) ((address) >> PGDIR_SHIFT) | ||
| 194 | |||
| 195 | /* to find an entry in a page-table-directory */ | ||
| 196 | static inline pgd_t *pgd_offset(const struct mm_struct *mm, | ||
| 197 | unsigned long address) | ||
| 198 | { | ||
| 199 | return mm->pgd + pgd_index(address); | ||
| 200 | } | ||
| 201 | |||
| 202 | #define swapper_pg_dir kernel_pg_dir | ||
| 203 | extern pgd_t kernel_pg_dir[128]; | ||
| 204 | |||
| 205 | static inline pgd_t *pgd_offset_k(unsigned long address) | ||
| 206 | { | ||
| 207 | return kernel_pg_dir + (address >> PGDIR_SHIFT); | ||
| 208 | } | ||
| 209 | |||
| 210 | |||
| 211 | /* Find an entry in the second-level page table.. */ | ||
| 212 | static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) | ||
| 213 | { | ||
| 214 | return (pmd_t *)__pgd_page(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PMD-1)); | ||
| 215 | } | ||
| 216 | |||
| 217 | /* Find an entry in the third-level page table.. */ | ||
| 218 | static inline pte_t *pte_offset_kernel(pmd_t *pmdp, unsigned long address) | ||
| 219 | { | ||
| 220 | return (pte_t *)__pmd_page(*pmdp) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); | ||
| 221 | } | ||
| 222 | |||
| 223 | #define pte_offset_map(pmdp,address) ((pte_t *)__pmd_page(*pmdp) + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) | ||
| 224 | #define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address) | ||
| 225 | #define pte_unmap(pte) ((void)0) | ||
| 226 | #define pte_unmap_nested(pte) ((void)0) | ||
| 227 | |||
| 228 | /* | ||
| 229 | * Allocate and free page tables. The xxx_kernel() versions are | ||
| 230 | * used to allocate a kernel page table - this turns on ASN bits | ||
| 231 | * if any. | ||
| 232 | */ | ||
| 233 | |||
| 234 | /* Prior to calling these routines, the page should have been flushed | ||
| 235 | * from both the cache and ATC, or the CPU might not notice that the | ||
| 236 | * cache setting for the page has been changed. -jskov | ||
| 237 | */ | ||
| 238 | static inline void nocache_page(void *vaddr) | ||
| 239 | { | ||
| 240 | unsigned long addr = (unsigned long)vaddr; | ||
| 241 | |||
| 242 | if (CPU_IS_040_OR_060) { | ||
| 243 | pgd_t *dir; | ||
| 244 | pmd_t *pmdp; | ||
| 245 | pte_t *ptep; | ||
| 246 | |||
| 247 | dir = pgd_offset_k(addr); | ||
| 248 | pmdp = pmd_offset(dir, addr); | ||
| 249 | ptep = pte_offset_kernel(pmdp, addr); | ||
| 250 | *ptep = pte_mknocache(*ptep); | ||
| 251 | } | ||
| 252 | } | ||
| 253 | |||
| 254 | static inline void cache_page(void *vaddr) | ||
| 255 | { | ||
| 256 | unsigned long addr = (unsigned long)vaddr; | ||
| 257 | |||
| 258 | if (CPU_IS_040_OR_060) { | ||
| 259 | pgd_t *dir; | ||
| 260 | pmd_t *pmdp; | ||
| 261 | pte_t *ptep; | ||
| 262 | |||
| 263 | dir = pgd_offset_k(addr); | ||
| 264 | pmdp = pmd_offset(dir, addr); | ||
| 265 | ptep = pte_offset_kernel(pmdp, addr); | ||
| 266 | *ptep = pte_mkcache(*ptep); | ||
| 267 | } | ||
| 268 | } | ||
| 269 | |||
| 270 | #define PTE_FILE_MAX_BITS 28 | ||
| 271 | |||
| 272 | static inline unsigned long pte_to_pgoff(pte_t pte) | ||
| 273 | { | ||
| 274 | return pte.pte >> 4; | ||
| 275 | } | ||
| 276 | |||
| 277 | static inline pte_t pgoff_to_pte(unsigned off) | ||
| 278 | { | ||
| 279 | pte_t pte = { (off << 4) + _PAGE_FILE }; | ||
| 280 | return pte; | ||
| 281 | } | ||
| 282 | |||
| 283 | /* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ | ||
| 284 | #define __swp_type(x) (((x).val >> 4) & 0xff) | ||
| 285 | #define __swp_offset(x) ((x).val >> 12) | ||
| 286 | #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 12) }) | ||
| 287 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
| 288 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | ||
| 289 | |||
| 290 | #endif /* !__ASSEMBLY__ */ | ||
| 291 | #endif /* _MOTOROLA_PGTABLE_H */ | ||
diff --git a/arch/m68k/include/asm/movs.h b/arch/m68k/include/asm/movs.h new file mode 100644 index 000000000000..67dbea36960f --- /dev/null +++ b/arch/m68k/include/asm/movs.h | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | #ifndef __MOVS_H__ | ||
| 2 | #define __MOVS_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | ** movs.h | ||
| 6 | ** | ||
| 7 | ** Inline assembly macros to generate movs & related instructions | ||
| 8 | */ | ||
| 9 | |||
| 10 | /* Set DFC register value */ | ||
| 11 | |||
| 12 | #define SET_DFC(x) \ | ||
| 13 | __asm__ __volatile__ (" movec %0,%/dfc" : : "d" (x)); | ||
| 14 | |||
| 15 | /* Get DFC register value */ | ||
| 16 | |||
| 17 | #define GET_DFC(x) \ | ||
| 18 | __asm__ __volatile__ (" movec %/dfc, %0" : "=d" (x) : ); | ||
| 19 | |||
| 20 | /* Set SFC register value */ | ||
| 21 | |||
| 22 | #define SET_SFC(x) \ | ||
| 23 | __asm__ __volatile__ (" movec %0,%/sfc" : : "d" (x)); | ||
| 24 | |||
| 25 | /* Get SFC register value */ | ||
| 26 | |||
| 27 | #define GET_SFC(x) \ | ||
| 28 | __asm__ __volatile__ (" movec %/sfc, %0" : "=d" (x) : ); | ||
| 29 | |||
| 30 | #define SET_VBR(x) \ | ||
| 31 | __asm__ __volatile__ (" movec %0,%/vbr" : : "r" (x)); | ||
| 32 | |||
| 33 | #define GET_VBR(x) \ | ||
| 34 | __asm__ __volatile__ (" movec %/vbr, %0" : "=g" (x) : ); | ||
| 35 | |||
| 36 | /* Set a byte using the "movs" instruction */ | ||
| 37 | |||
| 38 | #define SET_CONTROL_BYTE(addr,value) \ | ||
| 39 | __asm__ __volatile__ (" movsb %0, %1@" : : "d" (value), "a" (addr)); | ||
| 40 | |||
| 41 | /* Get a byte using the "movs" instruction */ | ||
| 42 | |||
| 43 | #define GET_CONTROL_BYTE(addr,value) \ | ||
| 44 | __asm__ __volatile__ (" movsb %1@, %0" : "=d" (value) : "a" (addr)); | ||
| 45 | |||
| 46 | /* Set a (long)word using the "movs" instruction */ | ||
| 47 | |||
| 48 | #define SET_CONTROL_WORD(addr,value) \ | ||
| 49 | __asm__ __volatile__ (" movsl %0, %1@" : : "d" (value), "a" (addr)); | ||
| 50 | |||
| 51 | /* Get a (long)word using the "movs" instruction */ | ||
| 52 | |||
| 53 | #define GET_CONTROL_WORD(addr,value) \ | ||
| 54 | __asm__ __volatile__ (" movsl %1@, %0" : "=d" (value) : "a" (addr)); | ||
| 55 | #endif | ||
diff --git a/arch/m68k/include/asm/msgbuf.h b/arch/m68k/include/asm/msgbuf.h new file mode 100644 index 000000000000..243cb798de8f --- /dev/null +++ b/arch/m68k/include/asm/msgbuf.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _M68K_MSGBUF_H | ||
| 2 | #define _M68K_MSGBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The msqid64_ds structure for m68k architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct msqid64_ds { | ||
| 15 | struct ipc64_perm msg_perm; | ||
| 16 | __kernel_time_t msg_stime; /* last msgsnd time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t msg_rtime; /* last msgrcv time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | __kernel_time_t msg_ctime; /* last change time */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long msg_cbytes; /* current number of bytes on queue */ | ||
| 23 | unsigned long msg_qnum; /* number of messages in queue */ | ||
| 24 | unsigned long msg_qbytes; /* max number of bytes on queue */ | ||
| 25 | __kernel_pid_t msg_lspid; /* pid of last msgsnd */ | ||
| 26 | __kernel_pid_t msg_lrpid; /* last receive pid */ | ||
| 27 | unsigned long __unused4; | ||
| 28 | unsigned long __unused5; | ||
| 29 | }; | ||
| 30 | |||
| 31 | #endif /* _M68K_MSGBUF_H */ | ||
diff --git a/arch/m68k/include/asm/mutex.h b/arch/m68k/include/asm/mutex.h new file mode 100644 index 000000000000..458c1f7fbc18 --- /dev/null +++ b/arch/m68k/include/asm/mutex.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | /* | ||
| 2 | * Pull in the generic implementation for the mutex fastpath. | ||
| 3 | * | ||
| 4 | * TODO: implement optimized primitives instead, or leave the generic | ||
| 5 | * implementation in place, or pick the atomic_xchg() based generic | ||
| 6 | * implementation. (see asm-generic/mutex-xchg.h for details) | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm-generic/mutex-dec.h> | ||
diff --git a/arch/m68k/include/asm/mvme147hw.h b/arch/m68k/include/asm/mvme147hw.h new file mode 100644 index 000000000000..b81043108472 --- /dev/null +++ b/arch/m68k/include/asm/mvme147hw.h | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | #ifndef _MVME147HW_H_ | ||
| 2 | #define _MVME147HW_H_ | ||
| 3 | |||
| 4 | #include <asm/irq.h> | ||
| 5 | |||
| 6 | typedef struct { | ||
| 7 | unsigned char | ||
| 8 | ctrl, | ||
| 9 | bcd_sec, | ||
| 10 | bcd_min, | ||
| 11 | bcd_hr, | ||
| 12 | bcd_dow, | ||
| 13 | bcd_dom, | ||
| 14 | bcd_mth, | ||
| 15 | bcd_year; | ||
| 16 | } MK48T02; | ||
| 17 | |||
| 18 | #define RTC_WRITE 0x80 | ||
| 19 | #define RTC_READ 0x40 | ||
| 20 | #define RTC_STOP 0x20 | ||
| 21 | |||
| 22 | #define m147_rtc ((MK48T02 * volatile)0xfffe07f8) | ||
| 23 | |||
| 24 | |||
| 25 | struct pcc_regs { | ||
| 26 | volatile u_long dma_tadr; | ||
| 27 | volatile u_long dma_dadr; | ||
| 28 | volatile u_long dma_bcr; | ||
| 29 | volatile u_long dma_hr; | ||
| 30 | volatile u_short t1_preload; | ||
| 31 | volatile u_short t1_count; | ||
| 32 | volatile u_short t2_preload; | ||
| 33 | volatile u_short t2_count; | ||
| 34 | volatile u_char t1_int_cntrl; | ||
| 35 | volatile u_char t1_cntrl; | ||
| 36 | volatile u_char t2_int_cntrl; | ||
| 37 | volatile u_char t2_cntrl; | ||
| 38 | volatile u_char ac_fail; | ||
| 39 | volatile u_char watchdog; | ||
| 40 | volatile u_char lpt_intr; | ||
| 41 | volatile u_char lpt_cntrl; | ||
| 42 | volatile u_char dma_intr; | ||
| 43 | volatile u_char dma_cntrl; | ||
| 44 | volatile u_char bus_error; | ||
| 45 | volatile u_char dma_status; | ||
| 46 | volatile u_char abort; | ||
| 47 | volatile u_char ta_fnctl; | ||
| 48 | volatile u_char serial_cntrl; | ||
| 49 | volatile u_char general_cntrl; | ||
| 50 | volatile u_char lan_cntrl; | ||
| 51 | volatile u_char general_status; | ||
| 52 | volatile u_char scsi_interrupt; | ||
| 53 | volatile u_char slave; | ||
| 54 | volatile u_char soft1_cntrl; | ||
| 55 | volatile u_char int_base; | ||
| 56 | volatile u_char soft2_cntrl; | ||
| 57 | volatile u_char revision_level; | ||
| 58 | volatile u_char lpt_data; | ||
| 59 | volatile u_char lpt_status; | ||
| 60 | }; | ||
| 61 | |||
| 62 | #define m147_pcc ((struct pcc_regs * volatile)0xfffe1000) | ||
| 63 | |||
| 64 | |||
| 65 | #define PCC_INT_ENAB 0x08 | ||
| 66 | |||
| 67 | #define PCC_TIMER_INT_CLR 0x80 | ||
| 68 | #define PCC_TIMER_PRELOAD 63936l | ||
| 69 | |||
| 70 | #define PCC_LEVEL_ABORT 0x07 | ||
| 71 | #define PCC_LEVEL_SERIAL 0x04 | ||
| 72 | #define PCC_LEVEL_ETH 0x04 | ||
| 73 | #define PCC_LEVEL_TIMER1 0x04 | ||
| 74 | #define PCC_LEVEL_SCSI_PORT 0x04 | ||
| 75 | #define PCC_LEVEL_SCSI_DMA 0x04 | ||
| 76 | |||
| 77 | #define PCC_IRQ_AC_FAIL (IRQ_USER+0) | ||
| 78 | #define PCC_IRQ_BERR (IRQ_USER+1) | ||
| 79 | #define PCC_IRQ_ABORT (IRQ_USER+2) | ||
| 80 | /* #define PCC_IRQ_SERIAL (IRQ_USER+3) */ | ||
| 81 | #define PCC_IRQ_PRINTER (IRQ_USER+7) | ||
| 82 | #define PCC_IRQ_TIMER1 (IRQ_USER+8) | ||
| 83 | #define PCC_IRQ_TIMER2 (IRQ_USER+9) | ||
| 84 | #define PCC_IRQ_SOFTWARE1 (IRQ_USER+10) | ||
| 85 | #define PCC_IRQ_SOFTWARE2 (IRQ_USER+11) | ||
| 86 | |||
| 87 | |||
| 88 | #define M147_SCC_A_ADDR 0xfffe3002 | ||
| 89 | #define M147_SCC_B_ADDR 0xfffe3000 | ||
| 90 | #define M147_SCC_PCLK 5000000 | ||
| 91 | |||
| 92 | #define MVME147_IRQ_SCSI_PORT (IRQ_USER+0x45) | ||
| 93 | #define MVME147_IRQ_SCSI_DMA (IRQ_USER+0x46) | ||
| 94 | |||
| 95 | /* SCC interrupts, for MVME147 */ | ||
| 96 | |||
| 97 | #define MVME147_IRQ_TYPE_PRIO 0 | ||
| 98 | #define MVME147_IRQ_SCC_BASE (IRQ_USER+32) | ||
| 99 | #define MVME147_IRQ_SCCB_TX (IRQ_USER+32) | ||
| 100 | #define MVME147_IRQ_SCCB_STAT (IRQ_USER+34) | ||
| 101 | #define MVME147_IRQ_SCCB_RX (IRQ_USER+36) | ||
| 102 | #define MVME147_IRQ_SCCB_SPCOND (IRQ_USER+38) | ||
| 103 | #define MVME147_IRQ_SCCA_TX (IRQ_USER+40) | ||
| 104 | #define MVME147_IRQ_SCCA_STAT (IRQ_USER+42) | ||
| 105 | #define MVME147_IRQ_SCCA_RX (IRQ_USER+44) | ||
| 106 | #define MVME147_IRQ_SCCA_SPCOND (IRQ_USER+46) | ||
| 107 | |||
| 108 | #define MVME147_LANCE_BASE 0xfffe1800 | ||
| 109 | #define MVME147_LANCE_IRQ (IRQ_USER+4) | ||
| 110 | |||
| 111 | #define ETHERNET_ADDRESS 0xfffe0778 | ||
| 112 | |||
| 113 | #endif | ||
diff --git a/arch/m68k/include/asm/mvme16xhw.h b/arch/m68k/include/asm/mvme16xhw.h new file mode 100644 index 000000000000..6117f56653d2 --- /dev/null +++ b/arch/m68k/include/asm/mvme16xhw.h | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | #ifndef _M68K_MVME16xHW_H_ | ||
| 2 | #define _M68K_MVME16xHW_H_ | ||
| 3 | |||
| 4 | #include <asm/irq.h> | ||
| 5 | |||
| 6 | /* Board ID data structure - pointer to this retrieved from Bug by head.S */ | ||
| 7 | |||
| 8 | /* Note, bytes 12 and 13 are board no in BCD (0162,0166,0167,0177,etc) */ | ||
| 9 | |||
| 10 | extern long mvme_bdid_ptr; | ||
| 11 | |||
| 12 | typedef struct { | ||
| 13 | char bdid[4]; | ||
| 14 | u_char rev, mth, day, yr; | ||
| 15 | u_short size, reserved; | ||
| 16 | u_short brdno; | ||
| 17 | char brdsuffix[2]; | ||
| 18 | u_long options; | ||
| 19 | u_short clun, dlun, ctype, dnum; | ||
| 20 | u_long option2; | ||
| 21 | } t_bdid, *p_bdid; | ||
| 22 | |||
| 23 | |||
| 24 | typedef struct { | ||
| 25 | u_char ack_icr, | ||
| 26 | flt_icr, | ||
| 27 | sel_icr, | ||
| 28 | pe_icr, | ||
| 29 | bsy_icr, | ||
| 30 | spare1, | ||
| 31 | isr, | ||
| 32 | cr, | ||
| 33 | spare2, | ||
| 34 | spare3, | ||
| 35 | spare4, | ||
| 36 | data; | ||
| 37 | } MVMElp, *MVMElpPtr; | ||
| 38 | |||
| 39 | #define MVME_LPR_BASE 0xfff42030 | ||
| 40 | |||
| 41 | #define mvmelp ((*(volatile MVMElpPtr)(MVME_LPR_BASE))) | ||
| 42 | |||
| 43 | typedef struct { | ||
| 44 | unsigned char | ||
| 45 | ctrl, | ||
| 46 | bcd_sec, | ||
| 47 | bcd_min, | ||
| 48 | bcd_hr, | ||
| 49 | bcd_dow, | ||
| 50 | bcd_dom, | ||
| 51 | bcd_mth, | ||
| 52 | bcd_year; | ||
| 53 | } MK48T08_t, *MK48T08ptr_t; | ||
| 54 | |||
| 55 | #define RTC_WRITE 0x80 | ||
| 56 | #define RTC_READ 0x40 | ||
| 57 | #define RTC_STOP 0x20 | ||
| 58 | |||
| 59 | #define MVME_RTC_BASE 0xfffc1ff8 | ||
| 60 | |||
| 61 | #define MVME_I596_BASE 0xfff46000 | ||
| 62 | |||
| 63 | #define MVME_SCC_A_ADDR 0xfff45005 | ||
| 64 | #define MVME_SCC_B_ADDR 0xfff45001 | ||
| 65 | #define MVME_SCC_PCLK 10000000 | ||
| 66 | |||
| 67 | #define MVME162_IRQ_TYPE_PRIO 0 | ||
| 68 | |||
| 69 | #define MVME167_IRQ_PRN (IRQ_USER+20) | ||
| 70 | #define MVME16x_IRQ_I596 (IRQ_USER+23) | ||
| 71 | #define MVME16x_IRQ_SCSI (IRQ_USER+21) | ||
| 72 | #define MVME16x_IRQ_FLY (IRQ_USER+63) | ||
| 73 | #define MVME167_IRQ_SER_ERR (IRQ_USER+28) | ||
| 74 | #define MVME167_IRQ_SER_MODEM (IRQ_USER+29) | ||
| 75 | #define MVME167_IRQ_SER_TX (IRQ_USER+30) | ||
| 76 | #define MVME167_IRQ_SER_RX (IRQ_USER+31) | ||
| 77 | #define MVME16x_IRQ_TIMER (IRQ_USER+25) | ||
| 78 | #define MVME167_IRQ_ABORT (IRQ_USER+46) | ||
| 79 | #define MVME162_IRQ_ABORT (IRQ_USER+30) | ||
| 80 | |||
| 81 | /* SCC interrupts, for MVME162 */ | ||
| 82 | #define MVME162_IRQ_SCC_BASE (IRQ_USER+0) | ||
| 83 | #define MVME162_IRQ_SCCB_TX (IRQ_USER+0) | ||
| 84 | #define MVME162_IRQ_SCCB_STAT (IRQ_USER+2) | ||
| 85 | #define MVME162_IRQ_SCCB_RX (IRQ_USER+4) | ||
| 86 | #define MVME162_IRQ_SCCB_SPCOND (IRQ_USER+6) | ||
| 87 | #define MVME162_IRQ_SCCA_TX (IRQ_USER+8) | ||
| 88 | #define MVME162_IRQ_SCCA_STAT (IRQ_USER+10) | ||
| 89 | #define MVME162_IRQ_SCCA_RX (IRQ_USER+12) | ||
| 90 | #define MVME162_IRQ_SCCA_SPCOND (IRQ_USER+14) | ||
| 91 | |||
| 92 | /* MVME162 version register */ | ||
| 93 | |||
| 94 | #define MVME162_VERSION_REG 0xfff4202e | ||
| 95 | |||
| 96 | extern unsigned short mvme16x_config; | ||
| 97 | |||
| 98 | /* Lower 8 bits must match the revision register in the MC2 chip */ | ||
| 99 | |||
| 100 | #define MVME16x_CONFIG_SPEED_32 0x0001 | ||
| 101 | #define MVME16x_CONFIG_NO_VMECHIP2 0x0002 | ||
| 102 | #define MVME16x_CONFIG_NO_SCSICHIP 0x0004 | ||
| 103 | #define MVME16x_CONFIG_NO_ETHERNET 0x0008 | ||
| 104 | #define MVME16x_CONFIG_GOT_FPU 0x0010 | ||
| 105 | |||
| 106 | #define MVME16x_CONFIG_GOT_LP 0x0100 | ||
| 107 | #define MVME16x_CONFIG_GOT_CD2401 0x0200 | ||
| 108 | #define MVME16x_CONFIG_GOT_SCCA 0x0400 | ||
| 109 | #define MVME16x_CONFIG_GOT_SCCB 0x0800 | ||
| 110 | |||
| 111 | #endif | ||
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h new file mode 100644 index 000000000000..0299f6a2deeb --- /dev/null +++ b/arch/m68k/include/asm/nettel.h | |||
| @@ -0,0 +1,108 @@ | |||
| 1 | /****************************************************************************/ | ||
| 2 | |||
| 3 | /* | ||
| 4 | * nettel.h -- Lineo (formerly Moreton Bay) NETtel support. | ||
| 5 | * | ||
| 6 | * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com) | ||
| 7 | * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com) | ||
| 8 | * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com) | ||
| 9 | */ | ||
| 10 | |||
| 11 | /****************************************************************************/ | ||
| 12 | #ifndef nettel_h | ||
| 13 | #define nettel_h | ||
| 14 | /****************************************************************************/ | ||
| 15 | |||
| 16 | |||
| 17 | /****************************************************************************/ | ||
| 18 | #ifdef CONFIG_NETtel | ||
| 19 | /****************************************************************************/ | ||
| 20 | |||
| 21 | #ifdef CONFIG_COLDFIRE | ||
| 22 | #include <asm/coldfire.h> | ||
| 23 | #include <asm/mcfsim.h> | ||
| 24 | #endif | ||
| 25 | |||
| 26 | /*---------------------------------------------------------------------------*/ | ||
| 27 | #if defined(CONFIG_M5307) | ||
| 28 | /* | ||
| 29 | * NETtel/5307 based hardware first. DTR/DCD lines are wired to | ||
| 30 | * GPIO lines. Most of the LED's are driver through a latch | ||
| 31 | * connected to CS2. | ||
| 32 | */ | ||
| 33 | #define MCFPP_DCD1 0x0001 | ||
| 34 | #define MCFPP_DCD0 0x0002 | ||
| 35 | #define MCFPP_DTR1 0x0004 | ||
| 36 | #define MCFPP_DTR0 0x0008 | ||
| 37 | |||
| 38 | #define NETtel_LEDADDR 0x30400000 | ||
| 39 | |||
| 40 | #ifndef __ASSEMBLY__ | ||
| 41 | |||
| 42 | extern volatile unsigned short ppdata; | ||
| 43 | |||
| 44 | /* | ||
| 45 | * These functions defined to give quasi generic access to the | ||
| 46 | * PPIO bits used for DTR/DCD. | ||
| 47 | */ | ||
| 48 | static __inline__ unsigned int mcf_getppdata(void) | ||
| 49 | { | ||
| 50 | volatile unsigned short *pp; | ||
| 51 | pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); | ||
| 52 | return((unsigned int) *pp); | ||
| 53 | } | ||
| 54 | |||
| 55 | static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) | ||
| 56 | { | ||
| 57 | volatile unsigned short *pp; | ||
| 58 | pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); | ||
| 59 | ppdata = (ppdata & ~mask) | bits; | ||
| 60 | *pp = ppdata; | ||
| 61 | } | ||
| 62 | #endif | ||
| 63 | |||
| 64 | /*---------------------------------------------------------------------------*/ | ||
| 65 | #elif defined(CONFIG_M5206e) | ||
| 66 | /* | ||
| 67 | * NETtel/5206e based hardware has leds on latch on CS3. | ||
| 68 | * No support modem for lines?? | ||
| 69 | */ | ||
| 70 | #define NETtel_LEDADDR 0x50000000 | ||
| 71 | |||
| 72 | /*---------------------------------------------------------------------------*/ | ||
| 73 | #elif defined(CONFIG_M5272) | ||
| 74 | /* | ||
| 75 | * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines. | ||
| 76 | */ | ||
| 77 | #define MCFPP_DCD0 0x0080 | ||
| 78 | #define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */ | ||
| 79 | #define MCFPP_DTR0 0x0040 | ||
| 80 | #define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */ | ||
| 81 | |||
| 82 | #ifndef __ASSEMBLY__ | ||
| 83 | /* | ||
| 84 | * These functions defined to give quasi generic access to the | ||
| 85 | * PPIO bits used for DTR/DCD. | ||
| 86 | */ | ||
| 87 | static __inline__ unsigned int mcf_getppdata(void) | ||
| 88 | { | ||
| 89 | volatile unsigned short *pp; | ||
| 90 | pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT); | ||
| 91 | return((unsigned int) *pp); | ||
| 92 | } | ||
| 93 | |||
| 94 | static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) | ||
| 95 | { | ||
| 96 | volatile unsigned short *pp; | ||
| 97 | pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT); | ||
| 98 | *pp = (*pp & ~mask) | bits; | ||
| 99 | } | ||
| 100 | #endif | ||
| 101 | |||
| 102 | #endif | ||
| 103 | /*---------------------------------------------------------------------------*/ | ||
| 104 | |||
| 105 | /****************************************************************************/ | ||
| 106 | #endif /* CONFIG_NETtel */ | ||
| 107 | /****************************************************************************/ | ||
| 108 | #endif /* nettel_h */ | ||
diff --git a/arch/m68k/include/asm/nubus.h b/arch/m68k/include/asm/nubus.h new file mode 100644 index 000000000000..d6be9976f1ae --- /dev/null +++ b/arch/m68k/include/asm/nubus.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | #ifndef _ASM_M68K_NUBUS_H | ||
| 2 | #define _ASM_M68K_NUBUS_H | ||
| 3 | |||
| 4 | #include <asm/raw_io.h> | ||
| 5 | |||
| 6 | #define nubus_readb raw_inb | ||
| 7 | #define nubus_readw raw_inw | ||
| 8 | #define nubus_readl raw_inl | ||
| 9 | |||
| 10 | #define nubus_writeb raw_outb | ||
| 11 | #define nubus_writew raw_outw | ||
| 12 | #define nubus_writel raw_outl | ||
| 13 | |||
| 14 | #define nubus_memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
| 15 | #define nubus_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
| 16 | #define nubus_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
| 17 | |||
| 18 | static inline void *nubus_remap_nocache_ser(unsigned long physaddr, | ||
| 19 | unsigned long size) | ||
| 20 | { | ||
| 21 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline void *nubus_remap_nocache_nonser(unsigned long physaddr, | ||
| 25 | unsigned long size) | ||
| 26 | { | ||
| 27 | return __ioremap(physaddr, size, IOMAP_NOCACHE_NONSER); | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline void *nbus_remap_writethrough(unsigned long physaddr, | ||
| 31 | unsigned long size) | ||
| 32 | { | ||
| 33 | return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void *nubus_remap_fullcache(unsigned long physaddr, | ||
| 37 | unsigned long size) | ||
| 38 | { | ||
| 39 | return __ioremap(physaddr, size, IOMAP_FULL_CACHING); | ||
| 40 | } | ||
| 41 | |||
| 42 | #define nubus_unmap iounmap | ||
| 43 | #define nubus_iounmap iounmap | ||
| 44 | #define nubus_ioremap nubus_remap_nocache_ser | ||
| 45 | |||
| 46 | #endif /* _ASM_NUBUS_H */ | ||
diff --git a/arch/m68k/include/asm/openprom.h b/arch/m68k/include/asm/openprom.h new file mode 100644 index 000000000000..d33cdadf78e1 --- /dev/null +++ b/arch/m68k/include/asm/openprom.h | |||
| @@ -0,0 +1,312 @@ | |||
| 1 | #ifndef __SPARC_OPENPROM_H | ||
| 2 | #define __SPARC_OPENPROM_H | ||
| 3 | |||
| 4 | /* openprom.h: Prom structures and defines for access to the OPENBOOT | ||
| 5 | * prom routines and data areas. | ||
| 6 | * | ||
| 7 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
| 8 | */ | ||
| 9 | |||
| 10 | |||
| 11 | /* Empirical constants... */ | ||
| 12 | #ifdef CONFIG_SUN3 | ||
| 13 | #define KADB_DEBUGGER_BEGVM 0x0fee0000 /* There is no kadb yet but...*/ | ||
| 14 | #define LINUX_OPPROM_BEGVM 0x0fef0000 | ||
| 15 | #define LINUX_OPPROM_ENDVM 0x0ff10000 /* I think this is right - tm */ | ||
| 16 | #else | ||
| 17 | #define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */ | ||
| 18 | #define LINUX_OPPROM_BEGVM 0xffd00000 | ||
| 19 | #define LINUX_OPPROM_ENDVM 0xfff00000 | ||
| 20 | #define LINUX_OPPROM_MAGIC 0x10010407 | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | /* V0 prom device operations. */ | ||
| 25 | struct linux_dev_v0_funcs { | ||
| 26 | int (*v0_devopen)(char *device_str); | ||
| 27 | int (*v0_devclose)(int dev_desc); | ||
| 28 | int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf); | ||
| 29 | int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf); | ||
| 30 | int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf); | ||
| 31 | int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf); | ||
| 32 | int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf); | ||
| 33 | int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf); | ||
| 34 | int (*v0_seekdev)(int dev_desc, long logical_offst, int from); | ||
| 35 | }; | ||
| 36 | |||
| 37 | /* V2 and later prom device operations. */ | ||
| 38 | struct linux_dev_v2_funcs { | ||
| 39 | int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */ | ||
| 40 | char * (*v2_dumb_mem_alloc)(char *va, unsigned sz); | ||
| 41 | void (*v2_dumb_mem_free)(char *va, unsigned sz); | ||
| 42 | |||
| 43 | /* To map devices into virtual I/O space. */ | ||
| 44 | char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz); | ||
| 45 | void (*v2_dumb_munmap)(char *virta, unsigned size); | ||
| 46 | |||
| 47 | int (*v2_dev_open)(char *devpath); | ||
| 48 | void (*v2_dev_close)(int d); | ||
| 49 | int (*v2_dev_read)(int d, char *buf, int nbytes); | ||
| 50 | int (*v2_dev_write)(int d, char *buf, int nbytes); | ||
| 51 | int (*v2_dev_seek)(int d, int hi, int lo); | ||
| 52 | |||
| 53 | /* Never issued (multistage load support) */ | ||
| 54 | void (*v2_wheee2)(void); | ||
| 55 | void (*v2_wheee3)(void); | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct linux_mlist_v0 { | ||
| 59 | struct linux_mlist_v0 *theres_more; | ||
| 60 | char *start_adr; | ||
| 61 | unsigned num_bytes; | ||
| 62 | }; | ||
| 63 | |||
| 64 | struct linux_mem_v0 { | ||
| 65 | struct linux_mlist_v0 **v0_totphys; | ||
| 66 | struct linux_mlist_v0 **v0_prommap; | ||
| 67 | struct linux_mlist_v0 **v0_available; /* What we can use */ | ||
| 68 | }; | ||
| 69 | |||
| 70 | /* Arguments sent to the kernel from the boot prompt. */ | ||
| 71 | struct linux_arguments_v0 { | ||
| 72 | char *argv[8]; | ||
| 73 | char args[100]; | ||
| 74 | char boot_dev[2]; | ||
| 75 | int boot_dev_ctrl; | ||
| 76 | int boot_dev_unit; | ||
| 77 | int dev_partition; | ||
| 78 | char *kernel_file_name; | ||
| 79 | void *aieee1; /* XXX */ | ||
| 80 | }; | ||
| 81 | |||
| 82 | /* V2 and up boot things. */ | ||
| 83 | struct linux_bootargs_v2 { | ||
| 84 | char **bootpath; | ||
| 85 | char **bootargs; | ||
| 86 | int *fd_stdin; | ||
| 87 | int *fd_stdout; | ||
| 88 | }; | ||
| 89 | |||
| 90 | #if defined(CONFIG_SUN3) || defined(CONFIG_SUN3X) | ||
| 91 | struct linux_romvec { | ||
| 92 | char *pv_initsp; | ||
| 93 | int (*pv_startmon)(void); | ||
| 94 | |||
| 95 | int *diagberr; | ||
| 96 | |||
| 97 | struct linux_arguments_v0 **pv_v0bootargs; | ||
| 98 | unsigned *pv_sun3mem; | ||
| 99 | |||
| 100 | unsigned char (*pv_getchar)(void); | ||
| 101 | int (*pv_putchar)(int ch); | ||
| 102 | int (*pv_nbgetchar)(void); | ||
| 103 | int (*pv_nbputchar)(int ch); | ||
| 104 | unsigned char *pv_echo; | ||
| 105 | unsigned char *pv_insource; | ||
| 106 | unsigned char *pv_outsink; | ||
| 107 | |||
| 108 | int (*pv_getkey)(void); | ||
| 109 | int (*pv_initgetkey)(void); | ||
| 110 | unsigned int *pv_translation; | ||
| 111 | unsigned char *pv_keybid; | ||
| 112 | int *pv_screen_x; | ||
| 113 | int *pv_screen_y; | ||
| 114 | struct keybuf *pv_keybuf; | ||
| 115 | |||
| 116 | char *pv_monid; | ||
| 117 | |||
| 118 | /* | ||
| 119 | * Frame buffer output and terminal emulation | ||
| 120 | */ | ||
| 121 | |||
| 122 | int (*pv_fbwritechar)(char); | ||
| 123 | int *pv_fbaddr; | ||
| 124 | char **pv_font; | ||
| 125 | int (*pv_fbwritestr)(char); | ||
| 126 | |||
| 127 | void (*pv_reboot)(char *bootstr); | ||
| 128 | |||
| 129 | /* | ||
| 130 | * Line input and parsing | ||
| 131 | */ | ||
| 132 | |||
| 133 | unsigned char *pv_linebuf; | ||
| 134 | unsigned char **pv_lineptr; | ||
| 135 | int *pv_linesize; | ||
| 136 | int (*pv_getline)(void); | ||
| 137 | unsigned char (*pv_getnextchar)(void); | ||
| 138 | unsigned char (*pv_peeknextchar)(void); | ||
| 139 | int *pv_fbthere; | ||
| 140 | int (*pv_getnum)(void); | ||
| 141 | |||
| 142 | void (*pv_printf)(const char *fmt, ...); | ||
| 143 | int (*pv_printhex)(void); | ||
| 144 | |||
| 145 | unsigned char *pv_leds; | ||
| 146 | int (*pv_setleds)(void); | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Non-maskable interrupt (nmi) information | ||
| 150 | */ | ||
| 151 | |||
| 152 | int (*pv_nmiaddr)(void); | ||
| 153 | int (*pv_abortentry)(void); | ||
| 154 | int *pv_nmiclock; | ||
| 155 | |||
| 156 | int *pv_fbtype; | ||
| 157 | |||
| 158 | /* | ||
| 159 | * Assorted other things | ||
| 160 | */ | ||
| 161 | |||
| 162 | unsigned pv_romvers; | ||
| 163 | struct globram *pv_globram; | ||
| 164 | char *pv_kbdzscc; | ||
| 165 | |||
| 166 | int *pv_keyrinit; | ||
| 167 | unsigned char *pv_keyrtick; | ||
| 168 | unsigned *pv_memoryavail; | ||
| 169 | long *pv_resetaddr; | ||
| 170 | long *pv_resetmap; | ||
| 171 | |||
| 172 | void (*pv_halt)(void); | ||
| 173 | unsigned char *pv_memorybitmap; | ||
| 174 | |||
| 175 | #ifdef CONFIG_SUN3 | ||
| 176 | void (*pv_setctxt)(int ctxt, char *va, int pmeg); | ||
| 177 | void (*pv_vector_cmd)(void); | ||
| 178 | int dummy1z; | ||
| 179 | int dummy2z; | ||
| 180 | int dummy3z; | ||
| 181 | int dummy4z; | ||
| 182 | #endif | ||
| 183 | }; | ||
| 184 | #else | ||
| 185 | /* The top level PROM vector. */ | ||
| 186 | struct linux_romvec { | ||
| 187 | /* Version numbers. */ | ||
| 188 | unsigned int pv_magic_cookie; | ||
| 189 | unsigned int pv_romvers; | ||
| 190 | unsigned int pv_plugin_revision; | ||
| 191 | unsigned int pv_printrev; | ||
| 192 | |||
| 193 | /* Version 0 memory descriptors. */ | ||
| 194 | struct linux_mem_v0 pv_v0mem; | ||
| 195 | |||
| 196 | /* Node operations. */ | ||
| 197 | struct linux_nodeops *pv_nodeops; | ||
| 198 | |||
| 199 | char **pv_bootstr; | ||
| 200 | struct linux_dev_v0_funcs pv_v0devops; | ||
| 201 | |||
| 202 | char *pv_stdin; | ||
| 203 | char *pv_stdout; | ||
| 204 | #define PROMDEV_KBD 0 /* input from keyboard */ | ||
| 205 | #define PROMDEV_SCREEN 0 /* output to screen */ | ||
| 206 | #define PROMDEV_TTYA 1 /* in/out to ttya */ | ||
| 207 | #define PROMDEV_TTYB 2 /* in/out to ttyb */ | ||
| 208 | |||
| 209 | /* Blocking getchar/putchar. NOT REENTRANT! (grr) */ | ||
| 210 | int (*pv_getchar)(void); | ||
| 211 | void (*pv_putchar)(int ch); | ||
| 212 | |||
| 213 | /* Non-blocking variants. */ | ||
| 214 | int (*pv_nbgetchar)(void); | ||
| 215 | int (*pv_nbputchar)(int ch); | ||
| 216 | |||
| 217 | void (*pv_putstr)(char *str, int len); | ||
| 218 | |||
| 219 | /* Miscellany. */ | ||
| 220 | void (*pv_reboot)(char *bootstr); | ||
| 221 | void (*pv_printf)(__const__ char *fmt, ...); | ||
| 222 | void (*pv_abort)(void); | ||
| 223 | __volatile__ int *pv_ticks; | ||
| 224 | void (*pv_halt)(void); | ||
| 225 | void (**pv_synchook)(void); | ||
| 226 | |||
| 227 | /* Evaluate a forth string, not different proto for V0 and V2->up. */ | ||
| 228 | union { | ||
| 229 | void (*v0_eval)(int len, char *str); | ||
| 230 | void (*v2_eval)(char *str); | ||
| 231 | } pv_fortheval; | ||
| 232 | |||
| 233 | struct linux_arguments_v0 **pv_v0bootargs; | ||
| 234 | |||
| 235 | /* Get ether address. */ | ||
| 236 | unsigned int (*pv_enaddr)(int d, char *enaddr); | ||
| 237 | |||
| 238 | struct linux_bootargs_v2 pv_v2bootargs; | ||
| 239 | struct linux_dev_v2_funcs pv_v2devops; | ||
| 240 | |||
| 241 | int filler[15]; | ||
| 242 | |||
| 243 | /* This one is sun4c/sun4 only. */ | ||
| 244 | void (*pv_setctxt)(int ctxt, char *va, int pmeg); | ||
| 245 | |||
| 246 | /* Prom version 3 Multiprocessor routines. This stuff is crazy. | ||
| 247 | * No joke. Calling these when there is only one cpu probably | ||
| 248 | * crashes the machine, have to test this. :-) | ||
| 249 | */ | ||
| 250 | |||
| 251 | /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context | ||
| 252 | * 'thiscontext' executing at address 'prog_counter' | ||
| 253 | */ | ||
| 254 | int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr, | ||
| 255 | int thiscontext, char *prog_counter); | ||
| 256 | |||
| 257 | /* v3_cpustop() will cause cpu 'whichcpu' to stop executing | ||
| 258 | * until a resume cpu call is made. | ||
| 259 | */ | ||
| 260 | int (*v3_cpustop)(unsigned int whichcpu); | ||
| 261 | |||
| 262 | /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or | ||
| 263 | * resume cpu call is made. | ||
| 264 | */ | ||
| 265 | int (*v3_cpuidle)(unsigned int whichcpu); | ||
| 266 | |||
| 267 | /* v3_cpuresume() will resume processor 'whichcpu' executing | ||
| 268 | * starting with whatever 'pc' and 'npc' were left at the | ||
| 269 | * last 'idle' or 'stop' call. | ||
| 270 | */ | ||
| 271 | int (*v3_cpuresume)(unsigned int whichcpu); | ||
| 272 | }; | ||
| 273 | #endif | ||
| 274 | |||
| 275 | /* Routines for traversing the prom device tree. */ | ||
| 276 | struct linux_nodeops { | ||
| 277 | int (*no_nextnode)(int node); | ||
| 278 | int (*no_child)(int node); | ||
| 279 | int (*no_proplen)(int node, char *name); | ||
| 280 | int (*no_getprop)(int node, char *name, char *val); | ||
| 281 | int (*no_setprop)(int node, char *name, char *val, int len); | ||
| 282 | char * (*no_nextprop)(int node, char *name); | ||
| 283 | }; | ||
| 284 | |||
| 285 | /* More fun PROM structures for device probing. */ | ||
| 286 | #define PROMREG_MAX 16 | ||
| 287 | #define PROMVADDR_MAX 16 | ||
| 288 | #define PROMINTR_MAX 15 | ||
| 289 | |||
| 290 | struct linux_prom_registers { | ||
| 291 | int which_io; /* is this in OBIO space? */ | ||
| 292 | char *phys_addr; /* The physical address of this register */ | ||
| 293 | int reg_size; /* How many bytes does this register take up? */ | ||
| 294 | }; | ||
| 295 | |||
| 296 | struct linux_prom_irqs { | ||
| 297 | int pri; /* IRQ priority */ | ||
| 298 | int vector; /* This is foobar, what does it do? */ | ||
| 299 | }; | ||
| 300 | |||
| 301 | /* Element of the "ranges" vector */ | ||
| 302 | struct linux_prom_ranges { | ||
| 303 | unsigned int ot_child_space; | ||
| 304 | unsigned int ot_child_base; /* Bus feels this */ | ||
| 305 | unsigned int ot_parent_space; | ||
| 306 | unsigned int ot_parent_base; /* CPU looks from here */ | ||
| 307 | unsigned int or_size; | ||
| 308 | }; | ||
| 309 | |||
| 310 | #endif /* !(__ASSEMBLY__) */ | ||
| 311 | |||
| 312 | #endif /* !(__SPARC_OPENPROM_H) */ | ||
diff --git a/arch/m68k/include/asm/oplib.h b/arch/m68k/include/asm/oplib.h new file mode 100644 index 000000000000..f082d03336bd --- /dev/null +++ b/arch/m68k/include/asm/oplib.h | |||
| @@ -0,0 +1,291 @@ | |||
| 1 | /* | ||
| 2 | * oplib.h: Describes the interface and available routines in the | ||
| 3 | * Linux Prom library. | ||
| 4 | * | ||
| 5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __SPARC_OPLIB_H | ||
| 9 | #define __SPARC_OPLIB_H | ||
| 10 | |||
| 11 | #include <asm/openprom.h> | ||
| 12 | |||
| 13 | /* The master romvec pointer... */ | ||
| 14 | extern struct linux_romvec *romvec; | ||
| 15 | |||
| 16 | /* Enumeration to describe the prom major version we have detected. */ | ||
| 17 | enum prom_major_version { | ||
| 18 | PROM_V0, /* Original sun4c V0 prom */ | ||
| 19 | PROM_V2, /* sun4c and early sun4m V2 prom */ | ||
| 20 | PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */ | ||
| 21 | PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */ | ||
| 22 | }; | ||
| 23 | |||
| 24 | extern enum prom_major_version prom_vers; | ||
| 25 | /* Revision, and firmware revision. */ | ||
| 26 | extern unsigned int prom_rev, prom_prev; | ||
| 27 | |||
| 28 | /* Root node of the prom device tree, this stays constant after | ||
| 29 | * initialization is complete. | ||
| 30 | */ | ||
| 31 | extern int prom_root_node; | ||
| 32 | |||
| 33 | /* Pointer to prom structure containing the device tree traversal | ||
| 34 | * and usage utility functions. Only prom-lib should use these, | ||
| 35 | * users use the interface defined by the library only! | ||
| 36 | */ | ||
| 37 | extern struct linux_nodeops *prom_nodeops; | ||
| 38 | |||
| 39 | /* The functions... */ | ||
| 40 | |||
| 41 | /* You must call prom_init() before using any of the library services, | ||
| 42 | * preferably as early as possible. Pass it the romvec pointer. | ||
| 43 | */ | ||
| 44 | extern void prom_init(struct linux_romvec *rom_ptr); | ||
| 45 | |||
| 46 | /* Boot argument acquisition, returns the boot command line string. */ | ||
| 47 | extern char *prom_getbootargs(void); | ||
| 48 | |||
| 49 | /* Device utilities. */ | ||
| 50 | |||
| 51 | /* Map and unmap devices in IO space at virtual addresses. Note that the | ||
| 52 | * virtual address you pass is a request and the prom may put your mappings | ||
| 53 | * somewhere else, so check your return value as that is where your new | ||
| 54 | * mappings really are! | ||
| 55 | * | ||
| 56 | * Another note, these are only available on V2 or higher proms! | ||
| 57 | */ | ||
| 58 | extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes); | ||
| 59 | extern void prom_unmapio(char *virt_addr, unsigned int num_bytes); | ||
| 60 | |||
| 61 | /* Device operations. */ | ||
| 62 | |||
| 63 | /* Open the device described by the passed string. Note, that the format | ||
| 64 | * of the string is different on V0 vs. V2->higher proms. The caller must | ||
| 65 | * know what he/she is doing! Returns the device descriptor, an int. | ||
| 66 | */ | ||
| 67 | extern int prom_devopen(char *device_string); | ||
| 68 | |||
| 69 | /* Close a previously opened device described by the passed integer | ||
| 70 | * descriptor. | ||
| 71 | */ | ||
| 72 | extern int prom_devclose(int device_handle); | ||
| 73 | |||
| 74 | /* Do a seek operation on the device described by the passed integer | ||
| 75 | * descriptor. | ||
| 76 | */ | ||
| 77 | extern void prom_seek(int device_handle, unsigned int seek_hival, | ||
| 78 | unsigned int seek_lowval); | ||
| 79 | |||
| 80 | /* Machine memory configuration routine. */ | ||
| 81 | |||
| 82 | /* This function returns a V0 format memory descriptor table, it has three | ||
| 83 | * entries. One for the total amount of physical ram on the machine, one | ||
| 84 | * for the amount of physical ram available, and one describing the virtual | ||
| 85 | * areas which are allocated by the prom. So, in a sense the physical | ||
| 86 | * available is a calculation of the total physical minus the physical mapped | ||
| 87 | * by the prom with virtual mappings. | ||
| 88 | * | ||
| 89 | * These lists are returned pre-sorted, this should make your life easier | ||
| 90 | * since the prom itself is way too lazy to do such nice things. | ||
| 91 | */ | ||
| 92 | extern struct linux_mem_v0 *prom_meminfo(void); | ||
| 93 | |||
| 94 | /* Miscellaneous routines, don't really fit in any category per se. */ | ||
| 95 | |||
| 96 | /* Reboot the machine with the command line passed. */ | ||
| 97 | extern void prom_reboot(char *boot_command); | ||
| 98 | |||
| 99 | /* Evaluate the forth string passed. */ | ||
| 100 | extern void prom_feval(char *forth_string); | ||
| 101 | |||
| 102 | /* Enter the prom, with possibility of continuation with the 'go' | ||
| 103 | * command in newer proms. | ||
| 104 | */ | ||
| 105 | extern void prom_cmdline(void); | ||
| 106 | |||
| 107 | /* Enter the prom, with no chance of continuation for the stand-alone | ||
| 108 | * which calls this. | ||
| 109 | */ | ||
| 110 | extern void prom_halt(void); | ||
| 111 | |||
| 112 | /* Set the PROM 'sync' callback function to the passed function pointer. | ||
| 113 | * When the user gives the 'sync' command at the prom prompt while the | ||
| 114 | * kernel is still active, the prom will call this routine. | ||
| 115 | * | ||
| 116 | * XXX The arguments are different on V0 vs. V2->higher proms, grrr! XXX | ||
| 117 | */ | ||
| 118 | typedef void (*sync_func_t)(void); | ||
| 119 | extern void prom_setsync(sync_func_t func_ptr); | ||
| 120 | |||
| 121 | /* Acquire the IDPROM of the root node in the prom device tree. This | ||
| 122 | * gets passed a buffer where you would like it stuffed. The return value | ||
| 123 | * is the format type of this idprom or 0xff on error. | ||
| 124 | */ | ||
| 125 | extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size); | ||
| 126 | |||
| 127 | /* Get the prom major version. */ | ||
| 128 | extern int prom_version(void); | ||
| 129 | |||
| 130 | /* Get the prom plugin revision. */ | ||
| 131 | extern int prom_getrev(void); | ||
| 132 | |||
| 133 | /* Get the prom firmware revision. */ | ||
| 134 | extern int prom_getprev(void); | ||
| 135 | |||
| 136 | /* Character operations to/from the console.... */ | ||
| 137 | |||
| 138 | /* Non-blocking get character from console. */ | ||
| 139 | extern int prom_nbgetchar(void); | ||
| 140 | |||
| 141 | /* Non-blocking put character to console. */ | ||
| 142 | extern int prom_nbputchar(char character); | ||
| 143 | |||
| 144 | /* Blocking get character from console. */ | ||
| 145 | extern char prom_getchar(void); | ||
| 146 | |||
| 147 | /* Blocking put character to console. */ | ||
| 148 | extern void prom_putchar(char character); | ||
| 149 | |||
| 150 | /* Prom's internal printf routine, don't use in kernel/boot code. */ | ||
| 151 | void prom_printf(char *fmt, ...); | ||
| 152 | |||
| 153 | /* Query for input device type */ | ||
| 154 | |||
| 155 | enum prom_input_device { | ||
| 156 | PROMDEV_IKBD, /* input from keyboard */ | ||
| 157 | PROMDEV_ITTYA, /* input from ttya */ | ||
| 158 | PROMDEV_ITTYB, /* input from ttyb */ | ||
| 159 | PROMDEV_I_UNK, | ||
| 160 | }; | ||
| 161 | |||
| 162 | extern enum prom_input_device prom_query_input_device(void); | ||
| 163 | |||
| 164 | /* Query for output device type */ | ||
| 165 | |||
| 166 | enum prom_output_device { | ||
| 167 | PROMDEV_OSCREEN, /* to screen */ | ||
| 168 | PROMDEV_OTTYA, /* to ttya */ | ||
| 169 | PROMDEV_OTTYB, /* to ttyb */ | ||
| 170 | PROMDEV_O_UNK, | ||
| 171 | }; | ||
| 172 | |||
| 173 | extern enum prom_output_device prom_query_output_device(void); | ||
| 174 | |||
| 175 | /* Multiprocessor operations... */ | ||
| 176 | |||
| 177 | /* Start the CPU with the given device tree node, context table, and context | ||
| 178 | * at the passed program counter. | ||
| 179 | */ | ||
| 180 | extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table, | ||
| 181 | int context, char *program_counter); | ||
| 182 | |||
| 183 | /* Stop the CPU with the passed device tree node. */ | ||
| 184 | extern int prom_stopcpu(int cpunode); | ||
| 185 | |||
| 186 | /* Idle the CPU with the passed device tree node. */ | ||
| 187 | extern int prom_idlecpu(int cpunode); | ||
| 188 | |||
| 189 | /* Re-Start the CPU with the passed device tree node. */ | ||
| 190 | extern int prom_restartcpu(int cpunode); | ||
| 191 | |||
| 192 | /* PROM memory allocation facilities... */ | ||
| 193 | |||
| 194 | /* Allocated at possibly the given virtual address a chunk of the | ||
| 195 | * indicated size. | ||
| 196 | */ | ||
| 197 | extern char *prom_alloc(char *virt_hint, unsigned int size); | ||
| 198 | |||
| 199 | /* Free a previously allocated chunk. */ | ||
| 200 | extern void prom_free(char *virt_addr, unsigned int size); | ||
| 201 | |||
| 202 | /* Sun4/sun4c specific memory-management startup hook. */ | ||
| 203 | |||
| 204 | /* Map the passed segment in the given context at the passed | ||
| 205 | * virtual address. | ||
| 206 | */ | ||
| 207 | extern void prom_putsegment(int context, unsigned long virt_addr, | ||
| 208 | int physical_segment); | ||
| 209 | |||
| 210 | /* PROM device tree traversal functions... */ | ||
| 211 | |||
| 212 | /* Get the child node of the given node, or zero if no child exists. */ | ||
| 213 | extern int prom_getchild(int parent_node); | ||
| 214 | |||
| 215 | /* Get the next sibling node of the given node, or zero if no further | ||
| 216 | * siblings exist. | ||
| 217 | */ | ||
| 218 | extern int prom_getsibling(int node); | ||
| 219 | |||
| 220 | /* Get the length, at the passed node, of the given property type. | ||
| 221 | * Returns -1 on error (ie. no such property at this node). | ||
| 222 | */ | ||
| 223 | extern int prom_getproplen(int thisnode, char *property); | ||
| 224 | |||
| 225 | /* Fetch the requested property using the given buffer. Returns | ||
| 226 | * the number of bytes the prom put into your buffer or -1 on error. | ||
| 227 | */ | ||
| 228 | extern int prom_getproperty(int thisnode, char *property, | ||
| 229 | char *prop_buffer, int propbuf_size); | ||
| 230 | |||
| 231 | /* Acquire an integer property. */ | ||
| 232 | extern int prom_getint(int node, char *property); | ||
| 233 | |||
| 234 | /* Acquire an integer property, with a default value. */ | ||
| 235 | extern int prom_getintdefault(int node, char *property, int defval); | ||
| 236 | |||
| 237 | /* Acquire a boolean property, 0=FALSE 1=TRUE. */ | ||
| 238 | extern int prom_getbool(int node, char *prop); | ||
| 239 | |||
| 240 | /* Acquire a string property, null string on error. */ | ||
| 241 | extern void prom_getstring(int node, char *prop, char *buf, int bufsize); | ||
| 242 | |||
| 243 | /* Does the passed node have the given "name"? YES=1 NO=0 */ | ||
| 244 | extern int prom_nodematch(int thisnode, char *name); | ||
| 245 | |||
| 246 | /* Search all siblings starting at the passed node for "name" matching | ||
| 247 | * the given string. Returns the node on success, zero on failure. | ||
| 248 | */ | ||
| 249 | extern int prom_searchsiblings(int node_start, char *name); | ||
| 250 | |||
| 251 | /* Return the first property type, as a string, for the given node. | ||
| 252 | * Returns a null string on error. | ||
| 253 | */ | ||
| 254 | extern char *prom_firstprop(int node); | ||
| 255 | |||
| 256 | /* Returns the next property after the passed property for the given | ||
| 257 | * node. Returns null string on failure. | ||
| 258 | */ | ||
| 259 | extern char *prom_nextprop(int node, char *prev_property); | ||
| 260 | |||
| 261 | /* Returns 1 if the specified node has given property. */ | ||
| 262 | extern int prom_node_has_property(int node, char *property); | ||
| 263 | |||
| 264 | /* Set the indicated property at the given node with the passed value. | ||
| 265 | * Returns the number of bytes of your value that the prom took. | ||
| 266 | */ | ||
| 267 | extern int prom_setprop(int node, char *prop_name, char *prop_value, | ||
| 268 | int value_size); | ||
| 269 | |||
| 270 | extern int prom_pathtoinode(char *path); | ||
| 271 | extern int prom_inst2pkg(int); | ||
| 272 | |||
| 273 | /* Dorking with Bus ranges... */ | ||
| 274 | |||
| 275 | /* Adjust reg values with the passed ranges. */ | ||
| 276 | extern void prom_adjust_regs(struct linux_prom_registers *regp, int nregs, | ||
| 277 | struct linux_prom_ranges *rangep, int nranges); | ||
| 278 | |||
| 279 | /* Adjust child ranges with the passed parent ranges. */ | ||
| 280 | extern void prom_adjust_ranges(struct linux_prom_ranges *cranges, int ncranges, | ||
| 281 | struct linux_prom_ranges *pranges, int npranges); | ||
| 282 | |||
| 283 | /* Apply promlib probed OBIO ranges to registers. */ | ||
| 284 | extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs); | ||
| 285 | |||
| 286 | /* Apply ranges of any prom node (and optionally parent node as well) to registers. */ | ||
| 287 | extern void prom_apply_generic_ranges(int node, int parent, | ||
| 288 | struct linux_prom_registers *sbusregs, int nregs); | ||
| 289 | |||
| 290 | |||
| 291 | #endif /* !(__SPARC_OPLIB_H) */ | ||
diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h new file mode 100644 index 000000000000..f2b4480cc98a --- /dev/null +++ b/arch/m68k/include/asm/page.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "page_no.h" | ||
| 3 | #else | ||
| 4 | #include "page_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/page_mm.h b/arch/m68k/include/asm/page_mm.h new file mode 100644 index 000000000000..a34b8bad7847 --- /dev/null +++ b/arch/m68k/include/asm/page_mm.h | |||
| @@ -0,0 +1,228 @@ | |||
| 1 | #ifndef _M68K_PAGE_H | ||
| 2 | #define _M68K_PAGE_H | ||
| 3 | |||
| 4 | #include <linux/const.h> | ||
| 5 | |||
| 6 | /* PAGE_SHIFT determines the page size */ | ||
| 7 | #ifndef CONFIG_SUN3 | ||
| 8 | #define PAGE_SHIFT (12) | ||
| 9 | #else | ||
| 10 | #define PAGE_SHIFT (13) | ||
| 11 | #endif | ||
| 12 | #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) | ||
| 13 | #define PAGE_MASK (~(PAGE_SIZE-1)) | ||
| 14 | |||
| 15 | #include <asm/setup.h> | ||
| 16 | |||
| 17 | #if PAGE_SHIFT < 13 | ||
| 18 | #define THREAD_SIZE (8192) | ||
| 19 | #else | ||
| 20 | #define THREAD_SIZE PAGE_SIZE | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | |||
| 25 | #include <linux/compiler.h> | ||
| 26 | |||
| 27 | #include <asm/module.h> | ||
| 28 | |||
| 29 | #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) | ||
| 30 | #define free_user_page(page, addr) free_page(addr) | ||
| 31 | |||
| 32 | /* | ||
| 33 | * We don't need to check for alignment etc. | ||
| 34 | */ | ||
| 35 | #ifdef CPU_M68040_OR_M68060_ONLY | ||
| 36 | static inline void copy_page(void *to, void *from) | ||
| 37 | { | ||
| 38 | unsigned long tmp; | ||
| 39 | |||
| 40 | __asm__ __volatile__("1:\t" | ||
| 41 | ".chip 68040\n\t" | ||
| 42 | "move16 %1@+,%0@+\n\t" | ||
| 43 | "move16 %1@+,%0@+\n\t" | ||
| 44 | ".chip 68k\n\t" | ||
| 45 | "dbra %2,1b\n\t" | ||
| 46 | : "=a" (to), "=a" (from), "=d" (tmp) | ||
| 47 | : "0" (to), "1" (from) , "2" (PAGE_SIZE / 32 - 1) | ||
| 48 | ); | ||
| 49 | } | ||
| 50 | |||
| 51 | static inline void clear_page(void *page) | ||
| 52 | { | ||
| 53 | unsigned long tmp; | ||
| 54 | unsigned long *sp = page; | ||
| 55 | |||
| 56 | *sp++ = 0; | ||
| 57 | *sp++ = 0; | ||
| 58 | *sp++ = 0; | ||
| 59 | *sp++ = 0; | ||
| 60 | |||
| 61 | __asm__ __volatile__("1:\t" | ||
| 62 | ".chip 68040\n\t" | ||
| 63 | "move16 %2@+,%0@+\n\t" | ||
| 64 | ".chip 68k\n\t" | ||
| 65 | "subqw #8,%2\n\t" | ||
| 66 | "subqw #8,%2\n\t" | ||
| 67 | "dbra %1,1b\n\t" | ||
| 68 | : "=a" (sp), "=d" (tmp) | ||
| 69 | : "a" (page), "0" (sp), | ||
| 70 | "1" ((PAGE_SIZE - 16) / 16 - 1)); | ||
| 71 | } | ||
| 72 | |||
| 73 | #else | ||
| 74 | #define clear_page(page) memset((page), 0, PAGE_SIZE) | ||
| 75 | #define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) | ||
| 76 | #endif | ||
| 77 | |||
| 78 | #define clear_user_page(addr, vaddr, page) \ | ||
| 79 | do { clear_page(addr); \ | ||
| 80 | flush_dcache_page(page); \ | ||
| 81 | } while (0) | ||
| 82 | #define copy_user_page(to, from, vaddr, page) \ | ||
| 83 | do { copy_page(to, from); \ | ||
| 84 | flush_dcache_page(page); \ | ||
| 85 | } while (0) | ||
| 86 | |||
| 87 | /* | ||
| 88 | * These are used to make use of C type-checking.. | ||
| 89 | */ | ||
| 90 | typedef struct { unsigned long pte; } pte_t; | ||
| 91 | typedef struct { unsigned long pmd[16]; } pmd_t; | ||
| 92 | typedef struct { unsigned long pgd; } pgd_t; | ||
| 93 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
| 94 | typedef struct page *pgtable_t; | ||
| 95 | |||
| 96 | #define pte_val(x) ((x).pte) | ||
| 97 | #define pmd_val(x) ((&x)->pmd[0]) | ||
| 98 | #define pgd_val(x) ((x).pgd) | ||
| 99 | #define pgprot_val(x) ((x).pgprot) | ||
| 100 | |||
| 101 | #define __pte(x) ((pte_t) { (x) } ) | ||
| 102 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
| 103 | #define __pgd(x) ((pgd_t) { (x) } ) | ||
| 104 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
| 105 | |||
| 106 | #endif /* !__ASSEMBLY__ */ | ||
| 107 | |||
| 108 | #include <asm/page_offset.h> | ||
| 109 | |||
| 110 | #define PAGE_OFFSET (PAGE_OFFSET_RAW) | ||
| 111 | |||
| 112 | #ifndef __ASSEMBLY__ | ||
| 113 | |||
| 114 | extern unsigned long m68k_memoffset; | ||
| 115 | |||
| 116 | #ifndef CONFIG_SUN3 | ||
| 117 | |||
| 118 | #define WANT_PAGE_VIRTUAL | ||
| 119 | |||
| 120 | static inline unsigned long ___pa(void *vaddr) | ||
| 121 | { | ||
| 122 | unsigned long paddr; | ||
| 123 | asm ( | ||
| 124 | "1: addl #0,%0\n" | ||
| 125 | m68k_fixup(%c2, 1b+2) | ||
| 126 | : "=r" (paddr) | ||
| 127 | : "0" (vaddr), "i" (m68k_fixup_memoffset)); | ||
| 128 | return paddr; | ||
| 129 | } | ||
| 130 | #define __pa(vaddr) ___pa((void *)(vaddr)) | ||
| 131 | static inline void *__va(unsigned long paddr) | ||
| 132 | { | ||
| 133 | void *vaddr; | ||
| 134 | asm ( | ||
| 135 | "1: subl #0,%0\n" | ||
| 136 | m68k_fixup(%c2, 1b+2) | ||
| 137 | : "=r" (vaddr) | ||
| 138 | : "0" (paddr), "i" (m68k_fixup_memoffset)); | ||
| 139 | return vaddr; | ||
| 140 | } | ||
| 141 | |||
| 142 | #else /* !CONFIG_SUN3 */ | ||
| 143 | /* This #define is a horrible hack to suppress lots of warnings. --m */ | ||
| 144 | #define __pa(x) ___pa((unsigned long)(x)) | ||
| 145 | static inline unsigned long ___pa(unsigned long x) | ||
| 146 | { | ||
| 147 | if(x == 0) | ||
| 148 | return 0; | ||
| 149 | if(x >= PAGE_OFFSET) | ||
| 150 | return (x-PAGE_OFFSET); | ||
| 151 | else | ||
| 152 | return (x+0x2000000); | ||
| 153 | } | ||
| 154 | |||
| 155 | static inline void *__va(unsigned long x) | ||
| 156 | { | ||
| 157 | if(x == 0) | ||
| 158 | return (void *)0; | ||
| 159 | |||
| 160 | if(x < 0x2000000) | ||
| 161 | return (void *)(x+PAGE_OFFSET); | ||
| 162 | else | ||
| 163 | return (void *)(x-0x2000000); | ||
| 164 | } | ||
| 165 | #endif /* CONFIG_SUN3 */ | ||
| 166 | |||
| 167 | /* | ||
| 168 | * NOTE: virtual isn't really correct, actually it should be the offset into the | ||
| 169 | * memory node, but we have no highmem, so that works for now. | ||
| 170 | * TODO: implement (fast) pfn<->pgdat_idx conversion functions, this makes lots | ||
| 171 | * of the shifts unnecessary. | ||
| 172 | */ | ||
| 173 | #define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) | ||
| 174 | #define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) | ||
| 175 | |||
| 176 | extern int m68k_virt_to_node_shift; | ||
| 177 | |||
| 178 | #ifdef CONFIG_SINGLE_MEMORY_CHUNK | ||
| 179 | #define __virt_to_node(addr) (&pg_data_map[0]) | ||
| 180 | #else | ||
| 181 | extern struct pglist_data *pg_data_table[]; | ||
| 182 | |||
| 183 | static inline __attribute_const__ int __virt_to_node_shift(void) | ||
| 184 | { | ||
| 185 | int shift; | ||
| 186 | |||
| 187 | asm ( | ||
| 188 | "1: moveq #0,%0\n" | ||
| 189 | m68k_fixup(%c1, 1b) | ||
| 190 | : "=d" (shift) | ||
| 191 | : "i" (m68k_fixup_vnode_shift)); | ||
| 192 | return shift; | ||
| 193 | } | ||
| 194 | |||
| 195 | #define __virt_to_node(addr) (pg_data_table[(unsigned long)(addr) >> __virt_to_node_shift()]) | ||
| 196 | #endif | ||
| 197 | |||
| 198 | #define virt_to_page(addr) ({ \ | ||
| 199 | pfn_to_page(virt_to_pfn(addr)); \ | ||
| 200 | }) | ||
| 201 | #define page_to_virt(page) ({ \ | ||
| 202 | pfn_to_virt(page_to_pfn(page)); \ | ||
| 203 | }) | ||
| 204 | |||
| 205 | #define pfn_to_page(pfn) ({ \ | ||
| 206 | unsigned long __pfn = (pfn); \ | ||
| 207 | struct pglist_data *pgdat; \ | ||
| 208 | pgdat = __virt_to_node((unsigned long)pfn_to_virt(__pfn)); \ | ||
| 209 | pgdat->node_mem_map + (__pfn - pgdat->node_start_pfn); \ | ||
| 210 | }) | ||
| 211 | #define page_to_pfn(_page) ({ \ | ||
| 212 | struct page *__p = (_page); \ | ||
| 213 | struct pglist_data *pgdat; \ | ||
| 214 | pgdat = &pg_data_map[page_to_nid(__p)]; \ | ||
| 215 | ((__p) - pgdat->node_mem_map) + pgdat->node_start_pfn; \ | ||
| 216 | }) | ||
| 217 | |||
| 218 | #define virt_addr_valid(kaddr) ((void *)(kaddr) >= (void *)PAGE_OFFSET && (void *)(kaddr) < high_memory) | ||
| 219 | #define pfn_valid(pfn) virt_addr_valid(pfn_to_virt(pfn)) | ||
| 220 | |||
| 221 | #endif /* __ASSEMBLY__ */ | ||
| 222 | |||
| 223 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ | ||
| 224 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | ||
| 225 | |||
| 226 | #include <asm-generic/page.h> | ||
| 227 | |||
| 228 | #endif /* _M68K_PAGE_H */ | ||
diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h new file mode 100644 index 000000000000..3a1ede4544cb --- /dev/null +++ b/arch/m68k/include/asm/page_no.h | |||
| @@ -0,0 +1,77 @@ | |||
| 1 | #ifndef _M68KNOMMU_PAGE_H | ||
| 2 | #define _M68KNOMMU_PAGE_H | ||
| 3 | |||
| 4 | /* PAGE_SHIFT determines the page size */ | ||
| 5 | |||
| 6 | #define PAGE_SHIFT (12) | ||
| 7 | #define PAGE_SIZE (1UL << PAGE_SHIFT) | ||
| 8 | #define PAGE_MASK (~(PAGE_SIZE-1)) | ||
| 9 | |||
| 10 | #include <asm/setup.h> | ||
| 11 | |||
| 12 | #ifndef __ASSEMBLY__ | ||
| 13 | |||
| 14 | #define get_user_page(vaddr) __get_free_page(GFP_KERNEL) | ||
| 15 | #define free_user_page(page, addr) free_page(addr) | ||
| 16 | |||
| 17 | #define clear_page(page) memset((page), 0, PAGE_SIZE) | ||
| 18 | #define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) | ||
| 19 | |||
| 20 | #define clear_user_page(page, vaddr, pg) clear_page(page) | ||
| 21 | #define copy_user_page(to, from, vaddr, pg) copy_page(to, from) | ||
| 22 | |||
| 23 | #define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ | ||
| 24 | alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) | ||
| 25 | #define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE | ||
| 26 | |||
| 27 | /* | ||
| 28 | * These are used to make use of C type-checking.. | ||
| 29 | */ | ||
| 30 | typedef struct { unsigned long pte; } pte_t; | ||
| 31 | typedef struct { unsigned long pmd[16]; } pmd_t; | ||
| 32 | typedef struct { unsigned long pgd; } pgd_t; | ||
| 33 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
| 34 | typedef struct page *pgtable_t; | ||
| 35 | |||
| 36 | #define pte_val(x) ((x).pte) | ||
| 37 | #define pmd_val(x) ((&x)->pmd[0]) | ||
| 38 | #define pgd_val(x) ((x).pgd) | ||
| 39 | #define pgprot_val(x) ((x).pgprot) | ||
| 40 | |||
| 41 | #define __pte(x) ((pte_t) { (x) } ) | ||
| 42 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
| 43 | #define __pgd(x) ((pgd_t) { (x) } ) | ||
| 44 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
| 45 | |||
| 46 | extern unsigned long memory_start; | ||
| 47 | extern unsigned long memory_end; | ||
| 48 | |||
| 49 | #endif /* !__ASSEMBLY__ */ | ||
| 50 | |||
| 51 | #include <asm/page_offset.h> | ||
| 52 | |||
| 53 | #define PAGE_OFFSET (PAGE_OFFSET_RAW) | ||
| 54 | |||
| 55 | #ifndef __ASSEMBLY__ | ||
| 56 | |||
| 57 | #define __pa(vaddr) virt_to_phys((void *)(vaddr)) | ||
| 58 | #define __va(paddr) phys_to_virt((unsigned long)(paddr)) | ||
| 59 | |||
| 60 | #define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) | ||
| 61 | #define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) | ||
| 62 | |||
| 63 | #define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) | ||
| 64 | #define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) | ||
| 65 | |||
| 66 | #define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) | ||
| 67 | #define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) | ||
| 68 | #define pfn_valid(pfn) ((pfn) < max_mapnr) | ||
| 69 | |||
| 70 | #define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ | ||
| 71 | ((void *)(kaddr) < (void *)memory_end)) | ||
| 72 | |||
| 73 | #endif /* __ASSEMBLY__ */ | ||
| 74 | |||
| 75 | #include <asm-generic/page.h> | ||
| 76 | |||
| 77 | #endif /* _M68KNOMMU_PAGE_H */ | ||
diff --git a/arch/m68k/include/asm/page_offset.h b/arch/m68k/include/asm/page_offset.h new file mode 100644 index 000000000000..66455c849fbb --- /dev/null +++ b/arch/m68k/include/asm/page_offset.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "page_offset_no.h" | ||
| 3 | #else | ||
| 4 | #include "page_offset_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/page_offset_mm.h b/arch/m68k/include/asm/page_offset_mm.h new file mode 100644 index 000000000000..1cbdb7f30ac2 --- /dev/null +++ b/arch/m68k/include/asm/page_offset_mm.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | |||
| 2 | /* This handles the memory map.. */ | ||
| 3 | #ifndef CONFIG_SUN3 | ||
| 4 | #define PAGE_OFFSET_RAW 0x00000000 | ||
| 5 | #else | ||
| 6 | #define PAGE_OFFSET_RAW 0x0E000000 | ||
| 7 | #endif | ||
| 8 | |||
diff --git a/arch/m68k/include/asm/page_offset_no.h b/arch/m68k/include/asm/page_offset_no.h new file mode 100644 index 000000000000..d4e73e0ba646 --- /dev/null +++ b/arch/m68k/include/asm/page_offset_no.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | |||
| 2 | |||
| 3 | /* This handles the memory map.. */ | ||
| 4 | #define PAGE_OFFSET_RAW CONFIG_RAMBASE | ||
| 5 | |||
diff --git a/arch/m68k/include/asm/param.h b/arch/m68k/include/asm/param.h new file mode 100644 index 000000000000..40d1112a4588 --- /dev/null +++ b/arch/m68k/include/asm/param.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "param_no.h" | ||
| 3 | #else | ||
| 4 | #include "param_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/param_mm.h b/arch/m68k/include/asm/param_mm.h new file mode 100644 index 000000000000..536a27888358 --- /dev/null +++ b/arch/m68k/include/asm/param_mm.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | #ifndef _M68K_PARAM_H | ||
| 2 | #define _M68K_PARAM_H | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ | ||
| 5 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ | ||
| 6 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | ||
| 7 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #ifndef HZ | ||
| 11 | #define HZ 100 | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define EXEC_PAGESIZE 8192 | ||
| 15 | |||
| 16 | #ifndef NOGROUP | ||
| 17 | #define NOGROUP (-1) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 21 | |||
| 22 | #endif /* _M68K_PARAM_H */ | ||
diff --git a/arch/m68k/include/asm/param_no.h b/arch/m68k/include/asm/param_no.h new file mode 100644 index 000000000000..6044397adb64 --- /dev/null +++ b/arch/m68k/include/asm/param_no.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | #ifndef _M68KNOMMU_PARAM_H | ||
| 2 | #define _M68KNOMMU_PARAM_H | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ | ||
| 5 | #define HZ CONFIG_HZ | ||
| 6 | #define USER_HZ HZ | ||
| 7 | #define CLOCKS_PER_SEC (USER_HZ) | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #ifndef HZ | ||
| 11 | #define HZ 100 | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define EXEC_PAGESIZE 4096 | ||
| 15 | |||
| 16 | #ifndef NOGROUP | ||
| 17 | #define NOGROUP (-1) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 21 | |||
| 22 | #endif /* _M68KNOMMU_PARAM_H */ | ||
diff --git a/arch/m68k/include/asm/parport.h b/arch/m68k/include/asm/parport.h new file mode 100644 index 000000000000..646b1872f73b --- /dev/null +++ b/arch/m68k/include/asm/parport.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * parport.h: platform-specific PC-style parport initialisation | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk> | ||
| 5 | * | ||
| 6 | * This file should only be included by drivers/parport/parport_pc.c. | ||
| 7 | * | ||
| 8 | * RZ: for use with Q40 and other ISA machines | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef _ASM_M68K_PARPORT_H | ||
| 12 | #define _ASM_M68K_PARPORT_H 1 | ||
| 13 | |||
| 14 | #define insl(port,buf,len) isa_insb(port,buf,(len)<<2) | ||
| 15 | #define outsl(port,buf,len) isa_outsb(port,buf,(len)<<2) | ||
| 16 | |||
| 17 | /* no dma, or IRQ autoprobing */ | ||
| 18 | static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma); | ||
| 19 | static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma) | ||
| 20 | { | ||
| 21 | if (! (MACH_IS_Q40)) | ||
| 22 | return 0; /* count=0 */ | ||
| 23 | return parport_pc_find_isa_ports (PARPORT_IRQ_NONE, PARPORT_DMA_NONE); | ||
| 24 | } | ||
| 25 | |||
| 26 | #endif /* !(_ASM_M68K_PARPORT_H) */ | ||
diff --git a/arch/m68k/include/asm/pci.h b/arch/m68k/include/asm/pci.h new file mode 100644 index 000000000000..dbea95373080 --- /dev/null +++ b/arch/m68k/include/asm/pci.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "pci_no.h" | ||
| 3 | #else | ||
| 4 | #include "pci_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/pci_mm.h b/arch/m68k/include/asm/pci_mm.h new file mode 100644 index 000000000000..4ad0aea48ab4 --- /dev/null +++ b/arch/m68k/include/asm/pci_mm.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | #ifndef _ASM_M68K_PCI_H | ||
| 2 | #define _ASM_M68K_PCI_H | ||
| 3 | |||
| 4 | #include <asm-generic/pci-dma-compat.h> | ||
| 5 | |||
| 6 | /* The PCI address space does equal the physical memory | ||
| 7 | * address space. The networking and block device layers use | ||
| 8 | * this boolean for bounce buffer decisions. | ||
| 9 | */ | ||
| 10 | #define PCI_DMA_BUS_IS_PHYS (1) | ||
| 11 | |||
| 12 | #endif /* _ASM_M68K_PCI_H */ | ||
diff --git a/arch/m68k/include/asm/pci_no.h b/arch/m68k/include/asm/pci_no.h new file mode 100644 index 000000000000..9abbc03c73ee --- /dev/null +++ b/arch/m68k/include/asm/pci_no.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | #ifndef M68KNOMMU_PCI_H | ||
| 2 | #define M68KNOMMU_PCI_H | ||
| 3 | |||
| 4 | #include <asm/pci_mm.h> | ||
| 5 | |||
| 6 | #ifdef CONFIG_COMEMPCI | ||
| 7 | /* | ||
| 8 | * These are pretty much arbitary with the CoMEM implementation. | ||
| 9 | * We have the whole address space to ourselves. | ||
| 10 | */ | ||
| 11 | #define PCIBIOS_MIN_IO 0x100 | ||
| 12 | #define PCIBIOS_MIN_MEM 0x00010000 | ||
| 13 | |||
| 14 | #define pcibios_scan_all_fns(a, b) 0 | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Return whether the given PCI device DMA address mask can | ||
| 18 | * be supported properly. For example, if your device can | ||
| 19 | * only drive the low 24-bits during PCI bus mastering, then | ||
| 20 | * you would pass 0x00ffffff as the mask to this function. | ||
| 21 | */ | ||
| 22 | static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) | ||
| 23 | { | ||
| 24 | return 1; | ||
| 25 | } | ||
| 26 | |||
| 27 | #endif /* CONFIG_COMEMPCI */ | ||
| 28 | |||
| 29 | #endif /* M68KNOMMU_PCI_H */ | ||
diff --git a/arch/m68k/include/asm/percpu.h b/arch/m68k/include/asm/percpu.h new file mode 100644 index 000000000000..0859d048faf5 --- /dev/null +++ b/arch/m68k/include/asm/percpu.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef __ASM_M68K_PERCPU_H | ||
| 2 | #define __ASM_M68K_PERCPU_H | ||
| 3 | |||
| 4 | #include <asm-generic/percpu.h> | ||
| 5 | |||
| 6 | #endif /* __ASM_M68K_PERCPU_H */ | ||
diff --git a/arch/m68k/include/asm/pgalloc.h b/arch/m68k/include/asm/pgalloc.h new file mode 100644 index 000000000000..059cb73e78fc --- /dev/null +++ b/arch/m68k/include/asm/pgalloc.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "pgalloc_no.h" | ||
| 3 | #else | ||
| 4 | #include "pgalloc_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/pgalloc_mm.h b/arch/m68k/include/asm/pgalloc_mm.h new file mode 100644 index 000000000000..4cb1a57ab763 --- /dev/null +++ b/arch/m68k/include/asm/pgalloc_mm.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | |||
| 2 | #ifndef M68K_PGALLOC_H | ||
| 3 | #define M68K_PGALLOC_H | ||
| 4 | |||
| 5 | #include <linux/mm.h> | ||
| 6 | #include <linux/highmem.h> | ||
| 7 | #include <asm/setup.h> | ||
| 8 | #include <asm/virtconvert.h> | ||
| 9 | |||
| 10 | |||
| 11 | #ifdef CONFIG_SUN3 | ||
| 12 | #include <asm/sun3_pgalloc.h> | ||
| 13 | #else | ||
| 14 | #include <asm/motorola_pgalloc.h> | ||
| 15 | #endif | ||
| 16 | |||
| 17 | extern void m68k_setup_node(int node); | ||
| 18 | |||
| 19 | #endif /* M68K_PGALLOC_H */ | ||
diff --git a/arch/m68k/include/asm/pgalloc_no.h b/arch/m68k/include/asm/pgalloc_no.h new file mode 100644 index 000000000000..d6352f671ec0 --- /dev/null +++ b/arch/m68k/include/asm/pgalloc_no.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef _M68KNOMMU_PGALLOC_H | ||
| 2 | #define _M68KNOMMU_PGALLOC_H | ||
| 3 | |||
| 4 | #include <asm/setup.h> | ||
| 5 | |||
| 6 | #define check_pgt_cache() do { } while (0) | ||
| 7 | |||
| 8 | #endif /* _M68KNOMMU_PGALLOC_H */ | ||
diff --git a/arch/m68k/include/asm/pgtable.h b/arch/m68k/include/asm/pgtable.h new file mode 100644 index 000000000000..ee6759eb445a --- /dev/null +++ b/arch/m68k/include/asm/pgtable.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "pgtable_no.h" | ||
| 3 | #else | ||
| 4 | #include "pgtable_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h new file mode 100644 index 000000000000..0b604f0f192d --- /dev/null +++ b/arch/m68k/include/asm/pgtable_mm.h | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | #ifndef _M68K_PGTABLE_H | ||
| 2 | #define _M68K_PGTABLE_H | ||
| 3 | |||
| 4 | #include <asm-generic/4level-fixup.h> | ||
| 5 | |||
| 6 | #include <asm/setup.h> | ||
| 7 | |||
| 8 | #ifndef __ASSEMBLY__ | ||
| 9 | #include <asm/processor.h> | ||
| 10 | #include <linux/sched.h> | ||
| 11 | #include <linux/threads.h> | ||
| 12 | |||
| 13 | /* | ||
| 14 | * This file contains the functions and defines necessary to modify and use | ||
| 15 | * the m68k page table tree. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <asm/virtconvert.h> | ||
| 19 | |||
| 20 | /* Certain architectures need to do special things when pte's | ||
| 21 | * within a page table are directly modified. Thus, the following | ||
| 22 | * hook is made available. | ||
| 23 | */ | ||
| 24 | #define set_pte(pteptr, pteval) \ | ||
| 25 | do{ \ | ||
| 26 | *(pteptr) = (pteval); \ | ||
| 27 | } while(0) | ||
| 28 | #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) | ||
| 29 | |||
| 30 | |||
| 31 | /* PMD_SHIFT determines the size of the area a second-level page table can map */ | ||
| 32 | #ifdef CONFIG_SUN3 | ||
| 33 | #define PMD_SHIFT 17 | ||
| 34 | #else | ||
| 35 | #define PMD_SHIFT 22 | ||
| 36 | #endif | ||
| 37 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
| 38 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
| 39 | |||
| 40 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ | ||
| 41 | #ifdef CONFIG_SUN3 | ||
| 42 | #define PGDIR_SHIFT 17 | ||
| 43 | #else | ||
| 44 | #define PGDIR_SHIFT 25 | ||
| 45 | #endif | ||
| 46 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
| 47 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
| 48 | |||
| 49 | /* | ||
| 50 | * entries per page directory level: the m68k is configured as three-level, | ||
| 51 | * so we do have PMD level physically. | ||
| 52 | */ | ||
| 53 | #ifdef CONFIG_SUN3 | ||
| 54 | #define PTRS_PER_PTE 16 | ||
| 55 | #define PTRS_PER_PMD 1 | ||
| 56 | #define PTRS_PER_PGD 2048 | ||
| 57 | #else | ||
| 58 | #define PTRS_PER_PTE 1024 | ||
| 59 | #define PTRS_PER_PMD 8 | ||
| 60 | #define PTRS_PER_PGD 128 | ||
| 61 | #endif | ||
| 62 | #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) | ||
| 63 | #define FIRST_USER_ADDRESS 0 | ||
| 64 | |||
| 65 | /* Virtual address region for use by kernel_map() */ | ||
| 66 | #ifdef CONFIG_SUN3 | ||
| 67 | #define KMAP_START 0x0DC00000 | ||
| 68 | #define KMAP_END 0x0E000000 | ||
| 69 | #else | ||
| 70 | #define KMAP_START 0xd0000000 | ||
| 71 | #define KMAP_END 0xf0000000 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef CONFIG_SUN3 | ||
| 75 | /* Just any arbitrary offset to the start of the vmalloc VM area: the | ||
| 76 | * current 8MB value just means that there will be a 8MB "hole" after the | ||
| 77 | * physical memory until the kernel virtual memory starts. That means that | ||
| 78 | * any out-of-bounds memory accesses will hopefully be caught. | ||
| 79 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
| 80 | * area for the same reason. ;) | ||
| 81 | */ | ||
| 82 | #define VMALLOC_OFFSET (8*1024*1024) | ||
| 83 | #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) | ||
| 84 | #define VMALLOC_END KMAP_START | ||
| 85 | #else | ||
| 86 | extern unsigned long vmalloc_end; | ||
| 87 | #define VMALLOC_START 0x0f800000 | ||
| 88 | #define VMALLOC_END vmalloc_end | ||
| 89 | #endif /* CONFIG_SUN3 */ | ||
| 90 | |||
| 91 | /* zero page used for uninitialized stuff */ | ||
| 92 | extern void *empty_zero_page; | ||
| 93 | |||
| 94 | /* | ||
| 95 | * ZERO_PAGE is a global shared page that is always zero: used | ||
| 96 | * for zero-mapped memory areas etc.. | ||
| 97 | */ | ||
| 98 | #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) | ||
| 99 | |||
| 100 | /* number of bits that fit into a memory pointer */ | ||
| 101 | #define BITS_PER_PTR (8*sizeof(unsigned long)) | ||
| 102 | |||
| 103 | /* to align the pointer to a pointer address */ | ||
| 104 | #define PTR_MASK (~(sizeof(void*)-1)) | ||
| 105 | |||
| 106 | /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ | ||
| 107 | /* 64-bit machines, beware! SRB. */ | ||
| 108 | #define SIZEOF_PTR_LOG2 2 | ||
| 109 | |||
| 110 | extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode); | ||
| 111 | |||
| 112 | /* | ||
| 113 | * The m68k doesn't have any external MMU info: the kernel page | ||
| 114 | * tables contain all the necessary information. The Sun3 does, but | ||
| 115 | * they are updated on demand. | ||
| 116 | */ | ||
| 117 | static inline void update_mmu_cache(struct vm_area_struct *vma, | ||
| 118 | unsigned long address, pte_t pte) | ||
| 119 | { | ||
| 120 | } | ||
| 121 | |||
| 122 | #endif /* !__ASSEMBLY__ */ | ||
| 123 | |||
| 124 | #define kern_addr_valid(addr) (1) | ||
| 125 | |||
| 126 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ | ||
| 127 | remap_pfn_range(vma, vaddr, pfn, size, prot) | ||
| 128 | |||
| 129 | /* MMU-specific headers */ | ||
| 130 | |||
| 131 | #ifdef CONFIG_SUN3 | ||
| 132 | #include <asm/sun3_pgtable.h> | ||
| 133 | #else | ||
| 134 | #include <asm/motorola_pgtable.h> | ||
| 135 | #endif | ||
| 136 | |||
| 137 | #ifndef __ASSEMBLY__ | ||
| 138 | #include <asm-generic/pgtable.h> | ||
| 139 | |||
| 140 | /* | ||
| 141 | * Macro to mark a page protection value as "uncacheable". | ||
| 142 | */ | ||
| 143 | #ifdef SUN3_PAGE_NOCACHE | ||
| 144 | # define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE | ||
| 145 | #else | ||
| 146 | # define __SUN3_PAGE_NOCACHE 0 | ||
| 147 | #endif | ||
| 148 | #define pgprot_noncached(prot) \ | ||
| 149 | (MMU_IS_SUN3 \ | ||
| 150 | ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \ | ||
| 151 | : ((MMU_IS_851 || MMU_IS_030) \ | ||
| 152 | ? (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE030)) \ | ||
| 153 | : (MMU_IS_040 || MMU_IS_060) \ | ||
| 154 | ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \ | ||
| 155 | : (prot))) | ||
| 156 | |||
| 157 | #endif /* !__ASSEMBLY__ */ | ||
| 158 | |||
| 159 | /* | ||
| 160 | * No page table caches to initialise | ||
| 161 | */ | ||
| 162 | #define pgtable_cache_init() do { } while (0) | ||
| 163 | |||
| 164 | #define check_pgt_cache() do { } while (0) | ||
| 165 | |||
| 166 | #endif /* _M68K_PGTABLE_H */ | ||
diff --git a/arch/m68k/include/asm/pgtable_no.h b/arch/m68k/include/asm/pgtable_no.h new file mode 100644 index 000000000000..46251016e821 --- /dev/null +++ b/arch/m68k/include/asm/pgtable_no.h | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | #ifndef _M68KNOMMU_PGTABLE_H | ||
| 2 | #define _M68KNOMMU_PGTABLE_H | ||
| 3 | |||
| 4 | #include <asm-generic/4level-fixup.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * (C) Copyright 2000-2002, Greg Ungerer <gerg@snapgear.com> | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/slab.h> | ||
| 11 | #include <asm/processor.h> | ||
| 12 | #include <asm/page.h> | ||
| 13 | #include <asm/io.h> | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Trivial page table functions. | ||
| 17 | */ | ||
| 18 | #define pgd_present(pgd) (1) | ||
| 19 | #define pgd_none(pgd) (0) | ||
| 20 | #define pgd_bad(pgd) (0) | ||
| 21 | #define pgd_clear(pgdp) | ||
| 22 | #define kern_addr_valid(addr) (1) | ||
| 23 | #define pmd_offset(a, b) ((void *)0) | ||
| 24 | |||
| 25 | #define PAGE_NONE __pgprot(0) | ||
| 26 | #define PAGE_SHARED __pgprot(0) | ||
| 27 | #define PAGE_COPY __pgprot(0) | ||
| 28 | #define PAGE_READONLY __pgprot(0) | ||
| 29 | #define PAGE_KERNEL __pgprot(0) | ||
| 30 | |||
| 31 | extern void paging_init(void); | ||
| 32 | #define swapper_pg_dir ((pgd_t *) 0) | ||
| 33 | |||
| 34 | #define __swp_type(x) (0) | ||
| 35 | #define __swp_offset(x) (0) | ||
| 36 | #define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) | ||
| 37 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
| 38 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | ||
| 39 | |||
| 40 | static inline int pte_file(pte_t pte) { return 0; } | ||
| 41 | |||
| 42 | /* | ||
| 43 | * ZERO_PAGE is a global shared page that is always zero: used | ||
| 44 | * for zero-mapped memory areas etc.. | ||
| 45 | */ | ||
| 46 | #define ZERO_PAGE(vaddr) (virt_to_page(0)) | ||
| 47 | |||
| 48 | /* | ||
| 49 | * These would be in other places but having them here reduces the diffs. | ||
| 50 | */ | ||
| 51 | extern unsigned int kobjsize(const void *objp); | ||
| 52 | |||
| 53 | /* | ||
| 54 | * No page table caches to initialise. | ||
| 55 | */ | ||
| 56 | #define pgtable_cache_init() do { } while (0) | ||
| 57 | |||
| 58 | #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ | ||
| 59 | remap_pfn_range(vma, vaddr, pfn, size, prot) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * All 32bit addresses are effectively valid for vmalloc... | ||
| 63 | * Sort of meaningless for non-VM targets. | ||
| 64 | */ | ||
| 65 | #define VMALLOC_START 0 | ||
| 66 | #define VMALLOC_END 0xffffffff | ||
| 67 | |||
| 68 | #include <asm-generic/pgtable.h> | ||
| 69 | |||
| 70 | #endif /* _M68KNOMMU_PGTABLE_H */ | ||
diff --git a/arch/m68k/include/asm/poll.h b/arch/m68k/include/asm/poll.h new file mode 100644 index 000000000000..f080fcdb61bf --- /dev/null +++ b/arch/m68k/include/asm/poll.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | #ifndef __m68k_POLL_H | ||
| 2 | #define __m68k_POLL_H | ||
| 3 | |||
| 4 | #define POLLWRNORM POLLOUT | ||
| 5 | #define POLLWRBAND 256 | ||
| 6 | |||
| 7 | #include <asm-generic/poll.h> | ||
| 8 | |||
| 9 | #endif | ||
diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h new file mode 100644 index 000000000000..63cdcc142d93 --- /dev/null +++ b/arch/m68k/include/asm/posix_types.h | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | #ifndef __ARCH_M68K_POSIX_TYPES_H | ||
| 2 | #define __ARCH_M68K_POSIX_TYPES_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is generally used by user-level software, so you need to | ||
| 6 | * be a little careful about namespace pollution etc. Also, we cannot | ||
| 7 | * assume GCC is being used. | ||
| 8 | */ | ||
| 9 | |||
| 10 | typedef unsigned long __kernel_ino_t; | ||
| 11 | typedef unsigned short __kernel_mode_t; | ||
| 12 | typedef unsigned short __kernel_nlink_t; | ||
| 13 | typedef long __kernel_off_t; | ||
| 14 | typedef int __kernel_pid_t; | ||
| 15 | typedef unsigned short __kernel_ipc_pid_t; | ||
| 16 | typedef unsigned short __kernel_uid_t; | ||
| 17 | typedef unsigned short __kernel_gid_t; | ||
| 18 | typedef unsigned int __kernel_size_t; | ||
| 19 | typedef int __kernel_ssize_t; | ||
| 20 | typedef int __kernel_ptrdiff_t; | ||
| 21 | typedef long __kernel_time_t; | ||
| 22 | typedef long __kernel_suseconds_t; | ||
| 23 | typedef long __kernel_clock_t; | ||
| 24 | typedef int __kernel_timer_t; | ||
| 25 | typedef int __kernel_clockid_t; | ||
| 26 | typedef int __kernel_daddr_t; | ||
| 27 | typedef char * __kernel_caddr_t; | ||
| 28 | typedef unsigned short __kernel_uid16_t; | ||
| 29 | typedef unsigned short __kernel_gid16_t; | ||
| 30 | typedef unsigned int __kernel_uid32_t; | ||
| 31 | typedef unsigned int __kernel_gid32_t; | ||
| 32 | |||
| 33 | typedef unsigned short __kernel_old_uid_t; | ||
| 34 | typedef unsigned short __kernel_old_gid_t; | ||
| 35 | typedef unsigned short __kernel_old_dev_t; | ||
| 36 | |||
| 37 | #ifdef __GNUC__ | ||
| 38 | typedef long long __kernel_loff_t; | ||
| 39 | #endif | ||
| 40 | |||
| 41 | typedef struct { | ||
| 42 | int val[2]; | ||
| 43 | } __kernel_fsid_t; | ||
| 44 | |||
| 45 | #if defined(__KERNEL__) | ||
| 46 | |||
| 47 | #undef __FD_SET | ||
| 48 | #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) | ||
| 49 | |||
| 50 | #undef __FD_CLR | ||
| 51 | #define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) | ||
| 52 | |||
| 53 | #undef __FD_ISSET | ||
| 54 | #define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) | ||
| 55 | |||
| 56 | #undef __FD_ZERO | ||
| 57 | #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) | ||
| 58 | |||
| 59 | #endif /* defined(__KERNEL__) */ | ||
| 60 | |||
| 61 | #endif | ||
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h new file mode 100644 index 000000000000..fc3f2c22f2b8 --- /dev/null +++ b/arch/m68k/include/asm/processor.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "processor_no.h" | ||
| 3 | #else | ||
| 4 | #include "processor_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/processor_mm.h b/arch/m68k/include/asm/processor_mm.h new file mode 100644 index 000000000000..1f61ef53f0e0 --- /dev/null +++ b/arch/m68k/include/asm/processor_mm.h | |||
| @@ -0,0 +1,130 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68k/processor.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1995 Hamish Macdonald | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_M68K_PROCESSOR_H | ||
| 8 | #define __ASM_M68K_PROCESSOR_H | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Default implementation of macro that returns current | ||
| 12 | * instruction pointer ("program counter"). | ||
| 13 | */ | ||
| 14 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | ||
| 15 | |||
| 16 | #include <linux/thread_info.h> | ||
| 17 | #include <asm/segment.h> | ||
| 18 | #include <asm/fpu.h> | ||
| 19 | #include <asm/ptrace.h> | ||
| 20 | |||
| 21 | static inline unsigned long rdusp(void) | ||
| 22 | { | ||
| 23 | unsigned long usp; | ||
| 24 | |||
| 25 | __asm__ __volatile__("move %/usp,%0" : "=a" (usp)); | ||
| 26 | return usp; | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline void wrusp(unsigned long usp) | ||
| 30 | { | ||
| 31 | __asm__ __volatile__("move %0,%/usp" : : "a" (usp)); | ||
| 32 | } | ||
| 33 | |||
| 34 | /* | ||
| 35 | * User space process size: 3.75GB. This is hardcoded into a few places, | ||
| 36 | * so don't change it unless you know what you are doing. | ||
| 37 | */ | ||
| 38 | #ifndef CONFIG_SUN3 | ||
| 39 | #define TASK_SIZE (0xF0000000UL) | ||
| 40 | #else | ||
| 41 | #define TASK_SIZE (0x0E000000UL) | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #ifdef __KERNEL__ | ||
| 45 | #define STACK_TOP TASK_SIZE | ||
| 46 | #define STACK_TOP_MAX STACK_TOP | ||
| 47 | #endif | ||
| 48 | |||
| 49 | /* This decides where the kernel will search for a free chunk of vm | ||
| 50 | * space during mmap's. | ||
| 51 | */ | ||
| 52 | #ifndef CONFIG_SUN3 | ||
| 53 | #define TASK_UNMAPPED_BASE 0xC0000000UL | ||
| 54 | #else | ||
| 55 | #define TASK_UNMAPPED_BASE 0x0A000000UL | ||
| 56 | #endif | ||
| 57 | #define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr) | ||
| 58 | |||
| 59 | struct thread_struct { | ||
| 60 | unsigned long ksp; /* kernel stack pointer */ | ||
| 61 | unsigned long usp; /* user stack pointer */ | ||
| 62 | unsigned short sr; /* saved status register */ | ||
| 63 | unsigned short fs; /* saved fs (sfc, dfc) */ | ||
| 64 | unsigned long crp[2]; /* cpu root pointer */ | ||
| 65 | unsigned long esp0; /* points to SR of stack frame */ | ||
| 66 | unsigned long faddr; /* info about last fault */ | ||
| 67 | int signo, code; | ||
| 68 | unsigned long fp[8*3]; | ||
| 69 | unsigned long fpcntl[3]; /* fp control regs */ | ||
| 70 | unsigned char fpstate[FPSTATESIZE]; /* floating point state */ | ||
| 71 | struct thread_info info; | ||
| 72 | }; | ||
| 73 | |||
| 74 | #define INIT_THREAD { \ | ||
| 75 | .ksp = sizeof(init_stack) + (unsigned long) init_stack, \ | ||
| 76 | .sr = PS_S, \ | ||
| 77 | .fs = __KERNEL_DS, \ | ||
| 78 | .info = INIT_THREAD_INFO(init_task), \ | ||
| 79 | } | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Do necessary setup to start up a newly executed thread. | ||
| 83 | */ | ||
| 84 | static inline void start_thread(struct pt_regs * regs, unsigned long pc, | ||
| 85 | unsigned long usp) | ||
| 86 | { | ||
| 87 | /* reads from user space */ | ||
| 88 | set_fs(USER_DS); | ||
| 89 | |||
| 90 | regs->pc = pc; | ||
| 91 | regs->sr &= ~0x2000; | ||
| 92 | wrusp(usp); | ||
| 93 | } | ||
| 94 | |||
| 95 | /* Forward declaration, a strange C thing */ | ||
| 96 | struct task_struct; | ||
| 97 | |||
| 98 | /* Free all resources held by a thread. */ | ||
| 99 | static inline void release_thread(struct task_struct *dead_task) | ||
| 100 | { | ||
| 101 | } | ||
| 102 | |||
| 103 | /* Prepare to copy thread state - unlazy all lazy status */ | ||
| 104 | #define prepare_to_copy(tsk) do { } while (0) | ||
| 105 | |||
| 106 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | ||
| 107 | |||
| 108 | /* | ||
| 109 | * Free current thread data structures etc.. | ||
| 110 | */ | ||
| 111 | static inline void exit_thread(void) | ||
| 112 | { | ||
| 113 | } | ||
| 114 | |||
| 115 | extern unsigned long thread_saved_pc(struct task_struct *tsk); | ||
| 116 | |||
| 117 | unsigned long get_wchan(struct task_struct *p); | ||
| 118 | |||
| 119 | #define KSTK_EIP(tsk) \ | ||
| 120 | ({ \ | ||
| 121 | unsigned long eip = 0; \ | ||
| 122 | if ((tsk)->thread.esp0 > PAGE_SIZE && \ | ||
| 123 | (virt_addr_valid((tsk)->thread.esp0))) \ | ||
| 124 | eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ | ||
| 125 | eip; }) | ||
| 126 | #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) | ||
| 127 | |||
| 128 | #define cpu_relax() barrier() | ||
| 129 | |||
| 130 | #endif | ||
diff --git a/arch/m68k/include/asm/processor_no.h b/arch/m68k/include/asm/processor_no.h new file mode 100644 index 000000000000..91cba18acdd3 --- /dev/null +++ b/arch/m68k/include/asm/processor_no.h | |||
| @@ -0,0 +1,143 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68knommu/processor.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1995 Hamish Macdonald | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __ASM_M68K_PROCESSOR_H | ||
| 8 | #define __ASM_M68K_PROCESSOR_H | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Default implementation of macro that returns current | ||
| 12 | * instruction pointer ("program counter"). | ||
| 13 | */ | ||
| 14 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | ||
| 15 | |||
| 16 | #include <linux/compiler.h> | ||
| 17 | #include <linux/threads.h> | ||
| 18 | #include <asm/types.h> | ||
| 19 | #include <asm/segment.h> | ||
| 20 | #include <asm/fpu.h> | ||
| 21 | #include <asm/ptrace.h> | ||
| 22 | #include <asm/current.h> | ||
| 23 | |||
| 24 | static inline unsigned long rdusp(void) | ||
| 25 | { | ||
| 26 | #ifdef CONFIG_COLDFIRE | ||
| 27 | extern unsigned int sw_usp; | ||
| 28 | return(sw_usp); | ||
| 29 | #else | ||
| 30 | unsigned long usp; | ||
| 31 | __asm__ __volatile__("move %/usp,%0" : "=a" (usp)); | ||
| 32 | return usp; | ||
| 33 | #endif | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void wrusp(unsigned long usp) | ||
| 37 | { | ||
| 38 | #ifdef CONFIG_COLDFIRE | ||
| 39 | extern unsigned int sw_usp; | ||
| 40 | sw_usp = usp; | ||
| 41 | #else | ||
| 42 | __asm__ __volatile__("move %0,%/usp" : : "a" (usp)); | ||
| 43 | #endif | ||
| 44 | } | ||
| 45 | |||
| 46 | /* | ||
| 47 | * User space process size: 3.75GB. This is hardcoded into a few places, | ||
| 48 | * so don't change it unless you know what you are doing. | ||
| 49 | */ | ||
| 50 | #define TASK_SIZE (0xF0000000UL) | ||
| 51 | |||
| 52 | /* | ||
| 53 | * This decides where the kernel will search for a free chunk of vm | ||
| 54 | * space during mmap's. We won't be using it | ||
| 55 | */ | ||
| 56 | #define TASK_UNMAPPED_BASE 0 | ||
| 57 | |||
| 58 | /* | ||
| 59 | * if you change this structure, you must change the code and offsets | ||
| 60 | * in m68k/machasm.S | ||
| 61 | */ | ||
| 62 | |||
| 63 | struct thread_struct { | ||
| 64 | unsigned long ksp; /* kernel stack pointer */ | ||
| 65 | unsigned long usp; /* user stack pointer */ | ||
| 66 | unsigned short sr; /* saved status register */ | ||
| 67 | unsigned short fs; /* saved fs (sfc, dfc) */ | ||
| 68 | unsigned long crp[2]; /* cpu root pointer */ | ||
| 69 | unsigned long esp0; /* points to SR of stack frame */ | ||
| 70 | unsigned long fp[8*3]; | ||
| 71 | unsigned long fpcntl[3]; /* fp control regs */ | ||
| 72 | unsigned char fpstate[FPSTATESIZE]; /* floating point state */ | ||
| 73 | }; | ||
| 74 | |||
| 75 | #define INIT_THREAD { \ | ||
| 76 | sizeof(init_stack) + (unsigned long) init_stack, 0, \ | ||
| 77 | PS_S, __KERNEL_DS, \ | ||
| 78 | {0, 0}, 0, {0,}, {0, 0, 0}, {0,}, \ | ||
| 79 | } | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Coldfire stacks need to be re-aligned on trap exit, conventional | ||
| 83 | * 68k can handle this case cleanly. | ||
| 84 | */ | ||
| 85 | #if defined(CONFIG_COLDFIRE) | ||
| 86 | #define reformat(_regs) do { (_regs)->format = 0x4; } while(0) | ||
| 87 | #else | ||
| 88 | #define reformat(_regs) do { } while (0) | ||
| 89 | #endif | ||
| 90 | |||
| 91 | /* | ||
| 92 | * Do necessary setup to start up a newly executed thread. | ||
| 93 | * | ||
| 94 | * pass the data segment into user programs if it exists, | ||
| 95 | * it can't hurt anything as far as I can tell | ||
| 96 | */ | ||
| 97 | #define start_thread(_regs, _pc, _usp) \ | ||
| 98 | do { \ | ||
| 99 | set_fs(USER_DS); /* reads from user space */ \ | ||
| 100 | (_regs)->pc = (_pc); \ | ||
| 101 | ((struct switch_stack *)(_regs))[-1].a6 = 0; \ | ||
| 102 | reformat(_regs); \ | ||
| 103 | if (current->mm) \ | ||
| 104 | (_regs)->d5 = current->mm->start_data; \ | ||
| 105 | (_regs)->sr &= ~0x2000; \ | ||
| 106 | wrusp(_usp); \ | ||
| 107 | } while(0) | ||
| 108 | |||
| 109 | /* Forward declaration, a strange C thing */ | ||
| 110 | struct task_struct; | ||
| 111 | |||
| 112 | /* Free all resources held by a thread. */ | ||
| 113 | static inline void release_thread(struct task_struct *dead_task) | ||
| 114 | { | ||
| 115 | } | ||
| 116 | |||
| 117 | /* Prepare to copy thread state - unlazy all lazy status */ | ||
| 118 | #define prepare_to_copy(tsk) do { } while (0) | ||
| 119 | |||
| 120 | extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); | ||
| 121 | |||
| 122 | /* | ||
| 123 | * Free current thread data structures etc.. | ||
| 124 | */ | ||
| 125 | static inline void exit_thread(void) | ||
| 126 | { | ||
| 127 | } | ||
| 128 | |||
| 129 | unsigned long thread_saved_pc(struct task_struct *tsk); | ||
| 130 | unsigned long get_wchan(struct task_struct *p); | ||
| 131 | |||
| 132 | #define KSTK_EIP(tsk) \ | ||
| 133 | ({ \ | ||
| 134 | unsigned long eip = 0; \ | ||
| 135 | if ((tsk)->thread.esp0 > PAGE_SIZE && \ | ||
| 136 | (virt_addr_valid((tsk)->thread.esp0))) \ | ||
| 137 | eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ | ||
| 138 | eip; }) | ||
| 139 | #define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) | ||
| 140 | |||
| 141 | #define cpu_relax() barrier() | ||
| 142 | |||
| 143 | #endif | ||
diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h new file mode 100644 index 000000000000..e83cd2f66101 --- /dev/null +++ b/arch/m68k/include/asm/ptrace.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "ptrace_no.h" | ||
| 3 | #else | ||
| 4 | #include "ptrace_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/ptrace_mm.h b/arch/m68k/include/asm/ptrace_mm.h new file mode 100644 index 000000000000..57e763d79bf4 --- /dev/null +++ b/arch/m68k/include/asm/ptrace_mm.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | #ifndef _M68K_PTRACE_H | ||
| 2 | #define _M68K_PTRACE_H | ||
| 3 | |||
| 4 | #define PT_D1 0 | ||
| 5 | #define PT_D2 1 | ||
| 6 | #define PT_D3 2 | ||
| 7 | #define PT_D4 3 | ||
| 8 | #define PT_D5 4 | ||
| 9 | #define PT_D6 5 | ||
| 10 | #define PT_D7 6 | ||
| 11 | #define PT_A0 7 | ||
| 12 | #define PT_A1 8 | ||
| 13 | #define PT_A2 9 | ||
| 14 | #define PT_A3 10 | ||
| 15 | #define PT_A4 11 | ||
| 16 | #define PT_A5 12 | ||
| 17 | #define PT_A6 13 | ||
| 18 | #define PT_D0 14 | ||
| 19 | #define PT_USP 15 | ||
| 20 | #define PT_ORIG_D0 16 | ||
| 21 | #define PT_SR 17 | ||
| 22 | #define PT_PC 18 | ||
| 23 | |||
| 24 | #ifndef __ASSEMBLY__ | ||
| 25 | |||
| 26 | /* this struct defines the way the registers are stored on the | ||
| 27 | stack during a system call. */ | ||
| 28 | |||
| 29 | struct pt_regs { | ||
| 30 | long d1; | ||
| 31 | long d2; | ||
| 32 | long d3; | ||
| 33 | long d4; | ||
| 34 | long d5; | ||
| 35 | long a0; | ||
| 36 | long a1; | ||
| 37 | long a2; | ||
| 38 | long d0; | ||
| 39 | long orig_d0; | ||
| 40 | long stkadj; | ||
| 41 | unsigned short sr; | ||
| 42 | unsigned long pc; | ||
| 43 | unsigned format : 4; /* frame format specifier */ | ||
| 44 | unsigned vector : 12; /* vector offset */ | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* | ||
| 48 | * This is the extended stack used by signal handlers and the context | ||
| 49 | * switcher: it's pushed after the normal "struct pt_regs". | ||
| 50 | */ | ||
| 51 | struct switch_stack { | ||
| 52 | unsigned long d6; | ||
| 53 | unsigned long d7; | ||
| 54 | unsigned long a3; | ||
| 55 | unsigned long a4; | ||
| 56 | unsigned long a5; | ||
| 57 | unsigned long a6; | ||
| 58 | unsigned long retpc; | ||
| 59 | }; | ||
| 60 | |||
| 61 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 62 | #define PTRACE_GETREGS 12 | ||
| 63 | #define PTRACE_SETREGS 13 | ||
| 64 | #define PTRACE_GETFPREGS 14 | ||
| 65 | #define PTRACE_SETFPREGS 15 | ||
| 66 | |||
| 67 | #ifdef __KERNEL__ | ||
| 68 | |||
| 69 | #ifndef PS_S | ||
| 70 | #define PS_S (0x2000) | ||
| 71 | #define PS_M (0x1000) | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #define user_mode(regs) (!((regs)->sr & PS_S)) | ||
| 75 | #define instruction_pointer(regs) ((regs)->pc) | ||
| 76 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 77 | extern void show_regs(struct pt_regs *); | ||
| 78 | #endif /* __KERNEL__ */ | ||
| 79 | #endif /* __ASSEMBLY__ */ | ||
| 80 | #endif /* _M68K_PTRACE_H */ | ||
diff --git a/arch/m68k/include/asm/ptrace_no.h b/arch/m68k/include/asm/ptrace_no.h new file mode 100644 index 000000000000..8c9194b98548 --- /dev/null +++ b/arch/m68k/include/asm/ptrace_no.h | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | #ifndef _M68K_PTRACE_H | ||
| 2 | #define _M68K_PTRACE_H | ||
| 3 | |||
| 4 | #define PT_D1 0 | ||
| 5 | #define PT_D2 1 | ||
| 6 | #define PT_D3 2 | ||
| 7 | #define PT_D4 3 | ||
| 8 | #define PT_D5 4 | ||
| 9 | #define PT_D6 5 | ||
| 10 | #define PT_D7 6 | ||
| 11 | #define PT_A0 7 | ||
| 12 | #define PT_A1 8 | ||
| 13 | #define PT_A2 9 | ||
| 14 | #define PT_A3 10 | ||
| 15 | #define PT_A4 11 | ||
| 16 | #define PT_A5 12 | ||
| 17 | #define PT_A6 13 | ||
| 18 | #define PT_D0 14 | ||
| 19 | #define PT_USP 15 | ||
| 20 | #define PT_ORIG_D0 16 | ||
| 21 | #define PT_SR 17 | ||
| 22 | #define PT_PC 18 | ||
| 23 | |||
| 24 | #ifndef __ASSEMBLY__ | ||
| 25 | |||
| 26 | /* this struct defines the way the registers are stored on the | ||
| 27 | stack during a system call. */ | ||
| 28 | |||
| 29 | struct pt_regs { | ||
| 30 | long d1; | ||
| 31 | long d2; | ||
| 32 | long d3; | ||
| 33 | long d4; | ||
| 34 | long d5; | ||
| 35 | long a0; | ||
| 36 | long a1; | ||
| 37 | long a2; | ||
| 38 | long d0; | ||
| 39 | long orig_d0; | ||
| 40 | long stkadj; | ||
| 41 | #ifdef CONFIG_COLDFIRE | ||
| 42 | unsigned format : 4; /* frame format specifier */ | ||
| 43 | unsigned vector : 12; /* vector offset */ | ||
| 44 | unsigned short sr; | ||
| 45 | unsigned long pc; | ||
| 46 | #else | ||
| 47 | unsigned short sr; | ||
| 48 | unsigned long pc; | ||
| 49 | unsigned format : 4; /* frame format specifier */ | ||
| 50 | unsigned vector : 12; /* vector offset */ | ||
| 51 | #endif | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* | ||
| 55 | * This is the extended stack used by signal handlers and the context | ||
| 56 | * switcher: it's pushed after the normal "struct pt_regs". | ||
| 57 | */ | ||
| 58 | struct switch_stack { | ||
| 59 | unsigned long d6; | ||
| 60 | unsigned long d7; | ||
| 61 | unsigned long a3; | ||
| 62 | unsigned long a4; | ||
| 63 | unsigned long a5; | ||
| 64 | unsigned long a6; | ||
| 65 | unsigned long retpc; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 69 | #define PTRACE_GETREGS 12 | ||
| 70 | #define PTRACE_SETREGS 13 | ||
| 71 | #define PTRACE_GETFPREGS 14 | ||
| 72 | #define PTRACE_SETFPREGS 15 | ||
| 73 | |||
| 74 | #ifdef __KERNEL__ | ||
| 75 | |||
| 76 | #ifndef PS_S | ||
| 77 | #define PS_S (0x2000) | ||
| 78 | #define PS_M (0x1000) | ||
| 79 | #endif | ||
| 80 | |||
| 81 | #define user_mode(regs) (!((regs)->sr & PS_S)) | ||
| 82 | #define instruction_pointer(regs) ((regs)->pc) | ||
| 83 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 84 | extern void show_regs(struct pt_regs *); | ||
| 85 | #endif /* __KERNEL__ */ | ||
| 86 | #endif /* __ASSEMBLY__ */ | ||
| 87 | #endif /* _M68K_PTRACE_H */ | ||
diff --git a/arch/m68k/include/asm/q40_master.h b/arch/m68k/include/asm/q40_master.h new file mode 100644 index 000000000000..3907a09d4fca --- /dev/null +++ b/arch/m68k/include/asm/q40_master.h | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * Q40 master Chip Control | ||
| 3 | * RTC stuff merged for compactnes.. | ||
| 4 | */ | ||
| 5 | |||
| 6 | #ifndef _Q40_MASTER_H | ||
| 7 | #define _Q40_MASTER_H | ||
| 8 | |||
| 9 | #include <asm/raw_io.h> | ||
| 10 | |||
| 11 | |||
| 12 | #define q40_master_addr 0xff000000 | ||
| 13 | |||
| 14 | #define IIRQ_REG 0x0 /* internal IRQ reg */ | ||
| 15 | #define EIRQ_REG 0x4 /* external ... */ | ||
| 16 | #define KEYCODE_REG 0x1c /* value of received scancode */ | ||
| 17 | #define DISPLAY_CONTROL_REG 0x18 | ||
| 18 | #define FRAME_CLEAR_REG 0x24 | ||
| 19 | #define LED_REG 0x30 | ||
| 20 | |||
| 21 | #define Q40_LED_ON() master_outb(1,LED_REG) | ||
| 22 | #define Q40_LED_OFF() master_outb(0,LED_REG) | ||
| 23 | |||
| 24 | #define INTERRUPT_REG IIRQ_REG /* "native" ints */ | ||
| 25 | #define KEY_IRQ_ENABLE_REG 0x08 /**/ | ||
| 26 | #define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */ | ||
| 27 | |||
| 28 | #define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */ | ||
| 29 | #define SAMPLE_RATE_REG 0x2c | ||
| 30 | #define SAMPLE_CLEAR_REG 0x28 | ||
| 31 | #define SAMPLE_LOW 0x00 | ||
| 32 | #define SAMPLE_HIGH 0x01 | ||
| 33 | |||
| 34 | #define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */ | ||
| 35 | |||
| 36 | #if 0 | ||
| 37 | #define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */ | ||
| 38 | #endif | ||
| 39 | #define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */ | ||
| 40 | |||
| 41 | |||
| 42 | #define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_) | ||
| 43 | #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_) | ||
| 44 | |||
| 45 | /* RTC defines */ | ||
| 46 | |||
| 47 | #define Q40_RTC_BASE (0xff021ffc) | ||
| 48 | |||
| 49 | #define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0)) | ||
| 50 | #define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4)) | ||
| 51 | #define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8)) | ||
| 52 | #define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12)) | ||
| 53 | #define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16)) | ||
| 54 | #define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20)) | ||
| 55 | #define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24)) | ||
| 56 | #define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28)) | ||
| 57 | |||
| 58 | /* some control bits */ | ||
| 59 | #define Q40_RTC_READ 64 /* prepare for reading */ | ||
| 60 | #define Q40_RTC_WRITE 128 | ||
| 61 | |||
| 62 | /* define some Q40 specific ints */ | ||
| 63 | #include "q40ints.h" | ||
| 64 | |||
| 65 | /* misc defs */ | ||
| 66 | #define DAC_LEFT ((unsigned char *)0xff008000) | ||
| 67 | #define DAC_RIGHT ((unsigned char *)0xff008004) | ||
| 68 | |||
| 69 | #endif /* _Q40_MASTER_H */ | ||
diff --git a/arch/m68k/include/asm/q40ints.h b/arch/m68k/include/asm/q40ints.h new file mode 100644 index 000000000000..3d970afb708f --- /dev/null +++ b/arch/m68k/include/asm/q40ints.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * contains some Q40 related interrupt definitions | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define Q40_IRQ_MAX (34) | ||
| 6 | |||
| 7 | #define Q40_IRQ_SAMPLE (34) | ||
| 8 | #define Q40_IRQ_KEYBOARD (32) | ||
| 9 | #define Q40_IRQ_FRAME (33) | ||
| 10 | |||
| 11 | |||
| 12 | /* masks for interrupt regiosters*/ | ||
| 13 | /* internal, IIRQ_REG */ | ||
| 14 | #define Q40_IRQ_KEYB_MASK (2) | ||
| 15 | #define Q40_IRQ_SER_MASK (1<<2) | ||
| 16 | #define Q40_IRQ_FRAME_MASK (1<<3) | ||
| 17 | #define Q40_IRQ_EXT_MASK (1<<4) /* is a EIRQ */ | ||
| 18 | /* eirq, EIRQ_REG */ | ||
| 19 | #define Q40_IRQ3_MASK (1) | ||
| 20 | #define Q40_IRQ4_MASK (1<<1) | ||
| 21 | #define Q40_IRQ5_MASK (1<<2) | ||
| 22 | #define Q40_IRQ6_MASK (1<<3) | ||
| 23 | #define Q40_IRQ7_MASK (1<<4) | ||
| 24 | #define Q40_IRQ10_MASK (1<<5) | ||
| 25 | #define Q40_IRQ14_MASK (1<<6) | ||
| 26 | #define Q40_IRQ15_MASK (1<<7) | ||
| 27 | |||
| 28 | extern unsigned long q40_probe_irq_on (void); | ||
| 29 | extern int q40_probe_irq_off (unsigned long irqs); | ||
diff --git a/arch/m68k/include/asm/quicc_simple.h b/arch/m68k/include/asm/quicc_simple.h new file mode 100644 index 000000000000..c3636932d4bc --- /dev/null +++ b/arch/m68k/include/asm/quicc_simple.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /*********************************** | ||
| 2 | * $Id: quicc_simple.h,v 1.1 2002/03/02 15:01:10 gerg Exp $ | ||
| 3 | *********************************** | ||
| 4 | * | ||
| 5 | *************************************** | ||
| 6 | * Simple drivers common header | ||
| 7 | *************************************** | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __SIMPLE_H | ||
| 11 | #define __SIMPLE_H | ||
| 12 | |||
| 13 | /* #include "quicc.h" */ | ||
| 14 | |||
| 15 | #define GLB_SCC_0 0 | ||
| 16 | #define GLB_SCC_1 1 | ||
| 17 | #define GLB_SCC_2 2 | ||
| 18 | #define GLB_SCC_3 3 | ||
| 19 | |||
| 20 | typedef void (int_routine)(unsigned short interrupt_event); | ||
| 21 | typedef int_routine *int_routine_ptr; | ||
| 22 | typedef void *(alloc_routine)(int length); | ||
| 23 | typedef void (free_routine)(int scc_num, int channel_num, void *buf); | ||
| 24 | typedef void (store_rx_buffer_routine)(int scc_num, int channel_num, void *buff, int length); | ||
| 25 | typedef int (handle_tx_error_routine)(int scc_num, int channel_num, QUICC_BD *tbd); | ||
| 26 | typedef void (handle_rx_error_routine)(int scc_num, int channel_num, QUICC_BD *rbd); | ||
| 27 | typedef void (handle_lost_error_routine)(int scc_num, int channel_num); | ||
| 28 | |||
| 29 | /* user defined functions for global errors */ | ||
| 30 | typedef void (handle_glob_overrun_routine)(int scc_number); | ||
| 31 | typedef void (handle_glob_underrun_routine)(int scc_number); | ||
| 32 | typedef void (glob_intr_q_overflow_routine)(int scc_number); | ||
| 33 | |||
| 34 | /* | ||
| 35 | * General initialization and command routines | ||
| 36 | */ | ||
| 37 | void quicc_issue_cmd (unsigned short cmd, int scc_num); | ||
| 38 | void quicc_init(void); | ||
| 39 | void quicc_scc_init(int scc_number, int number_of_rx_buf, int number_of_tx_buf); | ||
| 40 | void quicc_smc_init(int smc_number, int number_of_rx_buf, int number_of_tx_buf); | ||
| 41 | void quicc_scc_start(int scc_num); | ||
| 42 | void quicc_scc_loopback(int scc_num); | ||
| 43 | |||
| 44 | /* Interrupt enable/disable routines for critical pieces of code*/ | ||
| 45 | unsigned short IntrDis(void); | ||
| 46 | void IntrEna(unsigned short old_sr); | ||
| 47 | |||
| 48 | /* For debugging */ | ||
| 49 | void print_rbd(int scc_num); | ||
| 50 | void print_tbd(int scc_num); | ||
| 51 | |||
| 52 | #endif | ||
diff --git a/arch/m68k/include/asm/raw_io.h b/arch/m68k/include/asm/raw_io.h new file mode 100644 index 000000000000..d9eb9834ccc8 --- /dev/null +++ b/arch/m68k/include/asm/raw_io.h | |||
| @@ -0,0 +1,347 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-m68k/raw_io.h | ||
| 3 | * | ||
| 4 | * 10/20/00 RZ: - created from bits of io.h and ide.h to cleanup namespace | ||
| 5 | * | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _RAW_IO_H | ||
| 9 | #define _RAW_IO_H | ||
| 10 | |||
| 11 | #ifdef __KERNEL__ | ||
| 12 | |||
| 13 | #include <asm/types.h> | ||
| 14 | |||
| 15 | |||
| 16 | /* Values for nocacheflag and cmode */ | ||
| 17 | #define IOMAP_FULL_CACHING 0 | ||
| 18 | #define IOMAP_NOCACHE_SER 1 | ||
| 19 | #define IOMAP_NOCACHE_NONSER 2 | ||
| 20 | #define IOMAP_WRITETHROUGH 3 | ||
| 21 | |||
| 22 | extern void iounmap(void __iomem *addr); | ||
| 23 | |||
| 24 | extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size, | ||
| 25 | int cacheflag); | ||
| 26 | extern void __iounmap(void *addr, unsigned long size); | ||
| 27 | |||
| 28 | |||
| 29 | /* ++roman: The assignments to temp. vars avoid that gcc sometimes generates | ||
| 30 | * two accesses to memory, which may be undesirable for some devices. | ||
| 31 | */ | ||
| 32 | #define in_8(addr) \ | ||
| 33 | ({ u8 __v = (*(__force volatile u8 *) (addr)); __v; }) | ||
| 34 | #define in_be16(addr) \ | ||
| 35 | ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; }) | ||
| 36 | #define in_be32(addr) \ | ||
| 37 | ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; }) | ||
| 38 | #define in_le16(addr) \ | ||
| 39 | ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; }) | ||
| 40 | #define in_le32(addr) \ | ||
| 41 | ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; }) | ||
| 42 | |||
| 43 | #define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b)) | ||
| 44 | #define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w)) | ||
| 45 | #define out_be32(addr,l) (void)((*(__force volatile u32 *) (addr)) = (l)) | ||
| 46 | #define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w)) | ||
| 47 | #define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l)) | ||
| 48 | |||
| 49 | #define raw_inb in_8 | ||
| 50 | #define raw_inw in_be16 | ||
| 51 | #define raw_inl in_be32 | ||
| 52 | #define __raw_readb in_8 | ||
| 53 | #define __raw_readw in_be16 | ||
| 54 | #define __raw_readl in_be32 | ||
| 55 | |||
| 56 | #define raw_outb(val,port) out_8((port),(val)) | ||
| 57 | #define raw_outw(val,port) out_be16((port),(val)) | ||
| 58 | #define raw_outl(val,port) out_be32((port),(val)) | ||
| 59 | #define __raw_writeb(val,addr) out_8((addr),(val)) | ||
| 60 | #define __raw_writew(val,addr) out_be16((addr),(val)) | ||
| 61 | #define __raw_writel(val,addr) out_be32((addr),(val)) | ||
| 62 | |||
| 63 | static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len) | ||
| 64 | { | ||
| 65 | unsigned int i; | ||
| 66 | |||
| 67 | for (i = 0; i < len; i++) | ||
| 68 | *buf++ = in_8(port); | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline void raw_outsb(volatile u8 __iomem *port, const u8 *buf, | ||
| 72 | unsigned int len) | ||
| 73 | { | ||
| 74 | unsigned int i; | ||
| 75 | |||
| 76 | for (i = 0; i < len; i++) | ||
| 77 | out_8(port, *buf++); | ||
| 78 | } | ||
| 79 | |||
| 80 | static inline void raw_insw(volatile u16 __iomem *port, u16 *buf, unsigned int nr) | ||
| 81 | { | ||
| 82 | unsigned int tmp; | ||
| 83 | |||
| 84 | if (nr & 15) { | ||
| 85 | tmp = (nr & 15) - 1; | ||
| 86 | asm volatile ( | ||
| 87 | "1: movew %2@,%0@+; dbra %1,1b" | ||
| 88 | : "=a" (buf), "=d" (tmp) | ||
| 89 | : "a" (port), "0" (buf), | ||
| 90 | "1" (tmp)); | ||
| 91 | } | ||
| 92 | if (nr >> 4) { | ||
| 93 | tmp = (nr >> 4) - 1; | ||
| 94 | asm volatile ( | ||
| 95 | "1: " | ||
| 96 | "movew %2@,%0@+; " | ||
| 97 | "movew %2@,%0@+; " | ||
| 98 | "movew %2@,%0@+; " | ||
| 99 | "movew %2@,%0@+; " | ||
| 100 | "movew %2@,%0@+; " | ||
| 101 | "movew %2@,%0@+; " | ||
| 102 | "movew %2@,%0@+; " | ||
| 103 | "movew %2@,%0@+; " | ||
| 104 | "movew %2@,%0@+; " | ||
| 105 | "movew %2@,%0@+; " | ||
| 106 | "movew %2@,%0@+; " | ||
| 107 | "movew %2@,%0@+; " | ||
| 108 | "movew %2@,%0@+; " | ||
| 109 | "movew %2@,%0@+; " | ||
| 110 | "movew %2@,%0@+; " | ||
| 111 | "movew %2@,%0@+; " | ||
| 112 | "dbra %1,1b" | ||
| 113 | : "=a" (buf), "=d" (tmp) | ||
| 114 | : "a" (port), "0" (buf), | ||
| 115 | "1" (tmp)); | ||
| 116 | } | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline void raw_outsw(volatile u16 __iomem *port, const u16 *buf, | ||
| 120 | unsigned int nr) | ||
| 121 | { | ||
| 122 | unsigned int tmp; | ||
| 123 | |||
| 124 | if (nr & 15) { | ||
| 125 | tmp = (nr & 15) - 1; | ||
| 126 | asm volatile ( | ||
| 127 | "1: movew %0@+,%2@; dbra %1,1b" | ||
| 128 | : "=a" (buf), "=d" (tmp) | ||
| 129 | : "a" (port), "0" (buf), | ||
| 130 | "1" (tmp)); | ||
| 131 | } | ||
| 132 | if (nr >> 4) { | ||
| 133 | tmp = (nr >> 4) - 1; | ||
| 134 | asm volatile ( | ||
| 135 | "1: " | ||
| 136 | "movew %0@+,%2@; " | ||
| 137 | "movew %0@+,%2@; " | ||
| 138 | "movew %0@+,%2@; " | ||
| 139 | "movew %0@+,%2@; " | ||
| 140 | "movew %0@+,%2@; " | ||
| 141 | "movew %0@+,%2@; " | ||
| 142 | "movew %0@+,%2@; " | ||
| 143 | "movew %0@+,%2@; " | ||
| 144 | "movew %0@+,%2@; " | ||
| 145 | "movew %0@+,%2@; " | ||
| 146 | "movew %0@+,%2@; " | ||
| 147 | "movew %0@+,%2@; " | ||
| 148 | "movew %0@+,%2@; " | ||
| 149 | "movew %0@+,%2@; " | ||
| 150 | "movew %0@+,%2@; " | ||
| 151 | "movew %0@+,%2@; " | ||
| 152 | "dbra %1,1b" | ||
| 153 | : "=a" (buf), "=d" (tmp) | ||
| 154 | : "a" (port), "0" (buf), | ||
| 155 | "1" (tmp)); | ||
| 156 | } | ||
| 157 | } | ||
| 158 | |||
| 159 | static inline void raw_insl(volatile u32 __iomem *port, u32 *buf, unsigned int nr) | ||
| 160 | { | ||
| 161 | unsigned int tmp; | ||
| 162 | |||
| 163 | if (nr & 15) { | ||
| 164 | tmp = (nr & 15) - 1; | ||
| 165 | asm volatile ( | ||
| 166 | "1: movel %2@,%0@+; dbra %1,1b" | ||
| 167 | : "=a" (buf), "=d" (tmp) | ||
| 168 | : "a" (port), "0" (buf), | ||
| 169 | "1" (tmp)); | ||
| 170 | } | ||
| 171 | if (nr >> 4) { | ||
| 172 | tmp = (nr >> 4) - 1; | ||
| 173 | asm volatile ( | ||
| 174 | "1: " | ||
| 175 | "movel %2@,%0@+; " | ||
| 176 | "movel %2@,%0@+; " | ||
| 177 | "movel %2@,%0@+; " | ||
| 178 | "movel %2@,%0@+; " | ||
| 179 | "movel %2@,%0@+; " | ||
| 180 | "movel %2@,%0@+; " | ||
| 181 | "movel %2@,%0@+; " | ||
| 182 | "movel %2@,%0@+; " | ||
| 183 | "movel %2@,%0@+; " | ||
| 184 | "movel %2@,%0@+; " | ||
| 185 | "movel %2@,%0@+; " | ||
| 186 | "movel %2@,%0@+; " | ||
| 187 | "movel %2@,%0@+; " | ||
| 188 | "movel %2@,%0@+; " | ||
| 189 | "movel %2@,%0@+; " | ||
| 190 | "movel %2@,%0@+; " | ||
| 191 | "dbra %1,1b" | ||
| 192 | : "=a" (buf), "=d" (tmp) | ||
| 193 | : "a" (port), "0" (buf), | ||
| 194 | "1" (tmp)); | ||
| 195 | } | ||
| 196 | } | ||
| 197 | |||
| 198 | static inline void raw_outsl(volatile u32 __iomem *port, const u32 *buf, | ||
| 199 | unsigned int nr) | ||
| 200 | { | ||
| 201 | unsigned int tmp; | ||
| 202 | |||
| 203 | if (nr & 15) { | ||
| 204 | tmp = (nr & 15) - 1; | ||
| 205 | asm volatile ( | ||
| 206 | "1: movel %0@+,%2@; dbra %1,1b" | ||
| 207 | : "=a" (buf), "=d" (tmp) | ||
| 208 | : "a" (port), "0" (buf), | ||
| 209 | "1" (tmp)); | ||
| 210 | } | ||
| 211 | if (nr >> 4) { | ||
| 212 | tmp = (nr >> 4) - 1; | ||
| 213 | asm volatile ( | ||
| 214 | "1: " | ||
| 215 | "movel %0@+,%2@; " | ||
| 216 | "movel %0@+,%2@; " | ||
| 217 | "movel %0@+,%2@; " | ||
| 218 | "movel %0@+,%2@; " | ||
| 219 | "movel %0@+,%2@; " | ||
| 220 | "movel %0@+,%2@; " | ||
| 221 | "movel %0@+,%2@; " | ||
| 222 | "movel %0@+,%2@; " | ||
| 223 | "movel %0@+,%2@; " | ||
| 224 | "movel %0@+,%2@; " | ||
| 225 | "movel %0@+,%2@; " | ||
| 226 | "movel %0@+,%2@; " | ||
| 227 | "movel %0@+,%2@; " | ||
| 228 | "movel %0@+,%2@; " | ||
| 229 | "movel %0@+,%2@; " | ||
| 230 | "movel %0@+,%2@; " | ||
| 231 | "dbra %1,1b" | ||
| 232 | : "=a" (buf), "=d" (tmp) | ||
| 233 | : "a" (port), "0" (buf), | ||
| 234 | "1" (tmp)); | ||
| 235 | } | ||
| 236 | } | ||
| 237 | |||
| 238 | |||
| 239 | static inline void raw_insw_swapw(volatile u16 __iomem *port, u16 *buf, | ||
| 240 | unsigned int nr) | ||
| 241 | { | ||
| 242 | if ((nr) % 8) | ||
| 243 | __asm__ __volatile__ | ||
| 244 | ("\tmovel %0,%/a0\n\t" | ||
| 245 | "movel %1,%/a1\n\t" | ||
| 246 | "movel %2,%/d6\n\t" | ||
| 247 | "subql #1,%/d6\n" | ||
| 248 | "1:\tmovew %/a0@,%/d0\n\t" | ||
| 249 | "rolw #8,%/d0\n\t" | ||
| 250 | "movew %/d0,%/a1@+\n\t" | ||
| 251 | "dbra %/d6,1b" | ||
| 252 | : | ||
| 253 | : "g" (port), "g" (buf), "g" (nr) | ||
| 254 | : "d0", "a0", "a1", "d6"); | ||
| 255 | else | ||
| 256 | __asm__ __volatile__ | ||
| 257 | ("movel %0,%/a0\n\t" | ||
| 258 | "movel %1,%/a1\n\t" | ||
| 259 | "movel %2,%/d6\n\t" | ||
| 260 | "lsrl #3,%/d6\n\t" | ||
| 261 | "subql #1,%/d6\n" | ||
| 262 | "1:\tmovew %/a0@,%/d0\n\t" | ||
| 263 | "rolw #8,%/d0\n\t" | ||
| 264 | "movew %/d0,%/a1@+\n\t" | ||
| 265 | "movew %/a0@,%/d0\n\t" | ||
| 266 | "rolw #8,%/d0\n\t" | ||
| 267 | "movew %/d0,%/a1@+\n\t" | ||
| 268 | "movew %/a0@,%/d0\n\t" | ||
| 269 | "rolw #8,%/d0\n\t" | ||
| 270 | "movew %/d0,%/a1@+\n\t" | ||
| 271 | "movew %/a0@,%/d0\n\t" | ||
| 272 | "rolw #8,%/d0\n\t" | ||
| 273 | "movew %/d0,%/a1@+\n\t" | ||
| 274 | "movew %/a0@,%/d0\n\t" | ||
| 275 | "rolw #8,%/d0\n\t" | ||
| 276 | "movew %/d0,%/a1@+\n\t" | ||
| 277 | "movew %/a0@,%/d0\n\t" | ||
| 278 | "rolw #8,%/d0\n\t" | ||
| 279 | "movew %/d0,%/a1@+\n\t" | ||
| 280 | "movew %/a0@,%/d0\n\t" | ||
| 281 | "rolw #8,%/d0\n\t" | ||
| 282 | "movew %/d0,%/a1@+\n\t" | ||
| 283 | "movew %/a0@,%/d0\n\t" | ||
| 284 | "rolw #8,%/d0\n\t" | ||
| 285 | "movew %/d0,%/a1@+\n\t" | ||
| 286 | "dbra %/d6,1b" | ||
| 287 | : | ||
| 288 | : "g" (port), "g" (buf), "g" (nr) | ||
| 289 | : "d0", "a0", "a1", "d6"); | ||
| 290 | } | ||
| 291 | |||
| 292 | static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf, | ||
| 293 | unsigned int nr) | ||
| 294 | { | ||
| 295 | if ((nr) % 8) | ||
| 296 | __asm__ __volatile__ | ||
| 297 | ("movel %0,%/a0\n\t" | ||
| 298 | "movel %1,%/a1\n\t" | ||
| 299 | "movel %2,%/d6\n\t" | ||
| 300 | "subql #1,%/d6\n" | ||
| 301 | "1:\tmovew %/a1@+,%/d0\n\t" | ||
| 302 | "rolw #8,%/d0\n\t" | ||
| 303 | "movew %/d0,%/a0@\n\t" | ||
| 304 | "dbra %/d6,1b" | ||
| 305 | : | ||
| 306 | : "g" (port), "g" (buf), "g" (nr) | ||
| 307 | : "d0", "a0", "a1", "d6"); | ||
| 308 | else | ||
| 309 | __asm__ __volatile__ | ||
| 310 | ("movel %0,%/a0\n\t" | ||
| 311 | "movel %1,%/a1\n\t" | ||
| 312 | "movel %2,%/d6\n\t" | ||
| 313 | "lsrl #3,%/d6\n\t" | ||
| 314 | "subql #1,%/d6\n" | ||
| 315 | "1:\tmovew %/a1@+,%/d0\n\t" | ||
| 316 | "rolw #8,%/d0\n\t" | ||
| 317 | "movew %/d0,%/a0@\n\t" | ||
| 318 | "movew %/a1@+,%/d0\n\t" | ||
| 319 | "rolw #8,%/d0\n\t" | ||
| 320 | "movew %/d0,%/a0@\n\t" | ||
| 321 | "movew %/a1@+,%/d0\n\t" | ||
| 322 | "rolw #8,%/d0\n\t" | ||
| 323 | "movew %/d0,%/a0@\n\t" | ||
| 324 | "movew %/a1@+,%/d0\n\t" | ||
| 325 | "rolw #8,%/d0\n\t" | ||
| 326 | "movew %/d0,%/a0@\n\t" | ||
| 327 | "movew %/a1@+,%/d0\n\t" | ||
| 328 | "rolw #8,%/d0\n\t" | ||
| 329 | "movew %/d0,%/a0@\n\t" | ||
| 330 | "movew %/a1@+,%/d0\n\t" | ||
| 331 | "rolw #8,%/d0\n\t" | ||
| 332 | "movew %/d0,%/a0@\n\t" | ||
| 333 | "movew %/a1@+,%/d0\n\t" | ||
| 334 | "rolw #8,%/d0\n\t" | ||
| 335 | "movew %/d0,%/a0@\n\t" | ||
| 336 | "movew %/a1@+,%/d0\n\t" | ||
| 337 | "rolw #8,%/d0\n\t" | ||
| 338 | "movew %/d0,%/a0@\n\t" | ||
| 339 | "dbra %/d6,1b" | ||
| 340 | : | ||
| 341 | : "g" (port), "g" (buf), "g" (nr) | ||
| 342 | : "d0", "a0", "a1", "d6"); | ||
| 343 | } | ||
| 344 | |||
| 345 | #endif /* __KERNEL__ */ | ||
| 346 | |||
| 347 | #endif /* _RAW_IO_H */ | ||
diff --git a/arch/m68k/include/asm/resource.h b/arch/m68k/include/asm/resource.h new file mode 100644 index 000000000000..e7d35019f337 --- /dev/null +++ b/arch/m68k/include/asm/resource.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68K_RESOURCE_H | ||
| 2 | #define _M68K_RESOURCE_H | ||
| 3 | |||
| 4 | #include <asm-generic/resource.h> | ||
| 5 | |||
| 6 | #endif /* _M68K_RESOURCE_H */ | ||
diff --git a/arch/m68k/include/asm/rtc.h b/arch/m68k/include/asm/rtc.h new file mode 100644 index 000000000000..5d3e03859844 --- /dev/null +++ b/arch/m68k/include/asm/rtc.h | |||
| @@ -0,0 +1,76 @@ | |||
| 1 | /* include/asm-m68k/rtc.h | ||
| 2 | * | ||
| 3 | * Copyright Richard Zidlicky | ||
| 4 | * implementation details for genrtc/q40rtc driver | ||
| 5 | */ | ||
| 6 | /* permission is hereby granted to copy, modify and redistribute this code | ||
| 7 | * in terms of the GNU Library General Public License, Version 2 or later, | ||
| 8 | * at your option. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef _ASM_RTC_H | ||
| 12 | #define _ASM_RTC_H | ||
| 13 | |||
| 14 | #ifdef __KERNEL__ | ||
| 15 | |||
| 16 | #include <linux/rtc.h> | ||
| 17 | #include <asm/errno.h> | ||
| 18 | #include <asm/machdep.h> | ||
| 19 | |||
| 20 | #define RTC_PIE 0x40 /* periodic interrupt enable */ | ||
| 21 | #define RTC_AIE 0x20 /* alarm interrupt enable */ | ||
| 22 | #define RTC_UIE 0x10 /* update-finished interrupt enable */ | ||
| 23 | |||
| 24 | /* some dummy definitions */ | ||
| 25 | #define RTC_BATT_BAD 0x100 /* battery bad */ | ||
| 26 | #define RTC_SQWE 0x08 /* enable square-wave output */ | ||
| 27 | #define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ | ||
| 28 | #define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ | ||
| 29 | #define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ | ||
| 30 | |||
| 31 | static inline unsigned int get_rtc_time(struct rtc_time *time) | ||
| 32 | { | ||
| 33 | /* | ||
| 34 | * Only the values that we read from the RTC are set. We leave | ||
| 35 | * tm_wday, tm_yday and tm_isdst untouched. Even though the | ||
| 36 | * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated | ||
| 37 | * by the RTC when initially set to a non-zero value. | ||
| 38 | */ | ||
| 39 | mach_hwclk(0, time); | ||
| 40 | return RTC_24H; | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline int set_rtc_time(struct rtc_time *time) | ||
| 44 | { | ||
| 45 | return mach_hwclk(1, time); | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline unsigned int get_rtc_ss(void) | ||
| 49 | { | ||
| 50 | if (mach_get_ss) | ||
| 51 | return mach_get_ss(); | ||
| 52 | else{ | ||
| 53 | struct rtc_time h; | ||
| 54 | |||
| 55 | get_rtc_time(&h); | ||
| 56 | return h.tm_sec; | ||
| 57 | } | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline int get_rtc_pll(struct rtc_pll_info *pll) | ||
| 61 | { | ||
| 62 | if (mach_get_rtc_pll) | ||
| 63 | return mach_get_rtc_pll(pll); | ||
| 64 | else | ||
| 65 | return -EINVAL; | ||
| 66 | } | ||
| 67 | static inline int set_rtc_pll(struct rtc_pll_info *pll) | ||
| 68 | { | ||
| 69 | if (mach_set_rtc_pll) | ||
| 70 | return mach_set_rtc_pll(pll); | ||
| 71 | else | ||
| 72 | return -EINVAL; | ||
| 73 | } | ||
| 74 | #endif /* __KERNEL__ */ | ||
| 75 | |||
| 76 | #endif /* _ASM__RTC_H */ | ||
diff --git a/arch/m68k/include/asm/sbus.h b/arch/m68k/include/asm/sbus.h new file mode 100644 index 000000000000..bfe3ba147f2e --- /dev/null +++ b/arch/m68k/include/asm/sbus.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * some sbus structures and macros to make usage of sbus drivers possible | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __M68K_SBUS_H | ||
| 6 | #define __M68K_SBUS_H | ||
| 7 | |||
| 8 | struct sbus_dev { | ||
| 9 | struct { | ||
| 10 | unsigned int which_io; | ||
| 11 | unsigned int phys_addr; | ||
| 12 | } reg_addrs[1]; | ||
| 13 | }; | ||
| 14 | |||
| 15 | /* sbus IO functions stolen from include/asm-sparc/io.h for the serial driver */ | ||
| 16 | /* No SBUS on the Sun3, kludge -- sam */ | ||
| 17 | |||
| 18 | static inline void _sbus_writeb(unsigned char val, unsigned long addr) | ||
| 19 | { | ||
| 20 | *(volatile unsigned char *)addr = val; | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline unsigned char _sbus_readb(unsigned long addr) | ||
| 24 | { | ||
| 25 | return *(volatile unsigned char *)addr; | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline void _sbus_writel(unsigned long val, unsigned long addr) | ||
| 29 | { | ||
| 30 | *(volatile unsigned long *)addr = val; | ||
| 31 | |||
| 32 | } | ||
| 33 | |||
| 34 | extern inline unsigned long _sbus_readl(unsigned long addr) | ||
| 35 | { | ||
| 36 | return *(volatile unsigned long *)addr; | ||
| 37 | } | ||
| 38 | |||
| 39 | |||
| 40 | #define sbus_readb(a) _sbus_readb((unsigned long)a) | ||
| 41 | #define sbus_writeb(v, a) _sbus_writeb(v, (unsigned long)a) | ||
| 42 | #define sbus_readl(a) _sbus_readl((unsigned long)a) | ||
| 43 | #define sbus_writel(v, a) _sbus_writel(v, (unsigned long)a) | ||
| 44 | |||
| 45 | #endif | ||
diff --git a/arch/m68k/include/asm/scatterlist.h b/arch/m68k/include/asm/scatterlist.h new file mode 100644 index 000000000000..b7e528636252 --- /dev/null +++ b/arch/m68k/include/asm/scatterlist.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "scatterlist_no.h" | ||
| 3 | #else | ||
| 4 | #include "scatterlist_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/scatterlist_mm.h b/arch/m68k/include/asm/scatterlist_mm.h new file mode 100644 index 000000000000..d3a7a0edfeca --- /dev/null +++ b/arch/m68k/include/asm/scatterlist_mm.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef _M68K_SCATTERLIST_H | ||
| 2 | #define _M68K_SCATTERLIST_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | struct scatterlist { | ||
| 7 | #ifdef CONFIG_DEBUG_SG | ||
| 8 | unsigned long sg_magic; | ||
| 9 | #endif | ||
| 10 | unsigned long page_link; | ||
| 11 | unsigned int offset; | ||
| 12 | unsigned int length; | ||
| 13 | |||
| 14 | __u32 dma_address; /* A place to hang host-specific addresses at. */ | ||
| 15 | }; | ||
| 16 | |||
| 17 | /* This is bogus and should go away. */ | ||
| 18 | #define ISA_DMA_THRESHOLD (0x00ffffff) | ||
| 19 | |||
| 20 | #define sg_dma_address(sg) ((sg)->dma_address) | ||
| 21 | #define sg_dma_len(sg) ((sg)->length) | ||
| 22 | |||
| 23 | #endif /* !(_M68K_SCATTERLIST_H) */ | ||
diff --git a/arch/m68k/include/asm/scatterlist_no.h b/arch/m68k/include/asm/scatterlist_no.h new file mode 100644 index 000000000000..afc4788b0d2c --- /dev/null +++ b/arch/m68k/include/asm/scatterlist_no.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | #ifndef _M68KNOMMU_SCATTERLIST_H | ||
| 2 | #define _M68KNOMMU_SCATTERLIST_H | ||
| 3 | |||
| 4 | #include <linux/mm.h> | ||
| 5 | #include <asm/types.h> | ||
| 6 | |||
| 7 | struct scatterlist { | ||
| 8 | #ifdef CONFIG_DEBUG_SG | ||
| 9 | unsigned long sg_magic; | ||
| 10 | #endif | ||
| 11 | unsigned long page_link; | ||
| 12 | unsigned int offset; | ||
| 13 | dma_addr_t dma_address; | ||
| 14 | unsigned int length; | ||
| 15 | }; | ||
| 16 | |||
| 17 | #define sg_dma_address(sg) ((sg)->dma_address) | ||
| 18 | #define sg_dma_len(sg) ((sg)->length) | ||
| 19 | |||
| 20 | #define ISA_DMA_THRESHOLD (0xffffffff) | ||
| 21 | |||
| 22 | #endif /* !(_M68KNOMMU_SCATTERLIST_H) */ | ||
diff --git a/arch/m68k/include/asm/sections.h b/arch/m68k/include/asm/sections.h new file mode 100644 index 000000000000..d64967ecfec6 --- /dev/null +++ b/arch/m68k/include/asm/sections.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_M68K_SECTIONS_H | ||
| 2 | #define _ASM_M68K_SECTIONS_H | ||
| 3 | |||
| 4 | #include <asm-generic/sections.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_M68K_SECTIONS_H */ | ||
diff --git a/arch/m68k/include/asm/segment.h b/arch/m68k/include/asm/segment.h new file mode 100644 index 000000000000..82583bc004bd --- /dev/null +++ b/arch/m68k/include/asm/segment.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "segment_no.h" | ||
| 3 | #else | ||
| 4 | #include "segment_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/segment_mm.h b/arch/m68k/include/asm/segment_mm.h new file mode 100644 index 000000000000..7b0b2d3127f9 --- /dev/null +++ b/arch/m68k/include/asm/segment_mm.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | #ifndef _M68K_SEGMENT_H | ||
| 2 | #define _M68K_SEGMENT_H | ||
| 3 | |||
| 4 | /* define constants */ | ||
| 5 | /* Address spaces (FC0-FC2) */ | ||
| 6 | #define USER_DATA (1) | ||
| 7 | #ifndef __USER_DS | ||
| 8 | #define __USER_DS (USER_DATA) | ||
| 9 | #endif | ||
| 10 | #define USER_PROGRAM (2) | ||
| 11 | #define SUPER_DATA (5) | ||
| 12 | #ifndef __KERNEL_DS | ||
| 13 | #define __KERNEL_DS (SUPER_DATA) | ||
| 14 | #endif | ||
| 15 | #define SUPER_PROGRAM (6) | ||
| 16 | #define CPU_SPACE (7) | ||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | |||
| 20 | typedef struct { | ||
| 21 | unsigned long seg; | ||
| 22 | } mm_segment_t; | ||
| 23 | |||
| 24 | #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) | ||
| 25 | #define USER_DS MAKE_MM_SEG(__USER_DS) | ||
| 26 | #define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Get/set the SFC/DFC registers for MOVES instructions | ||
| 30 | */ | ||
| 31 | |||
| 32 | static inline mm_segment_t get_fs(void) | ||
| 33 | { | ||
| 34 | mm_segment_t _v; | ||
| 35 | __asm__ ("movec %/dfc,%0":"=r" (_v.seg):); | ||
| 36 | |||
| 37 | return _v; | ||
| 38 | } | ||
| 39 | |||
| 40 | static inline mm_segment_t get_ds(void) | ||
| 41 | { | ||
| 42 | /* return the supervisor data space code */ | ||
| 43 | return KERNEL_DS; | ||
| 44 | } | ||
| 45 | |||
| 46 | static inline void set_fs(mm_segment_t val) | ||
| 47 | { | ||
| 48 | __asm__ __volatile__ ("movec %0,%/sfc\n\t" | ||
| 49 | "movec %0,%/dfc\n\t" | ||
| 50 | : /* no outputs */ : "r" (val.seg) : "memory"); | ||
| 51 | } | ||
| 52 | |||
| 53 | #define segment_eq(a,b) ((a).seg == (b).seg) | ||
| 54 | |||
| 55 | #endif /* __ASSEMBLY__ */ | ||
| 56 | |||
| 57 | #endif /* _M68K_SEGMENT_H */ | ||
diff --git a/arch/m68k/include/asm/segment_no.h b/arch/m68k/include/asm/segment_no.h new file mode 100644 index 000000000000..42318ebec7ec --- /dev/null +++ b/arch/m68k/include/asm/segment_no.h | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | #ifndef _M68K_SEGMENT_H | ||
| 2 | #define _M68K_SEGMENT_H | ||
| 3 | |||
| 4 | /* define constants */ | ||
| 5 | /* Address spaces (FC0-FC2) */ | ||
| 6 | #define USER_DATA (1) | ||
| 7 | #ifndef __USER_DS | ||
| 8 | #define __USER_DS (USER_DATA) | ||
| 9 | #endif | ||
| 10 | #define USER_PROGRAM (2) | ||
| 11 | #define SUPER_DATA (5) | ||
| 12 | #ifndef __KERNEL_DS | ||
| 13 | #define __KERNEL_DS (SUPER_DATA) | ||
| 14 | #endif | ||
| 15 | #define SUPER_PROGRAM (6) | ||
| 16 | #define CPU_SPACE (7) | ||
| 17 | |||
| 18 | #ifndef __ASSEMBLY__ | ||
| 19 | |||
| 20 | typedef struct { | ||
| 21 | unsigned long seg; | ||
| 22 | } mm_segment_t; | ||
| 23 | |||
| 24 | #define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) | ||
| 25 | #define USER_DS MAKE_MM_SEG(__USER_DS) | ||
| 26 | #define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Get/set the SFC/DFC registers for MOVES instructions | ||
| 30 | */ | ||
| 31 | |||
| 32 | static inline mm_segment_t get_fs(void) | ||
| 33 | { | ||
| 34 | return USER_DS; | ||
| 35 | } | ||
| 36 | |||
| 37 | static inline mm_segment_t get_ds(void) | ||
| 38 | { | ||
| 39 | /* return the supervisor data space code */ | ||
| 40 | return KERNEL_DS; | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline void set_fs(mm_segment_t val) | ||
| 44 | { | ||
| 45 | } | ||
| 46 | |||
| 47 | #define segment_eq(a,b) ((a).seg == (b).seg) | ||
| 48 | |||
| 49 | #endif /* __ASSEMBLY__ */ | ||
| 50 | |||
| 51 | #endif /* _M68K_SEGMENT_H */ | ||
diff --git a/arch/m68k/include/asm/sembuf.h b/arch/m68k/include/asm/sembuf.h new file mode 100644 index 000000000000..2308052a8c24 --- /dev/null +++ b/arch/m68k/include/asm/sembuf.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | #ifndef _M68K_SEMBUF_H | ||
| 2 | #define _M68K_SEMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The semid64_ds structure for m68k architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct semid64_ds { | ||
| 15 | struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ | ||
| 16 | __kernel_time_t sem_otime; /* last semop time */ | ||
| 17 | unsigned long __unused1; | ||
| 18 | __kernel_time_t sem_ctime; /* last change time */ | ||
| 19 | unsigned long __unused2; | ||
| 20 | unsigned long sem_nsems; /* no. of semaphores in array */ | ||
| 21 | unsigned long __unused3; | ||
| 22 | unsigned long __unused4; | ||
| 23 | }; | ||
| 24 | |||
| 25 | #endif /* _M68K_SEMBUF_H */ | ||
diff --git a/arch/m68k/include/asm/serial.h b/arch/m68k/include/asm/serial.h new file mode 100644 index 000000000000..2b90d6e69070 --- /dev/null +++ b/arch/m68k/include/asm/serial.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-m68k/serial.h | ||
| 3 | * | ||
| 4 | * currently this seems useful only for a Q40, | ||
| 5 | * it's an almost exact copy of ../asm-alpha/serial.h | ||
| 6 | * | ||
| 7 | */ | ||
| 8 | |||
| 9 | |||
| 10 | /* | ||
| 11 | * This assumes you have a 1.8432 MHz clock for your UART. | ||
| 12 | * | ||
| 13 | * It'd be nice if someone built a serial card with a 24.576 MHz | ||
| 14 | * clock, since the 16550A is capable of handling a top speed of 1.5 | ||
| 15 | * megabits/second; but this requires the faster clock. | ||
| 16 | */ | ||
| 17 | #define BASE_BAUD ( 1843200 / 16 ) | ||
| 18 | |||
| 19 | /* Standard COM flags (except for COM4, because of the 8514 problem) */ | ||
| 20 | #ifdef CONFIG_SERIAL_DETECT_IRQ | ||
| 21 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) | ||
| 22 | #define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) | ||
| 23 | #else | ||
| 24 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) | ||
| 25 | #define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF | ||
| 26 | #endif | ||
| 27 | |||
| 28 | #define SERIAL_PORT_DFNS \ | ||
| 29 | /* UART CLK PORT IRQ FLAGS */ \ | ||
| 30 | { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ | ||
| 31 | { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ | ||
| 32 | { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ | ||
| 33 | { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ | ||
diff --git a/arch/m68k/include/asm/setup.h b/arch/m68k/include/asm/setup.h new file mode 100644 index 000000000000..842f86f75ccd --- /dev/null +++ b/arch/m68k/include/asm/setup.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "setup_no.h" | ||
| 3 | #else | ||
| 4 | #include "setup_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/setup_mm.h b/arch/m68k/include/asm/setup_mm.h new file mode 100644 index 000000000000..4dfb3952b375 --- /dev/null +++ b/arch/m68k/include/asm/setup_mm.h | |||
| @@ -0,0 +1,376 @@ | |||
| 1 | /* | ||
| 2 | ** asm/setup.h -- Definition of the Linux/m68k setup information | ||
| 3 | ** | ||
| 4 | ** Copyright 1992 by Greg Harp | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | ** Created 09/29/92 by Greg Harp | ||
| 11 | ** | ||
| 12 | ** 5/2/94 Roman Hodek: | ||
| 13 | ** Added bi_atari part of the machine dependent union bi_un; for now it | ||
| 14 | ** contains just a model field to distinguish between TT and Falcon. | ||
| 15 | ** 26/7/96 Roman Zippel: | ||
| 16 | ** Renamed to setup.h; added some useful macros to allow gcc some | ||
| 17 | ** optimizations if possible. | ||
| 18 | ** 5/10/96 Geert Uytterhoeven: | ||
| 19 | ** Redesign of the boot information structure; moved boot information | ||
| 20 | ** structure to bootinfo.h | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _M68K_SETUP_H | ||
| 24 | #define _M68K_SETUP_H | ||
| 25 | |||
| 26 | |||
| 27 | |||
| 28 | /* | ||
| 29 | * Linux/m68k Architectures | ||
| 30 | */ | ||
| 31 | |||
| 32 | #define MACH_AMIGA 1 | ||
| 33 | #define MACH_ATARI 2 | ||
| 34 | #define MACH_MAC 3 | ||
| 35 | #define MACH_APOLLO 4 | ||
| 36 | #define MACH_SUN3 5 | ||
| 37 | #define MACH_MVME147 6 | ||
| 38 | #define MACH_MVME16x 7 | ||
| 39 | #define MACH_BVME6000 8 | ||
| 40 | #define MACH_HP300 9 | ||
| 41 | #define MACH_Q40 10 | ||
| 42 | #define MACH_SUN3X 11 | ||
| 43 | |||
| 44 | #define COMMAND_LINE_SIZE 256 | ||
| 45 | |||
| 46 | #ifdef __KERNEL__ | ||
| 47 | |||
| 48 | #define CL_SIZE COMMAND_LINE_SIZE | ||
| 49 | |||
| 50 | #ifndef __ASSEMBLY__ | ||
| 51 | extern unsigned long m68k_machtype; | ||
| 52 | #endif /* !__ASSEMBLY__ */ | ||
| 53 | |||
| 54 | #if !defined(CONFIG_AMIGA) | ||
| 55 | # define MACH_IS_AMIGA (0) | ||
| 56 | #elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ | ||
| 57 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 58 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 59 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 60 | # define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA) | ||
| 61 | #else | ||
| 62 | # define MACH_AMIGA_ONLY | ||
| 63 | # define MACH_IS_AMIGA (1) | ||
| 64 | # define MACH_TYPE (MACH_AMIGA) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #if !defined(CONFIG_ATARI) | ||
| 68 | # define MACH_IS_ATARI (0) | ||
| 69 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ | ||
| 70 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 71 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 72 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 73 | # define MACH_IS_ATARI (m68k_machtype == MACH_ATARI) | ||
| 74 | #else | ||
| 75 | # define MACH_ATARI_ONLY | ||
| 76 | # define MACH_IS_ATARI (1) | ||
| 77 | # define MACH_TYPE (MACH_ATARI) | ||
| 78 | #endif | ||
| 79 | |||
| 80 | #if !defined(CONFIG_MAC) | ||
| 81 | # define MACH_IS_MAC (0) | ||
| 82 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \ | ||
| 83 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 84 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 85 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 86 | # define MACH_IS_MAC (m68k_machtype == MACH_MAC) | ||
| 87 | #else | ||
| 88 | # define MACH_MAC_ONLY | ||
| 89 | # define MACH_IS_MAC (1) | ||
| 90 | # define MACH_TYPE (MACH_MAC) | ||
| 91 | #endif | ||
| 92 | |||
| 93 | #if defined(CONFIG_SUN3) | ||
| 94 | #define MACH_IS_SUN3 (1) | ||
| 95 | #define MACH_SUN3_ONLY (1) | ||
| 96 | #define MACH_TYPE (MACH_SUN3) | ||
| 97 | #else | ||
| 98 | #define MACH_IS_SUN3 (0) | ||
| 99 | #endif | ||
| 100 | |||
| 101 | #if !defined (CONFIG_APOLLO) | ||
| 102 | # define MACH_IS_APOLLO (0) | ||
| 103 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 104 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 105 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 106 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 107 | # define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO) | ||
| 108 | #else | ||
| 109 | # define MACH_APOLLO_ONLY | ||
| 110 | # define MACH_IS_APOLLO (1) | ||
| 111 | # define MACH_TYPE (MACH_APOLLO) | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if !defined (CONFIG_MVME147) | ||
| 115 | # define MACH_IS_MVME147 (0) | ||
| 116 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 117 | || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ | ||
| 118 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 119 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x) | ||
| 120 | # define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147) | ||
| 121 | #else | ||
| 122 | # define MACH_MVME147_ONLY | ||
| 123 | # define MACH_IS_MVME147 (1) | ||
| 124 | # define MACH_TYPE (MACH_MVME147) | ||
| 125 | #endif | ||
| 126 | |||
| 127 | #if !defined (CONFIG_MVME16x) | ||
| 128 | # define MACH_IS_MVME16x (0) | ||
| 129 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 130 | || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ | ||
| 131 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 132 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 133 | # define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x) | ||
| 134 | #else | ||
| 135 | # define MACH_MVME16x_ONLY | ||
| 136 | # define MACH_IS_MVME16x (1) | ||
| 137 | # define MACH_TYPE (MACH_MVME16x) | ||
| 138 | #endif | ||
| 139 | |||
| 140 | #if !defined (CONFIG_BVME6000) | ||
| 141 | # define MACH_IS_BVME6000 (0) | ||
| 142 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 143 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 144 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 145 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 146 | # define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000) | ||
| 147 | #else | ||
| 148 | # define MACH_BVME6000_ONLY | ||
| 149 | # define MACH_IS_BVME6000 (1) | ||
| 150 | # define MACH_TYPE (MACH_BVME6000) | ||
| 151 | #endif | ||
| 152 | |||
| 153 | #if !defined (CONFIG_HP300) | ||
| 154 | # define MACH_IS_HP300 (0) | ||
| 155 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 156 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 157 | || defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \ | ||
| 158 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 159 | # define MACH_IS_HP300 (m68k_machtype == MACH_HP300) | ||
| 160 | #else | ||
| 161 | # define MACH_HP300_ONLY | ||
| 162 | # define MACH_IS_HP300 (1) | ||
| 163 | # define MACH_TYPE (MACH_HP300) | ||
| 164 | #endif | ||
| 165 | |||
| 166 | #if !defined (CONFIG_Q40) | ||
| 167 | # define MACH_IS_Q40 (0) | ||
| 168 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 169 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 170 | || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ | ||
| 171 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 172 | # define MACH_IS_Q40 (m68k_machtype == MACH_Q40) | ||
| 173 | #else | ||
| 174 | # define MACH_Q40_ONLY | ||
| 175 | # define MACH_IS_Q40 (1) | ||
| 176 | # define MACH_TYPE (MACH_Q40) | ||
| 177 | #endif | ||
| 178 | |||
| 179 | #if !defined (CONFIG_SUN3X) | ||
| 180 | # define MACH_IS_SUN3X (0) | ||
| 181 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 182 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 183 | || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ | ||
| 184 | || defined(CONFIG_Q40) || defined(CONFIG_MVME147) | ||
| 185 | # define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X) | ||
| 186 | #else | ||
| 187 | # define CONFIG_SUN3X_ONLY | ||
| 188 | # define MACH_IS_SUN3X (1) | ||
| 189 | # define MACH_TYPE (MACH_SUN3X) | ||
| 190 | #endif | ||
| 191 | |||
| 192 | #ifndef MACH_TYPE | ||
| 193 | # define MACH_TYPE (m68k_machtype) | ||
| 194 | #endif | ||
| 195 | |||
| 196 | #endif /* __KERNEL__ */ | ||
| 197 | |||
| 198 | |||
| 199 | /* | ||
| 200 | * CPU, FPU and MMU types | ||
| 201 | * | ||
| 202 | * Note: we may rely on the following equalities: | ||
| 203 | * | ||
| 204 | * CPU_68020 == MMU_68851 | ||
| 205 | * CPU_68030 == MMU_68030 | ||
| 206 | * CPU_68040 == FPU_68040 == MMU_68040 | ||
| 207 | * CPU_68060 == FPU_68060 == MMU_68060 | ||
| 208 | */ | ||
| 209 | |||
| 210 | #define CPUB_68020 0 | ||
| 211 | #define CPUB_68030 1 | ||
| 212 | #define CPUB_68040 2 | ||
| 213 | #define CPUB_68060 3 | ||
| 214 | |||
| 215 | #define CPU_68020 (1<<CPUB_68020) | ||
| 216 | #define CPU_68030 (1<<CPUB_68030) | ||
| 217 | #define CPU_68040 (1<<CPUB_68040) | ||
| 218 | #define CPU_68060 (1<<CPUB_68060) | ||
| 219 | |||
| 220 | #define FPUB_68881 0 | ||
| 221 | #define FPUB_68882 1 | ||
| 222 | #define FPUB_68040 2 /* Internal FPU */ | ||
| 223 | #define FPUB_68060 3 /* Internal FPU */ | ||
| 224 | #define FPUB_SUNFPA 4 /* Sun-3 FPA */ | ||
| 225 | |||
| 226 | #define FPU_68881 (1<<FPUB_68881) | ||
| 227 | #define FPU_68882 (1<<FPUB_68882) | ||
| 228 | #define FPU_68040 (1<<FPUB_68040) | ||
| 229 | #define FPU_68060 (1<<FPUB_68060) | ||
| 230 | #define FPU_SUNFPA (1<<FPUB_SUNFPA) | ||
| 231 | |||
| 232 | #define MMUB_68851 0 | ||
| 233 | #define MMUB_68030 1 /* Internal MMU */ | ||
| 234 | #define MMUB_68040 2 /* Internal MMU */ | ||
| 235 | #define MMUB_68060 3 /* Internal MMU */ | ||
| 236 | #define MMUB_APOLLO 4 /* Custom Apollo */ | ||
| 237 | #define MMUB_SUN3 5 /* Custom Sun-3 */ | ||
| 238 | |||
| 239 | #define MMU_68851 (1<<MMUB_68851) | ||
| 240 | #define MMU_68030 (1<<MMUB_68030) | ||
| 241 | #define MMU_68040 (1<<MMUB_68040) | ||
| 242 | #define MMU_68060 (1<<MMUB_68060) | ||
| 243 | #define MMU_SUN3 (1<<MMUB_SUN3) | ||
| 244 | #define MMU_APOLLO (1<<MMUB_APOLLO) | ||
| 245 | |||
| 246 | #ifdef __KERNEL__ | ||
| 247 | |||
| 248 | #ifndef __ASSEMBLY__ | ||
| 249 | extern unsigned long m68k_cputype; | ||
| 250 | extern unsigned long m68k_fputype; | ||
| 251 | extern unsigned long m68k_mmutype; | ||
| 252 | #ifdef CONFIG_VME | ||
| 253 | extern unsigned long vme_brdtype; | ||
| 254 | #endif | ||
| 255 | |||
| 256 | /* | ||
| 257 | * m68k_is040or060 is != 0 for a '040 or higher; | ||
| 258 | * used numbers are 4 for 68040 and 6 for 68060. | ||
| 259 | */ | ||
| 260 | |||
| 261 | extern int m68k_is040or060; | ||
| 262 | #endif /* !__ASSEMBLY__ */ | ||
| 263 | |||
| 264 | #if !defined(CONFIG_M68020) | ||
| 265 | # define CPU_IS_020 (0) | ||
| 266 | # define MMU_IS_851 (0) | ||
| 267 | # define MMU_IS_SUN3 (0) | ||
| 268 | #elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 269 | # define CPU_IS_020 (m68k_cputype & CPU_68020) | ||
| 270 | # define MMU_IS_851 (m68k_mmutype & MMU_68851) | ||
| 271 | # define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */ | ||
| 272 | #else | ||
| 273 | # define CPU_M68020_ONLY | ||
| 274 | # define CPU_IS_020 (1) | ||
| 275 | #ifdef MACH_SUN3_ONLY | ||
| 276 | # define MMU_IS_SUN3 (1) | ||
| 277 | # define MMU_IS_851 (0) | ||
| 278 | #else | ||
| 279 | # define MMU_IS_SUN3 (0) | ||
| 280 | # define MMU_IS_851 (1) | ||
| 281 | #endif | ||
| 282 | #endif | ||
| 283 | |||
| 284 | #if !defined(CONFIG_M68030) | ||
| 285 | # define CPU_IS_030 (0) | ||
| 286 | # define MMU_IS_030 (0) | ||
| 287 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 288 | # define CPU_IS_030 (m68k_cputype & CPU_68030) | ||
| 289 | # define MMU_IS_030 (m68k_mmutype & MMU_68030) | ||
| 290 | #else | ||
| 291 | # define CPU_M68030_ONLY | ||
| 292 | # define CPU_IS_030 (1) | ||
| 293 | # define MMU_IS_030 (1) | ||
| 294 | #endif | ||
| 295 | |||
| 296 | #if !defined(CONFIG_M68040) | ||
| 297 | # define CPU_IS_040 (0) | ||
| 298 | # define MMU_IS_040 (0) | ||
| 299 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060) | ||
| 300 | # define CPU_IS_040 (m68k_cputype & CPU_68040) | ||
| 301 | # define MMU_IS_040 (m68k_mmutype & MMU_68040) | ||
| 302 | #else | ||
| 303 | # define CPU_M68040_ONLY | ||
| 304 | # define CPU_IS_040 (1) | ||
| 305 | # define MMU_IS_040 (1) | ||
| 306 | #endif | ||
| 307 | |||
| 308 | #if !defined(CONFIG_M68060) | ||
| 309 | # define CPU_IS_060 (0) | ||
| 310 | # define MMU_IS_060 (0) | ||
| 311 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040) | ||
| 312 | # define CPU_IS_060 (m68k_cputype & CPU_68060) | ||
| 313 | # define MMU_IS_060 (m68k_mmutype & MMU_68060) | ||
| 314 | #else | ||
| 315 | # define CPU_M68060_ONLY | ||
| 316 | # define CPU_IS_060 (1) | ||
| 317 | # define MMU_IS_060 (1) | ||
| 318 | #endif | ||
| 319 | |||
| 320 | #if !defined(CONFIG_M68020) && !defined(CONFIG_M68030) | ||
| 321 | # define CPU_IS_020_OR_030 (0) | ||
| 322 | #else | ||
| 323 | # define CPU_M68020_OR_M68030 | ||
| 324 | # if defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 325 | # define CPU_IS_020_OR_030 (!m68k_is040or060) | ||
| 326 | # else | ||
| 327 | # define CPU_M68020_OR_M68030_ONLY | ||
| 328 | # define CPU_IS_020_OR_030 (1) | ||
| 329 | # endif | ||
| 330 | #endif | ||
| 331 | |||
| 332 | #if !defined(CONFIG_M68040) && !defined(CONFIG_M68060) | ||
| 333 | # define CPU_IS_040_OR_060 (0) | ||
| 334 | #else | ||
| 335 | # define CPU_M68040_OR_M68060 | ||
| 336 | # if defined(CONFIG_M68020) || defined(CONFIG_M68030) | ||
| 337 | # define CPU_IS_040_OR_060 (m68k_is040or060) | ||
| 338 | # else | ||
| 339 | # define CPU_M68040_OR_M68060_ONLY | ||
| 340 | # define CPU_IS_040_OR_060 (1) | ||
| 341 | # endif | ||
| 342 | #endif | ||
| 343 | |||
| 344 | #define CPU_TYPE (m68k_cputype) | ||
| 345 | |||
| 346 | #ifdef CONFIG_M68KFPU_EMU | ||
| 347 | # ifdef CONFIG_M68KFPU_EMU_ONLY | ||
| 348 | # define FPU_IS_EMU (1) | ||
| 349 | # else | ||
| 350 | # define FPU_IS_EMU (!m68k_fputype) | ||
| 351 | # endif | ||
| 352 | #else | ||
| 353 | # define FPU_IS_EMU (0) | ||
| 354 | #endif | ||
| 355 | |||
| 356 | |||
| 357 | /* | ||
| 358 | * Miscellaneous | ||
| 359 | */ | ||
| 360 | |||
| 361 | #define NUM_MEMINFO 4 | ||
| 362 | |||
| 363 | #ifndef __ASSEMBLY__ | ||
| 364 | struct mem_info { | ||
| 365 | unsigned long addr; /* physical address of memory chunk */ | ||
| 366 | unsigned long size; /* length of memory chunk (in bytes) */ | ||
| 367 | }; | ||
| 368 | |||
| 369 | extern int m68k_num_memory; /* # of memory blocks found (and used) */ | ||
| 370 | extern int m68k_realnum_memory; /* real # of memory blocks found */ | ||
| 371 | extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ | ||
| 372 | #endif | ||
| 373 | |||
| 374 | #endif /* __KERNEL__ */ | ||
| 375 | |||
| 376 | #endif /* _M68K_SETUP_H */ | ||
diff --git a/arch/m68k/include/asm/setup_no.h b/arch/m68k/include/asm/setup_no.h new file mode 100644 index 000000000000..45d286ce9398 --- /dev/null +++ b/arch/m68k/include/asm/setup_no.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | |||
| 3 | #include <asm/setup_mm.h> | ||
| 4 | |||
| 5 | /* We have a bigger command line buffer. */ | ||
| 6 | #undef COMMAND_LINE_SIZE | ||
| 7 | |||
| 8 | #endif /* __KERNEL__ */ | ||
| 9 | |||
| 10 | #define COMMAND_LINE_SIZE 512 | ||
diff --git a/arch/m68k/include/asm/shm.h b/arch/m68k/include/asm/shm.h new file mode 100644 index 000000000000..fa56ec84a126 --- /dev/null +++ b/arch/m68k/include/asm/shm.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _M68K_SHM_H | ||
| 2 | #define _M68K_SHM_H | ||
| 3 | |||
| 4 | |||
| 5 | /* format of page table entries that correspond to shared memory pages | ||
| 6 | currently out in swap space (see also mm/swap.c): | ||
| 7 | bits 0-1 (PAGE_PRESENT) is = 0 | ||
| 8 | bits 8..2 (SWP_TYPE) are = SHM_SWP_TYPE | ||
| 9 | bits 31..9 are used like this: | ||
| 10 | bits 15..9 (SHM_ID) the id of the shared memory segment | ||
| 11 | bits 30..16 (SHM_IDX) the index of the page within the shared memory segment | ||
| 12 | (actually only bits 25..16 get used since SHMMAX is so low) | ||
| 13 | bit 31 (SHM_READ_ONLY) flag whether the page belongs to a read-only attach | ||
| 14 | */ | ||
| 15 | /* on the m68k both bits 0 and 1 must be zero */ | ||
| 16 | /* format on the sun3 is similar, but bits 30, 31 are set to zero and all | ||
| 17 | others are reduced by 2. --m */ | ||
| 18 | |||
| 19 | #ifndef CONFIG_SUN3 | ||
| 20 | #define SHM_ID_SHIFT 9 | ||
| 21 | #else | ||
| 22 | #define SHM_ID_SHIFT 7 | ||
| 23 | #endif | ||
| 24 | #define _SHM_ID_BITS 7 | ||
| 25 | #define SHM_ID_MASK ((1<<_SHM_ID_BITS)-1) | ||
| 26 | |||
| 27 | #define SHM_IDX_SHIFT (SHM_ID_SHIFT+_SHM_ID_BITS) | ||
| 28 | #define _SHM_IDX_BITS 15 | ||
| 29 | #define SHM_IDX_MASK ((1<<_SHM_IDX_BITS)-1) | ||
| 30 | |||
| 31 | #endif /* _M68K_SHM_H */ | ||
diff --git a/arch/m68k/include/asm/shmbuf.h b/arch/m68k/include/asm/shmbuf.h new file mode 100644 index 000000000000..f8928d62f1b7 --- /dev/null +++ b/arch/m68k/include/asm/shmbuf.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | #ifndef _M68K_SHMBUF_H | ||
| 2 | #define _M68K_SHMBUF_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The shmid64_ds structure for m68k architecture. | ||
| 6 | * Note extra padding because this structure is passed back and forth | ||
| 7 | * between kernel and user space. | ||
| 8 | * | ||
| 9 | * Pad space is left for: | ||
| 10 | * - 64-bit time_t to solve y2038 problem | ||
| 11 | * - 2 miscellaneous 32-bit values | ||
| 12 | */ | ||
| 13 | |||
| 14 | struct shmid64_ds { | ||
| 15 | struct ipc64_perm shm_perm; /* operation perms */ | ||
| 16 | size_t shm_segsz; /* size of segment (bytes) */ | ||
| 17 | __kernel_time_t shm_atime; /* last attach time */ | ||
| 18 | unsigned long __unused1; | ||
| 19 | __kernel_time_t shm_dtime; /* last detach time */ | ||
| 20 | unsigned long __unused2; | ||
| 21 | __kernel_time_t shm_ctime; /* last change time */ | ||
| 22 | unsigned long __unused3; | ||
| 23 | __kernel_pid_t shm_cpid; /* pid of creator */ | ||
| 24 | __kernel_pid_t shm_lpid; /* pid of last operator */ | ||
| 25 | unsigned long shm_nattch; /* no. of current attaches */ | ||
| 26 | unsigned long __unused4; | ||
| 27 | unsigned long __unused5; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct shminfo64 { | ||
| 31 | unsigned long shmmax; | ||
| 32 | unsigned long shmmin; | ||
| 33 | unsigned long shmmni; | ||
| 34 | unsigned long shmseg; | ||
| 35 | unsigned long shmall; | ||
| 36 | unsigned long __unused1; | ||
| 37 | unsigned long __unused2; | ||
| 38 | unsigned long __unused3; | ||
| 39 | unsigned long __unused4; | ||
| 40 | }; | ||
| 41 | |||
| 42 | #endif /* _M68K_SHMBUF_H */ | ||
diff --git a/arch/m68k/include/asm/shmparam.h b/arch/m68k/include/asm/shmparam.h new file mode 100644 index 000000000000..558892a2efb3 --- /dev/null +++ b/arch/m68k/include/asm/shmparam.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68K_SHMPARAM_H | ||
| 2 | #define _M68K_SHMPARAM_H | ||
| 3 | |||
| 4 | #define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ | ||
| 5 | |||
| 6 | #endif /* _M68K_SHMPARAM_H */ | ||
diff --git a/arch/m68k/include/asm/sigcontext.h b/arch/m68k/include/asm/sigcontext.h new file mode 100644 index 000000000000..bff6d40345a9 --- /dev/null +++ b/arch/m68k/include/asm/sigcontext.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "sigcontext_no.h" | ||
| 3 | #else | ||
| 4 | #include "sigcontext_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/sigcontext_mm.h b/arch/m68k/include/asm/sigcontext_mm.h new file mode 100644 index 000000000000..64fbe34cf26f --- /dev/null +++ b/arch/m68k/include/asm/sigcontext_mm.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | #ifndef _ASM_M68k_SIGCONTEXT_H | ||
| 2 | #define _ASM_M68k_SIGCONTEXT_H | ||
| 3 | |||
| 4 | struct sigcontext { | ||
| 5 | unsigned long sc_mask; /* old sigmask */ | ||
| 6 | unsigned long sc_usp; /* old user stack pointer */ | ||
| 7 | unsigned long sc_d0; | ||
| 8 | unsigned long sc_d1; | ||
| 9 | unsigned long sc_a0; | ||
| 10 | unsigned long sc_a1; | ||
| 11 | unsigned short sc_sr; | ||
| 12 | unsigned long sc_pc; | ||
| 13 | unsigned short sc_formatvec; | ||
| 14 | unsigned long sc_fpregs[2*3]; /* room for two fp registers */ | ||
| 15 | unsigned long sc_fpcntl[3]; | ||
| 16 | unsigned char sc_fpstate[216]; | ||
| 17 | }; | ||
| 18 | |||
| 19 | #endif | ||
diff --git a/arch/m68k/include/asm/sigcontext_no.h b/arch/m68k/include/asm/sigcontext_no.h new file mode 100644 index 000000000000..36c293fc133d --- /dev/null +++ b/arch/m68k/include/asm/sigcontext_no.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | #ifndef _ASM_M68KNOMMU_SIGCONTEXT_H | ||
| 2 | #define _ASM_M68KNOMMU_SIGCONTEXT_H | ||
| 3 | |||
| 4 | struct sigcontext { | ||
| 5 | unsigned long sc_mask; /* old sigmask */ | ||
| 6 | unsigned long sc_usp; /* old user stack pointer */ | ||
| 7 | unsigned long sc_d0; | ||
| 8 | unsigned long sc_d1; | ||
| 9 | unsigned long sc_a0; | ||
| 10 | unsigned long sc_a1; | ||
| 11 | unsigned long sc_a5; | ||
| 12 | unsigned short sc_sr; | ||
| 13 | unsigned long sc_pc; | ||
| 14 | unsigned short sc_formatvec; | ||
| 15 | }; | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/arch/m68k/include/asm/siginfo.h b/arch/m68k/include/asm/siginfo.h new file mode 100644 index 000000000000..61219d7affc8 --- /dev/null +++ b/arch/m68k/include/asm/siginfo.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "siginfo_no.h" | ||
| 3 | #else | ||
| 4 | #include "siginfo_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/siginfo_mm.h b/arch/m68k/include/asm/siginfo_mm.h new file mode 100644 index 000000000000..05a8d6d90b58 --- /dev/null +++ b/arch/m68k/include/asm/siginfo_mm.h | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | #ifndef _M68K_SIGINFO_H | ||
| 2 | #define _M68K_SIGINFO_H | ||
| 3 | |||
| 4 | #define HAVE_ARCH_SIGINFO_T | ||
| 5 | #define HAVE_ARCH_COPY_SIGINFO | ||
| 6 | |||
| 7 | #include <asm-generic/siginfo.h> | ||
| 8 | |||
| 9 | typedef struct siginfo { | ||
| 10 | int si_signo; | ||
| 11 | int si_errno; | ||
| 12 | int si_code; | ||
| 13 | |||
| 14 | union { | ||
| 15 | int _pad[SI_PAD_SIZE]; | ||
| 16 | |||
| 17 | /* kill() */ | ||
| 18 | struct { | ||
| 19 | __kernel_pid_t _pid; /* sender's pid */ | ||
| 20 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 21 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 22 | } _kill; | ||
| 23 | |||
| 24 | /* POSIX.1b timers */ | ||
| 25 | struct { | ||
| 26 | timer_t _tid; /* timer id */ | ||
| 27 | int _overrun; /* overrun count */ | ||
| 28 | char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)]; | ||
| 29 | sigval_t _sigval; /* same as below */ | ||
| 30 | int _sys_private; /* not to be passed to user */ | ||
| 31 | } _timer; | ||
| 32 | |||
| 33 | /* POSIX.1b signals */ | ||
| 34 | struct { | ||
| 35 | __kernel_pid_t _pid; /* sender's pid */ | ||
| 36 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 37 | sigval_t _sigval; | ||
| 38 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 39 | } _rt; | ||
| 40 | |||
| 41 | /* SIGCHLD */ | ||
| 42 | struct { | ||
| 43 | __kernel_pid_t _pid; /* which child */ | ||
| 44 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 45 | int _status; /* exit code */ | ||
| 46 | clock_t _utime; | ||
| 47 | clock_t _stime; | ||
| 48 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 49 | } _sigchld; | ||
| 50 | |||
| 51 | /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ | ||
| 52 | struct { | ||
| 53 | void *_addr; /* faulting insn/memory ref. */ | ||
| 54 | } _sigfault; | ||
| 55 | |||
| 56 | /* SIGPOLL */ | ||
| 57 | struct { | ||
| 58 | int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ | ||
| 59 | int _fd; | ||
| 60 | } _sigpoll; | ||
| 61 | } _sifields; | ||
| 62 | } siginfo_t; | ||
| 63 | |||
| 64 | #define UID16_SIGINFO_COMPAT_NEEDED | ||
| 65 | |||
| 66 | /* | ||
| 67 | * How these fields are to be accessed. | ||
| 68 | */ | ||
| 69 | #undef si_uid | ||
| 70 | #ifdef __KERNEL__ | ||
| 71 | #define si_uid _sifields._kill._uid32 | ||
| 72 | #define si_uid16 _sifields._kill._uid | ||
| 73 | #else | ||
| 74 | #define si_uid _sifields._kill._uid | ||
| 75 | #endif | ||
| 76 | |||
| 77 | #ifdef __KERNEL__ | ||
| 78 | |||
| 79 | #include <linux/string.h> | ||
| 80 | |||
| 81 | static inline void copy_siginfo(struct siginfo *to, struct siginfo *from) | ||
| 82 | { | ||
| 83 | if (from->si_code < 0) | ||
| 84 | memcpy(to, from, sizeof(*to)); | ||
| 85 | else | ||
| 86 | /* _sigchld is currently the largest know union member */ | ||
| 87 | memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld)); | ||
| 88 | } | ||
| 89 | |||
| 90 | #endif /* __KERNEL__ */ | ||
| 91 | |||
| 92 | #endif | ||
diff --git a/arch/m68k/include/asm/siginfo_no.h b/arch/m68k/include/asm/siginfo_no.h new file mode 100644 index 000000000000..b18e5f4064ae --- /dev/null +++ b/arch/m68k/include/asm/siginfo_no.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68KNOMMU_SIGINFO_H | ||
| 2 | #define _M68KNOMMU_SIGINFO_H | ||
| 3 | |||
| 4 | #include <asm-generic/siginfo.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/m68k/include/asm/signal.h b/arch/m68k/include/asm/signal.h new file mode 100644 index 000000000000..3c19988bd93c --- /dev/null +++ b/arch/m68k/include/asm/signal.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "signal_no.h" | ||
| 3 | #else | ||
| 4 | #include "signal_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/signal_mm.h b/arch/m68k/include/asm/signal_mm.h new file mode 100644 index 000000000000..3db8a81942f1 --- /dev/null +++ b/arch/m68k/include/asm/signal_mm.h | |||
| @@ -0,0 +1,206 @@ | |||
| 1 | #ifndef _M68K_SIGNAL_H | ||
| 2 | #define _M68K_SIGNAL_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 23 | #else | ||
| 24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 25 | |||
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 78 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 79 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 80 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 81 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 82 | * | ||
| 83 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 84 | * Unix names RESETHAND and NODEFER respectively. | ||
| 85 | */ | ||
| 86 | #define SA_NOCLDSTOP 0x00000001 | ||
| 87 | #define SA_NOCLDWAIT 0x00000002 | ||
| 88 | #define SA_SIGINFO 0x00000004 | ||
| 89 | #define SA_ONSTACK 0x08000000 | ||
| 90 | #define SA_RESTART 0x10000000 | ||
| 91 | #define SA_NODEFER 0x40000000 | ||
| 92 | #define SA_RESETHAND 0x80000000 | ||
| 93 | |||
| 94 | #define SA_NOMASK SA_NODEFER | ||
| 95 | #define SA_ONESHOT SA_RESETHAND | ||
| 96 | |||
| 97 | /* | ||
| 98 | * sigaltstack controls | ||
| 99 | */ | ||
| 100 | #define SS_ONSTACK 1 | ||
| 101 | #define SS_DISABLE 2 | ||
| 102 | |||
| 103 | #define MINSIGSTKSZ 2048 | ||
| 104 | #define SIGSTKSZ 8192 | ||
| 105 | |||
| 106 | #include <asm-generic/signal.h> | ||
| 107 | |||
| 108 | #ifdef __KERNEL__ | ||
| 109 | struct old_sigaction { | ||
| 110 | __sighandler_t sa_handler; | ||
| 111 | old_sigset_t sa_mask; | ||
| 112 | unsigned long sa_flags; | ||
| 113 | __sigrestore_t sa_restorer; | ||
| 114 | }; | ||
| 115 | |||
| 116 | struct sigaction { | ||
| 117 | __sighandler_t sa_handler; | ||
| 118 | unsigned long sa_flags; | ||
| 119 | __sigrestore_t sa_restorer; | ||
| 120 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct k_sigaction { | ||
| 124 | struct sigaction sa; | ||
| 125 | }; | ||
| 126 | #else | ||
| 127 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 128 | |||
| 129 | struct sigaction { | ||
| 130 | union { | ||
| 131 | __sighandler_t _sa_handler; | ||
| 132 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 133 | } _u; | ||
| 134 | sigset_t sa_mask; | ||
| 135 | unsigned long sa_flags; | ||
| 136 | void (*sa_restorer)(void); | ||
| 137 | }; | ||
| 138 | |||
| 139 | #define sa_handler _u._sa_handler | ||
| 140 | #define sa_sigaction _u._sa_sigaction | ||
| 141 | |||
| 142 | #endif /* __KERNEL__ */ | ||
| 143 | |||
| 144 | typedef struct sigaltstack { | ||
| 145 | void __user *ss_sp; | ||
| 146 | int ss_flags; | ||
| 147 | size_t ss_size; | ||
| 148 | } stack_t; | ||
| 149 | |||
| 150 | #ifdef __KERNEL__ | ||
| 151 | #include <asm/sigcontext.h> | ||
| 152 | |||
| 153 | #define __HAVE_ARCH_SIG_BITOPS | ||
| 154 | |||
| 155 | static inline void sigaddset(sigset_t *set, int _sig) | ||
| 156 | { | ||
| 157 | asm ("bfset %0{%1,#1}" | ||
| 158 | : "+od" (*set) | ||
| 159 | : "id" ((_sig - 1) ^ 31) | ||
| 160 | : "cc"); | ||
| 161 | } | ||
| 162 | |||
| 163 | static inline void sigdelset(sigset_t *set, int _sig) | ||
| 164 | { | ||
| 165 | asm ("bfclr %0{%1,#1}" | ||
| 166 | : "+od" (*set) | ||
| 167 | : "id" ((_sig - 1) ^ 31) | ||
| 168 | : "cc"); | ||
| 169 | } | ||
| 170 | |||
| 171 | static inline int __const_sigismember(sigset_t *set, int _sig) | ||
| 172 | { | ||
| 173 | unsigned long sig = _sig - 1; | ||
| 174 | return 1 & (set->sig[sig / _NSIG_BPW] >> (sig % _NSIG_BPW)); | ||
| 175 | } | ||
| 176 | |||
| 177 | static inline int __gen_sigismember(sigset_t *set, int _sig) | ||
| 178 | { | ||
| 179 | int ret; | ||
| 180 | asm ("bfextu %1{%2,#1},%0" | ||
| 181 | : "=d" (ret) | ||
| 182 | : "od" (*set), "id" ((_sig-1) ^ 31) | ||
| 183 | : "cc"); | ||
| 184 | return ret; | ||
| 185 | } | ||
| 186 | |||
| 187 | #define sigismember(set,sig) \ | ||
| 188 | (__builtin_constant_p(sig) ? \ | ||
| 189 | __const_sigismember(set,sig) : \ | ||
| 190 | __gen_sigismember(set,sig)) | ||
| 191 | |||
| 192 | static inline int sigfindinword(unsigned long word) | ||
| 193 | { | ||
| 194 | asm ("bfffo %1{#0,#0},%0" | ||
| 195 | : "=d" (word) | ||
| 196 | : "d" (word & -word) | ||
| 197 | : "cc"); | ||
| 198 | return word ^ 31; | ||
| 199 | } | ||
| 200 | |||
| 201 | struct pt_regs; | ||
| 202 | extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie); | ||
| 203 | |||
| 204 | #endif /* __KERNEL__ */ | ||
| 205 | |||
| 206 | #endif /* _M68K_SIGNAL_H */ | ||
diff --git a/arch/m68k/include/asm/signal_no.h b/arch/m68k/include/asm/signal_no.h new file mode 100644 index 000000000000..216c08be54a0 --- /dev/null +++ b/arch/m68k/include/asm/signal_no.h | |||
| @@ -0,0 +1,159 @@ | |||
| 1 | #ifndef _M68KNOMMU_SIGNAL_H | ||
| 2 | #define _M68KNOMMU_SIGNAL_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 23 | #else | ||
| 24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 25 | |||
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 78 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 79 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 80 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 81 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 82 | * | ||
| 83 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 84 | * Unix names RESETHAND and NODEFER respectively. | ||
| 85 | */ | ||
| 86 | #define SA_NOCLDSTOP 0x00000001 | ||
| 87 | #define SA_NOCLDWAIT 0x00000002 | ||
| 88 | #define SA_SIGINFO 0x00000004 | ||
| 89 | #define SA_ONSTACK 0x08000000 | ||
| 90 | #define SA_RESTART 0x10000000 | ||
| 91 | #define SA_NODEFER 0x40000000 | ||
| 92 | #define SA_RESETHAND 0x80000000 | ||
| 93 | |||
| 94 | #define SA_NOMASK SA_NODEFER | ||
| 95 | #define SA_ONESHOT SA_RESETHAND | ||
| 96 | |||
| 97 | /* | ||
| 98 | * sigaltstack controls | ||
| 99 | */ | ||
| 100 | #define SS_ONSTACK 1 | ||
| 101 | #define SS_DISABLE 2 | ||
| 102 | |||
| 103 | #define MINSIGSTKSZ 2048 | ||
| 104 | #define SIGSTKSZ 8192 | ||
| 105 | |||
| 106 | #include <asm-generic/signal.h> | ||
| 107 | |||
| 108 | #ifdef __KERNEL__ | ||
| 109 | struct old_sigaction { | ||
| 110 | __sighandler_t sa_handler; | ||
| 111 | old_sigset_t sa_mask; | ||
| 112 | unsigned long sa_flags; | ||
| 113 | void (*sa_restorer)(void); | ||
| 114 | }; | ||
| 115 | |||
| 116 | struct sigaction { | ||
| 117 | __sighandler_t sa_handler; | ||
| 118 | unsigned long sa_flags; | ||
| 119 | void (*sa_restorer)(void); | ||
| 120 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct k_sigaction { | ||
| 124 | struct sigaction sa; | ||
| 125 | }; | ||
| 126 | #else | ||
| 127 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 128 | |||
| 129 | struct sigaction { | ||
| 130 | union { | ||
| 131 | __sighandler_t _sa_handler; | ||
| 132 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 133 | } _u; | ||
| 134 | sigset_t sa_mask; | ||
| 135 | unsigned long sa_flags; | ||
| 136 | void (*sa_restorer)(void); | ||
| 137 | }; | ||
| 138 | |||
| 139 | #define sa_handler _u._sa_handler | ||
| 140 | #define sa_sigaction _u._sa_sigaction | ||
| 141 | |||
| 142 | #endif /* __KERNEL__ */ | ||
| 143 | |||
| 144 | typedef struct sigaltstack { | ||
| 145 | void *ss_sp; | ||
| 146 | int ss_flags; | ||
| 147 | size_t ss_size; | ||
| 148 | } stack_t; | ||
| 149 | |||
| 150 | #ifdef __KERNEL__ | ||
| 151 | |||
| 152 | #include <asm/sigcontext.h> | ||
| 153 | #undef __HAVE_ARCH_SIG_BITOPS | ||
| 154 | |||
| 155 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
| 156 | |||
| 157 | #endif /* __KERNEL__ */ | ||
| 158 | |||
| 159 | #endif /* _M68KNOMMU_SIGNAL_H */ | ||
diff --git a/arch/m68k/include/asm/smp.h b/arch/m68k/include/asm/smp.h new file mode 100644 index 000000000000..9e9bd7e58922 --- /dev/null +++ b/arch/m68k/include/asm/smp.h | |||
| @@ -0,0 +1 @@ | |||
| /* nothing required here yet */ | |||
diff --git a/arch/m68k/include/asm/socket.h b/arch/m68k/include/asm/socket.h new file mode 100644 index 000000000000..dbc64e92c41a --- /dev/null +++ b/arch/m68k/include/asm/socket.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | #ifndef _ASM_SOCKET_H | ||
| 2 | #define _ASM_SOCKET_H | ||
| 3 | |||
| 4 | #include <asm/sockios.h> | ||
| 5 | |||
| 6 | /* For setsockopt(2) */ | ||
| 7 | #define SOL_SOCKET 1 | ||
| 8 | |||
| 9 | #define SO_DEBUG 1 | ||
| 10 | #define SO_REUSEADDR 2 | ||
| 11 | #define SO_TYPE 3 | ||
| 12 | #define SO_ERROR 4 | ||
| 13 | #define SO_DONTROUTE 5 | ||
| 14 | #define SO_BROADCAST 6 | ||
| 15 | #define SO_SNDBUF 7 | ||
| 16 | #define SO_RCVBUF 8 | ||
| 17 | #define SO_SNDBUFFORCE 32 | ||
| 18 | #define SO_RCVBUFFORCE 33 | ||
| 19 | #define SO_KEEPALIVE 9 | ||
| 20 | #define SO_OOBINLINE 10 | ||
| 21 | #define SO_NO_CHECK 11 | ||
| 22 | #define SO_PRIORITY 12 | ||
| 23 | #define SO_LINGER 13 | ||
| 24 | #define SO_BSDCOMPAT 14 | ||
| 25 | /* To add :#define SO_REUSEPORT 15 */ | ||
| 26 | #define SO_PASSCRED 16 | ||
| 27 | #define SO_PEERCRED 17 | ||
| 28 | #define SO_RCVLOWAT 18 | ||
| 29 | #define SO_SNDLOWAT 19 | ||
| 30 | #define SO_RCVTIMEO 20 | ||
| 31 | #define SO_SNDTIMEO 21 | ||
| 32 | |||
| 33 | /* Security levels - as per NRL IPv6 - don't actually do anything */ | ||
| 34 | #define SO_SECURITY_AUTHENTICATION 22 | ||
| 35 | #define SO_SECURITY_ENCRYPTION_TRANSPORT 23 | ||
| 36 | #define SO_SECURITY_ENCRYPTION_NETWORK 24 | ||
| 37 | |||
| 38 | #define SO_BINDTODEVICE 25 | ||
| 39 | |||
| 40 | /* Socket filtering */ | ||
| 41 | #define SO_ATTACH_FILTER 26 | ||
| 42 | #define SO_DETACH_FILTER 27 | ||
| 43 | |||
| 44 | #define SO_PEERNAME 28 | ||
| 45 | #define SO_TIMESTAMP 29 | ||
| 46 | #define SCM_TIMESTAMP SO_TIMESTAMP | ||
| 47 | |||
| 48 | #define SO_ACCEPTCONN 30 | ||
| 49 | |||
| 50 | #define SO_PEERSEC 31 | ||
| 51 | #define SO_PASSSEC 34 | ||
| 52 | #define SO_TIMESTAMPNS 35 | ||
| 53 | #define SCM_TIMESTAMPNS SO_TIMESTAMPNS | ||
| 54 | |||
| 55 | #define SO_MARK 36 | ||
| 56 | |||
| 57 | #endif /* _ASM_SOCKET_H */ | ||
diff --git a/arch/m68k/include/asm/sockios.h b/arch/m68k/include/asm/sockios.h new file mode 100644 index 000000000000..c04a23943cb7 --- /dev/null +++ b/arch/m68k/include/asm/sockios.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef __ARCH_M68K_SOCKIOS__ | ||
| 2 | #define __ARCH_M68K_SOCKIOS__ | ||
| 3 | |||
| 4 | /* Socket-level I/O control calls. */ | ||
| 5 | #define FIOSETOWN 0x8901 | ||
| 6 | #define SIOCSPGRP 0x8902 | ||
| 7 | #define FIOGETOWN 0x8903 | ||
| 8 | #define SIOCGPGRP 0x8904 | ||
| 9 | #define SIOCATMARK 0x8905 | ||
| 10 | #define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ | ||
| 11 | #define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ | ||
| 12 | |||
| 13 | #endif /* __ARCH_M68K_SOCKIOS__ */ | ||
diff --git a/arch/m68k/include/asm/spinlock.h b/arch/m68k/include/asm/spinlock.h new file mode 100644 index 000000000000..20f46e27b534 --- /dev/null +++ b/arch/m68k/include/asm/spinlock.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef __M68K_SPINLOCK_H | ||
| 2 | #define __M68K_SPINLOCK_H | ||
| 3 | |||
| 4 | #error "m68k doesn't do SMP yet" | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/m68k/include/asm/stat.h b/arch/m68k/include/asm/stat.h new file mode 100644 index 000000000000..dd38bc2e9f98 --- /dev/null +++ b/arch/m68k/include/asm/stat.h | |||
| @@ -0,0 +1,77 @@ | |||
| 1 | #ifndef _M68K_STAT_H | ||
| 2 | #define _M68K_STAT_H | ||
| 3 | |||
| 4 | struct __old_kernel_stat { | ||
| 5 | unsigned short st_dev; | ||
| 6 | unsigned short st_ino; | ||
| 7 | unsigned short st_mode; | ||
| 8 | unsigned short st_nlink; | ||
| 9 | unsigned short st_uid; | ||
| 10 | unsigned short st_gid; | ||
| 11 | unsigned short st_rdev; | ||
| 12 | unsigned long st_size; | ||
| 13 | unsigned long st_atime; | ||
| 14 | unsigned long st_mtime; | ||
| 15 | unsigned long st_ctime; | ||
| 16 | }; | ||
| 17 | |||
| 18 | struct stat { | ||
| 19 | unsigned short st_dev; | ||
| 20 | unsigned short __pad1; | ||
| 21 | unsigned long st_ino; | ||
| 22 | unsigned short st_mode; | ||
| 23 | unsigned short st_nlink; | ||
| 24 | unsigned short st_uid; | ||
| 25 | unsigned short st_gid; | ||
| 26 | unsigned short st_rdev; | ||
| 27 | unsigned short __pad2; | ||
| 28 | unsigned long st_size; | ||
| 29 | unsigned long st_blksize; | ||
| 30 | unsigned long st_blocks; | ||
| 31 | unsigned long st_atime; | ||
| 32 | unsigned long __unused1; | ||
| 33 | unsigned long st_mtime; | ||
| 34 | unsigned long __unused2; | ||
| 35 | unsigned long st_ctime; | ||
| 36 | unsigned long __unused3; | ||
| 37 | unsigned long __unused4; | ||
| 38 | unsigned long __unused5; | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* This matches struct stat64 in glibc2.1, hence the absolutely | ||
| 42 | * insane amounts of padding around dev_t's. | ||
| 43 | */ | ||
| 44 | struct stat64 { | ||
| 45 | unsigned long long st_dev; | ||
| 46 | unsigned char __pad1[2]; | ||
| 47 | |||
| 48 | #define STAT64_HAS_BROKEN_ST_INO 1 | ||
| 49 | unsigned long __st_ino; | ||
| 50 | |||
| 51 | unsigned int st_mode; | ||
| 52 | unsigned int st_nlink; | ||
| 53 | |||
| 54 | unsigned long st_uid; | ||
| 55 | unsigned long st_gid; | ||
| 56 | |||
| 57 | unsigned long long st_rdev; | ||
| 58 | unsigned char __pad3[2]; | ||
| 59 | |||
| 60 | long long st_size; | ||
| 61 | unsigned long st_blksize; | ||
| 62 | |||
| 63 | unsigned long long st_blocks; /* Number 512-byte blocks allocated. */ | ||
| 64 | |||
| 65 | unsigned long st_atime; | ||
| 66 | unsigned long st_atime_nsec; | ||
| 67 | |||
| 68 | unsigned long st_mtime; | ||
| 69 | unsigned long st_mtime_nsec; | ||
| 70 | |||
| 71 | unsigned long st_ctime; | ||
| 72 | unsigned long st_ctime_nsec; | ||
| 73 | |||
| 74 | unsigned long long st_ino; | ||
| 75 | }; | ||
| 76 | |||
| 77 | #endif /* _M68K_STAT_H */ | ||
diff --git a/arch/m68k/include/asm/statfs.h b/arch/m68k/include/asm/statfs.h new file mode 100644 index 000000000000..08d93f14e061 --- /dev/null +++ b/arch/m68k/include/asm/statfs.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68K_STATFS_H | ||
| 2 | #define _M68K_STATFS_H | ||
| 3 | |||
| 4 | #include <asm-generic/statfs.h> | ||
| 5 | |||
| 6 | #endif /* _M68K_STATFS_H */ | ||
diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h new file mode 100644 index 000000000000..2c356f90f171 --- /dev/null +++ b/arch/m68k/include/asm/string.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "string_no.h" | ||
| 3 | #else | ||
| 4 | #include "string_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/string_mm.h b/arch/m68k/include/asm/string_mm.h new file mode 100644 index 000000000000..2eb7df1e0f5d --- /dev/null +++ b/arch/m68k/include/asm/string_mm.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | #ifndef _M68K_STRING_H_ | ||
| 2 | #define _M68K_STRING_H_ | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | #include <linux/compiler.h> | ||
| 6 | |||
| 7 | static inline size_t __kernel_strlen(const char *s) | ||
| 8 | { | ||
| 9 | const char *sc; | ||
| 10 | |||
| 11 | for (sc = s; *sc++; ) | ||
| 12 | ; | ||
| 13 | return sc - s - 1; | ||
| 14 | } | ||
| 15 | |||
| 16 | static inline char *__kernel_strcpy(char *dest, const char *src) | ||
| 17 | { | ||
| 18 | char *xdest = dest; | ||
| 19 | |||
| 20 | asm volatile ("\n" | ||
| 21 | "1: move.b (%1)+,(%0)+\n" | ||
| 22 | " jne 1b" | ||
| 23 | : "+a" (dest), "+a" (src) | ||
| 24 | : : "memory"); | ||
| 25 | return xdest; | ||
| 26 | } | ||
| 27 | |||
| 28 | #ifndef __IN_STRING_C | ||
| 29 | |||
| 30 | #define __HAVE_ARCH_STRLEN | ||
| 31 | #define strlen(s) (__builtin_constant_p(s) ? \ | ||
| 32 | __builtin_strlen(s) : \ | ||
| 33 | __kernel_strlen(s)) | ||
| 34 | |||
| 35 | #define __HAVE_ARCH_STRNLEN | ||
| 36 | static inline size_t strnlen(const char *s, size_t count) | ||
| 37 | { | ||
| 38 | const char *sc = s; | ||
| 39 | |||
| 40 | asm volatile ("\n" | ||
| 41 | "1: subq.l #1,%1\n" | ||
| 42 | " jcs 2f\n" | ||
| 43 | " tst.b (%0)+\n" | ||
| 44 | " jne 1b\n" | ||
| 45 | " subq.l #1,%0\n" | ||
| 46 | "2:" | ||
| 47 | : "+a" (sc), "+d" (count)); | ||
| 48 | return sc - s; | ||
| 49 | } | ||
| 50 | |||
| 51 | #define __HAVE_ARCH_STRCPY | ||
| 52 | #if __GNUC__ >= 4 | ||
| 53 | #define strcpy(d, s) (__builtin_constant_p(s) && \ | ||
| 54 | __builtin_strlen(s) <= 32 ? \ | ||
| 55 | __builtin_strcpy(d, s) : \ | ||
| 56 | __kernel_strcpy(d, s)) | ||
| 57 | #else | ||
| 58 | #define strcpy(d, s) __kernel_strcpy(d, s) | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #define __HAVE_ARCH_STRNCPY | ||
| 62 | static inline char *strncpy(char *dest, const char *src, size_t n) | ||
| 63 | { | ||
| 64 | char *xdest = dest; | ||
| 65 | |||
| 66 | asm volatile ("\n" | ||
| 67 | " jra 2f\n" | ||
| 68 | "1: move.b (%1),(%0)+\n" | ||
| 69 | " jeq 2f\n" | ||
| 70 | " addq.l #1,%1\n" | ||
| 71 | "2: subq.l #1,%2\n" | ||
| 72 | " jcc 1b\n" | ||
| 73 | : "+a" (dest), "+a" (src), "+d" (n) | ||
| 74 | : : "memory"); | ||
| 75 | return xdest; | ||
| 76 | } | ||
| 77 | |||
| 78 | #define __HAVE_ARCH_STRCAT | ||
| 79 | #define strcat(d, s) ({ \ | ||
| 80 | char *__d = (d); \ | ||
| 81 | strcpy(__d + strlen(__d), (s)); \ | ||
| 82 | }) | ||
| 83 | |||
| 84 | #define __HAVE_ARCH_STRCHR | ||
| 85 | static inline char *strchr(const char *s, int c) | ||
| 86 | { | ||
| 87 | char sc, ch = c; | ||
| 88 | |||
| 89 | for (; (sc = *s++) != ch; ) { | ||
| 90 | if (!sc) | ||
| 91 | return NULL; | ||
| 92 | } | ||
| 93 | return (char *)s - 1; | ||
| 94 | } | ||
| 95 | |||
| 96 | #define __HAVE_ARCH_STRCMP | ||
| 97 | static inline int strcmp(const char *cs, const char *ct) | ||
| 98 | { | ||
| 99 | char res; | ||
| 100 | |||
| 101 | asm ("\n" | ||
| 102 | "1: move.b (%0)+,%2\n" /* get *cs */ | ||
| 103 | " cmp.b (%1)+,%2\n" /* compare a byte */ | ||
| 104 | " jne 2f\n" /* not equal, break out */ | ||
| 105 | " tst.b %2\n" /* at end of cs? */ | ||
| 106 | " jne 1b\n" /* no, keep going */ | ||
| 107 | " jra 3f\n" /* strings are equal */ | ||
| 108 | "2: sub.b -(%1),%2\n" /* *cs - *ct */ | ||
| 109 | "3:" | ||
| 110 | : "+a" (cs), "+a" (ct), "=d" (res)); | ||
| 111 | return res; | ||
| 112 | } | ||
| 113 | |||
| 114 | #define __HAVE_ARCH_MEMSET | ||
| 115 | extern void *memset(void *, int, __kernel_size_t); | ||
| 116 | #define memset(d, c, n) __builtin_memset(d, c, n) | ||
| 117 | |||
| 118 | #define __HAVE_ARCH_MEMCPY | ||
| 119 | extern void *memcpy(void *, const void *, __kernel_size_t); | ||
| 120 | #define memcpy(d, s, n) __builtin_memcpy(d, s, n) | ||
| 121 | |||
| 122 | #define __HAVE_ARCH_MEMMOVE | ||
| 123 | extern void *memmove(void *, const void *, __kernel_size_t); | ||
| 124 | |||
| 125 | #define __HAVE_ARCH_MEMCMP | ||
| 126 | extern int memcmp(const void *, const void *, __kernel_size_t); | ||
| 127 | #define memcmp(d, s, n) __builtin_memcmp(d, s, n) | ||
| 128 | |||
| 129 | #endif | ||
| 130 | |||
| 131 | #endif /* _M68K_STRING_H_ */ | ||
diff --git a/arch/m68k/include/asm/string_no.h b/arch/m68k/include/asm/string_no.h new file mode 100644 index 000000000000..af09e17000fc --- /dev/null +++ b/arch/m68k/include/asm/string_no.h | |||
| @@ -0,0 +1,126 @@ | |||
| 1 | #ifndef _M68KNOMMU_STRING_H_ | ||
| 2 | #define _M68KNOMMU_STRING_H_ | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ /* only set these up for kernel code */ | ||
| 5 | |||
| 6 | #include <asm/setup.h> | ||
| 7 | #include <asm/page.h> | ||
| 8 | |||
| 9 | #define __HAVE_ARCH_STRCPY | ||
| 10 | static inline char * strcpy(char * dest,const char *src) | ||
| 11 | { | ||
| 12 | char *xdest = dest; | ||
| 13 | |||
| 14 | __asm__ __volatile__ | ||
| 15 | ("1:\tmoveb %1@+,%0@+\n\t" | ||
| 16 | "jne 1b" | ||
| 17 | : "=a" (dest), "=a" (src) | ||
| 18 | : "0" (dest), "1" (src) : "memory"); | ||
| 19 | return xdest; | ||
| 20 | } | ||
| 21 | |||
| 22 | #define __HAVE_ARCH_STRNCPY | ||
| 23 | static inline char * strncpy(char *dest, const char *src, size_t n) | ||
| 24 | { | ||
| 25 | char *xdest = dest; | ||
| 26 | |||
| 27 | if (n == 0) | ||
| 28 | return xdest; | ||
| 29 | |||
| 30 | __asm__ __volatile__ | ||
| 31 | ("1:\tmoveb %1@+,%0@+\n\t" | ||
| 32 | "jeq 2f\n\t" | ||
| 33 | "subql #1,%2\n\t" | ||
| 34 | "jne 1b\n\t" | ||
| 35 | "2:" | ||
| 36 | : "=a" (dest), "=a" (src), "=d" (n) | ||
| 37 | : "0" (dest), "1" (src), "2" (n) | ||
| 38 | : "memory"); | ||
| 39 | return xdest; | ||
| 40 | } | ||
| 41 | |||
| 42 | |||
| 43 | #ifndef CONFIG_COLDFIRE | ||
| 44 | |||
| 45 | #define __HAVE_ARCH_STRCMP | ||
| 46 | static inline int strcmp(const char * cs,const char * ct) | ||
| 47 | { | ||
| 48 | char __res; | ||
| 49 | |||
| 50 | __asm__ | ||
| 51 | ("1:\tmoveb %0@+,%2\n\t" /* get *cs */ | ||
| 52 | "cmpb %1@+,%2\n\t" /* compare a byte */ | ||
| 53 | "jne 2f\n\t" /* not equal, break out */ | ||
| 54 | "tstb %2\n\t" /* at end of cs? */ | ||
| 55 | "jne 1b\n\t" /* no, keep going */ | ||
| 56 | "jra 3f\n\t" /* strings are equal */ | ||
| 57 | "2:\tsubb %1@-,%2\n\t" /* *cs - *ct */ | ||
| 58 | "3:" | ||
| 59 | : "=a" (cs), "=a" (ct), "=d" (__res) | ||
| 60 | : "0" (cs), "1" (ct)); | ||
| 61 | |||
| 62 | return __res; | ||
| 63 | } | ||
| 64 | |||
| 65 | #define __HAVE_ARCH_STRNCMP | ||
| 66 | static inline int strncmp(const char * cs,const char * ct,size_t count) | ||
| 67 | { | ||
| 68 | char __res; | ||
| 69 | |||
| 70 | if (!count) | ||
| 71 | return 0; | ||
| 72 | __asm__ | ||
| 73 | ("1:\tmovb %0@+,%3\n\t" /* get *cs */ | ||
| 74 | "cmpb %1@+,%3\n\t" /* compare a byte */ | ||
| 75 | "jne 3f\n\t" /* not equal, break out */ | ||
| 76 | "tstb %3\n\t" /* at end of cs? */ | ||
| 77 | "jeq 4f\n\t" /* yes, all done */ | ||
| 78 | "subql #1,%2\n\t" /* no, adjust count */ | ||
| 79 | "jne 1b\n\t" /* more to do, keep going */ | ||
| 80 | "2:\tmoveq #0,%3\n\t" /* strings are equal */ | ||
| 81 | "jra 4f\n\t" | ||
| 82 | "3:\tsubb %1@-,%3\n\t" /* *cs - *ct */ | ||
| 83 | "4:" | ||
| 84 | : "=a" (cs), "=a" (ct), "=d" (count), "=d" (__res) | ||
| 85 | : "0" (cs), "1" (ct), "2" (count)); | ||
| 86 | return __res; | ||
| 87 | } | ||
| 88 | |||
| 89 | #endif /* CONFIG_COLDFIRE */ | ||
| 90 | |||
| 91 | #define __HAVE_ARCH_MEMSET | ||
| 92 | extern void * memset(void * s, int c, size_t count); | ||
| 93 | |||
| 94 | #define __HAVE_ARCH_MEMCPY | ||
| 95 | extern void * memcpy(void *d, const void *s, size_t count); | ||
| 96 | |||
| 97 | #else /* KERNEL */ | ||
| 98 | |||
| 99 | /* | ||
| 100 | * let user libraries deal with these, | ||
| 101 | * IMHO the kernel has no place defining these functions for user apps | ||
| 102 | */ | ||
| 103 | |||
| 104 | #define __HAVE_ARCH_STRCPY 1 | ||
| 105 | #define __HAVE_ARCH_STRNCPY 1 | ||
| 106 | #define __HAVE_ARCH_STRCAT 1 | ||
| 107 | #define __HAVE_ARCH_STRNCAT 1 | ||
| 108 | #define __HAVE_ARCH_STRCMP 1 | ||
| 109 | #define __HAVE_ARCH_STRNCMP 1 | ||
| 110 | #define __HAVE_ARCH_STRNICMP 1 | ||
| 111 | #define __HAVE_ARCH_STRCHR 1 | ||
| 112 | #define __HAVE_ARCH_STRRCHR 1 | ||
| 113 | #define __HAVE_ARCH_STRSTR 1 | ||
| 114 | #define __HAVE_ARCH_STRLEN 1 | ||
| 115 | #define __HAVE_ARCH_STRNLEN 1 | ||
| 116 | #define __HAVE_ARCH_MEMSET 1 | ||
| 117 | #define __HAVE_ARCH_MEMCPY 1 | ||
| 118 | #define __HAVE_ARCH_MEMMOVE 1 | ||
| 119 | #define __HAVE_ARCH_MEMSCAN 1 | ||
| 120 | #define __HAVE_ARCH_MEMCMP 1 | ||
| 121 | #define __HAVE_ARCH_MEMCHR 1 | ||
| 122 | #define __HAVE_ARCH_STRTOK 1 | ||
| 123 | |||
| 124 | #endif /* KERNEL */ | ||
| 125 | |||
| 126 | #endif /* _M68K_STRING_H_ */ | ||
diff --git a/arch/m68k/include/asm/sun3-head.h b/arch/m68k/include/asm/sun3-head.h new file mode 100644 index 000000000000..05af2f18b3bd --- /dev/null +++ b/arch/m68k/include/asm/sun3-head.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | #ifndef __SUN3_HEAD_H | ||
| 2 | #define __SUN3_HEAD_H | ||
| 3 | |||
| 4 | #define KERNBASE 0xE000000 /* First address the kernel will eventually be */ | ||
| 5 | #define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */ | ||
| 6 | #define FC_CONTROL 3 | ||
| 7 | #define FC_SUPERD 5 | ||
| 8 | #define FC_CPU 7 | ||
| 9 | |||
| 10 | #endif /* __SUN3_HEAD_H */ | ||
diff --git a/arch/m68k/include/asm/sun3_pgalloc.h b/arch/m68k/include/asm/sun3_pgalloc.h new file mode 100644 index 000000000000..d4c83f143816 --- /dev/null +++ b/arch/m68k/include/asm/sun3_pgalloc.h | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | /* sun3_pgalloc.h -- | ||
| 2 | * reorganization around 2.3.39, routines moved from sun3_pgtable.h | ||
| 3 | * | ||
| 4 | * | ||
| 5 | * 02/27/2002 -- Modified to support "highpte" implementation in 2.5.5 (Sam) | ||
| 6 | * | ||
| 7 | * moved 1/26/2000 Sam Creasey | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _SUN3_PGALLOC_H | ||
| 11 | #define _SUN3_PGALLOC_H | ||
| 12 | |||
| 13 | #include <asm/tlb.h> | ||
| 14 | |||
| 15 | /* FIXME - when we get this compiling */ | ||
| 16 | /* erm, now that it's compiling, what do we do with it? */ | ||
| 17 | #define _KERNPG_TABLE 0 | ||
| 18 | |||
| 19 | extern const char bad_pmd_string[]; | ||
| 20 | |||
| 21 | #define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); }) | ||
| 22 | |||
| 23 | |||
| 24 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | ||
| 25 | { | ||
| 26 | free_page((unsigned long) pte); | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline void pte_free(struct mm_struct *mm, pgtable_t page) | ||
| 30 | { | ||
| 31 | pgtable_page_dtor(page); | ||
| 32 | __free_page(page); | ||
| 33 | } | ||
| 34 | |||
| 35 | #define __pte_free_tlb(tlb,pte) \ | ||
| 36 | do { \ | ||
| 37 | pgtable_page_dtor(pte); \ | ||
| 38 | tlb_remove_page((tlb), pte); \ | ||
| 39 | } while (0) | ||
| 40 | |||
| 41 | static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, | ||
| 42 | unsigned long address) | ||
| 43 | { | ||
| 44 | unsigned long page = __get_free_page(GFP_KERNEL|__GFP_REPEAT); | ||
| 45 | |||
| 46 | if (!page) | ||
| 47 | return NULL; | ||
| 48 | |||
| 49 | memset((void *)page, 0, PAGE_SIZE); | ||
| 50 | return (pte_t *) (page); | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline pgtable_t pte_alloc_one(struct mm_struct *mm, | ||
| 54 | unsigned long address) | ||
| 55 | { | ||
| 56 | struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0); | ||
| 57 | |||
| 58 | if (page == NULL) | ||
| 59 | return NULL; | ||
| 60 | |||
| 61 | clear_highpage(page); | ||
| 62 | pgtable_page_ctor(page); | ||
| 63 | return page; | ||
| 64 | |||
| 65 | } | ||
| 66 | |||
| 67 | static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) | ||
| 68 | { | ||
| 69 | pmd_val(*pmd) = __pa((unsigned long)pte); | ||
| 70 | } | ||
| 71 | |||
| 72 | static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page) | ||
| 73 | { | ||
| 74 | pmd_val(*pmd) = __pa((unsigned long)page_address(page)); | ||
| 75 | } | ||
| 76 | #define pmd_pgtable(pmd) pmd_page(pmd) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * allocating and freeing a pmd is trivial: the 1-entry pmd is | ||
| 80 | * inside the pgd, so has no extra memory associated with it. | ||
| 81 | */ | ||
| 82 | #define pmd_free(mm, x) do { } while (0) | ||
| 83 | #define __pmd_free_tlb(tlb, x) do { } while (0) | ||
| 84 | |||
| 85 | static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) | ||
| 86 | { | ||
| 87 | free_page((unsigned long) pgd); | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline pgd_t * pgd_alloc(struct mm_struct *mm) | ||
| 91 | { | ||
| 92 | pgd_t *new_pgd; | ||
| 93 | |||
| 94 | new_pgd = (pgd_t *)get_zeroed_page(GFP_KERNEL); | ||
| 95 | memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE); | ||
| 96 | memset(new_pgd, 0, (PAGE_OFFSET >> PGDIR_SHIFT)); | ||
| 97 | return new_pgd; | ||
| 98 | } | ||
| 99 | |||
| 100 | #define pgd_populate(mm, pmd, pte) BUG() | ||
| 101 | |||
| 102 | #endif /* SUN3_PGALLOC_H */ | ||
diff --git a/arch/m68k/include/asm/sun3_pgtable.h b/arch/m68k/include/asm/sun3_pgtable.h new file mode 100644 index 000000000000..f847ec732d62 --- /dev/null +++ b/arch/m68k/include/asm/sun3_pgtable.h | |||
| @@ -0,0 +1,234 @@ | |||
| 1 | #ifndef _SUN3_PGTABLE_H | ||
| 2 | #define _SUN3_PGTABLE_H | ||
| 3 | |||
| 4 | #include <asm/sun3mmu.h> | ||
| 5 | |||
| 6 | #ifndef __ASSEMBLY__ | ||
| 7 | #include <asm/virtconvert.h> | ||
| 8 | #include <linux/linkage.h> | ||
| 9 | |||
| 10 | /* | ||
| 11 | * This file contains all the things which change drastically for the sun3 | ||
| 12 | * pagetable stuff, to avoid making too much of a mess of the generic m68k | ||
| 13 | * `pgtable.h'; this should only be included from the generic file. --m | ||
| 14 | */ | ||
| 15 | |||
| 16 | /* For virtual address to physical address conversion */ | ||
| 17 | #define VTOP(addr) __pa(addr) | ||
| 18 | #define PTOV(addr) __va(addr) | ||
| 19 | |||
| 20 | |||
| 21 | #endif /* !__ASSEMBLY__ */ | ||
| 22 | |||
| 23 | /* These need to be defined for compatibility although the sun3 doesn't use them */ | ||
| 24 | #define _PAGE_NOCACHE030 0x040 | ||
| 25 | #define _CACHEMASK040 (~0x060) | ||
| 26 | #define _PAGE_NOCACHE_S 0x040 | ||
| 27 | |||
| 28 | /* Page protection values within PTE. */ | ||
| 29 | #define SUN3_PAGE_VALID (0x80000000) | ||
| 30 | #define SUN3_PAGE_WRITEABLE (0x40000000) | ||
| 31 | #define SUN3_PAGE_SYSTEM (0x20000000) | ||
| 32 | #define SUN3_PAGE_NOCACHE (0x10000000) | ||
| 33 | #define SUN3_PAGE_ACCESSED (0x02000000) | ||
| 34 | #define SUN3_PAGE_MODIFIED (0x01000000) | ||
| 35 | |||
| 36 | |||
| 37 | /* Externally used page protection values. */ | ||
| 38 | #define _PAGE_PRESENT (SUN3_PAGE_VALID) | ||
| 39 | #define _PAGE_ACCESSED (SUN3_PAGE_ACCESSED) | ||
| 40 | |||
| 41 | #define PTE_FILE_MAX_BITS 28 | ||
| 42 | |||
| 43 | /* Compound page protection values. */ | ||
| 44 | //todo: work out which ones *should* have SUN3_PAGE_NOCACHE and fix... | ||
| 45 | // is it just PAGE_KERNEL and PAGE_SHARED? | ||
| 46 | #define PAGE_NONE __pgprot(SUN3_PAGE_VALID \ | ||
| 47 | | SUN3_PAGE_ACCESSED \ | ||
| 48 | | SUN3_PAGE_NOCACHE) | ||
| 49 | #define PAGE_SHARED __pgprot(SUN3_PAGE_VALID \ | ||
| 50 | | SUN3_PAGE_WRITEABLE \ | ||
| 51 | | SUN3_PAGE_ACCESSED \ | ||
| 52 | | SUN3_PAGE_NOCACHE) | ||
| 53 | #define PAGE_COPY __pgprot(SUN3_PAGE_VALID \ | ||
| 54 | | SUN3_PAGE_ACCESSED \ | ||
| 55 | | SUN3_PAGE_NOCACHE) | ||
| 56 | #define PAGE_READONLY __pgprot(SUN3_PAGE_VALID \ | ||
| 57 | | SUN3_PAGE_ACCESSED \ | ||
| 58 | | SUN3_PAGE_NOCACHE) | ||
| 59 | #define PAGE_KERNEL __pgprot(SUN3_PAGE_VALID \ | ||
| 60 | | SUN3_PAGE_WRITEABLE \ | ||
| 61 | | SUN3_PAGE_SYSTEM \ | ||
| 62 | | SUN3_PAGE_NOCACHE \ | ||
| 63 | | SUN3_PAGE_ACCESSED \ | ||
| 64 | | SUN3_PAGE_MODIFIED) | ||
| 65 | #define PAGE_INIT __pgprot(SUN3_PAGE_VALID \ | ||
| 66 | | SUN3_PAGE_WRITEABLE \ | ||
| 67 | | SUN3_PAGE_SYSTEM \ | ||
| 68 | | SUN3_PAGE_NOCACHE) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Page protections for initialising protection_map. The sun3 has only two | ||
| 72 | * protection settings, valid (implying read and execute) and writeable. These | ||
| 73 | * are as close as we can get... | ||
| 74 | */ | ||
| 75 | #define __P000 PAGE_NONE | ||
| 76 | #define __P001 PAGE_READONLY | ||
| 77 | #define __P010 PAGE_COPY | ||
| 78 | #define __P011 PAGE_COPY | ||
| 79 | #define __P100 PAGE_READONLY | ||
| 80 | #define __P101 PAGE_READONLY | ||
| 81 | #define __P110 PAGE_COPY | ||
| 82 | #define __P111 PAGE_COPY | ||
| 83 | |||
| 84 | #define __S000 PAGE_NONE | ||
| 85 | #define __S001 PAGE_READONLY | ||
| 86 | #define __S010 PAGE_SHARED | ||
| 87 | #define __S011 PAGE_SHARED | ||
| 88 | #define __S100 PAGE_READONLY | ||
| 89 | #define __S101 PAGE_READONLY | ||
| 90 | #define __S110 PAGE_SHARED | ||
| 91 | #define __S111 PAGE_SHARED | ||
| 92 | |||
| 93 | /* Use these fake page-protections on PMDs. */ | ||
| 94 | #define SUN3_PMD_VALID (0x00000001) | ||
| 95 | #define SUN3_PMD_MASK (0x0000003F) | ||
| 96 | #define SUN3_PMD_MAGIC (0x0000002B) | ||
| 97 | |||
| 98 | #ifndef __ASSEMBLY__ | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Conversion functions: convert a page and protection to a page entry, | ||
| 102 | * and a page entry and page directory to the page they refer to. | ||
| 103 | */ | ||
| 104 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | ||
| 105 | |||
| 106 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | ||
| 107 | { | ||
| 108 | pte_val(pte) = (pte_val(pte) & SUN3_PAGE_CHG_MASK) | pgprot_val(newprot); | ||
| 109 | return pte; | ||
| 110 | } | ||
| 111 | |||
| 112 | #define pmd_set(pmdp,ptep) do {} while (0) | ||
| 113 | |||
| 114 | static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp) | ||
| 115 | { | ||
| 116 | pgd_val(*pgdp) = virt_to_phys(pmdp); | ||
| 117 | } | ||
| 118 | |||
| 119 | #define __pte_page(pte) \ | ||
| 120 | ((unsigned long) __va ((pte_val (pte) & SUN3_PAGE_PGNUM_MASK) << PAGE_SHIFT)) | ||
| 121 | #define __pmd_page(pmd) \ | ||
| 122 | ((unsigned long) __va (pmd_val (pmd) & PAGE_MASK)) | ||
| 123 | |||
| 124 | static inline int pte_none (pte_t pte) { return !pte_val (pte); } | ||
| 125 | static inline int pte_present (pte_t pte) { return pte_val (pte) & SUN3_PAGE_VALID; } | ||
| 126 | static inline void pte_clear (struct mm_struct *mm, unsigned long addr, pte_t *ptep) | ||
| 127 | { | ||
| 128 | pte_val (*ptep) = 0; | ||
| 129 | } | ||
| 130 | |||
| 131 | #define pte_pfn(pte) (pte_val(pte) & SUN3_PAGE_PGNUM_MASK) | ||
| 132 | #define pfn_pte(pfn, pgprot) \ | ||
| 133 | ({ pte_t __pte; pte_val(__pte) = pfn | pgprot_val(pgprot); __pte; }) | ||
| 134 | |||
| 135 | #define pte_page(pte) virt_to_page(__pte_page(pte)) | ||
| 136 | #define pmd_page(pmd) virt_to_page(__pmd_page(pmd)) | ||
| 137 | |||
| 138 | |||
| 139 | static inline int pmd_none2 (pmd_t *pmd) { return !pmd_val (*pmd); } | ||
| 140 | #define pmd_none(pmd) pmd_none2(&(pmd)) | ||
| 141 | //static inline int pmd_bad (pmd_t pmd) { return (pmd_val (pmd) & SUN3_PMD_MASK) != SUN3_PMD_MAGIC; } | ||
| 142 | static inline int pmd_bad2 (pmd_t *pmd) { return 0; } | ||
| 143 | #define pmd_bad(pmd) pmd_bad2(&(pmd)) | ||
| 144 | static inline int pmd_present2 (pmd_t *pmd) { return pmd_val (*pmd) & SUN3_PMD_VALID; } | ||
| 145 | /* #define pmd_present(pmd) pmd_present2(&(pmd)) */ | ||
| 146 | #define pmd_present(pmd) (!pmd_none2(&(pmd))) | ||
| 147 | static inline void pmd_clear (pmd_t *pmdp) { pmd_val (*pmdp) = 0; } | ||
| 148 | |||
| 149 | static inline int pgd_none (pgd_t pgd) { return 0; } | ||
| 150 | static inline int pgd_bad (pgd_t pgd) { return 0; } | ||
| 151 | static inline int pgd_present (pgd_t pgd) { return 1; } | ||
| 152 | static inline void pgd_clear (pgd_t *pgdp) {} | ||
| 153 | |||
| 154 | |||
| 155 | #define pte_ERROR(e) \ | ||
| 156 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | ||
| 157 | #define pmd_ERROR(e) \ | ||
| 158 | printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | ||
| 159 | #define pgd_ERROR(e) \ | ||
| 160 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | ||
| 161 | |||
| 162 | |||
| 163 | /* | ||
| 164 | * The following only work if pte_present() is true. | ||
| 165 | * Undefined behaviour if not... | ||
| 166 | * [we have the full set here even if they don't change from m68k] | ||
| 167 | */ | ||
| 168 | static inline int pte_write(pte_t pte) { return pte_val(pte) & SUN3_PAGE_WRITEABLE; } | ||
| 169 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & SUN3_PAGE_MODIFIED; } | ||
| 170 | static inline int pte_young(pte_t pte) { return pte_val(pte) & SUN3_PAGE_ACCESSED; } | ||
| 171 | static inline int pte_file(pte_t pte) { return pte_val(pte) & SUN3_PAGE_ACCESSED; } | ||
| 172 | static inline int pte_special(pte_t pte) { return 0; } | ||
| 173 | |||
| 174 | static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_WRITEABLE; return pte; } | ||
| 175 | static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_MODIFIED; return pte; } | ||
| 176 | static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_ACCESSED; return pte; } | ||
| 177 | static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= SUN3_PAGE_WRITEABLE; return pte; } | ||
| 178 | static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= SUN3_PAGE_MODIFIED; return pte; } | ||
| 179 | static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= SUN3_PAGE_ACCESSED; return pte; } | ||
| 180 | static inline pte_t pte_mknocache(pte_t pte) { pte_val(pte) |= SUN3_PAGE_NOCACHE; return pte; } | ||
| 181 | // use this version when caches work... | ||
| 182 | //static inline pte_t pte_mkcache(pte_t pte) { pte_val(pte) &= SUN3_PAGE_NOCACHE; return pte; } | ||
| 183 | // until then, use: | ||
| 184 | static inline pte_t pte_mkcache(pte_t pte) { return pte; } | ||
| 185 | static inline pte_t pte_mkspecial(pte_t pte) { return pte; } | ||
| 186 | |||
| 187 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | ||
| 188 | extern pgd_t kernel_pg_dir[PTRS_PER_PGD]; | ||
| 189 | |||
| 190 | /* Find an entry in a pagetable directory. */ | ||
| 191 | #define pgd_index(address) ((address) >> PGDIR_SHIFT) | ||
| 192 | |||
| 193 | #define pgd_offset(mm, address) \ | ||
| 194 | ((mm)->pgd + pgd_index(address)) | ||
| 195 | |||
| 196 | /* Find an entry in a kernel pagetable directory. */ | ||
| 197 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | ||
| 198 | |||
| 199 | /* Find an entry in the second-level pagetable. */ | ||
| 200 | static inline pmd_t *pmd_offset (pgd_t *pgd, unsigned long address) | ||
| 201 | { | ||
| 202 | return (pmd_t *) pgd; | ||
| 203 | } | ||
| 204 | |||
| 205 | static inline unsigned long pte_to_pgoff(pte_t pte) | ||
| 206 | { | ||
| 207 | return pte.pte & SUN3_PAGE_PGNUM_MASK; | ||
| 208 | } | ||
| 209 | |||
| 210 | static inline pte_t pgoff_to_pte(unsigned off) | ||
| 211 | { | ||
| 212 | pte_t pte = { off + SUN3_PAGE_ACCESSED }; | ||
| 213 | return pte; | ||
| 214 | } | ||
| 215 | |||
| 216 | |||
| 217 | /* Find an entry in the third-level pagetable. */ | ||
| 218 | #define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | ||
| 219 | #define pte_offset_kernel(pmd, address) ((pte_t *) __pmd_page(*pmd) + pte_index(address)) | ||
| 220 | /* FIXME: should we bother with kmap() here? */ | ||
| 221 | #define pte_offset_map(pmd, address) ((pte_t *)kmap(pmd_page(*pmd)) + pte_index(address)) | ||
| 222 | #define pte_offset_map_nested(pmd, address) pte_offset_map(pmd, address) | ||
| 223 | #define pte_unmap(pte) kunmap(pte) | ||
| 224 | #define pte_unmap_nested(pte) kunmap(pte) | ||
| 225 | |||
| 226 | /* Macros to (de)construct the fake PTEs representing swap pages. */ | ||
| 227 | #define __swp_type(x) ((x).val & 0x7F) | ||
| 228 | #define __swp_offset(x) (((x).val) >> 7) | ||
| 229 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) | ((offset) << 7)) }) | ||
| 230 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | ||
| 231 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | ||
| 232 | |||
| 233 | #endif /* !__ASSEMBLY__ */ | ||
| 234 | #endif /* !_SUN3_PGTABLE_H */ | ||
diff --git a/arch/m68k/include/asm/sun3ints.h b/arch/m68k/include/asm/sun3ints.h new file mode 100644 index 000000000000..309d6e6a1374 --- /dev/null +++ b/arch/m68k/include/asm/sun3ints.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * sun3ints.h -- Linux/Sun3 interrupt handling code definitions | ||
| 3 | * | ||
| 4 | * Erik Verbruggen (erik@bigmama.xtdnet.nl) | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef SUN3INTS_H | ||
| 12 | #define SUN3INTS_H | ||
| 13 | |||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <asm/intersil.h> | ||
| 17 | #include <asm/oplib.h> | ||
| 18 | #include <asm/traps.h> | ||
| 19 | #include <asm/irq.h> | ||
| 20 | |||
| 21 | #define SUN3_INT_VECS 192 | ||
| 22 | |||
| 23 | void sun3_enable_irq(unsigned int irq); | ||
| 24 | void sun3_disable_irq(unsigned int irq); | ||
| 25 | extern void sun3_init_IRQ (void); | ||
| 26 | extern void sun3_enable_interrupts (void); | ||
| 27 | extern void sun3_disable_interrupts (void); | ||
| 28 | extern volatile unsigned char* sun3_intreg; | ||
| 29 | |||
| 30 | /* master list of VME vectors -- don't fuck with this */ | ||
| 31 | #define SUN3_VEC_FLOPPY (IRQ_USER+0) | ||
| 32 | #define SUN3_VEC_VMESCSI0 (IRQ_USER+0) | ||
| 33 | #define SUN3_VEC_VMESCSI1 (IRQ_USER+1) | ||
| 34 | #define SUN3_VEC_CG (IRQ_USER+104) | ||
| 35 | |||
| 36 | |||
| 37 | #endif /* SUN3INTS_H */ | ||
diff --git a/arch/m68k/include/asm/sun3mmu.h b/arch/m68k/include/asm/sun3mmu.h new file mode 100644 index 000000000000..d8f17a0d8c9f --- /dev/null +++ b/arch/m68k/include/asm/sun3mmu.h | |||
| @@ -0,0 +1,171 @@ | |||
| 1 | /* | ||
| 2 | * Definitions for Sun3 custom MMU. | ||
| 3 | */ | ||
| 4 | #ifndef __SUN3_MMU_H__ | ||
| 5 | #define __SUN3_MMU_H__ | ||
| 6 | |||
| 7 | #include <linux/types.h> | ||
| 8 | #include <asm/movs.h> | ||
| 9 | #include <asm/sun3-head.h> | ||
| 10 | |||
| 11 | /* MMU characteristics. */ | ||
| 12 | #define SUN3_SEGMAPS_PER_CONTEXT 2048 | ||
| 13 | #define SUN3_PMEGS_NUM 256 | ||
| 14 | #define SUN3_CONTEXTS_NUM 8 | ||
| 15 | |||
| 16 | #define SUN3_PMEG_SIZE_BITS 17 | ||
| 17 | #define SUN3_PMEG_SIZE (1 << SUN3_PMEG_SIZE_BITS) | ||
| 18 | #define SUN3_PMEG_MASK (SUN3_PMEG_SIZE - 1) | ||
| 19 | |||
| 20 | #define SUN3_PTE_SIZE_BITS 13 | ||
| 21 | #define SUN3_PTE_SIZE (1 << SUN3_PTE_SIZE_BITS) | ||
| 22 | #define SUN3_PTE_MASK (SUN3_PTE_SIZE - 1) | ||
| 23 | |||
| 24 | #define SUN3_CONTROL_MASK (0x0FFFFFFC) | ||
| 25 | #define SUN3_INVALID_PMEG 255 | ||
| 26 | #define SUN3_INVALID_CONTEXT 255 | ||
| 27 | |||
| 28 | #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */ | ||
| 29 | #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */ | ||
| 30 | #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */ | ||
| 31 | #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */ | ||
| 32 | #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/ | ||
| 33 | #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */ | ||
| 34 | #define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */ | ||
| 35 | #define AC_SYNC_ERR 0x60000000 /* c fault type */ | ||
| 36 | #define AC_SYNC_VA 0x60000004 /* c fault virtual address */ | ||
| 37 | #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */ | ||
| 38 | #define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */ | ||
| 39 | #define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */ | ||
| 40 | #define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */ | ||
| 41 | #define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */ | ||
| 42 | #define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */ | ||
| 43 | #define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */ | ||
| 44 | #define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/ | ||
| 45 | |||
| 46 | #define SUN3_PAGE_CHG_MASK (SUN3_PAGE_PGNUM_MASK \ | ||
| 47 | | SUN3_PAGE_ACCESSED | SUN3_PAGE_MODIFIED) | ||
| 48 | |||
| 49 | /* Bus access type within PTE. */ | ||
| 50 | #define SUN3_PAGE_TYPE_MASK (0x0c000000) | ||
| 51 | #define SUN3_PAGE_TYPE_MEMORY (0x00000000) | ||
| 52 | #define SUN3_PAGE_TYPE_IO (0x04000000) | ||
| 53 | #define SUN3_PAGE_TYPE_VME16 (0x08000000) | ||
| 54 | #define SUN3_PAGE_TYPE_VME32 (0x0c000000) | ||
| 55 | |||
| 56 | /* Mask for page number within PTE. */ | ||
| 57 | #define SUN3_PAGE_PGNUM_MASK (0x0007FFFF) | ||
| 58 | |||
| 59 | /* Bits within bus-error register. */ | ||
| 60 | #define SUN3_BUSERR_WATCHDOG (0x01) | ||
| 61 | #define SUN3_BUSERR_unused (0x02) | ||
| 62 | #define SUN3_BUSERR_FPAENERR (0x04) | ||
| 63 | #define SUN3_BUSERR_FPABERR (0x08) | ||
| 64 | #define SUN3_BUSERR_VMEBERR (0x10) | ||
| 65 | #define SUN3_BUSERR_TIMEOUT (0x20) | ||
| 66 | #define SUN3_BUSERR_PROTERR (0x40) | ||
| 67 | #define SUN3_BUSERR_INVALID (0x80) | ||
| 68 | |||
| 69 | #ifndef __ASSEMBLY__ | ||
| 70 | |||
| 71 | /* Read bus error status register (implicitly clearing it). */ | ||
| 72 | static inline unsigned char sun3_get_buserr(void) | ||
| 73 | { | ||
| 74 | unsigned char sfc, c; | ||
| 75 | |||
| 76 | GET_SFC (sfc); | ||
| 77 | SET_SFC (FC_CONTROL); | ||
| 78 | GET_CONTROL_BYTE (AC_BUS_ERROR, c); | ||
| 79 | SET_SFC (sfc); | ||
| 80 | |||
| 81 | return c; | ||
| 82 | } | ||
| 83 | |||
| 84 | /* Read segmap from hardware MMU. */ | ||
| 85 | static inline unsigned long sun3_get_segmap(unsigned long addr) | ||
| 86 | { | ||
| 87 | register unsigned long entry; | ||
| 88 | unsigned char c, sfc; | ||
| 89 | |||
| 90 | GET_SFC (sfc); | ||
| 91 | SET_SFC (FC_CONTROL); | ||
| 92 | GET_CONTROL_BYTE (AC_SEGMAP | (addr & SUN3_CONTROL_MASK), c); | ||
| 93 | SET_SFC (sfc); | ||
| 94 | entry = c; | ||
| 95 | |||
| 96 | return entry; | ||
| 97 | } | ||
| 98 | |||
| 99 | /* Write segmap to hardware MMU. */ | ||
| 100 | static inline void sun3_put_segmap(unsigned long addr, unsigned long entry) | ||
| 101 | { | ||
| 102 | unsigned char sfc; | ||
| 103 | |||
| 104 | GET_DFC (sfc); | ||
| 105 | SET_DFC (FC_CONTROL); | ||
| 106 | SET_CONTROL_BYTE (AC_SEGMAP | (addr & SUN3_CONTROL_MASK), entry); | ||
| 107 | SET_DFC (sfc); | ||
| 108 | |||
| 109 | return; | ||
| 110 | } | ||
| 111 | |||
| 112 | /* Read PTE from hardware MMU. */ | ||
| 113 | static inline unsigned long sun3_get_pte(unsigned long addr) | ||
| 114 | { | ||
| 115 | register unsigned long entry; | ||
| 116 | unsigned char sfc; | ||
| 117 | |||
| 118 | GET_SFC (sfc); | ||
| 119 | SET_SFC (FC_CONTROL); | ||
| 120 | GET_CONTROL_WORD (AC_PAGEMAP | (addr & SUN3_CONTROL_MASK), entry); | ||
| 121 | SET_SFC (sfc); | ||
| 122 | |||
| 123 | return entry; | ||
| 124 | } | ||
| 125 | |||
| 126 | /* Write PTE to hardware MMU. */ | ||
| 127 | static inline void sun3_put_pte(unsigned long addr, unsigned long entry) | ||
| 128 | { | ||
| 129 | unsigned char sfc; | ||
| 130 | |||
| 131 | GET_DFC (sfc); | ||
| 132 | SET_DFC (FC_CONTROL); | ||
| 133 | SET_CONTROL_WORD (AC_PAGEMAP | (addr & SUN3_CONTROL_MASK), entry); | ||
| 134 | SET_DFC (sfc); | ||
| 135 | |||
| 136 | return; | ||
| 137 | } | ||
| 138 | |||
| 139 | /* get current context */ | ||
| 140 | static inline unsigned char sun3_get_context(void) | ||
| 141 | { | ||
| 142 | unsigned char sfc, c; | ||
| 143 | |||
| 144 | GET_SFC(sfc); | ||
| 145 | SET_SFC(FC_CONTROL); | ||
| 146 | GET_CONTROL_BYTE(AC_CONTEXT, c); | ||
| 147 | SET_SFC(sfc); | ||
| 148 | |||
| 149 | return c; | ||
| 150 | } | ||
| 151 | |||
| 152 | /* set alternate context */ | ||
| 153 | static inline void sun3_put_context(unsigned char c) | ||
| 154 | { | ||
| 155 | unsigned char dfc; | ||
| 156 | GET_DFC(dfc); | ||
| 157 | SET_DFC(FC_CONTROL); | ||
| 158 | SET_CONTROL_BYTE(AC_CONTEXT, c); | ||
| 159 | SET_DFC(dfc); | ||
| 160 | |||
| 161 | return; | ||
| 162 | } | ||
| 163 | |||
| 164 | extern void __iomem *sun3_ioremap(unsigned long phys, unsigned long size, | ||
| 165 | unsigned long type); | ||
| 166 | |||
| 167 | extern int sun3_map_test(unsigned long addr, char *val); | ||
| 168 | |||
| 169 | #endif /* !__ASSEMBLY__ */ | ||
| 170 | |||
| 171 | #endif /* !__SUN3_MMU_H__ */ | ||
diff --git a/arch/m68k/include/asm/sun3x.h b/arch/m68k/include/asm/sun3x.h new file mode 100644 index 000000000000..f5691a1ed7cc --- /dev/null +++ b/arch/m68k/include/asm/sun3x.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | #ifndef SUN3X_H | ||
| 2 | #define SUN3X_H | ||
| 3 | |||
| 4 | /* hardware addresses */ | ||
| 5 | #define SUN3X_IOMMU 0x60000000 | ||
| 6 | #define SUN3X_ENAREG 0x61000000 | ||
| 7 | #define SUN3X_INTREG 0x61001400 | ||
| 8 | #define SUN3X_DIAGREG 0x61001800 | ||
| 9 | #define SUN3X_ZS1 0x62000000 | ||
| 10 | #define SUN3X_ZS2 0x62002000 | ||
| 11 | #define SUN3X_LANCE 0x65002000 | ||
| 12 | #define SUN3X_EEPROM 0x64000000 | ||
| 13 | #define SUN3X_IDPROM 0x640007d8 | ||
| 14 | #define SUN3X_VIDEO_BASE 0x50000000 | ||
| 15 | #define SUN3X_VIDEO_P4ID 0x50300000 | ||
| 16 | #define SUN3X_ESP_BASE 0x66000000 | ||
| 17 | #define SUN3X_ESP_DMA 0x66001000 | ||
| 18 | #define SUN3X_FDC 0x6e000000 | ||
| 19 | #define SUN3X_FDC_FCR 0x6e000400 | ||
| 20 | #define SUN3X_FDC_FVR 0x6e000800 | ||
| 21 | |||
| 22 | /* some NVRAM addresses */ | ||
| 23 | #define SUN3X_EEPROM_CONS (SUN3X_EEPROM + 0x1f) | ||
| 24 | #define SUN3X_EEPROM_PORTA (SUN3X_EEPROM + 0x58) | ||
| 25 | #define SUN3X_EEPROM_PORTB (SUN3X_EEPROM + 0x60) | ||
| 26 | |||
| 27 | #endif | ||
diff --git a/arch/m68k/include/asm/sun3xflop.h b/arch/m68k/include/asm/sun3xflop.h new file mode 100644 index 000000000000..32c45f84ac60 --- /dev/null +++ b/arch/m68k/include/asm/sun3xflop.h | |||
| @@ -0,0 +1,263 @@ | |||
| 1 | /* sun3xflop.h: Sun3/80 specific parts of the floppy driver. | ||
| 2 | * | ||
| 3 | * Derived partially from asm-sparc/floppy.h, which is: | ||
| 4 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
| 5 | * | ||
| 6 | * Sun3x version 2/4/2000 Sam Creasey (sammy@sammy.net) | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_SUN3X_FLOPPY_H | ||
| 10 | #define __ASM_SUN3X_FLOPPY_H | ||
| 11 | |||
| 12 | #include <asm/page.h> | ||
| 13 | #include <asm/pgtable.h> | ||
| 14 | #include <asm/system.h> | ||
| 15 | #include <asm/irq.h> | ||
| 16 | #include <asm/sun3x.h> | ||
| 17 | |||
| 18 | /* default interrupt vector */ | ||
| 19 | #define SUN3X_FDC_IRQ 0x40 | ||
| 20 | |||
| 21 | /* some constants */ | ||
| 22 | #define FCR_TC 0x1 | ||
| 23 | #define FCR_EJECT 0x2 | ||
| 24 | #define FCR_MTRON 0x4 | ||
| 25 | #define FCR_DSEL1 0x8 | ||
| 26 | #define FCR_DSEL0 0x10 | ||
| 27 | |||
| 28 | /* We don't need no stinkin' I/O port allocation crap. */ | ||
| 29 | #undef release_region | ||
| 30 | #undef request_region | ||
| 31 | #define release_region(X, Y) do { } while(0) | ||
| 32 | #define request_region(X, Y, Z) (1) | ||
| 33 | |||
| 34 | struct sun3xflop_private { | ||
| 35 | volatile unsigned char *status_r; | ||
| 36 | volatile unsigned char *data_r; | ||
| 37 | volatile unsigned char *fcr_r; | ||
| 38 | volatile unsigned char *fvr_r; | ||
| 39 | unsigned char fcr; | ||
| 40 | } sun3x_fdc; | ||
| 41 | |||
| 42 | /* Super paranoid... */ | ||
| 43 | #undef HAVE_DISABLE_HLT | ||
| 44 | |||
| 45 | /* Routines unique to each controller type on a Sun. */ | ||
| 46 | static unsigned char sun3x_82072_fd_inb(int port) | ||
| 47 | { | ||
| 48 | static int once = 0; | ||
| 49 | // udelay(5); | ||
| 50 | switch(port & 7) { | ||
| 51 | default: | ||
| 52 | printk("floppy: Asked to read unknown port %d\n", port); | ||
| 53 | panic("floppy: Port bolixed."); | ||
| 54 | case 4: /* FD_STATUS */ | ||
| 55 | return (*sun3x_fdc.status_r) & ~STATUS_DMA; | ||
| 56 | case 5: /* FD_DATA */ | ||
| 57 | return (*sun3x_fdc.data_r); | ||
| 58 | case 7: /* FD_DIR */ | ||
| 59 | /* ugly hack, I can't find a way to actually detect the disk */ | ||
| 60 | if(!once) { | ||
| 61 | once = 1; | ||
| 62 | return 0x80; | ||
| 63 | } | ||
| 64 | return 0; | ||
| 65 | }; | ||
| 66 | panic("sun_82072_fd_inb: How did I get here?"); | ||
| 67 | } | ||
| 68 | |||
| 69 | static void sun3x_82072_fd_outb(unsigned char value, int port) | ||
| 70 | { | ||
| 71 | // udelay(5); | ||
| 72 | switch(port & 7) { | ||
| 73 | default: | ||
| 74 | printk("floppy: Asked to write to unknown port %d\n", port); | ||
| 75 | panic("floppy: Port bolixed."); | ||
| 76 | case 2: /* FD_DOR */ | ||
| 77 | /* Oh geese, 82072 on the Sun has no DOR register, | ||
| 78 | * so we make do with taunting the FCR. | ||
| 79 | * | ||
| 80 | * ASSUMPTIONS: There will only ever be one floppy | ||
| 81 | * drive attached to a Sun controller | ||
| 82 | * and it will be at drive zero. | ||
| 83 | */ | ||
| 84 | |||
| 85 | { | ||
| 86 | unsigned char fcr = sun3x_fdc.fcr; | ||
| 87 | |||
| 88 | if(value & 0x10) { | ||
| 89 | fcr |= (FCR_DSEL0 | FCR_MTRON); | ||
| 90 | } else | ||
| 91 | fcr &= ~(FCR_DSEL0 | FCR_MTRON); | ||
| 92 | |||
| 93 | |||
| 94 | if(fcr != sun3x_fdc.fcr) { | ||
| 95 | *(sun3x_fdc.fcr_r) = fcr; | ||
| 96 | sun3x_fdc.fcr = fcr; | ||
| 97 | } | ||
| 98 | } | ||
| 99 | break; | ||
| 100 | case 5: /* FD_DATA */ | ||
| 101 | *(sun3x_fdc.data_r) = value; | ||
| 102 | break; | ||
| 103 | case 7: /* FD_DCR */ | ||
| 104 | *(sun3x_fdc.status_r) = value; | ||
| 105 | break; | ||
| 106 | case 4: /* FD_STATUS */ | ||
| 107 | *(sun3x_fdc.status_r) = value; | ||
| 108 | break; | ||
| 109 | }; | ||
| 110 | return; | ||
| 111 | } | ||
| 112 | |||
| 113 | |||
| 114 | asmlinkage irqreturn_t sun3xflop_hardint(int irq, void *dev_id) | ||
| 115 | { | ||
| 116 | register unsigned char st; | ||
| 117 | |||
| 118 | #undef TRACE_FLPY_INT | ||
| 119 | #define NO_FLOPPY_ASSEMBLER | ||
| 120 | |||
| 121 | #ifdef TRACE_FLPY_INT | ||
| 122 | static int calls=0; | ||
| 123 | static int bytes=0; | ||
| 124 | static int dma_wait=0; | ||
| 125 | #endif | ||
| 126 | if(!doing_pdma) { | ||
| 127 | floppy_interrupt(irq, dev_id); | ||
| 128 | return IRQ_HANDLED; | ||
| 129 | } | ||
| 130 | |||
| 131 | // printk("doing pdma\n");// st %x\n", sun_fdc->status_82072); | ||
| 132 | |||
| 133 | #ifdef TRACE_FLPY_INT | ||
| 134 | if(!calls) | ||
| 135 | bytes = virtual_dma_count; | ||
| 136 | #endif | ||
| 137 | |||
| 138 | { | ||
| 139 | register int lcount; | ||
| 140 | register char *lptr; | ||
| 141 | |||
| 142 | for(lcount=virtual_dma_count, lptr=virtual_dma_addr; | ||
| 143 | lcount; lcount--, lptr++) { | ||
| 144 | /* st=fd_inb(virtual_dma_port+4) & 0x80 ; */ | ||
| 145 | st = *(sun3x_fdc.status_r); | ||
| 146 | /* if(st != 0xa0) */ | ||
| 147 | /* break; */ | ||
| 148 | |||
| 149 | if((st & 0x80) == 0) { | ||
| 150 | virtual_dma_count = lcount; | ||
| 151 | virtual_dma_addr = lptr; | ||
| 152 | return IRQ_HANDLED; | ||
| 153 | } | ||
| 154 | |||
| 155 | if((st & 0x20) == 0) | ||
| 156 | break; | ||
| 157 | |||
| 158 | if(virtual_dma_mode) | ||
| 159 | /* fd_outb(*lptr, virtual_dma_port+5); */ | ||
| 160 | *(sun3x_fdc.data_r) = *lptr; | ||
| 161 | else | ||
| 162 | /* *lptr = fd_inb(virtual_dma_port+5); */ | ||
| 163 | *lptr = *(sun3x_fdc.data_r); | ||
| 164 | } | ||
| 165 | |||
| 166 | virtual_dma_count = lcount; | ||
| 167 | virtual_dma_addr = lptr; | ||
| 168 | /* st = fd_inb(virtual_dma_port+4); */ | ||
| 169 | st = *(sun3x_fdc.status_r); | ||
| 170 | } | ||
| 171 | |||
| 172 | #ifdef TRACE_FLPY_INT | ||
| 173 | calls++; | ||
| 174 | #endif | ||
| 175 | // printk("st=%02x\n", st); | ||
| 176 | if(st == 0x20) | ||
| 177 | return IRQ_HANDLED; | ||
| 178 | if(!(st & 0x20)) { | ||
| 179 | virtual_dma_residue += virtual_dma_count; | ||
| 180 | virtual_dma_count=0; | ||
| 181 | doing_pdma = 0; | ||
| 182 | |||
| 183 | #ifdef TRACE_FLPY_INT | ||
| 184 | printk("count=%x, residue=%x calls=%d bytes=%x dma_wait=%d\n", | ||
| 185 | virtual_dma_count, virtual_dma_residue, calls, bytes, | ||
| 186 | dma_wait); | ||
| 187 | calls = 0; | ||
| 188 | dma_wait=0; | ||
| 189 | #endif | ||
| 190 | |||
| 191 | floppy_interrupt(irq, dev_id); | ||
| 192 | return IRQ_HANDLED; | ||
| 193 | } | ||
| 194 | |||
| 195 | |||
| 196 | #ifdef TRACE_FLPY_INT | ||
| 197 | if(!virtual_dma_count) | ||
| 198 | dma_wait++; | ||
| 199 | #endif | ||
| 200 | return IRQ_HANDLED; | ||
| 201 | } | ||
| 202 | |||
| 203 | static int sun3xflop_request_irq(void) | ||
| 204 | { | ||
| 205 | static int once = 0; | ||
| 206 | int error; | ||
| 207 | |||
| 208 | if(!once) { | ||
| 209 | once = 1; | ||
| 210 | error = request_irq(FLOPPY_IRQ, sun3xflop_hardint, | ||
| 211 | IRQF_DISABLED, "floppy", NULL); | ||
| 212 | return ((error == 0) ? 0 : -1); | ||
| 213 | } else return 0; | ||
| 214 | } | ||
| 215 | |||
| 216 | static void __init floppy_set_flags(int *ints,int param, int param2); | ||
| 217 | |||
| 218 | static int sun3xflop_init(void) | ||
| 219 | { | ||
| 220 | if(FLOPPY_IRQ < 0x40) | ||
| 221 | FLOPPY_IRQ = SUN3X_FDC_IRQ; | ||
| 222 | |||
| 223 | sun3x_fdc.status_r = (volatile unsigned char *)SUN3X_FDC; | ||
| 224 | sun3x_fdc.data_r = (volatile unsigned char *)(SUN3X_FDC+1); | ||
| 225 | sun3x_fdc.fcr_r = (volatile unsigned char *)SUN3X_FDC_FCR; | ||
| 226 | sun3x_fdc.fvr_r = (volatile unsigned char *)SUN3X_FDC_FVR; | ||
| 227 | sun3x_fdc.fcr = 0; | ||
| 228 | |||
| 229 | /* Last minute sanity check... */ | ||
| 230 | if(*sun3x_fdc.status_r == 0xff) { | ||
| 231 | return -1; | ||
| 232 | } | ||
| 233 | |||
| 234 | *sun3x_fdc.fvr_r = FLOPPY_IRQ; | ||
| 235 | |||
| 236 | *sun3x_fdc.fcr_r = FCR_TC; | ||
| 237 | udelay(10); | ||
| 238 | *sun3x_fdc.fcr_r = 0; | ||
| 239 | |||
| 240 | /* Success... */ | ||
| 241 | floppy_set_flags(NULL, 1, FD_BROKEN_DCL); // I don't know how to detect this. | ||
| 242 | allowed_drive_mask = 0x01; | ||
| 243 | return (int) SUN3X_FDC; | ||
| 244 | } | ||
| 245 | |||
| 246 | /* I'm not precisely sure this eject routine works */ | ||
| 247 | static int sun3x_eject(void) | ||
| 248 | { | ||
| 249 | if(MACH_IS_SUN3X) { | ||
| 250 | |||
| 251 | sun3x_fdc.fcr |= (FCR_DSEL0 | FCR_EJECT); | ||
| 252 | *(sun3x_fdc.fcr_r) = sun3x_fdc.fcr; | ||
| 253 | udelay(10); | ||
| 254 | sun3x_fdc.fcr &= ~(FCR_DSEL0 | FCR_EJECT); | ||
| 255 | *(sun3x_fdc.fcr_r) = sun3x_fdc.fcr; | ||
| 256 | } | ||
| 257 | |||
| 258 | return 0; | ||
| 259 | } | ||
| 260 | |||
| 261 | #define fd_eject(drive) sun3x_eject() | ||
| 262 | |||
| 263 | #endif /* !(__ASM_SUN3X_FLOPPY_H) */ | ||
diff --git a/arch/m68k/include/asm/sun3xprom.h b/arch/m68k/include/asm/sun3xprom.h new file mode 100644 index 000000000000..6735efcf5f6d --- /dev/null +++ b/arch/m68k/include/asm/sun3xprom.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* Useful PROM locations */ | ||
| 2 | |||
| 3 | #ifndef SUN3X_PROM_H | ||
| 4 | #define SUN3X_PROM_H | ||
| 5 | |||
| 6 | extern void (*sun3x_putchar)(int); | ||
| 7 | extern int (*sun3x_getchar)(void); | ||
| 8 | extern int (*sun3x_mayget)(void); | ||
| 9 | extern int (*sun3x_mayput)(int); | ||
| 10 | |||
| 11 | void sun3x_reboot(void); | ||
| 12 | void sun3x_abort(void); | ||
| 13 | void sun3x_prom_init(void); | ||
| 14 | unsigned long sun3x_prom_ptov(unsigned long pa, unsigned long size); | ||
| 15 | |||
| 16 | /* interesting hardware locations */ | ||
| 17 | #define SUN3X_IOMMU 0x60000000 | ||
| 18 | #define SUN3X_ENAREG 0x61000000 | ||
| 19 | #define SUN3X_INTREG 0x61001400 | ||
| 20 | #define SUN3X_DIAGREG 0x61001800 | ||
| 21 | #define SUN3X_ZS1 0x62000000 | ||
| 22 | #define SUN3X_ZS2 0x62002000 | ||
| 23 | #define SUN3X_LANCE 0x65002000 | ||
| 24 | #define SUN3X_EEPROM 0x64000000 | ||
| 25 | #define SUN3X_IDPROM 0x640007d8 | ||
| 26 | #define SUN3X_VIDEO_BASE 0x50400000 | ||
| 27 | #define SUN3X_VIDEO_REGS 0x50300000 | ||
| 28 | |||
| 29 | /* vector table */ | ||
| 30 | #define SUN3X_PROM_BASE 0xfefe0000 | ||
| 31 | #define SUN3X_P_GETCHAR (SUN3X_PROM_BASE + 20) | ||
| 32 | #define SUN3X_P_PUTCHAR (SUN3X_PROM_BASE + 24) | ||
| 33 | #define SUN3X_P_MAYGET (SUN3X_PROM_BASE + 28) | ||
| 34 | #define SUN3X_P_MAYPUT (SUN3X_PROM_BASE + 32) | ||
| 35 | #define SUN3X_P_REBOOT (SUN3X_PROM_BASE + 96) | ||
| 36 | #define SUN3X_P_SETLEDS (SUN3X_PROM_BASE + 144) | ||
| 37 | #define SUN3X_P_ABORT (SUN3X_PROM_BASE + 152) | ||
| 38 | |||
| 39 | /* mapped area */ | ||
| 40 | #define SUN3X_MAP_START 0xfee00000 | ||
| 41 | #define SUN3X_MAP_END 0xff000000 | ||
| 42 | |||
| 43 | #endif | ||
diff --git a/arch/m68k/include/asm/suspend.h b/arch/m68k/include/asm/suspend.h new file mode 100644 index 000000000000..57b3ddb4d269 --- /dev/null +++ b/arch/m68k/include/asm/suspend.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _M68K_SUSPEND_H | ||
| 2 | #define _M68K_SUSPEND_H | ||
| 3 | |||
| 4 | /* Dummy include. */ | ||
| 5 | |||
| 6 | #endif /* _M68K_SUSPEND_H */ | ||
diff --git a/arch/m68k/include/asm/swab.h b/arch/m68k/include/asm/swab.h new file mode 100644 index 000000000000..e69de29bb2d1 --- /dev/null +++ b/arch/m68k/include/asm/swab.h | |||
diff --git a/arch/m68k/include/asm/swab_mm.h b/arch/m68k/include/asm/swab_mm.h new file mode 100644 index 000000000000..7221e3066825 --- /dev/null +++ b/arch/m68k/include/asm/swab_mm.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | #ifndef _M68K_SWAB_H | ||
| 2 | #define _M68K_SWAB_H | ||
| 3 | |||
| 4 | #include <asm/types.h> | ||
| 5 | #include <linux/compiler.h> | ||
| 6 | |||
| 7 | #define __SWAB_64_THRU_32__ | ||
| 8 | |||
| 9 | static inline __attribute_const__ __u32 __arch_swab32(__u32 val) | ||
| 10 | { | ||
| 11 | __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val)); | ||
| 12 | return val; | ||
| 13 | } | ||
| 14 | #define __arch_swab32 __arch_swab32 | ||
| 15 | |||
| 16 | #endif /* _M68K_SWAB_H */ | ||
diff --git a/arch/m68k/include/asm/swab_no.h b/arch/m68k/include/asm/swab_no.h new file mode 100644 index 000000000000..e582257db300 --- /dev/null +++ b/arch/m68k/include/asm/swab_no.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | #ifndef _M68KNOMMU_SWAB_H | ||
| 2 | #define _M68KNOMMU_SWAB_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
| 7 | # define __SWAB_64_THRU_32__ | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #if defined (__mcfisaaplus__) || defined (__mcfisac__) | ||
| 11 | static inline __attribute_const__ __u32 __arch_swab32(__u32 val) | ||
| 12 | { | ||
| 13 | asm( | ||
| 14 | "byterev %0" | ||
| 15 | : "=d" (val) | ||
| 16 | : "0" (val) | ||
| 17 | ); | ||
| 18 | return val; | ||
| 19 | } | ||
| 20 | |||
| 21 | #define __arch_swab32 __arch_swab32 | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #endif /* _M68KNOMMU_SWAB_H */ | ||
diff --git a/arch/m68k/include/asm/system.h b/arch/m68k/include/asm/system.h new file mode 100644 index 000000000000..ccea925ff4f5 --- /dev/null +++ b/arch/m68k/include/asm/system.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "system_no.h" | ||
| 3 | #else | ||
| 4 | #include "system_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/system_mm.h b/arch/m68k/include/asm/system_mm.h new file mode 100644 index 000000000000..dbb6515ffd5b --- /dev/null +++ b/arch/m68k/include/asm/system_mm.h | |||
| @@ -0,0 +1,218 @@ | |||
| 1 | #ifndef _M68K_SYSTEM_H | ||
| 2 | #define _M68K_SYSTEM_H | ||
| 3 | |||
| 4 | #include <linux/linkage.h> | ||
| 5 | #include <linux/kernel.h> | ||
| 6 | #include <asm/segment.h> | ||
| 7 | #include <asm/entry.h> | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | |||
| 11 | /* | ||
| 12 | * switch_to(n) should switch tasks to task ptr, first checking that | ||
| 13 | * ptr isn't the current task, in which case it does nothing. This | ||
| 14 | * also clears the TS-flag if the task we switched to has used the | ||
| 15 | * math co-processor latest. | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * switch_to() saves the extra registers, that are not saved | ||
| 19 | * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and | ||
| 20 | * a0-a1. Some of these are used by schedule() and its predecessors | ||
| 21 | * and so we might get see unexpected behaviors when a task returns | ||
| 22 | * with unexpected register values. | ||
| 23 | * | ||
| 24 | * syscall stores these registers itself and none of them are used | ||
| 25 | * by syscall after the function in the syscall has been called. | ||
| 26 | * | ||
| 27 | * Beware that resume now expects *next to be in d1 and the offset of | ||
| 28 | * tss to be in a1. This saves a few instructions as we no longer have | ||
| 29 | * to push them onto the stack and read them back right after. | ||
| 30 | * | ||
| 31 | * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) | ||
| 32 | * | ||
| 33 | * Changed 96/09/19 by Andreas Schwab | ||
| 34 | * pass prev in a0, next in a1 | ||
| 35 | */ | ||
| 36 | asmlinkage void resume(void); | ||
| 37 | #define switch_to(prev,next,last) do { \ | ||
| 38 | register void *_prev __asm__ ("a0") = (prev); \ | ||
| 39 | register void *_next __asm__ ("a1") = (next); \ | ||
| 40 | register void *_last __asm__ ("d1"); \ | ||
| 41 | __asm__ __volatile__("jbsr resume" \ | ||
| 42 | : "=a" (_prev), "=a" (_next), "=d" (_last) \ | ||
| 43 | : "0" (_prev), "1" (_next) \ | ||
| 44 | : "d0", "d2", "d3", "d4", "d5"); \ | ||
| 45 | (last) = _last; \ | ||
| 46 | } while (0) | ||
| 47 | |||
| 48 | |||
| 49 | /* | ||
| 50 | * Force strict CPU ordering. | ||
| 51 | * Not really required on m68k... | ||
| 52 | */ | ||
| 53 | #define nop() do { asm volatile ("nop"); barrier(); } while (0) | ||
| 54 | #define mb() barrier() | ||
| 55 | #define rmb() barrier() | ||
| 56 | #define wmb() barrier() | ||
| 57 | #define read_barrier_depends() ((void)0) | ||
| 58 | #define set_mb(var, value) ({ (var) = (value); wmb(); }) | ||
| 59 | |||
| 60 | #define smp_mb() barrier() | ||
| 61 | #define smp_rmb() barrier() | ||
| 62 | #define smp_wmb() barrier() | ||
| 63 | #define smp_read_barrier_depends() ((void)0) | ||
| 64 | |||
| 65 | /* interrupt control.. */ | ||
| 66 | #if 0 | ||
| 67 | #define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory") | ||
| 68 | #else | ||
| 69 | #include <linux/hardirq.h> | ||
| 70 | #define local_irq_enable() ({ \ | ||
| 71 | if (MACH_IS_Q40 || !hardirq_count()) \ | ||
| 72 | asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \ | ||
| 73 | }) | ||
| 74 | #endif | ||
| 75 | #define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory") | ||
| 76 | #define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory") | ||
| 77 | #define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory") | ||
| 78 | |||
| 79 | static inline int irqs_disabled(void) | ||
| 80 | { | ||
| 81 | unsigned long flags; | ||
| 82 | local_save_flags(flags); | ||
| 83 | return flags & ~ALLOWINT; | ||
| 84 | } | ||
| 85 | |||
| 86 | /* For spinlocks etc */ | ||
| 87 | #define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); }) | ||
| 88 | |||
| 89 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
| 90 | |||
| 91 | struct __xchg_dummy { unsigned long a[100]; }; | ||
| 92 | #define __xg(x) ((volatile struct __xchg_dummy *)(x)) | ||
| 93 | |||
| 94 | #ifndef CONFIG_RMW_INSNS | ||
| 95 | static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) | ||
| 96 | { | ||
| 97 | unsigned long flags, tmp; | ||
| 98 | |||
| 99 | local_irq_save(flags); | ||
| 100 | |||
| 101 | switch (size) { | ||
| 102 | case 1: | ||
| 103 | tmp = *(u8 *)ptr; | ||
| 104 | *(u8 *)ptr = x; | ||
| 105 | x = tmp; | ||
| 106 | break; | ||
| 107 | case 2: | ||
| 108 | tmp = *(u16 *)ptr; | ||
| 109 | *(u16 *)ptr = x; | ||
| 110 | x = tmp; | ||
| 111 | break; | ||
| 112 | case 4: | ||
| 113 | tmp = *(u32 *)ptr; | ||
| 114 | *(u32 *)ptr = x; | ||
| 115 | x = tmp; | ||
| 116 | break; | ||
| 117 | default: | ||
| 118 | BUG(); | ||
| 119 | } | ||
| 120 | |||
| 121 | local_irq_restore(flags); | ||
| 122 | return x; | ||
| 123 | } | ||
| 124 | #else | ||
| 125 | static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) | ||
| 126 | { | ||
| 127 | switch (size) { | ||
| 128 | case 1: | ||
| 129 | __asm__ __volatile__ | ||
| 130 | ("moveb %2,%0\n\t" | ||
| 131 | "1:\n\t" | ||
| 132 | "casb %0,%1,%2\n\t" | ||
| 133 | "jne 1b" | ||
| 134 | : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 135 | break; | ||
| 136 | case 2: | ||
| 137 | __asm__ __volatile__ | ||
| 138 | ("movew %2,%0\n\t" | ||
| 139 | "1:\n\t" | ||
| 140 | "casw %0,%1,%2\n\t" | ||
| 141 | "jne 1b" | ||
| 142 | : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 143 | break; | ||
| 144 | case 4: | ||
| 145 | __asm__ __volatile__ | ||
| 146 | ("movel %2,%0\n\t" | ||
| 147 | "1:\n\t" | ||
| 148 | "casl %0,%1,%2\n\t" | ||
| 149 | "jne 1b" | ||
| 150 | : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 151 | break; | ||
| 152 | } | ||
| 153 | return x; | ||
| 154 | } | ||
| 155 | #endif | ||
| 156 | |||
| 157 | #include <asm-generic/cmpxchg-local.h> | ||
| 158 | |||
| 159 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | ||
| 160 | |||
| 161 | /* | ||
| 162 | * Atomic compare and exchange. Compare OLD with MEM, if identical, | ||
| 163 | * store NEW in MEM. Return the initial value in MEM. Success is | ||
| 164 | * indicated by comparing RETURN with OLD. | ||
| 165 | */ | ||
| 166 | #ifdef CONFIG_RMW_INSNS | ||
| 167 | #define __HAVE_ARCH_CMPXCHG 1 | ||
| 168 | |||
| 169 | static inline unsigned long __cmpxchg(volatile void *p, unsigned long old, | ||
| 170 | unsigned long new, int size) | ||
| 171 | { | ||
| 172 | switch (size) { | ||
| 173 | case 1: | ||
| 174 | __asm__ __volatile__ ("casb %0,%2,%1" | ||
| 175 | : "=d" (old), "=m" (*(char *)p) | ||
| 176 | : "d" (new), "0" (old), "m" (*(char *)p)); | ||
| 177 | break; | ||
| 178 | case 2: | ||
| 179 | __asm__ __volatile__ ("casw %0,%2,%1" | ||
| 180 | : "=d" (old), "=m" (*(short *)p) | ||
| 181 | : "d" (new), "0" (old), "m" (*(short *)p)); | ||
| 182 | break; | ||
| 183 | case 4: | ||
| 184 | __asm__ __volatile__ ("casl %0,%2,%1" | ||
| 185 | : "=d" (old), "=m" (*(int *)p) | ||
| 186 | : "d" (new), "0" (old), "m" (*(int *)p)); | ||
| 187 | break; | ||
| 188 | } | ||
| 189 | return old; | ||
| 190 | } | ||
| 191 | |||
| 192 | #define cmpxchg(ptr, o, n) \ | ||
| 193 | ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ | ||
| 194 | (unsigned long)(n), sizeof(*(ptr)))) | ||
| 195 | #define cmpxchg_local(ptr, o, n) \ | ||
| 196 | ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \ | ||
| 197 | (unsigned long)(n), sizeof(*(ptr)))) | ||
| 198 | #else | ||
| 199 | |||
| 200 | /* | ||
| 201 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make | ||
| 202 | * them available. | ||
| 203 | */ | ||
| 204 | #define cmpxchg_local(ptr, o, n) \ | ||
| 205 | ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ | ||
| 206 | (unsigned long)(n), sizeof(*(ptr)))) | ||
| 207 | |||
| 208 | #ifndef CONFIG_SMP | ||
| 209 | #include <asm-generic/cmpxchg.h> | ||
| 210 | #endif | ||
| 211 | |||
| 212 | #endif | ||
| 213 | |||
| 214 | #define arch_align_stack(x) (x) | ||
| 215 | |||
| 216 | #endif /* __KERNEL__ */ | ||
| 217 | |||
| 218 | #endif /* _M68K_SYSTEM_H */ | ||
diff --git a/arch/m68k/include/asm/system_no.h b/arch/m68k/include/asm/system_no.h new file mode 100644 index 000000000000..40f49de69821 --- /dev/null +++ b/arch/m68k/include/asm/system_no.h | |||
| @@ -0,0 +1,324 @@ | |||
| 1 | #ifndef _M68KNOMMU_SYSTEM_H | ||
| 2 | #define _M68KNOMMU_SYSTEM_H | ||
| 3 | |||
| 4 | #include <linux/linkage.h> | ||
| 5 | #include <asm/segment.h> | ||
| 6 | #include <asm/entry.h> | ||
| 7 | |||
| 8 | /* | ||
| 9 | * switch_to(n) should switch tasks to task ptr, first checking that | ||
| 10 | * ptr isn't the current task, in which case it does nothing. This | ||
| 11 | * also clears the TS-flag if the task we switched to has used the | ||
| 12 | * math co-processor latest. | ||
| 13 | */ | ||
| 14 | /* | ||
| 15 | * switch_to() saves the extra registers, that are not saved | ||
| 16 | * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and | ||
| 17 | * a0-a1. Some of these are used by schedule() and its predecessors | ||
| 18 | * and so we might get see unexpected behaviors when a task returns | ||
| 19 | * with unexpected register values. | ||
| 20 | * | ||
| 21 | * syscall stores these registers itself and none of them are used | ||
| 22 | * by syscall after the function in the syscall has been called. | ||
| 23 | * | ||
| 24 | * Beware that resume now expects *next to be in d1 and the offset of | ||
| 25 | * tss to be in a1. This saves a few instructions as we no longer have | ||
| 26 | * to push them onto the stack and read them back right after. | ||
| 27 | * | ||
| 28 | * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) | ||
| 29 | * | ||
| 30 | * Changed 96/09/19 by Andreas Schwab | ||
| 31 | * pass prev in a0, next in a1, offset of tss in d1, and whether | ||
| 32 | * the mm structures are shared in d2 (to avoid atc flushing). | ||
| 33 | */ | ||
| 34 | asmlinkage void resume(void); | ||
| 35 | #define switch_to(prev,next,last) \ | ||
| 36 | { \ | ||
| 37 | void *_last; \ | ||
| 38 | __asm__ __volatile__( \ | ||
| 39 | "movel %1, %%a0\n\t" \ | ||
| 40 | "movel %2, %%a1\n\t" \ | ||
| 41 | "jbsr resume\n\t" \ | ||
| 42 | "movel %%d1, %0\n\t" \ | ||
| 43 | : "=d" (_last) \ | ||
| 44 | : "d" (prev), "d" (next) \ | ||
| 45 | : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \ | ||
| 46 | (last) = _last; \ | ||
| 47 | } | ||
| 48 | |||
| 49 | #ifdef CONFIG_COLDFIRE | ||
| 50 | #define local_irq_enable() __asm__ __volatile__ ( \ | ||
| 51 | "move %/sr,%%d0\n\t" \ | ||
| 52 | "andi.l #0xf8ff,%%d0\n\t" \ | ||
| 53 | "move %%d0,%/sr\n" \ | ||
| 54 | : /* no outputs */ \ | ||
| 55 | : \ | ||
| 56 | : "cc", "%d0", "memory") | ||
| 57 | #define local_irq_disable() __asm__ __volatile__ ( \ | ||
| 58 | "move %/sr,%%d0\n\t" \ | ||
| 59 | "ori.l #0x0700,%%d0\n\t" \ | ||
| 60 | "move %%d0,%/sr\n" \ | ||
| 61 | : /* no outputs */ \ | ||
| 62 | : \ | ||
| 63 | : "cc", "%d0", "memory") | ||
| 64 | /* For spinlocks etc */ | ||
| 65 | #define local_irq_save(x) __asm__ __volatile__ ( \ | ||
| 66 | "movew %%sr,%0\n\t" \ | ||
| 67 | "movew #0x0700,%%d0\n\t" \ | ||
| 68 | "or.l %0,%%d0\n\t" \ | ||
| 69 | "movew %%d0,%/sr" \ | ||
| 70 | : "=d" (x) \ | ||
| 71 | : \ | ||
| 72 | : "cc", "%d0", "memory") | ||
| 73 | #else | ||
| 74 | |||
| 75 | /* portable version */ /* FIXME - see entry.h*/ | ||
| 76 | #define ALLOWINT 0xf8ff | ||
| 77 | |||
| 78 | #define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory") | ||
| 79 | #define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory") | ||
| 80 | #endif | ||
| 81 | |||
| 82 | #define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory") | ||
| 83 | #define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory") | ||
| 84 | |||
| 85 | /* For spinlocks etc */ | ||
| 86 | #ifndef local_irq_save | ||
| 87 | #define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0) | ||
| 88 | #endif | ||
| 89 | |||
| 90 | #define irqs_disabled() \ | ||
| 91 | ({ \ | ||
| 92 | unsigned long flags; \ | ||
| 93 | local_save_flags(flags); \ | ||
| 94 | ((flags & 0x0700) == 0x0700); \ | ||
| 95 | }) | ||
| 96 | |||
| 97 | #define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc") | ||
| 98 | |||
| 99 | /* | ||
| 100 | * Force strict CPU ordering. | ||
| 101 | * Not really required on m68k... | ||
| 102 | */ | ||
| 103 | #define nop() asm volatile ("nop"::) | ||
| 104 | #define mb() asm volatile ("" : : :"memory") | ||
| 105 | #define rmb() asm volatile ("" : : :"memory") | ||
| 106 | #define wmb() asm volatile ("" : : :"memory") | ||
| 107 | #define set_mb(var, value) ({ (var) = (value); wmb(); }) | ||
| 108 | |||
| 109 | #ifdef CONFIG_SMP | ||
| 110 | #define smp_mb() mb() | ||
| 111 | #define smp_rmb() rmb() | ||
| 112 | #define smp_wmb() wmb() | ||
| 113 | #define smp_read_barrier_depends() read_barrier_depends() | ||
| 114 | #else | ||
| 115 | #define smp_mb() barrier() | ||
| 116 | #define smp_rmb() barrier() | ||
| 117 | #define smp_wmb() barrier() | ||
| 118 | #define smp_read_barrier_depends() do { } while(0) | ||
| 119 | #endif | ||
| 120 | |||
| 121 | #define read_barrier_depends() ((void)0) | ||
| 122 | |||
| 123 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | ||
| 124 | |||
| 125 | struct __xchg_dummy { unsigned long a[100]; }; | ||
| 126 | #define __xg(x) ((volatile struct __xchg_dummy *)(x)) | ||
| 127 | |||
| 128 | #ifndef CONFIG_RMW_INSNS | ||
| 129 | static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) | ||
| 130 | { | ||
| 131 | unsigned long tmp, flags; | ||
| 132 | |||
| 133 | local_irq_save(flags); | ||
| 134 | |||
| 135 | switch (size) { | ||
| 136 | case 1: | ||
| 137 | __asm__ __volatile__ | ||
| 138 | ("moveb %2,%0\n\t" | ||
| 139 | "moveb %1,%2" | ||
| 140 | : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 141 | break; | ||
| 142 | case 2: | ||
| 143 | __asm__ __volatile__ | ||
| 144 | ("movew %2,%0\n\t" | ||
| 145 | "movew %1,%2" | ||
| 146 | : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 147 | break; | ||
| 148 | case 4: | ||
| 149 | __asm__ __volatile__ | ||
| 150 | ("movel %2,%0\n\t" | ||
| 151 | "movel %1,%2" | ||
| 152 | : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 153 | break; | ||
| 154 | } | ||
| 155 | local_irq_restore(flags); | ||
| 156 | return tmp; | ||
| 157 | } | ||
| 158 | #else | ||
| 159 | static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) | ||
| 160 | { | ||
| 161 | switch (size) { | ||
| 162 | case 1: | ||
| 163 | __asm__ __volatile__ | ||
| 164 | ("moveb %2,%0\n\t" | ||
| 165 | "1:\n\t" | ||
| 166 | "casb %0,%1,%2\n\t" | ||
| 167 | "jne 1b" | ||
| 168 | : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 169 | break; | ||
| 170 | case 2: | ||
| 171 | __asm__ __volatile__ | ||
| 172 | ("movew %2,%0\n\t" | ||
| 173 | "1:\n\t" | ||
| 174 | "casw %0,%1,%2\n\t" | ||
| 175 | "jne 1b" | ||
| 176 | : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 177 | break; | ||
| 178 | case 4: | ||
| 179 | __asm__ __volatile__ | ||
| 180 | ("movel %2,%0\n\t" | ||
| 181 | "1:\n\t" | ||
| 182 | "casl %0,%1,%2\n\t" | ||
| 183 | "jne 1b" | ||
| 184 | : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); | ||
| 185 | break; | ||
| 186 | } | ||
| 187 | return x; | ||
| 188 | } | ||
| 189 | #endif | ||
| 190 | |||
| 191 | #include <asm-generic/cmpxchg-local.h> | ||
| 192 | |||
| 193 | /* | ||
| 194 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make | ||
| 195 | * them available. | ||
| 196 | */ | ||
| 197 | #define cmpxchg_local(ptr, o, n) \ | ||
| 198 | ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ | ||
| 199 | (unsigned long)(n), sizeof(*(ptr)))) | ||
| 200 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | ||
| 201 | |||
| 202 | #ifndef CONFIG_SMP | ||
| 203 | #include <asm-generic/cmpxchg.h> | ||
| 204 | #endif | ||
| 205 | |||
| 206 | #if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \ | ||
| 207 | defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 ) | ||
| 208 | #define HARD_RESET_NOW() ({ \ | ||
| 209 | local_irq_disable(); \ | ||
| 210 | asm(" \ | ||
| 211 | moveal #0x10c00000, %a0; \ | ||
| 212 | moveb #0, 0xFFFFF300; \ | ||
| 213 | moveal 0(%a0), %sp; \ | ||
| 214 | moveal 4(%a0), %a0; \ | ||
| 215 | jmp (%a0); \ | ||
| 216 | "); \ | ||
| 217 | }) | ||
| 218 | #endif | ||
| 219 | |||
| 220 | #ifdef CONFIG_COLDFIRE | ||
| 221 | #if defined(CONFIG_M5272) && defined(CONFIG_NETtel) | ||
| 222 | /* | ||
| 223 | * Need to account for broken early mask of 5272 silicon. So don't | ||
| 224 | * jump through the original start address. Jump strait into the | ||
| 225 | * known start of the FLASH code. | ||
| 226 | */ | ||
| 227 | #define HARD_RESET_NOW() ({ \ | ||
| 228 | asm(" \ | ||
| 229 | movew #0x2700, %sr; \ | ||
| 230 | jmp 0xf0000400; \ | ||
| 231 | "); \ | ||
| 232 | }) | ||
| 233 | #elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \ | ||
| 234 | defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) | ||
| 235 | #define HARD_RESET_NOW() ({ \ | ||
| 236 | asm(" \ | ||
| 237 | movew #0x2700, %sr; \ | ||
| 238 | moveal #0x10000044, %a0; \ | ||
| 239 | movel #0xffffffff, (%a0); \ | ||
| 240 | moveal #0x10000001, %a0; \ | ||
| 241 | moveb #0x00, (%a0); \ | ||
| 242 | moveal #0xf0000004, %a0; \ | ||
| 243 | moveal (%a0), %a0; \ | ||
| 244 | jmp (%a0); \ | ||
| 245 | "); \ | ||
| 246 | }) | ||
| 247 | #elif defined(CONFIG_M5272) | ||
| 248 | /* | ||
| 249 | * Retrieve the boot address in flash using CSBR0 and CSOR0 | ||
| 250 | * find the reset vector at flash_address + 4 (e.g. 0x400) | ||
| 251 | * remap it in the flash's current location (e.g. 0xf0000400) | ||
| 252 | * and jump there. | ||
| 253 | */ | ||
| 254 | #define HARD_RESET_NOW() ({ \ | ||
| 255 | asm(" \ | ||
| 256 | movew #0x2700, %%sr; \ | ||
| 257 | move.l %0+0x40,%%d0; \ | ||
| 258 | and.l %0+0x44,%%d0; \ | ||
| 259 | andi.l #0xfffff000,%%d0; \ | ||
| 260 | mov.l %%d0,%%a0; \ | ||
| 261 | or.l 4(%%a0),%%d0; \ | ||
| 262 | mov.l %%d0,%%a0; \ | ||
| 263 | jmp (%%a0);" \ | ||
| 264 | : /* No output */ \ | ||
| 265 | : "o" (*(char *)MCF_MBAR) ); \ | ||
| 266 | }) | ||
| 267 | #elif defined(CONFIG_M528x) | ||
| 268 | /* | ||
| 269 | * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR), | ||
| 270 | * that when set, resets the MCF528x. | ||
| 271 | */ | ||
| 272 | #define HARD_RESET_NOW() \ | ||
| 273 | ({ \ | ||
| 274 | unsigned char volatile *reset; \ | ||
| 275 | asm("move.w #0x2700, %sr"); \ | ||
| 276 | reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \ | ||
| 277 | while(1) \ | ||
| 278 | *reset |= (0x01 << 7);\ | ||
| 279 | }) | ||
| 280 | #elif defined(CONFIG_M523x) | ||
| 281 | #define HARD_RESET_NOW() ({ \ | ||
| 282 | asm(" \ | ||
| 283 | movew #0x2700, %sr; \ | ||
| 284 | movel #0x01000000, %sp; \ | ||
| 285 | moveal #0x40110000, %a0; \ | ||
| 286 | moveb #0x80, (%a0); \ | ||
| 287 | "); \ | ||
| 288 | }) | ||
| 289 | #elif defined(CONFIG_M520x) | ||
| 290 | /* | ||
| 291 | * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register | ||
| 292 | * RCR), that when set, resets the MCF5208. | ||
| 293 | */ | ||
| 294 | #define HARD_RESET_NOW() \ | ||
| 295 | ({ \ | ||
| 296 | unsigned char volatile *reset; \ | ||
| 297 | asm("move.w #0x2700, %sr"); \ | ||
| 298 | reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \ | ||
| 299 | while(1) \ | ||
| 300 | *reset |= 0x80; \ | ||
| 301 | }) | ||
| 302 | #else | ||
| 303 | #define HARD_RESET_NOW() ({ \ | ||
| 304 | asm(" \ | ||
| 305 | movew #0x2700, %sr; \ | ||
| 306 | moveal #0x4, %a0; \ | ||
| 307 | moveal (%a0), %a0; \ | ||
| 308 | jmp (%a0); \ | ||
| 309 | "); \ | ||
| 310 | }) | ||
| 311 | #endif | ||
| 312 | #endif | ||
| 313 | #define arch_align_stack(x) (x) | ||
| 314 | |||
| 315 | |||
| 316 | static inline int irqs_disabled_flags(unsigned long flags) | ||
| 317 | { | ||
| 318 | if (flags & 0x0700) | ||
| 319 | return 0; | ||
| 320 | else | ||
| 321 | return 1; | ||
| 322 | } | ||
| 323 | |||
| 324 | #endif /* _M68KNOMMU_SYSTEM_H */ | ||
diff --git a/arch/m68k/include/asm/termbits.h b/arch/m68k/include/asm/termbits.h new file mode 100644 index 000000000000..8c14170996bb --- /dev/null +++ b/arch/m68k/include/asm/termbits.h | |||
| @@ -0,0 +1,200 @@ | |||
| 1 | #ifndef __ARCH_M68K_TERMBITS_H__ | ||
| 2 | #define __ARCH_M68K_TERMBITS_H__ | ||
| 3 | |||
| 4 | #include <linux/posix_types.h> | ||
| 5 | |||
| 6 | typedef unsigned char cc_t; | ||
| 7 | typedef unsigned int speed_t; | ||
| 8 | typedef unsigned int tcflag_t; | ||
| 9 | |||
| 10 | #define NCCS 19 | ||
| 11 | struct termios { | ||
| 12 | tcflag_t c_iflag; /* input mode flags */ | ||
| 13 | tcflag_t c_oflag; /* output mode flags */ | ||
| 14 | tcflag_t c_cflag; /* control mode flags */ | ||
| 15 | tcflag_t c_lflag; /* local mode flags */ | ||
| 16 | cc_t c_line; /* line discipline */ | ||
| 17 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 18 | }; | ||
| 19 | |||
| 20 | struct termios2 { | ||
| 21 | tcflag_t c_iflag; /* input mode flags */ | ||
| 22 | tcflag_t c_oflag; /* output mode flags */ | ||
| 23 | tcflag_t c_cflag; /* control mode flags */ | ||
| 24 | tcflag_t c_lflag; /* local mode flags */ | ||
| 25 | cc_t c_line; /* line discipline */ | ||
| 26 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 27 | speed_t c_ispeed; /* input speed */ | ||
| 28 | speed_t c_ospeed; /* output speed */ | ||
| 29 | }; | ||
| 30 | |||
| 31 | struct ktermios { | ||
| 32 | tcflag_t c_iflag; /* input mode flags */ | ||
| 33 | tcflag_t c_oflag; /* output mode flags */ | ||
| 34 | tcflag_t c_cflag; /* control mode flags */ | ||
| 35 | tcflag_t c_lflag; /* local mode flags */ | ||
| 36 | cc_t c_line; /* line discipline */ | ||
| 37 | cc_t c_cc[NCCS]; /* control characters */ | ||
| 38 | speed_t c_ispeed; /* input speed */ | ||
| 39 | speed_t c_ospeed; /* output speed */ | ||
| 40 | }; | ||
| 41 | |||
| 42 | /* c_cc characters */ | ||
| 43 | #define VINTR 0 | ||
| 44 | #define VQUIT 1 | ||
| 45 | #define VERASE 2 | ||
| 46 | #define VKILL 3 | ||
| 47 | #define VEOF 4 | ||
| 48 | #define VTIME 5 | ||
| 49 | #define VMIN 6 | ||
| 50 | #define VSWTC 7 | ||
| 51 | #define VSTART 8 | ||
| 52 | #define VSTOP 9 | ||
| 53 | #define VSUSP 10 | ||
| 54 | #define VEOL 11 | ||
| 55 | #define VREPRINT 12 | ||
| 56 | #define VDISCARD 13 | ||
| 57 | #define VWERASE 14 | ||
| 58 | #define VLNEXT 15 | ||
| 59 | #define VEOL2 16 | ||
| 60 | |||
| 61 | |||
| 62 | /* c_iflag bits */ | ||
| 63 | #define IGNBRK 0000001 | ||
| 64 | #define BRKINT 0000002 | ||
| 65 | #define IGNPAR 0000004 | ||
| 66 | #define PARMRK 0000010 | ||
| 67 | #define INPCK 0000020 | ||
| 68 | #define ISTRIP 0000040 | ||
| 69 | #define INLCR 0000100 | ||
| 70 | #define IGNCR 0000200 | ||
| 71 | #define ICRNL 0000400 | ||
| 72 | #define IUCLC 0001000 | ||
| 73 | #define IXON 0002000 | ||
| 74 | #define IXANY 0004000 | ||
| 75 | #define IXOFF 0010000 | ||
| 76 | #define IMAXBEL 0020000 | ||
| 77 | #define IUTF8 0040000 | ||
| 78 | |||
| 79 | /* c_oflag bits */ | ||
| 80 | #define OPOST 0000001 | ||
| 81 | #define OLCUC 0000002 | ||
| 82 | #define ONLCR 0000004 | ||
| 83 | #define OCRNL 0000010 | ||
| 84 | #define ONOCR 0000020 | ||
| 85 | #define ONLRET 0000040 | ||
| 86 | #define OFILL 0000100 | ||
| 87 | #define OFDEL 0000200 | ||
| 88 | #define NLDLY 0000400 | ||
| 89 | #define NL0 0000000 | ||
| 90 | #define NL1 0000400 | ||
| 91 | #define CRDLY 0003000 | ||
| 92 | #define CR0 0000000 | ||
| 93 | #define CR1 0001000 | ||
| 94 | #define CR2 0002000 | ||
| 95 | #define CR3 0003000 | ||
| 96 | #define TABDLY 0014000 | ||
| 97 | #define TAB0 0000000 | ||
| 98 | #define TAB1 0004000 | ||
| 99 | #define TAB2 0010000 | ||
| 100 | #define TAB3 0014000 | ||
| 101 | #define XTABS 0014000 | ||
| 102 | #define BSDLY 0020000 | ||
| 103 | #define BS0 0000000 | ||
| 104 | #define BS1 0020000 | ||
| 105 | #define VTDLY 0040000 | ||
| 106 | #define VT0 0000000 | ||
| 107 | #define VT1 0040000 | ||
| 108 | #define FFDLY 0100000 | ||
| 109 | #define FF0 0000000 | ||
| 110 | #define FF1 0100000 | ||
| 111 | |||
| 112 | /* c_cflag bit meaning */ | ||
| 113 | #define CBAUD 0010017 | ||
| 114 | #define B0 0000000 /* hang up */ | ||
| 115 | #define B50 0000001 | ||
| 116 | #define B75 0000002 | ||
| 117 | #define B110 0000003 | ||
| 118 | #define B134 0000004 | ||
| 119 | #define B150 0000005 | ||
| 120 | #define B200 0000006 | ||
| 121 | #define B300 0000007 | ||
| 122 | #define B600 0000010 | ||
| 123 | #define B1200 0000011 | ||
| 124 | #define B1800 0000012 | ||
| 125 | #define B2400 0000013 | ||
| 126 | #define B4800 0000014 | ||
| 127 | #define B9600 0000015 | ||
| 128 | #define B19200 0000016 | ||
| 129 | #define B38400 0000017 | ||
| 130 | #define EXTA B19200 | ||
| 131 | #define EXTB B38400 | ||
| 132 | #define CSIZE 0000060 | ||
| 133 | #define CS5 0000000 | ||
| 134 | #define CS6 0000020 | ||
| 135 | #define CS7 0000040 | ||
| 136 | #define CS8 0000060 | ||
| 137 | #define CSTOPB 0000100 | ||
| 138 | #define CREAD 0000200 | ||
| 139 | #define PARENB 0000400 | ||
| 140 | #define PARODD 0001000 | ||
| 141 | #define HUPCL 0002000 | ||
| 142 | #define CLOCAL 0004000 | ||
| 143 | #define CBAUDEX 0010000 | ||
| 144 | #define BOTHER 0010000 | ||
| 145 | #define B57600 0010001 | ||
| 146 | #define B115200 0010002 | ||
| 147 | #define B230400 0010003 | ||
| 148 | #define B460800 0010004 | ||
| 149 | #define B500000 0010005 | ||
| 150 | #define B576000 0010006 | ||
| 151 | #define B921600 0010007 | ||
| 152 | #define B1000000 0010010 | ||
| 153 | #define B1152000 0010011 | ||
| 154 | #define B1500000 0010012 | ||
| 155 | #define B2000000 0010013 | ||
| 156 | #define B2500000 0010014 | ||
| 157 | #define B3000000 0010015 | ||
| 158 | #define B3500000 0010016 | ||
| 159 | #define B4000000 0010017 | ||
| 160 | #define CIBAUD 002003600000 /* input baud rate */ | ||
| 161 | #define CMSPAR 010000000000 /* mark or space (stick) parity */ | ||
| 162 | #define CRTSCTS 020000000000 /* flow control */ | ||
| 163 | |||
| 164 | #define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ | ||
| 165 | |||
| 166 | /* c_lflag bits */ | ||
| 167 | #define ISIG 0000001 | ||
| 168 | #define ICANON 0000002 | ||
| 169 | #define XCASE 0000004 | ||
| 170 | #define ECHO 0000010 | ||
| 171 | #define ECHOE 0000020 | ||
| 172 | #define ECHOK 0000040 | ||
| 173 | #define ECHONL 0000100 | ||
| 174 | #define NOFLSH 0000200 | ||
| 175 | #define TOSTOP 0000400 | ||
| 176 | #define ECHOCTL 0001000 | ||
| 177 | #define ECHOPRT 0002000 | ||
| 178 | #define ECHOKE 0004000 | ||
| 179 | #define FLUSHO 0010000 | ||
| 180 | #define PENDIN 0040000 | ||
| 181 | #define IEXTEN 0100000 | ||
| 182 | |||
| 183 | |||
| 184 | /* tcflow() and TCXONC use these */ | ||
| 185 | #define TCOOFF 0 | ||
| 186 | #define TCOON 1 | ||
| 187 | #define TCIOFF 2 | ||
| 188 | #define TCION 3 | ||
| 189 | |||
| 190 | /* tcflush() and TCFLSH use these */ | ||
| 191 | #define TCIFLUSH 0 | ||
| 192 | #define TCOFLUSH 1 | ||
| 193 | #define TCIOFLUSH 2 | ||
| 194 | |||
| 195 | /* tcsetattr uses these */ | ||
| 196 | #define TCSANOW 0 | ||
| 197 | #define TCSADRAIN 1 | ||
| 198 | #define TCSAFLUSH 2 | ||
| 199 | |||
| 200 | #endif /* __ARCH_M68K_TERMBITS_H__ */ | ||
diff --git a/arch/m68k/include/asm/termios.h b/arch/m68k/include/asm/termios.h new file mode 100644 index 000000000000..0823032e4045 --- /dev/null +++ b/arch/m68k/include/asm/termios.h | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | #ifndef _M68K_TERMIOS_H | ||
| 2 | #define _M68K_TERMIOS_H | ||
| 3 | |||
| 4 | #include <asm/termbits.h> | ||
| 5 | #include <asm/ioctls.h> | ||
| 6 | |||
| 7 | struct winsize { | ||
| 8 | unsigned short ws_row; | ||
| 9 | unsigned short ws_col; | ||
| 10 | unsigned short ws_xpixel; | ||
| 11 | unsigned short ws_ypixel; | ||
| 12 | }; | ||
| 13 | |||
| 14 | #define NCC 8 | ||
| 15 | struct termio { | ||
| 16 | unsigned short c_iflag; /* input mode flags */ | ||
| 17 | unsigned short c_oflag; /* output mode flags */ | ||
| 18 | unsigned short c_cflag; /* control mode flags */ | ||
| 19 | unsigned short c_lflag; /* local mode flags */ | ||
| 20 | unsigned char c_line; /* line discipline */ | ||
| 21 | unsigned char c_cc[NCC]; /* control characters */ | ||
| 22 | }; | ||
| 23 | |||
| 24 | #ifdef __KERNEL__ | ||
| 25 | /* intr=^C quit=^| erase=del kill=^U | ||
| 26 | eof=^D vtime=\0 vmin=\1 sxtc=\0 | ||
| 27 | start=^Q stop=^S susp=^Z eol=\0 | ||
| 28 | reprint=^R discard=^U werase=^W lnext=^V | ||
| 29 | eol2=\0 | ||
| 30 | */ | ||
| 31 | #define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" | ||
| 32 | #endif | ||
| 33 | |||
| 34 | /* modem lines */ | ||
| 35 | #define TIOCM_LE 0x001 | ||
| 36 | #define TIOCM_DTR 0x002 | ||
| 37 | #define TIOCM_RTS 0x004 | ||
| 38 | #define TIOCM_ST 0x008 | ||
| 39 | #define TIOCM_SR 0x010 | ||
| 40 | #define TIOCM_CTS 0x020 | ||
| 41 | #define TIOCM_CAR 0x040 | ||
| 42 | #define TIOCM_RNG 0x080 | ||
| 43 | #define TIOCM_DSR 0x100 | ||
| 44 | #define TIOCM_CD TIOCM_CAR | ||
| 45 | #define TIOCM_RI TIOCM_RNG | ||
| 46 | #define TIOCM_OUT1 0x2000 | ||
| 47 | #define TIOCM_OUT2 0x4000 | ||
| 48 | #define TIOCM_LOOP 0x8000 | ||
| 49 | |||
| 50 | /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ | ||
| 51 | |||
| 52 | #ifdef __KERNEL__ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Translate a "termio" structure into a "termios". Ugh. | ||
| 56 | */ | ||
| 57 | #define user_termio_to_kernel_termios(termios, termio) \ | ||
| 58 | ({ \ | ||
| 59 | unsigned short tmp; \ | ||
| 60 | get_user(tmp, &(termio)->c_iflag); \ | ||
| 61 | (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ | ||
| 62 | get_user(tmp, &(termio)->c_oflag); \ | ||
| 63 | (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ | ||
| 64 | get_user(tmp, &(termio)->c_cflag); \ | ||
| 65 | (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ | ||
| 66 | get_user(tmp, &(termio)->c_lflag); \ | ||
| 67 | (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ | ||
| 68 | get_user((termios)->c_line, &(termio)->c_line); \ | ||
| 69 | copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ | ||
| 70 | }) | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Translate a "termios" structure into a "termio". Ugh. | ||
| 74 | */ | ||
| 75 | #define kernel_termios_to_user_termio(termio, termios) \ | ||
| 76 | ({ \ | ||
| 77 | put_user((termios)->c_iflag, &(termio)->c_iflag); \ | ||
| 78 | put_user((termios)->c_oflag, &(termio)->c_oflag); \ | ||
| 79 | put_user((termios)->c_cflag, &(termio)->c_cflag); \ | ||
| 80 | put_user((termios)->c_lflag, &(termio)->c_lflag); \ | ||
| 81 | put_user((termios)->c_line, &(termio)->c_line); \ | ||
| 82 | copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ | ||
| 83 | }) | ||
| 84 | |||
| 85 | #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) | ||
| 86 | #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) | ||
| 87 | #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) | ||
| 88 | #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) | ||
| 89 | |||
| 90 | #endif /* __KERNEL__ */ | ||
| 91 | |||
| 92 | #endif /* _M68K_TERMIOS_H */ | ||
diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h new file mode 100644 index 000000000000..f31a3f42b7b3 --- /dev/null +++ b/arch/m68k/include/asm/thread_info.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "thread_info_no.h" | ||
| 3 | #else | ||
| 4 | #include "thread_info_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/thread_info_mm.h b/arch/m68k/include/asm/thread_info_mm.h new file mode 100644 index 000000000000..af0fda46e94b --- /dev/null +++ b/arch/m68k/include/asm/thread_info_mm.h | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | #ifndef _ASM_M68K_THREAD_INFO_H | ||
| 2 | #define _ASM_M68K_THREAD_INFO_H | ||
| 3 | |||
| 4 | #include <asm/types.h> | ||
| 5 | #include <asm/page.h> | ||
| 6 | |||
| 7 | struct thread_info { | ||
| 8 | struct task_struct *task; /* main task structure */ | ||
| 9 | unsigned long flags; | ||
| 10 | struct exec_domain *exec_domain; /* execution domain */ | ||
| 11 | int preempt_count; /* 0 => preemptable, <0 => BUG */ | ||
| 12 | __u32 cpu; /* should always be 0 on m68k */ | ||
| 13 | struct restart_block restart_block; | ||
| 14 | }; | ||
| 15 | |||
| 16 | #define PREEMPT_ACTIVE 0x4000000 | ||
| 17 | |||
| 18 | #define INIT_THREAD_INFO(tsk) \ | ||
| 19 | { \ | ||
| 20 | .task = &tsk, \ | ||
| 21 | .exec_domain = &default_exec_domain, \ | ||
| 22 | .restart_block = { \ | ||
| 23 | .fn = do_no_restart_syscall, \ | ||
| 24 | }, \ | ||
| 25 | } | ||
| 26 | |||
| 27 | /* THREAD_SIZE should be 8k, so handle differently for 4k and 8k machines */ | ||
| 28 | #define THREAD_SIZE_ORDER (13 - PAGE_SHIFT) | ||
| 29 | |||
| 30 | #define init_thread_info (init_task.thread.info) | ||
| 31 | #define init_stack (init_thread_union.stack) | ||
| 32 | |||
| 33 | #define task_thread_info(tsk) (&(tsk)->thread.info) | ||
| 34 | #define task_stack_page(tsk) ((tsk)->stack) | ||
| 35 | #define current_thread_info() task_thread_info(current) | ||
| 36 | |||
| 37 | #define __HAVE_THREAD_FUNCTIONS | ||
| 38 | |||
| 39 | #define setup_thread_stack(p, org) ({ \ | ||
| 40 | *(struct task_struct **)(p)->stack = (p); \ | ||
| 41 | task_thread_info(p)->task = (p); \ | ||
| 42 | }) | ||
| 43 | |||
| 44 | #define end_of_stack(p) ((unsigned long *)(p)->stack + 1) | ||
| 45 | |||
| 46 | /* entry.S relies on these definitions! | ||
| 47 | * bits 0-7 are tested at every exception exit | ||
| 48 | * bits 8-15 are also tested at syscall exit | ||
| 49 | */ | ||
| 50 | #define TIF_SIGPENDING 6 /* signal pending */ | ||
| 51 | #define TIF_NEED_RESCHED 7 /* rescheduling necessary */ | ||
| 52 | #define TIF_DELAYED_TRACE 14 /* single step a syscall */ | ||
| 53 | #define TIF_SYSCALL_TRACE 15 /* syscall trace active */ | ||
| 54 | #define TIF_MEMDIE 16 | ||
| 55 | #define TIF_FREEZE 17 /* thread is freezing for suspend */ | ||
| 56 | |||
| 57 | #endif /* _ASM_M68K_THREAD_INFO_H */ | ||
diff --git a/arch/m68k/include/asm/thread_info_no.h b/arch/m68k/include/asm/thread_info_no.h new file mode 100644 index 000000000000..82529f424ea3 --- /dev/null +++ b/arch/m68k/include/asm/thread_info_no.h | |||
| @@ -0,0 +1,100 @@ | |||
| 1 | /* thread_info.h: m68knommu low-level thread information | ||
| 2 | * adapted from the i386 and PPC versions by Greg Ungerer (gerg@snapgear.com) | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 David Howells (dhowells@redhat.com) | ||
| 5 | * - Incorporating suggestions made by Linus Torvalds and Dave Miller | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _ASM_THREAD_INFO_H | ||
| 9 | #define _ASM_THREAD_INFO_H | ||
| 10 | |||
| 11 | #include <asm/page.h> | ||
| 12 | |||
| 13 | #ifdef __KERNEL__ | ||
| 14 | |||
| 15 | #ifndef __ASSEMBLY__ | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Size of kernel stack for each process. This must be a power of 2... | ||
| 19 | */ | ||
| 20 | #ifdef CONFIG_4KSTACKS | ||
| 21 | #define THREAD_SIZE_ORDER (0) | ||
| 22 | #else | ||
| 23 | #define THREAD_SIZE_ORDER (1) | ||
| 24 | #endif | ||
| 25 | |||
| 26 | /* | ||
| 27 | * for asm files, THREAD_SIZE is now generated by asm-offsets.c | ||
| 28 | */ | ||
| 29 | #define THREAD_SIZE (PAGE_SIZE<<THREAD_SIZE_ORDER) | ||
| 30 | |||
| 31 | /* | ||
| 32 | * low level task data. | ||
| 33 | */ | ||
| 34 | struct thread_info { | ||
| 35 | struct task_struct *task; /* main task structure */ | ||
| 36 | struct exec_domain *exec_domain; /* execution domain */ | ||
| 37 | unsigned long flags; /* low level flags */ | ||
| 38 | int cpu; /* cpu we're on */ | ||
| 39 | int preempt_count; /* 0 => preemptable, <0 => BUG */ | ||
| 40 | struct restart_block restart_block; | ||
| 41 | }; | ||
| 42 | |||
| 43 | /* | ||
| 44 | * macros/functions for gaining access to the thread information structure | ||
| 45 | */ | ||
| 46 | #define INIT_THREAD_INFO(tsk) \ | ||
| 47 | { \ | ||
| 48 | .task = &tsk, \ | ||
| 49 | .exec_domain = &default_exec_domain, \ | ||
| 50 | .flags = 0, \ | ||
| 51 | .cpu = 0, \ | ||
| 52 | .restart_block = { \ | ||
| 53 | .fn = do_no_restart_syscall, \ | ||
| 54 | }, \ | ||
| 55 | } | ||
| 56 | |||
| 57 | #define init_thread_info (init_thread_union.thread_info) | ||
| 58 | #define init_stack (init_thread_union.stack) | ||
| 59 | |||
| 60 | |||
| 61 | /* how to get the thread information struct from C */ | ||
| 62 | static inline struct thread_info *current_thread_info(void) | ||
| 63 | { | ||
| 64 | struct thread_info *ti; | ||
| 65 | __asm__( | ||
| 66 | "move.l %%sp, %0 \n\t" | ||
| 67 | "and.l %1, %0" | ||
| 68 | : "=&d"(ti) | ||
| 69 | : "di" (~(THREAD_SIZE-1)) | ||
| 70 | ); | ||
| 71 | return ti; | ||
| 72 | } | ||
| 73 | |||
| 74 | #endif /* __ASSEMBLY__ */ | ||
| 75 | |||
| 76 | #define PREEMPT_ACTIVE 0x4000000 | ||
| 77 | |||
| 78 | /* | ||
| 79 | * thread information flag bit numbers | ||
| 80 | */ | ||
| 81 | #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ | ||
| 82 | #define TIF_SIGPENDING 1 /* signal pending */ | ||
| 83 | #define TIF_NEED_RESCHED 2 /* rescheduling necessary */ | ||
| 84 | #define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling | ||
| 85 | TIF_NEED_RESCHED */ | ||
| 86 | #define TIF_MEMDIE 4 | ||
| 87 | #define TIF_FREEZE 16 /* is freezing for suspend */ | ||
| 88 | |||
| 89 | /* as above, but as bit values */ | ||
| 90 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | ||
| 91 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) | ||
| 92 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | ||
| 93 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | ||
| 94 | #define _TIF_FREEZE (1<<TIF_FREEZE) | ||
| 95 | |||
| 96 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ | ||
| 97 | |||
| 98 | #endif /* __KERNEL__ */ | ||
| 99 | |||
| 100 | #endif /* _ASM_THREAD_INFO_H */ | ||
diff --git a/arch/m68k/include/asm/timex.h b/arch/m68k/include/asm/timex.h new file mode 100644 index 000000000000..719762980578 --- /dev/null +++ b/arch/m68k/include/asm/timex.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "timex_no.h" | ||
| 3 | #else | ||
| 4 | #include "timex_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/timex_mm.h b/arch/m68k/include/asm/timex_mm.h new file mode 100644 index 000000000000..b87f2f278f67 --- /dev/null +++ b/arch/m68k/include/asm/timex_mm.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-m68k/timex.h | ||
| 3 | * | ||
| 4 | * m68k architecture timex specifications | ||
| 5 | */ | ||
| 6 | #ifndef _ASMm68k_TIMEX_H | ||
| 7 | #define _ASMm68k_TIMEX_H | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ | ||
| 10 | |||
| 11 | typedef unsigned long cycles_t; | ||
| 12 | |||
| 13 | static inline cycles_t get_cycles(void) | ||
| 14 | { | ||
| 15 | return 0; | ||
| 16 | } | ||
| 17 | |||
| 18 | #endif | ||
diff --git a/arch/m68k/include/asm/timex_no.h b/arch/m68k/include/asm/timex_no.h new file mode 100644 index 000000000000..109050f3fe91 --- /dev/null +++ b/arch/m68k/include/asm/timex_no.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-m68knommu/timex.h | ||
| 3 | * | ||
| 4 | * m68knommu architecture timex specifications | ||
| 5 | */ | ||
| 6 | #ifndef _ASM_M68KNOMMU_TIMEX_H | ||
| 7 | #define _ASM_M68KNOMMU_TIMEX_H | ||
| 8 | |||
| 9 | #ifdef CONFIG_COLDFIRE | ||
| 10 | #include <asm/coldfire.h> | ||
| 11 | #define CLOCK_TICK_RATE MCF_CLK | ||
| 12 | #else | ||
| 13 | #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ | ||
| 14 | #endif | ||
| 15 | |||
| 16 | typedef unsigned long cycles_t; | ||
| 17 | |||
| 18 | static inline cycles_t get_cycles(void) | ||
| 19 | { | ||
| 20 | return 0; | ||
| 21 | } | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/arch/m68k/include/asm/tlb.h b/arch/m68k/include/asm/tlb.h new file mode 100644 index 000000000000..1785cff73449 --- /dev/null +++ b/arch/m68k/include/asm/tlb.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | #ifndef _M68K_TLB_H | ||
| 2 | #define _M68K_TLB_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * m68k doesn't need any special per-pte or | ||
| 6 | * per-vma handling.. | ||
| 7 | */ | ||
| 8 | #define tlb_start_vma(tlb, vma) do { } while (0) | ||
| 9 | #define tlb_end_vma(tlb, vma) do { } while (0) | ||
| 10 | #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) | ||
| 11 | |||
| 12 | /* | ||
| 13 | * .. because we flush the whole mm when it | ||
| 14 | * fills up. | ||
| 15 | */ | ||
| 16 | #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) | ||
| 17 | |||
| 18 | #include <asm-generic/tlb.h> | ||
| 19 | |||
| 20 | #endif /* _M68K_TLB_H */ | ||
diff --git a/arch/m68k/include/asm/tlbflush.h b/arch/m68k/include/asm/tlbflush.h new file mode 100644 index 000000000000..b6f93b30951e --- /dev/null +++ b/arch/m68k/include/asm/tlbflush.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "tlbflush_no.h" | ||
| 3 | #else | ||
| 4 | #include "tlbflush_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/tlbflush_mm.h b/arch/m68k/include/asm/tlbflush_mm.h new file mode 100644 index 000000000000..acb6bf21a321 --- /dev/null +++ b/arch/m68k/include/asm/tlbflush_mm.h | |||
| @@ -0,0 +1,219 @@ | |||
| 1 | #ifndef _M68K_TLBFLUSH_H | ||
| 2 | #define _M68K_TLBFLUSH_H | ||
| 3 | |||
| 4 | |||
| 5 | #ifndef CONFIG_SUN3 | ||
| 6 | |||
| 7 | #include <asm/current.h> | ||
| 8 | |||
| 9 | static inline void flush_tlb_kernel_page(void *addr) | ||
| 10 | { | ||
| 11 | if (CPU_IS_040_OR_060) { | ||
| 12 | mm_segment_t old_fs = get_fs(); | ||
| 13 | set_fs(KERNEL_DS); | ||
| 14 | __asm__ __volatile__(".chip 68040\n\t" | ||
| 15 | "pflush (%0)\n\t" | ||
| 16 | ".chip 68k" | ||
| 17 | : : "a" (addr)); | ||
| 18 | set_fs(old_fs); | ||
| 19 | } else if (CPU_IS_020_OR_030) | ||
| 20 | __asm__ __volatile__("pflush #4,#4,(%0)" : : "a" (addr)); | ||
| 21 | } | ||
| 22 | |||
| 23 | /* | ||
| 24 | * flush all user-space atc entries. | ||
| 25 | */ | ||
| 26 | static inline void __flush_tlb(void) | ||
| 27 | { | ||
| 28 | if (CPU_IS_040_OR_060) | ||
| 29 | __asm__ __volatile__(".chip 68040\n\t" | ||
| 30 | "pflushan\n\t" | ||
| 31 | ".chip 68k"); | ||
| 32 | else if (CPU_IS_020_OR_030) | ||
| 33 | __asm__ __volatile__("pflush #0,#4"); | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline void __flush_tlb040_one(unsigned long addr) | ||
| 37 | { | ||
| 38 | __asm__ __volatile__(".chip 68040\n\t" | ||
| 39 | "pflush (%0)\n\t" | ||
| 40 | ".chip 68k" | ||
| 41 | : : "a" (addr)); | ||
| 42 | } | ||
| 43 | |||
| 44 | static inline void __flush_tlb_one(unsigned long addr) | ||
| 45 | { | ||
| 46 | if (CPU_IS_040_OR_060) | ||
| 47 | __flush_tlb040_one(addr); | ||
| 48 | else if (CPU_IS_020_OR_030) | ||
| 49 | __asm__ __volatile__("pflush #0,#4,(%0)" : : "a" (addr)); | ||
| 50 | } | ||
| 51 | |||
| 52 | #define flush_tlb() __flush_tlb() | ||
| 53 | |||
| 54 | /* | ||
| 55 | * flush all atc entries (both kernel and user-space entries). | ||
| 56 | */ | ||
| 57 | static inline void flush_tlb_all(void) | ||
| 58 | { | ||
| 59 | if (CPU_IS_040_OR_060) | ||
| 60 | __asm__ __volatile__(".chip 68040\n\t" | ||
| 61 | "pflusha\n\t" | ||
| 62 | ".chip 68k"); | ||
| 63 | else if (CPU_IS_020_OR_030) | ||
| 64 | __asm__ __volatile__("pflusha"); | ||
| 65 | } | ||
| 66 | |||
| 67 | static inline void flush_tlb_mm(struct mm_struct *mm) | ||
| 68 | { | ||
| 69 | if (mm == current->active_mm) | ||
| 70 | __flush_tlb(); | ||
| 71 | } | ||
| 72 | |||
| 73 | static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) | ||
| 74 | { | ||
| 75 | if (vma->vm_mm == current->active_mm) { | ||
| 76 | mm_segment_t old_fs = get_fs(); | ||
| 77 | set_fs(USER_DS); | ||
| 78 | __flush_tlb_one(addr); | ||
| 79 | set_fs(old_fs); | ||
| 80 | } | ||
| 81 | } | ||
| 82 | |||
| 83 | static inline void flush_tlb_range(struct vm_area_struct *vma, | ||
| 84 | unsigned long start, unsigned long end) | ||
| 85 | { | ||
| 86 | if (vma->vm_mm == current->active_mm) | ||
| 87 | __flush_tlb(); | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) | ||
| 91 | { | ||
| 92 | flush_tlb_all(); | ||
| 93 | } | ||
| 94 | |||
| 95 | #else | ||
| 96 | |||
| 97 | |||
| 98 | /* Reserved PMEGs. */ | ||
| 99 | extern char sun3_reserved_pmeg[SUN3_PMEGS_NUM]; | ||
| 100 | extern unsigned long pmeg_vaddr[SUN3_PMEGS_NUM]; | ||
| 101 | extern unsigned char pmeg_alloc[SUN3_PMEGS_NUM]; | ||
| 102 | extern unsigned char pmeg_ctx[SUN3_PMEGS_NUM]; | ||
| 103 | |||
| 104 | /* Flush all userspace mappings one by one... (why no flush command, | ||
| 105 | sun?) */ | ||
| 106 | static inline void flush_tlb_all(void) | ||
| 107 | { | ||
| 108 | unsigned long addr; | ||
| 109 | unsigned char ctx, oldctx; | ||
| 110 | |||
| 111 | oldctx = sun3_get_context(); | ||
| 112 | for(addr = 0x00000000; addr < TASK_SIZE; addr += SUN3_PMEG_SIZE) { | ||
| 113 | for(ctx = 0; ctx < 8; ctx++) { | ||
| 114 | sun3_put_context(ctx); | ||
| 115 | sun3_put_segmap(addr, SUN3_INVALID_PMEG); | ||
| 116 | } | ||
| 117 | } | ||
| 118 | |||
| 119 | sun3_put_context(oldctx); | ||
| 120 | /* erase all of the userspace pmeg maps, we've clobbered them | ||
| 121 | all anyway */ | ||
| 122 | for(addr = 0; addr < SUN3_INVALID_PMEG; addr++) { | ||
| 123 | if(pmeg_alloc[addr] == 1) { | ||
| 124 | pmeg_alloc[addr] = 0; | ||
| 125 | pmeg_ctx[addr] = 0; | ||
| 126 | pmeg_vaddr[addr] = 0; | ||
| 127 | } | ||
| 128 | } | ||
| 129 | |||
| 130 | } | ||
| 131 | |||
| 132 | /* Clear user TLB entries within the context named in mm */ | ||
| 133 | static inline void flush_tlb_mm (struct mm_struct *mm) | ||
| 134 | { | ||
| 135 | unsigned char oldctx; | ||
| 136 | unsigned char seg; | ||
| 137 | unsigned long i; | ||
| 138 | |||
| 139 | oldctx = sun3_get_context(); | ||
| 140 | sun3_put_context(mm->context); | ||
| 141 | |||
| 142 | for(i = 0; i < TASK_SIZE; i += SUN3_PMEG_SIZE) { | ||
| 143 | seg = sun3_get_segmap(i); | ||
| 144 | if(seg == SUN3_INVALID_PMEG) | ||
| 145 | continue; | ||
| 146 | |||
| 147 | sun3_put_segmap(i, SUN3_INVALID_PMEG); | ||
| 148 | pmeg_alloc[seg] = 0; | ||
| 149 | pmeg_ctx[seg] = 0; | ||
| 150 | pmeg_vaddr[seg] = 0; | ||
| 151 | } | ||
| 152 | |||
| 153 | sun3_put_context(oldctx); | ||
| 154 | |||
| 155 | } | ||
| 156 | |||
| 157 | /* Flush a single TLB page. In this case, we're limited to flushing a | ||
| 158 | single PMEG */ | ||
| 159 | static inline void flush_tlb_page (struct vm_area_struct *vma, | ||
| 160 | unsigned long addr) | ||
| 161 | { | ||
| 162 | unsigned char oldctx; | ||
| 163 | unsigned char i; | ||
| 164 | |||
| 165 | oldctx = sun3_get_context(); | ||
| 166 | sun3_put_context(vma->vm_mm->context); | ||
| 167 | addr &= ~SUN3_PMEG_MASK; | ||
| 168 | if((i = sun3_get_segmap(addr)) != SUN3_INVALID_PMEG) | ||
| 169 | { | ||
| 170 | pmeg_alloc[i] = 0; | ||
| 171 | pmeg_ctx[i] = 0; | ||
| 172 | pmeg_vaddr[i] = 0; | ||
| 173 | sun3_put_segmap (addr, SUN3_INVALID_PMEG); | ||
| 174 | } | ||
| 175 | sun3_put_context(oldctx); | ||
| 176 | |||
| 177 | } | ||
| 178 | /* Flush a range of pages from TLB. */ | ||
| 179 | |||
| 180 | static inline void flush_tlb_range (struct vm_area_struct *vma, | ||
| 181 | unsigned long start, unsigned long end) | ||
| 182 | { | ||
| 183 | struct mm_struct *mm = vma->vm_mm; | ||
| 184 | unsigned char seg, oldctx; | ||
| 185 | |||
| 186 | start &= ~SUN3_PMEG_MASK; | ||
| 187 | |||
| 188 | oldctx = sun3_get_context(); | ||
| 189 | sun3_put_context(mm->context); | ||
| 190 | |||
| 191 | while(start < end) | ||
| 192 | { | ||
| 193 | if((seg = sun3_get_segmap(start)) == SUN3_INVALID_PMEG) | ||
| 194 | goto next; | ||
| 195 | if(pmeg_ctx[seg] == mm->context) { | ||
| 196 | pmeg_alloc[seg] = 0; | ||
| 197 | pmeg_ctx[seg] = 0; | ||
| 198 | pmeg_vaddr[seg] = 0; | ||
| 199 | } | ||
| 200 | sun3_put_segmap(start, SUN3_INVALID_PMEG); | ||
| 201 | next: | ||
| 202 | start += SUN3_PMEG_SIZE; | ||
| 203 | } | ||
| 204 | } | ||
| 205 | |||
| 206 | static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) | ||
| 207 | { | ||
| 208 | flush_tlb_all(); | ||
| 209 | } | ||
| 210 | |||
| 211 | /* Flush kernel page from TLB. */ | ||
| 212 | static inline void flush_tlb_kernel_page (unsigned long addr) | ||
| 213 | { | ||
| 214 | sun3_put_segmap (addr & ~(SUN3_PMEG_SIZE - 1), SUN3_INVALID_PMEG); | ||
| 215 | } | ||
| 216 | |||
| 217 | #endif | ||
| 218 | |||
| 219 | #endif /* _M68K_TLBFLUSH_H */ | ||
diff --git a/arch/m68k/include/asm/tlbflush_no.h b/arch/m68k/include/asm/tlbflush_no.h new file mode 100644 index 000000000000..a470cfb803eb --- /dev/null +++ b/arch/m68k/include/asm/tlbflush_no.h | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | #ifndef _M68KNOMMU_TLBFLUSH_H | ||
| 2 | #define _M68KNOMMU_TLBFLUSH_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org> | ||
| 6 | * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com> | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/setup.h> | ||
| 10 | |||
| 11 | /* | ||
| 12 | * flush all user-space atc entries. | ||
| 13 | */ | ||
| 14 | static inline void __flush_tlb(void) | ||
| 15 | { | ||
| 16 | BUG(); | ||
| 17 | } | ||
| 18 | |||
| 19 | static inline void __flush_tlb_one(unsigned long addr) | ||
| 20 | { | ||
| 21 | BUG(); | ||
| 22 | } | ||
| 23 | |||
| 24 | #define flush_tlb() __flush_tlb() | ||
| 25 | |||
| 26 | /* | ||
| 27 | * flush all atc entries (both kernel and user-space entries). | ||
| 28 | */ | ||
| 29 | static inline void flush_tlb_all(void) | ||
| 30 | { | ||
| 31 | BUG(); | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void flush_tlb_mm(struct mm_struct *mm) | ||
| 35 | { | ||
| 36 | BUG(); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) | ||
| 40 | { | ||
| 41 | BUG(); | ||
| 42 | } | ||
| 43 | |||
| 44 | static inline void flush_tlb_range(struct mm_struct *mm, | ||
| 45 | unsigned long start, unsigned long end) | ||
| 46 | { | ||
| 47 | BUG(); | ||
| 48 | } | ||
| 49 | |||
| 50 | static inline void flush_tlb_kernel_page(unsigned long addr) | ||
| 51 | { | ||
| 52 | BUG(); | ||
| 53 | } | ||
| 54 | |||
| 55 | #endif /* _M68KNOMMU_TLBFLUSH_H */ | ||
diff --git a/arch/m68k/include/asm/topology.h b/arch/m68k/include/asm/topology.h new file mode 100644 index 000000000000..ca173e9f26ff --- /dev/null +++ b/arch/m68k/include/asm/topology.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef _ASM_M68K_TOPOLOGY_H | ||
| 2 | #define _ASM_M68K_TOPOLOGY_H | ||
| 3 | |||
| 4 | #include <asm-generic/topology.h> | ||
| 5 | |||
| 6 | #endif /* _ASM_M68K_TOPOLOGY_H */ | ||
diff --git a/arch/m68k/include/asm/traps.h b/arch/m68k/include/asm/traps.h new file mode 100644 index 000000000000..3011ec0f5365 --- /dev/null +++ b/arch/m68k/include/asm/traps.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "traps_no.h" | ||
| 3 | #else | ||
| 4 | #include "traps_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/traps_mm.h b/arch/m68k/include/asm/traps_mm.h new file mode 100644 index 000000000000..8caef25624c7 --- /dev/null +++ b/arch/m68k/include/asm/traps_mm.h | |||
| @@ -0,0 +1,272 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm/traps.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1993 Hamish Macdonald | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef _M68K_TRAPS_H | ||
| 12 | #define _M68K_TRAPS_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | #include <linux/linkage.h> | ||
| 17 | #include <asm/ptrace.h> | ||
| 18 | |||
| 19 | typedef void (*e_vector)(void); | ||
| 20 | |||
| 21 | asmlinkage void auto_inthandler(void); | ||
| 22 | asmlinkage void user_inthandler(void); | ||
| 23 | asmlinkage void bad_inthandler(void); | ||
| 24 | |||
| 25 | extern e_vector vectors[]; | ||
| 26 | |||
| 27 | #endif | ||
| 28 | |||
| 29 | #define VEC_RESETSP (0) | ||
| 30 | #define VEC_RESETPC (1) | ||
| 31 | #define VEC_BUSERR (2) | ||
| 32 | #define VEC_ADDRERR (3) | ||
| 33 | #define VEC_ILLEGAL (4) | ||
| 34 | #define VEC_ZERODIV (5) | ||
| 35 | #define VEC_CHK (6) | ||
| 36 | #define VEC_TRAP (7) | ||
| 37 | #define VEC_PRIV (8) | ||
| 38 | #define VEC_TRACE (9) | ||
| 39 | #define VEC_LINE10 (10) | ||
| 40 | #define VEC_LINE11 (11) | ||
| 41 | #define VEC_RESV12 (12) | ||
| 42 | #define VEC_COPROC (13) | ||
| 43 | #define VEC_FORMAT (14) | ||
| 44 | #define VEC_UNINT (15) | ||
| 45 | #define VEC_RESV16 (16) | ||
| 46 | #define VEC_RESV17 (17) | ||
| 47 | #define VEC_RESV18 (18) | ||
| 48 | #define VEC_RESV19 (19) | ||
| 49 | #define VEC_RESV20 (20) | ||
| 50 | #define VEC_RESV21 (21) | ||
| 51 | #define VEC_RESV22 (22) | ||
| 52 | #define VEC_RESV23 (23) | ||
| 53 | #define VEC_SPUR (24) | ||
| 54 | #define VEC_INT1 (25) | ||
| 55 | #define VEC_INT2 (26) | ||
| 56 | #define VEC_INT3 (27) | ||
| 57 | #define VEC_INT4 (28) | ||
| 58 | #define VEC_INT5 (29) | ||
| 59 | #define VEC_INT6 (30) | ||
| 60 | #define VEC_INT7 (31) | ||
| 61 | #define VEC_SYS (32) | ||
| 62 | #define VEC_TRAP1 (33) | ||
| 63 | #define VEC_TRAP2 (34) | ||
| 64 | #define VEC_TRAP3 (35) | ||
| 65 | #define VEC_TRAP4 (36) | ||
| 66 | #define VEC_TRAP5 (37) | ||
| 67 | #define VEC_TRAP6 (38) | ||
| 68 | #define VEC_TRAP7 (39) | ||
| 69 | #define VEC_TRAP8 (40) | ||
| 70 | #define VEC_TRAP9 (41) | ||
| 71 | #define VEC_TRAP10 (42) | ||
| 72 | #define VEC_TRAP11 (43) | ||
| 73 | #define VEC_TRAP12 (44) | ||
| 74 | #define VEC_TRAP13 (45) | ||
| 75 | #define VEC_TRAP14 (46) | ||
| 76 | #define VEC_TRAP15 (47) | ||
| 77 | #define VEC_FPBRUC (48) | ||
| 78 | #define VEC_FPIR (49) | ||
| 79 | #define VEC_FPDIVZ (50) | ||
| 80 | #define VEC_FPUNDER (51) | ||
| 81 | #define VEC_FPOE (52) | ||
| 82 | #define VEC_FPOVER (53) | ||
| 83 | #define VEC_FPNAN (54) | ||
| 84 | #define VEC_FPUNSUP (55) | ||
| 85 | #define VEC_MMUCFG (56) | ||
| 86 | #define VEC_MMUILL (57) | ||
| 87 | #define VEC_MMUACC (58) | ||
| 88 | #define VEC_RESV59 (59) | ||
| 89 | #define VEC_UNIMPEA (60) | ||
| 90 | #define VEC_UNIMPII (61) | ||
| 91 | #define VEC_RESV62 (62) | ||
| 92 | #define VEC_RESV63 (63) | ||
| 93 | #define VEC_USER (64) | ||
| 94 | |||
| 95 | #define VECOFF(vec) ((vec)<<2) | ||
| 96 | |||
| 97 | #ifndef __ASSEMBLY__ | ||
| 98 | |||
| 99 | /* Status register bits */ | ||
| 100 | #define PS_T (0x8000) | ||
| 101 | #define PS_S (0x2000) | ||
| 102 | #define PS_M (0x1000) | ||
| 103 | #define PS_C (0x0001) | ||
| 104 | |||
| 105 | /* bits for 68020/68030 special status word */ | ||
| 106 | |||
| 107 | #define FC (0x8000) | ||
| 108 | #define FB (0x4000) | ||
| 109 | #define RC (0x2000) | ||
| 110 | #define RB (0x1000) | ||
| 111 | #define DF (0x0100) | ||
| 112 | #define RM (0x0080) | ||
| 113 | #define RW (0x0040) | ||
| 114 | #define SZ (0x0030) | ||
| 115 | #define DFC (0x0007) | ||
| 116 | |||
| 117 | /* bits for 68030 MMU status register (mmusr,psr) */ | ||
| 118 | |||
| 119 | #define MMU_B (0x8000) /* bus error */ | ||
| 120 | #define MMU_L (0x4000) /* limit violation */ | ||
| 121 | #define MMU_S (0x2000) /* supervisor violation */ | ||
| 122 | #define MMU_WP (0x0800) /* write-protected */ | ||
| 123 | #define MMU_I (0x0400) /* invalid descriptor */ | ||
| 124 | #define MMU_M (0x0200) /* ATC entry modified */ | ||
| 125 | #define MMU_T (0x0040) /* transparent translation */ | ||
| 126 | #define MMU_NUM (0x0007) /* number of levels traversed */ | ||
| 127 | |||
| 128 | |||
| 129 | /* bits for 68040 special status word */ | ||
| 130 | #define CP_040 (0x8000) | ||
| 131 | #define CU_040 (0x4000) | ||
| 132 | #define CT_040 (0x2000) | ||
| 133 | #define CM_040 (0x1000) | ||
| 134 | #define MA_040 (0x0800) | ||
| 135 | #define ATC_040 (0x0400) | ||
| 136 | #define LK_040 (0x0200) | ||
| 137 | #define RW_040 (0x0100) | ||
| 138 | #define SIZ_040 (0x0060) | ||
| 139 | #define TT_040 (0x0018) | ||
| 140 | #define TM_040 (0x0007) | ||
| 141 | |||
| 142 | /* bits for 68040 write back status word */ | ||
| 143 | #define WBV_040 (0x80) | ||
| 144 | #define WBSIZ_040 (0x60) | ||
| 145 | #define WBBYT_040 (0x20) | ||
| 146 | #define WBWRD_040 (0x40) | ||
| 147 | #define WBLNG_040 (0x00) | ||
| 148 | #define WBTT_040 (0x18) | ||
| 149 | #define WBTM_040 (0x07) | ||
| 150 | |||
| 151 | /* bus access size codes */ | ||
| 152 | #define BA_SIZE_BYTE (0x20) | ||
| 153 | #define BA_SIZE_WORD (0x40) | ||
| 154 | #define BA_SIZE_LONG (0x00) | ||
| 155 | #define BA_SIZE_LINE (0x60) | ||
| 156 | |||
| 157 | /* bus access transfer type codes */ | ||
| 158 | #define BA_TT_MOVE16 (0x08) | ||
| 159 | |||
| 160 | /* bits for 68040 MMU status register (mmusr) */ | ||
| 161 | #define MMU_B_040 (0x0800) | ||
| 162 | #define MMU_G_040 (0x0400) | ||
| 163 | #define MMU_S_040 (0x0080) | ||
| 164 | #define MMU_CM_040 (0x0060) | ||
| 165 | #define MMU_M_040 (0x0010) | ||
| 166 | #define MMU_WP_040 (0x0004) | ||
| 167 | #define MMU_T_040 (0x0002) | ||
| 168 | #define MMU_R_040 (0x0001) | ||
| 169 | |||
| 170 | /* bits in the 68060 fault status long word (FSLW) */ | ||
| 171 | #define MMU060_MA (0x08000000) /* misaligned */ | ||
| 172 | #define MMU060_LK (0x02000000) /* locked transfer */ | ||
| 173 | #define MMU060_RW (0x01800000) /* read/write */ | ||
| 174 | # define MMU060_RW_W (0x00800000) /* write */ | ||
| 175 | # define MMU060_RW_R (0x01000000) /* read */ | ||
| 176 | # define MMU060_RW_RMW (0x01800000) /* read/modify/write */ | ||
| 177 | # define MMU060_W (0x00800000) /* general write, includes rmw */ | ||
| 178 | #define MMU060_SIZ (0x00600000) /* transfer size */ | ||
| 179 | #define MMU060_TT (0x00180000) /* transfer type (TT) bits */ | ||
| 180 | #define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */ | ||
| 181 | #define MMU060_IO (0x00008000) /* instruction or operand */ | ||
| 182 | #define MMU060_PBE (0x00004000) /* push buffer bus error */ | ||
| 183 | #define MMU060_SBE (0x00002000) /* store buffer bus error */ | ||
| 184 | #define MMU060_PTA (0x00001000) /* pointer A fault */ | ||
| 185 | #define MMU060_PTB (0x00000800) /* pointer B fault */ | ||
| 186 | #define MMU060_IL (0x00000400) /* double indirect descr fault */ | ||
| 187 | #define MMU060_PF (0x00000200) /* page fault (invalid descr) */ | ||
| 188 | #define MMU060_SP (0x00000100) /* supervisor protection */ | ||
| 189 | #define MMU060_WP (0x00000080) /* write protection */ | ||
| 190 | #define MMU060_TWE (0x00000040) /* bus error on table search */ | ||
| 191 | #define MMU060_RE (0x00000020) /* bus error on read */ | ||
| 192 | #define MMU060_WE (0x00000010) /* bus error on write */ | ||
| 193 | #define MMU060_TTR (0x00000008) /* error caused by TTR translation */ | ||
| 194 | #define MMU060_BPE (0x00000004) /* branch prediction error */ | ||
| 195 | #define MMU060_SEE (0x00000001) /* software emulated error */ | ||
| 196 | |||
| 197 | /* cases of missing or invalid descriptors */ | ||
| 198 | #define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \ | ||
| 199 | MMU060_IL | MMU060_PF) | ||
| 200 | /* bits that indicate real errors */ | ||
| 201 | #define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \ | ||
| 202 | MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE) | ||
| 203 | |||
| 204 | /* structure for stack frames */ | ||
| 205 | |||
| 206 | struct frame { | ||
| 207 | struct pt_regs ptregs; | ||
| 208 | union { | ||
| 209 | struct { | ||
| 210 | unsigned long iaddr; /* instruction address */ | ||
| 211 | } fmt2; | ||
| 212 | struct { | ||
| 213 | unsigned long effaddr; /* effective address */ | ||
| 214 | } fmt3; | ||
| 215 | struct { | ||
| 216 | unsigned long effaddr; /* effective address */ | ||
| 217 | unsigned long pc; /* pc of faulted instr */ | ||
| 218 | } fmt4; | ||
| 219 | struct { | ||
| 220 | unsigned long effaddr; /* effective address */ | ||
| 221 | unsigned short ssw; /* special status word */ | ||
| 222 | unsigned short wb3s; /* write back 3 status */ | ||
| 223 | unsigned short wb2s; /* write back 2 status */ | ||
| 224 | unsigned short wb1s; /* write back 1 status */ | ||
| 225 | unsigned long faddr; /* fault address */ | ||
| 226 | unsigned long wb3a; /* write back 3 address */ | ||
| 227 | unsigned long wb3d; /* write back 3 data */ | ||
| 228 | unsigned long wb2a; /* write back 2 address */ | ||
| 229 | unsigned long wb2d; /* write back 2 data */ | ||
| 230 | unsigned long wb1a; /* write back 1 address */ | ||
| 231 | unsigned long wb1dpd0; /* write back 1 data/push data 0*/ | ||
| 232 | unsigned long pd1; /* push data 1*/ | ||
| 233 | unsigned long pd2; /* push data 2*/ | ||
| 234 | unsigned long pd3; /* push data 3*/ | ||
| 235 | } fmt7; | ||
| 236 | struct { | ||
| 237 | unsigned long iaddr; /* instruction address */ | ||
| 238 | unsigned short int1[4]; /* internal registers */ | ||
| 239 | } fmt9; | ||
| 240 | struct { | ||
| 241 | unsigned short int1; | ||
| 242 | unsigned short ssw; /* special status word */ | ||
| 243 | unsigned short isc; /* instruction stage c */ | ||
| 244 | unsigned short isb; /* instruction stage b */ | ||
| 245 | unsigned long daddr; /* data cycle fault address */ | ||
| 246 | unsigned short int2[2]; | ||
| 247 | unsigned long dobuf; /* data cycle output buffer */ | ||
| 248 | unsigned short int3[2]; | ||
| 249 | } fmta; | ||
| 250 | struct { | ||
| 251 | unsigned short int1; | ||
| 252 | unsigned short ssw; /* special status word */ | ||
| 253 | unsigned short isc; /* instruction stage c */ | ||
| 254 | unsigned short isb; /* instruction stage b */ | ||
| 255 | unsigned long daddr; /* data cycle fault address */ | ||
| 256 | unsigned short int2[2]; | ||
| 257 | unsigned long dobuf; /* data cycle output buffer */ | ||
| 258 | unsigned short int3[4]; | ||
| 259 | unsigned long baddr; /* stage B address */ | ||
| 260 | unsigned short int4[2]; | ||
| 261 | unsigned long dibuf; /* data cycle input buffer */ | ||
| 262 | unsigned short int5[3]; | ||
| 263 | unsigned ver : 4; /* stack frame version # */ | ||
| 264 | unsigned int6:12; | ||
| 265 | unsigned short int7[18]; | ||
| 266 | } fmtb; | ||
| 267 | } un; | ||
| 268 | }; | ||
| 269 | |||
| 270 | #endif /* __ASSEMBLY__ */ | ||
| 271 | |||
| 272 | #endif /* _M68K_TRAPS_H */ | ||
diff --git a/arch/m68k/include/asm/traps_no.h b/arch/m68k/include/asm/traps_no.h new file mode 100644 index 000000000000..d0671e5f8e29 --- /dev/null +++ b/arch/m68k/include/asm/traps_no.h | |||
| @@ -0,0 +1,154 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm/traps.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1993 Hamish Macdonald | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive | ||
| 8 | * for more details. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef _M68KNOMMU_TRAPS_H | ||
| 12 | #define _M68KNOMMU_TRAPS_H | ||
| 13 | |||
| 14 | #ifndef __ASSEMBLY__ | ||
| 15 | |||
| 16 | typedef void (*e_vector)(void); | ||
| 17 | |||
| 18 | extern e_vector vectors[]; | ||
| 19 | extern void init_vectors(void); | ||
| 20 | extern void enable_vector(unsigned int irq); | ||
| 21 | extern void disable_vector(unsigned int irq); | ||
| 22 | extern void ack_vector(unsigned int irq); | ||
| 23 | |||
| 24 | #endif | ||
| 25 | |||
| 26 | #define VEC_BUSERR (2) | ||
| 27 | #define VEC_ADDRERR (3) | ||
| 28 | #define VEC_ILLEGAL (4) | ||
| 29 | #define VEC_ZERODIV (5) | ||
| 30 | #define VEC_CHK (6) | ||
| 31 | #define VEC_TRAP (7) | ||
| 32 | #define VEC_PRIV (8) | ||
| 33 | #define VEC_TRACE (9) | ||
| 34 | #define VEC_LINE10 (10) | ||
| 35 | #define VEC_LINE11 (11) | ||
| 36 | #define VEC_RESV1 (12) | ||
| 37 | #define VEC_COPROC (13) | ||
| 38 | #define VEC_FORMAT (14) | ||
| 39 | #define VEC_UNINT (15) | ||
| 40 | #define VEC_SPUR (24) | ||
| 41 | #define VEC_INT1 (25) | ||
| 42 | #define VEC_INT2 (26) | ||
| 43 | #define VEC_INT3 (27) | ||
| 44 | #define VEC_INT4 (28) | ||
| 45 | #define VEC_INT5 (29) | ||
| 46 | #define VEC_INT6 (30) | ||
| 47 | #define VEC_INT7 (31) | ||
| 48 | #define VEC_SYS (32) | ||
| 49 | #define VEC_TRAP1 (33) | ||
| 50 | #define VEC_TRAP2 (34) | ||
| 51 | #define VEC_TRAP3 (35) | ||
| 52 | #define VEC_TRAP4 (36) | ||
| 53 | #define VEC_TRAP5 (37) | ||
| 54 | #define VEC_TRAP6 (38) | ||
| 55 | #define VEC_TRAP7 (39) | ||
| 56 | #define VEC_TRAP8 (40) | ||
| 57 | #define VEC_TRAP9 (41) | ||
| 58 | #define VEC_TRAP10 (42) | ||
| 59 | #define VEC_TRAP11 (43) | ||
| 60 | #define VEC_TRAP12 (44) | ||
| 61 | #define VEC_TRAP13 (45) | ||
| 62 | #define VEC_TRAP14 (46) | ||
| 63 | #define VEC_TRAP15 (47) | ||
| 64 | #define VEC_FPBRUC (48) | ||
| 65 | #define VEC_FPIR (49) | ||
| 66 | #define VEC_FPDIVZ (50) | ||
| 67 | #define VEC_FPUNDER (51) | ||
| 68 | #define VEC_FPOE (52) | ||
| 69 | #define VEC_FPOVER (53) | ||
| 70 | #define VEC_FPNAN (54) | ||
| 71 | #define VEC_FPUNSUP (55) | ||
| 72 | #define VEC_UNIMPEA (60) | ||
| 73 | #define VEC_UNIMPII (61) | ||
| 74 | #define VEC_USER (64) | ||
| 75 | |||
| 76 | #define VECOFF(vec) ((vec)<<2) | ||
| 77 | |||
| 78 | #ifndef __ASSEMBLY__ | ||
| 79 | |||
| 80 | /* Status register bits */ | ||
| 81 | #define PS_T (0x8000) | ||
| 82 | #define PS_S (0x2000) | ||
| 83 | #define PS_M (0x1000) | ||
| 84 | #define PS_C (0x0001) | ||
| 85 | |||
| 86 | /* structure for stack frames */ | ||
| 87 | |||
| 88 | struct frame { | ||
| 89 | struct pt_regs ptregs; | ||
| 90 | union { | ||
| 91 | struct { | ||
| 92 | unsigned long iaddr; /* instruction address */ | ||
| 93 | } fmt2; | ||
| 94 | struct { | ||
| 95 | unsigned long effaddr; /* effective address */ | ||
| 96 | } fmt3; | ||
| 97 | struct { | ||
| 98 | unsigned long effaddr; /* effective address */ | ||
| 99 | unsigned long pc; /* pc of faulted instr */ | ||
| 100 | } fmt4; | ||
| 101 | struct { | ||
| 102 | unsigned long effaddr; /* effective address */ | ||
| 103 | unsigned short ssw; /* special status word */ | ||
| 104 | unsigned short wb3s; /* write back 3 status */ | ||
| 105 | unsigned short wb2s; /* write back 2 status */ | ||
| 106 | unsigned short wb1s; /* write back 1 status */ | ||
| 107 | unsigned long faddr; /* fault address */ | ||
| 108 | unsigned long wb3a; /* write back 3 address */ | ||
| 109 | unsigned long wb3d; /* write back 3 data */ | ||
| 110 | unsigned long wb2a; /* write back 2 address */ | ||
| 111 | unsigned long wb2d; /* write back 2 data */ | ||
| 112 | unsigned long wb1a; /* write back 1 address */ | ||
| 113 | unsigned long wb1dpd0; /* write back 1 data/push data 0*/ | ||
| 114 | unsigned long pd1; /* push data 1*/ | ||
| 115 | unsigned long pd2; /* push data 2*/ | ||
| 116 | unsigned long pd3; /* push data 3*/ | ||
| 117 | } fmt7; | ||
| 118 | struct { | ||
| 119 | unsigned long iaddr; /* instruction address */ | ||
| 120 | unsigned short int1[4]; /* internal registers */ | ||
| 121 | } fmt9; | ||
| 122 | struct { | ||
| 123 | unsigned short int1; | ||
| 124 | unsigned short ssw; /* special status word */ | ||
| 125 | unsigned short isc; /* instruction stage c */ | ||
| 126 | unsigned short isb; /* instruction stage b */ | ||
| 127 | unsigned long daddr; /* data cycle fault address */ | ||
| 128 | unsigned short int2[2]; | ||
| 129 | unsigned long dobuf; /* data cycle output buffer */ | ||
| 130 | unsigned short int3[2]; | ||
| 131 | } fmta; | ||
| 132 | struct { | ||
| 133 | unsigned short int1; | ||
| 134 | unsigned short ssw; /* special status word */ | ||
| 135 | unsigned short isc; /* instruction stage c */ | ||
| 136 | unsigned short isb; /* instruction stage b */ | ||
| 137 | unsigned long daddr; /* data cycle fault address */ | ||
| 138 | unsigned short int2[2]; | ||
| 139 | unsigned long dobuf; /* data cycle output buffer */ | ||
| 140 | unsigned short int3[4]; | ||
| 141 | unsigned long baddr; /* stage B address */ | ||
| 142 | unsigned short int4[2]; | ||
| 143 | unsigned long dibuf; /* data cycle input buffer */ | ||
| 144 | unsigned short int5[3]; | ||
| 145 | unsigned ver : 4; /* stack frame version # */ | ||
| 146 | unsigned int6:12; | ||
| 147 | unsigned short int7[18]; | ||
| 148 | } fmtb; | ||
| 149 | } un; | ||
| 150 | }; | ||
| 151 | |||
| 152 | #endif /* __ASSEMBLY__ */ | ||
| 153 | |||
| 154 | #endif /* _M68KNOMMU_TRAPS_H */ | ||
diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h new file mode 100644 index 000000000000..6441cb5f8e7c --- /dev/null +++ b/arch/m68k/include/asm/types.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | #ifndef _M68K_TYPES_H | ||
| 2 | #define _M68K_TYPES_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file is never included by application software unless | ||
| 6 | * explicitly requested (e.g., via linux/types.h) in which case the | ||
| 7 | * application is Linux specific so (user-) name space pollution is | ||
| 8 | * not a major issue. However, for interoperability, libraries still | ||
| 9 | * need to be careful to avoid a name clashes. | ||
| 10 | */ | ||
| 11 | #include <asm-generic/int-ll64.h> | ||
| 12 | |||
| 13 | #ifndef __ASSEMBLY__ | ||
| 14 | |||
| 15 | typedef unsigned short umode_t; | ||
| 16 | |||
| 17 | #endif /* __ASSEMBLY__ */ | ||
| 18 | |||
| 19 | /* | ||
| 20 | * These aren't exported outside the kernel to avoid name space clashes | ||
| 21 | */ | ||
| 22 | #ifdef __KERNEL__ | ||
| 23 | |||
| 24 | #define BITS_PER_LONG 32 | ||
| 25 | |||
| 26 | #ifndef __ASSEMBLY__ | ||
| 27 | |||
| 28 | /* DMA addresses are always 32-bits wide */ | ||
| 29 | |||
| 30 | typedef u32 dma_addr_t; | ||
| 31 | typedef u32 dma64_addr_t; | ||
| 32 | |||
| 33 | #endif /* __ASSEMBLY__ */ | ||
| 34 | |||
| 35 | #endif /* __KERNEL__ */ | ||
| 36 | |||
| 37 | #endif /* _M68K_TYPES_H */ | ||
diff --git a/arch/m68k/include/asm/uaccess.h b/arch/m68k/include/asm/uaccess.h new file mode 100644 index 000000000000..38f92dbb9a45 --- /dev/null +++ b/arch/m68k/include/asm/uaccess.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "uaccess_no.h" | ||
| 3 | #else | ||
| 4 | #include "uaccess_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/uaccess_mm.h b/arch/m68k/include/asm/uaccess_mm.h new file mode 100644 index 000000000000..7107f3fbdbb6 --- /dev/null +++ b/arch/m68k/include/asm/uaccess_mm.h | |||
| @@ -0,0 +1,374 @@ | |||
| 1 | #ifndef __M68K_UACCESS_H | ||
| 2 | #define __M68K_UACCESS_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * User space memory access functions | ||
| 6 | */ | ||
| 7 | #include <linux/compiler.h> | ||
| 8 | #include <linux/errno.h> | ||
| 9 | #include <linux/types.h> | ||
| 10 | #include <linux/sched.h> | ||
| 11 | #include <asm/segment.h> | ||
| 12 | |||
| 13 | #define VERIFY_READ 0 | ||
| 14 | #define VERIFY_WRITE 1 | ||
| 15 | |||
| 16 | /* We let the MMU do all checking */ | ||
| 17 | static inline int access_ok(int type, const void __user *addr, | ||
| 18 | unsigned long size) | ||
| 19 | { | ||
| 20 | return 1; | ||
| 21 | } | ||
| 22 | |||
| 23 | /* | ||
| 24 | * The exception table consists of pairs of addresses: the first is the | ||
| 25 | * address of an instruction that is allowed to fault, and the second is | ||
| 26 | * the address at which the program should continue. No registers are | ||
| 27 | * modified, so it is entirely up to the continuation code to figure out | ||
| 28 | * what to do. | ||
| 29 | * | ||
| 30 | * All the routines below use bits of fixup code that are out of line | ||
| 31 | * with the main instruction path. This means when everything is well, | ||
| 32 | * we don't even have to jump over them. Further, they do not intrude | ||
| 33 | * on our cache or tlb entries. | ||
| 34 | */ | ||
| 35 | |||
| 36 | struct exception_table_entry | ||
| 37 | { | ||
| 38 | unsigned long insn, fixup; | ||
| 39 | }; | ||
| 40 | |||
| 41 | extern int __put_user_bad(void); | ||
| 42 | extern int __get_user_bad(void); | ||
| 43 | |||
| 44 | #define __put_user_asm(res, x, ptr, bwl, reg, err) \ | ||
| 45 | asm volatile ("\n" \ | ||
| 46 | "1: moves."#bwl" %2,%1\n" \ | ||
| 47 | "2:\n" \ | ||
| 48 | " .section .fixup,\"ax\"\n" \ | ||
| 49 | " .even\n" \ | ||
| 50 | "10: moveq.l %3,%0\n" \ | ||
| 51 | " jra 2b\n" \ | ||
| 52 | " .previous\n" \ | ||
| 53 | "\n" \ | ||
| 54 | " .section __ex_table,\"a\"\n" \ | ||
| 55 | " .align 4\n" \ | ||
| 56 | " .long 1b,10b\n" \ | ||
| 57 | " .long 2b,10b\n" \ | ||
| 58 | " .previous" \ | ||
| 59 | : "+d" (res), "=m" (*(ptr)) \ | ||
| 60 | : #reg (x), "i" (err)) | ||
| 61 | |||
| 62 | /* | ||
| 63 | * These are the main single-value transfer routines. They automatically | ||
| 64 | * use the right size if we just have the right pointer type. | ||
| 65 | */ | ||
| 66 | |||
| 67 | #define __put_user(x, ptr) \ | ||
| 68 | ({ \ | ||
| 69 | typeof(*(ptr)) __pu_val = (x); \ | ||
| 70 | int __pu_err = 0; \ | ||
| 71 | __chk_user_ptr(ptr); \ | ||
| 72 | switch (sizeof (*(ptr))) { \ | ||
| 73 | case 1: \ | ||
| 74 | __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \ | ||
| 75 | break; \ | ||
| 76 | case 2: \ | ||
| 77 | __put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \ | ||
| 78 | break; \ | ||
| 79 | case 4: \ | ||
| 80 | __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \ | ||
| 81 | break; \ | ||
| 82 | case 8: \ | ||
| 83 | { \ | ||
| 84 | const void __user *__pu_ptr = (ptr); \ | ||
| 85 | asm volatile ("\n" \ | ||
| 86 | "1: moves.l %2,(%1)+\n" \ | ||
| 87 | "2: moves.l %R2,(%1)\n" \ | ||
| 88 | "3:\n" \ | ||
| 89 | " .section .fixup,\"ax\"\n" \ | ||
| 90 | " .even\n" \ | ||
| 91 | "10: movel %3,%0\n" \ | ||
| 92 | " jra 3b\n" \ | ||
| 93 | " .previous\n" \ | ||
| 94 | "\n" \ | ||
| 95 | " .section __ex_table,\"a\"\n" \ | ||
| 96 | " .align 4\n" \ | ||
| 97 | " .long 1b,10b\n" \ | ||
| 98 | " .long 2b,10b\n" \ | ||
| 99 | " .long 3b,10b\n" \ | ||
| 100 | " .previous" \ | ||
| 101 | : "+d" (__pu_err), "+a" (__pu_ptr) \ | ||
| 102 | : "r" (__pu_val), "i" (-EFAULT) \ | ||
| 103 | : "memory"); \ | ||
| 104 | break; \ | ||
| 105 | } \ | ||
| 106 | default: \ | ||
| 107 | __pu_err = __put_user_bad(); \ | ||
| 108 | break; \ | ||
| 109 | } \ | ||
| 110 | __pu_err; \ | ||
| 111 | }) | ||
| 112 | #define put_user(x, ptr) __put_user(x, ptr) | ||
| 113 | |||
| 114 | |||
| 115 | #define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \ | ||
| 116 | type __gu_val; \ | ||
| 117 | asm volatile ("\n" \ | ||
| 118 | "1: moves."#bwl" %2,%1\n" \ | ||
| 119 | "2:\n" \ | ||
| 120 | " .section .fixup,\"ax\"\n" \ | ||
| 121 | " .even\n" \ | ||
| 122 | "10: move.l %3,%0\n" \ | ||
| 123 | " sub."#bwl" %1,%1\n" \ | ||
| 124 | " jra 2b\n" \ | ||
| 125 | " .previous\n" \ | ||
| 126 | "\n" \ | ||
| 127 | " .section __ex_table,\"a\"\n" \ | ||
| 128 | " .align 4\n" \ | ||
| 129 | " .long 1b,10b\n" \ | ||
| 130 | " .previous" \ | ||
| 131 | : "+d" (res), "=&" #reg (__gu_val) \ | ||
| 132 | : "m" (*(ptr)), "i" (err)); \ | ||
| 133 | (x) = (typeof(*(ptr)))(unsigned long)__gu_val; \ | ||
| 134 | }) | ||
| 135 | |||
| 136 | #define __get_user(x, ptr) \ | ||
| 137 | ({ \ | ||
| 138 | int __gu_err = 0; \ | ||
| 139 | __chk_user_ptr(ptr); \ | ||
| 140 | switch (sizeof(*(ptr))) { \ | ||
| 141 | case 1: \ | ||
| 142 | __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \ | ||
| 143 | break; \ | ||
| 144 | case 2: \ | ||
| 145 | __get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT); \ | ||
| 146 | break; \ | ||
| 147 | case 4: \ | ||
| 148 | __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \ | ||
| 149 | break; \ | ||
| 150 | /* case 8: disabled because gcc-4.1 has a broken typeof \ | ||
| 151 | { \ | ||
| 152 | const void *__gu_ptr = (ptr); \ | ||
| 153 | u64 __gu_val; \ | ||
| 154 | asm volatile ("\n" \ | ||
| 155 | "1: moves.l (%2)+,%1\n" \ | ||
| 156 | "2: moves.l (%2),%R1\n" \ | ||
| 157 | "3:\n" \ | ||
| 158 | " .section .fixup,\"ax\"\n" \ | ||
| 159 | " .even\n" \ | ||
| 160 | "10: move.l %3,%0\n" \ | ||
| 161 | " sub.l %1,%1\n" \ | ||
| 162 | " sub.l %R1,%R1\n" \ | ||
| 163 | " jra 3b\n" \ | ||
| 164 | " .previous\n" \ | ||
| 165 | "\n" \ | ||
| 166 | " .section __ex_table,\"a\"\n" \ | ||
| 167 | " .align 4\n" \ | ||
| 168 | " .long 1b,10b\n" \ | ||
| 169 | " .long 2b,10b\n" \ | ||
| 170 | " .previous" \ | ||
| 171 | : "+d" (__gu_err), "=&r" (__gu_val), \ | ||
| 172 | "+a" (__gu_ptr) \ | ||
| 173 | : "i" (-EFAULT) \ | ||
| 174 | : "memory"); \ | ||
| 175 | (x) = (typeof(*(ptr)))__gu_val; \ | ||
| 176 | break; \ | ||
| 177 | } */ \ | ||
| 178 | default: \ | ||
| 179 | __gu_err = __get_user_bad(); \ | ||
| 180 | break; \ | ||
| 181 | } \ | ||
| 182 | __gu_err; \ | ||
| 183 | }) | ||
| 184 | #define get_user(x, ptr) __get_user(x, ptr) | ||
| 185 | |||
| 186 | unsigned long __generic_copy_from_user(void *to, const void __user *from, unsigned long n); | ||
| 187 | unsigned long __generic_copy_to_user(void __user *to, const void *from, unsigned long n); | ||
| 188 | |||
| 189 | #define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\ | ||
| 190 | asm volatile ("\n" \ | ||
| 191 | "1: moves."#s1" (%2)+,%3\n" \ | ||
| 192 | " move."#s1" %3,(%1)+\n" \ | ||
| 193 | "2: moves."#s2" (%2)+,%3\n" \ | ||
| 194 | " move."#s2" %3,(%1)+\n" \ | ||
| 195 | " .ifnc \""#s3"\",\"\"\n" \ | ||
| 196 | "3: moves."#s3" (%2)+,%3\n" \ | ||
| 197 | " move."#s3" %3,(%1)+\n" \ | ||
| 198 | " .endif\n" \ | ||
| 199 | "4:\n" \ | ||
| 200 | " .section __ex_table,\"a\"\n" \ | ||
| 201 | " .align 4\n" \ | ||
| 202 | " .long 1b,10f\n" \ | ||
| 203 | " .long 2b,20f\n" \ | ||
| 204 | " .ifnc \""#s3"\",\"\"\n" \ | ||
| 205 | " .long 3b,30f\n" \ | ||
| 206 | " .endif\n" \ | ||
| 207 | " .previous\n" \ | ||
| 208 | "\n" \ | ||
| 209 | " .section .fixup,\"ax\"\n" \ | ||
| 210 | " .even\n" \ | ||
| 211 | "10: clr."#s1" (%1)+\n" \ | ||
| 212 | "20: clr."#s2" (%1)+\n" \ | ||
| 213 | " .ifnc \""#s3"\",\"\"\n" \ | ||
| 214 | "30: clr."#s3" (%1)+\n" \ | ||
| 215 | " .endif\n" \ | ||
| 216 | " moveq.l #"#n",%0\n" \ | ||
| 217 | " jra 4b\n" \ | ||
| 218 | " .previous\n" \ | ||
| 219 | : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \ | ||
| 220 | : : "memory") | ||
| 221 | |||
| 222 | static __always_inline unsigned long | ||
| 223 | __constant_copy_from_user(void *to, const void __user *from, unsigned long n) | ||
| 224 | { | ||
| 225 | unsigned long res = 0, tmp; | ||
| 226 | |||
| 227 | switch (n) { | ||
| 228 | case 1: | ||
| 229 | __get_user_asm(res, *(u8 *)to, (u8 __user *)from, u8, b, d, 1); | ||
| 230 | break; | ||
| 231 | case 2: | ||
| 232 | __get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w, d, 2); | ||
| 233 | break; | ||
| 234 | case 3: | ||
| 235 | __constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,); | ||
| 236 | break; | ||
| 237 | case 4: | ||
| 238 | __get_user_asm(res, *(u32 *)to, (u32 __user *)from, u32, l, r, 4); | ||
| 239 | break; | ||
| 240 | case 5: | ||
| 241 | __constant_copy_from_user_asm(res, to, from, tmp, 5, l, b,); | ||
| 242 | break; | ||
| 243 | case 6: | ||
| 244 | __constant_copy_from_user_asm(res, to, from, tmp, 6, l, w,); | ||
| 245 | break; | ||
| 246 | case 7: | ||
| 247 | __constant_copy_from_user_asm(res, to, from, tmp, 7, l, w, b); | ||
| 248 | break; | ||
| 249 | case 8: | ||
| 250 | __constant_copy_from_user_asm(res, to, from, tmp, 8, l, l,); | ||
| 251 | break; | ||
| 252 | case 9: | ||
| 253 | __constant_copy_from_user_asm(res, to, from, tmp, 9, l, l, b); | ||
| 254 | break; | ||
| 255 | case 10: | ||
| 256 | __constant_copy_from_user_asm(res, to, from, tmp, 10, l, l, w); | ||
| 257 | break; | ||
| 258 | case 12: | ||
| 259 | __constant_copy_from_user_asm(res, to, from, tmp, 12, l, l, l); | ||
| 260 | break; | ||
| 261 | default: | ||
| 262 | /* we limit the inlined version to 3 moves */ | ||
| 263 | return __generic_copy_from_user(to, from, n); | ||
| 264 | } | ||
| 265 | |||
| 266 | return res; | ||
| 267 | } | ||
| 268 | |||
| 269 | #define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \ | ||
| 270 | asm volatile ("\n" \ | ||
| 271 | " move."#s1" (%2)+,%3\n" \ | ||
| 272 | "11: moves."#s1" %3,(%1)+\n" \ | ||
| 273 | "12: move."#s2" (%2)+,%3\n" \ | ||
| 274 | "21: moves."#s2" %3,(%1)+\n" \ | ||
| 275 | "22:\n" \ | ||
| 276 | " .ifnc \""#s3"\",\"\"\n" \ | ||
| 277 | " move."#s3" (%2)+,%3\n" \ | ||
| 278 | "31: moves."#s3" %3,(%1)+\n" \ | ||
| 279 | "32:\n" \ | ||
| 280 | " .endif\n" \ | ||
| 281 | "4:\n" \ | ||
| 282 | "\n" \ | ||
| 283 | " .section __ex_table,\"a\"\n" \ | ||
| 284 | " .align 4\n" \ | ||
| 285 | " .long 11b,5f\n" \ | ||
| 286 | " .long 12b,5f\n" \ | ||
| 287 | " .long 21b,5f\n" \ | ||
| 288 | " .long 22b,5f\n" \ | ||
| 289 | " .ifnc \""#s3"\",\"\"\n" \ | ||
| 290 | " .long 31b,5f\n" \ | ||
| 291 | " .long 32b,5f\n" \ | ||
| 292 | " .endif\n" \ | ||
| 293 | " .previous\n" \ | ||
| 294 | "\n" \ | ||
| 295 | " .section .fixup,\"ax\"\n" \ | ||
| 296 | " .even\n" \ | ||
| 297 | "5: moveq.l #"#n",%0\n" \ | ||
| 298 | " jra 4b\n" \ | ||
| 299 | " .previous\n" \ | ||
| 300 | : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \ | ||
| 301 | : : "memory") | ||
| 302 | |||
| 303 | static __always_inline unsigned long | ||
| 304 | __constant_copy_to_user(void __user *to, const void *from, unsigned long n) | ||
| 305 | { | ||
| 306 | unsigned long res = 0, tmp; | ||
| 307 | |||
| 308 | switch (n) { | ||
| 309 | case 1: | ||
| 310 | __put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1); | ||
| 311 | break; | ||
| 312 | case 2: | ||
| 313 | __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, d, 2); | ||
| 314 | break; | ||
| 315 | case 3: | ||
| 316 | __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,); | ||
| 317 | break; | ||
| 318 | case 4: | ||
| 319 | __put_user_asm(res, *(u32 *)from, (u32 __user *)to, l, r, 4); | ||
| 320 | break; | ||
| 321 | case 5: | ||
| 322 | __constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,); | ||
| 323 | break; | ||
| 324 | case 6: | ||
| 325 | __constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,); | ||
| 326 | break; | ||
| 327 | case 7: | ||
| 328 | __constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b); | ||
| 329 | break; | ||
| 330 | case 8: | ||
| 331 | __constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,); | ||
| 332 | break; | ||
| 333 | case 9: | ||
| 334 | __constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b); | ||
| 335 | break; | ||
| 336 | case 10: | ||
| 337 | __constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w); | ||
| 338 | break; | ||
| 339 | case 12: | ||
| 340 | __constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l); | ||
| 341 | break; | ||
| 342 | default: | ||
| 343 | /* limit the inlined version to 3 moves */ | ||
| 344 | return __generic_copy_to_user(to, from, n); | ||
| 345 | } | ||
| 346 | |||
| 347 | return res; | ||
| 348 | } | ||
| 349 | |||
| 350 | #define __copy_from_user(to, from, n) \ | ||
| 351 | (__builtin_constant_p(n) ? \ | ||
| 352 | __constant_copy_from_user(to, from, n) : \ | ||
| 353 | __generic_copy_from_user(to, from, n)) | ||
| 354 | |||
| 355 | #define __copy_to_user(to, from, n) \ | ||
| 356 | (__builtin_constant_p(n) ? \ | ||
| 357 | __constant_copy_to_user(to, from, n) : \ | ||
| 358 | __generic_copy_to_user(to, from, n)) | ||
| 359 | |||
| 360 | #define __copy_to_user_inatomic __copy_to_user | ||
| 361 | #define __copy_from_user_inatomic __copy_from_user | ||
| 362 | |||
| 363 | #define copy_from_user(to, from, n) __copy_from_user(to, from, n) | ||
| 364 | #define copy_to_user(to, from, n) __copy_to_user(to, from, n) | ||
| 365 | |||
| 366 | long strncpy_from_user(char *dst, const char __user *src, long count); | ||
| 367 | long strnlen_user(const char __user *src, long n); | ||
| 368 | unsigned long __clear_user(void __user *to, unsigned long n); | ||
| 369 | |||
| 370 | #define clear_user __clear_user | ||
| 371 | |||
| 372 | #define strlen_user(str) strnlen_user(str, 32767) | ||
| 373 | |||
| 374 | #endif /* _M68K_UACCESS_H */ | ||
diff --git a/arch/m68k/include/asm/uaccess_no.h b/arch/m68k/include/asm/uaccess_no.h new file mode 100644 index 000000000000..68bbe9b312f1 --- /dev/null +++ b/arch/m68k/include/asm/uaccess_no.h | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | #ifndef __M68KNOMMU_UACCESS_H | ||
| 2 | #define __M68KNOMMU_UACCESS_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * User space memory access functions | ||
| 6 | */ | ||
| 7 | #include <linux/sched.h> | ||
| 8 | #include <linux/mm.h> | ||
| 9 | #include <linux/string.h> | ||
| 10 | |||
| 11 | #include <asm/segment.h> | ||
| 12 | |||
| 13 | #define VERIFY_READ 0 | ||
| 14 | #define VERIFY_WRITE 1 | ||
| 15 | |||
| 16 | #define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) | ||
| 17 | |||
| 18 | /* | ||
| 19 | * It is not enough to just have access_ok check for a real RAM address. | ||
| 20 | * This would disallow the case of code/ro-data running XIP in flash/rom. | ||
| 21 | * Ideally we would check the possible flash ranges too, but that is | ||
| 22 | * currently not so easy. | ||
| 23 | */ | ||
| 24 | static inline int _access_ok(unsigned long addr, unsigned long size) | ||
| 25 | { | ||
| 26 | return 1; | ||
| 27 | } | ||
| 28 | |||
| 29 | /* | ||
| 30 | * The exception table consists of pairs of addresses: the first is the | ||
| 31 | * address of an instruction that is allowed to fault, and the second is | ||
| 32 | * the address at which the program should continue. No registers are | ||
| 33 | * modified, so it is entirely up to the continuation code to figure out | ||
| 34 | * what to do. | ||
| 35 | * | ||
| 36 | * All the routines below use bits of fixup code that are out of line | ||
| 37 | * with the main instruction path. This means when everything is well, | ||
| 38 | * we don't even have to jump over them. Further, they do not intrude | ||
| 39 | * on our cache or tlb entries. | ||
| 40 | */ | ||
| 41 | |||
| 42 | struct exception_table_entry | ||
| 43 | { | ||
| 44 | unsigned long insn, fixup; | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* Returns 0 if exception not found and fixup otherwise. */ | ||
| 48 | extern unsigned long search_exception_table(unsigned long); | ||
| 49 | |||
| 50 | |||
| 51 | /* | ||
| 52 | * These are the main single-value transfer routines. They automatically | ||
| 53 | * use the right size if we just have the right pointer type. | ||
| 54 | */ | ||
| 55 | |||
| 56 | #define put_user(x, ptr) \ | ||
| 57 | ({ \ | ||
| 58 | int __pu_err = 0; \ | ||
| 59 | typeof(*(ptr)) __pu_val = (x); \ | ||
| 60 | switch (sizeof (*(ptr))) { \ | ||
| 61 | case 1: \ | ||
| 62 | __put_user_asm(__pu_err, __pu_val, ptr, b); \ | ||
| 63 | break; \ | ||
| 64 | case 2: \ | ||
| 65 | __put_user_asm(__pu_err, __pu_val, ptr, w); \ | ||
| 66 | break; \ | ||
| 67 | case 4: \ | ||
| 68 | __put_user_asm(__pu_err, __pu_val, ptr, l); \ | ||
| 69 | break; \ | ||
| 70 | case 8: \ | ||
| 71 | memcpy(ptr, &__pu_val, sizeof (*(ptr))); \ | ||
| 72 | break; \ | ||
| 73 | default: \ | ||
| 74 | __pu_err = __put_user_bad(); \ | ||
| 75 | break; \ | ||
| 76 | } \ | ||
| 77 | __pu_err; \ | ||
| 78 | }) | ||
| 79 | #define __put_user(x, ptr) put_user(x, ptr) | ||
| 80 | |||
| 81 | extern int __put_user_bad(void); | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Tell gcc we read from memory instead of writing: this is because | ||
| 85 | * we do not write to any memory gcc knows about, so there are no | ||
| 86 | * aliasing issues. | ||
| 87 | */ | ||
| 88 | |||
| 89 | #define __ptr(x) ((unsigned long *)(x)) | ||
| 90 | |||
| 91 | #define __put_user_asm(err,x,ptr,bwl) \ | ||
| 92 | __asm__ ("move" #bwl " %0,%1" \ | ||
| 93 | : /* no outputs */ \ | ||
| 94 | :"d" (x),"m" (*__ptr(ptr)) : "memory") | ||
| 95 | |||
| 96 | #define get_user(x, ptr) \ | ||
| 97 | ({ \ | ||
| 98 | int __gu_err = 0; \ | ||
| 99 | typeof(x) __gu_val = 0; \ | ||
| 100 | switch (sizeof(*(ptr))) { \ | ||
| 101 | case 1: \ | ||
| 102 | __get_user_asm(__gu_err, __gu_val, ptr, b, "=d"); \ | ||
| 103 | break; \ | ||
| 104 | case 2: \ | ||
| 105 | __get_user_asm(__gu_err, __gu_val, ptr, w, "=r"); \ | ||
| 106 | break; \ | ||
| 107 | case 4: \ | ||
| 108 | __get_user_asm(__gu_err, __gu_val, ptr, l, "=r"); \ | ||
| 109 | break; \ | ||
| 110 | case 8: \ | ||
| 111 | memcpy((void *) &__gu_val, ptr, sizeof (*(ptr))); \ | ||
| 112 | break; \ | ||
| 113 | default: \ | ||
| 114 | __gu_val = 0; \ | ||
| 115 | __gu_err = __get_user_bad(); \ | ||
| 116 | break; \ | ||
| 117 | } \ | ||
| 118 | (x) = (typeof(*(ptr))) __gu_val; \ | ||
| 119 | __gu_err; \ | ||
| 120 | }) | ||
| 121 | #define __get_user(x, ptr) get_user(x, ptr) | ||
| 122 | |||
| 123 | extern int __get_user_bad(void); | ||
| 124 | |||
| 125 | #define __get_user_asm(err,x,ptr,bwl,reg) \ | ||
| 126 | __asm__ ("move" #bwl " %1,%0" \ | ||
| 127 | : "=d" (x) \ | ||
| 128 | : "m" (*__ptr(ptr))) | ||
| 129 | |||
| 130 | #define copy_from_user(to, from, n) (memcpy(to, from, n), 0) | ||
| 131 | #define copy_to_user(to, from, n) (memcpy(to, from, n), 0) | ||
| 132 | |||
| 133 | #define __copy_from_user(to, from, n) copy_from_user(to, from, n) | ||
| 134 | #define __copy_to_user(to, from, n) copy_to_user(to, from, n) | ||
| 135 | #define __copy_to_user_inatomic __copy_to_user | ||
| 136 | #define __copy_from_user_inatomic __copy_from_user | ||
| 137 | |||
| 138 | #define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; }) | ||
| 139 | |||
| 140 | #define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; }) | ||
| 141 | |||
| 142 | /* | ||
| 143 | * Copy a null terminated string from userspace. | ||
| 144 | */ | ||
| 145 | |||
| 146 | static inline long | ||
| 147 | strncpy_from_user(char *dst, const char *src, long count) | ||
| 148 | { | ||
| 149 | char *tmp; | ||
| 150 | strncpy(dst, src, count); | ||
| 151 | for (tmp = dst; *tmp && count > 0; tmp++, count--) | ||
| 152 | ; | ||
| 153 | return(tmp - dst); /* DAVIDM should we count a NUL ? check getname */ | ||
| 154 | } | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Return the size of a string (including the ending 0) | ||
| 158 | * | ||
| 159 | * Return 0 on exception, a value greater than N if too long | ||
| 160 | */ | ||
| 161 | static inline long strnlen_user(const char *src, long n) | ||
| 162 | { | ||
| 163 | return(strlen(src) + 1); /* DAVIDM make safer */ | ||
| 164 | } | ||
| 165 | |||
| 166 | #define strlen_user(str) strnlen_user(str, 32767) | ||
| 167 | |||
| 168 | /* | ||
| 169 | * Zero Userspace | ||
| 170 | */ | ||
| 171 | |||
| 172 | static inline unsigned long | ||
| 173 | __clear_user(void *to, unsigned long n) | ||
| 174 | { | ||
| 175 | memset(to, 0, n); | ||
| 176 | return 0; | ||
| 177 | } | ||
| 178 | |||
| 179 | #define clear_user(to,n) __clear_user(to,n) | ||
| 180 | |||
| 181 | #endif /* _M68KNOMMU_UACCESS_H */ | ||
diff --git a/arch/m68k/include/asm/ucontext.h b/arch/m68k/include/asm/ucontext.h new file mode 100644 index 000000000000..b53cd160c0b3 --- /dev/null +++ b/arch/m68k/include/asm/ucontext.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "ucontext_no.h" | ||
| 3 | #else | ||
| 4 | #include "ucontext_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/ucontext_mm.h b/arch/m68k/include/asm/ucontext_mm.h new file mode 100644 index 000000000000..e4e22669edc0 --- /dev/null +++ b/arch/m68k/include/asm/ucontext_mm.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | #ifndef _M68K_UCONTEXT_H | ||
| 2 | #define _M68K_UCONTEXT_H | ||
| 3 | |||
| 4 | typedef int greg_t; | ||
| 5 | #define NGREG 18 | ||
| 6 | typedef greg_t gregset_t[NGREG]; | ||
| 7 | |||
| 8 | typedef struct fpregset { | ||
| 9 | int f_fpcntl[3]; | ||
| 10 | int f_fpregs[8*3]; | ||
| 11 | } fpregset_t; | ||
| 12 | |||
| 13 | struct mcontext { | ||
| 14 | int version; | ||
| 15 | gregset_t gregs; | ||
| 16 | fpregset_t fpregs; | ||
| 17 | }; | ||
| 18 | |||
| 19 | #define MCONTEXT_VERSION 2 | ||
| 20 | |||
| 21 | struct ucontext { | ||
| 22 | unsigned long uc_flags; | ||
| 23 | struct ucontext *uc_link; | ||
| 24 | stack_t uc_stack; | ||
| 25 | struct mcontext uc_mcontext; | ||
| 26 | unsigned long uc_filler[80]; | ||
| 27 | sigset_t uc_sigmask; /* mask last for extensibility */ | ||
| 28 | }; | ||
| 29 | |||
| 30 | #endif | ||
diff --git a/arch/m68k/include/asm/ucontext_no.h b/arch/m68k/include/asm/ucontext_no.h new file mode 100644 index 000000000000..713a27f901cd --- /dev/null +++ b/arch/m68k/include/asm/ucontext_no.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | #ifndef _M68KNOMMU_UCONTEXT_H | ||
| 2 | #define _M68KNOMMU_UCONTEXT_H | ||
| 3 | |||
| 4 | typedef int greg_t; | ||
| 5 | #define NGREG 18 | ||
| 6 | typedef greg_t gregset_t[NGREG]; | ||
| 7 | |||
| 8 | typedef struct fpregset { | ||
| 9 | int f_pcr; | ||
| 10 | int f_psr; | ||
| 11 | int f_fpiaddr; | ||
| 12 | int f_fpregs[8][3]; | ||
| 13 | } fpregset_t; | ||
| 14 | |||
| 15 | struct mcontext { | ||
| 16 | int version; | ||
| 17 | gregset_t gregs; | ||
| 18 | fpregset_t fpregs; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #define MCONTEXT_VERSION 2 | ||
| 22 | |||
| 23 | struct ucontext { | ||
| 24 | unsigned long uc_flags; | ||
| 25 | struct ucontext *uc_link; | ||
| 26 | stack_t uc_stack; | ||
| 27 | struct mcontext uc_mcontext; | ||
| 28 | unsigned long uc_filler[80]; | ||
| 29 | sigset_t uc_sigmask; /* mask last for extensibility */ | ||
| 30 | }; | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h new file mode 100644 index 000000000000..c640bba3bdf4 --- /dev/null +++ b/arch/m68k/include/asm/unaligned.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "unaligned_no.h" | ||
| 3 | #else | ||
| 4 | #include "unaligned_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/unaligned_mm.h b/arch/m68k/include/asm/unaligned_mm.h new file mode 100644 index 000000000000..77698f2dc33c --- /dev/null +++ b/arch/m68k/include/asm/unaligned_mm.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef _ASM_M68K_UNALIGNED_H | ||
| 2 | #define _ASM_M68K_UNALIGNED_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * The m68k can do unaligned accesses itself. | ||
| 6 | */ | ||
| 7 | #include <linux/unaligned/access_ok.h> | ||
| 8 | #include <linux/unaligned/generic.h> | ||
| 9 | |||
| 10 | #define get_unaligned __get_unaligned_be | ||
| 11 | #define put_unaligned __put_unaligned_be | ||
| 12 | |||
| 13 | #endif /* _ASM_M68K_UNALIGNED_H */ | ||
diff --git a/arch/m68k/include/asm/unaligned_no.h b/arch/m68k/include/asm/unaligned_no.h new file mode 100644 index 000000000000..eb1ea4cb9a59 --- /dev/null +++ b/arch/m68k/include/asm/unaligned_no.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | #ifndef _ASM_M68KNOMMU_UNALIGNED_H | ||
| 2 | #define _ASM_M68KNOMMU_UNALIGNED_H | ||
| 3 | |||
| 4 | |||
| 5 | #ifdef CONFIG_COLDFIRE | ||
| 6 | #include <linux/unaligned/be_struct.h> | ||
| 7 | #include <linux/unaligned/le_byteshift.h> | ||
| 8 | #include <linux/unaligned/generic.h> | ||
| 9 | |||
| 10 | #define get_unaligned __get_unaligned_be | ||
| 11 | #define put_unaligned __put_unaligned_be | ||
| 12 | |||
| 13 | #else | ||
| 14 | /* | ||
| 15 | * The m68k can do unaligned accesses itself. | ||
| 16 | */ | ||
| 17 | #include <linux/unaligned/access_ok.h> | ||
| 18 | #include <linux/unaligned/generic.h> | ||
| 19 | |||
| 20 | #define get_unaligned __get_unaligned_be | ||
| 21 | #define put_unaligned __put_unaligned_be | ||
| 22 | |||
| 23 | #endif | ||
| 24 | |||
| 25 | #endif /* _ASM_M68KNOMMU_UNALIGNED_H */ | ||
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h new file mode 100644 index 000000000000..df1d9d4cb1fd --- /dev/null +++ b/arch/m68k/include/asm/unistd.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | #ifdef __uClinux__ | ||
| 2 | #include "unistd_no.h" | ||
| 3 | #else | ||
| 4 | #include "unistd_mm.h" | ||
| 5 | #endif | ||
diff --git a/arch/m68k/include/asm/unistd_mm.h b/arch/m68k/include/asm/unistd_mm.h new file mode 100644 index 000000000000..3c19027331fa --- /dev/null +++ b/arch/m68k/include/asm/unistd_mm.h | |||
| @@ -0,0 +1,372 @@ | |||
| 1 | #ifndef _ASM_M68K_UNISTD_H_ | ||
| 2 | #define _ASM_M68K_UNISTD_H_ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file contains the system call numbers. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define __NR_restart_syscall 0 | ||
| 9 | #define __NR_exit 1 | ||
| 10 | #define __NR_fork 2 | ||
| 11 | #define __NR_read 3 | ||
| 12 | #define __NR_write 4 | ||
| 13 | #define __NR_open 5 | ||
| 14 | #define __NR_close 6 | ||
| 15 | #define __NR_waitpid 7 | ||
| 16 | #define __NR_creat 8 | ||
| 17 | #define __NR_link 9 | ||
| 18 | #define __NR_unlink 10 | ||
| 19 | #define __NR_execve 11 | ||
| 20 | #define __NR_chdir 12 | ||
| 21 | #define __NR_time 13 | ||
| 22 | #define __NR_mknod 14 | ||
| 23 | #define __NR_chmod 15 | ||
| 24 | #define __NR_chown 16 | ||
| 25 | #define __NR_break 17 | ||
| 26 | #define __NR_oldstat 18 | ||
| 27 | #define __NR_lseek 19 | ||
| 28 | #define __NR_getpid 20 | ||
| 29 | #define __NR_mount 21 | ||
| 30 | #define __NR_umount 22 | ||
| 31 | #define __NR_setuid 23 | ||
| 32 | #define __NR_getuid 24 | ||
| 33 | #define __NR_stime 25 | ||
| 34 | #define __NR_ptrace 26 | ||
| 35 | #define __NR_alarm 27 | ||
| 36 | #define __NR_oldfstat 28 | ||
| 37 | #define __NR_pause 29 | ||
| 38 | #define __NR_utime 30 | ||
| 39 | #define __NR_stty 31 | ||
| 40 | #define __NR_gtty 32 | ||
| 41 | #define __NR_access 33 | ||
| 42 | #define __NR_nice 34 | ||
| 43 | #define __NR_ftime 35 | ||
| 44 | #define __NR_sync 36 | ||
| 45 | #define __NR_kill 37 | ||
| 46 | #define __NR_rename 38 | ||
| 47 | #define __NR_mkdir 39 | ||
| 48 | #define __NR_rmdir 40 | ||
| 49 | #define __NR_dup 41 | ||
| 50 | #define __NR_pipe 42 | ||
| 51 | #define __NR_times 43 | ||
| 52 | #define __NR_prof 44 | ||
| 53 | #define __NR_brk 45 | ||
| 54 | #define __NR_setgid 46 | ||
| 55 | #define __NR_getgid 47 | ||
| 56 | #define __NR_signal 48 | ||
| 57 | #define __NR_geteuid 49 | ||
| 58 | #define __NR_getegid 50 | ||
| 59 | #define __NR_acct 51 | ||
| 60 | #define __NR_umount2 52 | ||
| 61 | #define __NR_lock 53 | ||
| 62 | #define __NR_ioctl 54 | ||
| 63 | #define __NR_fcntl 55 | ||
| 64 | #define __NR_mpx 56 | ||
| 65 | #define __NR_setpgid 57 | ||
| 66 | #define __NR_ulimit 58 | ||
| 67 | #define __NR_oldolduname 59 | ||
| 68 | #define __NR_umask 60 | ||
| 69 | #define __NR_chroot 61 | ||
| 70 | #define __NR_ustat 62 | ||
| 71 | #define __NR_dup2 63 | ||
| 72 | #define __NR_getppid 64 | ||
| 73 | #define __NR_getpgrp 65 | ||
| 74 | #define __NR_setsid 66 | ||
| 75 | #define __NR_sigaction 67 | ||
| 76 | #define __NR_sgetmask 68 | ||
| 77 | #define __NR_ssetmask 69 | ||
| 78 | #define __NR_setreuid 70 | ||
| 79 | #define __NR_setregid 71 | ||
| 80 | #define __NR_sigsuspend 72 | ||
| 81 | #define __NR_sigpending 73 | ||
| 82 | #define __NR_sethostname 74 | ||
| 83 | #define __NR_setrlimit 75 | ||
| 84 | #define __NR_getrlimit 76 | ||
| 85 | #define __NR_getrusage 77 | ||
| 86 | #define __NR_gettimeofday 78 | ||
| 87 | #define __NR_settimeofday 79 | ||
| 88 | #define __NR_getgroups 80 | ||
| 89 | #define __NR_setgroups 81 | ||
| 90 | #define __NR_select 82 | ||
| 91 | #define __NR_symlink 83 | ||
| 92 | #define __NR_oldlstat 84 | ||
| 93 | #define __NR_readlink 85 | ||
| 94 | #define __NR_uselib 86 | ||
| 95 | #define __NR_swapon 87 | ||
| 96 | #define __NR_reboot 88 | ||
| 97 | #define __NR_readdir 89 | ||
| 98 | #define __NR_mmap 90 | ||
| 99 | #define __NR_munmap 91 | ||
| 100 | #define __NR_truncate 92 | ||
| 101 | #define __NR_ftruncate 93 | ||
| 102 | #define __NR_fchmod 94 | ||
| 103 | #define __NR_fchown 95 | ||
| 104 | #define __NR_getpriority 96 | ||
| 105 | #define __NR_setpriority 97 | ||
| 106 | #define __NR_profil 98 | ||
| 107 | #define __NR_statfs 99 | ||
| 108 | #define __NR_fstatfs 100 | ||
| 109 | #define __NR_ioperm 101 | ||
| 110 | #define __NR_socketcall 102 | ||
| 111 | #define __NR_syslog 103 | ||
| 112 | #define __NR_setitimer 104 | ||
| 113 | #define __NR_getitimer 105 | ||
| 114 | #define __NR_stat 106 | ||
| 115 | #define __NR_lstat 107 | ||
| 116 | #define __NR_fstat 108 | ||
| 117 | #define __NR_olduname 109 | ||
| 118 | #define __NR_iopl /* 110 */ not supported | ||
| 119 | #define __NR_vhangup 111 | ||
| 120 | #define __NR_idle /* 112 */ Obsolete | ||
| 121 | #define __NR_vm86 /* 113 */ not supported | ||
| 122 | #define __NR_wait4 114 | ||
| 123 | #define __NR_swapoff 115 | ||
| 124 | #define __NR_sysinfo 116 | ||
| 125 | #define __NR_ipc 117 | ||
| 126 | #define __NR_fsync 118 | ||
| 127 | #define __NR_sigreturn 119 | ||
| 128 | #define __NR_clone 120 | ||
| 129 | #define __NR_setdomainname 121 | ||
| 130 | #define __NR_uname 122 | ||
| 131 | #define __NR_cacheflush 123 | ||
| 132 | #define __NR_adjtimex 124 | ||
| 133 | #define __NR_mprotect 125 | ||
| 134 | #define __NR_sigprocmask 126 | ||
| 135 | #define __NR_create_module 127 | ||
| 136 | #define __NR_init_module 128 | ||
| 137 | #define __NR_delete_module 129 | ||
| 138 | #define __NR_get_kernel_syms 130 | ||
| 139 | #define __NR_quotactl 131 | ||
| 140 | #define __NR_getpgid 132 | ||
| 141 | #define __NR_fchdir 133 | ||
| 142 | #define __NR_bdflush 134 | ||
| 143 | #define __NR_sysfs 135 | ||
| 144 | #define __NR_personality 136 | ||
| 145 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 146 | #define __NR_setfsuid 138 | ||
| 147 | #define __NR_setfsgid 139 | ||
| 148 | #define __NR__llseek 140 | ||
| 149 | #define __NR_getdents 141 | ||
| 150 | #define __NR__newselect 142 | ||
| 151 | #define __NR_flock 143 | ||
| 152 | #define __NR_msync 144 | ||
| 153 | #define __NR_readv 145 | ||
| 154 | #define __NR_writev 146 | ||
| 155 | #define __NR_getsid 147 | ||
| 156 | #define __NR_fdatasync 148 | ||
| 157 | #define __NR__sysctl 149 | ||
| 158 | #define __NR_mlock 150 | ||
| 159 | #define __NR_munlock 151 | ||
| 160 | #define __NR_mlockall 152 | ||
| 161 | #define __NR_munlockall 153 | ||
| 162 | #define __NR_sched_setparam 154 | ||
| 163 | #define __NR_sched_getparam 155 | ||
| 164 | #define __NR_sched_setscheduler 156 | ||
| 165 | #define __NR_sched_getscheduler 157 | ||
| 166 | #define __NR_sched_yield 158 | ||
| 167 | #define __NR_sched_get_priority_max 159 | ||
| 168 | #define __NR_sched_get_priority_min 160 | ||
| 169 | #define __NR_sched_rr_get_interval 161 | ||
| 170 | #define __NR_nanosleep 162 | ||
| 171 | #define __NR_mremap 163 | ||
| 172 | #define __NR_setresuid 164 | ||
| 173 | #define __NR_getresuid 165 | ||
| 174 | #define __NR_getpagesize 166 | ||
| 175 | #define __NR_query_module 167 | ||
| 176 | #define __NR_poll 168 | ||
| 177 | #define __NR_nfsservctl 169 | ||
| 178 | #define __NR_setresgid 170 | ||
| 179 | #define __NR_getresgid 171 | ||
| 180 | #define __NR_prctl 172 | ||
| 181 | #define __NR_rt_sigreturn 173 | ||
| 182 | #define __NR_rt_sigaction 174 | ||
| 183 | #define __NR_rt_sigprocmask 175 | ||
| 184 | #define __NR_rt_sigpending 176 | ||
| 185 | #define __NR_rt_sigtimedwait 177 | ||
| 186 | #define __NR_rt_sigqueueinfo 178 | ||
| 187 | #define __NR_rt_sigsuspend 179 | ||
| 188 | #define __NR_pread64 180 | ||
| 189 | #define __NR_pwrite64 181 | ||
| 190 | #define __NR_lchown 182 | ||
| 191 | #define __NR_getcwd 183 | ||
| 192 | #define __NR_capget 184 | ||
| 193 | #define __NR_capset 185 | ||
| 194 | #define __NR_sigaltstack 186 | ||
| 195 | #define __NR_sendfile 187 | ||
| 196 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 197 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 198 | #define __NR_vfork 190 | ||
| 199 | #define __NR_ugetrlimit 191 | ||
| 200 | #define __NR_mmap2 192 | ||
| 201 | #define __NR_truncate64 193 | ||
| 202 | #define __NR_ftruncate64 194 | ||
| 203 | #define __NR_stat64 195 | ||
| 204 | #define __NR_lstat64 196 | ||
| 205 | #define __NR_fstat64 197 | ||
| 206 | #define __NR_chown32 198 | ||
| 207 | #define __NR_getuid32 199 | ||
| 208 | #define __NR_getgid32 200 | ||
| 209 | #define __NR_geteuid32 201 | ||
| 210 | #define __NR_getegid32 202 | ||
| 211 | #define __NR_setreuid32 203 | ||
| 212 | #define __NR_setregid32 204 | ||
| 213 | #define __NR_getgroups32 205 | ||
| 214 | #define __NR_setgroups32 206 | ||
| 215 | #define __NR_fchown32 207 | ||
| 216 | #define __NR_setresuid32 208 | ||
| 217 | #define __NR_getresuid32 209 | ||
| 218 | #define __NR_setresgid32 210 | ||
| 219 | #define __NR_getresgid32 211 | ||
| 220 | #define __NR_lchown32 212 | ||
| 221 | #define __NR_setuid32 213 | ||
| 222 | #define __NR_setgid32 214 | ||
| 223 | #define __NR_setfsuid32 215 | ||
| 224 | #define __NR_setfsgid32 216 | ||
| 225 | #define __NR_pivot_root 217 | ||
| 226 | #define __NR_getdents64 220 | ||
| 227 | #define __NR_gettid 221 | ||
| 228 | #define __NR_tkill 222 | ||
| 229 | #define __NR_setxattr 223 | ||
| 230 | #define __NR_lsetxattr 224 | ||
| 231 | #define __NR_fsetxattr 225 | ||
| 232 | #define __NR_getxattr 226 | ||
| 233 | #define __NR_lgetxattr 227 | ||
| 234 | #define __NR_fgetxattr 228 | ||
| 235 | #define __NR_listxattr 229 | ||
| 236 | #define __NR_llistxattr 230 | ||
| 237 | #define __NR_flistxattr 231 | ||
| 238 | #define __NR_removexattr 232 | ||
| 239 | #define __NR_lremovexattr 233 | ||
| 240 | #define __NR_fremovexattr 234 | ||
| 241 | #define __NR_futex 235 | ||
| 242 | #define __NR_sendfile64 236 | ||
| 243 | #define __NR_mincore 237 | ||
| 244 | #define __NR_madvise 238 | ||
| 245 | #define __NR_fcntl64 239 | ||
| 246 | #define __NR_readahead 240 | ||
| 247 | #define __NR_io_setup 241 | ||
| 248 | #define __NR_io_destroy 242 | ||
| 249 | #define __NR_io_getevents 243 | ||
| 250 | #define __NR_io_submit 244 | ||
| 251 | #define __NR_io_cancel 245 | ||
| 252 | #define __NR_fadvise64 246 | ||
| 253 | #define __NR_exit_group 247 | ||
| 254 | #define __NR_lookup_dcookie 248 | ||
| 255 | #define __NR_epoll_create 249 | ||
| 256 | #define __NR_epoll_ctl 250 | ||
| 257 | #define __NR_epoll_wait 251 | ||
| 258 | #define __NR_remap_file_pages 252 | ||
| 259 | #define __NR_set_tid_address 253 | ||
| 260 | #define __NR_timer_create 254 | ||
| 261 | #define __NR_timer_settime 255 | ||
| 262 | #define __NR_timer_gettime 256 | ||
| 263 | #define __NR_timer_getoverrun 257 | ||
| 264 | #define __NR_timer_delete 258 | ||
| 265 | #define __NR_clock_settime 259 | ||
| 266 | #define __NR_clock_gettime 260 | ||
| 267 | #define __NR_clock_getres 261 | ||
| 268 | #define __NR_clock_nanosleep 262 | ||
| 269 | #define __NR_statfs64 263 | ||
| 270 | #define __NR_fstatfs64 264 | ||
| 271 | #define __NR_tgkill 265 | ||
| 272 | #define __NR_utimes 266 | ||
| 273 | #define __NR_fadvise64_64 267 | ||
| 274 | #define __NR_mbind 268 | ||
| 275 | #define __NR_get_mempolicy 269 | ||
| 276 | #define __NR_set_mempolicy 270 | ||
| 277 | #define __NR_mq_open 271 | ||
| 278 | #define __NR_mq_unlink 272 | ||
| 279 | #define __NR_mq_timedsend 273 | ||
| 280 | #define __NR_mq_timedreceive 274 | ||
| 281 | #define __NR_mq_notify 275 | ||
| 282 | #define __NR_mq_getsetattr 276 | ||
| 283 | #define __NR_waitid 277 | ||
| 284 | #define __NR_vserver 278 | ||
| 285 | #define __NR_add_key 279 | ||
| 286 | #define __NR_request_key 280 | ||
| 287 | #define __NR_keyctl 281 | ||
| 288 | #define __NR_ioprio_set 282 | ||
| 289 | #define __NR_ioprio_get 283 | ||
| 290 | #define __NR_inotify_init 284 | ||
| 291 | #define __NR_inotify_add_watch 285 | ||
| 292 | #define __NR_inotify_rm_watch 286 | ||
| 293 | #define __NR_migrate_pages 287 | ||
| 294 | #define __NR_openat 288 | ||
| 295 | #define __NR_mkdirat 289 | ||
| 296 | #define __NR_mknodat 290 | ||
| 297 | #define __NR_fchownat 291 | ||
| 298 | #define __NR_futimesat 292 | ||
| 299 | #define __NR_fstatat64 293 | ||
| 300 | #define __NR_unlinkat 294 | ||
| 301 | #define __NR_renameat 295 | ||
| 302 | #define __NR_linkat 296 | ||
| 303 | #define __NR_symlinkat 297 | ||
| 304 | #define __NR_readlinkat 298 | ||
| 305 | #define __NR_fchmodat 299 | ||
| 306 | #define __NR_faccessat 300 | ||
| 307 | #define __NR_pselect6 301 | ||
| 308 | #define __NR_ppoll 302 | ||
| 309 | #define __NR_unshare 303 | ||
| 310 | #define __NR_set_robust_list 304 | ||
| 311 | #define __NR_get_robust_list 305 | ||
| 312 | #define __NR_splice 306 | ||
| 313 | #define __NR_sync_file_range 307 | ||
| 314 | #define __NR_tee 308 | ||
| 315 | #define __NR_vmsplice 309 | ||
| 316 | #define __NR_move_pages 310 | ||
| 317 | #define __NR_sched_setaffinity 311 | ||
| 318 | #define __NR_sched_getaffinity 312 | ||
| 319 | #define __NR_kexec_load 313 | ||
| 320 | #define __NR_getcpu 314 | ||
| 321 | #define __NR_epoll_pwait 315 | ||
| 322 | #define __NR_utimensat 316 | ||
| 323 | #define __NR_signalfd 317 | ||
| 324 | #define __NR_timerfd_create 318 | ||
| 325 | #define __NR_eventfd 319 | ||
| 326 | #define __NR_fallocate 320 | ||
| 327 | #define __NR_timerfd_settime 321 | ||
| 328 | #define __NR_timerfd_gettime 322 | ||
| 329 | #define __NR_signalfd4 323 | ||
| 330 | #define __NR_eventfd2 324 | ||
| 331 | #define __NR_epoll_create1 325 | ||
| 332 | #define __NR_dup3 326 | ||
| 333 | #define __NR_pipe2 327 | ||
| 334 | #define __NR_inotify_init1 328 | ||
| 335 | |||
| 336 | #ifdef __KERNEL__ | ||
| 337 | |||
| 338 | #define NR_syscalls 329 | ||
| 339 | |||
| 340 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 341 | #define __ARCH_WANT_OLD_READDIR | ||
| 342 | #define __ARCH_WANT_OLD_STAT | ||
| 343 | #define __ARCH_WANT_STAT64 | ||
| 344 | #define __ARCH_WANT_SYS_ALARM | ||
| 345 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 346 | #define __ARCH_WANT_SYS_PAUSE | ||
| 347 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 348 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 349 | #define __ARCH_WANT_SYS_TIME | ||
| 350 | #define __ARCH_WANT_SYS_UTIME | ||
| 351 | #define __ARCH_WANT_SYS_WAITPID | ||
| 352 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 353 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 354 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 355 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 356 | #define __ARCH_WANT_SYS_NICE | ||
| 357 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 358 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 359 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 360 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 361 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 362 | |||
| 363 | /* | ||
| 364 | * "Conditional" syscalls | ||
| 365 | * | ||
| 366 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 367 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 368 | */ | ||
| 369 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
| 370 | |||
| 371 | #endif /* __KERNEL__ */ | ||
| 372 | #endif /* _ASM_M68K_UNISTD_H_ */ | ||
diff --git a/arch/m68k/include/asm/unistd_no.h b/arch/m68k/include/asm/unistd_no.h new file mode 100644 index 000000000000..b034a2f7b444 --- /dev/null +++ b/arch/m68k/include/asm/unistd_no.h | |||
| @@ -0,0 +1,372 @@ | |||
| 1 | #ifndef _ASM_M68K_UNISTD_H_ | ||
| 2 | #define _ASM_M68K_UNISTD_H_ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file contains the system call numbers. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define __NR_restart_syscall 0 | ||
| 9 | #define __NR_exit 1 | ||
| 10 | #define __NR_fork 2 | ||
| 11 | #define __NR_read 3 | ||
| 12 | #define __NR_write 4 | ||
| 13 | #define __NR_open 5 | ||
| 14 | #define __NR_close 6 | ||
| 15 | #define __NR_waitpid 7 | ||
| 16 | #define __NR_creat 8 | ||
| 17 | #define __NR_link 9 | ||
| 18 | #define __NR_unlink 10 | ||
| 19 | #define __NR_execve 11 | ||
| 20 | #define __NR_chdir 12 | ||
| 21 | #define __NR_time 13 | ||
| 22 | #define __NR_mknod 14 | ||
| 23 | #define __NR_chmod 15 | ||
| 24 | #define __NR_chown 16 | ||
| 25 | #define __NR_break 17 | ||
| 26 | #define __NR_oldstat 18 | ||
| 27 | #define __NR_lseek 19 | ||
| 28 | #define __NR_getpid 20 | ||
| 29 | #define __NR_mount 21 | ||
| 30 | #define __NR_umount 22 | ||
| 31 | #define __NR_setuid 23 | ||
| 32 | #define __NR_getuid 24 | ||
| 33 | #define __NR_stime 25 | ||
| 34 | #define __NR_ptrace 26 | ||
| 35 | #define __NR_alarm 27 | ||
| 36 | #define __NR_oldfstat 28 | ||
| 37 | #define __NR_pause 29 | ||
| 38 | #define __NR_utime 30 | ||
| 39 | #define __NR_stty 31 | ||
| 40 | #define __NR_gtty 32 | ||
| 41 | #define __NR_access 33 | ||
| 42 | #define __NR_nice 34 | ||
| 43 | #define __NR_ftime 35 | ||
| 44 | #define __NR_sync 36 | ||
| 45 | #define __NR_kill 37 | ||
| 46 | #define __NR_rename 38 | ||
| 47 | #define __NR_mkdir 39 | ||
| 48 | #define __NR_rmdir 40 | ||
| 49 | #define __NR_dup 41 | ||
| 50 | #define __NR_pipe 42 | ||
| 51 | #define __NR_times 43 | ||
| 52 | #define __NR_prof 44 | ||
| 53 | #define __NR_brk 45 | ||
| 54 | #define __NR_setgid 46 | ||
| 55 | #define __NR_getgid 47 | ||
| 56 | #define __NR_signal 48 | ||
| 57 | #define __NR_geteuid 49 | ||
| 58 | #define __NR_getegid 50 | ||
| 59 | #define __NR_acct 51 | ||
| 60 | #define __NR_umount2 52 | ||
| 61 | #define __NR_lock 53 | ||
| 62 | #define __NR_ioctl 54 | ||
| 63 | #define __NR_fcntl 55 | ||
| 64 | #define __NR_mpx 56 | ||
| 65 | #define __NR_setpgid 57 | ||
| 66 | #define __NR_ulimit 58 | ||
| 67 | #define __NR_oldolduname 59 | ||
| 68 | #define __NR_umask 60 | ||
| 69 | #define __NR_chroot 61 | ||
| 70 | #define __NR_ustat 62 | ||
| 71 | #define __NR_dup2 63 | ||
| 72 | #define __NR_getppid 64 | ||
| 73 | #define __NR_getpgrp 65 | ||
| 74 | #define __NR_setsid 66 | ||
| 75 | #define __NR_sigaction 67 | ||
| 76 | #define __NR_sgetmask 68 | ||
| 77 | #define __NR_ssetmask 69 | ||
| 78 | #define __NR_setreuid 70 | ||
| 79 | #define __NR_setregid 71 | ||
| 80 | #define __NR_sigsuspend 72 | ||
| 81 | #define __NR_sigpending 73 | ||
| 82 | #define __NR_sethostname 74 | ||
| 83 | #define __NR_setrlimit 75 | ||
| 84 | #define __NR_getrlimit 76 | ||
| 85 | #define __NR_getrusage 77 | ||
| 86 | #define __NR_gettimeofday 78 | ||
| 87 | #define __NR_settimeofday 79 | ||
| 88 | #define __NR_getgroups 80 | ||
| 89 | #define __NR_setgroups 81 | ||
| 90 | #define __NR_select 82 | ||
| 91 | #define __NR_symlink 83 | ||
| 92 | #define __NR_oldlstat 84 | ||
| 93 | #define __NR_readlink 85 | ||
| 94 | #define __NR_uselib 86 | ||
| 95 | #define __NR_swapon 87 | ||
| 96 | #define __NR_reboot 88 | ||
| 97 | #define __NR_readdir 89 | ||
| 98 | #define __NR_mmap 90 | ||
| 99 | #define __NR_munmap 91 | ||
| 100 | #define __NR_truncate 92 | ||
| 101 | #define __NR_ftruncate 93 | ||
| 102 | #define __NR_fchmod 94 | ||
| 103 | #define __NR_fchown 95 | ||
| 104 | #define __NR_getpriority 96 | ||
| 105 | #define __NR_setpriority 97 | ||
| 106 | #define __NR_profil 98 | ||
| 107 | #define __NR_statfs 99 | ||
| 108 | #define __NR_fstatfs 100 | ||
| 109 | #define __NR_ioperm 101 | ||
| 110 | #define __NR_socketcall 102 | ||
| 111 | #define __NR_syslog 103 | ||
| 112 | #define __NR_setitimer 104 | ||
| 113 | #define __NR_getitimer 105 | ||
| 114 | #define __NR_stat 106 | ||
| 115 | #define __NR_lstat 107 | ||
| 116 | #define __NR_fstat 108 | ||
| 117 | #define __NR_olduname 109 | ||
| 118 | #define __NR_iopl /* 110 */ not supported | ||
| 119 | #define __NR_vhangup 111 | ||
| 120 | #define __NR_idle /* 112 */ Obsolete | ||
| 121 | #define __NR_vm86 /* 113 */ not supported | ||
| 122 | #define __NR_wait4 114 | ||
| 123 | #define __NR_swapoff 115 | ||
| 124 | #define __NR_sysinfo 116 | ||
| 125 | #define __NR_ipc 117 | ||
| 126 | #define __NR_fsync 118 | ||
| 127 | #define __NR_sigreturn 119 | ||
| 128 | #define __NR_clone 120 | ||
| 129 | #define __NR_setdomainname 121 | ||
| 130 | #define __NR_uname 122 | ||
| 131 | #define __NR_cacheflush 123 | ||
| 132 | #define __NR_adjtimex 124 | ||
| 133 | #define __NR_mprotect 125 | ||
| 134 | #define __NR_sigprocmask 126 | ||
| 135 | #define __NR_create_module 127 | ||
| 136 | #define __NR_init_module 128 | ||
| 137 | #define __NR_delete_module 129 | ||
| 138 | #define __NR_get_kernel_syms 130 | ||
| 139 | #define __NR_quotactl 131 | ||
| 140 | #define __NR_getpgid 132 | ||
| 141 | #define __NR_fchdir 133 | ||
| 142 | #define __NR_bdflush 134 | ||
| 143 | #define __NR_sysfs 135 | ||
| 144 | #define __NR_personality 136 | ||
| 145 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 146 | #define __NR_setfsuid 138 | ||
| 147 | #define __NR_setfsgid 139 | ||
| 148 | #define __NR__llseek 140 | ||
| 149 | #define __NR_getdents 141 | ||
| 150 | #define __NR__newselect 142 | ||
| 151 | #define __NR_flock 143 | ||
| 152 | #define __NR_msync 144 | ||
| 153 | #define __NR_readv 145 | ||
| 154 | #define __NR_writev 146 | ||
| 155 | #define __NR_getsid 147 | ||
| 156 | #define __NR_fdatasync 148 | ||
| 157 | #define __NR__sysctl 149 | ||
| 158 | #define __NR_mlock 150 | ||
| 159 | #define __NR_munlock 151 | ||
| 160 | #define __NR_mlockall 152 | ||
| 161 | #define __NR_munlockall 153 | ||
| 162 | #define __NR_sched_setparam 154 | ||
| 163 | #define __NR_sched_getparam 155 | ||
| 164 | #define __NR_sched_setscheduler 156 | ||
| 165 | #define __NR_sched_getscheduler 157 | ||
| 166 | #define __NR_sched_yield 158 | ||
| 167 | #define __NR_sched_get_priority_max 159 | ||
| 168 | #define __NR_sched_get_priority_min 160 | ||
| 169 | #define __NR_sched_rr_get_interval 161 | ||
| 170 | #define __NR_nanosleep 162 | ||
| 171 | #define __NR_mremap 163 | ||
| 172 | #define __NR_setresuid 164 | ||
| 173 | #define __NR_getresuid 165 | ||
| 174 | #define __NR_getpagesize 166 | ||
| 175 | #define __NR_query_module 167 | ||
| 176 | #define __NR_poll 168 | ||
| 177 | #define __NR_nfsservctl 169 | ||
| 178 | #define __NR_setresgid 170 | ||
| 179 | #define __NR_getresgid 171 | ||
| 180 | #define __NR_prctl 172 | ||
| 181 | #define __NR_rt_sigreturn 173 | ||
| 182 | #define __NR_rt_sigaction 174 | ||
| 183 | #define __NR_rt_sigprocmask 175 | ||
| 184 | #define __NR_rt_sigpending 176 | ||
| 185 | #define __NR_rt_sigtimedwait 177 | ||
| 186 | #define __NR_rt_sigqueueinfo 178 | ||
| 187 | #define __NR_rt_sigsuspend 179 | ||
| 188 | #define __NR_pread64 180 | ||
| 189 | #define __NR_pwrite64 181 | ||
| 190 | #define __NR_lchown 182 | ||
| 191 | #define __NR_getcwd 183 | ||
| 192 | #define __NR_capget 184 | ||
| 193 | #define __NR_capset 185 | ||
| 194 | #define __NR_sigaltstack 186 | ||
| 195 | #define __NR_sendfile 187 | ||
| 196 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 197 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 198 | #define __NR_vfork 190 | ||
| 199 | #define __NR_ugetrlimit 191 | ||
| 200 | #define __NR_mmap2 192 | ||
| 201 | #define __NR_truncate64 193 | ||
| 202 | #define __NR_ftruncate64 194 | ||
| 203 | #define __NR_stat64 195 | ||
| 204 | #define __NR_lstat64 196 | ||
| 205 | #define __NR_fstat64 197 | ||
| 206 | #define __NR_chown32 198 | ||
| 207 | #define __NR_getuid32 199 | ||
| 208 | #define __NR_getgid32 200 | ||
| 209 | #define __NR_geteuid32 201 | ||
| 210 | #define __NR_getegid32 202 | ||
| 211 | #define __NR_setreuid32 203 | ||
| 212 | #define __NR_setregid32 204 | ||
| 213 | #define __NR_getgroups32 205 | ||
| 214 | #define __NR_setgroups32 206 | ||
| 215 | #define __NR_fchown32 207 | ||
| 216 | #define __NR_setresuid32 208 | ||
| 217 | #define __NR_getresuid32 209 | ||
| 218 | #define __NR_setresgid32 210 | ||
| 219 | #define __NR_getresgid32 211 | ||
| 220 | #define __NR_lchown32 212 | ||
| 221 | #define __NR_setuid32 213 | ||
| 222 | #define __NR_setgid32 214 | ||
| 223 | #define __NR_setfsuid32 215 | ||
| 224 | #define __NR_setfsgid32 216 | ||
| 225 | #define __NR_pivot_root 217 | ||
| 226 | #define __NR_getdents64 220 | ||
| 227 | #define __NR_gettid 221 | ||
| 228 | #define __NR_tkill 222 | ||
| 229 | #define __NR_setxattr 223 | ||
| 230 | #define __NR_lsetxattr 224 | ||
| 231 | #define __NR_fsetxattr 225 | ||
| 232 | #define __NR_getxattr 226 | ||
| 233 | #define __NR_lgetxattr 227 | ||
| 234 | #define __NR_fgetxattr 228 | ||
| 235 | #define __NR_listxattr 229 | ||
| 236 | #define __NR_llistxattr 230 | ||
| 237 | #define __NR_flistxattr 231 | ||
| 238 | #define __NR_removexattr 232 | ||
| 239 | #define __NR_lremovexattr 233 | ||
| 240 | #define __NR_fremovexattr 234 | ||
| 241 | #define __NR_futex 235 | ||
| 242 | #define __NR_sendfile64 236 | ||
| 243 | #define __NR_mincore 237 | ||
| 244 | #define __NR_madvise 238 | ||
| 245 | #define __NR_fcntl64 239 | ||
| 246 | #define __NR_readahead 240 | ||
| 247 | #define __NR_io_setup 241 | ||
| 248 | #define __NR_io_destroy 242 | ||
| 249 | #define __NR_io_getevents 243 | ||
| 250 | #define __NR_io_submit 244 | ||
| 251 | #define __NR_io_cancel 245 | ||
| 252 | #define __NR_fadvise64 246 | ||
| 253 | #define __NR_exit_group 247 | ||
| 254 | #define __NR_lookup_dcookie 248 | ||
| 255 | #define __NR_epoll_create 249 | ||
| 256 | #define __NR_epoll_ctl 250 | ||
| 257 | #define __NR_epoll_wait 251 | ||
| 258 | #define __NR_remap_file_pages 252 | ||
| 259 | #define __NR_set_tid_address 253 | ||
| 260 | #define __NR_timer_create 254 | ||
| 261 | #define __NR_timer_settime 255 | ||
| 262 | #define __NR_timer_gettime 256 | ||
| 263 | #define __NR_timer_getoverrun 257 | ||
| 264 | #define __NR_timer_delete 258 | ||
| 265 | #define __NR_clock_settime 259 | ||
| 266 | #define __NR_clock_gettime 260 | ||
| 267 | #define __NR_clock_getres 261 | ||
| 268 | #define __NR_clock_nanosleep 262 | ||
| 269 | #define __NR_statfs64 263 | ||
| 270 | #define __NR_fstatfs64 264 | ||
| 271 | #define __NR_tgkill 265 | ||
| 272 | #define __NR_utimes 266 | ||
| 273 | #define __NR_fadvise64_64 267 | ||
| 274 | #define __NR_mbind 268 | ||
| 275 | #define __NR_get_mempolicy 269 | ||
| 276 | #define __NR_set_mempolicy 270 | ||
| 277 | #define __NR_mq_open 271 | ||
| 278 | #define __NR_mq_unlink 272 | ||
| 279 | #define __NR_mq_timedsend 273 | ||
| 280 | #define __NR_mq_timedreceive 274 | ||
| 281 | #define __NR_mq_notify 275 | ||
| 282 | #define __NR_mq_getsetattr 276 | ||
| 283 | #define __NR_waitid 277 | ||
| 284 | #define __NR_vserver 278 | ||
| 285 | #define __NR_add_key 279 | ||
| 286 | #define __NR_request_key 280 | ||
| 287 | #define __NR_keyctl 281 | ||
| 288 | #define __NR_ioprio_set 282 | ||
| 289 | #define __NR_ioprio_get 283 | ||
| 290 | #define __NR_inotify_init 284 | ||
| 291 | #define __NR_inotify_add_watch 285 | ||
| 292 | #define __NR_inotify_rm_watch 286 | ||
| 293 | #define __NR_migrate_pages 287 | ||
| 294 | #define __NR_openat 288 | ||
| 295 | #define __NR_mkdirat 289 | ||
| 296 | #define __NR_mknodat 290 | ||
| 297 | #define __NR_fchownat 291 | ||
| 298 | #define __NR_futimesat 292 | ||
| 299 | #define __NR_fstatat64 293 | ||
| 300 | #define __NR_unlinkat 294 | ||
| 301 | #define __NR_renameat 295 | ||
| 302 | #define __NR_linkat 296 | ||
| 303 | #define __NR_symlinkat 297 | ||
| 304 | #define __NR_readlinkat 298 | ||
| 305 | #define __NR_fchmodat 299 | ||
| 306 | #define __NR_faccessat 300 | ||
| 307 | #define __NR_pselect6 301 | ||
| 308 | #define __NR_ppoll 302 | ||
| 309 | #define __NR_unshare 303 | ||
| 310 | #define __NR_set_robust_list 304 | ||
| 311 | #define __NR_get_robust_list 305 | ||
| 312 | #define __NR_splice 306 | ||
| 313 | #define __NR_sync_file_range 307 | ||
| 314 | #define __NR_tee 308 | ||
| 315 | #define __NR_vmsplice 309 | ||
| 316 | #define __NR_move_pages 310 | ||
| 317 | #define __NR_sched_setaffinity 311 | ||
| 318 | #define __NR_sched_getaffinity 312 | ||
| 319 | #define __NR_kexec_load 313 | ||
| 320 | #define __NR_getcpu 314 | ||
| 321 | #define __NR_epoll_pwait 315 | ||
| 322 | #define __NR_utimensat 316 | ||
| 323 | #define __NR_signalfd 317 | ||
| 324 | #define __NR_timerfd_create 318 | ||
| 325 | #define __NR_eventfd 319 | ||
| 326 | #define __NR_fallocate 320 | ||
| 327 | #define __NR_timerfd_settime 321 | ||
| 328 | #define __NR_timerfd_gettime 322 | ||
| 329 | #define __NR_signalfd4 323 | ||
| 330 | #define __NR_eventfd2 324 | ||
| 331 | #define __NR_epoll_create1 325 | ||
| 332 | #define __NR_dup3 326 | ||
| 333 | #define __NR_pipe2 327 | ||
| 334 | #define __NR_inotify_init1 328 | ||
| 335 | |||
| 336 | #ifdef __KERNEL__ | ||
| 337 | |||
| 338 | #define NR_syscalls 329 | ||
| 339 | |||
| 340 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 341 | #define __ARCH_WANT_OLD_READDIR | ||
| 342 | #define __ARCH_WANT_OLD_STAT | ||
| 343 | #define __ARCH_WANT_STAT64 | ||
| 344 | #define __ARCH_WANT_SYS_ALARM | ||
| 345 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 346 | #define __ARCH_WANT_SYS_PAUSE | ||
| 347 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 348 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 349 | #define __ARCH_WANT_SYS_TIME | ||
| 350 | #define __ARCH_WANT_SYS_UTIME | ||
| 351 | #define __ARCH_WANT_SYS_WAITPID | ||
| 352 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 353 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 354 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 355 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 356 | #define __ARCH_WANT_SYS_NICE | ||
| 357 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 358 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 359 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 360 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 361 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 362 | |||
| 363 | /* | ||
| 364 | * "Conditional" syscalls | ||
| 365 | * | ||
| 366 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 367 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 368 | */ | ||
| 369 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
| 370 | |||
| 371 | #endif /* __KERNEL__ */ | ||
| 372 | #endif /* _ASM_M68K_UNISTD_H_ */ | ||
diff --git a/arch/m68k/include/asm/user.h b/arch/m68k/include/asm/user.h new file mode 100644 index 000000000000..f1f478d6e050 --- /dev/null +++ b/arch/m68k/include/asm/user.h | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | #ifndef _M68K_USER_H | ||
| 2 | #define _M68K_USER_H | ||
| 3 | |||
| 4 | /* Core file format: The core file is written in such a way that gdb | ||
| 5 | can understand it and provide useful information to the user (under | ||
| 6 | linux we use the 'trad-core' bfd). There are quite a number of | ||
| 7 | obstacles to being able to view the contents of the floating point | ||
| 8 | registers, and until these are solved you will not be able to view the | ||
| 9 | contents of them. Actually, you can read in the core file and look at | ||
| 10 | the contents of the user struct to find out what the floating point | ||
| 11 | registers contain. | ||
| 12 | The actual file contents are as follows: | ||
| 13 | UPAGE: 1 page consisting of a user struct that tells gdb what is present | ||
| 14 | in the file. Directly after this is a copy of the task_struct, which | ||
| 15 | is currently not used by gdb, but it may come in useful at some point. | ||
| 16 | All of the registers are stored as part of the upage. The upage should | ||
| 17 | always be only one page. | ||
| 18 | DATA: The data area is stored. We use current->end_text to | ||
| 19 | current->brk to pick up all of the user variables, plus any memory | ||
| 20 | that may have been malloced. No attempt is made to determine if a page | ||
| 21 | is demand-zero or if a page is totally unused, we just cover the entire | ||
| 22 | range. All of the addresses are rounded in such a way that an integral | ||
| 23 | number of pages is written. | ||
| 24 | STACK: We need the stack information in order to get a meaningful | ||
| 25 | backtrace. We need to write the data from (esp) to | ||
| 26 | current->start_stack, so we round each of these off in order to be able | ||
| 27 | to write an integer number of pages. | ||
| 28 | The minimum core file size is 3 pages, or 12288 bytes. | ||
| 29 | */ | ||
| 30 | |||
| 31 | struct user_m68kfp_struct { | ||
| 32 | unsigned long fpregs[8*3]; /* fp0-fp7 registers */ | ||
| 33 | unsigned long fpcntl[3]; /* fp control regs */ | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* This is the old layout of "struct pt_regs" as of Linux 1.x, and | ||
| 37 | is still the layout used by user (the new pt_regs doesn't have | ||
| 38 | all registers). */ | ||
| 39 | struct user_regs_struct { | ||
| 40 | long d1,d2,d3,d4,d5,d6,d7; | ||
| 41 | long a0,a1,a2,a3,a4,a5,a6; | ||
| 42 | long d0; | ||
| 43 | long usp; | ||
| 44 | long orig_d0; | ||
| 45 | short stkadj; | ||
| 46 | short sr; | ||
| 47 | long pc; | ||
| 48 | short fmtvec; | ||
| 49 | short __fill; | ||
| 50 | }; | ||
| 51 | |||
| 52 | |||
| 53 | /* When the kernel dumps core, it starts by dumping the user struct - | ||
| 54 | this will be used by gdb to figure out where the data and stack segments | ||
| 55 | are within the file, and what virtual addresses to use. */ | ||
| 56 | struct user{ | ||
| 57 | /* We start with the registers, to mimic the way that "memory" is returned | ||
| 58 | from the ptrace(3,...) function. */ | ||
| 59 | struct user_regs_struct regs; /* Where the registers are actually stored */ | ||
| 60 | /* ptrace does not yet supply these. Someday.... */ | ||
| 61 | int u_fpvalid; /* True if math co-processor being used. */ | ||
| 62 | /* for this mess. Not yet used. */ | ||
| 63 | struct user_m68kfp_struct m68kfp; /* Math Co-processor registers. */ | ||
| 64 | /* The rest of this junk is to help gdb figure out what goes where */ | ||
| 65 | unsigned long int u_tsize; /* Text segment size (pages). */ | ||
| 66 | unsigned long int u_dsize; /* Data segment size (pages). */ | ||
| 67 | unsigned long int u_ssize; /* Stack segment size (pages). */ | ||
| 68 | unsigned long start_code; /* Starting virtual address of text. */ | ||
| 69 | unsigned long start_stack; /* Starting virtual address of stack area. | ||
| 70 | This is actually the bottom of the stack, | ||
| 71 | the top of the stack is always found in the | ||
| 72 | esp register. */ | ||
| 73 | long int signal; /* Signal that caused the core dump. */ | ||
| 74 | int reserved; /* No longer used */ | ||
| 75 | unsigned long u_ar0; /* Used by gdb to help find the values for */ | ||
| 76 | /* the registers. */ | ||
| 77 | struct user_m68kfp_struct* u_fpstate; /* Math Co-processor pointer. */ | ||
| 78 | unsigned long magic; /* To uniquely identify a core file */ | ||
| 79 | char u_comm[32]; /* User command that was responsible */ | ||
| 80 | }; | ||
| 81 | #define NBPG 4096 | ||
| 82 | #define UPAGES 1 | ||
| 83 | #define HOST_TEXT_START_ADDR (u.start_code) | ||
| 84 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | ||
| 85 | |||
| 86 | #endif | ||
diff --git a/arch/m68k/include/asm/virtconvert.h b/arch/m68k/include/asm/virtconvert.h new file mode 100644 index 000000000000..22ab05c9c52b --- /dev/null +++ b/arch/m68k/include/asm/virtconvert.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | #ifndef __VIRT_CONVERT__ | ||
| 2 | #define __VIRT_CONVERT__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Macros used for converting between virtual and physical mappings. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifdef __KERNEL__ | ||
| 9 | |||
| 10 | #include <linux/compiler.h> | ||
| 11 | #include <linux/mmzone.h> | ||
| 12 | #include <asm/setup.h> | ||
| 13 | #include <asm/page.h> | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Change virtual addresses to physical addresses and vv. | ||
| 17 | */ | ||
| 18 | static inline unsigned long virt_to_phys(void *address) | ||
| 19 | { | ||
| 20 | return __pa(address); | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline void *phys_to_virt(unsigned long address) | ||
| 24 | { | ||
| 25 | return __va(address); | ||
| 26 | } | ||
| 27 | |||
| 28 | /* Permanent address of a page. */ | ||
| 29 | #ifdef CONFIG_SINGLE_MEMORY_CHUNK | ||
| 30 | #define page_to_phys(page) \ | ||
| 31 | __pa(PAGE_OFFSET + (((page) - pg_data_map[0].node_mem_map) << PAGE_SHIFT)) | ||
| 32 | #else | ||
| 33 | #define page_to_phys(_page) ({ \ | ||
| 34 | struct page *__page = _page; \ | ||
| 35 | struct pglist_data *pgdat; \ | ||
| 36 | pgdat = pg_data_table[page_to_nid(__page)]; \ | ||
| 37 | page_to_pfn(__page) << PAGE_SHIFT; \ | ||
| 38 | }) | ||
| 39 | #endif | ||
| 40 | |||
| 41 | /* | ||
| 42 | * IO bus memory addresses are 1:1 with the physical address, | ||
| 43 | */ | ||
| 44 | #define virt_to_bus virt_to_phys | ||
| 45 | #define bus_to_virt phys_to_virt | ||
| 46 | |||
| 47 | #endif | ||
| 48 | #endif | ||
diff --git a/arch/m68k/include/asm/xor.h b/arch/m68k/include/asm/xor.h new file mode 100644 index 000000000000..c82eb12a5b18 --- /dev/null +++ b/arch/m68k/include/asm/xor.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-generic/xor.h> | |||
diff --git a/arch/m68k/include/asm/zorro.h b/arch/m68k/include/asm/zorro.h new file mode 100644 index 000000000000..5ce97c22b582 --- /dev/null +++ b/arch/m68k/include/asm/zorro.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | #ifndef _ASM_M68K_ZORRO_H | ||
| 2 | #define _ASM_M68K_ZORRO_H | ||
| 3 | |||
| 4 | #include <asm/raw_io.h> | ||
| 5 | |||
| 6 | #define z_readb raw_inb | ||
| 7 | #define z_readw raw_inw | ||
| 8 | #define z_readl raw_inl | ||
| 9 | |||
| 10 | #define z_writeb raw_outb | ||
| 11 | #define z_writew raw_outw | ||
| 12 | #define z_writel raw_outl | ||
| 13 | |||
| 14 | #define z_memset_io(a,b,c) memset((void *)(a),(b),(c)) | ||
| 15 | #define z_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) | ||
| 16 | #define z_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) | ||
| 17 | |||
| 18 | static inline void __iomem *z_remap_nocache_ser(unsigned long physaddr, | ||
| 19 | unsigned long size) | ||
| 20 | { | ||
| 21 | return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline void __iomem *z_remap_nocache_nonser(unsigned long physaddr, | ||
| 25 | unsigned long size) | ||
| 26 | { | ||
| 27 | return __ioremap(physaddr, size, IOMAP_NOCACHE_NONSER); | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline void __iomem *z_remap_writethrough(unsigned long physaddr, | ||
| 31 | unsigned long size) | ||
| 32 | { | ||
| 33 | return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); | ||
| 34 | } | ||
| 35 | static inline void __iomem *z_remap_fullcache(unsigned long physaddr, | ||
| 36 | unsigned long size) | ||
| 37 | { | ||
| 38 | return __ioremap(physaddr, size, IOMAP_FULL_CACHING); | ||
| 39 | } | ||
| 40 | |||
| 41 | #define z_unmap iounmap | ||
| 42 | #define z_iounmap iounmap | ||
| 43 | #define z_ioremap z_remap_nocache_ser | ||
| 44 | |||
| 45 | #endif /* _ASM_M68K_ZORRO_H */ | ||