63 files changed, 2973 insertions, 1576 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 62d686f0b426..d13add71f72a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
 obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
-obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o
+obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index bba5a560e02b..feb65787c30b 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -31,6 +31,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/stamp9g20.h>
 #include "sam9_smc.h"
 #include "generic.h"
@@ -38,11 +39,7 @@
 static void __init pcontrol_g20_map_io(void)
 {
-        /* Initialize processor: 18.432 MHz crystal */
+        stamp9g20_map_io();
-        at91sam9260_initialize(18432000);
-        /* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */
-        at91_register_uart(0, 0, 0);
        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback  A2 */
        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
@@ -54,9 +51,6 @@ static void __init pcontrol_g20_map_io(void)
        /* USART2 on ttyS3. (Rx, Tx)  9bit-Bus  Multidrop-mode  X4 */
        at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
@@ -66,38 +60,6 @@ static void __init init_irq(void)
 }
-/*
- * NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB
- */
-static struct atmel_nand_data __initdata nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .rdy_pin        = AT91_PIN_PC13,
-        .enable_pin     = AT91_PIN_PC14,
-};
-/*
- * Bus timings; unit = 7.57ns
- */
-static struct sam9_smc_config __initdata nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
-                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
 static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
        .ncs_read_setup         = 16,
        .nrd_setup              = 18,
@@ -138,14 +100,6 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
        .tdf_cycles             = 1,
 } };
-static void __init add_device_nand(void)
-{
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &nand_smc_config);
-        at91_add_device_nand(&nand_data);
-}
 static void __init add_device_pcontrol(void)
 {
        /* configure chip-select 4 (IO compatible to 8051  X4 ) */
@@ -156,23 +110,6 @@ static void __init add_device_pcontrol(void)
 /*
- * MCI (SD/MMC)
- * det_pin, wp_pin and vcc_pin are not connected
- */
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-static struct mci_platform_data __initdata mmc_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-        },
-};
-#else
-static struct at91_mmc_data __initdata mmc_data = {
-        .wire4          = 1,
-};
-#endif
-/*
 * USB Host port
 */
 static struct at91_usbh_data __initdata usbh_data = {
@@ -265,42 +202,13 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
 };
-/*
- * Dallas 1-Wire  DS2431
- */
-static struct w1_gpio_platform_data w1_gpio_pdata = {
-        .pin            = AT91_PIN_PA29,
-        .is_open_drain  = 1,
-};
-static struct platform_device w1_device = {
-        .name                   = "w1-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &w1_gpio_pdata,
-};
-static void add_wire1(void)
-{
-        at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
-        at91_set_multi_drive(w1_gpio_pdata.pin, 1);
-        platform_device_register(&w1_device);
-}
 static void __init pcontrol_g20_board_init(void)
 {
-        at91_add_device_serial();
+        stamp9g20_board_init();
-        add_device_nand();
-#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
-        at91_add_device_mci(0, &mmc_data);
-#else
-        at91_add_device_mmc(0, &mmc_data);
-#endif
        at91_add_device_usbh(&usbh_data);
        at91_add_device_eth(&macb_data);
        at91_add_device_i2c(pcontrol_g20_i2c_devices,
                ARRAY_SIZE(pcontrol_g20_i2c_devices));
-        add_wire1();
        add_device_pcontrol();
        at91_add_device_spi(pcontrol_g20_spi_devices,
                ARRAY_SIZE(pcontrol_g20_spi_devices));
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 5206eef4a67e..f8902b118960 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -32,7 +32,7 @@
 #include "generic.h"
-static void __init portuxg20_map_io(void)
+void __init stamp9g20_map_io(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91sam9260_initialize(18432000);
@@ -40,6 +40,24 @@ static void __init portuxg20_map_io(void)
        /* DGBU on ttyS0. (Rx & Tx only) */
        at91_register_uart(0, 0, 0);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init stamp9g20evb_map_io(void)
+{
+        stamp9g20_map_io();
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
+                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
+}
+static void __init portuxg20_map_io(void)
+{
+        stamp9g20_map_io();
        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
@@ -56,26 +74,6 @@ static void __init portuxg20_map_io(void)
        /* USART5 on ttyS6. (Rx, Tx only) */
        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-static void __init stamp9g20_map_io(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91sam9260_initialize(18432000);
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
-                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static void __init init_irq(void)
@@ -156,7 +154,7 @@ static struct at91_udc_data __initdata portuxg20_udc_data = {
        .pullup_pin     = 0,            /* pull-up driven by UDC */
 };
-static struct at91_udc_data __initdata stamp9g20_udc_data = {
+static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
        .vbus_pin       = AT91_PIN_PA22,
        .pullup_pin     = 0,            /* pull-up driven by UDC */
 };
@@ -190,7 +188,7 @@ static struct gpio_led portuxg20_leds[] = {
        }
 };
-static struct gpio_led stamp9g20_leds[] = {
+static struct gpio_led stamp9g20evb_leds[] = {
        {
                .name                   = "D8",
                .gpio                   = AT91_PIN_PB18,
@@ -250,7 +248,7 @@ void add_w1(void)
 }
-static void __init generic_board_init(void)
+void __init stamp9g20_board_init(void)
 {
        /* Serial */
        at91_add_device_serial();
@@ -262,34 +260,40 @@ static void __init generic_board_init(void)
 #else
        at91_add_device_mmc(0, &mmc_data);
 #endif
-        /* USB Host */
-        at91_add_device_usbh(&usbh_data);
-        /* Ethernet */
-        at91_add_device_eth(&macb_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
        /* W1 */
        add_w1();
 }
 static void __init portuxg20_board_init(void)
 {
-        generic_board_init();
+        stamp9g20_board_init();
-        /* SPI */
+        /* USB Host */
-        at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
+        at91_add_device_usbh(&usbh_data);
        /* USB Device */
        at91_add_device_udc(&portuxg20_udc_data);
+        /* Ethernet */
+        at91_add_device_eth(&macb_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* SPI */
+        at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
        /* LEDs */
        at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
 }
-static void __init stamp9g20_board_init(void)
+static void __init stamp9g20evb_board_init(void)
 {
-        generic_board_init();
+        stamp9g20_board_init();
+        /* USB Host */
+        at91_add_device_usbh(&usbh_data);
        /* USB Device */
-        at91_add_device_udc(&stamp9g20_udc_data);
+        at91_add_device_udc(&stamp9g20evb_udc_data);
+        /* Ethernet */
+        at91_add_device_eth(&macb_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
        /* LEDs */
-        at91_gpio_leds(stamp9g20_leds, ARRAY_SIZE(stamp9g20_leds));
+        at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
 }
 MACHINE_START(PORTUXG20, "taskit PortuxG20")
@@ -305,7 +309,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
        /* Maintainer: taskit GmbH */
        .boot_params    = AT91_SDRAM_BASE + 0x100,
        .timer          = &at91sam926x_timer,
-        .map_io         = stamp9g20_map_io,
+        .map_io         = stamp9g20evb_map_io,
        .init_irq       = init_irq,
-        .init_machine   = stamp9g20_board_init,
+        .init_machine   = stamp9g20evb_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 7525cee3983f..9113da6845f1 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -658,7 +658,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        /* Now set uhpck values */
        uhpck.parent = &utmi_clk;
        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-        uhpck.rate_hz = utmi_clk.parent->rate_hz;
+        uhpck.rate_hz = utmi_clk.rate_hz;
        uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
new file mode 100644
index 000000000000..6120f9c46d59
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_STAMP9G20_H
+#define __MACH_STAMP9G20_H
+void stamp9g20_map_io(void);
+void stamp9g20_board_init(void);
+#endif
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 0b1c07ffa2f1..6ee19504845f 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,7 @@
 #
 # Common support
-obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o
+obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o
 obj-y += clock.o clock_data.o opp_data.o
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index e1439506eba9..bd0495a9ac3b 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -43,84 +43,82 @@
 static u8 ams_delta_latch1_reg;
 static u16 ams_delta_latch2_reg;
-static int ams_delta_keymap[] = {
+static const unsigned int ams_delta_keymap[] = {
        KEY(0, 0, KEY_F1),              /* Advert    */
-        KEY(3, 0, KEY_COFFEE),          /* Games     */
+        KEY(0, 3, KEY_COFFEE),          /* Games     */
-        KEY(2, 0, KEY_QUESTION),        /* Directory */
+        KEY(0, 2, KEY_QUESTION),        /* Directory */
-        KEY(3, 2, KEY_CONNECT),         /* Internet  */
+        KEY(2, 3, KEY_CONNECT),         /* Internet  */
-        KEY(2, 1, KEY_SHOP),            /* Services  */
+        KEY(1, 2, KEY_SHOP),            /* Services  */
        KEY(1, 1, KEY_PHONE),           /* VoiceMail */
-        KEY(1, 0, KEY_DELETE),          /* Delete    */
+        KEY(0, 1, KEY_DELETE),          /* Delete    */
        KEY(2, 2, KEY_PLAY),            /* Play      */
-        KEY(0, 1, KEY_PAGEUP),          /* Up        */
+        KEY(1, 0, KEY_PAGEUP),          /* Up        */
-        KEY(3, 1, KEY_PAGEDOWN),        /* Down      */
+        KEY(1, 3, KEY_PAGEDOWN),        /* Down      */
-        KEY(0, 2, KEY_EMAIL),           /* ReadEmail */
+        KEY(2, 0, KEY_EMAIL),           /* ReadEmail */
-        KEY(1, 2, KEY_STOP),            /* Stop      */
+        KEY(2, 1, KEY_STOP),            /* Stop      */
        /* Numeric keypad portion */
-        KEY(7, 0, KEY_KP1),
+        KEY(0, 7, KEY_KP1),
-        KEY(6, 0, KEY_KP2),
+        KEY(0, 6, KEY_KP2),
-        KEY(5, 0, KEY_KP3),
+        KEY(0, 5, KEY_KP3),
-        KEY(7, 1, KEY_KP4),
+        KEY(1, 7, KEY_KP4),
-        KEY(6, 1, KEY_KP5),
+        KEY(1, 6, KEY_KP5),
-        KEY(5, 1, KEY_KP6),
+        KEY(1, 5, KEY_KP6),
-        KEY(7, 2, KEY_KP7),
+        KEY(2, 7, KEY_KP7),
-        KEY(6, 2, KEY_KP8),
+        KEY(2, 6, KEY_KP8),
-        KEY(5, 2, KEY_KP9),
+        KEY(2, 5, KEY_KP9),
-        KEY(6, 3, KEY_KP0),
+        KEY(3, 6, KEY_KP0),
-        KEY(7, 3, KEY_KPASTERISK),
+        KEY(3, 7, KEY_KPASTERISK),
-        KEY(5, 3, KEY_KPDOT),           /* # key     */
+        KEY(3, 5, KEY_KPDOT),           /* # key     */
-        KEY(2, 7, KEY_NUMLOCK),         /* Mute      */
+        KEY(7, 2, KEY_NUMLOCK),         /* Mute      */
-        KEY(1, 7, KEY_KPMINUS),         /* Recall    */
+        KEY(7, 1, KEY_KPMINUS),         /* Recall    */
-        KEY(1, 6, KEY_KPPLUS),          /* Redial    */
+        KEY(6, 1, KEY_KPPLUS),          /* Redial    */
-        KEY(6, 7, KEY_KPSLASH),         /* Handsfree */
+        KEY(7, 6, KEY_KPSLASH),         /* Handsfree */
-        KEY(0, 6, KEY_ENTER),           /* Video     */
+        KEY(6, 0, KEY_ENTER),           /* Video     */
-        KEY(4, 7, KEY_CAMERA),          /* Photo     */
+        KEY(7, 4, KEY_CAMERA),          /* Photo     */
-        KEY(4, 0, KEY_F2),              /* Home      */
+        KEY(0, 4, KEY_F2),              /* Home      */
-        KEY(4, 1, KEY_F3),              /* Office    */
+        KEY(1, 4, KEY_F3),              /* Office    */
-        KEY(4, 2, KEY_F4),              /* Mobile    */
+        KEY(2, 4, KEY_F4),              /* Mobile    */
        KEY(7, 7, KEY_F5),              /* SMS       */
-        KEY(5, 7, KEY_F6),              /* Email     */
+        KEY(7, 5, KEY_F6),              /* Email     */
        /* QWERTY portion of keypad */
-        KEY(4, 3, KEY_Q),
+        KEY(3, 4, KEY_Q),
        KEY(3, 3, KEY_W),
-        KEY(2, 3, KEY_E),
+        KEY(3, 2, KEY_E),
-        KEY(1, 3, KEY_R),
+        KEY(3, 1, KEY_R),
-        KEY(0, 3, KEY_T),
+        KEY(3, 0, KEY_T),
-        KEY(7, 4, KEY_Y),
+        KEY(4, 7, KEY_Y),
-        KEY(6, 4, KEY_U),
+        KEY(4, 6, KEY_U),
-        KEY(5, 4, KEY_I),
+        KEY(4, 5, KEY_I),
        KEY(4, 4, KEY_O),
-        KEY(3, 4, KEY_P),
+        KEY(4, 3, KEY_P),
-        KEY(2, 4, KEY_A),
+        KEY(4, 2, KEY_A),
-        KEY(1, 4, KEY_S),
+        KEY(4, 1, KEY_S),
-        KEY(0, 4, KEY_D),
+        KEY(4, 0, KEY_D),
-        KEY(7, 5, KEY_F),
+        KEY(5, 7, KEY_F),
-        KEY(6, 5, KEY_G),
+        KEY(5, 6, KEY_G),
        KEY(5, 5, KEY_H),
-        KEY(4, 5, KEY_J),
+        KEY(5, 4, KEY_J),
-        KEY(3, 5, KEY_K),
+        KEY(5, 3, KEY_K),
-        KEY(2, 5, KEY_L),
+        KEY(5, 2, KEY_L),
-        KEY(1, 5, KEY_Z),
+        KEY(5, 1, KEY_Z),
-        KEY(0, 5, KEY_X),
+        KEY(5, 0, KEY_X),
-        KEY(7, 6, KEY_C),
+        KEY(6, 7, KEY_C),
        KEY(6, 6, KEY_V),
-        KEY(5, 6, KEY_B),
+        KEY(6, 5, KEY_B),
-        KEY(4, 6, KEY_N),
+        KEY(6, 4, KEY_N),
-        KEY(3, 6, KEY_M),
+        KEY(6, 3, KEY_M),
-        KEY(2, 6, KEY_SPACE),
+        KEY(6, 2, KEY_SPACE),
-        KEY(0, 7, KEY_LEFTSHIFT),       /* Vol up    */
+        KEY(7, 0, KEY_LEFTSHIFT),       /* Vol up    */
-        KEY(3, 7, KEY_LEFTCTRL),        /* Vol down  */
+        KEY(7, 3, KEY_LEFTCTRL),        /* Vol down  */
-        0
 };
 void ams_delta_latch1_write(u8 mask, u8 value)
@@ -189,11 +187,15 @@ static struct resource ams_delta_kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data ams_delta_keymap_data = {
+        .keymap         = ams_delta_keymap,
+        .keymap_size    = ARRAY_SIZE(ams_delta_keymap),
+};
 static struct omap_kp_platform_data ams_delta_kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = ams_delta_keymap,
+        .keymap_data    = &ams_delta_keymap_data,
-        .keymapsize     = ARRAY_SIZE(ams_delta_keymap),
        .delay          = 9,
 };
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 0c3f396328bd..0efb9dbae44c 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -69,36 +69,35 @@
 #define fsample_cpld_clear(bit) \
    fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
-static int fsample_keymap[] = {
+static const unsigned int fsample_keymap[] = {
-        KEY(0,0,KEY_UP),
+        KEY(0, 0, KEY_UP),
-        KEY(0,1,KEY_RIGHT),
+        KEY(1, 0, KEY_RIGHT),
-        KEY(0,2,KEY_LEFT),
+        KEY(2, 0, KEY_LEFT),
-        KEY(0,3,KEY_DOWN),
+        KEY(3, 0, KEY_DOWN),
-        KEY(0,4,KEY_ENTER),
+        KEY(4, 0, KEY_ENTER),
-        KEY(1,0,KEY_F10),
+        KEY(0, 1, KEY_F10),
-        KEY(1,1,KEY_SEND),
+        KEY(1, 1, KEY_SEND),
-        KEY(1,2,KEY_END),
+        KEY(2, 1, KEY_END),
-        KEY(1,3,KEY_VOLUMEDOWN),
+        KEY(3, 1, KEY_VOLUMEDOWN),
-        KEY(1,4,KEY_VOLUMEUP),
+        KEY(4, 1, KEY_VOLUMEUP),
-        KEY(1,5,KEY_RECORD),
+        KEY(5, 1, KEY_RECORD),
-        KEY(2,0,KEY_F9),
+        KEY(0, 2, KEY_F9),
-        KEY(2,1,KEY_3),
+        KEY(1, 2, KEY_3),
-        KEY(2,2,KEY_6),
+        KEY(2, 2, KEY_6),
-        KEY(2,3,KEY_9),
+        KEY(3, 2, KEY_9),
-        KEY(2,4,KEY_KPDOT),
+        KEY(4, 2, KEY_KPDOT),
-        KEY(3,0,KEY_BACK),
+        KEY(0, 3, KEY_BACK),
-        KEY(3,1,KEY_2),
+        KEY(1, 3, KEY_2),
-        KEY(3,2,KEY_5),
+        KEY(2, 3, KEY_5),
-        KEY(3,3,KEY_8),
+        KEY(3, 3, KEY_8),
-        KEY(3,4,KEY_0),
+        KEY(4, 3, KEY_0),
-        KEY(3,5,KEY_KPSLASH),
+        KEY(5, 3, KEY_KPSLASH),
-        KEY(4,0,KEY_HOME),
+        KEY(0, 4, KEY_HOME),
-        KEY(4,1,KEY_1),
+        KEY(1, 4, KEY_1),
-        KEY(4,2,KEY_4),
+        KEY(2, 4, KEY_4),
-        KEY(4,3,KEY_7),
+        KEY(3, 4, KEY_7),
-        KEY(4,4,KEY_KPASTERISK),
+        KEY(4, 4, KEY_KPASTERISK),
-        KEY(4,5,KEY_POWER),
+        KEY(5, 4, KEY_POWER),
-        0
 };
 static struct smc91x_platdata smc91x_info = {
@@ -253,11 +252,15 @@ static struct resource kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data fsample_keymap_data = {
+        .keymap         = fsample_keymap,
+        .keymap_size    = ARRAY_SIZE(fsample_keymap),
+};
 static struct omap_kp_platform_data kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = fsample_keymap,
+        .keymap_data    = &fsample_keymap_data,
-        .keymapsize     = ARRAY_SIZE(fsample_keymap),
        .delay          = 4,
 };
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 082a73ca5564..28b84aa9bdba 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -52,43 +52,42 @@
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
-static int h2_keymap[] = {
+static const unsigned int h2_keymap[] = {
        KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
+        KEY(1, 0, KEY_RIGHT),
-        KEY(0, 2, KEY_3),
+        KEY(2, 0, KEY_3),
-        KEY(0, 3, KEY_F10),
+        KEY(3, 0, KEY_F10),
-        KEY(0, 4, KEY_F5),
+        KEY(4, 0, KEY_F5),
-        KEY(0, 5, KEY_9),
+        KEY(5, 0, KEY_9),
-        KEY(1, 0, KEY_DOWN),
+        KEY(0, 1, KEY_DOWN),
        KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_2),
+        KEY(2, 1, KEY_2),
-        KEY(1, 3, KEY_F9),
+        KEY(3, 1, KEY_F9),
-        KEY(1, 4, KEY_F7),
+        KEY(4, 1, KEY_F7),
-        KEY(1, 5, KEY_0),
+        KEY(5, 1, KEY_0),
-        KEY(2, 0, KEY_ENTER),
+        KEY(0, 2, KEY_ENTER),
-        KEY(2, 1, KEY_6),
+        KEY(1, 2, KEY_6),
        KEY(2, 2, KEY_1),
-        KEY(2, 3, KEY_F2),
+        KEY(3, 2, KEY_F2),
-        KEY(2, 4, KEY_F6),
+        KEY(4, 2, KEY_F6),
-        KEY(2, 5, KEY_HOME),
+        KEY(5, 2, KEY_HOME),
-        KEY(3, 0, KEY_8),
+        KEY(0, 3, KEY_8),
-        KEY(3, 1, KEY_5),
+        KEY(1, 3, KEY_5),
-        KEY(3, 2, KEY_F12),
+        KEY(2, 3, KEY_F12),
        KEY(3, 3, KEY_F3),
-        KEY(3, 4, KEY_F8),
+        KEY(4, 3, KEY_F8),
-        KEY(3, 5, KEY_END),
+        KEY(5, 3, KEY_END),
-        KEY(4, 0, KEY_7),
+        KEY(0, 4, KEY_7),
-        KEY(4, 1, KEY_4),
+        KEY(1, 4, KEY_4),
-        KEY(4, 2, KEY_F11),
+        KEY(2, 4, KEY_F11),
-        KEY(4, 3, KEY_F1),
+        KEY(3, 4, KEY_F1),
        KEY(4, 4, KEY_F4),
-        KEY(4, 5, KEY_ESC),
+        KEY(5, 4, KEY_ESC),
-        KEY(5, 0, KEY_F13),
+        KEY(0, 5, KEY_F13),
-        KEY(5, 1, KEY_F14),
+        KEY(1, 5, KEY_F14),
-        KEY(5, 2, KEY_F15),
+        KEY(2, 5, KEY_F15),
-        KEY(5, 3, KEY_F16),
+        KEY(3, 5, KEY_F16),
-        KEY(5, 4, KEY_SLEEP),
+        KEY(4, 5, KEY_SLEEP),
-        0
 };
 static struct mtd_partition h2_nor_partitions[] = {
@@ -270,14 +269,18 @@ static struct resource h2_kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data h2_keymap_data = {
+        .keymap         = h2_keymap,
+        .keymap_size    = ARRAY_SIZE(h2_keymap),
+};
 static struct omap_kp_platform_data h2_kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = h2_keymap,
+        .keymap_data    = &h2_keymap_data,
-        .keymapsize     = ARRAY_SIZE(h2_keymap),
+        .rep            = true,
-        .rep            = 1,
        .delay          = 9,
-        .dbounce        = 1,
+        .dbounce        = true,
 };
 static struct platform_device h2_kp_device = {
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index d2cff5022fe5..dbc8b8d882ba 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -56,43 +56,42 @@
 #define H3_TS_GPIO      48
-static int h3_keymap[] = {
+static const unsigned int h3_keymap[] = {
        KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
+        KEY(1, 0, KEY_RIGHT),
-        KEY(0, 2, KEY_3),
+        KEY(2, 0, KEY_3),
-        KEY(0, 3, KEY_F10),
+        KEY(3, 0, KEY_F10),
-        KEY(0, 4, KEY_F5),
+        KEY(4, 0, KEY_F5),
-        KEY(0, 5, KEY_9),
+        KEY(5, 0, KEY_9),
-        KEY(1, 0, KEY_DOWN),
+        KEY(0, 1, KEY_DOWN),
        KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_2),
+        KEY(2, 1, KEY_2),
-        KEY(1, 3, KEY_F9),
+        KEY(3, 1, KEY_F9),
-        KEY(1, 4, KEY_F7),
+        KEY(4, 1, KEY_F7),
-        KEY(1, 5, KEY_0),
+        KEY(5, 1, KEY_0),
-        KEY(2, 0, KEY_ENTER),
+        KEY(0, 2, KEY_ENTER),
-        KEY(2, 1, KEY_6),
+        KEY(1, 2, KEY_6),
        KEY(2, 2, KEY_1),
-        KEY(2, 3, KEY_F2),
+        KEY(3, 2, KEY_F2),
-        KEY(2, 4, KEY_F6),
+        KEY(4, 2, KEY_F6),
-        KEY(2, 5, KEY_HOME),
+        KEY(5, 2, KEY_HOME),
-        KEY(3, 0, KEY_8),
+        KEY(0, 3, KEY_8),
-        KEY(3, 1, KEY_5),
+        KEY(1, 3, KEY_5),
-        KEY(3, 2, KEY_F12),
+        KEY(2, 3, KEY_F12),
        KEY(3, 3, KEY_F3),
-        KEY(3, 4, KEY_F8),
+        KEY(4, 3, KEY_F8),
-        KEY(3, 5, KEY_END),
+        KEY(5, 3, KEY_END),
-        KEY(4, 0, KEY_7),
+        KEY(0, 4, KEY_7),
-        KEY(4, 1, KEY_4),
+        KEY(1, 4, KEY_4),
-        KEY(4, 2, KEY_F11),
+        KEY(2, 4, KEY_F11),
-        KEY(4, 3, KEY_F1),
+        KEY(3, 4, KEY_F1),
        KEY(4, 4, KEY_F4),
-        KEY(4, 5, KEY_ESC),
+        KEY(5, 4, KEY_ESC),
-        KEY(5, 0, KEY_F13),
+        KEY(0, 5, KEY_F13),
-        KEY(5, 1, KEY_F14),
+        KEY(1, 5, KEY_F14),
-        KEY(5, 2, KEY_F15),
+        KEY(2, 5, KEY_F15),
-        KEY(5, 3, KEY_F16),
+        KEY(3, 5, KEY_F16),
-        KEY(5, 4, KEY_SLEEP),
+        KEY(4, 5, KEY_SLEEP),
-        0
 };
@@ -305,14 +304,18 @@ static struct resource h3_kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data h3_keymap_data = {
+        .keymap         = h3_keymap,
+        .keymap_size    = ARRAY_SIZE(h3_keymap),
+};
 static struct omap_kp_platform_data h3_kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = h3_keymap,
+        .keymap_data    = &h3_keymap_data,
-        .keymapsize     = ARRAY_SIZE(h3_keymap),
+        .rep            = true,
-        .rep            = 1,
        .delay          = 9,
-        .dbounce        = 1,
+        .dbounce        = true,
 };
 static struct platform_device h3_kp_device = {
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 742c6d107268..f2c5c585bc83 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -180,64 +180,68 @@
 /* Keyboard definition */
-static int htc_herald_keymap[] = {
+static const unsigned int htc_herald_keymap[] = {
        KEY(0, 0, KEY_RECORD), /* Mail button */
-        KEY(0, 1, KEY_CAMERA), /* Camera */
+        KEY(1, 0, KEY_CAMERA), /* Camera */
-        KEY(0, 2, KEY_PHONE), /* Send key */
+        KEY(2, 0, KEY_PHONE), /* Send key */
-        KEY(0, 3, KEY_VOLUMEUP), /* Volume up */
+        KEY(3, 0, KEY_VOLUMEUP), /* Volume up */
-        KEY(0, 4, KEY_F2),  /* Right bar (landscape) */
+        KEY(4, 0, KEY_F2),  /* Right bar (landscape) */
-        KEY(0, 5, KEY_MAIL), /* Win key (portrait) */
+        KEY(5, 0, KEY_MAIL), /* Win key (portrait) */
-        KEY(0, 6, KEY_DIRECTORY), /* Right bar (protrait) */
+        KEY(6, 0, KEY_DIRECTORY), /* Right bar (protrait) */
-        KEY(1, 0, KEY_LEFTCTRL), /* Windows key */
+        KEY(0, 1, KEY_LEFTCTRL), /* Windows key */
        KEY(1, 1, KEY_COMMA),
-        KEY(1, 2, KEY_M),
+        KEY(2, 1, KEY_M),
-        KEY(1, 3, KEY_K),
+        KEY(3, 1, KEY_K),
-        KEY(1, 4, KEY_SLASH), /* OK key */
+        KEY(4, 1, KEY_SLASH), /* OK key */
-        KEY(1, 5, KEY_I),
+        KEY(5, 1, KEY_I),
-        KEY(1, 6, KEY_U),
+        KEY(6, 1, KEY_U),
-        KEY(2, 0, KEY_LEFTALT),
+        KEY(0, 2, KEY_LEFTALT),
-        KEY(2, 1, KEY_TAB),
+        KEY(1, 2, KEY_TAB),
        KEY(2, 2, KEY_N),
-        KEY(2, 3, KEY_J),
+        KEY(3, 2, KEY_J),
-        KEY(2, 4, KEY_ENTER),
+        KEY(4, 2, KEY_ENTER),
-        KEY(2, 5, KEY_H),
+        KEY(5, 2, KEY_H),
-        KEY(2, 6, KEY_Y),
+        KEY(6, 2, KEY_Y),
-        KEY(3, 0, KEY_SPACE),
+        KEY(0, 3, KEY_SPACE),
-        KEY(3, 1, KEY_L),
+        KEY(1, 3, KEY_L),
-        KEY(3, 2, KEY_B),
+        KEY(2, 3, KEY_B),
        KEY(3, 3, KEY_V),
-        KEY(3, 4, KEY_BACKSPACE),
+        KEY(4, 3, KEY_BACKSPACE),
-        KEY(3, 5, KEY_G),
+        KEY(5, 3, KEY_G),
-        KEY(3, 6, KEY_T),
+        KEY(6, 3, KEY_T),
-        KEY(4, 0, KEY_CAPSLOCK), /* Shift */
+        KEY(0, 4, KEY_CAPSLOCK), /* Shift */
-        KEY(4, 1, KEY_C),
+        KEY(1, 4, KEY_C),
-        KEY(4, 2, KEY_F),
+        KEY(2, 4, KEY_F),
-        KEY(4, 3, KEY_R),
+        KEY(3, 4, KEY_R),
        KEY(4, 4, KEY_O),
-        KEY(4, 5, KEY_E),
+        KEY(5, 4, KEY_E),
-        KEY(4, 6, KEY_D),
+        KEY(6, 4, KEY_D),
-        KEY(5, 0, KEY_X),
+        KEY(0, 5, KEY_X),
-        KEY(5, 1, KEY_Z),
+        KEY(1, 5, KEY_Z),
-        KEY(5, 2, KEY_S),
+        KEY(2, 5, KEY_S),
-        KEY(5, 3, KEY_W),
+        KEY(3, 5, KEY_W),
-        KEY(5, 4, KEY_P),
+        KEY(4, 5, KEY_P),
        KEY(5, 5, KEY_Q),
-        KEY(5, 6, KEY_A),
+        KEY(6, 5, KEY_A),
-        KEY(6, 0, KEY_CONNECT), /* Voice button */
+        KEY(0, 6, KEY_CONNECT), /* Voice button */
-        KEY(6, 2, KEY_CANCEL), /* End key */
+        KEY(2, 6, KEY_CANCEL), /* End key */
-        KEY(6, 3, KEY_VOLUMEDOWN), /* Volume down */
+        KEY(3, 6, KEY_VOLUMEDOWN), /* Volume down */
-        KEY(6, 4, KEY_F1), /* Left bar (landscape) */
+        KEY(4, 6, KEY_F1), /* Left bar (landscape) */
-        KEY(6, 5, KEY_WWW), /* OK button (portrait) */
+        KEY(5, 6, KEY_WWW), /* OK button (portrait) */
        KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */
-        0
 };
-struct omap_kp_platform_data htcherald_kp_data = {
+static const struct matrix_keymap_data htc_herald_keymap_data = {
+        .keymap         = htc_herald_keymap,
+        .keymap_size    = ARRAY_SIZE(htc_herald_keymap),
+};
+static struct omap_kp_platform_data htcherald_kp_data = {
        .rows   = 7,
        .cols   = 7,
        .delay = 20,
-        .rep = 1,
+        .rep = true,
-        .keymap = htc_herald_keymap,
+        .keymap_data = &htc_herald_keymap_data,
 };
 static struct resource kp_resources[] = {
@@ -278,7 +282,7 @@ static struct gpio_keys_button herald_gpio_keys_table[] = {
 static struct gpio_keys_platform_data herald_gpio_keys_data = {
        .buttons        = herald_gpio_keys_table,
        .nbuttons       = ARRAY_SIZE(herald_gpio_keys_table),
-        .rep            = 1,
+        .rep            = true,
 };
 static struct platform_device herald_gpiokeys_device = {
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 8d59b078fc2c..a36e6742bf9b 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -44,17 +44,16 @@
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define INNOVATOR1610_ETHR_START        0x04000300
-static int innovator_keymap[] = {
+static const unsigned int innovator_keymap[] = {
        KEY(0, 0, KEY_F1),
-        KEY(0, 3, KEY_DOWN),
+        KEY(3, 0, KEY_DOWN),
        KEY(1, 1, KEY_F2),
-        KEY(1, 2, KEY_RIGHT),
+        KEY(2, 1, KEY_RIGHT),
-        KEY(2, 0, KEY_F3),
+        KEY(0, 2, KEY_F3),
-        KEY(2, 1, KEY_F4),
+        KEY(1, 2, KEY_F4),
        KEY(2, 2, KEY_UP),
-        KEY(3, 2, KEY_ENTER),
+        KEY(2, 3, KEY_ENTER),
        KEY(3, 3, KEY_LEFT),
-        0
 };
 static struct mtd_partition innovator_partitions[] = {
@@ -126,11 +125,15 @@ static struct resource innovator_kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data innovator_keymap_data = {
+        .keymap         = innovator_keymap,
+        .keymap_size    = ARRAY_SIZE(innovator_keymap),
+};
 static struct omap_kp_platform_data innovator_kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = innovator_keymap,
+        .keymap_data    = &innovator_keymap_data,
-        .keymapsize     = ARRAY_SIZE(innovator_keymap),
        .delay          = 4,
 };
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 605495bbc583..d21f09dc78f4 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -54,19 +54,18 @@ static void __init omap_nokia770_init_irq(void)
        omap_init_irq();
 }
-static int nokia770_keymap[] = {
+static const unsigned int nokia770_keymap[] = {
-        KEY(0, 1, GROUP_0 | KEY_UP),
+        KEY(1, 0, GROUP_0 | KEY_UP),
-        KEY(0, 2, GROUP_1 | KEY_F5),
+        KEY(2, 0, GROUP_1 | KEY_F5),
-        KEY(1, 0, GROUP_0 | KEY_LEFT),
+        KEY(0, 1, GROUP_0 | KEY_LEFT),
        KEY(1, 1, GROUP_0 | KEY_ENTER),
-        KEY(1, 2, GROUP_0 | KEY_RIGHT),
+        KEY(2, 1, GROUP_0 | KEY_RIGHT),
-        KEY(2, 0, GROUP_1 | KEY_ESC),
+        KEY(0, 2, GROUP_1 | KEY_ESC),
-        KEY(2, 1, GROUP_0 | KEY_DOWN),
+        KEY(1, 2, GROUP_0 | KEY_DOWN),
        KEY(2, 2, GROUP_1 | KEY_F4),
-        KEY(3, 0, GROUP_2 | KEY_F7),
+        KEY(0, 3, GROUP_2 | KEY_F7),
-        KEY(3, 1, GROUP_2 | KEY_F8),
+        KEY(1, 3, GROUP_2 | KEY_F8),
-        KEY(3, 2, GROUP_2 | KEY_F6),
+        KEY(2, 3, GROUP_2 | KEY_F6),
-        0
 };
 static struct resource nokia770_kp_resources[] = {
@@ -77,11 +76,15 @@ static struct resource nokia770_kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data nokia770_keymap_data = {
+        .keymap         = nokia770_keymap,
+        .keymap_size    = ARRAY_SIZE(nokia770_keymap),
+};
 static struct omap_kp_platform_data nokia770_kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = nokia770_keymap,
+        .keymap_data    = &nokia770_keymap_data,
-        .keymapsize     = ARRAY_SIZE(nokia770_keymap),
        .delay          = 4,
 };
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index d44e7172efc2..7c5e2112c776 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -338,25 +338,28 @@ static struct i2c_board_info __initdata mistral_i2c_board_info[] = {
         */
 };
-static const int osk_keymap[] = {
+static const unsigned int osk_keymap[] = {
        /* KEY(col, row, code) */
        KEY(0, 0, KEY_F1),              /* SW4 */
-        KEY(0, 3, KEY_UP),              /* (sw2/up) */
+        KEY(3, 0, KEY_UP),              /* (sw2/up) */
        KEY(1, 1, KEY_LEFTCTRL),        /* SW5 */
-        KEY(1, 2, KEY_LEFT),            /* (sw2/left) */
+        KEY(2, 1, KEY_LEFT),            /* (sw2/left) */
-        KEY(2, 0, KEY_SPACE),           /* SW3 */
+        KEY(0, 2, KEY_SPACE),           /* SW3 */
-        KEY(2, 1, KEY_ESC),             /* SW6 */
+        KEY(1, 2, KEY_ESC),             /* SW6 */
        KEY(2, 2, KEY_DOWN),            /* (sw2/down) */
-        KEY(3, 2, KEY_ENTER),           /* (sw2/select) */
+        KEY(2, 3, KEY_ENTER),           /* (sw2/select) */
        KEY(3, 3, KEY_RIGHT),           /* (sw2/right) */
-        0
+};
+static const struct matrix_keymap_data osk_keymap_data = {
+        .keymap         = osk_keymap,
+        .keymap_size    = ARRAY_SIZE(osk_keymap),
 };
 static struct omap_kp_platform_data osk_kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = (int *) osk_keymap,
+        .keymap_data    = &osk_keymap_data,
-        .keymapsize     = ARRAY_SIZE(osk_keymap),
        .delay          = 9,
 };
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 994dc6f50729..fb51ce6123d8 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -65,25 +65,29 @@ static void __init omap_palmte_init_irq(void)
        omap_init_irq();
 }
-static const int palmte_keymap[] = {
+static const unsigned int palmte_keymap[] = {
        KEY(0, 0, KEY_F1),              /* Calendar */
-        KEY(0, 1, KEY_F2),              /* Contacts */
+        KEY(1, 0, KEY_F2),              /* Contacts */
-        KEY(0, 2, KEY_F3),              /* Tasks List */
+        KEY(2, 0, KEY_F3),              /* Tasks List */
-        KEY(0, 3, KEY_F4),              /* Note Pad */
+        KEY(3, 0, KEY_F4),              /* Note Pad */
-        KEY(0, 4, KEY_POWER),
+        KEY(4, 0, KEY_POWER),
-        KEY(1, 0, KEY_LEFT),
+        KEY(0, 1, KEY_LEFT),
        KEY(1, 1, KEY_DOWN),
-        KEY(1, 2, KEY_UP),
+        KEY(2, 1, KEY_UP),
-        KEY(1, 3, KEY_RIGHT),
+        KEY(3, 1, KEY_RIGHT),
-        KEY(1, 4, KEY_ENTER),
+        KEY(4, 1, KEY_ENTER),
-        0,
+};
+static const struct matrix_keymap_data palmte_keymap_data = {
+        .keymap         = palmte_keymap,
+        .keymap_size    = ARRAY_SIZE(palmte_keymap),
 };
 static struct omap_kp_platform_data palmte_kp_data = {
        .rows   = 8,
        .cols   = 8,
-        .keymap = (int *) palmte_keymap,
+        .keymap_data = &palmte_keymap_data,
-        .rep    = 1,
+        .rep    = true,
        .delay  = 12,
 };
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index ed1400a67f75..f04f2d36e7d3 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -51,19 +51,18 @@
 #define PALMTT_MMC_WP_GPIO      8
 #define PALMTT_HDQ_GPIO         11
-static int palmtt_keymap[] = {
+static const unsigned int palmtt_keymap[] = {
        KEY(0, 0, KEY_ESC),
-        KEY(0, 1, KEY_SPACE),
+        KEY(1, 0, KEY_SPACE),
-        KEY(0, 2, KEY_LEFTCTRL),
+        KEY(2, 0, KEY_LEFTCTRL),
-        KEY(0, 3, KEY_TAB),
+        KEY(3, 0, KEY_TAB),
-        KEY(0, 4, KEY_ENTER),
+        KEY(4, 0, KEY_ENTER),
-        KEY(1, 0, KEY_LEFT),
+        KEY(0, 1, KEY_LEFT),
        KEY(1, 1, KEY_DOWN),
-        KEY(1, 2, KEY_UP),
+        KEY(2, 1, KEY_UP),
-        KEY(1, 3, KEY_RIGHT),
+        KEY(3, 1, KEY_RIGHT),
-        KEY(2, 0, KEY_SLEEP),
+        KEY(0, 2, KEY_SLEEP),
-        KEY(2, 4, KEY_Y),
+        KEY(4, 2, KEY_Y),
-        0
 };
 static struct mtd_partition palmtt_partitions[] = {
@@ -136,10 +135,15 @@ static struct resource palmtt_kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data palmtt_keymap_data = {
+        .keymap         = palmtt_keymap,
+        .keymap_size    = ARRAY_SIZE(palmtt_keymap),
+};
 static struct omap_kp_platform_data palmtt_kp_data = {
        .rows   = 6,
        .cols   = 3,
-        .keymap = palmtt_keymap,
+        .keymap_data = &palmtt_keymap_data,
 };
 static struct platform_device palmtt_kp_device = {
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 2afac598baee..d7bbbe721a75 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -64,26 +64,30 @@ omap_palmz71_init_irq(void)
        omap_init_irq();
 }
-static int palmz71_keymap[] = {
+static const unsigned int palmz71_keymap[] = {
        KEY(0, 0, KEY_F1),
-        KEY(0, 1, KEY_F2),
+        KEY(1, 0, KEY_F2),
-        KEY(0, 2, KEY_F3),
+        KEY(2, 0, KEY_F3),
-        KEY(0, 3, KEY_F4),
+        KEY(3, 0, KEY_F4),
-        KEY(0, 4, KEY_POWER),
+        KEY(4, 0, KEY_POWER),
-        KEY(1, 0, KEY_LEFT),
+        KEY(0, 1, KEY_LEFT),
        KEY(1, 1, KEY_DOWN),
-        KEY(1, 2, KEY_UP),
+        KEY(2, 1, KEY_UP),
-        KEY(1, 3, KEY_RIGHT),
+        KEY(3, 1, KEY_RIGHT),
-        KEY(1, 4, KEY_ENTER),
+        KEY(4, 1, KEY_ENTER),
-        KEY(2, 0, KEY_CAMERA),
+        KEY(0, 2, KEY_CAMERA),
-        0,
+};
+static const struct matrix_keymap_data palmz71_keymap_data = {
+        .keymap         = palmz71_keymap,
+        .keymap_size    = ARRAY_SIZE(palmz71_keymap),
 };
 static struct omap_kp_platform_data palmz71_kp_data = {
        .rows   = 8,
        .cols   = 8,
-        .keymap = palmz71_keymap,
+        .keymap_data    = &palmz71_keymap_data,
-        .rep    = 1,
+        .rep    = true,
        .delay  = 80,
 };
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 69fda218fb45..3c8ee8489458 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -36,36 +36,35 @@
 #include <plat/common.h>
 #include <plat/board.h>
-static int p2_keymap[] = {
+static const unsigned int p2_keymap[] = {
-        KEY(0,0,KEY_UP),
+        KEY(0, 0, KEY_UP),
-        KEY(0,1,KEY_RIGHT),
+        KEY(1, 0, KEY_RIGHT),
-        KEY(0,2,KEY_LEFT),
+        KEY(2, 0, KEY_LEFT),
-        KEY(0,3,KEY_DOWN),
+        KEY(3, 0, KEY_DOWN),
-        KEY(0,4,KEY_ENTER),
+        KEY(4, 0, KEY_ENTER),
-        KEY(1,0,KEY_F10),
+        KEY(0, 1, KEY_F10),
-        KEY(1,1,KEY_SEND),
+        KEY(1, 1, KEY_SEND),
-        KEY(1,2,KEY_END),
+        KEY(2, 1, KEY_END),
-        KEY(1,3,KEY_VOLUMEDOWN),
+        KEY(3, 1, KEY_VOLUMEDOWN),
-        KEY(1,4,KEY_VOLUMEUP),
+        KEY(4, 1, KEY_VOLUMEUP),
-        KEY(1,5,KEY_RECORD),
+        KEY(5, 1, KEY_RECORD),
-        KEY(2,0,KEY_F9),
+        KEY(0, 2, KEY_F9),
-        KEY(2,1,KEY_3),
+        KEY(1, 2, KEY_3),
-        KEY(2,2,KEY_6),
+        KEY(2, 2, KEY_6),
-        KEY(2,3,KEY_9),
+        KEY(3, 2, KEY_9),
-        KEY(2,4,KEY_KPDOT),
+        KEY(4, 2, KEY_KPDOT),
-        KEY(3,0,KEY_BACK),
+        KEY(0, 3, KEY_BACK),
-        KEY(3,1,KEY_2),
+        KEY(1, 3, KEY_2),
-        KEY(3,2,KEY_5),
+        KEY(2, 3, KEY_5),
-        KEY(3,3,KEY_8),
+        KEY(3, 3, KEY_8),
-        KEY(3,4,KEY_0),
+        KEY(4, 3, KEY_0),
-        KEY(3,5,KEY_KPSLASH),
+        KEY(5, 3, KEY_KPSLASH),
-        KEY(4,0,KEY_HOME),
+        KEY(0, 4, KEY_HOME),
-        KEY(4,1,KEY_1),
+        KEY(1, 4, KEY_1),
-        KEY(4,2,KEY_4),
+        KEY(2, 4, KEY_4),
-        KEY(4,3,KEY_7),
+        KEY(3, 4, KEY_7),
-        KEY(4,4,KEY_KPASTERISK),
+        KEY(4, 4, KEY_KPASTERISK),
-        KEY(4,5,KEY_POWER),
+        KEY(5, 4, KEY_POWER),
-        0
 };
 static struct smc91x_platdata smc91x_info = {
@@ -211,13 +210,17 @@ static struct resource kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data p2_keymap_data = {
+        .keymap         = p2_keymap,
+        .keymap_size    = ARRAY_SIZE(p2_keymap),
+};
 static struct omap_kp_platform_data kp_data = {
        .rows           = 8,
        .cols           = 8,
-        .keymap         = p2_keymap,
+        .keymap_data    = &p2_keymap_data,
-        .keymapsize     = ARRAY_SIZE(p2_keymap),
        .delay          = 4,
-        .dbounce        = 1,
+        .dbounce        = true,
 };
 static struct platform_device kp_device = {
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 463862c67819..d41fe2d0616a 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -164,36 +164,35 @@ EXPORT_SYMBOL(sx1_setusbpower);
 /*----------- Keypad -------------------------*/
-static int sx1_keymap[] = {
+static const unsigned int sx1_keymap[] = {
-        KEY(5, 3, GROUP_0 | 117), /* camera Qt::Key_F17 */
+        KEY(3, 5, GROUP_0 | 117), /* camera Qt::Key_F17 */
-        KEY(0, 4, GROUP_0 | 114), /* voice memo Qt::Key_F14 */
+        KEY(4, 0, GROUP_0 | 114), /* voice memo Qt::Key_F14 */
-        KEY(1, 4, GROUP_2 | 114), /* voice memo */
+        KEY(4, 1, GROUP_2 | 114), /* voice memo */
-        KEY(2, 4, GROUP_3 | 114), /* voice memo */
+        KEY(4, 2, GROUP_3 | 114), /* voice memo */
        KEY(0, 0, GROUP_1 | KEY_F12),   /* red button Qt::Key_Hangup */
-        KEY(4, 3, GROUP_1 | KEY_LEFT),
+        KEY(3, 4, GROUP_1 | KEY_LEFT),
-        KEY(2, 3, GROUP_1 | KEY_DOWN),
+        KEY(3, 2, GROUP_1 | KEY_DOWN),
-        KEY(1, 3, GROUP_1 | KEY_RIGHT),
+        KEY(3, 1, GROUP_1 | KEY_RIGHT),
-        KEY(0, 3, GROUP_1 | KEY_UP),
+        KEY(3, 0, GROUP_1 | KEY_UP),
        KEY(3, 3, GROUP_1 | KEY_POWER), /* joystick press or Qt::Key_Select */
-        KEY(5, 0, GROUP_1 | KEY_1),
+        KEY(0, 5, GROUP_1 | KEY_1),
-        KEY(4, 0, GROUP_1 | KEY_2),
+        KEY(0, 4, GROUP_1 | KEY_2),
-        KEY(3, 0, GROUP_1 | KEY_3),
+        KEY(0, 3, GROUP_1 | KEY_3),
-        KEY(3, 4, GROUP_1 | KEY_4),
+        KEY(4, 3, GROUP_1 | KEY_4),
        KEY(4, 4, GROUP_1 | KEY_5),
-        KEY(5, 4, GROUP_1 | KEY_KPASTERISK),/* "*" */
+        KEY(4, 5, GROUP_1 | KEY_KPASTERISK),/* "*" */
-        KEY(4, 1, GROUP_1 | KEY_6),
+        KEY(1, 4, GROUP_1 | KEY_6),
-        KEY(5, 1, GROUP_1 | KEY_7),
+        KEY(1, 5, GROUP_1 | KEY_7),
-        KEY(3, 1, GROUP_1 | KEY_8),
+        KEY(1, 3, GROUP_1 | KEY_8),
-        KEY(3, 2, GROUP_1 | KEY_9),
+        KEY(2, 3, GROUP_1 | KEY_9),
-        KEY(5, 2, GROUP_1 | KEY_0),
+        KEY(2, 5, GROUP_1 | KEY_0),
-        KEY(4, 2, GROUP_1 | 113),       /* # F13 Toggle input method Qt::Key_F13 */
+        KEY(2, 4, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */
-        KEY(0, 1, GROUP_1 | KEY_F11),   /* green button Qt::Key_Call */
+        KEY(1, 0, GROUP_1 | KEY_F11),   /* green button Qt::Key_Call */
-        KEY(1, 2, GROUP_1 | KEY_YEN),   /* left soft Qt::Key_Context1 */
+        KEY(2, 1, GROUP_1 | KEY_YEN),   /* left soft Qt::Key_Context1 */
        KEY(2, 2, GROUP_1 | KEY_F8),    /* right soft Qt::Key_Back */
-        KEY(2, 1, GROUP_1 | KEY_LEFTSHIFT), /* shift */
+        KEY(1, 2, GROUP_1 | KEY_LEFTSHIFT), /* shift */
        KEY(1, 1, GROUP_1 | KEY_BACKSPACE), /* C (clear) */
-        KEY(0, 2, GROUP_1 | KEY_F7),    /* menu Qt::Key_Menu */
+        KEY(2, 0, GROUP_1 | KEY_F7),    /* menu Qt::Key_Menu */
-        0
 };
 static struct resource sx1_kp_resources[] = {
@@ -204,11 +203,15 @@ static struct resource sx1_kp_resources[] = {
        },
 };
+static const struct matrix_keymap_data sx1_keymap_data = {
+        .keymap         = sx1_keymap,
+        .keymap_size    = ARRAY_SIZE(sx1_keymap),
+};
 static struct omap_kp_platform_data sx1_kp_data = {
        .rows           = 6,
        .cols           = 6,
-        .keymap = sx1_keymap,
+        .keymap_data    = &sx1_keymap_data,
-        .keymapsize = ARRAY_SIZE(sx1_keymap),
        .delay  = 80,
 };
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
new file mode 100644
index 000000000000..d8559344c6e2
--- /dev/null
+++ b/arch/arm/mach-omap1/dma.c
@@ -0,0 +1,390 @@
+/*
+ * OMAP1/OMAP7xx - specific DMA driver
+ *
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into platform driver
+ *                   - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <plat/dma.h>
+#include <plat/tc.h>
+#include <plat/irqs.h>
+#define OMAP1_DMA_BASE                  (0xfffed800)
+#define OMAP1_LOGICAL_DMA_CH_COUNT      17
+#define OMAP1_DMA_STRIDE                0x40
+static u32 errata;
+static u32 enable_1510_mode;
+static u8 dma_stride;
+static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+static u16 reg_map[] = {
+        [GCR]           = 0x400,
+        [GSCR]          = 0x404,
+        [GRST1]         = 0x408,
+        [HW_ID]         = 0x442,
+        [PCH2_ID]       = 0x444,
+        [PCH0_ID]       = 0x446,
+        [PCH1_ID]       = 0x448,
+        [PCHG_ID]       = 0x44a,
+        [PCHD_ID]       = 0x44c,
+        [CAPS_0]        = 0x44e,
+        [CAPS_1]        = 0x452,
+        [CAPS_2]        = 0x456,
+        [CAPS_3]        = 0x458,
+        [CAPS_4]        = 0x45a,
+        [PCH2_SR]       = 0x460,
+        [PCH0_SR]       = 0x480,
+        [PCH1_SR]       = 0x482,
+        [PCHD_SR]       = 0x4c0,
+        /* Common Registers */
+        [CSDP]          = 0x00,
+        [CCR]           = 0x02,
+        [CICR]          = 0x04,
+        [CSR]           = 0x06,
+        [CEN]           = 0x10,
+        [CFN]           = 0x12,
+        [CSFI]          = 0x14,
+        [CSEI]          = 0x16,
+        [CPC]           = 0x18, /* 15xx only */
+        [CSAC]          = 0x18,
+        [CDAC]          = 0x1a,
+        [CDEI]          = 0x1c,
+        [CDFI]          = 0x1e,
+        [CLNK_CTRL]     = 0x28,
+        /* Channel specific register offsets */
+        [CSSA]          = 0x08,
+        [CDSA]          = 0x0c,
+        [COLOR]         = 0x20,
+        [CCR2]          = 0x24,
+        [LCH_CTRL]      = 0x2a,
+};
+static struct resource res[] __initdata = {
+        [0] = {
+                .start  = OMAP1_DMA_BASE,
+                .end    = OMAP1_DMA_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "0",
+                .start  = INT_DMA_CH0_6,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .name   = "1",
+                .start  = INT_DMA_CH1_7,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .name   = "2",
+                .start  = INT_DMA_CH2_8,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [4] = {
+                .name   = "3",
+                .start  = INT_DMA_CH3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [5] = {
+                .name   = "4",
+                .start  = INT_DMA_CH4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [6] = {
+                .name   = "5",
+                .start  = INT_DMA_CH5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* Handled in lcd_dma.c */
+        [7] = {
+                .name   = "6",
+                .start  = INT_1610_DMA_CH6,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* irq's for omap16xx and omap7xx */
+        [8] = {
+                .name   = "7",
+                .start  = INT_1610_DMA_CH7,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [9] = {
+                .name   = "8",
+                .start  = INT_1610_DMA_CH8,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [10] = {
+                .name  = "9",
+                .start = INT_1610_DMA_CH9,
+                .flags = IORESOURCE_IRQ,
+        },
+        [11] = {
+                .name  = "10",
+                .start = INT_1610_DMA_CH10,
+                .flags = IORESOURCE_IRQ,
+        },
+        [12] = {
+                .name  = "11",
+                .start = INT_1610_DMA_CH11,
+                .flags = IORESOURCE_IRQ,
+        },
+        [13] = {
+                .name  = "12",
+                .start = INT_1610_DMA_CH12,
+                .flags = IORESOURCE_IRQ,
+        },
+        [14] = {
+                .name  = "13",
+                .start = INT_1610_DMA_CH13,
+                .flags = IORESOURCE_IRQ,
+        },
+        [15] = {
+                .name  = "14",
+                .start = INT_1610_DMA_CH14,
+                .flags = IORESOURCE_IRQ,
+        },
+        [16] = {
+                .name  = "15",
+                .start = INT_1610_DMA_CH15,
+                .flags = IORESOURCE_IRQ,
+        },
+        [17] = {
+                .name  = "16",
+                .start = INT_DMA_LCD,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static void __iomem *dma_base;
+static inline void dma_write(u32 val, int reg, int lch)
+{
+        u8  stride;
+        u32 offset;
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        __raw_writew(val, dma_base + offset);
+        if ((reg > CLNK_CTRL && reg < CCEN) ||
+                        (reg > PCHD_ID && reg < CAPS_2)) {
+                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
+                __raw_writew(val >> 16, dma_base + offset2);
+        }
+}
+static inline u32 dma_read(int reg, int lch)
+{
+        u8 stride;
+        u32 offset, val;
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        val = __raw_readw(dma_base + offset);
+        if ((reg > CLNK_CTRL && reg < CCEN) ||
+                        (reg > PCHD_ID && reg < CAPS_2)) {
+                u16 upper;
+                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
+                upper = __raw_readw(dma_base + offset2);
+                val |= (upper << 16);
+        }
+        return val;
+}
+static void omap1_clear_lch_regs(int lch)
+{
+        int i = dma_common_ch_start;
+        for (; i <= dma_common_ch_end; i += 1)
+                dma_write(0, i, lch);
+}
+static void omap1_clear_dma(int lch)
+{
+        u32 l;
+        l = dma_read(CCR, lch);
+        l &= ~OMAP_DMA_CCR_EN;
+        dma_write(l, CCR, lch);
+        /* Clear pending interrupts */
+        l = dma_read(CSR, lch);
+}
+static void omap1_show_dma_caps(void)
+{
+        if (enable_1510_mode) {
+                printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
+        } else {
+                u16 w;
+                printk(KERN_INFO "OMAP DMA hardware version %d\n",
+                                                        dma_read(HW_ID, 0));
+                printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
+                        dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
+                        dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
+                        dma_read(CAPS_4, 0));
+                /* Disable OMAP 3.0/3.1 compatibility mode. */
+                w = dma_read(GSCR, 0);
+                w |= 1 << 3;
+                dma_write(w, GSCR, 0);
+        }
+        return;
+}
+static u32 configure_dma_errata(void)
+{
+        /*
+         * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        if (!cpu_is_omap15xx())
+                SET_DMA_ERRATA(DMA_ERRATA_3_3);
+        return errata;
+}
+static int __init omap1_system_dma_init(void)
+{
+        struct omap_system_dma_plat_info        *p;
+        struct omap_dma_dev_attr                *d;
+        struct platform_device                  *pdev;
+        int ret;
+        pdev = platform_device_alloc("omap_dma_system", 0);
+        if (!pdev) {
+                pr_err("%s: Unable to device alloc for dma\n",
+                        __func__);
+                return -ENOMEM;
+        }
+        dma_base = ioremap(res[0].start, resource_size(&res[0]));
+        if (!dma_base) {
+                pr_err("%s: Unable to ioremap\n", __func__);
+                return -ENODEV;
+        }
+        ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+        if (ret) {
+                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
+                        __func__, pdev->name, pdev->id);
+                goto exit_device_del;
+        }
+        p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
+        if (!p) {
+                dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
+                        __func__, pdev->name);
+                ret = -ENOMEM;
+                goto exit_device_put;
+        }
+        d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
+        if (!d) {
+                dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
+                        __func__, pdev->name);
+                ret = -ENOMEM;
+                goto exit_release_p;
+        }
+        d->lch_count            = OMAP1_LOGICAL_DMA_CH_COUNT;
+        /* Valid attributes for omap1 plus processors */
+        if (cpu_is_omap15xx())
+                d->dev_caps = ENABLE_1510_MODE;
+        enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
+        d->dev_caps             |= SRC_PORT;
+        d->dev_caps             |= DST_PORT;
+        d->dev_caps             |= SRC_INDEX;
+        d->dev_caps             |= DST_INDEX;
+        d->dev_caps             |= IS_BURST_ONLY4;
+        d->dev_caps             |= CLEAR_CSR_ON_READ;
+        d->dev_caps             |= IS_WORD_16;
+        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
+                                        (d->lch_count), GFP_KERNEL);
+        if (!d->chan) {
+                dev_err(&pdev->dev, "%s: Memory allocation failed"
+                                        "for d->chan!!!\n", __func__);
+                goto exit_release_d;
+        }
+        if (cpu_is_omap15xx())
+                d->chan_count = 9;
+        else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
+                if (!(d->dev_caps & ENABLE_1510_MODE))
+                        d->chan_count = 16;
+                else
+                        d->chan_count = 9;
+        }
+        p->dma_attr = d;
+        p->show_dma_caps        = omap1_show_dma_caps;
+        p->clear_lch_regs       = omap1_clear_lch_regs;
+        p->clear_dma            = omap1_clear_dma;
+        p->dma_write            = dma_write;
+        p->dma_read             = dma_read;
+        p->disable_irq_lch      = NULL;
+        p->errata = configure_dma_errata();
+        ret = platform_device_add_data(pdev, p, sizeof(*p));
+        if (ret) {
+                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
+                        __func__, pdev->name, pdev->id);
+                goto exit_release_chan;
+        }
+        ret = platform_device_add(pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
+                        __func__, pdev->name, pdev->id);
+                goto exit_release_chan;
+        }
+        dma_stride              = OMAP1_DMA_STRIDE;
+        dma_common_ch_start     = CPC;
+        dma_common_ch_end       = COLOR;
+        return ret;
+exit_release_chan:
+        kfree(d->chan);
+exit_release_d:
+        kfree(d);
+exit_release_p:
+        kfree(p);
+exit_device_put:
+        platform_device_put(pdev);
+exit_device_del:
+        platform_device_del(pdev);
+        return ret;
+}
+arch_initcall(omap1_system_dma_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 92b004ba5a10..3e8c9e859f98 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -35,6 +35,8 @@ config ARCH_OMAP3
        select CPU_V7
        select USB_ARCH_HAS_EHCI
        select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
+        select ARCH_HAS_OPP
+        select PM_OPP if PM
 config ARCH_OMAP4
        bool "TI OMAP4"
@@ -44,6 +46,8 @@ config ARCH_OMAP4
        select ARM_GIC
        select PL310_ERRATA_588369
        select ARM_ERRATA_720789
+        select ARCH_HAS_OPP
+        select PM_OPP if PM
 comment "OMAP Core Type"
        depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b86b06292388..1b699d3c6cb8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
-         common.o gpio.o
+         common.o gpio.o dma.o
 omap-2-3-common                         = irq.o sdrc.o prm2xxx_3xxx.o
 hwmod-common                            = omap_hwmod.o \
@@ -49,6 +49,13 @@ obj-$(CONFIG_ARCH_OMAP4)		+= mux44xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
+# OPP table initialization
+ifeq ($(CONFIG_PM_OPP),y)
+obj-y                                   += opp.o
+obj-$(CONFIG_ARCH_OMAP3)                += opp3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += opp4xxx_data.o
+endif
 # Power Management
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a30a7fce8cbf..7392c67ce109 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -118,27 +118,27 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
        twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
        return 0;
 }
 static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
 {
        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
        return 0;
 }
 static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 static struct regulator_consumer_supply devkit8000_vmmc1_supply =
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 0a2d73cf036f..b386a403c379 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -51,38 +51,37 @@
 static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
 static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
-static int h4_keymap[] = {
+static const unsigned int h4_keymap[] = {
        KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
+        KEY(1, 0, KEY_RIGHT),
-        KEY(0, 2, KEY_A),
+        KEY(2, 0, KEY_A),
-        KEY(0, 3, KEY_B),
+        KEY(3, 0, KEY_B),
-        KEY(0, 4, KEY_C),
+        KEY(4, 0, KEY_C),
-        KEY(1, 0, KEY_DOWN),
+        KEY(0, 1, KEY_DOWN),
        KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_E),
+        KEY(2, 1, KEY_E),
-        KEY(1, 3, KEY_F),
+        KEY(3, 1, KEY_F),
-        KEY(1, 4, KEY_G),
+        KEY(4, 1, KEY_G),
-        KEY(2, 0, KEY_ENTER),
+        KEY(0, 2, KEY_ENTER),
-        KEY(2, 1, KEY_I),
+        KEY(1, 2, KEY_I),
        KEY(2, 2, KEY_J),
-        KEY(2, 3, KEY_K),
+        KEY(3, 2, KEY_K),
-        KEY(2, 4, KEY_3),
+        KEY(4, 2, KEY_3),
-        KEY(3, 0, KEY_M),
+        KEY(0, 3, KEY_M),
-        KEY(3, 1, KEY_N),
+        KEY(1, 3, KEY_N),
-        KEY(3, 2, KEY_O),
+        KEY(2, 3, KEY_O),
        KEY(3, 3, KEY_P),
-        KEY(3, 4, KEY_Q),
+        KEY(4, 3, KEY_Q),
-        KEY(4, 0, KEY_R),
+        KEY(0, 4, KEY_R),
-        KEY(4, 1, KEY_4),
+        KEY(1, 4, KEY_4),
-        KEY(4, 2, KEY_T),
+        KEY(2, 4, KEY_T),
-        KEY(4, 3, KEY_U),
+        KEY(3, 4, KEY_U),
        KEY(4, 4, KEY_ENTER),
-        KEY(5, 0, KEY_V),
+        KEY(0, 5, KEY_V),
-        KEY(5, 1, KEY_W),
+        KEY(1, 5, KEY_W),
-        KEY(5, 2, KEY_L),
+        KEY(2, 5, KEY_L),
-        KEY(5, 3, KEY_S),
+        KEY(3, 5, KEY_S),
-        KEY(5, 4, KEY_ENTER),
+        KEY(4, 5, KEY_ENTER),
-        0
 };
 static struct mtd_partition h4_partitions[] = {
@@ -136,12 +135,16 @@ static struct platform_device h4_flash_device = {
        .resource       = &h4_flash_resource,
 };
+static const struct matrix_keymap_data h4_keymap_data = {
+        .keymap         = h4_keymap,
+        .keymap_size    = ARRAY_SIZE(h4_keymap),
+};
 static struct omap_kp_platform_data h4_kp_data = {
        .rows           = 6,
        .cols           = 7,
-        .keymap         = h4_keymap,
+        .keymap_data    = &h4_keymap_data,
-        .keymapsize     = ARRAY_SIZE(h4_keymap),
+        .rep            = true,
-        .rep            = 1,
        .row_gpios      = row_gpios,
        .col_gpios      = col_gpios,
 };
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b82f2319a091..d4a9aa41e877 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -142,6 +142,7 @@ static struct omap2_hsmmc_info mmc[] = {
                .mmc            = 1,
                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
        },
        {}      /* Terminator */
 };
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index fd95ccf8be5c..e75e240cad67 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -359,17 +359,12 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
        REGULATOR_SUPPLY("DVDD", "2-0019"),
 };
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-extern struct platform_device rx51_display_device;
-#endif
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
+        REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
-        {
+};
-                .supply = "vdds_sdi",
-                .dev    = &rx51_display_device.dev,
+static struct regulator_consumer_supply rx51_vdac_supply[] = {
-        },
+        REGULATOR_SUPPLY("vdda_dac", "omapdss"),
-#endif
 };
 static struct regulator_init_data rx51_vaux1 = {
@@ -489,14 +484,17 @@ static struct regulator_init_data rx51_vsim = {
 static struct regulator_init_data rx51_vdac = {
        .constraints = {
+                .name                   = "VDAC",
                .min_uV                 = 1800000,
                .max_uV                 = 1800000,
+                .apply_uV               = true,
                .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_MODE
                                        | REGULATOR_CHANGE_STATUS,
        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = rx51_vdac_supply,
 };
 static struct regulator_init_data rx51_vio = {
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 9919581f3911..acd670054d9a 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -24,9 +24,6 @@
 #include "mux.h"
 #define RX51_LCD_RESET_GPIO     90
-/* REVISIT  to verify with rx51.c at sound/soc/omap */
-#define RX51_TVOUT_SEL_GPIO     40
 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
@@ -41,17 +38,6 @@ static void rx51_lcd_disable(struct omap_dss_device *dssdev)
        gpio_set_value(dssdev->reset_gpio, 0);
 }
-static int rx51_tvout_enable(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 1);
-        return 0;
-}
-static void rx51_tvout_disable(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 0);
-}
 static struct omap_dss_device rx51_lcd_device = {
        .name                   = "lcd",
        .driver_name            = "panel-acx565akm",
@@ -67,9 +53,6 @@ static struct omap_dss_device  rx51_tv_device = {
        .type                   = OMAP_DISPLAY_TYPE_VENC,
        .driver_name            = "venc",
        .phy.venc.type          = OMAP_DSS_VENC_TYPE_COMPOSITE,
-        .reset_gpio             = RX51_TVOUT_SEL_GPIO,
-        .platform_enable        = rx51_tvout_enable,
-        .platform_disable       = rx51_tvout_disable,
 };
 static struct omap_dss_device *rx51_dss_devices[] = {
@@ -112,9 +95,6 @@ static int __init rx51_video_init(void)
        gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
-        /* REVISIT  to verify with rx51.c at sound/soc/omap */
-        gpio_direction_output(RX51_TVOUT_SEL_GPIO, 1);
        platform_add_devices(rx51_video_devices,
                                ARRAY_SIZE(rx51_video_devices));
        return 0;
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294b6048..0269bb055b69 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -239,9 +239,19 @@ void omap3_save_scratchpad_contents(void)
        struct omap3_scratchpad_prcm_block prcm_block_contents;
        struct omap3_scratchpad_sdrc_block sdrc_block_contents;
-        /* Populate the Scratchpad contents */
+        /*
+         * Populate the Scratchpad contents
+         *
+         * The "get_*restore_pointer" functions are used to provide a
+         * physical restore address where the ROM code jumps while waking
+         * up from MPU OFF/OSWR state.
+         * The restore pointer is stored into the scratchpad.
+         */
        scratchpad_contents.boot_config_ptr = 0x0;
-        if (omap_rev() != OMAP3430_REV_ES3_0 &&
+        if (cpu_is_omap3630())
+                scratchpad_contents.public_restore_ptr =
+                        virt_to_phys(get_omap3630_restore_pointer());
+        else if (omap_rev() != OMAP3430_REV_ES3_0 &&
                                        omap_rev() != OMAP3430_REV_ES3_1)
                scratchpad_contents.public_restore_ptr =
                        virt_to_phys(get_restore_pointer());
@@ -474,4 +484,12 @@ void omap3_control_restore_context(void)
        omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
        return;
 }
+void omap3630_ctrl_disable_rta(void)
+{
+        if (!cpu_is_omap3630())
+                return;
+        omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
+}
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c450b3..ea20dc310522 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -204,6 +204,10 @@
 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL   0x40C
+#define OMAP36XX_RTA_DISABLE            0x0
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
@@ -270,6 +274,8 @@
 #define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
 #define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
 #define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
+#define OMAP343X_SCRATCHPAD_REGADDR(reg)        OMAP2_L4_IO_ADDRESS(\
+                                                OMAP343X_SCRATCHPAD + reg)
 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
@@ -309,7 +315,7 @@
 #define         FEAT_SGX_NONE           2
 #define OMAP3_IVA_SHIFT                 12
-#define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
+#define OMAP3_IVA_MASK                  (1 << OMAP3_IVA_SHIFT)
 #define         FEAT_IVA                0
 #define         FEAT_IVA_NONE           1
@@ -347,10 +353,11 @@ extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
 extern u32 *get_restore_pointer(void);
 extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
 extern u32 omap3_arm_context[128];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);
+extern void omap3630_ctrl_disable_rta(void);
 #else
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45d041c..0fb619c52588 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 /**
- * omap3_cpuidle_update_states - Update the cpuidle states.
+ * omap3_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state:  Enable states upto and including this for mpu domain
+ * @core_deepest_state: Enable states upto and including this for core domain
 *
- * Currently, this function toggles the validity of idle states based upon
+ * This goes through the list of states available and enables and disables the
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
+ * validity of C states based on deepest state that can be achieved for the
- * Else, states leading to OFF state set to be invalid.
+ * variable domain
 */
-void omap3_cpuidle_update_states(void)
+void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
 {
        int i;
        for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
                struct omap3_processor_cx *cx = &omap3_power_states[i];
-                if (enable_off_mode) {
+                if ((cx->mpu_state >= mpu_deepest_state) &&
+                    (cx->core_state >= core_deepest_state)) {
                        cx->valid = 1;
                } else {
-                        if ((cx->mpu_state == PWRDM_POWER_OFF) ||
+                        cx->valid = 0;
-                                (cx->core_state == PWRDM_POWER_OFF))
-                                cx->valid = 0;
                }
        }
 }
@@ -452,6 +453,18 @@ void omap_init_power_states(void)
        omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
        omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
                                CPUIDLE_FLAG_CHECK_BM;
+        /*
+         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+         * enable OFF mode in a stable form for previous revisions.
+         * we disable C7 state as a result.
+         */
+        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+                omap3_power_states[OMAP3_STATE_C7].valid = 0;
+                cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
+                WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
+                                __func__);
+        }
 }
 struct cpuidle_driver omap3_idle_driver = {
@@ -504,7 +517,10 @@ int __init omap3_idle_init(void)
                return -EINVAL;
        dev->state_count = count;
-        omap3_cpuidle_update_states();
+        if (enable_off_mode)
+                omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
+        else
+                omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
        if (cpuidle_register_device(dev)) {
                printk(KERN_ERR "%s: CPUidle register device failed\n",
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
new file mode 100644
index 000000000000..d2f15f5cfd36
--- /dev/null
+++ b/arch/arm/mach-omap2/dma.c
@@ -0,0 +1,297 @@
+/*
+ * OMAP2+ DMA driver
+ *
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into platform driver
+ *      - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/dma.h>
+#define OMAP2_DMA_STRIDE        0x60
+static u32 errata;
+static u8 dma_stride;
+static struct omap_dma_dev_attr *d;
+static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+static u16 reg_map[] = {
+        [REVISION]              = 0x00,
+        [GCR]                   = 0x78,
+        [IRQSTATUS_L0]          = 0x08,
+        [IRQSTATUS_L1]          = 0x0c,
+        [IRQSTATUS_L2]          = 0x10,
+        [IRQSTATUS_L3]          = 0x14,
+        [IRQENABLE_L0]          = 0x18,
+        [IRQENABLE_L1]          = 0x1c,
+        [IRQENABLE_L2]          = 0x20,
+        [IRQENABLE_L3]          = 0x24,
+        [SYSSTATUS]             = 0x28,
+        [OCP_SYSCONFIG]         = 0x2c,
+        [CAPS_0]                = 0x64,
+        [CAPS_2]                = 0x6c,
+        [CAPS_3]                = 0x70,
+        [CAPS_4]                = 0x74,
+        /* Common register offsets */
+        [CCR]                   = 0x80,
+        [CLNK_CTRL]             = 0x84,
+        [CICR]                  = 0x88,
+        [CSR]                   = 0x8c,
+        [CSDP]                  = 0x90,
+        [CEN]                   = 0x94,
+        [CFN]                   = 0x98,
+        [CSEI]                  = 0xa4,
+        [CSFI]                  = 0xa8,
+        [CDEI]                  = 0xac,
+        [CDFI]                  = 0xb0,
+        [CSAC]                  = 0xb4,
+        [CDAC]                  = 0xb8,
+        /* Channel specific register offsets */
+        [CSSA]                  = 0x9c,
+        [CDSA]                  = 0xa0,
+        [CCEN]                  = 0xbc,
+        [CCFN]                  = 0xc0,
+        [COLOR]                 = 0xc4,
+        /* OMAP4 specific registers */
+        [CDP]                   = 0xd0,
+        [CNDP]                  = 0xd4,
+        [CCDN]                  = 0xd8,
+};
+static struct omap_device_pm_latency omap2_dma_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+static void __iomem *dma_base;
+static inline void dma_write(u32 val, int reg, int lch)
+{
+        u8  stride;
+        u32 offset;
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        __raw_writel(val, dma_base + offset);
+}
+static inline u32 dma_read(int reg, int lch)
+{
+        u8 stride;
+        u32 offset, val;
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        val = __raw_readl(dma_base + offset);
+        return val;
+}
+static inline void omap2_disable_irq_lch(int lch)
+{
+        u32 val;
+        val = dma_read(IRQENABLE_L0, lch);
+        val &= ~(1 << lch);
+        dma_write(val, IRQENABLE_L0, lch);
+}
+static void omap2_clear_dma(int lch)
+{
+        int i = dma_common_ch_start;
+        for (; i <= dma_common_ch_end; i += 1)
+                dma_write(0, i, lch);
+}
+static void omap2_show_dma_caps(void)
+{
+        u8 revision = dma_read(REVISION, 0) & 0xff;
+        printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
+                                revision >> 4, revision & 0xf);
+        return;
+}
+static u32 configure_dma_errata(void)
+{
+        /*
+         * Errata applicable for OMAP2430ES1.0 and all omap2420
+         *
+         * I.
+         * Erratum ID: Not Available
+         * Inter Frame DMA buffering issue DMA will wrongly
+         * buffer elements if packing and bursting is enabled. This might
+         * result in data gets stalled in FIFO at the end of the block.
+         * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
+         * guarantee no data will stay in the DMA FIFO in case inter frame
+         * buffering occurs
+         *
+         * II.
+         * Erratum ID: Not Available
+         * DMA may hang when several channels are used in parallel
+         * In the following configuration, DMA channel hanging can occur:
+         * a. Channel i, hardware synchronized, is enabled
+         * b. Another channel (Channel x), software synchronized, is enabled.
+         * c. Channel i is disabled before end of transfer
+         * d. Channel i is reenabled.
+         * e. Steps 1 to 4 are repeated a certain number of times.
+         * f. A third channel (Channel y), software synchronized, is enabled.
+         * Channel x and Channel y may hang immediately after step 'f'.
+         * Workaround:
+         * For any channel used - make sure NextLCH_ID is set to the value j.
+         */
+        if (cpu_is_omap2420() || (cpu_is_omap2430() &&
+                                (omap_type() == OMAP2430_REV_ES1_0))) {
+                SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
+                SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
+        }
+        /*
+         * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
+         * after a transaction error.
+         * Workaround: SW should explicitely disable the channel.
+         */
+        if (cpu_class_is_omap2())
+                SET_DMA_ERRATA(DMA_ERRATA_i378);
+        /*
+         * Erratum ID: i541: sDMA FIFO draining does not finish
+         * If sDMA channel is disabled on the fly, sDMA enters standby even
+         * through FIFO Drain is still in progress
+         * Workaround: Put sDMA in NoStandby more before a logical channel is
+         * disabled, then put it back to SmartStandby right after the channel
+         * finishes FIFO draining.
+         */
+        if (cpu_is_omap34xx())
+                SET_DMA_ERRATA(DMA_ERRATA_i541);
+        /*
+         * Erratum ID: i88 : Special programming model needed to disable DMA
+         * before end of block.
+         * Workaround: software must ensure that the DMA is configured in No
+         * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
+         */
+        if (omap_type() == OMAP3430_REV_ES1_0)
+                SET_DMA_ERRATA(DMA_ERRATA_i88);
+        /*
+         * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        SET_DMA_ERRATA(DMA_ERRATA_3_3);
+        /*
+         * Erratum ID: Not Available
+         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+         * after secure sram context save and restore.
+         * Work around: Hence we need to manually clear those IRQs to avoid
+         * spurious interrupts. This affects only secure devices.
+         */
+        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                SET_DMA_ERRATA(DMA_ROMCODE_BUG);
+        return errata;
+}
+/* One time initializations */
+static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
+{
+        struct omap_device                      *od;
+        struct omap_system_dma_plat_info        *p;
+        struct resource                         *mem;
+        char                                    *name = "omap_dma_system";
+        dma_stride              = OMAP2_DMA_STRIDE;
+        dma_common_ch_start     = CSDP;
+        if (cpu_is_omap3630() || cpu_is_omap4430())
+                dma_common_ch_end = CCDN;
+        else
+                dma_common_ch_end = CCFN;
+        p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
+        if (!p) {
+                pr_err("%s: Unable to allocate pdata for %s:%s\n",
+                        __func__, name, oh->name);
+                return -ENOMEM;
+        }
+        p->dma_attr             = (struct omap_dma_dev_attr *)oh->dev_attr;
+        p->disable_irq_lch      = omap2_disable_irq_lch;
+        p->show_dma_caps        = omap2_show_dma_caps;
+        p->clear_dma            = omap2_clear_dma;
+        p->dma_write            = dma_write;
+        p->dma_read             = dma_read;
+        p->clear_lch_regs       = NULL;
+        p->errata               = configure_dma_errata();
+        od = omap_device_build(name, 0, oh, p, sizeof(*p),
+                        omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
+        kfree(p);
+        if (IS_ERR(od)) {
+                pr_err("%s: Cant build omap_device for %s:%s.\n",
+                        __func__, name, oh->name);
+                return IS_ERR(od);
+        }
+        mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
+                return -EINVAL;
+        }
+        dma_base = ioremap(mem->start, resource_size(mem));
+        if (!dma_base) {
+                dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
+                return -ENOMEM;
+        }
+        d = oh->dev_attr;
+        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
+                                        (d->lch_count), GFP_KERNEL);
+        if (!d->chan) {
+                dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
+                return -ENOMEM;
+        }
+        return 0;
+}
+static int __init omap2_system_dma_init(void)
+{
+        return omap_hwmod_for_each_by_class("dma",
+                        omap2_system_dma_init_dev, NULL);
+}
+arch_initcall(omap2_system_dma_init);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4605d5073a9b..5577ab2faad2 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -347,8 +347,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
        else if (cpu_is_omap44xx())
                omap44xx_hwmod_init();
-        /* The OPP tables have to be registered before a clk init */
+        omap_pm_if_early_init();
-        omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
        if (cpu_is_omap2420())
                omap2420_clk_init();
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d95342599793..42606f6b0cdf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -42,6 +42,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod;
 static struct omap_hwmod omap2420_gpio2_hwmod;
 static struct omap_hwmod omap2420_gpio3_hwmod;
 static struct omap_hwmod omap2420_gpio4_hwmod;
+static struct omap_hwmod omap2420_dma_system_hwmod;
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -779,6 +780,88 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
+/* system dma */
+static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap2420_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap2420_dma_sysc,
+};
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                                IS_CSSA_32 | IS_CDSA_32,
+        .lch_count = 32,
+};
+static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
+        .master         = &omap2420_dma_system_hwmod,
+        .slave          = &omap2420_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
+        &omap2420_dma_system__l3,
+};
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2420_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
+        &omap2420_l4_core__dma_system,
+};
+static struct omap_hwmod omap2420_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap2420_dma_hwmod_class,
+        .mpu_irqs       = omap2420_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dma_system_irqs),
+        .main_clk       = "core_l3_ck",
+        .slaves         = omap2420_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
+        .masters        = omap2420_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
        &omap2420_l3_main_hwmod,
        &omap2420_l4_core_hwmod,
@@ -797,6 +880,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
        &omap2420_gpio2_hwmod,
        &omap2420_gpio3_hwmod,
        &omap2420_gpio4_hwmod,
+        /* dma_system class*/
+        &omap2420_dma_system_hwmod,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index ab1d662cb072..3315d241feef 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -43,6 +43,7 @@ static struct omap_hwmod omap2430_gpio2_hwmod;
 static struct omap_hwmod omap2430_gpio3_hwmod;
 static struct omap_hwmod omap2430_gpio4_hwmod;
 static struct omap_hwmod omap2430_gpio5_hwmod;
+static struct omap_hwmod omap2430_dma_system_hwmod;
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -838,6 +839,88 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
+/* dma_system */
+static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap2430_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap2430_dma_sysc,
+};
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count = 32,
+};
+static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+        .master         = &omap2430_dma_system_hwmod,
+        .slave          = &omap2430_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
+        &omap2430_dma_system__l3,
+};
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2430_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
+        &omap2430_l4_core__dma_system,
+};
+static struct omap_hwmod omap2430_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap2430_dma_hwmod_class,
+        .mpu_irqs       = omap2430_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
+        .main_clk       = "core_l3_ck",
+        .slaves         = omap2430_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
+        .masters        = omap2430_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
        &omap2430_l3_main_hwmod,
        &omap2430_l4_core_hwmod,
@@ -857,6 +940,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
        &omap2430_gpio3_hwmod,
        &omap2430_gpio4_hwmod,
        &omap2430_gpio5_hwmod,
+        /* dma_system class*/
+        &omap2430_dma_system_hwmod,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 2687be10d7aa..d5acb63ba9e0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -52,6 +52,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod;
 static struct omap_hwmod omap3xxx_gpio5_hwmod;
 static struct omap_hwmod omap3xxx_gpio6_hwmod;
+static struct omap_hwmod omap3xxx_dma_system_hwmod;
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
        .master = &omap3xxx_l3_main_hwmod,
@@ -1090,6 +1092,98 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
+        .master         = &omap3xxx_dma_system_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count = 32,
+};
+static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap3xxx_dma_sysc,
+};
+/* dma_system */
+static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
+        &omap3xxx_dma_system__l3,
+};
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dma_system_hwmod,
+        .clk            = "core_l4_ick",
+        .addr           = omap3xxx_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
+        &omap3xxx_l4_core__dma_system,
+};
+static struct omap_hwmod omap3xxx_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap3xxx_dma_hwmod_class,
+        .mpu_irqs       = omap3xxx_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
+        .main_clk       = "core_l3_ick",
+        .prcm = {
+                .omap2 = {
+                        .module_offs            = CORE_MOD,
+                        .prcm_reg_id            = 1,
+                        .module_bit             = OMAP3430_ST_SDMA_SHIFT,
+                        .idlest_reg_id          = 1,
+                        .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
+        .masters        = omap3xxx_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .flags          = HWMOD_NO_IDLEST,
+};
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_l3_main_hwmod,
        &omap3xxx_l4_core_hwmod,
@@ -1113,6 +1207,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_gpio4_hwmod,
        &omap3xxx_gpio5_hwmod,
        &omap3xxx_gpio6_hwmod,
+        /* dma_system class*/
+        &omap3xxx_dma_system_hwmod,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index d258936410fb..f9778fba8322 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -23,6 +23,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
 #include <plat/gpio.h>
+#include <plat/dma.h>
 #include "omap_hwmod_common_data.h"
@@ -36,6 +37,7 @@
 #define OMAP44XX_DMA_REQ_START  1
 /* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod omap44xx_dma_system_hwmod;
 static struct omap_hwmod omap44xx_dmm_hwmod;
 static struct omap_hwmod omap44xx_emif_fw_hwmod;
 static struct omap_hwmod omap44xx_l3_instr_hwmod;
@@ -216,6 +218,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/* dma_system -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+        .master         = &omap44xx_dma_system_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 /* l4_cfg -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
        .master         = &omap44xx_l4_cfg_hwmod,
@@ -226,6 +236,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 /* l3_main_2 slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+        &omap44xx_dma_system__l3_main_2,
        &omap44xx_l3_main_1__l3_main_2,
        &omap44xx_l4_cfg__l3_main_2,
 };
@@ -1376,6 +1387,93 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count = 32,
+};
+static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &omap44xx_dma_sysc,
+};
+/* dma_system */
+static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
+        { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
+        { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
+        { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
+};
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
+        &omap44xx_dma_system__l3_main_2,
+};
+static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dma_system_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
+        &omap44xx_l4_cfg__dma_system,
+};
+static struct omap_hwmod omap44xx_dma_system_hwmod = {
+        .name           = "dma_system",
+        .class          = &omap44xx_dma_hwmod_class,
+        .mpu_irqs       = omap44xx_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
+        .main_clk       = "l3_div_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
+        .masters        = omap44xx_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
        /* dmm class */
        &omap44xx_dmm_hwmod,
@@ -1391,6 +1489,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
        &omap44xx_l4_cfg_hwmod,
        &omap44xx_l4_per_hwmod,
        &omap44xx_l4_wkup_hwmod,
+        /* dma class */
+        &omap44xx_dma_system_hwmod,
        /* i2c class */
        &omap44xx_i2c1_hwmod,
        &omap44xx_i2c2_hwmod,
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
new file mode 100644
index 000000000000..46ac27dd6c84
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -0,0 +1,72 @@
+/*
+ * OMAP SoC specific OPP Data helpers
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+#include <plat/omap_hwmod.h>
+/*
+ * *BIG FAT WARNING*:
+ * USE the following ONLY in opp data initialization common to an SoC.
+ * DO NOT USE these in board files/pm core etc.
+ */
+/**
+ * struct omap_opp_def - OMAP OPP Definition
+ * @hwmod_name: Name of the hwmod for this domain
+ * @freq:       Frequency in hertz corresponding to this OPP
+ * @u_volt:     Nominal voltage in microvolts corresponding to this OPP
+ * @default_available:  True/false - is this OPP available by default
+ *
+ * OMAP SOCs have a standard set of tuples consisting of frequency and voltage
+ * pairs that the device will support per voltage domain. This is called
+ * Operating Points or OPP. The actual definitions of OMAP Operating Points
+ * varies over silicon within the same family of devices. For a specific
+ * domain, you can have a set of {frequency, voltage} pairs and this is denoted
+ * by an array of omap_opp_def. As the kernel boots and more information is
+ * available, a set of these are activated based on the precise nature of
+ * device the kernel boots up on. It is interesting to remember that each IP
+ * which belongs to a voltage domain may define their own set of OPPs on top
+ * of this - but this is handled by the appropriate driver.
+ */
+struct omap_opp_def {
+        char *hwmod_name;
+        unsigned long freq;
+        unsigned long u_volt;
+        bool default_available;
+};
+/*
+ * Initialization wrapper used to define an OPP for OMAP variants.
+ */
+#define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv)      \
+{                                                               \
+        .hwmod_name     = _hwmod_name,                          \
+        .default_available      = _enabled,                     \
+        .freq           = _freq,                                \
+        .u_volt         = _uv,                                  \
+}
+/* Use this to initialize the default table */
+extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+                u32 opp_def_size);
+#endif          /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
new file mode 100644
index 000000000000..ab8b35b780b5
--- /dev/null
+++ b/arch/arm/mach-omap2/opp.c
@@ -0,0 +1,93 @@
+/*
+ * OMAP SoC specific OPP wrapper function
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <linux/opp.h>
+#include <plat/omap_device.h>
+#include "omap_opp_data.h"
+/* Temp variable to allow multiple calls */
+static u8 __initdata omap_table_init;
+/**
+ * omap_init_opp_table() - Initialize opp table as per the CPU type
+ * @opp_def:            opp default list for this silicon
+ * @opp_def_size:       number of opp entries for this silicon
+ *
+ * Register the initial OPP table with the OPP library based on the CPU
+ * type. This is meant to be used only by SoC specific registration.
+ */
+int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+                u32 opp_def_size)
+{
+        int i, r;
+        if (!opp_def || !opp_def_size) {
+                pr_err("%s: invalid params!\n", __func__);
+                return -EINVAL;
+        }
+        /*
+         * Initialize only if not already initialized even if the previous
+         * call failed, because, no reason we'd succeed again.
+         */
+        if (omap_table_init)
+                return -EEXIST;
+        omap_table_init = 1;
+        /* Lets now register with OPP library */
+        for (i = 0; i < opp_def_size; i++) {
+                struct omap_hwmod *oh;
+                struct device *dev;
+                if (!opp_def->hwmod_name) {
+                        pr_err("%s: NULL name of omap_hwmod, failing [%d].\n",
+                                __func__, i);
+                        return -EINVAL;
+                }
+                oh = omap_hwmod_lookup(opp_def->hwmod_name);
+                if (!oh || !oh->od) {
+                        pr_warn("%s: no hwmod or odev for %s, [%d] "
+                                "cannot add OPPs.\n", __func__,
+                                opp_def->hwmod_name, i);
+                        return -EINVAL;
+                }
+                dev = &oh->od->pdev.dev;
+                r = opp_add(dev, opp_def->freq, opp_def->u_volt);
+                if (r) {
+                        dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
+                                "result=%d\n",
+                               __func__, opp_def->freq,
+                               opp_def->hwmod_name, i, r);
+                } else {
+                        if (!opp_def->default_available)
+                                r = opp_disable(dev, opp_def->freq);
+                        if (r)
+                                dev_err(dev, "%s: disable %ld failed for %s "
+                                        "[%d] result=%d\n",
+                                        __func__, opp_def->freq,
+                                        opp_def->hwmod_name, i, r);
+                }
+                opp_def++;
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
new file mode 100644
index 000000000000..0486fce8a92c
--- /dev/null
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -0,0 +1,107 @@
+/*
+ * OMAP3 OPP table definitions.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <plat/cpu.h>
+#include "omap_opp_data.h"
+static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
+        /* MPU OPP1 */
+        OPP_INITIALIZER("mpu", true, 125000000, 975000),
+        /* MPU OPP2 */
+        OPP_INITIALIZER("mpu", true, 250000000, 1075000),
+        /* MPU OPP3 */
+        OPP_INITIALIZER("mpu", true, 500000000, 1200000),
+        /* MPU OPP4 */
+        OPP_INITIALIZER("mpu", true, 550000000, 1270000),
+        /* MPU OPP5 */
+        OPP_INITIALIZER("mpu", true, 600000000, 1350000),
+        /*
+         * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
+         * almost the same than the one at 83MHz thus providing very little
+         * gain for the power point of view. In term of energy it will even
+         * increase the consumption due to the very negative performance
+         * impact that frequency will do to the MPU and the whole system in
+         * general.
+         */
+        OPP_INITIALIZER("l3_main", false, 41500000, 975000),
+        /* L3 OPP2 */
+        OPP_INITIALIZER("l3_main", true, 83000000, 1050000),
+        /* L3 OPP3 */
+        OPP_INITIALIZER("l3_main", true, 166000000, 1150000),
+        /* DSP OPP1 */
+        OPP_INITIALIZER("iva", true, 90000000, 975000),
+        /* DSP OPP2 */
+        OPP_INITIALIZER("iva", true, 180000000, 1075000),
+        /* DSP OPP3 */
+        OPP_INITIALIZER("iva", true, 360000000, 1200000),
+        /* DSP OPP4 */
+        OPP_INITIALIZER("iva", true, 400000000, 1270000),
+        /* DSP OPP5 */
+        OPP_INITIALIZER("iva", true, 430000000, 1350000),
+};
+static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
+        /* MPU OPP1 - OPP50 */
+        OPP_INITIALIZER("mpu", true,  300000000, 1012500),
+        /* MPU OPP2 - OPP100 */
+        OPP_INITIALIZER("mpu", true,  600000000, 1200000),
+        /* MPU OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("mpu", false, 800000000, 1325000),
+        /* MPU OPP4 - OPP-SB */
+        OPP_INITIALIZER("mpu", false, 1000000000, 1375000),
+        /* L3 OPP1 - OPP50 */
+        OPP_INITIALIZER("l3_main", true, 100000000, 1000000),
+        /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+        OPP_INITIALIZER("l3_main", true, 200000000, 1200000),
+        /* DSP OPP1 - OPP50 */
+        OPP_INITIALIZER("iva", true,  260000000, 1012500),
+        /* DSP OPP2 - OPP100 */
+        OPP_INITIALIZER("iva", true,  520000000, 1200000),
+        /* DSP OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("iva", false, 660000000, 1325000),
+        /* DSP OPP4 - OPP-SB */
+        OPP_INITIALIZER("iva", false, 800000000, 1375000),
+};
+/**
+ * omap3_opp_init() - initialize omap3 opp table
+ */
+static int __init omap3_opp_init(void)
+{
+        int r = -ENODEV;
+        if (!cpu_is_omap34xx())
+                return r;
+        if (cpu_is_omap3630())
+                r = omap_init_opp_table(omap36xx_opp_def_list,
+                        ARRAY_SIZE(omap36xx_opp_def_list));
+        else
+                r = omap_init_opp_table(omap34xx_opp_def_list,
+                        ARRAY_SIZE(omap34xx_opp_def_list));
+        return r;
+}
+device_initcall(omap3_opp_init);
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
new file mode 100644
index 000000000000..a11fa566d8ee
--- /dev/null
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -0,0 +1,57 @@
+/*
+ * OMAP4 OPP table definitions.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ *      Thara Gopinath
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <plat/cpu.h>
+#include "omap_opp_data.h"
+static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+        /* MPU OPP1 - OPP50 */
+        OPP_INITIALIZER("mpu", true, 300000000, 1100000),
+        /* MPU OPP2 - OPP100 */
+        OPP_INITIALIZER("mpu", true, 600000000, 1200000),
+        /* MPU OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("mpu", false, 800000000, 1260000),
+        /* MPU OPP4 - OPP-SB */
+        OPP_INITIALIZER("mpu", false, 1008000000, 1350000),
+        /* L3 OPP1 - OPP50 */
+        OPP_INITIALIZER("l3_main_1", true, 100000000, 930000),
+        /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+        OPP_INITIALIZER("l3_main_1", true, 200000000, 1100000),
+        /* TODO: add IVA, DSP, aess, fdif, gpu */
+};
+/**
+ * omap4_opp_init() - initialize omap4 opp table
+ */
+static int __init omap4_opp_init(void)
+{
+        int r = -ENODEV;
+        if (!cpu_is_omap44xx())
+                return r;
+        r = omap_init_opp_table(omap44xx_opp_def_list,
+                        ARRAY_SIZE(omap44xx_opp_def_list));
+        return r;
+}
+device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 59ca03b0e691..6ec2ee12272a 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -143,5 +143,5 @@ static int __init omap2_common_pm_init(void)
        return 0;
 }
-device_initcall(omap2_common_pm_init);
+postcore_initcall(omap2_common_pm_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd1fdbe..8b4f45eba1b5 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -20,6 +20,20 @@ extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
+#if defined(CONFIG_PM_OPP)
+extern int omap3_opp_init(void);
+extern int omap4_opp_init(void);
+#else
+static inline int omap3_opp_init(void)
+{
+        return -EINVAL;
+}
+static inline int omap4_opp_init(void)
+{
+        return -EINVAL;
+}
+#endif
 struct cpuidle_params {
        u8  valid;
        u32 sleep_latency;
@@ -58,7 +72,7 @@ extern u32 sleep_while_idle;
 #endif
 #if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+extern void omap3_cpuidle_update_states(u32, u32);
 #endif
 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
@@ -80,9 +94,20 @@ extern void save_secure_ram_context(u32 *addr);
 extern void omap3_save_scratchpad_contents(void);
 extern unsigned int omap24xx_idle_loop_suspend_sz;
-extern unsigned int omap34xx_suspend_sz;
 extern unsigned int save_secure_ram_context_sz;
 extern unsigned int omap24xx_cpu_suspend_sz;
 extern unsigned int omap34xx_cpu_suspend_sz;
+#define PM_RTA_ERRATUM_i608             (1 << 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583     (1 << 1)
+#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
+extern u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id)           (pm34xx_errata & (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
+#else
+#define IS_PM34XX_ERRATUM(id)           0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
+#endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 #endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index aaeea49b9bdd..aea7ced9a2ff 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -301,14 +301,8 @@ out:
 static int omap2_pm_begin(suspend_state_t state)
 {
-        suspend_state = state;
-        return 0;
-}
-static int omap2_pm_prepare(void)
-{
-        /* We cannot sleep in idle until we have resumed */
        disable_hlt();
+        suspend_state = state;
        return 0;
 }
@@ -349,21 +343,15 @@ static int omap2_pm_enter(suspend_state_t state)
        return ret;
 }
-static void omap2_pm_finish(void)
-{
-        enable_hlt();
-}
 static void omap2_pm_end(void)
 {
        suspend_state = PM_SUSPEND_ON;
+        enable_hlt();
 }
 static struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap2_pm_begin,
-        .prepare        = omap2_pm_prepare,
        .enter          = omap2_pm_enter,
-        .finish         = omap2_pm_finish,
        .end            = omap2_pm_end,
        .valid          = suspend_valid_only_mem,
 };
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c50d024..c45b4fa1deeb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
+/* pm34xx errata defined in pm.h */
+u16 pm34xx_errata;
 struct power_state {
        struct powerdomain *pwrdm;
        u32 next_state;
@@ -143,7 +146,7 @@ static void omap3_core_save_context(void)
        /*
         * Force write last pad into memory, as this can fail in some
-         * cases according to erratas 1.157, 1.185
+         * cases according to errata 1.157, 1.185
         */
        omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
                OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
@@ -430,7 +433,7 @@ void omap_sram_idle(void)
        /*
        * On EMU/HS devices ROM code restores a SRDC value
        * from scratchpad which has automatic self refresh on timeout
-        * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
+        * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
        * Hence store/restore the SDRC_POWER register here.
        */
        if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@@ -529,12 +532,6 @@ out:
 }
 #ifdef CONFIG_SUSPEND
-static int omap3_pm_prepare(void)
-{
-        disable_hlt();
-        return 0;
-}
 static int omap3_pm_suspend(void)
 {
        struct power_state *pwrst;
@@ -597,14 +594,10 @@ static int omap3_pm_enter(suspend_state_t unused)
        return ret;
 }
-static void omap3_pm_finish(void)
-{
-        enable_hlt();
-}
 /* Hooks to enable / disable UART interrupts during suspend */
 static int omap3_pm_begin(suspend_state_t state)
 {
+        disable_hlt();
        suspend_state = state;
        omap_uart_enable_irqs(0);
        return 0;
@@ -614,15 +607,14 @@ static void omap3_pm_end(void)
 {
        suspend_state = PM_SUSPEND_ON;
        omap_uart_enable_irqs(1);
+        enable_hlt();
        return;
 }
 static struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap3_pm_begin,
        .end            = omap3_pm_end,
-        .prepare        = omap3_pm_prepare,
        .enter          = omap3_pm_enter,
-        .finish         = omap3_pm_finish,
        .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
@@ -925,12 +917,29 @@ void omap3_pm_off_mode_enable(int enable)
                state = PWRDM_POWER_RET;
 #ifdef CONFIG_CPU_IDLE
-        omap3_cpuidle_update_states();
+        /*
+         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+         * enable OFF mode in a stable form for previous revisions, restrict
+         * instead to RET
+         */
+        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+                omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+        else
+                omap3_cpuidle_update_states(state, state);
 #endif
        list_for_each_entry(pwrst, &pwrst_list, node) {
-                pwrst->next_state = state;
+                if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
-                omap_set_pwrdm_state(pwrst->pwrdm, state);
+                                pwrst->pwrdm == core_pwrdm &&
+                                state == PWRDM_POWER_OFF) {
+                        pwrst->next_state = PWRDM_POWER_RET;
+                        WARN_ONCE(1,
+                                "%s: Core OFF disabled due to errata i583\n",
+                                __func__);
+                } else {
+                        pwrst->next_state = state;
+                }
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
        }
 }
@@ -1002,6 +1011,17 @@ void omap_push_sram_idle(void)
                                save_secure_ram_context_sz);
 }
+static void __init pm_errata_configure(void)
+{
+        if (cpu_is_omap3630()) {
+                pm34xx_errata |= PM_RTA_ERRATUM_i608;
+                /* Enable the l2 cache toggling in sleep logic */
+                enable_omap3630_toggle_l2_on_restore();
+                if (omap_rev() < OMAP3630_REV_ES1_2)
+                        pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
+        }
+}
 static int __init omap3_pm_init(void)
 {
        struct power_state *pwrst, *tmp;
@@ -1011,6 +1031,8 @@ static int __init omap3_pm_init(void)
        if (!cpu_is_omap34xx())
                return -ENODEV;
+        pm_errata_configure();
        printk(KERN_ERR "Power Management for TI OMAP3.\n");
        /* XXX prcm_setup_regs needs to be before enabling hw
@@ -1058,6 +1080,14 @@ static int __init omap3_pm_init(void)
        pm_idle = omap3_pm_idle;
        omap3_idle_init();
+        /*
+         * RTA is disabled during initialization as per erratum i608
+         * it is safer to disable RTA by the bootloader, but we would like
+         * to be doubly sure here and prevent any mishaps.
+         */
+        if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
+                omap3630_ctrl_disable_rta();
        clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
        if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
                omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 54544b4fc76b..6aff9961e35d 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -31,12 +31,6 @@ struct power_state {
 static LIST_HEAD(pwrst_list);
 #ifdef CONFIG_SUSPEND
-static int omap4_pm_prepare(void)
-{
-        disable_hlt();
-        return 0;
-}
 static int omap4_pm_suspend(void)
 {
        do_wfi();
@@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state)
        return ret;
 }
-static void omap4_pm_finish(void)
-{
-        enable_hlt();
-        return;
-}
 static int omap4_pm_begin(suspend_state_t state)
 {
+        disable_hlt();
        return 0;
 }
 static void omap4_pm_end(void)
 {
+        enable_hlt();
        return;
 }
 static struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap4_pm_begin,
        .end            = omap4_pm_end,
-        .prepare        = omap4_pm_prepare,
        .enter          = omap4_pm_enter,
-        .finish         = omap4_pm_finish,
        .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 68f57bb67fc5..b3f83799e6cf 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg)
 */
 #define SDRC_MPURATE_LOOPS              96
 #endif
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2fb205a7f285..e3b5cd76c54c 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -1,6 +1,4 @@
 /*
- * linux/arch/arm/mach-omap2/sleep.S
- *
 * (C) Copyright 2007
 * Texas Instruments
 * Karthik Dasu <karthik-dp@ti.com>
@@ -26,6 +24,7 @@
 */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <plat/sram.h>
 #include <mach/io.h>
 #include "cm.h"
@@ -33,21 +32,27 @@
 #include "sdrc.h"
 #include "control.h"
-#define SDRC_SCRATCHPAD_SEM_V   0xfa00291c
+/*
+ * Registers access definitions
-#define PM_PREPWSTST_CORE_V     OMAP34XX_PRM_REGADDR(CORE_MOD, \
+ */
-                                OMAP3430_PM_PREPWSTST)
+#define SDRC_SCRATCHPAD_SEM_OFFS        0xc
-#define PM_PREPWSTST_CORE_P     0x48306AE8
+#define SDRC_SCRATCHPAD_SEM_V   OMAP343X_SCRATCHPAD_REGADDR\
-#define PM_PREPWSTST_MPU_V      OMAP34XX_PRM_REGADDR(MPU_MOD, \
+                                        (SDRC_SCRATCHPAD_SEM_OFFS)
-                                OMAP3430_PM_PREPWSTST)
+#define PM_PREPWSTST_CORE_P     OMAP3430_PRM_BASE + CORE_MOD +\
+                                        OMAP3430_PM_PREPWSTST
 #define PM_PWSTCTRL_MPU_P       OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
 #define CM_IDLEST1_CORE_V       OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
-#define SRAM_BASE_P             0x40200000
+#define CM_IDLEST_CKGEN_V       OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
-#define CONTROL_STAT            0x480022F0
+#define SRAM_BASE_P             OMAP3_SRAM_PA
-#define SCRATCHPAD_MEM_OFFS     0x310 /* Move this as correct place is
+#define CONTROL_STAT            OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
-                                       * available */
+#define CONTROL_MEM_RTA_CTRL    (OMAP343X_CTRL_BASE +\
-#define SCRATCHPAD_BASE_P       (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
+                                        OMAP36XX_CONTROL_MEM_RTA_CTRL)
-                                                + SCRATCHPAD_MEM_OFFS)
+/* Move this as correct place is available */
+#define SCRATCHPAD_MEM_OFFS     0x310
+#define SCRATCHPAD_BASE_P       (OMAP343X_CTRL_BASE +\
+                                        OMAP343X_CONTROL_MEM_WKUP +\
+                                        SCRATCHPAD_MEM_OFFS)
 #define SDRC_POWER_V            OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 #define SDRC_SYSCONFIG_P        (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
 #define SDRC_MR_0_P             (OMAP343X_SDRC_BASE + SDRC_MR_0)
@@ -59,48 +64,38 @@
 #define SDRC_DLLA_STATUS_V      OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 #define SDRC_DLLA_CTRL_V        OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
-        .text
-/* Function to acquire the semaphore in scratchpad */
+/*
-ENTRY(lock_scratchpad_sem)
+ * API functions
-        stmfd   sp!, {lr}       @ save registers on stack
+ */
-wait_sem:
-        mov     r0,#1
+/*
-        ldr     r1, sdrc_scratchpad_sem
+ * The "get_*restore_pointer" functions are used to provide a
-wait_loop:
+ * physical restore address where the ROM code jumps while waking
-        ldr     r2, [r1]        @ load the lock value
+ * up from MPU OFF/OSWR state.
-        cmp     r2, r0          @ is the lock free ?
+ * The restore pointer is stored into the scratchpad.
-        beq     wait_loop       @ not free...
+ */
-        swp     r2, r0, [r1]    @ semaphore free so lock it and proceed
-        cmp     r2, r0          @ did we succeed ?
-        beq     wait_sem        @ no - try again
-        ldmfd   sp!, {pc}       @ restore regs and return
-sdrc_scratchpad_sem:
-        .word SDRC_SCRATCHPAD_SEM_V
-ENTRY(lock_scratchpad_sem_sz)
-        .word   . - lock_scratchpad_sem
-        .text
-/* Function to release the scratchpad semaphore */
-ENTRY(unlock_scratchpad_sem)
-        stmfd   sp!, {lr}       @ save registers on stack
-        ldr     r3, sdrc_scratchpad_sem
-        mov     r2,#0
-        str     r2,[r3]
-        ldmfd   sp!, {pc}       @ restore regs and return
-ENTRY(unlock_scratchpad_sem_sz)
-        .word   . - unlock_scratchpad_sem
        .text
 /* Function call to get the restore pointer for resume from OFF */
 ENTRY(get_restore_pointer)
-        stmfd   sp!, {lr}     @ save registers on stack
+        stmfd   sp!, {lr}       @ save registers on stack
        adr     r0, restore
-        ldmfd   sp!, {pc}     @ restore regs and return
+        ldmfd   sp!, {pc}       @ restore regs and return
 ENTRY(get_restore_pointer_sz)
-        .word   . - get_restore_pointer
+        .word   . - get_restore_pointer
        .text
-/* Function call to get the restore pointer for for ES3 to resume from OFF */
+/* Function call to get the restore pointer for 3630 resume from OFF */
+ENTRY(get_omap3630_restore_pointer)
+        stmfd   sp!, {lr}       @ save registers on stack
+        adr     r0, restore_3630
+        ldmfd   sp!, {pc}       @ restore regs and return
+ENTRY(get_omap3630_restore_pointer_sz)
+        .word   . - get_omap3630_restore_pointer
+        .text
+/* Function call to get the restore pointer for ES3 to resume from OFF */
 ENTRY(get_es3_restore_pointer)
        stmfd   sp!, {lr}       @ save registers on stack
        adr     r0, restore_es3
@@ -108,54 +103,23 @@ ENTRY(get_es3_restore_pointer)
 ENTRY(get_es3_restore_pointer_sz)
        .word   . - get_es3_restore_pointer
-ENTRY(es3_sdrc_fix)
+        .text
-        ldr     r4, sdrc_syscfg         @ get config addr
+/*
-        ldr     r5, [r4]                @ get value
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
-        tst     r5, #0x100              @ is part access blocked
+ * This function sets up a flag that will allow for this toggling to take
-        it      eq
+ * place on 3630. Hopefully some version in the future may not need this.
-        biceq   r5, r5, #0x100          @ clear bit if set
+ */
-        str     r5, [r4]                @ write back change
+ENTRY(enable_omap3630_toggle_l2_on_restore)
-        ldr     r4, sdrc_mr_0           @ get config addr
+        stmfd   sp!, {lr}       @ save registers on stack
-        ldr     r5, [r4]                @ get value
+        /* Setup so that we will disable and enable l2 */
-        str     r5, [r4]                @ write back change
+        mov     r1, #0x1
-        ldr     r4, sdrc_emr2_0         @ get config addr
+        str     r1, l2dis_3630
-        ldr     r5, [r4]                @ get value
+        ldmfd   sp!, {pc}       @ restore regs and return
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_manual_0       @ get config addr
-        mov     r5, #0x2                @ autorefresh command
-        str     r5, [r4]                @ kick off refreshes
-        ldr     r4, sdrc_mr_1           @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_emr2_1         @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_manual_1       @ get config addr
-        mov     r5, #0x2                @ autorefresh command
-        str     r5, [r4]                @ kick off refreshes
-        bx      lr
-sdrc_syscfg:
-        .word   SDRC_SYSCONFIG_P
-sdrc_mr_0:
-        .word   SDRC_MR_0_P
-sdrc_emr2_0:
-        .word   SDRC_EMR2_0_P
-sdrc_manual_0:
-        .word   SDRC_MANUAL_0_P
-sdrc_mr_1:
-        .word   SDRC_MR_1_P
-sdrc_emr2_1:
-        .word   SDRC_EMR2_1_P
-sdrc_manual_1:
-        .word   SDRC_MANUAL_1_P
-ENTRY(es3_sdrc_fix_sz)
-        .word   . - es3_sdrc_fix
+        .text
 /* Function to call rom code to save secure ram context */
 ENTRY(save_secure_ram_context)
        stmfd   sp!, {r1-r12, lr}       @ save registers on stack
-save_secure_ram_debug:
-        /* b save_secure_ram_debug */   @ enable to debug save code
        adr     r3, api_params          @ r3 points to parameters
        str     r0, [r3,#0x4]           @ r0 has sdram address
        ldr     r12, high_mask
@@ -185,35 +149,162 @@ ENTRY(save_secure_ram_context_sz)
        .word   . - save_secure_ram_context
 /*
+ * ======================
+ * == Idle entry point ==
+ * ======================
+ */
+/*
 * Forces OMAP into idle state
 *
- * omap34xx_suspend() - This bit of code just executes the WFI
+ * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
- * for normal idles.
+ * and executes the WFI instruction. Calling WFI effectively changes the
+ * power domains states to the desired target power states.
+ *
 *
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
+ * Notes:
- *       wakes up it continues execution at the point it went to sleep.
+ * - this code gets copied to internal SRAM at boot and after wake-up
+ *   from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
+ * - when the OMAP wakes up it continues at different execution points
+ *   depending on the low power mode (non-OFF vs OFF modes),
+ *   cf. 'Resume path for xxx mode' comments.
 */
 ENTRY(omap34xx_cpu_suspend)
-        stmfd   sp!, {r0-r12, lr}               @ save registers on stack
+        stmfd   sp!, {r0-r12, lr}       @ save registers on stack
-loop:
-        /*b     loop*/  @Enable to debug by stepping through code
-        /* r0 contains restore pointer in sdram */
-        /* r1 contains information about saving context */
-        ldr     r4, sdrc_power          @ read the SDRC_POWER register
-        ldr     r5, [r4]                @ read the contents of SDRC_POWER
-        orr     r5, r5, #0x40           @ enable self refresh on idle req
-        str     r5, [r4]                @ write back to SDRC_POWER register
+        /*
+         * r0 contains restore pointer in sdram
+         * r1 contains information about saving context:
+         *   0 - No context lost
+         *   1 - Only L1 and logic lost
+         *   2 - Only L2 lost
+         *   3 - Both L1 and L2 lost
+         */
+        /* Directly jump to WFI is the context save is not required */
        cmp     r1, #0x0
-        /* If context save is required, do that and execute wfi */
+        beq     omap3_do_wfi
-        bne     save_context_wfi
+        /* Otherwise fall through to the save context code */
+save_context_wfi:
+        mov     r8, r0                  @ Store SDRAM address in r8
+        mrc     p15, 0, r5, c1, c0, 1   @ Read Auxiliary Control Register
+        mov     r4, #0x1                @ Number of parameters for restore call
+        stmia   r8!, {r4-r5}            @ Push parameters for restore call
+        mrc     p15, 1, r5, c9, c0, 2   @ Read L2 AUX ctrl register
+        stmia   r8!, {r4-r5}            @ Push parameters for restore call
+        /* Check what that target sleep state is from r1 */
+        cmp     r1, #0x2                @ Only L2 lost, no need to save context
+        beq     clean_caches
+l1_logic_lost:
+        /* Store sp and spsr to SDRAM */
+        mov     r4, sp
+        mrs     r5, spsr
+        mov     r6, lr
+        stmia   r8!, {r4-r6}
+        /* Save all ARM registers */
+        /* Coprocessor access control register */
+        mrc     p15, 0, r6, c1, c0, 2
+        stmia   r8!, {r6}
+        /* TTBR0, TTBR1 and Translation table base control */
+        mrc     p15, 0, r4, c2, c0, 0
+        mrc     p15, 0, r5, c2, c0, 1
+        mrc     p15, 0, r6, c2, c0, 2
+        stmia   r8!, {r4-r6}
+        /*
+         * Domain access control register, data fault status register,
+         * and instruction fault status register
+         */
+        mrc     p15, 0, r4, c3, c0, 0
+        mrc     p15, 0, r5, c5, c0, 0
+        mrc     p15, 0, r6, c5, c0, 1
+        stmia   r8!, {r4-r6}
+        /*
+         * Data aux fault status register, instruction aux fault status,
+         * data fault address register and instruction fault address register
+         */
+        mrc     p15, 0, r4, c5, c1, 0
+        mrc     p15, 0, r5, c5, c1, 1
+        mrc     p15, 0, r6, c6, c0, 0
+        mrc     p15, 0, r7, c6, c0, 2
+        stmia   r8!, {r4-r7}
+        /*
+         * user r/w thread and process ID, user r/o thread and process ID,
+         * priv only thread and process ID, cache size selection
+         */
+        mrc     p15, 0, r4, c13, c0, 2
+        mrc     p15, 0, r5, c13, c0, 3
+        mrc     p15, 0, r6, c13, c0, 4
+        mrc     p15, 2, r7, c0, c0, 0
+        stmia   r8!, {r4-r7}
+        /* Data TLB lockdown, instruction TLB lockdown registers */
+        mrc     p15, 0, r5, c10, c0, 0
+        mrc     p15, 0, r6, c10, c0, 1
+        stmia   r8!, {r5-r6}
+        /* Secure or non secure vector base address, FCSE PID, Context PID*/
+        mrc     p15, 0, r4, c12, c0, 0
+        mrc     p15, 0, r5, c13, c0, 0
+        mrc     p15, 0, r6, c13, c0, 1
+        stmia   r8!, {r4-r6}
+        /* Primary remap, normal remap registers */
+        mrc     p15, 0, r4, c10, c2, 0
+        mrc     p15, 0, r5, c10, c2, 1
+        stmia   r8!,{r4-r5}
+        /* Store current cpsr*/
+        mrs     r2, cpsr
+        stmia   r8!, {r2}
+        mrc     p15, 0, r4, c1, c0, 0
+        /* save control register */
+        stmia   r8!, {r4}
+clean_caches:
+        /*
+         * Clean Data or unified cache to POU
+         * How to invalidate only L1 cache???? - #FIX_ME#
+         * mcr  p15, 0, r11, c7, c11, 1
+         */
+        cmp     r1, #0x1                @ Check whether L2 inval is required
+        beq     omap3_do_wfi
+clean_l2:
+        /*
+         * jump out to kernel flush routine
+         *  - reuse that code is better
+         *  - it executes in a cached space so is faster than refetch per-block
+         *  - should be faster and will change with kernel
+         *  - 'might' have to copy address, load and jump to it
+         */
+        ldr     r1, kernel_flush
+        mov     lr, pc
+        bx      r1
+omap3_do_wfi:
+        ldr     r4, sdrc_power          @ read the SDRC_POWER register
+        ldr     r5, [r4]                @ read the contents of SDRC_POWER
+        orr     r5, r5, #0x40           @ enable self refresh on idle req
+        str     r5, [r4]                @ write back to SDRC_POWER register
        /* Data memory barrier and Data sync barrier */
        mov     r1, #0
        mcr     p15, 0, r1, c7, c10, 4
        mcr     p15, 0, r1, c7, c10, 5
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
        wfi                             @ wait for interrupt
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
        nop
        nop
        nop
@@ -226,9 +317,30 @@ loop:
        nop
        bl wait_sdrc_ok
-        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+/*
+ * ==============================
+ * == Resume path for OFF mode ==
+ * ==============================
+ */
+/*
+ * The restore_* functions are called by the ROM code
+ *  when back from WFI in OFF mode.
+ * Cf. the get_*restore_pointer functions.
+ *
+ *  restore_es3: applies to 34xx >= ES3.0
+ *  restore_3630: applies to 36xx
+ *  restore: common code for 3xxx
+ */
 restore_es3:
-        /*b restore_es3*/               @ Enable to debug restore code
        ldr     r5, pm_prepwstst_core_p
        ldr     r4, [r5]
        and     r4, r4, #0x3
@@ -245,82 +357,117 @@ copy_to_sram:
        bne     copy_to_sram
        ldr     r1, sram_base
        blx     r1
+        b       restore
+restore_3630:
+        ldr     r1, pm_prepwstst_core_p
+        ldr     r2, [r1]
+        and     r2, r2, #0x3
+        cmp     r2, #0x0        @ Check if previous power state of CORE is OFF
+        bne     restore
+        /* Disable RTA before giving control */
+        ldr     r1, control_mem_rta
+        mov     r2, #OMAP36XX_RTA_DISABLE
+        str     r2, [r1]
+        /* Fall through to common code for the remaining logic */
 restore:
-        /* b restore*/  @ Enable to debug restore code
+        /*
-        /* Check what was the reason for mpu reset and store the reason in r9*/
+         * Check what was the reason for mpu reset and store the reason in r9:
-        /* 1 - Only L1 and logic lost */
+         *  0 - No context lost
-        /* 2 - Only L2 lost - In this case, we wont be here */
+         *  1 - Only L1 and logic lost
-        /* 3 - Both L1 and L2 lost */
+         *  2 - Only L2 lost - In this case, we wont be here
-        ldr     r1, pm_pwstctrl_mpu
+         *  3 - Both L1 and L2 lost
+         */
+        ldr     r1, pm_pwstctrl_mpu
        ldr     r2, [r1]
-        and     r2, r2, #0x3
+        and     r2, r2, #0x3
-        cmp     r2, #0x0        @ Check if target power state was OFF or RET
+        cmp     r2, #0x0        @ Check if target power state was OFF or RET
-        moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
+        moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
        movne   r9, #0x1        @ Only L1 and L2 lost => avoid L2 invalidation
        bne     logic_l1_restore
+        ldr     r0, l2dis_3630
+        cmp     r0, #0x1        @ should we disable L2 on 3630?
+        bne     skipl2dis
+        mrc     p15, 0, r0, c1, c0, 1
+        bic     r0, r0, #2      @ disable L2 cache
+        mcr     p15, 0, r0, c1, c0, 1
+skipl2dis:
        ldr     r0, control_stat
        ldr     r1, [r0]
        and     r1, #0x700
        cmp     r1, #0x300
        beq     l2_inv_gp
-        mov     r0, #40         @ set service ID for PPA
+        mov     r0, #40                 @ set service ID for PPA
-        mov     r12, r0         @ copy secure Service ID in r12
+        mov     r12, r0                 @ copy secure Service ID in r12
-        mov     r1, #0          @ set task id for ROM code in r1
+        mov     r1, #0                  @ set task id for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r2, #4                  @ set some flags in r2, r6
        mov     r6, #0xff
        adr     r3, l2_inv_api_params   @ r3 points to dummy parameters
        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
        .word   0xE1600071              @ call SMI monitor (smi #1)
        /* Write to Aux control register to set some bits */
-        mov     r0, #42         @ set service ID for PPA
+        mov     r0, #42                 @ set service ID for PPA
-        mov     r12, r0         @ copy secure Service ID in r12
+        mov     r12, r0                 @ copy secure Service ID in r12
-        mov     r1, #0          @ set task id for ROM code in r1
+        mov     r1, #0                  @ set task id for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r2, #4                  @ set some flags in r2, r6
        mov     r6, #0xff
        ldr     r4, scratchpad_base
-        ldr     r3, [r4, #0xBC] @ r3 points to parameters
+        ldr     r3, [r4, #0xBC]         @ r3 points to parameters
        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
        .word   0xE1600071              @ call SMI monitor (smi #1)
 #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
        /* Restore L2 aux control register */
-        @ set service ID for PPA
+                                        @ set service ID for PPA
        mov     r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
-        mov     r12, r0         @ copy service ID in r12
+        mov     r12, r0                 @ copy service ID in r12
-        mov     r1, #0          @ set task ID for ROM code in r1
+        mov     r1, #0                  @ set task ID for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r2, #4                  @ set some flags in r2, r6
        mov     r6, #0xff
        ldr     r4, scratchpad_base
        ldr     r3, [r4, #0xBC]
-        adds    r3, r3, #8      @ r3 points to parameters
+        adds    r3, r3, #8              @ r3 points to parameters
        mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
        mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
        .word   0xE1600071              @ call SMI monitor (smi #1)
 #endif
        b       logic_l1_restore
 l2_inv_api_params:
-        .word   0x1, 0x00
+        .word   0x1, 0x00
 l2_inv_gp:
        /* Execute smi to invalidate L2 cache */
-        mov r12, #0x1                         @ set up to invalide L2
+        mov r12, #0x1                   @ set up to invalidate L2
-smi:    .word 0xE1600070                @ Call SMI monitor (smieq)
+        .word 0xE1600070                @ Call SMI monitor (smieq)
        /* Write to Aux control register to set some bits */
        ldr     r4, scratchpad_base
        ldr     r3, [r4,#0xBC]
        ldr     r0, [r3,#4]
        mov     r12, #0x3
-        .word 0xE1600070        @ Call SMI monitor (smieq)
+        .word   0xE1600070              @ Call SMI monitor (smieq)
        ldr     r4, scratchpad_base
        ldr     r3, [r4,#0xBC]
        ldr     r0, [r3,#12]
        mov     r12, #0x2
-        .word 0xE1600070        @ Call SMI monitor (smieq)
+        .word   0xE1600070              @ Call SMI monitor (smieq)
 logic_l1_restore:
+        ldr     r1, l2dis_3630
+        cmp     r1, #0x1                @ Test if L2 re-enable needed on 3630
+        bne     skipl2reen
+        mrc     p15, 0, r1, c1, c0, 1
+        orr     r1, r1, #2              @ re-enable L2 cache
+        mcr     p15, 0, r1, c1, c0, 1
+skipl2reen:
        mov     r1, #0
-        /* Invalidate all instruction caches to PoU
+        /*
-         * and flush branch target cache */
+         * Invalidate all instruction caches to PoU
+         * and flush branch target cache
+         */
        mcr     p15, 0, r1, c7, c5, 0
        ldr     r4, scratchpad_base
@@ -341,33 +488,33 @@ logic_l1_restore:
        MCR p15, 0, r6, c2, c0, 1
        /* Translation table base control register */
        MCR p15, 0, r7, c2, c0, 2
-        /*domain access Control Register */
+        /* Domain access Control Register */
        MCR p15, 0, r8, c3, c0, 0
-        /* data fault status Register */
+        /* Data fault status Register */
        MCR p15, 0, r9, c5, c0, 0
-        ldmia  r3!,{r4-r8}
+        ldmia   r3!,{r4-r8}
-        /* instruction fault status Register */
+        /* Instruction fault status Register */
        MCR p15, 0, r4, c5, c0, 1
-        /*Data Auxiliary Fault Status Register */
+        /* Data Auxiliary Fault Status Register */
        MCR p15, 0, r5, c5, c1, 0
-        /*Instruction Auxiliary Fault Status Register*/
+        /* Instruction Auxiliary Fault Status Register*/
        MCR p15, 0, r6, c5, c1, 1
-        /*Data Fault Address Register */
+        /* Data Fault Address Register */
        MCR p15, 0, r7, c6, c0, 0
-        /*Instruction Fault Address Register*/
+        /* Instruction Fault Address Register*/
        MCR p15, 0, r8, c6, c0, 2
-        ldmia  r3!,{r4-r7}
+        ldmia   r3!,{r4-r7}
-        /* user r/w thread and process ID */
+        /* User r/w thread and process ID */
        MCR p15, 0, r4, c13, c0, 2
-        /* user ro thread and process ID */
+        /* User ro thread and process ID */
        MCR p15, 0, r5, c13, c0, 3
-        /*Privileged only thread and process ID */
+        /* Privileged only thread and process ID */
        MCR p15, 0, r6, c13, c0, 4
-        /* cache size selection */
+        /* Cache size selection */
        MCR p15, 2, r7, c0, c0, 0
-        ldmia  r3!,{r4-r8}
+        ldmia   r3!,{r4-r8}
        /* Data TLB lockdown registers */
        MCR p15, 0, r4, c10, c0, 0
        /* Instruction TLB lockdown registers */
@@ -379,26 +526,27 @@ logic_l1_restore:
        /* Context PID */
        MCR p15, 0, r8, c13, c0, 1
-        ldmia  r3!,{r4-r5}
+        ldmia   r3!,{r4-r5}
-        /* primary memory remap register */
+        /* Primary memory remap register */
        MCR p15, 0, r4, c10, c2, 0
-        /*normal memory remap register */
+        /* Normal memory remap register */
        MCR p15, 0, r5, c10, c2, 1
        /* Restore cpsr */
-        ldmia   r3!,{r4}        /*load CPSR from SDRAM*/
+        ldmia   r3!,{r4}                @ load CPSR from SDRAM
-        msr     cpsr, r4        /*store cpsr */
+        msr     cpsr, r4                @ store cpsr
        /* Enabling MMU here */
-        mrc     p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
+        mrc     p15, 0, r7, c2, c0, 2   @ Read TTBRControl
-        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
+        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
        and     r7, #0x7
        cmp     r7, #0x0
        beq     usettbr0
 ttbr_error:
-        /* More work needs to be done to support N[0:2] value other than 0
+        /*
-        * So looping here so that the error can be detected
+         * More work needs to be done to support N[0:2] value other than 0
-        */
+         * So looping here so that the error can be detected
+         */
        b       ttbr_error
 usettbr0:
        mrc     p15, 0, r2, c2, c0, 0
@@ -406,21 +554,25 @@ usettbr0:
        and     r2, r5
        mov     r4, pc
        ldr     r5, table_index_mask
-        and     r4, r5 /* r4 = 31 to 20 bits of pc */
+        and     r4, r5                  @ r4 = 31 to 20 bits of pc
        /* Extract the value to be written to table entry */
        ldr     r1, table_entry
-        add     r1, r1, r4 /* r1 has value to be written to table entry*/
+        /* r1 has the value to be written to table entry*/
+        add     r1, r1, r4
        /* Getting the address of table entry to modify */
        lsr     r4, #18
-        add     r2, r4 /* r2 has the location which needs to be modified */
+        /* r2 has the location which needs to be modified */
+        add     r2, r4
        /* Storing previous entry of location being modified */
        ldr     r5, scratchpad_base
        ldr     r4, [r2]
        str     r4, [r5, #0xC0]
        /* Modify the table entry */
        str     r1, [r2]
-        /* Storing address of entry being modified
+        /*
-         * - will be restored after enabling MMU */
+         * Storing address of entry being modified
+         * - will be restored after enabling MMU
+         */
        ldr     r5, scratchpad_base
        str     r2, [r5, #0xC4]
@@ -429,8 +581,11 @@ usettbr0:
        mcr     p15, 0, r0, c7, c5, 6   @ Invalidate branch predictor array
        mcr     p15, 0, r0, c8, c5, 0   @ Invalidate instruction TLB
        mcr     p15, 0, r0, c8, c6, 0   @ Invalidate data TLB
-        /* Restore control register  but dont enable caches here*/
+        /*
-        /* Caches will be enabled after restoring MMU table entry */
+         * Restore control register. This enables the MMU.
+         * The caches and prediction are not enabled here, they
+         * will be enabled after restoring the MMU table entry.
+         */
        ldmia   r3!, {r4}
        /* Store previous value of control register in scratchpad */
        str     r4, [r5, #0xC8]
@@ -438,212 +593,144 @@ usettbr0:
        and     r4, r2
        mcr     p15, 0, r4, c1, c0, 0
-        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
+/*
-save_context_wfi:
+ * ==============================
-        /*b     save_context_wfi*/      @ enable to debug save code
+ * == Exit point from OFF mode ==
-        mov     r8, r0 /* Store SDRAM address in r8 */
+ * ==============================
-        mrc     p15, 0, r5, c1, c0, 1   @ Read Auxiliary Control Register
+ */
-        mov     r4, #0x1                @ Number of parameters for restore call
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
-        stmia   r8!, {r4-r5}            @ Push parameters for restore call
-        mrc     p15, 1, r5, c9, c0, 2   @ Read L2 AUX ctrl register
-        stmia   r8!, {r4-r5}            @ Push parameters for restore call
-        /* Check what that target sleep state is:stored in r1*/
-        /* 1 - Only L1 and logic lost */
-        /* 2 - Only L2 lost */
-        /* 3 - Both L1 and L2 lost */
-        cmp     r1, #0x2 /* Only L2 lost */
-        beq     clean_l2
-        cmp     r1, #0x1 /* L2 retained */
-        /* r9 stores whether to clean L2 or not*/
-        moveq   r9, #0x0 /* Dont Clean L2 */
-        movne   r9, #0x1 /* Clean L2 */
-l1_logic_lost:
-        /* Store sp and spsr to SDRAM */
-        mov     r4, sp
-        mrs     r5, spsr
-        mov     r6, lr
-        stmia   r8!, {r4-r6}
-        /* Save all ARM registers */
-        /* Coprocessor access control register */
-        mrc     p15, 0, r6, c1, c0, 2
-        stmia   r8!, {r6}
-        /* TTBR0, TTBR1 and Translation table base control */
-        mrc     p15, 0, r4, c2, c0, 0
-        mrc     p15, 0, r5, c2, c0, 1
-        mrc     p15, 0, r6, c2, c0, 2
-        stmia   r8!, {r4-r6}
-        /* Domain access control register, data fault status register,
-        and instruction fault status register */
-        mrc     p15, 0, r4, c3, c0, 0
-        mrc     p15, 0, r5, c5, c0, 0
-        mrc     p15, 0, r6, c5, c0, 1
-        stmia   r8!, {r4-r6}
-        /* Data aux fault status register, instruction aux fault status,
-        datat fault address register and instruction fault address register*/
-        mrc     p15, 0, r4, c5, c1, 0
-        mrc     p15, 0, r5, c5, c1, 1
-        mrc     p15, 0, r6, c6, c0, 0
-        mrc     p15, 0, r7, c6, c0, 2
-        stmia   r8!, {r4-r7}
-        /* user r/w thread and process ID, user r/o thread and process ID,
-        priv only thread and process ID, cache size selection */
-        mrc     p15, 0, r4, c13, c0, 2
-        mrc     p15, 0, r5, c13, c0, 3
-        mrc     p15, 0, r6, c13, c0, 4
-        mrc     p15, 2, r7, c0, c0, 0
-        stmia   r8!, {r4-r7}
-        /* Data TLB lockdown, instruction TLB lockdown registers */
-        mrc     p15, 0, r5, c10, c0, 0
-        mrc     p15, 0, r6, c10, c0, 1
-        stmia   r8!, {r5-r6}
-        /* Secure or non secure vector base address, FCSE PID, Context PID*/
-        mrc     p15, 0, r4, c12, c0, 0
-        mrc     p15, 0, r5, c13, c0, 0
-        mrc     p15, 0, r6, c13, c0, 1
-        stmia   r8!, {r4-r6}
-        /* Primary remap, normal remap registers */
-        mrc     p15, 0, r4, c10, c2, 0
-        mrc     p15, 0, r5, c10, c2, 1
-        stmia   r8!,{r4-r5}
-        /* Store current cpsr*/
-        mrs     r2, cpsr
-        stmia   r8!, {r2}
-        mrc     p15, 0, r4, c1, c0, 0
+/*
-        /* save control register */
+ * Internal functions
-        stmia   r8!, {r4}
+ */
-clean_caches:
-        /* Clean Data or unified cache to POU*/
-        /* How to invalidate only L1 cache???? - #FIX_ME# */
-        /* mcr  p15, 0, r11, c7, c11, 1 */
-        cmp     r9, #1 /* Check whether L2 inval is required or not*/
-        bne     skip_l2_inval
-clean_l2:
-        /* read clidr */
-        mrc     p15, 1, r0, c0, c0, 1
-        /* extract loc from clidr */
-        ands    r3, r0, #0x7000000
-        /* left align loc bit field */
-        mov     r3, r3, lsr #23
-        /* if loc is 0, then no need to clean */
-        beq     finished
-        /* start clean at cache level 0 */
-        mov     r10, #0
-loop1:
-        /* work out 3x current cache level */
-        add     r2, r10, r10, lsr #1
-        /* extract cache type bits from clidr*/
-        mov     r1, r0, lsr r2
-        /* mask of the bits for current cache only */
-        and     r1, r1, #7
-        /* see what cache we have at this level */
-        cmp     r1, #2
-        /* skip if no cache, or just i-cache */
-        blt     skip
-        /* select current cache level in cssr */
-        mcr     p15, 2, r10, c0, c0, 0
-        /* isb to sych the new cssr&csidr */
-        isb
-        /* read the new csidr */
-        mrc     p15, 1, r1, c0, c0, 0
-        /* extract the length of the cache lines */
-        and     r2, r1, #7
-        /* add 4 (line length offset) */
-        add     r2, r2, #4
-        ldr     r4, assoc_mask
-        /* find maximum number on the way size */
-        ands    r4, r4, r1, lsr #3
-        /* find bit position of way size increment */
-        clz     r5, r4
-        ldr     r7, numset_mask
-        /* extract max number of the index size*/
-        ands    r7, r7, r1, lsr #13
-loop2:
-        mov     r9, r4
-        /* create working copy of max way size*/
-loop3:
-        /* factor way and cache number into r11 */
-        orr     r11, r10, r9, lsl r5
-        /* factor index number into r11 */
-        orr     r11, r11, r7, lsl r2
-        /*clean & invalidate by set/way */
-        mcr     p15, 0, r11, c7, c10, 2
-        /* decrement the way*/
-        subs    r9, r9, #1
-        bge     loop3
-        /*decrement the index */
-        subs    r7, r7, #1
-        bge     loop2
-skip:
-        add     r10, r10, #2
-        /* increment cache number */
-        cmp     r3, r10
-        bgt     loop1
-finished:
-        /*swith back to cache level 0 */
-        mov     r10, #0
-        /* select current cache level in cssr */
-        mcr     p15, 2, r10, c0, c0, 0
-        isb
-skip_l2_inval:
-        /* Data memory barrier and Data sync barrier */
-        mov     r1, #0
-        mcr     p15, 0, r1, c7, c10, 4
-        mcr     p15, 0, r1, c7, c10, 5
-        wfi                             @ wait for interrupt
+/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
-        nop
+        .text
-        nop
+ENTRY(es3_sdrc_fix)
-        nop
+        ldr     r4, sdrc_syscfg         @ get config addr
-        nop
+        ldr     r5, [r4]                @ get value
-        nop
+        tst     r5, #0x100              @ is part access blocked
-        nop
+        it      eq
-        nop
+        biceq   r5, r5, #0x100          @ clear bit if set
-        nop
+        str     r5, [r4]                @ write back change
-        nop
+        ldr     r4, sdrc_mr_0           @ get config addr
-        nop
+        ldr     r5, [r4]                @ get value
-        bl wait_sdrc_ok
+        str     r5, [r4]                @ write back change
-        /* restore regs and return */
+        ldr     r4, sdrc_emr2_0         @ get config addr
-        ldmfd   sp!, {r0-r12, pc}
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_manual_0       @ get config addr
+        mov     r5, #0x2                @ autorefresh command
+        str     r5, [r4]                @ kick off refreshes
+        ldr     r4, sdrc_mr_1           @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_emr2_1         @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_manual_1       @ get config addr
+        mov     r5, #0x2                @ autorefresh command
+        str     r5, [r4]                @ kick off refreshes
+        bx      lr
+sdrc_syscfg:
+        .word   SDRC_SYSCONFIG_P
+sdrc_mr_0:
+        .word   SDRC_MR_0_P
+sdrc_emr2_0:
+        .word   SDRC_EMR2_0_P
+sdrc_manual_0:
+        .word   SDRC_MANUAL_0_P
+sdrc_mr_1:
+        .word   SDRC_MR_1_P
+sdrc_emr2_1:
+        .word   SDRC_EMR2_1_P
+sdrc_manual_1:
+        .word   SDRC_MANUAL_1_P
+ENTRY(es3_sdrc_fix_sz)
+        .word   . - es3_sdrc_fix
+/*
+ * This function implements the erratum ID i581 WA:
+ *  SDRC state restore before accessing the SDRAM
+ *
+ * Only used at return from non-OFF mode. For OFF
+ * mode the ROM code configures the SDRC and
+ * the DPLL before calling the restore code directly
+ * from DDR.
+ */
 /* Make sure SDRC accesses are ok */
 wait_sdrc_ok:
-        ldr     r4, cm_idlest1_core
-        ldr     r5, [r4]
+/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
-        and     r5, r5, #0x2
+        ldr     r4, cm_idlest_ckgen
-        cmp     r5, #0
+wait_dpll3_lock:
-        bne     wait_sdrc_ok
+        ldr     r5, [r4]
-        ldr     r4, sdrc_power
+        tst     r5, #1
-        ldr     r5, [r4]
+        beq     wait_dpll3_lock
-        bic     r5, r5, #0x40
-        str     r5, [r4]
+        ldr     r4, cm_idlest1_core
+wait_sdrc_ready:
+        ldr     r5, [r4]
+        tst     r5, #0x2
+        bne     wait_sdrc_ready
+        /* allow DLL powerdown upon hw idle req */
+        ldr     r4, sdrc_power
+        ldr     r5, [r4]
+        bic     r5, r5, #0x40
+        str     r5, [r4]
+is_dll_in_lock_mode:
+        /* Is dll in lock mode? */
+        ldr     r4, sdrc_dlla_ctrl
+        ldr     r5, [r4]
+        tst     r5, #0x4
+        bxne    lr                      @ Return if locked
+        /* wait till dll locks */
+wait_dll_lock_timed:
+        ldr     r4, wait_dll_lock_counter
+        add     r4, r4, #1
+        str     r4, wait_dll_lock_counter
+        ldr     r4, sdrc_dlla_status
+        /* Wait 20uS for lock */
+        mov     r6, #8
 wait_dll_lock:
-        /* Is dll in lock mode? */
+        subs    r6, r6, #0x1
-        ldr     r4, sdrc_dlla_ctrl
+        beq     kick_dll
-        ldr     r5, [r4]
+        ldr     r5, [r4]
-        tst     r5, #0x4
+        and     r5, r5, #0x4
-        bxne    lr
+        cmp     r5, #0x4
-        /* wait till dll locks */
+        bne     wait_dll_lock
-        ldr     r4, sdrc_dlla_status
+        bx      lr                      @ Return when locked
-        ldr     r5, [r4]
-        and     r5, r5, #0x4
+        /* disable/reenable DLL if not locked */
-        cmp     r5, #0x4
+kick_dll:
-        bne     wait_dll_lock
+        ldr     r4, sdrc_dlla_ctrl
-        bx      lr
+        ldr     r5, [r4]
+        mov     r6, r5
+        bic     r6, #(1<<3)             @ disable dll
+        str     r6, [r4]
+        dsb
+        orr     r6, r6, #(1<<3)         @ enable dll
+        str     r6, [r4]
+        dsb
+        ldr     r4, kick_counter
+        add     r4, r4, #1
+        str     r4, kick_counter
+        b       wait_dll_lock_timed
 cm_idlest1_core:
        .word   CM_IDLEST1_CORE_V
+cm_idlest_ckgen:
+        .word   CM_IDLEST_CKGEN_V
 sdrc_dlla_status:
        .word   SDRC_DLLA_STATUS_V
 sdrc_dlla_ctrl:
        .word   SDRC_DLLA_CTRL_V
-pm_prepwstst_core:
-        .word   PM_PREPWSTST_CORE_V
 pm_prepwstst_core_p:
        .word   PM_PREPWSTST_CORE_P
-pm_prepwstst_mpu:
-        .word   PM_PREPWSTST_MPU_V
 pm_pwstctrl_mpu:
        .word   PM_PWSTCTRL_MPU_P
 scratchpad_base:
@@ -651,13 +738,7 @@ scratchpad_base:
 sram_base:
        .word   SRAM_BASE_P + 0x8000
 sdrc_power:
-        .word SDRC_POWER_V
+        .word   SDRC_POWER_V
-clk_stabilize_delay:
-        .word 0x000001FF
-assoc_mask:
-        .word   0x3ff
-numset_mask:
-        .word   0x7fff
 ttbrbit_mask:
        .word   0xFFFFC000
 table_index_mask:
@@ -668,5 +749,20 @@ cache_pred_disable_mask:
        .word   0xFFFFE7FB
 control_stat:
        .word   CONTROL_STAT
+control_mem_rta:
+        .word   CONTROL_MEM_RTA_CTRL
+kernel_flush:
+        .word   v7_flush_dcache_all
+l2dis_3630:
+        .word   0
+        /*
+         * When exporting to userspace while the counters are in SRAM,
+         * these 2 words need to be at the end to facilitate retrival!
+         */
+kick_counter:
+        .word   0
+wait_dll_lock_counter:
+        .word   0
 ENTRY(omap34xx_cpu_suspend_sz)
        .word   . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index fa2e5bffbb8e..6983cb4d4cae 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -28,9 +28,16 @@ config S3C2412_DMA
 config S3C2412_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2412 power management
+config S3C2412_PM_SLEEP
+        bool
+        help
+          Internal config node to apply sleep for S3C2412 power management.
+          Can be selected by another SoCs with similar sleep procedure.
 # Note, the S3C2412 IOtiming support is in plat-s3c24xx
 config S3C2412_CPUFREQ
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 530ec46cbaea..6c48a91ea39e 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -14,7 +14,8 @@ obj-$(CONFIG_CPU_S3C2412)	+= irq.o
 obj-$(CONFIG_CPU_S3C2412)       += clock.o
 obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
-obj-$(CONFIG_S3C2412_PM)        += pm.o sleep.o
+obj-$(CONFIG_S3C2412_PM)        += pm.o
+obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
 # Machine support
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 27b3e7c9d613..df8d14974c90 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -27,6 +27,7 @@ config S3C2416_DMA
 config S3C2416_PM
        bool
+        select S3C2412_PM_SLEEP
        help
          Internal config node to apply S3C2416 power management
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 28677caf3613..461aa035afc0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -378,6 +378,12 @@ static struct max8998_regulator_data aquila_regulators[] = {
 static struct max8998_platform_data aquila_max8998_pdata = {
        .num_regulators = ARRAY_SIZE(aquila_regulators),
        .regulators     = aquila_regulators,
+        .buck1_set1     = S5PV210_GPH0(3),
+        .buck1_set2     = S5PV210_GPH0(4),
+        .buck2_set3     = S5PV210_GPH0(5),
+        .buck1_max_voltage1 = 1200000,
+        .buck1_max_voltage2 = 1200000,
+        .buck2_max_voltage = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index b1dcf964a768..e22d5112fd44 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -518,6 +518,12 @@ static struct max8998_regulator_data goni_regulators[] = {
 static struct max8998_platform_data goni_max8998_pdata = {
        .num_regulators = ARRAY_SIZE(goni_regulators),
        .regulators     = goni_regulators,
+        .buck1_set1     = S5PV210_GPH0(3),
+        .buck1_set2     = S5PV210_GPH0(4),
+        .buck2_set3     = S5PV210_GPH0(5),
+        .buck1_max_voltage1 = 1200000,
+        .buck1_max_voltage2 = 1200000,
+        .buck2_max_voltage = 1200000,
 };
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index a285d13c7416..f428c4db2b60 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2010 Magnus Damm
 * Copyright (C) 2008 Renesas Solutions Corp.
 *
 * This program is free software; you can redistribute it and/or modify
@@ -14,24 +15,45 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <mach/hardware.h>
 #include <mach/irqs.h>
+#define INTCA_BASE      0xe6980000
+#define INTFLGA_OFFS    0x00000018 /* accept pending interrupt */
+#define INTEVTA_OFFS    0x00000020 /* vector number of accepted interrupt */
+#define INTLVLA_OFFS    0x00000030 /* priority level of accepted interrupt */
+#define INTLVLB_OFFS    0x00000034 /* previous priority level */
        .macro  disable_fiq
        .endm
        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =INTFLGA
+        ldr     \base, =INTCA_BASE
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base]
+        /* The single INTFLGA read access below results in the following:
+         *
+         * 1. INTLVLB is updated with old priority value from INTLVLA
+         * 2. Highest priority interrupt is accepted
+         * 3. INTLVLA is updated to contain priority of accepted interrupt
+         * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
+         */
+        ldr     \irqnr, [\base, #INTFLGA_OFFS]
+        /* Restore INTLVLA with the value saved in INTLVLB.
+         * This is required to support interrupt priorities properly.
+         */
+        ldrb    \tmp, [\base, #INTLVLB_OFFS]
+        strb    \tmp, [\base, #INTLVLA_OFFS]
+        /* Handle invalid vector number case */
        cmp     \irqnr, #0
        beq     1000f
-        /* intevt to irq number */
+        /* Convert vector to irq number, same as the evt2irq() macro */
        lsr     \irqnr, \irqnr, #0x5
        subs    \irqnr, \irqnr, #16
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
index 4aecf6e3a859..2b8fd8b942fe 100644
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ b/arch/arm/mach-shmobile/include/mach/vmalloc.h
@@ -2,6 +2,6 @@
 #define __ASM_MACH_VMALLOC_H
 /* Vmalloc at ... - 0xe5ffffff */
-#define VMALLOC_END 0xe6000000
+#define VMALLOC_END 0xe6000000UL
 #endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index a863f5546a6b..c4b2b478b1a5 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -15,6 +15,10 @@
 *
 * Support functions for the OMAP internal DMA channels.
 *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into DMA platform driver.
+ *      - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -53,7 +57,11 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
+static struct omap_system_dma_plat_info *p;
+static struct omap_dma_dev_attr *d;
 static int enable_1510_mode;
+static u32 errata;
 static struct omap_dma_global_context_registers {
        u32 dma_irqenable_l0;
@@ -61,27 +69,6 @@ static struct omap_dma_global_context_registers {
        u32 dma_gcr;
 } omap_dma_global_context;
-struct omap_dma_lch {
-        int next_lch;
-        int dev_id;
-        u16 saved_csr;
-        u16 enabled_irqs;
-        const char *dev_name;
-        void (*callback)(int lch, u16 ch_status, void *data);
-        void *data;
-#ifndef CONFIG_ARCH_OMAP1
-        /* required for Dynamic chaining */
-        int prev_linked_ch;
-        int next_linked_ch;
-        int state;
-        int chain_id;
-        int status;
-#endif
-        long flags;
-};
 struct dma_link_info {
        int *linked_dmach_q;
        int no_of_lchs_linked;
@@ -137,15 +124,6 @@ static int omap_dma_reserve_channels;
 static spinlock_t dma_chan_lock;
 static struct omap_dma_lch *dma_chan;
-static void __iomem *omap_dma_base;
-static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
-        INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
-        INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
-        INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
-        INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
-        INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
-};
 static inline void disable_lnk(int lch);
 static void omap_disable_channel_irq(int lch);
@@ -154,27 +132,9 @@ static inline void omap_enable_channel_irq(int lch);
 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
                                                __func__);
-#define dma_read(reg)                                                   \
-({                                                                      \
-        u32 __val;                                                      \
-        if (cpu_class_is_omap1())                                       \
-                __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
-        else                                                            \
-                __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
-        __val;                                                          \
-})
-#define dma_write(val, reg)                                             \
-({                                                                      \
-        if (cpu_class_is_omap1())                                       \
-                __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
-        else                                                            \
-                __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
-})
 #ifdef CONFIG_ARCH_OMAP15XX
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-static int omap_dma_in_1510_mode(void)
+int omap_dma_in_1510_mode(void)
 {
        return enable_1510_mode;
 }
@@ -206,16 +166,6 @@ static inline void set_gdma_dev(int req, int dev)
 #define set_gdma_dev(req, dev)  do {} while (0)
 #endif
-/* Omap1 only */
-static void clear_lch_regs(int lch)
-{
-        int i;
-        void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
-        for (i = 0; i < 0x2c; i += 2)
-                __raw_writew(0, lch_base + i);
-}
 void omap_set_dma_priority(int lch, int dst_port, int priority)
 {
        unsigned long reg;
@@ -248,12 +198,12 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
        if (cpu_class_is_omap2()) {
                u32 ccr;
-                ccr = dma_read(CCR(lch));
+                ccr = p->dma_read(CCR, lch);
                if (priority)
                        ccr |= (1 << 6);
                else
                        ccr &= ~(1 << 6);
-                dma_write(ccr, CCR(lch));
+                p->dma_write(ccr, CCR, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_priority);
@@ -264,31 +214,31 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 {
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~0x03;
        l |= data_type;
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
        if (cpu_class_is_omap1()) {
                u16 ccr;
-                ccr = dma_read(CCR(lch));
+                ccr = p->dma_read(CCR, lch);
                ccr &= ~(1 << 5);
                if (sync_mode == OMAP_DMA_SYNC_FRAME)
                        ccr |= 1 << 5;
-                dma_write(ccr, CCR(lch));
+                p->dma_write(ccr, CCR, lch);
-                ccr = dma_read(CCR2(lch));
+                ccr = p->dma_read(CCR2, lch);
                ccr &= ~(1 << 2);
                if (sync_mode == OMAP_DMA_SYNC_BLOCK)
                        ccr |= 1 << 2;
-                dma_write(ccr, CCR2(lch));
+                p->dma_write(ccr, CCR2, lch);
        }
        if (cpu_class_is_omap2() && dma_trigger) {
                u32 val;
-                val = dma_read(CCR(lch));
+                val = p->dma_read(CCR, lch);
                /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
                val &= ~((1 << 23) | (3 << 19) | 0x1f);
@@ -313,11 +263,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                } else {
                        val &= ~(1 << 24);      /* dest synch */
                }
-                dma_write(val, CCR(lch));
+                p->dma_write(val, CCR, lch);
        }
-        dma_write(elem_count, CEN(lch));
+        p->dma_write(elem_count, CEN, lch);
-        dma_write(frame_count, CFN(lch));
+        p->dma_write(frame_count, CFN, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_transfer_params);
@@ -328,7 +278,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
        if (cpu_class_is_omap1()) {
                u16 w;
-                w = dma_read(CCR2(lch));
+                w = p->dma_read(CCR2, lch);
                w &= ~0x03;
                switch (mode) {
@@ -343,23 +293,22 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                default:
                        BUG();
                }
-                dma_write(w, CCR2(lch));
+                p->dma_write(w, CCR2, lch);
-                w = dma_read(LCH_CTRL(lch));
+                w = p->dma_read(LCH_CTRL, lch);
                w &= ~0x0f;
                /* Default is channel type 2D */
                if (mode) {
-                        dma_write((u16)color, COLOR_L(lch));
+                        p->dma_write(color, COLOR, lch);
-                        dma_write((u16)(color >> 16), COLOR_U(lch));
                        w |= 1;         /* Channel type G */
                }
-                dma_write(w, LCH_CTRL(lch));
+                p->dma_write(w, LCH_CTRL, lch);
        }
        if (cpu_class_is_omap2()) {
                u32 val;
-                val = dma_read(CCR(lch));
+                val = p->dma_read(CCR, lch);
                val &= ~((1 << 17) | (1 << 16));
                switch (mode) {
@@ -374,10 +323,10 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                default:
                        BUG();
                }
-                dma_write(val, CCR(lch));
+                p->dma_write(val, CCR, lch);
                color &= 0xffffff;
-                dma_write(color, COLOR(lch));
+                p->dma_write(color, COLOR, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_color_mode);
@@ -387,10 +336,10 @@ void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
        if (cpu_class_is_omap2()) {
                u32 csdp;
-                csdp = dma_read(CSDP(lch));
+                csdp = p->dma_read(CSDP, lch);
                csdp &= ~(0x3 << 16);
                csdp |= (mode << 16);
-                dma_write(csdp, CSDP(lch));
+                p->dma_write(csdp, CSDP, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_write_mode);
@@ -400,10 +349,10 @@ void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
        if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
                u32 l;
-                l = dma_read(LCH_CTRL(lch));
+                l = p->dma_read(LCH_CTRL, lch);
                l &= ~0x7;
                l |= mode;
-                dma_write(l, LCH_CTRL(lch));
+                p->dma_write(l, LCH_CTRL, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_channel_mode);
@@ -418,27 +367,21 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
        if (cpu_class_is_omap1()) {
                u16 w;
-                w = dma_read(CSDP(lch));
+                w = p->dma_read(CSDP, lch);
                w &= ~(0x1f << 2);
                w |= src_port << 2;
-                dma_write(w, CSDP(lch));
+                p->dma_write(w, CSDP, lch);
        }
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
        l &= ~(0x03 << 12);
        l |= src_amode << 12;
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
-        if (cpu_class_is_omap1()) {
-                dma_write(src_start >> 16, CSSA_U(lch));
-                dma_write((u16)src_start, CSSA_L(lch));
-        }
-        if (cpu_class_is_omap2())
+        p->dma_write(src_start, CSSA, lch);
-                dma_write(src_start, CSSA(lch));
-        dma_write(src_ei, CSEI(lch));
+        p->dma_write(src_ei, CSEI, lch);
-        dma_write(src_fi, CSFI(lch));
+        p->dma_write(src_fi, CSFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_params);
@@ -466,8 +409,8 @@ void omap_set_dma_src_index(int lch, int eidx, int fidx)
        if (cpu_class_is_omap2())
                return;
-        dma_write(eidx, CSEI(lch));
+        p->dma_write(eidx, CSEI, lch);
-        dma_write(fidx, CSFI(lch));
+        p->dma_write(fidx, CSFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_index);
@@ -475,11 +418,11 @@ void omap_set_dma_src_data_pack(int lch, int enable)
 {
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(1 << 6);
        if (enable)
                l |= (1 << 6);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
@@ -488,7 +431,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        unsigned int burst = 0;
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(0x03 << 7);
        switch (burst_mode) {
@@ -524,7 +467,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        }
        l |= (burst << 7);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
@@ -536,27 +479,21 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
        u32 l;
        if (cpu_class_is_omap1()) {
-                l = dma_read(CSDP(lch));
+                l = p->dma_read(CSDP, lch);
                l &= ~(0x1f << 9);
                l |= dest_port << 9;
-                dma_write(l, CSDP(lch));
+                p->dma_write(l, CSDP, lch);
        }
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
        l &= ~(0x03 << 14);
        l |= dest_amode << 14;
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
-        if (cpu_class_is_omap1()) {
-                dma_write(dest_start >> 16, CDSA_U(lch));
-                dma_write(dest_start, CDSA_L(lch));
-        }
-        if (cpu_class_is_omap2())
+        p->dma_write(dest_start, CDSA, lch);
-                dma_write(dest_start, CDSA(lch));
-        dma_write(dst_ei, CDEI(lch));
+        p->dma_write(dst_ei, CDEI, lch);
-        dma_write(dst_fi, CDFI(lch));
+        p->dma_write(dst_fi, CDFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_params);
@@ -565,8 +502,8 @@ void omap_set_dma_dest_index(int lch, int eidx, int fidx)
        if (cpu_class_is_omap2())
                return;
-        dma_write(eidx, CDEI(lch));
+        p->dma_write(eidx, CDEI, lch);
-        dma_write(fidx, CDFI(lch));
+        p->dma_write(fidx, CDFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_index);
@@ -574,11 +511,11 @@ void omap_set_dma_dest_data_pack(int lch, int enable)
 {
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(1 << 13);
        if (enable)
                l |= 1 << 13;
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
@@ -587,7 +524,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        unsigned int burst = 0;
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(0x03 << 14);
        switch (burst_mode) {
@@ -620,7 +557,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
                return;
        }
        l |= (burst << 14);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
@@ -630,18 +567,18 @@ static inline void omap_enable_channel_irq(int lch)
        /* Clear CSR */
        if (cpu_class_is_omap1())
-                status = dma_read(CSR(lch));
+                status = p->dma_read(CSR, lch);
        else if (cpu_class_is_omap2())
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
        /* Enable some nice interrupts. */
-        dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
+        p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 }
 static void omap_disable_channel_irq(int lch)
 {
        if (cpu_class_is_omap2())
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
 }
 void omap_enable_dma_irq(int lch, u16 bits)
@@ -660,7 +597,7 @@ static inline void enable_lnk(int lch)
 {
        u32 l;
-        l = dma_read(CLNK_CTRL(lch));
+        l = p->dma_read(CLNK_CTRL, lch);
        if (cpu_class_is_omap1())
                l &= ~(1 << 14);
@@ -675,18 +612,18 @@ static inline void enable_lnk(int lch)
                        l = dma_chan[lch].next_linked_ch | (1 << 15);
 #endif
-        dma_write(l, CLNK_CTRL(lch));
+        p->dma_write(l, CLNK_CTRL, lch);
 }
 static inline void disable_lnk(int lch)
 {
        u32 l;
-        l = dma_read(CLNK_CTRL(lch));
+        l = p->dma_read(CLNK_CTRL, lch);
        /* Disable interrupts */
        if (cpu_class_is_omap1()) {
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                /* Set the STOP_LNK bit */
                l |= 1 << 14;
        }
@@ -697,7 +634,7 @@ static inline void disable_lnk(int lch)
                l &= ~(1 << 15);
        }
-        dma_write(l, CLNK_CTRL(lch));
+        p->dma_write(l, CLNK_CTRL, lch);
        dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 }
@@ -710,9 +647,9 @@ static inline void omap2_enable_irq_lch(int lch)
                return;
        spin_lock_irqsave(&dma_chan_lock, flags);
-        val = dma_read(IRQENABLE_L0);
+        val = p->dma_read(IRQENABLE_L0, lch);
        val |= 1 << lch;
-        dma_write(val, IRQENABLE_L0);
+        p->dma_write(val, IRQENABLE_L0, lch);
        spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
@@ -725,9 +662,9 @@ static inline void omap2_disable_irq_lch(int lch)
                return;
        spin_lock_irqsave(&dma_chan_lock, flags);
-        val = dma_read(IRQENABLE_L0);
+        val = p->dma_read(IRQENABLE_L0, lch);
        val &= ~(1 << lch);
-        dma_write(val, IRQENABLE_L0);
+        p->dma_write(val, IRQENABLE_L0, lch);
        spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
@@ -754,8 +691,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
        chan = dma_chan + free_ch;
        chan->dev_id = dev_id;
-        if (cpu_class_is_omap1())
+        if (p->clear_lch_regs)
-                clear_lch_regs(free_ch);
+                p->clear_lch_regs(free_ch);
        if (cpu_class_is_omap2())
                omap_clear_dma(free_ch);
@@ -792,17 +729,17 @@ int omap_request_dma(int dev_id, const char *dev_name,
                 * Disable the 1510 compatibility mode and set the sync device
                 * id.
                 */
-                dma_write(dev_id | (1 << 10), CCR(free_ch));
+                p->dma_write(dev_id | (1 << 10), CCR, free_ch);
        } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
-                dma_write(dev_id, CCR(free_ch));
+                p->dma_write(dev_id, CCR, free_ch);
        }
        if (cpu_class_is_omap2()) {
                omap2_enable_irq_lch(free_ch);
                omap_enable_channel_irq(free_ch);
                /* Clear the CSR register and IRQ status register */
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
-                dma_write(1 << free_ch, IRQSTATUS_L0);
+                p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
        }
        *dma_ch_out = free_ch;
@@ -823,23 +760,23 @@ void omap_free_dma(int lch)
        if (cpu_class_is_omap1()) {
                /* Disable all DMA interrupts for the channel. */
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                /* Make sure the DMA transfer is stopped. */
-                dma_write(0, CCR(lch));
+                p->dma_write(0, CCR, lch);
        }
        if (cpu_class_is_omap2()) {
                omap2_disable_irq_lch(lch);
                /* Clear the CSR register and IRQ status register */
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
-                dma_write(1 << lch, IRQSTATUS_L0);
+                p->dma_write(1 << lch, IRQSTATUS_L0, lch);
                /* Disable all DMA interrupts for the channel. */
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                /* Make sure the DMA transfer is stopped. */
-                dma_write(0, CCR(lch));
+                p->dma_write(0, CCR, lch);
                omap_clear_dma(lch);
        }
@@ -880,7 +817,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
        reg |= (0x3 & tparams) << 12;
        reg |= (arb_rate & 0xff) << 16;
-        dma_write(reg, GCR);
+        p->dma_write(reg, GCR, 0);
 }
 EXPORT_SYMBOL(omap_dma_set_global_params);
@@ -903,14 +840,14 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                printk(KERN_ERR "Invalid channel id\n");
                return -EINVAL;
        }
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
        l &= ~((1 << 6) | (1 << 26));
        if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
                l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
        else
                l |= ((read_prio & 0x1) << 6);
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
        return 0;
 }
@@ -925,25 +862,7 @@ void omap_clear_dma(int lch)
        unsigned long flags;
        local_irq_save(flags);
+        p->clear_dma(lch);
-        if (cpu_class_is_omap1()) {
-                u32 l;
-                l = dma_read(CCR(lch));
-                l &= ~OMAP_DMA_CCR_EN;
-                dma_write(l, CCR(lch));
-                /* Clear pending interrupts */
-                l = dma_read(CSR(lch));
-        }
-        if (cpu_class_is_omap2()) {
-                int i;
-                void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
-                for (i = 0; i < 0x44; i += 4)
-                        __raw_writel(0, lch_base + i);
-        }
        local_irq_restore(flags);
 }
 EXPORT_SYMBOL(omap_clear_dma);
@@ -957,13 +876,13 @@ void omap_start_dma(int lch)
         * before starting dma transfer.
         */
        if (cpu_is_omap15xx())
-                dma_write(0, CPC(lch));
+                p->dma_write(0, CPC, lch);
        else
-                dma_write(0, CDAC(lch));
+                p->dma_write(0, CDAC, lch);
        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                int next_lch, cur_lch;
-                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[dma_lch_count];
                dma_chan_link_map[lch] = 1;
                /* Set the link register of the first channel */
@@ -985,32 +904,18 @@ void omap_start_dma(int lch)
                        cur_lch = next_lch;
                } while (next_lch != -1);
-        } else if (cpu_is_omap242x() ||
+        } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
-                (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
+                p->dma_write(lch, CLNK_CTRL, lch);
-                /* Errata: Need to write lch even if not using chaining */
-                dma_write(lch, CLNK_CTRL(lch));
-        }
        omap_enable_channel_irq(lch);
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
-        /*
-         * Errata: Inter Frame DMA buffering issue (All OMAP2420 and
-         * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and
-         * bursting is enabled. This might result in data gets stalled in
-         * FIFO at the end of the block.
-         * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
-         * guarantee no data will stay in the DMA FIFO in case inter frame
-         * buffering occurs.
-         */
-        if (cpu_is_omap2420() ||
-            (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0)))
-                l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
+        if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
+                        l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
        l |= OMAP_DMA_CCR_EN;
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 }
@@ -1022,46 +927,46 @@ void omap_stop_dma(int lch)
        /* Disable all interrupts on the channel */
        if (cpu_class_is_omap1())
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
-        /* OMAP3 Errata i541: sDMA FIFO draining does not finish */
+        if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
-        if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
+                        (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
                int i = 0;
                u32 sys_cf;
                /* Configure No-Standby */
-                l = dma_read(OCP_SYSCONFIG);
+                l = p->dma_read(OCP_SYSCONFIG, lch);
                sys_cf = l;
                l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
                l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
-                dma_write(l , OCP_SYSCONFIG);
+                p->dma_write(l , OCP_SYSCONFIG, 0);
-                l = dma_read(CCR(lch));
+                l = p->dma_read(CCR, lch);
                l &= ~OMAP_DMA_CCR_EN;
-                dma_write(l, CCR(lch));
+                p->dma_write(l, CCR, lch);
                /* Wait for sDMA FIFO drain */
-                l = dma_read(CCR(lch));
+                l = p->dma_read(CCR, lch);
                while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
                                        OMAP_DMA_CCR_WR_ACTIVE))) {
                        udelay(5);
                        i++;
-                        l = dma_read(CCR(lch));
+                        l = p->dma_read(CCR, lch);
                }
                if (i >= 100)
                        printk(KERN_ERR "DMA drain did not complete on "
                                        "lch %d\n", lch);
                /* Restore OCP_SYSCONFIG */
-                dma_write(sys_cf, OCP_SYSCONFIG);
+                p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
        } else {
                l &= ~OMAP_DMA_CCR_EN;
-                dma_write(l, CCR(lch));
+                p->dma_write(l, CCR, lch);
        }
        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                int next_lch, cur_lch = lch;
-                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[dma_lch_count];
                memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
                do {
@@ -1122,19 +1027,15 @@ dma_addr_t omap_get_dma_src_pos(int lch)
        dma_addr_t offset = 0;
        if (cpu_is_omap15xx())
-                offset = dma_read(CPC(lch));
+                offset = p->dma_read(CPC, lch);
        else
-                offset = dma_read(CSAC(lch));
+                offset = p->dma_read(CSAC, lch);
-        /*
+        if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
-         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+                offset = p->dma_read(CSAC, lch);
-         * read before the DMA controller finished disabling the channel.
-         */
-        if (!cpu_is_omap15xx() && offset == 0)
-                offset = dma_read(CSAC(lch));
        if (cpu_class_is_omap1())
-                offset |= (dma_read(CSSA_U(lch)) << 16);
+                offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
        return offset;
 }
@@ -1153,19 +1054,19 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
        dma_addr_t offset = 0;
        if (cpu_is_omap15xx())
-                offset = dma_read(CPC(lch));
+                offset = p->dma_read(CPC, lch);
        else
-                offset = dma_read(CDAC(lch));
+                offset = p->dma_read(CDAC, lch);
        /*
         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
         * read before the DMA controller finished disabling the channel.
         */
        if (!cpu_is_omap15xx() && offset == 0)
-                offset = dma_read(CDAC(lch));
+                offset = p->dma_read(CDAC, lch);
        if (cpu_class_is_omap1())
-                offset |= (dma_read(CDSA_U(lch)) << 16);
+                offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
        return offset;
 }
@@ -1173,7 +1074,7 @@ EXPORT_SYMBOL(omap_get_dma_dst_pos);
 int omap_get_dma_active_status(int lch)
 {
-        return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
+        return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
 }
 EXPORT_SYMBOL(omap_get_dma_active_status);
@@ -1186,7 +1087,7 @@ int omap_dma_running(void)
                        return 1;
        for (lch = 0; lch < dma_chan_count; lch++)
-                if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
+                if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
                        return 1;
        return 0;
@@ -1201,8 +1102,8 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
 {
        if (omap_dma_in_1510_mode()) {
                if (lch_head == lch_queue) {
-                        dma_write(dma_read(CCR(lch_head)) | (3 << 8),
+                        p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
-                                                                CCR(lch_head));
+                                                                CCR, lch_head);
                        return;
                }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -1228,8 +1129,8 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 {
        if (omap_dma_in_1510_mode()) {
                if (lch_head == lch_queue) {
-                        dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
+                        p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
-                                                                CCR(lch_head));
+                                                                CCR, lch_head);
                        return;
                }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -1255,8 +1156,6 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 }
 EXPORT_SYMBOL(omap_dma_unlink_lch);
-/*----------------------------------------------------------------------------*/
 #ifndef CONFIG_ARCH_OMAP1
 /* Create chain of DMA channesls */
 static void create_dma_lch_chain(int lch_head, int lch_queue)
@@ -1281,15 +1180,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
                                        lch_queue;
        }
-        l = dma_read(CLNK_CTRL(lch_head));
+        l = p->dma_read(CLNK_CTRL, lch_head);
        l &= ~(0x1f);
        l |= lch_queue;
-        dma_write(l, CLNK_CTRL(lch_head));
+        p->dma_write(l, CLNK_CTRL, lch_head);
-        l = dma_read(CLNK_CTRL(lch_queue));
+        l = p->dma_read(CLNK_CTRL, lch_queue);
        l &= ~(0x1f);
        l |= (dma_chan[lch_queue].next_linked_ch);
-        dma_write(l, CLNK_CTRL(lch_queue));
+        p->dma_write(l, CLNK_CTRL, lch_queue);
 }
 /**
@@ -1565,13 +1464,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
        /* Set the params to the free channel */
        if (src_start != 0)
-                dma_write(src_start, CSSA(lch));
+                p->dma_write(src_start, CSSA, lch);
        if (dest_start != 0)
-                dma_write(dest_start, CDSA(lch));
+                p->dma_write(dest_start, CDSA, lch);
        /* Write the buffer size */
-        dma_write(elem_count, CEN(lch));
+        p->dma_write(elem_count, CEN, lch);
-        dma_write(frame_count, CFN(lch));
+        p->dma_write(frame_count, CFN, lch);
        /*
         * If the chain is dynamically linked,
@@ -1604,8 +1503,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                enable_lnk(dma_chan[lch].prev_linked_ch);
                                dma_chan[lch].state = DMA_CH_QUEUED;
                                start_dma = 0;
-                                if (0 == ((1 << 7) & dma_read(
+                                if (0 == ((1 << 7) & p->dma_read(
-                                        CCR(dma_chan[lch].prev_linked_ch)))) {
+                                        CCR, dma_chan[lch].prev_linked_ch))) {
                                        disable_lnk(dma_chan[lch].
                                                    prev_linked_ch);
                                        pr_debug("\n prev ch is stopped\n");
@@ -1621,7 +1520,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                        }
                        omap_enable_channel_irq(lch);
-                        l = dma_read(CCR(lch));
+                        l = p->dma_read(CCR, lch);
                        if ((0 == (l & (1 << 24))))
                                l &= ~(1 << 25);
@@ -1632,12 +1531,12 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                        l |= (1 << 7);
                                        dma_chan[lch].state = DMA_CH_STARTED;
                                        pr_debug("starting %d\n", lch);
-                                        dma_write(l, CCR(lch));
+                                        p->dma_write(l, CCR, lch);
                                } else
                                        start_dma = 0;
                        } else {
                                if (0 == (l & (1 << 7)))
-                                        dma_write(l, CCR(lch));
+                                        p->dma_write(l, CCR, lch);
                        }
                        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
                }
@@ -1682,7 +1581,7 @@ int omap_start_dma_chain_transfers(int chain_id)
                omap_enable_channel_irq(channels[0]);
        }
-        l = dma_read(CCR(channels[0]));
+        l = p->dma_read(CCR, channels[0]);
        l |= (1 << 7);
        dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
        dma_chan[channels[0]].state = DMA_CH_STARTED;
@@ -1691,7 +1590,7 @@ int omap_start_dma_chain_transfers(int chain_id)
                l &= ~(1 << 25);
        else
                l |= (1 << 25);
-        dma_write(l, CCR(channels[0]));
+        p->dma_write(l, CCR, channels[0]);
        dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
@@ -1711,7 +1610,7 @@ int omap_stop_dma_chain_transfers(int chain_id)
 {
        int *channels;
        u32 l, i;
-        u32 sys_cf;
+        u32 sys_cf = 0;
        /* Check for input params */
        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
@@ -1726,22 +1625,20 @@ int omap_stop_dma_chain_transfers(int chain_id)
        }
        channels = dma_linked_lch[chain_id].linked_dmach_q;
-        /*
+        if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
-         * DMA Errata:
+                sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
-         * Special programming model needed to disable DMA before end of block
+                l = sys_cf;
-         */
+                /* Middle mode reg set no Standby */
-        sys_cf = dma_read(OCP_SYSCONFIG);
+                l &= ~((1 << 12)|(1 << 13));
-        l = sys_cf;
+                p->dma_write(l, OCP_SYSCONFIG, 0);
-        /* Middle mode reg set no Standby */
+        }
-        l &= ~((1 << 12)|(1 << 13));
-        dma_write(l, OCP_SYSCONFIG);
        for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
                /* Stop the Channel transmission */
-                l = dma_read(CCR(channels[i]));
+                l = p->dma_read(CCR, channels[i]);
                l &= ~(1 << 7);
-                dma_write(l, CCR(channels[i]));
+                p->dma_write(l, CCR, channels[i]);
                /* Disable the link in all the channels */
                disable_lnk(channels[i]);
@@ -1753,8 +1650,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
        /* Reset the Queue pointers */
        OMAP_DMA_CHAIN_QINIT(chain_id);
-        /* Errata - put in the old value */
+        if (IS_DMA_ERRATA(DMA_ERRATA_i88))
-        dma_write(sys_cf, OCP_SYSCONFIG);
+                p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
        return 0;
 }
@@ -1796,8 +1693,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
        /* Get the current channel */
        lch = channels[dma_linked_lch[chain_id].q_head];
-        *ei = dma_read(CCEN(lch));
+        *ei = p->dma_read(CCEN, lch);
-        *fi = dma_read(CCFN(lch));
+        *fi = p->dma_read(CCFN, lch);
        return 0;
 }
@@ -1834,7 +1731,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
        /* Get the current channel */
        lch = channels[dma_linked_lch[chain_id].q_head];
-        return dma_read(CDAC(lch));
+        return p->dma_read(CDAC, lch);
 }
 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
@@ -1868,7 +1765,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
        /* Get the current channel */
        lch = channels[dma_linked_lch[chain_id].q_head];
-        return dma_read(CSAC(lch));
+        return p->dma_read(CSAC, lch);
 }
 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
@@ -1885,7 +1782,7 @@ static int omap1_dma_handle_ch(int ch)
                csr = dma_chan[ch].saved_csr;
                dma_chan[ch].saved_csr = 0;
        } else
-                csr = dma_read(CSR(ch));
+                csr = p->dma_read(CSR, ch);
        if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
                dma_chan[ch + 6].saved_csr = csr >> 7;
                csr &= 0x7f;
@@ -1938,13 +1835,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 static int omap2_dma_handle_ch(int ch)
 {
-        u32 status = dma_read(CSR(ch));
+        u32 status = p->dma_read(CSR, ch);
        if (!status) {
                if (printk_ratelimit())
                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
                                ch);
-                dma_write(1 << ch, IRQSTATUS_L0);
+                p->dma_write(1 << ch, IRQSTATUS_L0, ch);
                return 0;
        }
        if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1960,17 +1857,12 @@ static int omap2_dma_handle_ch(int ch)
        if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
                printk(KERN_INFO "DMA transaction error with device %d\n",
                       dma_chan[ch].dev_id);
-                if (cpu_class_is_omap2()) {
+                if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
-                        /*
-                         * Errata: sDMA Channel is not disabled
-                         * after a transaction error. So we explicitely
-                         * disable the channel
-                         */
                        u32 ccr;
-                        ccr = dma_read(CCR(ch));
+                        ccr = p->dma_read(CCR, ch);
                        ccr &= ~OMAP_DMA_CCR_EN;
-                        dma_write(ccr, CCR(ch));
+                        p->dma_write(ccr, CCR, ch);
                        dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
                }
        }
@@ -1981,16 +1873,16 @@ static int omap2_dma_handle_ch(int ch)
                printk(KERN_INFO "DMA misaligned error with device %d\n",
                       dma_chan[ch].dev_id);
-        dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
+        p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch);
-        dma_write(1 << ch, IRQSTATUS_L0);
+        p->dma_write(1 << ch, IRQSTATUS_L0, ch);
        /* read back the register to flush the write */
-        dma_read(IRQSTATUS_L0);
+        p->dma_read(IRQSTATUS_L0, ch);
        /* If the ch is not chained then chain_id will be -1 */
        if (dma_chan[ch].chain_id != -1) {
                int chain_id = dma_chan[ch].chain_id;
                dma_chan[ch].state = DMA_CH_NOTSTARTED;
-                if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
+                if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
                        dma_chan[dma_chan[ch].next_linked_ch].state =
                                                        DMA_CH_STARTED;
                if (dma_linked_lch[chain_id].chain_mode ==
@@ -2000,10 +1892,10 @@ static int omap2_dma_handle_ch(int ch)
                if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
                        OMAP_DMA_CHAIN_INCQHEAD(chain_id);
-                status = dma_read(CSR(ch));
+                status = p->dma_read(CSR, ch);
        }
-        dma_write(status, CSR(ch));
+        p->dma_write(status, CSR, ch);
        if (likely(dma_chan[ch].callback != NULL))
                dma_chan[ch].callback(ch, status, dma_chan[ch].data);
@@ -2017,13 +1909,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
        u32 val, enable_reg;
        int i;
-        val = dma_read(IRQSTATUS_L0);
+        val = p->dma_read(IRQSTATUS_L0, 0);
        if (val == 0) {
                if (printk_ratelimit())
                        printk(KERN_WARNING "Spurious DMA IRQ\n");
                return IRQ_HANDLED;
        }
-        enable_reg = dma_read(IRQENABLE_L0);
+        enable_reg = p->dma_read(IRQENABLE_L0, 0);
        val &= enable_reg; /* Dispatch only relevant interrupts */
        for (i = 0; i < dma_lch_count && val != 0; i++) {
                if (val & 1)
@@ -2049,119 +1941,66 @@ static struct irqaction omap24xx_dma_irq;
 void omap_dma_global_context_save(void)
 {
        omap_dma_global_context.dma_irqenable_l0 =
-                dma_read(IRQENABLE_L0);
+                p->dma_read(IRQENABLE_L0, 0);
        omap_dma_global_context.dma_ocp_sysconfig =
-                dma_read(OCP_SYSCONFIG);
+                p->dma_read(OCP_SYSCONFIG, 0);
-        omap_dma_global_context.dma_gcr = dma_read(GCR);
+        omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
 }
 void omap_dma_global_context_restore(void)
 {
        int ch;
-        dma_write(omap_dma_global_context.dma_gcr, GCR);
+        p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
-        dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+        p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
-                OCP_SYSCONFIG);
+                OCP_SYSCONFIG, 0);
-        dma_write(omap_dma_global_context.dma_irqenable_l0,
+        p->dma_write(omap_dma_global_context.dma_irqenable_l0,
-                IRQENABLE_L0);
+                IRQENABLE_L0, 0);
-        /*
+        if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
-         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+                p->dma_write(0x3 , IRQSTATUS_L0, 0);
-         * after secure sram context save and restore. Hence we need to
-         * manually clear those IRQs to avoid spurious interrupts. This
-         * affects only secure devices.
-         */
-        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
-                dma_write(0x3 , IRQSTATUS_L0);
        for (ch = 0; ch < dma_chan_count; ch++)
                if (dma_chan[ch].dev_id != -1)
                        omap_clear_dma(ch);
 }
-/*----------------------------------------------------------------------------*/
+static int __devinit omap_system_dma_probe(struct platform_device *pdev)
-static int __init omap_init_dma(void)
 {
-        unsigned long base;
+        int ch, ret = 0;
-        int ch, r;
+        int dma_irq;
+        char irq_name[4];
-        if (cpu_class_is_omap1()) {
+        int irq_rel;
-                base = OMAP1_DMA_BASE;
-                dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
+        p = pdev->dev.platform_data;
-        } else if (cpu_is_omap24xx()) {
+        if (!p) {
-                base = OMAP24XX_DMA4_BASE;
+                dev_err(&pdev->dev, "%s: System DMA initialized without"
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+                        "platform data\n", __func__);
-        } else if (cpu_is_omap34xx()) {
+                return -EINVAL;
-                base = OMAP34XX_DMA4_BASE;
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
-        } else if (cpu_is_omap44xx()) {
-                base = OMAP44XX_DMA4_BASE;
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
-        } else {
-                pr_err("DMA init failed for unsupported omap\n");
-                return -ENODEV;
        }
-        omap_dma_base = ioremap(base, SZ_4K);
+        d                       = p->dma_attr;
-        BUG_ON(!omap_dma_base);
+        errata                  = p->errata;
-        if (cpu_class_is_omap2() && omap_dma_reserve_channels
+        if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
                        && (omap_dma_reserve_channels <= dma_lch_count))
-                dma_lch_count = omap_dma_reserve_channels;
+                d->lch_count    = omap_dma_reserve_channels;
-        dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
+        dma_lch_count           = d->lch_count;
-                                GFP_KERNEL);
+        dma_chan_count          = dma_lch_count;
-        if (!dma_chan) {
+        dma_chan                = d->chan;
-                r = -ENOMEM;
+        enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
-                goto out_unmap;
-        }
        if (cpu_class_is_omap2()) {
                dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                dma_lch_count, GFP_KERNEL);
                if (!dma_linked_lch) {
-                        r = -ENOMEM;
+                        ret = -ENOMEM;
-                        goto out_free;
+                        goto exit_dma_lch_fail;
                }
        }
-        if (cpu_is_omap15xx()) {
-                printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
-                dma_chan_count = 9;
-                enable_1510_mode = 1;
-        } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
-                printk(KERN_INFO "OMAP DMA hardware version %d\n",
-                       dma_read(HW_ID));
-                printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
-                       (dma_read(CAPS_0_U) << 16) |
-                       dma_read(CAPS_0_L),
-                       (dma_read(CAPS_1_U) << 16) |
-                       dma_read(CAPS_1_L),
-                       dma_read(CAPS_2), dma_read(CAPS_3),
-                       dma_read(CAPS_4));
-                if (!enable_1510_mode) {
-                        u16 w;
-                        /* Disable OMAP 3.0/3.1 compatibility mode. */
-                        w = dma_read(GSCR);
-                        w |= 1 << 3;
-                        dma_write(w, GSCR);
-                        dma_chan_count = 16;
-                } else
-                        dma_chan_count = 9;
-        } else if (cpu_class_is_omap2()) {
-                u8 revision = dma_read(REVISION) & 0xff;
-                printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
-                       revision >> 4, revision & 0xf);
-                dma_chan_count = dma_lch_count;
-        } else {
-                dma_chan_count = 0;
-                return 0;
-        }
        spin_lock_init(&dma_chan_lock);
        for (ch = 0; ch < dma_chan_count; ch++) {
                omap_clear_dma(ch);
                if (cpu_class_is_omap2())
@@ -2178,20 +2017,23 @@ static int __init omap_init_dma(void)
                         * request_irq() doesn't like dev_id (ie. ch) being
                         * zero, so we have to kludge around this.
                         */
-                        r = request_irq(omap1_dma_irq[ch],
+                        sprintf(&irq_name[0], "%d", ch);
+                        dma_irq = platform_get_irq_byname(pdev, irq_name);
+                        if (dma_irq < 0) {
+                                ret = dma_irq;
+                                goto exit_dma_irq_fail;
+                        }
+                        /* INT_DMA_LCD is handled in lcd_dma.c */
+                        if (dma_irq == INT_DMA_LCD)
+                                continue;
+                        ret = request_irq(dma_irq,
                                        omap1_dma_irq_handler, 0, "DMA",
                                        (void *) (ch + 1));
-                        if (r != 0) {
+                        if (ret != 0)
-                                int i;
+                                goto exit_dma_irq_fail;
-                                printk(KERN_ERR "unable to request IRQ %d "
-                                       "for DMA (error %d)\n",
-                                       omap1_dma_irq[ch], r);
-                                for (i = 0; i < ch; i++)
-                                        free_irq(omap1_dma_irq[i],
-                                                 (void *) (i + 1));
-                                goto out_free;
-                        }
                }
        }
@@ -2200,46 +2042,91 @@ static int __init omap_init_dma(void)
                                DMA_DEFAULT_FIFO_DEPTH, 0);
        if (cpu_class_is_omap2()) {
-                int irq;
+                strcpy(irq_name, "0");
-                if (cpu_is_omap44xx())
+                dma_irq = platform_get_irq_byname(pdev, irq_name);
-                        irq = OMAP44XX_IRQ_SDMA_0;
+                if (dma_irq < 0) {
-                else
+                        dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
-                        irq = INT_24XX_SDMA_IRQ0;
+                        goto exit_dma_lch_fail;
-                setup_irq(irq, &omap24xx_dma_irq);
+                }
-        }
+                ret = setup_irq(dma_irq, &omap24xx_dma_irq);
+                if (ret) {
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                        dev_err(&pdev->dev, "set_up failed for IRQ %d"
-                /* Enable smartidle idlemodes and autoidle */
+                                "for DMA (error %d)\n", dma_irq, ret);
-                u32 v = dma_read(OCP_SYSCONFIG);
+                        goto exit_dma_lch_fail;
-                v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
-                                DMA_SYSCONFIG_SIDLEMODE_MASK |
-                                DMA_SYSCONFIG_AUTOIDLE);
-                v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
-                        DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
-                        DMA_SYSCONFIG_AUTOIDLE);
-                dma_write(v , OCP_SYSCONFIG);
-                /* reserve dma channels 0 and 1 in high security devices */
-                if (cpu_is_omap34xx() &&
-                        (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
-                        printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
-                                        "HS ROM code\n");
-                        dma_chan[0].dev_id = 0;
-                        dma_chan[1].dev_id = 1;
                }
        }
+        /* reserve dma channels 0 and 1 in high security devices */
+        if (cpu_is_omap34xx() &&
+                (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+                printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+                                "HS ROM code\n");
+                dma_chan[0].dev_id = 0;
+                dma_chan[1].dev_id = 1;
+        }
+        p->show_dma_caps();
        return 0;
-out_free:
+exit_dma_irq_fail:
+        dev_err(&pdev->dev, "unable to request IRQ %d"
+                        "for DMA (error %d)\n", dma_irq, ret);
+        for (irq_rel = 0; irq_rel < ch; irq_rel++) {
+                dma_irq = platform_get_irq(pdev, irq_rel);
+                free_irq(dma_irq, (void *)(irq_rel + 1));
+        }
+exit_dma_lch_fail:
+        kfree(p);
+        kfree(d);
        kfree(dma_chan);
+        return ret;
+}
-out_unmap:
+static int __devexit omap_system_dma_remove(struct platform_device *pdev)
-        iounmap(omap_dma_base);
+{
+        int dma_irq;
-        return r;
+        if (cpu_class_is_omap2()) {
+                char irq_name[4];
+                strcpy(irq_name, "0");
+                dma_irq = platform_get_irq_byname(pdev, irq_name);
+                remove_irq(dma_irq, &omap24xx_dma_irq);
+        } else {
+                int irq_rel = 0;
+                for ( ; irq_rel < dma_chan_count; irq_rel++) {
+                        dma_irq = platform_get_irq(pdev, irq_rel);
+                        free_irq(dma_irq, (void *)(irq_rel + 1));
+                }
+        }
+        kfree(p);
+        kfree(d);
+        kfree(dma_chan);
+        return 0;
+}
+static struct platform_driver omap_system_dma_driver = {
+        .probe          = omap_system_dma_probe,
+        .remove         = omap_system_dma_remove,
+        .driver         = {
+                .name   = "omap_dma_system"
+        },
+};
+static int __init omap_system_dma_init(void)
+{
+        return platform_driver_register(&omap_system_dma_driver);
+}
+arch_initcall(omap_system_dma_init);
+static void __exit omap_system_dma_exit(void)
+{
+        platform_driver_unregister(&omap_system_dma_driver);
 }
-arch_initcall(omap_init_dma);
+MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
 /*
 * Reserve the omap SDMA channels using cmdline bootarg
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 0cce4ca83aa0..d1c916fcf770 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -21,141 +21,15 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
-/* Move omap4 specific defines to dma-44xx.h */
+#include <linux/platform_device.h>
-#include "dma-44xx.h"
-/* Hardware registers for omap1 */
+/*
-#define OMAP1_DMA_BASE                  (0xfffed800)
+ * TODO: These dma channel defines should go away once all
+ * the omap drivers hwmod adapted.
-#define OMAP1_DMA_GCR                   0x400
+ */
-#define OMAP1_DMA_GSCR                  0x404
-#define OMAP1_DMA_GRST                  0x408
-#define OMAP1_DMA_HW_ID                 0x442
-#define OMAP1_DMA_PCH2_ID               0x444
-#define OMAP1_DMA_PCH0_ID               0x446
-#define OMAP1_DMA_PCH1_ID               0x448
-#define OMAP1_DMA_PCHG_ID               0x44a
-#define OMAP1_DMA_PCHD_ID               0x44c
-#define OMAP1_DMA_CAPS_0_U              0x44e
-#define OMAP1_DMA_CAPS_0_L              0x450
-#define OMAP1_DMA_CAPS_1_U              0x452
-#define OMAP1_DMA_CAPS_1_L              0x454
-#define OMAP1_DMA_CAPS_2                0x456
-#define OMAP1_DMA_CAPS_3                0x458
-#define OMAP1_DMA_CAPS_4                0x45a
-#define OMAP1_DMA_PCH2_SR               0x460
-#define OMAP1_DMA_PCH0_SR               0x480
-#define OMAP1_DMA_PCH1_SR               0x482
-#define OMAP1_DMA_PCHD_SR               0x4c0
-/* Hardware registers for omap2 and omap3 */
-#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
-#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
-#define OMAP44XX_DMA4_BASE              (L4_44XX_BASE + 0x56000)
-#define OMAP_DMA4_REVISION              0x00
-#define OMAP_DMA4_GCR                   0x78
-#define OMAP_DMA4_IRQSTATUS_L0          0x08
-#define OMAP_DMA4_IRQSTATUS_L1          0x0c
-#define OMAP_DMA4_IRQSTATUS_L2          0x10
-#define OMAP_DMA4_IRQSTATUS_L3          0x14
-#define OMAP_DMA4_IRQENABLE_L0          0x18
-#define OMAP_DMA4_IRQENABLE_L1          0x1c
-#define OMAP_DMA4_IRQENABLE_L2          0x20
-#define OMAP_DMA4_IRQENABLE_L3          0x24
-#define OMAP_DMA4_SYSSTATUS             0x28
-#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
-#define OMAP_DMA4_CAPS_0                0x64
-#define OMAP_DMA4_CAPS_2                0x6c
-#define OMAP_DMA4_CAPS_3                0x70
-#define OMAP_DMA4_CAPS_4                0x74
-#define OMAP1_LOGICAL_DMA_CH_COUNT      17
-#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
-/* Common channel specific registers for omap1 */
-#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
-#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
-#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
-#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
-#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
-#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
-#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
-#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
-#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
-#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
-#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
-#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
-#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
-/* Common channel specific registers for omap2 */
-#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
-#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
-#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
-#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
-#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
-#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
-#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
-#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
-#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
-#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
-#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
-#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
-/* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
-#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
-#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
-#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
-#define OMAP1_DMA_CCEN(n)               0
-#define OMAP1_DMA_CCFN(n)               0
-/* Channel specific registers only on omap2 */
-#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
-#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
-#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
-#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
-#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
-/* Additional registers available on OMAP4 */
-#define OMAP_DMA4_CDP(n)                (0x60 * (n) + 0xd0)
-#define OMAP_DMA4_CNDP(n)               (0x60 * (n) + 0xd4)
-#define OMAP_DMA4_CCDN(n)               (0x60 * (n) + 0xd8)
-/* Dummy defines to keep multi-omap compiles happy */
-#define OMAP1_DMA_REVISION              0
-#define OMAP1_DMA_IRQSTATUS_L0          0
-#define OMAP1_DMA_IRQENABLE_L0          0
-#define OMAP1_DMA_OCP_SYSCONFIG         0
-#define OMAP_DMA4_HW_ID                 0
-#define OMAP_DMA4_CAPS_0_L              0
-#define OMAP_DMA4_CAPS_0_U              0
-#define OMAP_DMA4_CAPS_1_L              0
-#define OMAP_DMA4_CAPS_1_U              0
-#define OMAP_DMA4_GSCR                  0
-#define OMAP_DMA4_CPC(n)                0
-#define OMAP_DMA4_LCH_CTRL(n)           0
-#define OMAP_DMA4_COLOR_L(n)            0
-#define OMAP_DMA4_COLOR_U(n)            0
-#define OMAP_DMA4_CCR2(n)               0
-#define OMAP1_DMA_CSSA(n)               0
-#define OMAP1_DMA_CDSA(n)               0
-#define OMAP_DMA4_CSSA_L(n)             0
-#define OMAP_DMA4_CSSA_U(n)             0
-#define OMAP_DMA4_CDSA_L(n)             0
-#define OMAP_DMA4_CDSA_U(n)             0
-#define OMAP1_DMA_COLOR(n)              0
-/*----------------------------------------------------------------------------*/
+/* Move omap4 specific defines to dma-44xx.h */
+#include "dma-44xx.h"
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
@@ -405,6 +279,63 @@
 #define DMA_CH_PRIO_HIGH                0x1
 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
+/* Errata handling */
+#define IS_DMA_ERRATA(id)               (errata & (id))
+#define SET_DMA_ERRATA(id)              (errata |= (id))
+#define DMA_ERRATA_IFRAME_BUFFERING     BIT(0x0)
+#define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
+#define DMA_ERRATA_i378                 BIT(0x2)
+#define DMA_ERRATA_i541                 BIT(0x3)
+#define DMA_ERRATA_i88                  BIT(0x4)
+#define DMA_ERRATA_3_3                  BIT(0x5)
+#define DMA_ROMCODE_BUG                 BIT(0x6)
+/* Attributes for OMAP DMA Contrller */
+#define DMA_LINKED_LCH                  BIT(0x0)
+#define GLOBAL_PRIORITY                 BIT(0x1)
+#define RESERVE_CHANNEL                 BIT(0x2)
+#define IS_CSSA_32                      BIT(0x3)
+#define IS_CDSA_32                      BIT(0x4)
+#define IS_RW_PRIORITY                  BIT(0x5)
+#define ENABLE_1510_MODE                BIT(0x6)
+#define SRC_PORT                        BIT(0x7)
+#define DST_PORT                        BIT(0x8)
+#define SRC_INDEX                       BIT(0x9)
+#define DST_INDEX                       BIT(0xA)
+#define IS_BURST_ONLY4                  BIT(0xB)
+#define CLEAR_CSR_ON_READ               BIT(0xC)
+#define IS_WORD_16                      BIT(0xD)
+enum omap_reg_offsets {
+GCR,            GSCR,           GRST1,          HW_ID,
+PCH2_ID,        PCH0_ID,        PCH1_ID,        PCHG_ID,
+PCHD_ID,        CAPS_0,         CAPS_1,         CAPS_2,
+CAPS_3,         CAPS_4,         PCH2_SR,        PCH0_SR,
+PCH1_SR,        PCHD_SR,        REVISION,       IRQSTATUS_L0,
+IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
+IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
+OCP_SYSCONFIG,
+/* omap1+ specific */
+CPC, CCR2, LCH_CTRL,
+/* Common registers for all omap's */
+CSDP,           CCR,            CICR,           CSR,
+CEN,            CFN,            CSFI,           CSEI,
+CSAC,           CDAC,           CDEI,
+CDFI,           CLNK_CTRL,
+/* Channel specific registers */
+CSSA,           CDSA,           COLOR,
+CCEN,           CCFN,
+/* omap3630 and omap4 specific */
+CDP,            CNDP,           CCDN,
+};
 enum omap_dma_burst_mode {
        OMAP_DMA_DATA_BURST_DIS = 0,
        OMAP_DMA_DATA_BURST_4,
@@ -470,6 +401,41 @@ struct omap_dma_channel_params {
 #endif
 };
+struct omap_dma_lch {
+        int next_lch;
+        int dev_id;
+        u16 saved_csr;
+        u16 enabled_irqs;
+        const char *dev_name;
+        void (*callback)(int lch, u16 ch_status, void *data);
+        void *data;
+        long flags;
+        /* required for Dynamic chaining */
+        int prev_linked_ch;
+        int next_linked_ch;
+        int state;
+        int chain_id;
+        int status;
+};
+struct omap_dma_dev_attr {
+        u32 dev_caps;
+        u16 lch_count;
+        u16 chan_count;
+        struct omap_dma_lch *chan;
+};
+/* System DMA platform data structure */
+struct omap_system_dma_plat_info {
+        struct omap_dma_dev_attr *dma_attr;
+        u32 errata;
+        void (*disable_irq_lch)(int lch);
+        void (*show_dma_caps)(void);
+        void (*clear_lch_regs)(int lch);
+        void (*clear_dma)(int lch);
+        void (*dma_write)(u32 val, int reg, int lch);
+        u32 (*dma_read)(int reg, int lch);
+};
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 3ae52ccc793c..793ce9d53294 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -10,16 +10,18 @@
 #ifndef ASMARM_ARCH_KEYPAD_H
 #define ASMARM_ARCH_KEYPAD_H
-#warning: Please update the board to use matrix_keypad.h instead
+#ifndef CONFIG_ARCH_OMAP1
+#warning Please update the board to use matrix-keypad driver
+#endif
+#include <linux/input/matrix_keypad.h>
 struct omap_kp_platform_data {
        int rows;
        int cols;
-        int *keymap;
+        const struct matrix_keymap_data *keymap_data;
-        unsigned int keymapsize;
+        bool rep;
-        unsigned int rep:1;
        unsigned long delay;
-        unsigned int dbounce:1;
+        bool dbounce;
        /* specific to OMAP242x*/
        unsigned int *row_gpios;
        unsigned int *col_gpios;
@@ -28,18 +30,21 @@ struct omap_kp_platform_data {
 /* Group (0..3) -- when multiple keys are pressed, only the
 * keys pressed in the same group are considered as pressed. This is
 * in order to workaround certain crappy HW designs that produce ghost
- * keypresses. */
+ * keypresses. Two free bits, not used by neither row/col nor keynum,
-#define GROUP_0         (0 << 16)
+ * must be available for use as group bits. The below GROUP_SHIFT
-#define GROUP_1         (1 << 16)
+ * macro definition is based on some prior knowledge of the
-#define GROUP_2         (2 << 16)
+ * matrix_keypad defined KEY() macro internals.
-#define GROUP_3         (3 << 16)
+ */
+#define GROUP_SHIFT     14
+#define GROUP_0         (0 << GROUP_SHIFT)
+#define GROUP_1         (1 << GROUP_SHIFT)
+#define GROUP_2         (2 << GROUP_SHIFT)
+#define GROUP_3         (3 << GROUP_SHIFT)
 #define GROUP_MASK      GROUP_3
+#if KEY_MAX & GROUP_MASK
+#error Group bits in conflict with keynum bits
+#endif
-#define KEY_PERSISTENT          0x00800000
-#define KEYNUM_MASK             0x00EFFFFF
-#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
-#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
-                                                KEY_PERSISTENT)
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 728fbb9dd549..62c3fe918ab2 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -17,27 +17,10 @@
 #include <linux/device.h>
 #include <linux/cpufreq.h>
 #include <linux/clk.h>
+#include <linux/opp.h>
 #include "powerdomain.h"
-/**
- * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
- * @rate: target clock rate
- * @opp_id: OPP ID
- * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
- *
- * Operating performance point data.  Can vary by OMAP chip and board.
- */
-struct omap_opp {
-        unsigned long rate;
-        u8 opp_id;
-        u16 min_vdd;
-};
-extern struct omap_opp *mpu_opps;
-extern struct omap_opp *dsp_opps;
-extern struct omap_opp *l3_opps;
 /*
 * agent_id values for use with omap_pm_set_min_bus_tput():
 *
@@ -59,9 +42,11 @@ extern struct omap_opp *l3_opps;
 * framework starts.  The "_if_" is to avoid name collisions with the
 * PM idle-loop code.
 */
-int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
+#ifdef CONFIG_OMAP_PM_NONE
-                                 struct omap_opp *dsp_opp_table,
+#define omap_pm_if_early_init() 0
-                                 struct omap_opp *l3_opp_table);
+#else
+int __init omap_pm_if_early_init(void);
+#endif
 /**
 * omap_pm_if_init - OMAP PM init code called after clock fw init
@@ -69,7 +54,11 @@ int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
 * The main initialization code.  OPP tables are passed in here.  The
 * "_if_" is to avoid name collisions with the PM idle-loop code.
 */
+#ifdef CONFIG_OMAP_PM_NONE
+#define omap_pm_if_init() 0
+#else
 int __init omap_pm_if_init(void);
+#endif
 /**
 * omap_pm_if_exit - OMAP PM exit code
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 5905100b29a1..9967d5e855c7 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,6 +11,7 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
+#ifndef __ASSEMBLY__
 extern void * omap_sram_push(void * start, unsigned long size);
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
@@ -74,4 +75,14 @@ extern void omap_push_sram_idle(void);
 static inline void omap_push_sram_idle(void) {}
 #endif /* CONFIG_PM */
+#endif /* __ASSEMBLY__ */
+/*
+ * OMAP2+: define the SRAM PA addresses.
+ * Used by the SRAM management code and the idle sleep code.
+ */
+#define OMAP2_SRAM_PA           0x40200000
+#define OMAP3_SRAM_PA           0x40200000
+#define OMAP4_SRAM_PA           0x40300000
 #endif
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 7bbc0740cb46..ad98b85cae21 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -146,6 +146,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                DEBUG_LL_OMAP3(3, cm_t35);
                DEBUG_LL_OMAP3(3, cm_t3517);
                DEBUG_LL_OMAP3(3, craneboard);
+                DEBUG_LL_OMAP3(3, devkit8000);
                DEBUG_LL_OMAP3(3, igep0020);
                DEBUG_LL_OMAP3(3, igep0030);
                DEBUG_LL_OMAP3(3, nokia_rm680);
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index e129ce80c53b..ca75abb18068 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -26,10 +26,6 @@
 #include <plat/powerdomain.h>
-struct omap_opp *dsp_opps;
-struct omap_opp *mpu_opps;
-struct omap_opp *l3_opps;
 /*
 * Device-driver-originated constraints (via board-*.c files)
 */
@@ -308,13 +304,8 @@ int omap_pm_get_dev_context_loss_count(struct device *dev)
 /* Should be called before clk framework init */
-int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
+int __init omap_pm_if_early_init(void)
-                                 struct omap_opp *dsp_opp_table,
-                                 struct omap_opp *l3_opp_table)
 {
-        mpu_opps = mpu_opp_table;
-        dsp_opps = dsp_opp_table;
-        l3_opps = l3_opp_table;
        return 0;
 }
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 819ea0cfb81a..1a686c89d8dd 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -41,15 +41,12 @@
 #define OMAP1_SRAM_PA           0x20000000
 #define OMAP1_SRAM_VA           VMALLOC_END
-#define OMAP2_SRAM_PA           0x40200000
+#define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
-#define OMAP2_SRAM_PUB_PA       0x4020f800
 #define OMAP2_SRAM_VA           0xfe400000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
-#define OMAP3_SRAM_PA           0x40200000
 #define OMAP3_SRAM_VA           0xfe400000
-#define OMAP3_SRAM_PUB_PA       0x40208000
+#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_PA           0x40300000
 #define OMAP4_SRAM_VA           0xfe400000
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 5a27b1b538f2..eb105e61c746 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C24XX
        default y
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
-        select S3C_DEVICE_NAND
+        select S3C_DEV_NAND
        select S3C_GPIO_CFG_S3C24XX
        help
          Base platform code for any Samsung S3C24XX device