diff options
Diffstat (limited to 'arch/arm')
99 files changed, 835 insertions, 1404 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c1795c952bfe..476074fdb402 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -682,6 +682,7 @@ config ARCH_S3C2410 | |||
682 | select GENERIC_GPIO | 682 | select GENERIC_GPIO |
683 | select ARCH_HAS_CPUFREQ | 683 | select ARCH_HAS_CPUFREQ |
684 | select HAVE_CLK | 684 | select HAVE_CLK |
685 | select CLKDEV_LOOKUP | ||
685 | select ARCH_USES_GETTIMEOFFSET | 686 | select ARCH_USES_GETTIMEOFFSET |
686 | select HAVE_S3C2410_I2C if I2C | 687 | select HAVE_S3C2410_I2C if I2C |
687 | help | 688 | help |
@@ -699,6 +700,7 @@ config ARCH_S3C64XX | |||
699 | select CPU_V6 | 700 | select CPU_V6 |
700 | select ARM_VIC | 701 | select ARM_VIC |
701 | select HAVE_CLK | 702 | select HAVE_CLK |
703 | select CLKDEV_LOOKUP | ||
702 | select NO_IOPORT | 704 | select NO_IOPORT |
703 | select ARCH_USES_GETTIMEOFFSET | 705 | select ARCH_USES_GETTIMEOFFSET |
704 | select ARCH_HAS_CPUFREQ | 706 | select ARCH_HAS_CPUFREQ |
@@ -723,6 +725,8 @@ config ARCH_S5P64X0 | |||
723 | select CPU_V6 | 725 | select CPU_V6 |
724 | select GENERIC_GPIO | 726 | select GENERIC_GPIO |
725 | select HAVE_CLK | 727 | select HAVE_CLK |
728 | select CLKDEV_LOOKUP | ||
729 | select CLKSRC_MMIO | ||
726 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | 730 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
727 | select GENERIC_CLOCKEVENTS | 731 | select GENERIC_CLOCKEVENTS |
728 | select HAVE_SCHED_CLOCK | 732 | select HAVE_SCHED_CLOCK |
@@ -736,6 +740,7 @@ config ARCH_S5PC100 | |||
736 | bool "Samsung S5PC100" | 740 | bool "Samsung S5PC100" |
737 | select GENERIC_GPIO | 741 | select GENERIC_GPIO |
738 | select HAVE_CLK | 742 | select HAVE_CLK |
743 | select CLKDEV_LOOKUP | ||
739 | select CPU_V7 | 744 | select CPU_V7 |
740 | select ARM_L1_CACHE_SHIFT_6 | 745 | select ARM_L1_CACHE_SHIFT_6 |
741 | select ARCH_USES_GETTIMEOFFSET | 746 | select ARCH_USES_GETTIMEOFFSET |
@@ -751,6 +756,8 @@ config ARCH_S5PV210 | |||
751 | select ARCH_SPARSEMEM_ENABLE | 756 | select ARCH_SPARSEMEM_ENABLE |
752 | select GENERIC_GPIO | 757 | select GENERIC_GPIO |
753 | select HAVE_CLK | 758 | select HAVE_CLK |
759 | select CLKDEV_LOOKUP | ||
760 | select CLKSRC_MMIO | ||
754 | select ARM_L1_CACHE_SHIFT_6 | 761 | select ARM_L1_CACHE_SHIFT_6 |
755 | select ARCH_HAS_CPUFREQ | 762 | select ARCH_HAS_CPUFREQ |
756 | select GENERIC_CLOCKEVENTS | 763 | select GENERIC_CLOCKEVENTS |
@@ -767,6 +774,7 @@ config ARCH_EXYNOS4 | |||
767 | select ARCH_SPARSEMEM_ENABLE | 774 | select ARCH_SPARSEMEM_ENABLE |
768 | select GENERIC_GPIO | 775 | select GENERIC_GPIO |
769 | select HAVE_CLK | 776 | select HAVE_CLK |
777 | select CLKDEV_LOOKUP | ||
770 | select ARCH_HAS_CPUFREQ | 778 | select ARCH_HAS_CPUFREQ |
771 | select GENERIC_CLOCKEVENTS | 779 | select GENERIC_CLOCKEVENTS |
772 | select HAVE_S3C_RTC if RTC_CLASS | 780 | select HAVE_S3C_RTC if RTC_CLASS |
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index e5681636626f..841df7d21c2f 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c | |||
@@ -255,7 +255,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size, | |||
255 | if (buf == 0) { | 255 | if (buf == 0) { |
256 | dev_err(dev, "%s: unable to map unsafe buffer %p!\n", | 256 | dev_err(dev, "%s: unable to map unsafe buffer %p!\n", |
257 | __func__, ptr); | 257 | __func__, ptr); |
258 | return 0; | 258 | return ~0; |
259 | } | 259 | } |
260 | 260 | ||
261 | dev_dbg(dev, | 261 | dev_dbg(dev, |
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index d53c0abc4dd3..2b5b1421596c 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c | |||
@@ -583,7 +583,7 @@ static int armpmu_event_init(struct perf_event *event) | |||
583 | static void armpmu_enable(struct pmu *pmu) | 583 | static void armpmu_enable(struct pmu *pmu) |
584 | { | 584 | { |
585 | /* Enable all of the perf events on hardware. */ | 585 | /* Enable all of the perf events on hardware. */ |
586 | int idx; | 586 | int idx, enabled = 0; |
587 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | 587 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
588 | 588 | ||
589 | if (!armpmu) | 589 | if (!armpmu) |
@@ -596,9 +596,11 @@ static void armpmu_enable(struct pmu *pmu) | |||
596 | continue; | 596 | continue; |
597 | 597 | ||
598 | armpmu->enable(&event->hw, idx); | 598 | armpmu->enable(&event->hw, idx); |
599 | enabled = 1; | ||
599 | } | 600 | } |
600 | 601 | ||
601 | armpmu->start(); | 602 | if (enabled) |
603 | armpmu->start(); | ||
602 | } | 604 | } |
603 | 605 | ||
604 | static void armpmu_disable(struct pmu *pmu) | 606 | static void armpmu_disable(struct pmu *pmu) |
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index ed11fb08b05a..acbb447ac6b5 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
@@ -73,6 +73,7 @@ __setup("fpe=", fpe_setup); | |||
73 | #endif | 73 | #endif |
74 | 74 | ||
75 | extern void paging_init(struct machine_desc *desc); | 75 | extern void paging_init(struct machine_desc *desc); |
76 | extern void sanity_check_meminfo(void); | ||
76 | extern void reboot_setup(char *str); | 77 | extern void reboot_setup(char *str); |
77 | 78 | ||
78 | unsigned int processor_id; | 79 | unsigned int processor_id; |
@@ -900,6 +901,7 @@ void __init setup_arch(char **cmdline_p) | |||
900 | 901 | ||
901 | parse_early_param(); | 902 | parse_early_param(); |
902 | 903 | ||
904 | sanity_check_meminfo(); | ||
903 | arm_memblock_init(&meminfo, mdesc); | 905 | arm_memblock_init(&meminfo, mdesc); |
904 | 906 | ||
905 | paging_init(mdesc); | 907 | paging_init(mdesc); |
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 60636f499cb3..2c277d40cee6 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c | |||
@@ -115,7 +115,7 @@ static void __cpuinit twd_calibrate_rate(void) | |||
115 | twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); | 115 | twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); |
116 | 116 | ||
117 | printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000, | 117 | printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000, |
118 | (twd_timer_rate / 1000000) % 100); | 118 | (twd_timer_rate / 10000) % 100); |
119 | } | 119 | } |
120 | } | 120 | } |
121 | 121 | ||
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 1d4b65fd673e..6659a0d137a3 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
@@ -251,9 +251,9 @@ static void ep93xx_uart_set_mctrl(struct amba_device *dev, | |||
251 | unsigned int mcr; | 251 | unsigned int mcr; |
252 | 252 | ||
253 | mcr = 0; | 253 | mcr = 0; |
254 | if (!(mctrl & TIOCM_RTS)) | 254 | if (mctrl & TIOCM_RTS) |
255 | mcr |= 2; | 255 | mcr |= 2; |
256 | if (!(mctrl & TIOCM_DTR)) | 256 | if (mctrl & TIOCM_DTR) |
257 | mcr |= 1; | 257 | mcr |= 1; |
258 | 258 | ||
259 | __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); | 259 | __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); |
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index 1435fc31c4b2..ae433a052df6 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig | |||
@@ -110,6 +110,8 @@ config MACH_SMDKC210 | |||
110 | select S3C_DEV_HSMMC1 | 110 | select S3C_DEV_HSMMC1 |
111 | select S3C_DEV_HSMMC2 | 111 | select S3C_DEV_HSMMC2 |
112 | select S3C_DEV_HSMMC3 | 112 | select S3C_DEV_HSMMC3 |
113 | select SAMSUNG_DEV_PWM | ||
114 | select SAMSUNG_DEV_BACKLIGHT | ||
113 | select EXYNOS4_DEV_PD | 115 | select EXYNOS4_DEV_PD |
114 | select EXYNOS4_DEV_SYSMMU | 116 | select EXYNOS4_DEV_SYSMMU |
115 | select EXYNOS4_SETUP_I2C1 | 117 | select EXYNOS4_SETUP_I2C1 |
@@ -127,8 +129,10 @@ config MACH_SMDKV310 | |||
127 | select S3C_DEV_HSMMC1 | 129 | select S3C_DEV_HSMMC1 |
128 | select S3C_DEV_HSMMC2 | 130 | select S3C_DEV_HSMMC2 |
129 | select S3C_DEV_HSMMC3 | 131 | select S3C_DEV_HSMMC3 |
132 | select SAMSUNG_DEV_BACKLIGHT | ||
130 | select SAMSUNG_DEV_KEYPAD | 133 | select SAMSUNG_DEV_KEYPAD |
131 | select EXYNOS4_DEV_PD | 134 | select EXYNOS4_DEV_PD |
135 | select SAMSUNG_DEV_PWM | ||
132 | select EXYNOS4_DEV_SYSMMU | 136 | select EXYNOS4_DEV_SYSMMU |
133 | select EXYNOS4_SETUP_I2C1 | 137 | select EXYNOS4_SETUP_I2C1 |
134 | select EXYNOS4_SETUP_KEYPAD | 138 | select EXYNOS4_SETUP_KEYPAD |
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 871f9d508fde..66494f28bbef 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c | |||
@@ -27,24 +27,20 @@ | |||
27 | 27 | ||
28 | static struct clk clk_sclk_hdmi27m = { | 28 | static struct clk clk_sclk_hdmi27m = { |
29 | .name = "sclk_hdmi27m", | 29 | .name = "sclk_hdmi27m", |
30 | .id = -1, | ||
31 | .rate = 27000000, | 30 | .rate = 27000000, |
32 | }; | 31 | }; |
33 | 32 | ||
34 | static struct clk clk_sclk_hdmiphy = { | 33 | static struct clk clk_sclk_hdmiphy = { |
35 | .name = "sclk_hdmiphy", | 34 | .name = "sclk_hdmiphy", |
36 | .id = -1, | ||
37 | }; | 35 | }; |
38 | 36 | ||
39 | static struct clk clk_sclk_usbphy0 = { | 37 | static struct clk clk_sclk_usbphy0 = { |
40 | .name = "sclk_usbphy0", | 38 | .name = "sclk_usbphy0", |
41 | .id = -1, | ||
42 | .rate = 27000000, | 39 | .rate = 27000000, |
43 | }; | 40 | }; |
44 | 41 | ||
45 | static struct clk clk_sclk_usbphy1 = { | 42 | static struct clk clk_sclk_usbphy1 = { |
46 | .name = "sclk_usbphy1", | 43 | .name = "sclk_usbphy1", |
47 | .id = -1, | ||
48 | }; | 44 | }; |
49 | 45 | ||
50 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) | 46 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) |
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) | |||
132 | static struct clksrc_clk clk_mout_apll = { | 128 | static struct clksrc_clk clk_mout_apll = { |
133 | .clk = { | 129 | .clk = { |
134 | .name = "mout_apll", | 130 | .name = "mout_apll", |
135 | .id = -1, | ||
136 | }, | 131 | }, |
137 | .sources = &clk_src_apll, | 132 | .sources = &clk_src_apll, |
138 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, | 133 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, |
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = { | |||
141 | static struct clksrc_clk clk_sclk_apll = { | 136 | static struct clksrc_clk clk_sclk_apll = { |
142 | .clk = { | 137 | .clk = { |
143 | .name = "sclk_apll", | 138 | .name = "sclk_apll", |
144 | .id = -1, | ||
145 | .parent = &clk_mout_apll.clk, | 139 | .parent = &clk_mout_apll.clk, |
146 | }, | 140 | }, |
147 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, | 141 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, |
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = { | |||
150 | static struct clksrc_clk clk_mout_epll = { | 144 | static struct clksrc_clk clk_mout_epll = { |
151 | .clk = { | 145 | .clk = { |
152 | .name = "mout_epll", | 146 | .name = "mout_epll", |
153 | .id = -1, | ||
154 | }, | 147 | }, |
155 | .sources = &clk_src_epll, | 148 | .sources = &clk_src_epll, |
156 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, | 149 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, |
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = { | |||
159 | static struct clksrc_clk clk_mout_mpll = { | 152 | static struct clksrc_clk clk_mout_mpll = { |
160 | .clk = { | 153 | .clk = { |
161 | .name = "mout_mpll", | 154 | .name = "mout_mpll", |
162 | .id = -1, | ||
163 | }, | 155 | }, |
164 | .sources = &clk_src_mpll, | 156 | .sources = &clk_src_mpll, |
165 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, | 157 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, |
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = { | |||
178 | static struct clksrc_clk clk_moutcore = { | 170 | static struct clksrc_clk clk_moutcore = { |
179 | .clk = { | 171 | .clk = { |
180 | .name = "moutcore", | 172 | .name = "moutcore", |
181 | .id = -1, | ||
182 | }, | 173 | }, |
183 | .sources = &clkset_moutcore, | 174 | .sources = &clkset_moutcore, |
184 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, | 175 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, |
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = { | |||
187 | static struct clksrc_clk clk_coreclk = { | 178 | static struct clksrc_clk clk_coreclk = { |
188 | .clk = { | 179 | .clk = { |
189 | .name = "core_clk", | 180 | .name = "core_clk", |
190 | .id = -1, | ||
191 | .parent = &clk_moutcore.clk, | 181 | .parent = &clk_moutcore.clk, |
192 | }, | 182 | }, |
193 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, | 183 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, |
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = { | |||
196 | static struct clksrc_clk clk_armclk = { | 186 | static struct clksrc_clk clk_armclk = { |
197 | .clk = { | 187 | .clk = { |
198 | .name = "armclk", | 188 | .name = "armclk", |
199 | .id = -1, | ||
200 | .parent = &clk_coreclk.clk, | 189 | .parent = &clk_coreclk.clk, |
201 | }, | 190 | }, |
202 | }; | 191 | }; |
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = { | |||
204 | static struct clksrc_clk clk_aclk_corem0 = { | 193 | static struct clksrc_clk clk_aclk_corem0 = { |
205 | .clk = { | 194 | .clk = { |
206 | .name = "aclk_corem0", | 195 | .name = "aclk_corem0", |
207 | .id = -1, | ||
208 | .parent = &clk_coreclk.clk, | 196 | .parent = &clk_coreclk.clk, |
209 | }, | 197 | }, |
210 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | 198 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, |
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = { | |||
213 | static struct clksrc_clk clk_aclk_cores = { | 201 | static struct clksrc_clk clk_aclk_cores = { |
214 | .clk = { | 202 | .clk = { |
215 | .name = "aclk_cores", | 203 | .name = "aclk_cores", |
216 | .id = -1, | ||
217 | .parent = &clk_coreclk.clk, | 204 | .parent = &clk_coreclk.clk, |
218 | }, | 205 | }, |
219 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | 206 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, |
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = { | |||
222 | static struct clksrc_clk clk_aclk_corem1 = { | 209 | static struct clksrc_clk clk_aclk_corem1 = { |
223 | .clk = { | 210 | .clk = { |
224 | .name = "aclk_corem1", | 211 | .name = "aclk_corem1", |
225 | .id = -1, | ||
226 | .parent = &clk_coreclk.clk, | 212 | .parent = &clk_coreclk.clk, |
227 | }, | 213 | }, |
228 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, | 214 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, |
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = { | |||
231 | static struct clksrc_clk clk_periphclk = { | 217 | static struct clksrc_clk clk_periphclk = { |
232 | .clk = { | 218 | .clk = { |
233 | .name = "periphclk", | 219 | .name = "periphclk", |
234 | .id = -1, | ||
235 | .parent = &clk_coreclk.clk, | 220 | .parent = &clk_coreclk.clk, |
236 | }, | 221 | }, |
237 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, | 222 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, |
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = { | |||
252 | static struct clksrc_clk clk_mout_corebus = { | 237 | static struct clksrc_clk clk_mout_corebus = { |
253 | .clk = { | 238 | .clk = { |
254 | .name = "mout_corebus", | 239 | .name = "mout_corebus", |
255 | .id = -1, | ||
256 | }, | 240 | }, |
257 | .sources = &clkset_mout_corebus, | 241 | .sources = &clkset_mout_corebus, |
258 | .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, | 242 | .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, |
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = { | |||
261 | static struct clksrc_clk clk_sclk_dmc = { | 245 | static struct clksrc_clk clk_sclk_dmc = { |
262 | .clk = { | 246 | .clk = { |
263 | .name = "sclk_dmc", | 247 | .name = "sclk_dmc", |
264 | .id = -1, | ||
265 | .parent = &clk_mout_corebus.clk, | 248 | .parent = &clk_mout_corebus.clk, |
266 | }, | 249 | }, |
267 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, | 250 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, |
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = { | |||
270 | static struct clksrc_clk clk_aclk_cored = { | 253 | static struct clksrc_clk clk_aclk_cored = { |
271 | .clk = { | 254 | .clk = { |
272 | .name = "aclk_cored", | 255 | .name = "aclk_cored", |
273 | .id = -1, | ||
274 | .parent = &clk_sclk_dmc.clk, | 256 | .parent = &clk_sclk_dmc.clk, |
275 | }, | 257 | }, |
276 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, | 258 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, |
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = { | |||
279 | static struct clksrc_clk clk_aclk_corep = { | 261 | static struct clksrc_clk clk_aclk_corep = { |
280 | .clk = { | 262 | .clk = { |
281 | .name = "aclk_corep", | 263 | .name = "aclk_corep", |
282 | .id = -1, | ||
283 | .parent = &clk_aclk_cored.clk, | 264 | .parent = &clk_aclk_cored.clk, |
284 | }, | 265 | }, |
285 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, | 266 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, |
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = { | |||
288 | static struct clksrc_clk clk_aclk_acp = { | 269 | static struct clksrc_clk clk_aclk_acp = { |
289 | .clk = { | 270 | .clk = { |
290 | .name = "aclk_acp", | 271 | .name = "aclk_acp", |
291 | .id = -1, | ||
292 | .parent = &clk_mout_corebus.clk, | 272 | .parent = &clk_mout_corebus.clk, |
293 | }, | 273 | }, |
294 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, | 274 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, |
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = { | |||
297 | static struct clksrc_clk clk_pclk_acp = { | 277 | static struct clksrc_clk clk_pclk_acp = { |
298 | .clk = { | 278 | .clk = { |
299 | .name = "pclk_acp", | 279 | .name = "pclk_acp", |
300 | .id = -1, | ||
301 | .parent = &clk_aclk_acp.clk, | 280 | .parent = &clk_aclk_acp.clk, |
302 | }, | 281 | }, |
303 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, | 282 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, |
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = { | |||
318 | static struct clksrc_clk clk_aclk_200 = { | 297 | static struct clksrc_clk clk_aclk_200 = { |
319 | .clk = { | 298 | .clk = { |
320 | .name = "aclk_200", | 299 | .name = "aclk_200", |
321 | .id = -1, | ||
322 | }, | 300 | }, |
323 | .sources = &clkset_aclk, | 301 | .sources = &clkset_aclk, |
324 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, | 302 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, |
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = { | |||
328 | static struct clksrc_clk clk_aclk_100 = { | 306 | static struct clksrc_clk clk_aclk_100 = { |
329 | .clk = { | 307 | .clk = { |
330 | .name = "aclk_100", | 308 | .name = "aclk_100", |
331 | .id = -1, | ||
332 | }, | 309 | }, |
333 | .sources = &clkset_aclk, | 310 | .sources = &clkset_aclk, |
334 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, | 311 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, |
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = { | |||
338 | static struct clksrc_clk clk_aclk_160 = { | 315 | static struct clksrc_clk clk_aclk_160 = { |
339 | .clk = { | 316 | .clk = { |
340 | .name = "aclk_160", | 317 | .name = "aclk_160", |
341 | .id = -1, | ||
342 | }, | 318 | }, |
343 | .sources = &clkset_aclk, | 319 | .sources = &clkset_aclk, |
344 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, | 320 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, |
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = { | |||
348 | static struct clksrc_clk clk_aclk_133 = { | 324 | static struct clksrc_clk clk_aclk_133 = { |
349 | .clk = { | 325 | .clk = { |
350 | .name = "aclk_133", | 326 | .name = "aclk_133", |
351 | .id = -1, | ||
352 | }, | 327 | }, |
353 | .sources = &clkset_aclk, | 328 | .sources = &clkset_aclk, |
354 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, | 329 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, |
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = { | |||
368 | static struct clksrc_clk clk_vpllsrc = { | 343 | static struct clksrc_clk clk_vpllsrc = { |
369 | .clk = { | 344 | .clk = { |
370 | .name = "vpll_src", | 345 | .name = "vpll_src", |
371 | .id = -1, | ||
372 | .enable = exynos4_clksrc_mask_top_ctrl, | 346 | .enable = exynos4_clksrc_mask_top_ctrl, |
373 | .ctrlbit = (1 << 0), | 347 | .ctrlbit = (1 << 0), |
374 | }, | 348 | }, |
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = { | |||
389 | static struct clksrc_clk clk_sclk_vpll = { | 363 | static struct clksrc_clk clk_sclk_vpll = { |
390 | .clk = { | 364 | .clk = { |
391 | .name = "sclk_vpll", | 365 | .name = "sclk_vpll", |
392 | .id = -1, | ||
393 | }, | 366 | }, |
394 | .sources = &clkset_sclk_vpll, | 367 | .sources = &clkset_sclk_vpll, |
395 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, | 368 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, |
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = { | |||
398 | static struct clk init_clocks_off[] = { | 371 | static struct clk init_clocks_off[] = { |
399 | { | 372 | { |
400 | .name = "timers", | 373 | .name = "timers", |
401 | .id = -1, | ||
402 | .parent = &clk_aclk_100.clk, | 374 | .parent = &clk_aclk_100.clk, |
403 | .enable = exynos4_clk_ip_peril_ctrl, | 375 | .enable = exynos4_clk_ip_peril_ctrl, |
404 | .ctrlbit = (1<<24), | 376 | .ctrlbit = (1<<24), |
405 | }, { | 377 | }, { |
406 | .name = "csis", | 378 | .name = "csis", |
407 | .id = 0, | 379 | .devname = "s5p-mipi-csis.0", |
408 | .enable = exynos4_clk_ip_cam_ctrl, | 380 | .enable = exynos4_clk_ip_cam_ctrl, |
409 | .ctrlbit = (1 << 4), | 381 | .ctrlbit = (1 << 4), |
410 | }, { | 382 | }, { |
411 | .name = "csis", | 383 | .name = "csis", |
412 | .id = 1, | 384 | .devname = "s5p-mipi-csis.1", |
413 | .enable = exynos4_clk_ip_cam_ctrl, | 385 | .enable = exynos4_clk_ip_cam_ctrl, |
414 | .ctrlbit = (1 << 5), | 386 | .ctrlbit = (1 << 5), |
415 | }, { | 387 | }, { |
416 | .name = "fimc", | 388 | .name = "fimc", |
417 | .id = 0, | 389 | .devname = "exynos4-fimc.0", |
418 | .enable = exynos4_clk_ip_cam_ctrl, | 390 | .enable = exynos4_clk_ip_cam_ctrl, |
419 | .ctrlbit = (1 << 0), | 391 | .ctrlbit = (1 << 0), |
420 | }, { | 392 | }, { |
421 | .name = "fimc", | 393 | .name = "fimc", |
422 | .id = 1, | 394 | .devname = "exynos4-fimc.1", |
423 | .enable = exynos4_clk_ip_cam_ctrl, | 395 | .enable = exynos4_clk_ip_cam_ctrl, |
424 | .ctrlbit = (1 << 1), | 396 | .ctrlbit = (1 << 1), |
425 | }, { | 397 | }, { |
426 | .name = "fimc", | 398 | .name = "fimc", |
427 | .id = 2, | 399 | .devname = "exynos4-fimc.2", |
428 | .enable = exynos4_clk_ip_cam_ctrl, | 400 | .enable = exynos4_clk_ip_cam_ctrl, |
429 | .ctrlbit = (1 << 2), | 401 | .ctrlbit = (1 << 2), |
430 | }, { | 402 | }, { |
431 | .name = "fimc", | 403 | .name = "fimc", |
432 | .id = 3, | 404 | .devname = "exynos4-fimc.3", |
433 | .enable = exynos4_clk_ip_cam_ctrl, | 405 | .enable = exynos4_clk_ip_cam_ctrl, |
434 | .ctrlbit = (1 << 3), | 406 | .ctrlbit = (1 << 3), |
435 | }, { | 407 | }, { |
436 | .name = "fimd", | 408 | .name = "fimd", |
437 | .id = 0, | 409 | .devname = "exynos4-fb.0", |
438 | .enable = exynos4_clk_ip_lcd0_ctrl, | 410 | .enable = exynos4_clk_ip_lcd0_ctrl, |
439 | .ctrlbit = (1 << 0), | 411 | .ctrlbit = (1 << 0), |
440 | }, { | 412 | }, { |
441 | .name = "fimd", | 413 | .name = "fimd", |
442 | .id = 1, | 414 | .devname = "exynos4-fb.1", |
443 | .enable = exynos4_clk_ip_lcd1_ctrl, | 415 | .enable = exynos4_clk_ip_lcd1_ctrl, |
444 | .ctrlbit = (1 << 0), | 416 | .ctrlbit = (1 << 0), |
445 | }, { | 417 | }, { |
446 | .name = "sataphy", | 418 | .name = "sataphy", |
447 | .id = -1, | ||
448 | .parent = &clk_aclk_133.clk, | 419 | .parent = &clk_aclk_133.clk, |
449 | .enable = exynos4_clk_ip_fsys_ctrl, | 420 | .enable = exynos4_clk_ip_fsys_ctrl, |
450 | .ctrlbit = (1 << 3), | 421 | .ctrlbit = (1 << 3), |
451 | }, { | 422 | }, { |
452 | .name = "hsmmc", | 423 | .name = "hsmmc", |
453 | .id = 0, | 424 | .devname = "s3c-sdhci.0", |
454 | .parent = &clk_aclk_133.clk, | 425 | .parent = &clk_aclk_133.clk, |
455 | .enable = exynos4_clk_ip_fsys_ctrl, | 426 | .enable = exynos4_clk_ip_fsys_ctrl, |
456 | .ctrlbit = (1 << 5), | 427 | .ctrlbit = (1 << 5), |
457 | }, { | 428 | }, { |
458 | .name = "hsmmc", | 429 | .name = "hsmmc", |
459 | .id = 1, | 430 | .devname = "s3c-sdhci.1", |
460 | .parent = &clk_aclk_133.clk, | 431 | .parent = &clk_aclk_133.clk, |
461 | .enable = exynos4_clk_ip_fsys_ctrl, | 432 | .enable = exynos4_clk_ip_fsys_ctrl, |
462 | .ctrlbit = (1 << 6), | 433 | .ctrlbit = (1 << 6), |
463 | }, { | 434 | }, { |
464 | .name = "hsmmc", | 435 | .name = "hsmmc", |
465 | .id = 2, | 436 | .devname = "s3c-sdhci.2", |
466 | .parent = &clk_aclk_133.clk, | 437 | .parent = &clk_aclk_133.clk, |
467 | .enable = exynos4_clk_ip_fsys_ctrl, | 438 | .enable = exynos4_clk_ip_fsys_ctrl, |
468 | .ctrlbit = (1 << 7), | 439 | .ctrlbit = (1 << 7), |
469 | }, { | 440 | }, { |
470 | .name = "hsmmc", | 441 | .name = "hsmmc", |
471 | .id = 3, | 442 | .devname = "s3c-sdhci.3", |
472 | .parent = &clk_aclk_133.clk, | 443 | .parent = &clk_aclk_133.clk, |
473 | .enable = exynos4_clk_ip_fsys_ctrl, | 444 | .enable = exynos4_clk_ip_fsys_ctrl, |
474 | .ctrlbit = (1 << 8), | 445 | .ctrlbit = (1 << 8), |
475 | }, { | 446 | }, { |
476 | .name = "hsmmc", | 447 | .name = "dwmmc", |
477 | .id = 4, | ||
478 | .parent = &clk_aclk_133.clk, | 448 | .parent = &clk_aclk_133.clk, |
479 | .enable = exynos4_clk_ip_fsys_ctrl, | 449 | .enable = exynos4_clk_ip_fsys_ctrl, |
480 | .ctrlbit = (1 << 9), | 450 | .ctrlbit = (1 << 9), |
481 | }, { | 451 | }, { |
482 | .name = "sata", | 452 | .name = "sata", |
483 | .id = -1, | ||
484 | .parent = &clk_aclk_133.clk, | 453 | .parent = &clk_aclk_133.clk, |
485 | .enable = exynos4_clk_ip_fsys_ctrl, | 454 | .enable = exynos4_clk_ip_fsys_ctrl, |
486 | .ctrlbit = (1 << 10), | 455 | .ctrlbit = (1 << 10), |
487 | }, { | 456 | }, { |
488 | .name = "pdma", | 457 | .name = "pdma", |
489 | .id = 0, | 458 | .devname = "s3c-pl330.0", |
490 | .enable = exynos4_clk_ip_fsys_ctrl, | 459 | .enable = exynos4_clk_ip_fsys_ctrl, |
491 | .ctrlbit = (1 << 0), | 460 | .ctrlbit = (1 << 0), |
492 | }, { | 461 | }, { |
493 | .name = "pdma", | 462 | .name = "pdma", |
494 | .id = 1, | 463 | .devname = "s3c-pl330.1", |
495 | .enable = exynos4_clk_ip_fsys_ctrl, | 464 | .enable = exynos4_clk_ip_fsys_ctrl, |
496 | .ctrlbit = (1 << 1), | 465 | .ctrlbit = (1 << 1), |
497 | }, { | 466 | }, { |
498 | .name = "adc", | 467 | .name = "adc", |
499 | .id = -1, | ||
500 | .enable = exynos4_clk_ip_peril_ctrl, | 468 | .enable = exynos4_clk_ip_peril_ctrl, |
501 | .ctrlbit = (1 << 15), | 469 | .ctrlbit = (1 << 15), |
502 | }, { | 470 | }, { |
503 | .name = "keypad", | 471 | .name = "keypad", |
504 | .id = -1, | ||
505 | .enable = exynos4_clk_ip_perir_ctrl, | 472 | .enable = exynos4_clk_ip_perir_ctrl, |
506 | .ctrlbit = (1 << 16), | 473 | .ctrlbit = (1 << 16), |
507 | }, { | 474 | }, { |
508 | .name = "rtc", | 475 | .name = "rtc", |
509 | .id = -1, | ||
510 | .enable = exynos4_clk_ip_perir_ctrl, | 476 | .enable = exynos4_clk_ip_perir_ctrl, |
511 | .ctrlbit = (1 << 15), | 477 | .ctrlbit = (1 << 15), |
512 | }, { | 478 | }, { |
513 | .name = "watchdog", | 479 | .name = "watchdog", |
514 | .id = -1, | ||
515 | .parent = &clk_aclk_100.clk, | 480 | .parent = &clk_aclk_100.clk, |
516 | .enable = exynos4_clk_ip_perir_ctrl, | 481 | .enable = exynos4_clk_ip_perir_ctrl, |
517 | .ctrlbit = (1 << 14), | 482 | .ctrlbit = (1 << 14), |
518 | }, { | 483 | }, { |
519 | .name = "usbhost", | 484 | .name = "usbhost", |
520 | .id = -1, | ||
521 | .enable = exynos4_clk_ip_fsys_ctrl , | 485 | .enable = exynos4_clk_ip_fsys_ctrl , |
522 | .ctrlbit = (1 << 12), | 486 | .ctrlbit = (1 << 12), |
523 | }, { | 487 | }, { |
524 | .name = "otg", | 488 | .name = "otg", |
525 | .id = -1, | ||
526 | .enable = exynos4_clk_ip_fsys_ctrl, | 489 | .enable = exynos4_clk_ip_fsys_ctrl, |
527 | .ctrlbit = (1 << 13), | 490 | .ctrlbit = (1 << 13), |
528 | }, { | 491 | }, { |
529 | .name = "spi", | 492 | .name = "spi", |
530 | .id = 0, | 493 | .devname = "s3c64xx-spi.0", |
531 | .enable = exynos4_clk_ip_peril_ctrl, | 494 | .enable = exynos4_clk_ip_peril_ctrl, |
532 | .ctrlbit = (1 << 16), | 495 | .ctrlbit = (1 << 16), |
533 | }, { | 496 | }, { |
534 | .name = "spi", | 497 | .name = "spi", |
535 | .id = 1, | 498 | .devname = "s3c64xx-spi.1", |
536 | .enable = exynos4_clk_ip_peril_ctrl, | 499 | .enable = exynos4_clk_ip_peril_ctrl, |
537 | .ctrlbit = (1 << 17), | 500 | .ctrlbit = (1 << 17), |
538 | }, { | 501 | }, { |
539 | .name = "spi", | 502 | .name = "spi", |
540 | .id = 2, | 503 | .devname = "s3c64xx-spi.2", |
541 | .enable = exynos4_clk_ip_peril_ctrl, | 504 | .enable = exynos4_clk_ip_peril_ctrl, |
542 | .ctrlbit = (1 << 18), | 505 | .ctrlbit = (1 << 18), |
543 | }, { | 506 | }, { |
544 | .name = "iis", | 507 | .name = "iis", |
545 | .id = 0, | 508 | .devname = "samsung-i2s.0", |
546 | .enable = exynos4_clk_ip_peril_ctrl, | 509 | .enable = exynos4_clk_ip_peril_ctrl, |
547 | .ctrlbit = (1 << 19), | 510 | .ctrlbit = (1 << 19), |
548 | }, { | 511 | }, { |
549 | .name = "iis", | 512 | .name = "iis", |
550 | .id = 1, | 513 | .devname = "samsung-i2s.1", |
551 | .enable = exynos4_clk_ip_peril_ctrl, | 514 | .enable = exynos4_clk_ip_peril_ctrl, |
552 | .ctrlbit = (1 << 20), | 515 | .ctrlbit = (1 << 20), |
553 | }, { | 516 | }, { |
554 | .name = "iis", | 517 | .name = "iis", |
555 | .id = 2, | 518 | .devname = "samsung-i2s.2", |
556 | .enable = exynos4_clk_ip_peril_ctrl, | 519 | .enable = exynos4_clk_ip_peril_ctrl, |
557 | .ctrlbit = (1 << 21), | 520 | .ctrlbit = (1 << 21), |
558 | }, { | 521 | }, { |
@@ -562,125 +525,110 @@ static struct clk init_clocks_off[] = { | |||
562 | .ctrlbit = (1 << 27), | 525 | .ctrlbit = (1 << 27), |
563 | }, { | 526 | }, { |
564 | .name = "fimg2d", | 527 | .name = "fimg2d", |
565 | .id = -1, | ||
566 | .enable = exynos4_clk_ip_image_ctrl, | 528 | .enable = exynos4_clk_ip_image_ctrl, |
567 | .ctrlbit = (1 << 0), | 529 | .ctrlbit = (1 << 0), |
568 | }, { | 530 | }, { |
569 | .name = "i2c", | 531 | .name = "i2c", |
570 | .id = 0, | 532 | .devname = "s3c2440-i2c.0", |
571 | .parent = &clk_aclk_100.clk, | 533 | .parent = &clk_aclk_100.clk, |
572 | .enable = exynos4_clk_ip_peril_ctrl, | 534 | .enable = exynos4_clk_ip_peril_ctrl, |
573 | .ctrlbit = (1 << 6), | 535 | .ctrlbit = (1 << 6), |
574 | }, { | 536 | }, { |
575 | .name = "i2c", | 537 | .name = "i2c", |
576 | .id = 1, | 538 | .devname = "s3c2440-i2c.1", |
577 | .parent = &clk_aclk_100.clk, | 539 | .parent = &clk_aclk_100.clk, |
578 | .enable = exynos4_clk_ip_peril_ctrl, | 540 | .enable = exynos4_clk_ip_peril_ctrl, |
579 | .ctrlbit = (1 << 7), | 541 | .ctrlbit = (1 << 7), |
580 | }, { | 542 | }, { |
581 | .name = "i2c", | 543 | .name = "i2c", |
582 | .id = 2, | 544 | .devname = "s3c2440-i2c.2", |
583 | .parent = &clk_aclk_100.clk, | 545 | .parent = &clk_aclk_100.clk, |
584 | .enable = exynos4_clk_ip_peril_ctrl, | 546 | .enable = exynos4_clk_ip_peril_ctrl, |
585 | .ctrlbit = (1 << 8), | 547 | .ctrlbit = (1 << 8), |
586 | }, { | 548 | }, { |
587 | .name = "i2c", | 549 | .name = "i2c", |
588 | .id = 3, | 550 | .devname = "s3c2440-i2c.3", |
589 | .parent = &clk_aclk_100.clk, | 551 | .parent = &clk_aclk_100.clk, |
590 | .enable = exynos4_clk_ip_peril_ctrl, | 552 | .enable = exynos4_clk_ip_peril_ctrl, |
591 | .ctrlbit = (1 << 9), | 553 | .ctrlbit = (1 << 9), |
592 | }, { | 554 | }, { |
593 | .name = "i2c", | 555 | .name = "i2c", |
594 | .id = 4, | 556 | .devname = "s3c2440-i2c.4", |
595 | .parent = &clk_aclk_100.clk, | 557 | .parent = &clk_aclk_100.clk, |
596 | .enable = exynos4_clk_ip_peril_ctrl, | 558 | .enable = exynos4_clk_ip_peril_ctrl, |
597 | .ctrlbit = (1 << 10), | 559 | .ctrlbit = (1 << 10), |
598 | }, { | 560 | }, { |
599 | .name = "i2c", | 561 | .name = "i2c", |
600 | .id = 5, | 562 | .devname = "s3c2440-i2c.5", |
601 | .parent = &clk_aclk_100.clk, | 563 | .parent = &clk_aclk_100.clk, |
602 | .enable = exynos4_clk_ip_peril_ctrl, | 564 | .enable = exynos4_clk_ip_peril_ctrl, |
603 | .ctrlbit = (1 << 11), | 565 | .ctrlbit = (1 << 11), |
604 | }, { | 566 | }, { |
605 | .name = "i2c", | 567 | .name = "i2c", |
606 | .id = 6, | 568 | .devname = "s3c2440-i2c.6", |
607 | .parent = &clk_aclk_100.clk, | 569 | .parent = &clk_aclk_100.clk, |
608 | .enable = exynos4_clk_ip_peril_ctrl, | 570 | .enable = exynos4_clk_ip_peril_ctrl, |
609 | .ctrlbit = (1 << 12), | 571 | .ctrlbit = (1 << 12), |
610 | }, { | 572 | }, { |
611 | .name = "i2c", | 573 | .name = "i2c", |
612 | .id = 7, | 574 | .devname = "s3c2440-i2c.7", |
613 | .parent = &clk_aclk_100.clk, | 575 | .parent = &clk_aclk_100.clk, |
614 | .enable = exynos4_clk_ip_peril_ctrl, | 576 | .enable = exynos4_clk_ip_peril_ctrl, |
615 | .ctrlbit = (1 << 13), | 577 | .ctrlbit = (1 << 13), |
616 | }, { | 578 | }, { |
617 | .name = "SYSMMU_MDMA", | 579 | .name = "SYSMMU_MDMA", |
618 | .id = -1, | ||
619 | .enable = exynos4_clk_ip_image_ctrl, | 580 | .enable = exynos4_clk_ip_image_ctrl, |
620 | .ctrlbit = (1 << 5), | 581 | .ctrlbit = (1 << 5), |
621 | }, { | 582 | }, { |
622 | .name = "SYSMMU_FIMC0", | 583 | .name = "SYSMMU_FIMC0", |
623 | .id = -1, | ||
624 | .enable = exynos4_clk_ip_cam_ctrl, | 584 | .enable = exynos4_clk_ip_cam_ctrl, |
625 | .ctrlbit = (1 << 7), | 585 | .ctrlbit = (1 << 7), |
626 | }, { | 586 | }, { |
627 | .name = "SYSMMU_FIMC1", | 587 | .name = "SYSMMU_FIMC1", |
628 | .id = -1, | ||
629 | .enable = exynos4_clk_ip_cam_ctrl, | 588 | .enable = exynos4_clk_ip_cam_ctrl, |
630 | .ctrlbit = (1 << 8), | 589 | .ctrlbit = (1 << 8), |
631 | }, { | 590 | }, { |
632 | .name = "SYSMMU_FIMC2", | 591 | .name = "SYSMMU_FIMC2", |
633 | .id = -1, | ||
634 | .enable = exynos4_clk_ip_cam_ctrl, | 592 | .enable = exynos4_clk_ip_cam_ctrl, |
635 | .ctrlbit = (1 << 9), | 593 | .ctrlbit = (1 << 9), |
636 | }, { | 594 | }, { |
637 | .name = "SYSMMU_FIMC3", | 595 | .name = "SYSMMU_FIMC3", |
638 | .id = -1, | ||
639 | .enable = exynos4_clk_ip_cam_ctrl, | 596 | .enable = exynos4_clk_ip_cam_ctrl, |
640 | .ctrlbit = (1 << 10), | 597 | .ctrlbit = (1 << 10), |
641 | }, { | 598 | }, { |
642 | .name = "SYSMMU_JPEG", | 599 | .name = "SYSMMU_JPEG", |
643 | .id = -1, | ||
644 | .enable = exynos4_clk_ip_cam_ctrl, | 600 | .enable = exynos4_clk_ip_cam_ctrl, |
645 | .ctrlbit = (1 << 11), | 601 | .ctrlbit = (1 << 11), |
646 | }, { | 602 | }, { |
647 | .name = "SYSMMU_FIMD0", | 603 | .name = "SYSMMU_FIMD0", |
648 | .id = -1, | ||
649 | .enable = exynos4_clk_ip_lcd0_ctrl, | 604 | .enable = exynos4_clk_ip_lcd0_ctrl, |
650 | .ctrlbit = (1 << 4), | 605 | .ctrlbit = (1 << 4), |
651 | }, { | 606 | }, { |
652 | .name = "SYSMMU_FIMD1", | 607 | .name = "SYSMMU_FIMD1", |
653 | .id = -1, | ||
654 | .enable = exynos4_clk_ip_lcd1_ctrl, | 608 | .enable = exynos4_clk_ip_lcd1_ctrl, |
655 | .ctrlbit = (1 << 4), | 609 | .ctrlbit = (1 << 4), |
656 | }, { | 610 | }, { |
657 | .name = "SYSMMU_PCIe", | 611 | .name = "SYSMMU_PCIe", |
658 | .id = -1, | ||
659 | .enable = exynos4_clk_ip_fsys_ctrl, | 612 | .enable = exynos4_clk_ip_fsys_ctrl, |
660 | .ctrlbit = (1 << 18), | 613 | .ctrlbit = (1 << 18), |
661 | }, { | 614 | }, { |
662 | .name = "SYSMMU_G2D", | 615 | .name = "SYSMMU_G2D", |
663 | .id = -1, | ||
664 | .enable = exynos4_clk_ip_image_ctrl, | 616 | .enable = exynos4_clk_ip_image_ctrl, |
665 | .ctrlbit = (1 << 3), | 617 | .ctrlbit = (1 << 3), |
666 | }, { | 618 | }, { |
667 | .name = "SYSMMU_ROTATOR", | 619 | .name = "SYSMMU_ROTATOR", |
668 | .id = -1, | ||
669 | .enable = exynos4_clk_ip_image_ctrl, | 620 | .enable = exynos4_clk_ip_image_ctrl, |
670 | .ctrlbit = (1 << 4), | 621 | .ctrlbit = (1 << 4), |
671 | }, { | 622 | }, { |
672 | .name = "SYSMMU_TV", | 623 | .name = "SYSMMU_TV", |
673 | .id = -1, | ||
674 | .enable = exynos4_clk_ip_tv_ctrl, | 624 | .enable = exynos4_clk_ip_tv_ctrl, |
675 | .ctrlbit = (1 << 4), | 625 | .ctrlbit = (1 << 4), |
676 | }, { | 626 | }, { |
677 | .name = "SYSMMU_MFC_L", | 627 | .name = "SYSMMU_MFC_L", |
678 | .id = -1, | ||
679 | .enable = exynos4_clk_ip_mfc_ctrl, | 628 | .enable = exynos4_clk_ip_mfc_ctrl, |
680 | .ctrlbit = (1 << 1), | 629 | .ctrlbit = (1 << 1), |
681 | }, { | 630 | }, { |
682 | .name = "SYSMMU_MFC_R", | 631 | .name = "SYSMMU_MFC_R", |
683 | .id = -1, | ||
684 | .enable = exynos4_clk_ip_mfc_ctrl, | 632 | .enable = exynos4_clk_ip_mfc_ctrl, |
685 | .ctrlbit = (1 << 2), | 633 | .ctrlbit = (1 << 2), |
686 | } | 634 | } |
@@ -689,32 +637,32 @@ static struct clk init_clocks_off[] = { | |||
689 | static struct clk init_clocks[] = { | 637 | static struct clk init_clocks[] = { |
690 | { | 638 | { |
691 | .name = "uart", | 639 | .name = "uart", |
692 | .id = 0, | 640 | .devname = "s5pv210-uart.0", |
693 | .enable = exynos4_clk_ip_peril_ctrl, | 641 | .enable = exynos4_clk_ip_peril_ctrl, |
694 | .ctrlbit = (1 << 0), | 642 | .ctrlbit = (1 << 0), |
695 | }, { | 643 | }, { |
696 | .name = "uart", | 644 | .name = "uart", |
697 | .id = 1, | 645 | .devname = "s5pv210-uart.1", |
698 | .enable = exynos4_clk_ip_peril_ctrl, | 646 | .enable = exynos4_clk_ip_peril_ctrl, |
699 | .ctrlbit = (1 << 1), | 647 | .ctrlbit = (1 << 1), |
700 | }, { | 648 | }, { |
701 | .name = "uart", | 649 | .name = "uart", |
702 | .id = 2, | 650 | .devname = "s5pv210-uart.2", |
703 | .enable = exynos4_clk_ip_peril_ctrl, | 651 | .enable = exynos4_clk_ip_peril_ctrl, |
704 | .ctrlbit = (1 << 2), | 652 | .ctrlbit = (1 << 2), |
705 | }, { | 653 | }, { |
706 | .name = "uart", | 654 | .name = "uart", |
707 | .id = 3, | 655 | .devname = "s5pv210-uart.3", |
708 | .enable = exynos4_clk_ip_peril_ctrl, | 656 | .enable = exynos4_clk_ip_peril_ctrl, |
709 | .ctrlbit = (1 << 3), | 657 | .ctrlbit = (1 << 3), |
710 | }, { | 658 | }, { |
711 | .name = "uart", | 659 | .name = "uart", |
712 | .id = 4, | 660 | .devname = "s5pv210-uart.4", |
713 | .enable = exynos4_clk_ip_peril_ctrl, | 661 | .enable = exynos4_clk_ip_peril_ctrl, |
714 | .ctrlbit = (1 << 4), | 662 | .ctrlbit = (1 << 4), |
715 | }, { | 663 | }, { |
716 | .name = "uart", | 664 | .name = "uart", |
717 | .id = 5, | 665 | .devname = "s5pv210-uart.5", |
718 | .enable = exynos4_clk_ip_peril_ctrl, | 666 | .enable = exynos4_clk_ip_peril_ctrl, |
719 | .ctrlbit = (1 << 5), | 667 | .ctrlbit = (1 << 5), |
720 | } | 668 | } |
@@ -750,7 +698,6 @@ static struct clksrc_sources clkset_mout_g2d0 = { | |||
750 | static struct clksrc_clk clk_mout_g2d0 = { | 698 | static struct clksrc_clk clk_mout_g2d0 = { |
751 | .clk = { | 699 | .clk = { |
752 | .name = "mout_g2d0", | 700 | .name = "mout_g2d0", |
753 | .id = -1, | ||
754 | }, | 701 | }, |
755 | .sources = &clkset_mout_g2d0, | 702 | .sources = &clkset_mout_g2d0, |
756 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, | 703 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, |
@@ -769,7 +716,6 @@ static struct clksrc_sources clkset_mout_g2d1 = { | |||
769 | static struct clksrc_clk clk_mout_g2d1 = { | 716 | static struct clksrc_clk clk_mout_g2d1 = { |
770 | .clk = { | 717 | .clk = { |
771 | .name = "mout_g2d1", | 718 | .name = "mout_g2d1", |
772 | .id = -1, | ||
773 | }, | 719 | }, |
774 | .sources = &clkset_mout_g2d1, | 720 | .sources = &clkset_mout_g2d1, |
775 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, | 721 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, |
@@ -788,7 +734,6 @@ static struct clksrc_sources clkset_mout_g2d = { | |||
788 | static struct clksrc_clk clk_dout_mmc0 = { | 734 | static struct clksrc_clk clk_dout_mmc0 = { |
789 | .clk = { | 735 | .clk = { |
790 | .name = "dout_mmc0", | 736 | .name = "dout_mmc0", |
791 | .id = -1, | ||
792 | }, | 737 | }, |
793 | .sources = &clkset_group, | 738 | .sources = &clkset_group, |
794 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, | 739 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, |
@@ -798,7 +743,6 @@ static struct clksrc_clk clk_dout_mmc0 = { | |||
798 | static struct clksrc_clk clk_dout_mmc1 = { | 743 | static struct clksrc_clk clk_dout_mmc1 = { |
799 | .clk = { | 744 | .clk = { |
800 | .name = "dout_mmc1", | 745 | .name = "dout_mmc1", |
801 | .id = -1, | ||
802 | }, | 746 | }, |
803 | .sources = &clkset_group, | 747 | .sources = &clkset_group, |
804 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, | 748 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, |
@@ -808,7 +752,6 @@ static struct clksrc_clk clk_dout_mmc1 = { | |||
808 | static struct clksrc_clk clk_dout_mmc2 = { | 752 | static struct clksrc_clk clk_dout_mmc2 = { |
809 | .clk = { | 753 | .clk = { |
810 | .name = "dout_mmc2", | 754 | .name = "dout_mmc2", |
811 | .id = -1, | ||
812 | }, | 755 | }, |
813 | .sources = &clkset_group, | 756 | .sources = &clkset_group, |
814 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, | 757 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, |
@@ -818,7 +761,6 @@ static struct clksrc_clk clk_dout_mmc2 = { | |||
818 | static struct clksrc_clk clk_dout_mmc3 = { | 761 | static struct clksrc_clk clk_dout_mmc3 = { |
819 | .clk = { | 762 | .clk = { |
820 | .name = "dout_mmc3", | 763 | .name = "dout_mmc3", |
821 | .id = -1, | ||
822 | }, | 764 | }, |
823 | .sources = &clkset_group, | 765 | .sources = &clkset_group, |
824 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, | 766 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, |
@@ -828,7 +770,6 @@ static struct clksrc_clk clk_dout_mmc3 = { | |||
828 | static struct clksrc_clk clk_dout_mmc4 = { | 770 | static struct clksrc_clk clk_dout_mmc4 = { |
829 | .clk = { | 771 | .clk = { |
830 | .name = "dout_mmc4", | 772 | .name = "dout_mmc4", |
831 | .id = -1, | ||
832 | }, | 773 | }, |
833 | .sources = &clkset_group, | 774 | .sources = &clkset_group, |
834 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, | 775 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, |
@@ -839,7 +780,7 @@ static struct clksrc_clk clksrcs[] = { | |||
839 | { | 780 | { |
840 | .clk = { | 781 | .clk = { |
841 | .name = "uclk1", | 782 | .name = "uclk1", |
842 | .id = 0, | 783 | .devname = "s5pv210-uart.0", |
843 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 784 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
844 | .ctrlbit = (1 << 0), | 785 | .ctrlbit = (1 << 0), |
845 | }, | 786 | }, |
@@ -849,7 +790,7 @@ static struct clksrc_clk clksrcs[] = { | |||
849 | }, { | 790 | }, { |
850 | .clk = { | 791 | .clk = { |
851 | .name = "uclk1", | 792 | .name = "uclk1", |
852 | .id = 1, | 793 | .devname = "s5pv210-uart.1", |
853 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 794 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
854 | .ctrlbit = (1 << 4), | 795 | .ctrlbit = (1 << 4), |
855 | }, | 796 | }, |
@@ -859,7 +800,7 @@ static struct clksrc_clk clksrcs[] = { | |||
859 | }, { | 800 | }, { |
860 | .clk = { | 801 | .clk = { |
861 | .name = "uclk1", | 802 | .name = "uclk1", |
862 | .id = 2, | 803 | .devname = "s5pv210-uart.2", |
863 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 804 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
864 | .ctrlbit = (1 << 8), | 805 | .ctrlbit = (1 << 8), |
865 | }, | 806 | }, |
@@ -869,7 +810,7 @@ static struct clksrc_clk clksrcs[] = { | |||
869 | }, { | 810 | }, { |
870 | .clk = { | 811 | .clk = { |
871 | .name = "uclk1", | 812 | .name = "uclk1", |
872 | .id = 3, | 813 | .devname = "s5pv210-uart.3", |
873 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 814 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
874 | .ctrlbit = (1 << 12), | 815 | .ctrlbit = (1 << 12), |
875 | }, | 816 | }, |
@@ -879,7 +820,6 @@ static struct clksrc_clk clksrcs[] = { | |||
879 | }, { | 820 | }, { |
880 | .clk = { | 821 | .clk = { |
881 | .name = "sclk_pwm", | 822 | .name = "sclk_pwm", |
882 | .id = -1, | ||
883 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 823 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
884 | .ctrlbit = (1 << 24), | 824 | .ctrlbit = (1 << 24), |
885 | }, | 825 | }, |
@@ -889,7 +829,7 @@ static struct clksrc_clk clksrcs[] = { | |||
889 | }, { | 829 | }, { |
890 | .clk = { | 830 | .clk = { |
891 | .name = "sclk_csis", | 831 | .name = "sclk_csis", |
892 | .id = 0, | 832 | .devname = "s5p-mipi-csis.0", |
893 | .enable = exynos4_clksrc_mask_cam_ctrl, | 833 | .enable = exynos4_clksrc_mask_cam_ctrl, |
894 | .ctrlbit = (1 << 24), | 834 | .ctrlbit = (1 << 24), |
895 | }, | 835 | }, |
@@ -899,7 +839,7 @@ static struct clksrc_clk clksrcs[] = { | |||
899 | }, { | 839 | }, { |
900 | .clk = { | 840 | .clk = { |
901 | .name = "sclk_csis", | 841 | .name = "sclk_csis", |
902 | .id = 1, | 842 | .devname = "s5p-mipi-csis.1", |
903 | .enable = exynos4_clksrc_mask_cam_ctrl, | 843 | .enable = exynos4_clksrc_mask_cam_ctrl, |
904 | .ctrlbit = (1 << 28), | 844 | .ctrlbit = (1 << 28), |
905 | }, | 845 | }, |
@@ -909,7 +849,7 @@ static struct clksrc_clk clksrcs[] = { | |||
909 | }, { | 849 | }, { |
910 | .clk = { | 850 | .clk = { |
911 | .name = "sclk_cam", | 851 | .name = "sclk_cam", |
912 | .id = 0, | 852 | .devname = "exynos4-fimc.0", |
913 | .enable = exynos4_clksrc_mask_cam_ctrl, | 853 | .enable = exynos4_clksrc_mask_cam_ctrl, |
914 | .ctrlbit = (1 << 16), | 854 | .ctrlbit = (1 << 16), |
915 | }, | 855 | }, |
@@ -919,7 +859,7 @@ static struct clksrc_clk clksrcs[] = { | |||
919 | }, { | 859 | }, { |
920 | .clk = { | 860 | .clk = { |
921 | .name = "sclk_cam", | 861 | .name = "sclk_cam", |
922 | .id = 1, | 862 | .devname = "exynos4-fimc.1", |
923 | .enable = exynos4_clksrc_mask_cam_ctrl, | 863 | .enable = exynos4_clksrc_mask_cam_ctrl, |
924 | .ctrlbit = (1 << 20), | 864 | .ctrlbit = (1 << 20), |
925 | }, | 865 | }, |
@@ -929,7 +869,7 @@ static struct clksrc_clk clksrcs[] = { | |||
929 | }, { | 869 | }, { |
930 | .clk = { | 870 | .clk = { |
931 | .name = "sclk_fimc", | 871 | .name = "sclk_fimc", |
932 | .id = 0, | 872 | .devname = "exynos4-fimc.0", |
933 | .enable = exynos4_clksrc_mask_cam_ctrl, | 873 | .enable = exynos4_clksrc_mask_cam_ctrl, |
934 | .ctrlbit = (1 << 0), | 874 | .ctrlbit = (1 << 0), |
935 | }, | 875 | }, |
@@ -939,7 +879,7 @@ static struct clksrc_clk clksrcs[] = { | |||
939 | }, { | 879 | }, { |
940 | .clk = { | 880 | .clk = { |
941 | .name = "sclk_fimc", | 881 | .name = "sclk_fimc", |
942 | .id = 1, | 882 | .devname = "exynos4-fimc.1", |
943 | .enable = exynos4_clksrc_mask_cam_ctrl, | 883 | .enable = exynos4_clksrc_mask_cam_ctrl, |
944 | .ctrlbit = (1 << 4), | 884 | .ctrlbit = (1 << 4), |
945 | }, | 885 | }, |
@@ -949,7 +889,7 @@ static struct clksrc_clk clksrcs[] = { | |||
949 | }, { | 889 | }, { |
950 | .clk = { | 890 | .clk = { |
951 | .name = "sclk_fimc", | 891 | .name = "sclk_fimc", |
952 | .id = 2, | 892 | .devname = "exynos4-fimc.2", |
953 | .enable = exynos4_clksrc_mask_cam_ctrl, | 893 | .enable = exynos4_clksrc_mask_cam_ctrl, |
954 | .ctrlbit = (1 << 8), | 894 | .ctrlbit = (1 << 8), |
955 | }, | 895 | }, |
@@ -959,7 +899,7 @@ static struct clksrc_clk clksrcs[] = { | |||
959 | }, { | 899 | }, { |
960 | .clk = { | 900 | .clk = { |
961 | .name = "sclk_fimc", | 901 | .name = "sclk_fimc", |
962 | .id = 3, | 902 | .devname = "exynos4-fimc.3", |
963 | .enable = exynos4_clksrc_mask_cam_ctrl, | 903 | .enable = exynos4_clksrc_mask_cam_ctrl, |
964 | .ctrlbit = (1 << 12), | 904 | .ctrlbit = (1 << 12), |
965 | }, | 905 | }, |
@@ -969,7 +909,7 @@ static struct clksrc_clk clksrcs[] = { | |||
969 | }, { | 909 | }, { |
970 | .clk = { | 910 | .clk = { |
971 | .name = "sclk_fimd", | 911 | .name = "sclk_fimd", |
972 | .id = 0, | 912 | .devname = "exynos4-fb.0", |
973 | .enable = exynos4_clksrc_mask_lcd0_ctrl, | 913 | .enable = exynos4_clksrc_mask_lcd0_ctrl, |
974 | .ctrlbit = (1 << 0), | 914 | .ctrlbit = (1 << 0), |
975 | }, | 915 | }, |
@@ -979,7 +919,7 @@ static struct clksrc_clk clksrcs[] = { | |||
979 | }, { | 919 | }, { |
980 | .clk = { | 920 | .clk = { |
981 | .name = "sclk_fimd", | 921 | .name = "sclk_fimd", |
982 | .id = 1, | 922 | .devname = "exynos4-fb.1", |
983 | .enable = exynos4_clksrc_mask_lcd1_ctrl, | 923 | .enable = exynos4_clksrc_mask_lcd1_ctrl, |
984 | .ctrlbit = (1 << 0), | 924 | .ctrlbit = (1 << 0), |
985 | }, | 925 | }, |
@@ -989,7 +929,6 @@ static struct clksrc_clk clksrcs[] = { | |||
989 | }, { | 929 | }, { |
990 | .clk = { | 930 | .clk = { |
991 | .name = "sclk_sata", | 931 | .name = "sclk_sata", |
992 | .id = -1, | ||
993 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 932 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
994 | .ctrlbit = (1 << 24), | 933 | .ctrlbit = (1 << 24), |
995 | }, | 934 | }, |
@@ -999,7 +938,7 @@ static struct clksrc_clk clksrcs[] = { | |||
999 | }, { | 938 | }, { |
1000 | .clk = { | 939 | .clk = { |
1001 | .name = "sclk_spi", | 940 | .name = "sclk_spi", |
1002 | .id = 0, | 941 | .devname = "s3c64xx-spi.0", |
1003 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 942 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1004 | .ctrlbit = (1 << 16), | 943 | .ctrlbit = (1 << 16), |
1005 | }, | 944 | }, |
@@ -1009,7 +948,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1009 | }, { | 948 | }, { |
1010 | .clk = { | 949 | .clk = { |
1011 | .name = "sclk_spi", | 950 | .name = "sclk_spi", |
1012 | .id = 1, | 951 | .devname = "s3c64xx-spi.1", |
1013 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 952 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1014 | .ctrlbit = (1 << 20), | 953 | .ctrlbit = (1 << 20), |
1015 | }, | 954 | }, |
@@ -1019,7 +958,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1019 | }, { | 958 | }, { |
1020 | .clk = { | 959 | .clk = { |
1021 | .name = "sclk_spi", | 960 | .name = "sclk_spi", |
1022 | .id = 2, | 961 | .devname = "s3c64xx-spi.2", |
1023 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 962 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1024 | .ctrlbit = (1 << 24), | 963 | .ctrlbit = (1 << 24), |
1025 | }, | 964 | }, |
@@ -1029,7 +968,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1029 | }, { | 968 | }, { |
1030 | .clk = { | 969 | .clk = { |
1031 | .name = "sclk_fimg2d", | 970 | .name = "sclk_fimg2d", |
1032 | .id = -1, | ||
1033 | }, | 971 | }, |
1034 | .sources = &clkset_mout_g2d, | 972 | .sources = &clkset_mout_g2d, |
1035 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, | 973 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, |
@@ -1037,7 +975,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1037 | }, { | 975 | }, { |
1038 | .clk = { | 976 | .clk = { |
1039 | .name = "sclk_mmc", | 977 | .name = "sclk_mmc", |
1040 | .id = 0, | 978 | .devname = "s3c-sdhci.0", |
1041 | .parent = &clk_dout_mmc0.clk, | 979 | .parent = &clk_dout_mmc0.clk, |
1042 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 980 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1043 | .ctrlbit = (1 << 0), | 981 | .ctrlbit = (1 << 0), |
@@ -1046,7 +984,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1046 | }, { | 984 | }, { |
1047 | .clk = { | 985 | .clk = { |
1048 | .name = "sclk_mmc", | 986 | .name = "sclk_mmc", |
1049 | .id = 1, | 987 | .devname = "s3c-sdhci.1", |
1050 | .parent = &clk_dout_mmc1.clk, | 988 | .parent = &clk_dout_mmc1.clk, |
1051 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 989 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1052 | .ctrlbit = (1 << 4), | 990 | .ctrlbit = (1 << 4), |
@@ -1055,7 +993,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1055 | }, { | 993 | }, { |
1056 | .clk = { | 994 | .clk = { |
1057 | .name = "sclk_mmc", | 995 | .name = "sclk_mmc", |
1058 | .id = 2, | 996 | .devname = "s3c-sdhci.2", |
1059 | .parent = &clk_dout_mmc2.clk, | 997 | .parent = &clk_dout_mmc2.clk, |
1060 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 998 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1061 | .ctrlbit = (1 << 8), | 999 | .ctrlbit = (1 << 8), |
@@ -1064,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1064 | }, { | 1002 | }, { |
1065 | .clk = { | 1003 | .clk = { |
1066 | .name = "sclk_mmc", | 1004 | .name = "sclk_mmc", |
1067 | .id = 3, | 1005 | .devname = "s3c-sdhci.3", |
1068 | .parent = &clk_dout_mmc3.clk, | 1006 | .parent = &clk_dout_mmc3.clk, |
1069 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1007 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1070 | .ctrlbit = (1 << 12), | 1008 | .ctrlbit = (1 << 12), |
@@ -1072,8 +1010,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1072 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, | 1010 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
1073 | }, { | 1011 | }, { |
1074 | .clk = { | 1012 | .clk = { |
1075 | .name = "sclk_mmc", | 1013 | .name = "sclk_dwmmc", |
1076 | .id = 4, | ||
1077 | .parent = &clk_dout_mmc4.clk, | 1014 | .parent = &clk_dout_mmc4.clk, |
1078 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1015 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1079 | .ctrlbit = (1 << 16), | 1016 | .ctrlbit = (1 << 16), |
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index 9babe4473e88..bfd621460abf 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <plat/sdhci.h> | 23 | #include <plat/sdhci.h> |
24 | #include <plat/devs.h> | 24 | #include <plat/devs.h> |
25 | #include <plat/fimc-core.h> | 25 | #include <plat/fimc-core.h> |
26 | #include <plat/iic-core.h> | ||
26 | 27 | ||
27 | #include <mach/regs-irq.h> | 28 | #include <mach/regs-irq.h> |
28 | 29 | ||
@@ -132,6 +133,11 @@ void __init exynos4_map_io(void) | |||
132 | s3c_fimc_setname(1, "exynos4-fimc"); | 133 | s3c_fimc_setname(1, "exynos4-fimc"); |
133 | s3c_fimc_setname(2, "exynos4-fimc"); | 134 | s3c_fimc_setname(2, "exynos4-fimc"); |
134 | s3c_fimc_setname(3, "exynos4-fimc"); | 135 | s3c_fimc_setname(3, "exynos4-fimc"); |
136 | |||
137 | /* The I2C bus controllers are directly compatible with s3c2440 */ | ||
138 | s3c_i2c0_setname("s3c2440-i2c"); | ||
139 | s3c_i2c1_setname("s3c2440-i2c"); | ||
140 | s3c_i2c2_setname("s3c2440-i2c"); | ||
135 | } | 141 | } |
136 | 142 | ||
137 | void __init exynos4_init_clocks(int xtal) | 143 | void __init exynos4_init_clocks(int xtal) |
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c index 1eed5f9f7bd3..983069a53239 100644 --- a/arch/arm/mach-exynos4/dev-audio.c +++ b/arch/arm/mach-exynos4/dev-audio.c | |||
@@ -330,7 +330,7 @@ struct platform_device exynos4_device_ac97 = { | |||
330 | 330 | ||
331 | static int exynos4_spdif_cfg_gpio(struct platform_device *pdev) | 331 | static int exynos4_spdif_cfg_gpio(struct platform_device *pdev) |
332 | { | 332 | { |
333 | s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3)); | 333 | s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4)); |
334 | 334 | ||
335 | return 0; | 335 | return 0; |
336 | } | 336 | } |
diff --git a/arch/arm/mach-exynos4/headsmp.S b/arch/arm/mach-exynos4/headsmp.S index 6c6cfc50c46b..3cdeb3647542 100644 --- a/arch/arm/mach-exynos4/headsmp.S +++ b/arch/arm/mach-exynos4/headsmp.S | |||
@@ -13,7 +13,7 @@ | |||
13 | #include <linux/linkage.h> | 13 | #include <linux/linkage.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | 15 | ||
16 | __INIT | 16 | __CPUINIT |
17 | 17 | ||
18 | /* | 18 | /* |
19 | * exynos4 specific entry point for secondary CPUs. This provides | 19 | * exynos4 specific entry point for secondary CPUs. This provides |
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-exynos4/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c index e645f7a955f0..f606ea75bf43 100644 --- a/arch/arm/mach-exynos4/mach-smdkc210.c +++ b/arch/arm/mach-exynos4/mach-smdkc210.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/smsc911x.h> | 15 | #include <linux/smsc911x.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/i2c.h> | 17 | #include <linux/i2c.h> |
18 | #include <linux/pwm_backlight.h> | ||
18 | 19 | ||
19 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
20 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
@@ -27,6 +28,8 @@ | |||
27 | #include <plat/sdhci.h> | 28 | #include <plat/sdhci.h> |
28 | #include <plat/iic.h> | 29 | #include <plat/iic.h> |
29 | #include <plat/pd.h> | 30 | #include <plat/pd.h> |
31 | #include <plat/gpio-cfg.h> | ||
32 | #include <plat/backlight.h> | ||
30 | 33 | ||
31 | #include <mach/map.h> | 34 | #include <mach/map.h> |
32 | 35 | ||
@@ -191,6 +194,17 @@ static void __init smdkc210_smsc911x_init(void) | |||
191 | (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); | 194 | (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); |
192 | } | 195 | } |
193 | 196 | ||
197 | /* LCD Backlight data */ | ||
198 | static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = { | ||
199 | .no = EXYNOS4_GPD0(1), | ||
200 | .func = S3C_GPIO_SFN(2), | ||
201 | }; | ||
202 | |||
203 | static struct platform_pwm_backlight_data smdkc210_bl_data = { | ||
204 | .pwm_id = 1, | ||
205 | .pwm_period_ns = 1000, | ||
206 | }; | ||
207 | |||
194 | static void __init smdkc210_map_io(void) | 208 | static void __init smdkc210_map_io(void) |
195 | { | 209 | { |
196 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | 210 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); |
@@ -210,6 +224,8 @@ static void __init smdkc210_machine_init(void) | |||
210 | s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); | 224 | s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata); |
211 | s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); | 225 | s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata); |
212 | 226 | ||
227 | samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data); | ||
228 | |||
213 | platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); | 229 | platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices)); |
214 | } | 230 | } |
215 | 231 | ||
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index 152676471b67..df1107828abd 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/i2c.h> | 17 | #include <linux/i2c.h> |
18 | #include <linux/input.h> | 18 | #include <linux/input.h> |
19 | #include <linux/pwm_backlight.h> | ||
19 | 20 | ||
20 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
21 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
@@ -29,6 +30,8 @@ | |||
29 | #include <plat/sdhci.h> | 30 | #include <plat/sdhci.h> |
30 | #include <plat/iic.h> | 31 | #include <plat/iic.h> |
31 | #include <plat/pd.h> | 32 | #include <plat/pd.h> |
33 | #include <plat/gpio-cfg.h> | ||
34 | #include <plat/backlight.h> | ||
32 | 35 | ||
33 | #include <mach/map.h> | 36 | #include <mach/map.h> |
34 | 37 | ||
@@ -78,9 +81,7 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = { | |||
78 | }; | 81 | }; |
79 | 82 | ||
80 | static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { | 83 | static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { |
81 | .cd_type = S3C_SDHCI_CD_GPIO, | 84 | .cd_type = S3C_SDHCI_CD_INTERNAL, |
82 | .ext_cd_gpio = EXYNOS4_GPK0(2), | ||
83 | .ext_cd_gpio_invert = 1, | ||
84 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | 85 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
85 | #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT | 86 | #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT |
86 | .max_width = 8, | 87 | .max_width = 8, |
@@ -96,9 +97,7 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { | |||
96 | }; | 97 | }; |
97 | 98 | ||
98 | static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { | 99 | static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { |
99 | .cd_type = S3C_SDHCI_CD_GPIO, | 100 | .cd_type = S3C_SDHCI_CD_INTERNAL, |
100 | .ext_cd_gpio = EXYNOS4_GPK2(2), | ||
101 | .ext_cd_gpio_invert = 1, | ||
102 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | 101 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
103 | #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT | 102 | #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT |
104 | .max_width = 8, | 103 | .max_width = 8, |
@@ -213,6 +212,17 @@ static void __init smdkv310_smsc911x_init(void) | |||
213 | (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); | 212 | (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); |
214 | } | 213 | } |
215 | 214 | ||
215 | /* LCD Backlight data */ | ||
216 | static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = { | ||
217 | .no = EXYNOS4_GPD0(1), | ||
218 | .func = S3C_GPIO_SFN(2), | ||
219 | }; | ||
220 | |||
221 | static struct platform_pwm_backlight_data smdkv310_bl_data = { | ||
222 | .pwm_id = 1, | ||
223 | .pwm_period_ns = 1000, | ||
224 | }; | ||
225 | |||
216 | static void __init smdkv310_map_io(void) | 226 | static void __init smdkv310_map_io(void) |
217 | { | 227 | { |
218 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | 228 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); |
@@ -234,6 +244,8 @@ static void __init smdkv310_machine_init(void) | |||
234 | 244 | ||
235 | samsung_keypad_set_platdata(&smdkv310_keypad_data); | 245 | samsung_keypad_set_platdata(&smdkv310_keypad_data); |
236 | 246 | ||
247 | samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data); | ||
248 | |||
237 | platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); | 249 | platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); |
238 | } | 250 | } |
239 | 251 | ||
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index f1ac7fbf54a9..312ea6b0409d 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
@@ -215,7 +215,7 @@ static struct omap_kp_platform_data ams_delta_kp_data __initdata = { | |||
215 | .delay = 9, | 215 | .delay = 9, |
216 | }; | 216 | }; |
217 | 217 | ||
218 | static struct platform_device ams_delta_kp_device __initdata = { | 218 | static struct platform_device ams_delta_kp_device = { |
219 | .name = "omap-keypad", | 219 | .name = "omap-keypad", |
220 | .id = -1, | 220 | .id = -1, |
221 | .dev = { | 221 | .dev = { |
@@ -225,12 +225,12 @@ static struct platform_device ams_delta_kp_device __initdata = { | |||
225 | .resource = ams_delta_kp_resources, | 225 | .resource = ams_delta_kp_resources, |
226 | }; | 226 | }; |
227 | 227 | ||
228 | static struct platform_device ams_delta_lcd_device __initdata = { | 228 | static struct platform_device ams_delta_lcd_device = { |
229 | .name = "lcd_ams_delta", | 229 | .name = "lcd_ams_delta", |
230 | .id = -1, | 230 | .id = -1, |
231 | }; | 231 | }; |
232 | 232 | ||
233 | static struct platform_device ams_delta_led_device __initdata = { | 233 | static struct platform_device ams_delta_led_device = { |
234 | .name = "ams-delta-led", | 234 | .name = "ams-delta-led", |
235 | .id = -1 | 235 | .id = -1 |
236 | }; | 236 | }; |
@@ -267,7 +267,7 @@ static struct soc_camera_link ams_delta_iclink = { | |||
267 | .power = ams_delta_camera_power, | 267 | .power = ams_delta_camera_power, |
268 | }; | 268 | }; |
269 | 269 | ||
270 | static struct platform_device ams_delta_camera_device __initdata = { | 270 | static struct platform_device ams_delta_camera_device = { |
271 | .name = "soc-camera-pdrv", | 271 | .name = "soc-camera-pdrv", |
272 | .id = 0, | 272 | .id = 0, |
273 | .dev = { | 273 | .dev = { |
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c index 04c4b04cf54e..364137c2042c 100644 --- a/arch/arm/mach-omap1/gpio15xx.c +++ b/arch/arm/mach-omap1/gpio15xx.c | |||
@@ -41,7 +41,7 @@ static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { | |||
41 | .bank_stride = 1, | 41 | .bank_stride = 1, |
42 | }; | 42 | }; |
43 | 43 | ||
44 | static struct __initdata platform_device omap15xx_mpu_gpio = { | 44 | static struct platform_device omap15xx_mpu_gpio = { |
45 | .name = "omap_gpio", | 45 | .name = "omap_gpio", |
46 | .id = 0, | 46 | .id = 0, |
47 | .dev = { | 47 | .dev = { |
@@ -70,7 +70,7 @@ static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { | |||
70 | .bank_width = 16, | 70 | .bank_width = 16, |
71 | }; | 71 | }; |
72 | 72 | ||
73 | static struct __initdata platform_device omap15xx_gpio = { | 73 | static struct platform_device omap15xx_gpio = { |
74 | .name = "omap_gpio", | 74 | .name = "omap_gpio", |
75 | .id = 1, | 75 | .id = 1, |
76 | .dev = { | 76 | .dev = { |
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c index 5dd0d4c82b24..293a246e2824 100644 --- a/arch/arm/mach-omap1/gpio16xx.c +++ b/arch/arm/mach-omap1/gpio16xx.c | |||
@@ -44,7 +44,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { | |||
44 | .bank_stride = 1, | 44 | .bank_stride = 1, |
45 | }; | 45 | }; |
46 | 46 | ||
47 | static struct __initdata platform_device omap16xx_mpu_gpio = { | 47 | static struct platform_device omap16xx_mpu_gpio = { |
48 | .name = "omap_gpio", | 48 | .name = "omap_gpio", |
49 | .id = 0, | 49 | .id = 0, |
50 | .dev = { | 50 | .dev = { |
@@ -73,7 +73,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { | |||
73 | .bank_width = 16, | 73 | .bank_width = 16, |
74 | }; | 74 | }; |
75 | 75 | ||
76 | static struct __initdata platform_device omap16xx_gpio1 = { | 76 | static struct platform_device omap16xx_gpio1 = { |
77 | .name = "omap_gpio", | 77 | .name = "omap_gpio", |
78 | .id = 1, | 78 | .id = 1, |
79 | .dev = { | 79 | .dev = { |
@@ -102,7 +102,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { | |||
102 | .bank_width = 16, | 102 | .bank_width = 16, |
103 | }; | 103 | }; |
104 | 104 | ||
105 | static struct __initdata platform_device omap16xx_gpio2 = { | 105 | static struct platform_device omap16xx_gpio2 = { |
106 | .name = "omap_gpio", | 106 | .name = "omap_gpio", |
107 | .id = 2, | 107 | .id = 2, |
108 | .dev = { | 108 | .dev = { |
@@ -131,7 +131,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { | |||
131 | .bank_width = 16, | 131 | .bank_width = 16, |
132 | }; | 132 | }; |
133 | 133 | ||
134 | static struct __initdata platform_device omap16xx_gpio3 = { | 134 | static struct platform_device omap16xx_gpio3 = { |
135 | .name = "omap_gpio", | 135 | .name = "omap_gpio", |
136 | .id = 3, | 136 | .id = 3, |
137 | .dev = { | 137 | .dev = { |
@@ -160,7 +160,7 @@ static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { | |||
160 | .bank_width = 16, | 160 | .bank_width = 16, |
161 | }; | 161 | }; |
162 | 162 | ||
163 | static struct __initdata platform_device omap16xx_gpio4 = { | 163 | static struct platform_device omap16xx_gpio4 = { |
164 | .name = "omap_gpio", | 164 | .name = "omap_gpio", |
165 | .id = 4, | 165 | .id = 4, |
166 | .dev = { | 166 | .dev = { |
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c index 1204c8b871af..c6ad248d63a6 100644 --- a/arch/arm/mach-omap1/gpio7xx.c +++ b/arch/arm/mach-omap1/gpio7xx.c | |||
@@ -46,7 +46,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { | |||
46 | .bank_stride = 2, | 46 | .bank_stride = 2, |
47 | }; | 47 | }; |
48 | 48 | ||
49 | static struct __initdata platform_device omap7xx_mpu_gpio = { | 49 | static struct platform_device omap7xx_mpu_gpio = { |
50 | .name = "omap_gpio", | 50 | .name = "omap_gpio", |
51 | .id = 0, | 51 | .id = 0, |
52 | .dev = { | 52 | .dev = { |
@@ -75,7 +75,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { | |||
75 | .bank_width = 32, | 75 | .bank_width = 32, |
76 | }; | 76 | }; |
77 | 77 | ||
78 | static struct __initdata platform_device omap7xx_gpio1 = { | 78 | static struct platform_device omap7xx_gpio1 = { |
79 | .name = "omap_gpio", | 79 | .name = "omap_gpio", |
80 | .id = 1, | 80 | .id = 1, |
81 | .dev = { | 81 | .dev = { |
@@ -104,7 +104,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { | |||
104 | .bank_width = 32, | 104 | .bank_width = 32, |
105 | }; | 105 | }; |
106 | 106 | ||
107 | static struct __initdata platform_device omap7xx_gpio2 = { | 107 | static struct platform_device omap7xx_gpio2 = { |
108 | .name = "omap_gpio", | 108 | .name = "omap_gpio", |
109 | .id = 2, | 109 | .id = 2, |
110 | .dev = { | 110 | .dev = { |
@@ -133,7 +133,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { | |||
133 | .bank_width = 32, | 133 | .bank_width = 32, |
134 | }; | 134 | }; |
135 | 135 | ||
136 | static struct __initdata platform_device omap7xx_gpio3 = { | 136 | static struct platform_device omap7xx_gpio3 = { |
137 | .name = "omap_gpio", | 137 | .name = "omap_gpio", |
138 | .id = 3, | 138 | .id = 3, |
139 | .dev = { | 139 | .dev = { |
@@ -162,7 +162,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { | |||
162 | .bank_width = 32, | 162 | .bank_width = 32, |
163 | }; | 163 | }; |
164 | 164 | ||
165 | static struct __initdata platform_device omap7xx_gpio4 = { | 165 | static struct platform_device omap7xx_gpio4 = { |
166 | .name = "omap_gpio", | 166 | .name = "omap_gpio", |
167 | .id = 4, | 167 | .id = 4, |
168 | .dev = { | 168 | .dev = { |
@@ -191,7 +191,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { | |||
191 | .bank_width = 32, | 191 | .bank_width = 32, |
192 | }; | 192 | }; |
193 | 193 | ||
194 | static struct __initdata platform_device omap7xx_gpio5 = { | 194 | static struct platform_device omap7xx_gpio5 = { |
195 | .name = "omap_gpio", | 195 | .name = "omap_gpio", |
196 | .id = 5, | 196 | .id = 5, |
197 | .dev = { | 197 | .dev = { |
@@ -220,7 +220,7 @@ static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { | |||
220 | .bank_width = 32, | 220 | .bank_width = 32, |
221 | }; | 221 | }; |
222 | 222 | ||
223 | static struct __initdata platform_device omap7xx_gpio6 = { | 223 | static struct platform_device omap7xx_gpio6 = { |
224 | .name = "omap_gpio", | 224 | .name = "omap_gpio", |
225 | .id = 6, | 225 | .id = 6, |
226 | .dev = { | 226 | .dev = { |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 6140290721a0..bdb24db36004 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
@@ -538,7 +538,7 @@ static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = | |||
538 | .subdev_board_info = &rx51_si4713_board_info, | 538 | .subdev_board_info = &rx51_si4713_board_info, |
539 | }; | 539 | }; |
540 | 540 | ||
541 | static struct platform_device rx51_si4713_dev __initdata_or_module = { | 541 | static struct platform_device rx51_si4713_dev = { |
542 | .name = "radio-si4713", | 542 | .name = "radio-si4713", |
543 | .id = -1, | 543 | .id = -1, |
544 | .dev = { | 544 | .dev = { |
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 0c0505b025cb..140711db6c89 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c | |||
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) | |||
95 | 95 | ||
96 | static struct clk clk_erefclk = { | 96 | static struct clk clk_erefclk = { |
97 | .name = "erefclk", | 97 | .name = "erefclk", |
98 | .id = -1, | ||
99 | }; | 98 | }; |
100 | 99 | ||
101 | static struct clk clk_urefclk = { | 100 | static struct clk clk_urefclk = { |
102 | .name = "urefclk", | 101 | .name = "urefclk", |
103 | .id = -1, | ||
104 | }; | 102 | }; |
105 | 103 | ||
106 | static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) | 104 | static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) |
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) | |||
122 | 120 | ||
123 | static struct clk clk_usysclk = { | 121 | static struct clk clk_usysclk = { |
124 | .name = "usysclk", | 122 | .name = "usysclk", |
125 | .id = -1, | ||
126 | .parent = &clk_xtal, | 123 | .parent = &clk_xtal, |
127 | .ops = &(struct clk_ops) { | 124 | .ops = &(struct clk_ops) { |
128 | .set_parent = s3c2412_setparent_usysclk, | 125 | .set_parent = s3c2412_setparent_usysclk, |
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = { | |||
132 | static struct clk clk_mrefclk = { | 129 | static struct clk clk_mrefclk = { |
133 | .name = "mrefclk", | 130 | .name = "mrefclk", |
134 | .parent = &clk_xtal, | 131 | .parent = &clk_xtal, |
135 | .id = -1, | ||
136 | }; | 132 | }; |
137 | 133 | ||
138 | static struct clk clk_mdivclk = { | 134 | static struct clk clk_mdivclk = { |
139 | .name = "mdivclk", | 135 | .name = "mdivclk", |
140 | .parent = &clk_xtal, | 136 | .parent = &clk_xtal, |
141 | .id = -1, | ||
142 | }; | 137 | }; |
143 | 138 | ||
144 | static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) | 139 | static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) |
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) | |||
200 | 195 | ||
201 | static struct clk clk_usbsrc = { | 196 | static struct clk clk_usbsrc = { |
202 | .name = "usbsrc", | 197 | .name = "usbsrc", |
203 | .id = -1, | ||
204 | .ops = &(struct clk_ops) { | 198 | .ops = &(struct clk_ops) { |
205 | .get_rate = s3c2412_getrate_usbsrc, | 199 | .get_rate = s3c2412_getrate_usbsrc, |
206 | .set_rate = s3c2412_setrate_usbsrc, | 200 | .set_rate = s3c2412_setrate_usbsrc, |
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) | |||
228 | 222 | ||
229 | static struct clk clk_msysclk = { | 223 | static struct clk clk_msysclk = { |
230 | .name = "msysclk", | 224 | .name = "msysclk", |
231 | .id = -1, | ||
232 | .ops = &(struct clk_ops) { | 225 | .ops = &(struct clk_ops) { |
233 | .set_parent = s3c2412_setparent_msysclk, | 226 | .set_parent = s3c2412_setparent_msysclk, |
234 | }, | 227 | }, |
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) | |||
268 | 261 | ||
269 | static struct clk clk_armclk = { | 262 | static struct clk clk_armclk = { |
270 | .name = "armclk", | 263 | .name = "armclk", |
271 | .id = -1, | ||
272 | .parent = &clk_msysclk, | 264 | .parent = &clk_msysclk, |
273 | .ops = &(struct clk_ops) { | 265 | .ops = &(struct clk_ops) { |
274 | .set_parent = s3c2412_setparent_armclk, | 266 | .set_parent = s3c2412_setparent_armclk, |
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) | |||
344 | 336 | ||
345 | static struct clk clk_uart = { | 337 | static struct clk clk_uart = { |
346 | .name = "uartclk", | 338 | .name = "uartclk", |
347 | .id = -1, | ||
348 | .ops = &(struct clk_ops) { | 339 | .ops = &(struct clk_ops) { |
349 | .get_rate = s3c2412_getrate_uart, | 340 | .get_rate = s3c2412_getrate_uart, |
350 | .set_rate = s3c2412_setrate_uart, | 341 | .set_rate = s3c2412_setrate_uart, |
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) | |||
397 | 388 | ||
398 | static struct clk clk_i2s = { | 389 | static struct clk clk_i2s = { |
399 | .name = "i2sclk", | 390 | .name = "i2sclk", |
400 | .id = -1, | ||
401 | .ops = &(struct clk_ops) { | 391 | .ops = &(struct clk_ops) { |
402 | .get_rate = s3c2412_getrate_i2s, | 392 | .get_rate = s3c2412_getrate_i2s, |
403 | .set_rate = s3c2412_setrate_i2s, | 393 | .set_rate = s3c2412_setrate_i2s, |
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) | |||
449 | 439 | ||
450 | static struct clk clk_cam = { | 440 | static struct clk clk_cam = { |
451 | .name = "camif-upll", /* same as 2440 name */ | 441 | .name = "camif-upll", /* same as 2440 name */ |
452 | .id = -1, | ||
453 | .ops = &(struct clk_ops) { | 442 | .ops = &(struct clk_ops) { |
454 | .get_rate = s3c2412_getrate_cam, | 443 | .get_rate = s3c2412_getrate_cam, |
455 | .set_rate = s3c2412_setrate_cam, | 444 | .set_rate = s3c2412_setrate_cam, |
@@ -463,37 +452,31 @@ static struct clk clk_cam = { | |||
463 | static struct clk init_clocks_disable[] = { | 452 | static struct clk init_clocks_disable[] = { |
464 | { | 453 | { |
465 | .name = "nand", | 454 | .name = "nand", |
466 | .id = -1, | ||
467 | .parent = &clk_h, | 455 | .parent = &clk_h, |
468 | .enable = s3c2412_clkcon_enable, | 456 | .enable = s3c2412_clkcon_enable, |
469 | .ctrlbit = S3C2412_CLKCON_NAND, | 457 | .ctrlbit = S3C2412_CLKCON_NAND, |
470 | }, { | 458 | }, { |
471 | .name = "sdi", | 459 | .name = "sdi", |
472 | .id = -1, | ||
473 | .parent = &clk_p, | 460 | .parent = &clk_p, |
474 | .enable = s3c2412_clkcon_enable, | 461 | .enable = s3c2412_clkcon_enable, |
475 | .ctrlbit = S3C2412_CLKCON_SDI, | 462 | .ctrlbit = S3C2412_CLKCON_SDI, |
476 | }, { | 463 | }, { |
477 | .name = "adc", | 464 | .name = "adc", |
478 | .id = -1, | ||
479 | .parent = &clk_p, | 465 | .parent = &clk_p, |
480 | .enable = s3c2412_clkcon_enable, | 466 | .enable = s3c2412_clkcon_enable, |
481 | .ctrlbit = S3C2412_CLKCON_ADC, | 467 | .ctrlbit = S3C2412_CLKCON_ADC, |
482 | }, { | 468 | }, { |
483 | .name = "i2c", | 469 | .name = "i2c", |
484 | .id = -1, | ||
485 | .parent = &clk_p, | 470 | .parent = &clk_p, |
486 | .enable = s3c2412_clkcon_enable, | 471 | .enable = s3c2412_clkcon_enable, |
487 | .ctrlbit = S3C2412_CLKCON_IIC, | 472 | .ctrlbit = S3C2412_CLKCON_IIC, |
488 | }, { | 473 | }, { |
489 | .name = "iis", | 474 | .name = "iis", |
490 | .id = -1, | ||
491 | .parent = &clk_p, | 475 | .parent = &clk_p, |
492 | .enable = s3c2412_clkcon_enable, | 476 | .enable = s3c2412_clkcon_enable, |
493 | .ctrlbit = S3C2412_CLKCON_IIS, | 477 | .ctrlbit = S3C2412_CLKCON_IIS, |
494 | }, { | 478 | }, { |
495 | .name = "spi", | 479 | .name = "spi", |
496 | .id = -1, | ||
497 | .parent = &clk_p, | 480 | .parent = &clk_p, |
498 | .enable = s3c2412_clkcon_enable, | 481 | .enable = s3c2412_clkcon_enable, |
499 | .ctrlbit = S3C2412_CLKCON_SPI, | 482 | .ctrlbit = S3C2412_CLKCON_SPI, |
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = { | |||
503 | static struct clk init_clocks[] = { | 486 | static struct clk init_clocks[] = { |
504 | { | 487 | { |
505 | .name = "dma", | 488 | .name = "dma", |
506 | .id = 0, | ||
507 | .parent = &clk_h, | 489 | .parent = &clk_h, |
508 | .enable = s3c2412_clkcon_enable, | 490 | .enable = s3c2412_clkcon_enable, |
509 | .ctrlbit = S3C2412_CLKCON_DMA0, | 491 | .ctrlbit = S3C2412_CLKCON_DMA0, |
510 | }, { | 492 | }, { |
511 | .name = "dma", | 493 | .name = "dma", |
512 | .id = 1, | ||
513 | .parent = &clk_h, | 494 | .parent = &clk_h, |
514 | .enable = s3c2412_clkcon_enable, | 495 | .enable = s3c2412_clkcon_enable, |
515 | .ctrlbit = S3C2412_CLKCON_DMA1, | 496 | .ctrlbit = S3C2412_CLKCON_DMA1, |
516 | }, { | 497 | }, { |
517 | .name = "dma", | 498 | .name = "dma", |
518 | .id = 2, | ||
519 | .parent = &clk_h, | 499 | .parent = &clk_h, |
520 | .enable = s3c2412_clkcon_enable, | 500 | .enable = s3c2412_clkcon_enable, |
521 | .ctrlbit = S3C2412_CLKCON_DMA2, | 501 | .ctrlbit = S3C2412_CLKCON_DMA2, |
522 | }, { | 502 | }, { |
523 | .name = "dma", | 503 | .name = "dma", |
524 | .id = 3, | ||
525 | .parent = &clk_h, | 504 | .parent = &clk_h, |
526 | .enable = s3c2412_clkcon_enable, | 505 | .enable = s3c2412_clkcon_enable, |
527 | .ctrlbit = S3C2412_CLKCON_DMA3, | 506 | .ctrlbit = S3C2412_CLKCON_DMA3, |
528 | }, { | 507 | }, { |
529 | .name = "lcd", | 508 | .name = "lcd", |
530 | .id = -1, | ||
531 | .parent = &clk_h, | 509 | .parent = &clk_h, |
532 | .enable = s3c2412_clkcon_enable, | 510 | .enable = s3c2412_clkcon_enable, |
533 | .ctrlbit = S3C2412_CLKCON_LCDC, | 511 | .ctrlbit = S3C2412_CLKCON_LCDC, |
534 | }, { | 512 | }, { |
535 | .name = "gpio", | 513 | .name = "gpio", |
536 | .id = -1, | ||
537 | .parent = &clk_p, | 514 | .parent = &clk_p, |
538 | .enable = s3c2412_clkcon_enable, | 515 | .enable = s3c2412_clkcon_enable, |
539 | .ctrlbit = S3C2412_CLKCON_GPIO, | 516 | .ctrlbit = S3C2412_CLKCON_GPIO, |
540 | }, { | 517 | }, { |
541 | .name = "usb-host", | 518 | .name = "usb-host", |
542 | .id = -1, | ||
543 | .parent = &clk_h, | 519 | .parent = &clk_h, |
544 | .enable = s3c2412_clkcon_enable, | 520 | .enable = s3c2412_clkcon_enable, |
545 | .ctrlbit = S3C2412_CLKCON_USBH, | 521 | .ctrlbit = S3C2412_CLKCON_USBH, |
546 | }, { | 522 | }, { |
547 | .name = "usb-device", | 523 | .name = "usb-device", |
548 | .id = -1, | ||
549 | .parent = &clk_h, | 524 | .parent = &clk_h, |
550 | .enable = s3c2412_clkcon_enable, | 525 | .enable = s3c2412_clkcon_enable, |
551 | .ctrlbit = S3C2412_CLKCON_USBD, | 526 | .ctrlbit = S3C2412_CLKCON_USBD, |
552 | }, { | 527 | }, { |
553 | .name = "timers", | 528 | .name = "timers", |
554 | .id = -1, | ||
555 | .parent = &clk_p, | 529 | .parent = &clk_p, |
556 | .enable = s3c2412_clkcon_enable, | 530 | .enable = s3c2412_clkcon_enable, |
557 | .ctrlbit = S3C2412_CLKCON_PWMT, | 531 | .ctrlbit = S3C2412_CLKCON_PWMT, |
558 | }, { | 532 | }, { |
559 | .name = "uart", | 533 | .name = "uart", |
560 | .id = 0, | 534 | .devname = "s3c2412-uart.0", |
561 | .parent = &clk_p, | 535 | .parent = &clk_p, |
562 | .enable = s3c2412_clkcon_enable, | 536 | .enable = s3c2412_clkcon_enable, |
563 | .ctrlbit = S3C2412_CLKCON_UART0, | 537 | .ctrlbit = S3C2412_CLKCON_UART0, |
564 | }, { | 538 | }, { |
565 | .name = "uart", | 539 | .name = "uart", |
566 | .id = 1, | 540 | .devname = "s3c2412-uart.1", |
567 | .parent = &clk_p, | 541 | .parent = &clk_p, |
568 | .enable = s3c2412_clkcon_enable, | 542 | .enable = s3c2412_clkcon_enable, |
569 | .ctrlbit = S3C2412_CLKCON_UART1, | 543 | .ctrlbit = S3C2412_CLKCON_UART1, |
570 | }, { | 544 | }, { |
571 | .name = "uart", | 545 | .name = "uart", |
572 | .id = 2, | 546 | .devname = "s3c2412-uart.2", |
573 | .parent = &clk_p, | 547 | .parent = &clk_p, |
574 | .enable = s3c2412_clkcon_enable, | 548 | .enable = s3c2412_clkcon_enable, |
575 | .ctrlbit = S3C2412_CLKCON_UART2, | 549 | .ctrlbit = S3C2412_CLKCON_UART2, |
576 | }, { | 550 | }, { |
577 | .name = "rtc", | 551 | .name = "rtc", |
578 | .id = -1, | ||
579 | .parent = &clk_p, | 552 | .parent = &clk_p, |
580 | .enable = s3c2412_clkcon_enable, | 553 | .enable = s3c2412_clkcon_enable, |
581 | .ctrlbit = S3C2412_CLKCON_RTC, | 554 | .ctrlbit = S3C2412_CLKCON_RTC, |
582 | }, { | 555 | }, { |
583 | .name = "watchdog", | 556 | .name = "watchdog", |
584 | .id = -1, | ||
585 | .parent = &clk_p, | 557 | .parent = &clk_p, |
586 | .ctrlbit = 0, | 558 | .ctrlbit = 0, |
587 | }, { | 559 | }, { |
588 | .name = "usb-bus-gadget", | 560 | .name = "usb-bus-gadget", |
589 | .id = -1, | ||
590 | .parent = &clk_usb_bus, | 561 | .parent = &clk_usb_bus, |
591 | .enable = s3c2412_clkcon_enable, | 562 | .enable = s3c2412_clkcon_enable, |
592 | .ctrlbit = S3C2412_CLKCON_USB_DEV48, | 563 | .ctrlbit = S3C2412_CLKCON_USB_DEV48, |
593 | }, { | 564 | }, { |
594 | .name = "usb-bus-host", | 565 | .name = "usb-bus-host", |
595 | .id = -1, | ||
596 | .parent = &clk_usb_bus, | 566 | .parent = &clk_usb_bus, |
597 | .enable = s3c2412_clkcon_enable, | 567 | .enable = s3c2412_clkcon_enable, |
598 | .ctrlbit = S3C2412_CLKCON_USB_HOST48, | 568 | .ctrlbit = S3C2412_CLKCON_USB_HOST48, |
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 3b02d8506e25..21a5e81f0ab5 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c | |||
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = { | |||
42 | [0] = { | 42 | [0] = { |
43 | .clk = { | 43 | .clk = { |
44 | .name = "hsmmc-div", | 44 | .name = "hsmmc-div", |
45 | .id = 0, | 45 | .devname = "s3c-sdhci.0", |
46 | .parent = &clk_esysclk.clk, | 46 | .parent = &clk_esysclk.clk, |
47 | }, | 47 | }, |
48 | .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, | 48 | .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, |
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = { | |||
50 | [1] = { | 50 | [1] = { |
51 | .clk = { | 51 | .clk = { |
52 | .name = "hsmmc-div", | 52 | .name = "hsmmc-div", |
53 | .id = 1, | 53 | .devname = "s3c-sdhci.1", |
54 | .parent = &clk_esysclk.clk, | 54 | .parent = &clk_esysclk.clk, |
55 | }, | 55 | }, |
56 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, | 56 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, |
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = { | |||
60 | static struct clksrc_clk hsmmc_mux[] = { | 60 | static struct clksrc_clk hsmmc_mux[] = { |
61 | [0] = { | 61 | [0] = { |
62 | .clk = { | 62 | .clk = { |
63 | .id = 0, | ||
64 | .name = "hsmmc-if", | 63 | .name = "hsmmc-if", |
64 | .devname = "s3c-sdhci.0", | ||
65 | .ctrlbit = (1 << 6), | 65 | .ctrlbit = (1 << 6), |
66 | .enable = s3c2443_clkcon_enable_s, | 66 | .enable = s3c2443_clkcon_enable_s, |
67 | }, | 67 | }, |
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = { | |||
76 | }, | 76 | }, |
77 | [1] = { | 77 | [1] = { |
78 | .clk = { | 78 | .clk = { |
79 | .id = 1, | ||
80 | .name = "hsmmc-if", | 79 | .name = "hsmmc-if", |
80 | .devname = "s3c-sdhci.1", | ||
81 | .ctrlbit = (1 << 12), | 81 | .ctrlbit = (1 << 12), |
82 | .enable = s3c2443_clkcon_enable_s, | 82 | .enable = s3c2443_clkcon_enable_s, |
83 | }, | 83 | }, |
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = { | |||
94 | 94 | ||
95 | static struct clk hsmmc0_clk = { | 95 | static struct clk hsmmc0_clk = { |
96 | .name = "hsmmc", | 96 | .name = "hsmmc", |
97 | .id = 0, | 97 | .devname = "s3c-sdhci.0", |
98 | .parent = &clk_h, | 98 | .parent = &clk_h, |
99 | .enable = s3c2443_clkcon_enable_h, | 99 | .enable = s3c2443_clkcon_enable_h, |
100 | .ctrlbit = S3C2416_HCLKCON_HSMMC0, | 100 | .ctrlbit = S3C2416_HCLKCON_HSMMC0, |
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index 3dc2426e2345..554e0d3ec70b 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c | |||
@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate) | |||
90 | 90 | ||
91 | static struct clk s3c2440_clk_cam = { | 91 | static struct clk s3c2440_clk_cam = { |
92 | .name = "camif", | 92 | .name = "camif", |
93 | .id = -1, | ||
94 | .enable = s3c2410_clkcon_enable, | 93 | .enable = s3c2410_clkcon_enable, |
95 | .ctrlbit = S3C2440_CLKCON_CAMERA, | 94 | .ctrlbit = S3C2440_CLKCON_CAMERA, |
96 | }; | 95 | }; |
97 | 96 | ||
98 | static struct clk s3c2440_clk_cam_upll = { | 97 | static struct clk s3c2440_clk_cam_upll = { |
99 | .name = "camif-upll", | 98 | .name = "camif-upll", |
100 | .id = -1, | ||
101 | .ops = &(struct clk_ops) { | 99 | .ops = &(struct clk_ops) { |
102 | .set_rate = s3c2440_camif_upll_setrate, | 100 | .set_rate = s3c2440_camif_upll_setrate, |
103 | .round_rate = s3c2440_camif_upll_round, | 101 | .round_rate = s3c2440_camif_upll_round, |
@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = { | |||
106 | 104 | ||
107 | static struct clk s3c2440_clk_ac97 = { | 105 | static struct clk s3c2440_clk_ac97 = { |
108 | .name = "ac97", | 106 | .name = "ac97", |
109 | .id = -1, | ||
110 | .enable = s3c2410_clkcon_enable, | 107 | .enable = s3c2410_clkcon_enable, |
111 | .ctrlbit = S3C2440_CLKCON_CAMERA, | 108 | .ctrlbit = S3C2440_CLKCON_CAMERA, |
112 | }; | 109 | }; |
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index dd3120df09fe..fc2dc0b3d4fe 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c | |||
@@ -552,7 +552,7 @@ struct mini2440_features_t { | |||
552 | struct platform_device *optional[8]; | 552 | struct platform_device *optional[8]; |
553 | }; | 553 | }; |
554 | 554 | ||
555 | static void mini2440_parse_features( | 555 | static void __init mini2440_parse_features( |
556 | struct mini2440_features_t * features, | 556 | struct mini2440_features_t * features, |
557 | const char * features_str ) | 557 | const char * features_str ) |
558 | { | 558 | { |
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index f4ec6d5715c8..a1a7176675b9 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c | |||
@@ -59,7 +59,6 @@ | |||
59 | 59 | ||
60 | static struct clk clk_i2s_ext = { | 60 | static struct clk clk_i2s_ext = { |
61 | .name = "i2s-ext", | 61 | .name = "i2s-ext", |
62 | .id = -1, | ||
63 | }; | 62 | }; |
64 | 63 | ||
65 | /* armdiv | 64 | /* armdiv |
@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) | |||
139 | 138 | ||
140 | static struct clk clk_armdiv = { | 139 | static struct clk clk_armdiv = { |
141 | .name = "armdiv", | 140 | .name = "armdiv", |
142 | .id = -1, | ||
143 | .parent = &clk_msysclk.clk, | 141 | .parent = &clk_msysclk.clk, |
144 | .ops = &(struct clk_ops) { | 142 | .ops = &(struct clk_ops) { |
145 | .round_rate = s3c2443_armclk_roundrate, | 143 | .round_rate = s3c2443_armclk_roundrate, |
@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = { | |||
160 | static struct clksrc_clk clk_arm = { | 158 | static struct clksrc_clk clk_arm = { |
161 | .clk = { | 159 | .clk = { |
162 | .name = "armclk", | 160 | .name = "armclk", |
163 | .id = -1, | ||
164 | }, | 161 | }, |
165 | .sources = &(struct clksrc_sources) { | 162 | .sources = &(struct clksrc_sources) { |
166 | .sources = clk_arm_sources, | 163 | .sources = clk_arm_sources, |
@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = { | |||
177 | static struct clksrc_clk clk_hsspi = { | 174 | static struct clksrc_clk clk_hsspi = { |
178 | .clk = { | 175 | .clk = { |
179 | .name = "hsspi", | 176 | .name = "hsspi", |
180 | .id = -1, | ||
181 | .parent = &clk_esysclk.clk, | 177 | .parent = &clk_esysclk.clk, |
182 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, | 178 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, |
183 | .enable = s3c2443_clkcon_enable_s, | 179 | .enable = s3c2443_clkcon_enable_s, |
@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = { | |||
196 | static struct clksrc_clk clk_hsmmc_div = { | 192 | static struct clksrc_clk clk_hsmmc_div = { |
197 | .clk = { | 193 | .clk = { |
198 | .name = "hsmmc-div", | 194 | .name = "hsmmc-div", |
199 | .id = 1, | 195 | .devname = "s3c-sdhci.1", |
200 | .parent = &clk_esysclk.clk, | 196 | .parent = &clk_esysclk.clk, |
201 | }, | 197 | }, |
202 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, | 198 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, |
@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable) | |||
231 | 227 | ||
232 | static struct clk clk_hsmmc = { | 228 | static struct clk clk_hsmmc = { |
233 | .name = "hsmmc-if", | 229 | .name = "hsmmc-if", |
234 | .id = 1, | 230 | .devname = "s3c-sdhci.1", |
235 | .parent = &clk_hsmmc_div.clk, | 231 | .parent = &clk_hsmmc_div.clk, |
236 | .enable = s3c2443_enable_hsmmc, | 232 | .enable = s3c2443_enable_hsmmc, |
237 | .ops = &(struct clk_ops) { | 233 | .ops = &(struct clk_ops) { |
@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = { | |||
248 | static struct clksrc_clk clk_i2s_eplldiv = { | 244 | static struct clksrc_clk clk_i2s_eplldiv = { |
249 | .clk = { | 245 | .clk = { |
250 | .name = "i2s-eplldiv", | 246 | .name = "i2s-eplldiv", |
251 | .id = -1, | ||
252 | .parent = &clk_esysclk.clk, | 247 | .parent = &clk_esysclk.clk, |
253 | }, | 248 | }, |
254 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, | 249 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, |
@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = { | |||
271 | static struct clksrc_clk clk_i2s = { | 266 | static struct clksrc_clk clk_i2s = { |
272 | .clk = { | 267 | .clk = { |
273 | .name = "i2s-if", | 268 | .name = "i2s-if", |
274 | .id = -1, | ||
275 | .ctrlbit = S3C2443_SCLKCON_I2SCLK, | 269 | .ctrlbit = S3C2443_SCLKCON_I2SCLK, |
276 | .enable = s3c2443_clkcon_enable_s, | 270 | .enable = s3c2443_clkcon_enable_s, |
277 | 271 | ||
@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = { | |||
288 | static struct clk init_clocks_off[] = { | 282 | static struct clk init_clocks_off[] = { |
289 | { | 283 | { |
290 | .name = "sdi", | 284 | .name = "sdi", |
291 | .id = -1, | ||
292 | .parent = &clk_p, | 285 | .parent = &clk_p, |
293 | .enable = s3c2443_clkcon_enable_p, | 286 | .enable = s3c2443_clkcon_enable_p, |
294 | .ctrlbit = S3C2443_PCLKCON_SDI, | 287 | .ctrlbit = S3C2443_PCLKCON_SDI, |
295 | }, { | 288 | }, { |
296 | .name = "iis", | 289 | .name = "iis", |
297 | .id = -1, | ||
298 | .parent = &clk_p, | 290 | .parent = &clk_p, |
299 | .enable = s3c2443_clkcon_enable_p, | 291 | .enable = s3c2443_clkcon_enable_p, |
300 | .ctrlbit = S3C2443_PCLKCON_IIS, | 292 | .ctrlbit = S3C2443_PCLKCON_IIS, |
301 | }, { | 293 | }, { |
302 | .name = "spi", | 294 | .name = "spi", |
303 | .id = 0, | 295 | .devname = "s3c2410-spi.0", |
304 | .parent = &clk_p, | 296 | .parent = &clk_p, |
305 | .enable = s3c2443_clkcon_enable_p, | 297 | .enable = s3c2443_clkcon_enable_p, |
306 | .ctrlbit = S3C2443_PCLKCON_SPI0, | 298 | .ctrlbit = S3C2443_PCLKCON_SPI0, |
307 | }, { | 299 | }, { |
308 | .name = "spi", | 300 | .name = "spi", |
309 | .id = 1, | 301 | .devname = "s3c2410-spi.1", |
310 | .parent = &clk_p, | 302 | .parent = &clk_p, |
311 | .enable = s3c2443_clkcon_enable_p, | 303 | .enable = s3c2443_clkcon_enable_p, |
312 | .ctrlbit = S3C2443_PCLKCON_SPI1, | 304 | .ctrlbit = S3C2443_PCLKCON_SPI1, |
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index e4177e22557b..fdc89fc3b464 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig | |||
@@ -142,6 +142,7 @@ config MACH_SMDK6410 | |||
142 | select S3C_DEV_USB_HOST | 142 | select S3C_DEV_USB_HOST |
143 | select S3C_DEV_USB_HSOTG | 143 | select S3C_DEV_USB_HSOTG |
144 | select S3C_DEV_WDT | 144 | select S3C_DEV_WDT |
145 | select SAMSUNG_DEV_BACKLIGHT | ||
145 | select SAMSUNG_DEV_KEYPAD | 146 | select SAMSUNG_DEV_KEYPAD |
146 | select SAMSUNG_DEV_PWM | 147 | select SAMSUNG_DEV_PWM |
147 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | 148 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index fdfc4d5e37a1..8cf39e33579e 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c | |||
@@ -39,7 +39,6 @@ | |||
39 | 39 | ||
40 | static struct clk clk_ext_xtal_mux = { | 40 | static struct clk clk_ext_xtal_mux = { |
41 | .name = "ext_xtal", | 41 | .name = "ext_xtal", |
42 | .id = -1, | ||
43 | }; | 42 | }; |
44 | 43 | ||
45 | #define clk_fin_apll clk_ext_xtal_mux | 44 | #define clk_fin_apll clk_ext_xtal_mux |
@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = { | |||
51 | 50 | ||
52 | struct clk clk_h2 = { | 51 | struct clk clk_h2 = { |
53 | .name = "hclk2", | 52 | .name = "hclk2", |
54 | .id = -1, | ||
55 | .rate = 0, | 53 | .rate = 0, |
56 | }; | 54 | }; |
57 | 55 | ||
58 | struct clk clk_27m = { | 56 | struct clk clk_27m = { |
59 | .name = "clk_27m", | 57 | .name = "clk_27m", |
60 | .id = -1, | ||
61 | .rate = 27000000, | 58 | .rate = 27000000, |
62 | }; | 59 | }; |
63 | 60 | ||
@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable) | |||
83 | 80 | ||
84 | struct clk clk_48m = { | 81 | struct clk clk_48m = { |
85 | .name = "clk_48m", | 82 | .name = "clk_48m", |
86 | .id = -1, | ||
87 | .rate = 48000000, | 83 | .rate = 48000000, |
88 | .enable = clk_48m_ctrl, | 84 | .enable = clk_48m_ctrl, |
89 | }; | 85 | }; |
90 | 86 | ||
91 | struct clk clk_xusbxti = { | 87 | struct clk clk_xusbxti = { |
92 | .name = "xusbxti", | 88 | .name = "xusbxti", |
93 | .id = -1, | ||
94 | .rate = 48000000, | 89 | .rate = 48000000, |
95 | }; | 90 | }; |
96 | 91 | ||
@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable) | |||
130 | static struct clk init_clocks_off[] = { | 125 | static struct clk init_clocks_off[] = { |
131 | { | 126 | { |
132 | .name = "nand", | 127 | .name = "nand", |
133 | .id = -1, | ||
134 | .parent = &clk_h, | 128 | .parent = &clk_h, |
135 | }, { | 129 | }, { |
136 | .name = "rtc", | 130 | .name = "rtc", |
137 | .id = -1, | ||
138 | .parent = &clk_p, | 131 | .parent = &clk_p, |
139 | .enable = s3c64xx_pclk_ctrl, | 132 | .enable = s3c64xx_pclk_ctrl, |
140 | .ctrlbit = S3C_CLKCON_PCLK_RTC, | 133 | .ctrlbit = S3C_CLKCON_PCLK_RTC, |
141 | }, { | 134 | }, { |
142 | .name = "adc", | 135 | .name = "adc", |
143 | .id = -1, | ||
144 | .parent = &clk_p, | 136 | .parent = &clk_p, |
145 | .enable = s3c64xx_pclk_ctrl, | 137 | .enable = s3c64xx_pclk_ctrl, |
146 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, | 138 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, |
147 | }, { | 139 | }, { |
148 | .name = "i2c", | 140 | .name = "i2c", |
149 | .id = -1, | ||
150 | .parent = &clk_p, | 141 | .parent = &clk_p, |
151 | .enable = s3c64xx_pclk_ctrl, | 142 | .enable = s3c64xx_pclk_ctrl, |
152 | .ctrlbit = S3C_CLKCON_PCLK_IIC, | 143 | .ctrlbit = S3C_CLKCON_PCLK_IIC, |
153 | }, { | 144 | }, { |
154 | .name = "i2c", | 145 | .name = "i2c", |
155 | .id = 1, | 146 | .devname = "s3c2440-i2c.1", |
156 | .parent = &clk_p, | 147 | .parent = &clk_p, |
157 | .enable = s3c64xx_pclk_ctrl, | 148 | .enable = s3c64xx_pclk_ctrl, |
158 | .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, | 149 | .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, |
159 | }, { | 150 | }, { |
160 | .name = "iis", | 151 | .name = "iis", |
161 | .id = 0, | 152 | .devname = "samsung-i2s.0", |
162 | .parent = &clk_p, | 153 | .parent = &clk_p, |
163 | .enable = s3c64xx_pclk_ctrl, | 154 | .enable = s3c64xx_pclk_ctrl, |
164 | .ctrlbit = S3C_CLKCON_PCLK_IIS0, | 155 | .ctrlbit = S3C_CLKCON_PCLK_IIS0, |
165 | }, { | 156 | }, { |
166 | .name = "iis", | 157 | .name = "iis", |
167 | .id = 1, | 158 | .devname = "samsung-i2s.1", |
168 | .parent = &clk_p, | 159 | .parent = &clk_p, |
169 | .enable = s3c64xx_pclk_ctrl, | 160 | .enable = s3c64xx_pclk_ctrl, |
170 | .ctrlbit = S3C_CLKCON_PCLK_IIS1, | 161 | .ctrlbit = S3C_CLKCON_PCLK_IIS1, |
171 | }, { | 162 | }, { |
172 | #ifdef CONFIG_CPU_S3C6410 | 163 | #ifdef CONFIG_CPU_S3C6410 |
173 | .name = "iis", | 164 | .name = "iis", |
174 | .id = -1, /* There's only one IISv4 port */ | ||
175 | .parent = &clk_p, | 165 | .parent = &clk_p, |
176 | .enable = s3c64xx_pclk_ctrl, | 166 | .enable = s3c64xx_pclk_ctrl, |
177 | .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, | 167 | .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, |
178 | }, { | 168 | }, { |
179 | #endif | 169 | #endif |
180 | .name = "keypad", | 170 | .name = "keypad", |
181 | .id = -1, | ||
182 | .parent = &clk_p, | 171 | .parent = &clk_p, |
183 | .enable = s3c64xx_pclk_ctrl, | 172 | .enable = s3c64xx_pclk_ctrl, |
184 | .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, | 173 | .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, |
185 | }, { | 174 | }, { |
186 | .name = "spi", | 175 | .name = "spi", |
187 | .id = 0, | 176 | .devname = "s3c64xx-spi.0", |
188 | .parent = &clk_p, | 177 | .parent = &clk_p, |
189 | .enable = s3c64xx_pclk_ctrl, | 178 | .enable = s3c64xx_pclk_ctrl, |
190 | .ctrlbit = S3C_CLKCON_PCLK_SPI0, | 179 | .ctrlbit = S3C_CLKCON_PCLK_SPI0, |
191 | }, { | 180 | }, { |
192 | .name = "spi", | 181 | .name = "spi", |
193 | .id = 1, | 182 | .devname = "s3c64xx-spi.1", |
194 | .parent = &clk_p, | 183 | .parent = &clk_p, |
195 | .enable = s3c64xx_pclk_ctrl, | 184 | .enable = s3c64xx_pclk_ctrl, |
196 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, | 185 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, |
197 | }, { | 186 | }, { |
198 | .name = "spi_48m", | 187 | .name = "spi_48m", |
199 | .id = 0, | 188 | .devname = "s3c64xx-spi.0", |
200 | .parent = &clk_48m, | 189 | .parent = &clk_48m, |
201 | .enable = s3c64xx_sclk_ctrl, | 190 | .enable = s3c64xx_sclk_ctrl, |
202 | .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, | 191 | .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, |
203 | }, { | 192 | }, { |
204 | .name = "spi_48m", | 193 | .name = "spi_48m", |
205 | .id = 1, | 194 | .devname = "s3c64xx-spi.1", |
206 | .parent = &clk_48m, | 195 | .parent = &clk_48m, |
207 | .enable = s3c64xx_sclk_ctrl, | 196 | .enable = s3c64xx_sclk_ctrl, |
208 | .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, | 197 | .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, |
209 | }, { | 198 | }, { |
210 | .name = "48m", | 199 | .name = "48m", |
211 | .id = 0, | 200 | .devname = "s3c-sdhci.0", |
212 | .parent = &clk_48m, | 201 | .parent = &clk_48m, |
213 | .enable = s3c64xx_sclk_ctrl, | 202 | .enable = s3c64xx_sclk_ctrl, |
214 | .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, | 203 | .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, |
215 | }, { | 204 | }, { |
216 | .name = "48m", | 205 | .name = "48m", |
217 | .id = 1, | 206 | .devname = "s3c-sdhci.1", |
218 | .parent = &clk_48m, | 207 | .parent = &clk_48m, |
219 | .enable = s3c64xx_sclk_ctrl, | 208 | .enable = s3c64xx_sclk_ctrl, |
220 | .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, | 209 | .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, |
221 | }, { | 210 | }, { |
222 | .name = "48m", | 211 | .name = "48m", |
223 | .id = 2, | 212 | .devname = "s3c-sdhci.2", |
224 | .parent = &clk_48m, | 213 | .parent = &clk_48m, |
225 | .enable = s3c64xx_sclk_ctrl, | 214 | .enable = s3c64xx_sclk_ctrl, |
226 | .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, | 215 | .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, |
227 | }, { | 216 | }, { |
228 | .name = "dma0", | 217 | .name = "dma0", |
229 | .id = -1, | ||
230 | .parent = &clk_h, | 218 | .parent = &clk_h, |
231 | .enable = s3c64xx_hclk_ctrl, | 219 | .enable = s3c64xx_hclk_ctrl, |
232 | .ctrlbit = S3C_CLKCON_HCLK_DMA0, | 220 | .ctrlbit = S3C_CLKCON_HCLK_DMA0, |
233 | }, { | 221 | }, { |
234 | .name = "dma1", | 222 | .name = "dma1", |
235 | .id = -1, | ||
236 | .parent = &clk_h, | 223 | .parent = &clk_h, |
237 | .enable = s3c64xx_hclk_ctrl, | 224 | .enable = s3c64xx_hclk_ctrl, |
238 | .ctrlbit = S3C_CLKCON_HCLK_DMA1, | 225 | .ctrlbit = S3C_CLKCON_HCLK_DMA1, |
@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = { | |||
242 | static struct clk init_clocks[] = { | 229 | static struct clk init_clocks[] = { |
243 | { | 230 | { |
244 | .name = "lcd", | 231 | .name = "lcd", |
245 | .id = -1, | ||
246 | .parent = &clk_h, | 232 | .parent = &clk_h, |
247 | .enable = s3c64xx_hclk_ctrl, | 233 | .enable = s3c64xx_hclk_ctrl, |
248 | .ctrlbit = S3C_CLKCON_HCLK_LCD, | 234 | .ctrlbit = S3C_CLKCON_HCLK_LCD, |
249 | }, { | 235 | }, { |
250 | .name = "gpio", | 236 | .name = "gpio", |
251 | .id = -1, | ||
252 | .parent = &clk_p, | 237 | .parent = &clk_p, |
253 | .enable = s3c64xx_pclk_ctrl, | 238 | .enable = s3c64xx_pclk_ctrl, |
254 | .ctrlbit = S3C_CLKCON_PCLK_GPIO, | 239 | .ctrlbit = S3C_CLKCON_PCLK_GPIO, |
255 | }, { | 240 | }, { |
256 | .name = "usb-host", | 241 | .name = "usb-host", |
257 | .id = -1, | ||
258 | .parent = &clk_h, | 242 | .parent = &clk_h, |
259 | .enable = s3c64xx_hclk_ctrl, | 243 | .enable = s3c64xx_hclk_ctrl, |
260 | .ctrlbit = S3C_CLKCON_HCLK_UHOST, | 244 | .ctrlbit = S3C_CLKCON_HCLK_UHOST, |
261 | }, { | 245 | }, { |
262 | .name = "hsmmc", | 246 | .name = "hsmmc", |
263 | .id = 0, | 247 | .devname = "s3c-sdhci.0", |
264 | .parent = &clk_h, | 248 | .parent = &clk_h, |
265 | .enable = s3c64xx_hclk_ctrl, | 249 | .enable = s3c64xx_hclk_ctrl, |
266 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, | 250 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, |
267 | }, { | 251 | }, { |
268 | .name = "hsmmc", | 252 | .name = "hsmmc", |
269 | .id = 1, | 253 | .devname = "s3c-sdhci.1", |
270 | .parent = &clk_h, | 254 | .parent = &clk_h, |
271 | .enable = s3c64xx_hclk_ctrl, | 255 | .enable = s3c64xx_hclk_ctrl, |
272 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, | 256 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, |
273 | }, { | 257 | }, { |
274 | .name = "hsmmc", | 258 | .name = "hsmmc", |
275 | .id = 2, | 259 | .devname = "s3c-sdhci.2", |
276 | .parent = &clk_h, | 260 | .parent = &clk_h, |
277 | .enable = s3c64xx_hclk_ctrl, | 261 | .enable = s3c64xx_hclk_ctrl, |
278 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, | 262 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, |
279 | }, { | 263 | }, { |
280 | .name = "otg", | 264 | .name = "otg", |
281 | .id = -1, | ||
282 | .parent = &clk_h, | 265 | .parent = &clk_h, |
283 | .enable = s3c64xx_hclk_ctrl, | 266 | .enable = s3c64xx_hclk_ctrl, |
284 | .ctrlbit = S3C_CLKCON_HCLK_USB, | 267 | .ctrlbit = S3C_CLKCON_HCLK_USB, |
285 | }, { | 268 | }, { |
286 | .name = "timers", | 269 | .name = "timers", |
287 | .id = -1, | ||
288 | .parent = &clk_p, | 270 | .parent = &clk_p, |
289 | .enable = s3c64xx_pclk_ctrl, | 271 | .enable = s3c64xx_pclk_ctrl, |
290 | .ctrlbit = S3C_CLKCON_PCLK_PWM, | 272 | .ctrlbit = S3C_CLKCON_PCLK_PWM, |
291 | }, { | 273 | }, { |
292 | .name = "uart", | 274 | .name = "uart", |
293 | .id = 0, | 275 | .devname = "s3c6400-uart.0", |
294 | .parent = &clk_p, | 276 | .parent = &clk_p, |
295 | .enable = s3c64xx_pclk_ctrl, | 277 | .enable = s3c64xx_pclk_ctrl, |
296 | .ctrlbit = S3C_CLKCON_PCLK_UART0, | 278 | .ctrlbit = S3C_CLKCON_PCLK_UART0, |
297 | }, { | 279 | }, { |
298 | .name = "uart", | 280 | .name = "uart", |
299 | .id = 1, | 281 | .devname = "s3c6400-uart.1", |
300 | .parent = &clk_p, | 282 | .parent = &clk_p, |
301 | .enable = s3c64xx_pclk_ctrl, | 283 | .enable = s3c64xx_pclk_ctrl, |
302 | .ctrlbit = S3C_CLKCON_PCLK_UART1, | 284 | .ctrlbit = S3C_CLKCON_PCLK_UART1, |
303 | }, { | 285 | }, { |
304 | .name = "uart", | 286 | .name = "uart", |
305 | .id = 2, | 287 | .devname = "s3c6400-uart.2", |
306 | .parent = &clk_p, | 288 | .parent = &clk_p, |
307 | .enable = s3c64xx_pclk_ctrl, | 289 | .enable = s3c64xx_pclk_ctrl, |
308 | .ctrlbit = S3C_CLKCON_PCLK_UART2, | 290 | .ctrlbit = S3C_CLKCON_PCLK_UART2, |
309 | }, { | 291 | }, { |
310 | .name = "uart", | 292 | .name = "uart", |
311 | .id = 3, | 293 | .devname = "s3c6400-uart.3", |
312 | .parent = &clk_p, | 294 | .parent = &clk_p, |
313 | .enable = s3c64xx_pclk_ctrl, | 295 | .enable = s3c64xx_pclk_ctrl, |
314 | .ctrlbit = S3C_CLKCON_PCLK_UART3, | 296 | .ctrlbit = S3C_CLKCON_PCLK_UART3, |
315 | }, { | 297 | }, { |
316 | .name = "watchdog", | 298 | .name = "watchdog", |
317 | .id = -1, | ||
318 | .parent = &clk_p, | 299 | .parent = &clk_p, |
319 | .ctrlbit = S3C_CLKCON_PCLK_WDT, | 300 | .ctrlbit = S3C_CLKCON_PCLK_WDT, |
320 | }, { | 301 | }, { |
321 | .name = "ac97", | 302 | .name = "ac97", |
322 | .id = -1, | ||
323 | .parent = &clk_p, | 303 | .parent = &clk_p, |
324 | .ctrlbit = S3C_CLKCON_PCLK_AC97, | 304 | .ctrlbit = S3C_CLKCON_PCLK_AC97, |
325 | }, { | 305 | }, { |
326 | .name = "cfcon", | 306 | .name = "cfcon", |
327 | .id = -1, | ||
328 | .parent = &clk_h, | 307 | .parent = &clk_h, |
329 | .enable = s3c64xx_hclk_ctrl, | 308 | .enable = s3c64xx_hclk_ctrl, |
330 | .ctrlbit = S3C_CLKCON_HCLK_IHOST, | 309 | .ctrlbit = S3C_CLKCON_HCLK_IHOST, |
@@ -334,7 +313,6 @@ static struct clk init_clocks[] = { | |||
334 | 313 | ||
335 | static struct clk clk_fout_apll = { | 314 | static struct clk clk_fout_apll = { |
336 | .name = "fout_apll", | 315 | .name = "fout_apll", |
337 | .id = -1, | ||
338 | }; | 316 | }; |
339 | 317 | ||
340 | static struct clk *clk_src_apll_list[] = { | 318 | static struct clk *clk_src_apll_list[] = { |
@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = { | |||
350 | static struct clksrc_clk clk_mout_apll = { | 328 | static struct clksrc_clk clk_mout_apll = { |
351 | .clk = { | 329 | .clk = { |
352 | .name = "mout_apll", | 330 | .name = "mout_apll", |
353 | .id = -1, | ||
354 | }, | 331 | }, |
355 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, | 332 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, |
356 | .sources = &clk_src_apll, | 333 | .sources = &clk_src_apll, |
@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = { | |||
369 | static struct clksrc_clk clk_mout_epll = { | 346 | static struct clksrc_clk clk_mout_epll = { |
370 | .clk = { | 347 | .clk = { |
371 | .name = "mout_epll", | 348 | .name = "mout_epll", |
372 | .id = -1, | ||
373 | }, | 349 | }, |
374 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, | 350 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, |
375 | .sources = &clk_src_epll, | 351 | .sources = &clk_src_epll, |
@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = { | |||
388 | static struct clksrc_clk clk_mout_mpll = { | 364 | static struct clksrc_clk clk_mout_mpll = { |
389 | .clk = { | 365 | .clk = { |
390 | .name = "mout_mpll", | 366 | .name = "mout_mpll", |
391 | .id = -1, | ||
392 | }, | 367 | }, |
393 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, | 368 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, |
394 | .sources = &clk_src_mpll, | 369 | .sources = &clk_src_mpll, |
@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate) | |||
446 | 421 | ||
447 | static struct clk clk_arm = { | 422 | static struct clk clk_arm = { |
448 | .name = "armclk", | 423 | .name = "armclk", |
449 | .id = -1, | ||
450 | .parent = &clk_mout_apll.clk, | 424 | .parent = &clk_mout_apll.clk, |
451 | .ops = &(struct clk_ops) { | 425 | .ops = &(struct clk_ops) { |
452 | .get_rate = s3c64xx_clk_arm_get_rate, | 426 | .get_rate = s3c64xx_clk_arm_get_rate, |
@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = { | |||
473 | 447 | ||
474 | static struct clk clk_dout_mpll = { | 448 | static struct clk clk_dout_mpll = { |
475 | .name = "dout_mpll", | 449 | .name = "dout_mpll", |
476 | .id = -1, | ||
477 | .parent = &clk_mout_mpll.clk, | 450 | .parent = &clk_mout_mpll.clk, |
478 | .ops = &clk_dout_ops, | 451 | .ops = &clk_dout_ops, |
479 | }; | 452 | }; |
@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = { | |||
540 | 513 | ||
541 | static struct clk clk_iis_cd0 = { | 514 | static struct clk clk_iis_cd0 = { |
542 | .name = "iis_cdclk0", | 515 | .name = "iis_cdclk0", |
543 | .id = -1, | ||
544 | }; | 516 | }; |
545 | 517 | ||
546 | static struct clk clk_iis_cd1 = { | 518 | static struct clk clk_iis_cd1 = { |
547 | .name = "iis_cdclk1", | 519 | .name = "iis_cdclk1", |
548 | .id = -1, | ||
549 | }; | 520 | }; |
550 | 521 | ||
551 | static struct clk clk_iisv4_cd = { | 522 | static struct clk clk_iisv4_cd = { |
552 | .name = "iis_cdclk_v4", | 523 | .name = "iis_cdclk_v4", |
553 | .id = -1, | ||
554 | }; | 524 | }; |
555 | 525 | ||
556 | static struct clk clk_pcm_cd = { | 526 | static struct clk clk_pcm_cd = { |
557 | .name = "pcm_cdclk", | 527 | .name = "pcm_cdclk", |
558 | .id = -1, | ||
559 | }; | 528 | }; |
560 | 529 | ||
561 | static struct clk *clkset_audio0_list[] = { | 530 | static struct clk *clkset_audio0_list[] = { |
@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = { | |||
610 | { | 579 | { |
611 | .clk = { | 580 | .clk = { |
612 | .name = "mmc_bus", | 581 | .name = "mmc_bus", |
613 | .id = 0, | 582 | .devname = "s3c-sdhci.0", |
614 | .ctrlbit = S3C_CLKCON_SCLK_MMC0, | 583 | .ctrlbit = S3C_CLKCON_SCLK_MMC0, |
615 | .enable = s3c64xx_sclk_ctrl, | 584 | .enable = s3c64xx_sclk_ctrl, |
616 | }, | 585 | }, |
@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = { | |||
620 | }, { | 589 | }, { |
621 | .clk = { | 590 | .clk = { |
622 | .name = "mmc_bus", | 591 | .name = "mmc_bus", |
623 | .id = 1, | 592 | .devname = "s3c-sdhci.1", |
624 | .ctrlbit = S3C_CLKCON_SCLK_MMC1, | 593 | .ctrlbit = S3C_CLKCON_SCLK_MMC1, |
625 | .enable = s3c64xx_sclk_ctrl, | 594 | .enable = s3c64xx_sclk_ctrl, |
626 | }, | 595 | }, |
@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = { | |||
630 | }, { | 599 | }, { |
631 | .clk = { | 600 | .clk = { |
632 | .name = "mmc_bus", | 601 | .name = "mmc_bus", |
633 | .id = 2, | 602 | .devname = "s3c-sdhci.2", |
634 | .ctrlbit = S3C_CLKCON_SCLK_MMC2, | 603 | .ctrlbit = S3C_CLKCON_SCLK_MMC2, |
635 | .enable = s3c64xx_sclk_ctrl, | 604 | .enable = s3c64xx_sclk_ctrl, |
636 | }, | 605 | }, |
@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = { | |||
640 | }, { | 609 | }, { |
641 | .clk = { | 610 | .clk = { |
642 | .name = "usb-bus-host", | 611 | .name = "usb-bus-host", |
643 | .id = -1, | ||
644 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, | 612 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, |
645 | .enable = s3c64xx_sclk_ctrl, | 613 | .enable = s3c64xx_sclk_ctrl, |
646 | }, | 614 | }, |
@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = { | |||
650 | }, { | 618 | }, { |
651 | .clk = { | 619 | .clk = { |
652 | .name = "uclk1", | 620 | .name = "uclk1", |
653 | .id = -1, | ||
654 | .ctrlbit = S3C_CLKCON_SCLK_UART, | 621 | .ctrlbit = S3C_CLKCON_SCLK_UART, |
655 | .enable = s3c64xx_sclk_ctrl, | 622 | .enable = s3c64xx_sclk_ctrl, |
656 | }, | 623 | }, |
@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = { | |||
661 | /* Where does UCLK0 come from? */ | 628 | /* Where does UCLK0 come from? */ |
662 | .clk = { | 629 | .clk = { |
663 | .name = "spi-bus", | 630 | .name = "spi-bus", |
664 | .id = 0, | 631 | .devname = "s3c64xx-spi.0", |
665 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, | 632 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, |
666 | .enable = s3c64xx_sclk_ctrl, | 633 | .enable = s3c64xx_sclk_ctrl, |
667 | }, | 634 | }, |
@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = { | |||
671 | }, { | 638 | }, { |
672 | .clk = { | 639 | .clk = { |
673 | .name = "spi-bus", | 640 | .name = "spi-bus", |
674 | .id = 1, | 641 | .devname = "s3c64xx-spi.1", |
675 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, | ||
676 | .enable = s3c64xx_sclk_ctrl, | 642 | .enable = s3c64xx_sclk_ctrl, |
677 | }, | 643 | }, |
678 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, | 644 | .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, |
@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = { | |||
681 | }, { | 647 | }, { |
682 | .clk = { | 648 | .clk = { |
683 | .name = "audio-bus", | 649 | .name = "audio-bus", |
684 | .id = 0, | 650 | .devname = "samsung-i2s.0", |
685 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, | 651 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, |
686 | .enable = s3c64xx_sclk_ctrl, | 652 | .enable = s3c64xx_sclk_ctrl, |
687 | }, | 653 | }, |
@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = { | |||
691 | }, { | 657 | }, { |
692 | .clk = { | 658 | .clk = { |
693 | .name = "audio-bus", | 659 | .name = "audio-bus", |
694 | .id = 1, | 660 | .devname = "samsung-i2s.1", |
695 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, | 661 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, |
696 | .enable = s3c64xx_sclk_ctrl, | 662 | .enable = s3c64xx_sclk_ctrl, |
697 | }, | 663 | }, |
@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = { | |||
701 | }, { | 667 | }, { |
702 | .clk = { | 668 | .clk = { |
703 | .name = "audio-bus", | 669 | .name = "audio-bus", |
704 | .id = 2, | 670 | .devname = "samsung-i2s.2", |
705 | .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, | 671 | .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, |
706 | .enable = s3c64xx_sclk_ctrl, | 672 | .enable = s3c64xx_sclk_ctrl, |
707 | }, | 673 | }, |
@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = { | |||
711 | }, { | 677 | }, { |
712 | .clk = { | 678 | .clk = { |
713 | .name = "irda-bus", | 679 | .name = "irda-bus", |
714 | .id = 0, | ||
715 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, | 680 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, |
716 | .enable = s3c64xx_sclk_ctrl, | 681 | .enable = s3c64xx_sclk_ctrl, |
717 | }, | 682 | }, |
@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = { | |||
721 | }, { | 686 | }, { |
722 | .clk = { | 687 | .clk = { |
723 | .name = "camera", | 688 | .name = "camera", |
724 | .id = -1, | ||
725 | .ctrlbit = S3C_CLKCON_SCLK_CAM, | 689 | .ctrlbit = S3C_CLKCON_SCLK_CAM, |
726 | .enable = s3c64xx_sclk_ctrl, | 690 | .enable = s3c64xx_sclk_ctrl, |
727 | }, | 691 | }, |
diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c index 92ffd5bac104..999f9e17a1e4 100644 --- a/arch/arm/mach-s3c64xx/dev-onenand1.c +++ b/arch/arm/mach-s3c64xx/dev-onenand1.c | |||
@@ -19,6 +19,8 @@ | |||
19 | #include <mach/irqs.h> | 19 | #include <mach/irqs.h> |
20 | #include <mach/map.h> | 20 | #include <mach/map.h> |
21 | 21 | ||
22 | #include <plat/devs.h> | ||
23 | |||
22 | static struct resource s3c64xx_onenand1_resources[] = { | 24 | static struct resource s3c64xx_onenand1_resources[] = { |
23 | [0] = { | 25 | [0] = { |
24 | .start = S3C64XX_PA_ONENAND1, | 26 | .start = S3C64XX_PA_ONENAND1, |
@@ -46,10 +48,6 @@ struct platform_device s3c64xx_device_onenand1 = { | |||
46 | 48 | ||
47 | void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) | 49 | void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) |
48 | { | 50 | { |
49 | struct onenand_platform_data *pd; | 51 | s3c_set_platdata(pdata, sizeof(struct onenand_platform_data), |
50 | 52 | &s3c64xx_device_onenand1); | |
51 | pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); | ||
52 | if (!pd) | ||
53 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
54 | s3c64xx_device_onenand1.dev.platform_data = pd; | ||
55 | } | 53 | } |
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c index 82db072cb836..5e6b42089eb4 100644 --- a/arch/arm/mach-s3c64xx/dev-spi.c +++ b/arch/arm/mach-s3c64xx/dev-spi.c | |||
@@ -88,6 +88,7 @@ static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { | |||
88 | .cfg_gpio = s3c64xx_spi_cfg_gpio, | 88 | .cfg_gpio = s3c64xx_spi_cfg_gpio, |
89 | .fifo_lvl_mask = 0x7f, | 89 | .fifo_lvl_mask = 0x7f, |
90 | .rx_lvl_offset = 13, | 90 | .rx_lvl_offset = 13, |
91 | .tx_st_done = 21, | ||
91 | }; | 92 | }; |
92 | 93 | ||
93 | static u64 spi_dmamask = DMA_BIT_MASK(32); | 94 | static u64 spi_dmamask = DMA_BIT_MASK(32); |
@@ -132,6 +133,7 @@ static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { | |||
132 | .cfg_gpio = s3c64xx_spi_cfg_gpio, | 133 | .cfg_gpio = s3c64xx_spi_cfg_gpio, |
133 | .fifo_lvl_mask = 0x7f, | 134 | .fifo_lvl_mask = 0x7f, |
134 | .rx_lvl_offset = 13, | 135 | .rx_lvl_offset = 13, |
136 | .tx_st_done = 21, | ||
135 | }; | 137 | }; |
136 | 138 | ||
137 | struct platform_device s3c64xx_device_spi1 = { | 139 | struct platform_device s3c64xx_device_spi1 = { |
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h deleted file mode 100644 index a06ee0af9a4b..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Openmoko, Inc. | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Copyright 2009 Samsung Electronics Co. | ||
5 | * | ||
6 | * Pawel Osciak <p.osciak@samsung.com> | ||
7 | * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk> | ||
8 | * | ||
9 | * Framebuffer register definitions for Samsung S3C64xx. | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_MACH_REGS_FB_H | ||
17 | #define __ASM_ARCH_MACH_REGS_FB_H __FILE__ | ||
18 | |||
19 | #include <plat/regs-fb-v4.h> | ||
20 | |||
21 | #endif /* __ASM_ARCH_MACH_REGS_FB_H */ | ||
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index a53cf149476e..cb8864327ac4 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c | |||
@@ -35,7 +35,6 @@ | |||
35 | #include <asm/mach/irq.h> | 35 | #include <asm/mach/irq.h> |
36 | 36 | ||
37 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
38 | #include <mach/regs-fb.h> | ||
39 | #include <mach/map.h> | 38 | #include <mach/map.h> |
40 | 39 | ||
41 | #include <asm/irq.h> | 40 | #include <asm/irq.h> |
@@ -44,6 +43,7 @@ | |||
44 | #include <plat/regs-serial.h> | 43 | #include <plat/regs-serial.h> |
45 | #include <plat/iic.h> | 44 | #include <plat/iic.h> |
46 | #include <plat/fb.h> | 45 | #include <plat/fb.h> |
46 | #include <plat/regs-fb-v4.h> | ||
47 | 47 | ||
48 | #include <mach/s3c6410.h> | 48 | #include <mach/s3c6410.h> |
49 | #include <plat/clock.h> | 49 | #include <plat/clock.h> |
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index b2639582caca..b3d93cc8dde0 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c | |||
@@ -27,7 +27,6 @@ | |||
27 | #include <asm/mach/irq.h> | 27 | #include <asm/mach/irq.h> |
28 | 28 | ||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <mach/regs-fb.h> | ||
31 | #include <mach/map.h> | 30 | #include <mach/map.h> |
32 | 31 | ||
33 | #include <asm/irq.h> | 32 | #include <asm/irq.h> |
@@ -42,6 +41,7 @@ | |||
42 | #include <plat/clock.h> | 41 | #include <plat/clock.h> |
43 | #include <plat/devs.h> | 42 | #include <plat/devs.h> |
44 | #include <plat/cpu.h> | 43 | #include <plat/cpu.h> |
44 | #include <plat/regs-fb-v4.h> | ||
45 | 45 | ||
46 | #define UCON S3C2410_UCON_DEFAULT | 46 | #define UCON S3C2410_UCON_DEFAULT |
47 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) | 47 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) |
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index 89f35e02e883..527f49bd1b57 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c | |||
@@ -29,7 +29,6 @@ | |||
29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
30 | 30 | ||
31 | #include <mach/map.h> | 31 | #include <mach/map.h> |
32 | #include <mach/regs-fb.h> | ||
33 | #include <mach/regs-gpio.h> | 32 | #include <mach/regs-gpio.h> |
34 | #include <mach/regs-modem.h> | 33 | #include <mach/regs-modem.h> |
35 | #include <mach/regs-srom.h> | 34 | #include <mach/regs-srom.h> |
@@ -42,6 +41,7 @@ | |||
42 | #include <plat/nand.h> | 41 | #include <plat/nand.h> |
43 | #include <plat/regs-serial.h> | 42 | #include <plat/regs-serial.h> |
44 | #include <plat/ts.h> | 43 | #include <plat/ts.h> |
44 | #include <plat/regs-fb-v4.h> | ||
45 | 45 | ||
46 | #include <video/platform_lcd.h> | 46 | #include <video/platform_lcd.h> |
47 | 47 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c index c4986498cd12..01c6857c5b63 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c | |||
@@ -30,7 +30,6 @@ | |||
30 | #include <asm/mach/irq.h> | 30 | #include <asm/mach/irq.h> |
31 | 31 | ||
32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
33 | #include <mach/regs-fb.h> | ||
34 | #include <mach/map.h> | 33 | #include <mach/map.h> |
35 | 34 | ||
36 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
@@ -44,6 +43,7 @@ | |||
44 | #include <plat/clock.h> | 43 | #include <plat/clock.h> |
45 | #include <plat/devs.h> | 44 | #include <plat/devs.h> |
46 | #include <plat/cpu.h> | 45 | #include <plat/cpu.h> |
46 | #include <plat/regs-fb-v4.h> | ||
47 | 47 | ||
48 | #define UCON S3C2410_UCON_DEFAULT | 48 | #define UCON S3C2410_UCON_DEFAULT |
49 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | 49 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE |
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c index 4957ab0a0d4a..95b04b1729e3 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c64xx/mach-real6410.c | |||
@@ -30,7 +30,6 @@ | |||
30 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
31 | 31 | ||
32 | #include <mach/map.h> | 32 | #include <mach/map.h> |
33 | #include <mach/regs-fb.h> | ||
34 | #include <mach/regs-gpio.h> | 33 | #include <mach/regs-gpio.h> |
35 | #include <mach/regs-modem.h> | 34 | #include <mach/regs-modem.h> |
36 | #include <mach/regs-srom.h> | 35 | #include <mach/regs-srom.h> |
@@ -43,6 +42,7 @@ | |||
43 | #include <plat/nand.h> | 42 | #include <plat/nand.h> |
44 | #include <plat/regs-serial.h> | 43 | #include <plat/regs-serial.h> |
45 | #include <plat/ts.h> | 44 | #include <plat/ts.h> |
45 | #include <plat/regs-fb-v4.h> | ||
46 | 46 | ||
47 | #include <video/platform_lcd.h> | 47 | #include <video/platform_lcd.h> |
48 | 48 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c index 3a3e5acde523..342e8dfddf8b 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq5.c +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
22 | 22 | ||
23 | #include <mach/map.h> | 23 | #include <mach/map.h> |
24 | #include <mach/regs-fb.h> | ||
25 | #include <mach/regs-gpio.h> | 24 | #include <mach/regs-gpio.h> |
26 | #include <mach/s3c6410.h> | 25 | #include <mach/s3c6410.h> |
27 | 26 | ||
@@ -29,6 +28,7 @@ | |||
29 | #include <plat/devs.h> | 28 | #include <plat/devs.h> |
30 | #include <plat/fb.h> | 29 | #include <plat/fb.h> |
31 | #include <plat/gpio-cfg.h> | 30 | #include <plat/gpio-cfg.h> |
31 | #include <plat/regs-fb-v4.h> | ||
32 | 32 | ||
33 | #include "mach-smartq.h" | 33 | #include "mach-smartq.h" |
34 | 34 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c index e65375877d53..57963977da8e 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq7.c +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c | |||
@@ -21,7 +21,6 @@ | |||
21 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
22 | 22 | ||
23 | #include <mach/map.h> | 23 | #include <mach/map.h> |
24 | #include <mach/regs-fb.h> | ||
25 | #include <mach/regs-gpio.h> | 24 | #include <mach/regs-gpio.h> |
26 | #include <mach/s3c6410.h> | 25 | #include <mach/s3c6410.h> |
27 | 26 | ||
@@ -29,6 +28,7 @@ | |||
29 | #include <plat/devs.h> | 28 | #include <plat/devs.h> |
30 | #include <plat/fb.h> | 29 | #include <plat/fb.h> |
31 | #include <plat/gpio-cfg.h> | 30 | #include <plat/gpio-cfg.h> |
31 | #include <plat/regs-fb-v4.h> | ||
32 | 32 | ||
33 | #include "mach-smartq.h" | 33 | #include "mach-smartq.h" |
34 | 34 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 2c0353a80906..ecbea92bf83b 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c | |||
@@ -48,7 +48,6 @@ | |||
48 | #include <asm/mach/irq.h> | 48 | #include <asm/mach/irq.h> |
49 | 49 | ||
50 | #include <mach/hardware.h> | 50 | #include <mach/hardware.h> |
51 | #include <mach/regs-fb.h> | ||
52 | #include <mach/map.h> | 51 | #include <mach/map.h> |
53 | 52 | ||
54 | #include <asm/irq.h> | 53 | #include <asm/irq.h> |
@@ -71,6 +70,8 @@ | |||
71 | #include <plat/adc.h> | 70 | #include <plat/adc.h> |
72 | #include <plat/ts.h> | 71 | #include <plat/ts.h> |
73 | #include <plat/keypad.h> | 72 | #include <plat/keypad.h> |
73 | #include <plat/backlight.h> | ||
74 | #include <plat/regs-fb-v4.h> | ||
74 | 75 | ||
75 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | 76 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK |
76 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | 77 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB |
@@ -209,17 +210,9 @@ static struct platform_device smdk6410_smsc911x = { | |||
209 | }; | 210 | }; |
210 | 211 | ||
211 | #ifdef CONFIG_REGULATOR | 212 | #ifdef CONFIG_REGULATOR |
212 | static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = { | 213 | static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = { |
213 | { | 214 | REGULATOR_SUPPLY("PVDD", "0-001b"), |
214 | /* WM8580 */ | 215 | REGULATOR_SUPPLY("AVDD", "0-001b"), |
215 | .supply = "PVDD", | ||
216 | .dev_name = "0-001b", | ||
217 | }, | ||
218 | { | ||
219 | /* WM8580 */ | ||
220 | .supply = "AVDD", | ||
221 | .dev_name = "0-001b", | ||
222 | }, | ||
223 | }; | 216 | }; |
224 | 217 | ||
225 | static struct regulator_init_data smdk6410_b_pwr_5v_data = { | 218 | static struct regulator_init_data smdk6410_b_pwr_5v_data = { |
@@ -337,16 +330,12 @@ static struct platform_device *smdk6410_devices[] __initdata = { | |||
337 | &s3c_device_rtc, | 330 | &s3c_device_rtc, |
338 | &s3c_device_ts, | 331 | &s3c_device_ts, |
339 | &s3c_device_wdt, | 332 | &s3c_device_wdt, |
340 | &s3c_device_timer[1], | ||
341 | &smdk6410_backlight_device, | ||
342 | }; | 333 | }; |
343 | 334 | ||
344 | #ifdef CONFIG_REGULATOR | 335 | #ifdef CONFIG_REGULATOR |
345 | /* ARM core */ | 336 | /* ARM core */ |
346 | static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = { | 337 | static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = { |
347 | { | 338 | REGULATOR_SUPPLY("vddarm", NULL), |
348 | .supply = "vddarm", | ||
349 | } | ||
350 | }; | 339 | }; |
351 | 340 | ||
352 | /* VDDARM, BUCK1 on J5 */ | 341 | /* VDDARM, BUCK1 on J5 */ |
@@ -484,11 +473,7 @@ static struct regulator_init_data wm8350_dcdc3_data = { | |||
484 | 473 | ||
485 | /* USB, EXT, PCM, ADC/DAC, USB, MMC */ | 474 | /* USB, EXT, PCM, ADC/DAC, USB, MMC */ |
486 | static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { | 475 | static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { |
487 | { | 476 | REGULATOR_SUPPLY("DVDD", "0-001b"), |
488 | /* WM8580 */ | ||
489 | .supply = "DVDD", | ||
490 | .dev_name = "0-001b", | ||
491 | }, | ||
492 | }; | 477 | }; |
493 | 478 | ||
494 | static struct regulator_init_data wm8350_dcdc4_data = { | 479 | static struct regulator_init_data wm8350_dcdc4_data = { |
@@ -599,7 +584,7 @@ static struct regulator_init_data wm1192_dcdc3 = { | |||
599 | }; | 584 | }; |
600 | 585 | ||
601 | static struct regulator_consumer_supply wm1192_ldo1_consumers[] = { | 586 | static struct regulator_consumer_supply wm1192_ldo1_consumers[] = { |
602 | { .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */ | 587 | REGULATOR_SUPPLY("DVDD", "0-001b"), /* WM8580 */ |
603 | }; | 588 | }; |
604 | 589 | ||
605 | static struct regulator_init_data wm1192_ldo1 = { | 590 | static struct regulator_init_data wm1192_ldo1 = { |
@@ -679,6 +664,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | |||
679 | .oversampling_shift = 2, | 664 | .oversampling_shift = 2, |
680 | }; | 665 | }; |
681 | 666 | ||
667 | /* LCD Backlight data */ | ||
668 | static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = { | ||
669 | .no = S3C64XX_GPF(15), | ||
670 | .func = S3C_GPIO_SFN(2), | ||
671 | }; | ||
672 | |||
673 | static struct platform_pwm_backlight_data smdk6410_bl_data = { | ||
674 | .pwm_id = 1, | ||
675 | }; | ||
676 | |||
682 | static void __init smdk6410_map_io(void) | 677 | static void __init smdk6410_map_io(void) |
683 | { | 678 | { |
684 | u32 tmp; | 679 | u32 tmp; |
@@ -740,6 +735,8 @@ static void __init smdk6410_machine_init(void) | |||
740 | 735 | ||
741 | s3c_ide_set_platdata(&smdk6410_ide_pdata); | 736 | s3c_ide_set_platdata(&smdk6410_ide_pdata); |
742 | 737 | ||
738 | samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data); | ||
739 | |||
743 | platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); | 740 | platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); |
744 | } | 741 | } |
745 | 742 | ||
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c index 8f3091182f9c..83d2afb79e9f 100644 --- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c +++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <linux/fb.h> | 17 | #include <linux/fb.h> |
18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
19 | 19 | ||
20 | #include <mach/regs-fb.h> | ||
21 | #include <plat/fb.h> | 20 | #include <plat/fb.h> |
22 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
23 | 22 | ||
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig index 017af4c4293c..65c7518dad7f 100644 --- a/arch/arm/mach-s5p64x0/Kconfig +++ b/arch/arm/mach-s5p64x0/Kconfig | |||
@@ -36,6 +36,7 @@ config MACH_SMDK6440 | |||
36 | select S3C_DEV_WDT | 36 | select S3C_DEV_WDT |
37 | select S3C64XX_DEV_SPI | 37 | select S3C64XX_DEV_SPI |
38 | select SAMSUNG_DEV_ADC | 38 | select SAMSUNG_DEV_ADC |
39 | select SAMSUNG_DEV_BACKLIGHT | ||
39 | select SAMSUNG_DEV_PWM | 40 | select SAMSUNG_DEV_PWM |
40 | select SAMSUNG_DEV_TS | 41 | select SAMSUNG_DEV_TS |
41 | select S5P64X0_SETUP_I2C1 | 42 | select S5P64X0_SETUP_I2C1 |
@@ -50,6 +51,7 @@ config MACH_SMDK6450 | |||
50 | select S3C_DEV_WDT | 51 | select S3C_DEV_WDT |
51 | select S3C64XX_DEV_SPI | 52 | select S3C64XX_DEV_SPI |
52 | select SAMSUNG_DEV_ADC | 53 | select SAMSUNG_DEV_ADC |
54 | select SAMSUNG_DEV_BACKLIGHT | ||
53 | select SAMSUNG_DEV_PWM | 55 | select SAMSUNG_DEV_PWM |
54 | select SAMSUNG_DEV_TS | 56 | select SAMSUNG_DEV_TS |
55 | select S5P64X0_SETUP_I2C1 | 57 | select S5P64X0_SETUP_I2C1 |
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index 9f12c2ebf416..0e9cd3092dd2 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c | |||
@@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = { | |||
95 | static struct clksrc_clk clk_hclk = { | 95 | static struct clksrc_clk clk_hclk = { |
96 | .clk = { | 96 | .clk = { |
97 | .name = "clk_hclk", | 97 | .name = "clk_hclk", |
98 | .id = -1, | ||
99 | .parent = &clk_armclk.clk, | 98 | .parent = &clk_armclk.clk, |
100 | }, | 99 | }, |
101 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, | 100 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, |
@@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = { | |||
104 | static struct clksrc_clk clk_pclk = { | 103 | static struct clksrc_clk clk_pclk = { |
105 | .clk = { | 104 | .clk = { |
106 | .name = "clk_pclk", | 105 | .name = "clk_pclk", |
107 | .id = -1, | ||
108 | .parent = &clk_hclk.clk, | 106 | .parent = &clk_hclk.clk, |
109 | }, | 107 | }, |
110 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, | 108 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, |
@@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = { | |||
112 | static struct clksrc_clk clk_hclk_low = { | 110 | static struct clksrc_clk clk_hclk_low = { |
113 | .clk = { | 111 | .clk = { |
114 | .name = "clk_hclk_low", | 112 | .name = "clk_hclk_low", |
115 | .id = -1, | ||
116 | }, | 113 | }, |
117 | .sources = &clkset_hclk_low, | 114 | .sources = &clkset_hclk_low, |
118 | .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, | 115 | .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, |
@@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = { | |||
122 | static struct clksrc_clk clk_pclk_low = { | 119 | static struct clksrc_clk clk_pclk_low = { |
123 | .clk = { | 120 | .clk = { |
124 | .name = "clk_pclk_low", | 121 | .name = "clk_pclk_low", |
125 | .id = -1, | ||
126 | .parent = &clk_hclk_low.clk, | 122 | .parent = &clk_hclk_low.clk, |
127 | }, | 123 | }, |
128 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, | 124 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, |
@@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = { | |||
136 | static struct clk init_clocks_off[] = { | 132 | static struct clk init_clocks_off[] = { |
137 | { | 133 | { |
138 | .name = "nand", | 134 | .name = "nand", |
139 | .id = -1, | ||
140 | .parent = &clk_hclk.clk, | 135 | .parent = &clk_hclk.clk, |
141 | .enable = s5p64x0_mem_ctrl, | 136 | .enable = s5p64x0_mem_ctrl, |
142 | .ctrlbit = (1 << 2), | 137 | .ctrlbit = (1 << 2), |
143 | }, { | 138 | }, { |
144 | .name = "post", | 139 | .name = "post", |
145 | .id = -1, | ||
146 | .parent = &clk_hclk_low.clk, | 140 | .parent = &clk_hclk_low.clk, |
147 | .enable = s5p64x0_hclk0_ctrl, | 141 | .enable = s5p64x0_hclk0_ctrl, |
148 | .ctrlbit = (1 << 5) | 142 | .ctrlbit = (1 << 5) |
149 | }, { | 143 | }, { |
150 | .name = "2d", | 144 | .name = "2d", |
151 | .id = -1, | ||
152 | .parent = &clk_hclk.clk, | 145 | .parent = &clk_hclk.clk, |
153 | .enable = s5p64x0_hclk0_ctrl, | 146 | .enable = s5p64x0_hclk0_ctrl, |
154 | .ctrlbit = (1 << 8), | 147 | .ctrlbit = (1 << 8), |
155 | }, { | 148 | }, { |
156 | .name = "pdma", | 149 | .name = "pdma", |
157 | .id = -1, | ||
158 | .parent = &clk_hclk_low.clk, | 150 | .parent = &clk_hclk_low.clk, |
159 | .enable = s5p64x0_hclk0_ctrl, | 151 | .enable = s5p64x0_hclk0_ctrl, |
160 | .ctrlbit = (1 << 12), | 152 | .ctrlbit = (1 << 12), |
161 | }, { | 153 | }, { |
162 | .name = "hsmmc", | 154 | .name = "hsmmc", |
163 | .id = 0, | 155 | .devname = "s3c-sdhci.0", |
164 | .parent = &clk_hclk_low.clk, | 156 | .parent = &clk_hclk_low.clk, |
165 | .enable = s5p64x0_hclk0_ctrl, | 157 | .enable = s5p64x0_hclk0_ctrl, |
166 | .ctrlbit = (1 << 17), | 158 | .ctrlbit = (1 << 17), |
167 | }, { | 159 | }, { |
168 | .name = "hsmmc", | 160 | .name = "hsmmc", |
169 | .id = 1, | 161 | .devname = "s3c-sdhci.1", |
170 | .parent = &clk_hclk_low.clk, | 162 | .parent = &clk_hclk_low.clk, |
171 | .enable = s5p64x0_hclk0_ctrl, | 163 | .enable = s5p64x0_hclk0_ctrl, |
172 | .ctrlbit = (1 << 18), | 164 | .ctrlbit = (1 << 18), |
173 | }, { | 165 | }, { |
174 | .name = "hsmmc", | 166 | .name = "hsmmc", |
175 | .id = 2, | 167 | .devname = "s3c-sdhci.2", |
176 | .parent = &clk_hclk_low.clk, | 168 | .parent = &clk_hclk_low.clk, |
177 | .enable = s5p64x0_hclk0_ctrl, | 169 | .enable = s5p64x0_hclk0_ctrl, |
178 | .ctrlbit = (1 << 19), | 170 | .ctrlbit = (1 << 19), |
179 | }, { | 171 | }, { |
180 | .name = "otg", | 172 | .name = "otg", |
181 | .id = -1, | ||
182 | .parent = &clk_hclk_low.clk, | 173 | .parent = &clk_hclk_low.clk, |
183 | .enable = s5p64x0_hclk0_ctrl, | 174 | .enable = s5p64x0_hclk0_ctrl, |
184 | .ctrlbit = (1 << 20) | 175 | .ctrlbit = (1 << 20) |
185 | }, { | 176 | }, { |
186 | .name = "irom", | 177 | .name = "irom", |
187 | .id = -1, | ||
188 | .parent = &clk_hclk.clk, | 178 | .parent = &clk_hclk.clk, |
189 | .enable = s5p64x0_hclk0_ctrl, | 179 | .enable = s5p64x0_hclk0_ctrl, |
190 | .ctrlbit = (1 << 25), | 180 | .ctrlbit = (1 << 25), |
191 | }, { | 181 | }, { |
192 | .name = "lcd", | 182 | .name = "lcd", |
193 | .id = -1, | ||
194 | .parent = &clk_hclk_low.clk, | 183 | .parent = &clk_hclk_low.clk, |
195 | .enable = s5p64x0_hclk1_ctrl, | 184 | .enable = s5p64x0_hclk1_ctrl, |
196 | .ctrlbit = (1 << 1), | 185 | .ctrlbit = (1 << 1), |
197 | }, { | 186 | }, { |
198 | .name = "hclk_fimgvg", | 187 | .name = "hclk_fimgvg", |
199 | .id = -1, | ||
200 | .parent = &clk_hclk.clk, | 188 | .parent = &clk_hclk.clk, |
201 | .enable = s5p64x0_hclk1_ctrl, | 189 | .enable = s5p64x0_hclk1_ctrl, |
202 | .ctrlbit = (1 << 2), | 190 | .ctrlbit = (1 << 2), |
203 | }, { | 191 | }, { |
204 | .name = "tsi", | 192 | .name = "tsi", |
205 | .id = -1, | ||
206 | .parent = &clk_hclk_low.clk, | 193 | .parent = &clk_hclk_low.clk, |
207 | .enable = s5p64x0_hclk1_ctrl, | 194 | .enable = s5p64x0_hclk1_ctrl, |
208 | .ctrlbit = (1 << 0), | 195 | .ctrlbit = (1 << 0), |
209 | }, { | 196 | }, { |
210 | .name = "watchdog", | 197 | .name = "watchdog", |
211 | .id = -1, | ||
212 | .parent = &clk_pclk_low.clk, | 198 | .parent = &clk_pclk_low.clk, |
213 | .enable = s5p64x0_pclk_ctrl, | 199 | .enable = s5p64x0_pclk_ctrl, |
214 | .ctrlbit = (1 << 5), | 200 | .ctrlbit = (1 << 5), |
215 | }, { | 201 | }, { |
216 | .name = "rtc", | 202 | .name = "rtc", |
217 | .id = -1, | ||
218 | .parent = &clk_pclk_low.clk, | 203 | .parent = &clk_pclk_low.clk, |
219 | .enable = s5p64x0_pclk_ctrl, | 204 | .enable = s5p64x0_pclk_ctrl, |
220 | .ctrlbit = (1 << 6), | 205 | .ctrlbit = (1 << 6), |
221 | }, { | 206 | }, { |
222 | .name = "timers", | 207 | .name = "timers", |
223 | .id = -1, | ||
224 | .parent = &clk_pclk_low.clk, | 208 | .parent = &clk_pclk_low.clk, |
225 | .enable = s5p64x0_pclk_ctrl, | 209 | .enable = s5p64x0_pclk_ctrl, |
226 | .ctrlbit = (1 << 7), | 210 | .ctrlbit = (1 << 7), |
227 | }, { | 211 | }, { |
228 | .name = "pcm", | 212 | .name = "pcm", |
229 | .id = -1, | ||
230 | .parent = &clk_pclk_low.clk, | 213 | .parent = &clk_pclk_low.clk, |
231 | .enable = s5p64x0_pclk_ctrl, | 214 | .enable = s5p64x0_pclk_ctrl, |
232 | .ctrlbit = (1 << 8), | 215 | .ctrlbit = (1 << 8), |
233 | }, { | 216 | }, { |
234 | .name = "adc", | 217 | .name = "adc", |
235 | .id = -1, | ||
236 | .parent = &clk_pclk_low.clk, | 218 | .parent = &clk_pclk_low.clk, |
237 | .enable = s5p64x0_pclk_ctrl, | 219 | .enable = s5p64x0_pclk_ctrl, |
238 | .ctrlbit = (1 << 12), | 220 | .ctrlbit = (1 << 12), |
239 | }, { | 221 | }, { |
240 | .name = "i2c", | 222 | .name = "i2c", |
241 | .id = -1, | ||
242 | .parent = &clk_pclk_low.clk, | 223 | .parent = &clk_pclk_low.clk, |
243 | .enable = s5p64x0_pclk_ctrl, | 224 | .enable = s5p64x0_pclk_ctrl, |
244 | .ctrlbit = (1 << 17), | 225 | .ctrlbit = (1 << 17), |
245 | }, { | 226 | }, { |
246 | .name = "spi", | 227 | .name = "spi", |
247 | .id = 0, | 228 | .devname = "s3c64xx-spi.0", |
248 | .parent = &clk_pclk_low.clk, | 229 | .parent = &clk_pclk_low.clk, |
249 | .enable = s5p64x0_pclk_ctrl, | 230 | .enable = s5p64x0_pclk_ctrl, |
250 | .ctrlbit = (1 << 21), | 231 | .ctrlbit = (1 << 21), |
251 | }, { | 232 | }, { |
252 | .name = "spi", | 233 | .name = "spi", |
253 | .id = 1, | 234 | .devname = "s3c64xx-spi.1", |
254 | .parent = &clk_pclk_low.clk, | 235 | .parent = &clk_pclk_low.clk, |
255 | .enable = s5p64x0_pclk_ctrl, | 236 | .enable = s5p64x0_pclk_ctrl, |
256 | .ctrlbit = (1 << 22), | 237 | .ctrlbit = (1 << 22), |
257 | }, { | 238 | }, { |
258 | .name = "gps", | 239 | .name = "gps", |
259 | .id = -1, | ||
260 | .parent = &clk_pclk_low.clk, | 240 | .parent = &clk_pclk_low.clk, |
261 | .enable = s5p64x0_pclk_ctrl, | 241 | .enable = s5p64x0_pclk_ctrl, |
262 | .ctrlbit = (1 << 25), | 242 | .ctrlbit = (1 << 25), |
263 | }, { | 243 | }, { |
264 | .name = "iis", | 244 | .name = "iis", |
265 | .id = 0, | 245 | .devname = "samsung-i2s.0", |
266 | .parent = &clk_pclk_low.clk, | 246 | .parent = &clk_pclk_low.clk, |
267 | .enable = s5p64x0_pclk_ctrl, | 247 | .enable = s5p64x0_pclk_ctrl, |
268 | .ctrlbit = (1 << 26), | 248 | .ctrlbit = (1 << 26), |
269 | }, { | 249 | }, { |
270 | .name = "dsim", | 250 | .name = "dsim", |
271 | .id = -1, | ||
272 | .parent = &clk_pclk_low.clk, | 251 | .parent = &clk_pclk_low.clk, |
273 | .enable = s5p64x0_pclk_ctrl, | 252 | .enable = s5p64x0_pclk_ctrl, |
274 | .ctrlbit = (1 << 28), | 253 | .ctrlbit = (1 << 28), |
275 | }, { | 254 | }, { |
276 | .name = "etm", | 255 | .name = "etm", |
277 | .id = -1, | ||
278 | .parent = &clk_pclk.clk, | 256 | .parent = &clk_pclk.clk, |
279 | .enable = s5p64x0_pclk_ctrl, | 257 | .enable = s5p64x0_pclk_ctrl, |
280 | .ctrlbit = (1 << 29), | 258 | .ctrlbit = (1 << 29), |
281 | }, { | 259 | }, { |
282 | .name = "dmc0", | 260 | .name = "dmc0", |
283 | .id = -1, | ||
284 | .parent = &clk_pclk.clk, | 261 | .parent = &clk_pclk.clk, |
285 | .enable = s5p64x0_pclk_ctrl, | 262 | .enable = s5p64x0_pclk_ctrl, |
286 | .ctrlbit = (1 << 30), | 263 | .ctrlbit = (1 << 30), |
287 | }, { | 264 | }, { |
288 | .name = "pclk_fimgvg", | 265 | .name = "pclk_fimgvg", |
289 | .id = -1, | ||
290 | .parent = &clk_pclk.clk, | 266 | .parent = &clk_pclk.clk, |
291 | .enable = s5p64x0_pclk_ctrl, | 267 | .enable = s5p64x0_pclk_ctrl, |
292 | .ctrlbit = (1 << 31), | 268 | .ctrlbit = (1 << 31), |
293 | }, { | 269 | }, { |
294 | .name = "sclk_spi_48", | 270 | .name = "sclk_spi_48", |
295 | .id = 0, | 271 | .devname = "s3c64xx-spi.0", |
296 | .parent = &clk_48m, | 272 | .parent = &clk_48m, |
297 | .enable = s5p64x0_sclk_ctrl, | 273 | .enable = s5p64x0_sclk_ctrl, |
298 | .ctrlbit = (1 << 22), | 274 | .ctrlbit = (1 << 22), |
299 | }, { | 275 | }, { |
300 | .name = "sclk_spi_48", | 276 | .name = "sclk_spi_48", |
301 | .id = 1, | 277 | .devname = "s3c64xx-spi.1", |
302 | .parent = &clk_48m, | 278 | .parent = &clk_48m, |
303 | .enable = s5p64x0_sclk_ctrl, | 279 | .enable = s5p64x0_sclk_ctrl, |
304 | .ctrlbit = (1 << 23), | 280 | .ctrlbit = (1 << 23), |
305 | }, { | 281 | }, { |
306 | .name = "mmc_48m", | 282 | .name = "mmc_48m", |
307 | .id = 0, | 283 | .devname = "s3c-sdhci.0", |
308 | .parent = &clk_48m, | 284 | .parent = &clk_48m, |
309 | .enable = s5p64x0_sclk_ctrl, | 285 | .enable = s5p64x0_sclk_ctrl, |
310 | .ctrlbit = (1 << 27), | 286 | .ctrlbit = (1 << 27), |
311 | }, { | 287 | }, { |
312 | .name = "mmc_48m", | 288 | .name = "mmc_48m", |
313 | .id = 1, | 289 | .devname = "s3c-sdhci.1", |
314 | .parent = &clk_48m, | 290 | .parent = &clk_48m, |
315 | .enable = s5p64x0_sclk_ctrl, | 291 | .enable = s5p64x0_sclk_ctrl, |
316 | .ctrlbit = (1 << 28), | 292 | .ctrlbit = (1 << 28), |
317 | }, { | 293 | }, { |
318 | .name = "mmc_48m", | 294 | .name = "mmc_48m", |
319 | .id = 2, | 295 | .devname = "s3c-sdhci.2", |
320 | .parent = &clk_48m, | 296 | .parent = &clk_48m, |
321 | .enable = s5p64x0_sclk_ctrl, | 297 | .enable = s5p64x0_sclk_ctrl, |
322 | .ctrlbit = (1 << 29), | 298 | .ctrlbit = (1 << 29), |
@@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = { | |||
329 | static struct clk init_clocks[] = { | 305 | static struct clk init_clocks[] = { |
330 | { | 306 | { |
331 | .name = "intc", | 307 | .name = "intc", |
332 | .id = -1, | ||
333 | .parent = &clk_hclk.clk, | 308 | .parent = &clk_hclk.clk, |
334 | .enable = s5p64x0_hclk0_ctrl, | 309 | .enable = s5p64x0_hclk0_ctrl, |
335 | .ctrlbit = (1 << 1), | 310 | .ctrlbit = (1 << 1), |
336 | }, { | 311 | }, { |
337 | .name = "mem", | 312 | .name = "mem", |
338 | .id = -1, | ||
339 | .parent = &clk_hclk.clk, | 313 | .parent = &clk_hclk.clk, |
340 | .enable = s5p64x0_hclk0_ctrl, | 314 | .enable = s5p64x0_hclk0_ctrl, |
341 | .ctrlbit = (1 << 21), | 315 | .ctrlbit = (1 << 21), |
342 | }, { | 316 | }, { |
343 | .name = "uart", | 317 | .name = "uart", |
344 | .id = 0, | 318 | .devname = "s3c6400-uart.0", |
345 | .parent = &clk_pclk_low.clk, | 319 | .parent = &clk_pclk_low.clk, |
346 | .enable = s5p64x0_pclk_ctrl, | 320 | .enable = s5p64x0_pclk_ctrl, |
347 | .ctrlbit = (1 << 1), | 321 | .ctrlbit = (1 << 1), |
348 | }, { | 322 | }, { |
349 | .name = "uart", | 323 | .name = "uart", |
350 | .id = 1, | 324 | .devname = "s3c6400-uart.1", |
351 | .parent = &clk_pclk_low.clk, | 325 | .parent = &clk_pclk_low.clk, |
352 | .enable = s5p64x0_pclk_ctrl, | 326 | .enable = s5p64x0_pclk_ctrl, |
353 | .ctrlbit = (1 << 2), | 327 | .ctrlbit = (1 << 2), |
354 | }, { | 328 | }, { |
355 | .name = "uart", | 329 | .name = "uart", |
356 | .id = 2, | 330 | .devname = "s3c6400-uart.2", |
357 | .parent = &clk_pclk_low.clk, | 331 | .parent = &clk_pclk_low.clk, |
358 | .enable = s5p64x0_pclk_ctrl, | 332 | .enable = s5p64x0_pclk_ctrl, |
359 | .ctrlbit = (1 << 3), | 333 | .ctrlbit = (1 << 3), |
360 | }, { | 334 | }, { |
361 | .name = "uart", | 335 | .name = "uart", |
362 | .id = 3, | 336 | .devname = "s3c6400-uart.3", |
363 | .parent = &clk_pclk_low.clk, | 337 | .parent = &clk_pclk_low.clk, |
364 | .enable = s5p64x0_pclk_ctrl, | 338 | .enable = s5p64x0_pclk_ctrl, |
365 | .ctrlbit = (1 << 4), | 339 | .ctrlbit = (1 << 4), |
366 | }, { | 340 | }, { |
367 | .name = "gpio", | 341 | .name = "gpio", |
368 | .id = -1, | ||
369 | .parent = &clk_pclk_low.clk, | 342 | .parent = &clk_pclk_low.clk, |
370 | .enable = s5p64x0_pclk_ctrl, | 343 | .enable = s5p64x0_pclk_ctrl, |
371 | .ctrlbit = (1 << 18), | 344 | .ctrlbit = (1 << 18), |
@@ -374,12 +347,10 @@ static struct clk init_clocks[] = { | |||
374 | 347 | ||
375 | static struct clk clk_iis_cd_v40 = { | 348 | static struct clk clk_iis_cd_v40 = { |
376 | .name = "iis_cdclk_v40", | 349 | .name = "iis_cdclk_v40", |
377 | .id = -1, | ||
378 | }; | 350 | }; |
379 | 351 | ||
380 | static struct clk clk_pcm_cd = { | 352 | static struct clk clk_pcm_cd = { |
381 | .name = "pcm_cdclk", | 353 | .name = "pcm_cdclk", |
382 | .id = -1, | ||
383 | }; | 354 | }; |
384 | 355 | ||
385 | static struct clk *clkset_group1_list[] = { | 356 | static struct clk *clkset_group1_list[] = { |
@@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = { | |||
420 | { | 391 | { |
421 | .clk = { | 392 | .clk = { |
422 | .name = "sclk_mmc", | 393 | .name = "sclk_mmc", |
423 | .id = 0, | 394 | .devname = "s3c-sdhci.0", |
424 | .ctrlbit = (1 << 24), | 395 | .ctrlbit = (1 << 24), |
425 | .enable = s5p64x0_sclk_ctrl, | 396 | .enable = s5p64x0_sclk_ctrl, |
426 | }, | 397 | }, |
@@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = { | |||
430 | }, { | 401 | }, { |
431 | .clk = { | 402 | .clk = { |
432 | .name = "sclk_mmc", | 403 | .name = "sclk_mmc", |
433 | .id = 1, | 404 | .devname = "s3c-sdhci.1", |
434 | .ctrlbit = (1 << 25), | 405 | .ctrlbit = (1 << 25), |
435 | .enable = s5p64x0_sclk_ctrl, | 406 | .enable = s5p64x0_sclk_ctrl, |
436 | }, | 407 | }, |
@@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = { | |||
440 | }, { | 411 | }, { |
441 | .clk = { | 412 | .clk = { |
442 | .name = "sclk_mmc", | 413 | .name = "sclk_mmc", |
443 | .id = 2, | 414 | .devname = "s3c-sdhci.2", |
444 | .ctrlbit = (1 << 26), | 415 | .ctrlbit = (1 << 26), |
445 | .enable = s5p64x0_sclk_ctrl, | 416 | .enable = s5p64x0_sclk_ctrl, |
446 | }, | 417 | }, |
@@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = { | |||
450 | }, { | 421 | }, { |
451 | .clk = { | 422 | .clk = { |
452 | .name = "uclk1", | 423 | .name = "uclk1", |
453 | .id = -1, | ||
454 | .ctrlbit = (1 << 5), | 424 | .ctrlbit = (1 << 5), |
455 | .enable = s5p64x0_sclk_ctrl, | 425 | .enable = s5p64x0_sclk_ctrl, |
456 | }, | 426 | }, |
@@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = { | |||
460 | }, { | 430 | }, { |
461 | .clk = { | 431 | .clk = { |
462 | .name = "sclk_spi", | 432 | .name = "sclk_spi", |
463 | .id = 0, | 433 | .devname = "s3c64xx-spi.0", |
464 | .ctrlbit = (1 << 20), | 434 | .ctrlbit = (1 << 20), |
465 | .enable = s5p64x0_sclk_ctrl, | 435 | .enable = s5p64x0_sclk_ctrl, |
466 | }, | 436 | }, |
@@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = { | |||
470 | }, { | 440 | }, { |
471 | .clk = { | 441 | .clk = { |
472 | .name = "sclk_spi", | 442 | .name = "sclk_spi", |
473 | .id = 1, | 443 | .devname = "s3c64xx-spi.1", |
474 | .ctrlbit = (1 << 21), | 444 | .ctrlbit = (1 << 21), |
475 | .enable = s5p64x0_sclk_ctrl, | 445 | .enable = s5p64x0_sclk_ctrl, |
476 | }, | 446 | }, |
@@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = { | |||
480 | }, { | 450 | }, { |
481 | .clk = { | 451 | .clk = { |
482 | .name = "sclk_post", | 452 | .name = "sclk_post", |
483 | .id = -1, | ||
484 | .ctrlbit = (1 << 10), | 453 | .ctrlbit = (1 << 10), |
485 | .enable = s5p64x0_sclk_ctrl, | 454 | .enable = s5p64x0_sclk_ctrl, |
486 | }, | 455 | }, |
@@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = { | |||
490 | }, { | 459 | }, { |
491 | .clk = { | 460 | .clk = { |
492 | .name = "sclk_dispcon", | 461 | .name = "sclk_dispcon", |
493 | .id = -1, | ||
494 | .ctrlbit = (1 << 1), | 462 | .ctrlbit = (1 << 1), |
495 | .enable = s5p64x0_sclk1_ctrl, | 463 | .enable = s5p64x0_sclk1_ctrl, |
496 | }, | 464 | }, |
@@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = { | |||
500 | }, { | 468 | }, { |
501 | .clk = { | 469 | .clk = { |
502 | .name = "sclk_fimgvg", | 470 | .name = "sclk_fimgvg", |
503 | .id = -1, | ||
504 | .ctrlbit = (1 << 2), | 471 | .ctrlbit = (1 << 2), |
505 | .enable = s5p64x0_sclk1_ctrl, | 472 | .enable = s5p64x0_sclk1_ctrl, |
506 | }, | 473 | }, |
@@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = { | |||
510 | }, { | 477 | }, { |
511 | .clk = { | 478 | .clk = { |
512 | .name = "sclk_audio2", | 479 | .name = "sclk_audio2", |
513 | .id = -1, | ||
514 | .ctrlbit = (1 << 11), | 480 | .ctrlbit = (1 << 11), |
515 | .enable = s5p64x0_sclk_ctrl, | 481 | .enable = s5p64x0_sclk_ctrl, |
516 | }, | 482 | }, |
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 4eec457ddccc..d9dc16cde109 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c | |||
@@ -36,7 +36,6 @@ | |||
36 | static struct clksrc_clk clk_mout_dpll = { | 36 | static struct clksrc_clk clk_mout_dpll = { |
37 | .clk = { | 37 | .clk = { |
38 | .name = "mout_dpll", | 38 | .name = "mout_dpll", |
39 | .id = -1, | ||
40 | }, | 39 | }, |
41 | .sources = &clk_src_dpll, | 40 | .sources = &clk_src_dpll, |
42 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, | 41 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, |
@@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = { | |||
96 | static struct clksrc_clk clk_dout_epll = { | 95 | static struct clksrc_clk clk_dout_epll = { |
97 | .clk = { | 96 | .clk = { |
98 | .name = "dout_epll", | 97 | .name = "dout_epll", |
99 | .id = -1, | ||
100 | .parent = &clk_mout_epll.clk, | 98 | .parent = &clk_mout_epll.clk, |
101 | }, | 99 | }, |
102 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, | 100 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, |
@@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = { | |||
105 | static struct clksrc_clk clk_mout_hclk_sel = { | 103 | static struct clksrc_clk clk_mout_hclk_sel = { |
106 | .clk = { | 104 | .clk = { |
107 | .name = "mout_hclk_sel", | 105 | .name = "mout_hclk_sel", |
108 | .id = -1, | ||
109 | }, | 106 | }, |
110 | .sources = &clkset_hclk_low, | 107 | .sources = &clkset_hclk_low, |
111 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, | 108 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, |
@@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = { | |||
124 | static struct clksrc_clk clk_hclk = { | 121 | static struct clksrc_clk clk_hclk = { |
125 | .clk = { | 122 | .clk = { |
126 | .name = "clk_hclk", | 123 | .name = "clk_hclk", |
127 | .id = -1, | ||
128 | }, | 124 | }, |
129 | .sources = &clkset_hclk, | 125 | .sources = &clkset_hclk, |
130 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, | 126 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, |
@@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = { | |||
134 | static struct clksrc_clk clk_pclk = { | 130 | static struct clksrc_clk clk_pclk = { |
135 | .clk = { | 131 | .clk = { |
136 | .name = "clk_pclk", | 132 | .name = "clk_pclk", |
137 | .id = -1, | ||
138 | .parent = &clk_hclk.clk, | 133 | .parent = &clk_hclk.clk, |
139 | }, | 134 | }, |
140 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, | 135 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, |
@@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = { | |||
142 | static struct clksrc_clk clk_dout_pwm_ratio0 = { | 137 | static struct clksrc_clk clk_dout_pwm_ratio0 = { |
143 | .clk = { | 138 | .clk = { |
144 | .name = "clk_dout_pwm_ratio0", | 139 | .name = "clk_dout_pwm_ratio0", |
145 | .id = -1, | ||
146 | .parent = &clk_mout_hclk_sel.clk, | 140 | .parent = &clk_mout_hclk_sel.clk, |
147 | }, | 141 | }, |
148 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, | 142 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, |
@@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = { | |||
151 | static struct clksrc_clk clk_pclk_to_wdt_pwm = { | 145 | static struct clksrc_clk clk_pclk_to_wdt_pwm = { |
152 | .clk = { | 146 | .clk = { |
153 | .name = "clk_pclk_to_wdt_pwm", | 147 | .name = "clk_pclk_to_wdt_pwm", |
154 | .id = -1, | ||
155 | .parent = &clk_dout_pwm_ratio0.clk, | 148 | .parent = &clk_dout_pwm_ratio0.clk, |
156 | }, | 149 | }, |
157 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, | 150 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, |
@@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = { | |||
160 | static struct clksrc_clk clk_hclk_low = { | 153 | static struct clksrc_clk clk_hclk_low = { |
161 | .clk = { | 154 | .clk = { |
162 | .name = "clk_hclk_low", | 155 | .name = "clk_hclk_low", |
163 | .id = -1, | ||
164 | }, | 156 | }, |
165 | .sources = &clkset_hclk_low, | 157 | .sources = &clkset_hclk_low, |
166 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, | 158 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, |
@@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = { | |||
170 | static struct clksrc_clk clk_pclk_low = { | 162 | static struct clksrc_clk clk_pclk_low = { |
171 | .clk = { | 163 | .clk = { |
172 | .name = "clk_pclk_low", | 164 | .name = "clk_pclk_low", |
173 | .id = -1, | ||
174 | .parent = &clk_hclk_low.clk, | 165 | .parent = &clk_hclk_low.clk, |
175 | }, | 166 | }, |
176 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, | 167 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, |
@@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = { | |||
184 | static struct clk init_clocks_off[] = { | 175 | static struct clk init_clocks_off[] = { |
185 | { | 176 | { |
186 | .name = "usbhost", | 177 | .name = "usbhost", |
187 | .id = -1, | ||
188 | .parent = &clk_hclk_low.clk, | 178 | .parent = &clk_hclk_low.clk, |
189 | .enable = s5p64x0_hclk0_ctrl, | 179 | .enable = s5p64x0_hclk0_ctrl, |
190 | .ctrlbit = (1 << 3), | 180 | .ctrlbit = (1 << 3), |
191 | }, { | 181 | }, { |
192 | .name = "pdma", | 182 | .name = "pdma", |
193 | .id = -1, | ||
194 | .parent = &clk_hclk_low.clk, | 183 | .parent = &clk_hclk_low.clk, |
195 | .enable = s5p64x0_hclk0_ctrl, | 184 | .enable = s5p64x0_hclk0_ctrl, |
196 | .ctrlbit = (1 << 12), | 185 | .ctrlbit = (1 << 12), |
197 | }, { | 186 | }, { |
198 | .name = "hsmmc", | 187 | .name = "hsmmc", |
199 | .id = 0, | 188 | .devname = "s3c-sdhci.0", |
200 | .parent = &clk_hclk_low.clk, | 189 | .parent = &clk_hclk_low.clk, |
201 | .enable = s5p64x0_hclk0_ctrl, | 190 | .enable = s5p64x0_hclk0_ctrl, |
202 | .ctrlbit = (1 << 17), | 191 | .ctrlbit = (1 << 17), |
203 | }, { | 192 | }, { |
204 | .name = "hsmmc", | 193 | .name = "hsmmc", |
205 | .id = 1, | 194 | .devname = "s3c-sdhci.1", |
206 | .parent = &clk_hclk_low.clk, | 195 | .parent = &clk_hclk_low.clk, |
207 | .enable = s5p64x0_hclk0_ctrl, | 196 | .enable = s5p64x0_hclk0_ctrl, |
208 | .ctrlbit = (1 << 18), | 197 | .ctrlbit = (1 << 18), |
209 | }, { | 198 | }, { |
210 | .name = "hsmmc", | 199 | .name = "hsmmc", |
211 | .id = 2, | 200 | .devname = "s3c-sdhci.2", |
212 | .parent = &clk_hclk_low.clk, | 201 | .parent = &clk_hclk_low.clk, |
213 | .enable = s5p64x0_hclk0_ctrl, | 202 | .enable = s5p64x0_hclk0_ctrl, |
214 | .ctrlbit = (1 << 19), | 203 | .ctrlbit = (1 << 19), |
215 | }, { | 204 | }, { |
216 | .name = "usbotg", | 205 | .name = "usbotg", |
217 | .id = -1, | ||
218 | .parent = &clk_hclk_low.clk, | 206 | .parent = &clk_hclk_low.clk, |
219 | .enable = s5p64x0_hclk0_ctrl, | 207 | .enable = s5p64x0_hclk0_ctrl, |
220 | .ctrlbit = (1 << 20), | 208 | .ctrlbit = (1 << 20), |
221 | }, { | 209 | }, { |
222 | .name = "lcd", | 210 | .name = "lcd", |
223 | .id = -1, | ||
224 | .parent = &clk_h, | 211 | .parent = &clk_h, |
225 | .enable = s5p64x0_hclk1_ctrl, | 212 | .enable = s5p64x0_hclk1_ctrl, |
226 | .ctrlbit = (1 << 1), | 213 | .ctrlbit = (1 << 1), |
227 | }, { | 214 | }, { |
228 | .name = "watchdog", | 215 | .name = "watchdog", |
229 | .id = -1, | ||
230 | .parent = &clk_pclk_low.clk, | 216 | .parent = &clk_pclk_low.clk, |
231 | .enable = s5p64x0_pclk_ctrl, | 217 | .enable = s5p64x0_pclk_ctrl, |
232 | .ctrlbit = (1 << 5), | 218 | .ctrlbit = (1 << 5), |
233 | }, { | 219 | }, { |
234 | .name = "rtc", | 220 | .name = "rtc", |
235 | .id = -1, | ||
236 | .parent = &clk_pclk_low.clk, | 221 | .parent = &clk_pclk_low.clk, |
237 | .enable = s5p64x0_pclk_ctrl, | 222 | .enable = s5p64x0_pclk_ctrl, |
238 | .ctrlbit = (1 << 6), | 223 | .ctrlbit = (1 << 6), |
239 | }, { | 224 | }, { |
240 | .name = "adc", | 225 | .name = "adc", |
241 | .id = -1, | ||
242 | .parent = &clk_pclk_low.clk, | 226 | .parent = &clk_pclk_low.clk, |
243 | .enable = s5p64x0_pclk_ctrl, | 227 | .enable = s5p64x0_pclk_ctrl, |
244 | .ctrlbit = (1 << 12), | 228 | .ctrlbit = (1 << 12), |
245 | }, { | 229 | }, { |
246 | .name = "i2c", | 230 | .name = "i2c", |
247 | .id = 0, | 231 | .devname = "s3c2440-i2c.0", |
248 | .parent = &clk_pclk_low.clk, | 232 | .parent = &clk_pclk_low.clk, |
249 | .enable = s5p64x0_pclk_ctrl, | 233 | .enable = s5p64x0_pclk_ctrl, |
250 | .ctrlbit = (1 << 17), | 234 | .ctrlbit = (1 << 17), |
251 | }, { | 235 | }, { |
252 | .name = "spi", | 236 | .name = "spi", |
253 | .id = 0, | 237 | .devname = "s3c64xx-spi.0", |
254 | .parent = &clk_pclk_low.clk, | 238 | .parent = &clk_pclk_low.clk, |
255 | .enable = s5p64x0_pclk_ctrl, | 239 | .enable = s5p64x0_pclk_ctrl, |
256 | .ctrlbit = (1 << 21), | 240 | .ctrlbit = (1 << 21), |
257 | }, { | 241 | }, { |
258 | .name = "spi", | 242 | .name = "spi", |
259 | .id = 1, | 243 | .devname = "s3c64xx-spi.1", |
260 | .parent = &clk_pclk_low.clk, | 244 | .parent = &clk_pclk_low.clk, |
261 | .enable = s5p64x0_pclk_ctrl, | 245 | .enable = s5p64x0_pclk_ctrl, |
262 | .ctrlbit = (1 << 22), | 246 | .ctrlbit = (1 << 22), |
263 | }, { | 247 | }, { |
264 | .name = "iis", | 248 | .name = "iis", |
265 | .id = 0, | 249 | .devname = "samsung-i2s.0", |
266 | .parent = &clk_pclk_low.clk, | 250 | .parent = &clk_pclk_low.clk, |
267 | .enable = s5p64x0_pclk_ctrl, | 251 | .enable = s5p64x0_pclk_ctrl, |
268 | .ctrlbit = (1 << 26), | 252 | .ctrlbit = (1 << 26), |
269 | }, { | 253 | }, { |
270 | .name = "iis", | 254 | .name = "iis", |
271 | .id = 1, | 255 | .devname = "samsung-i2s.1", |
272 | .parent = &clk_pclk_low.clk, | 256 | .parent = &clk_pclk_low.clk, |
273 | .enable = s5p64x0_pclk_ctrl, | 257 | .enable = s5p64x0_pclk_ctrl, |
274 | .ctrlbit = (1 << 15), | 258 | .ctrlbit = (1 << 15), |
275 | }, { | 259 | }, { |
276 | .name = "iis", | 260 | .name = "iis", |
277 | .id = 2, | 261 | .devname = "samsung-i2s.2", |
278 | .parent = &clk_pclk_low.clk, | 262 | .parent = &clk_pclk_low.clk, |
279 | .enable = s5p64x0_pclk_ctrl, | 263 | .enable = s5p64x0_pclk_ctrl, |
280 | .ctrlbit = (1 << 16), | 264 | .ctrlbit = (1 << 16), |
281 | }, { | 265 | }, { |
282 | .name = "i2c", | 266 | .name = "i2c", |
283 | .id = 1, | 267 | .devname = "s3c2440-i2c.1", |
284 | .parent = &clk_pclk_low.clk, | 268 | .parent = &clk_pclk_low.clk, |
285 | .enable = s5p64x0_pclk_ctrl, | 269 | .enable = s5p64x0_pclk_ctrl, |
286 | .ctrlbit = (1 << 27), | 270 | .ctrlbit = (1 << 27), |
287 | }, { | 271 | }, { |
288 | .name = "dmc0", | 272 | .name = "dmc0", |
289 | .id = -1, | ||
290 | .parent = &clk_pclk.clk, | 273 | .parent = &clk_pclk.clk, |
291 | .enable = s5p64x0_pclk_ctrl, | 274 | .enable = s5p64x0_pclk_ctrl, |
292 | .ctrlbit = (1 << 30), | 275 | .ctrlbit = (1 << 30), |
@@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = { | |||
299 | static struct clk init_clocks[] = { | 282 | static struct clk init_clocks[] = { |
300 | { | 283 | { |
301 | .name = "intc", | 284 | .name = "intc", |
302 | .id = -1, | ||
303 | .parent = &clk_hclk.clk, | 285 | .parent = &clk_hclk.clk, |
304 | .enable = s5p64x0_hclk0_ctrl, | 286 | .enable = s5p64x0_hclk0_ctrl, |
305 | .ctrlbit = (1 << 1), | 287 | .ctrlbit = (1 << 1), |
306 | }, { | 288 | }, { |
307 | .name = "mem", | 289 | .name = "mem", |
308 | .id = -1, | ||
309 | .parent = &clk_hclk.clk, | 290 | .parent = &clk_hclk.clk, |
310 | .enable = s5p64x0_hclk0_ctrl, | 291 | .enable = s5p64x0_hclk0_ctrl, |
311 | .ctrlbit = (1 << 21), | 292 | .ctrlbit = (1 << 21), |
312 | }, { | 293 | }, { |
313 | .name = "uart", | 294 | .name = "uart", |
314 | .id = 0, | 295 | .devname = "s3c6400-uart.0", |
315 | .parent = &clk_pclk_low.clk, | 296 | .parent = &clk_pclk_low.clk, |
316 | .enable = s5p64x0_pclk_ctrl, | 297 | .enable = s5p64x0_pclk_ctrl, |
317 | .ctrlbit = (1 << 1), | 298 | .ctrlbit = (1 << 1), |
318 | }, { | 299 | }, { |
319 | .name = "uart", | 300 | .name = "uart", |
320 | .id = 1, | 301 | .devname = "s3c6400-uart.1", |
321 | .parent = &clk_pclk_low.clk, | 302 | .parent = &clk_pclk_low.clk, |
322 | .enable = s5p64x0_pclk_ctrl, | 303 | .enable = s5p64x0_pclk_ctrl, |
323 | .ctrlbit = (1 << 2), | 304 | .ctrlbit = (1 << 2), |
324 | }, { | 305 | }, { |
325 | .name = "uart", | 306 | .name = "uart", |
326 | .id = 2, | 307 | .devname = "s3c6400-uart.2", |
327 | .parent = &clk_pclk_low.clk, | 308 | .parent = &clk_pclk_low.clk, |
328 | .enable = s5p64x0_pclk_ctrl, | 309 | .enable = s5p64x0_pclk_ctrl, |
329 | .ctrlbit = (1 << 3), | 310 | .ctrlbit = (1 << 3), |
330 | }, { | 311 | }, { |
331 | .name = "uart", | 312 | .name = "uart", |
332 | .id = 3, | 313 | .devname = "s3c6400-uart.3", |
333 | .parent = &clk_pclk_low.clk, | 314 | .parent = &clk_pclk_low.clk, |
334 | .enable = s5p64x0_pclk_ctrl, | 315 | .enable = s5p64x0_pclk_ctrl, |
335 | .ctrlbit = (1 << 4), | 316 | .ctrlbit = (1 << 4), |
336 | }, { | 317 | }, { |
337 | .name = "timers", | 318 | .name = "timers", |
338 | .id = -1, | ||
339 | .parent = &clk_pclk_to_wdt_pwm.clk, | 319 | .parent = &clk_pclk_to_wdt_pwm.clk, |
340 | .enable = s5p64x0_pclk_ctrl, | 320 | .enable = s5p64x0_pclk_ctrl, |
341 | .ctrlbit = (1 << 7), | 321 | .ctrlbit = (1 << 7), |
342 | }, { | 322 | }, { |
343 | .name = "gpio", | 323 | .name = "gpio", |
344 | .id = -1, | ||
345 | .parent = &clk_pclk_low.clk, | 324 | .parent = &clk_pclk_low.clk, |
346 | .enable = s5p64x0_pclk_ctrl, | 325 | .enable = s5p64x0_pclk_ctrl, |
347 | .ctrlbit = (1 << 18), | 326 | .ctrlbit = (1 << 18), |
@@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = { | |||
421 | static struct clksrc_clk clk_sclk_audio0 = { | 400 | static struct clksrc_clk clk_sclk_audio0 = { |
422 | .clk = { | 401 | .clk = { |
423 | .name = "audio-bus", | 402 | .name = "audio-bus", |
424 | .id = -1, | ||
425 | .enable = s5p64x0_sclk_ctrl, | 403 | .enable = s5p64x0_sclk_ctrl, |
426 | .ctrlbit = (1 << 8), | 404 | .ctrlbit = (1 << 8), |
427 | .parent = &clk_dout_epll.clk, | 405 | .parent = &clk_dout_epll.clk, |
@@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = { | |||
435 | { | 413 | { |
436 | .clk = { | 414 | .clk = { |
437 | .name = "sclk_mmc", | 415 | .name = "sclk_mmc", |
438 | .id = 0, | 416 | .devname = "s3c-sdhci.0", |
439 | .ctrlbit = (1 << 24), | 417 | .ctrlbit = (1 << 24), |
440 | .enable = s5p64x0_sclk_ctrl, | 418 | .enable = s5p64x0_sclk_ctrl, |
441 | }, | 419 | }, |
@@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = { | |||
445 | }, { | 423 | }, { |
446 | .clk = { | 424 | .clk = { |
447 | .name = "sclk_mmc", | 425 | .name = "sclk_mmc", |
448 | .id = 1, | 426 | .devname = "s3c-sdhci.1", |
449 | .ctrlbit = (1 << 25), | 427 | .ctrlbit = (1 << 25), |
450 | .enable = s5p64x0_sclk_ctrl, | 428 | .enable = s5p64x0_sclk_ctrl, |
451 | }, | 429 | }, |
@@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = { | |||
455 | }, { | 433 | }, { |
456 | .clk = { | 434 | .clk = { |
457 | .name = "sclk_mmc", | 435 | .name = "sclk_mmc", |
458 | .id = 2, | 436 | .devname = "s3c-sdhci.2", |
459 | .ctrlbit = (1 << 26), | 437 | .ctrlbit = (1 << 26), |
460 | .enable = s5p64x0_sclk_ctrl, | 438 | .enable = s5p64x0_sclk_ctrl, |
461 | }, | 439 | }, |
@@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = { | |||
465 | }, { | 443 | }, { |
466 | .clk = { | 444 | .clk = { |
467 | .name = "uclk1", | 445 | .name = "uclk1", |
468 | .id = -1, | ||
469 | .ctrlbit = (1 << 5), | 446 | .ctrlbit = (1 << 5), |
470 | .enable = s5p64x0_sclk_ctrl, | 447 | .enable = s5p64x0_sclk_ctrl, |
471 | }, | 448 | }, |
@@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = { | |||
475 | }, { | 452 | }, { |
476 | .clk = { | 453 | .clk = { |
477 | .name = "sclk_spi", | 454 | .name = "sclk_spi", |
478 | .id = 0, | 455 | .devname = "s3c64xx-spi.0", |
479 | .ctrlbit = (1 << 20), | 456 | .ctrlbit = (1 << 20), |
480 | .enable = s5p64x0_sclk_ctrl, | 457 | .enable = s5p64x0_sclk_ctrl, |
481 | }, | 458 | }, |
@@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = { | |||
485 | }, { | 462 | }, { |
486 | .clk = { | 463 | .clk = { |
487 | .name = "sclk_spi", | 464 | .name = "sclk_spi", |
488 | .id = 1, | 465 | .devname = "s3c64xx-spi.1", |
489 | .ctrlbit = (1 << 21), | 466 | .ctrlbit = (1 << 21), |
490 | .enable = s5p64x0_sclk_ctrl, | 467 | .enable = s5p64x0_sclk_ctrl, |
491 | }, | 468 | }, |
@@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = { | |||
495 | }, { | 472 | }, { |
496 | .clk = { | 473 | .clk = { |
497 | .name = "sclk_fimc", | 474 | .name = "sclk_fimc", |
498 | .id = -1, | ||
499 | .ctrlbit = (1 << 10), | 475 | .ctrlbit = (1 << 10), |
500 | .enable = s5p64x0_sclk_ctrl, | 476 | .enable = s5p64x0_sclk_ctrl, |
501 | }, | 477 | }, |
@@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = { | |||
505 | }, { | 481 | }, { |
506 | .clk = { | 482 | .clk = { |
507 | .name = "aclk_mali", | 483 | .name = "aclk_mali", |
508 | .id = -1, | ||
509 | .ctrlbit = (1 << 2), | 484 | .ctrlbit = (1 << 2), |
510 | .enable = s5p64x0_sclk1_ctrl, | 485 | .enable = s5p64x0_sclk1_ctrl, |
511 | }, | 486 | }, |
@@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = { | |||
515 | }, { | 490 | }, { |
516 | .clk = { | 491 | .clk = { |
517 | .name = "sclk_2d", | 492 | .name = "sclk_2d", |
518 | .id = -1, | ||
519 | .ctrlbit = (1 << 12), | 493 | .ctrlbit = (1 << 12), |
520 | .enable = s5p64x0_sclk_ctrl, | 494 | .enable = s5p64x0_sclk_ctrl, |
521 | }, | 495 | }, |
@@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = { | |||
525 | }, { | 499 | }, { |
526 | .clk = { | 500 | .clk = { |
527 | .name = "sclk_usi", | 501 | .name = "sclk_usi", |
528 | .id = -1, | ||
529 | .ctrlbit = (1 << 7), | 502 | .ctrlbit = (1 << 7), |
530 | .enable = s5p64x0_sclk_ctrl, | 503 | .enable = s5p64x0_sclk_ctrl, |
531 | }, | 504 | }, |
@@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = { | |||
535 | }, { | 508 | }, { |
536 | .clk = { | 509 | .clk = { |
537 | .name = "sclk_camif", | 510 | .name = "sclk_camif", |
538 | .id = -1, | ||
539 | .ctrlbit = (1 << 6), | 511 | .ctrlbit = (1 << 6), |
540 | .enable = s5p64x0_sclk_ctrl, | 512 | .enable = s5p64x0_sclk_ctrl, |
541 | }, | 513 | }, |
@@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = { | |||
545 | }, { | 517 | }, { |
546 | .clk = { | 518 | .clk = { |
547 | .name = "sclk_dispcon", | 519 | .name = "sclk_dispcon", |
548 | .id = -1, | ||
549 | .ctrlbit = (1 << 1), | 520 | .ctrlbit = (1 << 1), |
550 | .enable = s5p64x0_sclk1_ctrl, | 521 | .enable = s5p64x0_sclk1_ctrl, |
551 | }, | 522 | }, |
@@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = { | |||
555 | }, { | 526 | }, { |
556 | .clk = { | 527 | .clk = { |
557 | .name = "sclk_hsmmc44", | 528 | .name = "sclk_hsmmc44", |
558 | .id = -1, | ||
559 | .ctrlbit = (1 << 30), | 529 | .ctrlbit = (1 << 30), |
560 | .enable = s5p64x0_sclk_ctrl, | 530 | .enable = s5p64x0_sclk_ctrl, |
561 | }, | 531 | }, |
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c index e78ee18c76e3..ac825e826326 100644 --- a/arch/arm/mach-s5p64x0/dev-spi.c +++ b/arch/arm/mach-s5p64x0/dev-spi.c | |||
@@ -112,12 +112,14 @@ static struct s3c64xx_spi_info s5p6440_spi0_pdata = { | |||
112 | .cfg_gpio = s5p6440_spi_cfg_gpio, | 112 | .cfg_gpio = s5p6440_spi_cfg_gpio, |
113 | .fifo_lvl_mask = 0x1ff, | 113 | .fifo_lvl_mask = 0x1ff, |
114 | .rx_lvl_offset = 15, | 114 | .rx_lvl_offset = 15, |
115 | .tx_st_done = 25, | ||
115 | }; | 116 | }; |
116 | 117 | ||
117 | static struct s3c64xx_spi_info s5p6450_spi0_pdata = { | 118 | static struct s3c64xx_spi_info s5p6450_spi0_pdata = { |
118 | .cfg_gpio = s5p6450_spi_cfg_gpio, | 119 | .cfg_gpio = s5p6450_spi_cfg_gpio, |
119 | .fifo_lvl_mask = 0x1ff, | 120 | .fifo_lvl_mask = 0x1ff, |
120 | .rx_lvl_offset = 15, | 121 | .rx_lvl_offset = 15, |
122 | .tx_st_done = 25, | ||
121 | }; | 123 | }; |
122 | 124 | ||
123 | static u64 spi_dmamask = DMA_BIT_MASK(32); | 125 | static u64 spi_dmamask = DMA_BIT_MASK(32); |
@@ -160,12 +162,14 @@ static struct s3c64xx_spi_info s5p6440_spi1_pdata = { | |||
160 | .cfg_gpio = s5p6440_spi_cfg_gpio, | 162 | .cfg_gpio = s5p6440_spi_cfg_gpio, |
161 | .fifo_lvl_mask = 0x7f, | 163 | .fifo_lvl_mask = 0x7f, |
162 | .rx_lvl_offset = 15, | 164 | .rx_lvl_offset = 15, |
165 | .tx_st_done = 25, | ||
163 | }; | 166 | }; |
164 | 167 | ||
165 | static struct s3c64xx_spi_info s5p6450_spi1_pdata = { | 168 | static struct s3c64xx_spi_info s5p6450_spi1_pdata = { |
166 | .cfg_gpio = s5p6450_spi_cfg_gpio, | 169 | .cfg_gpio = s5p6450_spi_cfg_gpio, |
167 | .fifo_lvl_mask = 0x7f, | 170 | .fifo_lvl_mask = 0x7f, |
168 | .rx_lvl_offset = 15, | 171 | .rx_lvl_offset = 15, |
172 | .tx_st_done = 25, | ||
169 | }; | 173 | }; |
170 | 174 | ||
171 | struct platform_device s5p64x0_device_spi1 = { | 175 | struct platform_device s5p64x0_device_spi1 = { |
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s5p64x0/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 2d559f10fd47..346f8dfa6f35 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c | |||
@@ -46,6 +46,7 @@ | |||
46 | #include <plat/adc.h> | 46 | #include <plat/adc.h> |
47 | #include <plat/ts.h> | 47 | #include <plat/ts.h> |
48 | #include <plat/s5p-time.h> | 48 | #include <plat/s5p-time.h> |
49 | #include <plat/backlight.h> | ||
49 | 50 | ||
50 | #define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 51 | #define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
51 | S3C2410_UCON_RXILEVEL | \ | 52 | S3C2410_UCON_RXILEVEL | \ |
@@ -91,45 +92,6 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { | |||
91 | }, | 92 | }, |
92 | }; | 93 | }; |
93 | 94 | ||
94 | static int smdk6440_backlight_init(struct device *dev) | ||
95 | { | ||
96 | int ret; | ||
97 | |||
98 | ret = gpio_request(S5P6440_GPF(15), "Backlight"); | ||
99 | if (ret) { | ||
100 | printk(KERN_ERR "failed to request GPF for PWM-OUT1\n"); | ||
101 | return ret; | ||
102 | } | ||
103 | |||
104 | /* Configure GPIO pin with S5P6440_GPF15_PWM_TOUT1 */ | ||
105 | s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_SFN(2)); | ||
106 | |||
107 | return 0; | ||
108 | } | ||
109 | |||
110 | static void smdk6440_backlight_exit(struct device *dev) | ||
111 | { | ||
112 | s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_OUTPUT); | ||
113 | gpio_free(S5P6440_GPF(15)); | ||
114 | } | ||
115 | |||
116 | static struct platform_pwm_backlight_data smdk6440_backlight_data = { | ||
117 | .pwm_id = 1, | ||
118 | .max_brightness = 255, | ||
119 | .dft_brightness = 255, | ||
120 | .pwm_period_ns = 78770, | ||
121 | .init = smdk6440_backlight_init, | ||
122 | .exit = smdk6440_backlight_exit, | ||
123 | }; | ||
124 | |||
125 | static struct platform_device smdk6440_backlight_device = { | ||
126 | .name = "pwm-backlight", | ||
127 | .dev = { | ||
128 | .parent = &s3c_device_timer[1].dev, | ||
129 | .platform_data = &smdk6440_backlight_data, | ||
130 | }, | ||
131 | }; | ||
132 | |||
133 | static struct platform_device *smdk6440_devices[] __initdata = { | 95 | static struct platform_device *smdk6440_devices[] __initdata = { |
134 | &s3c_device_adc, | 96 | &s3c_device_adc, |
135 | &s3c_device_rtc, | 97 | &s3c_device_rtc, |
@@ -139,8 +101,6 @@ static struct platform_device *smdk6440_devices[] __initdata = { | |||
139 | &s3c_device_wdt, | 101 | &s3c_device_wdt, |
140 | &samsung_asoc_dma, | 102 | &samsung_asoc_dma, |
141 | &s5p6440_device_iis, | 103 | &s5p6440_device_iis, |
142 | &s3c_device_timer[1], | ||
143 | &smdk6440_backlight_device, | ||
144 | }; | 104 | }; |
145 | 105 | ||
146 | static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { | 106 | static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { |
@@ -175,6 +135,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | |||
175 | .oversampling_shift = 2, | 135 | .oversampling_shift = 2, |
176 | }; | 136 | }; |
177 | 137 | ||
138 | /* LCD Backlight data */ | ||
139 | static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = { | ||
140 | .no = S5P6440_GPF(15), | ||
141 | .func = S3C_GPIO_SFN(2), | ||
142 | }; | ||
143 | |||
144 | static struct platform_pwm_backlight_data smdk6440_bl_data = { | ||
145 | .pwm_id = 1, | ||
146 | }; | ||
147 | |||
178 | static void __init smdk6440_map_io(void) | 148 | static void __init smdk6440_map_io(void) |
179 | { | 149 | { |
180 | s5p_init_io(NULL, 0, S5P64X0_SYS_ID); | 150 | s5p_init_io(NULL, 0, S5P64X0_SYS_ID); |
@@ -194,6 +164,8 @@ static void __init smdk6440_machine_init(void) | |||
194 | i2c_register_board_info(1, smdk6440_i2c_devs1, | 164 | i2c_register_board_info(1, smdk6440_i2c_devs1, |
195 | ARRAY_SIZE(smdk6440_i2c_devs1)); | 165 | ARRAY_SIZE(smdk6440_i2c_devs1)); |
196 | 166 | ||
167 | samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data); | ||
168 | |||
197 | platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); | 169 | platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); |
198 | } | 170 | } |
199 | 171 | ||
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index d19c4690ee97..33f2adf8f3fe 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c | |||
@@ -46,6 +46,7 @@ | |||
46 | #include <plat/adc.h> | 46 | #include <plat/adc.h> |
47 | #include <plat/ts.h> | 47 | #include <plat/ts.h> |
48 | #include <plat/s5p-time.h> | 48 | #include <plat/s5p-time.h> |
49 | #include <plat/backlight.h> | ||
49 | 50 | ||
50 | #define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 51 | #define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
51 | S3C2410_UCON_RXILEVEL | \ | 52 | S3C2410_UCON_RXILEVEL | \ |
@@ -109,45 +110,6 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = { | |||
109 | #endif | 110 | #endif |
110 | }; | 111 | }; |
111 | 112 | ||
112 | static int smdk6450_backlight_init(struct device *dev) | ||
113 | { | ||
114 | int ret; | ||
115 | |||
116 | ret = gpio_request(S5P6450_GPF(15), "Backlight"); | ||
117 | if (ret) { | ||
118 | printk(KERN_ERR "failed to request GPF for PWM-OUT1\n"); | ||
119 | return ret; | ||
120 | } | ||
121 | |||
122 | /* Configure GPIO pin with S5P6450_GPF15_PWM_TOUT1 */ | ||
123 | s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_SFN(2)); | ||
124 | |||
125 | return 0; | ||
126 | } | ||
127 | |||
128 | static void smdk6450_backlight_exit(struct device *dev) | ||
129 | { | ||
130 | s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_OUTPUT); | ||
131 | gpio_free(S5P6450_GPF(15)); | ||
132 | } | ||
133 | |||
134 | static struct platform_pwm_backlight_data smdk6450_backlight_data = { | ||
135 | .pwm_id = 1, | ||
136 | .max_brightness = 255, | ||
137 | .dft_brightness = 255, | ||
138 | .pwm_period_ns = 78770, | ||
139 | .init = smdk6450_backlight_init, | ||
140 | .exit = smdk6450_backlight_exit, | ||
141 | }; | ||
142 | |||
143 | static struct platform_device smdk6450_backlight_device = { | ||
144 | .name = "pwm-backlight", | ||
145 | .dev = { | ||
146 | .parent = &s3c_device_timer[1].dev, | ||
147 | .platform_data = &smdk6450_backlight_data, | ||
148 | }, | ||
149 | }; | ||
150 | |||
151 | static struct platform_device *smdk6450_devices[] __initdata = { | 113 | static struct platform_device *smdk6450_devices[] __initdata = { |
152 | &s3c_device_adc, | 114 | &s3c_device_adc, |
153 | &s3c_device_rtc, | 115 | &s3c_device_rtc, |
@@ -157,8 +119,6 @@ static struct platform_device *smdk6450_devices[] __initdata = { | |||
157 | &s3c_device_wdt, | 119 | &s3c_device_wdt, |
158 | &samsung_asoc_dma, | 120 | &samsung_asoc_dma, |
159 | &s5p6450_device_iis0, | 121 | &s5p6450_device_iis0, |
160 | &s3c_device_timer[1], | ||
161 | &smdk6450_backlight_device, | ||
162 | /* s5p6450_device_spi0 will be added */ | 122 | /* s5p6450_device_spi0 will be added */ |
163 | }; | 123 | }; |
164 | 124 | ||
@@ -194,6 +154,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | |||
194 | .oversampling_shift = 2, | 154 | .oversampling_shift = 2, |
195 | }; | 155 | }; |
196 | 156 | ||
157 | /* LCD Backlight data */ | ||
158 | static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = { | ||
159 | .no = S5P6450_GPF(15), | ||
160 | .func = S3C_GPIO_SFN(2), | ||
161 | }; | ||
162 | |||
163 | static struct platform_pwm_backlight_data smdk6450_bl_data = { | ||
164 | .pwm_id = 1, | ||
165 | }; | ||
166 | |||
197 | static void __init smdk6450_map_io(void) | 167 | static void __init smdk6450_map_io(void) |
198 | { | 168 | { |
199 | s5p_init_io(NULL, 0, S5P64X0_SYS_ID); | 169 | s5p_init_io(NULL, 0, S5P64X0_SYS_ID); |
@@ -213,6 +183,8 @@ static void __init smdk6450_machine_init(void) | |||
213 | i2c_register_board_info(1, smdk6450_i2c_devs1, | 183 | i2c_register_board_info(1, smdk6450_i2c_devs1, |
214 | ARRAY_SIZE(smdk6450_i2c_devs1)); | 184 | ARRAY_SIZE(smdk6450_i2c_devs1)); |
215 | 185 | ||
186 | samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data); | ||
187 | |||
216 | platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); | 188 | platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); |
217 | } | 189 | } |
218 | 190 | ||
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index 608722ff4f28..e8a33c4b054c 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig | |||
@@ -56,6 +56,7 @@ config MACH_SMDKC100 | |||
56 | select S3C_DEV_RTC | 56 | select S3C_DEV_RTC |
57 | select S3C_DEV_WDT | 57 | select S3C_DEV_WDT |
58 | select SAMSUNG_DEV_ADC | 58 | select SAMSUNG_DEV_ADC |
59 | select SAMSUNG_DEV_BACKLIGHT | ||
59 | select SAMSUNG_DEV_IDE | 60 | select SAMSUNG_DEV_IDE |
60 | select SAMSUNG_DEV_KEYPAD | 61 | select SAMSUNG_DEV_KEYPAD |
61 | select SAMSUNG_DEV_PWM | 62 | select SAMSUNG_DEV_PWM |
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 0305e9b8282d..ff5cbb30de5b 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c | |||
@@ -31,7 +31,6 @@ | |||
31 | 31 | ||
32 | static struct clk s5p_clk_otgphy = { | 32 | static struct clk s5p_clk_otgphy = { |
33 | .name = "otg_phy", | 33 | .name = "otg_phy", |
34 | .id = -1, | ||
35 | }; | 34 | }; |
36 | 35 | ||
37 | static struct clk *clk_src_mout_href_list[] = { | 36 | static struct clk *clk_src_mout_href_list[] = { |
@@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = { | |||
47 | static struct clksrc_clk clk_mout_href = { | 46 | static struct clksrc_clk clk_mout_href = { |
48 | .clk = { | 47 | .clk = { |
49 | .name = "mout_href", | 48 | .name = "mout_href", |
50 | .id = -1, | ||
51 | }, | 49 | }, |
52 | .sources = &clk_src_mout_href, | 50 | .sources = &clk_src_mout_href, |
53 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | 51 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, |
@@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = { | |||
66 | static struct clksrc_clk clk_mout_48m = { | 64 | static struct clksrc_clk clk_mout_48m = { |
67 | .clk = { | 65 | .clk = { |
68 | .name = "mout_48m", | 66 | .name = "mout_48m", |
69 | .id = -1, | ||
70 | }, | 67 | }, |
71 | .sources = &clk_src_mout_48m, | 68 | .sources = &clk_src_mout_48m, |
72 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, | 69 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, |
@@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = { | |||
75 | static struct clksrc_clk clk_mout_mpll = { | 72 | static struct clksrc_clk clk_mout_mpll = { |
76 | .clk = { | 73 | .clk = { |
77 | .name = "mout_mpll", | 74 | .name = "mout_mpll", |
78 | .id = -1, | ||
79 | }, | 75 | }, |
80 | .sources = &clk_src_mpll, | 76 | .sources = &clk_src_mpll, |
81 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | 77 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, |
@@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = { | |||
85 | static struct clksrc_clk clk_mout_apll = { | 81 | static struct clksrc_clk clk_mout_apll = { |
86 | .clk = { | 82 | .clk = { |
87 | .name = "mout_apll", | 83 | .name = "mout_apll", |
88 | .id = -1, | ||
89 | }, | 84 | }, |
90 | .sources = &clk_src_apll, | 85 | .sources = &clk_src_apll, |
91 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | 86 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, |
@@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = { | |||
94 | static struct clksrc_clk clk_mout_epll = { | 89 | static struct clksrc_clk clk_mout_epll = { |
95 | .clk = { | 90 | .clk = { |
96 | .name = "mout_epll", | 91 | .name = "mout_epll", |
97 | .id = -1, | ||
98 | }, | 92 | }, |
99 | .sources = &clk_src_epll, | 93 | .sources = &clk_src_epll, |
100 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | 94 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, |
@@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = { | |||
112 | static struct clksrc_clk clk_mout_hpll = { | 106 | static struct clksrc_clk clk_mout_hpll = { |
113 | .clk = { | 107 | .clk = { |
114 | .name = "mout_hpll", | 108 | .name = "mout_hpll", |
115 | .id = -1, | ||
116 | }, | 109 | }, |
117 | .sources = &clk_src_mout_hpll, | 110 | .sources = &clk_src_mout_hpll, |
118 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | 111 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, |
@@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = { | |||
121 | static struct clksrc_clk clk_div_apll = { | 114 | static struct clksrc_clk clk_div_apll = { |
122 | .clk = { | 115 | .clk = { |
123 | .name = "div_apll", | 116 | .name = "div_apll", |
124 | .id = -1, | ||
125 | .parent = &clk_mout_apll.clk, | 117 | .parent = &clk_mout_apll.clk, |
126 | }, | 118 | }, |
127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, | 119 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, |
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = { | |||
130 | static struct clksrc_clk clk_div_arm = { | 122 | static struct clksrc_clk clk_div_arm = { |
131 | .clk = { | 123 | .clk = { |
132 | .name = "div_arm", | 124 | .name = "div_arm", |
133 | .id = -1, | ||
134 | .parent = &clk_div_apll.clk, | 125 | .parent = &clk_div_apll.clk, |
135 | }, | 126 | }, |
136 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | 127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, |
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = { | |||
139 | static struct clksrc_clk clk_div_d0_bus = { | 130 | static struct clksrc_clk clk_div_d0_bus = { |
140 | .clk = { | 131 | .clk = { |
141 | .name = "div_d0_bus", | 132 | .name = "div_d0_bus", |
142 | .id = -1, | ||
143 | .parent = &clk_div_arm.clk, | 133 | .parent = &clk_div_arm.clk, |
144 | }, | 134 | }, |
145 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | 135 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, |
@@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = { | |||
148 | static struct clksrc_clk clk_div_pclkd0 = { | 138 | static struct clksrc_clk clk_div_pclkd0 = { |
149 | .clk = { | 139 | .clk = { |
150 | .name = "div_pclkd0", | 140 | .name = "div_pclkd0", |
151 | .id = -1, | ||
152 | .parent = &clk_div_d0_bus.clk, | 141 | .parent = &clk_div_d0_bus.clk, |
153 | }, | 142 | }, |
154 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | 143 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, |
@@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = { | |||
157 | static struct clksrc_clk clk_div_secss = { | 146 | static struct clksrc_clk clk_div_secss = { |
158 | .clk = { | 147 | .clk = { |
159 | .name = "div_secss", | 148 | .name = "div_secss", |
160 | .id = -1, | ||
161 | .parent = &clk_div_d0_bus.clk, | 149 | .parent = &clk_div_d0_bus.clk, |
162 | }, | 150 | }, |
163 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, | 151 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, |
@@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = { | |||
166 | static struct clksrc_clk clk_div_apll2 = { | 154 | static struct clksrc_clk clk_div_apll2 = { |
167 | .clk = { | 155 | .clk = { |
168 | .name = "div_apll2", | 156 | .name = "div_apll2", |
169 | .id = -1, | ||
170 | .parent = &clk_mout_apll.clk, | 157 | .parent = &clk_mout_apll.clk, |
171 | }, | 158 | }, |
172 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, | 159 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, |
@@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = { | |||
185 | static struct clksrc_clk clk_mout_am = { | 172 | static struct clksrc_clk clk_mout_am = { |
186 | .clk = { | 173 | .clk = { |
187 | .name = "mout_am", | 174 | .name = "mout_am", |
188 | .id = -1, | ||
189 | }, | 175 | }, |
190 | .sources = &clk_src_mout_am, | 176 | .sources = &clk_src_mout_am, |
191 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | 177 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, |
@@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = { | |||
194 | static struct clksrc_clk clk_div_d1_bus = { | 180 | static struct clksrc_clk clk_div_d1_bus = { |
195 | .clk = { | 181 | .clk = { |
196 | .name = "div_d1_bus", | 182 | .name = "div_d1_bus", |
197 | .id = -1, | ||
198 | .parent = &clk_mout_am.clk, | 183 | .parent = &clk_mout_am.clk, |
199 | }, | 184 | }, |
200 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, | 185 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, |
@@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = { | |||
203 | static struct clksrc_clk clk_div_mpll2 = { | 188 | static struct clksrc_clk clk_div_mpll2 = { |
204 | .clk = { | 189 | .clk = { |
205 | .name = "div_mpll2", | 190 | .name = "div_mpll2", |
206 | .id = -1, | ||
207 | .parent = &clk_mout_am.clk, | 191 | .parent = &clk_mout_am.clk, |
208 | }, | 192 | }, |
209 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, | 193 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, |
@@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = { | |||
212 | static struct clksrc_clk clk_div_mpll = { | 196 | static struct clksrc_clk clk_div_mpll = { |
213 | .clk = { | 197 | .clk = { |
214 | .name = "div_mpll", | 198 | .name = "div_mpll", |
215 | .id = -1, | ||
216 | .parent = &clk_mout_am.clk, | 199 | .parent = &clk_mout_am.clk, |
217 | }, | 200 | }, |
218 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, | 201 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, |
@@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = { | |||
231 | static struct clksrc_clk clk_mout_onenand = { | 214 | static struct clksrc_clk clk_mout_onenand = { |
232 | .clk = { | 215 | .clk = { |
233 | .name = "mout_onenand", | 216 | .name = "mout_onenand", |
234 | .id = -1, | ||
235 | }, | 217 | }, |
236 | .sources = &clk_src_mout_onenand, | 218 | .sources = &clk_src_mout_onenand, |
237 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | 219 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, |
@@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = { | |||
240 | static struct clksrc_clk clk_div_onenand = { | 222 | static struct clksrc_clk clk_div_onenand = { |
241 | .clk = { | 223 | .clk = { |
242 | .name = "div_onenand", | 224 | .name = "div_onenand", |
243 | .id = -1, | ||
244 | .parent = &clk_mout_onenand.clk, | 225 | .parent = &clk_mout_onenand.clk, |
245 | }, | 226 | }, |
246 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, | 227 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, |
@@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = { | |||
249 | static struct clksrc_clk clk_div_pclkd1 = { | 230 | static struct clksrc_clk clk_div_pclkd1 = { |
250 | .clk = { | 231 | .clk = { |
251 | .name = "div_pclkd1", | 232 | .name = "div_pclkd1", |
252 | .id = -1, | ||
253 | .parent = &clk_div_d1_bus.clk, | 233 | .parent = &clk_div_d1_bus.clk, |
254 | }, | 234 | }, |
255 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, | 235 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, |
@@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = { | |||
258 | static struct clksrc_clk clk_div_cam = { | 238 | static struct clksrc_clk clk_div_cam = { |
259 | .clk = { | 239 | .clk = { |
260 | .name = "div_cam", | 240 | .name = "div_cam", |
261 | .id = -1, | ||
262 | .parent = &clk_div_mpll2.clk, | 241 | .parent = &clk_div_mpll2.clk, |
263 | }, | 242 | }, |
264 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, | 243 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, |
@@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = { | |||
267 | static struct clksrc_clk clk_div_hdmi = { | 246 | static struct clksrc_clk clk_div_hdmi = { |
268 | .clk = { | 247 | .clk = { |
269 | .name = "div_hdmi", | 248 | .name = "div_hdmi", |
270 | .id = -1, | ||
271 | .parent = &clk_mout_hpll.clk, | 249 | .parent = &clk_mout_hpll.clk, |
272 | }, | 250 | }, |
273 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, | 251 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, |
@@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) | |||
399 | static struct clk init_clocks_off[] = { | 377 | static struct clk init_clocks_off[] = { |
400 | { | 378 | { |
401 | .name = "cssys", | 379 | .name = "cssys", |
402 | .id = -1, | ||
403 | .parent = &clk_div_d0_bus.clk, | 380 | .parent = &clk_div_d0_bus.clk, |
404 | .enable = s5pc100_d0_0_ctrl, | 381 | .enable = s5pc100_d0_0_ctrl, |
405 | .ctrlbit = (1 << 6), | 382 | .ctrlbit = (1 << 6), |
406 | }, { | 383 | }, { |
407 | .name = "secss", | 384 | .name = "secss", |
408 | .id = -1, | ||
409 | .parent = &clk_div_d0_bus.clk, | 385 | .parent = &clk_div_d0_bus.clk, |
410 | .enable = s5pc100_d0_0_ctrl, | 386 | .enable = s5pc100_d0_0_ctrl, |
411 | .ctrlbit = (1 << 5), | 387 | .ctrlbit = (1 << 5), |
412 | }, { | 388 | }, { |
413 | .name = "g2d", | 389 | .name = "g2d", |
414 | .id = -1, | ||
415 | .parent = &clk_div_d0_bus.clk, | 390 | .parent = &clk_div_d0_bus.clk, |
416 | .enable = s5pc100_d0_0_ctrl, | 391 | .enable = s5pc100_d0_0_ctrl, |
417 | .ctrlbit = (1 << 4), | 392 | .ctrlbit = (1 << 4), |
418 | }, { | 393 | }, { |
419 | .name = "mdma", | 394 | .name = "mdma", |
420 | .id = -1, | ||
421 | .parent = &clk_div_d0_bus.clk, | 395 | .parent = &clk_div_d0_bus.clk, |
422 | .enable = s5pc100_d0_0_ctrl, | 396 | .enable = s5pc100_d0_0_ctrl, |
423 | .ctrlbit = (1 << 3), | 397 | .ctrlbit = (1 << 3), |
424 | }, { | 398 | }, { |
425 | .name = "cfcon", | 399 | .name = "cfcon", |
426 | .id = -1, | ||
427 | .parent = &clk_div_d0_bus.clk, | 400 | .parent = &clk_div_d0_bus.clk, |
428 | .enable = s5pc100_d0_0_ctrl, | 401 | .enable = s5pc100_d0_0_ctrl, |
429 | .ctrlbit = (1 << 2), | 402 | .ctrlbit = (1 << 2), |
430 | }, { | 403 | }, { |
431 | .name = "nfcon", | 404 | .name = "nfcon", |
432 | .id = -1, | ||
433 | .parent = &clk_div_d0_bus.clk, | 405 | .parent = &clk_div_d0_bus.clk, |
434 | .enable = s5pc100_d0_1_ctrl, | 406 | .enable = s5pc100_d0_1_ctrl, |
435 | .ctrlbit = (1 << 3), | 407 | .ctrlbit = (1 << 3), |
436 | }, { | 408 | }, { |
437 | .name = "onenandc", | 409 | .name = "onenandc", |
438 | .id = -1, | ||
439 | .parent = &clk_div_d0_bus.clk, | 410 | .parent = &clk_div_d0_bus.clk, |
440 | .enable = s5pc100_d0_1_ctrl, | 411 | .enable = s5pc100_d0_1_ctrl, |
441 | .ctrlbit = (1 << 2), | 412 | .ctrlbit = (1 << 2), |
442 | }, { | 413 | }, { |
443 | .name = "sdm", | 414 | .name = "sdm", |
444 | .id = -1, | ||
445 | .parent = &clk_div_d0_bus.clk, | 415 | .parent = &clk_div_d0_bus.clk, |
446 | .enable = s5pc100_d0_2_ctrl, | 416 | .enable = s5pc100_d0_2_ctrl, |
447 | .ctrlbit = (1 << 2), | 417 | .ctrlbit = (1 << 2), |
448 | }, { | 418 | }, { |
449 | .name = "seckey", | 419 | .name = "seckey", |
450 | .id = -1, | ||
451 | .parent = &clk_div_d0_bus.clk, | 420 | .parent = &clk_div_d0_bus.clk, |
452 | .enable = s5pc100_d0_2_ctrl, | 421 | .enable = s5pc100_d0_2_ctrl, |
453 | .ctrlbit = (1 << 1), | 422 | .ctrlbit = (1 << 1), |
454 | }, { | 423 | }, { |
455 | .name = "hsmmc", | 424 | .name = "hsmmc", |
456 | .id = 2, | 425 | .devname = "s3c-sdhci.2", |
457 | .parent = &clk_div_d1_bus.clk, | 426 | .parent = &clk_div_d1_bus.clk, |
458 | .enable = s5pc100_d1_0_ctrl, | 427 | .enable = s5pc100_d1_0_ctrl, |
459 | .ctrlbit = (1 << 7), | 428 | .ctrlbit = (1 << 7), |
460 | }, { | 429 | }, { |
461 | .name = "hsmmc", | 430 | .name = "hsmmc", |
462 | .id = 1, | 431 | .devname = "s3c-sdhci.1", |
463 | .parent = &clk_div_d1_bus.clk, | 432 | .parent = &clk_div_d1_bus.clk, |
464 | .enable = s5pc100_d1_0_ctrl, | 433 | .enable = s5pc100_d1_0_ctrl, |
465 | .ctrlbit = (1 << 6), | 434 | .ctrlbit = (1 << 6), |
466 | }, { | 435 | }, { |
467 | .name = "hsmmc", | 436 | .name = "hsmmc", |
468 | .id = 0, | 437 | .devname = "s3c-sdhci.0", |
469 | .parent = &clk_div_d1_bus.clk, | 438 | .parent = &clk_div_d1_bus.clk, |
470 | .enable = s5pc100_d1_0_ctrl, | 439 | .enable = s5pc100_d1_0_ctrl, |
471 | .ctrlbit = (1 << 5), | 440 | .ctrlbit = (1 << 5), |
472 | }, { | 441 | }, { |
473 | .name = "modemif", | 442 | .name = "modemif", |
474 | .id = -1, | ||
475 | .parent = &clk_div_d1_bus.clk, | 443 | .parent = &clk_div_d1_bus.clk, |
476 | .enable = s5pc100_d1_0_ctrl, | 444 | .enable = s5pc100_d1_0_ctrl, |
477 | .ctrlbit = (1 << 4), | 445 | .ctrlbit = (1 << 4), |
478 | }, { | 446 | }, { |
479 | .name = "otg", | 447 | .name = "otg", |
480 | .id = -1, | ||
481 | .parent = &clk_div_d1_bus.clk, | 448 | .parent = &clk_div_d1_bus.clk, |
482 | .enable = s5pc100_d1_0_ctrl, | 449 | .enable = s5pc100_d1_0_ctrl, |
483 | .ctrlbit = (1 << 3), | 450 | .ctrlbit = (1 << 3), |
484 | }, { | 451 | }, { |
485 | .name = "usbhost", | 452 | .name = "usbhost", |
486 | .id = -1, | ||
487 | .parent = &clk_div_d1_bus.clk, | 453 | .parent = &clk_div_d1_bus.clk, |
488 | .enable = s5pc100_d1_0_ctrl, | 454 | .enable = s5pc100_d1_0_ctrl, |
489 | .ctrlbit = (1 << 2), | 455 | .ctrlbit = (1 << 2), |
490 | }, { | 456 | }, { |
491 | .name = "pdma", | 457 | .name = "pdma", |
492 | .id = 1, | 458 | .devname = "s3c-pl330.1", |
493 | .parent = &clk_div_d1_bus.clk, | 459 | .parent = &clk_div_d1_bus.clk, |
494 | .enable = s5pc100_d1_0_ctrl, | 460 | .enable = s5pc100_d1_0_ctrl, |
495 | .ctrlbit = (1 << 1), | 461 | .ctrlbit = (1 << 1), |
496 | }, { | 462 | }, { |
497 | .name = "pdma", | 463 | .name = "pdma", |
498 | .id = 0, | 464 | .devname = "s3c-pl330.0", |
499 | .parent = &clk_div_d1_bus.clk, | 465 | .parent = &clk_div_d1_bus.clk, |
500 | .enable = s5pc100_d1_0_ctrl, | 466 | .enable = s5pc100_d1_0_ctrl, |
501 | .ctrlbit = (1 << 0), | 467 | .ctrlbit = (1 << 0), |
502 | }, { | 468 | }, { |
503 | .name = "lcd", | 469 | .name = "lcd", |
504 | .id = -1, | ||
505 | .parent = &clk_div_d1_bus.clk, | 470 | .parent = &clk_div_d1_bus.clk, |
506 | .enable = s5pc100_d1_1_ctrl, | 471 | .enable = s5pc100_d1_1_ctrl, |
507 | .ctrlbit = (1 << 0), | 472 | .ctrlbit = (1 << 0), |
508 | }, { | 473 | }, { |
509 | .name = "rotator", | 474 | .name = "rotator", |
510 | .id = -1, | ||
511 | .parent = &clk_div_d1_bus.clk, | 475 | .parent = &clk_div_d1_bus.clk, |
512 | .enable = s5pc100_d1_1_ctrl, | 476 | .enable = s5pc100_d1_1_ctrl, |
513 | .ctrlbit = (1 << 1), | 477 | .ctrlbit = (1 << 1), |
514 | }, { | 478 | }, { |
515 | .name = "fimc", | 479 | .name = "fimc", |
516 | .id = 0, | 480 | .devname = "s5p-fimc.0", |
517 | .parent = &clk_div_d1_bus.clk, | 481 | .parent = &clk_div_d1_bus.clk, |
518 | .enable = s5pc100_d1_1_ctrl, | 482 | .enable = s5pc100_d1_1_ctrl, |
519 | .ctrlbit = (1 << 2), | 483 | .ctrlbit = (1 << 2), |
520 | }, { | 484 | }, { |
521 | .name = "fimc", | 485 | .name = "fimc", |
522 | .id = 1, | 486 | .devname = "s5p-fimc.1", |
523 | .parent = &clk_div_d1_bus.clk, | 487 | .parent = &clk_div_d1_bus.clk, |
524 | .enable = s5pc100_d1_1_ctrl, | 488 | .enable = s5pc100_d1_1_ctrl, |
525 | .ctrlbit = (1 << 3), | 489 | .ctrlbit = (1 << 3), |
526 | }, { | 490 | }, { |
527 | .name = "fimc", | 491 | .name = "fimc", |
528 | .id = 2, | 492 | .devname = "s5p-fimc.2", |
529 | .parent = &clk_div_d1_bus.clk, | ||
530 | .enable = s5pc100_d1_1_ctrl, | 493 | .enable = s5pc100_d1_1_ctrl, |
531 | .ctrlbit = (1 << 4), | 494 | .ctrlbit = (1 << 4), |
532 | }, { | 495 | }, { |
533 | .name = "jpeg", | 496 | .name = "jpeg", |
534 | .id = -1, | ||
535 | .parent = &clk_div_d1_bus.clk, | 497 | .parent = &clk_div_d1_bus.clk, |
536 | .enable = s5pc100_d1_1_ctrl, | 498 | .enable = s5pc100_d1_1_ctrl, |
537 | .ctrlbit = (1 << 5), | 499 | .ctrlbit = (1 << 5), |
538 | }, { | 500 | }, { |
539 | .name = "mipi-dsim", | 501 | .name = "mipi-dsim", |
540 | .id = -1, | ||
541 | .parent = &clk_div_d1_bus.clk, | 502 | .parent = &clk_div_d1_bus.clk, |
542 | .enable = s5pc100_d1_1_ctrl, | 503 | .enable = s5pc100_d1_1_ctrl, |
543 | .ctrlbit = (1 << 6), | 504 | .ctrlbit = (1 << 6), |
544 | }, { | 505 | }, { |
545 | .name = "mipi-csis", | 506 | .name = "mipi-csis", |
546 | .id = -1, | ||
547 | .parent = &clk_div_d1_bus.clk, | 507 | .parent = &clk_div_d1_bus.clk, |
548 | .enable = s5pc100_d1_1_ctrl, | 508 | .enable = s5pc100_d1_1_ctrl, |
549 | .ctrlbit = (1 << 7), | 509 | .ctrlbit = (1 << 7), |
550 | }, { | 510 | }, { |
551 | .name = "g3d", | 511 | .name = "g3d", |
552 | .id = 0, | ||
553 | .parent = &clk_div_d1_bus.clk, | 512 | .parent = &clk_div_d1_bus.clk, |
554 | .enable = s5pc100_d1_0_ctrl, | 513 | .enable = s5pc100_d1_0_ctrl, |
555 | .ctrlbit = (1 << 8), | 514 | .ctrlbit = (1 << 8), |
556 | }, { | 515 | }, { |
557 | .name = "tv", | 516 | .name = "tv", |
558 | .id = -1, | ||
559 | .parent = &clk_div_d1_bus.clk, | 517 | .parent = &clk_div_d1_bus.clk, |
560 | .enable = s5pc100_d1_2_ctrl, | 518 | .enable = s5pc100_d1_2_ctrl, |
561 | .ctrlbit = (1 << 0), | 519 | .ctrlbit = (1 << 0), |
562 | }, { | 520 | }, { |
563 | .name = "vp", | 521 | .name = "vp", |
564 | .id = -1, | ||
565 | .parent = &clk_div_d1_bus.clk, | 522 | .parent = &clk_div_d1_bus.clk, |
566 | .enable = s5pc100_d1_2_ctrl, | 523 | .enable = s5pc100_d1_2_ctrl, |
567 | .ctrlbit = (1 << 1), | 524 | .ctrlbit = (1 << 1), |
568 | }, { | 525 | }, { |
569 | .name = "mixer", | 526 | .name = "mixer", |
570 | .id = -1, | ||
571 | .parent = &clk_div_d1_bus.clk, | 527 | .parent = &clk_div_d1_bus.clk, |
572 | .enable = s5pc100_d1_2_ctrl, | 528 | .enable = s5pc100_d1_2_ctrl, |
573 | .ctrlbit = (1 << 2), | 529 | .ctrlbit = (1 << 2), |
574 | }, { | 530 | }, { |
575 | .name = "hdmi", | 531 | .name = "hdmi", |
576 | .id = -1, | ||
577 | .parent = &clk_div_d1_bus.clk, | 532 | .parent = &clk_div_d1_bus.clk, |
578 | .enable = s5pc100_d1_2_ctrl, | 533 | .enable = s5pc100_d1_2_ctrl, |
579 | .ctrlbit = (1 << 3), | 534 | .ctrlbit = (1 << 3), |
580 | }, { | 535 | }, { |
581 | .name = "mfc", | 536 | .name = "mfc", |
582 | .id = -1, | ||
583 | .parent = &clk_div_d1_bus.clk, | 537 | .parent = &clk_div_d1_bus.clk, |
584 | .enable = s5pc100_d1_2_ctrl, | 538 | .enable = s5pc100_d1_2_ctrl, |
585 | .ctrlbit = (1 << 4), | 539 | .ctrlbit = (1 << 4), |
586 | }, { | 540 | }, { |
587 | .name = "apc", | 541 | .name = "apc", |
588 | .id = -1, | ||
589 | .parent = &clk_div_d1_bus.clk, | 542 | .parent = &clk_div_d1_bus.clk, |
590 | .enable = s5pc100_d1_3_ctrl, | 543 | .enable = s5pc100_d1_3_ctrl, |
591 | .ctrlbit = (1 << 2), | 544 | .ctrlbit = (1 << 2), |
592 | }, { | 545 | }, { |
593 | .name = "iec", | 546 | .name = "iec", |
594 | .id = -1, | ||
595 | .parent = &clk_div_d1_bus.clk, | 547 | .parent = &clk_div_d1_bus.clk, |
596 | .enable = s5pc100_d1_3_ctrl, | 548 | .enable = s5pc100_d1_3_ctrl, |
597 | .ctrlbit = (1 << 3), | 549 | .ctrlbit = (1 << 3), |
598 | }, { | 550 | }, { |
599 | .name = "systimer", | 551 | .name = "systimer", |
600 | .id = -1, | ||
601 | .parent = &clk_div_d1_bus.clk, | 552 | .parent = &clk_div_d1_bus.clk, |
602 | .enable = s5pc100_d1_3_ctrl, | 553 | .enable = s5pc100_d1_3_ctrl, |
603 | .ctrlbit = (1 << 7), | 554 | .ctrlbit = (1 << 7), |
604 | }, { | 555 | }, { |
605 | .name = "watchdog", | 556 | .name = "watchdog", |
606 | .id = -1, | ||
607 | .parent = &clk_div_d1_bus.clk, | 557 | .parent = &clk_div_d1_bus.clk, |
608 | .enable = s5pc100_d1_3_ctrl, | 558 | .enable = s5pc100_d1_3_ctrl, |
609 | .ctrlbit = (1 << 8), | 559 | .ctrlbit = (1 << 8), |
610 | }, { | 560 | }, { |
611 | .name = "rtc", | 561 | .name = "rtc", |
612 | .id = -1, | ||
613 | .parent = &clk_div_d1_bus.clk, | 562 | .parent = &clk_div_d1_bus.clk, |
614 | .enable = s5pc100_d1_3_ctrl, | 563 | .enable = s5pc100_d1_3_ctrl, |
615 | .ctrlbit = (1 << 9), | 564 | .ctrlbit = (1 << 9), |
616 | }, { | 565 | }, { |
617 | .name = "i2c", | 566 | .name = "i2c", |
618 | .id = 0, | 567 | .devname = "s3c2440-i2c.0", |
619 | .parent = &clk_div_d1_bus.clk, | 568 | .parent = &clk_div_d1_bus.clk, |
620 | .enable = s5pc100_d1_4_ctrl, | 569 | .enable = s5pc100_d1_4_ctrl, |
621 | .ctrlbit = (1 << 4), | 570 | .ctrlbit = (1 << 4), |
622 | }, { | 571 | }, { |
623 | .name = "i2c", | 572 | .name = "i2c", |
624 | .id = 1, | 573 | .devname = "s3c2440-i2c.1", |
625 | .parent = &clk_div_d1_bus.clk, | 574 | .parent = &clk_div_d1_bus.clk, |
626 | .enable = s5pc100_d1_4_ctrl, | 575 | .enable = s5pc100_d1_4_ctrl, |
627 | .ctrlbit = (1 << 5), | 576 | .ctrlbit = (1 << 5), |
628 | }, { | 577 | }, { |
629 | .name = "spi", | 578 | .name = "spi", |
630 | .id = 0, | 579 | .devname = "s3c64xx-spi.0", |
631 | .parent = &clk_div_d1_bus.clk, | 580 | .parent = &clk_div_d1_bus.clk, |
632 | .enable = s5pc100_d1_4_ctrl, | 581 | .enable = s5pc100_d1_4_ctrl, |
633 | .ctrlbit = (1 << 6), | 582 | .ctrlbit = (1 << 6), |
634 | }, { | 583 | }, { |
635 | .name = "spi", | 584 | .name = "spi", |
636 | .id = 1, | 585 | .devname = "s3c64xx-spi.1", |
637 | .parent = &clk_div_d1_bus.clk, | 586 | .parent = &clk_div_d1_bus.clk, |
638 | .enable = s5pc100_d1_4_ctrl, | 587 | .enable = s5pc100_d1_4_ctrl, |
639 | .ctrlbit = (1 << 7), | 588 | .ctrlbit = (1 << 7), |
640 | }, { | 589 | }, { |
641 | .name = "spi", | 590 | .name = "spi", |
642 | .id = 2, | 591 | .devname = "s3c64xx-spi.2", |
643 | .parent = &clk_div_d1_bus.clk, | 592 | .parent = &clk_div_d1_bus.clk, |
644 | .enable = s5pc100_d1_4_ctrl, | 593 | .enable = s5pc100_d1_4_ctrl, |
645 | .ctrlbit = (1 << 8), | 594 | .ctrlbit = (1 << 8), |
646 | }, { | 595 | }, { |
647 | .name = "irda", | 596 | .name = "irda", |
648 | .id = -1, | ||
649 | .parent = &clk_div_d1_bus.clk, | 597 | .parent = &clk_div_d1_bus.clk, |
650 | .enable = s5pc100_d1_4_ctrl, | 598 | .enable = s5pc100_d1_4_ctrl, |
651 | .ctrlbit = (1 << 9), | 599 | .ctrlbit = (1 << 9), |
652 | }, { | 600 | }, { |
653 | .name = "ccan", | 601 | .name = "ccan", |
654 | .id = 0, | ||
655 | .parent = &clk_div_d1_bus.clk, | 602 | .parent = &clk_div_d1_bus.clk, |
656 | .enable = s5pc100_d1_4_ctrl, | 603 | .enable = s5pc100_d1_4_ctrl, |
657 | .ctrlbit = (1 << 10), | 604 | .ctrlbit = (1 << 10), |
658 | }, { | 605 | }, { |
659 | .name = "ccan", | 606 | .name = "ccan", |
660 | .id = 1, | ||
661 | .parent = &clk_div_d1_bus.clk, | 607 | .parent = &clk_div_d1_bus.clk, |
662 | .enable = s5pc100_d1_4_ctrl, | 608 | .enable = s5pc100_d1_4_ctrl, |
663 | .ctrlbit = (1 << 11), | 609 | .ctrlbit = (1 << 11), |
664 | }, { | 610 | }, { |
665 | .name = "hsitx", | 611 | .name = "hsitx", |
666 | .id = -1, | ||
667 | .parent = &clk_div_d1_bus.clk, | 612 | .parent = &clk_div_d1_bus.clk, |
668 | .enable = s5pc100_d1_4_ctrl, | 613 | .enable = s5pc100_d1_4_ctrl, |
669 | .ctrlbit = (1 << 12), | 614 | .ctrlbit = (1 << 12), |
670 | }, { | 615 | }, { |
671 | .name = "hsirx", | 616 | .name = "hsirx", |
672 | .id = -1, | ||
673 | .parent = &clk_div_d1_bus.clk, | 617 | .parent = &clk_div_d1_bus.clk, |
674 | .enable = s5pc100_d1_4_ctrl, | 618 | .enable = s5pc100_d1_4_ctrl, |
675 | .ctrlbit = (1 << 13), | 619 | .ctrlbit = (1 << 13), |
676 | }, { | 620 | }, { |
677 | .name = "iis", | 621 | .name = "iis", |
678 | .id = 0, | 622 | .devname = "samsung-i2s.0", |
679 | .parent = &clk_div_pclkd1.clk, | 623 | .parent = &clk_div_pclkd1.clk, |
680 | .enable = s5pc100_d1_5_ctrl, | 624 | .enable = s5pc100_d1_5_ctrl, |
681 | .ctrlbit = (1 << 0), | 625 | .ctrlbit = (1 << 0), |
682 | }, { | 626 | }, { |
683 | .name = "iis", | 627 | .name = "iis", |
684 | .id = 1, | 628 | .devname = "samsung-i2s.1", |
685 | .parent = &clk_div_pclkd1.clk, | 629 | .parent = &clk_div_pclkd1.clk, |
686 | .enable = s5pc100_d1_5_ctrl, | 630 | .enable = s5pc100_d1_5_ctrl, |
687 | .ctrlbit = (1 << 1), | 631 | .ctrlbit = (1 << 1), |
688 | }, { | 632 | }, { |
689 | .name = "iis", | 633 | .name = "iis", |
690 | .id = 2, | 634 | .devname = "samsung-i2s.2", |
691 | .parent = &clk_div_pclkd1.clk, | 635 | .parent = &clk_div_pclkd1.clk, |
692 | .enable = s5pc100_d1_5_ctrl, | 636 | .enable = s5pc100_d1_5_ctrl, |
693 | .ctrlbit = (1 << 2), | 637 | .ctrlbit = (1 << 2), |
694 | }, { | 638 | }, { |
695 | .name = "ac97", | 639 | .name = "ac97", |
696 | .id = -1, | ||
697 | .parent = &clk_div_pclkd1.clk, | 640 | .parent = &clk_div_pclkd1.clk, |
698 | .enable = s5pc100_d1_5_ctrl, | 641 | .enable = s5pc100_d1_5_ctrl, |
699 | .ctrlbit = (1 << 3), | 642 | .ctrlbit = (1 << 3), |
700 | }, { | 643 | }, { |
701 | .name = "pcm", | 644 | .name = "pcm", |
702 | .id = 0, | 645 | .devname = "samsung-pcm.0", |
703 | .parent = &clk_div_pclkd1.clk, | 646 | .parent = &clk_div_pclkd1.clk, |
704 | .enable = s5pc100_d1_5_ctrl, | 647 | .enable = s5pc100_d1_5_ctrl, |
705 | .ctrlbit = (1 << 4), | 648 | .ctrlbit = (1 << 4), |
706 | }, { | 649 | }, { |
707 | .name = "pcm", | 650 | .name = "pcm", |
708 | .id = 1, | 651 | .devname = "samsung-pcm.1", |
709 | .parent = &clk_div_pclkd1.clk, | 652 | .parent = &clk_div_pclkd1.clk, |
710 | .enable = s5pc100_d1_5_ctrl, | 653 | .enable = s5pc100_d1_5_ctrl, |
711 | .ctrlbit = (1 << 5), | 654 | .ctrlbit = (1 << 5), |
712 | }, { | 655 | }, { |
713 | .name = "spdif", | 656 | .name = "spdif", |
714 | .id = -1, | ||
715 | .parent = &clk_div_pclkd1.clk, | 657 | .parent = &clk_div_pclkd1.clk, |
716 | .enable = s5pc100_d1_5_ctrl, | 658 | .enable = s5pc100_d1_5_ctrl, |
717 | .ctrlbit = (1 << 6), | 659 | .ctrlbit = (1 << 6), |
718 | }, { | 660 | }, { |
719 | .name = "adc", | 661 | .name = "adc", |
720 | .id = -1, | ||
721 | .parent = &clk_div_pclkd1.clk, | 662 | .parent = &clk_div_pclkd1.clk, |
722 | .enable = s5pc100_d1_5_ctrl, | 663 | .enable = s5pc100_d1_5_ctrl, |
723 | .ctrlbit = (1 << 7), | 664 | .ctrlbit = (1 << 7), |
724 | }, { | 665 | }, { |
725 | .name = "keypad", | 666 | .name = "keypad", |
726 | .id = -1, | ||
727 | .parent = &clk_div_pclkd1.clk, | 667 | .parent = &clk_div_pclkd1.clk, |
728 | .enable = s5pc100_d1_5_ctrl, | 668 | .enable = s5pc100_d1_5_ctrl, |
729 | .ctrlbit = (1 << 8), | 669 | .ctrlbit = (1 << 8), |
730 | }, { | 670 | }, { |
731 | .name = "spi_48m", | 671 | .name = "spi_48m", |
732 | .id = 0, | 672 | .devname = "s3c64xx-spi.0", |
733 | .parent = &clk_mout_48m.clk, | 673 | .parent = &clk_mout_48m.clk, |
734 | .enable = s5pc100_sclk0_ctrl, | 674 | .enable = s5pc100_sclk0_ctrl, |
735 | .ctrlbit = (1 << 7), | 675 | .ctrlbit = (1 << 7), |
736 | }, { | 676 | }, { |
737 | .name = "spi_48m", | 677 | .name = "spi_48m", |
738 | .id = 1, | 678 | .devname = "s3c64xx-spi.1", |
739 | .parent = &clk_mout_48m.clk, | 679 | .parent = &clk_mout_48m.clk, |
740 | .enable = s5pc100_sclk0_ctrl, | 680 | .enable = s5pc100_sclk0_ctrl, |
741 | .ctrlbit = (1 << 8), | 681 | .ctrlbit = (1 << 8), |
742 | }, { | 682 | }, { |
743 | .name = "spi_48m", | 683 | .name = "spi_48m", |
744 | .id = 2, | 684 | .devname = "s3c64xx-spi.2", |
745 | .parent = &clk_mout_48m.clk, | 685 | .parent = &clk_mout_48m.clk, |
746 | .enable = s5pc100_sclk0_ctrl, | 686 | .enable = s5pc100_sclk0_ctrl, |
747 | .ctrlbit = (1 << 9), | 687 | .ctrlbit = (1 << 9), |
748 | }, { | 688 | }, { |
749 | .name = "mmc_48m", | 689 | .name = "mmc_48m", |
750 | .id = 0, | 690 | .devname = "s3c-sdhci.0", |
751 | .parent = &clk_mout_48m.clk, | 691 | .parent = &clk_mout_48m.clk, |
752 | .enable = s5pc100_sclk0_ctrl, | 692 | .enable = s5pc100_sclk0_ctrl, |
753 | .ctrlbit = (1 << 15), | 693 | .ctrlbit = (1 << 15), |
754 | }, { | 694 | }, { |
755 | .name = "mmc_48m", | 695 | .name = "mmc_48m", |
756 | .id = 1, | 696 | .devname = "s3c-sdhci.1", |
757 | .parent = &clk_mout_48m.clk, | 697 | .parent = &clk_mout_48m.clk, |
758 | .enable = s5pc100_sclk0_ctrl, | 698 | .enable = s5pc100_sclk0_ctrl, |
759 | .ctrlbit = (1 << 16), | 699 | .ctrlbit = (1 << 16), |
760 | }, { | 700 | }, { |
761 | .name = "mmc_48m", | 701 | .name = "mmc_48m", |
762 | .id = 2, | 702 | .devname = "s3c-sdhci.2", |
763 | .parent = &clk_mout_48m.clk, | 703 | .parent = &clk_mout_48m.clk, |
764 | .enable = s5pc100_sclk0_ctrl, | 704 | .enable = s5pc100_sclk0_ctrl, |
765 | .ctrlbit = (1 << 17), | 705 | .ctrlbit = (1 << 17), |
@@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = { | |||
768 | 708 | ||
769 | static struct clk clk_vclk54m = { | 709 | static struct clk clk_vclk54m = { |
770 | .name = "vclk_54m", | 710 | .name = "vclk_54m", |
771 | .id = -1, | ||
772 | .rate = 54000000, | 711 | .rate = 54000000, |
773 | }; | 712 | }; |
774 | 713 | ||
775 | static struct clk clk_i2scdclk0 = { | 714 | static struct clk clk_i2scdclk0 = { |
776 | .name = "i2s_cdclk0", | 715 | .name = "i2s_cdclk0", |
777 | .id = -1, | ||
778 | }; | 716 | }; |
779 | 717 | ||
780 | static struct clk clk_i2scdclk1 = { | 718 | static struct clk clk_i2scdclk1 = { |
781 | .name = "i2s_cdclk1", | 719 | .name = "i2s_cdclk1", |
782 | .id = -1, | ||
783 | }; | 720 | }; |
784 | 721 | ||
785 | static struct clk clk_i2scdclk2 = { | 722 | static struct clk clk_i2scdclk2 = { |
786 | .name = "i2s_cdclk2", | 723 | .name = "i2s_cdclk2", |
787 | .id = -1, | ||
788 | }; | 724 | }; |
789 | 725 | ||
790 | static struct clk clk_pcmcdclk0 = { | 726 | static struct clk clk_pcmcdclk0 = { |
791 | .name = "pcm_cdclk0", | 727 | .name = "pcm_cdclk0", |
792 | .id = -1, | ||
793 | }; | 728 | }; |
794 | 729 | ||
795 | static struct clk clk_pcmcdclk1 = { | 730 | static struct clk clk_pcmcdclk1 = { |
796 | .name = "pcm_cdclk1", | 731 | .name = "pcm_cdclk1", |
797 | .id = -1, | ||
798 | }; | 732 | }; |
799 | 733 | ||
800 | static struct clk *clk_src_group1_list[] = { | 734 | static struct clk *clk_src_group1_list[] = { |
@@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = { | |||
836 | static struct clksrc_clk clk_sclk_audio0 = { | 770 | static struct clksrc_clk clk_sclk_audio0 = { |
837 | .clk = { | 771 | .clk = { |
838 | .name = "sclk_audio", | 772 | .name = "sclk_audio", |
839 | .id = 0, | 773 | .devname = "samsung-pcm.0", |
840 | .ctrlbit = (1 << 8), | 774 | .ctrlbit = (1 << 8), |
841 | .enable = s5pc100_sclk1_ctrl, | 775 | .enable = s5pc100_sclk1_ctrl, |
842 | }, | 776 | }, |
@@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = { | |||
862 | static struct clksrc_clk clk_sclk_audio1 = { | 796 | static struct clksrc_clk clk_sclk_audio1 = { |
863 | .clk = { | 797 | .clk = { |
864 | .name = "sclk_audio", | 798 | .name = "sclk_audio", |
865 | .id = 1, | 799 | .devname = "samsung-pcm.1", |
866 | .ctrlbit = (1 << 9), | 800 | .ctrlbit = (1 << 9), |
867 | .enable = s5pc100_sclk1_ctrl, | 801 | .enable = s5pc100_sclk1_ctrl, |
868 | }, | 802 | }, |
@@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = { | |||
887 | static struct clksrc_clk clk_sclk_audio2 = { | 821 | static struct clksrc_clk clk_sclk_audio2 = { |
888 | .clk = { | 822 | .clk = { |
889 | .name = "sclk_audio", | 823 | .name = "sclk_audio", |
890 | .id = 2, | 824 | .devname = "samsung-pcm.2", |
891 | .ctrlbit = (1 << 10), | 825 | .ctrlbit = (1 << 10), |
892 | .enable = s5pc100_sclk1_ctrl, | 826 | .enable = s5pc100_sclk1_ctrl, |
893 | }, | 827 | }, |
@@ -976,48 +910,12 @@ struct clksrc_sources clk_src_sclk_spdif = { | |||
976 | .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), | 910 | .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), |
977 | }; | 911 | }; |
978 | 912 | ||
979 | static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate) | ||
980 | { | ||
981 | struct clk *pclk; | ||
982 | int ret; | ||
983 | |||
984 | pclk = clk_get_parent(clk); | ||
985 | if (IS_ERR(pclk)) | ||
986 | return -EINVAL; | ||
987 | |||
988 | ret = pclk->ops->set_rate(pclk, rate); | ||
989 | clk_put(pclk); | ||
990 | |||
991 | return ret; | ||
992 | } | ||
993 | |||
994 | static unsigned long s5pc100_spdif_get_rate(struct clk *clk) | ||
995 | { | ||
996 | struct clk *pclk; | ||
997 | int rate; | ||
998 | |||
999 | pclk = clk_get_parent(clk); | ||
1000 | if (IS_ERR(pclk)) | ||
1001 | return -EINVAL; | ||
1002 | |||
1003 | rate = pclk->ops->get_rate(clk); | ||
1004 | clk_put(pclk); | ||
1005 | |||
1006 | return rate; | ||
1007 | } | ||
1008 | |||
1009 | static struct clk_ops s5pc100_sclk_spdif_ops = { | ||
1010 | .set_rate = s5pc100_spdif_set_rate, | ||
1011 | .get_rate = s5pc100_spdif_get_rate, | ||
1012 | }; | ||
1013 | |||
1014 | static struct clksrc_clk clk_sclk_spdif = { | 913 | static struct clksrc_clk clk_sclk_spdif = { |
1015 | .clk = { | 914 | .clk = { |
1016 | .name = "sclk_spdif", | 915 | .name = "sclk_spdif", |
1017 | .id = -1, | ||
1018 | .ctrlbit = (1 << 11), | 916 | .ctrlbit = (1 << 11), |
1019 | .enable = s5pc100_sclk1_ctrl, | 917 | .enable = s5pc100_sclk1_ctrl, |
1020 | .ops = &s5pc100_sclk_spdif_ops, | 918 | .ops = &s5p_sclk_spdif_ops, |
1021 | }, | 919 | }, |
1022 | .sources = &clk_src_sclk_spdif, | 920 | .sources = &clk_src_sclk_spdif, |
1023 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 }, | 921 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 }, |
@@ -1027,7 +925,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1027 | { | 925 | { |
1028 | .clk = { | 926 | .clk = { |
1029 | .name = "sclk_spi", | 927 | .name = "sclk_spi", |
1030 | .id = 0, | 928 | .devname = "s3c64xx-spi.0", |
1031 | .ctrlbit = (1 << 4), | 929 | .ctrlbit = (1 << 4), |
1032 | .enable = s5pc100_sclk0_ctrl, | 930 | .enable = s5pc100_sclk0_ctrl, |
1033 | 931 | ||
@@ -1038,7 +936,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1038 | }, { | 936 | }, { |
1039 | .clk = { | 937 | .clk = { |
1040 | .name = "sclk_spi", | 938 | .name = "sclk_spi", |
1041 | .id = 1, | 939 | .devname = "s3c64xx-spi.1", |
1042 | .ctrlbit = (1 << 5), | 940 | .ctrlbit = (1 << 5), |
1043 | .enable = s5pc100_sclk0_ctrl, | 941 | .enable = s5pc100_sclk0_ctrl, |
1044 | 942 | ||
@@ -1049,7 +947,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1049 | }, { | 947 | }, { |
1050 | .clk = { | 948 | .clk = { |
1051 | .name = "sclk_spi", | 949 | .name = "sclk_spi", |
1052 | .id = 2, | 950 | .devname = "s3c64xx-spi.2", |
1053 | .ctrlbit = (1 << 6), | 951 | .ctrlbit = (1 << 6), |
1054 | .enable = s5pc100_sclk0_ctrl, | 952 | .enable = s5pc100_sclk0_ctrl, |
1055 | 953 | ||
@@ -1060,7 +958,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1060 | }, { | 958 | }, { |
1061 | .clk = { | 959 | .clk = { |
1062 | .name = "uclk1", | 960 | .name = "uclk1", |
1063 | .id = -1, | ||
1064 | .ctrlbit = (1 << 3), | 961 | .ctrlbit = (1 << 3), |
1065 | .enable = s5pc100_sclk0_ctrl, | 962 | .enable = s5pc100_sclk0_ctrl, |
1066 | 963 | ||
@@ -1071,7 +968,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1071 | }, { | 968 | }, { |
1072 | .clk = { | 969 | .clk = { |
1073 | .name = "sclk_mixer", | 970 | .name = "sclk_mixer", |
1074 | .id = -1, | ||
1075 | .ctrlbit = (1 << 6), | 971 | .ctrlbit = (1 << 6), |
1076 | .enable = s5pc100_sclk0_ctrl, | 972 | .enable = s5pc100_sclk0_ctrl, |
1077 | 973 | ||
@@ -1081,7 +977,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1081 | }, { | 977 | }, { |
1082 | .clk = { | 978 | .clk = { |
1083 | .name = "sclk_lcd", | 979 | .name = "sclk_lcd", |
1084 | .id = -1, | ||
1085 | .ctrlbit = (1 << 0), | 980 | .ctrlbit = (1 << 0), |
1086 | .enable = s5pc100_sclk1_ctrl, | 981 | .enable = s5pc100_sclk1_ctrl, |
1087 | 982 | ||
@@ -1092,7 +987,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1092 | }, { | 987 | }, { |
1093 | .clk = { | 988 | .clk = { |
1094 | .name = "sclk_fimc", | 989 | .name = "sclk_fimc", |
1095 | .id = 0, | 990 | .devname = "s5p-fimc.0", |
1096 | .ctrlbit = (1 << 1), | 991 | .ctrlbit = (1 << 1), |
1097 | .enable = s5pc100_sclk1_ctrl, | 992 | .enable = s5pc100_sclk1_ctrl, |
1098 | 993 | ||
@@ -1103,7 +998,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1103 | }, { | 998 | }, { |
1104 | .clk = { | 999 | .clk = { |
1105 | .name = "sclk_fimc", | 1000 | .name = "sclk_fimc", |
1106 | .id = 1, | 1001 | .devname = "s5p-fimc.1", |
1107 | .ctrlbit = (1 << 2), | 1002 | .ctrlbit = (1 << 2), |
1108 | .enable = s5pc100_sclk1_ctrl, | 1003 | .enable = s5pc100_sclk1_ctrl, |
1109 | 1004 | ||
@@ -1114,7 +1009,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1114 | }, { | 1009 | }, { |
1115 | .clk = { | 1010 | .clk = { |
1116 | .name = "sclk_fimc", | 1011 | .name = "sclk_fimc", |
1117 | .id = 2, | 1012 | .devname = "s5p-fimc.2", |
1118 | .ctrlbit = (1 << 3), | 1013 | .ctrlbit = (1 << 3), |
1119 | .enable = s5pc100_sclk1_ctrl, | 1014 | .enable = s5pc100_sclk1_ctrl, |
1120 | 1015 | ||
@@ -1125,7 +1020,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1125 | }, { | 1020 | }, { |
1126 | .clk = { | 1021 | .clk = { |
1127 | .name = "sclk_mmc", | 1022 | .name = "sclk_mmc", |
1128 | .id = 0, | 1023 | .devname = "s3c-sdhci.0", |
1129 | .ctrlbit = (1 << 12), | 1024 | .ctrlbit = (1 << 12), |
1130 | .enable = s5pc100_sclk1_ctrl, | 1025 | .enable = s5pc100_sclk1_ctrl, |
1131 | 1026 | ||
@@ -1136,7 +1031,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1136 | }, { | 1031 | }, { |
1137 | .clk = { | 1032 | .clk = { |
1138 | .name = "sclk_mmc", | 1033 | .name = "sclk_mmc", |
1139 | .id = 1, | 1034 | .devname = "s3c-sdhci.1", |
1140 | .ctrlbit = (1 << 13), | 1035 | .ctrlbit = (1 << 13), |
1141 | .enable = s5pc100_sclk1_ctrl, | 1036 | .enable = s5pc100_sclk1_ctrl, |
1142 | 1037 | ||
@@ -1147,7 +1042,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1147 | }, { | 1042 | }, { |
1148 | .clk = { | 1043 | .clk = { |
1149 | .name = "sclk_mmc", | 1044 | .name = "sclk_mmc", |
1150 | .id = 2, | 1045 | .devname = "s3c-sdhci.2", |
1151 | .ctrlbit = (1 << 14), | 1046 | .ctrlbit = (1 << 14), |
1152 | .enable = s5pc100_sclk1_ctrl, | 1047 | .enable = s5pc100_sclk1_ctrl, |
1153 | 1048 | ||
@@ -1158,7 +1053,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1158 | }, { | 1053 | }, { |
1159 | .clk = { | 1054 | .clk = { |
1160 | .name = "sclk_irda", | 1055 | .name = "sclk_irda", |
1161 | .id = 2, | ||
1162 | .ctrlbit = (1 << 10), | 1056 | .ctrlbit = (1 << 10), |
1163 | .enable = s5pc100_sclk0_ctrl, | 1057 | .enable = s5pc100_sclk0_ctrl, |
1164 | 1058 | ||
@@ -1169,7 +1063,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1169 | }, { | 1063 | }, { |
1170 | .clk = { | 1064 | .clk = { |
1171 | .name = "sclk_irda", | 1065 | .name = "sclk_irda", |
1172 | .id = -1, | ||
1173 | .ctrlbit = (1 << 10), | 1066 | .ctrlbit = (1 << 10), |
1174 | .enable = s5pc100_sclk0_ctrl, | 1067 | .enable = s5pc100_sclk0_ctrl, |
1175 | 1068 | ||
@@ -1180,7 +1073,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1180 | }, { | 1073 | }, { |
1181 | .clk = { | 1074 | .clk = { |
1182 | .name = "sclk_pwi", | 1075 | .name = "sclk_pwi", |
1183 | .id = -1, | ||
1184 | .ctrlbit = (1 << 1), | 1076 | .ctrlbit = (1 << 1), |
1185 | .enable = s5pc100_sclk0_ctrl, | 1077 | .enable = s5pc100_sclk0_ctrl, |
1186 | 1078 | ||
@@ -1191,7 +1083,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1191 | }, { | 1083 | }, { |
1192 | .clk = { | 1084 | .clk = { |
1193 | .name = "sclk_uhost", | 1085 | .name = "sclk_uhost", |
1194 | .id = -1, | ||
1195 | .ctrlbit = (1 << 11), | 1086 | .ctrlbit = (1 << 11), |
1196 | .enable = s5pc100_sclk0_ctrl, | 1087 | .enable = s5pc100_sclk0_ctrl, |
1197 | 1088 | ||
@@ -1291,79 +1182,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) | |||
1291 | static struct clk init_clocks[] = { | 1182 | static struct clk init_clocks[] = { |
1292 | { | 1183 | { |
1293 | .name = "tzic", | 1184 | .name = "tzic", |
1294 | .id = -1, | ||
1295 | .parent = &clk_div_d0_bus.clk, | 1185 | .parent = &clk_div_d0_bus.clk, |
1296 | .enable = s5pc100_d0_0_ctrl, | 1186 | .enable = s5pc100_d0_0_ctrl, |
1297 | .ctrlbit = (1 << 1), | 1187 | .ctrlbit = (1 << 1), |
1298 | }, { | 1188 | }, { |
1299 | .name = "intc", | 1189 | .name = "intc", |
1300 | .id = -1, | ||
1301 | .parent = &clk_div_d0_bus.clk, | 1190 | .parent = &clk_div_d0_bus.clk, |
1302 | .enable = s5pc100_d0_0_ctrl, | 1191 | .enable = s5pc100_d0_0_ctrl, |
1303 | .ctrlbit = (1 << 0), | 1192 | .ctrlbit = (1 << 0), |
1304 | }, { | 1193 | }, { |
1305 | .name = "ebi", | 1194 | .name = "ebi", |
1306 | .id = -1, | ||
1307 | .parent = &clk_div_d0_bus.clk, | 1195 | .parent = &clk_div_d0_bus.clk, |
1308 | .enable = s5pc100_d0_1_ctrl, | 1196 | .enable = s5pc100_d0_1_ctrl, |
1309 | .ctrlbit = (1 << 5), | 1197 | .ctrlbit = (1 << 5), |
1310 | }, { | 1198 | }, { |
1311 | .name = "intmem", | 1199 | .name = "intmem", |
1312 | .id = -1, | ||
1313 | .parent = &clk_div_d0_bus.clk, | 1200 | .parent = &clk_div_d0_bus.clk, |
1314 | .enable = s5pc100_d0_1_ctrl, | 1201 | .enable = s5pc100_d0_1_ctrl, |
1315 | .ctrlbit = (1 << 4), | 1202 | .ctrlbit = (1 << 4), |
1316 | }, { | 1203 | }, { |
1317 | .name = "sromc", | 1204 | .name = "sromc", |
1318 | .id = -1, | ||
1319 | .parent = &clk_div_d0_bus.clk, | 1205 | .parent = &clk_div_d0_bus.clk, |
1320 | .enable = s5pc100_d0_1_ctrl, | 1206 | .enable = s5pc100_d0_1_ctrl, |
1321 | .ctrlbit = (1 << 1), | 1207 | .ctrlbit = (1 << 1), |
1322 | }, { | 1208 | }, { |
1323 | .name = "dmc", | 1209 | .name = "dmc", |
1324 | .id = -1, | ||
1325 | .parent = &clk_div_d0_bus.clk, | 1210 | .parent = &clk_div_d0_bus.clk, |
1326 | .enable = s5pc100_d0_1_ctrl, | 1211 | .enable = s5pc100_d0_1_ctrl, |
1327 | .ctrlbit = (1 << 0), | 1212 | .ctrlbit = (1 << 0), |
1328 | }, { | 1213 | }, { |
1329 | .name = "chipid", | 1214 | .name = "chipid", |
1330 | .id = -1, | ||
1331 | .parent = &clk_div_d0_bus.clk, | 1215 | .parent = &clk_div_d0_bus.clk, |
1332 | .enable = s5pc100_d0_1_ctrl, | 1216 | .enable = s5pc100_d0_1_ctrl, |
1333 | .ctrlbit = (1 << 0), | 1217 | .ctrlbit = (1 << 0), |
1334 | }, { | 1218 | }, { |
1335 | .name = "gpio", | 1219 | .name = "gpio", |
1336 | .id = -1, | ||
1337 | .parent = &clk_div_d1_bus.clk, | 1220 | .parent = &clk_div_d1_bus.clk, |
1338 | .enable = s5pc100_d1_3_ctrl, | 1221 | .enable = s5pc100_d1_3_ctrl, |
1339 | .ctrlbit = (1 << 1), | 1222 | .ctrlbit = (1 << 1), |
1340 | }, { | 1223 | }, { |
1341 | .name = "uart", | 1224 | .name = "uart", |
1342 | .id = 0, | 1225 | .devname = "s3c6400-uart.0", |
1343 | .parent = &clk_div_d1_bus.clk, | 1226 | .parent = &clk_div_d1_bus.clk, |
1344 | .enable = s5pc100_d1_4_ctrl, | 1227 | .enable = s5pc100_d1_4_ctrl, |
1345 | .ctrlbit = (1 << 0), | 1228 | .ctrlbit = (1 << 0), |
1346 | }, { | 1229 | }, { |
1347 | .name = "uart", | 1230 | .name = "uart", |
1348 | .id = 1, | 1231 | .devname = "s3c6400-uart.1", |
1349 | .parent = &clk_div_d1_bus.clk, | 1232 | .parent = &clk_div_d1_bus.clk, |
1350 | .enable = s5pc100_d1_4_ctrl, | 1233 | .enable = s5pc100_d1_4_ctrl, |
1351 | .ctrlbit = (1 << 1), | 1234 | .ctrlbit = (1 << 1), |
1352 | }, { | 1235 | }, { |
1353 | .name = "uart", | 1236 | .name = "uart", |
1354 | .id = 2, | 1237 | .devname = "s3c6400-uart.2", |
1355 | .parent = &clk_div_d1_bus.clk, | 1238 | .parent = &clk_div_d1_bus.clk, |
1356 | .enable = s5pc100_d1_4_ctrl, | 1239 | .enable = s5pc100_d1_4_ctrl, |
1357 | .ctrlbit = (1 << 2), | 1240 | .ctrlbit = (1 << 2), |
1358 | }, { | 1241 | }, { |
1359 | .name = "uart", | 1242 | .name = "uart", |
1360 | .id = 3, | 1243 | .devname = "s3c6400-uart.3", |
1361 | .parent = &clk_div_d1_bus.clk, | 1244 | .parent = &clk_div_d1_bus.clk, |
1362 | .enable = s5pc100_d1_4_ctrl, | 1245 | .enable = s5pc100_d1_4_ctrl, |
1363 | .ctrlbit = (1 << 3), | 1246 | .ctrlbit = (1 << 3), |
1364 | }, { | 1247 | }, { |
1365 | .name = "timers", | 1248 | .name = "timers", |
1366 | .id = -1, | ||
1367 | .parent = &clk_div_d1_bus.clk, | 1249 | .parent = &clk_div_d1_bus.clk, |
1368 | .enable = s5pc100_d1_3_ctrl, | 1250 | .enable = s5pc100_d1_3_ctrl, |
1369 | .ctrlbit = (1 << 6), | 1251 | .ctrlbit = (1 << 6), |
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c index 57b19794d9bb..e5d6c4dceb56 100644 --- a/arch/arm/mach-s5pc100/dev-spi.c +++ b/arch/arm/mach-s5pc100/dev-spi.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <mach/dma.h> | 15 | #include <mach/dma.h> |
16 | #include <mach/map.h> | 16 | #include <mach/map.h> |
17 | #include <mach/spi-clocks.h> | 17 | #include <mach/spi-clocks.h> |
18 | #include <mach/irqs.h> | ||
18 | 19 | ||
19 | #include <plat/s3c64xx-spi.h> | 20 | #include <plat/s3c64xx-spi.h> |
20 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
@@ -90,6 +91,7 @@ static struct s3c64xx_spi_info s5pc100_spi0_pdata = { | |||
90 | .fifo_lvl_mask = 0x7f, | 91 | .fifo_lvl_mask = 0x7f, |
91 | .rx_lvl_offset = 13, | 92 | .rx_lvl_offset = 13, |
92 | .high_speed = 1, | 93 | .high_speed = 1, |
94 | .tx_st_done = 21, | ||
93 | }; | 95 | }; |
94 | 96 | ||
95 | static u64 spi_dmamask = DMA_BIT_MASK(32); | 97 | static u64 spi_dmamask = DMA_BIT_MASK(32); |
@@ -134,6 +136,7 @@ static struct s3c64xx_spi_info s5pc100_spi1_pdata = { | |||
134 | .fifo_lvl_mask = 0x7f, | 136 | .fifo_lvl_mask = 0x7f, |
135 | .rx_lvl_offset = 13, | 137 | .rx_lvl_offset = 13, |
136 | .high_speed = 1, | 138 | .high_speed = 1, |
139 | .tx_st_done = 21, | ||
137 | }; | 140 | }; |
138 | 141 | ||
139 | struct platform_device s5pc100_device_spi1 = { | 142 | struct platform_device s5pc100_device_spi1 = { |
@@ -176,6 +179,7 @@ static struct s3c64xx_spi_info s5pc100_spi2_pdata = { | |||
176 | .fifo_lvl_mask = 0x7f, | 179 | .fifo_lvl_mask = 0x7f, |
177 | .rx_lvl_offset = 13, | 180 | .rx_lvl_offset = 13, |
178 | .high_speed = 1, | 181 | .high_speed = 1, |
182 | .tx_st_done = 21, | ||
179 | }; | 183 | }; |
180 | 184 | ||
181 | struct platform_device s5pc100_device_spi2 = { | 185 | struct platform_device s5pc100_device_spi2 = { |
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h deleted file mode 100644 index 07aa4d6054fe..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h +++ /dev/null | |||
@@ -1,105 +0,0 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/regs-fb.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Pawel Osciak <p.osciak@samsung.com> | ||
5 | * | ||
6 | * Framebuffer register definitions for Samsung S5PC100. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_FB_H | ||
14 | #define __ASM_ARCH_REGS_FB_H __FILE__ | ||
15 | |||
16 | #include <plat/regs-fb-v4.h> | ||
17 | |||
18 | /* VP1 interface timing control */ | ||
19 | #define VP1CON0 (0x118) | ||
20 | #define VP1_RATECON_EN (1 << 31) | ||
21 | #define VP1_CLKRATE_MASK (0xff) | ||
22 | |||
23 | #define VP1CON1 (0x11c) | ||
24 | #define VP1_VTREGCON_EN (1 << 31) | ||
25 | #define VP1_VBPD_MASK (0xfff) | ||
26 | #define VP1_VBPD_SHIFT (16) | ||
27 | |||
28 | |||
29 | #define WPALCON_H (0x19c) | ||
30 | #define WPALCON_L (0x1a0) | ||
31 | |||
32 | /* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but | ||
33 | * different for WPAL2-4 | ||
34 | */ | ||
35 | /* In WPALCON_L (aka WPALCON) */ | ||
36 | #define WPALCON_W1PAL_32BPP_A888 (0x7 << 3) | ||
37 | #define WPALCON_W0PAL_32BPP_A888 (0x7 << 0) | ||
38 | |||
39 | /* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H, | ||
40 | * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]). | ||
41 | */ | ||
42 | #define WPALCON_L_WxPAL_L_MASK (0x1) | ||
43 | #define WPALCON_L_W2PAL_L_SHIFT (6) | ||
44 | #define WPALCON_L_W3PAL_L_SHIFT (7) | ||
45 | #define WPALCON_L_W4PAL_L_SHIFT (8) | ||
46 | |||
47 | #define WPALCON_L_WxPAL_H_MASK (0x3) | ||
48 | #define WPALCON_H_W2PAL_H_SHIFT (9) | ||
49 | #define WPALCON_H_W3PAL_H_SHIFT (13) | ||
50 | #define WPALCON_H_W4PAL_H_SHIFT (17) | ||
51 | |||
52 | /* Per-window alpha value registers */ | ||
53 | /* For window 0 8-bit alpha values are in VIDW0ALPHAx, | ||
54 | * for windows 1-4 alpha values consist of two parts, the 4 low bits are | ||
55 | * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC, | ||
56 | * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0]) | ||
57 | */ | ||
58 | #define VIDWxALPHA0(_win) (0x200 + (_win * 8)) | ||
59 | #define VIDWxALPHA1(_win) (0x204 + (_win * 8)) | ||
60 | |||
61 | /* Only for window 0 in VIDW0ALPHAx. */ | ||
62 | #define VIDW0ALPHAx_R(_x) ((_x) << 16) | ||
63 | #define VIDW0ALPHAx_R_MASK (0xff << 16) | ||
64 | #define VIDW0ALPHAx_R_SHIFT (16) | ||
65 | #define VIDW0ALPHAx_G(_x) ((_x) << 8) | ||
66 | #define VIDW0ALPHAx_G_MASK (0xff << 8) | ||
67 | #define VIDW0ALPHAx_G_SHIFT (8) | ||
68 | #define VIDW0ALPHAx_B(_x) ((_x) << 0) | ||
69 | #define VIDW0ALPHAx_B_MASK (0xff << 0) | ||
70 | #define VIDW0ALPHAx_B_SHIFT (0) | ||
71 | |||
72 | /* Low 4 bits of alpha0-1 for windows 1-4 */ | ||
73 | #define VIDW14ALPHAx_R_L(_x) ((_x) << 16) | ||
74 | #define VIDW14ALPHAx_R_L_MASK (0xf << 16) | ||
75 | #define VIDW14ALPHAx_R_L_SHIFT (16) | ||
76 | #define VIDW14ALPHAx_G_L(_x) ((_x) << 8) | ||
77 | #define VIDW14ALPHAx_G_L_MASK (0xf << 8) | ||
78 | #define VIDW14ALPHAx_G_L_SHIFT (8) | ||
79 | #define VIDW14ALPHAx_B_L(_x) ((_x) << 0) | ||
80 | #define VIDW14ALPHAx_B_L_MASK (0xf << 0) | ||
81 | #define VIDW14ALPHAx_B_L_SHIFT (0) | ||
82 | |||
83 | |||
84 | /* Per-window blending equation control registers */ | ||
85 | #define BLENDEQx(_win) (0x244 + ((_win) * 4)) | ||
86 | #define BLENDEQ1 (0x244) | ||
87 | #define BLENDEQ2 (0x248) | ||
88 | #define BLENDEQ3 (0x24c) | ||
89 | #define BLENDEQ4 (0x250) | ||
90 | |||
91 | #define BLENDEQx_Q_FUNC(_x) ((_x) << 18) | ||
92 | #define BLENDEQx_Q_FUNC_MASK (0xf << 18) | ||
93 | #define BLENDEQx_P_FUNC(_x) ((_x) << 12) | ||
94 | #define BLENDEQx_P_FUNC_MASK (0xf << 12) | ||
95 | #define BLENDEQx_B_FUNC(_x) ((_x) << 6) | ||
96 | #define BLENDEQx_B_FUNC_MASK (0xf << 6) | ||
97 | #define BLENDEQx_A_FUNC(_x) ((_x) << 0) | ||
98 | #define BLENDEQx_A_FUNC_MASK (0xf << 0) | ||
99 | |||
100 | #define BLENDCON (0x260) | ||
101 | #define BLENDCON_8BIT_ALPHA (1 << 0) | ||
102 | |||
103 | |||
104 | #endif /* __ASM_ARCH_REGS_FB_H */ | ||
105 | |||
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 0525cb3ef406..227d8908aab6 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
@@ -29,7 +29,6 @@ | |||
29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
30 | 30 | ||
31 | #include <mach/map.h> | 31 | #include <mach/map.h> |
32 | #include <mach/regs-fb.h> | ||
33 | #include <mach/regs-gpio.h> | 32 | #include <mach/regs-gpio.h> |
34 | 33 | ||
35 | #include <video/platform_lcd.h> | 34 | #include <video/platform_lcd.h> |
@@ -51,6 +50,8 @@ | |||
51 | #include <plat/keypad.h> | 50 | #include <plat/keypad.h> |
52 | #include <plat/ts.h> | 51 | #include <plat/ts.h> |
53 | #include <plat/audio.h> | 52 | #include <plat/audio.h> |
53 | #include <plat/backlight.h> | ||
54 | #include <plat/regs-fb-v4.h> | ||
54 | 55 | ||
55 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 56 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
56 | #define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 57 | #define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
@@ -179,45 +180,6 @@ static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = { | |||
179 | .cols = 8, | 180 | .cols = 8, |
180 | }; | 181 | }; |
181 | 182 | ||
182 | static int smdkc100_backlight_init(struct device *dev) | ||
183 | { | ||
184 | int ret; | ||
185 | |||
186 | ret = gpio_request(S5PC100_GPD(0), "Backlight"); | ||
187 | if (ret) { | ||
188 | printk(KERN_ERR "failed to request GPF for PWM-OUT0\n"); | ||
189 | return ret; | ||
190 | } | ||
191 | |||
192 | /* Configure GPIO pin with S5PC100_GPD_TOUT_0 */ | ||
193 | s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_SFN(2)); | ||
194 | |||
195 | return 0; | ||
196 | } | ||
197 | |||
198 | static void smdkc100_backlight_exit(struct device *dev) | ||
199 | { | ||
200 | s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_OUTPUT); | ||
201 | gpio_free(S5PC100_GPD(0)); | ||
202 | } | ||
203 | |||
204 | static struct platform_pwm_backlight_data smdkc100_backlight_data = { | ||
205 | .pwm_id = 0, | ||
206 | .max_brightness = 255, | ||
207 | .dft_brightness = 255, | ||
208 | .pwm_period_ns = 78770, | ||
209 | .init = smdkc100_backlight_init, | ||
210 | .exit = smdkc100_backlight_exit, | ||
211 | }; | ||
212 | |||
213 | static struct platform_device smdkc100_backlight_device = { | ||
214 | .name = "pwm-backlight", | ||
215 | .dev = { | ||
216 | .parent = &s3c_device_timer[0].dev, | ||
217 | .platform_data = &smdkc100_backlight_data, | ||
218 | }, | ||
219 | }; | ||
220 | |||
221 | static struct platform_device *smdkc100_devices[] __initdata = { | 183 | static struct platform_device *smdkc100_devices[] __initdata = { |
222 | &s3c_device_adc, | 184 | &s3c_device_adc, |
223 | &s3c_device_cfcon, | 185 | &s3c_device_cfcon, |
@@ -239,8 +201,6 @@ static struct platform_device *smdkc100_devices[] __initdata = { | |||
239 | &s5p_device_fimc1, | 201 | &s5p_device_fimc1, |
240 | &s5p_device_fimc2, | 202 | &s5p_device_fimc2, |
241 | &s5pc100_device_spdif, | 203 | &s5pc100_device_spdif, |
242 | &s3c_device_timer[0], | ||
243 | &smdkc100_backlight_device, | ||
244 | }; | 204 | }; |
245 | 205 | ||
246 | static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | 206 | static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { |
@@ -249,6 +209,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | |||
249 | .oversampling_shift = 2, | 209 | .oversampling_shift = 2, |
250 | }; | 210 | }; |
251 | 211 | ||
212 | /* LCD Backlight data */ | ||
213 | static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = { | ||
214 | .no = S5PC100_GPD(0), | ||
215 | .func = S3C_GPIO_SFN(2), | ||
216 | }; | ||
217 | |||
218 | static struct platform_pwm_backlight_data smdkc100_bl_data = { | ||
219 | .pwm_id = 0, | ||
220 | }; | ||
221 | |||
252 | static void __init smdkc100_map_io(void) | 222 | static void __init smdkc100_map_io(void) |
253 | { | 223 | { |
254 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | 224 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); |
@@ -276,6 +246,9 @@ static void __init smdkc100_machine_init(void) | |||
276 | /* LCD init */ | 246 | /* LCD init */ |
277 | gpio_request(S5PC100_GPH0(6), "GPH0"); | 247 | gpio_request(S5PC100_GPH0(6), "GPH0"); |
278 | smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); | 248 | smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); |
249 | |||
250 | samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data); | ||
251 | |||
279 | platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); | 252 | platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); |
280 | } | 253 | } |
281 | 254 | ||
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c index d31c0f3fe222..8978e4cf9ed5 100644 --- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/fb.h> | 15 | #include <linux/fb.h> |
16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
17 | 17 | ||
18 | #include <mach/regs-fb.h> | ||
19 | #include <mach/map.h> | 18 | #include <mach/map.h> |
20 | #include <plat/fb.h> | 19 | #include <plat/fb.h> |
21 | #include <plat/gpio-cfg.h> | 20 | #include <plat/gpio-cfg.h> |
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 37b5a97594a5..79bb3a0314ef 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig | |||
@@ -134,6 +134,7 @@ config MACH_SMDKV210 | |||
134 | select S3C_DEV_RTC | 134 | select S3C_DEV_RTC |
135 | select S3C_DEV_WDT | 135 | select S3C_DEV_WDT |
136 | select SAMSUNG_DEV_ADC | 136 | select SAMSUNG_DEV_ADC |
137 | select SAMSUNG_DEV_BACKLIGHT | ||
137 | select SAMSUNG_DEV_IDE | 138 | select SAMSUNG_DEV_IDE |
138 | select SAMSUNG_DEV_KEYPAD | 139 | select SAMSUNG_DEV_KEYPAD |
139 | select SAMSUNG_DEV_PWM | 140 | select SAMSUNG_DEV_PWM |
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 2d599499cefe..ae72f87eab15 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -36,7 +36,6 @@ static unsigned long xtal; | |||
36 | static struct clksrc_clk clk_mout_apll = { | 36 | static struct clksrc_clk clk_mout_apll = { |
37 | .clk = { | 37 | .clk = { |
38 | .name = "mout_apll", | 38 | .name = "mout_apll", |
39 | .id = -1, | ||
40 | }, | 39 | }, |
41 | .sources = &clk_src_apll, | 40 | .sources = &clk_src_apll, |
42 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | 41 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, |
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = { | |||
45 | static struct clksrc_clk clk_mout_epll = { | 44 | static struct clksrc_clk clk_mout_epll = { |
46 | .clk = { | 45 | .clk = { |
47 | .name = "mout_epll", | 46 | .name = "mout_epll", |
48 | .id = -1, | ||
49 | }, | 47 | }, |
50 | .sources = &clk_src_epll, | 48 | .sources = &clk_src_epll, |
51 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | 49 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, |
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = { | |||
54 | static struct clksrc_clk clk_mout_mpll = { | 52 | static struct clksrc_clk clk_mout_mpll = { |
55 | .clk = { | 53 | .clk = { |
56 | .name = "mout_mpll", | 54 | .name = "mout_mpll", |
57 | .id = -1, | ||
58 | }, | 55 | }, |
59 | .sources = &clk_src_mpll, | 56 | .sources = &clk_src_mpll, |
60 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | 57 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, |
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = { | |||
73 | static struct clksrc_clk clk_armclk = { | 70 | static struct clksrc_clk clk_armclk = { |
74 | .clk = { | 71 | .clk = { |
75 | .name = "armclk", | 72 | .name = "armclk", |
76 | .id = -1, | ||
77 | }, | 73 | }, |
78 | .sources = &clkset_armclk, | 74 | .sources = &clkset_armclk, |
79 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | 75 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, |
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = { | |||
83 | static struct clksrc_clk clk_hclk_msys = { | 79 | static struct clksrc_clk clk_hclk_msys = { |
84 | .clk = { | 80 | .clk = { |
85 | .name = "hclk_msys", | 81 | .name = "hclk_msys", |
86 | .id = -1, | ||
87 | .parent = &clk_armclk.clk, | 82 | .parent = &clk_armclk.clk, |
88 | }, | 83 | }, |
89 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | 84 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, |
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = { | |||
92 | static struct clksrc_clk clk_pclk_msys = { | 87 | static struct clksrc_clk clk_pclk_msys = { |
93 | .clk = { | 88 | .clk = { |
94 | .name = "pclk_msys", | 89 | .name = "pclk_msys", |
95 | .id = -1, | ||
96 | .parent = &clk_hclk_msys.clk, | 90 | .parent = &clk_hclk_msys.clk, |
97 | }, | 91 | }, |
98 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | 92 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, |
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = { | |||
101 | static struct clksrc_clk clk_sclk_a2m = { | 95 | static struct clksrc_clk clk_sclk_a2m = { |
102 | .clk = { | 96 | .clk = { |
103 | .name = "sclk_a2m", | 97 | .name = "sclk_a2m", |
104 | .id = -1, | ||
105 | .parent = &clk_mout_apll.clk, | 98 | .parent = &clk_mout_apll.clk, |
106 | }, | 99 | }, |
107 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | 100 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, |
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = { | |||
120 | static struct clksrc_clk clk_hclk_dsys = { | 113 | static struct clksrc_clk clk_hclk_dsys = { |
121 | .clk = { | 114 | .clk = { |
122 | .name = "hclk_dsys", | 115 | .name = "hclk_dsys", |
123 | .id = -1, | ||
124 | }, | 116 | }, |
125 | .sources = &clkset_hclk_sys, | 117 | .sources = &clkset_hclk_sys, |
126 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | 118 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, |
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = { | |||
130 | static struct clksrc_clk clk_pclk_dsys = { | 122 | static struct clksrc_clk clk_pclk_dsys = { |
131 | .clk = { | 123 | .clk = { |
132 | .name = "pclk_dsys", | 124 | .name = "pclk_dsys", |
133 | .id = -1, | ||
134 | .parent = &clk_hclk_dsys.clk, | 125 | .parent = &clk_hclk_dsys.clk, |
135 | }, | 126 | }, |
136 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, | 127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, |
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = { | |||
139 | static struct clksrc_clk clk_hclk_psys = { | 130 | static struct clksrc_clk clk_hclk_psys = { |
140 | .clk = { | 131 | .clk = { |
141 | .name = "hclk_psys", | 132 | .name = "hclk_psys", |
142 | .id = -1, | ||
143 | }, | 133 | }, |
144 | .sources = &clkset_hclk_sys, | 134 | .sources = &clkset_hclk_sys, |
145 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | 135 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, |
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = { | |||
149 | static struct clksrc_clk clk_pclk_psys = { | 139 | static struct clksrc_clk clk_pclk_psys = { |
150 | .clk = { | 140 | .clk = { |
151 | .name = "pclk_psys", | 141 | .name = "pclk_psys", |
152 | .id = -1, | ||
153 | .parent = &clk_hclk_psys.clk, | 142 | .parent = &clk_hclk_psys.clk, |
154 | }, | 143 | }, |
155 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, | 144 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, |
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) | |||
187 | 176 | ||
188 | static struct clk clk_sclk_hdmi27m = { | 177 | static struct clk clk_sclk_hdmi27m = { |
189 | .name = "sclk_hdmi27m", | 178 | .name = "sclk_hdmi27m", |
190 | .id = -1, | ||
191 | .rate = 27000000, | 179 | .rate = 27000000, |
192 | }; | 180 | }; |
193 | 181 | ||
194 | static struct clk clk_sclk_hdmiphy = { | 182 | static struct clk clk_sclk_hdmiphy = { |
195 | .name = "sclk_hdmiphy", | 183 | .name = "sclk_hdmiphy", |
196 | .id = -1, | ||
197 | }; | 184 | }; |
198 | 185 | ||
199 | static struct clk clk_sclk_usbphy0 = { | 186 | static struct clk clk_sclk_usbphy0 = { |
200 | .name = "sclk_usbphy0", | 187 | .name = "sclk_usbphy0", |
201 | .id = -1, | ||
202 | }; | 188 | }; |
203 | 189 | ||
204 | static struct clk clk_sclk_usbphy1 = { | 190 | static struct clk clk_sclk_usbphy1 = { |
205 | .name = "sclk_usbphy1", | 191 | .name = "sclk_usbphy1", |
206 | .id = -1, | ||
207 | }; | 192 | }; |
208 | 193 | ||
209 | static struct clk clk_pcmcdclk0 = { | 194 | static struct clk clk_pcmcdclk0 = { |
210 | .name = "pcmcdclk", | 195 | .name = "pcmcdclk", |
211 | .id = -1, | ||
212 | }; | 196 | }; |
213 | 197 | ||
214 | static struct clk clk_pcmcdclk1 = { | 198 | static struct clk clk_pcmcdclk1 = { |
215 | .name = "pcmcdclk", | 199 | .name = "pcmcdclk", |
216 | .id = -1, | ||
217 | }; | 200 | }; |
218 | 201 | ||
219 | static struct clk clk_pcmcdclk2 = { | 202 | static struct clk clk_pcmcdclk2 = { |
220 | .name = "pcmcdclk", | 203 | .name = "pcmcdclk", |
221 | .id = -1, | ||
222 | }; | 204 | }; |
223 | 205 | ||
224 | static struct clk *clkset_vpllsrc_list[] = { | 206 | static struct clk *clkset_vpllsrc_list[] = { |
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = { | |||
234 | static struct clksrc_clk clk_vpllsrc = { | 216 | static struct clksrc_clk clk_vpllsrc = { |
235 | .clk = { | 217 | .clk = { |
236 | .name = "vpll_src", | 218 | .name = "vpll_src", |
237 | .id = -1, | ||
238 | .enable = s5pv210_clk_mask0_ctrl, | 219 | .enable = s5pv210_clk_mask0_ctrl, |
239 | .ctrlbit = (1 << 7), | 220 | .ctrlbit = (1 << 7), |
240 | }, | 221 | }, |
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = { | |||
255 | static struct clksrc_clk clk_sclk_vpll = { | 236 | static struct clksrc_clk clk_sclk_vpll = { |
256 | .clk = { | 237 | .clk = { |
257 | .name = "sclk_vpll", | 238 | .name = "sclk_vpll", |
258 | .id = -1, | ||
259 | }, | 239 | }, |
260 | .sources = &clkset_sclk_vpll, | 240 | .sources = &clkset_sclk_vpll, |
261 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | 241 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, |
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = { | |||
276 | static struct clksrc_clk clk_mout_dmc0 = { | 256 | static struct clksrc_clk clk_mout_dmc0 = { |
277 | .clk = { | 257 | .clk = { |
278 | .name = "mout_dmc0", | 258 | .name = "mout_dmc0", |
279 | .id = -1, | ||
280 | }, | 259 | }, |
281 | .sources = &clkset_moutdmc0src, | 260 | .sources = &clkset_moutdmc0src, |
282 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | 261 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, |
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = { | |||
285 | static struct clksrc_clk clk_sclk_dmc0 = { | 264 | static struct clksrc_clk clk_sclk_dmc0 = { |
286 | .clk = { | 265 | .clk = { |
287 | .name = "sclk_dmc0", | 266 | .name = "sclk_dmc0", |
288 | .id = -1, | ||
289 | .parent = &clk_mout_dmc0.clk, | 267 | .parent = &clk_mout_dmc0.clk, |
290 | }, | 268 | }, |
291 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | 269 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, |
@@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = { | |||
312 | static struct clk init_clocks_off[] = { | 290 | static struct clk init_clocks_off[] = { |
313 | { | 291 | { |
314 | .name = "pdma", | 292 | .name = "pdma", |
315 | .id = 0, | 293 | .devname = "s3c-pl330.0", |
316 | .parent = &clk_hclk_psys.clk, | 294 | .parent = &clk_hclk_psys.clk, |
317 | .enable = s5pv210_clk_ip0_ctrl, | 295 | .enable = s5pv210_clk_ip0_ctrl, |
318 | .ctrlbit = (1 << 3), | 296 | .ctrlbit = (1 << 3), |
319 | }, { | 297 | }, { |
320 | .name = "pdma", | 298 | .name = "pdma", |
321 | .id = 1, | 299 | .devname = "s3c-pl330.1", |
322 | .parent = &clk_hclk_psys.clk, | 300 | .parent = &clk_hclk_psys.clk, |
323 | .enable = s5pv210_clk_ip0_ctrl, | 301 | .enable = s5pv210_clk_ip0_ctrl, |
324 | .ctrlbit = (1 << 4), | 302 | .ctrlbit = (1 << 4), |
325 | }, { | 303 | }, { |
326 | .name = "rot", | 304 | .name = "rot", |
327 | .id = -1, | ||
328 | .parent = &clk_hclk_dsys.clk, | 305 | .parent = &clk_hclk_dsys.clk, |
329 | .enable = s5pv210_clk_ip0_ctrl, | 306 | .enable = s5pv210_clk_ip0_ctrl, |
330 | .ctrlbit = (1<<29), | 307 | .ctrlbit = (1<<29), |
331 | }, { | 308 | }, { |
332 | .name = "fimc", | 309 | .name = "fimc", |
333 | .id = 0, | 310 | .devname = "s5pv210-fimc.0", |
334 | .parent = &clk_hclk_dsys.clk, | 311 | .parent = &clk_hclk_dsys.clk, |
335 | .enable = s5pv210_clk_ip0_ctrl, | 312 | .enable = s5pv210_clk_ip0_ctrl, |
336 | .ctrlbit = (1 << 24), | 313 | .ctrlbit = (1 << 24), |
337 | }, { | 314 | }, { |
338 | .name = "fimc", | 315 | .name = "fimc", |
339 | .id = 1, | 316 | .devname = "s5pv210-fimc.1", |
340 | .parent = &clk_hclk_dsys.clk, | 317 | .parent = &clk_hclk_dsys.clk, |
341 | .enable = s5pv210_clk_ip0_ctrl, | 318 | .enable = s5pv210_clk_ip0_ctrl, |
342 | .ctrlbit = (1 << 25), | 319 | .ctrlbit = (1 << 25), |
343 | }, { | 320 | }, { |
344 | .name = "fimc", | 321 | .name = "fimc", |
345 | .id = 2, | 322 | .devname = "s5pv210-fimc.2", |
346 | .parent = &clk_hclk_dsys.clk, | 323 | .parent = &clk_hclk_dsys.clk, |
347 | .enable = s5pv210_clk_ip0_ctrl, | 324 | .enable = s5pv210_clk_ip0_ctrl, |
348 | .ctrlbit = (1 << 26), | 325 | .ctrlbit = (1 << 26), |
349 | }, { | 326 | }, { |
350 | .name = "otg", | 327 | .name = "otg", |
351 | .id = -1, | ||
352 | .parent = &clk_hclk_psys.clk, | 328 | .parent = &clk_hclk_psys.clk, |
353 | .enable = s5pv210_clk_ip1_ctrl, | 329 | .enable = s5pv210_clk_ip1_ctrl, |
354 | .ctrlbit = (1<<16), | 330 | .ctrlbit = (1<<16), |
355 | }, { | 331 | }, { |
356 | .name = "usb-host", | 332 | .name = "usb-host", |
357 | .id = -1, | ||
358 | .parent = &clk_hclk_psys.clk, | 333 | .parent = &clk_hclk_psys.clk, |
359 | .enable = s5pv210_clk_ip1_ctrl, | 334 | .enable = s5pv210_clk_ip1_ctrl, |
360 | .ctrlbit = (1<<17), | 335 | .ctrlbit = (1<<17), |
361 | }, { | 336 | }, { |
362 | .name = "lcd", | 337 | .name = "lcd", |
363 | .id = -1, | ||
364 | .parent = &clk_hclk_dsys.clk, | 338 | .parent = &clk_hclk_dsys.clk, |
365 | .enable = s5pv210_clk_ip1_ctrl, | 339 | .enable = s5pv210_clk_ip1_ctrl, |
366 | .ctrlbit = (1<<0), | 340 | .ctrlbit = (1<<0), |
367 | }, { | 341 | }, { |
368 | .name = "cfcon", | 342 | .name = "cfcon", |
369 | .id = 0, | ||
370 | .parent = &clk_hclk_psys.clk, | 343 | .parent = &clk_hclk_psys.clk, |
371 | .enable = s5pv210_clk_ip1_ctrl, | 344 | .enable = s5pv210_clk_ip1_ctrl, |
372 | .ctrlbit = (1<<25), | 345 | .ctrlbit = (1<<25), |
373 | }, { | 346 | }, { |
374 | .name = "hsmmc", | 347 | .name = "hsmmc", |
375 | .id = 0, | 348 | .devname = "s3c-sdhci.0", |
376 | .parent = &clk_hclk_psys.clk, | 349 | .parent = &clk_hclk_psys.clk, |
377 | .enable = s5pv210_clk_ip2_ctrl, | 350 | .enable = s5pv210_clk_ip2_ctrl, |
378 | .ctrlbit = (1<<16), | 351 | .ctrlbit = (1<<16), |
379 | }, { | 352 | }, { |
380 | .name = "hsmmc", | 353 | .name = "hsmmc", |
381 | .id = 1, | 354 | .devname = "s3c-sdhci.1", |
382 | .parent = &clk_hclk_psys.clk, | 355 | .parent = &clk_hclk_psys.clk, |
383 | .enable = s5pv210_clk_ip2_ctrl, | 356 | .enable = s5pv210_clk_ip2_ctrl, |
384 | .ctrlbit = (1<<17), | 357 | .ctrlbit = (1<<17), |
385 | }, { | 358 | }, { |
386 | .name = "hsmmc", | 359 | .name = "hsmmc", |
387 | .id = 2, | 360 | .devname = "s3c-sdhci.2", |
388 | .parent = &clk_hclk_psys.clk, | 361 | .parent = &clk_hclk_psys.clk, |
389 | .enable = s5pv210_clk_ip2_ctrl, | 362 | .enable = s5pv210_clk_ip2_ctrl, |
390 | .ctrlbit = (1<<18), | 363 | .ctrlbit = (1<<18), |
391 | }, { | 364 | }, { |
392 | .name = "hsmmc", | 365 | .name = "hsmmc", |
393 | .id = 3, | 366 | .devname = "s3c-sdhci.3", |
394 | .parent = &clk_hclk_psys.clk, | 367 | .parent = &clk_hclk_psys.clk, |
395 | .enable = s5pv210_clk_ip2_ctrl, | 368 | .enable = s5pv210_clk_ip2_ctrl, |
396 | .ctrlbit = (1<<19), | 369 | .ctrlbit = (1<<19), |
397 | }, { | 370 | }, { |
398 | .name = "systimer", | 371 | .name = "systimer", |
399 | .id = -1, | ||
400 | .parent = &clk_pclk_psys.clk, | 372 | .parent = &clk_pclk_psys.clk, |
401 | .enable = s5pv210_clk_ip3_ctrl, | 373 | .enable = s5pv210_clk_ip3_ctrl, |
402 | .ctrlbit = (1<<16), | 374 | .ctrlbit = (1<<16), |
403 | }, { | 375 | }, { |
404 | .name = "watchdog", | 376 | .name = "watchdog", |
405 | .id = -1, | ||
406 | .parent = &clk_pclk_psys.clk, | 377 | .parent = &clk_pclk_psys.clk, |
407 | .enable = s5pv210_clk_ip3_ctrl, | 378 | .enable = s5pv210_clk_ip3_ctrl, |
408 | .ctrlbit = (1<<22), | 379 | .ctrlbit = (1<<22), |
409 | }, { | 380 | }, { |
410 | .name = "rtc", | 381 | .name = "rtc", |
411 | .id = -1, | ||
412 | .parent = &clk_pclk_psys.clk, | 382 | .parent = &clk_pclk_psys.clk, |
413 | .enable = s5pv210_clk_ip3_ctrl, | 383 | .enable = s5pv210_clk_ip3_ctrl, |
414 | .ctrlbit = (1<<15), | 384 | .ctrlbit = (1<<15), |
415 | }, { | 385 | }, { |
416 | .name = "i2c", | 386 | .name = "i2c", |
417 | .id = 0, | 387 | .devname = "s3c2440-i2c.0", |
418 | .parent = &clk_pclk_psys.clk, | 388 | .parent = &clk_pclk_psys.clk, |
419 | .enable = s5pv210_clk_ip3_ctrl, | 389 | .enable = s5pv210_clk_ip3_ctrl, |
420 | .ctrlbit = (1<<7), | 390 | .ctrlbit = (1<<7), |
421 | }, { | 391 | }, { |
422 | .name = "i2c", | 392 | .name = "i2c", |
423 | .id = 1, | 393 | .devname = "s3c2440-i2c.1", |
424 | .parent = &clk_pclk_psys.clk, | 394 | .parent = &clk_pclk_psys.clk, |
425 | .enable = s5pv210_clk_ip3_ctrl, | 395 | .enable = s5pv210_clk_ip3_ctrl, |
426 | .ctrlbit = (1 << 10), | 396 | .ctrlbit = (1 << 10), |
427 | }, { | 397 | }, { |
428 | .name = "i2c", | 398 | .name = "i2c", |
429 | .id = 2, | 399 | .devname = "s3c2440-i2c.2", |
430 | .parent = &clk_pclk_psys.clk, | 400 | .parent = &clk_pclk_psys.clk, |
431 | .enable = s5pv210_clk_ip3_ctrl, | 401 | .enable = s5pv210_clk_ip3_ctrl, |
432 | .ctrlbit = (1<<9), | 402 | .ctrlbit = (1<<9), |
433 | }, { | 403 | }, { |
434 | .name = "spi", | 404 | .name = "spi", |
435 | .id = 0, | 405 | .devname = "s3c64xx-spi.0", |
436 | .parent = &clk_pclk_psys.clk, | 406 | .parent = &clk_pclk_psys.clk, |
437 | .enable = s5pv210_clk_ip3_ctrl, | 407 | .enable = s5pv210_clk_ip3_ctrl, |
438 | .ctrlbit = (1<<12), | 408 | .ctrlbit = (1<<12), |
439 | }, { | 409 | }, { |
440 | .name = "spi", | 410 | .name = "spi", |
441 | .id = 1, | 411 | .devname = "s3c64xx-spi.1", |
442 | .parent = &clk_pclk_psys.clk, | 412 | .parent = &clk_pclk_psys.clk, |
443 | .enable = s5pv210_clk_ip3_ctrl, | 413 | .enable = s5pv210_clk_ip3_ctrl, |
444 | .ctrlbit = (1<<13), | 414 | .ctrlbit = (1<<13), |
445 | }, { | 415 | }, { |
446 | .name = "spi", | 416 | .name = "spi", |
447 | .id = 2, | 417 | .devname = "s3c64xx-spi.2", |
448 | .parent = &clk_pclk_psys.clk, | 418 | .parent = &clk_pclk_psys.clk, |
449 | .enable = s5pv210_clk_ip3_ctrl, | 419 | .enable = s5pv210_clk_ip3_ctrl, |
450 | .ctrlbit = (1<<14), | 420 | .ctrlbit = (1<<14), |
451 | }, { | 421 | }, { |
452 | .name = "timers", | 422 | .name = "timers", |
453 | .id = -1, | ||
454 | .parent = &clk_pclk_psys.clk, | 423 | .parent = &clk_pclk_psys.clk, |
455 | .enable = s5pv210_clk_ip3_ctrl, | 424 | .enable = s5pv210_clk_ip3_ctrl, |
456 | .ctrlbit = (1<<23), | 425 | .ctrlbit = (1<<23), |
457 | }, { | 426 | }, { |
458 | .name = "adc", | 427 | .name = "adc", |
459 | .id = -1, | ||
460 | .parent = &clk_pclk_psys.clk, | 428 | .parent = &clk_pclk_psys.clk, |
461 | .enable = s5pv210_clk_ip3_ctrl, | 429 | .enable = s5pv210_clk_ip3_ctrl, |
462 | .ctrlbit = (1<<24), | 430 | .ctrlbit = (1<<24), |
463 | }, { | 431 | }, { |
464 | .name = "keypad", | 432 | .name = "keypad", |
465 | .id = -1, | ||
466 | .parent = &clk_pclk_psys.clk, | 433 | .parent = &clk_pclk_psys.clk, |
467 | .enable = s5pv210_clk_ip3_ctrl, | 434 | .enable = s5pv210_clk_ip3_ctrl, |
468 | .ctrlbit = (1<<21), | 435 | .ctrlbit = (1<<21), |
469 | }, { | 436 | }, { |
470 | .name = "iis", | 437 | .name = "iis", |
471 | .id = 0, | 438 | .devname = "samsung-i2s.0", |
472 | .parent = &clk_p, | 439 | .parent = &clk_p, |
473 | .enable = s5pv210_clk_ip3_ctrl, | 440 | .enable = s5pv210_clk_ip3_ctrl, |
474 | .ctrlbit = (1<<4), | 441 | .ctrlbit = (1<<4), |
475 | }, { | 442 | }, { |
476 | .name = "iis", | 443 | .name = "iis", |
477 | .id = 1, | 444 | .devname = "samsung-i2s.1", |
478 | .parent = &clk_p, | 445 | .parent = &clk_p, |
479 | .enable = s5pv210_clk_ip3_ctrl, | 446 | .enable = s5pv210_clk_ip3_ctrl, |
480 | .ctrlbit = (1 << 5), | 447 | .ctrlbit = (1 << 5), |
481 | }, { | 448 | }, { |
482 | .name = "iis", | 449 | .name = "iis", |
483 | .id = 2, | 450 | .devname = "samsung-i2s.2", |
484 | .parent = &clk_p, | 451 | .parent = &clk_p, |
485 | .enable = s5pv210_clk_ip3_ctrl, | 452 | .enable = s5pv210_clk_ip3_ctrl, |
486 | .ctrlbit = (1 << 6), | 453 | .ctrlbit = (1 << 6), |
487 | }, { | 454 | }, { |
488 | .name = "spdif", | 455 | .name = "spdif", |
489 | .id = -1, | ||
490 | .parent = &clk_p, | 456 | .parent = &clk_p, |
491 | .enable = s5pv210_clk_ip3_ctrl, | 457 | .enable = s5pv210_clk_ip3_ctrl, |
492 | .ctrlbit = (1 << 0), | 458 | .ctrlbit = (1 << 0), |
@@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = { | |||
496 | static struct clk init_clocks[] = { | 462 | static struct clk init_clocks[] = { |
497 | { | 463 | { |
498 | .name = "hclk_imem", | 464 | .name = "hclk_imem", |
499 | .id = -1, | ||
500 | .parent = &clk_hclk_msys.clk, | 465 | .parent = &clk_hclk_msys.clk, |
501 | .ctrlbit = (1 << 5), | 466 | .ctrlbit = (1 << 5), |
502 | .enable = s5pv210_clk_ip0_ctrl, | 467 | .enable = s5pv210_clk_ip0_ctrl, |
503 | .ops = &clk_hclk_imem_ops, | 468 | .ops = &clk_hclk_imem_ops, |
504 | }, { | 469 | }, { |
505 | .name = "uart", | 470 | .name = "uart", |
506 | .id = 0, | 471 | .devname = "s5pv210-uart.0", |
507 | .parent = &clk_pclk_psys.clk, | 472 | .parent = &clk_pclk_psys.clk, |
508 | .enable = s5pv210_clk_ip3_ctrl, | 473 | .enable = s5pv210_clk_ip3_ctrl, |
509 | .ctrlbit = (1 << 17), | 474 | .ctrlbit = (1 << 17), |
510 | }, { | 475 | }, { |
511 | .name = "uart", | 476 | .name = "uart", |
512 | .id = 1, | 477 | .devname = "s5pv210-uart.1", |
513 | .parent = &clk_pclk_psys.clk, | 478 | .parent = &clk_pclk_psys.clk, |
514 | .enable = s5pv210_clk_ip3_ctrl, | 479 | .enable = s5pv210_clk_ip3_ctrl, |
515 | .ctrlbit = (1 << 18), | 480 | .ctrlbit = (1 << 18), |
516 | }, { | 481 | }, { |
517 | .name = "uart", | 482 | .name = "uart", |
518 | .id = 2, | 483 | .devname = "s5pv210-uart.2", |
519 | .parent = &clk_pclk_psys.clk, | 484 | .parent = &clk_pclk_psys.clk, |
520 | .enable = s5pv210_clk_ip3_ctrl, | 485 | .enable = s5pv210_clk_ip3_ctrl, |
521 | .ctrlbit = (1 << 19), | 486 | .ctrlbit = (1 << 19), |
522 | }, { | 487 | }, { |
523 | .name = "uart", | 488 | .name = "uart", |
524 | .id = 3, | 489 | .devname = "s5pv210-uart.3", |
525 | .parent = &clk_pclk_psys.clk, | 490 | .parent = &clk_pclk_psys.clk, |
526 | .enable = s5pv210_clk_ip3_ctrl, | 491 | .enable = s5pv210_clk_ip3_ctrl, |
527 | .ctrlbit = (1 << 20), | 492 | .ctrlbit = (1 << 20), |
528 | }, { | 493 | }, { |
529 | .name = "sromc", | 494 | .name = "sromc", |
530 | .id = -1, | ||
531 | .parent = &clk_hclk_psys.clk, | 495 | .parent = &clk_hclk_psys.clk, |
532 | .enable = s5pv210_clk_ip1_ctrl, | 496 | .enable = s5pv210_clk_ip1_ctrl, |
533 | .ctrlbit = (1 << 26), | 497 | .ctrlbit = (1 << 26), |
@@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = { | |||
579 | static struct clksrc_clk clk_sclk_dac = { | 543 | static struct clksrc_clk clk_sclk_dac = { |
580 | .clk = { | 544 | .clk = { |
581 | .name = "sclk_dac", | 545 | .name = "sclk_dac", |
582 | .id = -1, | ||
583 | .enable = s5pv210_clk_mask0_ctrl, | 546 | .enable = s5pv210_clk_mask0_ctrl, |
584 | .ctrlbit = (1 << 2), | 547 | .ctrlbit = (1 << 2), |
585 | }, | 548 | }, |
@@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = { | |||
590 | static struct clksrc_clk clk_sclk_pixel = { | 553 | static struct clksrc_clk clk_sclk_pixel = { |
591 | .clk = { | 554 | .clk = { |
592 | .name = "sclk_pixel", | 555 | .name = "sclk_pixel", |
593 | .id = -1, | ||
594 | .parent = &clk_sclk_vpll.clk, | 556 | .parent = &clk_sclk_vpll.clk, |
595 | }, | 557 | }, |
596 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, | 558 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, |
@@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = { | |||
609 | static struct clksrc_clk clk_sclk_hdmi = { | 571 | static struct clksrc_clk clk_sclk_hdmi = { |
610 | .clk = { | 572 | .clk = { |
611 | .name = "sclk_hdmi", | 573 | .name = "sclk_hdmi", |
612 | .id = -1, | ||
613 | .enable = s5pv210_clk_mask0_ctrl, | 574 | .enable = s5pv210_clk_mask0_ctrl, |
614 | .ctrlbit = (1 << 0), | 575 | .ctrlbit = (1 << 0), |
615 | }, | 576 | }, |
@@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = { | |||
647 | static struct clksrc_clk clk_sclk_audio0 = { | 608 | static struct clksrc_clk clk_sclk_audio0 = { |
648 | .clk = { | 609 | .clk = { |
649 | .name = "sclk_audio", | 610 | .name = "sclk_audio", |
650 | .id = 0, | 611 | .devname = "soc-audio.0", |
651 | .enable = s5pv210_clk_mask0_ctrl, | 612 | .enable = s5pv210_clk_mask0_ctrl, |
652 | .ctrlbit = (1 << 24), | 613 | .ctrlbit = (1 << 24), |
653 | }, | 614 | }, |
@@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = { | |||
676 | static struct clksrc_clk clk_sclk_audio1 = { | 637 | static struct clksrc_clk clk_sclk_audio1 = { |
677 | .clk = { | 638 | .clk = { |
678 | .name = "sclk_audio", | 639 | .name = "sclk_audio", |
679 | .id = 1, | 640 | .devname = "soc-audio.1", |
680 | .enable = s5pv210_clk_mask0_ctrl, | 641 | .enable = s5pv210_clk_mask0_ctrl, |
681 | .ctrlbit = (1 << 25), | 642 | .ctrlbit = (1 << 25), |
682 | }, | 643 | }, |
@@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = { | |||
705 | static struct clksrc_clk clk_sclk_audio2 = { | 666 | static struct clksrc_clk clk_sclk_audio2 = { |
706 | .clk = { | 667 | .clk = { |
707 | .name = "sclk_audio", | 668 | .name = "sclk_audio", |
708 | .id = 2, | 669 | .devname = "soc-audio.2", |
709 | .enable = s5pv210_clk_mask0_ctrl, | 670 | .enable = s5pv210_clk_mask0_ctrl, |
710 | .ctrlbit = (1 << 26), | 671 | .ctrlbit = (1 << 26), |
711 | }, | 672 | }, |
@@ -725,48 +686,12 @@ static struct clksrc_sources clkset_sclk_spdif = { | |||
725 | .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), | 686 | .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), |
726 | }; | 687 | }; |
727 | 688 | ||
728 | static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate) | ||
729 | { | ||
730 | struct clk *pclk; | ||
731 | int ret; | ||
732 | |||
733 | pclk = clk_get_parent(clk); | ||
734 | if (IS_ERR(pclk)) | ||
735 | return -EINVAL; | ||
736 | |||
737 | ret = pclk->ops->set_rate(pclk, rate); | ||
738 | clk_put(pclk); | ||
739 | |||
740 | return ret; | ||
741 | } | ||
742 | |||
743 | static unsigned long s5pv210_spdif_get_rate(struct clk *clk) | ||
744 | { | ||
745 | struct clk *pclk; | ||
746 | int rate; | ||
747 | |||
748 | pclk = clk_get_parent(clk); | ||
749 | if (IS_ERR(pclk)) | ||
750 | return -EINVAL; | ||
751 | |||
752 | rate = pclk->ops->get_rate(clk); | ||
753 | clk_put(pclk); | ||
754 | |||
755 | return rate; | ||
756 | } | ||
757 | |||
758 | static struct clk_ops s5pv210_sclk_spdif_ops = { | ||
759 | .set_rate = s5pv210_spdif_set_rate, | ||
760 | .get_rate = s5pv210_spdif_get_rate, | ||
761 | }; | ||
762 | |||
763 | static struct clksrc_clk clk_sclk_spdif = { | 689 | static struct clksrc_clk clk_sclk_spdif = { |
764 | .clk = { | 690 | .clk = { |
765 | .name = "sclk_spdif", | 691 | .name = "sclk_spdif", |
766 | .id = -1, | ||
767 | .enable = s5pv210_clk_mask0_ctrl, | 692 | .enable = s5pv210_clk_mask0_ctrl, |
768 | .ctrlbit = (1 << 27), | 693 | .ctrlbit = (1 << 27), |
769 | .ops = &s5pv210_sclk_spdif_ops, | 694 | .ops = &s5p_sclk_spdif_ops, |
770 | }, | 695 | }, |
771 | .sources = &clkset_sclk_spdif, | 696 | .sources = &clkset_sclk_spdif, |
772 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, | 697 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, |
@@ -793,7 +718,6 @@ static struct clksrc_clk clksrcs[] = { | |||
793 | { | 718 | { |
794 | .clk = { | 719 | .clk = { |
795 | .name = "sclk_dmc", | 720 | .name = "sclk_dmc", |
796 | .id = -1, | ||
797 | }, | 721 | }, |
798 | .sources = &clkset_group1, | 722 | .sources = &clkset_group1, |
799 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | 723 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, |
@@ -801,7 +725,6 @@ static struct clksrc_clk clksrcs[] = { | |||
801 | }, { | 725 | }, { |
802 | .clk = { | 726 | .clk = { |
803 | .name = "sclk_onenand", | 727 | .name = "sclk_onenand", |
804 | .id = -1, | ||
805 | }, | 728 | }, |
806 | .sources = &clkset_sclk_onenand, | 729 | .sources = &clkset_sclk_onenand, |
807 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, | 730 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, |
@@ -809,7 +732,7 @@ static struct clksrc_clk clksrcs[] = { | |||
809 | }, { | 732 | }, { |
810 | .clk = { | 733 | .clk = { |
811 | .name = "uclk1", | 734 | .name = "uclk1", |
812 | .id = 0, | 735 | .devname = "s5pv210-uart.0", |
813 | .enable = s5pv210_clk_mask0_ctrl, | 736 | .enable = s5pv210_clk_mask0_ctrl, |
814 | .ctrlbit = (1 << 12), | 737 | .ctrlbit = (1 << 12), |
815 | }, | 738 | }, |
@@ -819,7 +742,7 @@ static struct clksrc_clk clksrcs[] = { | |||
819 | }, { | 742 | }, { |
820 | .clk = { | 743 | .clk = { |
821 | .name = "uclk1", | 744 | .name = "uclk1", |
822 | .id = 1, | 745 | .devname = "s5pv210-uart.1", |
823 | .enable = s5pv210_clk_mask0_ctrl, | 746 | .enable = s5pv210_clk_mask0_ctrl, |
824 | .ctrlbit = (1 << 13), | 747 | .ctrlbit = (1 << 13), |
825 | }, | 748 | }, |
@@ -829,7 +752,7 @@ static struct clksrc_clk clksrcs[] = { | |||
829 | }, { | 752 | }, { |
830 | .clk = { | 753 | .clk = { |
831 | .name = "uclk1", | 754 | .name = "uclk1", |
832 | .id = 2, | 755 | .devname = "s5pv210-uart.2", |
833 | .enable = s5pv210_clk_mask0_ctrl, | 756 | .enable = s5pv210_clk_mask0_ctrl, |
834 | .ctrlbit = (1 << 14), | 757 | .ctrlbit = (1 << 14), |
835 | }, | 758 | }, |
@@ -839,7 +762,7 @@ static struct clksrc_clk clksrcs[] = { | |||
839 | }, { | 762 | }, { |
840 | .clk = { | 763 | .clk = { |
841 | .name = "uclk1", | 764 | .name = "uclk1", |
842 | .id = 3, | 765 | .devname = "s5pv210-uart.3", |
843 | .enable = s5pv210_clk_mask0_ctrl, | 766 | .enable = s5pv210_clk_mask0_ctrl, |
844 | .ctrlbit = (1 << 15), | 767 | .ctrlbit = (1 << 15), |
845 | }, | 768 | }, |
@@ -849,7 +772,6 @@ static struct clksrc_clk clksrcs[] = { | |||
849 | }, { | 772 | }, { |
850 | .clk = { | 773 | .clk = { |
851 | .name = "sclk_mixer", | 774 | .name = "sclk_mixer", |
852 | .id = -1, | ||
853 | .enable = s5pv210_clk_mask0_ctrl, | 775 | .enable = s5pv210_clk_mask0_ctrl, |
854 | .ctrlbit = (1 << 1), | 776 | .ctrlbit = (1 << 1), |
855 | }, | 777 | }, |
@@ -858,7 +780,7 @@ static struct clksrc_clk clksrcs[] = { | |||
858 | }, { | 780 | }, { |
859 | .clk = { | 781 | .clk = { |
860 | .name = "sclk_fimc", | 782 | .name = "sclk_fimc", |
861 | .id = 0, | 783 | .devname = "s5pv210-fimc.0", |
862 | .enable = s5pv210_clk_mask1_ctrl, | 784 | .enable = s5pv210_clk_mask1_ctrl, |
863 | .ctrlbit = (1 << 2), | 785 | .ctrlbit = (1 << 2), |
864 | }, | 786 | }, |
@@ -868,7 +790,7 @@ static struct clksrc_clk clksrcs[] = { | |||
868 | }, { | 790 | }, { |
869 | .clk = { | 791 | .clk = { |
870 | .name = "sclk_fimc", | 792 | .name = "sclk_fimc", |
871 | .id = 1, | 793 | .devname = "s5pv210-fimc.1", |
872 | .enable = s5pv210_clk_mask1_ctrl, | 794 | .enable = s5pv210_clk_mask1_ctrl, |
873 | .ctrlbit = (1 << 3), | 795 | .ctrlbit = (1 << 3), |
874 | }, | 796 | }, |
@@ -878,7 +800,7 @@ static struct clksrc_clk clksrcs[] = { | |||
878 | }, { | 800 | }, { |
879 | .clk = { | 801 | .clk = { |
880 | .name = "sclk_fimc", | 802 | .name = "sclk_fimc", |
881 | .id = 2, | 803 | .devname = "s5pv210-fimc.2", |
882 | .enable = s5pv210_clk_mask1_ctrl, | 804 | .enable = s5pv210_clk_mask1_ctrl, |
883 | .ctrlbit = (1 << 4), | 805 | .ctrlbit = (1 << 4), |
884 | }, | 806 | }, |
@@ -888,7 +810,7 @@ static struct clksrc_clk clksrcs[] = { | |||
888 | }, { | 810 | }, { |
889 | .clk = { | 811 | .clk = { |
890 | .name = "sclk_cam", | 812 | .name = "sclk_cam", |
891 | .id = 0, | 813 | .devname = "s5pv210-fimc.0", |
892 | .enable = s5pv210_clk_mask0_ctrl, | 814 | .enable = s5pv210_clk_mask0_ctrl, |
893 | .ctrlbit = (1 << 3), | 815 | .ctrlbit = (1 << 3), |
894 | }, | 816 | }, |
@@ -898,7 +820,7 @@ static struct clksrc_clk clksrcs[] = { | |||
898 | }, { | 820 | }, { |
899 | .clk = { | 821 | .clk = { |
900 | .name = "sclk_cam", | 822 | .name = "sclk_cam", |
901 | .id = 1, | 823 | .devname = "s5pv210-fimc.1", |
902 | .enable = s5pv210_clk_mask0_ctrl, | 824 | .enable = s5pv210_clk_mask0_ctrl, |
903 | .ctrlbit = (1 << 4), | 825 | .ctrlbit = (1 << 4), |
904 | }, | 826 | }, |
@@ -908,7 +830,6 @@ static struct clksrc_clk clksrcs[] = { | |||
908 | }, { | 830 | }, { |
909 | .clk = { | 831 | .clk = { |
910 | .name = "sclk_fimd", | 832 | .name = "sclk_fimd", |
911 | .id = -1, | ||
912 | .enable = s5pv210_clk_mask0_ctrl, | 833 | .enable = s5pv210_clk_mask0_ctrl, |
913 | .ctrlbit = (1 << 5), | 834 | .ctrlbit = (1 << 5), |
914 | }, | 835 | }, |
@@ -918,7 +839,7 @@ static struct clksrc_clk clksrcs[] = { | |||
918 | }, { | 839 | }, { |
919 | .clk = { | 840 | .clk = { |
920 | .name = "sclk_mmc", | 841 | .name = "sclk_mmc", |
921 | .id = 0, | 842 | .devname = "s3c-sdhci.0", |
922 | .enable = s5pv210_clk_mask0_ctrl, | 843 | .enable = s5pv210_clk_mask0_ctrl, |
923 | .ctrlbit = (1 << 8), | 844 | .ctrlbit = (1 << 8), |
924 | }, | 845 | }, |
@@ -928,7 +849,7 @@ static struct clksrc_clk clksrcs[] = { | |||
928 | }, { | 849 | }, { |
929 | .clk = { | 850 | .clk = { |
930 | .name = "sclk_mmc", | 851 | .name = "sclk_mmc", |
931 | .id = 1, | 852 | .devname = "s3c-sdhci.1", |
932 | .enable = s5pv210_clk_mask0_ctrl, | 853 | .enable = s5pv210_clk_mask0_ctrl, |
933 | .ctrlbit = (1 << 9), | 854 | .ctrlbit = (1 << 9), |
934 | }, | 855 | }, |
@@ -938,7 +859,7 @@ static struct clksrc_clk clksrcs[] = { | |||
938 | }, { | 859 | }, { |
939 | .clk = { | 860 | .clk = { |
940 | .name = "sclk_mmc", | 861 | .name = "sclk_mmc", |
941 | .id = 2, | 862 | .devname = "s3c-sdhci.2", |
942 | .enable = s5pv210_clk_mask0_ctrl, | 863 | .enable = s5pv210_clk_mask0_ctrl, |
943 | .ctrlbit = (1 << 10), | 864 | .ctrlbit = (1 << 10), |
944 | }, | 865 | }, |
@@ -948,7 +869,7 @@ static struct clksrc_clk clksrcs[] = { | |||
948 | }, { | 869 | }, { |
949 | .clk = { | 870 | .clk = { |
950 | .name = "sclk_mmc", | 871 | .name = "sclk_mmc", |
951 | .id = 3, | 872 | .devname = "s3c-sdhci.3", |
952 | .enable = s5pv210_clk_mask0_ctrl, | 873 | .enable = s5pv210_clk_mask0_ctrl, |
953 | .ctrlbit = (1 << 11), | 874 | .ctrlbit = (1 << 11), |
954 | }, | 875 | }, |
@@ -958,7 +879,6 @@ static struct clksrc_clk clksrcs[] = { | |||
958 | }, { | 879 | }, { |
959 | .clk = { | 880 | .clk = { |
960 | .name = "sclk_mfc", | 881 | .name = "sclk_mfc", |
961 | .id = -1, | ||
962 | .enable = s5pv210_clk_ip0_ctrl, | 882 | .enable = s5pv210_clk_ip0_ctrl, |
963 | .ctrlbit = (1 << 16), | 883 | .ctrlbit = (1 << 16), |
964 | }, | 884 | }, |
@@ -968,7 +888,6 @@ static struct clksrc_clk clksrcs[] = { | |||
968 | }, { | 888 | }, { |
969 | .clk = { | 889 | .clk = { |
970 | .name = "sclk_g2d", | 890 | .name = "sclk_g2d", |
971 | .id = -1, | ||
972 | .enable = s5pv210_clk_ip0_ctrl, | 891 | .enable = s5pv210_clk_ip0_ctrl, |
973 | .ctrlbit = (1 << 12), | 892 | .ctrlbit = (1 << 12), |
974 | }, | 893 | }, |
@@ -978,7 +897,6 @@ static struct clksrc_clk clksrcs[] = { | |||
978 | }, { | 897 | }, { |
979 | .clk = { | 898 | .clk = { |
980 | .name = "sclk_g3d", | 899 | .name = "sclk_g3d", |
981 | .id = -1, | ||
982 | .enable = s5pv210_clk_ip0_ctrl, | 900 | .enable = s5pv210_clk_ip0_ctrl, |
983 | .ctrlbit = (1 << 8), | 901 | .ctrlbit = (1 << 8), |
984 | }, | 902 | }, |
@@ -988,7 +906,6 @@ static struct clksrc_clk clksrcs[] = { | |||
988 | }, { | 906 | }, { |
989 | .clk = { | 907 | .clk = { |
990 | .name = "sclk_csis", | 908 | .name = "sclk_csis", |
991 | .id = -1, | ||
992 | .enable = s5pv210_clk_mask0_ctrl, | 909 | .enable = s5pv210_clk_mask0_ctrl, |
993 | .ctrlbit = (1 << 6), | 910 | .ctrlbit = (1 << 6), |
994 | }, | 911 | }, |
@@ -998,7 +915,7 @@ static struct clksrc_clk clksrcs[] = { | |||
998 | }, { | 915 | }, { |
999 | .clk = { | 916 | .clk = { |
1000 | .name = "sclk_spi", | 917 | .name = "sclk_spi", |
1001 | .id = 0, | 918 | .devname = "s3c64xx-spi.0", |
1002 | .enable = s5pv210_clk_mask0_ctrl, | 919 | .enable = s5pv210_clk_mask0_ctrl, |
1003 | .ctrlbit = (1 << 16), | 920 | .ctrlbit = (1 << 16), |
1004 | }, | 921 | }, |
@@ -1008,7 +925,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1008 | }, { | 925 | }, { |
1009 | .clk = { | 926 | .clk = { |
1010 | .name = "sclk_spi", | 927 | .name = "sclk_spi", |
1011 | .id = 1, | 928 | .devname = "s3c64xx-spi.1", |
1012 | .enable = s5pv210_clk_mask0_ctrl, | 929 | .enable = s5pv210_clk_mask0_ctrl, |
1013 | .ctrlbit = (1 << 17), | 930 | .ctrlbit = (1 << 17), |
1014 | }, | 931 | }, |
@@ -1018,7 +935,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1018 | }, { | 935 | }, { |
1019 | .clk = { | 936 | .clk = { |
1020 | .name = "sclk_pwi", | 937 | .name = "sclk_pwi", |
1021 | .id = -1, | ||
1022 | .enable = s5pv210_clk_mask0_ctrl, | 938 | .enable = s5pv210_clk_mask0_ctrl, |
1023 | .ctrlbit = (1 << 29), | 939 | .ctrlbit = (1 << 29), |
1024 | }, | 940 | }, |
@@ -1028,7 +944,6 @@ static struct clksrc_clk clksrcs[] = { | |||
1028 | }, { | 944 | }, { |
1029 | .clk = { | 945 | .clk = { |
1030 | .name = "sclk_pwm", | 946 | .name = "sclk_pwm", |
1031 | .id = -1, | ||
1032 | .enable = s5pv210_clk_mask0_ctrl, | 947 | .enable = s5pv210_clk_mask0_ctrl, |
1033 | .ctrlbit = (1 << 19), | 948 | .ctrlbit = (1 << 19), |
1034 | }, | 949 | }, |
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c index e3249a47e3b1..eaf9a7bff7a0 100644 --- a/arch/arm/mach-s5pv210/dev-spi.c +++ b/arch/arm/mach-s5pv210/dev-spi.c | |||
@@ -85,6 +85,7 @@ static struct s3c64xx_spi_info s5pv210_spi0_pdata = { | |||
85 | .fifo_lvl_mask = 0x1ff, | 85 | .fifo_lvl_mask = 0x1ff, |
86 | .rx_lvl_offset = 15, | 86 | .rx_lvl_offset = 15, |
87 | .high_speed = 1, | 87 | .high_speed = 1, |
88 | .tx_st_done = 25, | ||
88 | }; | 89 | }; |
89 | 90 | ||
90 | static u64 spi_dmamask = DMA_BIT_MASK(32); | 91 | static u64 spi_dmamask = DMA_BIT_MASK(32); |
@@ -129,6 +130,7 @@ static struct s3c64xx_spi_info s5pv210_spi1_pdata = { | |||
129 | .fifo_lvl_mask = 0x7f, | 130 | .fifo_lvl_mask = 0x7f, |
130 | .rx_lvl_offset = 15, | 131 | .rx_lvl_offset = 15, |
131 | .high_speed = 1, | 132 | .high_speed = 1, |
133 | .tx_st_done = 25, | ||
132 | }; | 134 | }; |
133 | 135 | ||
134 | struct platform_device s5pv210_device_spi1 = { | 136 | struct platform_device s5pv210_device_spi1 = { |
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h deleted file mode 100644 index 60d992989bdc..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/regs-fb.h +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Ben Dooks <ben-linux@fluff.org> | ||
3 | * | ||
4 | * Dummy framebuffer to allow build for the moment. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_MACH_REGS_FB_H | ||
12 | #define __ASM_ARCH_MACH_REGS_FB_H __FILE__ | ||
13 | |||
14 | #include <plat/regs-fb-v4.h> | ||
15 | |||
16 | static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) | ||
17 | { | ||
18 | return 0x2400 + (window * 256 *4 ) + reg; | ||
19 | } | ||
20 | |||
21 | #endif /* __ASM_ARCH_MACH_REGS_FB_H */ | ||
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index 4e1d8ff5ae59..509627f25111 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c | |||
@@ -29,7 +29,6 @@ | |||
29 | 29 | ||
30 | #include <mach/map.h> | 30 | #include <mach/map.h> |
31 | #include <mach/regs-clock.h> | 31 | #include <mach/regs-clock.h> |
32 | #include <mach/regs-fb.h> | ||
33 | 32 | ||
34 | #include <plat/gpio-cfg.h> | 33 | #include <plat/gpio-cfg.h> |
35 | #include <plat/regs-serial.h> | 34 | #include <plat/regs-serial.h> |
@@ -40,6 +39,7 @@ | |||
40 | #include <plat/fimc-core.h> | 39 | #include <plat/fimc-core.h> |
41 | #include <plat/sdhci.h> | 40 | #include <plat/sdhci.h> |
42 | #include <plat/s5p-time.h> | 41 | #include <plat/s5p-time.h> |
42 | #include <plat/regs-fb-v4.h> | ||
43 | 43 | ||
44 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 44 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
45 | #define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 45 | #define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 31d5aa769753..e0c4d06b9db6 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c | |||
@@ -34,7 +34,6 @@ | |||
34 | 34 | ||
35 | #include <mach/map.h> | 35 | #include <mach/map.h> |
36 | #include <mach/regs-clock.h> | 36 | #include <mach/regs-clock.h> |
37 | #include <mach/regs-fb.h> | ||
38 | 37 | ||
39 | #include <plat/gpio-cfg.h> | 38 | #include <plat/gpio-cfg.h> |
40 | #include <plat/regs-serial.h> | 39 | #include <plat/regs-serial.h> |
@@ -47,6 +46,7 @@ | |||
47 | #include <plat/sdhci.h> | 46 | #include <plat/sdhci.h> |
48 | #include <plat/clock.h> | 47 | #include <plat/clock.h> |
49 | #include <plat/s5p-time.h> | 48 | #include <plat/s5p-time.h> |
49 | #include <plat/regs-fb-v4.h> | ||
50 | 50 | ||
51 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 51 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
52 | #define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 52 | #define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index c6a9e86c2d5c..ef20f922249d 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c | |||
@@ -29,7 +29,6 @@ | |||
29 | 29 | ||
30 | #include <mach/map.h> | 30 | #include <mach/map.h> |
31 | #include <mach/regs-clock.h> | 31 | #include <mach/regs-clock.h> |
32 | #include <mach/regs-fb.h> | ||
33 | 32 | ||
34 | #include <plat/regs-serial.h> | 33 | #include <plat/regs-serial.h> |
35 | #include <plat/regs-srom.h> | 34 | #include <plat/regs-srom.h> |
@@ -45,6 +44,8 @@ | |||
45 | #include <plat/pm.h> | 44 | #include <plat/pm.h> |
46 | #include <plat/fb.h> | 45 | #include <plat/fb.h> |
47 | #include <plat/s5p-time.h> | 46 | #include <plat/s5p-time.h> |
47 | #include <plat/backlight.h> | ||
48 | #include <plat/regs-fb-v4.h> | ||
48 | 49 | ||
49 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 50 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
50 | #define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 51 | #define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
@@ -210,45 +211,6 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = { | |||
210 | .setup_gpio = s5pv210_fb_gpio_setup_24bpp, | 211 | .setup_gpio = s5pv210_fb_gpio_setup_24bpp, |
211 | }; | 212 | }; |
212 | 213 | ||
213 | static int smdkv210_backlight_init(struct device *dev) | ||
214 | { | ||
215 | int ret; | ||
216 | |||
217 | ret = gpio_request(S5PV210_GPD0(3), "Backlight"); | ||
218 | if (ret) { | ||
219 | printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n"); | ||
220 | return ret; | ||
221 | } | ||
222 | |||
223 | /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */ | ||
224 | s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2)); | ||
225 | |||
226 | return 0; | ||
227 | } | ||
228 | |||
229 | static void smdkv210_backlight_exit(struct device *dev) | ||
230 | { | ||
231 | s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT); | ||
232 | gpio_free(S5PV210_GPD0(3)); | ||
233 | } | ||
234 | |||
235 | static struct platform_pwm_backlight_data smdkv210_backlight_data = { | ||
236 | .pwm_id = 3, | ||
237 | .max_brightness = 255, | ||
238 | .dft_brightness = 255, | ||
239 | .pwm_period_ns = 78770, | ||
240 | .init = smdkv210_backlight_init, | ||
241 | .exit = smdkv210_backlight_exit, | ||
242 | }; | ||
243 | |||
244 | static struct platform_device smdkv210_backlight_device = { | ||
245 | .name = "pwm-backlight", | ||
246 | .dev = { | ||
247 | .parent = &s3c_device_timer[3].dev, | ||
248 | .platform_data = &smdkv210_backlight_data, | ||
249 | }, | ||
250 | }; | ||
251 | |||
252 | static struct platform_device *smdkv210_devices[] __initdata = { | 214 | static struct platform_device *smdkv210_devices[] __initdata = { |
253 | &s3c_device_adc, | 215 | &s3c_device_adc, |
254 | &s3c_device_cfcon, | 216 | &s3c_device_cfcon, |
@@ -270,8 +232,6 @@ static struct platform_device *smdkv210_devices[] __initdata = { | |||
270 | &samsung_device_keypad, | 232 | &samsung_device_keypad, |
271 | &smdkv210_dm9000, | 233 | &smdkv210_dm9000, |
272 | &smdkv210_lcd_lte480wv, | 234 | &smdkv210_lcd_lte480wv, |
273 | &s3c_device_timer[3], | ||
274 | &smdkv210_backlight_device, | ||
275 | }; | 235 | }; |
276 | 236 | ||
277 | static void __init smdkv210_dm9000_init(void) | 237 | static void __init smdkv210_dm9000_init(void) |
@@ -310,6 +270,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | |||
310 | .oversampling_shift = 2, | 270 | .oversampling_shift = 2, |
311 | }; | 271 | }; |
312 | 272 | ||
273 | /* LCD Backlight data */ | ||
274 | static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = { | ||
275 | .no = S5PV210_GPD0(3), | ||
276 | .func = S3C_GPIO_SFN(2), | ||
277 | }; | ||
278 | |||
279 | static struct platform_pwm_backlight_data smdkv210_bl_data = { | ||
280 | .pwm_id = 3, | ||
281 | }; | ||
282 | |||
313 | static void __init smdkv210_map_io(void) | 283 | static void __init smdkv210_map_io(void) |
314 | { | 284 | { |
315 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | 285 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); |
@@ -341,6 +311,8 @@ static void __init smdkv210_machine_init(void) | |||
341 | 311 | ||
342 | s3c_fb_set_platdata(&smdkv210_lcd0_pdata); | 312 | s3c_fb_set_platdata(&smdkv210_lcd0_pdata); |
343 | 313 | ||
314 | samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data); | ||
315 | |||
344 | platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); | 316 | platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); |
345 | } | 317 | } |
346 | 318 | ||
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c index e932ebfac56d..55103c8220b3 100644 --- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/fb.h> | 15 | #include <linux/fb.h> |
16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
17 | 17 | ||
18 | #include <mach/regs-fb.h> | ||
19 | #include <mach/map.h> | 18 | #include <mach/map.h> |
20 | #include <plat/fb.h> | 19 | #include <plat/fb.h> |
21 | #include <mach/regs-clock.h> | 20 | #include <mach/regs-clock.h> |
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c index 245140c0df10..642de0408f25 100644 --- a/arch/arm/mach-vt8500/irq.c +++ b/arch/arm/mach-vt8500/irq.c | |||
@@ -39,9 +39,10 @@ | |||
39 | static void __iomem *ic_regbase; | 39 | static void __iomem *ic_regbase; |
40 | static void __iomem *sic_regbase; | 40 | static void __iomem *sic_regbase; |
41 | 41 | ||
42 | static void vt8500_irq_mask(unsigned int irq) | 42 | static void vt8500_irq_mask(struct irq_data *d) |
43 | { | 43 | { |
44 | void __iomem *base = ic_regbase; | 44 | void __iomem *base = ic_regbase; |
45 | unsigned irq = d->irq; | ||
45 | u8 edge; | 46 | u8 edge; |
46 | 47 | ||
47 | if (irq >= 64) { | 48 | if (irq >= 64) { |
@@ -64,9 +65,10 @@ static void vt8500_irq_mask(unsigned int irq) | |||
64 | } | 65 | } |
65 | } | 66 | } |
66 | 67 | ||
67 | static void vt8500_irq_unmask(unsigned int irq) | 68 | static void vt8500_irq_unmask(struct irq_data *d) |
68 | { | 69 | { |
69 | void __iomem *base = ic_regbase; | 70 | void __iomem *base = ic_regbase; |
71 | unsigned irq = d->irq; | ||
70 | u8 dctr; | 72 | u8 dctr; |
71 | 73 | ||
72 | if (irq >= 64) { | 74 | if (irq >= 64) { |
@@ -78,10 +80,11 @@ static void vt8500_irq_unmask(unsigned int irq) | |||
78 | writeb(dctr, base + VT8500_IC_DCTR + irq); | 80 | writeb(dctr, base + VT8500_IC_DCTR + irq); |
79 | } | 81 | } |
80 | 82 | ||
81 | static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) | 83 | static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type) |
82 | { | 84 | { |
83 | void __iomem *base = ic_regbase; | 85 | void __iomem *base = ic_regbase; |
84 | unsigned int orig_irq = irq; | 86 | unsigned irq = d->irq; |
87 | unsigned orig_irq = irq; | ||
85 | u8 dctr; | 88 | u8 dctr; |
86 | 89 | ||
87 | if (irq >= 64) { | 90 | if (irq >= 64) { |
@@ -114,11 +117,11 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) | |||
114 | } | 117 | } |
115 | 118 | ||
116 | static struct irq_chip vt8500_irq_chip = { | 119 | static struct irq_chip vt8500_irq_chip = { |
117 | .name = "vt8500", | 120 | .name = "vt8500", |
118 | .ack = vt8500_irq_mask, | 121 | .irq_ack = vt8500_irq_mask, |
119 | .mask = vt8500_irq_mask, | 122 | .irq_mask = vt8500_irq_mask, |
120 | .unmask = vt8500_irq_unmask, | 123 | .irq_unmask = vt8500_irq_unmask, |
121 | .set_type = vt8500_irq_set_type, | 124 | .irq_set_type = vt8500_irq_set_type, |
122 | }; | 125 | }; |
123 | 126 | ||
124 | void __init vt8500_init_irq(void) | 127 | void __init vt8500_init_irq(void) |
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ef59099a5463..44c086710d2b 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -120,17 +120,22 @@ static void l2x0_cache_sync(void) | |||
120 | spin_unlock_irqrestore(&l2x0_lock, flags); | 120 | spin_unlock_irqrestore(&l2x0_lock, flags); |
121 | } | 121 | } |
122 | 122 | ||
123 | static void l2x0_flush_all(void) | 123 | static void __l2x0_flush_all(void) |
124 | { | 124 | { |
125 | unsigned long flags; | ||
126 | |||
127 | /* clean all ways */ | ||
128 | spin_lock_irqsave(&l2x0_lock, flags); | ||
129 | debug_writel(0x03); | 125 | debug_writel(0x03); |
130 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); | 126 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); |
131 | cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); | 127 | cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); |
132 | cache_sync(); | 128 | cache_sync(); |
133 | debug_writel(0x00); | 129 | debug_writel(0x00); |
130 | } | ||
131 | |||
132 | static void l2x0_flush_all(void) | ||
133 | { | ||
134 | unsigned long flags; | ||
135 | |||
136 | /* clean all ways */ | ||
137 | spin_lock_irqsave(&l2x0_lock, flags); | ||
138 | __l2x0_flush_all(); | ||
134 | spin_unlock_irqrestore(&l2x0_lock, flags); | 139 | spin_unlock_irqrestore(&l2x0_lock, flags); |
135 | } | 140 | } |
136 | 141 | ||
@@ -266,7 +271,9 @@ static void l2x0_disable(void) | |||
266 | unsigned long flags; | 271 | unsigned long flags; |
267 | 272 | ||
268 | spin_lock_irqsave(&l2x0_lock, flags); | 273 | spin_lock_irqsave(&l2x0_lock, flags); |
269 | writel(0, l2x0_base + L2X0_CTRL); | 274 | __l2x0_flush_all(); |
275 | writel_relaxed(0, l2x0_base + L2X0_CTRL); | ||
276 | dsb(); | ||
270 | spin_unlock_irqrestore(&l2x0_lock, flags); | 277 | spin_unlock_irqrestore(&l2x0_lock, flags); |
271 | } | 278 | } |
272 | 279 | ||
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 9d9e736c2b4f..594d677b92c8 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
@@ -759,7 +759,7 @@ early_param("vmalloc", early_vmalloc); | |||
759 | 759 | ||
760 | static phys_addr_t lowmem_limit __initdata = 0; | 760 | static phys_addr_t lowmem_limit __initdata = 0; |
761 | 761 | ||
762 | static void __init sanity_check_meminfo(void) | 762 | void __init sanity_check_meminfo(void) |
763 | { | 763 | { |
764 | int i, j, highmem = 0; | 764 | int i, j, highmem = 0; |
765 | 765 | ||
@@ -1032,8 +1032,9 @@ void __init paging_init(struct machine_desc *mdesc) | |||
1032 | { | 1032 | { |
1033 | void *zero_page; | 1033 | void *zero_page; |
1034 | 1034 | ||
1035 | memblock_set_current_limit(lowmem_limit); | ||
1036 | |||
1035 | build_mem_type_table(); | 1037 | build_mem_type_table(); |
1036 | sanity_check_meminfo(); | ||
1037 | prepare_page_table(); | 1038 | prepare_page_table(); |
1038 | map_lowmem(); | 1039 | map_lowmem(); |
1039 | devicemaps_init(mdesc); | 1040 | devicemaps_init(mdesc); |
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 687d02319a41..941a98c9e8aa 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c | |||
@@ -27,6 +27,10 @@ void __init arm_mm_memblock_reserve(void) | |||
27 | memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE); | 27 | memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE); |
28 | } | 28 | } |
29 | 29 | ||
30 | void __init sanity_check_meminfo(void) | ||
31 | { | ||
32 | } | ||
33 | |||
30 | /* | 34 | /* |
31 | * paging_init() sets up the page tables, initialises the zone memory | 35 | * paging_init() sets up the page tables, initialises the zone memory |
32 | * maps, and sets up the zero page, bad page and bad page tables. | 36 | * maps, and sets up the zero page, bad page and bad page tables. |
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c index cf97caafe56b..f95d3268ae1f 100644 --- a/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/arch/arm/plat-s3c24xx/clock-dclk.c | |||
@@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = { | |||
169 | 169 | ||
170 | struct clk s3c24xx_dclk0 = { | 170 | struct clk s3c24xx_dclk0 = { |
171 | .name = "dclk0", | 171 | .name = "dclk0", |
172 | .id = -1, | ||
173 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | 172 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, |
174 | .enable = s3c24xx_dclk_enable, | 173 | .enable = s3c24xx_dclk_enable, |
175 | .ops = &dclk_ops, | 174 | .ops = &dclk_ops, |
@@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = { | |||
177 | 176 | ||
178 | struct clk s3c24xx_dclk1 = { | 177 | struct clk s3c24xx_dclk1 = { |
179 | .name = "dclk1", | 178 | .name = "dclk1", |
180 | .id = -1, | ||
181 | .ctrlbit = S3C2410_DCLKCON_DCLK1EN, | 179 | .ctrlbit = S3C2410_DCLKCON_DCLK1EN, |
182 | .enable = s3c24xx_dclk_enable, | 180 | .enable = s3c24xx_dclk_enable, |
183 | .ops = &dclk_ops, | 181 | .ops = &dclk_ops, |
@@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = { | |||
189 | 187 | ||
190 | struct clk s3c24xx_clkout0 = { | 188 | struct clk s3c24xx_clkout0 = { |
191 | .name = "clkout0", | 189 | .name = "clkout0", |
192 | .id = -1, | ||
193 | .ops = &clkout_ops, | 190 | .ops = &clkout_ops, |
194 | }; | 191 | }; |
195 | 192 | ||
196 | struct clk s3c24xx_clkout1 = { | 193 | struct clk s3c24xx_clkout1 = { |
197 | .name = "clkout1", | 194 | .name = "clkout1", |
198 | .id = -1, | ||
199 | .ops = &clkout_ops, | 195 | .ops = &clkout_ops, |
200 | }; | 196 | }; |
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 73667994518a..a76bf2df3333 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c | |||
@@ -150,9 +150,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) | |||
150 | { | 150 | { |
151 | struct s3c2410fb_mach_info *npd; | 151 | struct s3c2410fb_mach_info *npd; |
152 | 152 | ||
153 | npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL); | 153 | npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd); |
154 | if (npd) { | 154 | if (npd) { |
155 | s3c_device_lcd.dev.platform_data = npd; | ||
156 | npd->displays = kmemdup(pd->displays, | 155 | npd->displays = kmemdup(pd->displays, |
157 | sizeof(struct s3c2410fb_display) * npd->num_displays, | 156 | sizeof(struct s3c2410fb_display) * npd->num_displays, |
158 | GFP_KERNEL); | 157 | GFP_KERNEL); |
@@ -188,12 +187,10 @@ struct platform_device s3c_device_ts = { | |||
188 | }; | 187 | }; |
189 | EXPORT_SYMBOL(s3c_device_ts); | 188 | EXPORT_SYMBOL(s3c_device_ts); |
190 | 189 | ||
191 | static struct s3c2410_ts_mach_info s3c2410ts_info; | ||
192 | |||
193 | void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info) | 190 | void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info) |
194 | { | 191 | { |
195 | memcpy(&s3c2410ts_info, hard_s3c2410ts_info, sizeof(struct s3c2410_ts_mach_info)); | 192 | s3c_set_platdata(hard_s3c2410ts_info, |
196 | s3c_device_ts.dev.platform_data = &s3c2410ts_info; | 193 | sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts); |
197 | } | 194 | } |
198 | 195 | ||
199 | /* USB Device (Gadget)*/ | 196 | /* USB Device (Gadget)*/ |
@@ -223,15 +220,7 @@ EXPORT_SYMBOL(s3c_device_usbgadget); | |||
223 | 220 | ||
224 | void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) | 221 | void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) |
225 | { | 222 | { |
226 | struct s3c2410_udc_mach_info *npd; | 223 | s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget); |
227 | |||
228 | npd = kmalloc(sizeof(*npd), GFP_KERNEL); | ||
229 | if (npd) { | ||
230 | memcpy(npd, pd, sizeof(*npd)); | ||
231 | s3c_device_usbgadget.dev.platform_data = npd; | ||
232 | } else { | ||
233 | printk(KERN_ERR "no memory for udc platform data\n"); | ||
234 | } | ||
235 | } | 224 | } |
236 | 225 | ||
237 | /* USB High Speed 2.0 Device (Gadget) */ | 226 | /* USB High Speed 2.0 Device (Gadget) */ |
@@ -263,15 +252,7 @@ struct platform_device s3c_device_usb_hsudc = { | |||
263 | 252 | ||
264 | void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd) | 253 | void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd) |
265 | { | 254 | { |
266 | struct s3c24xx_hsudc_platdata *npd; | 255 | s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc); |
267 | |||
268 | npd = kmalloc(sizeof(*npd), GFP_KERNEL); | ||
269 | if (npd) { | ||
270 | memcpy(npd, pd, sizeof(*npd)); | ||
271 | s3c_device_usb_hsudc.dev.platform_data = npd; | ||
272 | } else { | ||
273 | printk(KERN_ERR "no memory for udc platform data\n"); | ||
274 | } | ||
275 | } | 256 | } |
276 | 257 | ||
277 | /* IIS */ | 258 | /* IIS */ |
@@ -383,13 +364,8 @@ EXPORT_SYMBOL(s3c_device_sdi); | |||
383 | 364 | ||
384 | void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) | 365 | void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) |
385 | { | 366 | { |
386 | struct s3c24xx_mci_pdata *npd; | 367 | s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata), |
387 | 368 | &s3c_device_sdi); | |
388 | npd = kmemdup(pdata, sizeof(struct s3c24xx_mci_pdata), GFP_KERNEL); | ||
389 | if (!npd) | ||
390 | printk(KERN_ERR "%s: no memory to copy pdata", __func__); | ||
391 | |||
392 | s3c_device_sdi.dev.platform_data = npd; | ||
393 | } | 369 | } |
394 | 370 | ||
395 | 371 | ||
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 2abf9660bc6c..a79a8ccd25f6 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c | |||
@@ -1027,17 +1027,13 @@ int s3c2410_dma_config(unsigned int channel, | |||
1027 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | 1027 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); |
1028 | unsigned int dcon; | 1028 | unsigned int dcon; |
1029 | 1029 | ||
1030 | pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", | 1030 | pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit); |
1031 | __func__, channel, xferunit, dcon); | ||
1032 | 1031 | ||
1033 | if (chan == NULL) | 1032 | if (chan == NULL) |
1034 | return -EINVAL; | 1033 | return -EINVAL; |
1035 | 1034 | ||
1036 | pr_debug("%s: Initial dcon is %08x\n", __func__, dcon); | ||
1037 | |||
1038 | dcon = chan->dcon & dma_sel.dcon_mask; | 1035 | dcon = chan->dcon & dma_sel.dcon_mask; |
1039 | 1036 | pr_debug("%s: dcon is %08x\n", __func__, dcon); | |
1040 | pr_debug("%s: New dcon is %08x\n", __func__, dcon); | ||
1041 | 1037 | ||
1042 | switch (chan->req_ch) { | 1038 | switch (chan->req_ch) { |
1043 | case DMACH_I2S_IN: | 1039 | case DMACH_I2S_IN: |
@@ -1235,7 +1231,7 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp) | |||
1235 | /* restore channel's hardware configuration */ | 1231 | /* restore channel's hardware configuration */ |
1236 | 1232 | ||
1237 | if (!cp->in_use) | 1233 | if (!cp->in_use) |
1238 | return 0; | 1234 | return; |
1239 | 1235 | ||
1240 | printk(KERN_INFO "dma%d: restoring configuration\n", cp->number); | 1236 | printk(KERN_INFO "dma%d: restoring configuration\n", cp->number); |
1241 | 1237 | ||
@@ -1246,8 +1242,6 @@ static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp) | |||
1246 | 1242 | ||
1247 | if (cp->map != NULL) | 1243 | if (cp->map != NULL) |
1248 | dma_sel.select(cp, cp->map); | 1244 | dma_sel.select(cp, cp->map); |
1249 | |||
1250 | return 0; | ||
1251 | } | 1245 | } |
1252 | 1246 | ||
1253 | static void s3c2410_dma_resume(void) | 1247 | static void s3c2410_dma_resume(void) |
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h new file mode 100644 index 000000000000..7dffa83d23ff --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h | |||
@@ -0,0 +1,7 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c index 9ecc5d913679..def76aa3825a 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c | |||
@@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable) | |||
90 | static struct clk init_clocks_off[] = { | 90 | static struct clk init_clocks_off[] = { |
91 | { | 91 | { |
92 | .name = "nand", | 92 | .name = "nand", |
93 | .id = -1, | ||
94 | .parent = &clk_h, | 93 | .parent = &clk_h, |
95 | .enable = s3c2410_clkcon_enable, | 94 | .enable = s3c2410_clkcon_enable, |
96 | .ctrlbit = S3C2410_CLKCON_NAND, | 95 | .ctrlbit = S3C2410_CLKCON_NAND, |
97 | }, { | 96 | }, { |
98 | .name = "sdi", | 97 | .name = "sdi", |
99 | .id = -1, | ||
100 | .parent = &clk_p, | 98 | .parent = &clk_p, |
101 | .enable = s3c2410_clkcon_enable, | 99 | .enable = s3c2410_clkcon_enable, |
102 | .ctrlbit = S3C2410_CLKCON_SDI, | 100 | .ctrlbit = S3C2410_CLKCON_SDI, |
103 | }, { | 101 | }, { |
104 | .name = "adc", | 102 | .name = "adc", |
105 | .id = -1, | ||
106 | .parent = &clk_p, | 103 | .parent = &clk_p, |
107 | .enable = s3c2410_clkcon_enable, | 104 | .enable = s3c2410_clkcon_enable, |
108 | .ctrlbit = S3C2410_CLKCON_ADC, | 105 | .ctrlbit = S3C2410_CLKCON_ADC, |
109 | }, { | 106 | }, { |
110 | .name = "i2c", | 107 | .name = "i2c", |
111 | .id = -1, | ||
112 | .parent = &clk_p, | 108 | .parent = &clk_p, |
113 | .enable = s3c2410_clkcon_enable, | 109 | .enable = s3c2410_clkcon_enable, |
114 | .ctrlbit = S3C2410_CLKCON_IIC, | 110 | .ctrlbit = S3C2410_CLKCON_IIC, |
115 | }, { | 111 | }, { |
116 | .name = "iis", | 112 | .name = "iis", |
117 | .id = -1, | ||
118 | .parent = &clk_p, | 113 | .parent = &clk_p, |
119 | .enable = s3c2410_clkcon_enable, | 114 | .enable = s3c2410_clkcon_enable, |
120 | .ctrlbit = S3C2410_CLKCON_IIS, | 115 | .ctrlbit = S3C2410_CLKCON_IIS, |
121 | }, { | 116 | }, { |
122 | .name = "spi", | 117 | .name = "spi", |
123 | .id = -1, | ||
124 | .parent = &clk_p, | 118 | .parent = &clk_p, |
125 | .enable = s3c2410_clkcon_enable, | 119 | .enable = s3c2410_clkcon_enable, |
126 | .ctrlbit = S3C2410_CLKCON_SPI, | 120 | .ctrlbit = S3C2410_CLKCON_SPI, |
@@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = { | |||
130 | static struct clk init_clocks[] = { | 124 | static struct clk init_clocks[] = { |
131 | { | 125 | { |
132 | .name = "lcd", | 126 | .name = "lcd", |
133 | .id = -1, | ||
134 | .parent = &clk_h, | 127 | .parent = &clk_h, |
135 | .enable = s3c2410_clkcon_enable, | 128 | .enable = s3c2410_clkcon_enable, |
136 | .ctrlbit = S3C2410_CLKCON_LCDC, | 129 | .ctrlbit = S3C2410_CLKCON_LCDC, |
137 | }, { | 130 | }, { |
138 | .name = "gpio", | 131 | .name = "gpio", |
139 | .id = -1, | ||
140 | .parent = &clk_p, | 132 | .parent = &clk_p, |
141 | .enable = s3c2410_clkcon_enable, | 133 | .enable = s3c2410_clkcon_enable, |
142 | .ctrlbit = S3C2410_CLKCON_GPIO, | 134 | .ctrlbit = S3C2410_CLKCON_GPIO, |
143 | }, { | 135 | }, { |
144 | .name = "usb-host", | 136 | .name = "usb-host", |
145 | .id = -1, | ||
146 | .parent = &clk_h, | 137 | .parent = &clk_h, |
147 | .enable = s3c2410_clkcon_enable, | 138 | .enable = s3c2410_clkcon_enable, |
148 | .ctrlbit = S3C2410_CLKCON_USBH, | 139 | .ctrlbit = S3C2410_CLKCON_USBH, |
149 | }, { | 140 | }, { |
150 | .name = "usb-device", | 141 | .name = "usb-device", |
151 | .id = -1, | ||
152 | .parent = &clk_h, | 142 | .parent = &clk_h, |
153 | .enable = s3c2410_clkcon_enable, | 143 | .enable = s3c2410_clkcon_enable, |
154 | .ctrlbit = S3C2410_CLKCON_USBD, | 144 | .ctrlbit = S3C2410_CLKCON_USBD, |
155 | }, { | 145 | }, { |
156 | .name = "timers", | 146 | .name = "timers", |
157 | .id = -1, | ||
158 | .parent = &clk_p, | 147 | .parent = &clk_p, |
159 | .enable = s3c2410_clkcon_enable, | 148 | .enable = s3c2410_clkcon_enable, |
160 | .ctrlbit = S3C2410_CLKCON_PWMT, | 149 | .ctrlbit = S3C2410_CLKCON_PWMT, |
161 | }, { | 150 | }, { |
162 | .name = "uart", | 151 | .name = "uart", |
163 | .id = 0, | 152 | .devname = "s3c2410-uart.0", |
164 | .parent = &clk_p, | 153 | .parent = &clk_p, |
165 | .enable = s3c2410_clkcon_enable, | 154 | .enable = s3c2410_clkcon_enable, |
166 | .ctrlbit = S3C2410_CLKCON_UART0, | 155 | .ctrlbit = S3C2410_CLKCON_UART0, |
167 | }, { | 156 | }, { |
168 | .name = "uart", | 157 | .name = "uart", |
169 | .id = 1, | 158 | .devname = "s3c2410-uart.1", |
170 | .parent = &clk_p, | 159 | .parent = &clk_p, |
171 | .enable = s3c2410_clkcon_enable, | 160 | .enable = s3c2410_clkcon_enable, |
172 | .ctrlbit = S3C2410_CLKCON_UART1, | 161 | .ctrlbit = S3C2410_CLKCON_UART1, |
173 | }, { | 162 | }, { |
174 | .name = "uart", | 163 | .name = "uart", |
175 | .id = 2, | 164 | .devname = "s3c2410-uart.2", |
176 | .parent = &clk_p, | 165 | .parent = &clk_p, |
177 | .enable = s3c2410_clkcon_enable, | 166 | .enable = s3c2410_clkcon_enable, |
178 | .ctrlbit = S3C2410_CLKCON_UART2, | 167 | .ctrlbit = S3C2410_CLKCON_UART2, |
179 | }, { | 168 | }, { |
180 | .name = "rtc", | 169 | .name = "rtc", |
181 | .id = -1, | ||
182 | .parent = &clk_p, | 170 | .parent = &clk_p, |
183 | .enable = s3c2410_clkcon_enable, | 171 | .enable = s3c2410_clkcon_enable, |
184 | .ctrlbit = S3C2410_CLKCON_RTC, | 172 | .ctrlbit = S3C2410_CLKCON_RTC, |
185 | }, { | 173 | }, { |
186 | .name = "watchdog", | 174 | .name = "watchdog", |
187 | .id = -1, | ||
188 | .parent = &clk_p, | 175 | .parent = &clk_p, |
189 | .ctrlbit = 0, | 176 | .ctrlbit = 0, |
190 | }, { | 177 | }, { |
191 | .name = "usb-bus-host", | 178 | .name = "usb-bus-host", |
192 | .id = -1, | ||
193 | .parent = &clk_usb_bus, | 179 | .parent = &clk_usb_bus, |
194 | }, { | 180 | }, { |
195 | .name = "usb-bus-gadget", | 181 | .name = "usb-bus-gadget", |
196 | .id = -1, | ||
197 | .parent = &clk_usb_bus, | 182 | .parent = &clk_usb_bus, |
198 | }, | 183 | }, |
199 | }; | 184 | }; |
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 82f2d4a39291..59552c0ea5fb 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c | |||
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable) | |||
56 | struct clk clk_mpllref = { | 56 | struct clk clk_mpllref = { |
57 | .name = "mpllref", | 57 | .name = "mpllref", |
58 | .parent = &clk_xtal, | 58 | .parent = &clk_xtal, |
59 | .id = -1, | ||
60 | }; | 59 | }; |
61 | 60 | ||
62 | static struct clk *clk_epllref_sources[] = { | 61 | static struct clk *clk_epllref_sources[] = { |
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = { | |||
69 | struct clksrc_clk clk_epllref = { | 68 | struct clksrc_clk clk_epllref = { |
70 | .clk = { | 69 | .clk = { |
71 | .name = "epllref", | 70 | .name = "epllref", |
72 | .id = -1, | ||
73 | }, | 71 | }, |
74 | .sources = &(struct clksrc_sources) { | 72 | .sources = &(struct clksrc_sources) { |
75 | .sources = clk_epllref_sources, | 73 | .sources = clk_epllref_sources, |
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = { | |||
92 | .clk = { | 90 | .clk = { |
93 | .name = "esysclk", | 91 | .name = "esysclk", |
94 | .parent = &clk_epll, | 92 | .parent = &clk_epll, |
95 | .id = -1, | ||
96 | }, | 93 | }, |
97 | .sources = &(struct clksrc_sources) { | 94 | .sources = &(struct clksrc_sources) { |
98 | .sources = clk_sysclk_sources, | 95 | .sources = clk_sysclk_sources, |
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) | |||
115 | static struct clk clk_mdivclk = { | 112 | static struct clk clk_mdivclk = { |
116 | .name = "mdivclk", | 113 | .name = "mdivclk", |
117 | .parent = &clk_mpllref, | 114 | .parent = &clk_mpllref, |
118 | .id = -1, | ||
119 | .ops = &(struct clk_ops) { | 115 | .ops = &(struct clk_ops) { |
120 | .get_rate = s3c2443_getrate_mdivclk, | 116 | .get_rate = s3c2443_getrate_mdivclk, |
121 | }, | 117 | }, |
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = { | |||
132 | .clk = { | 128 | .clk = { |
133 | .name = "msysclk", | 129 | .name = "msysclk", |
134 | .parent = &clk_xtal, | 130 | .parent = &clk_xtal, |
135 | .id = -1, | ||
136 | }, | 131 | }, |
137 | .sources = &(struct clksrc_sources) { | 132 | .sources = &(struct clksrc_sources) { |
138 | .sources = clk_msysclk_sources, | 133 | .sources = clk_msysclk_sources, |
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk) | |||
159 | 154 | ||
160 | static struct clk clk_prediv = { | 155 | static struct clk clk_prediv = { |
161 | .name = "prediv", | 156 | .name = "prediv", |
162 | .id = -1, | ||
163 | .parent = &clk_msysclk.clk, | 157 | .parent = &clk_msysclk.clk, |
164 | .ops = &(struct clk_ops) { | 158 | .ops = &(struct clk_ops) { |
165 | .get_rate = s3c2443_prediv_getrate, | 159 | .get_rate = s3c2443_prediv_getrate, |
@@ -174,7 +168,6 @@ static struct clk clk_prediv = { | |||
174 | static struct clksrc_clk clk_usb_bus_host = { | 168 | static struct clksrc_clk clk_usb_bus_host = { |
175 | .clk = { | 169 | .clk = { |
176 | .name = "usb-bus-host-parent", | 170 | .name = "usb-bus-host-parent", |
177 | .id = -1, | ||
178 | .parent = &clk_esysclk.clk, | 171 | .parent = &clk_esysclk.clk, |
179 | .ctrlbit = S3C2443_SCLKCON_USBHOST, | 172 | .ctrlbit = S3C2443_SCLKCON_USBHOST, |
180 | .enable = s3c2443_clkcon_enable_s, | 173 | .enable = s3c2443_clkcon_enable_s, |
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = { | |||
189 | /* ART baud-rate clock sourced from esysclk via a divisor */ | 182 | /* ART baud-rate clock sourced from esysclk via a divisor */ |
190 | .clk = { | 183 | .clk = { |
191 | .name = "uartclk", | 184 | .name = "uartclk", |
192 | .id = -1, | ||
193 | .parent = &clk_esysclk.clk, | 185 | .parent = &clk_esysclk.clk, |
194 | }, | 186 | }, |
195 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, | 187 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, |
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = { | |||
197 | /* camera interface bus-clock, divided down from esysclk */ | 189 | /* camera interface bus-clock, divided down from esysclk */ |
198 | .clk = { | 190 | .clk = { |
199 | .name = "camif-upll", /* same as 2440 name */ | 191 | .name = "camif-upll", /* same as 2440 name */ |
200 | .id = -1, | ||
201 | .parent = &clk_esysclk.clk, | 192 | .parent = &clk_esysclk.clk, |
202 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, | 193 | .ctrlbit = S3C2443_SCLKCON_CAMCLK, |
203 | .enable = s3c2443_clkcon_enable_s, | 194 | .enable = s3c2443_clkcon_enable_s, |
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = { | |||
206 | }, { | 197 | }, { |
207 | .clk = { | 198 | .clk = { |
208 | .name = "display-if", | 199 | .name = "display-if", |
209 | .id = -1, | ||
210 | .parent = &clk_esysclk.clk, | 200 | .parent = &clk_esysclk.clk, |
211 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, | 201 | .ctrlbit = S3C2443_SCLKCON_DISPCLK, |
212 | .enable = s3c2443_clkcon_enable_s, | 202 | .enable = s3c2443_clkcon_enable_s, |
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = { | |||
219 | static struct clk init_clocks_off[] = { | 209 | static struct clk init_clocks_off[] = { |
220 | { | 210 | { |
221 | .name = "adc", | 211 | .name = "adc", |
222 | .id = -1, | ||
223 | .parent = &clk_p, | 212 | .parent = &clk_p, |
224 | .enable = s3c2443_clkcon_enable_p, | 213 | .enable = s3c2443_clkcon_enable_p, |
225 | .ctrlbit = S3C2443_PCLKCON_ADC, | 214 | .ctrlbit = S3C2443_PCLKCON_ADC, |
226 | }, { | 215 | }, { |
227 | .name = "i2c", | 216 | .name = "i2c", |
228 | .id = -1, | ||
229 | .parent = &clk_p, | 217 | .parent = &clk_p, |
230 | .enable = s3c2443_clkcon_enable_p, | 218 | .enable = s3c2443_clkcon_enable_p, |
231 | .ctrlbit = S3C2443_PCLKCON_IIC, | 219 | .ctrlbit = S3C2443_PCLKCON_IIC, |
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = { | |||
235 | static struct clk init_clocks[] = { | 223 | static struct clk init_clocks[] = { |
236 | { | 224 | { |
237 | .name = "dma", | 225 | .name = "dma", |
238 | .id = 0, | ||
239 | .parent = &clk_h, | 226 | .parent = &clk_h, |
240 | .enable = s3c2443_clkcon_enable_h, | 227 | .enable = s3c2443_clkcon_enable_h, |
241 | .ctrlbit = S3C2443_HCLKCON_DMA0, | 228 | .ctrlbit = S3C2443_HCLKCON_DMA0, |
242 | }, { | 229 | }, { |
243 | .name = "dma", | 230 | .name = "dma", |
244 | .id = 1, | ||
245 | .parent = &clk_h, | 231 | .parent = &clk_h, |
246 | .enable = s3c2443_clkcon_enable_h, | 232 | .enable = s3c2443_clkcon_enable_h, |
247 | .ctrlbit = S3C2443_HCLKCON_DMA1, | 233 | .ctrlbit = S3C2443_HCLKCON_DMA1, |
248 | }, { | 234 | }, { |
249 | .name = "dma", | 235 | .name = "dma", |
250 | .id = 2, | ||
251 | .parent = &clk_h, | 236 | .parent = &clk_h, |
252 | .enable = s3c2443_clkcon_enable_h, | 237 | .enable = s3c2443_clkcon_enable_h, |
253 | .ctrlbit = S3C2443_HCLKCON_DMA2, | 238 | .ctrlbit = S3C2443_HCLKCON_DMA2, |
254 | }, { | 239 | }, { |
255 | .name = "dma", | 240 | .name = "dma", |
256 | .id = 3, | ||
257 | .parent = &clk_h, | 241 | .parent = &clk_h, |
258 | .enable = s3c2443_clkcon_enable_h, | 242 | .enable = s3c2443_clkcon_enable_h, |
259 | .ctrlbit = S3C2443_HCLKCON_DMA3, | 243 | .ctrlbit = S3C2443_HCLKCON_DMA3, |
260 | }, { | 244 | }, { |
261 | .name = "dma", | 245 | .name = "dma", |
262 | .id = 4, | ||
263 | .parent = &clk_h, | 246 | .parent = &clk_h, |
264 | .enable = s3c2443_clkcon_enable_h, | 247 | .enable = s3c2443_clkcon_enable_h, |
265 | .ctrlbit = S3C2443_HCLKCON_DMA4, | 248 | .ctrlbit = S3C2443_HCLKCON_DMA4, |
266 | }, { | 249 | }, { |
267 | .name = "dma", | 250 | .name = "dma", |
268 | .id = 5, | ||
269 | .parent = &clk_h, | 251 | .parent = &clk_h, |
270 | .enable = s3c2443_clkcon_enable_h, | 252 | .enable = s3c2443_clkcon_enable_h, |
271 | .ctrlbit = S3C2443_HCLKCON_DMA5, | 253 | .ctrlbit = S3C2443_HCLKCON_DMA5, |
272 | }, { | 254 | }, { |
273 | .name = "hsmmc", | 255 | .name = "hsmmc", |
274 | .id = 1, | ||
275 | .parent = &clk_h, | 256 | .parent = &clk_h, |
276 | .enable = s3c2443_clkcon_enable_h, | 257 | .enable = s3c2443_clkcon_enable_h, |
277 | .ctrlbit = S3C2443_HCLKCON_HSMMC, | 258 | .ctrlbit = S3C2443_HCLKCON_HSMMC, |
278 | }, { | 259 | }, { |
279 | .name = "gpio", | 260 | .name = "gpio", |
280 | .id = -1, | ||
281 | .parent = &clk_p, | 261 | .parent = &clk_p, |
282 | .enable = s3c2443_clkcon_enable_p, | 262 | .enable = s3c2443_clkcon_enable_p, |
283 | .ctrlbit = S3C2443_PCLKCON_GPIO, | 263 | .ctrlbit = S3C2443_PCLKCON_GPIO, |
284 | }, { | 264 | }, { |
285 | .name = "usb-host", | 265 | .name = "usb-host", |
286 | .id = -1, | ||
287 | .parent = &clk_h, | 266 | .parent = &clk_h, |
288 | .enable = s3c2443_clkcon_enable_h, | 267 | .enable = s3c2443_clkcon_enable_h, |
289 | .ctrlbit = S3C2443_HCLKCON_USBH, | 268 | .ctrlbit = S3C2443_HCLKCON_USBH, |
290 | }, { | 269 | }, { |
291 | .name = "usb-device", | 270 | .name = "usb-device", |
292 | .id = -1, | ||
293 | .parent = &clk_h, | 271 | .parent = &clk_h, |
294 | .enable = s3c2443_clkcon_enable_h, | 272 | .enable = s3c2443_clkcon_enable_h, |
295 | .ctrlbit = S3C2443_HCLKCON_USBD, | 273 | .ctrlbit = S3C2443_HCLKCON_USBD, |
296 | }, { | 274 | }, { |
297 | .name = "lcd", | 275 | .name = "lcd", |
298 | .id = -1, | ||
299 | .parent = &clk_h, | 276 | .parent = &clk_h, |
300 | .enable = s3c2443_clkcon_enable_h, | 277 | .enable = s3c2443_clkcon_enable_h, |
301 | .ctrlbit = S3C2443_HCLKCON_LCDC, | 278 | .ctrlbit = S3C2443_HCLKCON_LCDC, |
302 | 279 | ||
303 | }, { | 280 | }, { |
304 | .name = "timers", | 281 | .name = "timers", |
305 | .id = -1, | ||
306 | .parent = &clk_p, | 282 | .parent = &clk_p, |
307 | .enable = s3c2443_clkcon_enable_p, | 283 | .enable = s3c2443_clkcon_enable_p, |
308 | .ctrlbit = S3C2443_PCLKCON_PWMT, | 284 | .ctrlbit = S3C2443_PCLKCON_PWMT, |
309 | }, { | 285 | }, { |
310 | .name = "cfc", | 286 | .name = "cfc", |
311 | .id = -1, | ||
312 | .parent = &clk_h, | 287 | .parent = &clk_h, |
313 | .enable = s3c2443_clkcon_enable_h, | 288 | .enable = s3c2443_clkcon_enable_h, |
314 | .ctrlbit = S3C2443_HCLKCON_CFC, | 289 | .ctrlbit = S3C2443_HCLKCON_CFC, |
315 | }, { | 290 | }, { |
316 | .name = "ssmc", | 291 | .name = "ssmc", |
317 | .id = -1, | ||
318 | .parent = &clk_h, | 292 | .parent = &clk_h, |
319 | .enable = s3c2443_clkcon_enable_h, | 293 | .enable = s3c2443_clkcon_enable_h, |
320 | .ctrlbit = S3C2443_HCLKCON_SSMC, | 294 | .ctrlbit = S3C2443_HCLKCON_SSMC, |
321 | }, { | 295 | }, { |
322 | .name = "uart", | 296 | .name = "uart", |
323 | .id = 0, | 297 | .devname = "s3c2440-uart.0", |
324 | .parent = &clk_p, | 298 | .parent = &clk_p, |
325 | .enable = s3c2443_clkcon_enable_p, | 299 | .enable = s3c2443_clkcon_enable_p, |
326 | .ctrlbit = S3C2443_PCLKCON_UART0, | 300 | .ctrlbit = S3C2443_PCLKCON_UART0, |
327 | }, { | 301 | }, { |
328 | .name = "uart", | 302 | .name = "uart", |
329 | .id = 1, | 303 | .devname = "s3c2440-uart.1", |
330 | .parent = &clk_p, | 304 | .parent = &clk_p, |
331 | .enable = s3c2443_clkcon_enable_p, | 305 | .enable = s3c2443_clkcon_enable_p, |
332 | .ctrlbit = S3C2443_PCLKCON_UART1, | 306 | .ctrlbit = S3C2443_PCLKCON_UART1, |
333 | }, { | 307 | }, { |
334 | .name = "uart", | 308 | .name = "uart", |
335 | .id = 2, | 309 | .devname = "s3c2440-uart.2", |
336 | .parent = &clk_p, | 310 | .parent = &clk_p, |
337 | .enable = s3c2443_clkcon_enable_p, | 311 | .enable = s3c2443_clkcon_enable_p, |
338 | .ctrlbit = S3C2443_PCLKCON_UART2, | 312 | .ctrlbit = S3C2443_PCLKCON_UART2, |
339 | }, { | 313 | }, { |
340 | .name = "uart", | 314 | .name = "uart", |
341 | .id = 3, | 315 | .devname = "s3c2440-uart.3", |
342 | .parent = &clk_p, | 316 | .parent = &clk_p, |
343 | .enable = s3c2443_clkcon_enable_p, | 317 | .enable = s3c2443_clkcon_enable_p, |
344 | .ctrlbit = S3C2443_PCLKCON_UART3, | 318 | .ctrlbit = S3C2443_PCLKCON_UART3, |
345 | }, { | 319 | }, { |
346 | .name = "rtc", | 320 | .name = "rtc", |
347 | .id = -1, | ||
348 | .parent = &clk_p, | 321 | .parent = &clk_p, |
349 | .enable = s3c2443_clkcon_enable_p, | 322 | .enable = s3c2443_clkcon_enable_p, |
350 | .ctrlbit = S3C2443_PCLKCON_RTC, | 323 | .ctrlbit = S3C2443_PCLKCON_RTC, |
351 | }, { | 324 | }, { |
352 | .name = "watchdog", | 325 | .name = "watchdog", |
353 | .id = -1, | ||
354 | .parent = &clk_p, | 326 | .parent = &clk_p, |
355 | .ctrlbit = S3C2443_PCLKCON_WDT, | 327 | .ctrlbit = S3C2443_PCLKCON_WDT, |
356 | }, { | 328 | }, { |
357 | .name = "ac97", | 329 | .name = "ac97", |
358 | .id = -1, | ||
359 | .parent = &clk_p, | 330 | .parent = &clk_p, |
360 | .ctrlbit = S3C2443_PCLKCON_AC97, | 331 | .ctrlbit = S3C2443_PCLKCON_AC97, |
361 | }, { | 332 | }, { |
362 | .name = "nand", | 333 | .name = "nand", |
363 | .id = -1, | ||
364 | .parent = &clk_h, | 334 | .parent = &clk_h, |
365 | }, { | 335 | }, { |
366 | .name = "usb-bus-host", | 336 | .name = "usb-bus-host", |
367 | .id = -1, | ||
368 | .parent = &clk_usb_bus_host.clk, | 337 | .parent = &clk_usb_bus_host.clk, |
369 | } | 338 | } |
370 | }; | 339 | }; |
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 8d081d968c58..02af235298e2 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c | |||
@@ -168,6 +168,41 @@ unsigned long s5p_epll_get_rate(struct clk *clk) | |||
168 | return clk->rate; | 168 | return clk->rate; |
169 | } | 169 | } |
170 | 170 | ||
171 | int s5p_spdif_set_rate(struct clk *clk, unsigned long rate) | ||
172 | { | ||
173 | struct clk *pclk; | ||
174 | int ret; | ||
175 | |||
176 | pclk = clk_get_parent(clk); | ||
177 | if (IS_ERR(pclk)) | ||
178 | return -EINVAL; | ||
179 | |||
180 | ret = pclk->ops->set_rate(pclk, rate); | ||
181 | clk_put(pclk); | ||
182 | |||
183 | return ret; | ||
184 | } | ||
185 | |||
186 | unsigned long s5p_spdif_get_rate(struct clk *clk) | ||
187 | { | ||
188 | struct clk *pclk; | ||
189 | int rate; | ||
190 | |||
191 | pclk = clk_get_parent(clk); | ||
192 | if (IS_ERR(pclk)) | ||
193 | return -EINVAL; | ||
194 | |||
195 | rate = pclk->ops->get_rate(clk); | ||
196 | clk_put(pclk); | ||
197 | |||
198 | return rate; | ||
199 | } | ||
200 | |||
201 | struct clk_ops s5p_sclk_spdif_ops = { | ||
202 | .set_rate = s5p_spdif_set_rate, | ||
203 | .get_rate = s5p_spdif_get_rate, | ||
204 | }; | ||
205 | |||
171 | static struct clk *s5p_clks[] __initdata = { | 206 | static struct clk *s5p_clks[] __initdata = { |
172 | &clk_ext_xtal_mux, | 207 | &clk_ext_xtal_mux, |
173 | &clk_48m, | 208 | &clk_48m, |
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h index 2b6dcff8ab2b..769b5bdfb046 100644 --- a/arch/arm/plat-s5p/include/plat/s5p-clock.h +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h | |||
@@ -47,4 +47,9 @@ extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); | |||
47 | extern int s5p_epll_enable(struct clk *clk, int enable); | 47 | extern int s5p_epll_enable(struct clk *clk, int enable); |
48 | extern unsigned long s5p_epll_get_rate(struct clk *clk); | 48 | extern unsigned long s5p_epll_get_rate(struct clk *clk); |
49 | 49 | ||
50 | /* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */ | ||
51 | extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate); | ||
52 | extern unsigned long s5p_spdif_get_rate(struct clk *clk); | ||
53 | |||
54 | extern struct clk_ops s5p_sclk_spdif_ops; | ||
50 | #endif /* __ASM_PLAT_S5P_CLOCK_H */ | 55 | #endif /* __ASM_PLAT_S5P_CLOCK_H */ |
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c index 899a8cc011ff..c833e7b57599 100644 --- a/arch/arm/plat-s5p/s5p-time.c +++ b/arch/arm/plat-s5p/s5p-time.c | |||
@@ -314,13 +314,6 @@ static void __iomem *s5p_timer_reg(void) | |||
314 | return S3C_TIMERREG(offset); | 314 | return S3C_TIMERREG(offset); |
315 | } | 315 | } |
316 | 316 | ||
317 | static cycle_t s5p_timer_read(struct clocksource *cs) | ||
318 | { | ||
319 | void __iomem *reg = s5p_timer_reg(); | ||
320 | |||
321 | return (cycle_t) (reg ? ~__raw_readl(reg) : 0); | ||
322 | } | ||
323 | |||
324 | /* | 317 | /* |
325 | * Override the global weak sched_clock symbol with this | 318 | * Override the global weak sched_clock symbol with this |
326 | * local implementation which uses the clocksource to get some | 319 | * local implementation which uses the clocksource to get some |
@@ -350,14 +343,6 @@ static void notrace s5p_update_sched_clock(void) | |||
350 | update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0); | 343 | update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0); |
351 | } | 344 | } |
352 | 345 | ||
353 | struct clocksource time_clocksource = { | ||
354 | .name = "s5p_clocksource_timer", | ||
355 | .rating = 250, | ||
356 | .read = s5p_timer_read, | ||
357 | .mask = CLOCKSOURCE_MASK(32), | ||
358 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
359 | }; | ||
360 | |||
361 | static void __init s5p_clocksource_init(void) | 346 | static void __init s5p_clocksource_init(void) |
362 | { | 347 | { |
363 | unsigned long pclk; | 348 | unsigned long pclk; |
@@ -370,13 +355,14 @@ static void __init s5p_clocksource_init(void) | |||
370 | 355 | ||
371 | clock_rate = clk_get_rate(tin_source); | 356 | clock_rate = clk_get_rate(tin_source); |
372 | 357 | ||
373 | init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate); | ||
374 | |||
375 | s5p_time_setup(timer_source.source_id, TCNT_MAX); | 358 | s5p_time_setup(timer_source.source_id, TCNT_MAX); |
376 | s5p_time_start(timer_source.source_id, PERIODIC); | 359 | s5p_time_start(timer_source.source_id, PERIODIC); |
377 | 360 | ||
378 | if (clocksource_register_hz(&time_clocksource, clock_rate)) | 361 | init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate); |
379 | panic("%s: can't register clocksource\n", time_clocksource.name); | 362 | |
363 | if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer", | ||
364 | clock_rate, 250, 32, clocksource_mmio_readl_down)) | ||
365 | panic("s5p_clocksource_timer: can't register clocksource\n"); | ||
380 | } | 366 | } |
381 | 367 | ||
382 | static void __init s5p_timer_resources(void) | 368 | static void __init s5p_timer_resources(void) |
@@ -384,6 +370,7 @@ static void __init s5p_timer_resources(void) | |||
384 | 370 | ||
385 | unsigned long event_id = timer_source.event_id; | 371 | unsigned long event_id = timer_source.event_id; |
386 | unsigned long source_id = timer_source.source_id; | 372 | unsigned long source_id = timer_source.source_id; |
373 | char devname[15]; | ||
387 | 374 | ||
388 | timerclk = clk_get(NULL, "timers"); | 375 | timerclk = clk_get(NULL, "timers"); |
389 | if (IS_ERR(timerclk)) | 376 | if (IS_ERR(timerclk)) |
@@ -391,6 +378,10 @@ static void __init s5p_timer_resources(void) | |||
391 | 378 | ||
392 | clk_enable(timerclk); | 379 | clk_enable(timerclk); |
393 | 380 | ||
381 | sprintf(devname, "s3c24xx-pwm.%lu", event_id); | ||
382 | s3c_device_timer[event_id].id = event_id; | ||
383 | s3c_device_timer[event_id].dev.init_name = devname; | ||
384 | |||
394 | tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); | 385 | tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); |
395 | if (IS_ERR(tin_event)) | 386 | if (IS_ERR(tin_event)) |
396 | panic("failed to get pwm-tin clock for event timer"); | 387 | panic("failed to get pwm-tin clock for event timer"); |
@@ -401,6 +392,10 @@ static void __init s5p_timer_resources(void) | |||
401 | 392 | ||
402 | clk_enable(tin_event); | 393 | clk_enable(tin_event); |
403 | 394 | ||
395 | sprintf(devname, "s3c24xx-pwm.%lu", source_id); | ||
396 | s3c_device_timer[source_id].id = source_id; | ||
397 | s3c_device_timer[source_id].dev.init_name = devname; | ||
398 | |||
404 | tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); | 399 | tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); |
405 | if (IS_ERR(tin_source)) | 400 | if (IS_ERR(tin_source)) |
406 | panic("failed to get pwm-tin clock for source timer"); | 401 | panic("failed to get pwm-tin clock for source timer"); |
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 4d79519d19a4..b3e10659e4b8 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
@@ -280,6 +280,12 @@ config SAMSUNG_DEV_PWM | |||
280 | help | 280 | help |
281 | Compile in platform device definition for PWM Timer | 281 | Compile in platform device definition for PWM Timer |
282 | 282 | ||
283 | config SAMSUNG_DEV_BACKLIGHT | ||
284 | bool | ||
285 | depends on SAMSUNG_DEV_PWM | ||
286 | help | ||
287 | Compile in platform device definition LCD backlight with PWM Timer | ||
288 | |||
283 | config S3C24XX_PWM | 289 | config S3C24XX_PWM |
284 | bool "PWM device support" | 290 | bool "PWM device support" |
285 | select HAVE_PWM | 291 | select HAVE_PWM |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 53eb15b0a07d..853764ba8cc5 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
@@ -59,6 +59,7 @@ obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o | |||
59 | obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o | 59 | obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o |
60 | obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o | 60 | obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o |
61 | obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o | 61 | obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o |
62 | obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o | ||
62 | 63 | ||
63 | # DMA support | 64 | # DMA support |
64 | 65 | ||
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 772892826ffc..aecf9e90d4fc 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c | |||
@@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable) | |||
71 | return 0; | 71 | return 0; |
72 | } | 72 | } |
73 | 73 | ||
74 | static int dev_is_s3c_uart(struct device *dev) | ||
75 | { | ||
76 | struct platform_device **pdev = s3c24xx_uart_devs; | ||
77 | int i; | ||
78 | for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++) | ||
79 | if (*pdev && dev == &(*pdev)->dev) | ||
80 | return 1; | ||
81 | return 0; | ||
82 | } | ||
83 | |||
84 | /* | ||
85 | * Serial drivers call get_clock() very early, before platform bus | ||
86 | * has been set up, this requires a special check to let them get | ||
87 | * a proper clock | ||
88 | */ | ||
89 | |||
90 | static int dev_is_platform_device(struct device *dev) | ||
91 | { | ||
92 | return dev->bus == &platform_bus_type || | ||
93 | (dev->bus == NULL && dev_is_s3c_uart(dev)); | ||
94 | } | ||
95 | |||
96 | /* Clock API calls */ | ||
97 | |||
98 | struct clk *clk_get(struct device *dev, const char *id) | ||
99 | { | ||
100 | struct clk *p; | ||
101 | struct clk *clk = ERR_PTR(-ENOENT); | ||
102 | int idno; | ||
103 | |||
104 | if (dev == NULL || !dev_is_platform_device(dev)) | ||
105 | idno = -1; | ||
106 | else | ||
107 | idno = to_platform_device(dev)->id; | ||
108 | |||
109 | spin_lock(&clocks_lock); | ||
110 | |||
111 | list_for_each_entry(p, &clocks, list) { | ||
112 | if (p->id == idno && | ||
113 | strcmp(id, p->name) == 0 && | ||
114 | try_module_get(p->owner)) { | ||
115 | clk = p; | ||
116 | break; | ||
117 | } | ||
118 | } | ||
119 | |||
120 | /* check for the case where a device was supplied, but the | ||
121 | * clock that was being searched for is not device specific */ | ||
122 | |||
123 | if (IS_ERR(clk)) { | ||
124 | list_for_each_entry(p, &clocks, list) { | ||
125 | if (p->id == -1 && strcmp(id, p->name) == 0 && | ||
126 | try_module_get(p->owner)) { | ||
127 | clk = p; | ||
128 | break; | ||
129 | } | ||
130 | } | ||
131 | } | ||
132 | |||
133 | spin_unlock(&clocks_lock); | ||
134 | return clk; | ||
135 | } | ||
136 | |||
137 | void clk_put(struct clk *clk) | ||
138 | { | ||
139 | module_put(clk->owner); | ||
140 | } | ||
141 | |||
142 | int clk_enable(struct clk *clk) | 74 | int clk_enable(struct clk *clk) |
143 | { | 75 | { |
144 | if (IS_ERR(clk) || clk == NULL) | 76 | if (IS_ERR(clk) || clk == NULL) |
@@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent) | |||
241 | return ret; | 173 | return ret; |
242 | } | 174 | } |
243 | 175 | ||
244 | EXPORT_SYMBOL(clk_get); | ||
245 | EXPORT_SYMBOL(clk_put); | ||
246 | EXPORT_SYMBOL(clk_enable); | 176 | EXPORT_SYMBOL(clk_enable); |
247 | EXPORT_SYMBOL(clk_disable); | 177 | EXPORT_SYMBOL(clk_disable); |
248 | EXPORT_SYMBOL(clk_get_rate); | 178 | EXPORT_SYMBOL(clk_get_rate); |
@@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = { | |||
265 | 195 | ||
266 | struct clk clk_xtal = { | 196 | struct clk clk_xtal = { |
267 | .name = "xtal", | 197 | .name = "xtal", |
268 | .id = -1, | ||
269 | .rate = 0, | 198 | .rate = 0, |
270 | .parent = NULL, | 199 | .parent = NULL, |
271 | .ctrlbit = 0, | 200 | .ctrlbit = 0, |
@@ -273,30 +202,25 @@ struct clk clk_xtal = { | |||
273 | 202 | ||
274 | struct clk clk_ext = { | 203 | struct clk clk_ext = { |
275 | .name = "ext", | 204 | .name = "ext", |
276 | .id = -1, | ||
277 | }; | 205 | }; |
278 | 206 | ||
279 | struct clk clk_epll = { | 207 | struct clk clk_epll = { |
280 | .name = "epll", | 208 | .name = "epll", |
281 | .id = -1, | ||
282 | }; | 209 | }; |
283 | 210 | ||
284 | struct clk clk_mpll = { | 211 | struct clk clk_mpll = { |
285 | .name = "mpll", | 212 | .name = "mpll", |
286 | .id = -1, | ||
287 | .ops = &clk_ops_def_setrate, | 213 | .ops = &clk_ops_def_setrate, |
288 | }; | 214 | }; |
289 | 215 | ||
290 | struct clk clk_upll = { | 216 | struct clk clk_upll = { |
291 | .name = "upll", | 217 | .name = "upll", |
292 | .id = -1, | ||
293 | .parent = NULL, | 218 | .parent = NULL, |
294 | .ctrlbit = 0, | 219 | .ctrlbit = 0, |
295 | }; | 220 | }; |
296 | 221 | ||
297 | struct clk clk_f = { | 222 | struct clk clk_f = { |
298 | .name = "fclk", | 223 | .name = "fclk", |
299 | .id = -1, | ||
300 | .rate = 0, | 224 | .rate = 0, |
301 | .parent = &clk_mpll, | 225 | .parent = &clk_mpll, |
302 | .ctrlbit = 0, | 226 | .ctrlbit = 0, |
@@ -304,7 +228,6 @@ struct clk clk_f = { | |||
304 | 228 | ||
305 | struct clk clk_h = { | 229 | struct clk clk_h = { |
306 | .name = "hclk", | 230 | .name = "hclk", |
307 | .id = -1, | ||
308 | .rate = 0, | 231 | .rate = 0, |
309 | .parent = NULL, | 232 | .parent = NULL, |
310 | .ctrlbit = 0, | 233 | .ctrlbit = 0, |
@@ -313,7 +236,6 @@ struct clk clk_h = { | |||
313 | 236 | ||
314 | struct clk clk_p = { | 237 | struct clk clk_p = { |
315 | .name = "pclk", | 238 | .name = "pclk", |
316 | .id = -1, | ||
317 | .rate = 0, | 239 | .rate = 0, |
318 | .parent = NULL, | 240 | .parent = NULL, |
319 | .ctrlbit = 0, | 241 | .ctrlbit = 0, |
@@ -322,7 +244,6 @@ struct clk clk_p = { | |||
322 | 244 | ||
323 | struct clk clk_usb_bus = { | 245 | struct clk clk_usb_bus = { |
324 | .name = "usb-bus", | 246 | .name = "usb-bus", |
325 | .id = -1, | ||
326 | .rate = 0, | 247 | .rate = 0, |
327 | .parent = &clk_upll, | 248 | .parent = &clk_upll, |
328 | }; | 249 | }; |
@@ -330,7 +251,6 @@ struct clk clk_usb_bus = { | |||
330 | 251 | ||
331 | struct clk s3c24xx_uclk = { | 252 | struct clk s3c24xx_uclk = { |
332 | .name = "uclk", | 253 | .name = "uclk", |
333 | .id = -1, | ||
334 | }; | 254 | }; |
335 | 255 | ||
336 | /* initialise the clock system */ | 256 | /* initialise the clock system */ |
@@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk) | |||
346 | if (clk->enable == NULL) | 266 | if (clk->enable == NULL) |
347 | clk->enable = clk_null_enable; | 267 | clk->enable = clk_null_enable; |
348 | 268 | ||
349 | /* add to the list of available clocks */ | 269 | /* fill up the clk_lookup structure and register it*/ |
350 | 270 | clk->lookup.dev_id = clk->devname; | |
351 | /* Quick check to see if this clock has already been registered. */ | 271 | clk->lookup.con_id = clk->name; |
352 | BUG_ON(clk->list.prev != clk->list.next); | 272 | clk->lookup.clk = clk; |
353 | 273 | clkdev_add(&clk->lookup); | |
354 | spin_lock(&clocks_lock); | ||
355 | list_add(&clk->list, &clocks); | ||
356 | spin_unlock(&clocks_lock); | ||
357 | 274 | ||
358 | return 0; | 275 | return 0; |
359 | } | 276 | } |
@@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c) | |||
463 | char s[255]; | 380 | char s[255]; |
464 | char *p = s; | 381 | char *p = s; |
465 | 382 | ||
466 | p += sprintf(p, "%s", c->name); | 383 | p += sprintf(p, "%s", c->devname); |
467 | |||
468 | if (c->id >= 0) | ||
469 | sprintf(p, ":%d", c->id); | ||
470 | 384 | ||
471 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); | 385 | d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); |
472 | if (!d) | 386 | if (!d) |
diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c new file mode 100644 index 000000000000..3cedd4c407af --- /dev/null +++ b/arch/arm/plat-samsung/dev-backlight.c | |||
@@ -0,0 +1,149 @@ | |||
1 | /* linux/arch/arm/plat-samsung/dev-backlight.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Common infrastructure for PWM Backlight for Samsung boards | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/gpio.h> | ||
14 | #include <linux/platform_device.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/pwm_backlight.h> | ||
17 | |||
18 | #include <plat/devs.h> | ||
19 | #include <plat/gpio-cfg.h> | ||
20 | #include <plat/backlight.h> | ||
21 | |||
22 | static int samsung_bl_init(struct device *dev) | ||
23 | { | ||
24 | int ret = 0; | ||
25 | struct platform_device *timer_dev = | ||
26 | container_of(dev->parent, struct platform_device, dev); | ||
27 | struct samsung_bl_gpio_info *bl_gpio_info = | ||
28 | timer_dev->dev.platform_data; | ||
29 | |||
30 | ret = gpio_request(bl_gpio_info->no, "Backlight"); | ||
31 | if (ret) { | ||
32 | printk(KERN_ERR "failed to request GPIO for LCD Backlight\n"); | ||
33 | return ret; | ||
34 | } | ||
35 | |||
36 | /* Configure GPIO pin with specific GPIO function for PWM timer */ | ||
37 | s3c_gpio_cfgpin(bl_gpio_info->no, bl_gpio_info->func); | ||
38 | |||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | static void samsung_bl_exit(struct device *dev) | ||
43 | { | ||
44 | struct platform_device *timer_dev = | ||
45 | container_of(dev->parent, struct platform_device, dev); | ||
46 | struct samsung_bl_gpio_info *bl_gpio_info = | ||
47 | timer_dev->dev.platform_data; | ||
48 | |||
49 | s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT); | ||
50 | gpio_free(bl_gpio_info->no); | ||
51 | } | ||
52 | |||
53 | /* Initialize few important fields of platform_pwm_backlight_data | ||
54 | * structure with default values. These fields can be overridden by | ||
55 | * board-specific values sent from machine file. | ||
56 | * For ease of operation, these fields are initialized with values | ||
57 | * used by most samsung boards. | ||
58 | * Users has the option of sending info about other parameters | ||
59 | * for their specific boards | ||
60 | */ | ||
61 | |||
62 | static struct platform_pwm_backlight_data samsung_dfl_bl_data __initdata = { | ||
63 | .max_brightness = 255, | ||
64 | .dft_brightness = 255, | ||
65 | .pwm_period_ns = 78770, | ||
66 | .init = samsung_bl_init, | ||
67 | .exit = samsung_bl_exit, | ||
68 | }; | ||
69 | |||
70 | static struct platform_device samsung_dfl_bl_device __initdata = { | ||
71 | .name = "pwm-backlight", | ||
72 | }; | ||
73 | |||
74 | /* samsung_bl_set - Set board specific data (if any) provided by user for | ||
75 | * PWM Backlight control and register specific PWM and backlight device. | ||
76 | * @gpio_info: structure containing GPIO info for PWM timer | ||
77 | * @bl_data: structure containing Backlight control data | ||
78 | */ | ||
79 | void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, | ||
80 | struct platform_pwm_backlight_data *bl_data) | ||
81 | { | ||
82 | int ret = 0; | ||
83 | struct platform_device *samsung_bl_device; | ||
84 | struct platform_pwm_backlight_data *samsung_bl_data; | ||
85 | |||
86 | samsung_bl_device = kmemdup(&samsung_dfl_bl_device, | ||
87 | sizeof(struct platform_device), GFP_KERNEL); | ||
88 | if (!samsung_bl_device) { | ||
89 | printk(KERN_ERR "%s: no memory for platform dev\n", __func__); | ||
90 | return; | ||
91 | } | ||
92 | |||
93 | samsung_bl_data = s3c_set_platdata(&samsung_dfl_bl_data, | ||
94 | sizeof(struct platform_pwm_backlight_data), samsung_bl_device); | ||
95 | if (!samsung_bl_data) { | ||
96 | printk(KERN_ERR "%s: no memory for platform dev\n", __func__); | ||
97 | goto err_data; | ||
98 | } | ||
99 | |||
100 | /* Copy board specific data provided by user */ | ||
101 | samsung_bl_data->pwm_id = bl_data->pwm_id; | ||
102 | samsung_bl_device->dev.parent = | ||
103 | &s3c_device_timer[samsung_bl_data->pwm_id].dev; | ||
104 | |||
105 | if (bl_data->max_brightness) | ||
106 | samsung_bl_data->max_brightness = bl_data->max_brightness; | ||
107 | if (bl_data->dft_brightness) | ||
108 | samsung_bl_data->dft_brightness = bl_data->dft_brightness; | ||
109 | if (bl_data->lth_brightness) | ||
110 | samsung_bl_data->lth_brightness = bl_data->lth_brightness; | ||
111 | if (bl_data->pwm_period_ns) | ||
112 | samsung_bl_data->pwm_period_ns = bl_data->pwm_period_ns; | ||
113 | if (bl_data->init) | ||
114 | samsung_bl_data->init = bl_data->init; | ||
115 | if (bl_data->notify) | ||
116 | samsung_bl_data->notify = bl_data->notify; | ||
117 | if (bl_data->exit) | ||
118 | samsung_bl_data->exit = bl_data->exit; | ||
119 | if (bl_data->check_fb) | ||
120 | samsung_bl_data->check_fb = bl_data->check_fb; | ||
121 | |||
122 | /* Keep the GPIO info for future use */ | ||
123 | s3c_device_timer[samsung_bl_data->pwm_id].dev.platform_data = gpio_info; | ||
124 | |||
125 | /* Register the specific PWM timer dev for Backlight control */ | ||
126 | ret = platform_device_register( | ||
127 | &s3c_device_timer[samsung_bl_data->pwm_id]); | ||
128 | if (ret) { | ||
129 | printk(KERN_ERR "failed to register pwm timer for backlight: %d\n", ret); | ||
130 | goto err_plat_reg1; | ||
131 | } | ||
132 | |||
133 | /* Register the Backlight dev */ | ||
134 | ret = platform_device_register(samsung_bl_device); | ||
135 | if (ret) { | ||
136 | printk(KERN_ERR "failed to register backlight device: %d\n", ret); | ||
137 | goto err_plat_reg2; | ||
138 | } | ||
139 | |||
140 | return; | ||
141 | |||
142 | err_plat_reg2: | ||
143 | platform_device_unregister(&s3c_device_timer[samsung_bl_data->pwm_id]); | ||
144 | err_plat_reg1: | ||
145 | kfree(samsung_bl_data); | ||
146 | err_data: | ||
147 | kfree(samsung_bl_device); | ||
148 | return; | ||
149 | } | ||
diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c index bf60204c6297..49a1362fd25b 100644 --- a/arch/arm/plat-samsung/dev-fb.c +++ b/arch/arm/plat-samsung/dev-fb.c | |||
@@ -58,16 +58,6 @@ struct platform_device s3c_device_fb = { | |||
58 | 58 | ||
59 | void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) | 59 | void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) |
60 | { | 60 | { |
61 | struct s3c_fb_platdata *npd; | 61 | s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), |
62 | 62 | &s3c_device_fb); | |
63 | if (!pd) { | ||
64 | printk(KERN_ERR "%s: no platform data\n", __func__); | ||
65 | return; | ||
66 | } | ||
67 | |||
68 | npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL); | ||
69 | if (!npd) | ||
70 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
71 | |||
72 | s3c_device_fb.dev.platform_data = npd; | ||
73 | } | 63 | } |
diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c index b3ffb9587250..c91a79ce8f39 100644 --- a/arch/arm/plat-samsung/dev-hwmon.c +++ b/arch/arm/plat-samsung/dev-hwmon.c | |||
@@ -27,16 +27,6 @@ struct platform_device s3c_device_hwmon = { | |||
27 | 27 | ||
28 | void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) | 28 | void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) |
29 | { | 29 | { |
30 | struct s3c_hwmon_pdata *npd; | 30 | s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata), |
31 | 31 | &s3c_device_hwmon); | |
32 | if (!pd) { | ||
33 | printk(KERN_ERR "%s: no platform data\n", __func__); | ||
34 | return; | ||
35 | } | ||
36 | |||
37 | npd = kmemdup(pd, sizeof(struct s3c_hwmon_pdata), GFP_KERNEL); | ||
38 | if (!npd) | ||
39 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
40 | |||
41 | s3c_device_hwmon.dev.platform_data = npd; | ||
42 | } | 32 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c index 3a601c16f03c..f8251f5098bd 100644 --- a/arch/arm/plat-samsung/dev-i2c0.c +++ b/arch/arm/plat-samsung/dev-i2c0.c | |||
@@ -48,7 +48,7 @@ struct platform_device s3c_device_i2c0 = { | |||
48 | .resource = s3c_i2c_resource, | 48 | .resource = s3c_i2c_resource, |
49 | }; | 49 | }; |
50 | 50 | ||
51 | static struct s3c2410_platform_i2c default_i2c_data0 __initdata = { | 51 | struct s3c2410_platform_i2c default_i2c_data __initdata = { |
52 | .flags = 0, | 52 | .flags = 0, |
53 | .slave_addr = 0x10, | 53 | .slave_addr = 0x10, |
54 | .frequency = 100*1000, | 54 | .frequency = 100*1000, |
@@ -60,13 +60,11 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) | |||
60 | struct s3c2410_platform_i2c *npd; | 60 | struct s3c2410_platform_i2c *npd; |
61 | 61 | ||
62 | if (!pd) | 62 | if (!pd) |
63 | pd = &default_i2c_data0; | 63 | pd = &default_i2c_data; |
64 | 64 | ||
65 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 65 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
66 | if (!npd) | 66 | &s3c_device_i2c0); |
67 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
68 | else if (!npd->cfg_gpio) | ||
69 | npd->cfg_gpio = s3c_i2c0_cfg_gpio; | ||
70 | 67 | ||
71 | s3c_device_i2c0.dev.platform_data = npd; | 68 | if (!npd->cfg_gpio) |
69 | npd->cfg_gpio = s3c_i2c0_cfg_gpio; | ||
72 | } | 70 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c index 858ee2a0414c..3b7c7bec1cf9 100644 --- a/arch/arm/plat-samsung/dev-i2c1.c +++ b/arch/arm/plat-samsung/dev-i2c1.c | |||
@@ -44,26 +44,18 @@ struct platform_device s3c_device_i2c1 = { | |||
44 | .resource = s3c_i2c_resource, | 44 | .resource = s3c_i2c_resource, |
45 | }; | 45 | }; |
46 | 46 | ||
47 | static struct s3c2410_platform_i2c default_i2c_data1 __initdata = { | ||
48 | .flags = 0, | ||
49 | .bus_num = 1, | ||
50 | .slave_addr = 0x10, | ||
51 | .frequency = 100*1000, | ||
52 | .sda_delay = 100, | ||
53 | }; | ||
54 | |||
55 | void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) | 47 | void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) |
56 | { | 48 | { |
57 | struct s3c2410_platform_i2c *npd; | 49 | struct s3c2410_platform_i2c *npd; |
58 | 50 | ||
59 | if (!pd) | 51 | if (!pd) { |
60 | pd = &default_i2c_data1; | 52 | pd = &default_i2c_data; |
53 | pd->bus_num = 1; | ||
54 | } | ||
61 | 55 | ||
62 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 56 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
63 | if (!npd) | 57 | &s3c_device_i2c1); |
64 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
65 | else if (!npd->cfg_gpio) | ||
66 | npd->cfg_gpio = s3c_i2c1_cfg_gpio; | ||
67 | 58 | ||
68 | s3c_device_i2c1.dev.platform_data = npd; | 59 | if (!npd->cfg_gpio) |
60 | npd->cfg_gpio = s3c_i2c1_cfg_gpio; | ||
69 | } | 61 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c index ff4ba69b6830..07e9fd0b1b8b 100644 --- a/arch/arm/plat-samsung/dev-i2c2.c +++ b/arch/arm/plat-samsung/dev-i2c2.c | |||
@@ -45,26 +45,18 @@ struct platform_device s3c_device_i2c2 = { | |||
45 | .resource = s3c_i2c_resource, | 45 | .resource = s3c_i2c_resource, |
46 | }; | 46 | }; |
47 | 47 | ||
48 | static struct s3c2410_platform_i2c default_i2c_data2 __initdata = { | ||
49 | .flags = 0, | ||
50 | .bus_num = 2, | ||
51 | .slave_addr = 0x10, | ||
52 | .frequency = 100*1000, | ||
53 | .sda_delay = 100, | ||
54 | }; | ||
55 | |||
56 | void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) | 48 | void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) |
57 | { | 49 | { |
58 | struct s3c2410_platform_i2c *npd; | 50 | struct s3c2410_platform_i2c *npd; |
59 | 51 | ||
60 | if (!pd) | 52 | if (!pd) { |
61 | pd = &default_i2c_data2; | 53 | pd = &default_i2c_data; |
54 | pd->bus_num = 2; | ||
55 | } | ||
62 | 56 | ||
63 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 57 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
64 | if (!npd) | 58 | &s3c_device_i2c2); |
65 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
66 | else if (!npd->cfg_gpio) | ||
67 | npd->cfg_gpio = s3c_i2c2_cfg_gpio; | ||
68 | 59 | ||
69 | s3c_device_i2c2.dev.platform_data = npd; | 60 | if (!npd->cfg_gpio) |
61 | npd->cfg_gpio = s3c_i2c2_cfg_gpio; | ||
70 | } | 62 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c3.c b/arch/arm/plat-samsung/dev-i2c3.c index 8586a10014b7..d48efa93c6e7 100644 --- a/arch/arm/plat-samsung/dev-i2c3.c +++ b/arch/arm/plat-samsung/dev-i2c3.c | |||
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c3 = { | |||
43 | .resource = s3c_i2c_resource, | 43 | .resource = s3c_i2c_resource, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct s3c2410_platform_i2c default_i2c_data3 __initdata = { | ||
47 | .flags = 0, | ||
48 | .bus_num = 3, | ||
49 | .slave_addr = 0x10, | ||
50 | .frequency = 100*1000, | ||
51 | .sda_delay = 100, | ||
52 | }; | ||
53 | |||
54 | void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd) | 46 | void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd) |
55 | { | 47 | { |
56 | struct s3c2410_platform_i2c *npd; | 48 | struct s3c2410_platform_i2c *npd; |
57 | 49 | ||
58 | if (!pd) | 50 | if (!pd) { |
59 | pd = &default_i2c_data3; | 51 | pd = &default_i2c_data; |
52 | pd->bus_num = 3; | ||
53 | } | ||
60 | 54 | ||
61 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 55 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
62 | if (!npd) | 56 | &s3c_device_i2c3); |
63 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
64 | else if (!npd->cfg_gpio) | ||
65 | npd->cfg_gpio = s3c_i2c3_cfg_gpio; | ||
66 | 57 | ||
67 | s3c_device_i2c3.dev.platform_data = npd; | 58 | if (!npd->cfg_gpio) |
59 | npd->cfg_gpio = s3c_i2c3_cfg_gpio; | ||
68 | } | 60 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c4.c b/arch/arm/plat-samsung/dev-i2c4.c index df2159e2daa6..07e26444efe6 100644 --- a/arch/arm/plat-samsung/dev-i2c4.c +++ b/arch/arm/plat-samsung/dev-i2c4.c | |||
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c4 = { | |||
43 | .resource = s3c_i2c_resource, | 43 | .resource = s3c_i2c_resource, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct s3c2410_platform_i2c default_i2c_data4 __initdata = { | ||
47 | .flags = 0, | ||
48 | .bus_num = 4, | ||
49 | .slave_addr = 0x10, | ||
50 | .frequency = 100*1000, | ||
51 | .sda_delay = 100, | ||
52 | }; | ||
53 | |||
54 | void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd) | 46 | void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd) |
55 | { | 47 | { |
56 | struct s3c2410_platform_i2c *npd; | 48 | struct s3c2410_platform_i2c *npd; |
57 | 49 | ||
58 | if (!pd) | 50 | if (!pd) { |
59 | pd = &default_i2c_data4; | 51 | pd = &default_i2c_data; |
52 | pd->bus_num = 4; | ||
53 | } | ||
60 | 54 | ||
61 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 55 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
62 | if (!npd) | 56 | &s3c_device_i2c4); |
63 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
64 | else if (!npd->cfg_gpio) | ||
65 | npd->cfg_gpio = s3c_i2c4_cfg_gpio; | ||
66 | 57 | ||
67 | s3c_device_i2c4.dev.platform_data = npd; | 58 | if (!npd->cfg_gpio) |
59 | npd->cfg_gpio = s3c_i2c4_cfg_gpio; | ||
68 | } | 60 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c5.c b/arch/arm/plat-samsung/dev-i2c5.c index 0499c2c3877b..f49655784563 100644 --- a/arch/arm/plat-samsung/dev-i2c5.c +++ b/arch/arm/plat-samsung/dev-i2c5.c | |||
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c5 = { | |||
43 | .resource = s3c_i2c_resource, | 43 | .resource = s3c_i2c_resource, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct s3c2410_platform_i2c default_i2c_data5 __initdata = { | ||
47 | .flags = 0, | ||
48 | .bus_num = 5, | ||
49 | .slave_addr = 0x10, | ||
50 | .frequency = 100*1000, | ||
51 | .sda_delay = 100, | ||
52 | }; | ||
53 | |||
54 | void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd) | 46 | void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd) |
55 | { | 47 | { |
56 | struct s3c2410_platform_i2c *npd; | 48 | struct s3c2410_platform_i2c *npd; |
57 | 49 | ||
58 | if (!pd) | 50 | if (!pd) { |
59 | pd = &default_i2c_data5; | 51 | pd = &default_i2c_data; |
52 | pd->bus_num = 5; | ||
53 | } | ||
60 | 54 | ||
61 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 55 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
62 | if (!npd) | 56 | &s3c_device_i2c5); |
63 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
64 | else if (!npd->cfg_gpio) | ||
65 | npd->cfg_gpio = s3c_i2c5_cfg_gpio; | ||
66 | 57 | ||
67 | s3c_device_i2c5.dev.platform_data = npd; | 58 | if (!npd->cfg_gpio) |
59 | npd->cfg_gpio = s3c_i2c5_cfg_gpio; | ||
68 | } | 60 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c6.c b/arch/arm/plat-samsung/dev-i2c6.c index 4083108908a8..141d799944e2 100644 --- a/arch/arm/plat-samsung/dev-i2c6.c +++ b/arch/arm/plat-samsung/dev-i2c6.c | |||
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c6 = { | |||
43 | .resource = s3c_i2c_resource, | 43 | .resource = s3c_i2c_resource, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct s3c2410_platform_i2c default_i2c_data6 __initdata = { | ||
47 | .flags = 0, | ||
48 | .bus_num = 6, | ||
49 | .slave_addr = 0x10, | ||
50 | .frequency = 100*1000, | ||
51 | .sda_delay = 100, | ||
52 | }; | ||
53 | |||
54 | void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd) | 46 | void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd) |
55 | { | 47 | { |
56 | struct s3c2410_platform_i2c *npd; | 48 | struct s3c2410_platform_i2c *npd; |
57 | 49 | ||
58 | if (!pd) | 50 | if (!pd) { |
59 | pd = &default_i2c_data6; | 51 | pd = &default_i2c_data; |
52 | pd->bus_num = 6; | ||
53 | } | ||
60 | 54 | ||
61 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 55 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
62 | if (!npd) | 56 | &s3c_device_i2c6); |
63 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
64 | else if (!npd->cfg_gpio) | ||
65 | npd->cfg_gpio = s3c_i2c6_cfg_gpio; | ||
66 | 57 | ||
67 | s3c_device_i2c6.dev.platform_data = npd; | 58 | if (!npd->cfg_gpio) |
59 | npd->cfg_gpio = s3c_i2c6_cfg_gpio; | ||
68 | } | 60 | } |
diff --git a/arch/arm/plat-samsung/dev-i2c7.c b/arch/arm/plat-samsung/dev-i2c7.c index 1182451d7dce..9dddcd1665b5 100644 --- a/arch/arm/plat-samsung/dev-i2c7.c +++ b/arch/arm/plat-samsung/dev-i2c7.c | |||
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c7 = { | |||
43 | .resource = s3c_i2c_resource, | 43 | .resource = s3c_i2c_resource, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct s3c2410_platform_i2c default_i2c_data7 __initdata = { | ||
47 | .flags = 0, | ||
48 | .bus_num = 7, | ||
49 | .slave_addr = 0x10, | ||
50 | .frequency = 100*1000, | ||
51 | .sda_delay = 100, | ||
52 | }; | ||
53 | |||
54 | void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd) | 46 | void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd) |
55 | { | 47 | { |
56 | struct s3c2410_platform_i2c *npd; | 48 | struct s3c2410_platform_i2c *npd; |
57 | 49 | ||
58 | if (!pd) | 50 | if (!pd) { |
59 | pd = &default_i2c_data7; | 51 | pd = &default_i2c_data; |
52 | pd->bus_num = 7; | ||
53 | } | ||
60 | 54 | ||
61 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | 55 | npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), |
62 | if (!npd) | 56 | &s3c_device_i2c7); |
63 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
64 | else if (!npd->cfg_gpio) | ||
65 | npd->cfg_gpio = s3c_i2c7_cfg_gpio; | ||
66 | 57 | ||
67 | s3c_device_i2c7.dev.platform_data = npd; | 58 | if (!npd->cfg_gpio) |
59 | npd->cfg_gpio = s3c_i2c7_cfg_gpio; | ||
68 | } | 60 | } |
diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c index 6927ae8fd118..b8e30ec6ac26 100644 --- a/arch/arm/plat-samsung/dev-nand.c +++ b/arch/arm/plat-samsung/dev-nand.c | |||
@@ -91,11 +91,10 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand) | |||
91 | * time then there is little chance the system is going to run. | 91 | * time then there is little chance the system is going to run. |
92 | */ | 92 | */ |
93 | 93 | ||
94 | npd = kmemdup(nand, sizeof(struct s3c2410_platform_nand), GFP_KERNEL); | 94 | npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand), |
95 | if (!npd) { | 95 | &s3c_device_nand); |
96 | printk(KERN_ERR "%s: failed copying platform data\n", __func__); | 96 | if (!npd) |
97 | return; | 97 | return; |
98 | } | ||
99 | 98 | ||
100 | /* now see if we need to copy any of the nand set data */ | 99 | /* now see if we need to copy any of the nand set data */ |
101 | 100 | ||
@@ -123,6 +122,4 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand) | |||
123 | to++; | 122 | to++; |
124 | } | 123 | } |
125 | } | 124 | } |
126 | |||
127 | s3c_device_nand.dev.platform_data = npd; | ||
128 | } | 125 | } |
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c index 3e4bd8147bf4..82543f0248ac 100644 --- a/arch/arm/plat-samsung/dev-ts.c +++ b/arch/arm/plat-samsung/dev-ts.c | |||
@@ -45,16 +45,6 @@ struct platform_device s3c_device_ts = { | |||
45 | 45 | ||
46 | void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) | 46 | void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) |
47 | { | 47 | { |
48 | struct s3c2410_ts_mach_info *npd; | 48 | s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info), |
49 | 49 | &s3c_device_ts); | |
50 | if (!pd) { | ||
51 | printk(KERN_ERR "%s: no platform data\n", __func__); | ||
52 | return; | ||
53 | } | ||
54 | |||
55 | npd = kmemdup(pd, sizeof(struct s3c2410_ts_mach_info), GFP_KERNEL); | ||
56 | if (!npd) | ||
57 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
58 | |||
59 | s3c_device_ts.dev.platform_data = npd; | ||
60 | } | 50 | } |
diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c index 0e0a3bf5c982..33fbaa967700 100644 --- a/arch/arm/plat-samsung/dev-usb.c +++ b/arch/arm/plat-samsung/dev-usb.c | |||
@@ -60,11 +60,6 @@ EXPORT_SYMBOL(s3c_device_ohci); | |||
60 | */ | 60 | */ |
61 | void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info) | 61 | void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info) |
62 | { | 62 | { |
63 | struct s3c2410_hcd_info *npd; | 63 | s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info), |
64 | 64 | &s3c_device_ohci); | |
65 | npd = kmemdup(info, sizeof(struct s3c2410_hcd_info), GFP_KERNEL); | ||
66 | if (!npd) | ||
67 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
68 | |||
69 | s3c_device_ohci.dev.platform_data = npd; | ||
70 | } | 65 | } |
diff --git a/arch/arm/plat-samsung/include/plat/backlight.h b/arch/arm/plat-samsung/include/plat/backlight.h new file mode 100644 index 000000000000..51d8da846a62 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/backlight.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/backlight.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_PLAT_BACKLIGHT_H | ||
12 | #define __ASM_PLAT_BACKLIGHT_H __FILE__ | ||
13 | |||
14 | /* samsung_bl_gpio_info - GPIO info for PWM Backlight control | ||
15 | * @no: GPIO number for PWM timer out | ||
16 | * @func: Special function of GPIO line for PWM timer | ||
17 | */ | ||
18 | struct samsung_bl_gpio_info { | ||
19 | int no; | ||
20 | int func; | ||
21 | }; | ||
22 | |||
23 | extern void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, | ||
24 | struct platform_pwm_backlight_data *bl_data); | ||
25 | |||
26 | #endif /* __ASM_PLAT_BACKLIGHT_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 983c578b8276..87d5b38a86fb 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h | |||
@@ -10,6 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/spinlock.h> | 12 | #include <linux/spinlock.h> |
13 | #include <linux/clkdev.h> | ||
13 | 14 | ||
14 | struct clk; | 15 | struct clk; |
15 | 16 | ||
@@ -40,6 +41,7 @@ struct clk { | |||
40 | struct module *owner; | 41 | struct module *owner; |
41 | struct clk *parent; | 42 | struct clk *parent; |
42 | const char *name; | 43 | const char *name; |
44 | const char *devname; | ||
43 | int id; | 45 | int id; |
44 | int usage; | 46 | int usage; |
45 | unsigned long rate; | 47 | unsigned long rate; |
@@ -47,6 +49,7 @@ struct clk { | |||
47 | 49 | ||
48 | struct clk_ops *ops; | 50 | struct clk_ops *ops; |
49 | int (*enable)(struct clk *, int enable); | 51 | int (*enable)(struct clk *, int enable); |
52 | struct clk_lookup lookup; | ||
50 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) | 53 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
51 | struct dentry *dent; /* For visible tree hierarchy */ | 54 | struct dentry *dent; /* For visible tree hierarchy */ |
52 | #endif | 55 | #endif |
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 4af108ff4112..e3b31c26ac3e 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
@@ -12,6 +12,10 @@ | |||
12 | * it under the terms of the GNU General Public License version 2 as | 12 | * it under the terms of the GNU General Public License version 2 as |
13 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
14 | */ | 14 | */ |
15 | |||
16 | #ifndef __PLAT_DEVS_H | ||
17 | #define __PLAT_DEVS_H __FILE__ | ||
18 | |||
15 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
16 | 20 | ||
17 | struct s3c24xx_uart_resources { | 21 | struct s3c24xx_uart_resources { |
@@ -159,3 +163,5 @@ extern struct platform_device s3c_device_ac97; | |||
159 | */ | 163 | */ |
160 | extern void *s3c_set_platdata(void *pd, size_t pdsize, | 164 | extern void *s3c_set_platdata(void *pd, size_t pdsize, |
161 | struct platform_device *pdev); | 165 | struct platform_device *pdev); |
166 | |||
167 | #endif /* __PLAT_DEVS_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h index 1543da8f85c1..56b0059439e1 100644 --- a/arch/arm/plat-samsung/include/plat/iic.h +++ b/arch/arm/plat-samsung/include/plat/iic.h | |||
@@ -71,4 +71,6 @@ extern void s3c_i2c5_cfg_gpio(struct platform_device *dev); | |||
71 | extern void s3c_i2c6_cfg_gpio(struct platform_device *dev); | 71 | extern void s3c_i2c6_cfg_gpio(struct platform_device *dev); |
72 | extern void s3c_i2c7_cfg_gpio(struct platform_device *dev); | 72 | extern void s3c_i2c7_cfg_gpio(struct platform_device *dev); |
73 | 73 | ||
74 | extern struct s3c2410_platform_i2c default_i2c_data; | ||
75 | |||
74 | #endif /* __ASM_ARCH_IIC_H */ | 76 | #endif /* __ASM_ARCH_IIC_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index 0ffe34a21554..4c16fa3621bb 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | |||
@@ -39,6 +39,7 @@ struct s3c64xx_spi_csinfo { | |||
39 | * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 | 39 | * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 |
40 | * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number | 40 | * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number |
41 | * @high_speed: If the controller supports HIGH_SPEED_EN bit | 41 | * @high_speed: If the controller supports HIGH_SPEED_EN bit |
42 | * @tx_st_done: Depends on tx fifo_lvl field | ||
42 | */ | 43 | */ |
43 | struct s3c64xx_spi_info { | 44 | struct s3c64xx_spi_info { |
44 | int src_clk_nr; | 45 | int src_clk_nr; |
@@ -53,6 +54,7 @@ struct s3c64xx_spi_info { | |||
53 | int fifo_lvl_mask; | 54 | int fifo_lvl_mask; |
54 | int rx_lvl_offset; | 55 | int rx_lvl_offset; |
55 | int high_speed; | 56 | int high_speed; |
57 | int tx_st_done; | ||
56 | }; | 58 | }; |
57 | 59 | ||
58 | /** | 60 | /** |
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c index 46c9381e083b..f1bba88ed2f5 100644 --- a/arch/arm/plat-samsung/pwm-clock.c +++ b/arch/arm/plat-samsung/pwm-clock.c | |||
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { | |||
268 | [0] = { | 268 | [0] = { |
269 | .clk = { | 269 | .clk = { |
270 | .name = "pwm-tdiv", | 270 | .name = "pwm-tdiv", |
271 | .devname = "s3c24xx-pwm.0", | ||
271 | .ops = &clk_tdiv_ops, | 272 | .ops = &clk_tdiv_ops, |
272 | .parent = &clk_timer_scaler[0], | 273 | .parent = &clk_timer_scaler[0], |
273 | }, | 274 | }, |
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { | |||
275 | [1] = { | 276 | [1] = { |
276 | .clk = { | 277 | .clk = { |
277 | .name = "pwm-tdiv", | 278 | .name = "pwm-tdiv", |
279 | .devname = "s3c24xx-pwm.1", | ||
278 | .ops = &clk_tdiv_ops, | 280 | .ops = &clk_tdiv_ops, |
279 | .parent = &clk_timer_scaler[0], | 281 | .parent = &clk_timer_scaler[0], |
280 | } | 282 | } |
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { | |||
282 | [2] = { | 284 | [2] = { |
283 | .clk = { | 285 | .clk = { |
284 | .name = "pwm-tdiv", | 286 | .name = "pwm-tdiv", |
287 | .devname = "s3c24xx-pwm.2", | ||
285 | .ops = &clk_tdiv_ops, | 288 | .ops = &clk_tdiv_ops, |
286 | .parent = &clk_timer_scaler[1], | 289 | .parent = &clk_timer_scaler[1], |
287 | }, | 290 | }, |
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { | |||
289 | [3] = { | 292 | [3] = { |
290 | .clk = { | 293 | .clk = { |
291 | .name = "pwm-tdiv", | 294 | .name = "pwm-tdiv", |
295 | .devname = "s3c24xx-pwm.3", | ||
292 | .ops = &clk_tdiv_ops, | 296 | .ops = &clk_tdiv_ops, |
293 | .parent = &clk_timer_scaler[1], | 297 | .parent = &clk_timer_scaler[1], |
294 | }, | 298 | }, |
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { | |||
296 | [4] = { | 300 | [4] = { |
297 | .clk = { | 301 | .clk = { |
298 | .name = "pwm-tdiv", | 302 | .name = "pwm-tdiv", |
303 | .devname = "s3c24xx-pwm.4", | ||
299 | .ops = &clk_tdiv_ops, | 304 | .ops = &clk_tdiv_ops, |
300 | .parent = &clk_timer_scaler[1], | 305 | .parent = &clk_timer_scaler[1], |
301 | }, | 306 | }, |
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = { | |||
361 | static struct clk clk_tin[] = { | 366 | static struct clk clk_tin[] = { |
362 | [0] = { | 367 | [0] = { |
363 | .name = "pwm-tin", | 368 | .name = "pwm-tin", |
369 | .devname = "s3c24xx-pwm.0", | ||
364 | .id = 0, | 370 | .id = 0, |
365 | .ops = &clk_tin_ops, | 371 | .ops = &clk_tin_ops, |
366 | }, | 372 | }, |
367 | [1] = { | 373 | [1] = { |
368 | .name = "pwm-tin", | 374 | .name = "pwm-tin", |
375 | .devname = "s3c24xx-pwm.1", | ||
369 | .id = 1, | 376 | .id = 1, |
370 | .ops = &clk_tin_ops, | 377 | .ops = &clk_tin_ops, |
371 | }, | 378 | }, |
372 | [2] = { | 379 | [2] = { |
373 | .name = "pwm-tin", | 380 | .name = "pwm-tin", |
381 | .devname = "s3c24xx-pwm.2", | ||
374 | .id = 2, | 382 | .id = 2, |
375 | .ops = &clk_tin_ops, | 383 | .ops = &clk_tin_ops, |
376 | }, | 384 | }, |
377 | [3] = { | 385 | [3] = { |
378 | .name = "pwm-tin", | 386 | .name = "pwm-tin", |
387 | .devname = "s3c24xx-pwm.3", | ||
379 | .id = 3, | 388 | .id = 3, |
380 | .ops = &clk_tin_ops, | 389 | .ops = &clk_tin_ops, |
381 | }, | 390 | }, |
382 | [4] = { | 391 | [4] = { |
383 | .name = "pwm-tin", | 392 | .name = "pwm-tin", |
393 | .devname = "s3c24xx-pwm.4", | ||
384 | .id = 4, | 394 | .id = 4, |
385 | .ops = &clk_tin_ops, | 395 | .ops = &clk_tin_ops, |
386 | }, | 396 | }, |
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c index 2231d80ad817..e3bb806bbafe 100644 --- a/arch/arm/plat-samsung/time.c +++ b/arch/arm/plat-samsung/time.c | |||
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void) | |||
259 | clk_enable(timerclk); | 259 | clk_enable(timerclk); |
260 | 260 | ||
261 | if (!use_tclk1_12()) { | 261 | if (!use_tclk1_12()) { |
262 | tmpdev.id = 4; | ||
263 | tmpdev.dev.init_name = "s3c24xx-pwm.4"; | ||
262 | tin = clk_get(&tmpdev.dev, "pwm-tin"); | 264 | tin = clk_get(&tmpdev.dev, "pwm-tin"); |
263 | if (IS_ERR(tin)) | 265 | if (IS_ERR(tin)) |
264 | panic("failed to get pwm-tin clock for system timer"); | 266 | panic("failed to get pwm-tin clock for system timer"); |