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-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c74
1 files changed, 20 insertions, 54 deletions
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 9f12c2ebf416..0e9cd3092dd2 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
95static struct clksrc_clk clk_hclk = { 95static struct clksrc_clk clk_hclk = {
96 .clk = { 96 .clk = {
97 .name = "clk_hclk", 97 .name = "clk_hclk",
98 .id = -1,
99 .parent = &clk_armclk.clk, 98 .parent = &clk_armclk.clk,
100 }, 99 },
101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, 100 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
104static struct clksrc_clk clk_pclk = { 103static struct clksrc_clk clk_pclk = {
105 .clk = { 104 .clk = {
106 .name = "clk_pclk", 105 .name = "clk_pclk",
107 .id = -1,
108 .parent = &clk_hclk.clk, 106 .parent = &clk_hclk.clk,
109 }, 107 },
110 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, 108 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
112static struct clksrc_clk clk_hclk_low = { 110static struct clksrc_clk clk_hclk_low = {
113 .clk = { 111 .clk = {
114 .name = "clk_hclk_low", 112 .name = "clk_hclk_low",
115 .id = -1,
116 }, 113 },
117 .sources = &clkset_hclk_low, 114 .sources = &clkset_hclk_low,
118 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, 115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
122static struct clksrc_clk clk_pclk_low = { 119static struct clksrc_clk clk_pclk_low = {
123 .clk = { 120 .clk = {
124 .name = "clk_pclk_low", 121 .name = "clk_pclk_low",
125 .id = -1,
126 .parent = &clk_hclk_low.clk, 122 .parent = &clk_hclk_low.clk,
127 }, 123 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, 124 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
136static struct clk init_clocks_off[] = { 132static struct clk init_clocks_off[] = {
137 { 133 {
138 .name = "nand", 134 .name = "nand",
139 .id = -1,
140 .parent = &clk_hclk.clk, 135 .parent = &clk_hclk.clk,
141 .enable = s5p64x0_mem_ctrl, 136 .enable = s5p64x0_mem_ctrl,
142 .ctrlbit = (1 << 2), 137 .ctrlbit = (1 << 2),
143 }, { 138 }, {
144 .name = "post", 139 .name = "post",
145 .id = -1,
146 .parent = &clk_hclk_low.clk, 140 .parent = &clk_hclk_low.clk,
147 .enable = s5p64x0_hclk0_ctrl, 141 .enable = s5p64x0_hclk0_ctrl,
148 .ctrlbit = (1 << 5) 142 .ctrlbit = (1 << 5)
149 }, { 143 }, {
150 .name = "2d", 144 .name = "2d",
151 .id = -1,
152 .parent = &clk_hclk.clk, 145 .parent = &clk_hclk.clk,
153 .enable = s5p64x0_hclk0_ctrl, 146 .enable = s5p64x0_hclk0_ctrl,
154 .ctrlbit = (1 << 8), 147 .ctrlbit = (1 << 8),
155 }, { 148 }, {
156 .name = "pdma", 149 .name = "pdma",
157 .id = -1,
158 .parent = &clk_hclk_low.clk, 150 .parent = &clk_hclk_low.clk,
159 .enable = s5p64x0_hclk0_ctrl, 151 .enable = s5p64x0_hclk0_ctrl,
160 .ctrlbit = (1 << 12), 152 .ctrlbit = (1 << 12),
161 }, { 153 }, {
162 .name = "hsmmc", 154 .name = "hsmmc",
163 .id = 0, 155 .devname = "s3c-sdhci.0",
164 .parent = &clk_hclk_low.clk, 156 .parent = &clk_hclk_low.clk,
165 .enable = s5p64x0_hclk0_ctrl, 157 .enable = s5p64x0_hclk0_ctrl,
166 .ctrlbit = (1 << 17), 158 .ctrlbit = (1 << 17),
167 }, { 159 }, {
168 .name = "hsmmc", 160 .name = "hsmmc",
169 .id = 1, 161 .devname = "s3c-sdhci.1",
170 .parent = &clk_hclk_low.clk, 162 .parent = &clk_hclk_low.clk,
171 .enable = s5p64x0_hclk0_ctrl, 163 .enable = s5p64x0_hclk0_ctrl,
172 .ctrlbit = (1 << 18), 164 .ctrlbit = (1 << 18),
173 }, { 165 }, {
174 .name = "hsmmc", 166 .name = "hsmmc",
175 .id = 2, 167 .devname = "s3c-sdhci.2",
176 .parent = &clk_hclk_low.clk, 168 .parent = &clk_hclk_low.clk,
177 .enable = s5p64x0_hclk0_ctrl, 169 .enable = s5p64x0_hclk0_ctrl,
178 .ctrlbit = (1 << 19), 170 .ctrlbit = (1 << 19),
179 }, { 171 }, {
180 .name = "otg", 172 .name = "otg",
181 .id = -1,
182 .parent = &clk_hclk_low.clk, 173 .parent = &clk_hclk_low.clk,
183 .enable = s5p64x0_hclk0_ctrl, 174 .enable = s5p64x0_hclk0_ctrl,
184 .ctrlbit = (1 << 20) 175 .ctrlbit = (1 << 20)
185 }, { 176 }, {
186 .name = "irom", 177 .name = "irom",
187 .id = -1,
188 .parent = &clk_hclk.clk, 178 .parent = &clk_hclk.clk,
189 .enable = s5p64x0_hclk0_ctrl, 179 .enable = s5p64x0_hclk0_ctrl,
190 .ctrlbit = (1 << 25), 180 .ctrlbit = (1 << 25),
191 }, { 181 }, {
192 .name = "lcd", 182 .name = "lcd",
193 .id = -1,
194 .parent = &clk_hclk_low.clk, 183 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk1_ctrl, 184 .enable = s5p64x0_hclk1_ctrl,
196 .ctrlbit = (1 << 1), 185 .ctrlbit = (1 << 1),
197 }, { 186 }, {
198 .name = "hclk_fimgvg", 187 .name = "hclk_fimgvg",
199 .id = -1,
200 .parent = &clk_hclk.clk, 188 .parent = &clk_hclk.clk,
201 .enable = s5p64x0_hclk1_ctrl, 189 .enable = s5p64x0_hclk1_ctrl,
202 .ctrlbit = (1 << 2), 190 .ctrlbit = (1 << 2),
203 }, { 191 }, {
204 .name = "tsi", 192 .name = "tsi",
205 .id = -1,
206 .parent = &clk_hclk_low.clk, 193 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk1_ctrl, 194 .enable = s5p64x0_hclk1_ctrl,
208 .ctrlbit = (1 << 0), 195 .ctrlbit = (1 << 0),
209 }, { 196 }, {
210 .name = "watchdog", 197 .name = "watchdog",
211 .id = -1,
212 .parent = &clk_pclk_low.clk, 198 .parent = &clk_pclk_low.clk,
213 .enable = s5p64x0_pclk_ctrl, 199 .enable = s5p64x0_pclk_ctrl,
214 .ctrlbit = (1 << 5), 200 .ctrlbit = (1 << 5),
215 }, { 201 }, {
216 .name = "rtc", 202 .name = "rtc",
217 .id = -1,
218 .parent = &clk_pclk_low.clk, 203 .parent = &clk_pclk_low.clk,
219 .enable = s5p64x0_pclk_ctrl, 204 .enable = s5p64x0_pclk_ctrl,
220 .ctrlbit = (1 << 6), 205 .ctrlbit = (1 << 6),
221 }, { 206 }, {
222 .name = "timers", 207 .name = "timers",
223 .id = -1,
224 .parent = &clk_pclk_low.clk, 208 .parent = &clk_pclk_low.clk,
225 .enable = s5p64x0_pclk_ctrl, 209 .enable = s5p64x0_pclk_ctrl,
226 .ctrlbit = (1 << 7), 210 .ctrlbit = (1 << 7),
227 }, { 211 }, {
228 .name = "pcm", 212 .name = "pcm",
229 .id = -1,
230 .parent = &clk_pclk_low.clk, 213 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl, 214 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 8), 215 .ctrlbit = (1 << 8),
233 }, { 216 }, {
234 .name = "adc", 217 .name = "adc",
235 .id = -1,
236 .parent = &clk_pclk_low.clk, 218 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl, 219 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 12), 220 .ctrlbit = (1 << 12),
239 }, { 221 }, {
240 .name = "i2c", 222 .name = "i2c",
241 .id = -1,
242 .parent = &clk_pclk_low.clk, 223 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl, 224 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 17), 225 .ctrlbit = (1 << 17),
245 }, { 226 }, {
246 .name = "spi", 227 .name = "spi",
247 .id = 0, 228 .devname = "s3c64xx-spi.0",
248 .parent = &clk_pclk_low.clk, 229 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl, 230 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 21), 231 .ctrlbit = (1 << 21),
251 }, { 232 }, {
252 .name = "spi", 233 .name = "spi",
253 .id = 1, 234 .devname = "s3c64xx-spi.1",
254 .parent = &clk_pclk_low.clk, 235 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl, 236 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 22), 237 .ctrlbit = (1 << 22),
257 }, { 238 }, {
258 .name = "gps", 239 .name = "gps",
259 .id = -1,
260 .parent = &clk_pclk_low.clk, 240 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl, 241 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 25), 242 .ctrlbit = (1 << 25),
263 }, { 243 }, {
264 .name = "iis", 244 .name = "iis",
265 .id = 0, 245 .devname = "samsung-i2s.0",
266 .parent = &clk_pclk_low.clk, 246 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl, 247 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 26), 248 .ctrlbit = (1 << 26),
269 }, { 249 }, {
270 .name = "dsim", 250 .name = "dsim",
271 .id = -1,
272 .parent = &clk_pclk_low.clk, 251 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl, 252 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 28), 253 .ctrlbit = (1 << 28),
275 }, { 254 }, {
276 .name = "etm", 255 .name = "etm",
277 .id = -1,
278 .parent = &clk_pclk.clk, 256 .parent = &clk_pclk.clk,
279 .enable = s5p64x0_pclk_ctrl, 257 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 29), 258 .ctrlbit = (1 << 29),
281 }, { 259 }, {
282 .name = "dmc0", 260 .name = "dmc0",
283 .id = -1,
284 .parent = &clk_pclk.clk, 261 .parent = &clk_pclk.clk,
285 .enable = s5p64x0_pclk_ctrl, 262 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 30), 263 .ctrlbit = (1 << 30),
287 }, { 264 }, {
288 .name = "pclk_fimgvg", 265 .name = "pclk_fimgvg",
289 .id = -1,
290 .parent = &clk_pclk.clk, 266 .parent = &clk_pclk.clk,
291 .enable = s5p64x0_pclk_ctrl, 267 .enable = s5p64x0_pclk_ctrl,
292 .ctrlbit = (1 << 31), 268 .ctrlbit = (1 << 31),
293 }, { 269 }, {
294 .name = "sclk_spi_48", 270 .name = "sclk_spi_48",
295 .id = 0, 271 .devname = "s3c64xx-spi.0",
296 .parent = &clk_48m, 272 .parent = &clk_48m,
297 .enable = s5p64x0_sclk_ctrl, 273 .enable = s5p64x0_sclk_ctrl,
298 .ctrlbit = (1 << 22), 274 .ctrlbit = (1 << 22),
299 }, { 275 }, {
300 .name = "sclk_spi_48", 276 .name = "sclk_spi_48",
301 .id = 1, 277 .devname = "s3c64xx-spi.1",
302 .parent = &clk_48m, 278 .parent = &clk_48m,
303 .enable = s5p64x0_sclk_ctrl, 279 .enable = s5p64x0_sclk_ctrl,
304 .ctrlbit = (1 << 23), 280 .ctrlbit = (1 << 23),
305 }, { 281 }, {
306 .name = "mmc_48m", 282 .name = "mmc_48m",
307 .id = 0, 283 .devname = "s3c-sdhci.0",
308 .parent = &clk_48m, 284 .parent = &clk_48m,
309 .enable = s5p64x0_sclk_ctrl, 285 .enable = s5p64x0_sclk_ctrl,
310 .ctrlbit = (1 << 27), 286 .ctrlbit = (1 << 27),
311 }, { 287 }, {
312 .name = "mmc_48m", 288 .name = "mmc_48m",
313 .id = 1, 289 .devname = "s3c-sdhci.1",
314 .parent = &clk_48m, 290 .parent = &clk_48m,
315 .enable = s5p64x0_sclk_ctrl, 291 .enable = s5p64x0_sclk_ctrl,
316 .ctrlbit = (1 << 28), 292 .ctrlbit = (1 << 28),
317 }, { 293 }, {
318 .name = "mmc_48m", 294 .name = "mmc_48m",
319 .id = 2, 295 .devname = "s3c-sdhci.2",
320 .parent = &clk_48m, 296 .parent = &clk_48m,
321 .enable = s5p64x0_sclk_ctrl, 297 .enable = s5p64x0_sclk_ctrl,
322 .ctrlbit = (1 << 29), 298 .ctrlbit = (1 << 29),
@@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
329static struct clk init_clocks[] = { 305static struct clk init_clocks[] = {
330 { 306 {
331 .name = "intc", 307 .name = "intc",
332 .id = -1,
333 .parent = &clk_hclk.clk, 308 .parent = &clk_hclk.clk,
334 .enable = s5p64x0_hclk0_ctrl, 309 .enable = s5p64x0_hclk0_ctrl,
335 .ctrlbit = (1 << 1), 310 .ctrlbit = (1 << 1),
336 }, { 311 }, {
337 .name = "mem", 312 .name = "mem",
338 .id = -1,
339 .parent = &clk_hclk.clk, 313 .parent = &clk_hclk.clk,
340 .enable = s5p64x0_hclk0_ctrl, 314 .enable = s5p64x0_hclk0_ctrl,
341 .ctrlbit = (1 << 21), 315 .ctrlbit = (1 << 21),
342 }, { 316 }, {
343 .name = "uart", 317 .name = "uart",
344 .id = 0, 318 .devname = "s3c6400-uart.0",
345 .parent = &clk_pclk_low.clk, 319 .parent = &clk_pclk_low.clk,
346 .enable = s5p64x0_pclk_ctrl, 320 .enable = s5p64x0_pclk_ctrl,
347 .ctrlbit = (1 << 1), 321 .ctrlbit = (1 << 1),
348 }, { 322 }, {
349 .name = "uart", 323 .name = "uart",
350 .id = 1, 324 .devname = "s3c6400-uart.1",
351 .parent = &clk_pclk_low.clk, 325 .parent = &clk_pclk_low.clk,
352 .enable = s5p64x0_pclk_ctrl, 326 .enable = s5p64x0_pclk_ctrl,
353 .ctrlbit = (1 << 2), 327 .ctrlbit = (1 << 2),
354 }, { 328 }, {
355 .name = "uart", 329 .name = "uart",
356 .id = 2, 330 .devname = "s3c6400-uart.2",
357 .parent = &clk_pclk_low.clk, 331 .parent = &clk_pclk_low.clk,
358 .enable = s5p64x0_pclk_ctrl, 332 .enable = s5p64x0_pclk_ctrl,
359 .ctrlbit = (1 << 3), 333 .ctrlbit = (1 << 3),
360 }, { 334 }, {
361 .name = "uart", 335 .name = "uart",
362 .id = 3, 336 .devname = "s3c6400-uart.3",
363 .parent = &clk_pclk_low.clk, 337 .parent = &clk_pclk_low.clk,
364 .enable = s5p64x0_pclk_ctrl, 338 .enable = s5p64x0_pclk_ctrl,
365 .ctrlbit = (1 << 4), 339 .ctrlbit = (1 << 4),
366 }, { 340 }, {
367 .name = "gpio", 341 .name = "gpio",
368 .id = -1,
369 .parent = &clk_pclk_low.clk, 342 .parent = &clk_pclk_low.clk,
370 .enable = s5p64x0_pclk_ctrl, 343 .enable = s5p64x0_pclk_ctrl,
371 .ctrlbit = (1 << 18), 344 .ctrlbit = (1 << 18),
@@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
374 347
375static struct clk clk_iis_cd_v40 = { 348static struct clk clk_iis_cd_v40 = {
376 .name = "iis_cdclk_v40", 349 .name = "iis_cdclk_v40",
377 .id = -1,
378}; 350};
379 351
380static struct clk clk_pcm_cd = { 352static struct clk clk_pcm_cd = {
381 .name = "pcm_cdclk", 353 .name = "pcm_cdclk",
382 .id = -1,
383}; 354};
384 355
385static struct clk *clkset_group1_list[] = { 356static struct clk *clkset_group1_list[] = {
@@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
420 { 391 {
421 .clk = { 392 .clk = {
422 .name = "sclk_mmc", 393 .name = "sclk_mmc",
423 .id = 0, 394 .devname = "s3c-sdhci.0",
424 .ctrlbit = (1 << 24), 395 .ctrlbit = (1 << 24),
425 .enable = s5p64x0_sclk_ctrl, 396 .enable = s5p64x0_sclk_ctrl,
426 }, 397 },
@@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
430 }, { 401 }, {
431 .clk = { 402 .clk = {
432 .name = "sclk_mmc", 403 .name = "sclk_mmc",
433 .id = 1, 404 .devname = "s3c-sdhci.1",
434 .ctrlbit = (1 << 25), 405 .ctrlbit = (1 << 25),
435 .enable = s5p64x0_sclk_ctrl, 406 .enable = s5p64x0_sclk_ctrl,
436 }, 407 },
@@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
440 }, { 411 }, {
441 .clk = { 412 .clk = {
442 .name = "sclk_mmc", 413 .name = "sclk_mmc",
443 .id = 2, 414 .devname = "s3c-sdhci.2",
444 .ctrlbit = (1 << 26), 415 .ctrlbit = (1 << 26),
445 .enable = s5p64x0_sclk_ctrl, 416 .enable = s5p64x0_sclk_ctrl,
446 }, 417 },
@@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
450 }, { 421 }, {
451 .clk = { 422 .clk = {
452 .name = "uclk1", 423 .name = "uclk1",
453 .id = -1,
454 .ctrlbit = (1 << 5), 424 .ctrlbit = (1 << 5),
455 .enable = s5p64x0_sclk_ctrl, 425 .enable = s5p64x0_sclk_ctrl,
456 }, 426 },
@@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
460 }, { 430 }, {
461 .clk = { 431 .clk = {
462 .name = "sclk_spi", 432 .name = "sclk_spi",
463 .id = 0, 433 .devname = "s3c64xx-spi.0",
464 .ctrlbit = (1 << 20), 434 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl, 435 .enable = s5p64x0_sclk_ctrl,
466 }, 436 },
@@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
470 }, { 440 }, {
471 .clk = { 441 .clk = {
472 .name = "sclk_spi", 442 .name = "sclk_spi",
473 .id = 1, 443 .devname = "s3c64xx-spi.1",
474 .ctrlbit = (1 << 21), 444 .ctrlbit = (1 << 21),
475 .enable = s5p64x0_sclk_ctrl, 445 .enable = s5p64x0_sclk_ctrl,
476 }, 446 },
@@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
480 }, { 450 }, {
481 .clk = { 451 .clk = {
482 .name = "sclk_post", 452 .name = "sclk_post",
483 .id = -1,
484 .ctrlbit = (1 << 10), 453 .ctrlbit = (1 << 10),
485 .enable = s5p64x0_sclk_ctrl, 454 .enable = s5p64x0_sclk_ctrl,
486 }, 455 },
@@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
490 }, { 459 }, {
491 .clk = { 460 .clk = {
492 .name = "sclk_dispcon", 461 .name = "sclk_dispcon",
493 .id = -1,
494 .ctrlbit = (1 << 1), 462 .ctrlbit = (1 << 1),
495 .enable = s5p64x0_sclk1_ctrl, 463 .enable = s5p64x0_sclk1_ctrl,
496 }, 464 },
@@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
500 }, { 468 }, {
501 .clk = { 469 .clk = {
502 .name = "sclk_fimgvg", 470 .name = "sclk_fimgvg",
503 .id = -1,
504 .ctrlbit = (1 << 2), 471 .ctrlbit = (1 << 2),
505 .enable = s5p64x0_sclk1_ctrl, 472 .enable = s5p64x0_sclk1_ctrl,
506 }, 473 },
@@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
510 }, { 477 }, {
511 .clk = { 478 .clk = {
512 .name = "sclk_audio2", 479 .name = "sclk_audio2",
513 .id = -1,
514 .ctrlbit = (1 << 11), 480 .ctrlbit = (1 << 11),
515 .enable = s5p64x0_sclk_ctrl, 481 .enable = s5p64x0_sclk_ctrl,
516 }, 482 },
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 02:04:04 -0500