2 files changed, 17 insertions, 17 deletions

diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index f123d6eb074b..f9c32ba73544 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -392,9 +392,9 @@ __arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached)
         unsigned int mtype;
 
         if (cached)
-                mtype = MT_MEMORY;
+                mtype = MT_MEMORY_RWX;
         else
-                mtype = MT_MEMORY_NONCACHED;
+                mtype = MT_MEMORY_RWX_NONCACHED;
 
         return __arm_ioremap_caller(phys_addr, size, mtype,
                         __builtin_return_address(0));
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 580ef2de82d7..fce2e7388098 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -287,7 +287,7 @@ static struct mem_type mem_types[] = {
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_USER,
         },
-        [MT_MEMORY] = {
+        [MT_MEMORY_RWX] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
@@ -297,26 +297,26 @@ static struct mem_type mem_types[] = {
                 .prot_sect = PMD_TYPE_SECT,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_NONCACHED] = {
+        [MT_MEMORY_RWX_NONCACHED] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                 L_PTE_MT_BUFFERABLE,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_DTCM] = {
+        [MT_MEMORY_RW_DTCM] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                 L_PTE_XN,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_ITCM] = {
+        [MT_MEMORY_RWX_ITCM] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_KERNEL,
         },
-        [MT_MEMORY_SO] = {
+        [MT_MEMORY_RW_SO] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
                                 L_PTE_MT_UNCACHED | L_PTE_XN,
                 .prot_l1   = PMD_TYPE_TABLE,
@@ -487,11 +487,11 @@ static void __init build_mem_type_table(void)
                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
-                        mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
-                        mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
-                        mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
-                        mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
                 }
         }
 
@@ -502,15 +502,15 @@ static void __init build_mem_type_table(void)
         if (cpu_arch >= CPU_ARCH_ARMv6) {
                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
                         /* Non-cacheable Normal is XCB = 001 */
-                        mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
                                 PMD_SECT_BUFFERED;
                 } else {
                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
-                        mem_types[MT_MEMORY_NONCACHED].prot_sect |=
+                        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
                                 PMD_SECT_TEX(1);
                 }
         } else {
-                mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
+                mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
         }
 
 #ifdef CONFIG_ARM_LPAE
@@ -543,10 +543,10 @@ static void __init build_mem_type_table(void)
 
         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
-        mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
-        mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
+        mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
+        mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
-        mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
+        mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
         mem_types[MT_ROM].prot_sect |= cp->pmd;
 
         switch (cp->pmd) {