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Diffstat (limited to 'arch/arm/mm/mmu.c')
-rw-r--r--arch/arm/mm/mmu.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 580ef2de82d7..fce2e7388098 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -287,7 +287,7 @@ static struct mem_type mem_types[] = {
287 .prot_l1 = PMD_TYPE_TABLE, 287 .prot_l1 = PMD_TYPE_TABLE,
288 .domain = DOMAIN_USER, 288 .domain = DOMAIN_USER,
289 }, 289 },
290 [MT_MEMORY] = { 290 [MT_MEMORY_RWX] = {
291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 291 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
292 .prot_l1 = PMD_TYPE_TABLE, 292 .prot_l1 = PMD_TYPE_TABLE,
293 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 293 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
@@ -297,26 +297,26 @@ static struct mem_type mem_types[] = {
297 .prot_sect = PMD_TYPE_SECT, 297 .prot_sect = PMD_TYPE_SECT,
298 .domain = DOMAIN_KERNEL, 298 .domain = DOMAIN_KERNEL,
299 }, 299 },
300 [MT_MEMORY_NONCACHED] = { 300 [MT_MEMORY_RWX_NONCACHED] = {
301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 301 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
302 L_PTE_MT_BUFFERABLE, 302 L_PTE_MT_BUFFERABLE,
303 .prot_l1 = PMD_TYPE_TABLE, 303 .prot_l1 = PMD_TYPE_TABLE,
304 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 304 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
305 .domain = DOMAIN_KERNEL, 305 .domain = DOMAIN_KERNEL,
306 }, 306 },
307 [MT_MEMORY_DTCM] = { 307 [MT_MEMORY_RW_DTCM] = {
308 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 308 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
309 L_PTE_XN, 309 L_PTE_XN,
310 .prot_l1 = PMD_TYPE_TABLE, 310 .prot_l1 = PMD_TYPE_TABLE,
311 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 311 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
312 .domain = DOMAIN_KERNEL, 312 .domain = DOMAIN_KERNEL,
313 }, 313 },
314 [MT_MEMORY_ITCM] = { 314 [MT_MEMORY_RWX_ITCM] = {
315 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 315 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
316 .prot_l1 = PMD_TYPE_TABLE, 316 .prot_l1 = PMD_TYPE_TABLE,
317 .domain = DOMAIN_KERNEL, 317 .domain = DOMAIN_KERNEL,
318 }, 318 },
319 [MT_MEMORY_SO] = { 319 [MT_MEMORY_RW_SO] = {
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_MT_UNCACHED | L_PTE_XN, 321 L_PTE_MT_UNCACHED | L_PTE_XN,
322 .prot_l1 = PMD_TYPE_TABLE, 322 .prot_l1 = PMD_TYPE_TABLE,
@@ -487,11 +487,11 @@ static void __init build_mem_type_table(void)
487 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 487 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
488 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 488 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
489 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 489 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
490 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 490 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
491 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 491 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
492 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; 492 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
493 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 493 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
494 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; 494 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
495 } 495 }
496 } 496 }
497 497
@@ -502,15 +502,15 @@ static void __init build_mem_type_table(void)
502 if (cpu_arch >= CPU_ARCH_ARMv6) { 502 if (cpu_arch >= CPU_ARCH_ARMv6) {
503 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 503 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
504 /* Non-cacheable Normal is XCB = 001 */ 504 /* Non-cacheable Normal is XCB = 001 */
505 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 505 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
506 PMD_SECT_BUFFERED; 506 PMD_SECT_BUFFERED;
507 } else { 507 } else {
508 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 508 /* For both ARMv6 and non-TEX-remapping ARMv7 */
509 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 509 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
510 PMD_SECT_TEX(1); 510 PMD_SECT_TEX(1);
511 } 511 }
512 } else { 512 } else {
513 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 513 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
514 } 514 }
515 515
516#ifdef CONFIG_ARM_LPAE 516#ifdef CONFIG_ARM_LPAE
@@ -543,10 +543,10 @@ static void __init build_mem_type_table(void)
543 543
544 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 544 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
545 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 545 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
546 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 546 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
547 mem_types[MT_MEMORY].prot_pte |= kern_pgprot; 547 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
548 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; 548 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
549 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; 549 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
550 mem_types[MT_ROM].prot_sect |= cp->pmd; 550 mem_types[MT_ROM].prot_sect |= cp->pmd;
551 551
552 switch (cp->pmd) { 552 switch (cp->pmd) {