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-rw-r--r--arch/arm/mach-tegra/fuse.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index c1afb2738769..f946d129423c 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -34,6 +34,7 @@
34int tegra_sku_id; 34int tegra_sku_id;
35int tegra_cpu_process_id; 35int tegra_cpu_process_id;
36int tegra_core_process_id; 36int tegra_core_process_id;
37int tegra_chip_id;
37enum tegra_revision tegra_revision; 38enum tegra_revision tegra_revision;
38 39
39/* The BCT to use at boot is specified by board straps that can be read 40/* The BCT to use at boot is specified by board straps that can be read
@@ -66,12 +67,9 @@ static inline bool get_spare_fuse(int bit)
66 return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); 67 return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
67} 68}
68 69
69static enum tegra_revision tegra_get_revision(void) 70static enum tegra_revision tegra_get_revision(u32 id)
70{ 71{
71 void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
72 u32 id = readl(chip_id);
73 u32 minor_rev = (id >> 16) & 0xf; 72 u32 minor_rev = (id >> 16) & 0xf;
74 u32 chipid = (id >> 8) & 0xff;
75 73
76 switch (minor_rev) { 74 switch (minor_rev) {
77 case 1: 75 case 1:
@@ -79,7 +77,8 @@ static enum tegra_revision tegra_get_revision(void)
79 case 2: 77 case 2:
80 return TEGRA_REVISION_A02; 78 return TEGRA_REVISION_A02;
81 case 3: 79 case 3:
82 if (chipid == 0x20 && (get_spare_fuse(18) || get_spare_fuse(19))) 80 if (tegra_chip_id == TEGRA20 &&
81 (get_spare_fuse(18) || get_spare_fuse(19)))
83 return TEGRA_REVISION_A03p; 82 return TEGRA_REVISION_A03p;
84 else 83 else
85 return TEGRA_REVISION_A03; 84 return TEGRA_REVISION_A03;
@@ -92,6 +91,8 @@ static enum tegra_revision tegra_get_revision(void)
92 91
93void tegra_init_fuse(void) 92void tegra_init_fuse(void)
94{ 93{
94 u32 id;
95
95 u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); 96 u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
96 reg |= 1 << 28; 97 reg |= 1 << 28;
97 writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); 98 writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
@@ -108,10 +109,13 @@ void tegra_init_fuse(void)
108 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); 109 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
109 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; 110 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
110 111
111 tegra_revision = tegra_get_revision(); 112 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
113 tegra_chip_id = (id >> 8) & 0xff;
114
115 tegra_revision = tegra_get_revision(id);
112 116
113 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", 117 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
114 tegra_revision_name[tegra_get_revision()], 118 tegra_revision_name[tegra_revision],
115 tegra_sku_id, tegra_cpu_process_id, 119 tegra_sku_id, tegra_cpu_process_id,
116 tegra_core_process_id); 120 tegra_core_process_id);
117} 121}