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-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts26
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi413
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts16
-rw-r--r--arch/arm/mach-exynos/Kconfig29
-rw-r--r--arch/arm/mach-exynos/Makefile5
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c14
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c1247
-rw-r--r--arch/arm/mach-exynos/common.c449
-rw-r--r--arch/arm/mach-exynos/common.h37
-rw-r--r--arch/arm/mach-exynos/dev-ahci.c4
-rw-r--r--arch/arm/mach-exynos/dev-audio.c4
-rw-r--r--arch/arm/mach-exynos/dev-uart.c78
-rw-r--r--arch/arm/mach-exynos/dma.c6
-rw-r--r--arch/arm/mach-exynos/include/mach/debug-macro.S9
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h597
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h41
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-clock.h62
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h20
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos/include/mach/uncompress.h17
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c78
-rw-r--r--arch/arm/mach-exynos/mct.c23
-rw-r--r--arch/arm/mach-exynos/platsmp.c9
-rw-r--r--arch/arm/mach-exynos/setup-i2c0.c9
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c1
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c11
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c7
-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c2
-rw-r--r--arch/arm/mach-tegra/common.c4
-rw-r--r--arch/arm/mach-tegra/flowctrl.c62
-rw-r--r--arch/arm/mach-tegra/flowctrl.h5
-rw-r--r--arch/arm/mach-tegra/fuse.c18
-rw-r--r--arch/arm/mach-tegra/fuse.h4
-rw-r--r--arch/arm/mach-tegra/headsmp.S167
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h3
-rw-r--r--arch/arm/mach-tegra/include/mach/powergate.h15
-rw-r--r--arch/arm/mach-tegra/platsmp.c137
-rw-r--r--arch/arm/mach-tegra/powergate.c53
-rw-r--r--arch/arm/mach-tegra/reset.c84
-rw-r--r--arch/arm/mach-tegra/reset.h50
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c31
-rw-r--r--arch/arm/mach-ux500/board-mop500.c74
-rw-r--r--arch/arm/mach-ux500/board-mop500.h8
-rw-r--r--arch/arm/mach-ux500/board-u5500-sdi.c4
-rw-r--r--arch/arm/mach-ux500/board-u5500.c27
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c36
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c44
-rw-r--r--arch/arm/mach-ux500/cpu.c75
-rw-r--r--arch/arm/mach-ux500/devices-common.c79
-rw-r--r--arch/arm/mach-ux500/devices-common.h83
-rw-r--r--arch/arm/mach-ux500/devices-db5500.h116
-rw-r--r--arch/arm/mach-ux500/devices-db8500.h176
-rw-r--r--arch/arm/mach-ux500/dma-db5500.c3
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h3
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h10
-rw-r--r--arch/arm/mach-ux500/include/mach/usb.h4
-rw-r--r--arch/arm/mach-ux500/usb.c7
-rw-r--r--arch/arm/plat-s5p/Kconfig8
-rw-r--r--arch/arm/plat-s5p/Makefile3
-rw-r--r--arch/arm/plat-s5p/clock.c36
-rw-r--r--arch/arm/plat-s5p/irq-pm.c25
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h10
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/uncompress.h2
-rw-r--r--arch/arm/plat-samsung/irq-vic-timer.c16
70 files changed, 3998 insertions, 719 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0106f75530c0..dcb088e868fe 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
180machine-$(CONFIG_ARCH_S5PC100) := s5pc100 180machine-$(CONFIG_ARCH_S5PC100) := s5pc100
181machine-$(CONFIG_ARCH_S5PV210) := s5pv210 181machine-$(CONFIG_ARCH_S5PV210) := s5pv210
182machine-$(CONFIG_ARCH_EXYNOS4) := exynos 182machine-$(CONFIG_ARCH_EXYNOS4) := exynos
183machine-$(CONFIG_ARCH_EXYNOS5) := exynos
183machine-$(CONFIG_ARCH_SA1100) := sa1100 184machine-$(CONFIG_ARCH_SA1100) := sa1100
184machine-$(CONFIG_ARCH_SHARK) := shark 185machine-$(CONFIG_ARCH_SHARK) := shark
185machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 186machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644
index 000000000000..399d17b231d2
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,26 @@
1/*
2 * SAMSUNG SMDK5250 board device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/dts-v1/;
13/include/ "exynos5250.dtsi"
14
15/ {
16 model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
17 compatible = "samsung,smdk5250", "samsung,exynos5250";
18
19 memory {
20 reg = <0x40000000 0x80000000>;
21 };
22
23 chosen {
24 bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
25 };
26};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644
index 000000000000..dfc433599436
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -0,0 +1,413 @@
1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20/include/ "skeleton.dtsi"
21
22/ {
23 compatible = "samsung,exynos5250";
24 interrupt-parent = <&gic>;
25
26 gic:interrupt-controller@10490000 {
27 compatible = "arm,cortex-a9-gic";
28 #interrupt-cells = <3>;
29 interrupt-controller;
30 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
31 };
32
33 watchdog {
34 compatible = "samsung,s3c2410-wdt";
35 reg = <0x101D0000 0x100>;
36 interrupts = <0 42 0>;
37 };
38
39 rtc {
40 compatible = "samsung,s3c6410-rtc";
41 reg = <0x101E0000 0x100>;
42 interrupts = <0 43 0>, <0 44 0>;
43 };
44
45 sdhci@12200000 {
46 compatible = "samsung,exynos4210-sdhci";
47 reg = <0x12200000 0x100>;
48 interrupts = <0 75 0>;
49 };
50
51 sdhci@12210000 {
52 compatible = "samsung,exynos4210-sdhci";
53 reg = <0x12210000 0x100>;
54 interrupts = <0 76 0>;
55 };
56
57 sdhci@12220000 {
58 compatible = "samsung,exynos4210-sdhci";
59 reg = <0x12220000 0x100>;
60 interrupts = <0 77 0>;
61 };
62
63 sdhci@12230000 {
64 compatible = "samsung,exynos4210-sdhci";
65 reg = <0x12230000 0x100>;
66 interrupts = <0 78 0>;
67 };
68
69 serial@12C00000 {
70 compatible = "samsung,exynos4210-uart";
71 reg = <0x12C00000 0x100>;
72 interrupts = <0 51 0>;
73 };
74
75 serial@12C10000 {
76 compatible = "samsung,exynos4210-uart";
77 reg = <0x12C10000 0x100>;
78 interrupts = <0 52 0>;
79 };
80
81 serial@12C20000 {
82 compatible = "samsung,exynos4210-uart";
83 reg = <0x12C20000 0x100>;
84 interrupts = <0 53 0>;
85 };
86
87 serial@12C30000 {
88 compatible = "samsung,exynos4210-uart";
89 reg = <0x12C30000 0x100>;
90 interrupts = <0 54 0>;
91 };
92
93 i2c@12C60000 {
94 compatible = "samsung,s3c2440-i2c";
95 reg = <0x12C60000 0x100>;
96 interrupts = <0 56 0>;
97 };
98
99 i2c@12C70000 {
100 compatible = "samsung,s3c2440-i2c";
101 reg = <0x12C70000 0x100>;
102 interrupts = <0 57 0>;
103 };
104
105 i2c@12C80000 {
106 compatible = "samsung,s3c2440-i2c";
107 reg = <0x12C80000 0x100>;
108 interrupts = <0 58 0>;
109 };
110
111 i2c@12C90000 {
112 compatible = "samsung,s3c2440-i2c";
113 reg = <0x12C90000 0x100>;
114 interrupts = <0 59 0>;
115 };
116
117 i2c@12CA0000 {
118 compatible = "samsung,s3c2440-i2c";
119 reg = <0x12CA0000 0x100>;
120 interrupts = <0 60 0>;
121 };
122
123 i2c@12CB0000 {
124 compatible = "samsung,s3c2440-i2c";
125 reg = <0x12CB0000 0x100>;
126 interrupts = <0 61 0>;
127 };
128
129 i2c@12CC0000 {
130 compatible = "samsung,s3c2440-i2c";
131 reg = <0x12CC0000 0x100>;
132 interrupts = <0 62 0>;
133 };
134
135 i2c@12CD0000 {
136 compatible = "samsung,s3c2440-i2c";
137 reg = <0x12CD0000 0x100>;
138 interrupts = <0 63 0>;
139 };
140
141 amba {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "arm,amba-bus";
145 interrupt-parent = <&gic>;
146 ranges;
147
148 pdma0: pdma@121A0000 {
149 compatible = "arm,pl330", "arm,primecell";
150 reg = <0x121A0000 0x1000>;
151 interrupts = <0 34 0>;
152 };
153
154 pdma1: pdma@121B0000 {
155 compatible = "arm,pl330", "arm,primecell";
156 reg = <0x121B0000 0x1000>;
157 interrupts = <0 35 0>;
158 };
159
160 mdma0: pdma@10800000 {
161 compatible = "arm,pl330", "arm,primecell";
162 reg = <0x10800000 0x1000>;
163 interrupts = <0 33 0>;
164 };
165
166 mdma1: pdma@11C10000 {
167 compatible = "arm,pl330", "arm,primecell";
168 reg = <0x11C10000 0x1000>;
169 interrupts = <0 124 0>;
170 };
171 };
172
173 gpio-controllers {
174 #address-cells = <1>;
175 #size-cells = <1>;
176 gpio-controller;
177 ranges;
178
179 gpa0: gpio-controller@11400000 {
180 compatible = "samsung,exynos4-gpio";
181 reg = <0x11400000 0x20>;
182 #gpio-cells = <4>;
183 };
184
185 gpa1: gpio-controller@11400020 {
186 compatible = "samsung,exynos4-gpio";
187 reg = <0x11400020 0x20>;
188 #gpio-cells = <4>;
189 };
190
191 gpa2: gpio-controller@11400040 {
192 compatible = "samsung,exynos4-gpio";
193 reg = <0x11400040 0x20>;
194 #gpio-cells = <4>;
195 };
196
197 gpb0: gpio-controller@11400060 {
198 compatible = "samsung,exynos4-gpio";
199 reg = <0x11400060 0x20>;
200 #gpio-cells = <4>;
201 };
202
203 gpb1: gpio-controller@11400080 {
204 compatible = "samsung,exynos4-gpio";
205 reg = <0x11400080 0x20>;
206 #gpio-cells = <4>;
207 };
208
209 gpb2: gpio-controller@114000A0 {
210 compatible = "samsung,exynos4-gpio";
211 reg = <0x114000A0 0x20>;
212 #gpio-cells = <4>;
213 };
214
215 gpb3: gpio-controller@114000C0 {
216 compatible = "samsung,exynos4-gpio";
217 reg = <0x114000C0 0x20>;
218 #gpio-cells = <4>;
219 };
220
221 gpc0: gpio-controller@114000E0 {
222 compatible = "samsung,exynos4-gpio";
223 reg = <0x114000E0 0x20>;
224 #gpio-cells = <4>;
225 };
226
227 gpc1: gpio-controller@11400100 {
228 compatible = "samsung,exynos4-gpio";
229 reg = <0x11400100 0x20>;
230 #gpio-cells = <4>;
231 };
232
233 gpc2: gpio-controller@11400120 {
234 compatible = "samsung,exynos4-gpio";
235 reg = <0x11400120 0x20>;
236 #gpio-cells = <4>;
237 };
238
239 gpc3: gpio-controller@11400140 {
240 compatible = "samsung,exynos4-gpio";
241 reg = <0x11400140 0x20>;
242 #gpio-cells = <4>;
243 };
244
245 gpd0: gpio-controller@11400160 {
246 compatible = "samsung,exynos4-gpio";
247 reg = <0x11400160 0x20>;
248 #gpio-cells = <4>;
249 };
250
251 gpd1: gpio-controller@11400180 {
252 compatible = "samsung,exynos4-gpio";
253 reg = <0x11400180 0x20>;
254 #gpio-cells = <4>;
255 };
256
257 gpy0: gpio-controller@114001A0 {
258 compatible = "samsung,exynos4-gpio";
259 reg = <0x114001A0 0x20>;
260 #gpio-cells = <4>;
261 };
262
263 gpy1: gpio-controller@114001C0 {
264 compatible = "samsung,exynos4-gpio";
265 reg = <0x114001C0 0x20>;
266 #gpio-cells = <4>;
267 };
268
269 gpy2: gpio-controller@114001E0 {
270 compatible = "samsung,exynos4-gpio";
271 reg = <0x114001E0 0x20>;
272 #gpio-cells = <4>;
273 };
274
275 gpy3: gpio-controller@11400200 {
276 compatible = "samsung,exynos4-gpio";
277 reg = <0x11400200 0x20>;
278 #gpio-cells = <4>;
279 };
280
281 gpy4: gpio-controller@11400220 {
282 compatible = "samsung,exynos4-gpio";
283 reg = <0x11400220 0x20>;
284 #gpio-cells = <4>;
285 };
286
287 gpy5: gpio-controller@11400240 {
288 compatible = "samsung,exynos4-gpio";
289 reg = <0x11400240 0x20>;
290 #gpio-cells = <4>;
291 };
292
293 gpy6: gpio-controller@11400260 {
294 compatible = "samsung,exynos4-gpio";
295 reg = <0x11400260 0x20>;
296 #gpio-cells = <4>;
297 };
298
299 gpx0: gpio-controller@11400C00 {
300 compatible = "samsung,exynos4-gpio";
301 reg = <0x11400C00 0x20>;
302 #gpio-cells = <4>;
303 };
304
305 gpx1: gpio-controller@11400C20 {
306 compatible = "samsung,exynos4-gpio";
307 reg = <0x11400C20 0x20>;
308 #gpio-cells = <4>;
309 };
310
311 gpx2: gpio-controller@11400C40 {
312 compatible = "samsung,exynos4-gpio";
313 reg = <0x11400C40 0x20>;
314 #gpio-cells = <4>;
315 };
316
317 gpx3: gpio-controller@11400C60 {
318 compatible = "samsung,exynos4-gpio";
319 reg = <0x11400C60 0x20>;
320 #gpio-cells = <4>;
321 };
322
323 gpe0: gpio-controller@13400000 {
324 compatible = "samsung,exynos4-gpio";
325 reg = <0x13400000 0x20>;
326 #gpio-cells = <4>;
327 };
328
329 gpe1: gpio-controller@13400020 {
330 compatible = "samsung,exynos4-gpio";
331 reg = <0x13400020 0x20>;
332 #gpio-cells = <4>;
333 };
334
335 gpf0: gpio-controller@13400040 {
336 compatible = "samsung,exynos4-gpio";
337 reg = <0x13400040 0x20>;
338 #gpio-cells = <4>;
339 };
340
341 gpf1: gpio-controller@13400060 {
342 compatible = "samsung,exynos4-gpio";
343 reg = <0x13400060 0x20>;
344 #gpio-cells = <4>;
345 };
346
347 gpg0: gpio-controller@13400080 {
348 compatible = "samsung,exynos4-gpio";
349 reg = <0x13400080 0x20>;
350 #gpio-cells = <4>;
351 };
352
353 gpg1: gpio-controller@134000A0 {
354 compatible = "samsung,exynos4-gpio";
355 reg = <0x134000A0 0x20>;
356 #gpio-cells = <4>;
357 };
358
359 gpg2: gpio-controller@134000C0 {
360 compatible = "samsung,exynos4-gpio";
361 reg = <0x134000C0 0x20>;
362 #gpio-cells = <4>;
363 };
364
365 gph0: gpio-controller@134000E0 {
366 compatible = "samsung,exynos4-gpio";
367 reg = <0x134000E0 0x20>;
368 #gpio-cells = <4>;
369 };
370
371 gph1: gpio-controller@13400100 {
372 compatible = "samsung,exynos4-gpio";
373 reg = <0x13400100 0x20>;
374 #gpio-cells = <4>;
375 };
376
377 gpv0: gpio-controller@10D10000 {
378 compatible = "samsung,exynos4-gpio";
379 reg = <0x10D10000 0x20>;
380 #gpio-cells = <4>;
381 };
382
383 gpv1: gpio-controller@10D10020 {
384 compatible = "samsung,exynos4-gpio";
385 reg = <0x10D10020 0x20>;
386 #gpio-cells = <4>;
387 };
388
389 gpv2: gpio-controller@10D10040 {
390 compatible = "samsung,exynos4-gpio";
391 reg = <0x10D10040 0x20>;
392 #gpio-cells = <4>;
393 };
394
395 gpv3: gpio-controller@10D10060 {
396 compatible = "samsung,exynos4-gpio";
397 reg = <0x10D10060 0x20>;
398 #gpio-cells = <4>;
399 };
400
401 gpv4: gpio-controller@10D10080 {
402 compatible = "samsung,exynos4-gpio";
403 reg = <0x10D10080 0x20>;
404 #gpio-cells = <4>;
405 };
406
407 gpz: gpio-controller@03860000 {
408 compatible = "samsung,exynos4-gpio";
409 reg = <0x03860000 0x20>;
410 #gpio-cells = <4>;
411 };
412 };
413};
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 73263501f581..ac3fb7558459 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -14,6 +14,22 @@
14 clock-frequency = < 408000000 >; 14 clock-frequency = < 408000000 >;
15 }; 15 };
16 16
17 serial@70006040 {
18 status = "disable";
19 };
20
21 serial@70006200 {
22 status = "disable";
23 };
24
25 serial@70006300 {
26 status = "disable";
27 };
28
29 serial@70006400 {
30 status = "disable";
31 };
32
17 i2c@7000c000 { 33 i2c@7000c000 {
18 clock-frequency = <100000>; 34 clock-frequency = <100000>;
19 }; 35 };
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 2bf7d6e23989..0491ceef1cda 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
11 11
12menu "SAMSUNG EXYNOS SoCs Support" 12menu "SAMSUNG EXYNOS SoCs Support"
13 13
14choice
15 prompt "EXYNOS System Type"
16 default ARCH_EXYNOS4
17
18config ARCH_EXYNOS4 14config ARCH_EXYNOS4
19 bool "SAMSUNG EXYNOS4" 15 bool "SAMSUNG EXYNOS4"
16 default y
20 select HAVE_SMP 17 select HAVE_SMP
21 select MIGHT_HAVE_CACHE_L2X0 18 select MIGHT_HAVE_CACHE_L2X0
22 help 19 help
23 Samsung EXYNOS4 SoCs based systems 20 Samsung EXYNOS4 SoCs based systems
24 21
25endchoice 22config ARCH_EXYNOS5
23 bool "SAMSUNG EXYNOS5"
24 select HAVE_SMP
25 help
26 Samsung EXYNOS5 (Cortex-A15) SoC based systems
26 27
27comment "EXYNOS SoCs" 28comment "EXYNOS SoCs"
28 29
@@ -56,6 +57,13 @@ config SOC_EXYNOS4412
56 help 57 help
57 Enable EXYNOS4412 SoC support 58 Enable EXYNOS4412 SoC support
58 59
60config SOC_EXYNOS5250
61 bool "SAMSUNG EXYNOS5250"
62 default y
63 depends on ARCH_EXYNOS5
64 help
65 Enable EXYNOS5250 SoC support
66
59config EXYNOS4_MCT 67config EXYNOS4_MCT
60 bool 68 bool
61 default y 69 default y
@@ -356,7 +364,7 @@ config MACH_SMDK4412
356 Machine support for Samsung SMDK4412 364 Machine support for Samsung SMDK4412
357endif 365endif
358 366
359comment "Flattened Device Tree based board for Exynos4 based SoC" 367comment "Flattened Device Tree based board for EXYNOS SoCs"
360 368
361config MACH_EXYNOS4_DT 369config MACH_EXYNOS4_DT
362 bool "Samsung Exynos4 Machine using device tree" 370 bool "Samsung Exynos4 Machine using device tree"
@@ -370,6 +378,15 @@ config MACH_EXYNOS4_DT
370 Note: This is under development and not all peripherals can be supported 378 Note: This is under development and not all peripherals can be supported
371 with this machine file. 379 with this machine file.
372 380
381config MACH_EXYNOS5_DT
382 bool "SAMSUNG EXYNOS5 Machine using device tree"
383 select SOC_EXYNOS5250
384 select USE_OF
385 select ARM_AMBA
386 help
387 Machine support for Samsung Exynos4 machine with device tree enabled.
388 Select this if a fdt blob is available for the EXYNOS4 SoC based board.
389
373if ARCH_EXYNOS4 390if ARCH_EXYNOS4
374 391
375comment "Configuration for HSMMC 8-bit bus width" 392comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9a4c09896509..8631840d1b5e 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,6 +14,7 @@ obj- :=
14 14
15obj-$(CONFIG_ARCH_EXYNOS) += common.o 15obj-$(CONFIG_ARCH_EXYNOS) += common.o
16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o 16obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
17obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o 18obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o 19obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
19 20
@@ -42,9 +43,11 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
42obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o 43obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
43 44
44obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o 45obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
46obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
45 47
46# device support 48# device support
47 49
50obj-y += dev-uart.o
48obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
49obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o 52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
50obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o 53obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
@@ -52,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
52obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o 55obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
53obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o 56obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
54 57
55obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o 58obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
56obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o 59obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
57obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o 60obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
58obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o 61obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 200159dcb341..df54c2a92225 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -496,11 +496,6 @@ static struct clk exynos4_init_clocks_off[] = {
496 .enable = exynos4_clk_ip_cam_ctrl, 496 .enable = exynos4_clk_ip_cam_ctrl,
497 .ctrlbit = (1 << 3), 497 .ctrlbit = (1 << 3),
498 }, { 498 }, {
499 .name = "fimd",
500 .devname = "exynos4-fb.0",
501 .enable = exynos4_clk_ip_lcd0_ctrl,
502 .ctrlbit = (1 << 0),
503 }, {
504 .name = "hsmmc", 499 .name = "hsmmc",
505 .devname = "s3c-sdhci.0", 500 .devname = "s3c-sdhci.0",
506 .parent = &exynos4_clk_aclk_133.clk, 501 .parent = &exynos4_clk_aclk_133.clk,
@@ -796,6 +791,13 @@ static struct clk exynos4_clk_mdma1 = {
796 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)), 791 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
797}; 792};
798 793
794static struct clk exynos4_clk_fimd0 = {
795 .name = "fimd",
796 .devname = "exynos4-fb.0",
797 .enable = exynos4_clk_ip_lcd0_ctrl,
798 .ctrlbit = (1 << 0),
799};
800
799struct clk *exynos4_clkset_group_list[] = { 801struct clk *exynos4_clkset_group_list[] = {
800 [0] = &clk_ext_xtal_mux, 802 [0] = &clk_ext_xtal_mux,
801 [1] = &clk_xusbxti, 803 [1] = &clk_xusbxti,
@@ -1315,6 +1317,7 @@ static struct clk *exynos4_clk_cdev[] = {
1315 &exynos4_clk_pdma0, 1317 &exynos4_clk_pdma0,
1316 &exynos4_clk_pdma1, 1318 &exynos4_clk_pdma1,
1317 &exynos4_clk_mdma1, 1319 &exynos4_clk_mdma1,
1320 &exynos4_clk_fimd0,
1318}; 1321};
1319 1322
1320static struct clksrc_clk *exynos4_clksrc_cdev[] = { 1323static struct clksrc_clk *exynos4_clksrc_cdev[] = {
@@ -1341,6 +1344,7 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1341 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), 1344 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1342 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), 1345 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1343 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), 1346 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1347 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1344 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), 1348 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1345 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), 1349 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1346 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), 1350 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 000000000000..d013982d0f8e
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1247 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Clock support for EXYNOS5 SoCs
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/syscore_ops.h>
16
17#include <plat/cpu-freq.h>
18#include <plat/clock.h>
19#include <plat/cpu.h>
20#include <plat/pll.h>
21#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h>
23#include <plat/pm.h>
24
25#include <mach/map.h>
26#include <mach/regs-clock.h>
27#include <mach/sysmmu.h>
28
29#include "common.h"
30
31#ifdef CONFIG_PM_SLEEP
32static struct sleep_save exynos5_clock_save[] = {
33 /* will be implemented */
34};
35#endif
36
37static struct clk exynos5_clk_sclk_dptxphy = {
38 .name = "sclk_dptx",
39};
40
41static struct clk exynos5_clk_sclk_hdmi24m = {
42 .name = "sclk_hdmi24m",
43 .rate = 24000000,
44};
45
46static struct clk exynos5_clk_sclk_hdmi27m = {
47 .name = "sclk_hdmi27m",
48 .rate = 27000000,
49};
50
51static struct clk exynos5_clk_sclk_hdmiphy = {
52 .name = "sclk_hdmiphy",
53};
54
55static struct clk exynos5_clk_sclk_usbphy = {
56 .name = "sclk_usbphy",
57 .rate = 48000000,
58};
59
60static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
61{
62 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
63}
64
65static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
66{
67 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
68}
69
70static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
71{
72 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
73}
74
75static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
76{
77 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
78}
79
80static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
81{
82 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
83}
84
85static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
86{
87 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
88}
89
90static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
91{
92 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
93}
94
95static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
96{
97 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
98}
99
100static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
101{
102 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
103}
104
105static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
106{
107 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
108}
109
110static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
111{
112 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
113}
114
115static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
116{
117 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
118}
119
120static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
121{
122 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
123}
124
125static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
126{
127 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
128}
129
130/* Core list of CMU_CPU side */
131
132static struct clksrc_clk exynos5_clk_mout_apll = {
133 .clk = {
134 .name = "mout_apll",
135 },
136 .sources = &clk_src_apll,
137 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
138};
139
140static struct clksrc_clk exynos5_clk_sclk_apll = {
141 .clk = {
142 .name = "sclk_apll",
143 .parent = &exynos5_clk_mout_apll.clk,
144 },
145 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
146};
147
148static struct clksrc_clk exynos5_clk_mout_bpll = {
149 .clk = {
150 .name = "mout_bpll",
151 },
152 .sources = &clk_src_bpll,
153 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
154};
155
156static struct clk *exynos5_clk_src_bpll_user_list[] = {
157 [0] = &clk_fin_mpll,
158 [1] = &exynos5_clk_mout_bpll.clk,
159};
160
161static struct clksrc_sources exynos5_clk_src_bpll_user = {
162 .sources = exynos5_clk_src_bpll_user_list,
163 .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
164};
165
166static struct clksrc_clk exynos5_clk_mout_bpll_user = {
167 .clk = {
168 .name = "mout_bpll_user",
169 },
170 .sources = &exynos5_clk_src_bpll_user,
171 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
172};
173
174static struct clksrc_clk exynos5_clk_mout_cpll = {
175 .clk = {
176 .name = "mout_cpll",
177 },
178 .sources = &clk_src_cpll,
179 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
180};
181
182static struct clksrc_clk exynos5_clk_mout_epll = {
183 .clk = {
184 .name = "mout_epll",
185 },
186 .sources = &clk_src_epll,
187 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
188};
189
190struct clksrc_clk exynos5_clk_mout_mpll = {
191 .clk = {
192 .name = "mout_mpll",
193 },
194 .sources = &clk_src_mpll,
195 .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
196};
197
198static struct clk *exynos_clkset_vpllsrc_list[] = {
199 [0] = &clk_fin_vpll,
200 [1] = &exynos5_clk_sclk_hdmi27m,
201};
202
203static struct clksrc_sources exynos5_clkset_vpllsrc = {
204 .sources = exynos_clkset_vpllsrc_list,
205 .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
206};
207
208static struct clksrc_clk exynos5_clk_vpllsrc = {
209 .clk = {
210 .name = "vpll_src",
211 .enable = exynos5_clksrc_mask_top_ctrl,
212 .ctrlbit = (1 << 0),
213 },
214 .sources = &exynos5_clkset_vpllsrc,
215 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
216};
217
218static struct clk *exynos5_clkset_sclk_vpll_list[] = {
219 [0] = &exynos5_clk_vpllsrc.clk,
220 [1] = &clk_fout_vpll,
221};
222
223static struct clksrc_sources exynos5_clkset_sclk_vpll = {
224 .sources = exynos5_clkset_sclk_vpll_list,
225 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
226};
227
228static struct clksrc_clk exynos5_clk_sclk_vpll = {
229 .clk = {
230 .name = "sclk_vpll",
231 },
232 .sources = &exynos5_clkset_sclk_vpll,
233 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
234};
235
236static struct clksrc_clk exynos5_clk_sclk_pixel = {
237 .clk = {
238 .name = "sclk_pixel",
239 .parent = &exynos5_clk_sclk_vpll.clk,
240 },
241 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
242};
243
244static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
245 [0] = &exynos5_clk_sclk_pixel.clk,
246 [1] = &exynos5_clk_sclk_hdmiphy,
247};
248
249static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
250 .sources = exynos5_clkset_sclk_hdmi_list,
251 .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
252};
253
254static struct clksrc_clk exynos5_clk_sclk_hdmi = {
255 .clk = {
256 .name = "sclk_hdmi",
257 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
258 .ctrlbit = (1 << 20),
259 },
260 .sources = &exynos5_clkset_sclk_hdmi,
261 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
262};
263
264static struct clksrc_clk *exynos5_sclk_tv[] = {
265 &exynos5_clk_sclk_pixel,
266 &exynos5_clk_sclk_hdmi,
267};
268
269static struct clk *exynos5_clk_src_mpll_user_list[] = {
270 [0] = &clk_fin_mpll,
271 [1] = &exynos5_clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources exynos5_clk_src_mpll_user = {
275 .sources = exynos5_clk_src_mpll_user_list,
276 .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
277};
278
279static struct clksrc_clk exynos5_clk_mout_mpll_user = {
280 .clk = {
281 .name = "mout_mpll_user",
282 },
283 .sources = &exynos5_clk_src_mpll_user,
284 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
285};
286
287static struct clk *exynos5_clkset_mout_cpu_list[] = {
288 [0] = &exynos5_clk_mout_apll.clk,
289 [1] = &exynos5_clk_mout_mpll.clk,
290};
291
292static struct clksrc_sources exynos5_clkset_mout_cpu = {
293 .sources = exynos5_clkset_mout_cpu_list,
294 .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
295};
296
297static struct clksrc_clk exynos5_clk_mout_cpu = {
298 .clk = {
299 .name = "mout_cpu",
300 },
301 .sources = &exynos5_clkset_mout_cpu,
302 .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
303};
304
305static struct clksrc_clk exynos5_clk_dout_armclk = {
306 .clk = {
307 .name = "dout_armclk",
308 .parent = &exynos5_clk_mout_cpu.clk,
309 },
310 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
311};
312
313static struct clksrc_clk exynos5_clk_dout_arm2clk = {
314 .clk = {
315 .name = "dout_arm2clk",
316 .parent = &exynos5_clk_dout_armclk.clk,
317 },
318 .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
319};
320
321static struct clk exynos5_clk_armclk = {
322 .name = "armclk",
323 .parent = &exynos5_clk_dout_arm2clk.clk,
324};
325
326/* Core list of CMU_CDREX side */
327
328static struct clk *exynos5_clkset_cdrex_list[] = {
329 [0] = &exynos5_clk_mout_mpll.clk,
330 [1] = &exynos5_clk_mout_bpll.clk,
331};
332
333static struct clksrc_sources exynos5_clkset_cdrex = {
334 .sources = exynos5_clkset_cdrex_list,
335 .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
336};
337
338static struct clksrc_clk exynos5_clk_cdrex = {
339 .clk = {
340 .name = "clk_cdrex",
341 },
342 .sources = &exynos5_clkset_cdrex,
343 .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
344 .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
345};
346
347static struct clksrc_clk exynos5_clk_aclk_acp = {
348 .clk = {
349 .name = "aclk_acp",
350 .parent = &exynos5_clk_mout_mpll.clk,
351 },
352 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
353};
354
355static struct clksrc_clk exynos5_clk_pclk_acp = {
356 .clk = {
357 .name = "pclk_acp",
358 .parent = &exynos5_clk_aclk_acp.clk,
359 },
360 .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
361};
362
363/* Core list of CMU_TOP side */
364
365struct clk *exynos5_clkset_aclk_top_list[] = {
366 [0] = &exynos5_clk_mout_mpll_user.clk,
367 [1] = &exynos5_clk_mout_bpll_user.clk,
368};
369
370struct clksrc_sources exynos5_clkset_aclk = {
371 .sources = exynos5_clkset_aclk_top_list,
372 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
373};
374
375static struct clksrc_clk exynos5_clk_aclk_400 = {
376 .clk = {
377 .name = "aclk_400",
378 },
379 .sources = &exynos5_clkset_aclk,
380 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
381 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
382};
383
384struct clk *exynos5_clkset_aclk_333_166_list[] = {
385 [0] = &exynos5_clk_mout_cpll.clk,
386 [1] = &exynos5_clk_mout_mpll_user.clk,
387};
388
389struct clksrc_sources exynos5_clkset_aclk_333_166 = {
390 .sources = exynos5_clkset_aclk_333_166_list,
391 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
392};
393
394static struct clksrc_clk exynos5_clk_aclk_333 = {
395 .clk = {
396 .name = "aclk_333",
397 },
398 .sources = &exynos5_clkset_aclk_333_166,
399 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
400 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
401};
402
403static struct clksrc_clk exynos5_clk_aclk_166 = {
404 .clk = {
405 .name = "aclk_166",
406 },
407 .sources = &exynos5_clkset_aclk_333_166,
408 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
409 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
410};
411
412static struct clksrc_clk exynos5_clk_aclk_266 = {
413 .clk = {
414 .name = "aclk_266",
415 .parent = &exynos5_clk_mout_mpll_user.clk,
416 },
417 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
418};
419
420static struct clksrc_clk exynos5_clk_aclk_200 = {
421 .clk = {
422 .name = "aclk_200",
423 },
424 .sources = &exynos5_clkset_aclk,
425 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
426 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
427};
428
429static struct clksrc_clk exynos5_clk_aclk_66_pre = {
430 .clk = {
431 .name = "aclk_66_pre",
432 .parent = &exynos5_clk_mout_mpll_user.clk,
433 },
434 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
435};
436
437static struct clksrc_clk exynos5_clk_aclk_66 = {
438 .clk = {
439 .name = "aclk_66",
440 .parent = &exynos5_clk_aclk_66_pre.clk,
441 },
442 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
443};
444
445static struct clk exynos5_init_clocks_off[] = {
446 {
447 .name = "timers",
448 .parent = &exynos5_clk_aclk_66.clk,
449 .enable = exynos5_clk_ip_peric_ctrl,
450 .ctrlbit = (1 << 24),
451 }, {
452 .name = "rtc",
453 .parent = &exynos5_clk_aclk_66.clk,
454 .enable = exynos5_clk_ip_peris_ctrl,
455 .ctrlbit = (1 << 20),
456 }, {
457 .name = "hsmmc",
458 .devname = "s3c-sdhci.0",
459 .parent = &exynos5_clk_aclk_200.clk,
460 .enable = exynos5_clk_ip_fsys_ctrl,
461 .ctrlbit = (1 << 12),
462 }, {
463 .name = "hsmmc",
464 .devname = "s3c-sdhci.1",
465 .parent = &exynos5_clk_aclk_200.clk,
466 .enable = exynos5_clk_ip_fsys_ctrl,
467 .ctrlbit = (1 << 13),
468 }, {
469 .name = "hsmmc",
470 .devname = "s3c-sdhci.2",
471 .parent = &exynos5_clk_aclk_200.clk,
472 .enable = exynos5_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 14),
474 }, {
475 .name = "hsmmc",
476 .devname = "s3c-sdhci.3",
477 .parent = &exynos5_clk_aclk_200.clk,
478 .enable = exynos5_clk_ip_fsys_ctrl,
479 .ctrlbit = (1 << 15),
480 }, {
481 .name = "dwmci",
482 .parent = &exynos5_clk_aclk_200.clk,
483 .enable = exynos5_clk_ip_fsys_ctrl,
484 .ctrlbit = (1 << 16),
485 }, {
486 .name = "sata",
487 .devname = "ahci",
488 .enable = exynos5_clk_ip_fsys_ctrl,
489 .ctrlbit = (1 << 6),
490 }, {
491 .name = "sata_phy",
492 .enable = exynos5_clk_ip_fsys_ctrl,
493 .ctrlbit = (1 << 24),
494 }, {
495 .name = "sata_phy_i2c",
496 .enable = exynos5_clk_ip_fsys_ctrl,
497 .ctrlbit = (1 << 25),
498 }, {
499 .name = "mfc",
500 .devname = "s5p-mfc",
501 .enable = exynos5_clk_ip_mfc_ctrl,
502 .ctrlbit = (1 << 0),
503 }, {
504 .name = "hdmi",
505 .devname = "exynos4-hdmi",
506 .enable = exynos5_clk_ip_disp1_ctrl,
507 .ctrlbit = (1 << 6),
508 }, {
509 .name = "mixer",
510 .devname = "s5p-mixer",
511 .enable = exynos5_clk_ip_disp1_ctrl,
512 .ctrlbit = (1 << 5),
513 }, {
514 .name = "jpeg",
515 .enable = exynos5_clk_ip_gen_ctrl,
516 .ctrlbit = (1 << 2),
517 }, {
518 .name = "dsim0",
519 .enable = exynos5_clk_ip_disp1_ctrl,
520 .ctrlbit = (1 << 3),
521 }, {
522 .name = "iis",
523 .devname = "samsung-i2s.1",
524 .enable = exynos5_clk_ip_peric_ctrl,
525 .ctrlbit = (1 << 20),
526 }, {
527 .name = "iis",
528 .devname = "samsung-i2s.2",
529 .enable = exynos5_clk_ip_peric_ctrl,
530 .ctrlbit = (1 << 21),
531 }, {
532 .name = "pcm",
533 .devname = "samsung-pcm.1",
534 .enable = exynos5_clk_ip_peric_ctrl,
535 .ctrlbit = (1 << 22),
536 }, {
537 .name = "pcm",
538 .devname = "samsung-pcm.2",
539 .enable = exynos5_clk_ip_peric_ctrl,
540 .ctrlbit = (1 << 23),
541 }, {
542 .name = "spdif",
543 .devname = "samsung-spdif",
544 .enable = exynos5_clk_ip_peric_ctrl,
545 .ctrlbit = (1 << 26),
546 }, {
547 .name = "ac97",
548 .devname = "samsung-ac97",
549 .enable = exynos5_clk_ip_peric_ctrl,
550 .ctrlbit = (1 << 27),
551 }, {
552 .name = "usbhost",
553 .enable = exynos5_clk_ip_fsys_ctrl ,
554 .ctrlbit = (1 << 18),
555 }, {
556 .name = "usbotg",
557 .enable = exynos5_clk_ip_fsys_ctrl,
558 .ctrlbit = (1 << 7),
559 }, {
560 .name = "gps",
561 .enable = exynos5_clk_ip_gps_ctrl,
562 .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)),
563 }, {
564 .name = "nfcon",
565 .enable = exynos5_clk_ip_fsys_ctrl,
566 .ctrlbit = (1 << 22),
567 }, {
568 .name = "iop",
569 .enable = exynos5_clk_ip_fsys_ctrl,
570 .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
571 }, {
572 .name = "core_iop",
573 .enable = exynos5_clk_ip_core_ctrl,
574 .ctrlbit = ((1 << 21) | (1 << 3)),
575 }, {
576 .name = "mcu_iop",
577 .enable = exynos5_clk_ip_fsys_ctrl,
578 .ctrlbit = (1 << 0),
579 }, {
580 .name = "i2c",
581 .devname = "s3c2440-i2c.0",
582 .parent = &exynos5_clk_aclk_66.clk,
583 .enable = exynos5_clk_ip_peric_ctrl,
584 .ctrlbit = (1 << 6),
585 }, {
586 .name = "i2c",
587 .devname = "s3c2440-i2c.1",
588 .parent = &exynos5_clk_aclk_66.clk,
589 .enable = exynos5_clk_ip_peric_ctrl,
590 .ctrlbit = (1 << 7),
591 }, {
592 .name = "i2c",
593 .devname = "s3c2440-i2c.2",
594 .parent = &exynos5_clk_aclk_66.clk,
595 .enable = exynos5_clk_ip_peric_ctrl,
596 .ctrlbit = (1 << 8),
597 }, {
598 .name = "i2c",
599 .devname = "s3c2440-i2c.3",
600 .parent = &exynos5_clk_aclk_66.clk,
601 .enable = exynos5_clk_ip_peric_ctrl,
602 .ctrlbit = (1 << 9),
603 }, {
604 .name = "i2c",
605 .devname = "s3c2440-i2c.4",
606 .parent = &exynos5_clk_aclk_66.clk,
607 .enable = exynos5_clk_ip_peric_ctrl,
608 .ctrlbit = (1 << 10),
609 }, {
610 .name = "i2c",
611 .devname = "s3c2440-i2c.5",
612 .parent = &exynos5_clk_aclk_66.clk,
613 .enable = exynos5_clk_ip_peric_ctrl,
614 .ctrlbit = (1 << 11),
615 }, {
616 .name = "i2c",
617 .devname = "s3c2440-i2c.6",
618 .parent = &exynos5_clk_aclk_66.clk,
619 .enable = exynos5_clk_ip_peric_ctrl,
620 .ctrlbit = (1 << 12),
621 }, {
622 .name = "i2c",
623 .devname = "s3c2440-i2c.7",
624 .parent = &exynos5_clk_aclk_66.clk,
625 .enable = exynos5_clk_ip_peric_ctrl,
626 .ctrlbit = (1 << 13),
627 }, {
628 .name = "i2c",
629 .devname = "s3c2440-hdmiphy-i2c",
630 .parent = &exynos5_clk_aclk_66.clk,
631 .enable = exynos5_clk_ip_peric_ctrl,
632 .ctrlbit = (1 << 14),
633 }
634};
635
636static struct clk exynos5_init_clocks_on[] = {
637 {
638 .name = "uart",
639 .devname = "s5pv210-uart.0",
640 .enable = exynos5_clk_ip_peric_ctrl,
641 .ctrlbit = (1 << 0),
642 }, {
643 .name = "uart",
644 .devname = "s5pv210-uart.1",
645 .enable = exynos5_clk_ip_peric_ctrl,
646 .ctrlbit = (1 << 1),
647 }, {
648 .name = "uart",
649 .devname = "s5pv210-uart.2",
650 .enable = exynos5_clk_ip_peric_ctrl,
651 .ctrlbit = (1 << 2),
652 }, {
653 .name = "uart",
654 .devname = "s5pv210-uart.3",
655 .enable = exynos5_clk_ip_peric_ctrl,
656 .ctrlbit = (1 << 3),
657 }, {
658 .name = "uart",
659 .devname = "s5pv210-uart.4",
660 .enable = exynos5_clk_ip_peric_ctrl,
661 .ctrlbit = (1 << 4),
662 }, {
663 .name = "uart",
664 .devname = "s5pv210-uart.5",
665 .enable = exynos5_clk_ip_peric_ctrl,
666 .ctrlbit = (1 << 5),
667 }
668};
669
670static struct clk exynos5_clk_pdma0 = {
671 .name = "dma",
672 .devname = "dma-pl330.0",
673 .enable = exynos5_clk_ip_fsys_ctrl,
674 .ctrlbit = (1 << 1),
675};
676
677static struct clk exynos5_clk_pdma1 = {
678 .name = "dma",
679 .devname = "dma-pl330.1",
680 .enable = exynos5_clk_ip_fsys_ctrl,
681 .ctrlbit = (1 << 1),
682};
683
684static struct clk exynos5_clk_mdma1 = {
685 .name = "dma",
686 .devname = "dma-pl330.2",
687 .enable = exynos5_clk_ip_gen_ctrl,
688 .ctrlbit = (1 << 4),
689};
690
691struct clk *exynos5_clkset_group_list[] = {
692 [0] = &clk_ext_xtal_mux,
693 [1] = NULL,
694 [2] = &exynos5_clk_sclk_hdmi24m,
695 [3] = &exynos5_clk_sclk_dptxphy,
696 [4] = &exynos5_clk_sclk_usbphy,
697 [5] = &exynos5_clk_sclk_hdmiphy,
698 [6] = &exynos5_clk_mout_mpll_user.clk,
699 [7] = &exynos5_clk_mout_epll.clk,
700 [8] = &exynos5_clk_sclk_vpll.clk,
701 [9] = &exynos5_clk_mout_cpll.clk,
702};
703
704struct clksrc_sources exynos5_clkset_group = {
705 .sources = exynos5_clkset_group_list,
706 .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
707};
708
709/* Possible clock sources for aclk_266_gscl_sub Mux */
710static struct clk *clk_src_gscl_266_list[] = {
711 [0] = &clk_ext_xtal_mux,
712 [1] = &exynos5_clk_aclk_266.clk,
713};
714
715static struct clksrc_sources clk_src_gscl_266 = {
716 .sources = clk_src_gscl_266_list,
717 .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
718};
719
720static struct clksrc_clk exynos5_clk_dout_mmc0 = {
721 .clk = {
722 .name = "dout_mmc0",
723 },
724 .sources = &exynos5_clkset_group,
725 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
726 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
727};
728
729static struct clksrc_clk exynos5_clk_dout_mmc1 = {
730 .clk = {
731 .name = "dout_mmc1",
732 },
733 .sources = &exynos5_clkset_group,
734 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
735 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
736};
737
738static struct clksrc_clk exynos5_clk_dout_mmc2 = {
739 .clk = {
740 .name = "dout_mmc2",
741 },
742 .sources = &exynos5_clkset_group,
743 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
744 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
745};
746
747static struct clksrc_clk exynos5_clk_dout_mmc3 = {
748 .clk = {
749 .name = "dout_mmc3",
750 },
751 .sources = &exynos5_clkset_group,
752 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
753 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
754};
755
756static struct clksrc_clk exynos5_clk_dout_mmc4 = {
757 .clk = {
758 .name = "dout_mmc4",
759 },
760 .sources = &exynos5_clkset_group,
761 .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
762 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
763};
764
765static struct clksrc_clk exynos5_clk_sclk_uart0 = {
766 .clk = {
767 .name = "uclk1",
768 .devname = "exynos4210-uart.0",
769 .enable = exynos5_clksrc_mask_peric0_ctrl,
770 .ctrlbit = (1 << 0),
771 },
772 .sources = &exynos5_clkset_group,
773 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
774 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
775};
776
777static struct clksrc_clk exynos5_clk_sclk_uart1 = {
778 .clk = {
779 .name = "uclk1",
780 .devname = "exynos4210-uart.1",
781 .enable = exynos5_clksrc_mask_peric0_ctrl,
782 .ctrlbit = (1 << 4),
783 },
784 .sources = &exynos5_clkset_group,
785 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
786 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
787};
788
789static struct clksrc_clk exynos5_clk_sclk_uart2 = {
790 .clk = {
791 .name = "uclk1",
792 .devname = "exynos4210-uart.2",
793 .enable = exynos5_clksrc_mask_peric0_ctrl,
794 .ctrlbit = (1 << 8),
795 },
796 .sources = &exynos5_clkset_group,
797 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
798 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
799};
800
801static struct clksrc_clk exynos5_clk_sclk_uart3 = {
802 .clk = {
803 .name = "uclk1",
804 .devname = "exynos4210-uart.3",
805 .enable = exynos5_clksrc_mask_peric0_ctrl,
806 .ctrlbit = (1 << 12),
807 },
808 .sources = &exynos5_clkset_group,
809 .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
810 .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
811};
812
813static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
814 .clk = {
815 .name = "sclk_mmc",
816 .devname = "s3c-sdhci.0",
817 .parent = &exynos5_clk_dout_mmc0.clk,
818 .enable = exynos5_clksrc_mask_fsys_ctrl,
819 .ctrlbit = (1 << 0),
820 },
821 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
822};
823
824static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
825 .clk = {
826 .name = "sclk_mmc",
827 .devname = "s3c-sdhci.1",
828 .parent = &exynos5_clk_dout_mmc1.clk,
829 .enable = exynos5_clksrc_mask_fsys_ctrl,
830 .ctrlbit = (1 << 4),
831 },
832 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
833};
834
835static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
836 .clk = {
837 .name = "sclk_mmc",
838 .devname = "s3c-sdhci.2",
839 .parent = &exynos5_clk_dout_mmc2.clk,
840 .enable = exynos5_clksrc_mask_fsys_ctrl,
841 .ctrlbit = (1 << 8),
842 },
843 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
844};
845
846static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
847 .clk = {
848 .name = "sclk_mmc",
849 .devname = "s3c-sdhci.3",
850 .parent = &exynos5_clk_dout_mmc3.clk,
851 .enable = exynos5_clksrc_mask_fsys_ctrl,
852 .ctrlbit = (1 << 12),
853 },
854 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
855};
856
857static struct clksrc_clk exynos5_clksrcs[] = {
858 {
859 .clk = {
860 .name = "sclk_dwmci",
861 .parent = &exynos5_clk_dout_mmc4.clk,
862 .enable = exynos5_clksrc_mask_fsys_ctrl,
863 .ctrlbit = (1 << 16),
864 },
865 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
866 }, {
867 .clk = {
868 .name = "sclk_fimd",
869 .devname = "s3cfb.1",
870 .enable = exynos5_clksrc_mask_disp1_0_ctrl,
871 .ctrlbit = (1 << 0),
872 },
873 .sources = &exynos5_clkset_group,
874 .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
875 .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
876 }, {
877 .clk = {
878 .name = "aclk_266_gscl",
879 },
880 .sources = &clk_src_gscl_266,
881 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
882 }, {
883 .clk = {
884 .name = "sclk_g3d",
885 .devname = "mali-t604.0",
886 .enable = exynos5_clk_block_ctrl,
887 .ctrlbit = (1 << 1),
888 },
889 .sources = &exynos5_clkset_aclk,
890 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
891 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
892 }, {
893 .clk = {
894 .name = "sclk_gscl_wrap",
895 .devname = "s5p-mipi-csis.0",
896 .enable = exynos5_clksrc_mask_gscl_ctrl,
897 .ctrlbit = (1 << 24),
898 },
899 .sources = &exynos5_clkset_group,
900 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
901 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
902 }, {
903 .clk = {
904 .name = "sclk_gscl_wrap",
905 .devname = "s5p-mipi-csis.1",
906 .enable = exynos5_clksrc_mask_gscl_ctrl,
907 .ctrlbit = (1 << 28),
908 },
909 .sources = &exynos5_clkset_group,
910 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
911 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
912 }, {
913 .clk = {
914 .name = "sclk_cam0",
915 .enable = exynos5_clksrc_mask_gscl_ctrl,
916 .ctrlbit = (1 << 16),
917 },
918 .sources = &exynos5_clkset_group,
919 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
920 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
921 }, {
922 .clk = {
923 .name = "sclk_cam1",
924 .enable = exynos5_clksrc_mask_gscl_ctrl,
925 .ctrlbit = (1 << 20),
926 },
927 .sources = &exynos5_clkset_group,
928 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
929 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
930 }, {
931 .clk = {
932 .name = "sclk_jpeg",
933 .parent = &exynos5_clk_mout_cpll.clk,
934 },
935 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
936 },
937};
938
939/* Clock initialization code */
940static struct clksrc_clk *exynos5_sysclks[] = {
941 &exynos5_clk_mout_apll,
942 &exynos5_clk_sclk_apll,
943 &exynos5_clk_mout_bpll,
944 &exynos5_clk_mout_bpll_user,
945 &exynos5_clk_mout_cpll,
946 &exynos5_clk_mout_epll,
947 &exynos5_clk_mout_mpll,
948 &exynos5_clk_mout_mpll_user,
949 &exynos5_clk_vpllsrc,
950 &exynos5_clk_sclk_vpll,
951 &exynos5_clk_mout_cpu,
952 &exynos5_clk_dout_armclk,
953 &exynos5_clk_dout_arm2clk,
954 &exynos5_clk_cdrex,
955 &exynos5_clk_aclk_400,
956 &exynos5_clk_aclk_333,
957 &exynos5_clk_aclk_266,
958 &exynos5_clk_aclk_200,
959 &exynos5_clk_aclk_166,
960 &exynos5_clk_aclk_66_pre,
961 &exynos5_clk_aclk_66,
962 &exynos5_clk_dout_mmc0,
963 &exynos5_clk_dout_mmc1,
964 &exynos5_clk_dout_mmc2,
965 &exynos5_clk_dout_mmc3,
966 &exynos5_clk_dout_mmc4,
967 &exynos5_clk_aclk_acp,
968 &exynos5_clk_pclk_acp,
969};
970
971static struct clk *exynos5_clk_cdev[] = {
972 &exynos5_clk_pdma0,
973 &exynos5_clk_pdma1,
974 &exynos5_clk_mdma1,
975};
976
977static struct clksrc_clk *exynos5_clksrc_cdev[] = {
978 &exynos5_clk_sclk_uart0,
979 &exynos5_clk_sclk_uart1,
980 &exynos5_clk_sclk_uart2,
981 &exynos5_clk_sclk_uart3,
982 &exynos5_clk_sclk_mmc0,
983 &exynos5_clk_sclk_mmc1,
984 &exynos5_clk_sclk_mmc2,
985 &exynos5_clk_sclk_mmc3,
986};
987
988static struct clk_lookup exynos5_clk_lookup[] = {
989 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
990 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
991 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
992 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
993 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
994 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
995 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
996 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
997 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
998 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
999 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1000};
1001
1002static unsigned long exynos5_epll_get_rate(struct clk *clk)
1003{
1004 return clk->rate;
1005}
1006
1007static struct clk *exynos5_clks[] __initdata = {
1008 &exynos5_clk_sclk_hdmi27m,
1009 &exynos5_clk_sclk_hdmiphy,
1010 &clk_fout_bpll,
1011 &clk_fout_cpll,
1012 &exynos5_clk_armclk,
1013};
1014
1015static u32 epll_div[][6] = {
1016 { 192000000, 0, 48, 3, 1, 0 },
1017 { 180000000, 0, 45, 3, 1, 0 },
1018 { 73728000, 1, 73, 3, 3, 47710 },
1019 { 67737600, 1, 90, 4, 3, 20762 },
1020 { 49152000, 0, 49, 3, 3, 9961 },
1021 { 45158400, 0, 45, 3, 3, 10381 },
1022 { 180633600, 0, 45, 3, 1, 10381 },
1023};
1024
1025static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1026{
1027 unsigned int epll_con, epll_con_k;
1028 unsigned int i;
1029 unsigned int tmp;
1030 unsigned int epll_rate;
1031 unsigned int locktime;
1032 unsigned int lockcnt;
1033
1034 /* Return if nothing changed */
1035 if (clk->rate == rate)
1036 return 0;
1037
1038 if (clk->parent)
1039 epll_rate = clk_get_rate(clk->parent);
1040 else
1041 epll_rate = clk_ext_xtal_mux.rate;
1042
1043 if (epll_rate != 24000000) {
1044 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1045 return -EINVAL;
1046 }
1047
1048 epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1049 epll_con &= ~(0x1 << 27 | \
1050 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1051 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1052 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1053
1054 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1055 if (epll_div[i][0] == rate) {
1056 epll_con_k = epll_div[i][5] << 0;
1057 epll_con |= epll_div[i][1] << 27;
1058 epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1059 epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1060 epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1061 break;
1062 }
1063 }
1064
1065 if (i == ARRAY_SIZE(epll_div)) {
1066 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1067 __func__);
1068 return -EINVAL;
1069 }
1070
1071 epll_rate /= 1000000;
1072
1073 /* 3000 max_cycls : specification data */
1074 locktime = 3000 / epll_rate * epll_div[i][3];
1075 lockcnt = locktime * 10000 / (10000 / epll_rate);
1076
1077 __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1078
1079 __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1080 __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1081
1082 do {
1083 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1084 } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1085
1086 clk->rate = rate;
1087
1088 return 0;
1089}
1090
1091static struct clk_ops exynos5_epll_ops = {
1092 .get_rate = exynos5_epll_get_rate,
1093 .set_rate = exynos5_epll_set_rate,
1094};
1095
1096static int xtal_rate;
1097
1098static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1099{
1100 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1101}
1102
1103static struct clk_ops exynos5_fout_apll_ops = {
1104 .get_rate = exynos5_fout_apll_get_rate,
1105};
1106
1107#ifdef CONFIG_PM
1108static int exynos5_clock_suspend(void)
1109{
1110 s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1111
1112 return 0;
1113}
1114
1115static void exynos5_clock_resume(void)
1116{
1117 s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1118}
1119#else
1120#define exynos5_clock_suspend NULL
1121#define exynos5_clock_resume NULL
1122#endif
1123
1124struct syscore_ops exynos5_clock_syscore_ops = {
1125 .suspend = exynos5_clock_suspend,
1126 .resume = exynos5_clock_resume,
1127};
1128
1129void __init_or_cpufreq exynos5_setup_clocks(void)
1130{
1131 struct clk *xtal_clk;
1132 unsigned long apll;
1133 unsigned long bpll;
1134 unsigned long cpll;
1135 unsigned long mpll;
1136 unsigned long epll;
1137 unsigned long vpll;
1138 unsigned long vpllsrc;
1139 unsigned long xtal;
1140 unsigned long armclk;
1141 unsigned long mout_cdrex;
1142 unsigned long aclk_400;
1143 unsigned long aclk_333;
1144 unsigned long aclk_266;
1145 unsigned long aclk_200;
1146 unsigned long aclk_166;
1147 unsigned long aclk_66;
1148 unsigned int ptr;
1149
1150 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1151
1152 xtal_clk = clk_get(NULL, "xtal");
1153 BUG_ON(IS_ERR(xtal_clk));
1154
1155 xtal = clk_get_rate(xtal_clk);
1156
1157 xtal_rate = xtal;
1158
1159 clk_put(xtal_clk);
1160
1161 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1162
1163 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1164 bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1165 cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1166 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1167 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1168 __raw_readl(EXYNOS5_EPLL_CON1));
1169
1170 vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1171 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1172 __raw_readl(EXYNOS5_VPLL_CON1));
1173
1174 clk_fout_apll.ops = &exynos5_fout_apll_ops;
1175 clk_fout_bpll.rate = bpll;
1176 clk_fout_cpll.rate = cpll;
1177 clk_fout_mpll.rate = mpll;
1178 clk_fout_epll.rate = epll;
1179 clk_fout_vpll.rate = vpll;
1180
1181 printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1182 "M=%ld, E=%ld V=%ld",
1183 apll, bpll, cpll, mpll, epll, vpll);
1184
1185 armclk = clk_get_rate(&exynos5_clk_armclk);
1186 mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1187
1188 aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1189 aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1190 aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1191 aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1192 aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1193 aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1194
1195 printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1196 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1197 "ACLK166=%ld, ACLK66=%ld\n",
1198 armclk, mout_cdrex, aclk_400,
1199 aclk_333, aclk_266, aclk_200,
1200 aclk_166, aclk_66);
1201
1202
1203 clk_fout_epll.ops = &exynos5_epll_ops;
1204
1205 if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1206 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1207 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1208
1209 clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1210 clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1211
1212 clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1213 clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1214
1215 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1216 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1217}
1218
1219void __init exynos5_register_clocks(void)
1220{
1221 int ptr;
1222
1223 s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1224
1225 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1226 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1227
1228 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1229 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1230
1231 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1232 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1233
1234 s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1235 s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1236
1237 s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1238 for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1239 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1240
1241 s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1242 s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1243 clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1244
1245 register_syscore_ops(&exynos5_clock_syscore_ops);
1246 s3c_pwmclk_init();
1247}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d67e21e526e6..e6cc50e94a58 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,14 @@
53static const char name_exynos4210[] = "EXYNOS4210"; 53static const char name_exynos4210[] = "EXYNOS4210";
54static const char name_exynos4212[] = "EXYNOS4212"; 54static const char name_exynos4212[] = "EXYNOS4212";
55static const char name_exynos4412[] = "EXYNOS4412"; 55static const char name_exynos4412[] = "EXYNOS4412";
56static const char name_exynos5250[] = "EXYNOS5250";
57
58static void exynos4_map_io(void);
59static void exynos5_map_io(void);
60static void exynos4_init_clocks(int xtal);
61static void exynos5_init_clocks(int xtal);
62static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
63static int exynos_init(void);
56 64
57static struct cpu_table cpu_ids[] __initdata = { 65static struct cpu_table cpu_ids[] __initdata = {
58 { 66 {
@@ -60,7 +68,7 @@ static struct cpu_table cpu_ids[] __initdata = {
60 .idmask = EXYNOS4_CPU_MASK, 68 .idmask = EXYNOS4_CPU_MASK,
61 .map_io = exynos4_map_io, 69 .map_io = exynos4_map_io,
62 .init_clocks = exynos4_init_clocks, 70 .init_clocks = exynos4_init_clocks,
63 .init_uarts = exynos4_init_uarts, 71 .init_uarts = exynos_init_uarts,
64 .init = exynos_init, 72 .init = exynos_init,
65 .name = name_exynos4210, 73 .name = name_exynos4210,
66 }, { 74 }, {
@@ -68,7 +76,7 @@ static struct cpu_table cpu_ids[] __initdata = {
68 .idmask = EXYNOS4_CPU_MASK, 76 .idmask = EXYNOS4_CPU_MASK,
69 .map_io = exynos4_map_io, 77 .map_io = exynos4_map_io,
70 .init_clocks = exynos4_init_clocks, 78 .init_clocks = exynos4_init_clocks,
71 .init_uarts = exynos4_init_uarts, 79 .init_uarts = exynos_init_uarts,
72 .init = exynos_init, 80 .init = exynos_init,
73 .name = name_exynos4212, 81 .name = name_exynos4212,
74 }, { 82 }, {
@@ -76,9 +84,17 @@ static struct cpu_table cpu_ids[] __initdata = {
76 .idmask = EXYNOS4_CPU_MASK, 84 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io, 85 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks, 86 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos4_init_uarts, 87 .init_uarts = exynos_init_uarts,
80 .init = exynos_init, 88 .init = exynos_init,
81 .name = name_exynos4412, 89 .name = name_exynos4412,
90 }, {
91 .idcode = EXYNOS5250_SOC_ID,
92 .idmask = EXYNOS5_SOC_MASK,
93 .map_io = exynos5_map_io,
94 .init_clocks = exynos5_init_clocks,
95 .init_uarts = exynos_init_uarts,
96 .init = exynos_init,
97 .name = name_exynos5250,
82 }, 98 },
83}; 99};
84 100
@@ -87,10 +103,14 @@ static struct cpu_table cpu_ids[] __initdata = {
87static struct map_desc exynos_iodesc[] __initdata = { 103static struct map_desc exynos_iodesc[] __initdata = {
88 { 104 {
89 .virtual = (unsigned long)S5P_VA_CHIPID, 105 .virtual = (unsigned long)S5P_VA_CHIPID,
90 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID), 106 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
91 .length = SZ_4K, 107 .length = SZ_4K,
92 .type = MT_DEVICE, 108 .type = MT_DEVICE,
93 }, { 109 },
110};
111
112static struct map_desc exynos4_iodesc[] __initdata = {
113 {
94 .virtual = (unsigned long)S3C_VA_SYS, 114 .virtual = (unsigned long)S3C_VA_SYS,
95 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), 115 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
96 .length = SZ_64K, 116 .length = SZ_64K,
@@ -140,11 +160,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
140 .pfn = __phys_to_pfn(EXYNOS4_PA_UART), 160 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
141 .length = SZ_512K, 161 .length = SZ_512K,
142 .type = MT_DEVICE, 162 .type = MT_DEVICE,
143 }, 163 }, {
144};
145
146static struct map_desc exynos4_iodesc[] __initdata = {
147 {
148 .virtual = (unsigned long)S5P_VA_CMU, 164 .virtual = (unsigned long)S5P_VA_CMU,
149 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 165 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
150 .length = SZ_128K, 166 .length = SZ_128K,
@@ -195,11 +211,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
195 }, 211 },
196}; 212};
197 213
214static struct map_desc exynos5_iodesc[] __initdata = {
215 {
216 .virtual = (unsigned long)S3C_VA_SYS,
217 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
218 .length = SZ_64K,
219 .type = MT_DEVICE,
220 }, {
221 .virtual = (unsigned long)S3C_VA_TIMER,
222 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
223 .length = SZ_16K,
224 .type = MT_DEVICE,
225 }, {
226 .virtual = (unsigned long)S3C_VA_WATCHDOG,
227 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
228 .length = SZ_4K,
229 .type = MT_DEVICE,
230 }, {
231 .virtual = (unsigned long)S5P_VA_SROMC,
232 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
233 .length = SZ_4K,
234 .type = MT_DEVICE,
235 }, {
236 .virtual = (unsigned long)S5P_VA_SYSTIMER,
237 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
238 .length = SZ_4K,
239 .type = MT_DEVICE,
240 }, {
241 .virtual = (unsigned long)S5P_VA_SYSRAM,
242 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
243 .length = SZ_4K,
244 .type = MT_DEVICE,
245 }, {
246 .virtual = (unsigned long)S5P_VA_CMU,
247 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
248 .length = 144 * SZ_1K,
249 .type = MT_DEVICE,
250 }, {
251 .virtual = (unsigned long)S5P_VA_PMU,
252 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
253 .length = SZ_64K,
254 .type = MT_DEVICE,
255 }, {
256 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
257 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
258 .length = SZ_4K,
259 .type = MT_DEVICE,
260 }, {
261 .virtual = (unsigned long)S3C_VA_UART,
262 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
263 .length = SZ_512K,
264 .type = MT_DEVICE,
265 }, {
266 .virtual = (unsigned long)S5P_VA_GIC_CPU,
267 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
268 .length = SZ_64K,
269 .type = MT_DEVICE,
270 }, {
271 .virtual = (unsigned long)S5P_VA_GIC_DIST,
272 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
273 .length = SZ_64K,
274 .type = MT_DEVICE,
275 },
276};
277
198void exynos4_restart(char mode, const char *cmd) 278void exynos4_restart(char mode, const char *cmd)
199{ 279{
200 __raw_writel(0x1, S5P_SWRESET); 280 __raw_writel(0x1, S5P_SWRESET);
201} 281}
202 282
283void exynos5_restart(char mode, const char *cmd)
284{
285 __raw_writel(0x1, EXYNOS_SWRESET);
286}
287
203/* 288/*
204 * exynos_map_io 289 * exynos_map_io
205 * 290 *
@@ -219,7 +304,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
219 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 304 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
220} 305}
221 306
222void __init exynos4_map_io(void) 307static void __init exynos4_map_io(void)
223{ 308{
224 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 309 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
225 310
@@ -250,7 +335,22 @@ void __init exynos4_map_io(void)
250 s5p_hdmi_setname("exynos4-hdmi"); 335 s5p_hdmi_setname("exynos4-hdmi");
251} 336}
252 337
253void __init exynos4_init_clocks(int xtal) 338static void __init exynos5_map_io(void)
339{
340 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
341
342 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
343 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
344 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
345 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
346
347 /* The I2C bus controllers are directly compatible with s3c2440 */
348 s3c_i2c0_setname("s3c2440-i2c");
349 s3c_i2c1_setname("s3c2440-i2c");
350 s3c_i2c2_setname("s3c2440-i2c");
351}
352
353static void __init exynos4_init_clocks(int xtal)
254{ 354{
255 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 355 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
256 356
@@ -266,6 +366,17 @@ void __init exynos4_init_clocks(int xtal)
266 exynos4_setup_clocks(); 366 exynos4_setup_clocks();
267} 367}
268 368
369static void __init exynos5_init_clocks(int xtal)
370{
371 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
372
373 s3c24xx_register_baseclocks(xtal);
374 s5p_register_clocks(xtal);
375
376 exynos5_register_clocks();
377 exynos5_setup_clocks();
378}
379
269#define COMBINER_ENABLE_SET 0x0 380#define COMBINER_ENABLE_SET 0x0
270#define COMBINER_ENABLE_CLEAR 0x4 381#define COMBINER_ENABLE_CLEAR 0x4
271#define COMBINER_INT_STATUS 0xC 382#define COMBINER_INT_STATUS 0xC
@@ -339,7 +450,14 @@ static struct irq_chip combiner_chip = {
339 450
340static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 451static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
341{ 452{
342 if (combiner_nr >= MAX_COMBINER_NR) 453 unsigned int max_nr;
454
455 if (soc_is_exynos5250())
456 max_nr = EXYNOS5_MAX_COMBINER_NR;
457 else
458 max_nr = EXYNOS4_MAX_COMBINER_NR;
459
460 if (combiner_nr >= max_nr)
343 BUG(); 461 BUG();
344 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) 462 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
345 BUG(); 463 BUG();
@@ -350,8 +468,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
350 unsigned int irq_start) 468 unsigned int irq_start)
351{ 469{
352 unsigned int i; 470 unsigned int i;
471 unsigned int max_nr;
353 472
354 if (combiner_nr >= MAX_COMBINER_NR) 473 if (soc_is_exynos5250())
474 max_nr = EXYNOS5_MAX_COMBINER_NR;
475 else
476 max_nr = EXYNOS4_MAX_COMBINER_NR;
477
478 if (combiner_nr >= max_nr)
355 BUG(); 479 BUG();
356 480
357 combiner_data[combiner_nr].base = base; 481 combiner_data[combiner_nr].base = base;
@@ -394,8 +518,28 @@ void __init exynos4_init_irq(void)
394 of_irq_init(exynos4_dt_irq_match); 518 of_irq_init(exynos4_dt_irq_match);
395#endif 519#endif
396 520
397 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 521 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
522
523 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
524 COMBINER_IRQ(irq, 0));
525 combiner_cascade_irq(irq, IRQ_SPI(irq));
526 }
527
528 /*
529 * The parameters of s5p_init_irq() are for VIC init.
530 * Theses parameters should be NULL and 0 because EXYNOS4
531 * uses GIC instead of VIC.
532 */
533 s5p_init_irq(NULL, 0);
534}
535
536void __init exynos5_init_irq(void)
537{
538 int irq;
539
540 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
398 541
542 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
399 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), 543 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
400 COMBINER_IRQ(irq, 0)); 544 COMBINER_IRQ(irq, 0));
401 combiner_cascade_irq(irq, IRQ_SPI(irq)); 545 combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -414,19 +558,34 @@ struct bus_type exynos4_subsys = {
414 .dev_name = "exynos4-core", 558 .dev_name = "exynos4-core",
415}; 559};
416 560
561struct bus_type exynos5_subsys = {
562 .name = "exynos5-core",
563 .dev_name = "exynos5-core",
564};
565
417static struct device exynos4_dev = { 566static struct device exynos4_dev = {
418 .bus = &exynos4_subsys, 567 .bus = &exynos4_subsys,
419}; 568};
420 569
421static int __init exynos4_core_init(void) 570static struct device exynos5_dev = {
571 .bus = &exynos5_subsys,
572};
573
574static int __init exynos_core_init(void)
422{ 575{
423 return subsys_system_register(&exynos4_subsys, NULL); 576 if (soc_is_exynos5250())
577 return subsys_system_register(&exynos5_subsys, NULL);
578 else
579 return subsys_system_register(&exynos4_subsys, NULL);
424} 580}
425core_initcall(exynos4_core_init); 581core_initcall(exynos_core_init);
426 582
427#ifdef CONFIG_CACHE_L2X0 583#ifdef CONFIG_CACHE_L2X0
428static int __init exynos4_l2x0_cache_init(void) 584static int __init exynos4_l2x0_cache_init(void)
429{ 585{
586 if (soc_is_exynos5250())
587 return 0;
588
430 int ret; 589 int ret;
431 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); 590 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
432 if (!ret) { 591 if (!ret) {
@@ -471,19 +630,47 @@ static int __init exynos4_l2x0_cache_init(void)
471 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); 630 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
472 return 0; 631 return 0;
473} 632}
474
475early_initcall(exynos4_l2x0_cache_init); 633early_initcall(exynos4_l2x0_cache_init);
476#endif 634#endif
477 635
478int __init exynos_init(void) 636static int __init exynos5_l2_cache_init(void)
637{
638 unsigned int val;
639
640 if (!soc_is_exynos5250())
641 return 0;
642
643 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
644 "bic %0, %0, #(1 << 2)\n" /* cache disable */
645 "mcr p15, 0, %0, c1, c0, 0\n"
646 "mrc p15, 1, %0, c9, c0, 2\n"
647 : "=r"(val));
648
649 val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
650
651 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
652 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
653 "orr %0, %0, #(1 << 2)\n" /* cache enable */
654 "mcr p15, 0, %0, c1, c0, 0\n"
655 : : "r"(val));
656
657 return 0;
658}
659early_initcall(exynos5_l2_cache_init);
660
661static int __init exynos_init(void)
479{ 662{
480 printk(KERN_INFO "EXYNOS: Initializing architecture\n"); 663 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
481 return device_register(&exynos4_dev); 664
665 if (soc_is_exynos5250())
666 return device_register(&exynos5_dev);
667 else
668 return device_register(&exynos4_dev);
482} 669}
483 670
484/* uart registration process */ 671/* uart registration process */
485 672
486void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) 673static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
487{ 674{
488 struct s3c2410_uartcfg *tcfg = cfg; 675 struct s3c2410_uartcfg *tcfg = cfg;
489 u32 ucnt; 676 u32 ucnt;
@@ -491,69 +678,138 @@ void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
491 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) 678 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
492 tcfg->has_fracval = 1; 679 tcfg->has_fracval = 1;
493 680
494 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no); 681 if (soc_is_exynos5250())
682 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
683 else
684 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
495} 685}
496 686
687static void __iomem *exynos_eint_base;
688
497static DEFINE_SPINLOCK(eint_lock); 689static DEFINE_SPINLOCK(eint_lock);
498 690
499static unsigned int eint0_15_data[16]; 691static unsigned int eint0_15_data[16];
500 692
501static unsigned int exynos4_get_irq_nr(unsigned int number) 693static inline int exynos4_irq_to_gpio(unsigned int irq)
502{ 694{
503 u32 ret = 0; 695 if (irq < IRQ_EINT(0))
696 return -EINVAL;
504 697
505 switch (number) { 698 irq -= IRQ_EINT(0);
506 case 0 ... 3: 699 if (irq < 8)
507 ret = (number + IRQ_EINT0); 700 return EXYNOS4_GPX0(irq);
508 break; 701
509 case 4 ... 7: 702 irq -= 8;
510 ret = (number + (IRQ_EINT4 - 4)); 703 if (irq < 8)
511 break; 704 return EXYNOS4_GPX1(irq);
512 case 8 ... 15: 705
513 ret = (number + (IRQ_EINT8 - 8)); 706 irq -= 8;
514 break; 707 if (irq < 8)
515 default: 708 return EXYNOS4_GPX2(irq);
516 printk(KERN_ERR "number available : %d\n", number); 709
517 } 710 irq -= 8;
711 if (irq < 8)
712 return EXYNOS4_GPX3(irq);
713
714 return -EINVAL;
715}
716
717static inline int exynos5_irq_to_gpio(unsigned int irq)
718{
719 if (irq < IRQ_EINT(0))
720 return -EINVAL;
721
722 irq -= IRQ_EINT(0);
723 if (irq < 8)
724 return EXYNOS5_GPX0(irq);
725
726 irq -= 8;
727 if (irq < 8)
728 return EXYNOS5_GPX1(irq);
729
730 irq -= 8;
731 if (irq < 8)
732 return EXYNOS5_GPX2(irq);
518 733
519 return ret; 734 irq -= 8;
735 if (irq < 8)
736 return EXYNOS5_GPX3(irq);
737
738 return -EINVAL;
520} 739}
521 740
522static inline void exynos4_irq_eint_mask(struct irq_data *data) 741static unsigned int exynos4_eint0_15_src_int[16] = {
742 EXYNOS4_IRQ_EINT0,
743 EXYNOS4_IRQ_EINT1,
744 EXYNOS4_IRQ_EINT2,
745 EXYNOS4_IRQ_EINT3,
746 EXYNOS4_IRQ_EINT4,
747 EXYNOS4_IRQ_EINT5,
748 EXYNOS4_IRQ_EINT6,
749 EXYNOS4_IRQ_EINT7,
750 EXYNOS4_IRQ_EINT8,
751 EXYNOS4_IRQ_EINT9,
752 EXYNOS4_IRQ_EINT10,
753 EXYNOS4_IRQ_EINT11,
754 EXYNOS4_IRQ_EINT12,
755 EXYNOS4_IRQ_EINT13,
756 EXYNOS4_IRQ_EINT14,
757 EXYNOS4_IRQ_EINT15,
758};
759
760static unsigned int exynos5_eint0_15_src_int[16] = {
761 EXYNOS5_IRQ_EINT0,
762 EXYNOS5_IRQ_EINT1,
763 EXYNOS5_IRQ_EINT2,
764 EXYNOS5_IRQ_EINT3,
765 EXYNOS5_IRQ_EINT4,
766 EXYNOS5_IRQ_EINT5,
767 EXYNOS5_IRQ_EINT6,
768 EXYNOS5_IRQ_EINT7,
769 EXYNOS5_IRQ_EINT8,
770 EXYNOS5_IRQ_EINT9,
771 EXYNOS5_IRQ_EINT10,
772 EXYNOS5_IRQ_EINT11,
773 EXYNOS5_IRQ_EINT12,
774 EXYNOS5_IRQ_EINT13,
775 EXYNOS5_IRQ_EINT14,
776 EXYNOS5_IRQ_EINT15,
777};
778static inline void exynos_irq_eint_mask(struct irq_data *data)
523{ 779{
524 u32 mask; 780 u32 mask;
525 781
526 spin_lock(&eint_lock); 782 spin_lock(&eint_lock);
527 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); 783 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
528 mask |= eint_irq_to_bit(data->irq); 784 mask |= EINT_OFFSET_BIT(data->irq);
529 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); 785 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
530 spin_unlock(&eint_lock); 786 spin_unlock(&eint_lock);
531} 787}
532 788
533static void exynos4_irq_eint_unmask(struct irq_data *data) 789static void exynos_irq_eint_unmask(struct irq_data *data)
534{ 790{
535 u32 mask; 791 u32 mask;
536 792
537 spin_lock(&eint_lock); 793 spin_lock(&eint_lock);
538 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); 794 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
539 mask &= ~(eint_irq_to_bit(data->irq)); 795 mask &= ~(EINT_OFFSET_BIT(data->irq));
540 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); 796 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
541 spin_unlock(&eint_lock); 797 spin_unlock(&eint_lock);
542} 798}
543 799
544static inline void exynos4_irq_eint_ack(struct irq_data *data) 800static inline void exynos_irq_eint_ack(struct irq_data *data)
545{ 801{
546 __raw_writel(eint_irq_to_bit(data->irq), 802 __raw_writel(EINT_OFFSET_BIT(data->irq),
547 S5P_EINT_PEND(EINT_REG_NR(data->irq))); 803 EINT_PEND(exynos_eint_base, data->irq));
548} 804}
549 805
550static void exynos4_irq_eint_maskack(struct irq_data *data) 806static void exynos_irq_eint_maskack(struct irq_data *data)
551{ 807{
552 exynos4_irq_eint_mask(data); 808 exynos_irq_eint_mask(data);
553 exynos4_irq_eint_ack(data); 809 exynos_irq_eint_ack(data);
554} 810}
555 811
556static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type) 812static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
557{ 813{
558 int offs = EINT_OFFSET(data->irq); 814 int offs = EINT_OFFSET(data->irq);
559 int shift; 815 int shift;
@@ -590,39 +846,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
590 mask = 0x7 << shift; 846 mask = 0x7 << shift;
591 847
592 spin_lock(&eint_lock); 848 spin_lock(&eint_lock);
593 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); 849 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
594 ctrl &= ~mask; 850 ctrl &= ~mask;
595 ctrl |= newvalue << shift; 851 ctrl |= newvalue << shift;
596 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); 852 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
597 spin_unlock(&eint_lock); 853 spin_unlock(&eint_lock);
598 854
599 switch (offs) { 855 if (soc_is_exynos5250())
600 case 0 ... 7: 856 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
601 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); 857 else
602 break; 858 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
603 case 8 ... 15:
604 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
605 break;
606 case 16 ... 23:
607 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
608 break;
609 case 24 ... 31:
610 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
611 break;
612 default:
613 printk(KERN_ERR "No such irq number %d", offs);
614 }
615 859
616 return 0; 860 return 0;
617} 861}
618 862
619static struct irq_chip exynos4_irq_eint = { 863static struct irq_chip exynos_irq_eint = {
620 .name = "exynos4-eint", 864 .name = "exynos-eint",
621 .irq_mask = exynos4_irq_eint_mask, 865 .irq_mask = exynos_irq_eint_mask,
622 .irq_unmask = exynos4_irq_eint_unmask, 866 .irq_unmask = exynos_irq_eint_unmask,
623 .irq_mask_ack = exynos4_irq_eint_maskack, 867 .irq_mask_ack = exynos_irq_eint_maskack,
624 .irq_ack = exynos4_irq_eint_ack, 868 .irq_ack = exynos_irq_eint_ack,
625 .irq_set_type = exynos4_irq_eint_set_type, 869 .irq_set_type = exynos_irq_eint_set_type,
626#ifdef CONFIG_PM 870#ifdef CONFIG_PM
627 .irq_set_wake = s3c_irqext_wake, 871 .irq_set_wake = s3c_irqext_wake,
628#endif 872#endif
@@ -637,12 +881,12 @@ static struct irq_chip exynos4_irq_eint = {
637 * 881 *
638 * Each EINT pend/mask registers handle eight of them. 882 * Each EINT pend/mask registers handle eight of them.
639 */ 883 */
640static inline void exynos4_irq_demux_eint(unsigned int start) 884static inline void exynos_irq_demux_eint(unsigned int start)
641{ 885{
642 unsigned int irq; 886 unsigned int irq;
643 887
644 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); 888 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
645 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); 889 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
646 890
647 status &= ~mask; 891 status &= ~mask;
648 status &= 0xff; 892 status &= 0xff;
@@ -654,16 +898,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
654 } 898 }
655} 899}
656 900
657static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 901static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
658{ 902{
659 struct irq_chip *chip = irq_get_chip(irq); 903 struct irq_chip *chip = irq_get_chip(irq);
660 chained_irq_enter(chip, desc); 904 chained_irq_enter(chip, desc);
661 exynos4_irq_demux_eint(IRQ_EINT(16)); 905 exynos_irq_demux_eint(IRQ_EINT(16));
662 exynos4_irq_demux_eint(IRQ_EINT(24)); 906 exynos_irq_demux_eint(IRQ_EINT(24));
663 chained_irq_exit(chip, desc); 907 chained_irq_exit(chip, desc);
664} 908}
665 909
666static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 910static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
667{ 911{
668 u32 *irq_data = irq_get_handler_data(irq); 912 u32 *irq_data = irq_get_handler_data(irq);
669 struct irq_chip *chip = irq_get_chip(irq); 913 struct irq_chip *chip = irq_get_chip(irq);
@@ -680,27 +924,44 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
680 chained_irq_exit(chip, desc); 924 chained_irq_exit(chip, desc);
681} 925}
682 926
683static int __init exynos4_init_irq_eint(void) 927static int __init exynos_init_irq_eint(void)
684{ 928{
685 int irq; 929 int irq;
686 930
931 if (soc_is_exynos5250())
932 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
933 else
934 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
935
936 if (exynos_eint_base == NULL) {
937 pr_err("unable to ioremap for EINT base address\n");
938 return -ENOMEM;
939 }
940
687 for (irq = 0 ; irq <= 31 ; irq++) { 941 for (irq = 0 ; irq <= 31 ; irq++) {
688 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, 942 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
689 handle_level_irq); 943 handle_level_irq);
690 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 944 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
691 } 945 }
692 946
693 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); 947 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
694 948
695 for (irq = 0 ; irq <= 15 ; irq++) { 949 for (irq = 0 ; irq <= 15 ; irq++) {
696 eint0_15_data[irq] = IRQ_EINT(irq); 950 eint0_15_data[irq] = IRQ_EINT(irq);
697 951
698 irq_set_handler_data(exynos4_get_irq_nr(irq), 952 if (soc_is_exynos5250()) {
699 &eint0_15_data[irq]); 953 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
700 irq_set_chained_handler(exynos4_get_irq_nr(irq), 954 &eint0_15_data[irq]);
701 exynos4_irq_eint0_15); 955 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
956 exynos_irq_eint0_15);
957 } else {
958 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
959 &eint0_15_data[irq]);
960 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
961 exynos_irq_eint0_15);
962 }
702 } 963 }
703 964
704 return 0; 965 return 0;
705} 966}
706arch_initcall(exynos4_init_irq_eint); 967arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 8c1efe692c20..677b5467df18 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,39 +12,44 @@
12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H 12#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H 13#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
14 14
15extern struct sys_timer exynos4_timer;
16
15void exynos_init_io(struct map_desc *mach_desc, int size); 17void exynos_init_io(struct map_desc *mach_desc, int size);
16void exynos4_init_irq(void); 18void exynos4_init_irq(void);
19void exynos5_init_irq(void);
20void exynos4_restart(char mode, const char *cmd);
21void exynos5_restart(char mode, const char *cmd);
17 22
18#ifdef CONFIG_ARCH_EXYNOS4 23#ifdef CONFIG_ARCH_EXYNOS4
19void exynos4_register_clocks(void); 24void exynos4_register_clocks(void);
20void exynos4_setup_clocks(void); 25void exynos4_setup_clocks(void);
21 26
22void exynos4210_register_clocks(void);
23void exynos4212_register_clocks(void);
24
25#else 27#else
26#define exynos4_register_clocks() 28#define exynos4_register_clocks()
27#define exynos4_setup_clocks() 29#define exynos4_setup_clocks()
30#endif
28 31
29#define exynos4210_register_clocks() 32#ifdef CONFIG_ARCH_EXYNOS5
30#define exynos4212_register_clocks() 33void exynos5_register_clocks(void);
34void exynos5_setup_clocks(void);
35
36#else
37#define exynos5_register_clocks()
38#define exynos5_setup_clocks()
31#endif 39#endif
32 40
33void exynos4_restart(char mode, const char *cmd); 41#ifdef CONFIG_CPU_EXYNOS4210
42void exynos4210_register_clocks(void);
34 43
35extern struct sys_timer exynos4_timer; 44#else
45#define exynos4210_register_clocks()
46#endif
36 47
37#ifdef CONFIG_ARCH_EXYNOS 48#ifdef CONFIG_SOC_EXYNOS4212
38extern int exynos_init(void); 49void exynos4212_register_clocks(void);
39extern void exynos4_map_io(void);
40extern void exynos4_init_clocks(int xtal);
41extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
42 50
43#else 51#else
44#define exynos4_init_clocks NULL 52#define exynos4212_register_clocks()
45#define exynos4_init_uarts NULL
46#define exynos4_map_io NULL
47#define exynos_init NULL
48#endif 53#endif
49 54
50#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ 55#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index f57a3de8e1d2..50ce5b0adcf1 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
242 .flags = IORESOURCE_MEM, 242 .flags = IORESOURCE_MEM,
243 }, 243 },
244 [1] = { 244 [1] = {
245 .start = IRQ_SATA, 245 .start = EXYNOS4_IRQ_SATA,
246 .end = IRQ_SATA, 246 .end = EXYNOS4_IRQ_SATA,
247 .flags = IORESOURCE_IRQ, 247 .flags = IORESOURCE_IRQ,
248 }, 248 },
249}; 249};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 5a9f9c2e53bf..7199e1ae79b4 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
304 .flags = IORESOURCE_DMA, 304 .flags = IORESOURCE_DMA,
305 }, 305 },
306 [4] = { 306 [4] = {
307 .start = IRQ_AC97, 307 .start = EXYNOS4_IRQ_AC97,
308 .end = IRQ_AC97, 308 .end = EXYNOS4_IRQ_AC97,
309 .flags = IORESOURCE_IRQ, 309 .flags = IORESOURCE_IRQ,
310 }, 310 },
311}; 311};
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 000000000000..2e85c022fd16
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Base EXYNOS UART resource and device definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/irq.h>
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/devs.h>
25
26#define EXYNOS_UART_RESOURCE(_series, _nr) \
27static struct resource exynos##_series##_uart##_nr##_resource[] = { \
28 [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
29 [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
30};
31
32EXYNOS_UART_RESOURCE(4, 0)
33EXYNOS_UART_RESOURCE(4, 1)
34EXYNOS_UART_RESOURCE(4, 2)
35EXYNOS_UART_RESOURCE(4, 3)
36
37struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
38 [0] = {
39 .resources = exynos4_uart0_resource,
40 .nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
41 },
42 [1] = {
43 .resources = exynos4_uart1_resource,
44 .nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
45 },
46 [2] = {
47 .resources = exynos4_uart2_resource,
48 .nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
49 },
50 [3] = {
51 .resources = exynos4_uart3_resource,
52 .nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
53 },
54};
55
56EXYNOS_UART_RESOURCE(5, 0)
57EXYNOS_UART_RESOURCE(5, 1)
58EXYNOS_UART_RESOURCE(5, 2)
59EXYNOS_UART_RESOURCE(5, 3)
60
61struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
62 [0] = {
63 .resources = exynos5_uart0_resource,
64 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
65 },
66 [1] = {
67 .resources = exynos5_uart1_resource,
68 .nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
69 },
70 [2] = {
71 .resources = exynos5_uart2_resource,
72 .nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
73 },
74 [3] = {
75 .resources = exynos5_uart3_resource,
76 .nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
77 },
78};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 13607c4328b3..3983abee4264 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -108,7 +108,7 @@ static u8 exynos4212_pdma0_peri[] = {
108struct dma_pl330_platdata exynos4_pdma0_pdata; 108struct dma_pl330_platdata exynos4_pdma0_pdata;
109 109
110static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, 110static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
111 EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata); 111 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
112 112
113static u8 exynos4210_pdma1_peri[] = { 113static u8 exynos4210_pdma1_peri[] = {
114 DMACH_PCM0_RX, 114 DMACH_PCM0_RX,
@@ -174,7 +174,7 @@ static u8 exynos4212_pdma1_peri[] = {
174static struct dma_pl330_platdata exynos4_pdma1_pdata; 174static struct dma_pl330_platdata exynos4_pdma1_pdata;
175 175
176static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, 176static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
177 EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata); 177 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
178 178
179static u8 mdma_peri[] = { 179static u8 mdma_peri[] = {
180 DMACH_MTOM_0, 180 DMACH_MTOM_0,
@@ -193,7 +193,7 @@ static struct dma_pl330_platdata exynos4_mdma1_pdata = {
193}; 193};
194 194
195static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330, 195static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
196 EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata); 196 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
197 197
198static int __init exynos4_dma_init(void) 198static int __init exynos4_dma_init(void)
199{ 199{
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16a67a6..6c857ff0b5d8 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
21 */ 21 */
22 22
23 .macro addruart, rp, rv, tmp 23 .macro addruart, rp, rv, tmp
24 ldr \rp, = S3C_PA_UART 24 mov \rp, #0x10000000
25 ldr \rv, = S3C_VA_UART 25 ldr \rp, [\rp, #0x0]
26 and \rp, \rp, #0xf00000
27 teq \rp, #0x500000 @@ EXYNOS5
28 ldreq \rp, =EXYNOS5_PA_UART
29 movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
30 ldr \rv, =S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0 31#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) 32 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) 33 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1d401c957835..9bee8535d9e0 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/irqs.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - IRQ definitions 5 * EXYNOS - IRQ definitions
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -17,160 +16,450 @@
17 16
18/* PPI: Private Peripheral Interrupt */ 17/* PPI: Private Peripheral Interrupt */
19 18
20#define IRQ_PPI(x) (x+16) 19#define IRQ_PPI(x) (x + 16)
21
22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
23 20
24/* SPI: Shared Peripheral Interrupt */ 21/* SPI: Shared Peripheral Interrupt */
25 22
26#define IRQ_SPI(x) (x+32) 23#define IRQ_SPI(x) (x + 32)
27 24
28#define IRQ_EINT0 IRQ_SPI(16) 25/* COMBINER */
29#define IRQ_EINT1 IRQ_SPI(17) 26
30#define IRQ_EINT2 IRQ_SPI(18) 27#define MAX_IRQ_IN_COMBINER 8
31#define IRQ_EINT3 IRQ_SPI(19) 28#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
32#define IRQ_EINT4 IRQ_SPI(20) 29#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
33#define IRQ_EINT5 IRQ_SPI(21) 30
34#define IRQ_EINT6 IRQ_SPI(22) 31/* For EXYNOS4 and EXYNOS5 */
35#define IRQ_EINT7 IRQ_SPI(23) 32
36#define IRQ_EINT8 IRQ_SPI(24) 33#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
37#define IRQ_EINT9 IRQ_SPI(25) 34
38#define IRQ_EINT10 IRQ_SPI(26) 35#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
39#define IRQ_EINT11 IRQ_SPI(27) 36
40#define IRQ_EINT12 IRQ_SPI(28) 37/* For EXYNOS4 SoCs */
41#define IRQ_EINT13 IRQ_SPI(29) 38
42#define IRQ_EINT14 IRQ_SPI(30) 39#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
43#define IRQ_EINT15 IRQ_SPI(31) 40#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
44#define IRQ_EINT16_31 IRQ_SPI(32) 41#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
45 42#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
46#define IRQ_MDMA0 IRQ_SPI(33) 43#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
47#define IRQ_MDMA1 IRQ_SPI(34) 44#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
48#define IRQ_PDMA0 IRQ_SPI(35) 45#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
49#define IRQ_PDMA1 IRQ_SPI(36) 46#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
50#define IRQ_TIMER0_VIC IRQ_SPI(37) 47#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
51#define IRQ_TIMER1_VIC IRQ_SPI(38) 48#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
52#define IRQ_TIMER2_VIC IRQ_SPI(39) 49#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
53#define IRQ_TIMER3_VIC IRQ_SPI(40) 50#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
54#define IRQ_TIMER4_VIC IRQ_SPI(41) 51#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
55#define IRQ_MCT_L0 IRQ_SPI(42) 52#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
56#define IRQ_WDT IRQ_SPI(43) 53#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
57#define IRQ_RTC_ALARM IRQ_SPI(44) 54#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
58#define IRQ_RTC_TIC IRQ_SPI(45) 55
59#define IRQ_GPIO_XB IRQ_SPI(46) 56#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
60#define IRQ_GPIO_XA IRQ_SPI(47) 57#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
61#define IRQ_MCT_L1 IRQ_SPI(48) 58#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
62 59#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
63#define IRQ_UART0 IRQ_SPI(52) 60#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
64#define IRQ_UART1 IRQ_SPI(53) 61#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
65#define IRQ_UART2 IRQ_SPI(54) 62#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
66#define IRQ_UART3 IRQ_SPI(55) 63#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
67#define IRQ_UART4 IRQ_SPI(56) 64#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
68#define IRQ_MCT_G0 IRQ_SPI(57) 65#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
69#define IRQ_IIC IRQ_SPI(58) 66#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
70#define IRQ_IIC1 IRQ_SPI(59) 67#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
71#define IRQ_IIC2 IRQ_SPI(60) 68#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
72#define IRQ_IIC3 IRQ_SPI(61) 69#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
73#define IRQ_IIC4 IRQ_SPI(62) 70#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
74#define IRQ_IIC5 IRQ_SPI(63) 71#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
75#define IRQ_IIC6 IRQ_SPI(64) 72
76#define IRQ_IIC7 IRQ_SPI(65) 73#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
77#define IRQ_SPI0 IRQ_SPI(66) 74#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
78#define IRQ_SPI1 IRQ_SPI(67) 75#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
79#define IRQ_SPI2 IRQ_SPI(68) 76#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
80 77#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
81#define IRQ_USB_HOST IRQ_SPI(70) 78#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
82#define IRQ_USB_HSOTG IRQ_SPI(71) 79#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
83#define IRQ_MODEM_IF IRQ_SPI(72) 80#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
84#define IRQ_HSMMC0 IRQ_SPI(73) 81#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
85#define IRQ_HSMMC1 IRQ_SPI(74) 82#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
86#define IRQ_HSMMC2 IRQ_SPI(75) 83#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
87#define IRQ_HSMMC3 IRQ_SPI(76) 84#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
88#define IRQ_DWMCI IRQ_SPI(77) 85#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
89 86#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
90#define IRQ_MIPI_CSIS0 IRQ_SPI(78) 87#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
91#define IRQ_MIPI_CSIS1 IRQ_SPI(80) 88#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
92 89#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
93#define IRQ_ONENAND_AUDI IRQ_SPI(82) 90
94#define IRQ_ROTATOR IRQ_SPI(83) 91#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
95#define IRQ_FIMC0 IRQ_SPI(84) 92#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
96#define IRQ_FIMC1 IRQ_SPI(85) 93#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
97#define IRQ_FIMC2 IRQ_SPI(86) 94#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
98#define IRQ_FIMC3 IRQ_SPI(87) 95#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
99#define IRQ_JPEG IRQ_SPI(88) 96#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
100#define IRQ_2D IRQ_SPI(89) 97#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
101#define IRQ_PCIE IRQ_SPI(90) 98#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
102 99
103#define IRQ_MIXER IRQ_SPI(91) 100#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
104#define IRQ_HDMI IRQ_SPI(92) 101#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
105#define IRQ_IIC_HDMIPHY IRQ_SPI(93) 102
106#define IRQ_MFC IRQ_SPI(94) 103#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
107#define IRQ_SDO IRQ_SPI(95) 104#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
108 105#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
109#define IRQ_AUDIO_SS IRQ_SPI(96) 106#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
110#define IRQ_I2S0 IRQ_SPI(97) 107#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
111#define IRQ_I2S1 IRQ_SPI(98) 108#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
112#define IRQ_I2S2 IRQ_SPI(99) 109#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
113#define IRQ_AC97 IRQ_SPI(100) 110#define EXYNOS4_IRQ_2D IRQ_SPI(89)
114 111#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
115#define IRQ_SPDIF IRQ_SPI(104) 112
116#define IRQ_ADC0 IRQ_SPI(105) 113#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
117#define IRQ_PEN0 IRQ_SPI(106) 114#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
118#define IRQ_ADC1 IRQ_SPI(107) 115#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
119#define IRQ_PEN1 IRQ_SPI(108) 116#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
120#define IRQ_KEYPAD IRQ_SPI(109) 117#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
121#define IRQ_PMU IRQ_SPI(110) 118
122#define IRQ_GPS IRQ_SPI(111) 119#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
123#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) 120#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
124#define IRQ_SLIMBUS IRQ_SPI(113) 121#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
125 122#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
126#define IRQ_TSI IRQ_SPI(115) 123#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
127#define IRQ_SATA IRQ_SPI(116) 124
128 125#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
129#define MAX_IRQ_IN_COMBINER 8 126#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
130#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) 127#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
131#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 128#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
132 129#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
133#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) 130#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
134#define IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) 131#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
135#define IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) 132#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
136#define IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) 133#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
137#define IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) 134#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
138#define IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) 135
139#define IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) 136#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
140#define IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) 137#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
141 138
142#define IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) 139#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
143#define IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) 140#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
144#define IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) 141#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
145#define IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) 142#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
146#define IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) 143#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
147#define IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) 144#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
148#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) 145#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
149#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) 146#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
150 147
151#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) 148#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
152#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) 149#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
153#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) 150#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
154 151#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
155#define MAX_COMBINER_NR 16 152#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
156 153#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
157#define IRQ_ADC IRQ_ADC0 154#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
158#define IRQ_TC IRQ_PEN0 155#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
159 156
160#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 157#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
161 158#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
162#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0) 159#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
163#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16) 160
164 161#define EXYNOS4_MAX_COMBINER_NR 16
165/* optional GPIO interrupts */ 162
166#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32) 163#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
167#define IRQ_GPIO1_NR_GROUPS 16 164#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
168#define IRQ_GPIO2_NR_GROUPS 9 165
169#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 166/*
170 167 * For Compatibility:
171#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) 168 * the default is for EXYNOS4, and
169 * for exynos5, should be re-mapped at function
170 */
171
172#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
173#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
174#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
175#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
176#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
177
178#define IRQ_WDT EXYNOS4_IRQ_WDT
179#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
180#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
181#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
182#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
183
184#define IRQ_IIC EXYNOS4_IRQ_IIC
185#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
186#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
187#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
188#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
189#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
190
191#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
192
193#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
194#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
195#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
196#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
197
198#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
199
200#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
201
202#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
203#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
204#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
205#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
206#define IRQ_JPEG EXYNOS4_IRQ_JPEG
207#define IRQ_2D EXYNOS4_IRQ_2D
208
209#define IRQ_MIXER EXYNOS4_IRQ_MIXER
210#define IRQ_HDMI EXYNOS4_IRQ_HDMI
211#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
212#define IRQ_MFC EXYNOS4_IRQ_MFC
213#define IRQ_SDO EXYNOS4_IRQ_SDO
214
215#define IRQ_ADC EXYNOS4_IRQ_ADC0
216#define IRQ_TC EXYNOS4_IRQ_PEN0
217
218#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
219#define IRQ_PMU EXYNOS4_IRQ_PMU
220
221#define IRQ_SYSMMU_MDMA0_0 EXYNOS4_IRQ_SYSMMU_MDMA0_0
222#define IRQ_SYSMMU_SSS_0 EXYNOS4_IRQ_SYSMMU_SSS_0
223#define IRQ_SYSMMU_FIMC0_0 EXYNOS4_IRQ_SYSMMU_FIMC0_0
224#define IRQ_SYSMMU_FIMC1_0 EXYNOS4_IRQ_SYSMMU_FIMC1_0
225#define IRQ_SYSMMU_FIMC2_0 EXYNOS4_IRQ_SYSMMU_FIMC2_0
226#define IRQ_SYSMMU_FIMC3_0 EXYNOS4_IRQ_SYSMMU_FIMC3_0
227#define IRQ_SYSMMU_JPEG_0 EXYNOS4_IRQ_SYSMMU_JPEG_0
228#define IRQ_SYSMMU_2D_0 EXYNOS4_IRQ_SYSMMU_2D_0
229
230#define IRQ_SYSMMU_ROTATOR_0 EXYNOS4_IRQ_SYSMMU_ROTATOR_0
231#define IRQ_SYSMMU_MDMA1_0 EXYNOS4_IRQ_SYSMMU_MDMA1_0
232#define IRQ_SYSMMU_LCD0_M0_0 EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
233#define IRQ_SYSMMU_LCD1_M1_0 EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
234#define IRQ_SYSMMU_TV_M0_0 EXYNOS4_IRQ_SYSMMU_TV_M0_0
235#define IRQ_SYSMMU_MFC_M0_0 EXYNOS4_IRQ_SYSMMU_MFC_M0_0
236#define IRQ_SYSMMU_MFC_M1_0 EXYNOS4_IRQ_SYSMMU_MFC_M1_0
237#define IRQ_SYSMMU_PCIE_0 EXYNOS4_IRQ_SYSMMU_PCIE_0
238
239#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
240#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
241#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
242
243#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
244#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
245
246/* For EXYNOS5 SoCs */
247
248#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
249#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
250#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
251#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
252#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
253#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
254#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
255#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
256#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
257#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
258#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
259#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
260#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
261#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
262#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
263#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
264#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
265#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
266#define EXYNOS5_IRQ_UART0 IRQ_SPI(51)
267#define EXYNOS5_IRQ_UART1 IRQ_SPI(52)
268#define EXYNOS5_IRQ_UART2 IRQ_SPI(53)
269#define EXYNOS5_IRQ_UART3 IRQ_SPI(54)
270#define EXYNOS5_IRQ_UART4 IRQ_SPI(55)
271#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
272#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
273#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
274#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
275#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
276#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
277#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
278#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
279#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
280#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
281#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
282#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
283#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
284#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
285#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
286#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
287#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
288#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
289#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
290#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
291#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
292#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
293#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
294#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
295#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
296#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
297#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
298#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
299#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
300#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
301#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
302#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
303#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
304#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
305#define EXYNOS5_IRQ_2D IRQ_SPI(91)
306#define EXYNOS5_IRQ_SFMC0 IRQ_SPI(92)
307#define EXYNOS5_IRQ_SFMC1 IRQ_SPI(93)
308#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
309#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
310#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
311#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
312#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
313#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
314#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
315#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
316#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
317#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
318#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
319#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
320#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
321
322#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
323#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
324#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
325#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
326#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
327#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
328#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
329#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
330#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)
331
332#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
333#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
334#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
335#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
336#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
337
338#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
339#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(1, 6)
340
341#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
342#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
343#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
344#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
345#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
346#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
347#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
348#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
349
350#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
351#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
352#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
353#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
354#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
355#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
356
357#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
358#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
359#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
360#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
361
362#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
363#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
364#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
365#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
366#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
367#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
368#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
369#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
370
371#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
372#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
373#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(6, 2)
374#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(6, 3)
375#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
376#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
377#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
378#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
379
380#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
381#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
382#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
383#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
384#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
385#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
386#define EXYNOS5_IRQ_SYSMMU_GPSX_0 COMBINER_IRQ(7, 6)
387#define EXYNOS5_IRQ_SYSMMU_GPSX_1 COMBINER_IRQ(7, 7)
388
389#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(8, 5)
390#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(8, 6)
391
392#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
393#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
394
395#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
396#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
397#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
398#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
399#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
400
401#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
402#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
403#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
404#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
405
406#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
407#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
408#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
409
410#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
411#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
412#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
413#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
414#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
415#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
416#define EXYNOS5_IRQ_MCT_G3 COMBINER_IRQ(23, 6)
417
418#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
419#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
420#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
421#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
422#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
423
424#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
425#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
426
427#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
428#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
429
430#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
431#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
432
433#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
434#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
435
436#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
437#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
438
439#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
440#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
441
442#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
443#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
444
445#define EXYNOS5_MAX_COMBINER_NR 32
446
447#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 13
448#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
449#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
450#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
451
452#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
453 EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
454
455#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
456#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
457#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
458#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
459#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
172 460
173/* Set the default NR_IRQS */ 461/* Set the default NR_IRQS */
174#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) 462
463#define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
175 464
176#endif /* __ASM_ARCH_IRQS_H */ 465#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 54307b09813a..024d38ff1718 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,6 +25,7 @@
25 25
26#define EXYNOS4_PA_SYSRAM0 0x02025000 26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000 27#define EXYNOS4_PA_SYSRAM1 0x02020000
28#define EXYNOS5_PA_SYSRAM 0x02020000
28 29
29#define EXYNOS4_PA_FIMC0 0x11800000 30#define EXYNOS4_PA_FIMC0 0x11800000
30#define EXYNOS4_PA_FIMC1 0x11810000 31#define EXYNOS4_PA_FIMC1 0x11810000
@@ -48,14 +49,23 @@
48#define EXYNOS4_PA_ONENAND 0x0C000000 49#define EXYNOS4_PA_ONENAND 0x0C000000
49#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 50#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
50 51
51#define EXYNOS4_PA_CHIPID 0x10000000 52#define EXYNOS_PA_CHIPID 0x10000000
52 53
53#define EXYNOS4_PA_SYSCON 0x10010000 54#define EXYNOS4_PA_SYSCON 0x10010000
55#define EXYNOS5_PA_SYSCON 0x10050100
56
54#define EXYNOS4_PA_PMU 0x10020000 57#define EXYNOS4_PA_PMU 0x10020000
58#define EXYNOS5_PA_PMU 0x10040000
59
55#define EXYNOS4_PA_CMU 0x10030000 60#define EXYNOS4_PA_CMU 0x10030000
61#define EXYNOS5_PA_CMU 0x10010000
56 62
57#define EXYNOS4_PA_SYSTIMER 0x10050000 63#define EXYNOS4_PA_SYSTIMER 0x10050000
64#define EXYNOS5_PA_SYSTIMER 0x101C0000
65
58#define EXYNOS4_PA_WATCHDOG 0x10060000 66#define EXYNOS4_PA_WATCHDOG 0x10060000
67#define EXYNOS5_PA_WATCHDOG 0x101D0000
68
59#define EXYNOS4_PA_RTC 0x10070000 69#define EXYNOS4_PA_RTC 0x10070000
60 70
61#define EXYNOS4_PA_KEYPAD 0x100A0000 71#define EXYNOS4_PA_KEYPAD 0x100A0000
@@ -64,9 +74,12 @@
64#define EXYNOS4_PA_DMC1 0x10410000 74#define EXYNOS4_PA_DMC1 0x10410000
65 75
66#define EXYNOS4_PA_COMBINER 0x10440000 76#define EXYNOS4_PA_COMBINER 0x10440000
77#define EXYNOS5_PA_COMBINER 0x10440000
67 78
68#define EXYNOS4_PA_GIC_CPU 0x10480000 79#define EXYNOS4_PA_GIC_CPU 0x10480000
69#define EXYNOS4_PA_GIC_DIST 0x10490000 80#define EXYNOS4_PA_GIC_DIST 0x10490000
81#define EXYNOS5_PA_GIC_CPU 0x10480000
82#define EXYNOS5_PA_GIC_DIST 0x10490000
70 83
71#define EXYNOS4_PA_COREPERI 0x10500000 84#define EXYNOS4_PA_COREPERI 0x10500000
72#define EXYNOS4_PA_TWD 0x10500600 85#define EXYNOS4_PA_TWD 0x10500600
@@ -97,7 +110,6 @@
97#define EXYNOS4_PA_SPI1 0x13930000 110#define EXYNOS4_PA_SPI1 0x13930000
98#define EXYNOS4_PA_SPI2 0x13940000 111#define EXYNOS4_PA_SPI2 0x13940000
99 112
100
101#define EXYNOS4_PA_GPIO1 0x11400000 113#define EXYNOS4_PA_GPIO1 0x11400000
102#define EXYNOS4_PA_GPIO2 0x11000000 114#define EXYNOS4_PA_GPIO2 0x11000000
103#define EXYNOS4_PA_GPIO3 0x03860000 115#define EXYNOS4_PA_GPIO3 0x03860000
@@ -119,6 +131,7 @@
119#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 131#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
120 132
121#define EXYNOS4_PA_SROMC 0x12570000 133#define EXYNOS4_PA_SROMC 0x12570000
134#define EXYNOS5_PA_SROMC 0x12250000
122 135
123#define EXYNOS4_PA_EHCI 0x12580000 136#define EXYNOS4_PA_EHCI 0x12580000
124#define EXYNOS4_PA_OHCI 0x12590000 137#define EXYNOS4_PA_OHCI 0x12590000
@@ -126,6 +139,7 @@
126#define EXYNOS4_PA_MFC 0x13400000 139#define EXYNOS4_PA_MFC 0x13400000
127 140
128#define EXYNOS4_PA_UART 0x13800000 141#define EXYNOS4_PA_UART 0x13800000
142#define EXYNOS5_PA_UART 0x12C00000
129 143
130#define EXYNOS4_PA_VP 0x12C00000 144#define EXYNOS4_PA_VP 0x12C00000
131#define EXYNOS4_PA_MIXER 0x12C10000 145#define EXYNOS4_PA_MIXER 0x12C10000
@@ -134,6 +148,7 @@
134#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 148#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
135 149
136#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 150#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
151#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
137 152
138#define EXYNOS4_PA_ADC 0x13910000 153#define EXYNOS4_PA_ADC 0x13910000
139#define EXYNOS4_PA_ADC1 0x13911000 154#define EXYNOS4_PA_ADC1 0x13911000
@@ -143,8 +158,10 @@
143#define EXYNOS4_PA_SPDIF 0x139B0000 158#define EXYNOS4_PA_SPDIF 0x139B0000
144 159
145#define EXYNOS4_PA_TIMER 0x139D0000 160#define EXYNOS4_PA_TIMER 0x139D0000
161#define EXYNOS5_PA_TIMER 0x12DD0000
146 162
147#define EXYNOS4_PA_SDRAM 0x40000000 163#define EXYNOS4_PA_SDRAM 0x40000000
164#define EXYNOS5_PA_SDRAM 0x40000000
148 165
149/* Compatibiltiy Defines */ 166/* Compatibiltiy Defines */
150 167
@@ -162,7 +179,6 @@
162#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 179#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
163#define S3C_PA_RTC EXYNOS4_PA_RTC 180#define S3C_PA_RTC EXYNOS4_PA_RTC
164#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 181#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
165#define S3C_PA_UART EXYNOS4_PA_UART
166#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 182#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
167#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 183#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
168#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 184#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
@@ -193,15 +209,18 @@
193 209
194/* Compatibility UART */ 210/* Compatibility UART */
195 211
196#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 212#define EXYNOS4_PA_UART0 0x13800000
213#define EXYNOS4_PA_UART1 0x13810000
214#define EXYNOS4_PA_UART2 0x13820000
215#define EXYNOS4_PA_UART3 0x13830000
216#define EXYNOS4_SZ_UART SZ_256
197 217
198#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET)) 218#define EXYNOS5_PA_UART0 0x12C00000
199#define S5P_PA_UART0 S5P_PA_UART(0) 219#define EXYNOS5_PA_UART1 0x12C10000
200#define S5P_PA_UART1 S5P_PA_UART(1) 220#define EXYNOS5_PA_UART2 0x12C20000
201#define S5P_PA_UART2 S5P_PA_UART(2) 221#define EXYNOS5_PA_UART3 0x12C30000
202#define S5P_PA_UART3 S5P_PA_UART(3) 222#define EXYNOS5_SZ_UART SZ_256
203#define S5P_PA_UART4 S5P_PA_UART(4)
204 223
205#define S5P_SZ_UART SZ_256 224#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
206 225
207#endif /* __ASM_ARCH_MAP_H */ 226#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 1e4abd64a547..e141c1fd68d8 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -253,6 +253,68 @@
253#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) 253#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
254#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) 254#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
255 255
256/* For EXYNOS5250 */
257
258#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
259#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
260#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
261#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
262#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
263
264#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
265
266#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
267
268#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
269#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
270#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
271#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
272#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
273#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
274
275#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
276#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
277#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
278#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
279#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
280#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
281
282#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
283#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
284#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
285#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
286#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
287
288#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
289#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
290#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
291#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
292#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
293#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
294#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
295#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
296#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
297#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
298
299#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
300#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
301#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
302#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
303#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
304#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
305#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
306#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
307#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
308#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
309
310#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
311#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
312#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
313
314#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
315
316#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
317
256/* Compatibility defines and inclusion */ 318/* Compatibility defines and inclusion */
257 319
258#include <mach/regs-pmu.h> 320#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21663a5..e4b5b60dcb85 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
16#include <mach/map.h> 16#include <mach/map.h>
17#include <mach/irqs.h> 17#include <mach/irqs.h>
18 18
19#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
20#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
21#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
22#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
23#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
24
25#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
26
27/* compatibility for plat-s5p/irq-pm.c */
19#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) 28#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4)) 29#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
21 30
@@ -28,15 +37,4 @@
28#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40) 37#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4)) 38#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
30 39
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
38#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
39#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
40#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */ 40#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e938fec..4c53f38b5a9e 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) 31#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
32 32
33#define S5P_SWRESET S5P_PMUREG(0x0400) 33#define S5P_SWRESET S5P_PMUREG(0x0400)
34#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
34 35
35#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) 36#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
36#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) 37#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bcd9acb..493f4f365ddf 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - uncompress code 5 * EXYNOS - uncompress code
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
13#ifndef __ASM_ARCH_UNCOMPRESS_H 12#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H __FILE__ 13#define __ASM_ARCH_UNCOMPRESS_H __FILE__
15 14
15#include <asm/mach-types.h>
16
16#include <mach/map.h> 17#include <mach/map.h>
18
19volatile u8 *uart_base;
20
17#include <plat/uncompress.h> 21#include <plat/uncompress.h>
18 22
19static void arch_detect_cpu(void) 23static void arch_detect_cpu(void)
20{ 24{
21 /* we do not need to do any cpu detection here at the moment. */ 25 if (machine_is_smdk5250())
26 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
27 else
28 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
22 29
23 /* 30 /*
24 * For preventing FIFO overrun or infinite loop of UART console, 31 * For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e6b02fdf1b09..8245f1c761d9 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -37,13 +37,13 @@
37 * data from the device tree. 37 * data from the device tree.
38 */ 38 */
39static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { 39static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0, 40 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
41 "exynos4210-uart.0", NULL), 41 "exynos4210-uart.0", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1, 42 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
43 "exynos4210-uart.1", NULL), 43 "exynos4210-uart.1", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2, 44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
45 "exynos4210-uart.2", NULL), 45 "exynos4210-uart.2", NULL),
46 OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3, 46 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
47 "exynos4210-uart.3", NULL), 47 "exynos4210-uart.3", NULL),
48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0), 48 OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
49 "exynos4-sdhci.0", NULL), 49 "exynos4-sdhci.0", NULL),
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 000000000000..0d26f50081ad
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
1/*
2 * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/of_platform.h>
13#include <linux/serial_core.h>
14
15#include <asm/mach/arch.h>
16#include <asm/hardware/gic.h>
17#include <mach/map.h>
18
19#include <plat/cpu.h>
20#include <plat/regs-serial.h>
21
22#include "common.h"
23
24/*
25 * The following lookup table is used to override device names when devices
26 * are registered from device tree. This is temporarily added to enable
27 * device tree support addition for the EXYNOS5 architecture.
28 *
29 * For drivers that require platform data to be provided from the machine
30 * file, a platform data pointer can also be supplied along with the
31 * devices names. Usually, the platform data elements that cannot be parsed
32 * from the device tree by the drivers (example: function pointers) are
33 * supplied. But it should be noted that this is a temporary mechanism and
34 * at some point, the drivers should be capable of parsing all the platform
35 * data from the device tree.
36 */
37static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
38 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
39 "exynos4210-uart.0", NULL),
40 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
41 "exynos4210-uart.1", NULL),
42 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
43 "exynos4210-uart.2", NULL),
44 OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
45 "exynos4210-uart.3", NULL),
46 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
47 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
48 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
49 {},
50};
51
52static void __init exynos5250_dt_map_io(void)
53{
54 exynos_init_io(NULL, 0);
55 s3c24xx_init_clocks(24000000);
56}
57
58static void __init exynos5250_dt_machine_init(void)
59{
60 of_platform_populate(NULL, of_default_bus_match_table,
61 exynos5250_auxdata_lookup, NULL);
62}
63
64static char const *exynos5250_dt_compat[] __initdata = {
65 "samsung,exynos5250",
66 NULL
67};
68
69DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
70 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
71 .init_irq = exynos5_init_irq,
72 .map_io = exynos5250_dt_map_io,
73 .handle_irq = gic_handle_irq,
74 .init_machine = exynos5250_dt_machine_init,
75 .timer = &exynos4_timer,
76 .dt_compat = exynos5250_dt_compat,
77 .restart = exynos5_restart,
78MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index e8a1caaf1902..897d9a9cf226 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -261,7 +261,10 @@ static void exynos4_clockevent_init(void)
261 mct_comp_device.cpumask = cpumask_of(0); 261 mct_comp_device.cpumask = cpumask_of(0);
262 clockevents_register_device(&mct_comp_device); 262 clockevents_register_device(&mct_comp_device);
263 263
264 setup_irq(IRQ_MCT_G0, &mct_comp_event_irq); 264 if (soc_is_exynos5250())
265 setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
266 else
267 setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
265} 268}
266 269
267#ifdef CONFIG_LOCAL_TIMERS 270#ifdef CONFIG_LOCAL_TIMERS
@@ -412,16 +415,16 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
412 if (mct_int_type == MCT_INT_SPI) { 415 if (mct_int_type == MCT_INT_SPI) {
413 if (cpu == 0) { 416 if (cpu == 0) {
414 mct_tick0_event_irq.dev_id = mevt; 417 mct_tick0_event_irq.dev_id = mevt;
415 evt->irq = IRQ_MCT_L0; 418 evt->irq = EXYNOS4_IRQ_MCT_L0;
416 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); 419 setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
417 } else { 420 } else {
418 mct_tick1_event_irq.dev_id = mevt; 421 mct_tick1_event_irq.dev_id = mevt;
419 evt->irq = IRQ_MCT_L1; 422 evt->irq = EXYNOS4_IRQ_MCT_L1;
420 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); 423 setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
421 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); 424 irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
422 } 425 }
423 } else { 426 } else {
424 enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0); 427 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
425 } 428 }
426 429
427 return 0; 430 return 0;
@@ -437,7 +440,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
437 else 440 else
438 remove_irq(evt->irq, &mct_tick1_event_irq); 441 remove_irq(evt->irq, &mct_tick1_event_irq);
439 else 442 else
440 disable_percpu_irq(IRQ_MCT_LOCALTIMER); 443 disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
441} 444}
442 445
443static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { 446static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -457,11 +460,11 @@ static void __init exynos4_timer_resources(void)
457 if (mct_int_type == MCT_INT_PPI) { 460 if (mct_int_type == MCT_INT_PPI) {
458 int err; 461 int err;
459 462
460 err = request_percpu_irq(IRQ_MCT_LOCALTIMER, 463 err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
461 exynos4_mct_tick_isr, "MCT", 464 exynos4_mct_tick_isr, "MCT",
462 &percpu_mct_tick); 465 &percpu_mct_tick);
463 WARN(err, "MCT: can't request IRQ %d (%d)\n", 466 WARN(err, "MCT: can't request IRQ %d (%d)\n",
464 IRQ_MCT_LOCALTIMER, err); 467 EXYNOS_IRQ_MCT_LOCALTIMER, err);
465 } 468 }
466 469
467 local_timer_register(&exynos4_mct_tick_ops); 470 local_timer_register(&exynos4_mct_tick_ops);
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0f2035a1eb6e..36c3984aaa47 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
166 void __iomem *scu_base = scu_base_addr(); 166 void __iomem *scu_base = scu_base_addr();
167 unsigned int i, ncores; 167 unsigned int i, ncores;
168 168
169 ncores = scu_base ? scu_get_core_count(scu_base) : 1; 169 if (soc_is_exynos5250())
170 ncores = 2;
171 else
172 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
170 173
171 /* sanity check */ 174 /* sanity check */
172 if (ncores > nr_cpu_ids) { 175 if (ncores > nr_cpu_ids) {
@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
183 186
184void __init platform_smp_prepare_cpus(unsigned int max_cpus) 187void __init platform_smp_prepare_cpus(unsigned int max_cpus)
185{ 188{
186 189 if (!soc_is_exynos5250())
187 scu_enable(scu_base_addr()); 190 scu_enable(scu_base_addr());
188 191
189 /* 192 /*
190 * Write the address of secondary startup into the 193 * Write the address of secondary startup into the
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd17c38b..b90d94c17f7c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-exynos4/setup-i2c0.c 2 * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/ 3 * http://www.samsung.com/
6 * 4 *
7 * I2C0 GPIO configuration. 5 * I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
18#include <linux/gpio.h> 16#include <linux/gpio.h>
19#include <plat/iic.h> 17#include <plat/iic.h>
20#include <plat/gpio-cfg.h> 18#include <plat/gpio-cfg.h>
19#include <plat/cpu.h>
21 20
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 21void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 22{
23 if (soc_is_exynos5250())
24 /* will be implemented with gpio function */
25 return;
26
24 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2, 27 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26} 29}
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 262f8def5577..b56dde2732bb 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1186,6 +1186,7 @@ static struct i2c_board_info i2c1_devices[] = {
1186 }, 1186 },
1187}; 1187};
1188 1188
1189
1189#define GPIO_PORT9CR 0xE6051009 1190#define GPIO_PORT9CR 0xE6051009
1190#define GPIO_PORT10CR 0xE605100A 1191#define GPIO_PORT10CR 0xE605100A
1191#define USCCR1 0xE6058144 1192#define USCCR1 0xE6058144
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index bd4253ba05b6..ca609502d6cd 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1327,15 +1327,6 @@ static struct i2c_board_info i2c1_devices[] = {
1327 }, 1327 },
1328}; 1328};
1329 1329
1330static void __init mackerel_map_io(void)
1331{
1332 sh7372_map_io();
1333 /* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
1334 * enough to allocate the frame buffer memory.
1335 */
1336 init_consistent_dma_size(12 << 20);
1337}
1338
1339#define GPIO_PORT9CR 0xE6051009 1330#define GPIO_PORT9CR 0xE6051009
1340#define GPIO_PORT10CR 0xE605100A 1331#define GPIO_PORT10CR 0xE605100A
1341#define GPIO_PORT167CR 0xE60520A7 1332#define GPIO_PORT167CR 0xE60520A7
@@ -1555,7 +1546,7 @@ static void __init mackerel_init(void)
1555} 1546}
1556 1547
1557MACHINE_START(MACKEREL, "mackerel") 1548MACHINE_START(MACKEREL, "mackerel")
1558 .map_io = mackerel_map_io, 1549 .map_io = sh7372_map_io,
1559 .init_early = sh7372_add_early_devices, 1550 .init_early = sh7372_add_early_devices,
1560 .init_irq = sh7372_init_irq, 1551 .init_irq = sh7372_init_irq,
1561 .handle_irq = shmobile_handle_irq_intc, 1552 .handle_irq = shmobile_handle_irq_intc,
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5375325d7ca7..4e818b7de781 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -31,6 +31,7 @@
31#include <linux/sh_intc.h> 31#include <linux/sh_intc.h>
32#include <linux/sh_timer.h> 32#include <linux/sh_timer.h>
33#include <linux/pm_domain.h> 33#include <linux/pm_domain.h>
34#include <linux/dma-mapping.h>
34#include <mach/hardware.h> 35#include <mach/hardware.h>
35#include <mach/sh7372.h> 36#include <mach/sh7372.h>
36#include <mach/common.h> 37#include <mach/common.h>
@@ -54,6 +55,12 @@ static struct map_desc sh7372_io_desc[] __initdata = {
54void __init sh7372_map_io(void) 55void __init sh7372_map_io(void)
55{ 56{
56 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc)); 57 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
58
59 /*
60 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
61 * enough to allocate the frame buffer memory.
62 */
63 init_consistent_dma_size(12 << 20);
57} 64}
58 65
59/* SCIFA0 */ 66/* SCIFA0 */
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1dd2726986cf..d87d968115ec 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,6 +8,7 @@ obj-y += timer.o
8obj-y += pinmux.o 8obj-y += pinmux.o
9obj-y += fuse.o 9obj-y += fuse.o
10obj-y += pmc.o 10obj-y += pmc.o
11obj-y += flowctrl.o
11obj-$(CONFIG_CPU_IDLE) += cpuidle.o 12obj-$(CONFIG_CPU_IDLE) += cpuidle.o
12obj-$(CONFIG_CPU_IDLE) += sleep.o 13obj-$(CONFIG_CPU_IDLE) += sleep.o
13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
@@ -18,6 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o 19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
20obj-$(CONFIG_SMP) += platsmp.o headsmp.o 21obj-$(CONFIG_SMP) += platsmp.o headsmp.o
22obj-$(CONFIG_SMP) += reset.o
21obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 23obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
22obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o 24obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o
23obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o 25obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 96f6c0d030bd..5f7c03e972f3 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -56,7 +56,7 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
56 56
57static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 57static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
58 /* name parent rate enabled */ 58 /* name parent rate enabled */
59 { "uartd", "pll_p", 408000000, true }, 59 { "uarta", "pll_p", 408000000, true },
60 { NULL, NULL, 0, 0}, 60 { NULL, NULL, 0, 0},
61}; 61};
62 62
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 2f86fcca64a6..22df10fb9972 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -27,6 +27,7 @@
27#include <asm/hardware/gic.h> 27#include <asm/hardware/gic.h>
28 28
29#include <mach/iomap.h> 29#include <mach/iomap.h>
30#include <mach/powergate.h>
30 31
31#include "board.h" 32#include "board.h"
32#include "clock.h" 33#include "clock.h"
@@ -118,13 +119,16 @@ void __init tegra20_init_early(void)
118 tegra_clk_init_from_table(tegra20_clk_init_table); 119 tegra_clk_init_from_table(tegra20_clk_init_table);
119 tegra_init_cache(0x331, 0x441); 120 tegra_init_cache(0x331, 0x441);
120 tegra_pmc_init(); 121 tegra_pmc_init();
122 tegra_powergate_init();
121} 123}
122#endif 124#endif
123#ifdef CONFIG_ARCH_TEGRA_3x_SOC 125#ifdef CONFIG_ARCH_TEGRA_3x_SOC
124void __init tegra30_init_early(void) 126void __init tegra30_init_early(void)
125{ 127{
128 tegra_init_fuse();
126 tegra30_init_clocks(); 129 tegra30_init_clocks();
127 tegra_init_cache(0x441, 0x551); 130 tegra_init_cache(0x441, 0x551);
128 tegra_pmc_init(); 131 tegra_pmc_init();
132 tegra_powergate_init();
129} 133}
130#endif 134#endif
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
new file mode 100644
index 000000000000..fef66a7486ed
--- /dev/null
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -0,0 +1,62 @@
1/*
2 * arch/arm/mach-tegra/flowctrl.c
3 *
4 * functions and macros to control the flowcontroller
5 *
6 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24
25#include <mach/iomap.h>
26
27#include "flowctrl.h"
28
29u8 flowctrl_offset_halt_cpu[] = {
30 FLOW_CTRL_HALT_CPU0_EVENTS,
31 FLOW_CTRL_HALT_CPU1_EVENTS,
32 FLOW_CTRL_HALT_CPU1_EVENTS + 8,
33 FLOW_CTRL_HALT_CPU1_EVENTS + 16,
34};
35
36u8 flowctrl_offset_cpu_csr[] = {
37 FLOW_CTRL_CPU0_CSR,
38 FLOW_CTRL_CPU1_CSR,
39 FLOW_CTRL_CPU1_CSR + 8,
40 FLOW_CTRL_CPU1_CSR + 16,
41};
42
43static void flowctrl_update(u8 offset, u32 value)
44{
45 void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
46
47 writel(value, addr);
48
49 /* ensure the update has reached the flow controller */
50 wmb();
51 readl_relaxed(addr);
52}
53
54void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
55{
56 return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
57}
58
59void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
60{
61 return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
62}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 74c6efbe52fa..19428173855e 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -34,4 +34,9 @@
34#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 34#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
35#define FLOW_CTRL_CPU1_CSR 0x18 35#define FLOW_CTRL_CPU1_CSR 0x18
36 36
37#ifndef __ASSEMBLY__
38void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
39void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
40#endif
41
37#endif 42#endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index c1afb2738769..f946d129423c 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -34,6 +34,7 @@
34int tegra_sku_id; 34int tegra_sku_id;
35int tegra_cpu_process_id; 35int tegra_cpu_process_id;
36int tegra_core_process_id; 36int tegra_core_process_id;
37int tegra_chip_id;
37enum tegra_revision tegra_revision; 38enum tegra_revision tegra_revision;
38 39
39/* The BCT to use at boot is specified by board straps that can be read 40/* The BCT to use at boot is specified by board straps that can be read
@@ -66,12 +67,9 @@ static inline bool get_spare_fuse(int bit)
66 return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); 67 return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
67} 68}
68 69
69static enum tegra_revision tegra_get_revision(void) 70static enum tegra_revision tegra_get_revision(u32 id)
70{ 71{
71 void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
72 u32 id = readl(chip_id);
73 u32 minor_rev = (id >> 16) & 0xf; 72 u32 minor_rev = (id >> 16) & 0xf;
74 u32 chipid = (id >> 8) & 0xff;
75 73
76 switch (minor_rev) { 74 switch (minor_rev) {
77 case 1: 75 case 1:
@@ -79,7 +77,8 @@ static enum tegra_revision tegra_get_revision(void)
79 case 2: 77 case 2:
80 return TEGRA_REVISION_A02; 78 return TEGRA_REVISION_A02;
81 case 3: 79 case 3:
82 if (chipid == 0x20 && (get_spare_fuse(18) || get_spare_fuse(19))) 80 if (tegra_chip_id == TEGRA20 &&
81 (get_spare_fuse(18) || get_spare_fuse(19)))
83 return TEGRA_REVISION_A03p; 82 return TEGRA_REVISION_A03p;
84 else 83 else
85 return TEGRA_REVISION_A03; 84 return TEGRA_REVISION_A03;
@@ -92,6 +91,8 @@ static enum tegra_revision tegra_get_revision(void)
92 91
93void tegra_init_fuse(void) 92void tegra_init_fuse(void)
94{ 93{
94 u32 id;
95
95 u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); 96 u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
96 reg |= 1 << 28; 97 reg |= 1 << 28;
97 writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); 98 writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
@@ -108,10 +109,13 @@ void tegra_init_fuse(void)
108 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); 109 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
109 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; 110 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
110 111
111 tegra_revision = tegra_get_revision(); 112 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
113 tegra_chip_id = (id >> 8) & 0xff;
114
115 tegra_revision = tegra_get_revision(id);
112 116
113 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", 117 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
114 tegra_revision_name[tegra_get_revision()], 118 tegra_revision_name[tegra_revision],
115 tegra_sku_id, tegra_cpu_process_id, 119 tegra_sku_id, tegra_cpu_process_id,
116 tegra_core_process_id); 120 tegra_core_process_id);
117} 121}
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index d65d2abf803b..d2107b2cb85a 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -35,9 +35,13 @@ enum tegra_revision {
35#define SKU_ID_AP25E 27 35#define SKU_ID_AP25E 27
36#define SKU_ID_T25E 28 36#define SKU_ID_T25E 28
37 37
38#define TEGRA20 0x20
39#define TEGRA30 0x30
40
38extern int tegra_sku_id; 41extern int tegra_sku_id;
39extern int tegra_cpu_process_id; 42extern int tegra_cpu_process_id;
40extern int tegra_core_process_id; 43extern int tegra_core_process_id;
44extern int tegra_chip_id;
41extern enum tegra_revision tegra_revision; 45extern enum tegra_revision tegra_revision;
42 46
43extern int tegra_bct_strapping; 47extern int tegra_bct_strapping;
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index b5349b2f13d2..fef9c2c51370 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -1,6 +1,23 @@
1#include <linux/linkage.h> 1#include <linux/linkage.h>
2#include <linux/init.h> 2#include <linux/init.h>
3 3
4#include <asm/cache.h>
5
6#include <mach/iomap.h>
7
8#include "flowctrl.h"
9#include "reset.h"
10
11#define APB_MISC_GP_HIDREV 0x804
12#define PMC_SCRATCH41 0x140
13
14#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
15
16 .macro mov32, reg, val
17 movw \reg, #:lower16:\val
18 movt \reg, #:upper16:\val
19 .endm
20
4 .section ".text.head", "ax" 21 .section ".text.head", "ax"
5 __CPUINIT 22 __CPUINIT
6 23
@@ -47,15 +64,149 @@ ENTRY(v7_invalidate_l1)
47 mov pc, lr 64 mov pc, lr
48ENDPROC(v7_invalidate_l1) 65ENDPROC(v7_invalidate_l1)
49 66
67
50ENTRY(tegra_secondary_startup) 68ENTRY(tegra_secondary_startup)
51 msr cpsr_fsxc, #0xd3
52 bl v7_invalidate_l1 69 bl v7_invalidate_l1
53 mrc p15, 0, r0, c0, c0, 5 70 /* Enable coresight */
54 and r0, r0, #15 71 mov32 r0, 0xC5ACCE55
55 ldr r1, =0x6000f100 72 mcr p14, 0, r0, c7, c12, 6
56 str r0, [r1]
571: ldr r2, [r1]
58 cmp r0, r2
59 beq 1b
60 b secondary_startup 73 b secondary_startup
61ENDPROC(tegra_secondary_startup) 74ENDPROC(tegra_secondary_startup)
75
76 .align L1_CACHE_SHIFT
77ENTRY(__tegra_cpu_reset_handler_start)
78
79/*
80 * __tegra_cpu_reset_handler:
81 *
82 * Common handler for all CPU reset events.
83 *
84 * Register usage within the reset handler:
85 *
86 * R7 = CPU present (to the OS) mask
87 * R8 = CPU in LP1 state mask
88 * R9 = CPU in LP2 state mask
89 * R10 = CPU number
90 * R11 = CPU mask
91 * R12 = pointer to reset handler data
92 *
93 * NOTE: This code is copied to IRAM. All code and data accesses
94 * must be position-independent.
95 */
96
97 .align L1_CACHE_SHIFT
98ENTRY(__tegra_cpu_reset_handler)
99
100 cpsid aif, 0x13 @ SVC mode, interrupts disabled
101 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
102 and r10, r10, #0x3 @ R10 = CPU number
103 mov r11, #1
104 mov r11, r11, lsl r10 @ R11 = CPU mask
105 adr r12, __tegra_cpu_reset_handler_data
106
107#ifdef CONFIG_SMP
108 /* Does the OS know about this CPU? */
109 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
110 tst r7, r11 @ if !present
111 bleq __die @ CPU not present (to OS)
112#endif
113
114#ifdef CONFIG_ARCH_TEGRA_2x_SOC
115 /* Are we on Tegra20? */
116 mov32 r6, TEGRA_APB_MISC_BASE
117 ldr r0, [r6, #APB_MISC_GP_HIDREV]
118 and r0, r0, #0xff00
119 cmp r0, #(0x20 << 8)
120 bne 1f
121 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
122 mov32 r6, TEGRA_PMC_BASE
123 mov r0, #0
124 cmp r10, #0
125 strne r0, [r6, #PMC_SCRATCH41]
1261:
127#endif
128
129#ifdef CONFIG_SMP
130 /*
131 * Can only be secondary boot (initial or hotplug) but CPU 0
132 * cannot be here.
133 */
134 cmp r10, #0
135 bleq __die @ CPU0 cannot be here
136 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
137 cmp lr, #0
138 bleq __die @ no secondary startup handler
139 bx lr
140#endif
141
142/*
143 * We don't know why the CPU reset. Just kill it.
144 * The LR register will contain the address we died at + 4.
145 */
146
147__die:
148 sub lr, lr, #4
149 mov32 r7, TEGRA_PMC_BASE
150 str lr, [r7, #PMC_SCRATCH41]
151
152 mov32 r7, TEGRA_CLK_RESET_BASE
153
154 /* Are we on Tegra20? */
155 mov32 r6, TEGRA_APB_MISC_BASE
156 ldr r0, [r6, #APB_MISC_GP_HIDREV]
157 and r0, r0, #0xff00
158 cmp r0, #(0x20 << 8)
159 bne 1f
160
161#ifdef CONFIG_ARCH_TEGRA_2x_SOC
162 mov32 r0, 0x1111
163 mov r1, r0, lsl r10
164 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
165#endif
1661:
167#ifdef CONFIG_ARCH_TEGRA_3x_SOC
168 mov32 r6, TEGRA_FLOW_CTRL_BASE
169
170 cmp r10, #0
171 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
172 moveq r2, #FLOW_CTRL_CPU0_CSR
173 movne r1, r10, lsl #3
174 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
175 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
176
177 /* Clear CPU "event" and "interrupt" flags and power gate
178 it when halting but not before it is in the "WFI" state. */
179 ldr r0, [r6, +r2]
180 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
181 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
182 str r0, [r6, +r2]
183
184 /* Unconditionally halt this CPU */
185 mov r0, #FLOW_CTRL_WAITEVENT
186 str r0, [r6, +r1]
187 ldr r0, [r6, +r1] @ memory barrier
188
189 dsb
190 isb
191 wfi @ CPU should be power gated here
192
193 /* If the CPU didn't power gate above just kill it's clock. */
194
195 mov r0, r11, lsl #8
196 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
197#endif
198
199 /* If the CPU still isn't dead, just spin here. */
200 b .
201ENDPROC(__tegra_cpu_reset_handler)
202
203 .align L1_CACHE_SHIFT
204 .type __tegra_cpu_reset_handler_data, %object
205 .globl __tegra_cpu_reset_handler_data
206__tegra_cpu_reset_handler_data:
207 .rept TEGRA_RESET_DATA_SIZE
208 .long 0
209 .endr
210 .align L1_CACHE_SHIFT
211
212ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 67644c905d8e..cff672a344f4 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -113,6 +113,9 @@
113#define TEGRA_AHB_GIZMO_BASE 0x6000C004 113#define TEGRA_AHB_GIZMO_BASE 0x6000C004
114#define TEGRA_AHB_GIZMO_SIZE 0x10C 114#define TEGRA_AHB_GIZMO_SIZE 0x10C
115 115
116#define TEGRA_SB_BASE 0x6000C200
117#define TEGRA_SB_SIZE 256
118
116#define TEGRA_STATMON_BASE 0x6000C400 119#define TEGRA_STATMON_BASE 0x6000C400
117#define TEGRA_STATMON_SIZE SZ_1K 120#define TEGRA_STATMON_SIZE SZ_1K
118 121
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 39c396d2ddb0..4752b1a68f35 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -27,8 +27,21 @@
27#define TEGRA_POWERGATE_VDEC 4 27#define TEGRA_POWERGATE_VDEC 4
28#define TEGRA_POWERGATE_L2 5 28#define TEGRA_POWERGATE_L2 5
29#define TEGRA_POWERGATE_MPE 6 29#define TEGRA_POWERGATE_MPE 6
30#define TEGRA_NUM_POWERGATE 7 30#define TEGRA_POWERGATE_HEG 7
31#define TEGRA_POWERGATE_SATA 8
32#define TEGRA_POWERGATE_CPU1 9
33#define TEGRA_POWERGATE_CPU2 10
34#define TEGRA_POWERGATE_CPU3 11
35#define TEGRA_POWERGATE_CELP 12
36#define TEGRA_POWERGATE_3D1 13
31 37
38#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
39#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
40
41int __init tegra_powergate_init(void);
42
43int tegra_cpu_powergate_id(int cpuid);
44int tegra_powergate_is_powered(int id);
32int tegra_powergate_power_on(int id); 45int tegra_powergate_power_on(int id);
33int tegra_powergate_power_off(int id); 46int tegra_powergate_power_off(int id);
34int tegra_powergate_remove_clamping(int id); 47int tegra_powergate_remove_clamping(int id);
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 7d2b5d03c1df..1a208dbf682f 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,19 +24,31 @@
24#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25#include <asm/smp_scu.h> 25#include <asm/smp_scu.h>
26 26
27#include <mach/clk.h>
27#include <mach/iomap.h> 28#include <mach/iomap.h>
29#include <mach/powergate.h>
30
31#include "fuse.h"
32#include "flowctrl.h"
33#include "reset.h"
28 34
29extern void tegra_secondary_startup(void); 35extern void tegra_secondary_startup(void);
30 36
31static DEFINE_SPINLOCK(boot_lock);
32static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); 37static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
33 38
34#define EVP_CPU_RESET_VECTOR \ 39#define EVP_CPU_RESET_VECTOR \
35 (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) 40 (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
36#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \ 41#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
37 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c) 42 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
43#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
44 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
38#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \ 45#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
39 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344) 46 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
47#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
48 (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
49
50#define CPU_CLOCK(cpu) (0x1<<(8+cpu))
51#define CPU_RESET(cpu) (0x1111ul<<(cpu))
40 52
41void __cpuinit platform_secondary_init(unsigned int cpu) 53void __cpuinit platform_secondary_init(unsigned int cpu)
42{ 54{
@@ -47,63 +59,106 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
47 */ 59 */
48 gic_secondary_init(0); 60 gic_secondary_init(0);
49 61
50 /*
51 * Synchronise with the boot thread.
52 */
53 spin_lock(&boot_lock);
54 spin_unlock(&boot_lock);
55} 62}
56 63
57int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 64static int tegra20_power_up_cpu(unsigned int cpu)
58{ 65{
59 unsigned long old_boot_vector;
60 unsigned long boot_vector;
61 unsigned long timeout;
62 u32 reg; 66 u32 reg;
63 67
64 /* 68 /* Enable the CPU clock. */
65 * set synchronisation state between this boot processor 69 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
66 * and the secondary one 70 writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
67 */ 71 barrier();
68 spin_lock(&boot_lock); 72 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
69 73
74 /* Clear flow controller CSR. */
75 flowctrl_write_cpu_csr(cpu, 0);
70 76
71 /* set the reset vector to point to the secondary_startup routine */ 77 return 0;
78}
72 79
73 boot_vector = virt_to_phys(tegra_secondary_startup); 80static int tegra30_power_up_cpu(unsigned int cpu)
74 old_boot_vector = readl(EVP_CPU_RESET_VECTOR); 81{
75 writel(boot_vector, EVP_CPU_RESET_VECTOR); 82 u32 reg;
83 int ret, pwrgateid;
84 unsigned long timeout;
76 85
77 /* enable cpu clock on cpu1 */ 86 pwrgateid = tegra_cpu_powergate_id(cpu);
78 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 87 if (pwrgateid < 0)
79 writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 88 return pwrgateid;
89
90 /* If this is the first boot, toggle powergates directly. */
91 if (!tegra_powergate_is_powered(pwrgateid)) {
92 ret = tegra_powergate_power_on(pwrgateid);
93 if (ret)
94 return ret;
95
96 /* Wait for the power to come up. */
97 timeout = jiffies + 10*HZ;
98 while (tegra_powergate_is_powered(pwrgateid)) {
99 if (time_after(jiffies, timeout))
100 return -ETIMEDOUT;
101 udelay(10);
102 }
103 }
80 104
81 reg = (1<<13) | (1<<9) | (1<<5) | (1<<1); 105 /* CPU partition is powered. Enable the CPU clock. */
82 writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 106 writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
107 reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
108 udelay(10);
83 109
84 smp_wmb(); 110 /* Remove I/O clamps. */
85 flush_cache_all(); 111 ret = tegra_powergate_remove_clamping(pwrgateid);
112 udelay(10);
86 113
87 /* unhalt the cpu */ 114 /* Clear flow controller CSR. */
88 writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14); 115 flowctrl_write_cpu_csr(cpu, 0);
89 116
90 timeout = jiffies + (1 * HZ); 117 return 0;
91 while (time_before(jiffies, timeout)) { 118}
92 if (readl(EVP_CPU_RESET_VECTOR) != boot_vector) 119
93 break; 120int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
94 udelay(10); 121{
95 } 122 int status;
96 123
97 /* put the old boot vector back */ 124 /*
98 writel(old_boot_vector, EVP_CPU_RESET_VECTOR); 125 * Force the CPU into reset. The CPU must remain in reset when the
126 * flow controller state is cleared (which will cause the flow
127 * controller to stop driving reset if the CPU has been power-gated
128 * via the flow controller). This will have no effect on first boot
129 * of the CPU since it should already be in reset.
130 */
131 writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
132 dmb();
99 133
100 /* 134 /*
101 * now the secondary core is starting up let it run its 135 * Unhalt the CPU. If the flow controller was used to power-gate the
102 * calibrations, then wait for it to finish 136 * CPU this will cause the flow controller to stop driving reset.
137 * The CPU will remain in reset because the clock and reset block
138 * is now driving reset.
103 */ 139 */
104 spin_unlock(&boot_lock); 140 flowctrl_write_cpu_halt(cpu, 0);
141
142 switch (tegra_chip_id) {
143 case TEGRA20:
144 status = tegra20_power_up_cpu(cpu);
145 break;
146 case TEGRA30:
147 status = tegra30_power_up_cpu(cpu);
148 break;
149 default:
150 status = -EINVAL;
151 break;
152 }
105 153
106 return 0; 154 if (status)
155 goto done;
156
157 /* Take the CPU out of reset. */
158 writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
159 wmb();
160done:
161 return status;
107} 162}
108 163
109/* 164/*
@@ -128,6 +183,6 @@ void __init smp_init_cpus(void)
128 183
129void __init platform_smp_prepare_cpus(unsigned int max_cpus) 184void __init platform_smp_prepare_cpus(unsigned int max_cpus)
130{ 185{
131 186 tegra_cpu_reset_handler_init();
132 scu_enable(scu_base); 187 scu_enable(scu_base);
133} 188}
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 948306491a59..c238699ae86f 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -31,6 +31,8 @@
31#include <mach/iomap.h> 31#include <mach/iomap.h>
32#include <mach/powergate.h> 32#include <mach/powergate.h>
33 33
34#include "fuse.h"
35
34#define PWRGATE_TOGGLE 0x30 36#define PWRGATE_TOGGLE 0x30
35#define PWRGATE_TOGGLE_START (1 << 8) 37#define PWRGATE_TOGGLE_START (1 << 8)
36 38
@@ -38,6 +40,16 @@
38 40
39#define PWRGATE_STATUS 0x38 41#define PWRGATE_STATUS 0x38
40 42
43static int tegra_num_powerdomains;
44static int tegra_num_cpu_domains;
45static u8 *tegra_cpu_domains;
46static u8 tegra30_cpu_domains[] = {
47 TEGRA_POWERGATE_CPU0,
48 TEGRA_POWERGATE_CPU1,
49 TEGRA_POWERGATE_CPU2,
50 TEGRA_POWERGATE_CPU3,
51};
52
41static DEFINE_SPINLOCK(tegra_powergate_lock); 53static DEFINE_SPINLOCK(tegra_powergate_lock);
42 54
43static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 55static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
@@ -75,7 +87,7 @@ static int tegra_powergate_set(int id, bool new_state)
75 87
76int tegra_powergate_power_on(int id) 88int tegra_powergate_power_on(int id)
77{ 89{
78 if (id < 0 || id >= TEGRA_NUM_POWERGATE) 90 if (id < 0 || id >= tegra_num_powerdomains)
79 return -EINVAL; 91 return -EINVAL;
80 92
81 return tegra_powergate_set(id, true); 93 return tegra_powergate_set(id, true);
@@ -83,17 +95,18 @@ int tegra_powergate_power_on(int id)
83 95
84int tegra_powergate_power_off(int id) 96int tegra_powergate_power_off(int id)
85{ 97{
86 if (id < 0 || id >= TEGRA_NUM_POWERGATE) 98 if (id < 0 || id >= tegra_num_powerdomains)
87 return -EINVAL; 99 return -EINVAL;
88 100
89 return tegra_powergate_set(id, false); 101 return tegra_powergate_set(id, false);
90} 102}
91 103
92static bool tegra_powergate_is_powered(int id) 104int tegra_powergate_is_powered(int id)
93{ 105{
94 u32 status; 106 u32 status;
95 107
96 WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE); 108 if (id < 0 || id >= tegra_num_powerdomains)
109 return -EINVAL;
97 110
98 status = pmc_read(PWRGATE_STATUS) & (1 << id); 111 status = pmc_read(PWRGATE_STATUS) & (1 << id);
99 return !!status; 112 return !!status;
@@ -103,7 +116,7 @@ int tegra_powergate_remove_clamping(int id)
103{ 116{
104 u32 mask; 117 u32 mask;
105 118
106 if (id < 0 || id >= TEGRA_NUM_POWERGATE) 119 if (id < 0 || id >= tegra_num_powerdomains)
107 return -EINVAL; 120 return -EINVAL;
108 121
109 /* 122 /*
@@ -156,6 +169,34 @@ err_power:
156 return ret; 169 return ret;
157} 170}
158 171
172int tegra_cpu_powergate_id(int cpuid)
173{
174 if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
175 return tegra_cpu_domains[cpuid];
176
177 return -EINVAL;
178}
179
180int __init tegra_powergate_init(void)
181{
182 switch (tegra_chip_id) {
183 case TEGRA20:
184 tegra_num_powerdomains = 7;
185 break;
186 case TEGRA30:
187 tegra_num_powerdomains = 14;
188 tegra_num_cpu_domains = 4;
189 tegra_cpu_domains = tegra30_cpu_domains;
190 break;
191 default:
192 /* Unknown Tegra variant. Disable powergating */
193 tegra_num_powerdomains = 0;
194 break;
195 }
196
197 return 0;
198}
199
159#ifdef CONFIG_DEBUG_FS 200#ifdef CONFIG_DEBUG_FS
160 201
161static const char * const powergate_name[] = { 202static const char * const powergate_name[] = {
@@ -175,7 +216,7 @@ static int powergate_show(struct seq_file *s, void *data)
175 seq_printf(s, " powergate powered\n"); 216 seq_printf(s, " powergate powered\n");
176 seq_printf(s, "------------------\n"); 217 seq_printf(s, "------------------\n");
177 218
178 for (i = 0; i < TEGRA_NUM_POWERGATE; i++) 219 for (i = 0; i < tegra_num_powerdomains; i++)
179 seq_printf(s, " %9s %7s\n", powergate_name[i], 220 seq_printf(s, " %9s %7s\n", powergate_name[i],
180 tegra_powergate_is_powered(i) ? "yes" : "no"); 221 tegra_powergate_is_powered(i) ? "yes" : "no");
181 return 0; 222 return 0;
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
new file mode 100644
index 000000000000..4d6a2ee99c3b
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.c
@@ -0,0 +1,84 @@
1/*
2 * arch/arm/mach-tegra/reset.c
3 *
4 * Copyright (C) 2011,2012 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/cpumask.h>
20#include <linux/bitops.h>
21
22#include <asm/cacheflush.h>
23#include <asm/hardware/cache-l2x0.h>
24
25#include <mach/iomap.h>
26#include <mach/irammap.h>
27
28#include "reset.h"
29#include "fuse.h"
30
31#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
32 TEGRA_IRAM_RESET_HANDLER_OFFSET)
33
34static bool is_enabled;
35
36static void tegra_cpu_reset_handler_enable(void)
37{
38 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
39 void __iomem *evp_cpu_reset =
40 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
41 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
42 u32 reg;
43
44 BUG_ON(is_enabled);
45 BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
46
47 memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
48 tegra_cpu_reset_handler_size);
49
50 /*
51 * NOTE: This must be the one and only write to the EVP CPU reset
52 * vector in the entire system.
53 */
54 writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
55 evp_cpu_reset);
56 wmb();
57 reg = readl(evp_cpu_reset);
58
59 /*
60 * Prevent further modifications to the physical reset vector.
61 * NOTE: Has no effect on chips prior to Tegra30.
62 */
63 if (tegra_chip_id != TEGRA20) {
64 reg = readl(sb_ctrl);
65 reg |= 2;
66 writel(reg, sb_ctrl);
67 wmb();
68 }
69
70 is_enabled = true;
71}
72
73void __init tegra_cpu_reset_handler_init(void)
74{
75
76#ifdef CONFIG_SMP
77 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
78 *((u32 *)cpu_present_mask);
79 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
80 virt_to_phys((void *)tegra_secondary_startup);
81#endif
82
83 tegra_cpu_reset_handler_enable();
84}
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
new file mode 100644
index 000000000000..de88bf851dd3
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.h
@@ -0,0 +1,50 @@
1/*
2 * arch/arm/mach-tegra/reset.h
3 *
4 * CPU reset dispatcher.
5 *
6 * Copyright (c) 2011, NVIDIA Corporation.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef __MACH_TEGRA_RESET_H
20#define __MACH_TEGRA_RESET_H
21
22#define TEGRA_RESET_MASK_PRESENT 0
23#define TEGRA_RESET_MASK_LP1 1
24#define TEGRA_RESET_MASK_LP2 2
25#define TEGRA_RESET_STARTUP_SECONDARY 3
26#define TEGRA_RESET_STARTUP_LP2 4
27#define TEGRA_RESET_STARTUP_LP1 5
28#define TEGRA_RESET_DATA_SIZE 6
29
30#ifndef __ASSEMBLY__
31
32extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
33
34void __tegra_cpu_reset_handler_start(void);
35void __tegra_cpu_reset_handler(void);
36void __tegra_cpu_reset_handler_end(void);
37void tegra_secondary_startup(void);
38
39#define tegra_cpu_reset_handler_offset \
40 ((u32)__tegra_cpu_reset_handler - \
41 (u32)__tegra_cpu_reset_handler_start)
42
43#define tegra_cpu_reset_handler_size \
44 (__tegra_cpu_reset_handler_end - \
45 __tegra_cpu_reset_handler_start)
46
47void __init tegra_cpu_reset_handler_init(void);
48
49#endif
50#endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 9ec635812349..8904d18de01a 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -27,6 +27,7 @@ config MACH_MOP500
27 select UX500_SOC_DB8500 27 select UX500_SOC_DB8500
28 select I2C 28 select I2C
29 select I2C_NOMADIK 29 select I2C_NOMADIK
30 select SOC_BUS
30 help 31 help
31 Include support for the MOP500 development platform. 32 Include support for the MOP500 development platform.
32 33
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 1daead3e583e..920251cf834c 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -99,7 +99,7 @@ static struct mmci_platform_data mop500_sdi0_data = {
99#endif 99#endif
100}; 100};
101 101
102static void sdi0_configure(void) 102static void sdi0_configure(struct device *parent)
103{ 103{
104 int ret; 104 int ret;
105 105
@@ -118,15 +118,15 @@ static void sdi0_configure(void)
118 gpio_direction_output(sdi0_en, 1); 118 gpio_direction_output(sdi0_en, 1);
119 119
120 /* Add the device, force v2 to subrevision 1 */ 120 /* Add the device, force v2 to subrevision 1 */
121 db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID); 121 db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
122} 122}
123 123
124void mop500_sdi_tc35892_init(void) 124void mop500_sdi_tc35892_init(struct device *parent)
125{ 125{
126 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD; 126 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
127 sdi0_en = GPIO_SDMMC_EN; 127 sdi0_en = GPIO_SDMMC_EN;
128 sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL; 128 sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
129 sdi0_configure(); 129 sdi0_configure(parent);
130} 130}
131 131
132/* 132/*
@@ -241,12 +241,13 @@ static struct mmci_platform_data mop500_sdi4_data = {
241#endif 241#endif
242}; 242};
243 243
244void __init mop500_sdi_init(void) 244void __init mop500_sdi_init(struct device *parent)
245{ 245{
246 /* PoP:ed eMMC */ 246 /* PoP:ed eMMC */
247 db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); 247 db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
248 /* On-board eMMC */ 248 /* On-board eMMC */
249 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); 249 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
250
250 /* 251 /*
251 * On boards with the TC35892 GPIO expander, sdi0 will finally 252 * On boards with the TC35892 GPIO expander, sdi0 will finally
252 * be added when the TC35892 initializes and calls 253 * be added when the TC35892 initializes and calls
@@ -254,31 +255,31 @@ void __init mop500_sdi_init(void)
254 */ 255 */
255} 256}
256 257
257void __init snowball_sdi_init(void) 258void __init snowball_sdi_init(struct device *parent)
258{ 259{
259 /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */ 260 /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
260 mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED; 261 mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
261 /* On-board eMMC */ 262 /* On-board eMMC */
262 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); 263 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
263 /* External Micro SD slot */ 264 /* External Micro SD slot */
264 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; 265 mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
265 mop500_sdi0_data.cd_invert = true; 266 mop500_sdi0_data.cd_invert = true;
266 sdi0_en = SNOWBALL_SDMMC_EN_GPIO; 267 sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
267 sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; 268 sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
268 sdi0_configure(); 269 sdi0_configure(parent);
269} 270}
270 271
271void __init hrefv60_sdi_init(void) 272void __init hrefv60_sdi_init(struct device *parent)
272{ 273{
273 /* PoP:ed eMMC */ 274 /* PoP:ed eMMC */
274 db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); 275 db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
275 /* On-board eMMC */ 276 /* On-board eMMC */
276 db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); 277 db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
277 /* External Micro SD slot */ 278 /* External Micro SD slot */
278 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; 279 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
279 sdi0_en = HREFV60_SDMMC_EN_GPIO; 280 sdi0_en = HREFV60_SDMMC_EN_GPIO;
280 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; 281 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
281 sdi0_configure(); 282 sdi0_configure(parent);
282 /* WLAN SDIO channel */ 283 /* WLAN SDIO channel */
283 db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID); 284 db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
284} 285}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 6d672a556df8..29d330374994 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -226,7 +226,12 @@ static struct tps6105x_platform_data mop500_tps61052_data = {
226 226
227static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base) 227static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
228{ 228{
229 mop500_sdi_tc35892_init(); 229 struct device *parent = NULL;
230#if 0
231 /* FIXME: Is the sdi actually part of tc3589x? */
232 parent = tc3589x->dev;
233#endif
234 mop500_sdi_tc35892_init(parent);
230} 235}
231 236
232static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = { 237static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
@@ -353,12 +358,12 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
353U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); 358U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
354U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); 359U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
355 360
356static void __init mop500_i2c_init(void) 361static void __init mop500_i2c_init(struct device *parent)
357{ 362{
358 db8500_add_i2c0(&u8500_i2c0_data); 363 db8500_add_i2c0(parent, &u8500_i2c0_data);
359 db8500_add_i2c1(&u8500_i2c1_data); 364 db8500_add_i2c1(parent, &u8500_i2c1_data);
360 db8500_add_i2c2(&u8500_i2c2_data); 365 db8500_add_i2c2(parent, &u8500_i2c2_data);
361 db8500_add_i2c3(&u8500_i2c3_data); 366 db8500_add_i2c3(parent, &u8500_i2c3_data);
362} 367}
363 368
364static struct gpio_keys_button mop500_gpio_keys[] = { 369static struct gpio_keys_button mop500_gpio_keys[] = {
@@ -451,9 +456,9 @@ static struct pl022_ssp_controller ssp0_platform_data = {
451 .num_chipselect = 5, 456 .num_chipselect = 5,
452}; 457};
453 458
454static void __init mop500_spi_init(void) 459static void __init mop500_spi_init(struct device *parent)
455{ 460{
456 db8500_add_ssp0(&ssp0_platform_data); 461 db8500_add_ssp0(parent, &ssp0_platform_data);
457} 462}
458 463
459#ifdef CONFIG_STE_DMA40 464#ifdef CONFIG_STE_DMA40
@@ -587,11 +592,11 @@ static struct amba_pl011_data uart2_plat = {
587#endif 592#endif
588}; 593};
589 594
590static void __init mop500_uart_init(void) 595static void __init mop500_uart_init(struct device *parent)
591{ 596{
592 db8500_add_uart0(&uart0_plat); 597 db8500_add_uart0(parent, &uart0_plat);
593 db8500_add_uart1(&uart1_plat); 598 db8500_add_uart1(parent, &uart1_plat);
594 db8500_add_uart2(&uart2_plat); 599 db8500_add_uart2(parent, &uart2_plat);
595} 600}
596 601
597static struct platform_device *snowball_platform_devs[] __initdata = { 602static struct platform_device *snowball_platform_devs[] __initdata = {
@@ -603,21 +608,26 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
603 608
604static void __init mop500_init_machine(void) 609static void __init mop500_init_machine(void)
605{ 610{
611 struct device *parent = NULL;
606 int i2c0_devs; 612 int i2c0_devs;
613 int i;
607 614
608 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; 615 mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
609 616
610 u8500_init_devices(); 617 parent = u8500_init_devices();
611 618
612 mop500_pins_init(); 619 mop500_pins_init();
613 620
621 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
622 mop500_platform_devs[i]->dev.parent = parent;
623
614 platform_add_devices(mop500_platform_devs, 624 platform_add_devices(mop500_platform_devs,
615 ARRAY_SIZE(mop500_platform_devs)); 625 ARRAY_SIZE(mop500_platform_devs));
616 626
617 mop500_i2c_init(); 627 mop500_i2c_init(parent);
618 mop500_sdi_init(); 628 mop500_sdi_init(parent);
619 mop500_spi_init(); 629 mop500_spi_init(parent);
620 mop500_uart_init(); 630 mop500_uart_init(parent);
621 631
622 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 632 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
623 633
@@ -631,19 +641,24 @@ static void __init mop500_init_machine(void)
631 641
632static void __init snowball_init_machine(void) 642static void __init snowball_init_machine(void)
633{ 643{
644 struct device *parent = NULL;
634 int i2c0_devs; 645 int i2c0_devs;
646 int i;
635 647
636 u8500_init_devices(); 648 parent = u8500_init_devices();
637 649
638 snowball_pins_init(); 650 snowball_pins_init();
639 651
652 for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
653 snowball_platform_devs[i]->dev.parent = parent;
654
640 platform_add_devices(snowball_platform_devs, 655 platform_add_devices(snowball_platform_devs,
641 ARRAY_SIZE(snowball_platform_devs)); 656 ARRAY_SIZE(snowball_platform_devs));
642 657
643 mop500_i2c_init(); 658 mop500_i2c_init(parent);
644 snowball_sdi_init(); 659 snowball_sdi_init(parent);
645 mop500_spi_init(); 660 mop500_spi_init(parent);
646 mop500_uart_init(); 661 mop500_uart_init(parent);
647 662
648 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 663 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
649 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); 664 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
@@ -656,7 +671,9 @@ static void __init snowball_init_machine(void)
656 671
657static void __init hrefv60_init_machine(void) 672static void __init hrefv60_init_machine(void)
658{ 673{
674 struct device *parent = NULL;
659 int i2c0_devs; 675 int i2c0_devs;
676 int i;
660 677
661 /* 678 /*
662 * The HREFv60 board removed a GPIO expander and routed 679 * The HREFv60 board removed a GPIO expander and routed
@@ -665,17 +682,20 @@ static void __init hrefv60_init_machine(void)
665 */ 682 */
666 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; 683 mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
667 684
668 u8500_init_devices(); 685 parent = u8500_init_devices();
669 686
670 hrefv60_pins_init(); 687 hrefv60_pins_init();
671 688
689 for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
690 mop500_platform_devs[i]->dev.parent = parent;
691
672 platform_add_devices(mop500_platform_devs, 692 platform_add_devices(mop500_platform_devs,
673 ARRAY_SIZE(mop500_platform_devs)); 693 ARRAY_SIZE(mop500_platform_devs));
674 694
675 mop500_i2c_init(); 695 mop500_i2c_init(parent);
676 hrefv60_sdi_init(); 696 hrefv60_sdi_init(parent);
677 mop500_spi_init(); 697 mop500_spi_init(parent);
678 mop500_uart_init(); 698 mop500_uart_init(parent);
679 699
680 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 700 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
681 701
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 7ff6cbffc104..fdcfa8721bb4 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -75,10 +75,10 @@
75 75
76struct i2c_board_info; 76struct i2c_board_info;
77 77
78extern void mop500_sdi_init(void); 78extern void mop500_sdi_init(struct device *parent);
79extern void snowball_sdi_init(void); 79extern void snowball_sdi_init(struct device *parent);
80extern void hrefv60_sdi_init(void); 80extern void hrefv60_sdi_init(struct device *parent);
81extern void mop500_sdi_tc35892_init(void); 81extern void mop500_sdi_tc35892_init(struct device *parent);
82void __init mop500_u8500uib_init(void); 82void __init mop500_u8500uib_init(void);
83void __init mop500_stuib_init(void); 83void __init mop500_stuib_init(void);
84void __init mop500_pins_init(void); 84void __init mop500_pins_init(void);
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
index 63c3f8058ffc..836112eedde7 100644
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -66,9 +66,9 @@ static struct mmci_platform_data u5500_sdi0_data = {
66#endif 66#endif
67}; 67};
68 68
69void __init u5500_sdi_init(void) 69void __init u5500_sdi_init(struct device *parent)
70{ 70{
71 nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins)); 71 nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
72 72
73 db5500_add_sdi0(&u5500_sdi0_data); 73 db5500_add_sdi0(parent, &u5500_sdi0_data);
74} 74}
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 9de9e9c4dbbb..0ff4be72a809 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -97,9 +97,9 @@ static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
97 }, 97 },
98}; 98};
99 99
100static void __init u5500_i2c_init(void) 100static void __init u5500_i2c_init(struct device *parent)
101{ 101{
102 db5500_add_i2c2(&u5500_i2c2_data); 102 db5500_add_i2c2(parent, &u5500_i2c2_data);
103 i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices)); 103 i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
104} 104}
105 105
@@ -126,20 +126,27 @@ static struct platform_device *u5500_platform_devices[] __initdata = {
126 &ab5500_device, 126 &ab5500_device,
127}; 127};
128 128
129static void __init u5500_uart_init(void) 129static void __init u5500_uart_init(struct device *parent)
130{ 130{
131 db5500_add_uart0(NULL); 131 db5500_add_uart0(parent, NULL);
132 db5500_add_uart1(NULL); 132 db5500_add_uart1(parent, NULL);
133 db5500_add_uart2(NULL); 133 db5500_add_uart2(parent, NULL);
134} 134}
135 135
136static void __init u5500_init_machine(void) 136static void __init u5500_init_machine(void)
137{ 137{
138 u5500_init_devices(); 138 struct device *parent = NULL;
139 int i;
140
141 parent = u5500_init_devices();
139 nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins)); 142 nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
140 u5500_i2c_init(); 143
141 u5500_sdi_init(); 144 u5500_i2c_init(parent);
142 u5500_uart_init(); 145 u5500_sdi_init(parent);
146 u5500_uart_init(parent);
147
148 for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++)
149 u5500_platform_devices[i]->dev.parent = parent;
143 150
144 platform_add_devices(u5500_platform_devices, 151 platform_add_devices(u5500_platform_devices,
145 ARRAY_SIZE(u5500_platform_devices)); 152 ARRAY_SIZE(u5500_platform_devices));
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 18aa5c05c69e..bca47f32082f 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -147,13 +147,13 @@ static resource_size_t __initdata db5500_gpio_base[] = {
147 U5500_GPIOBANK7_BASE, 147 U5500_GPIOBANK7_BASE,
148}; 148};
149 149
150static void __init db5500_add_gpios(void) 150static void __init db5500_add_gpios(struct device *parent)
151{ 151{
152 struct nmk_gpio_platform_data pdata = { 152 struct nmk_gpio_platform_data pdata = {
153 /* No custom data yet */ 153 /* No custom data yet */
154 }; 154 };
155 155
156 dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base), 156 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base),
157 IRQ_DB5500_GPIO0, &pdata); 157 IRQ_DB5500_GPIO0, &pdata);
158} 158}
159 159
@@ -212,14 +212,36 @@ static int usb_db5500_tx_dma_cfg[] = {
212 DB5500_DMA_DEV38_USB_OTG_OEP_8 212 DB5500_DMA_DEV38_USB_OTG_OEP_8
213}; 213};
214 214
215void __init u5500_init_devices(void) 215static const char *db5500_read_soc_id(void)
216{ 216{
217 db5500_add_gpios(); 217 return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n");
218}
219
220static struct device * __init db5500_soc_device_init(void)
221{
222 const char *soc_id = db5500_read_soc_id();
223
224 return ux500_soc_device_init(soc_id);
225}
226
227struct device * __init u5500_init_devices(void)
228{
229 struct device *parent;
230 int i;
231
232 parent = db5500_soc_device_init();
233
234 db5500_add_gpios(parent);
218 db5500_pmu_init(); 235 db5500_pmu_init();
219 db5500_dma_init(); 236 db5500_dma_init(parent);
220 db5500_add_rtc(); 237 db5500_add_rtc(parent);
221 db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); 238 db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
239
240 for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++)
241 db5500_platform_devs[i]->dev.parent = parent;
222 242
223 platform_add_devices(db5500_platform_devs, 243 platform_add_devices(db5500_platform_devs,
224 ARRAY_SIZE(db5500_platform_devs)); 244 ARRAY_SIZE(db5500_platform_devs));
245
246 return parent;
225} 247}
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7176ee7491ab..9bd8163896cf 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -24,6 +24,7 @@
24#include <mach/setup.h> 24#include <mach/setup.h>
25#include <mach/devices.h> 25#include <mach/devices.h>
26#include <mach/usb.h> 26#include <mach/usb.h>
27#include <mach/db8500-regs.h>
27 28
28#include "devices-db8500.h" 29#include "devices-db8500.h"
29#include "ste-dma40-db8500.h" 30#include "ste-dma40-db8500.h"
@@ -132,13 +133,13 @@ static resource_size_t __initdata db8500_gpio_base[] = {
132 U8500_GPIOBANK8_BASE, 133 U8500_GPIOBANK8_BASE,
133}; 134};
134 135
135static void __init db8500_add_gpios(void) 136static void __init db8500_add_gpios(struct device *parent)
136{ 137{
137 struct nmk_gpio_platform_data pdata = { 138 struct nmk_gpio_platform_data pdata = {
138 .supports_sleepmode = true, 139 .supports_sleepmode = true,
139 }; 140 };
140 141
141 dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), 142 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
142 IRQ_DB8500_GPIO0, &pdata); 143 IRQ_DB8500_GPIO0, &pdata);
143} 144}
144 145
@@ -164,17 +165,44 @@ static int usb_db8500_tx_dma_cfg[] = {
164 DB8500_DMA_DEV39_USB_OTG_OEP_8 165 DB8500_DMA_DEV39_USB_OTG_OEP_8
165}; 166};
166 167
168static const char *db8500_read_soc_id(void)
169{
170 void __iomem *uid = __io_address(U8500_BB_UID_BASE);
171
172 return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
173 readl((u32 *)uid+1),
174 readl((u32 *)uid+1), readl((u32 *)uid+2),
175 readl((u32 *)uid+3), readl((u32 *)uid+4));
176}
177
178static struct device * __init db8500_soc_device_init(void)
179{
180 const char *soc_id = db8500_read_soc_id();
181
182 return ux500_soc_device_init(soc_id);
183}
184
167/* 185/*
168 * This function is called from the board init 186 * This function is called from the board init
169 */ 187 */
170void __init u8500_init_devices(void) 188struct device * __init u8500_init_devices(void)
171{ 189{
172 db8500_add_rtc(); 190 struct device *parent;
173 db8500_add_gpios(); 191 int i;
174 db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 192
193 parent = db8500_soc_device_init();
194
195 db8500_add_rtc(parent);
196 db8500_add_gpios(parent);
197 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
198
199 platform_device_register_data(parent,
200 "cpufreq-u8500", -1, NULL, 0);
201
202 for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
203 platform_devs[i]->dev.parent = parent;
175 204
176 platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
177 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 205 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
178 206
179 return ; 207 return parent;
180} 208}
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 851308bf6424..6242e88e5fd3 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -2,6 +2,7 @@
2 * Copyright (C) ST-Ericsson SA 2010 2 * Copyright (C) ST-Ericsson SA 2010
3 * 3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2 6 * License terms: GNU General Public License (GPL) version 2
6 */ 7 */
7 8
@@ -11,6 +12,10 @@
11#include <linux/mfd/db8500-prcmu.h> 12#include <linux/mfd/db8500-prcmu.h>
12#include <linux/mfd/db5500-prcmu.h> 13#include <linux/mfd/db5500-prcmu.h>
13#include <linux/clksrc-dbx500-prcmu.h> 14#include <linux/clksrc-dbx500-prcmu.h>
15#include <linux/sys_soc.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <linux/stat.h>
14 19
15#include <asm/hardware/gic.h> 20#include <asm/hardware/gic.h>
16#include <asm/mach/map.h> 21#include <asm/mach/map.h>
@@ -49,3 +54,73 @@ void __init ux500_init_irq(void)
49 db8500_prcmu_early_init(); 54 db8500_prcmu_early_init();
50 clk_init(); 55 clk_init();
51} 56}
57
58static const char * __init ux500_get_machine(void)
59{
60 return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber());
61}
62
63static const char * __init ux500_get_family(void)
64{
65 return kasprintf(GFP_KERNEL, "ux500");
66}
67
68static const char * __init ux500_get_revision(void)
69{
70 unsigned int rev = dbx500_revision();
71
72 if (rev == 0x01)
73 return kasprintf(GFP_KERNEL, "%s", "ED");
74 else if (rev >= 0xA0)
75 return kasprintf(GFP_KERNEL, "%d.%d",
76 (rev >> 4) - 0xA + 1, rev & 0xf);
77
78 return kasprintf(GFP_KERNEL, "%s", "Unknown");
79}
80
81static ssize_t ux500_get_process(struct device *dev,
82 struct device_attribute *attr,
83 char *buf)
84{
85 if (dbx500_id.process == 0x00)
86 return sprintf(buf, "Standard\n");
87
88 return sprintf(buf, "%02xnm\n", dbx500_id.process);
89}
90
91static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr,
92 const char *soc_id)
93{
94 soc_dev_attr->soc_id = soc_id;
95 soc_dev_attr->machine = ux500_get_machine();
96 soc_dev_attr->family = ux500_get_family();
97 soc_dev_attr->revision = ux500_get_revision();
98}
99
100struct device_attribute ux500_soc_attr =
101 __ATTR(process, S_IRUGO, ux500_get_process, NULL);
102
103struct device * __init ux500_soc_device_init(const char *soc_id)
104{
105 struct device *parent;
106 struct soc_device *soc_dev;
107 struct soc_device_attribute *soc_dev_attr;
108
109 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
110 if (!soc_dev_attr)
111 return ERR_PTR(-ENOMEM);
112
113 soc_info_populate(soc_dev_attr, soc_id);
114
115 soc_dev = soc_device_register(soc_dev_attr);
116 if (IS_ERR_OR_NULL(soc_dev)) {
117 kfree(soc_dev_attr);
118 return NULL;
119 }
120
121 parent = soc_device_to_device(soc_dev);
122 if (!IS_ERR_OR_NULL(parent))
123 device_create_file(parent, &ux500_soc_attr);
124
125 return parent;
126}
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index 898a64517b09..c5312a4b49f5 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -20,8 +20,9 @@
20#include "devices-common.h" 20#include "devices-common.h"
21 21
22struct amba_device * 22struct amba_device *
23dbx500_add_amba_device(const char *name, resource_size_t base, 23dbx500_add_amba_device(struct device *parent, const char *name,
24 int irq, void *pdata, unsigned int periphid) 24 resource_size_t base, int irq, void *pdata,
25 unsigned int periphid)
25{ 26{
26 struct amba_device *dev; 27 struct amba_device *dev;
27 int ret; 28 int ret;
@@ -39,6 +40,8 @@ dbx500_add_amba_device(const char *name, resource_size_t base,
39 40
40 dev->dev.platform_data = pdata; 41 dev->dev.platform_data = pdata;
41 42
43 dev->dev.parent = parent;
44
42 ret = amba_device_add(dev, &iomem_resource); 45 ret = amba_device_add(dev, &iomem_resource);
43 if (ret) { 46 if (ret) {
44 amba_device_put(dev); 47 amba_device_put(dev);
@@ -49,60 +52,7 @@ dbx500_add_amba_device(const char *name, resource_size_t base,
49} 52}
50 53
51static struct platform_device * 54static struct platform_device *
52dbx500_add_platform_device(const char *name, int id, void *pdata, 55dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq,
53 struct resource *res, int resnum)
54{
55 struct platform_device *dev;
56 int ret;
57
58 dev = platform_device_alloc(name, id);
59 if (!dev)
60 return ERR_PTR(-ENOMEM);
61
62 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
63 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
64
65 ret = platform_device_add_resources(dev, res, resnum);
66 if (ret)
67 goto out_free;
68
69 dev->dev.platform_data = pdata;
70
71 ret = platform_device_add(dev);
72 if (ret)
73 goto out_free;
74
75 return dev;
76
77out_free:
78 platform_device_put(dev);
79 return ERR_PTR(ret);
80}
81
82struct platform_device *
83dbx500_add_platform_device_4k1irq(const char *name, int id,
84 resource_size_t base,
85 int irq, void *pdata)
86{
87 struct resource resources[] = {
88 [0] = {
89 .start = base,
90 .end = base + SZ_4K - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = irq,
95 .end = irq,
96 .flags = IORESOURCE_IRQ,
97 }
98 };
99
100 return dbx500_add_platform_device(name, id, pdata, resources,
101 ARRAY_SIZE(resources));
102}
103
104static struct platform_device *
105dbx500_add_gpio(int id, resource_size_t addr, int irq,
106 struct nmk_gpio_platform_data *pdata) 56 struct nmk_gpio_platform_data *pdata)
107{ 57{
108 struct resource resources[] = { 58 struct resource resources[] = {
@@ -118,13 +68,18 @@ dbx500_add_gpio(int id, resource_size_t addr, int irq,
118 } 68 }
119 }; 69 };
120 70
121 return platform_device_register_resndata(NULL, "gpio", id, 71 return platform_device_register_resndata(
122 resources, ARRAY_SIZE(resources), 72 parent,
123 pdata, sizeof(*pdata)); 73 "gpio",
74 id,
75 resources,
76 ARRAY_SIZE(resources),
77 pdata,
78 sizeof(*pdata));
124} 79}
125 80
126void dbx500_add_gpios(resource_size_t *base, int num, int irq, 81void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
127 struct nmk_gpio_platform_data *pdata) 82 int irq, struct nmk_gpio_platform_data *pdata)
128{ 83{
129 int first = 0; 84 int first = 0;
130 int i; 85 int i;
@@ -134,6 +89,6 @@ void dbx500_add_gpios(resource_size_t *base, int num, int irq,
134 pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); 89 pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
135 pdata->num_gpio = 32; 90 pdata->num_gpio = 32;
136 91
137 dbx500_add_gpio(i, base[i], irq, pdata); 92 dbx500_add_gpio(parent, i, base[i], irq, pdata);
138 } 93 }
139} 94}
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 7825705033bf..39c74ec82add 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -8,80 +8,89 @@
8#ifndef __DEVICES_COMMON_H 8#ifndef __DEVICES_COMMON_H
9#define __DEVICES_COMMON_H 9#define __DEVICES_COMMON_H
10 10
11extern struct amba_device * 11#include <linux/platform_device.h>
12dbx500_add_amba_device(const char *name, resource_size_t base, 12#include <linux/dma-mapping.h>
13 int irq, void *pdata, unsigned int periphid); 13#include <linux/sys_soc.h>
14#include <plat/i2c.h>
14 15
15extern struct platform_device * 16extern struct amba_device *
16dbx500_add_platform_device_4k1irq(const char *name, int id, 17dbx500_add_amba_device(struct device *parent, const char *name,
17 resource_size_t base, 18 resource_size_t base, int irq, void *pdata,
18 int irq, void *pdata); 19 unsigned int periphid);
19 20
20struct spi_master_cntlr; 21struct spi_master_cntlr;
21 22
22static inline struct amba_device * 23static inline struct amba_device *
23dbx500_add_msp_spi(const char *name, resource_size_t base, int irq, 24dbx500_add_msp_spi(struct device *parent, const char *name,
25 resource_size_t base, int irq,
24 struct spi_master_cntlr *pdata) 26 struct spi_master_cntlr *pdata)
25{ 27{
26 return dbx500_add_amba_device(name, base, irq, pdata, 0); 28 return dbx500_add_amba_device(parent, name, base, irq,
29 pdata, 0);
27} 30}
28 31
29static inline struct amba_device * 32static inline struct amba_device *
30dbx500_add_spi(const char *name, resource_size_t base, int irq, 33dbx500_add_spi(struct device *parent, const char *name, resource_size_t base,
31 struct spi_master_cntlr *pdata, 34 int irq, struct spi_master_cntlr *pdata,
32 u32 periphid) 35 u32 periphid)
33{ 36{
34 return dbx500_add_amba_device(name, base, irq, pdata, periphid); 37 return dbx500_add_amba_device(parent, name, base, irq,
38 pdata, periphid);
35} 39}
36 40
37struct mmci_platform_data; 41struct mmci_platform_data;
38 42
39static inline struct amba_device * 43static inline struct amba_device *
40dbx500_add_sdi(const char *name, resource_size_t base, int irq, 44dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base,
41 struct mmci_platform_data *pdata, 45 int irq, struct mmci_platform_data *pdata, u32 periphid)
42 u32 periphid)
43{ 46{
44 return dbx500_add_amba_device(name, base, irq, pdata, periphid); 47 return dbx500_add_amba_device(parent, name, base, irq,
48 pdata, periphid);
45} 49}
46 50
47struct amba_pl011_data; 51struct amba_pl011_data;
48 52
49static inline struct amba_device * 53static inline struct amba_device *
50dbx500_add_uart(const char *name, resource_size_t base, int irq, 54dbx500_add_uart(struct device *parent, const char *name, resource_size_t base,
51 struct amba_pl011_data *pdata) 55 int irq, struct amba_pl011_data *pdata)
52{ 56{
53 return dbx500_add_amba_device(name, base, irq, pdata, 0); 57 return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
54} 58}
55 59
56struct nmk_i2c_controller; 60struct nmk_i2c_controller;
57 61
58static inline struct platform_device * 62static inline struct platform_device *
59dbx500_add_i2c(int id, resource_size_t base, int irq, 63dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq,
60 struct nmk_i2c_controller *pdata) 64 struct nmk_i2c_controller *data)
61{
62 return dbx500_add_platform_device_4k1irq("nmk-i2c", id, base, irq,
63 pdata);
64}
65
66struct msp_i2s_platform_data;
67
68static inline struct platform_device *
69dbx500_add_msp_i2s(int id, resource_size_t base, int irq,
70 struct msp_i2s_platform_data *pdata)
71{ 65{
72 return dbx500_add_platform_device_4k1irq("MSP_I2S", id, base, irq, 66 struct resource res[] = {
73 pdata); 67 DEFINE_RES_MEM(base, SZ_4K),
68 DEFINE_RES_IRQ(irq),
69 };
70
71 struct platform_device_info pdevinfo = {
72 .parent = parent,
73 .name = "nmk-i2c",
74 .id = id,
75 .res = res,
76 .num_res = ARRAY_SIZE(res),
77 .data = data,
78 .size_data = sizeof(*data),
79 .dma_mask = DMA_BIT_MASK(32),
80 };
81
82 return platform_device_register_full(&pdevinfo);
74} 83}
75 84
76static inline struct amba_device * 85static inline struct amba_device *
77dbx500_add_rtc(resource_size_t base, int irq) 86dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
78{ 87{
79 return dbx500_add_amba_device("rtc-pl031", base, irq, NULL, 0); 88 return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0);
80} 89}
81 90
82struct nmk_gpio_platform_data; 91struct nmk_gpio_platform_data;
83 92
84void dbx500_add_gpios(resource_size_t *base, int num, int irq, 93void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
85 struct nmk_gpio_platform_data *pdata); 94 int irq, struct nmk_gpio_platform_data *pdata);
86 95
87#endif 96#endif
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index 0c4bccd02b90..e70955502c35 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -10,70 +10,90 @@
10 10
11#include "devices-common.h" 11#include "devices-common.h"
12 12
13#define db5500_add_i2c1(pdata) \ 13#define db5500_add_i2c1(parent, pdata) \
14 dbx500_add_i2c(1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata) 14 dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
15#define db5500_add_i2c2(pdata) \ 15#define db5500_add_i2c2(parent, pdata) \
16 dbx500_add_i2c(2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata) 16 dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
17#define db5500_add_i2c3(pdata) \ 17#define db5500_add_i2c3(parent, pdata) \
18 dbx500_add_i2c(3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata) 18 dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
19 19
20#define db5500_add_msp0_i2s(pdata) \ 20#define db5500_add_msp0_spi(parent, pdata) \
21 dbx500_add_msp_i2s(0, U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata) 21 dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
22#define db5500_add_msp1_i2s(pdata) \ 22 IRQ_DB5500_MSP0, pdata)
23 dbx500_add_msp_i2s(1, U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata) 23#define db5500_add_msp1_spi(parent, pdata) \
24#define db5500_add_msp2_i2s(pdata) \ 24 dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
25 dbx500_add_msp_i2s(2, U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata) 25 IRQ_DB5500_MSP1, pdata)
26#define db5500_add_msp2_spi(parent, pdata) \
27 dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
28 IRQ_DB5500_MSP2, pdata)
26 29
27#define db5500_add_msp0_spi(pdata) \ 30#define db5500_add_msp0_spi(parent, pdata) \
28 dbx500_add_msp_spi("msp0", U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata) 31 dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
29#define db5500_add_msp1_spi(pdata) \ 32 IRQ_DB5500_MSP0, pdata)
30 dbx500_add_msp_spi("msp1", U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata) 33#define db5500_add_msp1_spi(parent, pdata) \
31#define db5500_add_msp2_spi(pdata) \ 34 dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
32 dbx500_add_msp_spi("msp2", U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata) 35 IRQ_DB5500_MSP1, pdata)
36#define db5500_add_msp2_spi(parent, pdata) \
37 dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
38 IRQ_DB5500_MSP2, pdata)
33 39
34#define db5500_add_rtc() \ 40#define db5500_add_rtc(parent) \
35 dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC); 41 dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC);
36 42
37#define db5500_add_usb(rx_cfg, tx_cfg) \ 43#define db5500_add_usb(parent, rx_cfg, tx_cfg) \
38 ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg) 44 ux500_add_usb(parent, U5500_USBOTG_BASE, \
45 IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
39 46
40#define db5500_add_sdi0(pdata) \ 47#define db5500_add_sdi0(parent, pdata) \
41 dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata, \ 48 dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \
49 IRQ_DB5500_SDMMC0, pdata, \
42 0x10480180) 50 0x10480180)
43#define db5500_add_sdi1(pdata) \ 51#define db5500_add_sdi1(parent, pdata) \
44 dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata, \ 52 dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \
53 IRQ_DB5500_SDMMC1, pdata, \
45 0x10480180) 54 0x10480180)
46#define db5500_add_sdi2(pdata) \ 55#define db5500_add_sdi2(parent, pdata) \
47 dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata \ 56 dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \
57 IRQ_DB5500_SDMMC2, pdata \
48 0x10480180) 58 0x10480180)
49#define db5500_add_sdi3(pdata) \ 59#define db5500_add_sdi3(parent, pdata) \
50 dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata \ 60 dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \
61 IRQ_DB5500_SDMMC3, pdata \
51 0x10480180) 62 0x10480180)
52#define db5500_add_sdi4(pdata) \ 63#define db5500_add_sdi4(parent, pdata) \
53 dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata \ 64 dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \
65 IRQ_DB5500_SDMMC4, pdata \
54 0x10480180) 66 0x10480180)
55 67
56/* This one has a bad peripheral ID in the U5500 silicon */ 68/* This one has a bad peripheral ID in the U5500 silicon */
57#define db5500_add_spi0(pdata) \ 69#define db5500_add_spi0(parent, pdata) \
58 dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata, \ 70 dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \
71 IRQ_DB5500_SPI0, pdata, \
59 0x10080023) 72 0x10080023)
60#define db5500_add_spi1(pdata) \ 73#define db5500_add_spi1(parent, pdata) \
61 dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata, \ 74 dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \
75 IRQ_DB5500_SPI1, pdata, \
62 0x10080023) 76 0x10080023)
63#define db5500_add_spi2(pdata) \ 77#define db5500_add_spi2(parent, pdata) \
64 dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata \ 78 dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \
79 IRQ_DB5500_SPI2, pdata \
65 0x10080023) 80 0x10080023)
66#define db5500_add_spi3(pdata) \ 81#define db5500_add_spi3(parent, pdata) \
67 dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata \ 82 dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \
83 IRQ_DB5500_SPI3, pdata \
68 0x10080023) 84 0x10080023)
69 85
70#define db5500_add_uart0(plat) \ 86#define db5500_add_uart0(parent, plat) \
71 dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat) 87 dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \
72#define db5500_add_uart1(plat) \ 88 IRQ_DB5500_UART0, plat)
73 dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1, plat) 89#define db5500_add_uart1(parent, plat) \
74#define db5500_add_uart2(plat) \ 90 dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \
75 dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2, plat) 91 IRQ_DB5500_UART1, plat)
76#define db5500_add_uart3(plat) \ 92#define db5500_add_uart2(parent, plat) \
77 dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3, plat) 93 dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \
94 IRQ_DB5500_UART2, plat)
95#define db5500_add_uart3(parent, plat) \
96 dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \
97 IRQ_DB5500_UART3, plat)
78 98
79#endif 99#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index cbd4a9ae8109..9fd93e9da529 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -14,88 +14,114 @@ struct ske_keypad_platform_data;
14struct pl022_ssp_controller; 14struct pl022_ssp_controller;
15 15
16static inline struct platform_device * 16static inline struct platform_device *
17db8500_add_ske_keypad(struct ske_keypad_platform_data *pdata) 17db8500_add_ske_keypad(struct device *parent,
18 struct ske_keypad_platform_data *pdata,
19 size_t size)
18{ 20{
19 return dbx500_add_platform_device_4k1irq("nmk-ske-keypad", -1, 21 struct resource resources[] = {
20 U8500_SKE_BASE, 22 DEFINE_RES_MEM(U8500_SKE_BASE, SZ_4K),
21 IRQ_DB8500_KB, pdata); 23 DEFINE_RES_IRQ(IRQ_DB8500_KB),
24 };
25
26 return platform_device_register_resndata(parent, "nmk-ske-keypad", -1,
27 resources, 2, pdata, size);
22} 28}
23 29
24static inline struct amba_device * 30static inline struct amba_device *
25db8500_add_ssp(const char *name, resource_size_t base, int irq, 31db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
26 struct pl022_ssp_controller *pdata) 32 int irq, struct pl022_ssp_controller *pdata)
27{ 33{
28 return dbx500_add_amba_device(name, base, irq, pdata, 0); 34 return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
29} 35}
30 36
31 37
32#define db8500_add_i2c0(pdata) \ 38#define db8500_add_i2c0(parent, pdata) \
33 dbx500_add_i2c(0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) 39 dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
34#define db8500_add_i2c1(pdata) \ 40#define db8500_add_i2c1(parent, pdata) \
35 dbx500_add_i2c(1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata) 41 dbx500_add_i2c(parent, 1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata)
36#define db8500_add_i2c2(pdata) \ 42#define db8500_add_i2c2(parent, pdata) \
37 dbx500_add_i2c(2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata) 43 dbx500_add_i2c(parent, 2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata)
38#define db8500_add_i2c3(pdata) \ 44#define db8500_add_i2c3(parent, pdata) \
39 dbx500_add_i2c(3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata) 45 dbx500_add_i2c(parent, 3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata)
40#define db8500_add_i2c4(pdata) \ 46#define db8500_add_i2c4(parent, pdata) \
41 dbx500_add_i2c(4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) 47 dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
42 48
43#define db8500_add_msp0_i2s(pdata) \ 49#define db8500_add_msp0_i2s(parent, pdata) \
44 dbx500_add_msp_i2s(0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) 50 dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
45#define db8500_add_msp1_i2s(pdata) \ 51#define db8500_add_msp1_i2s(parent, pdata) \
46 dbx500_add_msp_i2s(1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) 52 dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
47#define db8500_add_msp2_i2s(pdata) \ 53#define db8500_add_msp2_i2s(parent, pdata) \
48 dbx500_add_msp_i2s(2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) 54 dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
49#define db8500_add_msp3_i2s(pdata) \ 55#define db8500_add_msp3_i2s(parent, pdata) \
50 dbx500_add_msp_i2s(3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) 56 dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
51 57
52#define db8500_add_msp0_spi(pdata) \ 58#define db8500_add_msp0_spi(parent, pdata) \
53 dbx500_add_msp_spi("msp0", U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) 59 dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
54#define db8500_add_msp1_spi(pdata) \ 60 IRQ_DB8500_MSP0, pdata)
55 dbx500_add_msp_spi("msp1", U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) 61#define db8500_add_msp1_spi(parent, pdata) \
56#define db8500_add_msp2_spi(pdata) \ 62 dbx500_add_msp_spi(parent, "msp1", U8500_MSP1_BASE, \
57 dbx500_add_msp_spi("msp2", U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) 63 IRQ_DB8500_MSP1, pdata)
58#define db8500_add_msp3_spi(pdata) \ 64#define db8500_add_msp2_spi(parent, pdata) \
59 dbx500_add_msp_spi("msp3", U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) 65 dbx500_add_msp_spi(parent, "msp2", U8500_MSP2_BASE, \
60 66 IRQ_DB8500_MSP2, pdata)
61#define db8500_add_rtc() \ 67#define db8500_add_msp3_spi(parent, pdata) \
62 dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC); 68 dbx500_add_msp_spi(parent, "msp3", U8500_MSP3_BASE, \
63 69 IRQ_DB8500_MSP1, pdata)
64#define db8500_add_usb(rx_cfg, tx_cfg) \ 70
65 ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg) 71#define db8500_add_rtc(parent) \
66 72 dbx500_add_rtc(parent, U8500_RTC_BASE, IRQ_DB8500_RTC);
67#define db8500_add_sdi0(pdata, pid) \ 73
68 dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata, pid) 74#define db8500_add_usb(parent, rx_cfg, tx_cfg) \
69#define db8500_add_sdi1(pdata, pid) \ 75 ux500_add_usb(parent, U8500_USBOTG_BASE, \
70 dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata, pid) 76 IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
71#define db8500_add_sdi2(pdata, pid) \ 77
72 dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata, pid) 78#define db8500_add_sdi0(parent, pdata, pid) \
73#define db8500_add_sdi3(pdata, pid) \ 79 dbx500_add_sdi(parent, "sdi0", U8500_SDI0_BASE, \
74 dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata, pid) 80 IRQ_DB8500_SDMMC0, pdata, pid)
75#define db8500_add_sdi4(pdata, pid) \ 81#define db8500_add_sdi1(parent, pdata, pid) \
76 dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata, pid) 82 dbx500_add_sdi(parent, "sdi1", U8500_SDI1_BASE, \
77#define db8500_add_sdi5(pdata, pid) \ 83 IRQ_DB8500_SDMMC1, pdata, pid)
78 dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata, pid) 84#define db8500_add_sdi2(parent, pdata, pid) \
79 85 dbx500_add_sdi(parent, "sdi2", U8500_SDI2_BASE, \
80#define db8500_add_ssp0(pdata) \ 86 IRQ_DB8500_SDMMC2, pdata, pid)
81 db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata) 87#define db8500_add_sdi3(parent, pdata, pid) \
82#define db8500_add_ssp1(pdata) \ 88 dbx500_add_sdi(parent, "sdi3", U8500_SDI3_BASE, \
83 db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata) 89 IRQ_DB8500_SDMMC3, pdata, pid)
84 90#define db8500_add_sdi4(parent, pdata, pid) \
85#define db8500_add_spi0(pdata) \ 91 dbx500_add_sdi(parent, "sdi4", U8500_SDI4_BASE, \
86 dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata, 0) 92 IRQ_DB8500_SDMMC4, pdata, pid)
87#define db8500_add_spi1(pdata) \ 93#define db8500_add_sdi5(parent, pdata, pid) \
88 dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata, 0) 94 dbx500_add_sdi(parent, "sdi5", U8500_SDI5_BASE, \
89#define db8500_add_spi2(pdata) \ 95 IRQ_DB8500_SDMMC5, pdata, pid)
90 dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata, 0) 96
91#define db8500_add_spi3(pdata) \ 97#define db8500_add_ssp0(parent, pdata) \
92 dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata, 0) 98 db8500_add_ssp(parent, "ssp0", U8500_SSP0_BASE, \
93 99 IRQ_DB8500_SSP0, pdata)
94#define db8500_add_uart0(pdata) \ 100#define db8500_add_ssp1(parent, pdata) \
95 dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata) 101 db8500_add_ssp(parent, "ssp1", U8500_SSP1_BASE, \
96#define db8500_add_uart1(pdata) \ 102 IRQ_DB8500_SSP1, pdata)
97 dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1, pdata) 103
98#define db8500_add_uart2(pdata) \ 104#define db8500_add_spi0(parent, pdata) \
99 dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2, pdata) 105 dbx500_add_spi(parent, "spi0", U8500_SPI0_BASE, \
106 IRQ_DB8500_SPI0, pdata, 0)
107#define db8500_add_spi1(parent, pdata) \
108 dbx500_add_spi(parent, "spi1", U8500_SPI1_BASE, \
109 IRQ_DB8500_SPI1, pdata, 0)
110#define db8500_add_spi2(parent, pdata) \
111 dbx500_add_spi(parent, "spi2", U8500_SPI2_BASE, \
112 IRQ_DB8500_SPI2, pdata, 0)
113#define db8500_add_spi3(parent, pdata) \
114 dbx500_add_spi(parent, "spi3", U8500_SPI3_BASE, \
115 IRQ_DB8500_SPI3, pdata, 0)
116
117#define db8500_add_uart0(parent, pdata) \
118 dbx500_add_uart(parent, "uart0", U8500_UART0_BASE, \
119 IRQ_DB8500_UART0, pdata)
120#define db8500_add_uart1(parent, pdata) \
121 dbx500_add_uart(parent, "uart1", U8500_UART1_BASE, \
122 IRQ_DB8500_UART1, pdata)
123#define db8500_add_uart2(parent, pdata) \
124 dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \
125 IRQ_DB8500_UART2, pdata)
100 126
101#endif 127#endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
index 1cfab68ae417..41e9470fa0e6 100644
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -125,10 +125,11 @@ static struct platform_device dma40_device = {
125 .resource = dma40_resources 125 .resource = dma40_resources
126}; 126};
127 127
128void __init db5500_dma_init(void) 128void __init db5500_dma_init(struct device *parent)
129{ 129{
130 int ret; 130 int ret;
131 131
132 dma40_device.dev.parent = parent;
132 ret = platform_device_register(&dma40_device); 133 ret = platform_device_register(&dma40_device);
133 if (ret) 134 if (ret)
134 dev_err(&dma40_device.dev, "unable to register device: %d\n", ret); 135 dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 80e10f50282e..9ec20b96d8f2 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -161,4 +161,7 @@
161#define U8500_MODEM_BASE 0xe000000 161#define U8500_MODEM_BASE 0xe000000
162#define U8500_APE_BASE 0x6000000 162#define U8500_APE_BASE 0x6000000
163 163
164/* SoC identification number information */
165#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0)
166
164#endif 167#endif
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 93d403955eaa..3dc00ffa7bfa 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -18,14 +18,16 @@ void __init ux500_map_io(void);
18extern void __init u5500_map_io(void); 18extern void __init u5500_map_io(void);
19extern void __init u8500_map_io(void); 19extern void __init u8500_map_io(void);
20 20
21extern void __init u5500_init_devices(void); 21extern struct device * __init u5500_init_devices(void);
22extern void __init u8500_init_devices(void); 22extern struct device * __init u8500_init_devices(void);
23 23
24extern void __init ux500_init_irq(void); 24extern void __init ux500_init_irq(void);
25 25
26extern void __init u5500_sdi_init(void); 26extern void __init u5500_sdi_init(struct device *parent);
27 27
28extern void __init db5500_dma_init(void); 28extern void __init db5500_dma_init(struct device *parent);
29
30extern struct device *ux500_soc_device_init(const char *soc_id);
29 31
30struct amba_device; 32struct amba_device;
31extern void __init amba_add_devices(struct amba_device *devs[], int num); 33extern void __init amba_add_devices(struct amba_device *devs[], int num);
diff --git a/arch/arm/mach-ux500/include/mach/usb.h b/arch/arm/mach-ux500/include/mach/usb.h
index d3739d418813..4c1cc50a595a 100644
--- a/arch/arm/mach-ux500/include/mach/usb.h
+++ b/arch/arm/mach-ux500/include/mach/usb.h
@@ -20,6 +20,6 @@ struct ux500_musb_board_data {
20 bool (*dma_filter)(struct dma_chan *chan, void *filter_param); 20 bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
21}; 21};
22 22
23void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg, 23void ux500_add_usb(struct device *parent, resource_size_t base,
24 int *dma_tx_cfg); 24 int irq, int *dma_rx_cfg, int *dma_tx_cfg);
25#endif 25#endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 9f9e1c203061..a74af389bc63 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -7,6 +7,7 @@
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/usb/musb.h> 8#include <linux/usb/musb.h>
9#include <linux/dma-mapping.h> 9#include <linux/dma-mapping.h>
10
10#include <plat/ste_dma40.h> 11#include <plat/ste_dma40.h>
11#include <mach/hardware.h> 12#include <mach/hardware.h>
12#include <mach/usb.h> 13#include <mach/usb.h>
@@ -140,8 +141,8 @@ static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
140 musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx]; 141 musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
141} 142}
142 143
143void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg, 144void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
144 int *dma_tx_cfg) 145 int *dma_rx_cfg, int *dma_tx_cfg)
145{ 146{
146 ux500_musb_device.resource[0].start = base; 147 ux500_musb_device.resource[0].start = base;
147 ux500_musb_device.resource[0].end = base + SZ_64K - 1; 148 ux500_musb_device.resource[0].end = base + SZ_64K - 1;
@@ -151,5 +152,7 @@ void ux500_add_usb(resource_size_t base, int irq, int *dma_rx_cfg,
151 ux500_usb_dma_update_rx_ch_config(dma_rx_cfg); 152 ux500_usb_dma_update_rx_ch_config(dma_rx_cfg);
152 ux500_usb_dma_update_tx_ch_config(dma_tx_cfg); 153 ux500_usb_dma_update_tx_ch_config(dma_tx_cfg);
153 154
155 ux500_musb_device.dev.parent = parent;
156
154 platform_device_register(&ux500_musb_device); 157 platform_device_register(&ux500_musb_device);
155} 158}
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 7a308699f816..96bea3202304 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -9,8 +9,8 @@ config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) 10 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
11 default y 11 default y
12 select ARM_VIC if !ARCH_EXYNOS4 12 select ARM_VIC if !ARCH_EXYNOS
13 select ARM_GIC if ARCH_EXYNOS4 13 select ARM_GIC if ARCH_EXYNOS
14 select GIC_NON_BANKED if ARCH_EXYNOS4 14 select GIC_NON_BANKED if ARCH_EXYNOS4
15 select NO_IOPORT 15 select NO_IOPORT
16 select ARCH_REQUIRE_GPIOLIB 16 select ARCH_REQUIRE_GPIOLIB
@@ -40,6 +40,10 @@ config S5P_HRT
40 help 40 help
41 Use the High Resolution timer support 41 Use the High Resolution timer support
42 42
43config S5P_DEV_UART
44 def_bool y
45 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
46
43config S5P_PM 47config S5P_PM
44 bool 48 bool
45 help 49 help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 30d8c3016e6b..4bd824136659 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -12,7 +12,6 @@ obj- :=
12 12
13# Core files 13# Core files
14 14
15obj-y += dev-uart.o
16obj-y += clock.o 15obj-y += clock.o
17obj-y += irq.o 16obj-y += irq.o
18obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o 17obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
@@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP) += sleep.o
23obj-$(CONFIG_S5P_HRT) += s5p-time.o 22obj-$(CONFIG_S5P_HRT) += s5p-time.o
24 23
25# devices 24# devices
25
26obj-$(CONFIG_S5P_DEV_UART) += dev-uart.o
26obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o 27obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
27obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o 28obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 963edea7f7e7..f68a9bb11948 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
61 .id = -1, 61 .id = -1,
62}; 62};
63 63
64/* BPLL clock output */
65
66struct clk clk_fout_bpll = {
67 .name = "fout_bpll",
68 .id = -1,
69};
70
71/* CPLL clock output */
72
73struct clk clk_fout_cpll = {
74 .name = "fout_cpll",
75 .id = -1,
76};
77
64/* MPLL clock output 78/* MPLL clock output
65 * No need .ctrlbit, this is always on 79 * No need .ctrlbit, this is always on
66*/ 80*/
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
101 .nr_sources = ARRAY_SIZE(clk_src_apll_list), 115 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
102}; 116};
103 117
118/* Possible clock sources for BPLL Mux */
119static struct clk *clk_src_bpll_list[] = {
120 [0] = &clk_fin_bpll,
121 [1] = &clk_fout_bpll,
122};
123
124struct clksrc_sources clk_src_bpll = {
125 .sources = clk_src_bpll_list,
126 .nr_sources = ARRAY_SIZE(clk_src_bpll_list),
127};
128
129/* Possible clock sources for CPLL Mux */
130static struct clk *clk_src_cpll_list[] = {
131 [0] = &clk_fin_cpll,
132 [1] = &clk_fout_cpll,
133};
134
135struct clksrc_sources clk_src_cpll = {
136 .sources = clk_src_cpll_list,
137 .nr_sources = ARRAY_SIZE(clk_src_cpll_list),
138};
139
104/* Possible clock sources for MPLL Mux */ 140/* Possible clock sources for MPLL Mux */
105static struct clk *clk_src_mpll_list[] = { 141static struct clk *clk_src_mpll_list[] = {
106 [0] = &clk_fin_mpll, 142 [0] = &clk_fin_mpll,
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
index 327acb3a4464..d1bfecae6c9f 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow = 0xffffffffL;
39int s3c_irq_wake(struct irq_data *data, unsigned int state) 39int s3c_irq_wake(struct irq_data *data, unsigned int state)
40{ 40{
41 unsigned long irqbit; 41 unsigned long irqbit;
42 unsigned int irq_rtc_tic, irq_rtc_alarm;
43
44#ifdef CONFIG_ARCH_EXYNOS
45 if (soc_is_exynos5250()) {
46 irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
47 irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
48 } else {
49 irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
50 irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
51 }
52#else
53 irq_rtc_tic = IRQ_RTC_TIC;
54 irq_rtc_alarm = IRQ_RTC_ALARM;
55#endif
56
57 if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
58 irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
42 59
43 switch (data->irq) {
44 case IRQ_RTC_TIC:
45 case IRQ_RTC_ALARM:
46 irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
47 if (!state) 60 if (!state)
48 s3c_irqwake_intmask |= irqbit; 61 s3c_irqwake_intmask |= irqbit;
49 else 62 else
50 s3c_irqwake_intmask &= ~irqbit; 63 s3c_irqwake_intmask &= ~irqbit;
51 break; 64 } else {
52 default:
53 return -ENOENT; 65 return -ENOENT;
54 } 66 }
67
55 return 0; 68 return 0;
56} 69}
57 70
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 73cb3cfd0685..787ceaca0be8 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
42#define EXYNOS4412_CPU_ID 0xE4412200 42#define EXYNOS4412_CPU_ID 0xE4412200
43#define EXYNOS4_CPU_MASK 0xFFFE0000 43#define EXYNOS4_CPU_MASK 0xFFFE0000
44 44
45#define EXYNOS5250_SOC_ID 0x43520000
46#define EXYNOS5_SOC_MASK 0xFFFFF000
47
45#define IS_SAMSUNG_CPU(name, id, mask) \ 48#define IS_SAMSUNG_CPU(name, id, mask) \
46static inline int is_samsung_##name(void) \ 49static inline int is_samsung_##name(void) \
47{ \ 50{ \
@@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
58IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) 61IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
59IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) 62IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
60IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) 63IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
64IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
61 65
62#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 66#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
63 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \ 67 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
120#define EXYNOS4210_REV_1_0 (0x10) 124#define EXYNOS4210_REV_1_0 (0x10)
121#define EXYNOS4210_REV_1_1 (0x11) 125#define EXYNOS4210_REV_1_1 (0x11)
122 126
127#if defined(CONFIG_SOC_EXYNOS5250)
128# define soc_is_exynos5250() is_samsung_exynos5250()
129#else
130# define soc_is_exynos5250() 0
131#endif
132
123#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 133#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
124 134
125#ifndef MHZ 135#ifndef MHZ
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 5e7972de3ed5..2155d4af62a3 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -26,6 +26,8 @@ struct s3c24xx_uart_resources {
26extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; 26extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; 27extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
28extern struct s3c24xx_uart_resources s5p_uart_resources[]; 28extern struct s3c24xx_uart_resources s5p_uart_resources[];
29extern struct s3c24xx_uart_resources exynos4_uart_resources[];
30extern struct s3c24xx_uart_resources exynos5_uart_resources[];
29 31
30extern struct platform_device *s3c24xx_uart_devs[]; 32extern struct platform_device *s3c24xx_uart_devs[];
31extern struct platform_device *s3c24xx_uart_src[]; 33extern struct platform_device *s3c24xx_uart_src[];
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 984bf9e7bc89..1de4b32f98e9 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -18,6 +18,8 @@
18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 18#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
19 19
20#define clk_fin_apll clk_ext_xtal_mux 20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_bpll clk_ext_xtal_mux
22#define clk_fin_cpll clk_ext_xtal_mux
21#define clk_fin_mpll clk_ext_xtal_mux 23#define clk_fin_mpll clk_ext_xtal_mux
22#define clk_fin_epll clk_ext_xtal_mux 24#define clk_fin_epll clk_ext_xtal_mux
23#define clk_fin_dpll clk_ext_xtal_mux 25#define clk_fin_dpll clk_ext_xtal_mux
@@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
29extern struct clk clk_48m; 31extern struct clk clk_48m;
30extern struct clk s5p_clk_27m; 32extern struct clk s5p_clk_27m;
31extern struct clk clk_fout_apll; 33extern struct clk clk_fout_apll;
34extern struct clk clk_fout_bpll;
35extern struct clk clk_fout_cpll;
32extern struct clk clk_fout_mpll; 36extern struct clk clk_fout_mpll;
33extern struct clk clk_fout_epll; 37extern struct clk clk_fout_epll;
34extern struct clk clk_fout_dpll; 38extern struct clk clk_fout_dpll;
@@ -37,6 +41,8 @@ extern struct clk clk_arm;
37extern struct clk clk_vpll; 41extern struct clk clk_vpll;
38 42
39extern struct clksrc_sources clk_src_apll; 43extern struct clksrc_sources clk_src_apll;
44extern struct clksrc_sources clk_src_bpll;
45extern struct clksrc_sources clk_src_cpll;
40extern struct clksrc_sources clk_src_mpll; 46extern struct clksrc_sources clk_src_mpll;
41extern struct clksrc_sources clk_src_epll; 47extern struct clksrc_sources clk_src_epll;
42extern struct clksrc_sources clk_src_dpll; 48extern struct clksrc_sources clk_src_dpll;
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index ee48e12a1e72..7e068d182c3d 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -37,7 +37,9 @@ static void arch_detect_cpu(void);
37/* how many bytes we allow into the FIFO at a time in FIFO mode */ 37/* how many bytes we allow into the FIFO at a time in FIFO mode */
38#define FIFO_MAX (14) 38#define FIFO_MAX (14)
39 39
40#ifdef S3C_PA_UART
40#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) 41#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
42#endif
41 43
42static __inline__ void 44static __inline__ void
43uart_wr(unsigned int reg, unsigned int val) 45uart_wr(unsigned int reg, unsigned int val)
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 51583cd30164..f980cf3d2baa 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include <mach/map.h> 21#include <mach/map.h>
22#include <plat/cpu.h>
22#include <plat/irq-vic-timer.h> 23#include <plat/irq-vic-timer.h>
23#include <plat/regs-timer.h> 24#include <plat/regs-timer.h>
24 25
@@ -57,6 +58,21 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
57 struct irq_chip_type *ct; 58 struct irq_chip_type *ct;
58 unsigned int i; 59 unsigned int i;
59 60
61#ifdef CONFIG_ARCH_EXYNOS
62 if (soc_is_exynos5250()) {
63 pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
64 pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
65 pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
66 pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
67 pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
68 } else {
69 pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
70 pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
71 pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
72 pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
73 pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
74 }
75#endif
60 s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq, 76 s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
61 S3C64XX_TINT_CSTAT, handle_level_irq); 77 S3C64XX_TINT_CSTAT, handle_level_irq);
62 78
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 14:09:59 -0500