diff options
Diffstat (limited to 'arch/arm/mach-spear3xx/include/mach/spear310.h')
-rw-r--r-- | arch/arm/mach-spear3xx/include/mach/spear310.h | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index 1e853479b8cd..1567d0da725f 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h | |||
@@ -29,29 +29,29 @@ | |||
29 | #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) | 29 | #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) |
30 | 30 | ||
31 | /* Interrupt registers offsets and masks */ | 31 | /* Interrupt registers offsets and masks */ |
32 | #define INT_STS_MASK_REG 0x04 | 32 | #define SPEAR310_INT_STS_MASK_REG 0x04 |
33 | #define SMII0_IRQ_MASK (1 << 0) | 33 | #define SPEAR310_SMII0_IRQ_MASK (1 << 0) |
34 | #define SMII1_IRQ_MASK (1 << 1) | 34 | #define SPEAR310_SMII1_IRQ_MASK (1 << 1) |
35 | #define SMII2_IRQ_MASK (1 << 2) | 35 | #define SPEAR310_SMII2_IRQ_MASK (1 << 2) |
36 | #define SMII3_IRQ_MASK (1 << 3) | 36 | #define SPEAR310_SMII3_IRQ_MASK (1 << 3) |
37 | #define WAKEUP_SMII0_IRQ_MASK (1 << 4) | 37 | #define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) |
38 | #define WAKEUP_SMII1_IRQ_MASK (1 << 5) | 38 | #define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) |
39 | #define WAKEUP_SMII2_IRQ_MASK (1 << 6) | 39 | #define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) |
40 | #define WAKEUP_SMII3_IRQ_MASK (1 << 7) | 40 | #define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) |
41 | #define UART1_IRQ_MASK (1 << 8) | 41 | #define SPEAR310_UART1_IRQ_MASK (1 << 8) |
42 | #define UART2_IRQ_MASK (1 << 9) | 42 | #define SPEAR310_UART2_IRQ_MASK (1 << 9) |
43 | #define UART3_IRQ_MASK (1 << 10) | 43 | #define SPEAR310_UART3_IRQ_MASK (1 << 10) |
44 | #define UART4_IRQ_MASK (1 << 11) | 44 | #define SPEAR310_UART4_IRQ_MASK (1 << 11) |
45 | #define UART5_IRQ_MASK (1 << 12) | 45 | #define SPEAR310_UART5_IRQ_MASK (1 << 12) |
46 | #define EMI_IRQ_MASK (1 << 13) | 46 | #define SPEAR310_EMI_IRQ_MASK (1 << 13) |
47 | #define TDM_HDLC_IRQ_MASK (1 << 14) | 47 | #define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) |
48 | #define RS485_0_IRQ_MASK (1 << 15) | 48 | #define SPEAR310_RS485_0_IRQ_MASK (1 << 15) |
49 | #define RS485_1_IRQ_MASK (1 << 16) | 49 | #define SPEAR310_RS485_1_IRQ_MASK (1 << 16) |
50 | 50 | ||
51 | #define SHIRQ_RAS1_MASK 0x000FF | 51 | #define SPEAR310_SHIRQ_RAS1_MASK 0x000FF |
52 | #define SHIRQ_RAS2_MASK 0x01F00 | 52 | #define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 |
53 | #define SHIRQ_RAS3_MASK 0x02000 | 53 | #define SPEAR310_SHIRQ_RAS3_MASK 0x02000 |
54 | #define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 | 54 | #define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 |
55 | 55 | ||
56 | #endif /* __MACH_SPEAR310_H */ | 56 | #endif /* __MACH_SPEAR310_H */ |
57 | 57 | ||