aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-sa1100/include/mach
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach')
-rw-r--r--arch/arm/mach-sa1100/include/mach/collie.h12
-rw-r--r--arch/arm/mach-sa1100/include/mach/h3600.h73
-rw-r--r--arch/arm/mach-sa1100/include/mach/h3600_gpio.h463
-rw-r--r--arch/arm/mach-sa1100/include/mach/irqs.h22
-rw-r--r--arch/arm/mach-sa1100/include/mach/system.h2
5 files changed, 9 insertions, 563 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index 69e962416e3f..9efb569cdb60 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -14,21 +14,21 @@
14#define __ASM_ARCH_COLLIE_H 14#define __ASM_ARCH_COLLIE_H
15 15
16 16
17#define COLLIE_SCP_CHARGE_ON SCOOP_GPCR_PA11 17#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
18#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0)
18#define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 19#define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12
19#define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 20#define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13
20#define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 21#define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14
21#define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 22#define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15
22#define COLLIE_SCP_5VON SCOOP_GPCR_PA16 23#define COLLIE_SCP_5VON SCOOP_GPCR_PA16
23#define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 24#define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17
24#define COLLIE_SCP_VPEN SCOOP_GPCR_PA18 25#define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7)
25#define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 26#define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19
26 27
27#define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ 28#define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
28 COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \ 29 COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \
29 COLLIE_SCP_LB_VOL_CHG ) 30 COLLIE_SCP_LB_VOL_CHG )
30#define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \ 31#define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R )
31 COLLIE_SCP_CHARGE_ON )
32 32
33/* GPIOs for which the generic definition doesn't say much */ 33/* GPIOs for which the generic definition doesn't say much */
34 34
diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h
index 9cc47fddb335..2827faa47421 100644
--- a/arch/arm/mach-sa1100/include/mach/h3600.h
+++ b/arch/arm/mach-sa1100/include/mach/h3600.h
@@ -29,7 +29,7 @@ typedef int __bitwise pm_request_t;
29#define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ 29#define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */
30 30
31/* generalized support for H3xxx series Compaq Pocket PC's */ 31/* generalized support for H3xxx series Compaq Pocket PC's */
32#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) 32#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600())
33 33
34/* Physical memory regions corresponding to chip selects */ 34/* Physical memory regions corresponding to chip selects */
35#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) 35#define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000)
@@ -93,76 +93,7 @@ enum ipaq_egpio_type {
93 IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ 93 IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */
94}; 94};
95 95
96struct ipaq_model_ops { 96extern void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level);
97 const char *generic_name;
98 void (*control)(enum ipaq_egpio_type, int);
99 unsigned long (*read)(void);
100 void (*blank_callback)(int blank);
101 int (*pm_callback)(int req); /* Primary model callback */
102 int (*pm_callback_aux)(int req); /* Secondary callback (used by HAL modules) */
103};
104
105extern struct ipaq_model_ops ipaq_model_ops;
106
107static __inline__ const char * h3600_generic_name(void)
108{
109 return ipaq_model_ops.generic_name;
110}
111
112static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level)
113{
114 if (ipaq_model_ops.control)
115 ipaq_model_ops.control(x,level);
116}
117
118static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x)
119{
120 if (ipaq_model_ops.control)
121 ipaq_model_ops.control(x,0);
122}
123
124static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x)
125{
126 if (ipaq_model_ops.control)
127 ipaq_model_ops.control(x,1);
128}
129
130static __inline__ unsigned long read_h3600_egpio(void)
131{
132 if (ipaq_model_ops.read)
133 return ipaq_model_ops.read();
134 return 0;
135}
136
137static __inline__ int h3600_register_blank_callback(void (*f)(int))
138{
139 ipaq_model_ops.blank_callback = f;
140 return 0;
141}
142
143static __inline__ void h3600_unregister_blank_callback(void (*f)(int))
144{
145 ipaq_model_ops.blank_callback = NULL;
146}
147
148
149static __inline__ int h3600_register_pm_callback(int (*f)(int))
150{
151 ipaq_model_ops.pm_callback_aux = f;
152 return 0;
153}
154
155static __inline__ void h3600_unregister_pm_callback(int (*f)(int))
156{
157 ipaq_model_ops.pm_callback_aux = NULL;
158}
159
160static __inline__ int h3600_power_management(int req)
161{
162 if (ipaq_model_ops.pm_callback)
163 return ipaq_model_ops.pm_callback(req);
164 return 0;
165}
166 97
167#endif /* ASSEMBLY */ 98#endif /* ASSEMBLY */
168 99
diff --git a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
index 62b0b7879685..a36ca76d018b 100644
--- a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h
@@ -48,22 +48,11 @@
48#define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) 48#define GPIO_H3600_OPT_LOCK GPIO_GPIO (22)
49#define GPIO_H3600_OPT_DET GPIO_GPIO (27) 49#define GPIO_H3600_OPT_DET GPIO_GPIO (27)
50 50
51/* H3800 specific pins */
52#define GPIO_H3800_AC_IN GPIO_GPIO (12)
53#define GPIO_H3800_COM_DSR GPIO_GPIO (13)
54#define GPIO_H3800_MMC_INT GPIO_GPIO (18)
55#define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */
56#define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22)
57#define GPIO_H3800_CLK_OUT GPIO_GPIO (27)
58
59/****************************************************/ 51/****************************************************/
60 52
61#define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 53#define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18
62#define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 54#define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27
63 55
64#define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18
65#define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */
66
67/* H3100 / 3600 EGPIO pins */ 56/* H3100 / 3600 EGPIO pins */
68#define EGPIO_H3600_VPP_ON (1 << 0) 57#define EGPIO_H3600_VPP_ON (1 << 0)
69#define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ 58#define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */
@@ -84,457 +73,5 @@
84#define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ 73#define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */
85#define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ 74#define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */
86 75
87/********************* H3800, ASIC #2 ********************/
88
89#define _H3800_ASIC2_Base (H3600_EGPIO_VIRT)
90#define H3800_ASIC2_OFFSET(s,x,y) \
91 (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
92#define H3800_ASIC2_NOFFSET(s,x,n,y) \
93 (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
94
95#define _H3800_ASIC2_GPIO_Base 0x0000
96#define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */
97#define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */
98#define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */
99#define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */
100#define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */
101#define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */
102#define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */
103#define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */
104#define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */
105#define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */
106
107#define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction )
108#define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
109#define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
110#define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
111#define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
112#define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
113#define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data )
114#define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
115#define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
116#define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
117
118#define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */
119#define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */
120#define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */
121#define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */
122#define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */
123#define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */
124#define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */
125#define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */
126#define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */
127#define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */
128#define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */
129#define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */
130
131#define _H3800_ASIC2_KPIO_Base 0x0200
132#define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */
133#define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */
134#define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */
135#define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */
136#define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */
137#define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */
138#define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */
139#define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */
140#define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */
141#define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */
142
143#define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction )
144#define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType )
145#define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType )
146#define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType )
147#define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear )
148#define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag )
149#define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data )
150#define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut )
151#define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable )
152#define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate )
153
154#define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 )
155#define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 )
156#define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 )
157#define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 )
158#define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 )
159#define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 )
160#define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 )
161#define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 )
162
163#define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */
164#define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */
165#define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */
166#define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */
167#define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */
168#define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */
169#define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */
170#define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */
171#define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */
172#define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */
173#define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */
174#define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */
175
176/* Alternate KPIO functions (set by default) */
177#define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */
178#define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */
179#define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */
180#define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */
181#define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */
182
183#define _H3800_ASIC2_SPI_Base 0x0400
184#define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */
185#define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */
186#define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */
187
188#define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control )
189#define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data )
190#define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled )
191
192#define _H3800_ASIC2_PWM_0_Base 0x0600
193#define _H3800_ASIC2_PWM_1_Base 0x0700
194#define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */
195#define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */
196#define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */
197
198#define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase )
199#define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime )
200#define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime )
201
202#define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase )
203#define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime )
204#define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime )
205
206#define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */
207#define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */
208#define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */
209
210#define _H3800_ASIC2_LED_0_Base 0x0800
211#define _H3800_ASIC2_LED_1_Base 0x0880
212#define _H3800_ASIC2_LED_2_Base 0x0900
213#define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */
214#define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */
215#define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */
216#define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */
217
218#define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase )
219#define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime )
220#define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime )
221#define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock )
222
223#define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase )
224#define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime )
225#define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime )
226#define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock )
227
228#define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase )
229#define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime )
230#define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime )
231#define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock )
232
233#define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */
234#define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */
235#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 )
236#define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */
237
238#define _H3800_ASIC2_UART_0_Base 0x0A00
239#define _H3800_ASIC2_UART_1_Base 0x0C00
240#define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */
241#define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */
242#define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */
243#define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */
244#define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */
245#define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */
246#define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */
247#define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */
248#define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */
249#define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */
250#define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */
251
252#define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive )
253#define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit )
254#define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable )
255#define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify )
256#define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl )
257#define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl )
258#define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus )
259#define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus )
260#define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad )
261#define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL )
262#define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH )
263
264#define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive )
265#define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit )
266#define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable )
267#define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify )
268#define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl )
269#define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl )
270#define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus )
271#define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus )
272#define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad )
273#define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL )
274#define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH )
275
276#define _H3800_ASIC2_TIMER_Base 0x0E00
277#define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */
278
279#define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command )
280
281#define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */
282#define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */
283#define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */
284#define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */
285#define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */
286#define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */
287#define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */
288#define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */
289
290#define _H3800_ASIC2_CLOCK_Base 0x1000
291#define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */
292
293#define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable )
294
295#define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */
296#define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */
297#define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */
298#define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */
299#define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */
300#define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */
301#define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */
302#define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */
303#define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */
304#define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */
305#define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */
306#define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */
307#define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */
308#define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */
309#define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */
310#define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */
311#define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */
312#define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */
313#define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */
314
315#define _H3800_ASIC2_ADC_Base 0x1200
316#define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */
317#define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */
318#define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */
319
320#define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer )
321#define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus )
322#define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data )
323
324#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */
325#define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */
326
327#define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */
328#define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 )
329#define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 )
330#define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */
331#define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */
332
333
334#define _H3800_ASIC2_INTR_Base 0x1600
335#define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */
336#define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */
337#define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */
338
339#define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag )
340#define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale )
341#define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet )
342
343#define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */
344#define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */
345#define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */
346#define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 )
347#define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 )
348#define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 )
349#define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 )
350
351#define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */
352#define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */
353
354
355#define _H3800_ASIC2_OWM_Base 0x1800
356#define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */
357#define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */
358#define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */
359#define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */
360#define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */
361
362#define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command )
363#define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data )
364#define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt )
365#define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable )
366#define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor )
367
368#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */
369#define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */
370#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */
371#define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */
372
373#define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */
374#define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */
375#define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */
376#define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */
377#define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */
378
379#define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */
380#define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */
381#define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */
382#define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */
383#define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */
384
385#define _H3800_ASIC2_FlashCtl_Base 0x1A00
386
387/****************************************************/
388/* H3800, ASIC #1
389 * This ASIC is accesed through ASIC #2, and
390 * mapped into the 1c00 - 1f00 region
391 */
392
393#define H3800_ASIC1_OFFSET(s,x,y) \
394 (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1))))
395
396#define _H3800_ASIC1_MMC_Base 0x1c00
397
398#define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */
399#define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */
400#define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */
401#define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */
402#define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */
403#define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */
404#define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */
405#define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */
406#define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */
407#define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */
408#define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */
409#define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */
410#define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */
411#define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */
412#define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */
413
414#define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock )
415#define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status )
416#define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate )
417#define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister )
418#define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont )
419#define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout )
420#define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout )
421#define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength )
422#define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks )
423#define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask )
424#define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber )
425#define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH )
426#define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL )
427#define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo )
428#define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull )
429
430#define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */
431#define H3800_ASIC1_MMC_START_CLOCK (1 << 1)
432
433#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0)
434#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1)
435#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2)
436#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3)
437#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */
438#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5)
439#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6)
440#define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7)
441#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */
442#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */
443#define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */
444#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */
445
446#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */
447#define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */
448#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */
449#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */
450
451#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00
452#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01
453#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02
454#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03
455#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */
456#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */
457#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */
458#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */
459#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */
460
461#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0)
462#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1)
463#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2)
464#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3)
465
466#define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0)
467
468/********* GPIO **********/
469
470#define _H3800_ASIC1_GPIO_Base 0x1e00
471
472#define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */
473#define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */
474#define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */
475#define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */
476#define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */
477#define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */
478#define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */
479#define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */
480#define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */
481#define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */
482#define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */
483#define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */
484#define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */
485#define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */
486#define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */
487#define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */
488
489#define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask )
490#define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction )
491#define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out )
492#define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType )
493#define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger )
494#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger )
495#define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus )
496#define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus )
497#define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State )
498#define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset )
499#define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask )
500#define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir )
501#define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut )
502#define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status )
503#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir )
504#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut )
505
506#define H3800_ASIC1_GPIO_STATE_MASK (1 << 0)
507#define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1)
508#define H3800_ASIC1_GPIO_STATE_OUT (1 << 2)
509#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3)
510#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4)
511#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5)
512
513#define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0)
514#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1)
515#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2)
516
517/* These are all outputs */
518#define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */
519#define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */
520#define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */
521#define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */
522#define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */
523#define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */
524#define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */
525#define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */
526#define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */
527#define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */
528#define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */
529#define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */
530#define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */
531#define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */
532#define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */
533
534/* Write enable for the flash */
535
536#define _H3800_ASIC1_FlashWP_Base 0x1F00
537#define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */
538#define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON )
539 76
540#endif /* _INCLUDE_H3600_GPIO_H_ */ 77#endif /* _INCLUDE_H3600_GPIO_H_ */
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index 0cb36609b3ac..ae81f80b0cf9 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -153,8 +153,6 @@
153 */ 153 */
154#ifdef CONFIG_SA1111 154#ifdef CONFIG_SA1111
155#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) 155#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
156#elif defined(CONFIG_SA1100_H3800)
157#define NR_IRQS (IRQ_BOARD_END)
158#elif defined(CONFIG_SHARP_LOCOMO) 156#elif defined(CONFIG_SHARP_LOCOMO)
159#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 157#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
160#else 158#else
@@ -175,23 +173,3 @@
175#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) 173#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
176#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) 174#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
177 175
178/* H3800-specific IRQs (CONFIG_SA1100_H3800) */
179#define H3800_KPIO_IRQ_START (IRQ_BOARD_START)
180#define IRQ_H3800_KEY (IRQ_BOARD_START + 0)
181#define IRQ_H3800_SPI (IRQ_BOARD_START + 1)
182#define IRQ_H3800_OWM (IRQ_BOARD_START + 2)
183#define IRQ_H3800_ADC (IRQ_BOARD_START + 3)
184#define IRQ_H3800_UART_0 (IRQ_BOARD_START + 4)
185#define IRQ_H3800_UART_1 (IRQ_BOARD_START + 5)
186#define IRQ_H3800_TIMER_0 (IRQ_BOARD_START + 6)
187#define IRQ_H3800_TIMER_1 (IRQ_BOARD_START + 7)
188#define IRQ_H3800_TIMER_2 (IRQ_BOARD_START + 8)
189#define H3800_KPIO_IRQ_COUNT 9
190
191#define H3800_GPIO_IRQ_START (IRQ_BOARD_START + 9)
192#define IRQ_H3800_PEN (IRQ_BOARD_START + 9)
193#define IRQ_H3800_SD_DETECT (IRQ_BOARD_START + 10)
194#define IRQ_H3800_EAR_IN (IRQ_BOARD_START + 11)
195#define IRQ_H3800_USB_DETECT (IRQ_BOARD_START + 12)
196#define IRQ_H3800_SD_CON_SLT (IRQ_BOARD_START + 13)
197#define H3800_GPIO_IRQ_COUNT 5
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
index 63755ca5b1b4..942b153e251d 100644
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ b/arch/arm/mach-sa1100/include/mach/system.h
@@ -10,7 +10,7 @@ static inline void arch_idle(void)
10 cpu_do_idle(); 10 cpu_do_idle();
11} 11}
12 12
13static inline void arch_reset(char mode) 13static inline void arch_reset(char mode, const char *cmd)
14{ 14{
15 if (mode == 's') { 15 if (mode == 's') {
16 /* Jump into ROM at address 0 */ 16 /* Jump into ROM at address 0 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 04:37:14 -0500