diff options
731 files changed, 43409 insertions, 13869 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/Suspend.txt b/Documentation/arm/Samsung-S3C24XX/Suspend.txt index 0dab6e32c130..a30fe510572b 100644 --- a/Documentation/arm/Samsung-S3C24XX/Suspend.txt +++ b/Documentation/arm/Samsung-S3C24XX/Suspend.txt | |||
| @@ -40,13 +40,13 @@ Resuming | |||
| 40 | Machine Support | 40 | Machine Support |
| 41 | --------------- | 41 | --------------- |
| 42 | 42 | ||
| 43 | The machine specific functions must call the s3c2410_pm_init() function | 43 | The machine specific functions must call the s3c_pm_init() function |
| 44 | to say that its bootloader is capable of resuming. This can be as | 44 | to say that its bootloader is capable of resuming. This can be as |
| 45 | simple as adding the following to the machine's definition: | 45 | simple as adding the following to the machine's definition: |
| 46 | 46 | ||
| 47 | INITMACHINE(s3c2410_pm_init) | 47 | INITMACHINE(s3c_pm_init) |
| 48 | 48 | ||
| 49 | A board can do its own setup before calling s3c2410_pm_init, if it | 49 | A board can do its own setup before calling s3c_pm_init, if it |
| 50 | needs to setup anything else for power management support. | 50 | needs to setup anything else for power management support. |
| 51 | 51 | ||
| 52 | There is currently no support for over-riding the default method of | 52 | There is currently no support for over-riding the default method of |
| @@ -74,7 +74,7 @@ statuc void __init machine_init(void) | |||
| 74 | 74 | ||
| 75 | enable_irq_wake(IRQ_EINT0); | 75 | enable_irq_wake(IRQ_EINT0); |
| 76 | 76 | ||
| 77 | s3c2410_pm_init(); | 77 | s3c_pm_init(); |
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | 80 | ||
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt index dc6045577a8b..43cb1004d35f 100644 --- a/Documentation/arm/memory.txt +++ b/Documentation/arm/memory.txt | |||
| @@ -29,7 +29,14 @@ ffff0000 ffff0fff CPU vector page. | |||
| 29 | CPU supports vector relocation (control | 29 | CPU supports vector relocation (control |
| 30 | register V bit.) | 30 | register V bit.) |
| 31 | 31 | ||
| 32 | ffc00000 fffeffff DMA memory mapping region. Memory returned | 32 | fffe0000 fffeffff XScale cache flush area. This is used |
| 33 | in proc-xscale.S to flush the whole data | ||
| 34 | cache. Free for other usage on non-XScale. | ||
| 35 | |||
| 36 | fff00000 fffdffff Fixmap mapping region. Addresses provided | ||
| 37 | by fix_to_virt() will be located here. | ||
| 38 | |||
| 39 | ffc00000 ffefffff DMA memory mapping region. Memory returned | ||
| 33 | by the dma_alloc_xxx functions will be | 40 | by the dma_alloc_xxx functions will be |
| 34 | dynamically mapped here. | 41 | dynamically mapped here. |
| 35 | 42 | ||
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 6b979d1d09ab..d1e2fcb6298b 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt | |||
| @@ -836,6 +836,12 @@ and is between 256 and 4096 characters. It is defined in the file | |||
| 836 | If specified, z/VM IUCV HVC accepts connections | 836 | If specified, z/VM IUCV HVC accepts connections |
| 837 | from listed z/VM user IDs only. | 837 | from listed z/VM user IDs only. |
| 838 | 838 | ||
| 839 | i2c_bus= [HW] Override the default board specific I2C bus speed | ||
| 840 | or register an additional I2C bus that is not | ||
| 841 | registered from board initialization code. | ||
| 842 | Format: | ||
| 843 | <bus_id>,<clkrate> | ||
| 844 | |||
| 839 | i8042.debug [HW] Toggle i8042 debug mode | 845 | i8042.debug [HW] Toggle i8042 debug mode |
| 840 | i8042.direct [HW] Put keyboard port into non-translated mode | 846 | i8042.direct [HW] Put keyboard port into non-translated mode |
| 841 | i8042.dumbkbd [HW] Pretend that controller can only read data from | 847 | i8042.dumbkbd [HW] Pretend that controller can only read data from |
diff --git a/MAINTAINERS b/MAINTAINERS index d8a4c8d0a554..01243ce6d998 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -502,6 +502,13 @@ P: Richard Purdie | |||
| 502 | M: rpurdie@rpsys.net | 502 | M: rpurdie@rpsys.net |
| 503 | S: Maintained | 503 | S: Maintained |
| 504 | 504 | ||
| 505 | ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE | ||
| 506 | P: Paulius Zaleckas | ||
| 507 | M: paulius.zaleckas@teltonika.lt | ||
| 508 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 509 | T: git gitorious.org/linux-gemini/mainline.git | ||
| 510 | S: Maintained | ||
| 511 | |||
| 505 | ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6) | 512 | ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6) |
| 506 | P: Daniel Ribeiro | 513 | P: Daniel Ribeiro |
| 507 | M: drwyrm@gmail.com | 514 | M: drwyrm@gmail.com |
| @@ -513,6 +520,12 @@ L: openezx-devel@lists.openezx.org (subscribers-only) | |||
| 513 | W: http://www.openezx.org/ | 520 | W: http://www.openezx.org/ |
| 514 | S: Maintained | 521 | S: Maintained |
| 515 | 522 | ||
| 523 | ARM/FARADAY FA526 PORT | ||
| 524 | P: Paulius Zaleckas | ||
| 525 | M: paulius.zaleckas@teltonika.lt | ||
| 526 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 527 | S: Maintained | ||
| 528 | |||
| 516 | ARM/FREESCALE IMX / MXC ARM ARCHITECTURE | 529 | ARM/FREESCALE IMX / MXC ARM ARCHITECTURE |
| 517 | P: Sascha Hauer | 530 | P: Sascha Hauer |
| 518 | M: kernel@pengutronix.de | 531 | M: kernel@pengutronix.de |
| @@ -622,7 +635,7 @@ P: Dirk Opfer | |||
| 622 | M: dirk@opfer-online.de | 635 | M: dirk@opfer-online.de |
| 623 | S: Maintained | 636 | S: Maintained |
| 624 | 637 | ||
| 625 | ARM/PALMTX SUPPORT | 638 | ARM/PALMTX,PALMT5,PALMLD SUPPORT |
| 626 | P: Marek Vasut | 639 | P: Marek Vasut |
| 627 | M: marek.vasut@gmail.com | 640 | M: marek.vasut@gmail.com |
| 628 | W: http://hackndev.com | 641 | W: http://hackndev.com |
| @@ -3570,6 +3583,22 @@ M: linux@arm.linux.org.uk | |||
| 3570 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | 3583 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) |
| 3571 | S: Maintained | 3584 | S: Maintained |
| 3572 | 3585 | ||
| 3586 | PXA168 SUPPORT | ||
| 3587 | P: Eric Miao | ||
| 3588 | M: eric.miao@marvell.com | ||
| 3589 | P: Jason Chagas | ||
| 3590 | M: jason.chagas@marvell.com | ||
| 3591 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 3592 | T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git | ||
| 3593 | S: Supported | ||
| 3594 | |||
| 3595 | PXA910 SUPPORT | ||
| 3596 | P: Eric Miao | ||
| 3597 | M: eric.miao@marvell.com | ||
| 3598 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 3599 | T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git | ||
| 3600 | S: Supported | ||
| 3601 | |||
| 3573 | PXA MMCI DRIVER | 3602 | PXA MMCI DRIVER |
| 3574 | S: Orphan | 3603 | S: Orphan |
| 3575 | 3604 | ||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dbfdf87f993f..e02b893fb909 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -241,6 +241,7 @@ config ARCH_VERSATILE | |||
| 241 | config ARCH_AT91 | 241 | config ARCH_AT91 |
| 242 | bool "Atmel AT91" | 242 | bool "Atmel AT91" |
| 243 | select GENERIC_GPIO | 243 | select GENERIC_GPIO |
| 244 | select ARCH_REQUIRE_GPIOLIB | ||
| 244 | select HAVE_CLK | 245 | select HAVE_CLK |
| 245 | help | 246 | help |
| 246 | This enables support for systems based on the Atmel AT91RM9200, | 247 | This enables support for systems based on the Atmel AT91RM9200, |
| @@ -275,6 +276,14 @@ config ARCH_EP93XX | |||
| 275 | help | 276 | help |
| 276 | This enables support for the Cirrus EP93xx series of CPUs. | 277 | This enables support for the Cirrus EP93xx series of CPUs. |
| 277 | 278 | ||
| 279 | config ARCH_GEMINI | ||
| 280 | bool "Cortina Systems Gemini" | ||
| 281 | select CPU_FA526 | ||
| 282 | select GENERIC_GPIO | ||
| 283 | select ARCH_REQUIRE_GPIOLIB | ||
| 284 | help | ||
| 285 | Support for the Cortina Systems Gemini family SoCs | ||
| 286 | |||
| 278 | config ARCH_FOOTBRIDGE | 287 | config ARCH_FOOTBRIDGE |
| 279 | bool "FootBridge" | 288 | bool "FootBridge" |
| 280 | select CPU_SA110 | 289 | select CPU_SA110 |
| @@ -477,12 +486,29 @@ config ARCH_PXA | |||
| 477 | select HAVE_CLK | 486 | select HAVE_CLK |
| 478 | select COMMON_CLKDEV | 487 | select COMMON_CLKDEV |
| 479 | select ARCH_REQUIRE_GPIOLIB | 488 | select ARCH_REQUIRE_GPIOLIB |
| 489 | select HAVE_CLK | ||
| 490 | select COMMON_CLKDEV | ||
| 480 | select GENERIC_TIME | 491 | select GENERIC_TIME |
| 481 | select GENERIC_CLOCKEVENTS | 492 | select GENERIC_CLOCKEVENTS |
| 482 | select TICK_ONESHOT | 493 | select TICK_ONESHOT |
| 494 | select PLAT_PXA | ||
| 483 | help | 495 | help |
| 484 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | 496 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
| 485 | 497 | ||
| 498 | config ARCH_MMP | ||
| 499 | bool "Marvell PXA168/910" | ||
| 500 | depends on MMU | ||
| 501 | select GENERIC_GPIO | ||
| 502 | select ARCH_REQUIRE_GPIOLIB | ||
| 503 | select HAVE_CLK | ||
| 504 | select COMMON_CLKDEV | ||
| 505 | select GENERIC_TIME | ||
| 506 | select GENERIC_CLOCKEVENTS | ||
| 507 | select TICK_ONESHOT | ||
| 508 | select PLAT_PXA | ||
| 509 | help | ||
| 510 | Support for Marvell's PXA168/910 processor line. | ||
| 511 | |||
| 486 | config ARCH_RPC | 512 | config ARCH_RPC |
| 487 | bool "RiscPC" | 513 | bool "RiscPC" |
| 488 | select ARCH_ACORN | 514 | select ARCH_ACORN |
| @@ -598,6 +624,8 @@ source "arch/arm/mach-ep93xx/Kconfig" | |||
| 598 | 624 | ||
| 599 | source "arch/arm/mach-footbridge/Kconfig" | 625 | source "arch/arm/mach-footbridge/Kconfig" |
| 600 | 626 | ||
| 627 | source "arch/arm/mach-gemini/Kconfig" | ||
| 628 | |||
| 601 | source "arch/arm/mach-integrator/Kconfig" | 629 | source "arch/arm/mach-integrator/Kconfig" |
| 602 | 630 | ||
| 603 | source "arch/arm/mach-iop32x/Kconfig" | 631 | source "arch/arm/mach-iop32x/Kconfig" |
| @@ -617,6 +645,9 @@ source "arch/arm/mach-loki/Kconfig" | |||
| 617 | source "arch/arm/mach-mv78xx0/Kconfig" | 645 | source "arch/arm/mach-mv78xx0/Kconfig" |
| 618 | 646 | ||
| 619 | source "arch/arm/mach-pxa/Kconfig" | 647 | source "arch/arm/mach-pxa/Kconfig" |
| 648 | source "arch/arm/plat-pxa/Kconfig" | ||
| 649 | |||
| 650 | source "arch/arm/mach-mmp/Kconfig" | ||
| 620 | 651 | ||
| 621 | source "arch/arm/mach-sa1100/Kconfig" | 652 | source "arch/arm/mach-sa1100/Kconfig" |
| 622 | 653 | ||
| @@ -686,12 +717,15 @@ config PLAT_IOP | |||
| 686 | config PLAT_ORION | 717 | config PLAT_ORION |
| 687 | bool | 718 | bool |
| 688 | 719 | ||
| 720 | config PLAT_PXA | ||
| 721 | bool | ||
| 722 | |||
| 689 | source arch/arm/mm/Kconfig | 723 | source arch/arm/mm/Kconfig |
| 690 | 724 | ||
| 691 | config IWMMXT | 725 | config IWMMXT |
| 692 | bool "Enable iWMMXt support" | 726 | bool "Enable iWMMXt support" |
| 693 | depends on CPU_XSCALE || CPU_XSC3 | 727 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK |
| 694 | default y if PXA27x || PXA3xx | 728 | default y if PXA27x || PXA3xx || ARCH_MMP |
| 695 | help | 729 | help |
| 696 | Enable support for iWMMXt context switching at run time if | 730 | Enable support for iWMMXt context switching at run time if |
| 697 | running on a CPU that supports it. | 731 | running on a CPU that supports it. |
| @@ -915,6 +949,23 @@ config NODES_SHIFT | |||
| 915 | default "2" | 949 | default "2" |
| 916 | depends on NEED_MULTIPLE_NODES | 950 | depends on NEED_MULTIPLE_NODES |
| 917 | 951 | ||
| 952 | config HIGHMEM | ||
| 953 | bool "High Memory Support (EXPERIMENTAL)" | ||
| 954 | depends on MMU && EXPERIMENTAL | ||
| 955 | help | ||
| 956 | The address space of ARM processors is only 4 Gigabytes large | ||
| 957 | and it has to accommodate user address space, kernel address | ||
| 958 | space as well as some memory mapped IO. That means that, if you | ||
| 959 | have a large amount of physical memory and/or IO, not all of the | ||
| 960 | memory can be "permanently mapped" by the kernel. The physical | ||
| 961 | memory that is not permanently mapped is called "high memory". | ||
| 962 | |||
| 963 | Depending on the selected kernel/user memory split, minimum | ||
| 964 | vmalloc space and actual amount of RAM, you may not need this | ||
| 965 | option which should result in a slightly faster kernel. | ||
| 966 | |||
| 967 | If unsure, say n. | ||
| 968 | |||
| 918 | source "mm/Kconfig" | 969 | source "mm/Kconfig" |
| 919 | 970 | ||
| 920 | config LEDS | 971 | config LEDS |
| @@ -1092,7 +1143,7 @@ source "drivers/cpufreq/Kconfig" | |||
| 1092 | 1143 | ||
| 1093 | config CPU_FREQ_SA1100 | 1144 | config CPU_FREQ_SA1100 |
| 1094 | bool | 1145 | bool |
| 1095 | depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT) | 1146 | depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT) |
| 1096 | default y | 1147 | default y |
| 1097 | 1148 | ||
| 1098 | config CPU_FREQ_SA1110 | 1149 | config CPU_FREQ_SA1110 |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 192ee01a9ba2..a71fd941ade7 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
| @@ -2,18 +2,29 @@ menu "Kernel hacking" | |||
| 2 | 2 | ||
| 3 | source "lib/Kconfig.debug" | 3 | source "lib/Kconfig.debug" |
| 4 | 4 | ||
| 5 | # RMK wants arm kernels compiled with frame pointers so hardwire this to y. | 5 | # RMK wants arm kernels compiled with frame pointers or stack unwinding. |
| 6 | # If you know what you are doing and are willing to live without stack | 6 | # If you know what you are doing and are willing to live without stack |
| 7 | # traces, you can get a slightly smaller kernel by setting this option to | 7 | # traces, you can get a slightly smaller kernel by setting this option to |
| 8 | # n, but then RMK will have to kill you ;). | 8 | # n, but then RMK will have to kill you ;). |
| 9 | config FRAME_POINTER | 9 | config FRAME_POINTER |
| 10 | bool | 10 | bool |
| 11 | default y | 11 | default y if !ARM_UNWIND |
| 12 | help | 12 | help |
| 13 | If you say N here, the resulting kernel will be slightly smaller and | 13 | If you say N here, the resulting kernel will be slightly smaller and |
| 14 | faster. However, when a problem occurs with the kernel, the | 14 | faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled, |
| 15 | information that is reported is severely limited. Most people | 15 | when a problem occurs with the kernel, the information that is |
| 16 | should say Y here. | 16 | reported is severely limited. |
| 17 | |||
| 18 | config ARM_UNWIND | ||
| 19 | bool "Enable stack unwinding support" | ||
| 20 | depends on AEABI && EXPERIMENTAL | ||
| 21 | default y | ||
| 22 | help | ||
| 23 | This option enables stack unwinding support in the kernel | ||
| 24 | using the information automatically generated by the | ||
| 25 | compiler. The resulting kernel image is slightly bigger but | ||
| 26 | the performance is not affected. Currently, this feature | ||
| 27 | only works with EABI compilers. If unsure say Y. | ||
| 17 | 28 | ||
| 18 | config DEBUG_USER | 29 | config DEBUG_USER |
| 19 | bool "Verbose user fault messages" | 30 | bool "Verbose user fault messages" |
| @@ -66,7 +77,7 @@ config DEBUG_ICEDCC | |||
| 66 | Say Y here if you want the debug print routines to direct their | 77 | Say Y here if you want the debug print routines to direct their |
| 67 | output to the EmbeddedICE macrocell's DCC channel using | 78 | output to the EmbeddedICE macrocell's DCC channel using |
| 68 | co-processor 14. This is known to work on the ARM9 style ICE | 79 | co-processor 14. This is known to work on the ARM9 style ICE |
| 69 | channel. | 80 | channel and on the XScale with the PEEDI. |
| 70 | 81 | ||
| 71 | It does include a timeout to ensure that the system does not | 82 | It does include a timeout to ensure that the system does not |
| 72 | totally freeze when there is nothing connected to read. | 83 | totally freeze when there is nothing connected to read. |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 24e0f0187697..e84729bf13d4 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -72,6 +72,7 @@ tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi | |||
| 72 | tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi | 72 | tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi |
| 73 | tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi | 73 | tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi |
| 74 | tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi | 74 | tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi |
| 75 | tune-$(CONFIG_CPU_FA526) :=-mtune=arm9tdmi | ||
| 75 | tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 | 76 | tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 |
| 76 | tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 | 77 | tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 |
| 77 | tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale | 78 | tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale |
| @@ -85,6 +86,10 @@ else | |||
| 85 | CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) | 86 | CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) |
| 86 | endif | 87 | endif |
| 87 | 88 | ||
| 89 | ifeq ($(CONFIG_ARM_UNWIND),y) | ||
| 90 | CFLAGS_ABI +=-funwind-tables | ||
| 91 | endif | ||
| 92 | |||
| 88 | # Need -Uarm for gcc < 3.x | 93 | # Need -Uarm for gcc < 3.x |
| 89 | KBUILD_CFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm | 94 | KBUILD_CFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm |
| 90 | KBUILD_AFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float | 95 | KBUILD_AFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float |
| @@ -105,8 +110,11 @@ ifeq ($(CONFIG_ARCH_SA1100),y) | |||
| 105 | textofs-$(CONFIG_SA1111) := 0x00208000 | 110 | textofs-$(CONFIG_SA1111) := 0x00208000 |
| 106 | endif | 111 | endif |
| 107 | machine-$(CONFIG_ARCH_PXA) := pxa | 112 | machine-$(CONFIG_ARCH_PXA) := pxa |
| 113 | machine-$(CONFIG_ARCH_MMP) := mmp | ||
| 114 | plat-$(CONFIG_PLAT_PXA) := pxa | ||
| 108 | machine-$(CONFIG_ARCH_L7200) := l7200 | 115 | machine-$(CONFIG_ARCH_L7200) := l7200 |
| 109 | machine-$(CONFIG_ARCH_INTEGRATOR) := integrator | 116 | machine-$(CONFIG_ARCH_INTEGRATOR) := integrator |
| 117 | machine-$(CONFIG_ARCH_GEMINI) := gemini | ||
| 110 | textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 | 118 | textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 |
| 111 | machine-$(CONFIG_ARCH_CLPS711X) := clps711x | 119 | machine-$(CONFIG_ARCH_CLPS711X) := clps711x |
| 112 | machine-$(CONFIG_ARCH_IOP32X) := iop32x | 120 | machine-$(CONFIG_ARCH_IOP32X) := iop32x |
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 77d614232d81..b371fba1b954 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
| @@ -27,6 +27,12 @@ | |||
| 27 | .macro writeb, ch, rb | 27 | .macro writeb, ch, rb |
| 28 | mcr p14, 0, \ch, c0, c5, 0 | 28 | mcr p14, 0, \ch, c0, c5, 0 |
| 29 | .endm | 29 | .endm |
| 30 | #elif defined(CONFIG_CPU_XSCALE) | ||
| 31 | .macro loadsp, rb | ||
| 32 | .endm | ||
| 33 | .macro writeb, ch, rb | ||
| 34 | mcr p14, 0, \ch, c8, c0, 0 | ||
| 35 | .endm | ||
| 30 | #else | 36 | #else |
| 31 | .macro loadsp, rb | 37 | .macro loadsp, rb |
| 32 | .endm | 38 | .endm |
| @@ -459,6 +465,20 @@ __armv7_mmu_cache_on: | |||
| 459 | mcr p15, 0, r0, c7, c5, 4 @ ISB | 465 | mcr p15, 0, r0, c7, c5, 4 @ ISB |
| 460 | mov pc, r12 | 466 | mov pc, r12 |
| 461 | 467 | ||
| 468 | __fa526_cache_on: | ||
| 469 | mov r12, lr | ||
| 470 | bl __setup_mmu | ||
| 471 | mov r0, #0 | ||
| 472 | mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache | ||
| 473 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 474 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | ||
| 475 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | ||
| 476 | orr r0, r0, #0x1000 @ I-cache enable | ||
| 477 | bl __common_mmu_cache_on | ||
| 478 | mov r0, #0 | ||
| 479 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | ||
| 480 | mov pc, r12 | ||
| 481 | |||
| 462 | __arm6_mmu_cache_on: | 482 | __arm6_mmu_cache_on: |
| 463 | mov r12, lr | 483 | mov r12, lr |
| 464 | bl __setup_mmu | 484 | bl __setup_mmu |
| @@ -630,12 +650,30 @@ proc_types: | |||
| 630 | b __armv4_mmu_cache_off | 650 | b __armv4_mmu_cache_off |
| 631 | b __armv4_mmu_cache_flush | 651 | b __armv4_mmu_cache_flush |
| 632 | 652 | ||
| 653 | .word 0x56158000 @ PXA168 | ||
| 654 | .word 0xfffff000 | ||
| 655 | b __armv4_mmu_cache_on | ||
| 656 | b __armv4_mmu_cache_off | ||
| 657 | b __armv5tej_mmu_cache_flush | ||
| 658 | |||
| 659 | .word 0x56056930 | ||
| 660 | .word 0xff0ffff0 @ PXA935 | ||
| 661 | b __armv4_mmu_cache_on | ||
| 662 | b __armv4_mmu_cache_off | ||
| 663 | b __armv4_mmu_cache_flush | ||
| 664 | |||
| 633 | .word 0x56050000 @ Feroceon | 665 | .word 0x56050000 @ Feroceon |
| 634 | .word 0xff0f0000 | 666 | .word 0xff0f0000 |
| 635 | b __armv4_mmu_cache_on | 667 | b __armv4_mmu_cache_on |
| 636 | b __armv4_mmu_cache_off | 668 | b __armv4_mmu_cache_off |
| 637 | b __armv5tej_mmu_cache_flush | 669 | b __armv5tej_mmu_cache_flush |
| 638 | 670 | ||
| 671 | .word 0x66015261 @ FA526 | ||
| 672 | .word 0xff01fff1 | ||
| 673 | b __fa526_cache_on | ||
| 674 | b __armv4_mmu_cache_off | ||
| 675 | b __fa526_cache_flush | ||
| 676 | |||
| 639 | @ These match on the architecture ID | 677 | @ These match on the architecture ID |
| 640 | 678 | ||
| 641 | .word 0x00020000 @ ARMv4T | 679 | .word 0x00020000 @ ARMv4T |
| @@ -775,6 +813,12 @@ __armv4_mpu_cache_flush: | |||
| 775 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | 813 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
| 776 | mov pc, lr | 814 | mov pc, lr |
| 777 | 815 | ||
| 816 | __fa526_cache_flush: | ||
| 817 | mov r1, #0 | ||
| 818 | mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache | ||
| 819 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | ||
| 820 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | ||
| 821 | mov pc, lr | ||
| 778 | 822 | ||
| 779 | __armv6_mmu_cache_flush: | 823 | __armv6_mmu_cache_flush: |
| 780 | mov r1, #0 | 824 | mov r1, #0 |
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 3fc08413fff0..393c81641314 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c | |||
| @@ -46,6 +46,21 @@ static void icedcc_putc(int ch) | |||
| 46 | 46 | ||
| 47 | asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); | 47 | asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); |
| 48 | } | 48 | } |
| 49 | #elif defined(CONFIG_CPU_XSCALE) | ||
| 50 | |||
| 51 | static void icedcc_putc(int ch) | ||
| 52 | { | ||
| 53 | int status, i = 0x4000000; | ||
| 54 | |||
| 55 | do { | ||
| 56 | if (--i < 0) | ||
| 57 | return; | ||
| 58 | |||
| 59 | asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); | ||
| 60 | } while (status & (1 << 28)); | ||
| 61 | |||
| 62 | asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); | ||
| 63 | } | ||
| 49 | 64 | ||
| 50 | #else | 65 | #else |
| 51 | 66 | ||
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index 153a07e7222b..a5924b9b88bd 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in | |||
| @@ -11,6 +11,11 @@ OUTPUT_ARCH(arm) | |||
| 11 | ENTRY(_start) | 11 | ENTRY(_start) |
| 12 | SECTIONS | 12 | SECTIONS |
| 13 | { | 13 | { |
| 14 | /DISCARD/ : { | ||
| 15 | *(.ARM.exidx*) | ||
| 16 | *(.ARM.extab*) | ||
| 17 | } | ||
| 18 | |||
| 14 | . = TEXT_START; | 19 | . = TEXT_START; |
| 15 | _text = .; | 20 | _text = .; |
| 16 | 21 | ||
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c index 1037bba18329..5589444ff437 100644 --- a/arch/arm/common/clkdev.c +++ b/arch/arm/common/clkdev.c | |||
| @@ -62,9 +62,8 @@ static struct clk *clk_find(const char *dev_id, const char *con_id) | |||
| 62 | return clk; | 62 | return clk; |
| 63 | } | 63 | } |
| 64 | 64 | ||
| 65 | struct clk *clk_get(struct device *dev, const char *con_id) | 65 | struct clk *clk_get_sys(const char *dev_id, const char *con_id) |
| 66 | { | 66 | { |
| 67 | const char *dev_id = dev ? dev_name(dev) : NULL; | ||
| 68 | struct clk *clk; | 67 | struct clk *clk; |
| 69 | 68 | ||
| 70 | mutex_lock(&clocks_mutex); | 69 | mutex_lock(&clocks_mutex); |
| @@ -75,6 +74,14 @@ struct clk *clk_get(struct device *dev, const char *con_id) | |||
| 75 | 74 | ||
| 76 | return clk ? clk : ERR_PTR(-ENOENT); | 75 | return clk ? clk : ERR_PTR(-ENOENT); |
| 77 | } | 76 | } |
| 77 | EXPORT_SYMBOL(clk_get_sys); | ||
| 78 | |||
| 79 | struct clk *clk_get(struct device *dev, const char *con_id) | ||
| 80 | { | ||
| 81 | const char *dev_id = dev ? dev_name(dev) : NULL; | ||
| 82 | |||
| 83 | return clk_get_sys(dev_id, con_id); | ||
| 84 | } | ||
| 78 | EXPORT_SYMBOL(clk_get); | 85 | EXPORT_SYMBOL(clk_get); |
| 79 | 86 | ||
| 80 | void clk_put(struct clk *clk) | 87 | void clk_put(struct clk *clk) |
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index f030f0775be7..734ac9135998 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/module.h> | 25 | #include <linux/module.h> |
| 26 | #include <linux/init.h> | 26 | #include <linux/init.h> |
| 27 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
| 28 | #include <linux/page-flags.h> | ||
| 28 | #include <linux/device.h> | 29 | #include <linux/device.h> |
| 29 | #include <linux/dma-mapping.h> | 30 | #include <linux/dma-mapping.h> |
| 30 | #include <linux/dmapool.h> | 31 | #include <linux/dmapool.h> |
| @@ -349,6 +350,12 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
| 349 | 350 | ||
| 350 | BUG_ON(!valid_dma_direction(dir)); | 351 | BUG_ON(!valid_dma_direction(dir)); |
| 351 | 352 | ||
| 353 | if (PageHighMem(page)) { | ||
| 354 | dev_err(dev, "DMA buffer bouncing of HIGHMEM pages " | ||
| 355 | "is not supported\n"); | ||
| 356 | return ~0; | ||
| 357 | } | ||
| 358 | |||
| 352 | return map_single(dev, page_address(page) + offset, size, dir); | 359 | return map_single(dev, page_address(page) + offset, size, dir); |
| 353 | } | 360 | } |
| 354 | EXPORT_SYMBOL(dma_map_page); | 361 | EXPORT_SYMBOL(dma_map_page); |
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 697c64913990..7713a08bb10c 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c | |||
| @@ -124,37 +124,6 @@ static int scoop_gpio_direction_output(struct gpio_chip *chip, | |||
| 124 | return 0; | 124 | return 0; |
| 125 | } | 125 | } |
| 126 | 126 | ||
| 127 | unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) | ||
| 128 | { | ||
| 129 | unsigned short gpio_bit; | ||
| 130 | unsigned long flag; | ||
| 131 | struct scoop_dev *sdev = dev_get_drvdata(dev); | ||
| 132 | |||
| 133 | spin_lock_irqsave(&sdev->scoop_lock, flag); | ||
| 134 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit; | ||
| 135 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); | ||
| 136 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | ||
| 137 | |||
| 138 | return gpio_bit; | ||
| 139 | } | ||
| 140 | |||
| 141 | unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit) | ||
| 142 | { | ||
| 143 | unsigned short gpio_bit; | ||
| 144 | unsigned long flag; | ||
| 145 | struct scoop_dev *sdev = dev_get_drvdata(dev); | ||
| 146 | |||
| 147 | spin_lock_irqsave(&sdev->scoop_lock, flag); | ||
| 148 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit; | ||
| 149 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); | ||
| 150 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | ||
| 151 | |||
| 152 | return gpio_bit; | ||
| 153 | } | ||
| 154 | |||
| 155 | EXPORT_SYMBOL(set_scoop_gpio); | ||
| 156 | EXPORT_SYMBOL(reset_scoop_gpio); | ||
| 157 | |||
| 158 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) | 127 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) |
| 159 | { | 128 | { |
| 160 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 129 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index 780bbf7cb26f..140f1d721d50 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c | |||
| @@ -29,8 +29,8 @@ | |||
| 29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 30 | #include <asm/irq.h> | 30 | #include <asm/irq.h> |
| 31 | #include <mach/pm.h> | 31 | #include <mach/pm.h> |
| 32 | #include <mach/pxa-regs.h> | ||
| 33 | #include <mach/pxa2xx-regs.h> | 32 | #include <mach/pxa2xx-regs.h> |
| 33 | #include <mach/regs-rtc.h> | ||
| 34 | #include <mach/sharpsl.h> | 34 | #include <mach/sharpsl.h> |
| 35 | #include <asm/hardware/sharpsl_pm.h> | 35 | #include <asm/hardware/sharpsl_pm.h> |
| 36 | 36 | ||
diff --git a/arch/arm/configs/acs5k_defconfig b/arch/arm/configs/acs5k_defconfig new file mode 100644 index 000000000000..1cab4e79d368 --- /dev/null +++ b/arch/arm/configs/acs5k_defconfig | |||
| @@ -0,0 +1,1233 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.27-simtec-micrel1 | ||
| 4 | # Tue Dec 16 13:31:34 2008 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 26 | CONFIG_ZONE_DMA=y | ||
| 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 28 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 29 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 30 | |||
| 31 | # | ||
| 32 | # General setup | ||
| 33 | # | ||
| 34 | CONFIG_EXPERIMENTAL=y | ||
| 35 | CONFIG_BROKEN_ON_SMP=y | ||
| 36 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 37 | CONFIG_LOCALVERSION="" | ||
| 38 | CONFIG_LOCALVERSION_AUTO=y | ||
| 39 | # CONFIG_SWAP is not set | ||
| 40 | CONFIG_SYSVIPC=y | ||
| 41 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 42 | CONFIG_POSIX_MQUEUE=y | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | # CONFIG_IKCONFIG is not set | ||
| 47 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 48 | # CONFIG_CGROUPS is not set | ||
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | CONFIG_SYSFS_DEPRECATED=y | ||
| 51 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 52 | # CONFIG_RELAY is not set | ||
| 53 | CONFIG_NAMESPACES=y | ||
| 54 | # CONFIG_UTS_NS is not set | ||
| 55 | # CONFIG_IPC_NS is not set | ||
| 56 | # CONFIG_USER_NS is not set | ||
| 57 | # CONFIG_PID_NS is not set | ||
| 58 | CONFIG_BLK_DEV_INITRD=y | ||
| 59 | CONFIG_INITRAMFS_SOURCE="" | ||
| 60 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 61 | CONFIG_SYSCTL=y | ||
| 62 | # CONFIG_EMBEDDED is not set | ||
| 63 | CONFIG_UID16=y | ||
| 64 | CONFIG_SYSCTL_SYSCALL=y | ||
| 65 | CONFIG_KALLSYMS=y | ||
| 66 | # CONFIG_KALLSYMS_ALL is not set | ||
| 67 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 68 | CONFIG_HOTPLUG=y | ||
| 69 | CONFIG_PRINTK=y | ||
| 70 | CONFIG_BUG=y | ||
| 71 | CONFIG_ELF_CORE=y | ||
| 72 | CONFIG_COMPAT_BRK=y | ||
| 73 | CONFIG_BASE_FULL=y | ||
| 74 | CONFIG_FUTEX=y | ||
| 75 | CONFIG_ANON_INODES=y | ||
| 76 | CONFIG_EPOLL=y | ||
| 77 | CONFIG_SIGNALFD=y | ||
| 78 | CONFIG_TIMERFD=y | ||
| 79 | CONFIG_EVENTFD=y | ||
| 80 | CONFIG_SHMEM=y | ||
| 81 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 82 | CONFIG_SLAB=y | ||
| 83 | # CONFIG_SLUB is not set | ||
| 84 | # CONFIG_SLOB is not set | ||
| 85 | # CONFIG_PROFILING is not set | ||
| 86 | # CONFIG_MARKERS is not set | ||
| 87 | CONFIG_HAVE_OPROFILE=y | ||
| 88 | # CONFIG_KPROBES is not set | ||
| 89 | # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set | ||
| 90 | # CONFIG_HAVE_IOREMAP_PROT is not set | ||
| 91 | CONFIG_HAVE_KPROBES=y | ||
| 92 | CONFIG_HAVE_KRETPROBES=y | ||
| 93 | # CONFIG_HAVE_ARCH_TRACEHOOK is not set | ||
| 94 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 95 | # CONFIG_USE_GENERIC_SMP_HELPERS is not set | ||
| 96 | # CONFIG_HAVE_CLK is not set | ||
| 97 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 98 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 99 | CONFIG_SLABINFO=y | ||
| 100 | CONFIG_RT_MUTEXES=y | ||
| 101 | # CONFIG_TINY_SHMEM is not set | ||
| 102 | CONFIG_BASE_SMALL=0 | ||
| 103 | CONFIG_MODULES=y | ||
| 104 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 105 | CONFIG_MODULE_UNLOAD=y | ||
| 106 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 107 | # CONFIG_MODVERSIONS is not set | ||
| 108 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 109 | CONFIG_KMOD=y | ||
| 110 | CONFIG_BLOCK=y | ||
| 111 | # CONFIG_LBD is not set | ||
| 112 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 113 | # CONFIG_LSF is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | CONFIG_IOSCHED_AS=y | ||
| 122 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 123 | # CONFIG_IOSCHED_CFQ is not set | ||
| 124 | CONFIG_DEFAULT_AS=y | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | # CONFIG_DEFAULT_CFQ is not set | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 129 | CONFIG_CLASSIC_RCU=y | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 140 | # CONFIG_ARCH_CLPS711X is not set | ||
| 141 | # CONFIG_ARCH_EBSA110 is not set | ||
| 142 | # CONFIG_ARCH_EP93XX is not set | ||
| 143 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 144 | # CONFIG_ARCH_NETX is not set | ||
| 145 | # CONFIG_ARCH_H720X is not set | ||
| 146 | # CONFIG_ARCH_IMX is not set | ||
| 147 | # CONFIG_ARCH_IOP13XX is not set | ||
| 148 | # CONFIG_ARCH_IOP32X is not set | ||
| 149 | # CONFIG_ARCH_IOP33X is not set | ||
| 150 | # CONFIG_ARCH_IXP23XX is not set | ||
| 151 | # CONFIG_ARCH_IXP2000 is not set | ||
| 152 | # CONFIG_ARCH_IXP4XX is not set | ||
| 153 | # CONFIG_ARCH_L7200 is not set | ||
| 154 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 155 | CONFIG_ARCH_KS8695=y | ||
| 156 | # CONFIG_ARCH_NS9XXX is not set | ||
| 157 | # CONFIG_ARCH_LOKI is not set | ||
| 158 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 159 | # CONFIG_ARCH_MXC is not set | ||
| 160 | # CONFIG_ARCH_ORION5X is not set | ||
| 161 | # CONFIG_ARCH_PNX4008 is not set | ||
| 162 | # CONFIG_ARCH_PXA is not set | ||
| 163 | # CONFIG_ARCH_RPC is not set | ||
| 164 | # CONFIG_ARCH_SA1100 is not set | ||
| 165 | # CONFIG_ARCH_S3C2410 is not set | ||
| 166 | # CONFIG_ARCH_SHARK is not set | ||
| 167 | # CONFIG_ARCH_LH7A40X is not set | ||
| 168 | # CONFIG_ARCH_DAVINCI is not set | ||
| 169 | # CONFIG_ARCH_OMAP is not set | ||
| 170 | # CONFIG_ARCH_MSM7X00A is not set | ||
| 171 | |||
| 172 | # | ||
| 173 | # Boot options | ||
| 174 | # | ||
| 175 | |||
| 176 | # | ||
| 177 | # Power management | ||
| 178 | # | ||
| 179 | |||
| 180 | # | ||
| 181 | # Kendin/Micrel KS8695 Implementations | ||
| 182 | # | ||
| 183 | CONFIG_MACH_KS8695=y | ||
| 184 | CONFIG_MACH_DSM320=y | ||
| 185 | CONFIG_MACH_ACS5K=y | ||
| 186 | |||
| 187 | # | ||
| 188 | # Processor Type | ||
| 189 | # | ||
| 190 | CONFIG_CPU_32=y | ||
| 191 | CONFIG_CPU_ARM922T=y | ||
| 192 | CONFIG_CPU_32v4T=y | ||
| 193 | CONFIG_CPU_ABRT_EV4T=y | ||
| 194 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 195 | CONFIG_CPU_CACHE_V4WT=y | ||
| 196 | CONFIG_CPU_CACHE_VIVT=y | ||
| 197 | CONFIG_CPU_COPY_V4WB=y | ||
| 198 | CONFIG_CPU_TLB_V4WBI=y | ||
| 199 | CONFIG_CPU_CP15=y | ||
| 200 | CONFIG_CPU_CP15_MMU=y | ||
| 201 | |||
| 202 | # | ||
| 203 | # Processor Features | ||
| 204 | # | ||
| 205 | # CONFIG_ARM_THUMB is not set | ||
| 206 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 207 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 208 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 209 | # CONFIG_OUTER_CACHE is not set | ||
| 210 | |||
| 211 | # | ||
| 212 | # Bus support | ||
| 213 | # | ||
| 214 | CONFIG_PCI=y | ||
| 215 | CONFIG_PCI_SYSCALL=y | ||
| 216 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 217 | CONFIG_PCI_LEGACY=y | ||
| 218 | CONFIG_PCI_DEBUG=y | ||
| 219 | CONFIG_PCCARD=y | ||
| 220 | # CONFIG_PCMCIA_DEBUG is not set | ||
| 221 | CONFIG_PCMCIA=y | ||
| 222 | CONFIG_PCMCIA_LOAD_CIS=y | ||
| 223 | CONFIG_PCMCIA_IOCTL=y | ||
| 224 | CONFIG_CARDBUS=y | ||
| 225 | |||
| 226 | # | ||
| 227 | # PC-card bridges | ||
| 228 | # | ||
| 229 | CONFIG_YENTA=y | ||
| 230 | CONFIG_YENTA_O2=y | ||
| 231 | CONFIG_YENTA_RICOH=y | ||
| 232 | CONFIG_YENTA_TI=y | ||
| 233 | CONFIG_YENTA_ENE_TUNE=y | ||
| 234 | CONFIG_YENTA_TOSHIBA=y | ||
| 235 | # CONFIG_PD6729 is not set | ||
| 236 | # CONFIG_I82092 is not set | ||
| 237 | CONFIG_PCCARD_NONSTATIC=y | ||
| 238 | |||
| 239 | # | ||
| 240 | # Kernel Features | ||
| 241 | # | ||
| 242 | # CONFIG_TICK_ONESHOT is not set | ||
| 243 | # CONFIG_PREEMPT is not set | ||
| 244 | CONFIG_HZ=100 | ||
| 245 | CONFIG_AEABI=y | ||
| 246 | CONFIG_OABI_COMPAT=y | ||
| 247 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 248 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 249 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 250 | CONFIG_FLATMEM_MANUAL=y | ||
| 251 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 252 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 253 | CONFIG_FLATMEM=y | ||
| 254 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 255 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 256 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 257 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 258 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 259 | # CONFIG_RESOURCES_64BIT is not set | ||
| 260 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 261 | CONFIG_BOUNCE=y | ||
| 262 | CONFIG_VIRT_TO_BUS=y | ||
| 263 | # CONFIG_LEDS is not set | ||
| 264 | CONFIG_ALIGNMENT_TRAP=y | ||
| 265 | |||
| 266 | # | ||
| 267 | # Boot options | ||
| 268 | # | ||
| 269 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 270 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 271 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" | ||
| 272 | # CONFIG_XIP_KERNEL is not set | ||
| 273 | # CONFIG_KEXEC is not set | ||
| 274 | |||
| 275 | # | ||
| 276 | # Floating point emulation | ||
| 277 | # | ||
| 278 | |||
| 279 | # | ||
| 280 | # At least one emulation must be selected | ||
| 281 | # | ||
| 282 | # CONFIG_FPE_NWFPE is not set | ||
| 283 | # CONFIG_FPE_FASTFPE is not set | ||
| 284 | |||
| 285 | # | ||
| 286 | # Userspace binary formats | ||
| 287 | # | ||
| 288 | CONFIG_BINFMT_ELF=y | ||
| 289 | # CONFIG_BINFMT_AOUT is not set | ||
| 290 | # CONFIG_BINFMT_MISC is not set | ||
| 291 | |||
| 292 | # | ||
| 293 | # Power management options | ||
| 294 | # | ||
| 295 | # CONFIG_PM is not set | ||
| 296 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 297 | CONFIG_NET=y | ||
| 298 | |||
| 299 | # | ||
| 300 | # Networking options | ||
| 301 | # | ||
| 302 | CONFIG_PACKET=y | ||
| 303 | # CONFIG_PACKET_MMAP is not set | ||
| 304 | CONFIG_UNIX=y | ||
| 305 | CONFIG_XFRM=y | ||
| 306 | # CONFIG_XFRM_USER is not set | ||
| 307 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 308 | # CONFIG_XFRM_MIGRATE is not set | ||
| 309 | # CONFIG_XFRM_STATISTICS is not set | ||
| 310 | # CONFIG_NET_KEY is not set | ||
| 311 | CONFIG_INET=y | ||
| 312 | # CONFIG_IP_MULTICAST is not set | ||
| 313 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 314 | CONFIG_IP_FIB_HASH=y | ||
| 315 | CONFIG_IP_PNP=y | ||
| 316 | CONFIG_IP_PNP_DHCP=y | ||
| 317 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 318 | # CONFIG_IP_PNP_RARP is not set | ||
| 319 | # CONFIG_NET_IPIP is not set | ||
| 320 | # CONFIG_NET_IPGRE is not set | ||
| 321 | # CONFIG_ARPD is not set | ||
| 322 | # CONFIG_SYN_COOKIES is not set | ||
| 323 | # CONFIG_INET_AH is not set | ||
| 324 | # CONFIG_INET_ESP is not set | ||
| 325 | # CONFIG_INET_IPCOMP is not set | ||
| 326 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 327 | # CONFIG_INET_TUNNEL is not set | ||
| 328 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 329 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 330 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 331 | # CONFIG_INET_LRO is not set | ||
| 332 | CONFIG_INET_DIAG=y | ||
| 333 | CONFIG_INET_TCP_DIAG=y | ||
| 334 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 335 | CONFIG_TCP_CONG_CUBIC=y | ||
| 336 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 337 | # CONFIG_TCP_MD5SIG is not set | ||
| 338 | # CONFIG_IPV6 is not set | ||
| 339 | # CONFIG_NETWORK_SECMARK is not set | ||
| 340 | # CONFIG_NETFILTER is not set | ||
| 341 | # CONFIG_IP_DCCP is not set | ||
| 342 | # CONFIG_IP_SCTP is not set | ||
| 343 | # CONFIG_TIPC is not set | ||
| 344 | # CONFIG_ATM is not set | ||
| 345 | # CONFIG_BRIDGE is not set | ||
| 346 | # CONFIG_VLAN_8021Q is not set | ||
| 347 | # CONFIG_DECNET is not set | ||
| 348 | # CONFIG_LLC2 is not set | ||
| 349 | # CONFIG_IPX is not set | ||
| 350 | # CONFIG_ATALK is not set | ||
| 351 | # CONFIG_X25 is not set | ||
| 352 | # CONFIG_LAPB is not set | ||
| 353 | # CONFIG_ECONET is not set | ||
| 354 | # CONFIG_WAN_ROUTER is not set | ||
| 355 | # CONFIG_NET_SCHED is not set | ||
| 356 | |||
| 357 | # | ||
| 358 | # Network testing | ||
| 359 | # | ||
| 360 | # CONFIG_NET_PKTGEN is not set | ||
| 361 | # CONFIG_HAMRADIO is not set | ||
| 362 | # CONFIG_CAN is not set | ||
| 363 | # CONFIG_IRDA is not set | ||
| 364 | # CONFIG_BT is not set | ||
| 365 | # CONFIG_AF_RXRPC is not set | ||
| 366 | |||
| 367 | # | ||
| 368 | # Wireless | ||
| 369 | # | ||
| 370 | # CONFIG_CFG80211 is not set | ||
| 371 | CONFIG_WIRELESS_EXT=y | ||
| 372 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 373 | # CONFIG_MAC80211 is not set | ||
| 374 | # CONFIG_IEEE80211 is not set | ||
| 375 | # CONFIG_RFKILL is not set | ||
| 376 | # CONFIG_NET_9P is not set | ||
| 377 | |||
| 378 | # | ||
| 379 | # Device Drivers | ||
| 380 | # | ||
| 381 | |||
| 382 | # | ||
| 383 | # Generic Driver Options | ||
| 384 | # | ||
| 385 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 386 | CONFIG_STANDALONE=y | ||
| 387 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 388 | CONFIG_FW_LOADER=y | ||
| 389 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 390 | CONFIG_EXTRA_FIRMWARE="" | ||
| 391 | # CONFIG_DEBUG_DRIVER is not set | ||
| 392 | # CONFIG_DEBUG_DEVRES is not set | ||
| 393 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 394 | # CONFIG_CONNECTOR is not set | ||
| 395 | CONFIG_MTD=y | ||
| 396 | # CONFIG_MTD_DEBUG is not set | ||
| 397 | CONFIG_MTD_CONCAT=y | ||
| 398 | CONFIG_MTD_PARTITIONS=y | ||
| 399 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 400 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 401 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 402 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 403 | |||
| 404 | # | ||
| 405 | # User Modules And Translation Layers | ||
| 406 | # | ||
| 407 | CONFIG_MTD_CHAR=y | ||
| 408 | CONFIG_MTD_BLKDEVS=y | ||
| 409 | CONFIG_MTD_BLOCK=y | ||
| 410 | # CONFIG_FTL is not set | ||
| 411 | # CONFIG_NFTL is not set | ||
| 412 | # CONFIG_INFTL is not set | ||
| 413 | # CONFIG_RFD_FTL is not set | ||
| 414 | # CONFIG_SSFDC is not set | ||
| 415 | # CONFIG_MTD_OOPS is not set | ||
| 416 | |||
| 417 | # | ||
| 418 | # RAM/ROM/Flash chip drivers | ||
| 419 | # | ||
| 420 | CONFIG_MTD_CFI=y | ||
| 421 | CONFIG_MTD_JEDECPROBE=y | ||
| 422 | CONFIG_MTD_GEN_PROBE=y | ||
| 423 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 424 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 425 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 426 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 427 | # CONFIG_MTD_CFI_GEOMETRY is not set | ||
| 428 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 429 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 430 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 431 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 432 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 433 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 434 | CONFIG_MTD_CFI_I1=y | ||
| 435 | CONFIG_MTD_CFI_I2=y | ||
| 436 | # CONFIG_MTD_CFI_I4 is not set | ||
| 437 | # CONFIG_MTD_CFI_I8 is not set | ||
| 438 | # CONFIG_MTD_OTP is not set | ||
| 439 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 440 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 441 | # CONFIG_MTD_CFI_STAA is not set | ||
| 442 | CONFIG_MTD_CFI_UTIL=y | ||
| 443 | # CONFIG_MTD_RAM is not set | ||
| 444 | # CONFIG_MTD_ROM is not set | ||
| 445 | # CONFIG_MTD_ABSENT is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Mapping drivers for chip access | ||
| 449 | # | ||
| 450 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 451 | CONFIG_MTD_PHYSMAP=y | ||
| 452 | CONFIG_MTD_PHYSMAP_START=0x8000000 | ||
| 453 | CONFIG_MTD_PHYSMAP_LEN=0 | ||
| 454 | CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | ||
| 455 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 456 | # CONFIG_MTD_IMPA7 is not set | ||
| 457 | # CONFIG_MTD_INTEL_VR_NOR is not set | ||
| 458 | # CONFIG_MTD_PLATRAM is not set | ||
| 459 | |||
| 460 | # | ||
| 461 | # Self-contained MTD device drivers | ||
| 462 | # | ||
| 463 | # CONFIG_MTD_PMC551 is not set | ||
| 464 | # CONFIG_MTD_SLRAM is not set | ||
| 465 | # CONFIG_MTD_PHRAM is not set | ||
| 466 | # CONFIG_MTD_MTDRAM is not set | ||
| 467 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # Disk-On-Chip Device Drivers | ||
| 471 | # | ||
| 472 | # CONFIG_MTD_DOC2000 is not set | ||
| 473 | # CONFIG_MTD_DOC2001 is not set | ||
| 474 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 475 | # CONFIG_MTD_NAND is not set | ||
| 476 | # CONFIG_MTD_ONENAND is not set | ||
| 477 | |||
| 478 | # | ||
| 479 | # UBI - Unsorted block images | ||
| 480 | # | ||
| 481 | # CONFIG_MTD_UBI is not set | ||
| 482 | # CONFIG_PARPORT is not set | ||
| 483 | CONFIG_BLK_DEV=y | ||
| 484 | # CONFIG_BLK_CPQ_DA is not set | ||
| 485 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
| 486 | # CONFIG_BLK_DEV_DAC960 is not set | ||
| 487 | # CONFIG_BLK_DEV_UMEM is not set | ||
| 488 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 489 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 490 | # CONFIG_BLK_DEV_NBD is not set | ||
| 491 | # CONFIG_BLK_DEV_SX8 is not set | ||
| 492 | CONFIG_BLK_DEV_RAM=y | ||
| 493 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 494 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 495 | # CONFIG_BLK_DEV_XIP is not set | ||
| 496 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 497 | # CONFIG_ATA_OVER_ETH is not set | ||
| 498 | CONFIG_MISC_DEVICES=y | ||
| 499 | # CONFIG_PHANTOM is not set | ||
| 500 | # CONFIG_EEPROM_93CX6 is not set | ||
| 501 | # CONFIG_SGI_IOC4 is not set | ||
| 502 | # CONFIG_TIFM_CORE is not set | ||
| 503 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 504 | # CONFIG_HP_ILO is not set | ||
| 505 | CONFIG_HAVE_IDE=y | ||
| 506 | # CONFIG_IDE is not set | ||
| 507 | |||
| 508 | # | ||
| 509 | # SCSI device support | ||
| 510 | # | ||
| 511 | # CONFIG_RAID_ATTRS is not set | ||
| 512 | # CONFIG_SCSI is not set | ||
| 513 | # CONFIG_SCSI_DMA is not set | ||
| 514 | # CONFIG_SCSI_NETLINK is not set | ||
| 515 | # CONFIG_ATA is not set | ||
| 516 | # CONFIG_MD is not set | ||
| 517 | # CONFIG_FUSION is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # IEEE 1394 (FireWire) support | ||
| 521 | # | ||
| 522 | |||
| 523 | # | ||
| 524 | # Enable only one of the two stacks, unless you know what you are doing | ||
| 525 | # | ||
| 526 | # CONFIG_FIREWIRE is not set | ||
| 527 | # CONFIG_IEEE1394 is not set | ||
| 528 | # CONFIG_I2O is not set | ||
| 529 | CONFIG_NETDEVICES=y | ||
| 530 | # CONFIG_DUMMY is not set | ||
| 531 | # CONFIG_BONDING is not set | ||
| 532 | # CONFIG_MACVLAN is not set | ||
| 533 | # CONFIG_EQUALIZER is not set | ||
| 534 | # CONFIG_TUN is not set | ||
| 535 | # CONFIG_VETH is not set | ||
| 536 | # CONFIG_ARCNET is not set | ||
| 537 | # CONFIG_PHYLIB is not set | ||
| 538 | CONFIG_NET_ETHERNET=y | ||
| 539 | CONFIG_MII=y | ||
| 540 | CONFIG_ARM_KS8695_ETHER=y | ||
| 541 | # CONFIG_AX88796 is not set | ||
| 542 | # CONFIG_HAPPYMEAL is not set | ||
| 543 | # CONFIG_SUNGEM is not set | ||
| 544 | # CONFIG_CASSINI is not set | ||
| 545 | # CONFIG_NET_VENDOR_3COM is not set | ||
| 546 | # CONFIG_SMC91X is not set | ||
| 547 | # CONFIG_DM9000 is not set | ||
| 548 | # CONFIG_NET_TULIP is not set | ||
| 549 | # CONFIG_HP100 is not set | ||
| 550 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 551 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 552 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 553 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 554 | # CONFIG_NET_PCI is not set | ||
| 555 | # CONFIG_B44 is not set | ||
| 556 | # CONFIG_NETDEV_1000 is not set | ||
| 557 | # CONFIG_NETDEV_10000 is not set | ||
| 558 | # CONFIG_TR is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Wireless LAN | ||
| 562 | # | ||
| 563 | # CONFIG_WLAN_PRE80211 is not set | ||
| 564 | CONFIG_WLAN_80211=y | ||
| 565 | # CONFIG_PCMCIA_RAYCS is not set | ||
| 566 | # CONFIG_IPW2100 is not set | ||
| 567 | # CONFIG_IPW2200 is not set | ||
| 568 | # CONFIG_LIBERTAS is not set | ||
| 569 | # CONFIG_HERMES is not set | ||
| 570 | # CONFIG_ATMEL is not set | ||
| 571 | # CONFIG_AIRO_CS is not set | ||
| 572 | # CONFIG_PCMCIA_WL3501 is not set | ||
| 573 | CONFIG_PRISM54=m | ||
| 574 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 575 | # CONFIG_HOSTAP is not set | ||
| 576 | # CONFIG_NET_PCMCIA is not set | ||
| 577 | # CONFIG_WAN is not set | ||
| 578 | # CONFIG_FDDI is not set | ||
| 579 | # CONFIG_HIPPI is not set | ||
| 580 | # CONFIG_PPP is not set | ||
| 581 | # CONFIG_SLIP is not set | ||
| 582 | # CONFIG_NETCONSOLE is not set | ||
| 583 | # CONFIG_NETPOLL is not set | ||
| 584 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 585 | # CONFIG_ISDN is not set | ||
| 586 | |||
| 587 | # | ||
| 588 | # Input device support | ||
| 589 | # | ||
| 590 | CONFIG_INPUT=y | ||
| 591 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 592 | # CONFIG_INPUT_POLLDEV is not set | ||
| 593 | |||
| 594 | # | ||
| 595 | # Userland interfaces | ||
| 596 | # | ||
| 597 | CONFIG_INPUT_MOUSEDEV=y | ||
| 598 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 599 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 600 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 601 | # CONFIG_INPUT_JOYDEV is not set | ||
| 602 | # CONFIG_INPUT_EVDEV is not set | ||
| 603 | # CONFIG_INPUT_EVBUG is not set | ||
| 604 | |||
| 605 | # | ||
| 606 | # Input Device Drivers | ||
| 607 | # | ||
| 608 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 609 | # CONFIG_INPUT_MOUSE is not set | ||
| 610 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 611 | # CONFIG_INPUT_TABLET is not set | ||
| 612 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 613 | # CONFIG_INPUT_MISC is not set | ||
| 614 | |||
| 615 | # | ||
| 616 | # Hardware I/O ports | ||
| 617 | # | ||
| 618 | # CONFIG_SERIO is not set | ||
| 619 | # CONFIG_GAMEPORT is not set | ||
| 620 | |||
| 621 | # | ||
| 622 | # Character devices | ||
| 623 | # | ||
| 624 | CONFIG_VT=y | ||
| 625 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 626 | CONFIG_VT_CONSOLE=y | ||
| 627 | CONFIG_HW_CONSOLE=y | ||
| 628 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 629 | CONFIG_DEVKMEM=y | ||
| 630 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 631 | # CONFIG_NOZOMI is not set | ||
| 632 | |||
| 633 | # | ||
| 634 | # Serial drivers | ||
| 635 | # | ||
| 636 | # CONFIG_SERIAL_8250 is not set | ||
| 637 | |||
| 638 | # | ||
| 639 | # Non-8250 serial port support | ||
| 640 | # | ||
| 641 | CONFIG_SERIAL_KS8695=y | ||
| 642 | CONFIG_SERIAL_KS8695_CONSOLE=y | ||
| 643 | CONFIG_SERIAL_CORE=y | ||
| 644 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 645 | # CONFIG_SERIAL_JSM is not set | ||
| 646 | CONFIG_UNIX98_PTYS=y | ||
| 647 | CONFIG_LEGACY_PTYS=y | ||
| 648 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 649 | # CONFIG_IPMI_HANDLER is not set | ||
| 650 | CONFIG_HW_RANDOM=m | ||
| 651 | # CONFIG_NVRAM is not set | ||
| 652 | # CONFIG_R3964 is not set | ||
| 653 | # CONFIG_APPLICOM is not set | ||
| 654 | |||
| 655 | # | ||
| 656 | # PCMCIA character devices | ||
| 657 | # | ||
| 658 | # CONFIG_SYNCLINK_CS is not set | ||
| 659 | # CONFIG_CARDMAN_4000 is not set | ||
| 660 | # CONFIG_CARDMAN_4040 is not set | ||
| 661 | # CONFIG_IPWIRELESS is not set | ||
| 662 | # CONFIG_RAW_DRIVER is not set | ||
| 663 | # CONFIG_TCG_TPM is not set | ||
| 664 | CONFIG_DEVPORT=y | ||
| 665 | CONFIG_ACS5KCAN=y | ||
| 666 | CONFIG_I2C=y | ||
| 667 | CONFIG_I2C_BOARDINFO=y | ||
| 668 | CONFIG_I2C_CHARDEV=y | ||
| 669 | CONFIG_I2C_HELPER_AUTO=y | ||
| 670 | CONFIG_I2C_ALGOBIT=y | ||
| 671 | |||
| 672 | # | ||
| 673 | # I2C Hardware Bus support | ||
| 674 | # | ||
| 675 | |||
| 676 | # | ||
| 677 | # PC SMBus host controller drivers | ||
| 678 | # | ||
| 679 | # CONFIG_I2C_ALI1535 is not set | ||
| 680 | # CONFIG_I2C_ALI1563 is not set | ||
| 681 | # CONFIG_I2C_ALI15X3 is not set | ||
| 682 | # CONFIG_I2C_AMD756 is not set | ||
| 683 | # CONFIG_I2C_AMD8111 is not set | ||
| 684 | # CONFIG_I2C_I801 is not set | ||
| 685 | # CONFIG_I2C_ISCH is not set | ||
| 686 | # CONFIG_I2C_PIIX4 is not set | ||
| 687 | # CONFIG_I2C_NFORCE2 is not set | ||
| 688 | # CONFIG_I2C_SIS5595 is not set | ||
| 689 | # CONFIG_I2C_SIS630 is not set | ||
| 690 | # CONFIG_I2C_SIS96X is not set | ||
| 691 | # CONFIG_I2C_VIA is not set | ||
| 692 | # CONFIG_I2C_VIAPRO is not set | ||
| 693 | |||
| 694 | # | ||
| 695 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 696 | # | ||
| 697 | CONFIG_I2C_GPIO=y | ||
| 698 | # CONFIG_I2C_OCORES is not set | ||
| 699 | # CONFIG_I2C_SIMTEC is not set | ||
| 700 | |||
| 701 | # | ||
| 702 | # External I2C/SMBus adapter drivers | ||
| 703 | # | ||
| 704 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 705 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 706 | |||
| 707 | # | ||
| 708 | # Graphics adapter I2C/DDC channel drivers | ||
| 709 | # | ||
| 710 | # CONFIG_I2C_VOODOO3 is not set | ||
| 711 | |||
| 712 | # | ||
| 713 | # Other I2C/SMBus bus drivers | ||
| 714 | # | ||
| 715 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 716 | # CONFIG_I2C_STUB is not set | ||
| 717 | |||
| 718 | # | ||
| 719 | # Miscellaneous I2C Chip support | ||
| 720 | # | ||
| 721 | # CONFIG_DS1682 is not set | ||
| 722 | # CONFIG_AT24 is not set | ||
| 723 | # CONFIG_SENSORS_EEPROM is not set | ||
| 724 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 725 | # CONFIG_PCF8575 is not set | ||
| 726 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 727 | # CONFIG_TPS65010 is not set | ||
| 728 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 729 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 730 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 731 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 732 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 733 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 734 | # CONFIG_SPI is not set | ||
| 735 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 736 | CONFIG_GPIOLIB=y | ||
| 737 | # CONFIG_DEBUG_GPIO is not set | ||
| 738 | CONFIG_GPIO_SYSFS=y | ||
| 739 | |||
| 740 | # | ||
| 741 | # I2C GPIO expanders: | ||
| 742 | # | ||
| 743 | # CONFIG_GPIO_MAX732X is not set | ||
| 744 | CONFIG_GPIO_PCA953X=y | ||
| 745 | # CONFIG_GPIO_PCF857X is not set | ||
| 746 | |||
| 747 | # | ||
| 748 | # PCI GPIO expanders: | ||
| 749 | # | ||
| 750 | # CONFIG_GPIO_BT8XX is not set | ||
| 751 | |||
| 752 | # | ||
| 753 | # SPI GPIO expanders: | ||
| 754 | # | ||
| 755 | # CONFIG_W1 is not set | ||
| 756 | # CONFIG_POWER_SUPPLY is not set | ||
| 757 | CONFIG_HWMON=y | ||
| 758 | # CONFIG_HWMON_VID is not set | ||
| 759 | # CONFIG_SENSORS_AD7414 is not set | ||
| 760 | # CONFIG_SENSORS_AD7418 is not set | ||
| 761 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 762 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 763 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 764 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 765 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 766 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 767 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 768 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 769 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 770 | # CONFIG_SENSORS_DS1621 is not set | ||
| 771 | # CONFIG_SENSORS_I5K_AMB is not set | ||
| 772 | # CONFIG_SENSORS_F71805F is not set | ||
| 773 | # CONFIG_SENSORS_F71882FG is not set | ||
| 774 | # CONFIG_SENSORS_F75375S is not set | ||
| 775 | # CONFIG_SENSORS_GL518SM is not set | ||
| 776 | # CONFIG_SENSORS_GL520SM is not set | ||
| 777 | # CONFIG_SENSORS_IT87 is not set | ||
| 778 | # CONFIG_SENSORS_LM63 is not set | ||
| 779 | # CONFIG_SENSORS_LM75 is not set | ||
| 780 | # CONFIG_SENSORS_LM77 is not set | ||
| 781 | # CONFIG_SENSORS_LM78 is not set | ||
| 782 | # CONFIG_SENSORS_LM80 is not set | ||
| 783 | # CONFIG_SENSORS_LM83 is not set | ||
| 784 | # CONFIG_SENSORS_LM85 is not set | ||
| 785 | # CONFIG_SENSORS_LM87 is not set | ||
| 786 | # CONFIG_SENSORS_LM90 is not set | ||
| 787 | # CONFIG_SENSORS_LM92 is not set | ||
| 788 | # CONFIG_SENSORS_LM93 is not set | ||
| 789 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 790 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 791 | # CONFIG_SENSORS_PC87360 is not set | ||
| 792 | # CONFIG_SENSORS_PC87427 is not set | ||
| 793 | # CONFIG_SENSORS_SIS5595 is not set | ||
| 794 | # CONFIG_SENSORS_DME1737 is not set | ||
| 795 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 796 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 797 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 798 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 799 | # CONFIG_SENSORS_THMC50 is not set | ||
| 800 | # CONFIG_SENSORS_VIA686A is not set | ||
| 801 | # CONFIG_SENSORS_VT1211 is not set | ||
| 802 | # CONFIG_SENSORS_VT8231 is not set | ||
| 803 | # CONFIG_SENSORS_W83781D is not set | ||
| 804 | # CONFIG_SENSORS_W83791D is not set | ||
| 805 | # CONFIG_SENSORS_W83792D is not set | ||
| 806 | # CONFIG_SENSORS_W83793 is not set | ||
| 807 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 808 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 809 | # CONFIG_SENSORS_W83627HF is not set | ||
| 810 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 811 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 812 | CONFIG_WATCHDOG=y | ||
| 813 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 814 | |||
| 815 | # | ||
| 816 | # Watchdog Device Drivers | ||
| 817 | # | ||
| 818 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 819 | CONFIG_KS8695_WATCHDOG=y | ||
| 820 | # CONFIG_ALIM7101_WDT is not set | ||
| 821 | |||
| 822 | # | ||
| 823 | # PCI-based Watchdog Cards | ||
| 824 | # | ||
| 825 | # CONFIG_PCIPCWATCHDOG is not set | ||
| 826 | # CONFIG_WDTPCI is not set | ||
| 827 | |||
| 828 | # | ||
| 829 | # Sonics Silicon Backplane | ||
| 830 | # | ||
| 831 | CONFIG_SSB_POSSIBLE=y | ||
| 832 | # CONFIG_SSB is not set | ||
| 833 | |||
| 834 | # | ||
| 835 | # Multifunction device drivers | ||
| 836 | # | ||
| 837 | # CONFIG_MFD_CORE is not set | ||
| 838 | # CONFIG_MFD_SM501 is not set | ||
| 839 | # CONFIG_MFD_ASIC3 is not set | ||
| 840 | # CONFIG_HTC_EGPIO is not set | ||
| 841 | # CONFIG_HTC_PASIC3 is not set | ||
| 842 | # CONFIG_MFD_TMIO is not set | ||
| 843 | # CONFIG_MFD_T7L66XB is not set | ||
| 844 | # CONFIG_MFD_TC6387XB is not set | ||
| 845 | # CONFIG_MFD_TC6393XB is not set | ||
| 846 | |||
| 847 | # | ||
| 848 | # Multimedia devices | ||
| 849 | # | ||
| 850 | |||
| 851 | # | ||
| 852 | # Multimedia core support | ||
| 853 | # | ||
| 854 | # CONFIG_VIDEO_DEV is not set | ||
| 855 | # CONFIG_DVB_CORE is not set | ||
| 856 | # CONFIG_VIDEO_MEDIA is not set | ||
| 857 | |||
| 858 | # | ||
| 859 | # Multimedia drivers | ||
| 860 | # | ||
| 861 | # CONFIG_DAB is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # Graphics support | ||
| 865 | # | ||
| 866 | # CONFIG_DRM is not set | ||
| 867 | # CONFIG_VGASTATE is not set | ||
| 868 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 869 | # CONFIG_FB is not set | ||
| 870 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 871 | |||
| 872 | # | ||
| 873 | # Display device support | ||
| 874 | # | ||
| 875 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 876 | |||
| 877 | # | ||
| 878 | # Console display driver support | ||
| 879 | # | ||
| 880 | # CONFIG_VGA_CONSOLE is not set | ||
| 881 | CONFIG_DUMMY_CONSOLE=y | ||
| 882 | # CONFIG_SOUND is not set | ||
| 883 | CONFIG_HID_SUPPORT=y | ||
| 884 | CONFIG_HID=y | ||
| 885 | CONFIG_HID_DEBUG=y | ||
| 886 | # CONFIG_HIDRAW is not set | ||
| 887 | CONFIG_USB_SUPPORT=y | ||
| 888 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 889 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 890 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 891 | # CONFIG_USB is not set | ||
| 892 | |||
| 893 | # | ||
| 894 | # Enable Host or Gadget support to see Inventra options | ||
| 895 | # | ||
| 896 | |||
| 897 | # | ||
| 898 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 899 | # | ||
| 900 | # CONFIG_USB_GADGET is not set | ||
| 901 | # CONFIG_MMC is not set | ||
| 902 | # CONFIG_NEW_LEDS is not set | ||
| 903 | CONFIG_RTC_LIB=y | ||
| 904 | CONFIG_RTC_CLASS=y | ||
| 905 | CONFIG_RTC_HCTOSYS=y | ||
| 906 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 907 | # CONFIG_RTC_DEBUG is not set | ||
| 908 | |||
| 909 | # | ||
| 910 | # RTC interfaces | ||
| 911 | # | ||
| 912 | CONFIG_RTC_INTF_SYSFS=y | ||
| 913 | CONFIG_RTC_INTF_PROC=y | ||
| 914 | CONFIG_RTC_INTF_DEV=y | ||
| 915 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 916 | # CONFIG_RTC_DRV_TEST is not set | ||
| 917 | |||
| 918 | # | ||
| 919 | # I2C RTC drivers | ||
| 920 | # | ||
| 921 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 922 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 923 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 924 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 925 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 926 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 927 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 928 | CONFIG_RTC_DRV_PCF8563=y | ||
| 929 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 930 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 931 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 932 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 933 | |||
| 934 | # | ||
| 935 | # SPI RTC drivers | ||
| 936 | # | ||
| 937 | |||
| 938 | # | ||
| 939 | # Platform RTC drivers | ||
| 940 | # | ||
| 941 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 942 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 943 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 944 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 945 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 946 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 947 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 948 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 949 | |||
| 950 | # | ||
| 951 | # on-CPU RTC drivers | ||
| 952 | # | ||
| 953 | # CONFIG_DMADEVICES is not set | ||
| 954 | |||
| 955 | # | ||
| 956 | # Voltage and Current regulators | ||
| 957 | # | ||
| 958 | # CONFIG_REGULATOR is not set | ||
| 959 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 960 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 961 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 962 | # CONFIG_UIO is not set | ||
| 963 | |||
| 964 | # | ||
| 965 | # File systems | ||
| 966 | # | ||
| 967 | CONFIG_EXT2_FS=y | ||
| 968 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 969 | # CONFIG_EXT2_FS_XIP is not set | ||
| 970 | # CONFIG_EXT3_FS is not set | ||
| 971 | # CONFIG_EXT4DEV_FS is not set | ||
| 972 | # CONFIG_REISERFS_FS is not set | ||
| 973 | # CONFIG_JFS_FS is not set | ||
| 974 | # CONFIG_FS_POSIX_ACL is not set | ||
| 975 | # CONFIG_XFS_FS is not set | ||
| 976 | # CONFIG_OCFS2_FS is not set | ||
| 977 | CONFIG_DNOTIFY=y | ||
| 978 | CONFIG_INOTIFY=y | ||
| 979 | CONFIG_INOTIFY_USER=y | ||
| 980 | # CONFIG_QUOTA is not set | ||
| 981 | # CONFIG_AUTOFS_FS is not set | ||
| 982 | # CONFIG_AUTOFS4_FS is not set | ||
| 983 | # CONFIG_FUSE_FS is not set | ||
| 984 | |||
| 985 | # | ||
| 986 | # CD-ROM/DVD Filesystems | ||
| 987 | # | ||
| 988 | # CONFIG_ISO9660_FS is not set | ||
| 989 | # CONFIG_UDF_FS is not set | ||
| 990 | |||
| 991 | # | ||
| 992 | # DOS/FAT/NT Filesystems | ||
| 993 | # | ||
| 994 | # CONFIG_MSDOS_FS is not set | ||
| 995 | # CONFIG_VFAT_FS is not set | ||
| 996 | # CONFIG_NTFS_FS is not set | ||
| 997 | |||
| 998 | # | ||
| 999 | # Pseudo filesystems | ||
| 1000 | # | ||
| 1001 | CONFIG_PROC_FS=y | ||
| 1002 | CONFIG_PROC_SYSCTL=y | ||
| 1003 | CONFIG_SYSFS=y | ||
| 1004 | CONFIG_TMPFS=y | ||
| 1005 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1006 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1007 | # CONFIG_CONFIGFS_FS is not set | ||
| 1008 | |||
| 1009 | # | ||
| 1010 | # Miscellaneous filesystems | ||
| 1011 | # | ||
| 1012 | # CONFIG_ADFS_FS is not set | ||
| 1013 | # CONFIG_AFFS_FS is not set | ||
| 1014 | # CONFIG_HFS_FS is not set | ||
| 1015 | # CONFIG_HFSPLUS_FS is not set | ||
| 1016 | # CONFIG_BEFS_FS is not set | ||
| 1017 | # CONFIG_BFS_FS is not set | ||
| 1018 | # CONFIG_EFS_FS is not set | ||
| 1019 | CONFIG_JFFS2_FS=y | ||
| 1020 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1021 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1022 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1023 | CONFIG_JFFS2_SUMMARY=y | ||
| 1024 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1025 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 1026 | CONFIG_JFFS2_ZLIB=y | ||
| 1027 | # CONFIG_JFFS2_LZO is not set | ||
| 1028 | CONFIG_JFFS2_RTIME=y | ||
| 1029 | CONFIG_JFFS2_RUBIN=y | ||
| 1030 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 1031 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 1032 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 1033 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 1034 | CONFIG_CRAMFS=y | ||
| 1035 | # CONFIG_VXFS_FS is not set | ||
| 1036 | # CONFIG_MINIX_FS is not set | ||
| 1037 | # CONFIG_OMFS_FS is not set | ||
| 1038 | # CONFIG_HPFS_FS is not set | ||
| 1039 | # CONFIG_QNX4FS_FS is not set | ||
| 1040 | # CONFIG_ROMFS_FS is not set | ||
| 1041 | # CONFIG_SYSV_FS is not set | ||
| 1042 | # CONFIG_UFS_FS is not set | ||
| 1043 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1044 | CONFIG_NFS_FS=y | ||
| 1045 | CONFIG_NFS_V3=y | ||
| 1046 | # CONFIG_NFS_V3_ACL is not set | ||
| 1047 | # CONFIG_NFS_V4 is not set | ||
| 1048 | CONFIG_ROOT_NFS=y | ||
| 1049 | # CONFIG_NFSD is not set | ||
| 1050 | CONFIG_LOCKD=y | ||
| 1051 | CONFIG_LOCKD_V4=y | ||
| 1052 | CONFIG_NFS_COMMON=y | ||
| 1053 | CONFIG_SUNRPC=y | ||
| 1054 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1055 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1056 | # CONFIG_SMB_FS is not set | ||
| 1057 | # CONFIG_CIFS is not set | ||
| 1058 | # CONFIG_NCP_FS is not set | ||
| 1059 | # CONFIG_CODA_FS is not set | ||
| 1060 | # CONFIG_AFS_FS is not set | ||
| 1061 | |||
| 1062 | # | ||
| 1063 | # Partition Types | ||
| 1064 | # | ||
| 1065 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 1066 | CONFIG_MSDOS_PARTITION=y | ||
| 1067 | # CONFIG_NLS is not set | ||
| 1068 | # CONFIG_DLM is not set | ||
| 1069 | |||
| 1070 | # | ||
| 1071 | # Kernel hacking | ||
| 1072 | # | ||
| 1073 | # CONFIG_PRINTK_TIME is not set | ||
| 1074 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1075 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1076 | CONFIG_FRAME_WARN=1024 | ||
| 1077 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1078 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1079 | # CONFIG_DEBUG_FS is not set | ||
| 1080 | # CONFIG_HEADERS_CHECK is not set | ||
| 1081 | CONFIG_DEBUG_KERNEL=y | ||
| 1082 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1083 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1084 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1085 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1086 | CONFIG_SCHED_DEBUG=y | ||
| 1087 | # CONFIG_SCHEDSTATS is not set | ||
| 1088 | # CONFIG_TIMER_STATS is not set | ||
| 1089 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1090 | # CONFIG_DEBUG_SLAB is not set | ||
| 1091 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1092 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1093 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1094 | CONFIG_DEBUG_MUTEXES=y | ||
| 1095 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1096 | # CONFIG_PROVE_LOCKING is not set | ||
| 1097 | # CONFIG_LOCK_STAT is not set | ||
| 1098 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1099 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1100 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1101 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1102 | # CONFIG_DEBUG_INFO is not set | ||
| 1103 | # CONFIG_DEBUG_VM is not set | ||
| 1104 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1105 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1106 | # CONFIG_DEBUG_LIST is not set | ||
| 1107 | # CONFIG_DEBUG_SG is not set | ||
| 1108 | CONFIG_FRAME_POINTER=y | ||
| 1109 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1110 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1111 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1112 | # CONFIG_FAULT_INJECTION is not set | ||
| 1113 | # CONFIG_LATENCYTOP is not set | ||
| 1114 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1115 | CONFIG_HAVE_FTRACE=y | ||
| 1116 | CONFIG_HAVE_DYNAMIC_FTRACE=y | ||
| 1117 | # CONFIG_FTRACE is not set | ||
| 1118 | # CONFIG_SCHED_TRACER is not set | ||
| 1119 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1120 | # CONFIG_SAMPLES is not set | ||
| 1121 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1122 | # CONFIG_KGDB is not set | ||
| 1123 | CONFIG_DEBUG_USER=y | ||
| 1124 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1125 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1126 | CONFIG_DEBUG_LL=y | ||
| 1127 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1128 | |||
| 1129 | # | ||
| 1130 | # Security options | ||
| 1131 | # | ||
| 1132 | # CONFIG_KEYS is not set | ||
| 1133 | # CONFIG_SECURITY is not set | ||
| 1134 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1135 | CONFIG_CRYPTO=y | ||
| 1136 | |||
| 1137 | # | ||
| 1138 | # Crypto core or helper | ||
| 1139 | # | ||
| 1140 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1141 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1142 | # CONFIG_CRYPTO_NULL is not set | ||
| 1143 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1144 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1145 | # CONFIG_CRYPTO_TEST is not set | ||
| 1146 | |||
| 1147 | # | ||
| 1148 | # Authenticated Encryption with Associated Data | ||
| 1149 | # | ||
| 1150 | # CONFIG_CRYPTO_CCM is not set | ||
| 1151 | # CONFIG_CRYPTO_GCM is not set | ||
| 1152 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1153 | |||
| 1154 | # | ||
| 1155 | # Block modes | ||
| 1156 | # | ||
| 1157 | # CONFIG_CRYPTO_CBC is not set | ||
| 1158 | # CONFIG_CRYPTO_CTR is not set | ||
| 1159 | # CONFIG_CRYPTO_CTS is not set | ||
| 1160 | # CONFIG_CRYPTO_ECB is not set | ||
| 1161 | # CONFIG_CRYPTO_LRW is not set | ||
| 1162 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1163 | # CONFIG_CRYPTO_XTS is not set | ||
| 1164 | |||
| 1165 | # | ||
| 1166 | # Hash modes | ||
| 1167 | # | ||
| 1168 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1169 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1170 | |||
| 1171 | # | ||
| 1172 | # Digest | ||
| 1173 | # | ||
| 1174 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1175 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1176 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1177 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1178 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1179 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1180 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1181 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1182 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1183 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1184 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1185 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1186 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1187 | |||
| 1188 | # | ||
| 1189 | # Ciphers | ||
| 1190 | # | ||
| 1191 | # CONFIG_CRYPTO_AES is not set | ||
| 1192 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1193 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1194 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1195 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1196 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1197 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1198 | # CONFIG_CRYPTO_DES is not set | ||
| 1199 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1200 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1201 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1202 | # CONFIG_CRYPTO_SEED is not set | ||
| 1203 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1204 | # CONFIG_CRYPTO_TEA is not set | ||
| 1205 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1206 | |||
| 1207 | # | ||
| 1208 | # Compression | ||
| 1209 | # | ||
| 1210 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1211 | # CONFIG_CRYPTO_LZO is not set | ||
| 1212 | CONFIG_CRYPTO_HW=y | ||
| 1213 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | ||
| 1214 | |||
| 1215 | # | ||
| 1216 | # Library routines | ||
| 1217 | # | ||
| 1218 | CONFIG_BITREVERSE=y | ||
| 1219 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | ||
| 1220 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
| 1221 | # CONFIG_CRC_CCITT is not set | ||
| 1222 | # CONFIG_CRC16 is not set | ||
| 1223 | # CONFIG_CRC_T10DIF is not set | ||
| 1224 | # CONFIG_CRC_ITU_T is not set | ||
| 1225 | CONFIG_CRC32=y | ||
| 1226 | # CONFIG_CRC7 is not set | ||
| 1227 | # CONFIG_LIBCRC32C is not set | ||
| 1228 | CONFIG_ZLIB_INFLATE=y | ||
| 1229 | CONFIG_ZLIB_DEFLATE=y | ||
| 1230 | CONFIG_PLIST=y | ||
| 1231 | CONFIG_HAS_IOMEM=y | ||
| 1232 | CONFIG_HAS_IOPORT=y | ||
| 1233 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig new file mode 100644 index 000000000000..8e3d084afd78 --- /dev/null +++ b/arch/arm/configs/acs5k_tiny_defconfig | |||
| @@ -0,0 +1,941 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.27-simtec-micrel1 | ||
| 4 | # Tue Jan 6 13:23:07 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 26 | CONFIG_ZONE_DMA=y | ||
| 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 28 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 29 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 30 | |||
| 31 | # | ||
| 32 | # General setup | ||
| 33 | # | ||
| 34 | CONFIG_EXPERIMENTAL=y | ||
| 35 | CONFIG_BROKEN_ON_SMP=y | ||
| 36 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 37 | CONFIG_LOCALVERSION="" | ||
| 38 | CONFIG_LOCALVERSION_AUTO=y | ||
| 39 | # CONFIG_SWAP is not set | ||
| 40 | CONFIG_SYSVIPC=y | ||
| 41 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 42 | CONFIG_POSIX_MQUEUE=y | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | # CONFIG_IKCONFIG is not set | ||
| 47 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 48 | # CONFIG_CGROUPS is not set | ||
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | CONFIG_SYSFS_DEPRECATED=y | ||
| 51 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 52 | # CONFIG_RELAY is not set | ||
| 53 | CONFIG_NAMESPACES=y | ||
| 54 | # CONFIG_UTS_NS is not set | ||
| 55 | # CONFIG_IPC_NS is not set | ||
| 56 | # CONFIG_USER_NS is not set | ||
| 57 | # CONFIG_PID_NS is not set | ||
| 58 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 59 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 60 | CONFIG_SYSCTL=y | ||
| 61 | # CONFIG_EMBEDDED is not set | ||
| 62 | CONFIG_UID16=y | ||
| 63 | CONFIG_SYSCTL_SYSCALL=y | ||
| 64 | CONFIG_KALLSYMS=y | ||
| 65 | # CONFIG_KALLSYMS_ALL is not set | ||
| 66 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 67 | CONFIG_HOTPLUG=y | ||
| 68 | CONFIG_PRINTK=y | ||
| 69 | CONFIG_BUG=y | ||
| 70 | CONFIG_ELF_CORE=y | ||
| 71 | CONFIG_COMPAT_BRK=y | ||
| 72 | CONFIG_BASE_FULL=y | ||
| 73 | CONFIG_FUTEX=y | ||
| 74 | CONFIG_ANON_INODES=y | ||
| 75 | CONFIG_EPOLL=y | ||
| 76 | CONFIG_SIGNALFD=y | ||
| 77 | CONFIG_TIMERFD=y | ||
| 78 | CONFIG_EVENTFD=y | ||
| 79 | CONFIG_SHMEM=y | ||
| 80 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 81 | CONFIG_SLAB=y | ||
| 82 | # CONFIG_SLUB is not set | ||
| 83 | # CONFIG_SLOB is not set | ||
| 84 | # CONFIG_PROFILING is not set | ||
| 85 | # CONFIG_MARKERS is not set | ||
| 86 | CONFIG_HAVE_OPROFILE=y | ||
| 87 | # CONFIG_KPROBES is not set | ||
| 88 | # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set | ||
| 89 | # CONFIG_HAVE_IOREMAP_PROT is not set | ||
| 90 | CONFIG_HAVE_KPROBES=y | ||
| 91 | CONFIG_HAVE_KRETPROBES=y | ||
| 92 | # CONFIG_HAVE_ARCH_TRACEHOOK is not set | ||
| 93 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 94 | # CONFIG_USE_GENERIC_SMP_HELPERS is not set | ||
| 95 | # CONFIG_HAVE_CLK is not set | ||
| 96 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 97 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 98 | CONFIG_SLABINFO=y | ||
| 99 | CONFIG_RT_MUTEXES=y | ||
| 100 | # CONFIG_TINY_SHMEM is not set | ||
| 101 | CONFIG_BASE_SMALL=0 | ||
| 102 | CONFIG_MODULES=y | ||
| 103 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 104 | CONFIG_MODULE_UNLOAD=y | ||
| 105 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 106 | # CONFIG_MODVERSIONS is not set | ||
| 107 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 108 | CONFIG_KMOD=y | ||
| 109 | CONFIG_BLOCK=y | ||
| 110 | # CONFIG_LBD is not set | ||
| 111 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 112 | # CONFIG_LSF is not set | ||
| 113 | # CONFIG_BLK_DEV_BSG is not set | ||
| 114 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 115 | |||
| 116 | # | ||
| 117 | # IO Schedulers | ||
| 118 | # | ||
| 119 | CONFIG_IOSCHED_NOOP=y | ||
| 120 | CONFIG_IOSCHED_AS=y | ||
| 121 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 122 | # CONFIG_IOSCHED_CFQ is not set | ||
| 123 | CONFIG_DEFAULT_AS=y | ||
| 124 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 125 | # CONFIG_DEFAULT_CFQ is not set | ||
| 126 | # CONFIG_DEFAULT_NOOP is not set | ||
| 127 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 128 | CONFIG_CLASSIC_RCU=y | ||
| 129 | |||
| 130 | # | ||
| 131 | # System Type | ||
| 132 | # | ||
| 133 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 134 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 135 | # CONFIG_ARCH_REALVIEW is not set | ||
| 136 | # CONFIG_ARCH_VERSATILE is not set | ||
| 137 | # CONFIG_ARCH_AT91 is not set | ||
| 138 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | CONFIG_ARCH_KS8695=y | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | # CONFIG_ARCH_RPC is not set | ||
| 163 | # CONFIG_ARCH_SA1100 is not set | ||
| 164 | # CONFIG_ARCH_S3C2410 is not set | ||
| 165 | # CONFIG_ARCH_SHARK is not set | ||
| 166 | # CONFIG_ARCH_LH7A40X is not set | ||
| 167 | # CONFIG_ARCH_DAVINCI is not set | ||
| 168 | # CONFIG_ARCH_OMAP is not set | ||
| 169 | # CONFIG_ARCH_MSM7X00A is not set | ||
| 170 | |||
| 171 | # | ||
| 172 | # Boot options | ||
| 173 | # | ||
| 174 | |||
| 175 | # | ||
| 176 | # Power management | ||
| 177 | # | ||
| 178 | |||
| 179 | # | ||
| 180 | # Kendin/Micrel KS8695 Implementations | ||
| 181 | # | ||
| 182 | # CONFIG_MACH_KS8695 is not set | ||
| 183 | # CONFIG_MACH_DSM320 is not set | ||
| 184 | CONFIG_MACH_ACS5K=y | ||
| 185 | |||
| 186 | # | ||
| 187 | # Processor Type | ||
| 188 | # | ||
| 189 | CONFIG_CPU_32=y | ||
| 190 | CONFIG_CPU_ARM922T=y | ||
| 191 | CONFIG_CPU_32v4T=y | ||
| 192 | CONFIG_CPU_ABRT_EV4T=y | ||
| 193 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 194 | CONFIG_CPU_CACHE_V4WT=y | ||
| 195 | CONFIG_CPU_CACHE_VIVT=y | ||
| 196 | CONFIG_CPU_COPY_V4WB=y | ||
| 197 | CONFIG_CPU_TLB_V4WBI=y | ||
| 198 | CONFIG_CPU_CP15=y | ||
| 199 | CONFIG_CPU_CP15_MMU=y | ||
| 200 | |||
| 201 | # | ||
| 202 | # Processor Features | ||
| 203 | # | ||
| 204 | # CONFIG_ARM_THUMB is not set | ||
| 205 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 206 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 207 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 208 | # CONFIG_OUTER_CACHE is not set | ||
| 209 | |||
| 210 | # | ||
| 211 | # Bus support | ||
| 212 | # | ||
| 213 | # CONFIG_PCI is not set | ||
| 214 | # CONFIG_PCI_SYSCALL is not set | ||
| 215 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 216 | # CONFIG_PCCARD is not set | ||
| 217 | |||
| 218 | # | ||
| 219 | # Kernel Features | ||
| 220 | # | ||
| 221 | # CONFIG_TICK_ONESHOT is not set | ||
| 222 | # CONFIG_PREEMPT is not set | ||
| 223 | CONFIG_HZ=100 | ||
| 224 | CONFIG_AEABI=y | ||
| 225 | CONFIG_OABI_COMPAT=y | ||
| 226 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 227 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 228 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 229 | CONFIG_FLATMEM_MANUAL=y | ||
| 230 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 231 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 232 | CONFIG_FLATMEM=y | ||
| 233 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 234 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 235 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 236 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 237 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 238 | # CONFIG_RESOURCES_64BIT is not set | ||
| 239 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 240 | CONFIG_BOUNCE=y | ||
| 241 | CONFIG_VIRT_TO_BUS=y | ||
| 242 | # CONFIG_LEDS is not set | ||
| 243 | CONFIG_ALIGNMENT_TRAP=y | ||
| 244 | |||
| 245 | # | ||
| 246 | # Boot options | ||
| 247 | # | ||
| 248 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 249 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 250 | CONFIG_CMDLINE="console=ttyAM0,115200 init=/bin/sh" | ||
| 251 | # CONFIG_XIP_KERNEL is not set | ||
| 252 | # CONFIG_KEXEC is not set | ||
| 253 | |||
| 254 | # | ||
| 255 | # Floating point emulation | ||
| 256 | # | ||
| 257 | |||
| 258 | # | ||
| 259 | # At least one emulation must be selected | ||
| 260 | # | ||
| 261 | CONFIG_FPE_NWFPE=y | ||
| 262 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 263 | # CONFIG_FPE_FASTFPE is not set | ||
| 264 | |||
| 265 | # | ||
| 266 | # Userspace binary formats | ||
| 267 | # | ||
| 268 | CONFIG_BINFMT_ELF=y | ||
| 269 | # CONFIG_BINFMT_AOUT is not set | ||
| 270 | # CONFIG_BINFMT_MISC is not set | ||
| 271 | |||
| 272 | # | ||
| 273 | # Power management options | ||
| 274 | # | ||
| 275 | # CONFIG_PM is not set | ||
| 276 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 277 | CONFIG_NET=y | ||
| 278 | |||
| 279 | # | ||
| 280 | # Networking options | ||
| 281 | # | ||
| 282 | CONFIG_PACKET=y | ||
| 283 | # CONFIG_PACKET_MMAP is not set | ||
| 284 | CONFIG_UNIX=y | ||
| 285 | # CONFIG_NET_KEY is not set | ||
| 286 | CONFIG_INET=y | ||
| 287 | # CONFIG_IP_MULTICAST is not set | ||
| 288 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 289 | CONFIG_IP_FIB_HASH=y | ||
| 290 | # CONFIG_IP_PNP is not set | ||
| 291 | # CONFIG_NET_IPIP is not set | ||
| 292 | # CONFIG_NET_IPGRE is not set | ||
| 293 | # CONFIG_ARPD is not set | ||
| 294 | # CONFIG_SYN_COOKIES is not set | ||
| 295 | # CONFIG_INET_AH is not set | ||
| 296 | # CONFIG_INET_ESP is not set | ||
| 297 | # CONFIG_INET_IPCOMP is not set | ||
| 298 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 299 | # CONFIG_INET_TUNNEL is not set | ||
| 300 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 301 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 302 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 303 | # CONFIG_INET_LRO is not set | ||
| 304 | CONFIG_INET_DIAG=y | ||
| 305 | CONFIG_INET_TCP_DIAG=y | ||
| 306 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 307 | CONFIG_TCP_CONG_CUBIC=y | ||
| 308 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 309 | # CONFIG_TCP_MD5SIG is not set | ||
| 310 | # CONFIG_IPV6 is not set | ||
| 311 | # CONFIG_NETWORK_SECMARK is not set | ||
| 312 | # CONFIG_NETFILTER is not set | ||
| 313 | # CONFIG_IP_DCCP is not set | ||
| 314 | # CONFIG_IP_SCTP is not set | ||
| 315 | # CONFIG_TIPC is not set | ||
| 316 | # CONFIG_ATM is not set | ||
| 317 | # CONFIG_BRIDGE is not set | ||
| 318 | # CONFIG_VLAN_8021Q is not set | ||
| 319 | # CONFIG_DECNET is not set | ||
| 320 | # CONFIG_LLC2 is not set | ||
| 321 | # CONFIG_IPX is not set | ||
| 322 | # CONFIG_ATALK is not set | ||
| 323 | # CONFIG_X25 is not set | ||
| 324 | # CONFIG_LAPB is not set | ||
| 325 | # CONFIG_ECONET is not set | ||
| 326 | # CONFIG_WAN_ROUTER is not set | ||
| 327 | # CONFIG_NET_SCHED is not set | ||
| 328 | |||
| 329 | # | ||
| 330 | # Network testing | ||
| 331 | # | ||
| 332 | # CONFIG_NET_PKTGEN is not set | ||
| 333 | # CONFIG_HAMRADIO is not set | ||
| 334 | # CONFIG_CAN is not set | ||
| 335 | # CONFIG_IRDA is not set | ||
| 336 | # CONFIG_BT is not set | ||
| 337 | # CONFIG_AF_RXRPC is not set | ||
| 338 | |||
| 339 | # | ||
| 340 | # Wireless | ||
| 341 | # | ||
| 342 | # CONFIG_CFG80211 is not set | ||
| 343 | # CONFIG_WIRELESS_EXT is not set | ||
| 344 | # CONFIG_MAC80211 is not set | ||
| 345 | # CONFIG_IEEE80211 is not set | ||
| 346 | # CONFIG_RFKILL is not set | ||
| 347 | # CONFIG_NET_9P is not set | ||
| 348 | |||
| 349 | # | ||
| 350 | # Device Drivers | ||
| 351 | # | ||
| 352 | |||
| 353 | # | ||
| 354 | # Generic Driver Options | ||
| 355 | # | ||
| 356 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 357 | CONFIG_STANDALONE=y | ||
| 358 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 359 | CONFIG_FW_LOADER=y | ||
| 360 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 361 | CONFIG_EXTRA_FIRMWARE="" | ||
| 362 | # CONFIG_DEBUG_DRIVER is not set | ||
| 363 | # CONFIG_DEBUG_DEVRES is not set | ||
| 364 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 365 | # CONFIG_CONNECTOR is not set | ||
| 366 | CONFIG_MTD=y | ||
| 367 | # CONFIG_MTD_DEBUG is not set | ||
| 368 | CONFIG_MTD_CONCAT=y | ||
| 369 | CONFIG_MTD_PARTITIONS=y | ||
| 370 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 371 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 372 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 373 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 374 | |||
| 375 | # | ||
| 376 | # User Modules And Translation Layers | ||
| 377 | # | ||
| 378 | CONFIG_MTD_CHAR=y | ||
| 379 | CONFIG_MTD_BLKDEVS=y | ||
| 380 | CONFIG_MTD_BLOCK=y | ||
| 381 | # CONFIG_FTL is not set | ||
| 382 | # CONFIG_NFTL is not set | ||
| 383 | # CONFIG_INFTL is not set | ||
| 384 | # CONFIG_RFD_FTL is not set | ||
| 385 | # CONFIG_SSFDC is not set | ||
| 386 | # CONFIG_MTD_OOPS is not set | ||
| 387 | |||
| 388 | # | ||
| 389 | # RAM/ROM/Flash chip drivers | ||
| 390 | # | ||
| 391 | CONFIG_MTD_CFI=y | ||
| 392 | CONFIG_MTD_JEDECPROBE=y | ||
| 393 | CONFIG_MTD_GEN_PROBE=y | ||
| 394 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 395 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 396 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 397 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 398 | # CONFIG_MTD_CFI_GEOMETRY is not set | ||
| 399 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 400 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 401 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 402 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 403 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 404 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 405 | CONFIG_MTD_CFI_I1=y | ||
| 406 | CONFIG_MTD_CFI_I2=y | ||
| 407 | # CONFIG_MTD_CFI_I4 is not set | ||
| 408 | # CONFIG_MTD_CFI_I8 is not set | ||
| 409 | # CONFIG_MTD_OTP is not set | ||
| 410 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 411 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 412 | # CONFIG_MTD_CFI_STAA is not set | ||
| 413 | CONFIG_MTD_CFI_UTIL=y | ||
| 414 | # CONFIG_MTD_RAM is not set | ||
| 415 | # CONFIG_MTD_ROM is not set | ||
| 416 | # CONFIG_MTD_ABSENT is not set | ||
| 417 | |||
| 418 | # | ||
| 419 | # Mapping drivers for chip access | ||
| 420 | # | ||
| 421 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 422 | CONFIG_MTD_PHYSMAP=y | ||
| 423 | CONFIG_MTD_PHYSMAP_START=0x8000000 | ||
| 424 | CONFIG_MTD_PHYSMAP_LEN=0 | ||
| 425 | CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | ||
| 426 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 427 | # CONFIG_MTD_IMPA7 is not set | ||
| 428 | # CONFIG_MTD_PLATRAM is not set | ||
| 429 | |||
| 430 | # | ||
| 431 | # Self-contained MTD device drivers | ||
| 432 | # | ||
| 433 | # CONFIG_MTD_SLRAM is not set | ||
| 434 | # CONFIG_MTD_PHRAM is not set | ||
| 435 | # CONFIG_MTD_MTDRAM is not set | ||
| 436 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 437 | |||
| 438 | # | ||
| 439 | # Disk-On-Chip Device Drivers | ||
| 440 | # | ||
| 441 | # CONFIG_MTD_DOC2000 is not set | ||
| 442 | # CONFIG_MTD_DOC2001 is not set | ||
| 443 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 444 | # CONFIG_MTD_NAND is not set | ||
| 445 | # CONFIG_MTD_ONENAND is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # UBI - Unsorted block images | ||
| 449 | # | ||
| 450 | # CONFIG_MTD_UBI is not set | ||
| 451 | # CONFIG_PARPORT is not set | ||
| 452 | # CONFIG_BLK_DEV is not set | ||
| 453 | # CONFIG_MISC_DEVICES is not set | ||
| 454 | CONFIG_HAVE_IDE=y | ||
| 455 | # CONFIG_IDE is not set | ||
| 456 | |||
| 457 | # | ||
| 458 | # SCSI device support | ||
| 459 | # | ||
| 460 | # CONFIG_RAID_ATTRS is not set | ||
| 461 | # CONFIG_SCSI is not set | ||
| 462 | # CONFIG_SCSI_DMA is not set | ||
| 463 | # CONFIG_SCSI_NETLINK is not set | ||
| 464 | # CONFIG_ATA is not set | ||
| 465 | # CONFIG_MD is not set | ||
| 466 | CONFIG_NETDEVICES=y | ||
| 467 | # CONFIG_DUMMY is not set | ||
| 468 | # CONFIG_BONDING is not set | ||
| 469 | # CONFIG_MACVLAN is not set | ||
| 470 | # CONFIG_EQUALIZER is not set | ||
| 471 | # CONFIG_TUN is not set | ||
| 472 | # CONFIG_VETH is not set | ||
| 473 | # CONFIG_PHYLIB is not set | ||
| 474 | CONFIG_NET_ETHERNET=y | ||
| 475 | CONFIG_MII=y | ||
| 476 | CONFIG_ARM_KS8695_ETHER=y | ||
| 477 | # CONFIG_AX88796 is not set | ||
| 478 | # CONFIG_SMC91X is not set | ||
| 479 | # CONFIG_DM9000 is not set | ||
| 480 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 481 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 482 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 483 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 484 | # CONFIG_B44 is not set | ||
| 485 | # CONFIG_NETDEV_1000 is not set | ||
| 486 | # CONFIG_NETDEV_10000 is not set | ||
| 487 | |||
| 488 | # | ||
| 489 | # Wireless LAN | ||
| 490 | # | ||
| 491 | # CONFIG_WLAN_PRE80211 is not set | ||
| 492 | CONFIG_WLAN_80211=y | ||
| 493 | # CONFIG_LIBERTAS is not set | ||
| 494 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 495 | # CONFIG_HOSTAP is not set | ||
| 496 | # CONFIG_WAN is not set | ||
| 497 | # CONFIG_PPP is not set | ||
| 498 | # CONFIG_SLIP is not set | ||
| 499 | # CONFIG_NETCONSOLE is not set | ||
| 500 | # CONFIG_NETPOLL is not set | ||
| 501 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 502 | # CONFIG_ISDN is not set | ||
| 503 | |||
| 504 | # | ||
| 505 | # Input device support | ||
| 506 | # | ||
| 507 | CONFIG_INPUT=y | ||
| 508 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 509 | # CONFIG_INPUT_POLLDEV is not set | ||
| 510 | |||
| 511 | # | ||
| 512 | # Userland interfaces | ||
| 513 | # | ||
| 514 | CONFIG_INPUT_MOUSEDEV=y | ||
| 515 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 516 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 517 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 518 | # CONFIG_INPUT_JOYDEV is not set | ||
| 519 | # CONFIG_INPUT_EVDEV is not set | ||
| 520 | # CONFIG_INPUT_EVBUG is not set | ||
| 521 | |||
| 522 | # | ||
| 523 | # Input Device Drivers | ||
| 524 | # | ||
| 525 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 526 | # CONFIG_INPUT_MOUSE is not set | ||
| 527 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 528 | # CONFIG_INPUT_TABLET is not set | ||
| 529 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 530 | # CONFIG_INPUT_MISC is not set | ||
| 531 | |||
| 532 | # | ||
| 533 | # Hardware I/O ports | ||
| 534 | # | ||
| 535 | # CONFIG_SERIO is not set | ||
| 536 | # CONFIG_GAMEPORT is not set | ||
| 537 | |||
| 538 | # | ||
| 539 | # Character devices | ||
| 540 | # | ||
| 541 | CONFIG_VT=y | ||
| 542 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 543 | CONFIG_VT_CONSOLE=y | ||
| 544 | CONFIG_HW_CONSOLE=y | ||
| 545 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 546 | CONFIG_DEVKMEM=y | ||
| 547 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 548 | |||
| 549 | # | ||
| 550 | # Serial drivers | ||
| 551 | # | ||
| 552 | # CONFIG_SERIAL_8250 is not set | ||
| 553 | |||
| 554 | # | ||
| 555 | # Non-8250 serial port support | ||
| 556 | # | ||
| 557 | CONFIG_SERIAL_KS8695=y | ||
| 558 | CONFIG_SERIAL_KS8695_CONSOLE=y | ||
| 559 | CONFIG_SERIAL_CORE=y | ||
| 560 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 561 | CONFIG_UNIX98_PTYS=y | ||
| 562 | CONFIG_LEGACY_PTYS=y | ||
| 563 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 564 | # CONFIG_IPMI_HANDLER is not set | ||
| 565 | # CONFIG_HW_RANDOM is not set | ||
| 566 | # CONFIG_NVRAM is not set | ||
| 567 | # CONFIG_R3964 is not set | ||
| 568 | # CONFIG_RAW_DRIVER is not set | ||
| 569 | # CONFIG_TCG_TPM is not set | ||
| 570 | CONFIG_ACS5KCAN=y | ||
| 571 | CONFIG_I2C=y | ||
| 572 | CONFIG_I2C_BOARDINFO=y | ||
| 573 | CONFIG_I2C_CHARDEV=y | ||
| 574 | CONFIG_I2C_HELPER_AUTO=y | ||
| 575 | CONFIG_I2C_ALGOBIT=y | ||
| 576 | |||
| 577 | # | ||
| 578 | # I2C Hardware Bus support | ||
| 579 | # | ||
| 580 | |||
| 581 | # | ||
| 582 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 583 | # | ||
| 584 | CONFIG_I2C_GPIO=y | ||
| 585 | # CONFIG_I2C_OCORES is not set | ||
| 586 | # CONFIG_I2C_SIMTEC is not set | ||
| 587 | |||
| 588 | # | ||
| 589 | # External I2C/SMBus adapter drivers | ||
| 590 | # | ||
| 591 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 592 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 593 | |||
| 594 | # | ||
| 595 | # Other I2C/SMBus bus drivers | ||
| 596 | # | ||
| 597 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 598 | # CONFIG_I2C_STUB is not set | ||
| 599 | |||
| 600 | # | ||
| 601 | # Miscellaneous I2C Chip support | ||
| 602 | # | ||
| 603 | # CONFIG_DS1682 is not set | ||
| 604 | # CONFIG_AT24 is not set | ||
| 605 | # CONFIG_SENSORS_EEPROM is not set | ||
| 606 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 607 | # CONFIG_PCF8575 is not set | ||
| 608 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 609 | # CONFIG_TPS65010 is not set | ||
| 610 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 611 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 612 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 613 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 614 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 615 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 616 | # CONFIG_SPI is not set | ||
| 617 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 618 | CONFIG_GPIOLIB=y | ||
| 619 | # CONFIG_DEBUG_GPIO is not set | ||
| 620 | CONFIG_GPIO_SYSFS=y | ||
| 621 | |||
| 622 | # | ||
| 623 | # I2C GPIO expanders: | ||
| 624 | # | ||
| 625 | # CONFIG_GPIO_MAX732X is not set | ||
| 626 | CONFIG_GPIO_PCA953X=y | ||
| 627 | # CONFIG_GPIO_PCF857X is not set | ||
| 628 | |||
| 629 | # | ||
| 630 | # PCI GPIO expanders: | ||
| 631 | # | ||
| 632 | |||
| 633 | # | ||
| 634 | # SPI GPIO expanders: | ||
| 635 | # | ||
| 636 | # CONFIG_W1 is not set | ||
| 637 | # CONFIG_POWER_SUPPLY is not set | ||
| 638 | # CONFIG_HWMON is not set | ||
| 639 | CONFIG_WATCHDOG=y | ||
| 640 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 641 | |||
| 642 | # | ||
| 643 | # Watchdog Device Drivers | ||
| 644 | # | ||
| 645 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 646 | CONFIG_KS8695_WATCHDOG=y | ||
| 647 | |||
| 648 | # | ||
| 649 | # Sonics Silicon Backplane | ||
| 650 | # | ||
| 651 | CONFIG_SSB_POSSIBLE=y | ||
| 652 | # CONFIG_SSB is not set | ||
| 653 | |||
| 654 | # | ||
| 655 | # Multifunction device drivers | ||
| 656 | # | ||
| 657 | # CONFIG_MFD_CORE is not set | ||
| 658 | # CONFIG_MFD_SM501 is not set | ||
| 659 | # CONFIG_MFD_ASIC3 is not set | ||
| 660 | # CONFIG_HTC_EGPIO is not set | ||
| 661 | # CONFIG_HTC_PASIC3 is not set | ||
| 662 | # CONFIG_MFD_TMIO is not set | ||
| 663 | # CONFIG_MFD_T7L66XB is not set | ||
| 664 | # CONFIG_MFD_TC6387XB is not set | ||
| 665 | # CONFIG_MFD_TC6393XB is not set | ||
| 666 | |||
| 667 | # | ||
| 668 | # Multimedia devices | ||
| 669 | # | ||
| 670 | |||
| 671 | # | ||
| 672 | # Multimedia core support | ||
| 673 | # | ||
| 674 | # CONFIG_VIDEO_DEV is not set | ||
| 675 | # CONFIG_DVB_CORE is not set | ||
| 676 | # CONFIG_VIDEO_MEDIA is not set | ||
| 677 | |||
| 678 | # | ||
| 679 | # Multimedia drivers | ||
| 680 | # | ||
| 681 | # CONFIG_DAB is not set | ||
| 682 | |||
| 683 | # | ||
| 684 | # Graphics support | ||
| 685 | # | ||
| 686 | # CONFIG_VGASTATE is not set | ||
| 687 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 688 | # CONFIG_FB is not set | ||
| 689 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 690 | |||
| 691 | # | ||
| 692 | # Display device support | ||
| 693 | # | ||
| 694 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 695 | |||
| 696 | # | ||
| 697 | # Console display driver support | ||
| 698 | # | ||
| 699 | # CONFIG_VGA_CONSOLE is not set | ||
| 700 | CONFIG_DUMMY_CONSOLE=y | ||
| 701 | # CONFIG_SOUND is not set | ||
| 702 | # CONFIG_HID_SUPPORT is not set | ||
| 703 | # CONFIG_USB_SUPPORT is not set | ||
| 704 | # CONFIG_MMC is not set | ||
| 705 | # CONFIG_NEW_LEDS is not set | ||
| 706 | CONFIG_RTC_LIB=y | ||
| 707 | CONFIG_RTC_CLASS=y | ||
| 708 | CONFIG_RTC_HCTOSYS=y | ||
| 709 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 710 | # CONFIG_RTC_DEBUG is not set | ||
| 711 | |||
| 712 | # | ||
| 713 | # RTC interfaces | ||
| 714 | # | ||
| 715 | CONFIG_RTC_INTF_SYSFS=y | ||
| 716 | CONFIG_RTC_INTF_PROC=y | ||
| 717 | CONFIG_RTC_INTF_DEV=y | ||
| 718 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 719 | # CONFIG_RTC_DRV_TEST is not set | ||
| 720 | |||
| 721 | # | ||
| 722 | # I2C RTC drivers | ||
| 723 | # | ||
| 724 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 725 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 726 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 727 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 728 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 729 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 730 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 731 | CONFIG_RTC_DRV_PCF8563=y | ||
| 732 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 733 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 734 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 735 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 736 | |||
| 737 | # | ||
| 738 | # SPI RTC drivers | ||
| 739 | # | ||
| 740 | |||
| 741 | # | ||
| 742 | # Platform RTC drivers | ||
| 743 | # | ||
| 744 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 745 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 746 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 747 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 748 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 749 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 750 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 751 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 752 | |||
| 753 | # | ||
| 754 | # on-CPU RTC drivers | ||
| 755 | # | ||
| 756 | # CONFIG_DMADEVICES is not set | ||
| 757 | |||
| 758 | # | ||
| 759 | # Voltage and Current regulators | ||
| 760 | # | ||
| 761 | # CONFIG_REGULATOR is not set | ||
| 762 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 763 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 764 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 765 | # CONFIG_UIO is not set | ||
| 766 | |||
| 767 | # | ||
| 768 | # File systems | ||
| 769 | # | ||
| 770 | # CONFIG_EXT2_FS is not set | ||
| 771 | # CONFIG_EXT3_FS is not set | ||
| 772 | # CONFIG_EXT4DEV_FS is not set | ||
| 773 | # CONFIG_REISERFS_FS is not set | ||
| 774 | # CONFIG_JFS_FS is not set | ||
| 775 | # CONFIG_FS_POSIX_ACL is not set | ||
| 776 | # CONFIG_XFS_FS is not set | ||
| 777 | # CONFIG_OCFS2_FS is not set | ||
| 778 | CONFIG_DNOTIFY=y | ||
| 779 | CONFIG_INOTIFY=y | ||
| 780 | CONFIG_INOTIFY_USER=y | ||
| 781 | # CONFIG_QUOTA is not set | ||
| 782 | # CONFIG_AUTOFS_FS is not set | ||
| 783 | # CONFIG_AUTOFS4_FS is not set | ||
| 784 | # CONFIG_FUSE_FS is not set | ||
| 785 | |||
| 786 | # | ||
| 787 | # CD-ROM/DVD Filesystems | ||
| 788 | # | ||
| 789 | # CONFIG_ISO9660_FS is not set | ||
| 790 | # CONFIG_UDF_FS is not set | ||
| 791 | |||
| 792 | # | ||
| 793 | # DOS/FAT/NT Filesystems | ||
| 794 | # | ||
| 795 | # CONFIG_MSDOS_FS is not set | ||
| 796 | # CONFIG_VFAT_FS is not set | ||
| 797 | # CONFIG_NTFS_FS is not set | ||
| 798 | |||
| 799 | # | ||
| 800 | # Pseudo filesystems | ||
| 801 | # | ||
| 802 | CONFIG_PROC_FS=y | ||
| 803 | CONFIG_PROC_SYSCTL=y | ||
| 804 | CONFIG_SYSFS=y | ||
| 805 | CONFIG_TMPFS=y | ||
| 806 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 807 | # CONFIG_HUGETLB_PAGE is not set | ||
| 808 | # CONFIG_CONFIGFS_FS is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Miscellaneous filesystems | ||
| 812 | # | ||
| 813 | # CONFIG_ADFS_FS is not set | ||
| 814 | # CONFIG_AFFS_FS is not set | ||
| 815 | # CONFIG_HFS_FS is not set | ||
| 816 | # CONFIG_HFSPLUS_FS is not set | ||
| 817 | # CONFIG_BEFS_FS is not set | ||
| 818 | # CONFIG_BFS_FS is not set | ||
| 819 | # CONFIG_EFS_FS is not set | ||
| 820 | CONFIG_JFFS2_FS=y | ||
| 821 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 822 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 823 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 824 | CONFIG_JFFS2_SUMMARY=y | ||
| 825 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 826 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 827 | CONFIG_JFFS2_ZLIB=y | ||
| 828 | # CONFIG_JFFS2_LZO is not set | ||
| 829 | CONFIG_JFFS2_RTIME=y | ||
| 830 | CONFIG_JFFS2_RUBIN=y | ||
| 831 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 832 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 833 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 834 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 835 | # CONFIG_CRAMFS is not set | ||
| 836 | CONFIG_SQUASHFS=y | ||
| 837 | # CONFIG_SQUASHFS_EMBEDDED is not set | ||
| 838 | CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 | ||
| 839 | # CONFIG_VXFS_FS is not set | ||
| 840 | # CONFIG_MINIX_FS is not set | ||
| 841 | # CONFIG_OMFS_FS is not set | ||
| 842 | # CONFIG_HPFS_FS is not set | ||
| 843 | # CONFIG_QNX4FS_FS is not set | ||
| 844 | # CONFIG_ROMFS_FS is not set | ||
| 845 | # CONFIG_SYSV_FS is not set | ||
| 846 | # CONFIG_UFS_FS is not set | ||
| 847 | # CONFIG_NETWORK_FILESYSTEMS is not set | ||
| 848 | |||
| 849 | # | ||
| 850 | # Partition Types | ||
| 851 | # | ||
| 852 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 853 | CONFIG_MSDOS_PARTITION=y | ||
| 854 | # CONFIG_NLS is not set | ||
| 855 | # CONFIG_DLM is not set | ||
| 856 | |||
| 857 | # | ||
| 858 | # Kernel hacking | ||
| 859 | # | ||
| 860 | # CONFIG_PRINTK_TIME is not set | ||
| 861 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 862 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 863 | CONFIG_FRAME_WARN=1024 | ||
| 864 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 865 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 866 | # CONFIG_DEBUG_FS is not set | ||
| 867 | # CONFIG_HEADERS_CHECK is not set | ||
| 868 | CONFIG_DEBUG_KERNEL=y | ||
| 869 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 870 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 871 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 872 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 873 | CONFIG_SCHED_DEBUG=y | ||
| 874 | # CONFIG_SCHEDSTATS is not set | ||
| 875 | # CONFIG_TIMER_STATS is not set | ||
| 876 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 877 | # CONFIG_DEBUG_SLAB is not set | ||
| 878 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 879 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 880 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 881 | CONFIG_DEBUG_MUTEXES=y | ||
| 882 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 883 | # CONFIG_PROVE_LOCKING is not set | ||
| 884 | # CONFIG_LOCK_STAT is not set | ||
| 885 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 886 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 887 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 888 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 889 | # CONFIG_DEBUG_INFO is not set | ||
| 890 | # CONFIG_DEBUG_VM is not set | ||
| 891 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 892 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 893 | # CONFIG_DEBUG_LIST is not set | ||
| 894 | # CONFIG_DEBUG_SG is not set | ||
| 895 | CONFIG_FRAME_POINTER=y | ||
| 896 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 897 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 898 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 899 | # CONFIG_FAULT_INJECTION is not set | ||
| 900 | # CONFIG_LATENCYTOP is not set | ||
| 901 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 902 | CONFIG_HAVE_FTRACE=y | ||
| 903 | CONFIG_HAVE_DYNAMIC_FTRACE=y | ||
| 904 | # CONFIG_FTRACE is not set | ||
| 905 | # CONFIG_SCHED_TRACER is not set | ||
| 906 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 907 | # CONFIG_SAMPLES is not set | ||
| 908 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 909 | # CONFIG_KGDB is not set | ||
| 910 | CONFIG_DEBUG_USER=y | ||
| 911 | # CONFIG_DEBUG_ERRORS is not set | ||
| 912 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 913 | # CONFIG_DEBUG_LL is not set | ||
| 914 | |||
| 915 | # | ||
| 916 | # Security options | ||
| 917 | # | ||
| 918 | # CONFIG_KEYS is not set | ||
| 919 | # CONFIG_SECURITY is not set | ||
| 920 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 921 | # CONFIG_CRYPTO is not set | ||
| 922 | |||
| 923 | # | ||
| 924 | # Library routines | ||
| 925 | # | ||
| 926 | CONFIG_BITREVERSE=y | ||
| 927 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | ||
| 928 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
| 929 | # CONFIG_CRC_CCITT is not set | ||
| 930 | # CONFIG_CRC16 is not set | ||
| 931 | # CONFIG_CRC_T10DIF is not set | ||
| 932 | # CONFIG_CRC_ITU_T is not set | ||
| 933 | CONFIG_CRC32=y | ||
| 934 | # CONFIG_CRC7 is not set | ||
| 935 | # CONFIG_LIBCRC32C is not set | ||
| 936 | CONFIG_ZLIB_INFLATE=y | ||
| 937 | CONFIG_ZLIB_DEFLATE=y | ||
| 938 | CONFIG_PLIST=y | ||
| 939 | CONFIG_HAS_IOMEM=y | ||
| 940 | CONFIG_HAS_IOPORT=y | ||
| 941 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig index b1cd331aaecf..c66dd399e426 100644 --- a/arch/arm/configs/assabet_defconfig +++ b/arch/arm/configs/assabet_defconfig | |||
| @@ -89,7 +89,6 @@ CONFIG_SA1100_ASSABET=y | |||
| 89 | # CONFIG_SA1100_COLLIE is not set | 89 | # CONFIG_SA1100_COLLIE is not set |
| 90 | # CONFIG_SA1100_H3100 is not set | 90 | # CONFIG_SA1100_H3100 is not set |
| 91 | # CONFIG_SA1100_H3600 is not set | 91 | # CONFIG_SA1100_H3600 is not set |
| 92 | # CONFIG_SA1100_H3800 is not set | ||
| 93 | # CONFIG_SA1100_BADGE4 is not set | 92 | # CONFIG_SA1100_BADGE4 is not set |
| 94 | # CONFIG_SA1100_JORNADA720 is not set | 93 | # CONFIG_SA1100_JORNADA720 is not set |
| 95 | # CONFIG_SA1100_HACKKIT is not set | 94 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index 80222feb7dad..f264846218a2 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig | |||
| @@ -91,7 +91,6 @@ CONFIG_ARCH_SA1100=y | |||
| 91 | # CONFIG_SA1100_COLLIE is not set | 91 | # CONFIG_SA1100_COLLIE is not set |
| 92 | # CONFIG_SA1100_H3100 is not set | 92 | # CONFIG_SA1100_H3100 is not set |
| 93 | # CONFIG_SA1100_H3600 is not set | 93 | # CONFIG_SA1100_H3600 is not set |
| 94 | # CONFIG_SA1100_H3800 is not set | ||
| 95 | CONFIG_SA1100_BADGE4=y | 94 | CONFIG_SA1100_BADGE4=y |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| 97 | # CONFIG_SA1100_HACKKIT is not set | 96 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig index ee130b528bd4..2b4c0668b1b4 100644 --- a/arch/arm/configs/cerfcube_defconfig +++ b/arch/arm/configs/cerfcube_defconfig | |||
| @@ -93,7 +93,6 @@ CONFIG_SA1100_CERF_FLASH_16MB=y | |||
| 93 | # CONFIG_SA1100_COLLIE is not set | 93 | # CONFIG_SA1100_COLLIE is not set |
| 94 | # CONFIG_SA1100_H3100 is not set | 94 | # CONFIG_SA1100_H3100 is not set |
| 95 | # CONFIG_SA1100_H3600 is not set | 95 | # CONFIG_SA1100_H3600 is not set |
| 96 | # CONFIG_SA1100_H3800 is not set | ||
| 97 | # CONFIG_SA1100_BADGE4 is not set | 96 | # CONFIG_SA1100_BADGE4 is not set |
| 98 | # CONFIG_SA1100_JORNADA720 is not set | 97 | # CONFIG_SA1100_JORNADA720 is not set |
| 99 | # CONFIG_SA1100_HACKKIT is not set | 98 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/xm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig index 1039f366bf8d..797b790cba78 100644 --- a/arch/arm/configs/xm_x2xx_defconfig +++ b/arch/arm/configs/cm_x2xx_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.27-rc8 | 3 | # Linux kernel version: 2.6.29-rc2 |
| 4 | # Sun Oct 5 11:05:36 2008 | 4 | # Sun Feb 1 16:31:36 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| @@ -22,7 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 23 | CONFIG_GENERIC_HWEIGHT=y | 23 | CONFIG_GENERIC_HWEIGHT=y |
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 26 | CONFIG_ZONE_DMA=y | 25 | CONFIG_ZONE_DMA=y |
| 27 | CONFIG_ARCH_MTD_XIP=y | 26 | CONFIG_ARCH_MTD_XIP=y |
| 28 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| @@ -47,12 +46,12 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 47 | CONFIG_IKCONFIG=y | 46 | CONFIG_IKCONFIG=y |
| 48 | CONFIG_IKCONFIG_PROC=y | 47 | CONFIG_IKCONFIG_PROC=y |
| 49 | CONFIG_LOG_BUF_SHIFT=14 | 48 | CONFIG_LOG_BUF_SHIFT=14 |
| 50 | # CONFIG_CGROUPS is not set | ||
| 51 | CONFIG_GROUP_SCHED=y | 49 | CONFIG_GROUP_SCHED=y |
| 52 | CONFIG_FAIR_GROUP_SCHED=y | 50 | CONFIG_FAIR_GROUP_SCHED=y |
| 53 | # CONFIG_RT_GROUP_SCHED is not set | 51 | # CONFIG_RT_GROUP_SCHED is not set |
| 54 | CONFIG_USER_SCHED=y | 52 | CONFIG_USER_SCHED=y |
| 55 | # CONFIG_CGROUP_SCHED is not set | 53 | # CONFIG_CGROUP_SCHED is not set |
| 54 | # CONFIG_CGROUPS is not set | ||
| 56 | CONFIG_SYSFS_DEPRECATED=y | 55 | CONFIG_SYSFS_DEPRECATED=y |
| 57 | CONFIG_SYSFS_DEPRECATED_V2=y | 56 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 58 | # CONFIG_RELAY is not set | 57 | # CONFIG_RELAY is not set |
| @@ -80,27 +79,21 @@ CONFIG_SIGNALFD=y | |||
| 80 | CONFIG_TIMERFD=y | 79 | CONFIG_TIMERFD=y |
| 81 | CONFIG_EVENTFD=y | 80 | CONFIG_EVENTFD=y |
| 82 | CONFIG_SHMEM=y | 81 | CONFIG_SHMEM=y |
| 82 | CONFIG_AIO=y | ||
| 83 | # CONFIG_VM_EVENT_COUNTERS is not set | 83 | # CONFIG_VM_EVENT_COUNTERS is not set |
| 84 | CONFIG_PCI_QUIRKS=y | ||
| 84 | # CONFIG_SLUB_DEBUG is not set | 85 | # CONFIG_SLUB_DEBUG is not set |
| 85 | # CONFIG_SLAB is not set | 86 | # CONFIG_SLAB is not set |
| 86 | CONFIG_SLUB=y | 87 | CONFIG_SLUB=y |
| 87 | # CONFIG_SLOB is not set | 88 | # CONFIG_SLOB is not set |
| 88 | # CONFIG_PROFILING is not set | 89 | # CONFIG_PROFILING is not set |
| 89 | # CONFIG_MARKERS is not set | ||
| 90 | CONFIG_HAVE_OPROFILE=y | 90 | CONFIG_HAVE_OPROFILE=y |
| 91 | # CONFIG_KPROBES is not set | 91 | # CONFIG_KPROBES is not set |
| 92 | # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set | ||
| 93 | # CONFIG_HAVE_IOREMAP_PROT is not set | ||
| 94 | CONFIG_HAVE_KPROBES=y | 92 | CONFIG_HAVE_KPROBES=y |
| 95 | CONFIG_HAVE_KRETPROBES=y | 93 | CONFIG_HAVE_KRETPROBES=y |
| 96 | # CONFIG_HAVE_ARCH_TRACEHOOK is not set | ||
| 97 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 98 | # CONFIG_USE_GENERIC_SMP_HELPERS is not set | ||
| 99 | CONFIG_HAVE_CLK=y | 94 | CONFIG_HAVE_CLK=y |
| 100 | # CONFIG_PROC_PAGE_MONITOR is not set | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 95 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 102 | CONFIG_RT_MUTEXES=y | 96 | CONFIG_RT_MUTEXES=y |
| 103 | # CONFIG_TINY_SHMEM is not set | ||
| 104 | CONFIG_BASE_SMALL=0 | 97 | CONFIG_BASE_SMALL=0 |
| 105 | CONFIG_MODULES=y | 98 | CONFIG_MODULES=y |
| 106 | # CONFIG_MODULE_FORCE_LOAD is not set | 99 | # CONFIG_MODULE_FORCE_LOAD is not set |
| @@ -108,11 +101,9 @@ CONFIG_MODULE_UNLOAD=y | |||
| 108 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 101 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 109 | # CONFIG_MODVERSIONS is not set | 102 | # CONFIG_MODVERSIONS is not set |
| 110 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 103 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 111 | CONFIG_KMOD=y | ||
| 112 | CONFIG_BLOCK=y | 104 | CONFIG_BLOCK=y |
| 113 | # CONFIG_LBD is not set | 105 | # CONFIG_LBD is not set |
| 114 | # CONFIG_BLK_DEV_IO_TRACE is not set | 106 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 115 | # CONFIG_LSF is not set | ||
| 116 | # CONFIG_BLK_DEV_BSG is not set | 107 | # CONFIG_BLK_DEV_BSG is not set |
| 117 | # CONFIG_BLK_DEV_INTEGRITY is not set | 108 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 118 | 109 | ||
| @@ -129,6 +120,11 @@ CONFIG_DEFAULT_CFQ=y | |||
| 129 | # CONFIG_DEFAULT_NOOP is not set | 120 | # CONFIG_DEFAULT_NOOP is not set |
| 130 | CONFIG_DEFAULT_IOSCHED="cfq" | 121 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 131 | CONFIG_CLASSIC_RCU=y | 122 | CONFIG_CLASSIC_RCU=y |
| 123 | # CONFIG_TREE_RCU is not set | ||
| 124 | # CONFIG_PREEMPT_RCU is not set | ||
| 125 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 126 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 127 | CONFIG_FREEZER=y | ||
| 132 | 128 | ||
| 133 | # | 129 | # |
| 134 | # System Type | 130 | # System Type |
| @@ -138,7 +134,6 @@ CONFIG_CLASSIC_RCU=y | |||
| 138 | # CONFIG_ARCH_REALVIEW is not set | 134 | # CONFIG_ARCH_REALVIEW is not set |
| 139 | # CONFIG_ARCH_VERSATILE is not set | 135 | # CONFIG_ARCH_VERSATILE is not set |
| 140 | # CONFIG_ARCH_AT91 is not set | 136 | # CONFIG_ARCH_AT91 is not set |
| 141 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 142 | # CONFIG_ARCH_CLPS711X is not set | 137 | # CONFIG_ARCH_CLPS711X is not set |
| 143 | # CONFIG_ARCH_EBSA110 is not set | 138 | # CONFIG_ARCH_EBSA110 is not set |
| 144 | # CONFIG_ARCH_EP93XX is not set | 139 | # CONFIG_ARCH_EP93XX is not set |
| @@ -165,17 +160,19 @@ CONFIG_ARCH_PXA=y | |||
| 165 | # CONFIG_ARCH_RPC is not set | 160 | # CONFIG_ARCH_RPC is not set |
| 166 | # CONFIG_ARCH_SA1100 is not set | 161 | # CONFIG_ARCH_SA1100 is not set |
| 167 | # CONFIG_ARCH_S3C2410 is not set | 162 | # CONFIG_ARCH_S3C2410 is not set |
| 163 | # CONFIG_ARCH_S3C64XX is not set | ||
| 168 | # CONFIG_ARCH_SHARK is not set | 164 | # CONFIG_ARCH_SHARK is not set |
| 169 | # CONFIG_ARCH_LH7A40X is not set | 165 | # CONFIG_ARCH_LH7A40X is not set |
| 170 | # CONFIG_ARCH_DAVINCI is not set | 166 | # CONFIG_ARCH_DAVINCI is not set |
| 171 | # CONFIG_ARCH_OMAP is not set | 167 | # CONFIG_ARCH_OMAP is not set |
| 172 | # CONFIG_ARCH_MSM7X00A is not set | 168 | # CONFIG_ARCH_MSM is not set |
| 173 | CONFIG_DMABOUNCE=y | 169 | # CONFIG_ARCH_W90X900 is not set |
| 174 | 170 | ||
| 175 | # | 171 | # |
| 176 | # Intel PXA2xx/PXA3xx Implementations | 172 | # Intel PXA2xx/PXA3xx Implementations |
| 177 | # | 173 | # |
| 178 | # CONFIG_ARCH_GUMSTIX is not set | 174 | # CONFIG_ARCH_GUMSTIX is not set |
| 175 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 179 | # CONFIG_ARCH_LUBBOCK is not set | 176 | # CONFIG_ARCH_LUBBOCK is not set |
| 180 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 177 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 181 | # CONFIG_MACH_MAINSTONE is not set | 178 | # CONFIG_MACH_MAINSTONE is not set |
| @@ -185,7 +182,9 @@ CONFIG_DMABOUNCE=y | |||
| 185 | # CONFIG_ARCH_VIPER is not set | 182 | # CONFIG_ARCH_VIPER is not set |
| 186 | # CONFIG_ARCH_PXA_ESERIES is not set | 183 | # CONFIG_ARCH_PXA_ESERIES is not set |
| 187 | # CONFIG_TRIZEPS_PXA is not set | 184 | # CONFIG_TRIZEPS_PXA is not set |
| 188 | CONFIG_MACH_EM_X270=y | 185 | # CONFIG_MACH_H5000 is not set |
| 186 | # CONFIG_MACH_EM_X270 is not set | ||
| 187 | # CONFIG_MACH_EXEDA is not set | ||
| 189 | # CONFIG_MACH_COLIBRI is not set | 188 | # CONFIG_MACH_COLIBRI is not set |
| 190 | # CONFIG_MACH_ZYLONITE is not set | 189 | # CONFIG_MACH_ZYLONITE is not set |
| 191 | # CONFIG_MACH_LITTLETON is not set | 190 | # CONFIG_MACH_LITTLETON is not set |
| @@ -204,14 +203,6 @@ CONFIG_PXA_SSP=y | |||
| 204 | # CONFIG_PXA_PWM is not set | 203 | # CONFIG_PXA_PWM is not set |
| 205 | 204 | ||
| 206 | # | 205 | # |
| 207 | # Boot options | ||
| 208 | # | ||
| 209 | |||
| 210 | # | ||
| 211 | # Power management | ||
| 212 | # | ||
| 213 | |||
| 214 | # | ||
| 215 | # Processor Type | 206 | # Processor Type |
| 216 | # | 207 | # |
| 217 | CONFIG_CPU_32=y | 208 | CONFIG_CPU_32=y |
| @@ -232,6 +223,8 @@ CONFIG_ARM_THUMB=y | |||
| 232 | # CONFIG_OUTER_CACHE is not set | 223 | # CONFIG_OUTER_CACHE is not set |
| 233 | CONFIG_IWMMXT=y | 224 | CONFIG_IWMMXT=y |
| 234 | CONFIG_XSCALE_PMU=y | 225 | CONFIG_XSCALE_PMU=y |
| 226 | CONFIG_DMABOUNCE=y | ||
| 227 | CONFIG_COMMON_CLKDEV=y | ||
| 235 | 228 | ||
| 236 | # | 229 | # |
| 237 | # Bus support | 230 | # Bus support |
| @@ -242,6 +235,7 @@ CONFIG_PCI_HOST_ITE8152=y | |||
| 242 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 235 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 243 | CONFIG_PCI_LEGACY=y | 236 | CONFIG_PCI_LEGACY=y |
| 244 | # CONFIG_PCI_DEBUG is not set | 237 | # CONFIG_PCI_DEBUG is not set |
| 238 | # CONFIG_PCI_STUB is not set | ||
| 245 | CONFIG_PCCARD=m | 239 | CONFIG_PCCARD=m |
| 246 | # CONFIG_PCMCIA_DEBUG is not set | 240 | # CONFIG_PCMCIA_DEBUG is not set |
| 247 | CONFIG_PCMCIA=m | 241 | CONFIG_PCMCIA=m |
| @@ -287,14 +281,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 287 | # CONFIG_SPARSEMEM_MANUAL is not set | 281 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 288 | CONFIG_FLATMEM=y | 282 | CONFIG_FLATMEM=y |
| 289 | CONFIG_FLAT_NODE_MEM_MAP=y | 283 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 290 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 291 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 292 | CONFIG_PAGEFLAGS_EXTENDED=y | 284 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 293 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 285 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 294 | # CONFIG_RESOURCES_64BIT is not set | 286 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 295 | CONFIG_ZONE_DMA_FLAG=1 | 287 | CONFIG_ZONE_DMA_FLAG=1 |
| 296 | CONFIG_BOUNCE=y | 288 | CONFIG_BOUNCE=y |
| 297 | CONFIG_VIRT_TO_BUS=y | 289 | CONFIG_VIRT_TO_BUS=y |
| 290 | CONFIG_UNEVICTABLE_LRU=y | ||
| 298 | CONFIG_ALIGNMENT_TRAP=y | 291 | CONFIG_ALIGNMENT_TRAP=y |
| 299 | 292 | ||
| 300 | # | 293 | # |
| @@ -327,6 +320,8 @@ CONFIG_FPE_NWFPE=y | |||
| 327 | # Userspace binary formats | 320 | # Userspace binary formats |
| 328 | # | 321 | # |
| 329 | CONFIG_BINFMT_ELF=y | 322 | CONFIG_BINFMT_ELF=y |
| 323 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 324 | CONFIG_HAVE_AOUT=y | ||
| 330 | # CONFIG_BINFMT_AOUT is not set | 325 | # CONFIG_BINFMT_AOUT is not set |
| 331 | # CONFIG_BINFMT_MISC is not set | 326 | # CONFIG_BINFMT_MISC is not set |
| 332 | 327 | ||
| @@ -345,6 +340,7 @@ CONFIG_NET=y | |||
| 345 | # | 340 | # |
| 346 | # Networking options | 341 | # Networking options |
| 347 | # | 342 | # |
| 343 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 348 | CONFIG_PACKET=y | 344 | CONFIG_PACKET=y |
| 349 | CONFIG_PACKET_MMAP=y | 345 | CONFIG_PACKET_MMAP=y |
| 350 | CONFIG_UNIX=y | 346 | CONFIG_UNIX=y |
| @@ -389,6 +385,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 389 | # CONFIG_TIPC is not set | 385 | # CONFIG_TIPC is not set |
| 390 | # CONFIG_ATM is not set | 386 | # CONFIG_ATM is not set |
| 391 | # CONFIG_BRIDGE is not set | 387 | # CONFIG_BRIDGE is not set |
| 388 | # CONFIG_NET_DSA is not set | ||
| 392 | # CONFIG_VLAN_8021Q is not set | 389 | # CONFIG_VLAN_8021Q is not set |
| 393 | # CONFIG_DECNET is not set | 390 | # CONFIG_DECNET is not set |
| 394 | # CONFIG_LLC2 is not set | 391 | # CONFIG_LLC2 is not set |
| @@ -399,6 +396,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 399 | # CONFIG_ECONET is not set | 396 | # CONFIG_ECONET is not set |
| 400 | # CONFIG_WAN_ROUTER is not set | 397 | # CONFIG_WAN_ROUTER is not set |
| 401 | # CONFIG_NET_SCHED is not set | 398 | # CONFIG_NET_SCHED is not set |
| 399 | # CONFIG_DCB is not set | ||
| 402 | 400 | ||
| 403 | # | 401 | # |
| 404 | # Network testing | 402 | # Network testing |
| @@ -420,8 +418,6 @@ CONFIG_BT_HIDP=m | |||
| 420 | # | 418 | # |
| 421 | # Bluetooth device drivers | 419 | # Bluetooth device drivers |
| 422 | # | 420 | # |
| 423 | CONFIG_BT_HCIUSB=m | ||
| 424 | CONFIG_BT_HCIUSB_SCO=y | ||
| 425 | # CONFIG_BT_HCIBTUSB is not set | 421 | # CONFIG_BT_HCIBTUSB is not set |
| 426 | # CONFIG_BT_HCIBTSDIO is not set | 422 | # CONFIG_BT_HCIBTSDIO is not set |
| 427 | # CONFIG_BT_HCIUART is not set | 423 | # CONFIG_BT_HCIUART is not set |
| @@ -434,15 +430,15 @@ CONFIG_BT_HCIUSB_SCO=y | |||
| 434 | # CONFIG_BT_HCIBTUART is not set | 430 | # CONFIG_BT_HCIBTUART is not set |
| 435 | # CONFIG_BT_HCIVHCI is not set | 431 | # CONFIG_BT_HCIVHCI is not set |
| 436 | # CONFIG_AF_RXRPC is not set | 432 | # CONFIG_AF_RXRPC is not set |
| 437 | 433 | # CONFIG_PHONET is not set | |
| 438 | # | 434 | CONFIG_WIRELESS=y |
| 439 | # Wireless | ||
| 440 | # | ||
| 441 | # CONFIG_CFG80211 is not set | 435 | # CONFIG_CFG80211 is not set |
| 436 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 442 | CONFIG_WIRELESS_EXT=y | 437 | CONFIG_WIRELESS_EXT=y |
| 443 | CONFIG_WIRELESS_EXT_SYSFS=y | 438 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 439 | CONFIG_LIB80211=m | ||
| 444 | # CONFIG_MAC80211 is not set | 440 | # CONFIG_MAC80211 is not set |
| 445 | # CONFIG_IEEE80211 is not set | 441 | # CONFIG_WIMAX is not set |
| 446 | # CONFIG_RFKILL is not set | 442 | # CONFIG_RFKILL is not set |
| 447 | # CONFIG_NET_9P is not set | 443 | # CONFIG_NET_9P is not set |
| 448 | 444 | ||
| @@ -467,6 +463,7 @@ CONFIG_MTD=y | |||
| 467 | # CONFIG_MTD_DEBUG is not set | 463 | # CONFIG_MTD_DEBUG is not set |
| 468 | # CONFIG_MTD_CONCAT is not set | 464 | # CONFIG_MTD_CONCAT is not set |
| 469 | CONFIG_MTD_PARTITIONS=y | 465 | CONFIG_MTD_PARTITIONS=y |
| 466 | # CONFIG_MTD_TESTS is not set | ||
| 470 | # CONFIG_MTD_REDBOOT_PARTS is not set | 467 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 471 | CONFIG_MTD_CMDLINE_PARTS=y | 468 | CONFIG_MTD_CMDLINE_PARTS=y |
| 472 | # CONFIG_MTD_AFS_PARTS is not set | 469 | # CONFIG_MTD_AFS_PARTS is not set |
| @@ -521,9 +518,7 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 521 | # | 518 | # |
| 522 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 519 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 523 | CONFIG_MTD_PHYSMAP=y | 520 | CONFIG_MTD_PHYSMAP=y |
| 524 | CONFIG_MTD_PHYSMAP_START=0x0 | 521 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 525 | CONFIG_MTD_PHYSMAP_LEN=0x400000 | ||
| 526 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 527 | CONFIG_MTD_PXA2XX=y | 522 | CONFIG_MTD_PXA2XX=y |
| 528 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 523 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 529 | # CONFIG_MTD_IMPA7 is not set | 524 | # CONFIG_MTD_IMPA7 is not set |
| @@ -535,6 +530,8 @@ CONFIG_MTD_PXA2XX=y | |||
| 535 | # Self-contained MTD device drivers | 530 | # Self-contained MTD device drivers |
| 536 | # | 531 | # |
| 537 | # CONFIG_MTD_PMC551 is not set | 532 | # CONFIG_MTD_PMC551 is not set |
| 533 | # CONFIG_MTD_DATAFLASH is not set | ||
| 534 | # CONFIG_MTD_M25P80 is not set | ||
| 538 | # CONFIG_MTD_SLRAM is not set | 535 | # CONFIG_MTD_SLRAM is not set |
| 539 | # CONFIG_MTD_PHRAM is not set | 536 | # CONFIG_MTD_PHRAM is not set |
| 540 | # CONFIG_MTD_MTDRAM is not set | 537 | # CONFIG_MTD_MTDRAM is not set |
| @@ -563,6 +560,12 @@ CONFIG_MTD_NAND_PLATFORM=y | |||
| 563 | # CONFIG_MTD_ONENAND is not set | 560 | # CONFIG_MTD_ONENAND is not set |
| 564 | 561 | ||
| 565 | # | 562 | # |
| 563 | # LPDDR flash memory drivers | ||
| 564 | # | ||
| 565 | # CONFIG_MTD_LPDDR is not set | ||
| 566 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 567 | |||
| 568 | # | ||
| 566 | # UBI - Unsorted block images | 569 | # UBI - Unsorted block images |
| 567 | # | 570 | # |
| 568 | # CONFIG_MTD_UBI is not set | 571 | # CONFIG_MTD_UBI is not set |
| @@ -642,6 +645,8 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 642 | # CONFIG_MEGARAID_LEGACY is not set | 645 | # CONFIG_MEGARAID_LEGACY is not set |
| 643 | # CONFIG_MEGARAID_SAS is not set | 646 | # CONFIG_MEGARAID_SAS is not set |
| 644 | # CONFIG_SCSI_HPTIOP is not set | 647 | # CONFIG_SCSI_HPTIOP is not set |
| 648 | # CONFIG_LIBFC is not set | ||
| 649 | # CONFIG_FCOE is not set | ||
| 645 | # CONFIG_SCSI_DMX3191D is not set | 650 | # CONFIG_SCSI_DMX3191D is not set |
| 646 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 651 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 647 | # CONFIG_SCSI_IPS is not set | 652 | # CONFIG_SCSI_IPS is not set |
| @@ -756,26 +761,30 @@ CONFIG_MII=y | |||
| 756 | CONFIG_DM9000=y | 761 | CONFIG_DM9000=y |
| 757 | CONFIG_DM9000_DEBUGLEVEL=1 | 762 | CONFIG_DM9000_DEBUGLEVEL=1 |
| 758 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | 763 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set |
| 764 | # CONFIG_ENC28J60 is not set | ||
| 759 | # CONFIG_SMC911X is not set | 765 | # CONFIG_SMC911X is not set |
| 766 | # CONFIG_SMSC911X is not set | ||
| 760 | # CONFIG_NET_TULIP is not set | 767 | # CONFIG_NET_TULIP is not set |
| 761 | # CONFIG_HP100 is not set | 768 | # CONFIG_HP100 is not set |
| 762 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 769 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 763 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 770 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 764 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 771 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 765 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 772 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 773 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 774 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 775 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 766 | CONFIG_NET_PCI=y | 776 | CONFIG_NET_PCI=y |
| 767 | # CONFIG_PCNET32 is not set | 777 | # CONFIG_PCNET32 is not set |
| 768 | # CONFIG_AMD8111_ETH is not set | 778 | # CONFIG_AMD8111_ETH is not set |
| 769 | # CONFIG_ADAPTEC_STARFIRE is not set | 779 | # CONFIG_ADAPTEC_STARFIRE is not set |
| 770 | # CONFIG_B44 is not set | 780 | # CONFIG_B44 is not set |
| 771 | # CONFIG_FORCEDETH is not set | 781 | # CONFIG_FORCEDETH is not set |
| 772 | # CONFIG_EEPRO100 is not set | ||
| 773 | # CONFIG_E100 is not set | 782 | # CONFIG_E100 is not set |
| 774 | # CONFIG_FEALNX is not set | 783 | # CONFIG_FEALNX is not set |
| 775 | # CONFIG_NATSEMI is not set | 784 | # CONFIG_NATSEMI is not set |
| 776 | # CONFIG_NE2K_PCI is not set | 785 | # CONFIG_NE2K_PCI is not set |
| 777 | # CONFIG_8139CP is not set | 786 | # CONFIG_8139CP is not set |
| 778 | CONFIG_8139TOO=y | 787 | CONFIG_8139TOO=m |
| 779 | # CONFIG_8139TOO_PIO is not set | 788 | # CONFIG_8139TOO_PIO is not set |
| 780 | # CONFIG_8139TOO_TUNE_TWISTER is not set | 789 | # CONFIG_8139TOO_TUNE_TWISTER is not set |
| 781 | # CONFIG_8139TOO_8129 is not set | 790 | # CONFIG_8139TOO_8129 is not set |
| @@ -783,10 +792,12 @@ CONFIG_8139TOO=y | |||
| 783 | # CONFIG_R6040 is not set | 792 | # CONFIG_R6040 is not set |
| 784 | # CONFIG_SIS900 is not set | 793 | # CONFIG_SIS900 is not set |
| 785 | # CONFIG_EPIC100 is not set | 794 | # CONFIG_EPIC100 is not set |
| 795 | # CONFIG_SMSC9420 is not set | ||
| 786 | # CONFIG_SUNDANCE is not set | 796 | # CONFIG_SUNDANCE is not set |
| 787 | # CONFIG_TLAN is not set | 797 | # CONFIG_TLAN is not set |
| 788 | # CONFIG_VIA_RHINE is not set | 798 | # CONFIG_VIA_RHINE is not set |
| 789 | # CONFIG_SC92031 is not set | 799 | # CONFIG_SC92031 is not set |
| 800 | # CONFIG_ATL2 is not set | ||
| 790 | # CONFIG_NETDEV_1000 is not set | 801 | # CONFIG_NETDEV_1000 is not set |
| 791 | # CONFIG_NETDEV_10000 is not set | 802 | # CONFIG_NETDEV_10000 is not set |
| 792 | # CONFIG_TR is not set | 803 | # CONFIG_TR is not set |
| @@ -797,8 +808,6 @@ CONFIG_8139TOO=y | |||
| 797 | # CONFIG_WLAN_PRE80211 is not set | 808 | # CONFIG_WLAN_PRE80211 is not set |
| 798 | CONFIG_WLAN_80211=y | 809 | CONFIG_WLAN_80211=y |
| 799 | # CONFIG_PCMCIA_RAYCS is not set | 810 | # CONFIG_PCMCIA_RAYCS is not set |
| 800 | # CONFIG_IPW2100 is not set | ||
| 801 | # CONFIG_IPW2200 is not set | ||
| 802 | CONFIG_LIBERTAS=m | 811 | CONFIG_LIBERTAS=m |
| 803 | # CONFIG_LIBERTAS_USB is not set | 812 | # CONFIG_LIBERTAS_USB is not set |
| 804 | # CONFIG_LIBERTAS_CS is not set | 813 | # CONFIG_LIBERTAS_CS is not set |
| @@ -811,10 +820,16 @@ CONFIG_LIBERTAS_SDIO=m | |||
| 811 | # CONFIG_PRISM54 is not set | 820 | # CONFIG_PRISM54 is not set |
| 812 | # CONFIG_USB_ZD1201 is not set | 821 | # CONFIG_USB_ZD1201 is not set |
| 813 | # CONFIG_USB_NET_RNDIS_WLAN is not set | 822 | # CONFIG_USB_NET_RNDIS_WLAN is not set |
| 823 | # CONFIG_IPW2100 is not set | ||
| 824 | # CONFIG_IPW2200 is not set | ||
| 814 | # CONFIG_IWLWIFI_LEDS is not set | 825 | # CONFIG_IWLWIFI_LEDS is not set |
| 815 | # CONFIG_HOSTAP is not set | 826 | # CONFIG_HOSTAP is not set |
| 816 | 827 | ||
| 817 | # | 828 | # |
| 829 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 830 | # | ||
| 831 | |||
| 832 | # | ||
| 818 | # USB Network Adapters | 833 | # USB Network Adapters |
| 819 | # | 834 | # |
| 820 | # CONFIG_USB_CATC is not set | 835 | # CONFIG_USB_CATC is not set |
| @@ -879,22 +894,22 @@ CONFIG_KEYBOARD_PXA27x=m | |||
| 879 | # CONFIG_INPUT_JOYSTICK is not set | 894 | # CONFIG_INPUT_JOYSTICK is not set |
| 880 | # CONFIG_INPUT_TABLET is not set | 895 | # CONFIG_INPUT_TABLET is not set |
| 881 | CONFIG_INPUT_TOUCHSCREEN=y | 896 | CONFIG_INPUT_TOUCHSCREEN=y |
| 897 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 882 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 898 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 883 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 899 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 884 | # CONFIG_TOUCHSCREEN_ELO is not set | 900 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 901 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 885 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 902 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 886 | # CONFIG_TOUCHSCREEN_INEXIO is not set | 903 | # CONFIG_TOUCHSCREEN_INEXIO is not set |
| 887 | # CONFIG_TOUCHSCREEN_MK712 is not set | 904 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 888 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 905 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 889 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 906 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 890 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 907 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 891 | CONFIG_TOUCHSCREEN_WM97XX=m | 908 | CONFIG_TOUCHSCREEN_UCB1400=m |
| 892 | # CONFIG_TOUCHSCREEN_WM9705 is not set | 909 | # CONFIG_TOUCHSCREEN_WM97XX is not set |
| 893 | CONFIG_TOUCHSCREEN_WM9712=y | ||
| 894 | # CONFIG_TOUCHSCREEN_WM9713 is not set | ||
| 895 | # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set | ||
| 896 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 910 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 897 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | 911 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set |
| 912 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 898 | # CONFIG_INPUT_MISC is not set | 913 | # CONFIG_INPUT_MISC is not set |
| 899 | 914 | ||
| 900 | # | 915 | # |
| @@ -933,6 +948,7 @@ CONFIG_SERIAL_CORE=y | |||
| 933 | CONFIG_SERIAL_CORE_CONSOLE=y | 948 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 934 | # CONFIG_SERIAL_JSM is not set | 949 | # CONFIG_SERIAL_JSM is not set |
| 935 | CONFIG_UNIX98_PTYS=y | 950 | CONFIG_UNIX98_PTYS=y |
| 951 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 936 | CONFIG_LEGACY_PTYS=y | 952 | CONFIG_LEGACY_PTYS=y |
| 937 | CONFIG_LEGACY_PTY_COUNT=16 | 953 | CONFIG_LEGACY_PTY_COUNT=16 |
| 938 | # CONFIG_IPMI_HANDLER is not set | 954 | # CONFIG_IPMI_HANDLER is not set |
| @@ -1009,26 +1025,45 @@ CONFIG_I2C_PXA=y | |||
| 1009 | # Miscellaneous I2C Chip support | 1025 | # Miscellaneous I2C Chip support |
| 1010 | # | 1026 | # |
| 1011 | # CONFIG_DS1682 is not set | 1027 | # CONFIG_DS1682 is not set |
| 1012 | # CONFIG_EEPROM_AT24 is not set | 1028 | # CONFIG_AT24 is not set |
| 1013 | # CONFIG_EEPROM_LEGACY is not set | 1029 | # CONFIG_SENSORS_EEPROM is not set |
| 1014 | # CONFIG_SENSORS_PCF8574 is not set | 1030 | # CONFIG_SENSORS_PCF8574 is not set |
| 1015 | # CONFIG_PCF8575 is not set | 1031 | # CONFIG_PCF8575 is not set |
| 1016 | # CONFIG_SENSORS_PCA9539 is not set | 1032 | # CONFIG_SENSORS_PCA9539 is not set |
| 1017 | # CONFIG_SENSORS_PCF8591 is not set | 1033 | # CONFIG_SENSORS_PCF8591 is not set |
| 1018 | # CONFIG_TPS65010 is not set | ||
| 1019 | # CONFIG_SENSORS_MAX6875 is not set | 1034 | # CONFIG_SENSORS_MAX6875 is not set |
| 1020 | # CONFIG_SENSORS_TSL2550 is not set | 1035 | # CONFIG_SENSORS_TSL2550 is not set |
| 1021 | # CONFIG_I2C_DEBUG_CORE is not set | 1036 | # CONFIG_I2C_DEBUG_CORE is not set |
| 1022 | # CONFIG_I2C_DEBUG_ALGO is not set | 1037 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 1023 | # CONFIG_I2C_DEBUG_BUS is not set | 1038 | # CONFIG_I2C_DEBUG_BUS is not set |
| 1024 | # CONFIG_I2C_DEBUG_CHIP is not set | 1039 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 1025 | # CONFIG_SPI is not set | 1040 | CONFIG_SPI=y |
| 1041 | # CONFIG_SPI_DEBUG is not set | ||
| 1042 | CONFIG_SPI_MASTER=y | ||
| 1043 | |||
| 1044 | # | ||
| 1045 | # SPI Master Controller Drivers | ||
| 1046 | # | ||
| 1047 | # CONFIG_SPI_BITBANG is not set | ||
| 1048 | # CONFIG_SPI_GPIO is not set | ||
| 1049 | CONFIG_SPI_PXA2XX=m | ||
| 1050 | |||
| 1051 | # | ||
| 1052 | # SPI Protocol Masters | ||
| 1053 | # | ||
| 1054 | # CONFIG_SPI_AT25 is not set | ||
| 1055 | # CONFIG_SPI_SPIDEV is not set | ||
| 1056 | # CONFIG_SPI_TLE62X0 is not set | ||
| 1026 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 1057 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 1027 | CONFIG_GPIOLIB=y | 1058 | CONFIG_GPIOLIB=y |
| 1028 | # CONFIG_DEBUG_GPIO is not set | 1059 | # CONFIG_DEBUG_GPIO is not set |
| 1029 | # CONFIG_GPIO_SYSFS is not set | 1060 | # CONFIG_GPIO_SYSFS is not set |
| 1030 | 1061 | ||
| 1031 | # | 1062 | # |
| 1063 | # Memory mapped GPIO expanders: | ||
| 1064 | # | ||
| 1065 | |||
| 1066 | # | ||
| 1032 | # I2C GPIO expanders: | 1067 | # I2C GPIO expanders: |
| 1033 | # | 1068 | # |
| 1034 | # CONFIG_GPIO_MAX732X is not set | 1069 | # CONFIG_GPIO_MAX732X is not set |
| @@ -1043,17 +1078,19 @@ CONFIG_GPIOLIB=y | |||
| 1043 | # | 1078 | # |
| 1044 | # SPI GPIO expanders: | 1079 | # SPI GPIO expanders: |
| 1045 | # | 1080 | # |
| 1081 | # CONFIG_GPIO_MAX7301 is not set | ||
| 1082 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 1046 | # CONFIG_W1 is not set | 1083 | # CONFIG_W1 is not set |
| 1047 | # CONFIG_POWER_SUPPLY is not set | 1084 | # CONFIG_POWER_SUPPLY is not set |
| 1048 | # CONFIG_HWMON is not set | 1085 | # CONFIG_HWMON is not set |
| 1049 | # CONFIG_THERMAL is not set | 1086 | # CONFIG_THERMAL is not set |
| 1050 | # CONFIG_THERMAL_HWMON is not set | 1087 | # CONFIG_THERMAL_HWMON is not set |
| 1051 | # CONFIG_WATCHDOG is not set | 1088 | # CONFIG_WATCHDOG is not set |
| 1089 | CONFIG_SSB_POSSIBLE=y | ||
| 1052 | 1090 | ||
| 1053 | # | 1091 | # |
| 1054 | # Sonics Silicon Backplane | 1092 | # Sonics Silicon Backplane |
| 1055 | # | 1093 | # |
| 1056 | CONFIG_SSB_POSSIBLE=y | ||
| 1057 | # CONFIG_SSB is not set | 1094 | # CONFIG_SSB is not set |
| 1058 | 1095 | ||
| 1059 | # | 1096 | # |
| @@ -1064,11 +1101,17 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1064 | # CONFIG_MFD_ASIC3 is not set | 1101 | # CONFIG_MFD_ASIC3 is not set |
| 1065 | # CONFIG_HTC_EGPIO is not set | 1102 | # CONFIG_HTC_EGPIO is not set |
| 1066 | # CONFIG_HTC_PASIC3 is not set | 1103 | # CONFIG_HTC_PASIC3 is not set |
| 1067 | # CONFIG_UCB1400_CORE is not set | 1104 | CONFIG_UCB1400_CORE=m |
| 1105 | # CONFIG_TPS65010 is not set | ||
| 1106 | # CONFIG_TWL4030_CORE is not set | ||
| 1068 | # CONFIG_MFD_TMIO is not set | 1107 | # CONFIG_MFD_TMIO is not set |
| 1069 | # CONFIG_MFD_T7L66XB is not set | 1108 | # CONFIG_MFD_T7L66XB is not set |
| 1070 | # CONFIG_MFD_TC6387XB is not set | 1109 | # CONFIG_MFD_TC6387XB is not set |
| 1071 | # CONFIG_MFD_TC6393XB is not set | 1110 | # CONFIG_MFD_TC6393XB is not set |
| 1111 | # CONFIG_PMIC_DA903X is not set | ||
| 1112 | # CONFIG_MFD_WM8400 is not set | ||
| 1113 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1114 | # CONFIG_MFD_PCF50633 is not set | ||
| 1072 | 1115 | ||
| 1073 | # | 1116 | # |
| 1074 | # Multimedia devices | 1117 | # Multimedia devices |
| @@ -1077,13 +1120,117 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1077 | # | 1120 | # |
| 1078 | # Multimedia core support | 1121 | # Multimedia core support |
| 1079 | # | 1122 | # |
| 1080 | # CONFIG_VIDEO_DEV is not set | 1123 | CONFIG_VIDEO_DEV=m |
| 1124 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1125 | # CONFIG_VIDEO_ALLOW_V4L1 is not set | ||
| 1126 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1081 | # CONFIG_DVB_CORE is not set | 1127 | # CONFIG_DVB_CORE is not set |
| 1082 | # CONFIG_VIDEO_MEDIA is not set | 1128 | CONFIG_VIDEO_MEDIA=m |
| 1083 | 1129 | ||
| 1084 | # | 1130 | # |
| 1085 | # Multimedia drivers | 1131 | # Multimedia drivers |
| 1086 | # | 1132 | # |
| 1133 | # CONFIG_MEDIA_ATTACH is not set | ||
| 1134 | CONFIG_MEDIA_TUNER=m | ||
| 1135 | CONFIG_MEDIA_TUNER_CUSTOMIZE=y | ||
| 1136 | # CONFIG_MEDIA_TUNER_SIMPLE is not set | ||
| 1137 | # CONFIG_MEDIA_TUNER_TDA8290 is not set | ||
| 1138 | # CONFIG_MEDIA_TUNER_TDA827X is not set | ||
| 1139 | # CONFIG_MEDIA_TUNER_TDA18271 is not set | ||
| 1140 | # CONFIG_MEDIA_TUNER_TDA9887 is not set | ||
| 1141 | # CONFIG_MEDIA_TUNER_TEA5761 is not set | ||
| 1142 | # CONFIG_MEDIA_TUNER_TEA5767 is not set | ||
| 1143 | # CONFIG_MEDIA_TUNER_MT20XX is not set | ||
| 1144 | # CONFIG_MEDIA_TUNER_MT2060 is not set | ||
| 1145 | # CONFIG_MEDIA_TUNER_MT2266 is not set | ||
| 1146 | # CONFIG_MEDIA_TUNER_MT2131 is not set | ||
| 1147 | # CONFIG_MEDIA_TUNER_QT1010 is not set | ||
| 1148 | # CONFIG_MEDIA_TUNER_XC2028 is not set | ||
| 1149 | # CONFIG_MEDIA_TUNER_XC5000 is not set | ||
| 1150 | # CONFIG_MEDIA_TUNER_MXL5005S is not set | ||
| 1151 | # CONFIG_MEDIA_TUNER_MXL5007T is not set | ||
| 1152 | CONFIG_VIDEO_V4L2=m | ||
| 1153 | CONFIG_VIDEOBUF_GEN=m | ||
| 1154 | CONFIG_VIDEOBUF_DMA_SG=m | ||
| 1155 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1156 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1157 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1158 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set | ||
| 1159 | |||
| 1160 | # | ||
| 1161 | # Encoders/decoders and other helper chips | ||
| 1162 | # | ||
| 1163 | |||
| 1164 | # | ||
| 1165 | # Audio decoders | ||
| 1166 | # | ||
| 1167 | # CONFIG_VIDEO_TVAUDIO is not set | ||
| 1168 | # CONFIG_VIDEO_TDA7432 is not set | ||
| 1169 | # CONFIG_VIDEO_TDA9840 is not set | ||
| 1170 | # CONFIG_VIDEO_TDA9875 is not set | ||
| 1171 | # CONFIG_VIDEO_TEA6415C is not set | ||
| 1172 | # CONFIG_VIDEO_TEA6420 is not set | ||
| 1173 | # CONFIG_VIDEO_MSP3400 is not set | ||
| 1174 | # CONFIG_VIDEO_CS5345 is not set | ||
| 1175 | # CONFIG_VIDEO_CS53L32A is not set | ||
| 1176 | # CONFIG_VIDEO_M52790 is not set | ||
| 1177 | # CONFIG_VIDEO_TLV320AIC23B is not set | ||
| 1178 | # CONFIG_VIDEO_WM8775 is not set | ||
| 1179 | # CONFIG_VIDEO_WM8739 is not set | ||
| 1180 | # CONFIG_VIDEO_VP27SMPX is not set | ||
| 1181 | |||
| 1182 | # | ||
| 1183 | # Video decoders | ||
| 1184 | # | ||
| 1185 | # CONFIG_VIDEO_OV7670 is not set | ||
| 1186 | # CONFIG_VIDEO_TCM825X is not set | ||
| 1187 | # CONFIG_VIDEO_SAA711X is not set | ||
| 1188 | # CONFIG_VIDEO_SAA717X is not set | ||
| 1189 | # CONFIG_VIDEO_TVP514X is not set | ||
| 1190 | # CONFIG_VIDEO_TVP5150 is not set | ||
| 1191 | |||
| 1192 | # | ||
| 1193 | # Video and audio decoders | ||
| 1194 | # | ||
| 1195 | # CONFIG_VIDEO_CX25840 is not set | ||
| 1196 | |||
| 1197 | # | ||
| 1198 | # MPEG video encoders | ||
| 1199 | # | ||
| 1200 | # CONFIG_VIDEO_CX2341X is not set | ||
| 1201 | |||
| 1202 | # | ||
| 1203 | # Video encoders | ||
| 1204 | # | ||
| 1205 | # CONFIG_VIDEO_SAA7127 is not set | ||
| 1206 | |||
| 1207 | # | ||
| 1208 | # Video improvement chips | ||
| 1209 | # | ||
| 1210 | # CONFIG_VIDEO_UPD64031A is not set | ||
| 1211 | # CONFIG_VIDEO_UPD64083 is not set | ||
| 1212 | # CONFIG_VIDEO_VIVI is not set | ||
| 1213 | # CONFIG_VIDEO_BT848 is not set | ||
| 1214 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1215 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1216 | # CONFIG_VIDEO_SAA7134 is not set | ||
| 1217 | # CONFIG_VIDEO_HEXIUM_ORION is not set | ||
| 1218 | # CONFIG_VIDEO_HEXIUM_GEMINI is not set | ||
| 1219 | # CONFIG_VIDEO_CX88 is not set | ||
| 1220 | # CONFIG_VIDEO_IVTV is not set | ||
| 1221 | # CONFIG_VIDEO_CAFE_CCIC is not set | ||
| 1222 | CONFIG_SOC_CAMERA=m | ||
| 1223 | # CONFIG_SOC_CAMERA_MT9M001 is not set | ||
| 1224 | CONFIG_SOC_CAMERA_MT9M111=m | ||
| 1225 | # CONFIG_SOC_CAMERA_MT9T031 is not set | ||
| 1226 | # CONFIG_SOC_CAMERA_MT9V022 is not set | ||
| 1227 | # CONFIG_SOC_CAMERA_TW9910 is not set | ||
| 1228 | # CONFIG_SOC_CAMERA_PLATFORM is not set | ||
| 1229 | # CONFIG_SOC_CAMERA_OV772X is not set | ||
| 1230 | CONFIG_VIDEO_PXA27x=m | ||
| 1231 | # CONFIG_VIDEO_SH_MOBILE_CEU is not set | ||
| 1232 | # CONFIG_V4L_USB_DRIVERS is not set | ||
| 1233 | # CONFIG_RADIO_ADAPTERS is not set | ||
| 1087 | # CONFIG_DAB is not set | 1234 | # CONFIG_DAB is not set |
| 1088 | 1235 | ||
| 1089 | # | 1236 | # |
| @@ -1095,6 +1242,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1095 | CONFIG_FB=y | 1242 | CONFIG_FB=y |
| 1096 | # CONFIG_FIRMWARE_EDID is not set | 1243 | # CONFIG_FIRMWARE_EDID is not set |
| 1097 | # CONFIG_FB_DDC is not set | 1244 | # CONFIG_FB_DDC is not set |
| 1245 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1098 | CONFIG_FB_CFB_FILLRECT=y | 1246 | CONFIG_FB_CFB_FILLRECT=y |
| 1099 | CONFIG_FB_CFB_COPYAREA=y | 1247 | CONFIG_FB_CFB_COPYAREA=y |
| 1100 | CONFIG_FB_CFB_IMAGEBLIT=y | 1248 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -1128,6 +1276,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 1128 | # CONFIG_FB_S3 is not set | 1276 | # CONFIG_FB_S3 is not set |
| 1129 | # CONFIG_FB_SAVAGE is not set | 1277 | # CONFIG_FB_SAVAGE is not set |
| 1130 | # CONFIG_FB_SIS is not set | 1278 | # CONFIG_FB_SIS is not set |
| 1279 | # CONFIG_FB_VIA is not set | ||
| 1131 | # CONFIG_FB_NEOMAGIC is not set | 1280 | # CONFIG_FB_NEOMAGIC is not set |
| 1132 | # CONFIG_FB_KYRO is not set | 1281 | # CONFIG_FB_KYRO is not set |
| 1133 | # CONFIG_FB_3DFX is not set | 1282 | # CONFIG_FB_3DFX is not set |
| @@ -1138,13 +1287,17 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 1138 | # CONFIG_FB_PM3 is not set | 1287 | # CONFIG_FB_PM3 is not set |
| 1139 | # CONFIG_FB_CARMINE is not set | 1288 | # CONFIG_FB_CARMINE is not set |
| 1140 | CONFIG_FB_PXA=y | 1289 | CONFIG_FB_PXA=y |
| 1290 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 1141 | # CONFIG_FB_PXA_SMARTPANEL is not set | 1291 | # CONFIG_FB_PXA_SMARTPANEL is not set |
| 1142 | CONFIG_FB_PXA_PARAMETERS=y | 1292 | CONFIG_FB_PXA_PARAMETERS=y |
| 1143 | CONFIG_FB_MBX=m | 1293 | CONFIG_FB_MBX=m |
| 1144 | # CONFIG_FB_W100 is not set | 1294 | # CONFIG_FB_W100 is not set |
| 1145 | # CONFIG_FB_VIRTUAL is not set | 1295 | # CONFIG_FB_VIRTUAL is not set |
| 1146 | # CONFIG_FB_METRONOME is not set | 1296 | # CONFIG_FB_METRONOME is not set |
| 1147 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 1297 | # CONFIG_FB_MB862XX is not set |
| 1298 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 1299 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 1300 | # CONFIG_BACKLIGHT_CLASS_DEVICE is not set | ||
| 1148 | 1301 | ||
| 1149 | # | 1302 | # |
| 1150 | # Display device support | 1303 | # Display device support |
| @@ -1167,6 +1320,7 @@ CONFIG_LOGO_LINUX_MONO=y | |||
| 1167 | CONFIG_LOGO_LINUX_VGA16=y | 1320 | CONFIG_LOGO_LINUX_VGA16=y |
| 1168 | CONFIG_LOGO_LINUX_CLUT224=y | 1321 | CONFIG_LOGO_LINUX_CLUT224=y |
| 1169 | CONFIG_SOUND=m | 1322 | CONFIG_SOUND=m |
| 1323 | CONFIG_SOUND_OSS_CORE=y | ||
| 1170 | CONFIG_SND=m | 1324 | CONFIG_SND=m |
| 1171 | CONFIG_SND_TIMER=m | 1325 | CONFIG_SND_TIMER=m |
| 1172 | CONFIG_SND_PCM=m | 1326 | CONFIG_SND_PCM=m |
| @@ -1182,81 +1336,16 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 1182 | # CONFIG_SND_DEBUG is not set | 1336 | # CONFIG_SND_DEBUG is not set |
| 1183 | CONFIG_SND_VMASTER=y | 1337 | CONFIG_SND_VMASTER=y |
| 1184 | CONFIG_SND_AC97_CODEC=m | 1338 | CONFIG_SND_AC97_CODEC=m |
| 1185 | CONFIG_SND_DRIVERS=y | 1339 | # CONFIG_SND_DRIVERS is not set |
| 1186 | # CONFIG_SND_DUMMY is not set | 1340 | # CONFIG_SND_PCI is not set |
| 1187 | # CONFIG_SND_MTPAV is not set | ||
| 1188 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1189 | # CONFIG_SND_MPU401 is not set | ||
| 1190 | # CONFIG_SND_AC97_POWER_SAVE is not set | ||
| 1191 | CONFIG_SND_PCI=y | ||
| 1192 | # CONFIG_SND_AD1889 is not set | ||
| 1193 | # CONFIG_SND_ALS300 is not set | ||
| 1194 | # CONFIG_SND_ALI5451 is not set | ||
| 1195 | # CONFIG_SND_ATIIXP is not set | ||
| 1196 | # CONFIG_SND_ATIIXP_MODEM is not set | ||
| 1197 | # CONFIG_SND_AU8810 is not set | ||
| 1198 | # CONFIG_SND_AU8820 is not set | ||
| 1199 | # CONFIG_SND_AU8830 is not set | ||
| 1200 | # CONFIG_SND_AW2 is not set | ||
| 1201 | # CONFIG_SND_AZT3328 is not set | ||
| 1202 | # CONFIG_SND_BT87X is not set | ||
| 1203 | # CONFIG_SND_CA0106 is not set | ||
| 1204 | # CONFIG_SND_CMIPCI is not set | ||
| 1205 | # CONFIG_SND_OXYGEN is not set | ||
| 1206 | # CONFIG_SND_CS4281 is not set | ||
| 1207 | # CONFIG_SND_CS46XX is not set | ||
| 1208 | # CONFIG_SND_DARLA20 is not set | ||
| 1209 | # CONFIG_SND_GINA20 is not set | ||
| 1210 | # CONFIG_SND_LAYLA20 is not set | ||
| 1211 | # CONFIG_SND_DARLA24 is not set | ||
| 1212 | # CONFIG_SND_GINA24 is not set | ||
| 1213 | # CONFIG_SND_LAYLA24 is not set | ||
| 1214 | # CONFIG_SND_MONA is not set | ||
| 1215 | # CONFIG_SND_MIA is not set | ||
| 1216 | # CONFIG_SND_ECHO3G is not set | ||
| 1217 | # CONFIG_SND_INDIGO is not set | ||
| 1218 | # CONFIG_SND_INDIGOIO is not set | ||
| 1219 | # CONFIG_SND_INDIGODJ is not set | ||
| 1220 | # CONFIG_SND_EMU10K1 is not set | ||
| 1221 | # CONFIG_SND_EMU10K1X is not set | ||
| 1222 | # CONFIG_SND_ENS1370 is not set | ||
| 1223 | # CONFIG_SND_ENS1371 is not set | ||
| 1224 | # CONFIG_SND_ES1938 is not set | ||
| 1225 | # CONFIG_SND_ES1968 is not set | ||
| 1226 | # CONFIG_SND_FM801 is not set | ||
| 1227 | # CONFIG_SND_HDA_INTEL is not set | ||
| 1228 | # CONFIG_SND_HDSP is not set | ||
| 1229 | # CONFIG_SND_HDSPM is not set | ||
| 1230 | # CONFIG_SND_HIFIER is not set | ||
| 1231 | # CONFIG_SND_ICE1712 is not set | ||
| 1232 | # CONFIG_SND_ICE1724 is not set | ||
| 1233 | # CONFIG_SND_INTEL8X0 is not set | ||
| 1234 | # CONFIG_SND_INTEL8X0M is not set | ||
| 1235 | # CONFIG_SND_KORG1212 is not set | ||
| 1236 | # CONFIG_SND_MAESTRO3 is not set | ||
| 1237 | # CONFIG_SND_MIXART is not set | ||
| 1238 | # CONFIG_SND_NM256 is not set | ||
| 1239 | # CONFIG_SND_PCXHR is not set | ||
| 1240 | # CONFIG_SND_RIPTIDE is not set | ||
| 1241 | # CONFIG_SND_RME32 is not set | ||
| 1242 | # CONFIG_SND_RME96 is not set | ||
| 1243 | # CONFIG_SND_RME9652 is not set | ||
| 1244 | # CONFIG_SND_SONICVIBES is not set | ||
| 1245 | # CONFIG_SND_TRIDENT is not set | ||
| 1246 | # CONFIG_SND_VIA82XX is not set | ||
| 1247 | # CONFIG_SND_VIA82XX_MODEM is not set | ||
| 1248 | # CONFIG_SND_VIRTUOSO is not set | ||
| 1249 | # CONFIG_SND_VX222 is not set | ||
| 1250 | # CONFIG_SND_YMFPCI is not set | ||
| 1251 | CONFIG_SND_ARM=y | 1341 | CONFIG_SND_ARM=y |
| 1252 | CONFIG_SND_PXA2XX_PCM=m | 1342 | CONFIG_SND_PXA2XX_PCM=m |
| 1343 | CONFIG_SND_PXA2XX_LIB=m | ||
| 1344 | CONFIG_SND_PXA2XX_LIB_AC97=y | ||
| 1253 | CONFIG_SND_PXA2XX_AC97=m | 1345 | CONFIG_SND_PXA2XX_AC97=m |
| 1254 | CONFIG_SND_USB=y | 1346 | # CONFIG_SND_SPI is not set |
| 1255 | # CONFIG_SND_USB_AUDIO is not set | 1347 | # CONFIG_SND_USB is not set |
| 1256 | # CONFIG_SND_USB_CAIAQ is not set | 1348 | # CONFIG_SND_PCMCIA is not set |
| 1257 | CONFIG_SND_PCMCIA=y | ||
| 1258 | # CONFIG_SND_VXPOCKET is not set | ||
| 1259 | # CONFIG_SND_PDAUDIOCF is not set | ||
| 1260 | # CONFIG_SND_SOC is not set | 1349 | # CONFIG_SND_SOC is not set |
| 1261 | # CONFIG_SOUND_PRIME is not set | 1350 | # CONFIG_SOUND_PRIME is not set |
| 1262 | CONFIG_AC97_BUS=m | 1351 | CONFIG_AC97_BUS=m |
| @@ -1269,9 +1358,37 @@ CONFIG_HID_DEBUG=y | |||
| 1269 | # USB Input Devices | 1358 | # USB Input Devices |
| 1270 | # | 1359 | # |
| 1271 | CONFIG_USB_HID=y | 1360 | CONFIG_USB_HID=y |
| 1272 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 1361 | # CONFIG_HID_PID is not set |
| 1273 | # CONFIG_HID_FF is not set | ||
| 1274 | # CONFIG_USB_HIDDEV is not set | 1362 | # CONFIG_USB_HIDDEV is not set |
| 1363 | |||
| 1364 | # | ||
| 1365 | # Special HID drivers | ||
| 1366 | # | ||
| 1367 | CONFIG_HID_COMPAT=y | ||
| 1368 | CONFIG_HID_A4TECH=y | ||
| 1369 | CONFIG_HID_APPLE=y | ||
| 1370 | CONFIG_HID_BELKIN=y | ||
| 1371 | CONFIG_HID_CHERRY=y | ||
| 1372 | CONFIG_HID_CHICONY=y | ||
| 1373 | CONFIG_HID_CYPRESS=y | ||
| 1374 | CONFIG_HID_EZKEY=y | ||
| 1375 | CONFIG_HID_GYRATION=y | ||
| 1376 | CONFIG_HID_LOGITECH=y | ||
| 1377 | # CONFIG_LOGITECH_FF is not set | ||
| 1378 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1379 | CONFIG_HID_MICROSOFT=y | ||
| 1380 | CONFIG_HID_MONTEREY=y | ||
| 1381 | # CONFIG_HID_NTRIG is not set | ||
| 1382 | CONFIG_HID_PANTHERLORD=y | ||
| 1383 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1384 | CONFIG_HID_PETALYNX=y | ||
| 1385 | CONFIG_HID_SAMSUNG=y | ||
| 1386 | CONFIG_HID_SONY=y | ||
| 1387 | CONFIG_HID_SUNPLUS=y | ||
| 1388 | # CONFIG_GREENASIA_FF is not set | ||
| 1389 | # CONFIG_HID_TOPSEED is not set | ||
| 1390 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1391 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1275 | CONFIG_USB_SUPPORT=y | 1392 | CONFIG_USB_SUPPORT=y |
| 1276 | CONFIG_USB_ARCH_HAS_HCD=y | 1393 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1277 | CONFIG_USB_ARCH_HAS_OHCI=y | 1394 | CONFIG_USB_ARCH_HAS_OHCI=y |
| @@ -1291,12 +1408,15 @@ CONFIG_USB_DEVICEFS=y | |||
| 1291 | # CONFIG_USB_OTG_WHITELIST is not set | 1408 | # CONFIG_USB_OTG_WHITELIST is not set |
| 1292 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | 1409 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set |
| 1293 | CONFIG_USB_MON=y | 1410 | CONFIG_USB_MON=y |
| 1411 | # CONFIG_USB_WUSB is not set | ||
| 1412 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1294 | 1413 | ||
| 1295 | # | 1414 | # |
| 1296 | # USB Host Controller Drivers | 1415 | # USB Host Controller Drivers |
| 1297 | # | 1416 | # |
| 1298 | # CONFIG_USB_C67X00_HCD is not set | 1417 | # CONFIG_USB_C67X00_HCD is not set |
| 1299 | # CONFIG_USB_EHCI_HCD is not set | 1418 | # CONFIG_USB_EHCI_HCD is not set |
| 1419 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1300 | # CONFIG_USB_ISP116X_HCD is not set | 1420 | # CONFIG_USB_ISP116X_HCD is not set |
| 1301 | # CONFIG_USB_ISP1760_HCD is not set | 1421 | # CONFIG_USB_ISP1760_HCD is not set |
| 1302 | CONFIG_USB_OHCI_HCD=y | 1422 | CONFIG_USB_OHCI_HCD=y |
| @@ -1306,6 +1426,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1306 | # CONFIG_USB_UHCI_HCD is not set | 1426 | # CONFIG_USB_UHCI_HCD is not set |
| 1307 | # CONFIG_USB_SL811_HCD is not set | 1427 | # CONFIG_USB_SL811_HCD is not set |
| 1308 | # CONFIG_USB_R8A66597_HCD is not set | 1428 | # CONFIG_USB_R8A66597_HCD is not set |
| 1429 | # CONFIG_USB_WHCI_HCD is not set | ||
| 1430 | # CONFIG_USB_HWA_HCD is not set | ||
| 1309 | # CONFIG_USB_MUSB_HDRC is not set | 1431 | # CONFIG_USB_MUSB_HDRC is not set |
| 1310 | 1432 | ||
| 1311 | # | 1433 | # |
| @@ -1314,20 +1436,20 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1314 | # CONFIG_USB_ACM is not set | 1436 | # CONFIG_USB_ACM is not set |
| 1315 | # CONFIG_USB_PRINTER is not set | 1437 | # CONFIG_USB_PRINTER is not set |
| 1316 | # CONFIG_USB_WDM is not set | 1438 | # CONFIG_USB_WDM is not set |
| 1439 | # CONFIG_USB_TMC is not set | ||
| 1317 | 1440 | ||
| 1318 | # | 1441 | # |
| 1319 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1442 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 1320 | # | 1443 | # |
| 1321 | 1444 | ||
| 1322 | # | 1445 | # |
| 1323 | # may also be needed; see USB_STORAGE Help for more information | 1446 | # see USB_STORAGE Help for more information |
| 1324 | # | 1447 | # |
| 1325 | CONFIG_USB_STORAGE=y | 1448 | CONFIG_USB_STORAGE=y |
| 1326 | # CONFIG_USB_STORAGE_DEBUG is not set | 1449 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 1327 | # CONFIG_USB_STORAGE_DATAFAB is not set | 1450 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 1328 | # CONFIG_USB_STORAGE_FREECOM is not set | 1451 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 1329 | # CONFIG_USB_STORAGE_ISD200 is not set | 1452 | # CONFIG_USB_STORAGE_ISD200 is not set |
| 1330 | # CONFIG_USB_STORAGE_DPCM is not set | ||
| 1331 | # CONFIG_USB_STORAGE_USBAT is not set | 1453 | # CONFIG_USB_STORAGE_USBAT is not set |
| 1332 | # CONFIG_USB_STORAGE_SDDR09 is not set | 1454 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| 1333 | # CONFIG_USB_STORAGE_SDDR55 is not set | 1455 | # CONFIG_USB_STORAGE_SDDR55 is not set |
| @@ -1355,6 +1477,7 @@ CONFIG_USB_STORAGE=y | |||
| 1355 | # CONFIG_USB_EMI62 is not set | 1477 | # CONFIG_USB_EMI62 is not set |
| 1356 | # CONFIG_USB_EMI26 is not set | 1478 | # CONFIG_USB_EMI26 is not set |
| 1357 | # CONFIG_USB_ADUTUX is not set | 1479 | # CONFIG_USB_ADUTUX is not set |
| 1480 | # CONFIG_USB_SEVSEG is not set | ||
| 1358 | # CONFIG_USB_RIO500 is not set | 1481 | # CONFIG_USB_RIO500 is not set |
| 1359 | # CONFIG_USB_LEGOTOWER is not set | 1482 | # CONFIG_USB_LEGOTOWER is not set |
| 1360 | # CONFIG_USB_LCD is not set | 1483 | # CONFIG_USB_LCD is not set |
| @@ -1371,13 +1494,20 @@ CONFIG_USB_STORAGE=y | |||
| 1371 | # CONFIG_USB_IOWARRIOR is not set | 1494 | # CONFIG_USB_IOWARRIOR is not set |
| 1372 | # CONFIG_USB_TEST is not set | 1495 | # CONFIG_USB_TEST is not set |
| 1373 | # CONFIG_USB_ISIGHTFW is not set | 1496 | # CONFIG_USB_ISIGHTFW is not set |
| 1497 | # CONFIG_USB_VST is not set | ||
| 1374 | # CONFIG_USB_GADGET is not set | 1498 | # CONFIG_USB_GADGET is not set |
| 1499 | |||
| 1500 | # | ||
| 1501 | # OTG and related infrastructure | ||
| 1502 | # | ||
| 1503 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1504 | # CONFIG_UWB is not set | ||
| 1375 | CONFIG_MMC=m | 1505 | CONFIG_MMC=m |
| 1376 | # CONFIG_MMC_DEBUG is not set | 1506 | # CONFIG_MMC_DEBUG is not set |
| 1377 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1507 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 1378 | 1508 | ||
| 1379 | # | 1509 | # |
| 1380 | # MMC/SD Card Drivers | 1510 | # MMC/SD/SDIO Card Drivers |
| 1381 | # | 1511 | # |
| 1382 | CONFIG_MMC_BLOCK=m | 1512 | CONFIG_MMC_BLOCK=m |
| 1383 | CONFIG_MMC_BLOCK_BOUNCE=y | 1513 | CONFIG_MMC_BLOCK_BOUNCE=y |
| @@ -1385,11 +1515,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y | |||
| 1385 | # CONFIG_MMC_TEST is not set | 1515 | # CONFIG_MMC_TEST is not set |
| 1386 | 1516 | ||
| 1387 | # | 1517 | # |
| 1388 | # MMC/SD Host Controller Drivers | 1518 | # MMC/SD/SDIO Host Controller Drivers |
| 1389 | # | 1519 | # |
| 1390 | CONFIG_MMC_PXA=m | 1520 | CONFIG_MMC_PXA=m |
| 1391 | # CONFIG_MMC_SDHCI is not set | 1521 | # CONFIG_MMC_SDHCI is not set |
| 1392 | # CONFIG_MMC_TIFM_SD is not set | 1522 | # CONFIG_MMC_TIFM_SD is not set |
| 1523 | # CONFIG_MMC_SPI is not set | ||
| 1393 | # CONFIG_MMC_SDRICOH_CS is not set | 1524 | # CONFIG_MMC_SDRICOH_CS is not set |
| 1394 | # CONFIG_MEMSTICK is not set | 1525 | # CONFIG_MEMSTICK is not set |
| 1395 | # CONFIG_ACCESSIBILITY is not set | 1526 | # CONFIG_ACCESSIBILITY is not set |
| @@ -1400,8 +1531,7 @@ CONFIG_LEDS_CLASS=y | |||
| 1400 | # LED drivers | 1531 | # LED drivers |
| 1401 | # | 1532 | # |
| 1402 | # CONFIG_LEDS_PCA9532 is not set | 1533 | # CONFIG_LEDS_PCA9532 is not set |
| 1403 | # CONFIG_LEDS_GPIO is not set | 1534 | CONFIG_LEDS_GPIO=m |
| 1404 | CONFIG_LEDS_CM_X270=y | ||
| 1405 | # CONFIG_LEDS_PCA955X is not set | 1535 | # CONFIG_LEDS_PCA955X is not set |
| 1406 | 1536 | ||
| 1407 | # | 1537 | # |
| @@ -1410,6 +1540,7 @@ CONFIG_LEDS_CM_X270=y | |||
| 1410 | CONFIG_LEDS_TRIGGERS=y | 1540 | CONFIG_LEDS_TRIGGERS=y |
| 1411 | # CONFIG_LEDS_TRIGGER_TIMER is not set | 1541 | # CONFIG_LEDS_TRIGGER_TIMER is not set |
| 1412 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 1542 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 1543 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1413 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | 1544 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set |
| 1414 | CONFIG_RTC_LIB=y | 1545 | CONFIG_RTC_LIB=y |
| 1415 | CONFIG_RTC_CLASS=y | 1546 | CONFIG_RTC_CLASS=y |
| @@ -1441,37 +1572,43 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1441 | # CONFIG_RTC_DRV_M41T80 is not set | 1572 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1442 | # CONFIG_RTC_DRV_S35390A is not set | 1573 | # CONFIG_RTC_DRV_S35390A is not set |
| 1443 | # CONFIG_RTC_DRV_FM3130 is not set | 1574 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1575 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1444 | 1576 | ||
| 1445 | # | 1577 | # |
| 1446 | # SPI RTC drivers | 1578 | # SPI RTC drivers |
| 1447 | # | 1579 | # |
| 1580 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1581 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1582 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1583 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1584 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1585 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1586 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1448 | 1587 | ||
| 1449 | # | 1588 | # |
| 1450 | # Platform RTC drivers | 1589 | # Platform RTC drivers |
| 1451 | # | 1590 | # |
| 1452 | # CONFIG_RTC_DRV_CMOS is not set | 1591 | # CONFIG_RTC_DRV_CMOS is not set |
| 1592 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1453 | # CONFIG_RTC_DRV_DS1511 is not set | 1593 | # CONFIG_RTC_DRV_DS1511 is not set |
| 1454 | # CONFIG_RTC_DRV_DS1553 is not set | 1594 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1455 | # CONFIG_RTC_DRV_DS1742 is not set | 1595 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1456 | # CONFIG_RTC_DRV_STK17TA8 is not set | 1596 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 1457 | # CONFIG_RTC_DRV_M48T86 is not set | 1597 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1598 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1458 | # CONFIG_RTC_DRV_M48T59 is not set | 1599 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1600 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1459 | CONFIG_RTC_DRV_V3020=y | 1601 | CONFIG_RTC_DRV_V3020=y |
| 1460 | 1602 | ||
| 1461 | # | 1603 | # |
| 1462 | # on-CPU RTC drivers | 1604 | # on-CPU RTC drivers |
| 1463 | # | 1605 | # |
| 1464 | CONFIG_RTC_DRV_SA1100=y | 1606 | CONFIG_RTC_DRV_SA1100=y |
| 1607 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1465 | # CONFIG_DMADEVICES is not set | 1608 | # CONFIG_DMADEVICES is not set |
| 1466 | |||
| 1467 | # | ||
| 1468 | # Voltage and Current regulators | ||
| 1469 | # | ||
| 1470 | # CONFIG_REGULATOR is not set | 1609 | # CONFIG_REGULATOR is not set |
| 1471 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 1472 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 1473 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 1474 | # CONFIG_UIO is not set | 1610 | # CONFIG_UIO is not set |
| 1611 | # CONFIG_STAGING is not set | ||
| 1475 | 1612 | ||
| 1476 | # | 1613 | # |
| 1477 | # File systems | 1614 | # File systems |
| @@ -1483,14 +1620,16 @@ CONFIG_EXT3_FS=y | |||
| 1483 | CONFIG_EXT3_FS_XATTR=y | 1620 | CONFIG_EXT3_FS_XATTR=y |
| 1484 | # CONFIG_EXT3_FS_POSIX_ACL is not set | 1621 | # CONFIG_EXT3_FS_POSIX_ACL is not set |
| 1485 | # CONFIG_EXT3_FS_SECURITY is not set | 1622 | # CONFIG_EXT3_FS_SECURITY is not set |
| 1486 | # CONFIG_EXT4DEV_FS is not set | 1623 | # CONFIG_EXT4_FS is not set |
| 1487 | CONFIG_JBD=y | 1624 | CONFIG_JBD=y |
| 1488 | CONFIG_FS_MBCACHE=y | 1625 | CONFIG_FS_MBCACHE=y |
| 1489 | # CONFIG_REISERFS_FS is not set | 1626 | # CONFIG_REISERFS_FS is not set |
| 1490 | # CONFIG_JFS_FS is not set | 1627 | # CONFIG_JFS_FS is not set |
| 1491 | # CONFIG_FS_POSIX_ACL is not set | 1628 | # CONFIG_FS_POSIX_ACL is not set |
| 1629 | CONFIG_FILE_LOCKING=y | ||
| 1492 | # CONFIG_XFS_FS is not set | 1630 | # CONFIG_XFS_FS is not set |
| 1493 | # CONFIG_OCFS2_FS is not set | 1631 | # CONFIG_OCFS2_FS is not set |
| 1632 | # CONFIG_BTRFS_FS is not set | ||
| 1494 | CONFIG_DNOTIFY=y | 1633 | CONFIG_DNOTIFY=y |
| 1495 | CONFIG_INOTIFY=y | 1634 | CONFIG_INOTIFY=y |
| 1496 | CONFIG_INOTIFY_USER=y | 1635 | CONFIG_INOTIFY_USER=y |
| @@ -1520,15 +1659,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 1520 | # | 1659 | # |
| 1521 | CONFIG_PROC_FS=y | 1660 | CONFIG_PROC_FS=y |
| 1522 | CONFIG_PROC_SYSCTL=y | 1661 | CONFIG_PROC_SYSCTL=y |
| 1662 | # CONFIG_PROC_PAGE_MONITOR is not set | ||
| 1523 | CONFIG_SYSFS=y | 1663 | CONFIG_SYSFS=y |
| 1524 | CONFIG_TMPFS=y | 1664 | CONFIG_TMPFS=y |
| 1525 | # CONFIG_TMPFS_POSIX_ACL is not set | 1665 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1526 | # CONFIG_HUGETLB_PAGE is not set | 1666 | # CONFIG_HUGETLB_PAGE is not set |
| 1527 | # CONFIG_CONFIGFS_FS is not set | 1667 | # CONFIG_CONFIGFS_FS is not set |
| 1528 | 1668 | CONFIG_MISC_FILESYSTEMS=y | |
| 1529 | # | ||
| 1530 | # Miscellaneous filesystems | ||
| 1531 | # | ||
| 1532 | # CONFIG_ADFS_FS is not set | 1669 | # CONFIG_ADFS_FS is not set |
| 1533 | # CONFIG_AFFS_FS is not set | 1670 | # CONFIG_AFFS_FS is not set |
| 1534 | # CONFIG_HFS_FS is not set | 1671 | # CONFIG_HFS_FS is not set |
| @@ -1548,6 +1685,7 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1548 | CONFIG_JFFS2_RTIME=y | 1685 | CONFIG_JFFS2_RTIME=y |
| 1549 | # CONFIG_JFFS2_RUBIN is not set | 1686 | # CONFIG_JFFS2_RUBIN is not set |
| 1550 | # CONFIG_CRAMFS is not set | 1687 | # CONFIG_CRAMFS is not set |
| 1688 | # CONFIG_SQUASHFS is not set | ||
| 1551 | # CONFIG_VXFS_FS is not set | 1689 | # CONFIG_VXFS_FS is not set |
| 1552 | # CONFIG_MINIX_FS is not set | 1690 | # CONFIG_MINIX_FS is not set |
| 1553 | # CONFIG_OMFS_FS is not set | 1691 | # CONFIG_OMFS_FS is not set |
| @@ -1567,6 +1705,7 @@ CONFIG_LOCKD=y | |||
| 1567 | CONFIG_LOCKD_V4=y | 1705 | CONFIG_LOCKD_V4=y |
| 1568 | CONFIG_NFS_COMMON=y | 1706 | CONFIG_NFS_COMMON=y |
| 1569 | CONFIG_SUNRPC=y | 1707 | CONFIG_SUNRPC=y |
| 1708 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1570 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1709 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1571 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1710 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1572 | # CONFIG_SMB_FS is not set | 1711 | # CONFIG_SMB_FS is not set |
| @@ -1678,19 +1817,29 @@ CONFIG_DEBUG_KERNEL=y | |||
| 1678 | # CONFIG_DEBUG_MEMORY_INIT is not set | 1817 | # CONFIG_DEBUG_MEMORY_INIT is not set |
| 1679 | # CONFIG_DEBUG_LIST is not set | 1818 | # CONFIG_DEBUG_LIST is not set |
| 1680 | # CONFIG_DEBUG_SG is not set | 1819 | # CONFIG_DEBUG_SG is not set |
| 1820 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1681 | CONFIG_FRAME_POINTER=y | 1821 | CONFIG_FRAME_POINTER=y |
| 1682 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1822 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1683 | # CONFIG_RCU_TORTURE_TEST is not set | 1823 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1824 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1684 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1825 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1826 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1685 | # CONFIG_FAULT_INJECTION is not set | 1827 | # CONFIG_FAULT_INJECTION is not set |
| 1686 | # CONFIG_LATENCYTOP is not set | 1828 | # CONFIG_LATENCYTOP is not set |
| 1687 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 1829 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 1688 | CONFIG_HAVE_FTRACE=y | 1830 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1689 | CONFIG_HAVE_DYNAMIC_FTRACE=y | 1831 | |
| 1690 | # CONFIG_FTRACE is not set | 1832 | # |
| 1833 | # Tracers | ||
| 1834 | # | ||
| 1835 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1691 | # CONFIG_IRQSOFF_TRACER is not set | 1836 | # CONFIG_IRQSOFF_TRACER is not set |
| 1692 | # CONFIG_SCHED_TRACER is not set | 1837 | # CONFIG_SCHED_TRACER is not set |
| 1693 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 1838 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 1839 | # CONFIG_BOOT_TRACER is not set | ||
| 1840 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1841 | # CONFIG_STACK_TRACER is not set | ||
| 1842 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1694 | # CONFIG_SAMPLES is not set | 1843 | # CONFIG_SAMPLES is not set |
| 1695 | CONFIG_HAVE_ARCH_KGDB=y | 1844 | CONFIG_HAVE_ARCH_KGDB=y |
| 1696 | # CONFIG_KGDB is not set | 1845 | # CONFIG_KGDB is not set |
| @@ -1705,13 +1854,16 @@ CONFIG_DEBUG_LL=y | |||
| 1705 | # | 1854 | # |
| 1706 | # CONFIG_KEYS is not set | 1855 | # CONFIG_KEYS is not set |
| 1707 | # CONFIG_SECURITY is not set | 1856 | # CONFIG_SECURITY is not set |
| 1857 | # CONFIG_SECURITYFS is not set | ||
| 1708 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1858 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1709 | CONFIG_CRYPTO=y | 1859 | CONFIG_CRYPTO=y |
| 1710 | 1860 | ||
| 1711 | # | 1861 | # |
| 1712 | # Crypto core or helper | 1862 | # Crypto core or helper |
| 1713 | # | 1863 | # |
| 1864 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1714 | # CONFIG_CRYPTO_MANAGER is not set | 1865 | # CONFIG_CRYPTO_MANAGER is not set |
| 1866 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 1715 | # CONFIG_CRYPTO_GF128MUL is not set | 1867 | # CONFIG_CRYPTO_GF128MUL is not set |
| 1716 | # CONFIG_CRYPTO_NULL is not set | 1868 | # CONFIG_CRYPTO_NULL is not set |
| 1717 | # CONFIG_CRYPTO_CRYPTD is not set | 1869 | # CONFIG_CRYPTO_CRYPTD is not set |
| @@ -1783,14 +1935,18 @@ CONFIG_CRYPTO=y | |||
| 1783 | # | 1935 | # |
| 1784 | # CONFIG_CRYPTO_DEFLATE is not set | 1936 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1785 | # CONFIG_CRYPTO_LZO is not set | 1937 | # CONFIG_CRYPTO_LZO is not set |
| 1938 | |||
| 1939 | # | ||
| 1940 | # Random Number Generation | ||
| 1941 | # | ||
| 1942 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1786 | # CONFIG_CRYPTO_HW is not set | 1943 | # CONFIG_CRYPTO_HW is not set |
| 1787 | 1944 | ||
| 1788 | # | 1945 | # |
| 1789 | # Library routines | 1946 | # Library routines |
| 1790 | # | 1947 | # |
| 1791 | CONFIG_BITREVERSE=y | 1948 | CONFIG_BITREVERSE=y |
| 1792 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | 1949 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 1793 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
| 1794 | CONFIG_CRC_CCITT=m | 1950 | CONFIG_CRC_CCITT=m |
| 1795 | # CONFIG_CRC16 is not set | 1951 | # CONFIG_CRC16 is not set |
| 1796 | # CONFIG_CRC_T10DIF is not set | 1952 | # CONFIG_CRC_T10DIF is not set |
diff --git a/arch/arm/configs/colibri_defconfig b/arch/arm/configs/colibri_pxa270_defconfig index 744086fff414..4cf3bde1c522 100644 --- a/arch/arm/configs/colibri_defconfig +++ b/arch/arm/configs/colibri_pxa270_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24-rc3 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Mon Dec 3 13:36:09 2007 | 4 | # Fri Mar 13 16:18:17 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| @@ -12,6 +12,7 @@ CONFIG_MMU=y | |||
| 12 | # CONFIG_NO_IOPORT is not set | 12 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 14 | CONFIG_STACKTRACE_SUPPORT=y |
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | 16 | CONFIG_LOCKDEP_SUPPORT=y |
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | 18 | CONFIG_HARDIRQS_SW_RESEND=y |
| @@ -21,8 +22,8 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 22 | CONFIG_GENERIC_HWEIGHT=y | 23 | CONFIG_GENERIC_HWEIGHT=y |
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | 25 | CONFIG_ARCH_MTD_XIP=y |
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | 27 | CONFIG_VECTORS_BASE=0xffff0000 |
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 28 | 29 | ||
| @@ -42,22 +43,30 @@ CONFIG_POSIX_MQUEUE=y | |||
| 42 | CONFIG_BSD_PROCESS_ACCT=y | 43 | CONFIG_BSD_PROCESS_ACCT=y |
| 43 | CONFIG_BSD_PROCESS_ACCT_V3=y | 44 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 44 | # CONFIG_TASKSTATS is not set | 45 | # CONFIG_TASKSTATS is not set |
| 45 | # CONFIG_USER_NS is not set | ||
| 46 | # CONFIG_PID_NS is not set | ||
| 47 | # CONFIG_AUDIT is not set | 46 | # CONFIG_AUDIT is not set |
| 47 | |||
| 48 | # | ||
| 49 | # RCU Subsystem | ||
| 50 | # | ||
| 51 | CONFIG_CLASSIC_RCU=y | ||
| 52 | # CONFIG_TREE_RCU is not set | ||
| 53 | # CONFIG_PREEMPT_RCU is not set | ||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 55 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 48 | CONFIG_IKCONFIG=y | 56 | CONFIG_IKCONFIG=y |
| 49 | CONFIG_IKCONFIG_PROC=y | 57 | CONFIG_IKCONFIG_PROC=y |
| 50 | CONFIG_LOG_BUF_SHIFT=14 | 58 | CONFIG_LOG_BUF_SHIFT=14 |
| 59 | # CONFIG_GROUP_SCHED is not set | ||
| 51 | # CONFIG_CGROUPS is not set | 60 | # CONFIG_CGROUPS is not set |
| 52 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 53 | CONFIG_FAIR_USER_SCHED=y | ||
| 54 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 55 | CONFIG_SYSFS_DEPRECATED=y | 61 | CONFIG_SYSFS_DEPRECATED=y |
| 62 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 56 | # CONFIG_RELAY is not set | 63 | # CONFIG_RELAY is not set |
| 64 | # CONFIG_NAMESPACES is not set | ||
| 57 | CONFIG_BLK_DEV_INITRD=y | 65 | CONFIG_BLK_DEV_INITRD=y |
| 58 | CONFIG_INITRAMFS_SOURCE="" | 66 | CONFIG_INITRAMFS_SOURCE="" |
| 59 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 67 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 60 | CONFIG_SYSCTL=y | 68 | CONFIG_SYSCTL=y |
| 69 | CONFIG_ANON_INODES=y | ||
| 61 | CONFIG_EMBEDDED=y | 70 | CONFIG_EMBEDDED=y |
| 62 | CONFIG_UID16=y | 71 | CONFIG_UID16=y |
| 63 | CONFIG_SYSCTL_SYSCALL=y | 72 | CONFIG_SYSCTL_SYSCALL=y |
| @@ -70,29 +79,38 @@ CONFIG_BUG=y | |||
| 70 | CONFIG_ELF_CORE=y | 79 | CONFIG_ELF_CORE=y |
| 71 | CONFIG_BASE_FULL=y | 80 | CONFIG_BASE_FULL=y |
| 72 | CONFIG_FUTEX=y | 81 | CONFIG_FUTEX=y |
| 73 | CONFIG_ANON_INODES=y | ||
| 74 | CONFIG_EPOLL=y | 82 | CONFIG_EPOLL=y |
| 75 | CONFIG_SIGNALFD=y | 83 | CONFIG_SIGNALFD=y |
| 84 | CONFIG_TIMERFD=y | ||
| 76 | CONFIG_EVENTFD=y | 85 | CONFIG_EVENTFD=y |
| 77 | CONFIG_SHMEM=y | 86 | CONFIG_SHMEM=y |
| 87 | CONFIG_AIO=y | ||
| 78 | CONFIG_VM_EVENT_COUNTERS=y | 88 | CONFIG_VM_EVENT_COUNTERS=y |
| 89 | CONFIG_COMPAT_BRK=y | ||
| 79 | CONFIG_SLAB=y | 90 | CONFIG_SLAB=y |
| 80 | # CONFIG_SLUB is not set | 91 | # CONFIG_SLUB is not set |
| 81 | # CONFIG_SLOB is not set | 92 | # CONFIG_SLOB is not set |
| 93 | # CONFIG_PROFILING is not set | ||
| 94 | CONFIG_HAVE_OPROFILE=y | ||
| 95 | # CONFIG_KPROBES is not set | ||
| 96 | CONFIG_HAVE_KPROBES=y | ||
| 97 | CONFIG_HAVE_KRETPROBES=y | ||
| 98 | CONFIG_HAVE_CLK=y | ||
| 99 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 100 | CONFIG_SLABINFO=y | ||
| 82 | CONFIG_RT_MUTEXES=y | 101 | CONFIG_RT_MUTEXES=y |
| 83 | # CONFIG_TINY_SHMEM is not set | ||
| 84 | CONFIG_BASE_SMALL=0 | 102 | CONFIG_BASE_SMALL=0 |
| 85 | CONFIG_MODULES=y | 103 | CONFIG_MODULES=y |
| 104 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 86 | CONFIG_MODULE_UNLOAD=y | 105 | CONFIG_MODULE_UNLOAD=y |
| 87 | CONFIG_MODULE_FORCE_UNLOAD=y | 106 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 88 | CONFIG_MODVERSIONS=y | 107 | CONFIG_MODVERSIONS=y |
| 89 | CONFIG_MODULE_SRCVERSION_ALL=y | 108 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 90 | CONFIG_KMOD=y | ||
| 91 | CONFIG_BLOCK=y | 109 | CONFIG_BLOCK=y |
| 92 | CONFIG_LBD=y | 110 | CONFIG_LBD=y |
| 93 | # CONFIG_BLK_DEV_IO_TRACE is not set | 111 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 94 | CONFIG_LSF=y | ||
| 95 | # CONFIG_BLK_DEV_BSG is not set | 112 | # CONFIG_BLK_DEV_BSG is not set |
| 113 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 96 | 114 | ||
| 97 | # | 115 | # |
| 98 | # IO Schedulers | 116 | # IO Schedulers |
| @@ -106,6 +124,7 @@ CONFIG_DEFAULT_AS=y | |||
| 106 | # CONFIG_DEFAULT_CFQ is not set | 124 | # CONFIG_DEFAULT_CFQ is not set |
| 107 | # CONFIG_DEFAULT_NOOP is not set | 125 | # CONFIG_DEFAULT_NOOP is not set |
| 108 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 126 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 127 | CONFIG_FREEZER=y | ||
| 109 | 128 | ||
| 110 | # | 129 | # |
| 111 | # System Type | 130 | # System Type |
| @@ -115,9 +134,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
| 115 | # CONFIG_ARCH_REALVIEW is not set | 134 | # CONFIG_ARCH_REALVIEW is not set |
| 116 | # CONFIG_ARCH_VERSATILE is not set | 135 | # CONFIG_ARCH_VERSATILE is not set |
| 117 | # CONFIG_ARCH_AT91 is not set | 136 | # CONFIG_ARCH_AT91 is not set |
| 118 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 119 | # CONFIG_ARCH_CLPS711X is not set | 137 | # CONFIG_ARCH_CLPS711X is not set |
| 120 | # CONFIG_ARCH_CO285 is not set | ||
| 121 | # CONFIG_ARCH_EBSA110 is not set | 138 | # CONFIG_ARCH_EBSA110 is not set |
| 122 | # CONFIG_ARCH_EP93XX is not set | 139 | # CONFIG_ARCH_EP93XX is not set |
| 123 | # CONFIG_ARCH_FOOTBRIDGE is not set | 140 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| @@ -131,41 +148,58 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
| 131 | # CONFIG_ARCH_IXP2000 is not set | 148 | # CONFIG_ARCH_IXP2000 is not set |
| 132 | # CONFIG_ARCH_IXP4XX is not set | 149 | # CONFIG_ARCH_IXP4XX is not set |
| 133 | # CONFIG_ARCH_L7200 is not set | 150 | # CONFIG_ARCH_L7200 is not set |
| 151 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 134 | # CONFIG_ARCH_KS8695 is not set | 152 | # CONFIG_ARCH_KS8695 is not set |
| 135 | # CONFIG_ARCH_NS9XXX is not set | 153 | # CONFIG_ARCH_NS9XXX is not set |
| 154 | # CONFIG_ARCH_LOKI is not set | ||
| 155 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 136 | # CONFIG_ARCH_MXC is not set | 156 | # CONFIG_ARCH_MXC is not set |
| 157 | # CONFIG_ARCH_ORION5X is not set | ||
| 137 | # CONFIG_ARCH_PNX4008 is not set | 158 | # CONFIG_ARCH_PNX4008 is not set |
| 138 | CONFIG_ARCH_PXA=y | 159 | CONFIG_ARCH_PXA=y |
| 139 | # CONFIG_ARCH_RPC is not set | 160 | # CONFIG_ARCH_RPC is not set |
| 140 | # CONFIG_ARCH_SA1100 is not set | 161 | # CONFIG_ARCH_SA1100 is not set |
| 141 | # CONFIG_ARCH_S3C2410 is not set | 162 | # CONFIG_ARCH_S3C2410 is not set |
| 163 | # CONFIG_ARCH_S3C64XX is not set | ||
| 142 | # CONFIG_ARCH_SHARK is not set | 164 | # CONFIG_ARCH_SHARK is not set |
| 143 | # CONFIG_ARCH_LH7A40X is not set | 165 | # CONFIG_ARCH_LH7A40X is not set |
| 144 | # CONFIG_ARCH_DAVINCI is not set | 166 | # CONFIG_ARCH_DAVINCI is not set |
| 145 | # CONFIG_ARCH_OMAP is not set | 167 | # CONFIG_ARCH_OMAP is not set |
| 168 | # CONFIG_ARCH_MSM is not set | ||
| 169 | # CONFIG_ARCH_W90X900 is not set | ||
| 146 | 170 | ||
| 147 | # | 171 | # |
| 148 | # Intel PXA2xx/PXA3xx Implementations | 172 | # Intel PXA2xx/PXA3xx Implementations |
| 149 | # | 173 | # |
| 174 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 175 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 150 | # CONFIG_ARCH_LUBBOCK is not set | 176 | # CONFIG_ARCH_LUBBOCK is not set |
| 151 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 177 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 152 | # CONFIG_MACH_MAINSTONE is not set | 178 | # CONFIG_MACH_MAINSTONE is not set |
| 179 | # CONFIG_MACH_MP900C is not set | ||
| 153 | # CONFIG_ARCH_PXA_IDP is not set | 180 | # CONFIG_ARCH_PXA_IDP is not set |
| 154 | # CONFIG_PXA_SHARPSL is not set | 181 | # CONFIG_PXA_SHARPSL is not set |
| 155 | # CONFIG_MACH_TRIZEPS4 is not set | 182 | # CONFIG_ARCH_VIPER is not set |
| 183 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 184 | # CONFIG_TRIZEPS_PXA is not set | ||
| 185 | # CONFIG_MACH_H5000 is not set | ||
| 156 | # CONFIG_MACH_EM_X270 is not set | 186 | # CONFIG_MACH_EM_X270 is not set |
| 157 | CONFIG_MACH_COLIBRI=y | 187 | CONFIG_MACH_COLIBRI=y |
| 188 | # CONFIG_MACH_COLIBRI300 is not set | ||
| 158 | # CONFIG_MACH_ZYLONITE is not set | 189 | # CONFIG_MACH_ZYLONITE is not set |
| 190 | # CONFIG_MACH_LITTLETON is not set | ||
| 191 | # CONFIG_MACH_RAUMFELD_PROTO is not set | ||
| 192 | # CONFIG_MACH_TAVOREVB is not set | ||
| 193 | # CONFIG_MACH_SAAR is not set | ||
| 159 | # CONFIG_MACH_ARMCORE is not set | 194 | # CONFIG_MACH_ARMCORE is not set |
| 195 | # CONFIG_MACH_CM_X300 is not set | ||
| 196 | # CONFIG_MACH_MAGICIAN is not set | ||
| 197 | # CONFIG_MACH_MIOA701 is not set | ||
| 198 | # CONFIG_MACH_PCM027 is not set | ||
| 199 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 200 | # CONFIG_PXA_EZX is not set | ||
| 160 | CONFIG_PXA27x=y | 201 | CONFIG_PXA27x=y |
| 161 | 202 | # CONFIG_PXA_PWM is not set | |
| 162 | # | ||
| 163 | # Boot options | ||
| 164 | # | ||
| 165 | |||
| 166 | # | ||
| 167 | # Power management | ||
| 168 | # | ||
| 169 | 203 | ||
| 170 | # | 204 | # |
| 171 | # Processor Type | 205 | # Processor Type |
| @@ -174,6 +208,7 @@ CONFIG_CPU_32=y | |||
| 174 | CONFIG_CPU_XSCALE=y | 208 | CONFIG_CPU_XSCALE=y |
| 175 | CONFIG_CPU_32v5=y | 209 | CONFIG_CPU_32v5=y |
| 176 | CONFIG_CPU_ABRT_EV5T=y | 210 | CONFIG_CPU_ABRT_EV5T=y |
| 211 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 177 | CONFIG_CPU_CACHE_VIVT=y | 212 | CONFIG_CPU_CACHE_VIVT=y |
| 178 | CONFIG_CPU_TLB_V4WBI=y | 213 | CONFIG_CPU_TLB_V4WBI=y |
| 179 | CONFIG_CPU_CP15=y | 214 | CONFIG_CPU_CP15=y |
| @@ -187,6 +222,7 @@ CONFIG_ARM_THUMB=y | |||
| 187 | # CONFIG_OUTER_CACHE is not set | 222 | # CONFIG_OUTER_CACHE is not set |
| 188 | CONFIG_IWMMXT=y | 223 | CONFIG_IWMMXT=y |
| 189 | CONFIG_XSCALE_PMU=y | 224 | CONFIG_XSCALE_PMU=y |
| 225 | CONFIG_COMMON_CLKDEV=y | ||
| 190 | 226 | ||
| 191 | # | 227 | # |
| 192 | # Bus support | 228 | # Bus support |
| @@ -198,28 +234,33 @@ CONFIG_XSCALE_PMU=y | |||
| 198 | # | 234 | # |
| 199 | # Kernel Features | 235 | # Kernel Features |
| 200 | # | 236 | # |
| 201 | # CONFIG_TICK_ONESHOT is not set | 237 | CONFIG_TICK_ONESHOT=y |
| 202 | # CONFIG_NO_HZ is not set | 238 | # CONFIG_NO_HZ is not set |
| 203 | # CONFIG_HIGH_RES_TIMERS is not set | 239 | # CONFIG_HIGH_RES_TIMERS is not set |
| 204 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 240 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 241 | CONFIG_VMSPLIT_3G=y | ||
| 242 | # CONFIG_VMSPLIT_2G is not set | ||
| 243 | # CONFIG_VMSPLIT_1G is not set | ||
| 244 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 205 | CONFIG_PREEMPT=y | 245 | CONFIG_PREEMPT=y |
| 206 | CONFIG_HZ=100 | 246 | CONFIG_HZ=100 |
| 207 | CONFIG_AEABI=y | 247 | CONFIG_AEABI=y |
| 208 | CONFIG_OABI_COMPAT=y | 248 | CONFIG_OABI_COMPAT=y |
| 209 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | 249 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y |
| 250 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 251 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 210 | CONFIG_SELECT_MEMORY_MODEL=y | 252 | CONFIG_SELECT_MEMORY_MODEL=y |
| 211 | CONFIG_FLATMEM_MANUAL=y | 253 | CONFIG_FLATMEM_MANUAL=y |
| 212 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 254 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 213 | # CONFIG_SPARSEMEM_MANUAL is not set | 255 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 214 | CONFIG_FLATMEM=y | 256 | CONFIG_FLATMEM=y |
| 215 | CONFIG_FLAT_NODE_MEM_MAP=y | 257 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 216 | # CONFIG_SPARSEMEM_STATIC is not set | 258 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 217 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 218 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 259 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 219 | # CONFIG_RESOURCES_64BIT is not set | 260 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 220 | CONFIG_ZONE_DMA_FLAG=1 | 261 | CONFIG_ZONE_DMA_FLAG=0 |
| 221 | CONFIG_BOUNCE=y | ||
| 222 | CONFIG_VIRT_TO_BUS=y | 262 | CONFIG_VIRT_TO_BUS=y |
| 263 | CONFIG_UNEVICTABLE_LRU=y | ||
| 223 | CONFIG_ALIGNMENT_TRAP=y | 264 | CONFIG_ALIGNMENT_TRAP=y |
| 224 | 265 | ||
| 225 | # | 266 | # |
| @@ -232,6 +273,12 @@ CONFIG_CMDLINE="" | |||
| 232 | # CONFIG_KEXEC is not set | 273 | # CONFIG_KEXEC is not set |
| 233 | 274 | ||
| 234 | # | 275 | # |
| 276 | # CPU Power Management | ||
| 277 | # | ||
| 278 | # CONFIG_CPU_FREQ is not set | ||
| 279 | # CONFIG_CPU_IDLE is not set | ||
| 280 | |||
| 281 | # | ||
| 235 | # Floating point emulation | 282 | # Floating point emulation |
| 236 | # | 283 | # |
| 237 | 284 | ||
| @@ -246,6 +293,8 @@ CONFIG_FPE_NWFPE=y | |||
| 246 | # Userspace binary formats | 293 | # Userspace binary formats |
| 247 | # | 294 | # |
| 248 | CONFIG_BINFMT_ELF=y | 295 | CONFIG_BINFMT_ELF=y |
| 296 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 297 | CONFIG_HAVE_AOUT=y | ||
| 249 | # CONFIG_BINFMT_AOUT is not set | 298 | # CONFIG_BINFMT_AOUT is not set |
| 250 | # CONFIG_BINFMT_MISC is not set | 299 | # CONFIG_BINFMT_MISC is not set |
| 251 | 300 | ||
| @@ -253,21 +302,18 @@ CONFIG_BINFMT_ELF=y | |||
| 253 | # Power management options | 302 | # Power management options |
| 254 | # | 303 | # |
| 255 | CONFIG_PM=y | 304 | CONFIG_PM=y |
| 256 | # CONFIG_PM_LEGACY is not set | ||
| 257 | # CONFIG_PM_DEBUG is not set | 305 | # CONFIG_PM_DEBUG is not set |
| 258 | CONFIG_PM_SLEEP=y | 306 | CONFIG_PM_SLEEP=y |
| 259 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 260 | CONFIG_SUSPEND=y | 307 | CONFIG_SUSPEND=y |
| 308 | CONFIG_SUSPEND_FREEZER=y | ||
| 261 | # CONFIG_APM_EMULATION is not set | 309 | # CONFIG_APM_EMULATION is not set |
| 262 | 310 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | |
| 263 | # | ||
| 264 | # Networking | ||
| 265 | # | ||
| 266 | CONFIG_NET=y | 311 | CONFIG_NET=y |
| 267 | 312 | ||
| 268 | # | 313 | # |
| 269 | # Networking options | 314 | # Networking options |
| 270 | # | 315 | # |
| 316 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 271 | CONFIG_PACKET=y | 317 | CONFIG_PACKET=y |
| 272 | CONFIG_PACKET_MMAP=y | 318 | CONFIG_PACKET_MMAP=y |
| 273 | CONFIG_UNIX=y | 319 | CONFIG_UNIX=y |
| @@ -275,6 +321,7 @@ CONFIG_XFRM=y | |||
| 275 | CONFIG_XFRM_USER=m | 321 | CONFIG_XFRM_USER=m |
| 276 | # CONFIG_XFRM_SUB_POLICY is not set | 322 | # CONFIG_XFRM_SUB_POLICY is not set |
| 277 | # CONFIG_XFRM_MIGRATE is not set | 323 | # CONFIG_XFRM_MIGRATE is not set |
| 324 | # CONFIG_XFRM_STATISTICS is not set | ||
| 278 | CONFIG_NET_KEY=y | 325 | CONFIG_NET_KEY=y |
| 279 | # CONFIG_NET_KEY_MIGRATE is not set | 326 | # CONFIG_NET_KEY_MIGRATE is not set |
| 280 | CONFIG_INET=y | 327 | CONFIG_INET=y |
| @@ -304,26 +351,26 @@ CONFIG_INET_TCP_DIAG=y | |||
| 304 | CONFIG_TCP_CONG_CUBIC=y | 351 | CONFIG_TCP_CONG_CUBIC=y |
| 305 | CONFIG_DEFAULT_TCP_CONG="cubic" | 352 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 306 | # CONFIG_TCP_MD5SIG is not set | 353 | # CONFIG_TCP_MD5SIG is not set |
| 307 | # CONFIG_IP_VS is not set | ||
| 308 | # CONFIG_IPV6 is not set | 354 | # CONFIG_IPV6 is not set |
| 309 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 310 | # CONFIG_INET6_TUNNEL is not set | ||
| 311 | # CONFIG_NETLABEL is not set | 355 | # CONFIG_NETLABEL is not set |
| 312 | # CONFIG_NETWORK_SECMARK is not set | 356 | # CONFIG_NETWORK_SECMARK is not set |
| 313 | CONFIG_NETFILTER=y | 357 | CONFIG_NETFILTER=y |
| 314 | # CONFIG_NETFILTER_DEBUG is not set | 358 | # CONFIG_NETFILTER_DEBUG is not set |
| 359 | CONFIG_NETFILTER_ADVANCED=y | ||
| 315 | 360 | ||
| 316 | # | 361 | # |
| 317 | # Core Netfilter Configuration | 362 | # Core Netfilter Configuration |
| 318 | # | 363 | # |
| 319 | # CONFIG_NETFILTER_NETLINK is not set | 364 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set |
| 320 | # CONFIG_NF_CONNTRACK_ENABLED is not set | 365 | # CONFIG_NETFILTER_NETLINK_LOG is not set |
| 321 | # CONFIG_NF_CONNTRACK is not set | 366 | # CONFIG_NF_CONNTRACK is not set |
| 322 | # CONFIG_NETFILTER_XTABLES is not set | 367 | # CONFIG_NETFILTER_XTABLES is not set |
| 368 | # CONFIG_IP_VS is not set | ||
| 323 | 369 | ||
| 324 | # | 370 | # |
| 325 | # IP: Netfilter Configuration | 371 | # IP: Netfilter Configuration |
| 326 | # | 372 | # |
| 373 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 327 | CONFIG_IP_NF_QUEUE=m | 374 | CONFIG_IP_NF_QUEUE=m |
| 328 | # CONFIG_IP_NF_IPTABLES is not set | 375 | # CONFIG_IP_NF_IPTABLES is not set |
| 329 | # CONFIG_IP_NF_ARPTABLES is not set | 376 | # CONFIG_IP_NF_ARPTABLES is not set |
| @@ -332,7 +379,9 @@ CONFIG_IP_NF_QUEUE=m | |||
| 332 | # CONFIG_TIPC is not set | 379 | # CONFIG_TIPC is not set |
| 333 | # CONFIG_ATM is not set | 380 | # CONFIG_ATM is not set |
| 334 | # CONFIG_BRIDGE is not set | 381 | # CONFIG_BRIDGE is not set |
| 382 | # CONFIG_NET_DSA is not set | ||
| 335 | CONFIG_VLAN_8021Q=m | 383 | CONFIG_VLAN_8021Q=m |
| 384 | # CONFIG_VLAN_8021Q_GVRP is not set | ||
| 336 | # CONFIG_DECNET is not set | 385 | # CONFIG_DECNET is not set |
| 337 | # CONFIG_LLC2 is not set | 386 | # CONFIG_LLC2 is not set |
| 338 | # CONFIG_IPX is not set | 387 | # CONFIG_IPX is not set |
| @@ -342,12 +391,14 @@ CONFIG_VLAN_8021Q=m | |||
| 342 | # CONFIG_ECONET is not set | 391 | # CONFIG_ECONET is not set |
| 343 | # CONFIG_WAN_ROUTER is not set | 392 | # CONFIG_WAN_ROUTER is not set |
| 344 | # CONFIG_NET_SCHED is not set | 393 | # CONFIG_NET_SCHED is not set |
| 394 | # CONFIG_DCB is not set | ||
| 345 | 395 | ||
| 346 | # | 396 | # |
| 347 | # Network testing | 397 | # Network testing |
| 348 | # | 398 | # |
| 349 | # CONFIG_NET_PKTGEN is not set | 399 | # CONFIG_NET_PKTGEN is not set |
| 350 | # CONFIG_HAMRADIO is not set | 400 | # CONFIG_HAMRADIO is not set |
| 401 | # CONFIG_CAN is not set | ||
| 351 | CONFIG_IRDA=m | 402 | CONFIG_IRDA=m |
| 352 | 403 | ||
| 353 | # | 404 | # |
| @@ -382,15 +433,6 @@ CONFIG_IRTTY_SIR=m | |||
| 382 | # CONFIG_KS959_DONGLE is not set | 433 | # CONFIG_KS959_DONGLE is not set |
| 383 | 434 | ||
| 384 | # | 435 | # |
| 385 | # Old SIR device drivers | ||
| 386 | # | ||
| 387 | # CONFIG_IRPORT_SIR is not set | ||
| 388 | |||
| 389 | # | ||
| 390 | # Old Serial dongle support | ||
| 391 | # | ||
| 392 | |||
| 393 | # | ||
| 394 | # FIR device drivers | 436 | # FIR device drivers |
| 395 | # | 437 | # |
| 396 | # CONFIG_USB_IRDA is not set | 438 | # CONFIG_USB_IRDA is not set |
| @@ -410,7 +452,6 @@ CONFIG_BT_HIDP=m | |||
| 410 | # | 452 | # |
| 411 | # Bluetooth device drivers | 453 | # Bluetooth device drivers |
| 412 | # | 454 | # |
| 413 | # CONFIG_BT_HCIUSB is not set | ||
| 414 | # CONFIG_BT_HCIBTUSB is not set | 455 | # CONFIG_BT_HCIBTUSB is not set |
| 415 | # CONFIG_BT_HCIBTSDIO is not set | 456 | # CONFIG_BT_HCIBTSDIO is not set |
| 416 | # CONFIG_BT_HCIUART is not set | 457 | # CONFIG_BT_HCIUART is not set |
| @@ -419,21 +460,20 @@ CONFIG_BT_HIDP=m | |||
| 419 | # CONFIG_BT_HCIBFUSB is not set | 460 | # CONFIG_BT_HCIBFUSB is not set |
| 420 | # CONFIG_BT_HCIVHCI is not set | 461 | # CONFIG_BT_HCIVHCI is not set |
| 421 | # CONFIG_AF_RXRPC is not set | 462 | # CONFIG_AF_RXRPC is not set |
| 422 | 463 | # CONFIG_PHONET is not set | |
| 423 | # | 464 | CONFIG_WIRELESS=y |
| 424 | # Wireless | ||
| 425 | # | ||
| 426 | CONFIG_CFG80211=y | 465 | CONFIG_CFG80211=y |
| 466 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 427 | CONFIG_NL80211=y | 467 | CONFIG_NL80211=y |
| 468 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 428 | CONFIG_WIRELESS_EXT=y | 469 | CONFIG_WIRELESS_EXT=y |
| 470 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 471 | CONFIG_LIB80211=y | ||
| 472 | CONFIG_LIB80211_CRYPT_WEP=y | ||
| 473 | CONFIG_LIB80211_CRYPT_CCMP=y | ||
| 474 | CONFIG_LIB80211_CRYPT_TKIP=y | ||
| 429 | # CONFIG_MAC80211 is not set | 475 | # CONFIG_MAC80211 is not set |
| 430 | CONFIG_IEEE80211=y | 476 | # CONFIG_WIMAX is not set |
| 431 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 432 | CONFIG_IEEE80211_CRYPT_WEP=y | ||
| 433 | CONFIG_IEEE80211_CRYPT_CCMP=m | ||
| 434 | CONFIG_IEEE80211_CRYPT_TKIP=m | ||
| 435 | CONFIG_IEEE80211_SOFTMAC=m | ||
| 436 | # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set | ||
| 437 | # CONFIG_RFKILL is not set | 477 | # CONFIG_RFKILL is not set |
| 438 | # CONFIG_NET_9P is not set | 478 | # CONFIG_NET_9P is not set |
| 439 | 479 | ||
| @@ -448,6 +488,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 448 | CONFIG_STANDALONE=y | 488 | CONFIG_STANDALONE=y |
| 449 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 489 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 450 | CONFIG_FW_LOADER=y | 490 | CONFIG_FW_LOADER=y |
| 491 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 492 | CONFIG_EXTRA_FIRMWARE="" | ||
| 451 | # CONFIG_DEBUG_DRIVER is not set | 493 | # CONFIG_DEBUG_DRIVER is not set |
| 452 | # CONFIG_DEBUG_DEVRES is not set | 494 | # CONFIG_DEBUG_DEVRES is not set |
| 453 | # CONFIG_SYS_HYPERVISOR is not set | 495 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -457,9 +499,11 @@ CONFIG_MTD=y | |||
| 457 | # CONFIG_MTD_DEBUG is not set | 499 | # CONFIG_MTD_DEBUG is not set |
| 458 | CONFIG_MTD_CONCAT=y | 500 | CONFIG_MTD_CONCAT=y |
| 459 | CONFIG_MTD_PARTITIONS=y | 501 | CONFIG_MTD_PARTITIONS=y |
| 502 | # CONFIG_MTD_TESTS is not set | ||
| 460 | # CONFIG_MTD_REDBOOT_PARTS is not set | 503 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 461 | # CONFIG_MTD_CMDLINE_PARTS is not set | 504 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 462 | # CONFIG_MTD_AFS_PARTS is not set | 505 | # CONFIG_MTD_AFS_PARTS is not set |
| 506 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 463 | 507 | ||
| 464 | # | 508 | # |
| 465 | # User Modules And Translation Layers | 509 | # User Modules And Translation Layers |
| @@ -510,9 +554,7 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 510 | # | 554 | # |
| 511 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 555 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 512 | CONFIG_MTD_PHYSMAP=y | 556 | CONFIG_MTD_PHYSMAP=y |
| 513 | CONFIG_MTD_PHYSMAP_START=0x0 | 557 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 514 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 515 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 516 | CONFIG_MTD_PXA2XX=y | 558 | CONFIG_MTD_PXA2XX=y |
| 517 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 559 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 518 | # CONFIG_MTD_IMPA7 is not set | 560 | # CONFIG_MTD_IMPA7 is not set |
| @@ -538,6 +580,7 @@ CONFIG_MTD_NAND=y | |||
| 538 | # CONFIG_MTD_NAND_ECC_SMC is not set | 580 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 539 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | 581 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set |
| 540 | # CONFIG_MTD_NAND_H1900 is not set | 582 | # CONFIG_MTD_NAND_H1900 is not set |
| 583 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 541 | CONFIG_MTD_NAND_IDS=y | 584 | CONFIG_MTD_NAND_IDS=y |
| 542 | CONFIG_MTD_NAND_DISKONCHIP=y | 585 | CONFIG_MTD_NAND_DISKONCHIP=y |
| 543 | CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y | 586 | CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y |
| @@ -556,6 +599,11 @@ CONFIG_MTD_ONENAND=y | |||
| 556 | # CONFIG_MTD_ONENAND_SIM is not set | 599 | # CONFIG_MTD_ONENAND_SIM is not set |
| 557 | 600 | ||
| 558 | # | 601 | # |
| 602 | # LPDDR flash memory drivers | ||
| 603 | # | ||
| 604 | # CONFIG_MTD_LPDDR is not set | ||
| 605 | |||
| 606 | # | ||
| 559 | # UBI - Unsorted block images | 607 | # UBI - Unsorted block images |
| 560 | # | 608 | # |
| 561 | # CONFIG_MTD_UBI is not set | 609 | # CONFIG_MTD_UBI is not set |
| @@ -569,36 +617,41 @@ CONFIG_BLK_DEV_NBD=y | |||
| 569 | CONFIG_BLK_DEV_RAM=y | 617 | CONFIG_BLK_DEV_RAM=y |
| 570 | CONFIG_BLK_DEV_RAM_COUNT=8 | 618 | CONFIG_BLK_DEV_RAM_COUNT=8 |
| 571 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 619 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 572 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 620 | # CONFIG_BLK_DEV_XIP is not set |
| 573 | # CONFIG_CDROM_PKTCDVD is not set | 621 | # CONFIG_CDROM_PKTCDVD is not set |
| 574 | # CONFIG_ATA_OVER_ETH is not set | 622 | # CONFIG_ATA_OVER_ETH is not set |
| 575 | CONFIG_MISC_DEVICES=y | 623 | CONFIG_MISC_DEVICES=y |
| 624 | # CONFIG_ICS932S401 is not set | ||
| 625 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 626 | # CONFIG_ISL29003 is not set | ||
| 627 | # CONFIG_C2PORT is not set | ||
| 628 | |||
| 629 | # | ||
| 630 | # EEPROM support | ||
| 631 | # | ||
| 632 | # CONFIG_EEPROM_AT24 is not set | ||
| 633 | # CONFIG_EEPROM_LEGACY is not set | ||
| 576 | # CONFIG_EEPROM_93CX6 is not set | 634 | # CONFIG_EEPROM_93CX6 is not set |
| 635 | CONFIG_HAVE_IDE=y | ||
| 577 | CONFIG_IDE=y | 636 | CONFIG_IDE=y |
| 578 | CONFIG_IDE_MAX_HWIFS=4 | ||
| 579 | CONFIG_BLK_DEV_IDE=y | ||
| 580 | 637 | ||
| 581 | # | 638 | # |
| 582 | # Please see Documentation/ide.txt for help/info on IDE drives | 639 | # Please see Documentation/ide/ide.txt for help/info on IDE drives |
| 583 | # | 640 | # |
| 584 | # CONFIG_BLK_DEV_IDE_SATA is not set | 641 | # CONFIG_BLK_DEV_IDE_SATA is not set |
| 585 | CONFIG_BLK_DEV_IDEDISK=y | 642 | CONFIG_IDE_GD=y |
| 586 | CONFIG_IDEDISK_MULTI_MODE=y | 643 | CONFIG_IDE_GD_ATA=y |
| 644 | # CONFIG_IDE_GD_ATAPI is not set | ||
| 587 | # CONFIG_BLK_DEV_IDECD is not set | 645 | # CONFIG_BLK_DEV_IDECD is not set |
| 588 | # CONFIG_BLK_DEV_IDETAPE is not set | 646 | # CONFIG_BLK_DEV_IDETAPE is not set |
| 589 | # CONFIG_BLK_DEV_IDEFLOPPY is not set | ||
| 590 | # CONFIG_IDE_TASK_IOCTL is not set | 647 | # CONFIG_IDE_TASK_IOCTL is not set |
| 591 | CONFIG_IDE_PROC_FS=y | 648 | CONFIG_IDE_PROC_FS=y |
| 592 | 649 | ||
| 593 | # | 650 | # |
| 594 | # IDE chipset support/bugfixes | 651 | # IDE chipset support/bugfixes |
| 595 | # | 652 | # |
| 596 | CONFIG_IDE_GENERIC=y | ||
| 597 | # CONFIG_BLK_DEV_PLATFORM is not set | 653 | # CONFIG_BLK_DEV_PLATFORM is not set |
| 598 | # CONFIG_IDE_ARM is not set | ||
| 599 | # CONFIG_BLK_DEV_IDEDMA is not set | 654 | # CONFIG_BLK_DEV_IDEDMA is not set |
| 600 | CONFIG_IDE_ARCH_OBSOLETE_INIT=y | ||
| 601 | # CONFIG_BLK_DEV_HD is not set | ||
| 602 | 655 | ||
| 603 | # | 656 | # |
| 604 | # SCSI device support | 657 | # SCSI device support |
| @@ -610,7 +663,6 @@ CONFIG_IDE_ARCH_OBSOLETE_INIT=y | |||
| 610 | # CONFIG_ATA is not set | 663 | # CONFIG_ATA is not set |
| 611 | # CONFIG_MD is not set | 664 | # CONFIG_MD is not set |
| 612 | CONFIG_NETDEVICES=y | 665 | CONFIG_NETDEVICES=y |
| 613 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 614 | # CONFIG_DUMMY is not set | 666 | # CONFIG_DUMMY is not set |
| 615 | # CONFIG_BONDING is not set | 667 | # CONFIG_BONDING is not set |
| 616 | # CONFIG_MACVLAN is not set | 668 | # CONFIG_MACVLAN is not set |
| @@ -631,6 +683,10 @@ CONFIG_PHYLIB=y | |||
| 631 | # CONFIG_SMSC_PHY is not set | 683 | # CONFIG_SMSC_PHY is not set |
| 632 | # CONFIG_BROADCOM_PHY is not set | 684 | # CONFIG_BROADCOM_PHY is not set |
| 633 | # CONFIG_ICPLUS_PHY is not set | 685 | # CONFIG_ICPLUS_PHY is not set |
| 686 | # CONFIG_REALTEK_PHY is not set | ||
| 687 | # CONFIG_NATIONAL_PHY is not set | ||
| 688 | # CONFIG_STE10XP is not set | ||
| 689 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 634 | # CONFIG_FIXED_PHY is not set | 690 | # CONFIG_FIXED_PHY is not set |
| 635 | # CONFIG_MDIO_BITBANG is not set | 691 | # CONFIG_MDIO_BITBANG is not set |
| 636 | CONFIG_NET_ETHERNET=y | 692 | CONFIG_NET_ETHERNET=y |
| @@ -638,11 +694,17 @@ CONFIG_MII=y | |||
| 638 | # CONFIG_AX88796 is not set | 694 | # CONFIG_AX88796 is not set |
| 639 | # CONFIG_SMC91X is not set | 695 | # CONFIG_SMC91X is not set |
| 640 | CONFIG_DM9000=y | 696 | CONFIG_DM9000=y |
| 697 | CONFIG_DM9000_DEBUGLEVEL=4 | ||
| 698 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | ||
| 641 | # CONFIG_SMC911X is not set | 699 | # CONFIG_SMC911X is not set |
| 700 | # CONFIG_SMSC911X is not set | ||
| 642 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 701 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 643 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 702 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 644 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 703 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 645 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 704 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 705 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 706 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 707 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 646 | # CONFIG_B44 is not set | 708 | # CONFIG_B44 is not set |
| 647 | # CONFIG_NETDEV_1000 is not set | 709 | # CONFIG_NETDEV_1000 is not set |
| 648 | # CONFIG_NETDEV_10000 is not set | 710 | # CONFIG_NETDEV_10000 is not set |
| @@ -654,10 +716,15 @@ CONFIG_DM9000=y | |||
| 654 | CONFIG_WLAN_80211=y | 716 | CONFIG_WLAN_80211=y |
| 655 | # CONFIG_LIBERTAS is not set | 717 | # CONFIG_LIBERTAS is not set |
| 656 | # CONFIG_USB_ZD1201 is not set | 718 | # CONFIG_USB_ZD1201 is not set |
| 719 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 720 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 657 | CONFIG_HOSTAP=y | 721 | CONFIG_HOSTAP=y |
| 658 | CONFIG_HOSTAP_FIRMWARE=y | 722 | CONFIG_HOSTAP_FIRMWARE=y |
| 659 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | 723 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y |
| 660 | # CONFIG_ZD1211RW is not set | 724 | |
| 725 | # | ||
| 726 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 727 | # | ||
| 661 | 728 | ||
| 662 | # | 729 | # |
| 663 | # USB Network Adapters | 730 | # USB Network Adapters |
| @@ -670,7 +737,6 @@ CONFIG_HOSTAP_FIRMWARE_NVRAM=y | |||
| 670 | # CONFIG_WAN is not set | 737 | # CONFIG_WAN is not set |
| 671 | # CONFIG_PPP is not set | 738 | # CONFIG_PPP is not set |
| 672 | # CONFIG_SLIP is not set | 739 | # CONFIG_SLIP is not set |
| 673 | # CONFIG_SHAPER is not set | ||
| 674 | # CONFIG_NETCONSOLE is not set | 740 | # CONFIG_NETCONSOLE is not set |
| 675 | # CONFIG_NETPOLL is not set | 741 | # CONFIG_NETPOLL is not set |
| 676 | # CONFIG_NET_POLL_CONTROLLER is not set | 742 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -710,6 +776,7 @@ CONFIG_INPUT_MOUSE=y | |||
| 710 | # CONFIG_MOUSE_PS2 is not set | 776 | # CONFIG_MOUSE_PS2 is not set |
| 711 | CONFIG_MOUSE_SERIAL=m | 777 | CONFIG_MOUSE_SERIAL=m |
| 712 | # CONFIG_MOUSE_APPLETOUCH is not set | 778 | # CONFIG_MOUSE_APPLETOUCH is not set |
| 779 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 713 | # CONFIG_MOUSE_VSXXXAA is not set | 780 | # CONFIG_MOUSE_VSXXXAA is not set |
| 714 | # CONFIG_MOUSE_GPIO is not set | 781 | # CONFIG_MOUSE_GPIO is not set |
| 715 | # CONFIG_INPUT_JOYSTICK is not set | 782 | # CONFIG_INPUT_JOYSTICK is not set |
| @@ -718,20 +785,25 @@ CONFIG_INPUT_TOUCHSCREEN=y | |||
| 718 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 785 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 719 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 786 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 720 | # CONFIG_TOUCHSCREEN_ELO is not set | 787 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 788 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 721 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 789 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 790 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 722 | # CONFIG_TOUCHSCREEN_MK712 is not set | 791 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 723 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 792 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 724 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 793 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 725 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 794 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 726 | CONFIG_TOUCHSCREEN_UCB1400=y | ||
| 727 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 795 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 796 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 797 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 728 | CONFIG_INPUT_MISC=y | 798 | CONFIG_INPUT_MISC=y |
| 729 | # CONFIG_INPUT_ATI_REMOTE is not set | 799 | # CONFIG_INPUT_ATI_REMOTE is not set |
| 730 | # CONFIG_INPUT_ATI_REMOTE2 is not set | 800 | # CONFIG_INPUT_ATI_REMOTE2 is not set |
| 731 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | 801 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set |
| 732 | # CONFIG_INPUT_POWERMATE is not set | 802 | # CONFIG_INPUT_POWERMATE is not set |
| 733 | # CONFIG_INPUT_YEALINK is not set | 803 | # CONFIG_INPUT_YEALINK is not set |
| 804 | # CONFIG_INPUT_CM109 is not set | ||
| 734 | CONFIG_INPUT_UINPUT=m | 805 | CONFIG_INPUT_UINPUT=m |
| 806 | # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set | ||
| 735 | 807 | ||
| 736 | # | 808 | # |
| 737 | # Hardware I/O ports | 809 | # Hardware I/O ports |
| @@ -746,9 +818,11 @@ CONFIG_SERIO_LIBPS2=y | |||
| 746 | # Character devices | 818 | # Character devices |
| 747 | # | 819 | # |
| 748 | CONFIG_VT=y | 820 | CONFIG_VT=y |
| 821 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 749 | CONFIG_VT_CONSOLE=y | 822 | CONFIG_VT_CONSOLE=y |
| 750 | CONFIG_HW_CONSOLE=y | 823 | CONFIG_HW_CONSOLE=y |
| 751 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 824 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 825 | CONFIG_DEVKMEM=y | ||
| 752 | # CONFIG_SERIAL_NONSTANDARD is not set | 826 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 753 | 827 | ||
| 754 | # | 828 | # |
| @@ -764,45 +838,50 @@ CONFIG_SERIAL_PXA_CONSOLE=y | |||
| 764 | CONFIG_SERIAL_CORE=y | 838 | CONFIG_SERIAL_CORE=y |
| 765 | CONFIG_SERIAL_CORE_CONSOLE=y | 839 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 766 | CONFIG_UNIX98_PTYS=y | 840 | CONFIG_UNIX98_PTYS=y |
| 841 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 767 | CONFIG_LEGACY_PTYS=y | 842 | CONFIG_LEGACY_PTYS=y |
| 768 | CONFIG_LEGACY_PTY_COUNT=256 | 843 | CONFIG_LEGACY_PTY_COUNT=256 |
| 769 | # CONFIG_IPMI_HANDLER is not set | 844 | # CONFIG_IPMI_HANDLER is not set |
| 770 | CONFIG_HW_RANDOM=y | 845 | CONFIG_HW_RANDOM=y |
| 771 | # CONFIG_NVRAM is not set | ||
| 772 | # CONFIG_R3964 is not set | 846 | # CONFIG_R3964 is not set |
| 773 | # CONFIG_RAW_DRIVER is not set | 847 | # CONFIG_RAW_DRIVER is not set |
| 774 | # CONFIG_TCG_TPM is not set | 848 | # CONFIG_TCG_TPM is not set |
| 775 | CONFIG_I2C=y | 849 | CONFIG_I2C=y |
| 776 | CONFIG_I2C_BOARDINFO=y | 850 | CONFIG_I2C_BOARDINFO=y |
| 777 | CONFIG_I2C_CHARDEV=y | 851 | CONFIG_I2C_CHARDEV=y |
| 852 | CONFIG_I2C_HELPER_AUTO=y | ||
| 778 | 853 | ||
| 779 | # | 854 | # |
| 780 | # I2C Algorithms | 855 | # I2C Hardware Bus support |
| 781 | # | 856 | # |
| 782 | # CONFIG_I2C_ALGOBIT is not set | ||
| 783 | # CONFIG_I2C_ALGOPCF is not set | ||
| 784 | # CONFIG_I2C_ALGOPCA is not set | ||
| 785 | 857 | ||
| 786 | # | 858 | # |
| 787 | # I2C Hardware Bus support | 859 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 788 | # | 860 | # |
| 789 | # CONFIG_I2C_GPIO is not set | 861 | # CONFIG_I2C_GPIO is not set |
| 790 | # CONFIG_I2C_PXA is not set | ||
| 791 | # CONFIG_I2C_OCORES is not set | 862 | # CONFIG_I2C_OCORES is not set |
| 792 | # CONFIG_I2C_PARPORT_LIGHT is not set | 863 | # CONFIG_I2C_PXA is not set |
| 793 | # CONFIG_I2C_SIMTEC is not set | 864 | # CONFIG_I2C_SIMTEC is not set |
| 865 | |||
| 866 | # | ||
| 867 | # External I2C/SMBus adapter drivers | ||
| 868 | # | ||
| 869 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 794 | # CONFIG_I2C_TAOS_EVM is not set | 870 | # CONFIG_I2C_TAOS_EVM is not set |
| 795 | # CONFIG_I2C_STUB is not set | ||
| 796 | # CONFIG_I2C_TINY_USB is not set | 871 | # CONFIG_I2C_TINY_USB is not set |
| 797 | 872 | ||
| 798 | # | 873 | # |
| 874 | # Other I2C/SMBus bus drivers | ||
| 875 | # | ||
| 876 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 877 | # CONFIG_I2C_STUB is not set | ||
| 878 | |||
| 879 | # | ||
| 799 | # Miscellaneous I2C Chip support | 880 | # Miscellaneous I2C Chip support |
| 800 | # | 881 | # |
| 801 | # CONFIG_SENSORS_DS1337 is not set | ||
| 802 | # CONFIG_SENSORS_DS1374 is not set | ||
| 803 | # CONFIG_DS1682 is not set | 882 | # CONFIG_DS1682 is not set |
| 804 | # CONFIG_EEPROM_LEGACY is not set | ||
| 805 | # CONFIG_SENSORS_PCF8574 is not set | 883 | # CONFIG_SENSORS_PCF8574 is not set |
| 884 | # CONFIG_PCF8575 is not set | ||
| 806 | # CONFIG_SENSORS_PCA9539 is not set | 885 | # CONFIG_SENSORS_PCA9539 is not set |
| 807 | # CONFIG_SENSORS_PCF8591 is not set | 886 | # CONFIG_SENSORS_PCF8591 is not set |
| 808 | # CONFIG_SENSORS_MAX6875 is not set | 887 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -811,16 +890,35 @@ CONFIG_I2C_CHARDEV=y | |||
| 811 | # CONFIG_I2C_DEBUG_ALGO is not set | 890 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 812 | # CONFIG_I2C_DEBUG_BUS is not set | 891 | # CONFIG_I2C_DEBUG_BUS is not set |
| 813 | # CONFIG_I2C_DEBUG_CHIP is not set | 892 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 893 | # CONFIG_SPI is not set | ||
| 894 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 895 | CONFIG_GPIOLIB=y | ||
| 896 | # CONFIG_DEBUG_GPIO is not set | ||
| 897 | # CONFIG_GPIO_SYSFS is not set | ||
| 814 | 898 | ||
| 815 | # | 899 | # |
| 816 | # SPI support | 900 | # Memory mapped GPIO expanders: |
| 901 | # | ||
| 902 | |||
| 903 | # | ||
| 904 | # I2C GPIO expanders: | ||
| 905 | # | ||
| 906 | # CONFIG_GPIO_MAX732X is not set | ||
| 907 | # CONFIG_GPIO_PCA953X is not set | ||
| 908 | # CONFIG_GPIO_PCF857X is not set | ||
| 909 | |||
| 910 | # | ||
| 911 | # PCI GPIO expanders: | ||
| 912 | # | ||
| 913 | |||
| 914 | # | ||
| 915 | # SPI GPIO expanders: | ||
| 817 | # | 916 | # |
| 818 | # CONFIG_SPI is not set | ||
| 819 | # CONFIG_SPI_MASTER is not set | ||
| 820 | # CONFIG_W1 is not set | 917 | # CONFIG_W1 is not set |
| 821 | # CONFIG_POWER_SUPPLY is not set | 918 | # CONFIG_POWER_SUPPLY is not set |
| 822 | CONFIG_HWMON=y | 919 | CONFIG_HWMON=y |
| 823 | # CONFIG_HWMON_VID is not set | 920 | # CONFIG_HWMON_VID is not set |
| 921 | # CONFIG_SENSORS_AD7414 is not set | ||
| 824 | # CONFIG_SENSORS_AD7418 is not set | 922 | # CONFIG_SENSORS_AD7418 is not set |
| 825 | # CONFIG_SENSORS_ADM1021 is not set | 923 | # CONFIG_SENSORS_ADM1021 is not set |
| 826 | # CONFIG_SENSORS_ADM1025 is not set | 924 | # CONFIG_SENSORS_ADM1025 is not set |
| @@ -828,7 +926,10 @@ CONFIG_HWMON=y | |||
| 828 | # CONFIG_SENSORS_ADM1029 is not set | 926 | # CONFIG_SENSORS_ADM1029 is not set |
| 829 | # CONFIG_SENSORS_ADM1031 is not set | 927 | # CONFIG_SENSORS_ADM1031 is not set |
| 830 | # CONFIG_SENSORS_ADM9240 is not set | 928 | # CONFIG_SENSORS_ADM9240 is not set |
| 929 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 831 | # CONFIG_SENSORS_ADT7470 is not set | 930 | # CONFIG_SENSORS_ADT7470 is not set |
| 931 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 932 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 832 | # CONFIG_SENSORS_ATXP1 is not set | 933 | # CONFIG_SENSORS_ATXP1 is not set |
| 833 | # CONFIG_SENSORS_DS1621 is not set | 934 | # CONFIG_SENSORS_DS1621 is not set |
| 834 | # CONFIG_SENSORS_F71805F is not set | 935 | # CONFIG_SENSORS_F71805F is not set |
| @@ -848,6 +949,7 @@ CONFIG_HWMON=y | |||
| 848 | # CONFIG_SENSORS_LM90 is not set | 949 | # CONFIG_SENSORS_LM90 is not set |
| 849 | # CONFIG_SENSORS_LM92 is not set | 950 | # CONFIG_SENSORS_LM92 is not set |
| 850 | # CONFIG_SENSORS_LM93 is not set | 951 | # CONFIG_SENSORS_LM93 is not set |
| 952 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 851 | # CONFIG_SENSORS_MAX1619 is not set | 953 | # CONFIG_SENSORS_MAX1619 is not set |
| 852 | # CONFIG_SENSORS_MAX6650 is not set | 954 | # CONFIG_SENSORS_MAX6650 is not set |
| 853 | # CONFIG_SENSORS_PC87360 is not set | 955 | # CONFIG_SENSORS_PC87360 is not set |
| @@ -856,6 +958,7 @@ CONFIG_HWMON=y | |||
| 856 | # CONFIG_SENSORS_SMSC47M1 is not set | 958 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 857 | # CONFIG_SENSORS_SMSC47M192 is not set | 959 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 858 | # CONFIG_SENSORS_SMSC47B397 is not set | 960 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 961 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 859 | # CONFIG_SENSORS_THMC50 is not set | 962 | # CONFIG_SENSORS_THMC50 is not set |
| 860 | # CONFIG_SENSORS_VT1211 is not set | 963 | # CONFIG_SENSORS_VT1211 is not set |
| 861 | # CONFIG_SENSORS_W83781D is not set | 964 | # CONFIG_SENSORS_W83781D is not set |
| @@ -863,9 +966,12 @@ CONFIG_HWMON=y | |||
| 863 | # CONFIG_SENSORS_W83792D is not set | 966 | # CONFIG_SENSORS_W83792D is not set |
| 864 | # CONFIG_SENSORS_W83793 is not set | 967 | # CONFIG_SENSORS_W83793 is not set |
| 865 | # CONFIG_SENSORS_W83L785TS is not set | 968 | # CONFIG_SENSORS_W83L785TS is not set |
| 969 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 866 | # CONFIG_SENSORS_W83627HF is not set | 970 | # CONFIG_SENSORS_W83627HF is not set |
| 867 | # CONFIG_SENSORS_W83627EHF is not set | 971 | # CONFIG_SENSORS_W83627EHF is not set |
| 868 | # CONFIG_HWMON_DEBUG_CHIP is not set | 972 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 973 | # CONFIG_THERMAL is not set | ||
| 974 | # CONFIG_THERMAL_HWMON is not set | ||
| 869 | CONFIG_WATCHDOG=y | 975 | CONFIG_WATCHDOG=y |
| 870 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 976 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 871 | 977 | ||
| @@ -879,23 +985,46 @@ CONFIG_WATCHDOG=y | |||
| 879 | # USB-based Watchdog Cards | 985 | # USB-based Watchdog Cards |
| 880 | # | 986 | # |
| 881 | # CONFIG_USBPCWATCHDOG is not set | 987 | # CONFIG_USBPCWATCHDOG is not set |
| 988 | CONFIG_SSB_POSSIBLE=y | ||
| 882 | 989 | ||
| 883 | # | 990 | # |
| 884 | # Sonics Silicon Backplane | 991 | # Sonics Silicon Backplane |
| 885 | # | 992 | # |
| 886 | CONFIG_SSB_POSSIBLE=y | ||
| 887 | # CONFIG_SSB is not set | 993 | # CONFIG_SSB is not set |
| 888 | 994 | ||
| 889 | # | 995 | # |
| 890 | # Multifunction device drivers | 996 | # Multifunction device drivers |
| 891 | # | 997 | # |
| 998 | # CONFIG_MFD_CORE is not set | ||
| 892 | # CONFIG_MFD_SM501 is not set | 999 | # CONFIG_MFD_SM501 is not set |
| 1000 | # CONFIG_MFD_ASIC3 is not set | ||
| 1001 | # CONFIG_HTC_EGPIO is not set | ||
| 1002 | # CONFIG_HTC_PASIC3 is not set | ||
| 1003 | # CONFIG_TPS65010 is not set | ||
| 1004 | # CONFIG_TWL4030_CORE is not set | ||
| 1005 | # CONFIG_MFD_TMIO is not set | ||
| 1006 | # CONFIG_MFD_T7L66XB is not set | ||
| 1007 | # CONFIG_MFD_TC6387XB is not set | ||
| 1008 | # CONFIG_MFD_TC6393XB is not set | ||
| 1009 | # CONFIG_PMIC_DA903X is not set | ||
| 1010 | # CONFIG_MFD_WM8400 is not set | ||
| 1011 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1012 | # CONFIG_MFD_PCF50633 is not set | ||
| 893 | 1013 | ||
| 894 | # | 1014 | # |
| 895 | # Multimedia devices | 1015 | # Multimedia devices |
| 896 | # | 1016 | # |
| 1017 | |||
| 1018 | # | ||
| 1019 | # Multimedia core support | ||
| 1020 | # | ||
| 897 | # CONFIG_VIDEO_DEV is not set | 1021 | # CONFIG_VIDEO_DEV is not set |
| 898 | # CONFIG_DVB_CORE is not set | 1022 | # CONFIG_DVB_CORE is not set |
| 1023 | # CONFIG_VIDEO_MEDIA is not set | ||
| 1024 | |||
| 1025 | # | ||
| 1026 | # Multimedia drivers | ||
| 1027 | # | ||
| 899 | CONFIG_DAB=y | 1028 | CONFIG_DAB=y |
| 900 | # CONFIG_USB_DABUSB is not set | 1029 | # CONFIG_USB_DABUSB is not set |
| 901 | 1030 | ||
| @@ -907,6 +1036,7 @@ CONFIG_DAB=y | |||
| 907 | CONFIG_FB=y | 1036 | CONFIG_FB=y |
| 908 | CONFIG_FIRMWARE_EDID=y | 1037 | CONFIG_FIRMWARE_EDID=y |
| 909 | # CONFIG_FB_DDC is not set | 1038 | # CONFIG_FB_DDC is not set |
| 1039 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 910 | CONFIG_FB_CFB_FILLRECT=y | 1040 | CONFIG_FB_CFB_FILLRECT=y |
| 911 | CONFIG_FB_CFB_COPYAREA=y | 1041 | CONFIG_FB_CFB_COPYAREA=y |
| 912 | CONFIG_FB_CFB_IMAGEBLIT=y | 1042 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -914,8 +1044,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 914 | # CONFIG_FB_SYS_FILLRECT is not set | 1044 | # CONFIG_FB_SYS_FILLRECT is not set |
| 915 | # CONFIG_FB_SYS_COPYAREA is not set | 1045 | # CONFIG_FB_SYS_COPYAREA is not set |
| 916 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 1046 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 1047 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 917 | # CONFIG_FB_SYS_FOPS is not set | 1048 | # CONFIG_FB_SYS_FOPS is not set |
| 918 | CONFIG_FB_DEFERRED_IO=y | ||
| 919 | # CONFIG_FB_SVGALIB is not set | 1049 | # CONFIG_FB_SVGALIB is not set |
| 920 | # CONFIG_FB_MACMODES is not set | 1050 | # CONFIG_FB_MACMODES is not set |
| 921 | # CONFIG_FB_BACKLIGHT is not set | 1051 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -928,13 +1058,20 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 928 | # CONFIG_FB_UVESA is not set | 1058 | # CONFIG_FB_UVESA is not set |
| 929 | # CONFIG_FB_S1D13XXX is not set | 1059 | # CONFIG_FB_S1D13XXX is not set |
| 930 | CONFIG_FB_PXA=y | 1060 | CONFIG_FB_PXA=y |
| 1061 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 1062 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 931 | # CONFIG_FB_PXA_PARAMETERS is not set | 1063 | # CONFIG_FB_PXA_PARAMETERS is not set |
| 932 | # CONFIG_FB_MBX is not set | 1064 | # CONFIG_FB_MBX is not set |
| 1065 | # CONFIG_FB_W100 is not set | ||
| 933 | # CONFIG_FB_VIRTUAL is not set | 1066 | # CONFIG_FB_VIRTUAL is not set |
| 1067 | # CONFIG_FB_METRONOME is not set | ||
| 1068 | # CONFIG_FB_MB862XX is not set | ||
| 934 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 1069 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 935 | CONFIG_LCD_CLASS_DEVICE=y | 1070 | CONFIG_LCD_CLASS_DEVICE=y |
| 1071 | # CONFIG_LCD_ILI9320 is not set | ||
| 1072 | # CONFIG_LCD_PLATFORM is not set | ||
| 936 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 1073 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 937 | # CONFIG_BACKLIGHT_CORGI is not set | 1074 | CONFIG_BACKLIGHT_GENERIC=y |
| 938 | 1075 | ||
| 939 | # | 1076 | # |
| 940 | # Display device support | 1077 | # Display device support |
| @@ -964,12 +1101,7 @@ CONFIG_LOGO=y | |||
| 964 | CONFIG_LOGO_LINUX_MONO=y | 1101 | CONFIG_LOGO_LINUX_MONO=y |
| 965 | CONFIG_LOGO_LINUX_VGA16=y | 1102 | CONFIG_LOGO_LINUX_VGA16=y |
| 966 | CONFIG_LOGO_LINUX_CLUT224=y | 1103 | CONFIG_LOGO_LINUX_CLUT224=y |
| 967 | |||
| 968 | # | ||
| 969 | # Sound | ||
| 970 | # | ||
| 971 | # CONFIG_SOUND is not set | 1104 | # CONFIG_SOUND is not set |
| 972 | CONFIG_AC97_BUS=y | ||
| 973 | CONFIG_HID_SUPPORT=y | 1105 | CONFIG_HID_SUPPORT=y |
| 974 | CONFIG_HID=y | 1106 | CONFIG_HID=y |
| 975 | # CONFIG_HID_DEBUG is not set | 1107 | # CONFIG_HID_DEBUG is not set |
| @@ -979,18 +1111,26 @@ CONFIG_HID=y | |||
| 979 | # USB Input Devices | 1111 | # USB Input Devices |
| 980 | # | 1112 | # |
| 981 | # CONFIG_USB_HID is not set | 1113 | # CONFIG_USB_HID is not set |
| 1114 | # CONFIG_HID_PID is not set | ||
| 982 | 1115 | ||
| 983 | # | 1116 | # |
| 984 | # USB HID Boot Protocol drivers | 1117 | # USB HID Boot Protocol drivers |
| 985 | # | 1118 | # |
| 986 | # CONFIG_USB_KBD is not set | 1119 | # CONFIG_USB_KBD is not set |
| 987 | # CONFIG_USB_MOUSE is not set | 1120 | # CONFIG_USB_MOUSE is not set |
| 1121 | |||
| 1122 | # | ||
| 1123 | # Special HID drivers | ||
| 1124 | # | ||
| 1125 | CONFIG_HID_COMPAT=y | ||
| 1126 | # CONFIG_HID_APPLE is not set | ||
| 988 | CONFIG_USB_SUPPORT=y | 1127 | CONFIG_USB_SUPPORT=y |
| 989 | CONFIG_USB_ARCH_HAS_HCD=y | 1128 | CONFIG_USB_ARCH_HAS_HCD=y |
| 990 | CONFIG_USB_ARCH_HAS_OHCI=y | 1129 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 991 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 1130 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 992 | CONFIG_USB=y | 1131 | CONFIG_USB=y |
| 993 | # CONFIG_USB_DEBUG is not set | 1132 | # CONFIG_USB_DEBUG is not set |
| 1133 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 994 | 1134 | ||
| 995 | # | 1135 | # |
| 996 | # Miscellaneous USB options | 1136 | # Miscellaneous USB options |
| @@ -999,29 +1139,40 @@ CONFIG_USB_DEVICEFS=y | |||
| 999 | # CONFIG_USB_DEVICE_CLASS is not set | 1139 | # CONFIG_USB_DEVICE_CLASS is not set |
| 1000 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1140 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1001 | # CONFIG_USB_SUSPEND is not set | 1141 | # CONFIG_USB_SUSPEND is not set |
| 1002 | # CONFIG_USB_PERSIST is not set | ||
| 1003 | # CONFIG_USB_OTG is not set | 1142 | # CONFIG_USB_OTG is not set |
| 1143 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1144 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1145 | # CONFIG_USB_MON is not set | ||
| 1146 | # CONFIG_USB_WUSB is not set | ||
| 1147 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1004 | 1148 | ||
| 1005 | # | 1149 | # |
| 1006 | # USB Host Controller Drivers | 1150 | # USB Host Controller Drivers |
| 1007 | # | 1151 | # |
| 1152 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1153 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1008 | # CONFIG_USB_ISP116X_HCD is not set | 1154 | # CONFIG_USB_ISP116X_HCD is not set |
| 1009 | # CONFIG_USB_OHCI_HCD is not set | 1155 | # CONFIG_USB_OHCI_HCD is not set |
| 1010 | # CONFIG_USB_SL811_HCD is not set | 1156 | # CONFIG_USB_SL811_HCD is not set |
| 1011 | # CONFIG_USB_R8A66597_HCD is not set | 1157 | # CONFIG_USB_R8A66597_HCD is not set |
| 1158 | # CONFIG_USB_HWA_HCD is not set | ||
| 1159 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1160 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1012 | 1161 | ||
| 1013 | # | 1162 | # |
| 1014 | # USB Device Class drivers | 1163 | # USB Device Class drivers |
| 1015 | # | 1164 | # |
| 1016 | # CONFIG_USB_ACM is not set | 1165 | # CONFIG_USB_ACM is not set |
| 1017 | # CONFIG_USB_PRINTER is not set | 1166 | # CONFIG_USB_PRINTER is not set |
| 1167 | # CONFIG_USB_WDM is not set | ||
| 1168 | # CONFIG_USB_TMC is not set | ||
| 1018 | 1169 | ||
| 1019 | # | 1170 | # |
| 1020 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1171 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 1021 | # | 1172 | # |
| 1022 | 1173 | ||
| 1023 | # | 1174 | # |
| 1024 | # may also be needed; see USB_STORAGE Help for more information | 1175 | # see USB_STORAGE Help for more information |
| 1025 | # | 1176 | # |
| 1026 | # CONFIG_USB_LIBUSUAL is not set | 1177 | # CONFIG_USB_LIBUSUAL is not set |
| 1027 | 1178 | ||
| @@ -1029,19 +1180,14 @@ CONFIG_USB_DEVICEFS=y | |||
| 1029 | # USB Imaging devices | 1180 | # USB Imaging devices |
| 1030 | # | 1181 | # |
| 1031 | # CONFIG_USB_MDC800 is not set | 1182 | # CONFIG_USB_MDC800 is not set |
| 1032 | # CONFIG_USB_MON is not set | ||
| 1033 | 1183 | ||
| 1034 | # | 1184 | # |
| 1035 | # USB port drivers | 1185 | # USB port drivers |
| 1036 | # | 1186 | # |
| 1037 | |||
| 1038 | # | ||
| 1039 | # USB Serial Converter support | ||
| 1040 | # | ||
| 1041 | CONFIG_USB_SERIAL=m | 1187 | CONFIG_USB_SERIAL=m |
| 1188 | # CONFIG_USB_EZUSB is not set | ||
| 1042 | # CONFIG_USB_SERIAL_GENERIC is not set | 1189 | # CONFIG_USB_SERIAL_GENERIC is not set |
| 1043 | # CONFIG_USB_SERIAL_AIRCABLE is not set | 1190 | # CONFIG_USB_SERIAL_AIRCABLE is not set |
| 1044 | # CONFIG_USB_SERIAL_AIRPRIME is not set | ||
| 1045 | # CONFIG_USB_SERIAL_ARK3116 is not set | 1191 | # CONFIG_USB_SERIAL_ARK3116 is not set |
| 1046 | # CONFIG_USB_SERIAL_BELKIN is not set | 1192 | # CONFIG_USB_SERIAL_BELKIN is not set |
| 1047 | # CONFIG_USB_SERIAL_CH341 is not set | 1193 | # CONFIG_USB_SERIAL_CH341 is not set |
| @@ -1059,6 +1205,7 @@ CONFIG_USB_SERIAL=m | |||
| 1059 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set | 1205 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set |
| 1060 | # CONFIG_USB_SERIAL_GARMIN is not set | 1206 | # CONFIG_USB_SERIAL_GARMIN is not set |
| 1061 | # CONFIG_USB_SERIAL_IPW is not set | 1207 | # CONFIG_USB_SERIAL_IPW is not set |
| 1208 | # CONFIG_USB_SERIAL_IUU is not set | ||
| 1062 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | 1209 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set |
| 1063 | # CONFIG_USB_SERIAL_KEYSPAN is not set | 1210 | # CONFIG_USB_SERIAL_KEYSPAN is not set |
| 1064 | # CONFIG_USB_SERIAL_KLSI is not set | 1211 | # CONFIG_USB_SERIAL_KLSI is not set |
| @@ -1066,17 +1213,21 @@ CONFIG_USB_SERIAL=m | |||
| 1066 | # CONFIG_USB_SERIAL_MCT_U232 is not set | 1213 | # CONFIG_USB_SERIAL_MCT_U232 is not set |
| 1067 | # CONFIG_USB_SERIAL_MOS7720 is not set | 1214 | # CONFIG_USB_SERIAL_MOS7720 is not set |
| 1068 | # CONFIG_USB_SERIAL_MOS7840 is not set | 1215 | # CONFIG_USB_SERIAL_MOS7840 is not set |
| 1216 | # CONFIG_USB_SERIAL_MOTOROLA is not set | ||
| 1069 | # CONFIG_USB_SERIAL_NAVMAN is not set | 1217 | # CONFIG_USB_SERIAL_NAVMAN is not set |
| 1070 | # CONFIG_USB_SERIAL_PL2303 is not set | 1218 | # CONFIG_USB_SERIAL_PL2303 is not set |
| 1071 | # CONFIG_USB_SERIAL_OTI6858 is not set | 1219 | # CONFIG_USB_SERIAL_OTI6858 is not set |
| 1220 | # CONFIG_USB_SERIAL_SPCP8X5 is not set | ||
| 1072 | # CONFIG_USB_SERIAL_HP4X is not set | 1221 | # CONFIG_USB_SERIAL_HP4X is not set |
| 1073 | # CONFIG_USB_SERIAL_SAFE is not set | 1222 | # CONFIG_USB_SERIAL_SAFE is not set |
| 1223 | # CONFIG_USB_SERIAL_SIEMENS_MPI is not set | ||
| 1074 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | 1224 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set |
| 1075 | # CONFIG_USB_SERIAL_TI is not set | 1225 | # CONFIG_USB_SERIAL_TI is not set |
| 1076 | # CONFIG_USB_SERIAL_CYBERJACK is not set | 1226 | # CONFIG_USB_SERIAL_CYBERJACK is not set |
| 1077 | # CONFIG_USB_SERIAL_XIRCOM is not set | 1227 | # CONFIG_USB_SERIAL_XIRCOM is not set |
| 1078 | # CONFIG_USB_SERIAL_OPTION is not set | 1228 | # CONFIG_USB_SERIAL_OPTION is not set |
| 1079 | # CONFIG_USB_SERIAL_OMNINET is not set | 1229 | # CONFIG_USB_SERIAL_OMNINET is not set |
| 1230 | # CONFIG_USB_SERIAL_OPTICON is not set | ||
| 1080 | # CONFIG_USB_SERIAL_DEBUG is not set | 1231 | # CONFIG_USB_SERIAL_DEBUG is not set |
| 1081 | 1232 | ||
| 1082 | # | 1233 | # |
| @@ -1085,7 +1236,7 @@ CONFIG_USB_SERIAL=m | |||
| 1085 | # CONFIG_USB_EMI62 is not set | 1236 | # CONFIG_USB_EMI62 is not set |
| 1086 | # CONFIG_USB_EMI26 is not set | 1237 | # CONFIG_USB_EMI26 is not set |
| 1087 | # CONFIG_USB_ADUTUX is not set | 1238 | # CONFIG_USB_ADUTUX is not set |
| 1088 | # CONFIG_USB_AUERSWALD is not set | 1239 | # CONFIG_USB_SEVSEG is not set |
| 1089 | # CONFIG_USB_RIO500 is not set | 1240 | # CONFIG_USB_RIO500 is not set |
| 1090 | # CONFIG_USB_LEGOTOWER is not set | 1241 | # CONFIG_USB_LEGOTOWER is not set |
| 1091 | # CONFIG_USB_LCD is not set | 1242 | # CONFIG_USB_LCD is not set |
| @@ -1101,30 +1252,29 @@ CONFIG_USB_SERIAL=m | |||
| 1101 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1252 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1102 | # CONFIG_USB_IOWARRIOR is not set | 1253 | # CONFIG_USB_IOWARRIOR is not set |
| 1103 | # CONFIG_USB_TEST is not set | 1254 | # CONFIG_USB_TEST is not set |
| 1104 | 1255 | # CONFIG_USB_ISIGHTFW is not set | |
| 1105 | # | 1256 | # CONFIG_USB_VST is not set |
| 1106 | # USB DSL modem support | ||
| 1107 | # | ||
| 1108 | |||
| 1109 | # | ||
| 1110 | # USB Gadget Support | ||
| 1111 | # | ||
| 1112 | CONFIG_USB_GADGET=m | 1257 | CONFIG_USB_GADGET=m |
| 1113 | # CONFIG_USB_GADGET_DEBUG is not set | 1258 | # CONFIG_USB_GADGET_DEBUG is not set |
| 1114 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | 1259 | # CONFIG_USB_GADGET_DEBUG_FILES is not set |
| 1115 | # CONFIG_USB_GADGET_DEBUG_FS is not set | 1260 | # CONFIG_USB_GADGET_DEBUG_FS is not set |
| 1261 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1116 | CONFIG_USB_GADGET_SELECTED=y | 1262 | CONFIG_USB_GADGET_SELECTED=y |
| 1117 | # CONFIG_USB_GADGET_AMD5536UDC is not set | 1263 | # CONFIG_USB_GADGET_AT91 is not set |
| 1118 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | 1264 | # CONFIG_USB_GADGET_ATMEL_USBA is not set |
| 1119 | # CONFIG_USB_GADGET_FSL_USB2 is not set | 1265 | # CONFIG_USB_GADGET_FSL_USB2 is not set |
| 1120 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1121 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
| 1122 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1123 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1124 | # CONFIG_USB_GADGET_LH7A40X is not set | 1266 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 1125 | # CONFIG_USB_GADGET_OMAP is not set | 1267 | # CONFIG_USB_GADGET_OMAP is not set |
| 1268 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1269 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1126 | # CONFIG_USB_GADGET_S3C2410 is not set | 1270 | # CONFIG_USB_GADGET_S3C2410 is not set |
| 1127 | # CONFIG_USB_GADGET_AT91 is not set | 1271 | # CONFIG_USB_GADGET_IMX is not set |
| 1272 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1273 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1274 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1275 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1276 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1277 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1128 | CONFIG_USB_GADGET_DUMMY_HCD=y | 1278 | CONFIG_USB_GADGET_DUMMY_HCD=y |
| 1129 | CONFIG_USB_DUMMY_HCD=m | 1279 | CONFIG_USB_DUMMY_HCD=m |
| 1130 | CONFIG_USB_GADGET_DUALSPEED=y | 1280 | CONFIG_USB_GADGET_DUALSPEED=y |
| @@ -1134,21 +1284,32 @@ CONFIG_USB_GADGET_DUALSPEED=y | |||
| 1134 | # CONFIG_USB_FILE_STORAGE is not set | 1284 | # CONFIG_USB_FILE_STORAGE is not set |
| 1135 | # CONFIG_USB_G_SERIAL is not set | 1285 | # CONFIG_USB_G_SERIAL is not set |
| 1136 | # CONFIG_USB_MIDI_GADGET is not set | 1286 | # CONFIG_USB_MIDI_GADGET is not set |
| 1287 | # CONFIG_USB_G_PRINTER is not set | ||
| 1288 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1289 | |||
| 1290 | # | ||
| 1291 | # OTG and related infrastructure | ||
| 1292 | # | ||
| 1293 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1137 | CONFIG_MMC=y | 1294 | CONFIG_MMC=y |
| 1138 | # CONFIG_MMC_DEBUG is not set | 1295 | # CONFIG_MMC_DEBUG is not set |
| 1139 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1296 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 1140 | 1297 | ||
| 1141 | # | 1298 | # |
| 1142 | # MMC/SD Card Drivers | 1299 | # MMC/SD/SDIO Card Drivers |
| 1143 | # | 1300 | # |
| 1144 | CONFIG_MMC_BLOCK=y | 1301 | CONFIG_MMC_BLOCK=y |
| 1145 | CONFIG_MMC_BLOCK_BOUNCE=y | 1302 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 1146 | # CONFIG_SDIO_UART is not set | 1303 | # CONFIG_SDIO_UART is not set |
| 1304 | # CONFIG_MMC_TEST is not set | ||
| 1147 | 1305 | ||
| 1148 | # | 1306 | # |
| 1149 | # MMC/SD Host Controller Drivers | 1307 | # MMC/SD/SDIO Host Controller Drivers |
| 1150 | # | 1308 | # |
| 1151 | # CONFIG_MMC_PXA is not set | 1309 | # CONFIG_MMC_PXA is not set |
| 1310 | # CONFIG_MMC_SDHCI is not set | ||
| 1311 | # CONFIG_MEMSTICK is not set | ||
| 1312 | # CONFIG_ACCESSIBILITY is not set | ||
| 1152 | CONFIG_NEW_LEDS=y | 1313 | CONFIG_NEW_LEDS=y |
| 1153 | # CONFIG_LEDS_CLASS is not set | 1314 | # CONFIG_LEDS_CLASS is not set |
| 1154 | 1315 | ||
| @@ -1163,6 +1324,8 @@ CONFIG_LEDS_TRIGGERS=y | |||
| 1163 | CONFIG_LEDS_TRIGGER_TIMER=y | 1324 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 1164 | # CONFIG_LEDS_TRIGGER_IDE_DISK is not set | 1325 | # CONFIG_LEDS_TRIGGER_IDE_DISK is not set |
| 1165 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 1326 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 1327 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1328 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1166 | CONFIG_RTC_LIB=y | 1329 | CONFIG_RTC_LIB=y |
| 1167 | CONFIG_RTC_CLASS=y | 1330 | CONFIG_RTC_CLASS=y |
| 1168 | # CONFIG_RTC_HCTOSYS is not set | 1331 | # CONFIG_RTC_HCTOSYS is not set |
| @@ -1190,6 +1353,9 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1190 | # CONFIG_RTC_DRV_PCF8563 is not set | 1353 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1191 | CONFIG_RTC_DRV_PCF8583=m | 1354 | CONFIG_RTC_DRV_PCF8583=m |
| 1192 | # CONFIG_RTC_DRV_M41T80 is not set | 1355 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1356 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1357 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1358 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1193 | 1359 | ||
| 1194 | # | 1360 | # |
| 1195 | # SPI RTC drivers | 1361 | # SPI RTC drivers |
| @@ -1199,36 +1365,45 @@ CONFIG_RTC_DRV_PCF8583=m | |||
| 1199 | # Platform RTC drivers | 1365 | # Platform RTC drivers |
| 1200 | # | 1366 | # |
| 1201 | # CONFIG_RTC_DRV_CMOS is not set | 1367 | # CONFIG_RTC_DRV_CMOS is not set |
| 1368 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1369 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1202 | # CONFIG_RTC_DRV_DS1553 is not set | 1370 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1203 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1204 | # CONFIG_RTC_DRV_DS1742 is not set | 1371 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1372 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1205 | # CONFIG_RTC_DRV_M48T86 is not set | 1373 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1374 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1206 | # CONFIG_RTC_DRV_M48T59 is not set | 1375 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1376 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1207 | # CONFIG_RTC_DRV_V3020 is not set | 1377 | # CONFIG_RTC_DRV_V3020 is not set |
| 1208 | 1378 | ||
| 1209 | # | 1379 | # |
| 1210 | # on-CPU RTC drivers | 1380 | # on-CPU RTC drivers |
| 1211 | # | 1381 | # |
| 1212 | # CONFIG_RTC_DRV_SA1100 is not set | 1382 | # CONFIG_RTC_DRV_SA1100 is not set |
| 1383 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1384 | # CONFIG_DMADEVICES is not set | ||
| 1385 | # CONFIG_REGULATOR is not set | ||
| 1386 | # CONFIG_UIO is not set | ||
| 1387 | # CONFIG_STAGING is not set | ||
| 1213 | 1388 | ||
| 1214 | # | 1389 | # |
| 1215 | # File systems | 1390 | # File systems |
| 1216 | # | 1391 | # |
| 1217 | # CONFIG_EXT2_FS is not set | 1392 | # CONFIG_EXT2_FS is not set |
| 1218 | # CONFIG_EXT3_FS is not set | 1393 | # CONFIG_EXT3_FS is not set |
| 1219 | # CONFIG_EXT4DEV_FS is not set | 1394 | # CONFIG_EXT4_FS is not set |
| 1220 | # CONFIG_REISERFS_FS is not set | 1395 | # CONFIG_REISERFS_FS is not set |
| 1221 | # CONFIG_JFS_FS is not set | 1396 | # CONFIG_JFS_FS is not set |
| 1222 | CONFIG_FS_POSIX_ACL=y | 1397 | CONFIG_FS_POSIX_ACL=y |
| 1398 | CONFIG_FILE_LOCKING=y | ||
| 1223 | # CONFIG_XFS_FS is not set | 1399 | # CONFIG_XFS_FS is not set |
| 1224 | # CONFIG_GFS2_FS is not set | 1400 | # CONFIG_GFS2_FS is not set |
| 1225 | # CONFIG_OCFS2_FS is not set | 1401 | # CONFIG_OCFS2_FS is not set |
| 1226 | # CONFIG_MINIX_FS is not set | 1402 | # CONFIG_BTRFS_FS is not set |
| 1227 | # CONFIG_ROMFS_FS is not set | 1403 | CONFIG_DNOTIFY=y |
| 1228 | CONFIG_INOTIFY=y | 1404 | CONFIG_INOTIFY=y |
| 1229 | CONFIG_INOTIFY_USER=y | 1405 | CONFIG_INOTIFY_USER=y |
| 1230 | # CONFIG_QUOTA is not set | 1406 | # CONFIG_QUOTA is not set |
| 1231 | CONFIG_DNOTIFY=y | ||
| 1232 | # CONFIG_AUTOFS_FS is not set | 1407 | # CONFIG_AUTOFS_FS is not set |
| 1233 | CONFIG_AUTOFS4_FS=y | 1408 | CONFIG_AUTOFS4_FS=y |
| 1234 | # CONFIG_FUSE_FS is not set | 1409 | # CONFIG_FUSE_FS is not set |
| @@ -1254,15 +1429,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" | |||
| 1254 | # | 1429 | # |
| 1255 | CONFIG_PROC_FS=y | 1430 | CONFIG_PROC_FS=y |
| 1256 | CONFIG_PROC_SYSCTL=y | 1431 | CONFIG_PROC_SYSCTL=y |
| 1432 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1257 | CONFIG_SYSFS=y | 1433 | CONFIG_SYSFS=y |
| 1258 | CONFIG_TMPFS=y | 1434 | CONFIG_TMPFS=y |
| 1259 | # CONFIG_TMPFS_POSIX_ACL is not set | 1435 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1260 | # CONFIG_HUGETLB_PAGE is not set | 1436 | # CONFIG_HUGETLB_PAGE is not set |
| 1261 | CONFIG_CONFIGFS_FS=y | 1437 | CONFIG_CONFIGFS_FS=y |
| 1262 | 1438 | CONFIG_MISC_FILESYSTEMS=y | |
| 1263 | # | ||
| 1264 | # Miscellaneous filesystems | ||
| 1265 | # | ||
| 1266 | # CONFIG_ADFS_FS is not set | 1439 | # CONFIG_ADFS_FS is not set |
| 1267 | # CONFIG_AFFS_FS is not set | 1440 | # CONFIG_AFFS_FS is not set |
| 1268 | # CONFIG_ECRYPT_FS is not set | 1441 | # CONFIG_ECRYPT_FS is not set |
| @@ -1283,9 +1456,13 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1283 | CONFIG_JFFS2_RTIME=y | 1456 | CONFIG_JFFS2_RTIME=y |
| 1284 | # CONFIG_JFFS2_RUBIN is not set | 1457 | # CONFIG_JFFS2_RUBIN is not set |
| 1285 | # CONFIG_CRAMFS is not set | 1458 | # CONFIG_CRAMFS is not set |
| 1459 | # CONFIG_SQUASHFS is not set | ||
| 1286 | # CONFIG_VXFS_FS is not set | 1460 | # CONFIG_VXFS_FS is not set |
| 1461 | # CONFIG_MINIX_FS is not set | ||
| 1462 | # CONFIG_OMFS_FS is not set | ||
| 1287 | # CONFIG_HPFS_FS is not set | 1463 | # CONFIG_HPFS_FS is not set |
| 1288 | # CONFIG_QNX4FS_FS is not set | 1464 | # CONFIG_QNX4FS_FS is not set |
| 1465 | # CONFIG_ROMFS_FS is not set | ||
| 1289 | # CONFIG_SYSV_FS is not set | 1466 | # CONFIG_SYSV_FS is not set |
| 1290 | # CONFIG_UFS_FS is not set | 1467 | # CONFIG_UFS_FS is not set |
| 1291 | CONFIG_NETWORK_FILESYSTEMS=y | 1468 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1293,20 +1470,18 @@ CONFIG_NFS_FS=y | |||
| 1293 | CONFIG_NFS_V3=y | 1470 | CONFIG_NFS_V3=y |
| 1294 | # CONFIG_NFS_V3_ACL is not set | 1471 | # CONFIG_NFS_V3_ACL is not set |
| 1295 | CONFIG_NFS_V4=y | 1472 | CONFIG_NFS_V4=y |
| 1296 | # CONFIG_NFS_DIRECTIO is not set | 1473 | CONFIG_ROOT_NFS=y |
| 1297 | CONFIG_NFSD=y | 1474 | CONFIG_NFSD=y |
| 1298 | CONFIG_NFSD_V3=y | 1475 | CONFIG_NFSD_V3=y |
| 1299 | # CONFIG_NFSD_V3_ACL is not set | 1476 | # CONFIG_NFSD_V3_ACL is not set |
| 1300 | CONFIG_NFSD_V4=y | 1477 | CONFIG_NFSD_V4=y |
| 1301 | CONFIG_NFSD_TCP=y | ||
| 1302 | CONFIG_ROOT_NFS=y | ||
| 1303 | CONFIG_LOCKD=y | 1478 | CONFIG_LOCKD=y |
| 1304 | CONFIG_LOCKD_V4=y | 1479 | CONFIG_LOCKD_V4=y |
| 1305 | CONFIG_EXPORTFS=y | 1480 | CONFIG_EXPORTFS=y |
| 1306 | CONFIG_NFS_COMMON=y | 1481 | CONFIG_NFS_COMMON=y |
| 1307 | CONFIG_SUNRPC=y | 1482 | CONFIG_SUNRPC=y |
| 1308 | CONFIG_SUNRPC_GSS=y | 1483 | CONFIG_SUNRPC_GSS=y |
| 1309 | # CONFIG_SUNRPC_BIND34 is not set | 1484 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1310 | CONFIG_RPCSEC_GSS_KRB5=y | 1485 | CONFIG_RPCSEC_GSS_KRB5=y |
| 1311 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1486 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1312 | # CONFIG_SMB_FS is not set | 1487 | # CONFIG_SMB_FS is not set |
| @@ -1361,9 +1536,6 @@ CONFIG_NLS_ISO8859_15=m | |||
| 1361 | # CONFIG_NLS_KOI8_U is not set | 1536 | # CONFIG_NLS_KOI8_U is not set |
| 1362 | CONFIG_NLS_UTF8=m | 1537 | CONFIG_NLS_UTF8=m |
| 1363 | # CONFIG_DLM is not set | 1538 | # CONFIG_DLM is not set |
| 1364 | CONFIG_INSTRUMENTATION=y | ||
| 1365 | # CONFIG_PROFILING is not set | ||
| 1366 | # CONFIG_MARKERS is not set | ||
| 1367 | 1539 | ||
| 1368 | # | 1540 | # |
| 1369 | # Kernel hacking | 1541 | # Kernel hacking |
| @@ -1371,6 +1543,7 @@ CONFIG_INSTRUMENTATION=y | |||
| 1371 | CONFIG_PRINTK_TIME=y | 1543 | CONFIG_PRINTK_TIME=y |
| 1372 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1544 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1373 | CONFIG_ENABLE_MUST_CHECK=y | 1545 | CONFIG_ENABLE_MUST_CHECK=y |
| 1546 | CONFIG_FRAME_WARN=1024 | ||
| 1374 | CONFIG_MAGIC_SYSRQ=y | 1547 | CONFIG_MAGIC_SYSRQ=y |
| 1375 | # CONFIG_UNUSED_SYMBOLS is not set | 1548 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1376 | CONFIG_DEBUG_FS=y | 1549 | CONFIG_DEBUG_FS=y |
| @@ -1378,9 +1551,12 @@ CONFIG_DEBUG_FS=y | |||
| 1378 | CONFIG_DEBUG_KERNEL=y | 1551 | CONFIG_DEBUG_KERNEL=y |
| 1379 | # CONFIG_DEBUG_SHIRQ is not set | 1552 | # CONFIG_DEBUG_SHIRQ is not set |
| 1380 | CONFIG_DETECT_SOFTLOCKUP=y | 1553 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1554 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1555 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1381 | CONFIG_SCHED_DEBUG=y | 1556 | CONFIG_SCHED_DEBUG=y |
| 1382 | # CONFIG_SCHEDSTATS is not set | 1557 | # CONFIG_SCHEDSTATS is not set |
| 1383 | # CONFIG_TIMER_STATS is not set | 1558 | # CONFIG_TIMER_STATS is not set |
| 1559 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1384 | # CONFIG_DEBUG_SLAB is not set | 1560 | # CONFIG_DEBUG_SLAB is not set |
| 1385 | CONFIG_DEBUG_PREEMPT=y | 1561 | CONFIG_DEBUG_PREEMPT=y |
| 1386 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1562 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| @@ -1396,16 +1572,40 @@ CONFIG_DEBUG_PREEMPT=y | |||
| 1396 | CONFIG_DEBUG_BUGVERBOSE=y | 1572 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1397 | CONFIG_DEBUG_INFO=y | 1573 | CONFIG_DEBUG_INFO=y |
| 1398 | # CONFIG_DEBUG_VM is not set | 1574 | # CONFIG_DEBUG_VM is not set |
| 1575 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1576 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1399 | # CONFIG_DEBUG_LIST is not set | 1577 | # CONFIG_DEBUG_LIST is not set |
| 1400 | # CONFIG_DEBUG_SG is not set | 1578 | # CONFIG_DEBUG_SG is not set |
| 1579 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1401 | CONFIG_FRAME_POINTER=y | 1580 | CONFIG_FRAME_POINTER=y |
| 1402 | CONFIG_FORCED_INLINING=y | ||
| 1403 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1581 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1404 | # CONFIG_RCU_TORTURE_TEST is not set | 1582 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1583 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1584 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1585 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1405 | # CONFIG_FAULT_INJECTION is not set | 1586 | # CONFIG_FAULT_INJECTION is not set |
| 1587 | # CONFIG_LATENCYTOP is not set | ||
| 1588 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1589 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1590 | |||
| 1591 | # | ||
| 1592 | # Tracers | ||
| 1593 | # | ||
| 1594 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1595 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1596 | # CONFIG_PREEMPT_TRACER is not set | ||
| 1597 | # CONFIG_SCHED_TRACER is not set | ||
| 1598 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1599 | # CONFIG_BOOT_TRACER is not set | ||
| 1600 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1601 | # CONFIG_STACK_TRACER is not set | ||
| 1602 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1406 | # CONFIG_SAMPLES is not set | 1603 | # CONFIG_SAMPLES is not set |
| 1604 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1605 | # CONFIG_KGDB is not set | ||
| 1407 | CONFIG_DEBUG_USER=y | 1606 | CONFIG_DEBUG_USER=y |
| 1408 | CONFIG_DEBUG_ERRORS=y | 1607 | CONFIG_DEBUG_ERRORS=y |
| 1608 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1409 | CONFIG_DEBUG_LL=y | 1609 | CONFIG_DEBUG_LL=y |
| 1410 | # CONFIG_DEBUG_ICEDCC is not set | 1610 | # CONFIG_DEBUG_ICEDCC is not set |
| 1411 | 1611 | ||
| @@ -1415,58 +1615,114 @@ CONFIG_DEBUG_LL=y | |||
| 1415 | CONFIG_KEYS=y | 1615 | CONFIG_KEYS=y |
| 1416 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | 1616 | CONFIG_KEYS_DEBUG_PROC_KEYS=y |
| 1417 | CONFIG_SECURITY=y | 1617 | CONFIG_SECURITY=y |
| 1618 | # CONFIG_SECURITYFS is not set | ||
| 1418 | # CONFIG_SECURITY_NETWORK is not set | 1619 | # CONFIG_SECURITY_NETWORK is not set |
| 1419 | CONFIG_SECURITY_CAPABILITIES=y | 1620 | # CONFIG_SECURITY_PATH is not set |
| 1420 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1621 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1421 | # CONFIG_SECURITY_ROOTPLUG is not set | 1622 | # CONFIG_SECURITY_ROOTPLUG is not set |
| 1623 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1422 | CONFIG_CRYPTO=y | 1624 | CONFIG_CRYPTO=y |
| 1625 | |||
| 1626 | # | ||
| 1627 | # Crypto core or helper | ||
| 1628 | # | ||
| 1629 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1423 | CONFIG_CRYPTO_ALGAPI=y | 1630 | CONFIG_CRYPTO_ALGAPI=y |
| 1631 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1632 | CONFIG_CRYPTO_AEAD2=y | ||
| 1424 | CONFIG_CRYPTO_BLKCIPHER=y | 1633 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1634 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1635 | CONFIG_CRYPTO_HASH=y | ||
| 1636 | CONFIG_CRYPTO_HASH2=y | ||
| 1637 | CONFIG_CRYPTO_RNG2=y | ||
| 1425 | CONFIG_CRYPTO_MANAGER=y | 1638 | CONFIG_CRYPTO_MANAGER=y |
| 1639 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1640 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1641 | # CONFIG_CRYPTO_NULL is not set | ||
| 1642 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1643 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1644 | # CONFIG_CRYPTO_TEST is not set | ||
| 1645 | |||
| 1646 | # | ||
| 1647 | # Authenticated Encryption with Associated Data | ||
| 1648 | # | ||
| 1649 | # CONFIG_CRYPTO_CCM is not set | ||
| 1650 | # CONFIG_CRYPTO_GCM is not set | ||
| 1651 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1652 | |||
| 1653 | # | ||
| 1654 | # Block modes | ||
| 1655 | # | ||
| 1656 | CONFIG_CRYPTO_CBC=y | ||
| 1657 | # CONFIG_CRYPTO_CTR is not set | ||
| 1658 | # CONFIG_CRYPTO_CTS is not set | ||
| 1659 | CONFIG_CRYPTO_ECB=y | ||
| 1660 | # CONFIG_CRYPTO_LRW is not set | ||
| 1661 | CONFIG_CRYPTO_PCBC=m | ||
| 1662 | # CONFIG_CRYPTO_XTS is not set | ||
| 1663 | |||
| 1664 | # | ||
| 1665 | # Hash modes | ||
| 1666 | # | ||
| 1426 | # CONFIG_CRYPTO_HMAC is not set | 1667 | # CONFIG_CRYPTO_HMAC is not set |
| 1427 | # CONFIG_CRYPTO_XCBC is not set | 1668 | # CONFIG_CRYPTO_XCBC is not set |
| 1428 | # CONFIG_CRYPTO_NULL is not set | 1669 | |
| 1670 | # | ||
| 1671 | # Digest | ||
| 1672 | # | ||
| 1673 | CONFIG_CRYPTO_CRC32C=y | ||
| 1429 | # CONFIG_CRYPTO_MD4 is not set | 1674 | # CONFIG_CRYPTO_MD4 is not set |
| 1430 | CONFIG_CRYPTO_MD5=y | 1675 | CONFIG_CRYPTO_MD5=y |
| 1676 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 1677 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1678 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1679 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1680 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1431 | CONFIG_CRYPTO_SHA1=m | 1681 | CONFIG_CRYPTO_SHA1=m |
| 1432 | CONFIG_CRYPTO_SHA256=m | 1682 | CONFIG_CRYPTO_SHA256=m |
| 1433 | CONFIG_CRYPTO_SHA512=m | 1683 | CONFIG_CRYPTO_SHA512=m |
| 1434 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1435 | # CONFIG_CRYPTO_TGR192 is not set | 1684 | # CONFIG_CRYPTO_TGR192 is not set |
| 1436 | # CONFIG_CRYPTO_GF128MUL is not set | 1685 | # CONFIG_CRYPTO_WP512 is not set |
| 1437 | CONFIG_CRYPTO_ECB=y | 1686 | |
| 1438 | CONFIG_CRYPTO_CBC=y | 1687 | # |
| 1439 | CONFIG_CRYPTO_PCBC=m | 1688 | # Ciphers |
| 1440 | # CONFIG_CRYPTO_LRW is not set | 1689 | # |
| 1441 | # CONFIG_CRYPTO_XTS is not set | 1690 | CONFIG_CRYPTO_AES=y |
| 1442 | # CONFIG_CRYPTO_CRYPTD is not set | 1691 | # CONFIG_CRYPTO_ANUBIS is not set |
| 1443 | CONFIG_CRYPTO_DES=y | 1692 | CONFIG_CRYPTO_ARC4=y |
| 1444 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1445 | # CONFIG_CRYPTO_BLOWFISH is not set | 1693 | # CONFIG_CRYPTO_BLOWFISH is not set |
| 1446 | # CONFIG_CRYPTO_TWOFISH is not set | 1694 | # CONFIG_CRYPTO_CAMELLIA is not set |
| 1447 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1448 | CONFIG_CRYPTO_AES=m | ||
| 1449 | # CONFIG_CRYPTO_CAST5 is not set | 1695 | # CONFIG_CRYPTO_CAST5 is not set |
| 1450 | # CONFIG_CRYPTO_CAST6 is not set | 1696 | # CONFIG_CRYPTO_CAST6 is not set |
| 1451 | # CONFIG_CRYPTO_TEA is not set | 1697 | CONFIG_CRYPTO_DES=y |
| 1452 | CONFIG_CRYPTO_ARC4=y | 1698 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1453 | # CONFIG_CRYPTO_KHAZAD is not set | 1699 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1454 | # CONFIG_CRYPTO_ANUBIS is not set | 1700 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1455 | # CONFIG_CRYPTO_SEED is not set | 1701 | # CONFIG_CRYPTO_SEED is not set |
| 1702 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1703 | # CONFIG_CRYPTO_TEA is not set | ||
| 1704 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1705 | |||
| 1706 | # | ||
| 1707 | # Compression | ||
| 1708 | # | ||
| 1456 | CONFIG_CRYPTO_DEFLATE=m | 1709 | CONFIG_CRYPTO_DEFLATE=m |
| 1457 | CONFIG_CRYPTO_MICHAEL_MIC=m | 1710 | # CONFIG_CRYPTO_LZO is not set |
| 1458 | CONFIG_CRYPTO_CRC32C=y | 1711 | |
| 1459 | # CONFIG_CRYPTO_CAMELLIA is not set | 1712 | # |
| 1460 | # CONFIG_CRYPTO_TEST is not set | 1713 | # Random Number Generation |
| 1461 | # CONFIG_CRYPTO_AUTHENC is not set | 1714 | # |
| 1715 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1462 | CONFIG_CRYPTO_HW=y | 1716 | CONFIG_CRYPTO_HW=y |
| 1463 | 1717 | ||
| 1464 | # | 1718 | # |
| 1465 | # Library routines | 1719 | # Library routines |
| 1466 | # | 1720 | # |
| 1467 | CONFIG_BITREVERSE=y | 1721 | CONFIG_BITREVERSE=y |
| 1722 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1468 | CONFIG_CRC_CCITT=y | 1723 | CONFIG_CRC_CCITT=y |
| 1469 | CONFIG_CRC16=y | 1724 | CONFIG_CRC16=y |
| 1725 | # CONFIG_CRC_T10DIF is not set | ||
| 1470 | # CONFIG_CRC_ITU_T is not set | 1726 | # CONFIG_CRC_ITU_T is not set |
| 1471 | CONFIG_CRC32=y | 1727 | CONFIG_CRC32=y |
| 1472 | # CONFIG_CRC7 is not set | 1728 | # CONFIG_CRC7 is not set |
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig new file mode 100644 index 000000000000..4774a36fa740 --- /dev/null +++ b/arch/arm/configs/colibri_pxa300_defconfig | |||
| @@ -0,0 +1,1156 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc8 | ||
| 4 | # Fri Mar 13 16:13:20 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | # CONFIG_SYSVIPC is not set | ||
| 40 | # CONFIG_POSIX_MQUEUE is not set | ||
| 41 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 42 | # CONFIG_TASKSTATS is not set | ||
| 43 | # CONFIG_AUDIT is not set | ||
| 44 | |||
| 45 | # | ||
| 46 | # RCU Subsystem | ||
| 47 | # | ||
| 48 | CONFIG_CLASSIC_RCU=y | ||
| 49 | # CONFIG_TREE_RCU is not set | ||
| 50 | # CONFIG_PREEMPT_RCU is not set | ||
| 51 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 52 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 53 | # CONFIG_IKCONFIG is not set | ||
| 54 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 55 | # CONFIG_GROUP_SCHED is not set | ||
| 56 | # CONFIG_CGROUPS is not set | ||
| 57 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 58 | # CONFIG_RELAY is not set | ||
| 59 | CONFIG_NAMESPACES=y | ||
| 60 | # CONFIG_UTS_NS is not set | ||
| 61 | # CONFIG_USER_NS is not set | ||
| 62 | # CONFIG_PID_NS is not set | ||
| 63 | # CONFIG_NET_NS is not set | ||
| 64 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 65 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 66 | CONFIG_SYSCTL=y | ||
| 67 | CONFIG_ANON_INODES=y | ||
| 68 | # CONFIG_EMBEDDED is not set | ||
| 69 | CONFIG_UID16=y | ||
| 70 | CONFIG_SYSCTL_SYSCALL=y | ||
| 71 | CONFIG_KALLSYMS=y | ||
| 72 | # CONFIG_KALLSYMS_ALL is not set | ||
| 73 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 74 | CONFIG_HOTPLUG=y | ||
| 75 | CONFIG_PRINTK=y | ||
| 76 | CONFIG_BUG=y | ||
| 77 | CONFIG_ELF_CORE=y | ||
| 78 | CONFIG_BASE_FULL=y | ||
| 79 | CONFIG_FUTEX=y | ||
| 80 | CONFIG_EPOLL=y | ||
| 81 | CONFIG_SIGNALFD=y | ||
| 82 | CONFIG_TIMERFD=y | ||
| 83 | CONFIG_EVENTFD=y | ||
| 84 | CONFIG_SHMEM=y | ||
| 85 | CONFIG_AIO=y | ||
| 86 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 87 | CONFIG_SLUB_DEBUG=y | ||
| 88 | CONFIG_COMPAT_BRK=y | ||
| 89 | # CONFIG_SLAB is not set | ||
| 90 | CONFIG_SLUB=y | ||
| 91 | # CONFIG_SLOB is not set | ||
| 92 | # CONFIG_PROFILING is not set | ||
| 93 | CONFIG_HAVE_OPROFILE=y | ||
| 94 | # CONFIG_KPROBES is not set | ||
| 95 | CONFIG_HAVE_KPROBES=y | ||
| 96 | CONFIG_HAVE_KRETPROBES=y | ||
| 97 | CONFIG_HAVE_CLK=y | ||
| 98 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 99 | CONFIG_SLABINFO=y | ||
| 100 | CONFIG_RT_MUTEXES=y | ||
| 101 | CONFIG_BASE_SMALL=0 | ||
| 102 | CONFIG_MODULES=y | ||
| 103 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 104 | CONFIG_MODULE_UNLOAD=y | ||
| 105 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 106 | # CONFIG_MODVERSIONS is not set | ||
| 107 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 108 | CONFIG_BLOCK=y | ||
| 109 | # CONFIG_LBD is not set | ||
| 110 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 111 | # CONFIG_BLK_DEV_BSG is not set | ||
| 112 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 113 | |||
| 114 | # | ||
| 115 | # IO Schedulers | ||
| 116 | # | ||
| 117 | CONFIG_IOSCHED_NOOP=y | ||
| 118 | CONFIG_IOSCHED_AS=y | ||
| 119 | CONFIG_IOSCHED_DEADLINE=y | ||
| 120 | CONFIG_IOSCHED_CFQ=y | ||
| 121 | # CONFIG_DEFAULT_AS is not set | ||
| 122 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 123 | CONFIG_DEFAULT_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_NOOP is not set | ||
| 125 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 126 | # CONFIG_FREEZER is not set | ||
| 127 | |||
| 128 | # | ||
| 129 | # System Type | ||
| 130 | # | ||
| 131 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 132 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 133 | # CONFIG_ARCH_REALVIEW is not set | ||
| 134 | # CONFIG_ARCH_VERSATILE is not set | ||
| 135 | # CONFIG_ARCH_AT91 is not set | ||
| 136 | # CONFIG_ARCH_CLPS711X is not set | ||
| 137 | # CONFIG_ARCH_EBSA110 is not set | ||
| 138 | # CONFIG_ARCH_EP93XX is not set | ||
| 139 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 140 | # CONFIG_ARCH_NETX is not set | ||
| 141 | # CONFIG_ARCH_H720X is not set | ||
| 142 | # CONFIG_ARCH_IMX is not set | ||
| 143 | # CONFIG_ARCH_IOP13XX is not set | ||
| 144 | # CONFIG_ARCH_IOP32X is not set | ||
| 145 | # CONFIG_ARCH_IOP33X is not set | ||
| 146 | # CONFIG_ARCH_IXP23XX is not set | ||
| 147 | # CONFIG_ARCH_IXP2000 is not set | ||
| 148 | # CONFIG_ARCH_IXP4XX is not set | ||
| 149 | # CONFIG_ARCH_L7200 is not set | ||
| 150 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 151 | # CONFIG_ARCH_KS8695 is not set | ||
| 152 | # CONFIG_ARCH_NS9XXX is not set | ||
| 153 | # CONFIG_ARCH_LOKI is not set | ||
| 154 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 155 | # CONFIG_ARCH_MXC is not set | ||
| 156 | # CONFIG_ARCH_ORION5X is not set | ||
| 157 | # CONFIG_ARCH_PNX4008 is not set | ||
| 158 | CONFIG_ARCH_PXA=y | ||
| 159 | # CONFIG_ARCH_RPC is not set | ||
| 160 | # CONFIG_ARCH_SA1100 is not set | ||
| 161 | # CONFIG_ARCH_S3C2410 is not set | ||
| 162 | # CONFIG_ARCH_S3C64XX is not set | ||
| 163 | # CONFIG_ARCH_SHARK is not set | ||
| 164 | # CONFIG_ARCH_LH7A40X is not set | ||
| 165 | # CONFIG_ARCH_DAVINCI is not set | ||
| 166 | # CONFIG_ARCH_OMAP is not set | ||
| 167 | # CONFIG_ARCH_MSM is not set | ||
| 168 | # CONFIG_ARCH_W90X900 is not set | ||
| 169 | |||
| 170 | # | ||
| 171 | # Intel PXA2xx/PXA3xx Implementations | ||
| 172 | # | ||
| 173 | |||
| 174 | # | ||
| 175 | # Supported PXA3xx Processor Variants | ||
| 176 | # | ||
| 177 | CONFIG_CPU_PXA300=y | ||
| 178 | # CONFIG_CPU_PXA310 is not set | ||
| 179 | # CONFIG_CPU_PXA320 is not set | ||
| 180 | # CONFIG_CPU_PXA930 is not set | ||
| 181 | # CONFIG_CPU_PXA935 is not set | ||
| 182 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 183 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 184 | # CONFIG_ARCH_LUBBOCK is not set | ||
| 185 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
| 186 | # CONFIG_MACH_MAINSTONE is not set | ||
| 187 | # CONFIG_MACH_MP900C is not set | ||
| 188 | # CONFIG_ARCH_PXA_IDP is not set | ||
| 189 | # CONFIG_PXA_SHARPSL is not set | ||
| 190 | # CONFIG_ARCH_VIPER is not set | ||
| 191 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 192 | # CONFIG_TRIZEPS_PXA is not set | ||
| 193 | # CONFIG_MACH_H5000 is not set | ||
| 194 | # CONFIG_MACH_EM_X270 is not set | ||
| 195 | # CONFIG_MACH_COLIBRI is not set | ||
| 196 | CONFIG_MACH_COLIBRI300=y | ||
| 197 | # CONFIG_MACH_ZYLONITE is not set | ||
| 198 | # CONFIG_MACH_LITTLETON is not set | ||
| 199 | # CONFIG_MACH_RAUMFELD_PROTO is not set | ||
| 200 | # CONFIG_MACH_TAVOREVB is not set | ||
| 201 | # CONFIG_MACH_SAAR is not set | ||
| 202 | # CONFIG_MACH_ARMCORE is not set | ||
| 203 | # CONFIG_MACH_CM_X300 is not set | ||
| 204 | # CONFIG_MACH_MAGICIAN is not set | ||
| 205 | # CONFIG_MACH_MIOA701 is not set | ||
| 206 | # CONFIG_MACH_PCM027 is not set | ||
| 207 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 208 | # CONFIG_PXA_EZX is not set | ||
| 209 | CONFIG_PXA3xx=y | ||
| 210 | # CONFIG_PXA_PWM is not set | ||
| 211 | |||
| 212 | # | ||
| 213 | # Processor Type | ||
| 214 | # | ||
| 215 | CONFIG_CPU_32=y | ||
| 216 | CONFIG_CPU_XSC3=y | ||
| 217 | CONFIG_CPU_32v5=y | ||
| 218 | CONFIG_CPU_ABRT_EV5T=y | ||
| 219 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 220 | CONFIG_CPU_CACHE_VIVT=y | ||
| 221 | CONFIG_CPU_TLB_V4WBI=y | ||
| 222 | CONFIG_CPU_CP15=y | ||
| 223 | CONFIG_CPU_CP15_MMU=y | ||
| 224 | CONFIG_IO_36=y | ||
| 225 | |||
| 226 | # | ||
| 227 | # Processor Features | ||
| 228 | # | ||
| 229 | CONFIG_ARM_THUMB=y | ||
| 230 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 231 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 232 | CONFIG_OUTER_CACHE=y | ||
| 233 | CONFIG_CACHE_XSC3L2=y | ||
| 234 | CONFIG_IWMMXT=y | ||
| 235 | CONFIG_COMMON_CLKDEV=y | ||
| 236 | |||
| 237 | # | ||
| 238 | # Bus support | ||
| 239 | # | ||
| 240 | # CONFIG_PCI_SYSCALL is not set | ||
| 241 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 242 | # CONFIG_PCCARD is not set | ||
| 243 | |||
| 244 | # | ||
| 245 | # Kernel Features | ||
| 246 | # | ||
| 247 | CONFIG_TICK_ONESHOT=y | ||
| 248 | # CONFIG_NO_HZ is not set | ||
| 249 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 250 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 251 | CONFIG_VMSPLIT_3G=y | ||
| 252 | # CONFIG_VMSPLIT_2G is not set | ||
| 253 | # CONFIG_VMSPLIT_1G is not set | ||
| 254 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 255 | # CONFIG_PREEMPT is not set | ||
| 256 | CONFIG_HZ=100 | ||
| 257 | CONFIG_AEABI=y | ||
| 258 | CONFIG_OABI_COMPAT=y | ||
| 259 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 260 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 261 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 262 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 263 | CONFIG_FLATMEM_MANUAL=y | ||
| 264 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 265 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 266 | CONFIG_FLATMEM=y | ||
| 267 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 268 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 269 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 270 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 271 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 272 | CONFIG_VIRT_TO_BUS=y | ||
| 273 | CONFIG_UNEVICTABLE_LRU=y | ||
| 274 | CONFIG_ALIGNMENT_TRAP=y | ||
| 275 | |||
| 276 | # | ||
| 277 | # Boot options | ||
| 278 | # | ||
| 279 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
| 280 | CONFIG_ZBOOT_ROM_BSS=0 | ||
| 281 | CONFIG_CMDLINE="console=ttyS0,115200 rw" | ||
| 282 | # CONFIG_XIP_KERNEL is not set | ||
| 283 | # CONFIG_KEXEC is not set | ||
| 284 | |||
| 285 | # | ||
| 286 | # CPU Power Management | ||
| 287 | # | ||
| 288 | # CONFIG_CPU_FREQ is not set | ||
| 289 | CONFIG_CPU_IDLE=y | ||
| 290 | CONFIG_CPU_IDLE_GOV_LADDER=y | ||
| 291 | |||
| 292 | # | ||
| 293 | # Floating point emulation | ||
| 294 | # | ||
| 295 | |||
| 296 | # | ||
| 297 | # At least one emulation must be selected | ||
| 298 | # | ||
| 299 | CONFIG_FPE_NWFPE=y | ||
| 300 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 301 | # CONFIG_FPE_FASTFPE is not set | ||
| 302 | |||
| 303 | # | ||
| 304 | # Userspace binary formats | ||
| 305 | # | ||
| 306 | CONFIG_BINFMT_ELF=y | ||
| 307 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 308 | CONFIG_HAVE_AOUT=y | ||
| 309 | # CONFIG_BINFMT_AOUT is not set | ||
| 310 | # CONFIG_BINFMT_MISC is not set | ||
| 311 | |||
| 312 | # | ||
| 313 | # Power management options | ||
| 314 | # | ||
| 315 | # CONFIG_PM is not set | ||
| 316 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 317 | CONFIG_NET=y | ||
| 318 | |||
| 319 | # | ||
| 320 | # Networking options | ||
| 321 | # | ||
| 322 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 323 | # CONFIG_PACKET is not set | ||
| 324 | CONFIG_UNIX=y | ||
| 325 | CONFIG_XFRM=y | ||
| 326 | # CONFIG_XFRM_USER is not set | ||
| 327 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 328 | # CONFIG_XFRM_MIGRATE is not set | ||
| 329 | # CONFIG_XFRM_STATISTICS is not set | ||
| 330 | # CONFIG_NET_KEY is not set | ||
| 331 | CONFIG_INET=y | ||
| 332 | CONFIG_IP_MULTICAST=y | ||
| 333 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 334 | CONFIG_IP_FIB_HASH=y | ||
| 335 | CONFIG_IP_PNP=y | ||
| 336 | # CONFIG_IP_PNP_DHCP is not set | ||
| 337 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 338 | # CONFIG_IP_PNP_RARP is not set | ||
| 339 | # CONFIG_NET_IPIP is not set | ||
| 340 | # CONFIG_NET_IPGRE is not set | ||
| 341 | # CONFIG_IP_MROUTE is not set | ||
| 342 | # CONFIG_ARPD is not set | ||
| 343 | CONFIG_SYN_COOKIES=y | ||
| 344 | # CONFIG_INET_AH is not set | ||
| 345 | # CONFIG_INET_ESP is not set | ||
| 346 | # CONFIG_INET_IPCOMP is not set | ||
| 347 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 348 | CONFIG_INET_TUNNEL=y | ||
| 349 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 350 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 351 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 352 | # CONFIG_INET_LRO is not set | ||
| 353 | CONFIG_INET_DIAG=y | ||
| 354 | CONFIG_INET_TCP_DIAG=y | ||
| 355 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 356 | CONFIG_TCP_CONG_CUBIC=y | ||
| 357 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 358 | # CONFIG_TCP_MD5SIG is not set | ||
| 359 | CONFIG_IPV6=y | ||
| 360 | # CONFIG_IPV6_PRIVACY is not set | ||
| 361 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 362 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 363 | # CONFIG_INET6_AH is not set | ||
| 364 | # CONFIG_INET6_ESP is not set | ||
| 365 | # CONFIG_INET6_IPCOMP is not set | ||
| 366 | # CONFIG_IPV6_MIP6 is not set | ||
| 367 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 368 | # CONFIG_INET6_TUNNEL is not set | ||
| 369 | CONFIG_INET6_XFRM_MODE_TRANSPORT=y | ||
| 370 | CONFIG_INET6_XFRM_MODE_TUNNEL=y | ||
| 371 | CONFIG_INET6_XFRM_MODE_BEET=y | ||
| 372 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 373 | CONFIG_IPV6_SIT=y | ||
| 374 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 375 | # CONFIG_IPV6_TUNNEL is not set | ||
| 376 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 377 | # CONFIG_IPV6_MROUTE is not set | ||
| 378 | # CONFIG_NETWORK_SECMARK is not set | ||
| 379 | # CONFIG_NETFILTER is not set | ||
| 380 | # CONFIG_IP_DCCP is not set | ||
| 381 | # CONFIG_IP_SCTP is not set | ||
| 382 | # CONFIG_TIPC is not set | ||
| 383 | # CONFIG_ATM is not set | ||
| 384 | # CONFIG_BRIDGE is not set | ||
| 385 | # CONFIG_NET_DSA is not set | ||
| 386 | # CONFIG_VLAN_8021Q is not set | ||
| 387 | # CONFIG_DECNET is not set | ||
| 388 | # CONFIG_LLC2 is not set | ||
| 389 | # CONFIG_IPX is not set | ||
| 390 | # CONFIG_ATALK is not set | ||
| 391 | # CONFIG_X25 is not set | ||
| 392 | # CONFIG_LAPB is not set | ||
| 393 | # CONFIG_ECONET is not set | ||
| 394 | # CONFIG_WAN_ROUTER is not set | ||
| 395 | # CONFIG_NET_SCHED is not set | ||
| 396 | # CONFIG_DCB is not set | ||
| 397 | |||
| 398 | # | ||
| 399 | # Network testing | ||
| 400 | # | ||
| 401 | # CONFIG_NET_PKTGEN is not set | ||
| 402 | # CONFIG_HAMRADIO is not set | ||
| 403 | # CONFIG_CAN is not set | ||
| 404 | # CONFIG_IRDA is not set | ||
| 405 | # CONFIG_BT is not set | ||
| 406 | # CONFIG_AF_RXRPC is not set | ||
| 407 | # CONFIG_PHONET is not set | ||
| 408 | # CONFIG_WIRELESS is not set | ||
| 409 | # CONFIG_WIMAX is not set | ||
| 410 | # CONFIG_RFKILL is not set | ||
| 411 | # CONFIG_NET_9P is not set | ||
| 412 | |||
| 413 | # | ||
| 414 | # Device Drivers | ||
| 415 | # | ||
| 416 | |||
| 417 | # | ||
| 418 | # Generic Driver Options | ||
| 419 | # | ||
| 420 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 421 | CONFIG_STANDALONE=y | ||
| 422 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 423 | CONFIG_FW_LOADER=y | ||
| 424 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 425 | CONFIG_EXTRA_FIRMWARE="" | ||
| 426 | # CONFIG_DEBUG_DRIVER is not set | ||
| 427 | # CONFIG_DEBUG_DEVRES is not set | ||
| 428 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 429 | # CONFIG_CONNECTOR is not set | ||
| 430 | # CONFIG_MTD is not set | ||
| 431 | # CONFIG_PARPORT is not set | ||
| 432 | CONFIG_BLK_DEV=y | ||
| 433 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 434 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 435 | # CONFIG_BLK_DEV_NBD is not set | ||
| 436 | # CONFIG_BLK_DEV_UB is not set | ||
| 437 | # CONFIG_BLK_DEV_RAM is not set | ||
| 438 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 439 | # CONFIG_ATA_OVER_ETH is not set | ||
| 440 | # CONFIG_MISC_DEVICES is not set | ||
| 441 | CONFIG_HAVE_IDE=y | ||
| 442 | # CONFIG_IDE is not set | ||
| 443 | |||
| 444 | # | ||
| 445 | # SCSI device support | ||
| 446 | # | ||
| 447 | # CONFIG_RAID_ATTRS is not set | ||
| 448 | CONFIG_SCSI=y | ||
| 449 | CONFIG_SCSI_DMA=y | ||
| 450 | # CONFIG_SCSI_TGT is not set | ||
| 451 | # CONFIG_SCSI_NETLINK is not set | ||
| 452 | CONFIG_SCSI_PROC_FS=y | ||
| 453 | |||
| 454 | # | ||
| 455 | # SCSI support type (disk, tape, CD-ROM) | ||
| 456 | # | ||
| 457 | CONFIG_BLK_DEV_SD=y | ||
| 458 | # CONFIG_CHR_DEV_ST is not set | ||
| 459 | # CONFIG_CHR_DEV_OSST is not set | ||
| 460 | # CONFIG_BLK_DEV_SR is not set | ||
| 461 | CONFIG_CHR_DEV_SG=y | ||
| 462 | # CONFIG_CHR_DEV_SCH is not set | ||
| 463 | |||
| 464 | # | ||
| 465 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 466 | # | ||
| 467 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 468 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 469 | # CONFIG_SCSI_LOGGING is not set | ||
| 470 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 471 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 472 | |||
| 473 | # | ||
| 474 | # SCSI Transports | ||
| 475 | # | ||
| 476 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 477 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 478 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 479 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 480 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 481 | CONFIG_SCSI_LOWLEVEL=y | ||
| 482 | # CONFIG_ISCSI_TCP is not set | ||
| 483 | # CONFIG_LIBFC is not set | ||
| 484 | # CONFIG_SCSI_DEBUG is not set | ||
| 485 | # CONFIG_SCSI_DH is not set | ||
| 486 | # CONFIG_ATA is not set | ||
| 487 | # CONFIG_MD is not set | ||
| 488 | CONFIG_NETDEVICES=y | ||
| 489 | # CONFIG_DUMMY is not set | ||
| 490 | # CONFIG_BONDING is not set | ||
| 491 | # CONFIG_MACVLAN is not set | ||
| 492 | # CONFIG_EQUALIZER is not set | ||
| 493 | # CONFIG_TUN is not set | ||
| 494 | # CONFIG_VETH is not set | ||
| 495 | # CONFIG_PHYLIB is not set | ||
| 496 | CONFIG_NET_ETHERNET=y | ||
| 497 | CONFIG_MII=y | ||
| 498 | CONFIG_AX88796=y | ||
| 499 | # CONFIG_AX88796_93CX6 is not set | ||
| 500 | # CONFIG_SMC91X is not set | ||
| 501 | # CONFIG_DM9000 is not set | ||
| 502 | # CONFIG_SMC911X is not set | ||
| 503 | # CONFIG_SMSC911X is not set | ||
| 504 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 505 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 506 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 507 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 508 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 509 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 510 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 511 | # CONFIG_B44 is not set | ||
| 512 | # CONFIG_NETDEV_1000 is not set | ||
| 513 | # CONFIG_NETDEV_10000 is not set | ||
| 514 | |||
| 515 | # | ||
| 516 | # Wireless LAN | ||
| 517 | # | ||
| 518 | # CONFIG_WLAN_PRE80211 is not set | ||
| 519 | # CONFIG_WLAN_80211 is not set | ||
| 520 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 521 | |||
| 522 | # | ||
| 523 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 524 | # | ||
| 525 | |||
| 526 | # | ||
| 527 | # USB Network Adapters | ||
| 528 | # | ||
| 529 | # CONFIG_USB_CATC is not set | ||
| 530 | # CONFIG_USB_KAWETH is not set | ||
| 531 | # CONFIG_USB_PEGASUS is not set | ||
| 532 | # CONFIG_USB_RTL8150 is not set | ||
| 533 | # CONFIG_USB_USBNET is not set | ||
| 534 | # CONFIG_WAN is not set | ||
| 535 | # CONFIG_PPP is not set | ||
| 536 | # CONFIG_SLIP is not set | ||
| 537 | # CONFIG_NETCONSOLE is not set | ||
| 538 | # CONFIG_NETPOLL is not set | ||
| 539 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 540 | # CONFIG_ISDN is not set | ||
| 541 | |||
| 542 | # | ||
| 543 | # Input device support | ||
| 544 | # | ||
| 545 | CONFIG_INPUT=y | ||
| 546 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 547 | # CONFIG_INPUT_POLLDEV is not set | ||
| 548 | |||
| 549 | # | ||
| 550 | # Userland interfaces | ||
| 551 | # | ||
| 552 | CONFIG_INPUT_MOUSEDEV=y | ||
| 553 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 554 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 555 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 556 | # CONFIG_INPUT_JOYDEV is not set | ||
| 557 | CONFIG_INPUT_EVDEV=y | ||
| 558 | # CONFIG_INPUT_EVBUG is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Input Device Drivers | ||
| 562 | # | ||
| 563 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 564 | # CONFIG_INPUT_MOUSE is not set | ||
| 565 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 566 | # CONFIG_INPUT_TABLET is not set | ||
| 567 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 568 | CONFIG_INPUT_MISC=y | ||
| 569 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 570 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 571 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 572 | # CONFIG_INPUT_POWERMATE is not set | ||
| 573 | # CONFIG_INPUT_YEALINK is not set | ||
| 574 | # CONFIG_INPUT_CM109 is not set | ||
| 575 | # CONFIG_INPUT_UINPUT is not set | ||
| 576 | CONFIG_INPUT_GPIO_ROTARY_ENCODER=y | ||
| 577 | |||
| 578 | # | ||
| 579 | # Hardware I/O ports | ||
| 580 | # | ||
| 581 | CONFIG_SERIO=y | ||
| 582 | CONFIG_SERIO_SERPORT=y | ||
| 583 | # CONFIG_SERIO_RAW is not set | ||
| 584 | # CONFIG_GAMEPORT is not set | ||
| 585 | |||
| 586 | # | ||
| 587 | # Character devices | ||
| 588 | # | ||
| 589 | CONFIG_VT=y | ||
| 590 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 591 | CONFIG_VT_CONSOLE=y | ||
| 592 | CONFIG_HW_CONSOLE=y | ||
| 593 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 594 | CONFIG_DEVKMEM=y | ||
| 595 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 596 | |||
| 597 | # | ||
| 598 | # Serial drivers | ||
| 599 | # | ||
| 600 | # CONFIG_SERIAL_8250 is not set | ||
| 601 | |||
| 602 | # | ||
| 603 | # Non-8250 serial port support | ||
| 604 | # | ||
| 605 | CONFIG_SERIAL_PXA=y | ||
| 606 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 607 | CONFIG_SERIAL_CORE=y | ||
| 608 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 609 | CONFIG_UNIX98_PTYS=y | ||
| 610 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 611 | CONFIG_LEGACY_PTYS=y | ||
| 612 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 613 | # CONFIG_IPMI_HANDLER is not set | ||
| 614 | CONFIG_HW_RANDOM=y | ||
| 615 | # CONFIG_R3964 is not set | ||
| 616 | # CONFIG_RAW_DRIVER is not set | ||
| 617 | # CONFIG_TCG_TPM is not set | ||
| 618 | # CONFIG_I2C is not set | ||
| 619 | # CONFIG_SPI is not set | ||
| 620 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 621 | CONFIG_GPIOLIB=y | ||
| 622 | CONFIG_DEBUG_GPIO=y | ||
| 623 | # CONFIG_GPIO_SYSFS is not set | ||
| 624 | |||
| 625 | # | ||
| 626 | # Memory mapped GPIO expanders: | ||
| 627 | # | ||
| 628 | |||
| 629 | # | ||
| 630 | # I2C GPIO expanders: | ||
| 631 | # | ||
| 632 | |||
| 633 | # | ||
| 634 | # PCI GPIO expanders: | ||
| 635 | # | ||
| 636 | |||
| 637 | # | ||
| 638 | # SPI GPIO expanders: | ||
| 639 | # | ||
| 640 | # CONFIG_W1 is not set | ||
| 641 | # CONFIG_POWER_SUPPLY is not set | ||
| 642 | # CONFIG_HWMON is not set | ||
| 643 | # CONFIG_THERMAL is not set | ||
| 644 | # CONFIG_THERMAL_HWMON is not set | ||
| 645 | # CONFIG_WATCHDOG is not set | ||
| 646 | CONFIG_SSB_POSSIBLE=y | ||
| 647 | |||
| 648 | # | ||
| 649 | # Sonics Silicon Backplane | ||
| 650 | # | ||
| 651 | # CONFIG_SSB is not set | ||
| 652 | |||
| 653 | # | ||
| 654 | # Multifunction device drivers | ||
| 655 | # | ||
| 656 | # CONFIG_MFD_CORE is not set | ||
| 657 | # CONFIG_MFD_SM501 is not set | ||
| 658 | # CONFIG_MFD_ASIC3 is not set | ||
| 659 | # CONFIG_HTC_EGPIO is not set | ||
| 660 | # CONFIG_HTC_PASIC3 is not set | ||
| 661 | # CONFIG_MFD_TMIO is not set | ||
| 662 | # CONFIG_MFD_T7L66XB is not set | ||
| 663 | # CONFIG_MFD_TC6387XB is not set | ||
| 664 | # CONFIG_MFD_TC6393XB is not set | ||
| 665 | |||
| 666 | # | ||
| 667 | # Multimedia devices | ||
| 668 | # | ||
| 669 | |||
| 670 | # | ||
| 671 | # Multimedia core support | ||
| 672 | # | ||
| 673 | # CONFIG_VIDEO_DEV is not set | ||
| 674 | # CONFIG_DVB_CORE is not set | ||
| 675 | # CONFIG_VIDEO_MEDIA is not set | ||
| 676 | |||
| 677 | # | ||
| 678 | # Multimedia drivers | ||
| 679 | # | ||
| 680 | # CONFIG_DAB is not set | ||
| 681 | |||
| 682 | # | ||
| 683 | # Graphics support | ||
| 684 | # | ||
| 685 | # CONFIG_VGASTATE is not set | ||
| 686 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 687 | CONFIG_FB=y | ||
| 688 | # CONFIG_FIRMWARE_EDID is not set | ||
| 689 | # CONFIG_FB_DDC is not set | ||
| 690 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 691 | CONFIG_FB_CFB_FILLRECT=y | ||
| 692 | CONFIG_FB_CFB_COPYAREA=y | ||
| 693 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 694 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 695 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 696 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 697 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 698 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 699 | # CONFIG_FB_SYS_FOPS is not set | ||
| 700 | # CONFIG_FB_SVGALIB is not set | ||
| 701 | # CONFIG_FB_MACMODES is not set | ||
| 702 | # CONFIG_FB_BACKLIGHT is not set | ||
| 703 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 704 | # CONFIG_FB_TILEBLITTING is not set | ||
| 705 | |||
| 706 | # | ||
| 707 | # Frame buffer hardware drivers | ||
| 708 | # | ||
| 709 | # CONFIG_FB_S1D13XXX is not set | ||
| 710 | CONFIG_FB_PXA=y | ||
| 711 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 712 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 713 | # CONFIG_FB_PXA_PARAMETERS is not set | ||
| 714 | # CONFIG_FB_MBX is not set | ||
| 715 | # CONFIG_FB_W100 is not set | ||
| 716 | # CONFIG_FB_VIRTUAL is not set | ||
| 717 | # CONFIG_FB_METRONOME is not set | ||
| 718 | # CONFIG_FB_MB862XX is not set | ||
| 719 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 720 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 721 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 722 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 723 | |||
| 724 | # | ||
| 725 | # Display device support | ||
| 726 | # | ||
| 727 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 728 | |||
| 729 | # | ||
| 730 | # Console display driver support | ||
| 731 | # | ||
| 732 | # CONFIG_VGA_CONSOLE is not set | ||
| 733 | CONFIG_DUMMY_CONSOLE=y | ||
| 734 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 735 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 736 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 737 | # CONFIG_FONTS is not set | ||
| 738 | CONFIG_FONT_8x8=y | ||
| 739 | CONFIG_FONT_8x16=y | ||
| 740 | CONFIG_LOGO=y | ||
| 741 | CONFIG_LOGO_LINUX_MONO=y | ||
| 742 | CONFIG_LOGO_LINUX_VGA16=y | ||
| 743 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 744 | # CONFIG_SOUND is not set | ||
| 745 | # CONFIG_HID_SUPPORT is not set | ||
| 746 | CONFIG_USB_SUPPORT=y | ||
| 747 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 748 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 749 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 750 | CONFIG_USB=y | ||
| 751 | CONFIG_USB_DEBUG=y | ||
| 752 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 753 | |||
| 754 | # | ||
| 755 | # Miscellaneous USB options | ||
| 756 | # | ||
| 757 | CONFIG_USB_DEVICEFS=y | ||
| 758 | CONFIG_USB_DEVICE_CLASS=y | ||
| 759 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 760 | # CONFIG_USB_OTG is not set | ||
| 761 | CONFIG_USB_MON=y | ||
| 762 | # CONFIG_USB_WUSB is not set | ||
| 763 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 764 | |||
| 765 | # | ||
| 766 | # USB Host Controller Drivers | ||
| 767 | # | ||
| 768 | # CONFIG_USB_C67X00_HCD is not set | ||
| 769 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 770 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 771 | # CONFIG_USB_OHCI_HCD is not set | ||
| 772 | # CONFIG_USB_SL811_HCD is not set | ||
| 773 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 774 | # CONFIG_USB_HWA_HCD is not set | ||
| 775 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 776 | |||
| 777 | # | ||
| 778 | # USB Device Class drivers | ||
| 779 | # | ||
| 780 | # CONFIG_USB_ACM is not set | ||
| 781 | # CONFIG_USB_PRINTER is not set | ||
| 782 | # CONFIG_USB_WDM is not set | ||
| 783 | # CONFIG_USB_TMC is not set | ||
| 784 | |||
| 785 | # | ||
| 786 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 787 | # | ||
| 788 | |||
| 789 | # | ||
| 790 | # see USB_STORAGE Help for more information | ||
| 791 | # | ||
| 792 | CONFIG_USB_STORAGE=y | ||
| 793 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 794 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 795 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 796 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 797 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 798 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 799 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 800 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 801 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 802 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 803 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 804 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 805 | # CONFIG_USB_LIBUSUAL is not set | ||
| 806 | |||
| 807 | # | ||
| 808 | # USB Imaging devices | ||
| 809 | # | ||
| 810 | # CONFIG_USB_MDC800 is not set | ||
| 811 | # CONFIG_USB_MICROTEK is not set | ||
| 812 | |||
| 813 | # | ||
| 814 | # USB port drivers | ||
| 815 | # | ||
| 816 | # CONFIG_USB_SERIAL is not set | ||
| 817 | |||
| 818 | # | ||
| 819 | # USB Miscellaneous drivers | ||
| 820 | # | ||
| 821 | # CONFIG_USB_EMI62 is not set | ||
| 822 | # CONFIG_USB_EMI26 is not set | ||
| 823 | # CONFIG_USB_ADUTUX is not set | ||
| 824 | # CONFIG_USB_SEVSEG is not set | ||
| 825 | # CONFIG_USB_RIO500 is not set | ||
| 826 | # CONFIG_USB_LEGOTOWER is not set | ||
| 827 | # CONFIG_USB_LCD is not set | ||
| 828 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 829 | # CONFIG_USB_LED is not set | ||
| 830 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 831 | # CONFIG_USB_CYTHERM is not set | ||
| 832 | # CONFIG_USB_PHIDGET is not set | ||
| 833 | # CONFIG_USB_IDMOUSE is not set | ||
| 834 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 835 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 836 | # CONFIG_USB_LD is not set | ||
| 837 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 838 | # CONFIG_USB_IOWARRIOR is not set | ||
| 839 | # CONFIG_USB_TEST is not set | ||
| 840 | # CONFIG_USB_ISIGHTFW is not set | ||
| 841 | # CONFIG_USB_VST is not set | ||
| 842 | # CONFIG_USB_GADGET is not set | ||
| 843 | |||
| 844 | # | ||
| 845 | # OTG and related infrastructure | ||
| 846 | # | ||
| 847 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 848 | CONFIG_MMC=y | ||
| 849 | # CONFIG_MMC_DEBUG is not set | ||
| 850 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 851 | |||
| 852 | # | ||
| 853 | # MMC/SD/SDIO Card Drivers | ||
| 854 | # | ||
| 855 | CONFIG_MMC_BLOCK=y | ||
| 856 | # CONFIG_MMC_BLOCK_BOUNCE is not set | ||
| 857 | # CONFIG_SDIO_UART is not set | ||
| 858 | # CONFIG_MMC_TEST is not set | ||
| 859 | |||
| 860 | # | ||
| 861 | # MMC/SD/SDIO Host Controller Drivers | ||
| 862 | # | ||
| 863 | CONFIG_MMC_PXA=y | ||
| 864 | # CONFIG_MMC_SDHCI is not set | ||
| 865 | # CONFIG_MEMSTICK is not set | ||
| 866 | # CONFIG_ACCESSIBILITY is not set | ||
| 867 | # CONFIG_NEW_LEDS is not set | ||
| 868 | CONFIG_RTC_LIB=y | ||
| 869 | # CONFIG_RTC_CLASS is not set | ||
| 870 | # CONFIG_DMADEVICES is not set | ||
| 871 | # CONFIG_REGULATOR is not set | ||
| 872 | # CONFIG_UIO is not set | ||
| 873 | # CONFIG_STAGING is not set | ||
| 874 | |||
| 875 | # | ||
| 876 | # File systems | ||
| 877 | # | ||
| 878 | # CONFIG_EXT2_FS is not set | ||
| 879 | CONFIG_EXT3_FS=y | ||
| 880 | CONFIG_EXT3_FS_XATTR=y | ||
| 881 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 882 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 883 | # CONFIG_EXT4_FS is not set | ||
| 884 | CONFIG_JBD=y | ||
| 885 | CONFIG_FS_MBCACHE=y | ||
| 886 | # CONFIG_REISERFS_FS is not set | ||
| 887 | # CONFIG_JFS_FS is not set | ||
| 888 | # CONFIG_FS_POSIX_ACL is not set | ||
| 889 | CONFIG_FILE_LOCKING=y | ||
| 890 | # CONFIG_XFS_FS is not set | ||
| 891 | # CONFIG_OCFS2_FS is not set | ||
| 892 | # CONFIG_BTRFS_FS is not set | ||
| 893 | CONFIG_DNOTIFY=y | ||
| 894 | CONFIG_INOTIFY=y | ||
| 895 | CONFIG_INOTIFY_USER=y | ||
| 896 | # CONFIG_QUOTA is not set | ||
| 897 | # CONFIG_AUTOFS_FS is not set | ||
| 898 | # CONFIG_AUTOFS4_FS is not set | ||
| 899 | # CONFIG_FUSE_FS is not set | ||
| 900 | |||
| 901 | # | ||
| 902 | # CD-ROM/DVD Filesystems | ||
| 903 | # | ||
| 904 | # CONFIG_ISO9660_FS is not set | ||
| 905 | # CONFIG_UDF_FS is not set | ||
| 906 | |||
| 907 | # | ||
| 908 | # DOS/FAT/NT Filesystems | ||
| 909 | # | ||
| 910 | # CONFIG_MSDOS_FS is not set | ||
| 911 | # CONFIG_VFAT_FS is not set | ||
| 912 | # CONFIG_NTFS_FS is not set | ||
| 913 | |||
| 914 | # | ||
| 915 | # Pseudo filesystems | ||
| 916 | # | ||
| 917 | CONFIG_PROC_FS=y | ||
| 918 | CONFIG_PROC_SYSCTL=y | ||
| 919 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 920 | CONFIG_SYSFS=y | ||
| 921 | # CONFIG_TMPFS is not set | ||
| 922 | # CONFIG_HUGETLB_PAGE is not set | ||
| 923 | # CONFIG_CONFIGFS_FS is not set | ||
| 924 | CONFIG_MISC_FILESYSTEMS=y | ||
| 925 | # CONFIG_ADFS_FS is not set | ||
| 926 | # CONFIG_AFFS_FS is not set | ||
| 927 | # CONFIG_HFS_FS is not set | ||
| 928 | # CONFIG_HFSPLUS_FS is not set | ||
| 929 | # CONFIG_BEFS_FS is not set | ||
| 930 | # CONFIG_BFS_FS is not set | ||
| 931 | # CONFIG_EFS_FS is not set | ||
| 932 | # CONFIG_CRAMFS is not set | ||
| 933 | # CONFIG_SQUASHFS is not set | ||
| 934 | # CONFIG_VXFS_FS is not set | ||
| 935 | # CONFIG_MINIX_FS is not set | ||
| 936 | # CONFIG_OMFS_FS is not set | ||
| 937 | # CONFIG_HPFS_FS is not set | ||
| 938 | # CONFIG_QNX4FS_FS is not set | ||
| 939 | # CONFIG_ROMFS_FS is not set | ||
| 940 | # CONFIG_SYSV_FS is not set | ||
| 941 | # CONFIG_UFS_FS is not set | ||
| 942 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 943 | CONFIG_NFS_FS=y | ||
| 944 | CONFIG_NFS_V3=y | ||
| 945 | # CONFIG_NFS_V3_ACL is not set | ||
| 946 | # CONFIG_NFS_V4 is not set | ||
| 947 | CONFIG_ROOT_NFS=y | ||
| 948 | # CONFIG_NFSD is not set | ||
| 949 | CONFIG_LOCKD=y | ||
| 950 | CONFIG_LOCKD_V4=y | ||
| 951 | CONFIG_NFS_COMMON=y | ||
| 952 | CONFIG_SUNRPC=y | ||
| 953 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 954 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 955 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 956 | # CONFIG_SMB_FS is not set | ||
| 957 | # CONFIG_CIFS is not set | ||
| 958 | # CONFIG_NCP_FS is not set | ||
| 959 | # CONFIG_CODA_FS is not set | ||
| 960 | # CONFIG_AFS_FS is not set | ||
| 961 | |||
| 962 | # | ||
| 963 | # Partition Types | ||
| 964 | # | ||
| 965 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 966 | CONFIG_MSDOS_PARTITION=y | ||
| 967 | # CONFIG_NLS is not set | ||
| 968 | # CONFIG_DLM is not set | ||
| 969 | |||
| 970 | # | ||
| 971 | # Kernel hacking | ||
| 972 | # | ||
| 973 | CONFIG_PRINTK_TIME=y | ||
| 974 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 975 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 976 | CONFIG_FRAME_WARN=1024 | ||
| 977 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 978 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 979 | # CONFIG_DEBUG_FS is not set | ||
| 980 | # CONFIG_HEADERS_CHECK is not set | ||
| 981 | CONFIG_DEBUG_KERNEL=y | ||
| 982 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 983 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 984 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 985 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 986 | CONFIG_SCHED_DEBUG=y | ||
| 987 | # CONFIG_SCHEDSTATS is not set | ||
| 988 | # CONFIG_TIMER_STATS is not set | ||
| 989 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 990 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 991 | # CONFIG_SLUB_STATS is not set | ||
| 992 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 993 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 994 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 995 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 996 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 997 | # CONFIG_PROVE_LOCKING is not set | ||
| 998 | # CONFIG_LOCK_STAT is not set | ||
| 999 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1000 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1001 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1002 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1003 | CONFIG_DEBUG_INFO=y | ||
| 1004 | # CONFIG_DEBUG_VM is not set | ||
| 1005 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1006 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1007 | # CONFIG_DEBUG_LIST is not set | ||
| 1008 | # CONFIG_DEBUG_SG is not set | ||
| 1009 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1010 | CONFIG_FRAME_POINTER=y | ||
| 1011 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1012 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1013 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1014 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1015 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1016 | # CONFIG_FAULT_INJECTION is not set | ||
| 1017 | # CONFIG_LATENCYTOP is not set | ||
| 1018 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1019 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1020 | |||
| 1021 | # | ||
| 1022 | # Tracers | ||
| 1023 | # | ||
| 1024 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1025 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1026 | # CONFIG_SCHED_TRACER is not set | ||
| 1027 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1028 | # CONFIG_BOOT_TRACER is not set | ||
| 1029 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1030 | # CONFIG_STACK_TRACER is not set | ||
| 1031 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1032 | # CONFIG_SAMPLES is not set | ||
| 1033 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1034 | # CONFIG_KGDB is not set | ||
| 1035 | CONFIG_DEBUG_USER=y | ||
| 1036 | CONFIG_DEBUG_ERRORS=y | ||
| 1037 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1038 | CONFIG_DEBUG_LL=y | ||
| 1039 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1040 | |||
| 1041 | # | ||
| 1042 | # Security options | ||
| 1043 | # | ||
| 1044 | # CONFIG_KEYS is not set | ||
| 1045 | # CONFIG_SECURITY is not set | ||
| 1046 | # CONFIG_SECURITYFS is not set | ||
| 1047 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1048 | CONFIG_CRYPTO=y | ||
| 1049 | |||
| 1050 | # | ||
| 1051 | # Crypto core or helper | ||
| 1052 | # | ||
| 1053 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1054 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1055 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1056 | CONFIG_CRYPTO_AEAD2=y | ||
| 1057 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1058 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1059 | CONFIG_CRYPTO_HASH2=y | ||
| 1060 | CONFIG_CRYPTO_RNG2=y | ||
| 1061 | CONFIG_CRYPTO_MANAGER=y | ||
| 1062 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1063 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1064 | # CONFIG_CRYPTO_NULL is not set | ||
| 1065 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1066 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1067 | # CONFIG_CRYPTO_TEST is not set | ||
| 1068 | |||
| 1069 | # | ||
| 1070 | # Authenticated Encryption with Associated Data | ||
| 1071 | # | ||
| 1072 | # CONFIG_CRYPTO_CCM is not set | ||
| 1073 | # CONFIG_CRYPTO_GCM is not set | ||
| 1074 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1075 | |||
| 1076 | # | ||
| 1077 | # Block modes | ||
| 1078 | # | ||
| 1079 | # CONFIG_CRYPTO_CBC is not set | ||
| 1080 | # CONFIG_CRYPTO_CTR is not set | ||
| 1081 | # CONFIG_CRYPTO_CTS is not set | ||
| 1082 | CONFIG_CRYPTO_ECB=y | ||
| 1083 | # CONFIG_CRYPTO_LRW is not set | ||
| 1084 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1085 | # CONFIG_CRYPTO_XTS is not set | ||
| 1086 | |||
| 1087 | # | ||
| 1088 | # Hash modes | ||
| 1089 | # | ||
| 1090 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1091 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1092 | |||
| 1093 | # | ||
| 1094 | # Digest | ||
| 1095 | # | ||
| 1096 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1097 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1098 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1099 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1100 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1101 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1102 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1103 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1104 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1105 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1106 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1107 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1108 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1109 | |||
| 1110 | # | ||
| 1111 | # Ciphers | ||
| 1112 | # | ||
| 1113 | CONFIG_CRYPTO_AES=y | ||
| 1114 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1115 | CONFIG_CRYPTO_ARC4=y | ||
| 1116 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1117 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1118 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1119 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1120 | # CONFIG_CRYPTO_DES is not set | ||
| 1121 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1122 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1123 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1124 | # CONFIG_CRYPTO_SEED is not set | ||
| 1125 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1126 | # CONFIG_CRYPTO_TEA is not set | ||
| 1127 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1128 | |||
| 1129 | # | ||
| 1130 | # Compression | ||
| 1131 | # | ||
| 1132 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1133 | # CONFIG_CRYPTO_LZO is not set | ||
| 1134 | |||
| 1135 | # | ||
| 1136 | # Random Number Generation | ||
| 1137 | # | ||
| 1138 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1139 | CONFIG_CRYPTO_HW=y | ||
| 1140 | |||
| 1141 | # | ||
| 1142 | # Library routines | ||
| 1143 | # | ||
| 1144 | CONFIG_BITREVERSE=y | ||
| 1145 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1146 | # CONFIG_CRC_CCITT is not set | ||
| 1147 | # CONFIG_CRC16 is not set | ||
| 1148 | # CONFIG_CRC_T10DIF is not set | ||
| 1149 | # CONFIG_CRC_ITU_T is not set | ||
| 1150 | CONFIG_CRC32=y | ||
| 1151 | # CONFIG_CRC7 is not set | ||
| 1152 | # CONFIG_LIBCRC32C is not set | ||
| 1153 | CONFIG_PLIST=y | ||
| 1154 | CONFIG_HAS_IOMEM=y | ||
| 1155 | CONFIG_HAS_IOPORT=y | ||
| 1156 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig index f7622e658163..1aa62249031b 100644 --- a/arch/arm/configs/collie_defconfig +++ b/arch/arm/configs/collie_defconfig | |||
| @@ -113,7 +113,6 @@ CONFIG_ARCH_SA1100=y | |||
| 113 | CONFIG_SA1100_COLLIE=y | 113 | CONFIG_SA1100_COLLIE=y |
| 114 | # CONFIG_SA1100_H3100 is not set | 114 | # CONFIG_SA1100_H3100 is not set |
| 115 | # CONFIG_SA1100_H3600 is not set | 115 | # CONFIG_SA1100_H3600 is not set |
| 116 | # CONFIG_SA1100_H3800 is not set | ||
| 117 | # CONFIG_SA1100_BADGE4 is not set | 116 | # CONFIG_SA1100_BADGE4 is not set |
| 118 | # CONFIG_SA1100_JORNADA720 is not set | 117 | # CONFIG_SA1100_JORNADA720 is not set |
| 119 | # CONFIG_SA1100_HACKKIT is not set | 118 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig new file mode 100644 index 000000000000..e9955b786c80 --- /dev/null +++ b/arch/arm/configs/em_x270_defconfig | |||
| @@ -0,0 +1,1741 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc2 | ||
| 4 | # Sun Feb 1 16:43:31 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | CONFIG_IKCONFIG=y | ||
| 46 | CONFIG_IKCONFIG_PROC=y | ||
| 47 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 48 | CONFIG_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 50 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 51 | CONFIG_USER_SCHED=y | ||
| 52 | # CONFIG_CGROUP_SCHED is not set | ||
| 53 | # CONFIG_CGROUPS is not set | ||
| 54 | CONFIG_SYSFS_DEPRECATED=y | ||
| 55 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 56 | # CONFIG_RELAY is not set | ||
| 57 | # CONFIG_NAMESPACES is not set | ||
| 58 | CONFIG_BLK_DEV_INITRD=y | ||
| 59 | CONFIG_INITRAMFS_SOURCE="" | ||
| 60 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 61 | CONFIG_SYSCTL=y | ||
| 62 | CONFIG_EMBEDDED=y | ||
| 63 | CONFIG_UID16=y | ||
| 64 | CONFIG_SYSCTL_SYSCALL=y | ||
| 65 | CONFIG_KALLSYMS=y | ||
| 66 | # CONFIG_KALLSYMS_ALL is not set | ||
| 67 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 68 | CONFIG_HOTPLUG=y | ||
| 69 | CONFIG_PRINTK=y | ||
| 70 | CONFIG_BUG=y | ||
| 71 | CONFIG_ELF_CORE=y | ||
| 72 | # CONFIG_COMPAT_BRK is not set | ||
| 73 | CONFIG_BASE_FULL=y | ||
| 74 | CONFIG_FUTEX=y | ||
| 75 | CONFIG_ANON_INODES=y | ||
| 76 | CONFIG_EPOLL=y | ||
| 77 | CONFIG_SIGNALFD=y | ||
| 78 | CONFIG_TIMERFD=y | ||
| 79 | CONFIG_EVENTFD=y | ||
| 80 | CONFIG_SHMEM=y | ||
| 81 | CONFIG_AIO=y | ||
| 82 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 83 | # CONFIG_SLUB_DEBUG is not set | ||
| 84 | # CONFIG_SLAB is not set | ||
| 85 | CONFIG_SLUB=y | ||
| 86 | # CONFIG_SLOB is not set | ||
| 87 | # CONFIG_PROFILING is not set | ||
| 88 | CONFIG_HAVE_OPROFILE=y | ||
| 89 | # CONFIG_KPROBES is not set | ||
| 90 | CONFIG_HAVE_KPROBES=y | ||
| 91 | CONFIG_HAVE_KRETPROBES=y | ||
| 92 | CONFIG_HAVE_CLK=y | ||
| 93 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 94 | CONFIG_RT_MUTEXES=y | ||
| 95 | CONFIG_BASE_SMALL=0 | ||
| 96 | CONFIG_MODULES=y | ||
| 97 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 98 | CONFIG_MODULE_UNLOAD=y | ||
| 99 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 100 | # CONFIG_MODVERSIONS is not set | ||
| 101 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 102 | CONFIG_BLOCK=y | ||
| 103 | # CONFIG_LBD is not set | ||
| 104 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 105 | # CONFIG_BLK_DEV_BSG is not set | ||
| 106 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 107 | |||
| 108 | # | ||
| 109 | # IO Schedulers | ||
| 110 | # | ||
| 111 | CONFIG_IOSCHED_NOOP=y | ||
| 112 | CONFIG_IOSCHED_AS=y | ||
| 113 | CONFIG_IOSCHED_DEADLINE=y | ||
| 114 | CONFIG_IOSCHED_CFQ=y | ||
| 115 | # CONFIG_DEFAULT_AS is not set | ||
| 116 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 117 | CONFIG_DEFAULT_CFQ=y | ||
| 118 | # CONFIG_DEFAULT_NOOP is not set | ||
| 119 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 120 | CONFIG_CLASSIC_RCU=y | ||
| 121 | # CONFIG_TREE_RCU is not set | ||
| 122 | # CONFIG_PREEMPT_RCU is not set | ||
| 123 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 124 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 125 | CONFIG_FREEZER=y | ||
| 126 | |||
| 127 | # | ||
| 128 | # System Type | ||
| 129 | # | ||
| 130 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 131 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 132 | # CONFIG_ARCH_REALVIEW is not set | ||
| 133 | # CONFIG_ARCH_VERSATILE is not set | ||
| 134 | # CONFIG_ARCH_AT91 is not set | ||
| 135 | # CONFIG_ARCH_CLPS711X is not set | ||
| 136 | # CONFIG_ARCH_EBSA110 is not set | ||
| 137 | # CONFIG_ARCH_EP93XX is not set | ||
| 138 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 139 | # CONFIG_ARCH_NETX is not set | ||
| 140 | # CONFIG_ARCH_H720X is not set | ||
| 141 | # CONFIG_ARCH_IMX is not set | ||
| 142 | # CONFIG_ARCH_IOP13XX is not set | ||
| 143 | # CONFIG_ARCH_IOP32X is not set | ||
| 144 | # CONFIG_ARCH_IOP33X is not set | ||
| 145 | # CONFIG_ARCH_IXP23XX is not set | ||
| 146 | # CONFIG_ARCH_IXP2000 is not set | ||
| 147 | # CONFIG_ARCH_IXP4XX is not set | ||
| 148 | # CONFIG_ARCH_L7200 is not set | ||
| 149 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 150 | # CONFIG_ARCH_KS8695 is not set | ||
| 151 | # CONFIG_ARCH_NS9XXX is not set | ||
| 152 | # CONFIG_ARCH_LOKI is not set | ||
| 153 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 154 | # CONFIG_ARCH_MXC is not set | ||
| 155 | # CONFIG_ARCH_ORION5X is not set | ||
| 156 | # CONFIG_ARCH_PNX4008 is not set | ||
| 157 | CONFIG_ARCH_PXA=y | ||
| 158 | # CONFIG_ARCH_RPC is not set | ||
| 159 | # CONFIG_ARCH_SA1100 is not set | ||
| 160 | # CONFIG_ARCH_S3C2410 is not set | ||
| 161 | # CONFIG_ARCH_S3C64XX is not set | ||
| 162 | # CONFIG_ARCH_SHARK is not set | ||
| 163 | # CONFIG_ARCH_LH7A40X is not set | ||
| 164 | # CONFIG_ARCH_DAVINCI is not set | ||
| 165 | # CONFIG_ARCH_OMAP is not set | ||
| 166 | # CONFIG_ARCH_MSM is not set | ||
| 167 | # CONFIG_ARCH_W90X900 is not set | ||
| 168 | |||
| 169 | # | ||
| 170 | # Intel PXA2xx/PXA3xx Implementations | ||
| 171 | # | ||
| 172 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 173 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 174 | # CONFIG_ARCH_LUBBOCK is not set | ||
| 175 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
| 176 | # CONFIG_MACH_MAINSTONE is not set | ||
| 177 | # CONFIG_MACH_MP900C is not set | ||
| 178 | # CONFIG_ARCH_PXA_IDP is not set | ||
| 179 | # CONFIG_PXA_SHARPSL is not set | ||
| 180 | # CONFIG_ARCH_VIPER is not set | ||
| 181 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 182 | # CONFIG_TRIZEPS_PXA is not set | ||
| 183 | # CONFIG_MACH_H5000 is not set | ||
| 184 | CONFIG_MACH_EM_X270=y | ||
| 185 | CONFIG_MACH_EXEDA=y | ||
| 186 | # CONFIG_MACH_COLIBRI is not set | ||
| 187 | # CONFIG_MACH_ZYLONITE is not set | ||
| 188 | # CONFIG_MACH_LITTLETON is not set | ||
| 189 | # CONFIG_MACH_TAVOREVB is not set | ||
| 190 | # CONFIG_MACH_SAAR is not set | ||
| 191 | # CONFIG_MACH_ARMCORE is not set | ||
| 192 | # CONFIG_MACH_CM_X300 is not set | ||
| 193 | # CONFIG_MACH_MAGICIAN is not set | ||
| 194 | # CONFIG_MACH_MIOA701 is not set | ||
| 195 | # CONFIG_MACH_PCM027 is not set | ||
| 196 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 197 | # CONFIG_PXA_EZX is not set | ||
| 198 | CONFIG_PXA27x=y | ||
| 199 | CONFIG_PXA_SSP=y | ||
| 200 | # CONFIG_PXA_PWM is not set | ||
| 201 | |||
| 202 | # | ||
| 203 | # Processor Type | ||
| 204 | # | ||
| 205 | CONFIG_CPU_32=y | ||
| 206 | CONFIG_CPU_XSCALE=y | ||
| 207 | CONFIG_CPU_32v5=y | ||
| 208 | CONFIG_CPU_ABRT_EV5T=y | ||
| 209 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 210 | CONFIG_CPU_CACHE_VIVT=y | ||
| 211 | CONFIG_CPU_TLB_V4WBI=y | ||
| 212 | CONFIG_CPU_CP15=y | ||
| 213 | CONFIG_CPU_CP15_MMU=y | ||
| 214 | |||
| 215 | # | ||
| 216 | # Processor Features | ||
| 217 | # | ||
| 218 | CONFIG_ARM_THUMB=y | ||
| 219 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 220 | # CONFIG_OUTER_CACHE is not set | ||
| 221 | CONFIG_IWMMXT=y | ||
| 222 | CONFIG_XSCALE_PMU=y | ||
| 223 | CONFIG_COMMON_CLKDEV=y | ||
| 224 | |||
| 225 | # | ||
| 226 | # Bus support | ||
| 227 | # | ||
| 228 | # CONFIG_PCI_SYSCALL is not set | ||
| 229 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 230 | # CONFIG_PCCARD is not set | ||
| 231 | |||
| 232 | # | ||
| 233 | # Kernel Features | ||
| 234 | # | ||
| 235 | CONFIG_TICK_ONESHOT=y | ||
| 236 | CONFIG_NO_HZ=y | ||
| 237 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 238 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 239 | CONFIG_VMSPLIT_3G=y | ||
| 240 | # CONFIG_VMSPLIT_2G is not set | ||
| 241 | # CONFIG_VMSPLIT_1G is not set | ||
| 242 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 243 | # CONFIG_PREEMPT is not set | ||
| 244 | CONFIG_HZ=100 | ||
| 245 | CONFIG_AEABI=y | ||
| 246 | CONFIG_OABI_COMPAT=y | ||
| 247 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 248 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 249 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 250 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 251 | CONFIG_FLATMEM_MANUAL=y | ||
| 252 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 253 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 254 | CONFIG_FLATMEM=y | ||
| 255 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 256 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 257 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 258 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 259 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 260 | CONFIG_VIRT_TO_BUS=y | ||
| 261 | CONFIG_UNEVICTABLE_LRU=y | ||
| 262 | CONFIG_ALIGNMENT_TRAP=y | ||
| 263 | |||
| 264 | # | ||
| 265 | # Boot options | ||
| 266 | # | ||
| 267 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 268 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 269 | CONFIG_CMDLINE="root=1f03 mem=32M" | ||
| 270 | # CONFIG_XIP_KERNEL is not set | ||
| 271 | # CONFIG_KEXEC is not set | ||
| 272 | |||
| 273 | # | ||
| 274 | # CPU Power Management | ||
| 275 | # | ||
| 276 | CONFIG_CPU_FREQ=y | ||
| 277 | CONFIG_CPU_FREQ_TABLE=y | ||
| 278 | # CONFIG_CPU_FREQ_DEBUG is not set | ||
| 279 | CONFIG_CPU_FREQ_STAT=y | ||
| 280 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | ||
| 281 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
| 282 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 283 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
| 284 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
| 285 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
| 286 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
| 287 | # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set | ||
| 288 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | ||
| 289 | # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set | ||
| 290 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | ||
| 291 | # CONFIG_CPU_IDLE is not set | ||
| 292 | |||
| 293 | # | ||
| 294 | # Floating point emulation | ||
| 295 | # | ||
| 296 | |||
| 297 | # | ||
| 298 | # At least one emulation must be selected | ||
| 299 | # | ||
| 300 | CONFIG_FPE_NWFPE=y | ||
| 301 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 302 | # CONFIG_FPE_FASTFPE is not set | ||
| 303 | |||
| 304 | # | ||
| 305 | # Userspace binary formats | ||
| 306 | # | ||
| 307 | CONFIG_BINFMT_ELF=y | ||
| 308 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 309 | CONFIG_HAVE_AOUT=y | ||
| 310 | # CONFIG_BINFMT_AOUT is not set | ||
| 311 | # CONFIG_BINFMT_MISC is not set | ||
| 312 | |||
| 313 | # | ||
| 314 | # Power management options | ||
| 315 | # | ||
| 316 | CONFIG_PM=y | ||
| 317 | # CONFIG_PM_DEBUG is not set | ||
| 318 | CONFIG_PM_SLEEP=y | ||
| 319 | CONFIG_SUSPEND=y | ||
| 320 | CONFIG_SUSPEND_FREEZER=y | ||
| 321 | CONFIG_APM_EMULATION=y | ||
| 322 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 323 | CONFIG_NET=y | ||
| 324 | |||
| 325 | # | ||
| 326 | # Networking options | ||
| 327 | # | ||
| 328 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 329 | CONFIG_PACKET=y | ||
| 330 | CONFIG_PACKET_MMAP=y | ||
| 331 | CONFIG_UNIX=y | ||
| 332 | CONFIG_XFRM=y | ||
| 333 | # CONFIG_XFRM_USER is not set | ||
| 334 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 335 | # CONFIG_XFRM_MIGRATE is not set | ||
| 336 | # CONFIG_XFRM_STATISTICS is not set | ||
| 337 | # CONFIG_NET_KEY is not set | ||
| 338 | CONFIG_INET=y | ||
| 339 | CONFIG_IP_MULTICAST=y | ||
| 340 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 341 | CONFIG_IP_FIB_HASH=y | ||
| 342 | CONFIG_IP_PNP=y | ||
| 343 | CONFIG_IP_PNP_DHCP=y | ||
| 344 | CONFIG_IP_PNP_BOOTP=y | ||
| 345 | # CONFIG_IP_PNP_RARP is not set | ||
| 346 | # CONFIG_NET_IPIP is not set | ||
| 347 | # CONFIG_NET_IPGRE is not set | ||
| 348 | # CONFIG_IP_MROUTE is not set | ||
| 349 | # CONFIG_ARPD is not set | ||
| 350 | # CONFIG_SYN_COOKIES is not set | ||
| 351 | # CONFIG_INET_AH is not set | ||
| 352 | # CONFIG_INET_ESP is not set | ||
| 353 | # CONFIG_INET_IPCOMP is not set | ||
| 354 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 355 | # CONFIG_INET_TUNNEL is not set | ||
| 356 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 357 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 358 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 359 | # CONFIG_INET_LRO is not set | ||
| 360 | # CONFIG_INET_DIAG is not set | ||
| 361 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 362 | CONFIG_TCP_CONG_CUBIC=y | ||
| 363 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 364 | # CONFIG_TCP_MD5SIG is not set | ||
| 365 | # CONFIG_IPV6 is not set | ||
| 366 | # CONFIG_NETWORK_SECMARK is not set | ||
| 367 | # CONFIG_NETFILTER is not set | ||
| 368 | # CONFIG_IP_DCCP is not set | ||
| 369 | # CONFIG_IP_SCTP is not set | ||
| 370 | # CONFIG_TIPC is not set | ||
| 371 | # CONFIG_ATM is not set | ||
| 372 | # CONFIG_BRIDGE is not set | ||
| 373 | # CONFIG_NET_DSA is not set | ||
| 374 | # CONFIG_VLAN_8021Q is not set | ||
| 375 | # CONFIG_DECNET is not set | ||
| 376 | # CONFIG_LLC2 is not set | ||
| 377 | # CONFIG_IPX is not set | ||
| 378 | # CONFIG_ATALK is not set | ||
| 379 | # CONFIG_X25 is not set | ||
| 380 | # CONFIG_LAPB is not set | ||
| 381 | # CONFIG_ECONET is not set | ||
| 382 | # CONFIG_WAN_ROUTER is not set | ||
| 383 | # CONFIG_NET_SCHED is not set | ||
| 384 | # CONFIG_DCB is not set | ||
| 385 | |||
| 386 | # | ||
| 387 | # Network testing | ||
| 388 | # | ||
| 389 | # CONFIG_NET_PKTGEN is not set | ||
| 390 | # CONFIG_HAMRADIO is not set | ||
| 391 | # CONFIG_CAN is not set | ||
| 392 | # CONFIG_IRDA is not set | ||
| 393 | CONFIG_BT=m | ||
| 394 | CONFIG_BT_L2CAP=m | ||
| 395 | CONFIG_BT_SCO=m | ||
| 396 | CONFIG_BT_RFCOMM=m | ||
| 397 | # CONFIG_BT_RFCOMM_TTY is not set | ||
| 398 | CONFIG_BT_BNEP=m | ||
| 399 | # CONFIG_BT_BNEP_MC_FILTER is not set | ||
| 400 | # CONFIG_BT_BNEP_PROTO_FILTER is not set | ||
| 401 | CONFIG_BT_HIDP=m | ||
| 402 | |||
| 403 | # | ||
| 404 | # Bluetooth device drivers | ||
| 405 | # | ||
| 406 | CONFIG_BT_HCIBTUSB=m | ||
| 407 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 408 | # CONFIG_BT_HCIUART is not set | ||
| 409 | # CONFIG_BT_HCIBCM203X is not set | ||
| 410 | # CONFIG_BT_HCIBPA10X is not set | ||
| 411 | # CONFIG_BT_HCIBFUSB is not set | ||
| 412 | # CONFIG_BT_HCIVHCI is not set | ||
| 413 | # CONFIG_AF_RXRPC is not set | ||
| 414 | # CONFIG_PHONET is not set | ||
| 415 | CONFIG_WIRELESS=y | ||
| 416 | # CONFIG_CFG80211 is not set | ||
| 417 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 418 | CONFIG_WIRELESS_EXT=y | ||
| 419 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 420 | CONFIG_LIB80211=m | ||
| 421 | # CONFIG_MAC80211 is not set | ||
| 422 | # CONFIG_WIMAX is not set | ||
| 423 | # CONFIG_RFKILL is not set | ||
| 424 | # CONFIG_NET_9P is not set | ||
| 425 | |||
| 426 | # | ||
| 427 | # Device Drivers | ||
| 428 | # | ||
| 429 | |||
| 430 | # | ||
| 431 | # Generic Driver Options | ||
| 432 | # | ||
| 433 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 434 | CONFIG_STANDALONE=y | ||
| 435 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 436 | CONFIG_FW_LOADER=m | ||
| 437 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 438 | CONFIG_EXTRA_FIRMWARE="" | ||
| 439 | # CONFIG_DEBUG_DRIVER is not set | ||
| 440 | # CONFIG_DEBUG_DEVRES is not set | ||
| 441 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 442 | # CONFIG_CONNECTOR is not set | ||
| 443 | CONFIG_MTD=y | ||
| 444 | # CONFIG_MTD_DEBUG is not set | ||
| 445 | # CONFIG_MTD_CONCAT is not set | ||
| 446 | CONFIG_MTD_PARTITIONS=y | ||
| 447 | # CONFIG_MTD_TESTS is not set | ||
| 448 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 449 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 450 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 451 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 452 | |||
| 453 | # | ||
| 454 | # User Modules And Translation Layers | ||
| 455 | # | ||
| 456 | CONFIG_MTD_CHAR=y | ||
| 457 | CONFIG_MTD_BLKDEVS=y | ||
| 458 | CONFIG_MTD_BLOCK=y | ||
| 459 | # CONFIG_FTL is not set | ||
| 460 | # CONFIG_NFTL is not set | ||
| 461 | # CONFIG_INFTL is not set | ||
| 462 | # CONFIG_RFD_FTL is not set | ||
| 463 | # CONFIG_SSFDC is not set | ||
| 464 | # CONFIG_MTD_OOPS is not set | ||
| 465 | |||
| 466 | # | ||
| 467 | # RAM/ROM/Flash chip drivers | ||
| 468 | # | ||
| 469 | CONFIG_MTD_CFI=y | ||
| 470 | CONFIG_MTD_JEDECPROBE=y | ||
| 471 | CONFIG_MTD_GEN_PROBE=y | ||
| 472 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 473 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 474 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 475 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 476 | # CONFIG_MTD_CFI_GEOMETRY is not set | ||
| 477 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 478 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 479 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 480 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 481 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 482 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 483 | CONFIG_MTD_CFI_I1=y | ||
| 484 | CONFIG_MTD_CFI_I2=y | ||
| 485 | # CONFIG_MTD_CFI_I4 is not set | ||
| 486 | # CONFIG_MTD_CFI_I8 is not set | ||
| 487 | # CONFIG_MTD_OTP is not set | ||
| 488 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 489 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 490 | CONFIG_MTD_CFI_STAA=y | ||
| 491 | CONFIG_MTD_CFI_UTIL=y | ||
| 492 | # CONFIG_MTD_RAM is not set | ||
| 493 | # CONFIG_MTD_ROM is not set | ||
| 494 | # CONFIG_MTD_ABSENT is not set | ||
| 495 | # CONFIG_MTD_XIP is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # Mapping drivers for chip access | ||
| 499 | # | ||
| 500 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 501 | CONFIG_MTD_PHYSMAP=y | ||
| 502 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 503 | CONFIG_MTD_PXA2XX=y | ||
| 504 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 505 | # CONFIG_MTD_IMPA7 is not set | ||
| 506 | # CONFIG_MTD_SHARP_SL is not set | ||
| 507 | # CONFIG_MTD_PLATRAM is not set | ||
| 508 | |||
| 509 | # | ||
| 510 | # Self-contained MTD device drivers | ||
| 511 | # | ||
| 512 | # CONFIG_MTD_DATAFLASH is not set | ||
| 513 | # CONFIG_MTD_M25P80 is not set | ||
| 514 | # CONFIG_MTD_SLRAM is not set | ||
| 515 | # CONFIG_MTD_PHRAM is not set | ||
| 516 | # CONFIG_MTD_MTDRAM is not set | ||
| 517 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # Disk-On-Chip Device Drivers | ||
| 521 | # | ||
| 522 | # CONFIG_MTD_DOC2000 is not set | ||
| 523 | # CONFIG_MTD_DOC2001 is not set | ||
| 524 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 525 | CONFIG_MTD_NAND=y | ||
| 526 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 527 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 528 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 529 | # CONFIG_MTD_NAND_H1900 is not set | ||
| 530 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 531 | CONFIG_MTD_NAND_IDS=y | ||
| 532 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 533 | # CONFIG_MTD_NAND_SHARPSL is not set | ||
| 534 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 535 | CONFIG_MTD_NAND_PLATFORM=y | ||
| 536 | # CONFIG_MTD_ALAUDA is not set | ||
| 537 | # CONFIG_MTD_ONENAND is not set | ||
| 538 | |||
| 539 | # | ||
| 540 | # LPDDR flash memory drivers | ||
| 541 | # | ||
| 542 | # CONFIG_MTD_LPDDR is not set | ||
| 543 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 544 | |||
| 545 | # | ||
| 546 | # UBI - Unsorted block images | ||
| 547 | # | ||
| 548 | # CONFIG_MTD_UBI is not set | ||
| 549 | # CONFIG_PARPORT is not set | ||
| 550 | CONFIG_BLK_DEV=y | ||
| 551 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 552 | CONFIG_BLK_DEV_LOOP=y | ||
| 553 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 554 | # CONFIG_BLK_DEV_NBD is not set | ||
| 555 | # CONFIG_BLK_DEV_UB is not set | ||
| 556 | CONFIG_BLK_DEV_RAM=y | ||
| 557 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 558 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 559 | # CONFIG_BLK_DEV_XIP is not set | ||
| 560 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 561 | # CONFIG_ATA_OVER_ETH is not set | ||
| 562 | # CONFIG_MISC_DEVICES is not set | ||
| 563 | CONFIG_HAVE_IDE=y | ||
| 564 | # CONFIG_IDE is not set | ||
| 565 | |||
| 566 | # | ||
| 567 | # SCSI device support | ||
| 568 | # | ||
| 569 | # CONFIG_RAID_ATTRS is not set | ||
| 570 | CONFIG_SCSI=y | ||
| 571 | CONFIG_SCSI_DMA=y | ||
| 572 | # CONFIG_SCSI_TGT is not set | ||
| 573 | # CONFIG_SCSI_NETLINK is not set | ||
| 574 | CONFIG_SCSI_PROC_FS=y | ||
| 575 | |||
| 576 | # | ||
| 577 | # SCSI support type (disk, tape, CD-ROM) | ||
| 578 | # | ||
| 579 | CONFIG_BLK_DEV_SD=y | ||
| 580 | # CONFIG_CHR_DEV_ST is not set | ||
| 581 | # CONFIG_CHR_DEV_OSST is not set | ||
| 582 | # CONFIG_BLK_DEV_SR is not set | ||
| 583 | # CONFIG_CHR_DEV_SG is not set | ||
| 584 | # CONFIG_CHR_DEV_SCH is not set | ||
| 585 | |||
| 586 | # | ||
| 587 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 588 | # | ||
| 589 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 590 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 591 | # CONFIG_SCSI_LOGGING is not set | ||
| 592 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 593 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 594 | |||
| 595 | # | ||
| 596 | # SCSI Transports | ||
| 597 | # | ||
| 598 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 599 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 600 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 601 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 602 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 603 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 604 | # CONFIG_SCSI_DH is not set | ||
| 605 | # CONFIG_ATA is not set | ||
| 606 | # CONFIG_MD is not set | ||
| 607 | CONFIG_NETDEVICES=y | ||
| 608 | # CONFIG_DUMMY is not set | ||
| 609 | # CONFIG_BONDING is not set | ||
| 610 | # CONFIG_MACVLAN is not set | ||
| 611 | # CONFIG_EQUALIZER is not set | ||
| 612 | # CONFIG_TUN is not set | ||
| 613 | # CONFIG_VETH is not set | ||
| 614 | # CONFIG_PHYLIB is not set | ||
| 615 | CONFIG_NET_ETHERNET=y | ||
| 616 | CONFIG_MII=y | ||
| 617 | # CONFIG_AX88796 is not set | ||
| 618 | # CONFIG_SMC91X is not set | ||
| 619 | CONFIG_DM9000=y | ||
| 620 | CONFIG_DM9000_DEBUGLEVEL=1 | ||
| 621 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | ||
| 622 | # CONFIG_ENC28J60 is not set | ||
| 623 | # CONFIG_SMC911X is not set | ||
| 624 | # CONFIG_SMSC911X is not set | ||
| 625 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 626 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 627 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 628 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 629 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 630 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 631 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 632 | # CONFIG_B44 is not set | ||
| 633 | # CONFIG_NETDEV_1000 is not set | ||
| 634 | # CONFIG_NETDEV_10000 is not set | ||
| 635 | |||
| 636 | # | ||
| 637 | # Wireless LAN | ||
| 638 | # | ||
| 639 | # CONFIG_WLAN_PRE80211 is not set | ||
| 640 | CONFIG_WLAN_80211=y | ||
| 641 | CONFIG_LIBERTAS=m | ||
| 642 | # CONFIG_LIBERTAS_USB is not set | ||
| 643 | CONFIG_LIBERTAS_SDIO=m | ||
| 644 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 645 | # CONFIG_USB_ZD1201 is not set | ||
| 646 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 647 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 648 | # CONFIG_HOSTAP is not set | ||
| 649 | |||
| 650 | # | ||
| 651 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 652 | # | ||
| 653 | |||
| 654 | # | ||
| 655 | # USB Network Adapters | ||
| 656 | # | ||
| 657 | # CONFIG_USB_CATC is not set | ||
| 658 | # CONFIG_USB_KAWETH is not set | ||
| 659 | # CONFIG_USB_PEGASUS is not set | ||
| 660 | # CONFIG_USB_RTL8150 is not set | ||
| 661 | # CONFIG_USB_USBNET is not set | ||
| 662 | # CONFIG_WAN is not set | ||
| 663 | CONFIG_PPP=m | ||
| 664 | CONFIG_PPP_MULTILINK=y | ||
| 665 | CONFIG_PPP_FILTER=y | ||
| 666 | CONFIG_PPP_ASYNC=m | ||
| 667 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 668 | CONFIG_PPP_DEFLATE=m | ||
| 669 | CONFIG_PPP_BSDCOMP=m | ||
| 670 | # CONFIG_PPP_MPPE is not set | ||
| 671 | # CONFIG_PPPOE is not set | ||
| 672 | # CONFIG_PPPOL2TP is not set | ||
| 673 | # CONFIG_SLIP is not set | ||
| 674 | CONFIG_SLHC=m | ||
| 675 | # CONFIG_NETCONSOLE is not set | ||
| 676 | # CONFIG_NETPOLL is not set | ||
| 677 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 678 | # CONFIG_ISDN is not set | ||
| 679 | |||
| 680 | # | ||
| 681 | # Input device support | ||
| 682 | # | ||
| 683 | CONFIG_INPUT=y | ||
| 684 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 685 | # CONFIG_INPUT_POLLDEV is not set | ||
| 686 | |||
| 687 | # | ||
| 688 | # Userland interfaces | ||
| 689 | # | ||
| 690 | CONFIG_INPUT_MOUSEDEV=y | ||
| 691 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 692 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 693 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 694 | # CONFIG_INPUT_JOYDEV is not set | ||
| 695 | CONFIG_INPUT_EVDEV=y | ||
| 696 | # CONFIG_INPUT_EVBUG is not set | ||
| 697 | CONFIG_INPUT_APMPOWER=y | ||
| 698 | |||
| 699 | # | ||
| 700 | # Input Device Drivers | ||
| 701 | # | ||
| 702 | CONFIG_INPUT_KEYBOARD=y | ||
| 703 | CONFIG_KEYBOARD_ATKBD=y | ||
| 704 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 705 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 706 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 707 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 708 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 709 | CONFIG_KEYBOARD_PXA27x=y | ||
| 710 | CONFIG_KEYBOARD_GPIO=y | ||
| 711 | # CONFIG_INPUT_MOUSE is not set | ||
| 712 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 713 | # CONFIG_INPUT_TABLET is not set | ||
| 714 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 715 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 716 | # CONFIG_TOUCHSCREEN_DA9034 is not set | ||
| 717 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 718 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 719 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 720 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 721 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 722 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 723 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 724 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 725 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 726 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 727 | CONFIG_TOUCHSCREEN_WM97XX=m | ||
| 728 | # CONFIG_TOUCHSCREEN_WM9705 is not set | ||
| 729 | CONFIG_TOUCHSCREEN_WM9712=y | ||
| 730 | # CONFIG_TOUCHSCREEN_WM9713 is not set | ||
| 731 | # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set | ||
| 732 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 733 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 734 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 735 | # CONFIG_INPUT_MISC is not set | ||
| 736 | |||
| 737 | # | ||
| 738 | # Hardware I/O ports | ||
| 739 | # | ||
| 740 | CONFIG_SERIO=y | ||
| 741 | # CONFIG_SERIO_SERPORT is not set | ||
| 742 | CONFIG_SERIO_LIBPS2=y | ||
| 743 | # CONFIG_SERIO_RAW is not set | ||
| 744 | # CONFIG_GAMEPORT is not set | ||
| 745 | |||
| 746 | # | ||
| 747 | # Character devices | ||
| 748 | # | ||
| 749 | CONFIG_VT=y | ||
| 750 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 751 | CONFIG_VT_CONSOLE=y | ||
| 752 | CONFIG_HW_CONSOLE=y | ||
| 753 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 754 | CONFIG_DEVKMEM=y | ||
| 755 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 756 | |||
| 757 | # | ||
| 758 | # Serial drivers | ||
| 759 | # | ||
| 760 | # CONFIG_SERIAL_8250 is not set | ||
| 761 | |||
| 762 | # | ||
| 763 | # Non-8250 serial port support | ||
| 764 | # | ||
| 765 | CONFIG_SERIAL_PXA=y | ||
| 766 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 767 | CONFIG_SERIAL_CORE=y | ||
| 768 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 769 | CONFIG_UNIX98_PTYS=y | ||
| 770 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 771 | CONFIG_LEGACY_PTYS=y | ||
| 772 | CONFIG_LEGACY_PTY_COUNT=16 | ||
| 773 | # CONFIG_IPMI_HANDLER is not set | ||
| 774 | # CONFIG_HW_RANDOM is not set | ||
| 775 | # CONFIG_NVRAM is not set | ||
| 776 | # CONFIG_R3964 is not set | ||
| 777 | # CONFIG_RAW_DRIVER is not set | ||
| 778 | # CONFIG_TCG_TPM is not set | ||
| 779 | CONFIG_I2C=y | ||
| 780 | CONFIG_I2C_BOARDINFO=y | ||
| 781 | CONFIG_I2C_CHARDEV=m | ||
| 782 | CONFIG_I2C_HELPER_AUTO=y | ||
| 783 | |||
| 784 | # | ||
| 785 | # I2C Hardware Bus support | ||
| 786 | # | ||
| 787 | |||
| 788 | # | ||
| 789 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 790 | # | ||
| 791 | # CONFIG_I2C_GPIO is not set | ||
| 792 | # CONFIG_I2C_OCORES is not set | ||
| 793 | CONFIG_I2C_PXA=y | ||
| 794 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 795 | # CONFIG_I2C_SIMTEC is not set | ||
| 796 | |||
| 797 | # | ||
| 798 | # External I2C/SMBus adapter drivers | ||
| 799 | # | ||
| 800 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 801 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 802 | # CONFIG_I2C_TINY_USB is not set | ||
| 803 | |||
| 804 | # | ||
| 805 | # Other I2C/SMBus bus drivers | ||
| 806 | # | ||
| 807 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 808 | # CONFIG_I2C_STUB is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Miscellaneous I2C Chip support | ||
| 812 | # | ||
| 813 | # CONFIG_DS1682 is not set | ||
| 814 | # CONFIG_EEPROM_AT24 is not set | ||
| 815 | # CONFIG_EEPROM_LEGACY is not set | ||
| 816 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 817 | # CONFIG_PCF8575 is not set | ||
| 818 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 819 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 820 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 821 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 822 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 823 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 824 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 825 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 826 | CONFIG_SPI=y | ||
| 827 | # CONFIG_SPI_DEBUG is not set | ||
| 828 | CONFIG_SPI_MASTER=y | ||
| 829 | |||
| 830 | # | ||
| 831 | # SPI Master Controller Drivers | ||
| 832 | # | ||
| 833 | # CONFIG_SPI_BITBANG is not set | ||
| 834 | # CONFIG_SPI_GPIO is not set | ||
| 835 | CONFIG_SPI_PXA2XX=y | ||
| 836 | |||
| 837 | # | ||
| 838 | # SPI Protocol Masters | ||
| 839 | # | ||
| 840 | # CONFIG_SPI_AT25 is not set | ||
| 841 | # CONFIG_SPI_SPIDEV is not set | ||
| 842 | # CONFIG_SPI_TLE62X0 is not set | ||
| 843 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 844 | CONFIG_GPIOLIB=y | ||
| 845 | # CONFIG_DEBUG_GPIO is not set | ||
| 846 | # CONFIG_GPIO_SYSFS is not set | ||
| 847 | |||
| 848 | # | ||
| 849 | # Memory mapped GPIO expanders: | ||
| 850 | # | ||
| 851 | |||
| 852 | # | ||
| 853 | # I2C GPIO expanders: | ||
| 854 | # | ||
| 855 | # CONFIG_GPIO_MAX732X is not set | ||
| 856 | # CONFIG_GPIO_PCA953X is not set | ||
| 857 | # CONFIG_GPIO_PCF857X is not set | ||
| 858 | |||
| 859 | # | ||
| 860 | # PCI GPIO expanders: | ||
| 861 | # | ||
| 862 | |||
| 863 | # | ||
| 864 | # SPI GPIO expanders: | ||
| 865 | # | ||
| 866 | # CONFIG_GPIO_MAX7301 is not set | ||
| 867 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 868 | # CONFIG_W1 is not set | ||
| 869 | CONFIG_POWER_SUPPLY=y | ||
| 870 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 871 | # CONFIG_PDA_POWER is not set | ||
| 872 | # CONFIG_APM_POWER is not set | ||
| 873 | # CONFIG_BATTERY_DS2760 is not set | ||
| 874 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 875 | CONFIG_BATTERY_DA9030=y | ||
| 876 | # CONFIG_HWMON is not set | ||
| 877 | # CONFIG_THERMAL is not set | ||
| 878 | # CONFIG_THERMAL_HWMON is not set | ||
| 879 | # CONFIG_WATCHDOG is not set | ||
| 880 | CONFIG_SSB_POSSIBLE=y | ||
| 881 | |||
| 882 | # | ||
| 883 | # Sonics Silicon Backplane | ||
| 884 | # | ||
| 885 | # CONFIG_SSB is not set | ||
| 886 | |||
| 887 | # | ||
| 888 | # Multifunction device drivers | ||
| 889 | # | ||
| 890 | # CONFIG_MFD_CORE is not set | ||
| 891 | # CONFIG_MFD_SM501 is not set | ||
| 892 | # CONFIG_MFD_ASIC3 is not set | ||
| 893 | # CONFIG_HTC_EGPIO is not set | ||
| 894 | # CONFIG_HTC_PASIC3 is not set | ||
| 895 | # CONFIG_UCB1400_CORE is not set | ||
| 896 | # CONFIG_TPS65010 is not set | ||
| 897 | # CONFIG_TWL4030_CORE is not set | ||
| 898 | # CONFIG_MFD_TMIO is not set | ||
| 899 | # CONFIG_MFD_T7L66XB is not set | ||
| 900 | # CONFIG_MFD_TC6387XB is not set | ||
| 901 | # CONFIG_MFD_TC6393XB is not set | ||
| 902 | CONFIG_PMIC_DA903X=y | ||
| 903 | # CONFIG_MFD_WM8400 is not set | ||
| 904 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 905 | # CONFIG_MFD_PCF50633 is not set | ||
| 906 | |||
| 907 | # | ||
| 908 | # Multimedia devices | ||
| 909 | # | ||
| 910 | |||
| 911 | # | ||
| 912 | # Multimedia core support | ||
| 913 | # | ||
| 914 | CONFIG_VIDEO_DEV=m | ||
| 915 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 916 | # CONFIG_VIDEO_ALLOW_V4L1 is not set | ||
| 917 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 918 | # CONFIG_DVB_CORE is not set | ||
| 919 | CONFIG_VIDEO_MEDIA=m | ||
| 920 | |||
| 921 | # | ||
| 922 | # Multimedia drivers | ||
| 923 | # | ||
| 924 | # CONFIG_MEDIA_ATTACH is not set | ||
| 925 | CONFIG_MEDIA_TUNER=m | ||
| 926 | CONFIG_MEDIA_TUNER_CUSTOMIZE=y | ||
| 927 | # CONFIG_MEDIA_TUNER_SIMPLE is not set | ||
| 928 | # CONFIG_MEDIA_TUNER_TDA8290 is not set | ||
| 929 | # CONFIG_MEDIA_TUNER_TDA827X is not set | ||
| 930 | # CONFIG_MEDIA_TUNER_TDA18271 is not set | ||
| 931 | # CONFIG_MEDIA_TUNER_TDA9887 is not set | ||
| 932 | # CONFIG_MEDIA_TUNER_TEA5761 is not set | ||
| 933 | # CONFIG_MEDIA_TUNER_TEA5767 is not set | ||
| 934 | # CONFIG_MEDIA_TUNER_MT20XX is not set | ||
| 935 | # CONFIG_MEDIA_TUNER_MT2060 is not set | ||
| 936 | # CONFIG_MEDIA_TUNER_MT2266 is not set | ||
| 937 | # CONFIG_MEDIA_TUNER_MT2131 is not set | ||
| 938 | # CONFIG_MEDIA_TUNER_QT1010 is not set | ||
| 939 | # CONFIG_MEDIA_TUNER_XC2028 is not set | ||
| 940 | # CONFIG_MEDIA_TUNER_XC5000 is not set | ||
| 941 | # CONFIG_MEDIA_TUNER_MXL5005S is not set | ||
| 942 | # CONFIG_MEDIA_TUNER_MXL5007T is not set | ||
| 943 | CONFIG_VIDEO_V4L2=m | ||
| 944 | CONFIG_VIDEOBUF_GEN=m | ||
| 945 | CONFIG_VIDEOBUF_DMA_SG=m | ||
| 946 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 947 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 948 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 949 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set | ||
| 950 | |||
| 951 | # | ||
| 952 | # Encoders/decoders and other helper chips | ||
| 953 | # | ||
| 954 | |||
| 955 | # | ||
| 956 | # Audio decoders | ||
| 957 | # | ||
| 958 | # CONFIG_VIDEO_TVAUDIO is not set | ||
| 959 | # CONFIG_VIDEO_TDA7432 is not set | ||
| 960 | # CONFIG_VIDEO_TDA9840 is not set | ||
| 961 | # CONFIG_VIDEO_TDA9875 is not set | ||
| 962 | # CONFIG_VIDEO_TEA6415C is not set | ||
| 963 | # CONFIG_VIDEO_TEA6420 is not set | ||
| 964 | # CONFIG_VIDEO_MSP3400 is not set | ||
| 965 | # CONFIG_VIDEO_CS5345 is not set | ||
| 966 | # CONFIG_VIDEO_CS53L32A is not set | ||
| 967 | # CONFIG_VIDEO_M52790 is not set | ||
| 968 | # CONFIG_VIDEO_TLV320AIC23B is not set | ||
| 969 | # CONFIG_VIDEO_WM8775 is not set | ||
| 970 | # CONFIG_VIDEO_WM8739 is not set | ||
| 971 | # CONFIG_VIDEO_VP27SMPX is not set | ||
| 972 | |||
| 973 | # | ||
| 974 | # Video decoders | ||
| 975 | # | ||
| 976 | # CONFIG_VIDEO_OV7670 is not set | ||
| 977 | # CONFIG_VIDEO_TCM825X is not set | ||
| 978 | # CONFIG_VIDEO_SAA711X is not set | ||
| 979 | # CONFIG_VIDEO_SAA717X is not set | ||
| 980 | # CONFIG_VIDEO_TVP514X is not set | ||
| 981 | # CONFIG_VIDEO_TVP5150 is not set | ||
| 982 | |||
| 983 | # | ||
| 984 | # Video and audio decoders | ||
| 985 | # | ||
| 986 | # CONFIG_VIDEO_CX25840 is not set | ||
| 987 | |||
| 988 | # | ||
| 989 | # MPEG video encoders | ||
| 990 | # | ||
| 991 | # CONFIG_VIDEO_CX2341X is not set | ||
| 992 | |||
| 993 | # | ||
| 994 | # Video encoders | ||
| 995 | # | ||
| 996 | # CONFIG_VIDEO_SAA7127 is not set | ||
| 997 | |||
| 998 | # | ||
| 999 | # Video improvement chips | ||
| 1000 | # | ||
| 1001 | # CONFIG_VIDEO_UPD64031A is not set | ||
| 1002 | # CONFIG_VIDEO_UPD64083 is not set | ||
| 1003 | # CONFIG_VIDEO_VIVI is not set | ||
| 1004 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1005 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1006 | CONFIG_SOC_CAMERA=m | ||
| 1007 | # CONFIG_SOC_CAMERA_MT9M001 is not set | ||
| 1008 | CONFIG_SOC_CAMERA_MT9M111=m | ||
| 1009 | # CONFIG_SOC_CAMERA_MT9T031 is not set | ||
| 1010 | # CONFIG_SOC_CAMERA_MT9V022 is not set | ||
| 1011 | # CONFIG_SOC_CAMERA_TW9910 is not set | ||
| 1012 | # CONFIG_SOC_CAMERA_PLATFORM is not set | ||
| 1013 | # CONFIG_SOC_CAMERA_OV772X is not set | ||
| 1014 | CONFIG_VIDEO_PXA27x=m | ||
| 1015 | # CONFIG_VIDEO_SH_MOBILE_CEU is not set | ||
| 1016 | # CONFIG_V4L_USB_DRIVERS is not set | ||
| 1017 | # CONFIG_RADIO_ADAPTERS is not set | ||
| 1018 | # CONFIG_DAB is not set | ||
| 1019 | |||
| 1020 | # | ||
| 1021 | # Graphics support | ||
| 1022 | # | ||
| 1023 | # CONFIG_VGASTATE is not set | ||
| 1024 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1025 | CONFIG_FB=y | ||
| 1026 | # CONFIG_FIRMWARE_EDID is not set | ||
| 1027 | # CONFIG_FB_DDC is not set | ||
| 1028 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1029 | CONFIG_FB_CFB_FILLRECT=y | ||
| 1030 | CONFIG_FB_CFB_COPYAREA=y | ||
| 1031 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 1032 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 1033 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 1034 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 1035 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 1036 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 1037 | # CONFIG_FB_SYS_FOPS is not set | ||
| 1038 | # CONFIG_FB_SVGALIB is not set | ||
| 1039 | # CONFIG_FB_MACMODES is not set | ||
| 1040 | # CONFIG_FB_BACKLIGHT is not set | ||
| 1041 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 1042 | # CONFIG_FB_TILEBLITTING is not set | ||
| 1043 | |||
| 1044 | # | ||
| 1045 | # Frame buffer hardware drivers | ||
| 1046 | # | ||
| 1047 | # CONFIG_FB_S1D13XXX is not set | ||
| 1048 | CONFIG_FB_PXA=y | ||
| 1049 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 1050 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 1051 | CONFIG_FB_PXA_PARAMETERS=y | ||
| 1052 | CONFIG_FB_MBX=m | ||
| 1053 | # CONFIG_FB_MBX_DEBUG is not set | ||
| 1054 | # CONFIG_FB_W100 is not set | ||
| 1055 | # CONFIG_FB_VIRTUAL is not set | ||
| 1056 | # CONFIG_FB_METRONOME is not set | ||
| 1057 | # CONFIG_FB_MB862XX is not set | ||
| 1058 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 1059 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 1060 | # CONFIG_LCD_LTV350QV is not set | ||
| 1061 | # CONFIG_LCD_ILI9320 is not set | ||
| 1062 | CONFIG_LCD_TDO24M=y | ||
| 1063 | # CONFIG_LCD_VGG2432A4 is not set | ||
| 1064 | # CONFIG_LCD_PLATFORM is not set | ||
| 1065 | CONFIG_BACKLIGHT_CLASS_DEVICE=m | ||
| 1066 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 1067 | CONFIG_BACKLIGHT_DA903X=m | ||
| 1068 | |||
| 1069 | # | ||
| 1070 | # Display device support | ||
| 1071 | # | ||
| 1072 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 1073 | |||
| 1074 | # | ||
| 1075 | # Console display driver support | ||
| 1076 | # | ||
| 1077 | # CONFIG_VGA_CONSOLE is not set | ||
| 1078 | CONFIG_DUMMY_CONSOLE=y | ||
| 1079 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 1080 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 1081 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 1082 | # CONFIG_FONTS is not set | ||
| 1083 | CONFIG_FONT_8x8=y | ||
| 1084 | CONFIG_FONT_8x16=y | ||
| 1085 | CONFIG_LOGO=y | ||
| 1086 | CONFIG_LOGO_LINUX_MONO=y | ||
| 1087 | CONFIG_LOGO_LINUX_VGA16=y | ||
| 1088 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 1089 | CONFIG_SOUND=m | ||
| 1090 | CONFIG_SOUND_OSS_CORE=y | ||
| 1091 | CONFIG_SND=m | ||
| 1092 | CONFIG_SND_TIMER=m | ||
| 1093 | CONFIG_SND_PCM=m | ||
| 1094 | # CONFIG_SND_SEQUENCER is not set | ||
| 1095 | CONFIG_SND_OSSEMUL=y | ||
| 1096 | CONFIG_SND_MIXER_OSS=m | ||
| 1097 | CONFIG_SND_PCM_OSS=m | ||
| 1098 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 1099 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1100 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1101 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1102 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 1103 | # CONFIG_SND_DEBUG is not set | ||
| 1104 | CONFIG_SND_VMASTER=y | ||
| 1105 | CONFIG_SND_AC97_CODEC=m | ||
| 1106 | # CONFIG_SND_DRIVERS is not set | ||
| 1107 | CONFIG_SND_ARM=y | ||
| 1108 | CONFIG_SND_PXA2XX_LIB=m | ||
| 1109 | CONFIG_SND_PXA2XX_LIB_AC97=y | ||
| 1110 | # CONFIG_SND_PXA2XX_AC97 is not set | ||
| 1111 | # CONFIG_SND_SPI is not set | ||
| 1112 | # CONFIG_SND_USB is not set | ||
| 1113 | CONFIG_SND_SOC=m | ||
| 1114 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 1115 | CONFIG_SND_PXA2XX_SOC=m | ||
| 1116 | CONFIG_SND_PXA2XX_SOC_AC97=m | ||
| 1117 | CONFIG_SND_PXA2XX_SOC_EM_X270=m | ||
| 1118 | CONFIG_SND_SOC_I2C_AND_SPI=m | ||
| 1119 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1120 | CONFIG_SND_SOC_WM9712=m | ||
| 1121 | # CONFIG_SOUND_PRIME is not set | ||
| 1122 | CONFIG_AC97_BUS=m | ||
| 1123 | CONFIG_HID_SUPPORT=y | ||
| 1124 | CONFIG_HID=y | ||
| 1125 | CONFIG_HID_DEBUG=y | ||
| 1126 | # CONFIG_HIDRAW is not set | ||
| 1127 | |||
| 1128 | # | ||
| 1129 | # USB Input Devices | ||
| 1130 | # | ||
| 1131 | CONFIG_USB_HID=y | ||
| 1132 | # CONFIG_HID_PID is not set | ||
| 1133 | # CONFIG_USB_HIDDEV is not set | ||
| 1134 | |||
| 1135 | # | ||
| 1136 | # Special HID drivers | ||
| 1137 | # | ||
| 1138 | CONFIG_HID_COMPAT=y | ||
| 1139 | CONFIG_HID_A4TECH=y | ||
| 1140 | CONFIG_HID_APPLE=y | ||
| 1141 | CONFIG_HID_BELKIN=y | ||
| 1142 | CONFIG_HID_CHERRY=y | ||
| 1143 | CONFIG_HID_CHICONY=y | ||
| 1144 | CONFIG_HID_CYPRESS=y | ||
| 1145 | CONFIG_HID_EZKEY=y | ||
| 1146 | CONFIG_HID_GYRATION=y | ||
| 1147 | CONFIG_HID_LOGITECH=y | ||
| 1148 | # CONFIG_LOGITECH_FF is not set | ||
| 1149 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1150 | CONFIG_HID_MICROSOFT=y | ||
| 1151 | CONFIG_HID_MONTEREY=y | ||
| 1152 | # CONFIG_HID_NTRIG is not set | ||
| 1153 | CONFIG_HID_PANTHERLORD=y | ||
| 1154 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1155 | CONFIG_HID_PETALYNX=y | ||
| 1156 | CONFIG_HID_SAMSUNG=y | ||
| 1157 | CONFIG_HID_SONY=y | ||
| 1158 | CONFIG_HID_SUNPLUS=y | ||
| 1159 | # CONFIG_GREENASIA_FF is not set | ||
| 1160 | # CONFIG_HID_TOPSEED is not set | ||
| 1161 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1162 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1163 | CONFIG_USB_SUPPORT=y | ||
| 1164 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1165 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1166 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1167 | CONFIG_USB=y | ||
| 1168 | # CONFIG_USB_DEBUG is not set | ||
| 1169 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1170 | |||
| 1171 | # | ||
| 1172 | # Miscellaneous USB options | ||
| 1173 | # | ||
| 1174 | CONFIG_USB_DEVICEFS=y | ||
| 1175 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 1176 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1177 | # CONFIG_USB_SUSPEND is not set | ||
| 1178 | # CONFIG_USB_OTG is not set | ||
| 1179 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1180 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1181 | CONFIG_USB_MON=y | ||
| 1182 | # CONFIG_USB_WUSB is not set | ||
| 1183 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1184 | |||
| 1185 | # | ||
| 1186 | # USB Host Controller Drivers | ||
| 1187 | # | ||
| 1188 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1189 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1190 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1191 | CONFIG_USB_OHCI_HCD=y | ||
| 1192 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 1193 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 1194 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 1195 | # CONFIG_USB_SL811_HCD is not set | ||
| 1196 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1197 | # CONFIG_USB_HWA_HCD is not set | ||
| 1198 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1199 | |||
| 1200 | # | ||
| 1201 | # USB Device Class drivers | ||
| 1202 | # | ||
| 1203 | # CONFIG_USB_ACM is not set | ||
| 1204 | # CONFIG_USB_PRINTER is not set | ||
| 1205 | # CONFIG_USB_WDM is not set | ||
| 1206 | # CONFIG_USB_TMC is not set | ||
| 1207 | |||
| 1208 | # | ||
| 1209 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1210 | # | ||
| 1211 | |||
| 1212 | # | ||
| 1213 | # see USB_STORAGE Help for more information | ||
| 1214 | # | ||
| 1215 | CONFIG_USB_STORAGE=y | ||
| 1216 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1217 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1218 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1219 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1220 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1221 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1222 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1223 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1224 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1225 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1226 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1227 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1228 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1229 | |||
| 1230 | # | ||
| 1231 | # USB Imaging devices | ||
| 1232 | # | ||
| 1233 | # CONFIG_USB_MDC800 is not set | ||
| 1234 | # CONFIG_USB_MICROTEK is not set | ||
| 1235 | |||
| 1236 | # | ||
| 1237 | # USB port drivers | ||
| 1238 | # | ||
| 1239 | # CONFIG_USB_SERIAL is not set | ||
| 1240 | |||
| 1241 | # | ||
| 1242 | # USB Miscellaneous drivers | ||
| 1243 | # | ||
| 1244 | # CONFIG_USB_EMI62 is not set | ||
| 1245 | # CONFIG_USB_EMI26 is not set | ||
| 1246 | # CONFIG_USB_ADUTUX is not set | ||
| 1247 | # CONFIG_USB_SEVSEG is not set | ||
| 1248 | # CONFIG_USB_RIO500 is not set | ||
| 1249 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1250 | # CONFIG_USB_LCD is not set | ||
| 1251 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1252 | # CONFIG_USB_LED is not set | ||
| 1253 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1254 | # CONFIG_USB_CYTHERM is not set | ||
| 1255 | # CONFIG_USB_PHIDGET is not set | ||
| 1256 | # CONFIG_USB_IDMOUSE is not set | ||
| 1257 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1258 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1259 | # CONFIG_USB_LD is not set | ||
| 1260 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1261 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1262 | # CONFIG_USB_TEST is not set | ||
| 1263 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1264 | # CONFIG_USB_VST is not set | ||
| 1265 | # CONFIG_USB_GADGET is not set | ||
| 1266 | |||
| 1267 | # | ||
| 1268 | # OTG and related infrastructure | ||
| 1269 | # | ||
| 1270 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1271 | CONFIG_MMC=m | ||
| 1272 | # CONFIG_MMC_DEBUG is not set | ||
| 1273 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1274 | |||
| 1275 | # | ||
| 1276 | # MMC/SD/SDIO Card Drivers | ||
| 1277 | # | ||
| 1278 | CONFIG_MMC_BLOCK=m | ||
| 1279 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1280 | # CONFIG_SDIO_UART is not set | ||
| 1281 | # CONFIG_MMC_TEST is not set | ||
| 1282 | |||
| 1283 | # | ||
| 1284 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1285 | # | ||
| 1286 | CONFIG_MMC_PXA=m | ||
| 1287 | # CONFIG_MMC_SDHCI is not set | ||
| 1288 | # CONFIG_MMC_SPI is not set | ||
| 1289 | # CONFIG_MEMSTICK is not set | ||
| 1290 | # CONFIG_ACCESSIBILITY is not set | ||
| 1291 | CONFIG_NEW_LEDS=y | ||
| 1292 | CONFIG_LEDS_CLASS=y | ||
| 1293 | |||
| 1294 | # | ||
| 1295 | # LED drivers | ||
| 1296 | # | ||
| 1297 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1298 | # CONFIG_LEDS_GPIO is not set | ||
| 1299 | # CONFIG_LEDS_PCA955X is not set | ||
| 1300 | CONFIG_LEDS_DA903X=y | ||
| 1301 | |||
| 1302 | # | ||
| 1303 | # LED Triggers | ||
| 1304 | # | ||
| 1305 | CONFIG_LEDS_TRIGGERS=y | ||
| 1306 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1307 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1308 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1309 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1310 | CONFIG_RTC_LIB=y | ||
| 1311 | CONFIG_RTC_CLASS=y | ||
| 1312 | CONFIG_RTC_HCTOSYS=y | ||
| 1313 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1314 | # CONFIG_RTC_DEBUG is not set | ||
| 1315 | |||
| 1316 | # | ||
| 1317 | # RTC interfaces | ||
| 1318 | # | ||
| 1319 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1320 | CONFIG_RTC_INTF_PROC=y | ||
| 1321 | CONFIG_RTC_INTF_DEV=y | ||
| 1322 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1323 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1324 | |||
| 1325 | # | ||
| 1326 | # I2C RTC drivers | ||
| 1327 | # | ||
| 1328 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1329 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1330 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1331 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1332 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1333 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1334 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1335 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1336 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1337 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1338 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1339 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1340 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1341 | |||
| 1342 | # | ||
| 1343 | # SPI RTC drivers | ||
| 1344 | # | ||
| 1345 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1346 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1347 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1348 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1349 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1350 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1351 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1352 | |||
| 1353 | # | ||
| 1354 | # Platform RTC drivers | ||
| 1355 | # | ||
| 1356 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1357 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1358 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1359 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1360 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1361 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1362 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1363 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1364 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1365 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1366 | CONFIG_RTC_DRV_V3020=y | ||
| 1367 | |||
| 1368 | # | ||
| 1369 | # on-CPU RTC drivers | ||
| 1370 | # | ||
| 1371 | CONFIG_RTC_DRV_SA1100=y | ||
| 1372 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1373 | # CONFIG_DMADEVICES is not set | ||
| 1374 | CONFIG_REGULATOR=y | ||
| 1375 | # CONFIG_REGULATOR_DEBUG is not set | ||
| 1376 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 1377 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 1378 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 1379 | CONFIG_REGULATOR_DA903X=y | ||
| 1380 | # CONFIG_UIO is not set | ||
| 1381 | # CONFIG_STAGING is not set | ||
| 1382 | |||
| 1383 | # | ||
| 1384 | # File systems | ||
| 1385 | # | ||
| 1386 | CONFIG_EXT2_FS=y | ||
| 1387 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1388 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1389 | CONFIG_EXT3_FS=y | ||
| 1390 | CONFIG_EXT3_FS_XATTR=y | ||
| 1391 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 1392 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 1393 | # CONFIG_EXT4_FS is not set | ||
| 1394 | CONFIG_JBD=y | ||
| 1395 | # CONFIG_JBD_DEBUG is not set | ||
| 1396 | CONFIG_FS_MBCACHE=y | ||
| 1397 | # CONFIG_REISERFS_FS is not set | ||
| 1398 | # CONFIG_JFS_FS is not set | ||
| 1399 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1400 | CONFIG_FILE_LOCKING=y | ||
| 1401 | # CONFIG_XFS_FS is not set | ||
| 1402 | # CONFIG_OCFS2_FS is not set | ||
| 1403 | # CONFIG_BTRFS_FS is not set | ||
| 1404 | CONFIG_DNOTIFY=y | ||
| 1405 | CONFIG_INOTIFY=y | ||
| 1406 | CONFIG_INOTIFY_USER=y | ||
| 1407 | # CONFIG_QUOTA is not set | ||
| 1408 | # CONFIG_AUTOFS_FS is not set | ||
| 1409 | # CONFIG_AUTOFS4_FS is not set | ||
| 1410 | # CONFIG_FUSE_FS is not set | ||
| 1411 | |||
| 1412 | # | ||
| 1413 | # CD-ROM/DVD Filesystems | ||
| 1414 | # | ||
| 1415 | # CONFIG_ISO9660_FS is not set | ||
| 1416 | # CONFIG_UDF_FS is not set | ||
| 1417 | |||
| 1418 | # | ||
| 1419 | # DOS/FAT/NT Filesystems | ||
| 1420 | # | ||
| 1421 | CONFIG_FAT_FS=m | ||
| 1422 | # CONFIG_MSDOS_FS is not set | ||
| 1423 | CONFIG_VFAT_FS=m | ||
| 1424 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1425 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1426 | # CONFIG_NTFS_FS is not set | ||
| 1427 | |||
| 1428 | # | ||
| 1429 | # Pseudo filesystems | ||
| 1430 | # | ||
| 1431 | CONFIG_PROC_FS=y | ||
| 1432 | CONFIG_PROC_SYSCTL=y | ||
| 1433 | # CONFIG_PROC_PAGE_MONITOR is not set | ||
| 1434 | CONFIG_SYSFS=y | ||
| 1435 | CONFIG_TMPFS=y | ||
| 1436 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1437 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1438 | # CONFIG_CONFIGFS_FS is not set | ||
| 1439 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1440 | # CONFIG_ADFS_FS is not set | ||
| 1441 | # CONFIG_AFFS_FS is not set | ||
| 1442 | # CONFIG_HFS_FS is not set | ||
| 1443 | # CONFIG_HFSPLUS_FS is not set | ||
| 1444 | # CONFIG_BEFS_FS is not set | ||
| 1445 | # CONFIG_BFS_FS is not set | ||
| 1446 | # CONFIG_EFS_FS is not set | ||
| 1447 | CONFIG_JFFS2_FS=y | ||
| 1448 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1449 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1450 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1451 | CONFIG_JFFS2_SUMMARY=y | ||
| 1452 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1453 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1454 | CONFIG_JFFS2_ZLIB=y | ||
| 1455 | # CONFIG_JFFS2_LZO is not set | ||
| 1456 | CONFIG_JFFS2_RTIME=y | ||
| 1457 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1458 | # CONFIG_CRAMFS is not set | ||
| 1459 | # CONFIG_SQUASHFS is not set | ||
| 1460 | # CONFIG_VXFS_FS is not set | ||
| 1461 | # CONFIG_MINIX_FS is not set | ||
| 1462 | # CONFIG_OMFS_FS is not set | ||
| 1463 | # CONFIG_HPFS_FS is not set | ||
| 1464 | # CONFIG_QNX4FS_FS is not set | ||
| 1465 | # CONFIG_ROMFS_FS is not set | ||
| 1466 | # CONFIG_SYSV_FS is not set | ||
| 1467 | # CONFIG_UFS_FS is not set | ||
| 1468 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1469 | CONFIG_NFS_FS=y | ||
| 1470 | CONFIG_NFS_V3=y | ||
| 1471 | # CONFIG_NFS_V3_ACL is not set | ||
| 1472 | # CONFIG_NFS_V4 is not set | ||
| 1473 | CONFIG_ROOT_NFS=y | ||
| 1474 | # CONFIG_NFSD is not set | ||
| 1475 | CONFIG_LOCKD=y | ||
| 1476 | CONFIG_LOCKD_V4=y | ||
| 1477 | CONFIG_NFS_COMMON=y | ||
| 1478 | CONFIG_SUNRPC=y | ||
| 1479 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1480 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1481 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1482 | # CONFIG_SMB_FS is not set | ||
| 1483 | CONFIG_CIFS=m | ||
| 1484 | # CONFIG_CIFS_STATS is not set | ||
| 1485 | # CONFIG_CIFS_WEAK_PW_HASH is not set | ||
| 1486 | # CONFIG_CIFS_XATTR is not set | ||
| 1487 | # CONFIG_CIFS_DEBUG2 is not set | ||
| 1488 | # CONFIG_CIFS_EXPERIMENTAL is not set | ||
| 1489 | # CONFIG_NCP_FS is not set | ||
| 1490 | # CONFIG_CODA_FS is not set | ||
| 1491 | # CONFIG_AFS_FS is not set | ||
| 1492 | |||
| 1493 | # | ||
| 1494 | # Partition Types | ||
| 1495 | # | ||
| 1496 | CONFIG_PARTITION_ADVANCED=y | ||
| 1497 | # CONFIG_ACORN_PARTITION is not set | ||
| 1498 | # CONFIG_OSF_PARTITION is not set | ||
| 1499 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1500 | # CONFIG_ATARI_PARTITION is not set | ||
| 1501 | # CONFIG_MAC_PARTITION is not set | ||
| 1502 | CONFIG_MSDOS_PARTITION=y | ||
| 1503 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1504 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1505 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1506 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1507 | # CONFIG_LDM_PARTITION is not set | ||
| 1508 | # CONFIG_SGI_PARTITION is not set | ||
| 1509 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1510 | # CONFIG_SUN_PARTITION is not set | ||
| 1511 | # CONFIG_KARMA_PARTITION is not set | ||
| 1512 | # CONFIG_EFI_PARTITION is not set | ||
| 1513 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1514 | CONFIG_NLS=m | ||
| 1515 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1516 | CONFIG_NLS_CODEPAGE_437=m | ||
| 1517 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1518 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1519 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1520 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1521 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1522 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1523 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1524 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1525 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1526 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1527 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1528 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1529 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1530 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1531 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1532 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1533 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1534 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1535 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1536 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1537 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1538 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1539 | # CONFIG_NLS_ASCII is not set | ||
| 1540 | CONFIG_NLS_ISO8859_1=m | ||
| 1541 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1542 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1543 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1544 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1545 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1546 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1547 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1548 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1549 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1550 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1551 | # CONFIG_NLS_KOI8_R is not set | ||
| 1552 | # CONFIG_NLS_KOI8_U is not set | ||
| 1553 | CONFIG_NLS_UTF8=m | ||
| 1554 | # CONFIG_DLM is not set | ||
| 1555 | |||
| 1556 | # | ||
| 1557 | # Kernel hacking | ||
| 1558 | # | ||
| 1559 | # CONFIG_PRINTK_TIME is not set | ||
| 1560 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1561 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1562 | CONFIG_FRAME_WARN=0 | ||
| 1563 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1564 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1565 | CONFIG_DEBUG_FS=y | ||
| 1566 | # CONFIG_HEADERS_CHECK is not set | ||
| 1567 | CONFIG_DEBUG_KERNEL=y | ||
| 1568 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1569 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 1570 | # CONFIG_SCHED_DEBUG is not set | ||
| 1571 | # CONFIG_SCHEDSTATS is not set | ||
| 1572 | # CONFIG_TIMER_STATS is not set | ||
| 1573 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1574 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1575 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1576 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1577 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1578 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1579 | # CONFIG_PROVE_LOCKING is not set | ||
| 1580 | # CONFIG_LOCK_STAT is not set | ||
| 1581 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1582 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1583 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1584 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1585 | # CONFIG_DEBUG_INFO is not set | ||
| 1586 | # CONFIG_DEBUG_VM is not set | ||
| 1587 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1588 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1589 | # CONFIG_DEBUG_LIST is not set | ||
| 1590 | # CONFIG_DEBUG_SG is not set | ||
| 1591 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1592 | CONFIG_FRAME_POINTER=y | ||
| 1593 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1594 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1595 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1596 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1597 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1598 | # CONFIG_FAULT_INJECTION is not set | ||
| 1599 | # CONFIG_LATENCYTOP is not set | ||
| 1600 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1601 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1602 | |||
| 1603 | # | ||
| 1604 | # Tracers | ||
| 1605 | # | ||
| 1606 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1607 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1608 | # CONFIG_SCHED_TRACER is not set | ||
| 1609 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1610 | # CONFIG_BOOT_TRACER is not set | ||
| 1611 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1612 | # CONFIG_STACK_TRACER is not set | ||
| 1613 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1614 | # CONFIG_SAMPLES is not set | ||
| 1615 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1616 | # CONFIG_KGDB is not set | ||
| 1617 | CONFIG_DEBUG_USER=y | ||
| 1618 | CONFIG_DEBUG_ERRORS=y | ||
| 1619 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1620 | CONFIG_DEBUG_LL=y | ||
| 1621 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1622 | |||
| 1623 | # | ||
| 1624 | # Security options | ||
| 1625 | # | ||
| 1626 | # CONFIG_KEYS is not set | ||
| 1627 | # CONFIG_SECURITY is not set | ||
| 1628 | # CONFIG_SECURITYFS is not set | ||
| 1629 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1630 | CONFIG_CRYPTO=y | ||
| 1631 | |||
| 1632 | # | ||
| 1633 | # Crypto core or helper | ||
| 1634 | # | ||
| 1635 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1636 | CONFIG_CRYPTO_ALGAPI=m | ||
| 1637 | CONFIG_CRYPTO_ALGAPI2=m | ||
| 1638 | CONFIG_CRYPTO_AEAD2=m | ||
| 1639 | CONFIG_CRYPTO_BLKCIPHER=m | ||
| 1640 | CONFIG_CRYPTO_BLKCIPHER2=m | ||
| 1641 | CONFIG_CRYPTO_HASH=m | ||
| 1642 | CONFIG_CRYPTO_HASH2=m | ||
| 1643 | CONFIG_CRYPTO_RNG2=m | ||
| 1644 | CONFIG_CRYPTO_MANAGER=m | ||
| 1645 | CONFIG_CRYPTO_MANAGER2=m | ||
| 1646 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1647 | # CONFIG_CRYPTO_NULL is not set | ||
| 1648 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1649 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1650 | # CONFIG_CRYPTO_TEST is not set | ||
| 1651 | |||
| 1652 | # | ||
| 1653 | # Authenticated Encryption with Associated Data | ||
| 1654 | # | ||
| 1655 | # CONFIG_CRYPTO_CCM is not set | ||
| 1656 | # CONFIG_CRYPTO_GCM is not set | ||
| 1657 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1658 | |||
| 1659 | # | ||
| 1660 | # Block modes | ||
| 1661 | # | ||
| 1662 | # CONFIG_CRYPTO_CBC is not set | ||
| 1663 | # CONFIG_CRYPTO_CTR is not set | ||
| 1664 | # CONFIG_CRYPTO_CTS is not set | ||
| 1665 | CONFIG_CRYPTO_ECB=m | ||
| 1666 | # CONFIG_CRYPTO_LRW is not set | ||
| 1667 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1668 | # CONFIG_CRYPTO_XTS is not set | ||
| 1669 | |||
| 1670 | # | ||
| 1671 | # Hash modes | ||
| 1672 | # | ||
| 1673 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1674 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1675 | |||
| 1676 | # | ||
| 1677 | # Digest | ||
| 1678 | # | ||
| 1679 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1680 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1681 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1682 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 1683 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1684 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1685 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1686 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1687 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1688 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1689 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1690 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1691 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1692 | |||
| 1693 | # | ||
| 1694 | # Ciphers | ||
| 1695 | # | ||
| 1696 | CONFIG_CRYPTO_AES=m | ||
| 1697 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1698 | CONFIG_CRYPTO_ARC4=m | ||
| 1699 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1700 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1701 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1702 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1703 | # CONFIG_CRYPTO_DES is not set | ||
| 1704 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1705 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1706 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1707 | # CONFIG_CRYPTO_SEED is not set | ||
| 1708 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1709 | # CONFIG_CRYPTO_TEA is not set | ||
| 1710 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1711 | |||
| 1712 | # | ||
| 1713 | # Compression | ||
| 1714 | # | ||
| 1715 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1716 | # CONFIG_CRYPTO_LZO is not set | ||
| 1717 | |||
| 1718 | # | ||
| 1719 | # Random Number Generation | ||
| 1720 | # | ||
| 1721 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1722 | # CONFIG_CRYPTO_HW is not set | ||
| 1723 | |||
| 1724 | # | ||
| 1725 | # Library routines | ||
| 1726 | # | ||
| 1727 | CONFIG_BITREVERSE=y | ||
| 1728 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1729 | CONFIG_CRC_CCITT=m | ||
| 1730 | # CONFIG_CRC16 is not set | ||
| 1731 | # CONFIG_CRC_T10DIF is not set | ||
| 1732 | # CONFIG_CRC_ITU_T is not set | ||
| 1733 | CONFIG_CRC32=y | ||
| 1734 | # CONFIG_CRC7 is not set | ||
| 1735 | # CONFIG_LIBCRC32C is not set | ||
| 1736 | CONFIG_ZLIB_INFLATE=y | ||
| 1737 | CONFIG_ZLIB_DEFLATE=y | ||
| 1738 | CONFIG_PLIST=y | ||
| 1739 | CONFIG_HAS_IOMEM=y | ||
| 1740 | CONFIG_HAS_IOPORT=y | ||
| 1741 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig index 8f986e9f1c62..1502957db2c3 100644 --- a/arch/arm/configs/h3600_defconfig +++ b/arch/arm/configs/h3600_defconfig | |||
| @@ -90,7 +90,6 @@ CONFIG_ARCH_SA1100=y | |||
| 90 | # CONFIG_SA1100_COLLIE is not set | 90 | # CONFIG_SA1100_COLLIE is not set |
| 91 | # CONFIG_SA1100_H3100 is not set | 91 | # CONFIG_SA1100_H3100 is not set |
| 92 | CONFIG_SA1100_H3600=y | 92 | CONFIG_SA1100_H3600=y |
| 93 | # CONFIG_SA1100_H3800 is not set | ||
| 94 | CONFIG_SA1100_H3XXX=y | 93 | CONFIG_SA1100_H3XXX=y |
| 95 | # CONFIG_SA1100_BADGE4 is not set | 94 | # CONFIG_SA1100_BADGE4 is not set |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| @@ -100,7 +99,6 @@ CONFIG_SA1100_H3XXX=y | |||
| 100 | # CONFIG_SA1100_SHANNON is not set | 99 | # CONFIG_SA1100_SHANNON is not set |
| 101 | # CONFIG_SA1100_SIMPAD is not set | 100 | # CONFIG_SA1100_SIMPAD is not set |
| 102 | # CONFIG_SA1100_SSP is not set | 101 | # CONFIG_SA1100_SSP is not set |
| 103 | # CONFIG_H3600_SLEEVE is not set | ||
| 104 | 102 | ||
| 105 | # | 103 | # |
| 106 | # Processor Type | 104 | # Processor Type |
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig index 1c8fb89a6730..db0708d5cbea 100644 --- a/arch/arm/configs/hackkit_defconfig +++ b/arch/arm/configs/hackkit_defconfig | |||
| @@ -91,7 +91,6 @@ CONFIG_ARCH_SA1100=y | |||
| 91 | # CONFIG_SA1100_COLLIE is not set | 91 | # CONFIG_SA1100_COLLIE is not set |
| 92 | # CONFIG_SA1100_H3100 is not set | 92 | # CONFIG_SA1100_H3100 is not set |
| 93 | # CONFIG_SA1100_H3600 is not set | 93 | # CONFIG_SA1100_H3600 is not set |
| 94 | # CONFIG_SA1100_H3800 is not set | ||
| 95 | # CONFIG_SA1100_BADGE4 is not set | 94 | # CONFIG_SA1100_BADGE4 is not set |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| 97 | CONFIG_SA1100_HACKKIT=y | 96 | CONFIG_SA1100_HACKKIT=y |
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index 81fadafae02d..f3074e49f2fa 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig | |||
| @@ -178,7 +178,6 @@ CONFIG_DMABOUNCE=y | |||
| 178 | # CONFIG_SA1100_COLLIE is not set | 178 | # CONFIG_SA1100_COLLIE is not set |
| 179 | # CONFIG_SA1100_H3100 is not set | 179 | # CONFIG_SA1100_H3100 is not set |
| 180 | # CONFIG_SA1100_H3600 is not set | 180 | # CONFIG_SA1100_H3600 is not set |
| 181 | # CONFIG_SA1100_H3800 is not set | ||
| 182 | # CONFIG_SA1100_BADGE4 is not set | 181 | # CONFIG_SA1100_BADGE4 is not set |
| 183 | CONFIG_SA1100_JORNADA720=y | 182 | CONFIG_SA1100_JORNADA720=y |
| 184 | CONFIG_SA1100_JORNADA720_SSP=y | 183 | CONFIG_SA1100_JORNADA720_SSP=y |
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 4bc38078d580..c367ae44012e 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28-rc7 | 3 | # Linux kernel version: 2.6.29-rc5 |
| 4 | # Thu Dec 4 15:27:39 2008 | 4 | # Tue Mar 3 21:45:57 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | # CONFIG_GENERIC_GPIO is not set | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_GENERIC_TIME=y | 9 | CONFIG_GENERIC_TIME=y |
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | 10 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 11 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| @@ -42,10 +42,19 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | 42 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 43 | # CONFIG_TASKSTATS is not set | 43 | # CONFIG_TASKSTATS is not set |
| 44 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 45 | # CONFIG_IKCONFIG is not set | 54 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | 55 | CONFIG_LOG_BUF_SHIFT=19 |
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | # CONFIG_GROUP_SCHED is not set | 56 | # CONFIG_GROUP_SCHED is not set |
| 57 | # CONFIG_CGROUPS is not set | ||
| 49 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | 58 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 50 | # CONFIG_RELAY is not set | 59 | # CONFIG_RELAY is not set |
| 51 | CONFIG_NAMESPACES=y | 60 | CONFIG_NAMESPACES=y |
| @@ -53,6 +62,7 @@ CONFIG_NAMESPACES=y | |||
| 53 | # CONFIG_IPC_NS is not set | 62 | # CONFIG_IPC_NS is not set |
| 54 | # CONFIG_USER_NS is not set | 63 | # CONFIG_USER_NS is not set |
| 55 | # CONFIG_PID_NS is not set | 64 | # CONFIG_PID_NS is not set |
| 65 | # CONFIG_NET_NS is not set | ||
| 56 | # CONFIG_BLK_DEV_INITRD is not set | 66 | # CONFIG_BLK_DEV_INITRD is not set |
| 57 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 67 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 58 | CONFIG_SYSCTL=y | 68 | CONFIG_SYSCTL=y |
| @@ -83,6 +93,7 @@ CONFIG_SLUB_DEBUG=y | |||
| 83 | CONFIG_SLUB=y | 93 | CONFIG_SLUB=y |
| 84 | # CONFIG_SLOB is not set | 94 | # CONFIG_SLOB is not set |
| 85 | CONFIG_PROFILING=y | 95 | CONFIG_PROFILING=y |
| 96 | CONFIG_TRACEPOINTS=y | ||
| 86 | # CONFIG_MARKERS is not set | 97 | # CONFIG_MARKERS is not set |
| 87 | CONFIG_OPROFILE=y | 98 | CONFIG_OPROFILE=y |
| 88 | CONFIG_HAVE_OPROFILE=y | 99 | CONFIG_HAVE_OPROFILE=y |
| @@ -93,7 +104,6 @@ CONFIG_HAVE_KRETPROBES=y | |||
| 93 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 104 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 94 | CONFIG_SLABINFO=y | 105 | CONFIG_SLABINFO=y |
| 95 | CONFIG_RT_MUTEXES=y | 106 | CONFIG_RT_MUTEXES=y |
| 96 | # CONFIG_TINY_SHMEM is not set | ||
| 97 | CONFIG_BASE_SMALL=0 | 107 | CONFIG_BASE_SMALL=0 |
| 98 | CONFIG_MODULES=y | 108 | CONFIG_MODULES=y |
| 99 | # CONFIG_MODULE_FORCE_LOAD is not set | 109 | # CONFIG_MODULE_FORCE_LOAD is not set |
| @@ -101,11 +111,9 @@ CONFIG_MODULE_UNLOAD=y | |||
| 101 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 111 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 102 | # CONFIG_MODVERSIONS is not set | 112 | # CONFIG_MODVERSIONS is not set |
| 103 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 113 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 104 | CONFIG_KMOD=y | ||
| 105 | CONFIG_BLOCK=y | 114 | CONFIG_BLOCK=y |
| 106 | # CONFIG_LBD is not set | 115 | # CONFIG_LBD is not set |
| 107 | # CONFIG_BLK_DEV_IO_TRACE is not set | 116 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 108 | # CONFIG_LSF is not set | ||
| 109 | # CONFIG_BLK_DEV_BSG is not set | 117 | # CONFIG_BLK_DEV_BSG is not set |
| 110 | # CONFIG_BLK_DEV_INTEGRITY is not set | 118 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 111 | 119 | ||
| @@ -121,7 +129,6 @@ CONFIG_IOSCHED_CFQ=y | |||
| 121 | CONFIG_DEFAULT_CFQ=y | 129 | CONFIG_DEFAULT_CFQ=y |
| 122 | # CONFIG_DEFAULT_NOOP is not set | 130 | # CONFIG_DEFAULT_NOOP is not set |
| 123 | CONFIG_DEFAULT_IOSCHED="cfq" | 131 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 124 | CONFIG_CLASSIC_RCU=y | ||
| 125 | # CONFIG_FREEZER is not set | 132 | # CONFIG_FREEZER is not set |
| 126 | 133 | ||
| 127 | # | 134 | # |
| @@ -132,7 +139,6 @@ CONFIG_CLASSIC_RCU=y | |||
| 132 | # CONFIG_ARCH_REALVIEW is not set | 139 | # CONFIG_ARCH_REALVIEW is not set |
| 133 | # CONFIG_ARCH_VERSATILE is not set | 140 | # CONFIG_ARCH_VERSATILE is not set |
| 134 | # CONFIG_ARCH_AT91 is not set | 141 | # CONFIG_ARCH_AT91 is not set |
| 135 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 136 | # CONFIG_ARCH_CLPS711X is not set | 142 | # CONFIG_ARCH_CLPS711X is not set |
| 137 | # CONFIG_ARCH_EBSA110 is not set | 143 | # CONFIG_ARCH_EBSA110 is not set |
| 138 | # CONFIG_ARCH_EP93XX is not set | 144 | # CONFIG_ARCH_EP93XX is not set |
| @@ -159,11 +165,13 @@ CONFIG_ARCH_KIRKWOOD=y | |||
| 159 | # CONFIG_ARCH_RPC is not set | 165 | # CONFIG_ARCH_RPC is not set |
| 160 | # CONFIG_ARCH_SA1100 is not set | 166 | # CONFIG_ARCH_SA1100 is not set |
| 161 | # CONFIG_ARCH_S3C2410 is not set | 167 | # CONFIG_ARCH_S3C2410 is not set |
| 168 | # CONFIG_ARCH_S3C64XX is not set | ||
| 162 | # CONFIG_ARCH_SHARK is not set | 169 | # CONFIG_ARCH_SHARK is not set |
| 163 | # CONFIG_ARCH_LH7A40X is not set | 170 | # CONFIG_ARCH_LH7A40X is not set |
| 164 | # CONFIG_ARCH_DAVINCI is not set | 171 | # CONFIG_ARCH_DAVINCI is not set |
| 165 | # CONFIG_ARCH_OMAP is not set | 172 | # CONFIG_ARCH_OMAP is not set |
| 166 | # CONFIG_ARCH_MSM is not set | 173 | # CONFIG_ARCH_MSM is not set |
| 174 | # CONFIG_ARCH_W90X900 is not set | ||
| 167 | 175 | ||
| 168 | # | 176 | # |
| 169 | # Marvell Kirkwood Implementations | 177 | # Marvell Kirkwood Implementations |
| @@ -171,14 +179,8 @@ CONFIG_ARCH_KIRKWOOD=y | |||
| 171 | CONFIG_MACH_DB88F6281_BP=y | 179 | CONFIG_MACH_DB88F6281_BP=y |
| 172 | CONFIG_MACH_RD88F6192_NAS=y | 180 | CONFIG_MACH_RD88F6192_NAS=y |
| 173 | CONFIG_MACH_RD88F6281=y | 181 | CONFIG_MACH_RD88F6281=y |
| 174 | 182 | CONFIG_MACH_SHEEVAPLUG=y | |
| 175 | # | 183 | CONFIG_MACH_TS219=y |
| 176 | # Boot options | ||
| 177 | # | ||
| 178 | |||
| 179 | # | ||
| 180 | # Power management | ||
| 181 | # | ||
| 182 | CONFIG_PLAT_ORION=y | 184 | CONFIG_PLAT_ORION=y |
| 183 | 185 | ||
| 184 | # | 186 | # |
| @@ -214,6 +216,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 214 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 216 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 215 | CONFIG_PCI_LEGACY=y | 217 | CONFIG_PCI_LEGACY=y |
| 216 | # CONFIG_PCI_DEBUG is not set | 218 | # CONFIG_PCI_DEBUG is not set |
| 219 | # CONFIG_PCI_STUB is not set | ||
| 217 | # CONFIG_PCCARD is not set | 220 | # CONFIG_PCCARD is not set |
| 218 | 221 | ||
| 219 | # | 222 | # |
| @@ -242,7 +245,6 @@ CONFIG_FLATMEM=y | |||
| 242 | CONFIG_FLAT_NODE_MEM_MAP=y | 245 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 243 | CONFIG_PAGEFLAGS_EXTENDED=y | 246 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 244 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 247 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 245 | # CONFIG_RESOURCES_64BIT is not set | ||
| 246 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 248 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 247 | CONFIG_ZONE_DMA_FLAG=0 | 249 | CONFIG_ZONE_DMA_FLAG=0 |
| 248 | CONFIG_VIRT_TO_BUS=y | 250 | CONFIG_VIRT_TO_BUS=y |
| @@ -291,6 +293,7 @@ CONFIG_NET=y | |||
| 291 | # | 293 | # |
| 292 | # Networking options | 294 | # Networking options |
| 293 | # | 295 | # |
| 296 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 294 | CONFIG_PACKET=y | 297 | CONFIG_PACKET=y |
| 295 | CONFIG_PACKET_MMAP=y | 298 | CONFIG_PACKET_MMAP=y |
| 296 | CONFIG_UNIX=y | 299 | CONFIG_UNIX=y |
| @@ -355,6 +358,7 @@ CONFIG_NET_DSA_MV88E6123_61_65=y | |||
| 355 | # CONFIG_ECONET is not set | 358 | # CONFIG_ECONET is not set |
| 356 | # CONFIG_WAN_ROUTER is not set | 359 | # CONFIG_WAN_ROUTER is not set |
| 357 | # CONFIG_NET_SCHED is not set | 360 | # CONFIG_NET_SCHED is not set |
| 361 | # CONFIG_DCB is not set | ||
| 358 | 362 | ||
| 359 | # | 363 | # |
| 360 | # Network testing | 364 | # Network testing |
| @@ -368,12 +372,27 @@ CONFIG_NET_PKTGEN=m | |||
| 368 | # CONFIG_AF_RXRPC is not set | 372 | # CONFIG_AF_RXRPC is not set |
| 369 | # CONFIG_PHONET is not set | 373 | # CONFIG_PHONET is not set |
| 370 | CONFIG_WIRELESS=y | 374 | CONFIG_WIRELESS=y |
| 371 | # CONFIG_CFG80211 is not set | 375 | CONFIG_CFG80211=y |
| 376 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 377 | # CONFIG_NL80211 is not set | ||
| 372 | CONFIG_WIRELESS_OLD_REGULATORY=y | 378 | CONFIG_WIRELESS_OLD_REGULATORY=y |
| 373 | CONFIG_WIRELESS_EXT=y | 379 | CONFIG_WIRELESS_EXT=y |
| 374 | CONFIG_WIRELESS_EXT_SYSFS=y | 380 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 375 | # CONFIG_MAC80211 is not set | 381 | CONFIG_LIB80211=y |
| 376 | # CONFIG_IEEE80211 is not set | 382 | CONFIG_MAC80211=y |
| 383 | |||
| 384 | # | ||
| 385 | # Rate control algorithm selection | ||
| 386 | # | ||
| 387 | CONFIG_MAC80211_RC_MINSTREL=y | ||
| 388 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set | ||
| 389 | CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y | ||
| 390 | CONFIG_MAC80211_RC_DEFAULT="minstrel" | ||
| 391 | # CONFIG_MAC80211_MESH is not set | ||
| 392 | # CONFIG_MAC80211_LEDS is not set | ||
| 393 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 394 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 395 | # CONFIG_WIMAX is not set | ||
| 377 | # CONFIG_RFKILL is not set | 396 | # CONFIG_RFKILL is not set |
| 378 | # CONFIG_NET_9P is not set | 397 | # CONFIG_NET_9P is not set |
| 379 | 398 | ||
| @@ -398,6 +417,7 @@ CONFIG_MTD=y | |||
| 398 | # CONFIG_MTD_DEBUG is not set | 417 | # CONFIG_MTD_DEBUG is not set |
| 399 | # CONFIG_MTD_CONCAT is not set | 418 | # CONFIG_MTD_CONCAT is not set |
| 400 | CONFIG_MTD_PARTITIONS=y | 419 | CONFIG_MTD_PARTITIONS=y |
| 420 | # CONFIG_MTD_TESTS is not set | ||
| 401 | # CONFIG_MTD_REDBOOT_PARTS is not set | 421 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 402 | CONFIG_MTD_CMDLINE_PARTS=y | 422 | CONFIG_MTD_CMDLINE_PARTS=y |
| 403 | # CONFIG_MTD_AFS_PARTS is not set | 423 | # CONFIG_MTD_AFS_PARTS is not set |
| @@ -451,9 +471,7 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 451 | # | 471 | # |
| 452 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 472 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 453 | CONFIG_MTD_PHYSMAP=y | 473 | CONFIG_MTD_PHYSMAP=y |
| 454 | CONFIG_MTD_PHYSMAP_START=0x0 | 474 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 455 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 456 | CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | ||
| 457 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 475 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 458 | # CONFIG_MTD_IMPA7 is not set | 476 | # CONFIG_MTD_IMPA7 is not set |
| 459 | # CONFIG_MTD_INTEL_VR_NOR is not set | 477 | # CONFIG_MTD_INTEL_VR_NOR is not set |
| @@ -481,6 +499,7 @@ CONFIG_MTD_NAND=y | |||
| 481 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | 499 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set |
| 482 | # CONFIG_MTD_NAND_ECC_SMC is not set | 500 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 483 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | 501 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set |
| 502 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 484 | CONFIG_MTD_NAND_IDS=y | 503 | CONFIG_MTD_NAND_IDS=y |
| 485 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 504 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 486 | # CONFIG_MTD_NAND_CAFE is not set | 505 | # CONFIG_MTD_NAND_CAFE is not set |
| @@ -491,6 +510,12 @@ CONFIG_MTD_NAND_ORION=y | |||
| 491 | # CONFIG_MTD_ONENAND is not set | 510 | # CONFIG_MTD_ONENAND is not set |
| 492 | 511 | ||
| 493 | # | 512 | # |
| 513 | # LPDDR flash memory drivers | ||
| 514 | # | ||
| 515 | # CONFIG_MTD_LPDDR is not set | ||
| 516 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 517 | |||
| 518 | # | ||
| 494 | # UBI - Unsorted block images | 519 | # UBI - Unsorted block images |
| 495 | # | 520 | # |
| 496 | # CONFIG_MTD_UBI is not set | 521 | # CONFIG_MTD_UBI is not set |
| @@ -568,6 +593,8 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 568 | # CONFIG_MEGARAID_LEGACY is not set | 593 | # CONFIG_MEGARAID_LEGACY is not set |
| 569 | # CONFIG_MEGARAID_SAS is not set | 594 | # CONFIG_MEGARAID_SAS is not set |
| 570 | # CONFIG_SCSI_HPTIOP is not set | 595 | # CONFIG_SCSI_HPTIOP is not set |
| 596 | # CONFIG_LIBFC is not set | ||
| 597 | # CONFIG_FCOE is not set | ||
| 571 | # CONFIG_SCSI_DMX3191D is not set | 598 | # CONFIG_SCSI_DMX3191D is not set |
| 572 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 599 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 573 | # CONFIG_SCSI_IPS is not set | 600 | # CONFIG_SCSI_IPS is not set |
| @@ -682,6 +709,9 @@ CONFIG_MARVELL_PHY=y | |||
| 682 | # CONFIG_BROADCOM_PHY is not set | 709 | # CONFIG_BROADCOM_PHY is not set |
| 683 | # CONFIG_ICPLUS_PHY is not set | 710 | # CONFIG_ICPLUS_PHY is not set |
| 684 | # CONFIG_REALTEK_PHY is not set | 711 | # CONFIG_REALTEK_PHY is not set |
| 712 | # CONFIG_NATIONAL_PHY is not set | ||
| 713 | # CONFIG_STE10XP is not set | ||
| 714 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 685 | # CONFIG_FIXED_PHY is not set | 715 | # CONFIG_FIXED_PHY is not set |
| 686 | # CONFIG_MDIO_BITBANG is not set | 716 | # CONFIG_MDIO_BITBANG is not set |
| 687 | CONFIG_NET_ETHERNET=y | 717 | CONFIG_NET_ETHERNET=y |
| @@ -695,6 +725,7 @@ CONFIG_MII=y | |||
| 695 | # CONFIG_DM9000 is not set | 725 | # CONFIG_DM9000 is not set |
| 696 | # CONFIG_ENC28J60 is not set | 726 | # CONFIG_ENC28J60 is not set |
| 697 | # CONFIG_SMC911X is not set | 727 | # CONFIG_SMC911X is not set |
| 728 | # CONFIG_SMSC911X is not set | ||
| 698 | # CONFIG_NET_TULIP is not set | 729 | # CONFIG_NET_TULIP is not set |
| 699 | # CONFIG_HP100 is not set | 730 | # CONFIG_HP100 is not set |
| 700 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 731 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| @@ -710,7 +741,6 @@ CONFIG_NET_PCI=y | |||
| 710 | # CONFIG_ADAPTEC_STARFIRE is not set | 741 | # CONFIG_ADAPTEC_STARFIRE is not set |
| 711 | # CONFIG_B44 is not set | 742 | # CONFIG_B44 is not set |
| 712 | # CONFIG_FORCEDETH is not set | 743 | # CONFIG_FORCEDETH is not set |
| 713 | # CONFIG_EEPRO100 is not set | ||
| 714 | # CONFIG_E100 is not set | 744 | # CONFIG_E100 is not set |
| 715 | # CONFIG_FEALNX is not set | 745 | # CONFIG_FEALNX is not set |
| 716 | # CONFIG_NATSEMI is not set | 746 | # CONFIG_NATSEMI is not set |
| @@ -720,6 +750,7 @@ CONFIG_NET_PCI=y | |||
| 720 | # CONFIG_R6040 is not set | 750 | # CONFIG_R6040 is not set |
| 721 | # CONFIG_SIS900 is not set | 751 | # CONFIG_SIS900 is not set |
| 722 | # CONFIG_EPIC100 is not set | 752 | # CONFIG_EPIC100 is not set |
| 753 | # CONFIG_SMSC9420 is not set | ||
| 723 | # CONFIG_SUNDANCE is not set | 754 | # CONFIG_SUNDANCE is not set |
| 724 | # CONFIG_TLAN is not set | 755 | # CONFIG_TLAN is not set |
| 725 | # CONFIG_VIA_RHINE is not set | 756 | # CONFIG_VIA_RHINE is not set |
| @@ -754,8 +785,39 @@ CONFIG_MV643XX_ETH=y | |||
| 754 | # Wireless LAN | 785 | # Wireless LAN |
| 755 | # | 786 | # |
| 756 | # CONFIG_WLAN_PRE80211 is not set | 787 | # CONFIG_WLAN_PRE80211 is not set |
| 757 | # CONFIG_WLAN_80211 is not set | 788 | CONFIG_WLAN_80211=y |
| 789 | CONFIG_LIBERTAS=y | ||
| 790 | # CONFIG_LIBERTAS_USB is not set | ||
| 791 | CONFIG_LIBERTAS_SDIO=y | ||
| 792 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 793 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 794 | # CONFIG_HERMES is not set | ||
| 795 | # CONFIG_ATMEL is not set | ||
| 796 | # CONFIG_PRISM54 is not set | ||
| 797 | # CONFIG_USB_ZD1201 is not set | ||
| 798 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 799 | # CONFIG_RTL8180 is not set | ||
| 800 | # CONFIG_RTL8187 is not set | ||
| 801 | # CONFIG_ADM8211 is not set | ||
| 802 | # CONFIG_MAC80211_HWSIM is not set | ||
| 803 | # CONFIG_P54_COMMON is not set | ||
| 804 | # CONFIG_ATH5K is not set | ||
| 805 | # CONFIG_ATH9K is not set | ||
| 806 | # CONFIG_IPW2100 is not set | ||
| 807 | # CONFIG_IPW2200 is not set | ||
| 808 | # CONFIG_IWLCORE is not set | ||
| 758 | # CONFIG_IWLWIFI_LEDS is not set | 809 | # CONFIG_IWLWIFI_LEDS is not set |
| 810 | # CONFIG_IWLAGN is not set | ||
| 811 | # CONFIG_IWL3945 is not set | ||
| 812 | # CONFIG_HOSTAP is not set | ||
| 813 | # CONFIG_B43 is not set | ||
| 814 | # CONFIG_B43LEGACY is not set | ||
| 815 | # CONFIG_ZD1211RW is not set | ||
| 816 | # CONFIG_RT2X00 is not set | ||
| 817 | |||
| 818 | # | ||
| 819 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 820 | # | ||
| 759 | 821 | ||
| 760 | # | 822 | # |
| 761 | # USB Network Adapters | 823 | # USB Network Adapters |
| @@ -791,13 +853,20 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 791 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 853 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 792 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 854 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 793 | # CONFIG_INPUT_JOYDEV is not set | 855 | # CONFIG_INPUT_JOYDEV is not set |
| 794 | # CONFIG_INPUT_EVDEV is not set | 856 | CONFIG_INPUT_EVDEV=y |
| 795 | # CONFIG_INPUT_EVBUG is not set | 857 | # CONFIG_INPUT_EVBUG is not set |
| 796 | 858 | ||
| 797 | # | 859 | # |
| 798 | # Input Device Drivers | 860 | # Input Device Drivers |
| 799 | # | 861 | # |
| 800 | # CONFIG_INPUT_KEYBOARD is not set | 862 | CONFIG_INPUT_KEYBOARD=y |
| 863 | CONFIG_KEYBOARD_ATKBD=y | ||
| 864 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 865 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 866 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 867 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 868 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 869 | CONFIG_KEYBOARD_GPIO=y | ||
| 801 | # CONFIG_INPUT_MOUSE is not set | 870 | # CONFIG_INPUT_MOUSE is not set |
| 802 | # CONFIG_INPUT_JOYSTICK is not set | 871 | # CONFIG_INPUT_JOYSTICK is not set |
| 803 | # CONFIG_INPUT_TABLET is not set | 872 | # CONFIG_INPUT_TABLET is not set |
| @@ -807,7 +876,11 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | |||
| 807 | # | 876 | # |
| 808 | # Hardware I/O ports | 877 | # Hardware I/O ports |
| 809 | # | 878 | # |
| 810 | # CONFIG_SERIO is not set | 879 | CONFIG_SERIO=y |
| 880 | CONFIG_SERIO_SERPORT=y | ||
| 881 | # CONFIG_SERIO_PCIPS2 is not set | ||
| 882 | CONFIG_SERIO_LIBPS2=y | ||
| 883 | # CONFIG_SERIO_RAW is not set | ||
| 811 | # CONFIG_GAMEPORT is not set | 884 | # CONFIG_GAMEPORT is not set |
| 812 | 885 | ||
| 813 | # | 886 | # |
| @@ -839,11 +912,11 @@ CONFIG_SERIAL_CORE=y | |||
| 839 | CONFIG_SERIAL_CORE_CONSOLE=y | 912 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 840 | # CONFIG_SERIAL_JSM is not set | 913 | # CONFIG_SERIAL_JSM is not set |
| 841 | CONFIG_UNIX98_PTYS=y | 914 | CONFIG_UNIX98_PTYS=y |
| 915 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 842 | CONFIG_LEGACY_PTYS=y | 916 | CONFIG_LEGACY_PTYS=y |
| 843 | CONFIG_LEGACY_PTY_COUNT=16 | 917 | CONFIG_LEGACY_PTY_COUNT=16 |
| 844 | # CONFIG_IPMI_HANDLER is not set | 918 | # CONFIG_IPMI_HANDLER is not set |
| 845 | # CONFIG_HW_RANDOM is not set | 919 | # CONFIG_HW_RANDOM is not set |
| 846 | # CONFIG_NVRAM is not set | ||
| 847 | # CONFIG_R3964 is not set | 920 | # CONFIG_R3964 is not set |
| 848 | # CONFIG_APPLICOM is not set | 921 | # CONFIG_APPLICOM is not set |
| 849 | # CONFIG_RAW_DRIVER is not set | 922 | # CONFIG_RAW_DRIVER is not set |
| @@ -879,6 +952,7 @@ CONFIG_I2C_HELPER_AUTO=y | |||
| 879 | # | 952 | # |
| 880 | # I2C system bus drivers (mostly embedded / system-on-chip) | 953 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 881 | # | 954 | # |
| 955 | # CONFIG_I2C_GPIO is not set | ||
| 882 | CONFIG_I2C_MV64XXX=y | 956 | CONFIG_I2C_MV64XXX=y |
| 883 | # CONFIG_I2C_OCORES is not set | 957 | # CONFIG_I2C_OCORES is not set |
| 884 | # CONFIG_I2C_SIMTEC is not set | 958 | # CONFIG_I2C_SIMTEC is not set |
| @@ -905,8 +979,6 @@ CONFIG_I2C_MV64XXX=y | |||
| 905 | # Miscellaneous I2C Chip support | 979 | # Miscellaneous I2C Chip support |
| 906 | # | 980 | # |
| 907 | # CONFIG_DS1682 is not set | 981 | # CONFIG_DS1682 is not set |
| 908 | # CONFIG_EEPROM_AT24 is not set | ||
| 909 | # CONFIG_EEPROM_LEGACY is not set | ||
| 910 | # CONFIG_SENSORS_PCF8574 is not set | 982 | # CONFIG_SENSORS_PCF8574 is not set |
| 911 | # CONFIG_PCF8575 is not set | 983 | # CONFIG_PCF8575 is not set |
| 912 | # CONFIG_SENSORS_PCA9539 is not set | 984 | # CONFIG_SENSORS_PCA9539 is not set |
| @@ -925,12 +997,12 @@ CONFIG_SPI_MASTER=y | |||
| 925 | # SPI Master Controller Drivers | 997 | # SPI Master Controller Drivers |
| 926 | # | 998 | # |
| 927 | # CONFIG_SPI_BITBANG is not set | 999 | # CONFIG_SPI_BITBANG is not set |
| 1000 | # CONFIG_SPI_GPIO is not set | ||
| 928 | CONFIG_SPI_ORION=y | 1001 | CONFIG_SPI_ORION=y |
| 929 | 1002 | ||
| 930 | # | 1003 | # |
| 931 | # SPI Protocol Masters | 1004 | # SPI Protocol Masters |
| 932 | # | 1005 | # |
| 933 | # CONFIG_EEPROM_AT25 is not set | ||
| 934 | # CONFIG_SPI_SPIDEV is not set | 1006 | # CONFIG_SPI_SPIDEV is not set |
| 935 | # CONFIG_SPI_TLE62X0 is not set | 1007 | # CONFIG_SPI_TLE62X0 is not set |
| 936 | # CONFIG_W1 is not set | 1008 | # CONFIG_W1 is not set |
| @@ -952,10 +1024,12 @@ CONFIG_SSB_POSSIBLE=y | |||
| 952 | # CONFIG_MFD_CORE is not set | 1024 | # CONFIG_MFD_CORE is not set |
| 953 | # CONFIG_MFD_SM501 is not set | 1025 | # CONFIG_MFD_SM501 is not set |
| 954 | # CONFIG_HTC_PASIC3 is not set | 1026 | # CONFIG_HTC_PASIC3 is not set |
| 1027 | # CONFIG_TWL4030_CORE is not set | ||
| 955 | # CONFIG_MFD_TMIO is not set | 1028 | # CONFIG_MFD_TMIO is not set |
| 956 | # CONFIG_PMIC_DA903X is not set | 1029 | # CONFIG_PMIC_DA903X is not set |
| 957 | # CONFIG_MFD_WM8400 is not set | 1030 | # CONFIG_MFD_WM8400 is not set |
| 958 | # CONFIG_MFD_WM8350_I2C is not set | 1031 | # CONFIG_MFD_WM8350_I2C is not set |
| 1032 | # CONFIG_MFD_PCF50633 is not set | ||
| 959 | 1033 | ||
| 960 | # | 1034 | # |
| 961 | # Multimedia devices | 1035 | # Multimedia devices |
| @@ -1012,11 +1086,9 @@ CONFIG_HID_COMPAT=y | |||
| 1012 | CONFIG_HID_A4TECH=y | 1086 | CONFIG_HID_A4TECH=y |
| 1013 | CONFIG_HID_APPLE=y | 1087 | CONFIG_HID_APPLE=y |
| 1014 | CONFIG_HID_BELKIN=y | 1088 | CONFIG_HID_BELKIN=y |
| 1015 | CONFIG_HID_BRIGHT=y | ||
| 1016 | CONFIG_HID_CHERRY=y | 1089 | CONFIG_HID_CHERRY=y |
| 1017 | CONFIG_HID_CHICONY=y | 1090 | CONFIG_HID_CHICONY=y |
| 1018 | CONFIG_HID_CYPRESS=y | 1091 | CONFIG_HID_CYPRESS=y |
| 1019 | CONFIG_HID_DELL=y | ||
| 1020 | CONFIG_HID_EZKEY=y | 1092 | CONFIG_HID_EZKEY=y |
| 1021 | CONFIG_HID_GYRATION=y | 1093 | CONFIG_HID_GYRATION=y |
| 1022 | CONFIG_HID_LOGITECH=y | 1094 | CONFIG_HID_LOGITECH=y |
| @@ -1024,12 +1096,15 @@ CONFIG_HID_LOGITECH=y | |||
| 1024 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | 1096 | # CONFIG_LOGIRUMBLEPAD2_FF is not set |
| 1025 | CONFIG_HID_MICROSOFT=y | 1097 | CONFIG_HID_MICROSOFT=y |
| 1026 | CONFIG_HID_MONTEREY=y | 1098 | CONFIG_HID_MONTEREY=y |
| 1099 | CONFIG_HID_NTRIG=y | ||
| 1027 | CONFIG_HID_PANTHERLORD=y | 1100 | CONFIG_HID_PANTHERLORD=y |
| 1028 | # CONFIG_PANTHERLORD_FF is not set | 1101 | # CONFIG_PANTHERLORD_FF is not set |
| 1029 | CONFIG_HID_PETALYNX=y | 1102 | CONFIG_HID_PETALYNX=y |
| 1030 | CONFIG_HID_SAMSUNG=y | 1103 | CONFIG_HID_SAMSUNG=y |
| 1031 | CONFIG_HID_SONY=y | 1104 | CONFIG_HID_SONY=y |
| 1032 | CONFIG_HID_SUNPLUS=y | 1105 | CONFIG_HID_SUNPLUS=y |
| 1106 | # CONFIG_GREENASIA_FF is not set | ||
| 1107 | CONFIG_HID_TOPSEED=y | ||
| 1033 | # CONFIG_THRUSTMASTER_FF is not set | 1108 | # CONFIG_THRUSTMASTER_FF is not set |
| 1034 | # CONFIG_ZEROPLUS_FF is not set | 1109 | # CONFIG_ZEROPLUS_FF is not set |
| 1035 | CONFIG_USB_SUPPORT=y | 1110 | CONFIG_USB_SUPPORT=y |
| @@ -1058,6 +1133,7 @@ CONFIG_USB_DEVICE_CLASS=y | |||
| 1058 | CONFIG_USB_EHCI_HCD=y | 1133 | CONFIG_USB_EHCI_HCD=y |
| 1059 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | 1134 | CONFIG_USB_EHCI_ROOT_HUB_TT=y |
| 1060 | CONFIG_USB_EHCI_TT_NEWSCHED=y | 1135 | CONFIG_USB_EHCI_TT_NEWSCHED=y |
| 1136 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1061 | # CONFIG_USB_ISP116X_HCD is not set | 1137 | # CONFIG_USB_ISP116X_HCD is not set |
| 1062 | # CONFIG_USB_ISP1760_HCD is not set | 1138 | # CONFIG_USB_ISP1760_HCD is not set |
| 1063 | # CONFIG_USB_OHCI_HCD is not set | 1139 | # CONFIG_USB_OHCI_HCD is not set |
| @@ -1087,7 +1163,6 @@ CONFIG_USB_STORAGE=y | |||
| 1087 | CONFIG_USB_STORAGE_DATAFAB=y | 1163 | CONFIG_USB_STORAGE_DATAFAB=y |
| 1088 | CONFIG_USB_STORAGE_FREECOM=y | 1164 | CONFIG_USB_STORAGE_FREECOM=y |
| 1089 | # CONFIG_USB_STORAGE_ISD200 is not set | 1165 | # CONFIG_USB_STORAGE_ISD200 is not set |
| 1090 | CONFIG_USB_STORAGE_DPCM=y | ||
| 1091 | # CONFIG_USB_STORAGE_USBAT is not set | 1166 | # CONFIG_USB_STORAGE_USBAT is not set |
| 1092 | CONFIG_USB_STORAGE_SDDR09=y | 1167 | CONFIG_USB_STORAGE_SDDR09=y |
| 1093 | CONFIG_USB_STORAGE_SDDR55=y | 1168 | CONFIG_USB_STORAGE_SDDR55=y |
| @@ -1135,21 +1210,51 @@ CONFIG_USB_STORAGE_JUMPSHOT=y | |||
| 1135 | # CONFIG_USB_ISIGHTFW is not set | 1210 | # CONFIG_USB_ISIGHTFW is not set |
| 1136 | # CONFIG_USB_VST is not set | 1211 | # CONFIG_USB_VST is not set |
| 1137 | # CONFIG_USB_GADGET is not set | 1212 | # CONFIG_USB_GADGET is not set |
| 1213 | |||
| 1214 | # | ||
| 1215 | # OTG and related infrastructure | ||
| 1216 | # | ||
| 1217 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1138 | # CONFIG_UWB is not set | 1218 | # CONFIG_UWB is not set |
| 1139 | # CONFIG_MMC is not set | 1219 | CONFIG_MMC=y |
| 1220 | # CONFIG_MMC_DEBUG is not set | ||
| 1221 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1222 | |||
| 1223 | # | ||
| 1224 | # MMC/SD/SDIO Card Drivers | ||
| 1225 | # | ||
| 1226 | CONFIG_MMC_BLOCK=y | ||
| 1227 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1228 | CONFIG_SDIO_UART=y | ||
| 1229 | # CONFIG_MMC_TEST is not set | ||
| 1230 | |||
| 1231 | # | ||
| 1232 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1233 | # | ||
| 1234 | # CONFIG_MMC_SDHCI is not set | ||
| 1235 | # CONFIG_MMC_TIFM_SD is not set | ||
| 1236 | CONFIG_MMC_MVSDIO=y | ||
| 1237 | # CONFIG_MMC_SPI is not set | ||
| 1140 | # CONFIG_MEMSTICK is not set | 1238 | # CONFIG_MEMSTICK is not set |
| 1141 | # CONFIG_ACCESSIBILITY is not set | 1239 | # CONFIG_ACCESSIBILITY is not set |
| 1142 | CONFIG_NEW_LEDS=y | 1240 | CONFIG_NEW_LEDS=y |
| 1143 | # CONFIG_LEDS_CLASS is not set | 1241 | CONFIG_LEDS_CLASS=y |
| 1144 | 1242 | ||
| 1145 | # | 1243 | # |
| 1146 | # LED drivers | 1244 | # LED drivers |
| 1147 | # | 1245 | # |
| 1246 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1247 | CONFIG_LEDS_GPIO=y | ||
| 1248 | # CONFIG_LEDS_PCA955X is not set | ||
| 1148 | 1249 | ||
| 1149 | # | 1250 | # |
| 1150 | # LED Triggers | 1251 | # LED Triggers |
| 1151 | # | 1252 | # |
| 1152 | # CONFIG_LEDS_TRIGGERS is not set | 1253 | CONFIG_LEDS_TRIGGERS=y |
| 1254 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1255 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1256 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1257 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 1153 | CONFIG_RTC_LIB=y | 1258 | CONFIG_RTC_LIB=y |
| 1154 | CONFIG_RTC_CLASS=y | 1259 | CONFIG_RTC_CLASS=y |
| 1155 | CONFIG_RTC_HCTOSYS=y | 1260 | CONFIG_RTC_HCTOSYS=y |
| @@ -1178,7 +1283,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1178 | # CONFIG_RTC_DRV_PCF8563 is not set | 1283 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1179 | # CONFIG_RTC_DRV_PCF8583 is not set | 1284 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1180 | # CONFIG_RTC_DRV_M41T80 is not set | 1285 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1181 | # CONFIG_RTC_DRV_S35390A is not set | 1286 | CONFIG_RTC_DRV_S35390A=y |
| 1182 | # CONFIG_RTC_DRV_FM3130 is not set | 1287 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1183 | # CONFIG_RTC_DRV_RX8581 is not set | 1288 | # CONFIG_RTC_DRV_RX8581 is not set |
| 1184 | 1289 | ||
| @@ -1227,6 +1332,7 @@ CONFIG_DMA_ENGINE=y | |||
| 1227 | # CONFIG_DMATEST is not set | 1332 | # CONFIG_DMATEST is not set |
| 1228 | # CONFIG_REGULATOR is not set | 1333 | # CONFIG_REGULATOR is not set |
| 1229 | # CONFIG_UIO is not set | 1334 | # CONFIG_UIO is not set |
| 1335 | # CONFIG_STAGING is not set | ||
| 1230 | 1336 | ||
| 1231 | # | 1337 | # |
| 1232 | # File systems | 1338 | # File systems |
| @@ -1238,16 +1344,14 @@ CONFIG_EXT3_FS=y | |||
| 1238 | # CONFIG_EXT3_FS_XATTR is not set | 1344 | # CONFIG_EXT3_FS_XATTR is not set |
| 1239 | # CONFIG_EXT4_FS is not set | 1345 | # CONFIG_EXT4_FS is not set |
| 1240 | CONFIG_JBD=y | 1346 | CONFIG_JBD=y |
| 1347 | # CONFIG_JBD_DEBUG is not set | ||
| 1241 | # CONFIG_REISERFS_FS is not set | 1348 | # CONFIG_REISERFS_FS is not set |
| 1242 | # CONFIG_JFS_FS is not set | 1349 | # CONFIG_JFS_FS is not set |
| 1243 | # CONFIG_FS_POSIX_ACL is not set | 1350 | # CONFIG_FS_POSIX_ACL is not set |
| 1244 | CONFIG_FILE_LOCKING=y | 1351 | CONFIG_FILE_LOCKING=y |
| 1245 | CONFIG_XFS_FS=y | 1352 | # CONFIG_XFS_FS is not set |
| 1246 | # CONFIG_XFS_QUOTA is not set | ||
| 1247 | # CONFIG_XFS_POSIX_ACL is not set | ||
| 1248 | # CONFIG_XFS_RT is not set | ||
| 1249 | # CONFIG_XFS_DEBUG is not set | ||
| 1250 | # CONFIG_OCFS2_FS is not set | 1353 | # CONFIG_OCFS2_FS is not set |
| 1354 | # CONFIG_BTRFS_FS is not set | ||
| 1251 | CONFIG_DNOTIFY=y | 1355 | CONFIG_DNOTIFY=y |
| 1252 | CONFIG_INOTIFY=y | 1356 | CONFIG_INOTIFY=y |
| 1253 | CONFIG_INOTIFY_USER=y | 1357 | CONFIG_INOTIFY_USER=y |
| @@ -1268,9 +1372,9 @@ CONFIG_UDF_NLS=y | |||
| 1268 | # | 1372 | # |
| 1269 | # DOS/FAT/NT Filesystems | 1373 | # DOS/FAT/NT Filesystems |
| 1270 | # | 1374 | # |
| 1271 | CONFIG_FAT_FS=m | 1375 | CONFIG_FAT_FS=y |
| 1272 | CONFIG_MSDOS_FS=m | 1376 | CONFIG_MSDOS_FS=y |
| 1273 | CONFIG_VFAT_FS=m | 1377 | CONFIG_VFAT_FS=y |
| 1274 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | 1378 | CONFIG_FAT_DEFAULT_CODEPAGE=437 |
| 1275 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | 1379 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" |
| 1276 | # CONFIG_NTFS_FS is not set | 1380 | # CONFIG_NTFS_FS is not set |
| @@ -1286,10 +1390,7 @@ CONFIG_TMPFS=y | |||
| 1286 | # CONFIG_TMPFS_POSIX_ACL is not set | 1390 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1287 | # CONFIG_HUGETLB_PAGE is not set | 1391 | # CONFIG_HUGETLB_PAGE is not set |
| 1288 | # CONFIG_CONFIGFS_FS is not set | 1392 | # CONFIG_CONFIGFS_FS is not set |
| 1289 | 1393 | CONFIG_MISC_FILESYSTEMS=y | |
| 1290 | # | ||
| 1291 | # Miscellaneous filesystems | ||
| 1292 | # | ||
| 1293 | # CONFIG_ADFS_FS is not set | 1394 | # CONFIG_ADFS_FS is not set |
| 1294 | # CONFIG_AFFS_FS is not set | 1395 | # CONFIG_AFFS_FS is not set |
| 1295 | # CONFIG_HFS_FS is not set | 1396 | # CONFIG_HFS_FS is not set |
| @@ -1309,6 +1410,7 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1309 | CONFIG_JFFS2_RTIME=y | 1410 | CONFIG_JFFS2_RTIME=y |
| 1310 | # CONFIG_JFFS2_RUBIN is not set | 1411 | # CONFIG_JFFS2_RUBIN is not set |
| 1311 | CONFIG_CRAMFS=y | 1412 | CONFIG_CRAMFS=y |
| 1413 | # CONFIG_SQUASHFS is not set | ||
| 1312 | # CONFIG_VXFS_FS is not set | 1414 | # CONFIG_VXFS_FS is not set |
| 1313 | # CONFIG_MINIX_FS is not set | 1415 | # CONFIG_MINIX_FS is not set |
| 1314 | # CONFIG_OMFS_FS is not set | 1416 | # CONFIG_OMFS_FS is not set |
| @@ -1393,7 +1495,7 @@ CONFIG_ENABLE_MUST_CHECK=y | |||
| 1393 | CONFIG_FRAME_WARN=1024 | 1495 | CONFIG_FRAME_WARN=1024 |
| 1394 | CONFIG_MAGIC_SYSRQ=y | 1496 | CONFIG_MAGIC_SYSRQ=y |
| 1395 | # CONFIG_UNUSED_SYMBOLS is not set | 1497 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1396 | # CONFIG_DEBUG_FS is not set | 1498 | CONFIG_DEBUG_FS=y |
| 1397 | # CONFIG_HEADERS_CHECK is not set | 1499 | # CONFIG_HEADERS_CHECK is not set |
| 1398 | CONFIG_DEBUG_KERNEL=y | 1500 | CONFIG_DEBUG_KERNEL=y |
| 1399 | # CONFIG_DEBUG_SHIRQ is not set | 1501 | # CONFIG_DEBUG_SHIRQ is not set |
| @@ -1416,6 +1518,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | |||
| 1416 | # CONFIG_LOCK_STAT is not set | 1518 | # CONFIG_LOCK_STAT is not set |
| 1417 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1519 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1418 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1520 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1521 | CONFIG_STACKTRACE=y | ||
| 1419 | # CONFIG_DEBUG_KOBJECT is not set | 1522 | # CONFIG_DEBUG_KOBJECT is not set |
| 1420 | CONFIG_DEBUG_BUGVERBOSE=y | 1523 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1421 | CONFIG_DEBUG_INFO=y | 1524 | CONFIG_DEBUG_INFO=y |
| @@ -1424,7 +1527,7 @@ CONFIG_DEBUG_INFO=y | |||
| 1424 | CONFIG_DEBUG_MEMORY_INIT=y | 1527 | CONFIG_DEBUG_MEMORY_INIT=y |
| 1425 | # CONFIG_DEBUG_LIST is not set | 1528 | # CONFIG_DEBUG_LIST is not set |
| 1426 | # CONFIG_DEBUG_SG is not set | 1529 | # CONFIG_DEBUG_SG is not set |
| 1427 | CONFIG_FRAME_POINTER=y | 1530 | # CONFIG_DEBUG_NOTIFIERS is not set |
| 1428 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1531 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1429 | # CONFIG_RCU_TORTURE_TEST is not set | 1532 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1430 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 1533 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| @@ -1435,7 +1538,10 @@ CONFIG_FRAME_POINTER=y | |||
| 1435 | # CONFIG_FAULT_INJECTION is not set | 1538 | # CONFIG_FAULT_INJECTION is not set |
| 1436 | # CONFIG_LATENCYTOP is not set | 1539 | # CONFIG_LATENCYTOP is not set |
| 1437 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 1540 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 1541 | CONFIG_NOP_TRACER=y | ||
| 1438 | CONFIG_HAVE_FUNCTION_TRACER=y | 1542 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1543 | CONFIG_RING_BUFFER=y | ||
| 1544 | CONFIG_TRACING=y | ||
| 1439 | 1545 | ||
| 1440 | # | 1546 | # |
| 1441 | # Tracers | 1547 | # Tracers |
| @@ -1446,11 +1552,14 @@ CONFIG_HAVE_FUNCTION_TRACER=y | |||
| 1446 | # CONFIG_SCHED_TRACER is not set | 1552 | # CONFIG_SCHED_TRACER is not set |
| 1447 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 1553 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 1448 | # CONFIG_BOOT_TRACER is not set | 1554 | # CONFIG_BOOT_TRACER is not set |
| 1555 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1449 | # CONFIG_STACK_TRACER is not set | 1556 | # CONFIG_STACK_TRACER is not set |
| 1557 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1450 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | 1558 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set |
| 1451 | # CONFIG_SAMPLES is not set | 1559 | # CONFIG_SAMPLES is not set |
| 1452 | CONFIG_HAVE_ARCH_KGDB=y | 1560 | CONFIG_HAVE_ARCH_KGDB=y |
| 1453 | # CONFIG_KGDB is not set | 1561 | # CONFIG_KGDB is not set |
| 1562 | CONFIG_ARM_UNWIND=y | ||
| 1454 | CONFIG_DEBUG_USER=y | 1563 | CONFIG_DEBUG_USER=y |
| 1455 | CONFIG_DEBUG_ERRORS=y | 1564 | CONFIG_DEBUG_ERRORS=y |
| 1456 | # CONFIG_DEBUG_STACK_USAGE is not set | 1565 | # CONFIG_DEBUG_STACK_USAGE is not set |
| @@ -1464,19 +1573,22 @@ CONFIG_DEBUG_LL=y | |||
| 1464 | # CONFIG_SECURITY is not set | 1573 | # CONFIG_SECURITY is not set |
| 1465 | # CONFIG_SECURITYFS is not set | 1574 | # CONFIG_SECURITYFS is not set |
| 1466 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1575 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1467 | CONFIG_ASYNC_CORE=y | ||
| 1468 | CONFIG_CRYPTO=y | 1576 | CONFIG_CRYPTO=y |
| 1469 | 1577 | ||
| 1470 | # | 1578 | # |
| 1471 | # Crypto core or helper | 1579 | # Crypto core or helper |
| 1472 | # | 1580 | # |
| 1473 | # CONFIG_CRYPTO_FIPS is not set | 1581 | # CONFIG_CRYPTO_FIPS is not set |
| 1474 | CONFIG_CRYPTO_ALGAPI=m | 1582 | CONFIG_CRYPTO_ALGAPI=y |
| 1475 | CONFIG_CRYPTO_AEAD=m | 1583 | CONFIG_CRYPTO_ALGAPI2=y |
| 1476 | CONFIG_CRYPTO_BLKCIPHER=m | 1584 | CONFIG_CRYPTO_AEAD2=y |
| 1477 | CONFIG_CRYPTO_HASH=m | 1585 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1478 | CONFIG_CRYPTO_RNG=m | 1586 | CONFIG_CRYPTO_BLKCIPHER2=y |
| 1479 | CONFIG_CRYPTO_MANAGER=m | 1587 | CONFIG_CRYPTO_HASH=y |
| 1588 | CONFIG_CRYPTO_HASH2=y | ||
| 1589 | CONFIG_CRYPTO_RNG2=y | ||
| 1590 | CONFIG_CRYPTO_MANAGER=y | ||
| 1591 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1480 | # CONFIG_CRYPTO_GF128MUL is not set | 1592 | # CONFIG_CRYPTO_GF128MUL is not set |
| 1481 | # CONFIG_CRYPTO_NULL is not set | 1593 | # CONFIG_CRYPTO_NULL is not set |
| 1482 | # CONFIG_CRYPTO_CRYPTD is not set | 1594 | # CONFIG_CRYPTO_CRYPTD is not set |
| @@ -1496,7 +1608,7 @@ CONFIG_CRYPTO_MANAGER=m | |||
| 1496 | CONFIG_CRYPTO_CBC=m | 1608 | CONFIG_CRYPTO_CBC=m |
| 1497 | # CONFIG_CRYPTO_CTR is not set | 1609 | # CONFIG_CRYPTO_CTR is not set |
| 1498 | # CONFIG_CRYPTO_CTS is not set | 1610 | # CONFIG_CRYPTO_CTS is not set |
| 1499 | CONFIG_CRYPTO_ECB=m | 1611 | CONFIG_CRYPTO_ECB=y |
| 1500 | # CONFIG_CRYPTO_LRW is not set | 1612 | # CONFIG_CRYPTO_LRW is not set |
| 1501 | CONFIG_CRYPTO_PCBC=m | 1613 | CONFIG_CRYPTO_PCBC=m |
| 1502 | # CONFIG_CRYPTO_XTS is not set | 1614 | # CONFIG_CRYPTO_XTS is not set |
| @@ -1510,7 +1622,7 @@ CONFIG_CRYPTO_PCBC=m | |||
| 1510 | # | 1622 | # |
| 1511 | # Digest | 1623 | # Digest |
| 1512 | # | 1624 | # |
| 1513 | # CONFIG_CRYPTO_CRC32C is not set | 1625 | CONFIG_CRYPTO_CRC32C=y |
| 1514 | # CONFIG_CRYPTO_MD4 is not set | 1626 | # CONFIG_CRYPTO_MD4 is not set |
| 1515 | # CONFIG_CRYPTO_MD5 is not set | 1627 | # CONFIG_CRYPTO_MD5 is not set |
| 1516 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1628 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
| @@ -1527,9 +1639,9 @@ CONFIG_CRYPTO_PCBC=m | |||
| 1527 | # | 1639 | # |
| 1528 | # Ciphers | 1640 | # Ciphers |
| 1529 | # | 1641 | # |
| 1530 | # CONFIG_CRYPTO_AES is not set | 1642 | CONFIG_CRYPTO_AES=y |
| 1531 | # CONFIG_CRYPTO_ANUBIS is not set | 1643 | # CONFIG_CRYPTO_ANUBIS is not set |
| 1532 | # CONFIG_CRYPTO_ARC4 is not set | 1644 | CONFIG_CRYPTO_ARC4=y |
| 1533 | # CONFIG_CRYPTO_BLOWFISH is not set | 1645 | # CONFIG_CRYPTO_BLOWFISH is not set |
| 1534 | # CONFIG_CRYPTO_CAMELLIA is not set | 1646 | # CONFIG_CRYPTO_CAMELLIA is not set |
| 1535 | # CONFIG_CRYPTO_CAST5 is not set | 1647 | # CONFIG_CRYPTO_CAST5 is not set |
| @@ -1560,6 +1672,7 @@ CONFIG_CRYPTO_HW=y | |||
| 1560 | # Library routines | 1672 | # Library routines |
| 1561 | # | 1673 | # |
| 1562 | CONFIG_BITREVERSE=y | 1674 | CONFIG_BITREVERSE=y |
| 1675 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1563 | CONFIG_CRC_CCITT=y | 1676 | CONFIG_CRC_CCITT=y |
| 1564 | CONFIG_CRC16=y | 1677 | CONFIG_CRC16=y |
| 1565 | # CONFIG_CRC_T10DIF is not set | 1678 | # CONFIG_CRC_T10DIF is not set |
diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig index a1cc34f25602..56ae56899d2e 100644 --- a/arch/arm/configs/lart_defconfig +++ b/arch/arm/configs/lart_defconfig | |||
| @@ -87,7 +87,6 @@ CONFIG_ARCH_SA1100=y | |||
| 87 | # CONFIG_SA1100_COLLIE is not set | 87 | # CONFIG_SA1100_COLLIE is not set |
| 88 | # CONFIG_SA1100_H3100 is not set | 88 | # CONFIG_SA1100_H3100 is not set |
| 89 | # CONFIG_SA1100_H3600 is not set | 89 | # CONFIG_SA1100_H3600 is not set |
| 90 | # CONFIG_SA1100_H3800 is not set | ||
| 91 | # CONFIG_SA1100_BADGE4 is not set | 90 | # CONFIG_SA1100_BADGE4 is not set |
| 92 | # CONFIG_SA1100_JORNADA720 is not set | 91 | # CONFIG_SA1100_JORNADA720 is not set |
| 93 | # CONFIG_SA1100_HACKKIT is not set | 92 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index 73ba62b71063..82428c2f234c 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig | |||
| @@ -1,9 +1,10 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24-rc6 | 3 | # Linux kernel version: 2.6.29-rc3 |
| 4 | # Sun Dec 30 13:02:54 2007 | 4 | # Fri Jan 30 12:42:03 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_HAVE_PWM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 8 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 9 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_GENERIC_TIME=y | 10 | CONFIG_GENERIC_TIME=y |
| @@ -12,6 +13,7 @@ CONFIG_MMU=y | |||
| 12 | # CONFIG_NO_IOPORT is not set | 13 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | 14 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 15 | CONFIG_STACKTRACE_SUPPORT=y |
| 16 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | 17 | CONFIG_LOCKDEP_SUPPORT=y |
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 18 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | 19 | CONFIG_HARDIRQS_SW_RESEND=y |
| @@ -21,8 +23,8 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 23 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 22 | CONFIG_GENERIC_HWEIGHT=y | 24 | CONFIG_GENERIC_HWEIGHT=y |
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 25 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | 26 | CONFIG_ARCH_MTD_XIP=y |
| 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | 28 | CONFIG_VECTORS_BASE=0xffff0000 |
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 29 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 28 | 30 | ||
| @@ -41,16 +43,24 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 41 | # CONFIG_POSIX_MQUEUE is not set | 43 | # CONFIG_POSIX_MQUEUE is not set |
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | 44 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 43 | # CONFIG_TASKSTATS is not set | 45 | # CONFIG_TASKSTATS is not set |
| 44 | # CONFIG_USER_NS is not set | ||
| 45 | # CONFIG_PID_NS is not set | ||
| 46 | # CONFIG_AUDIT is not set | 46 | # CONFIG_AUDIT is not set |
| 47 | |||
| 48 | # | ||
| 49 | # RCU Subsystem | ||
| 50 | # | ||
| 51 | CONFIG_CLASSIC_RCU=y | ||
| 52 | # CONFIG_TREE_RCU is not set | ||
| 53 | # CONFIG_PREEMPT_RCU is not set | ||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 55 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 47 | CONFIG_IKCONFIG=y | 56 | CONFIG_IKCONFIG=y |
| 48 | CONFIG_IKCONFIG_PROC=y | 57 | CONFIG_IKCONFIG_PROC=y |
| 49 | CONFIG_LOG_BUF_SHIFT=16 | 58 | CONFIG_LOG_BUF_SHIFT=16 |
| 59 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | # CONFIG_CGROUPS is not set | 60 | # CONFIG_CGROUPS is not set |
| 51 | # CONFIG_FAIR_GROUP_SCHED is not set | 61 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 52 | # CONFIG_SYSFS_DEPRECATED is not set | ||
| 53 | # CONFIG_RELAY is not set | 62 | # CONFIG_RELAY is not set |
| 63 | # CONFIG_NAMESPACES is not set | ||
| 54 | CONFIG_BLK_DEV_INITRD=y | 64 | CONFIG_BLK_DEV_INITRD=y |
| 55 | CONFIG_INITRAMFS_SOURCE="" | 65 | CONFIG_INITRAMFS_SOURCE="" |
| 56 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 66 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| @@ -65,31 +75,41 @@ CONFIG_HOTPLUG=y | |||
| 65 | CONFIG_PRINTK=y | 75 | CONFIG_PRINTK=y |
| 66 | CONFIG_BUG=y | 76 | CONFIG_BUG=y |
| 67 | CONFIG_ELF_CORE=y | 77 | CONFIG_ELF_CORE=y |
| 78 | CONFIG_COMPAT_BRK=y | ||
| 68 | CONFIG_BASE_FULL=y | 79 | CONFIG_BASE_FULL=y |
| 69 | CONFIG_FUTEX=y | 80 | CONFIG_FUTEX=y |
| 70 | CONFIG_ANON_INODES=y | 81 | CONFIG_ANON_INODES=y |
| 71 | CONFIG_EPOLL=y | 82 | CONFIG_EPOLL=y |
| 72 | CONFIG_SIGNALFD=y | 83 | CONFIG_SIGNALFD=y |
| 84 | CONFIG_TIMERFD=y | ||
| 73 | CONFIG_EVENTFD=y | 85 | CONFIG_EVENTFD=y |
| 74 | CONFIG_SHMEM=y | 86 | CONFIG_SHMEM=y |
| 87 | CONFIG_AIO=y | ||
| 75 | CONFIG_VM_EVENT_COUNTERS=y | 88 | CONFIG_VM_EVENT_COUNTERS=y |
| 76 | CONFIG_SLAB=y | 89 | CONFIG_SLAB=y |
| 77 | # CONFIG_SLUB is not set | 90 | # CONFIG_SLUB is not set |
| 78 | # CONFIG_SLOB is not set | 91 | # CONFIG_SLOB is not set |
| 92 | # CONFIG_PROFILING is not set | ||
| 93 | CONFIG_HAVE_OPROFILE=y | ||
| 94 | # CONFIG_KPROBES is not set | ||
| 95 | CONFIG_HAVE_KPROBES=y | ||
| 96 | CONFIG_HAVE_KRETPROBES=y | ||
| 97 | CONFIG_HAVE_CLK=y | ||
| 98 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 99 | CONFIG_SLABINFO=y | ||
| 79 | CONFIG_RT_MUTEXES=y | 100 | CONFIG_RT_MUTEXES=y |
| 80 | # CONFIG_TINY_SHMEM is not set | ||
| 81 | CONFIG_BASE_SMALL=0 | 101 | CONFIG_BASE_SMALL=0 |
| 82 | CONFIG_MODULES=y | 102 | CONFIG_MODULES=y |
| 103 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 83 | CONFIG_MODULE_UNLOAD=y | 104 | CONFIG_MODULE_UNLOAD=y |
| 84 | CONFIG_MODULE_FORCE_UNLOAD=y | 105 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 85 | # CONFIG_MODVERSIONS is not set | 106 | # CONFIG_MODVERSIONS is not set |
| 86 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 107 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 87 | CONFIG_KMOD=y | ||
| 88 | CONFIG_BLOCK=y | 108 | CONFIG_BLOCK=y |
| 89 | # CONFIG_LBD is not set | 109 | # CONFIG_LBD is not set |
| 90 | # CONFIG_BLK_DEV_IO_TRACE is not set | 110 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 91 | # CONFIG_LSF is not set | ||
| 92 | # CONFIG_BLK_DEV_BSG is not set | 111 | # CONFIG_BLK_DEV_BSG is not set |
| 112 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 93 | 113 | ||
| 94 | # | 114 | # |
| 95 | # IO Schedulers | 115 | # IO Schedulers |
| @@ -103,8 +123,7 @@ CONFIG_IOSCHED_NOOP=y | |||
| 103 | # CONFIG_DEFAULT_CFQ is not set | 123 | # CONFIG_DEFAULT_CFQ is not set |
| 104 | CONFIG_DEFAULT_NOOP=y | 124 | CONFIG_DEFAULT_NOOP=y |
| 105 | CONFIG_DEFAULT_IOSCHED="noop" | 125 | CONFIG_DEFAULT_IOSCHED="noop" |
| 106 | CONFIG_CLASSIC_RCU=y | 126 | CONFIG_FREEZER=y |
| 107 | # CONFIG_PREEMPT_RCU is not set | ||
| 108 | 127 | ||
| 109 | # | 128 | # |
| 110 | # System Type | 129 | # System Type |
| @@ -114,9 +133,7 @@ CONFIG_CLASSIC_RCU=y | |||
| 114 | # CONFIG_ARCH_REALVIEW is not set | 133 | # CONFIG_ARCH_REALVIEW is not set |
| 115 | # CONFIG_ARCH_VERSATILE is not set | 134 | # CONFIG_ARCH_VERSATILE is not set |
| 116 | # CONFIG_ARCH_AT91 is not set | 135 | # CONFIG_ARCH_AT91 is not set |
| 117 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 118 | # CONFIG_ARCH_CLPS711X is not set | 136 | # CONFIG_ARCH_CLPS711X is not set |
| 119 | # CONFIG_ARCH_CO285 is not set | ||
| 120 | # CONFIG_ARCH_EBSA110 is not set | 137 | # CONFIG_ARCH_EBSA110 is not set |
| 121 | # CONFIG_ARCH_EP93XX is not set | 138 | # CONFIG_ARCH_EP93XX is not set |
| 122 | # CONFIG_ARCH_FOOTBRIDGE is not set | 139 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| @@ -130,41 +147,58 @@ CONFIG_CLASSIC_RCU=y | |||
| 130 | # CONFIG_ARCH_IXP2000 is not set | 147 | # CONFIG_ARCH_IXP2000 is not set |
| 131 | # CONFIG_ARCH_IXP4XX is not set | 148 | # CONFIG_ARCH_IXP4XX is not set |
| 132 | # CONFIG_ARCH_L7200 is not set | 149 | # CONFIG_ARCH_L7200 is not set |
| 150 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 133 | # CONFIG_ARCH_KS8695 is not set | 151 | # CONFIG_ARCH_KS8695 is not set |
| 134 | # CONFIG_ARCH_NS9XXX is not set | 152 | # CONFIG_ARCH_NS9XXX is not set |
| 153 | # CONFIG_ARCH_LOKI is not set | ||
| 154 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 135 | # CONFIG_ARCH_MXC is not set | 155 | # CONFIG_ARCH_MXC is not set |
| 156 | # CONFIG_ARCH_ORION5X is not set | ||
| 136 | # CONFIG_ARCH_PNX4008 is not set | 157 | # CONFIG_ARCH_PNX4008 is not set |
| 137 | CONFIG_ARCH_PXA=y | 158 | CONFIG_ARCH_PXA=y |
| 138 | # CONFIG_ARCH_RPC is not set | 159 | # CONFIG_ARCH_RPC is not set |
| 139 | # CONFIG_ARCH_SA1100 is not set | 160 | # CONFIG_ARCH_SA1100 is not set |
| 140 | # CONFIG_ARCH_S3C2410 is not set | 161 | # CONFIG_ARCH_S3C2410 is not set |
| 162 | # CONFIG_ARCH_S3C64XX is not set | ||
| 141 | # CONFIG_ARCH_SHARK is not set | 163 | # CONFIG_ARCH_SHARK is not set |
| 142 | # CONFIG_ARCH_LH7A40X is not set | 164 | # CONFIG_ARCH_LH7A40X is not set |
| 143 | # CONFIG_ARCH_DAVINCI is not set | 165 | # CONFIG_ARCH_DAVINCI is not set |
| 144 | # CONFIG_ARCH_OMAP is not set | 166 | # CONFIG_ARCH_OMAP is not set |
| 167 | # CONFIG_ARCH_MSM is not set | ||
| 168 | # CONFIG_ARCH_W90X900 is not set | ||
| 145 | 169 | ||
| 146 | # | 170 | # |
| 147 | # Intel PXA2xx/PXA3xx Implementations | 171 | # Intel PXA2xx/PXA3xx Implementations |
| 148 | # | 172 | # |
| 173 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 174 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 149 | # CONFIG_ARCH_LUBBOCK is not set | 175 | # CONFIG_ARCH_LUBBOCK is not set |
| 150 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 176 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 151 | # CONFIG_MACH_MAINSTONE is not set | 177 | # CONFIG_MACH_MAINSTONE is not set |
| 178 | # CONFIG_MACH_MP900C is not set | ||
| 152 | # CONFIG_ARCH_PXA_IDP is not set | 179 | # CONFIG_ARCH_PXA_IDP is not set |
| 153 | # CONFIG_PXA_SHARPSL is not set | 180 | # CONFIG_PXA_SHARPSL is not set |
| 154 | # CONFIG_MACH_TRIZEPS4 is not set | 181 | # CONFIG_ARCH_VIPER is not set |
| 182 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 183 | # CONFIG_TRIZEPS_PXA is not set | ||
| 184 | # CONFIG_MACH_H5000 is not set | ||
| 155 | # CONFIG_MACH_EM_X270 is not set | 185 | # CONFIG_MACH_EM_X270 is not set |
| 186 | # CONFIG_MACH_COLIBRI is not set | ||
| 156 | # CONFIG_MACH_ZYLONITE is not set | 187 | # CONFIG_MACH_ZYLONITE is not set |
| 188 | # CONFIG_MACH_LITTLETON is not set | ||
| 189 | # CONFIG_MACH_TAVOREVB is not set | ||
| 190 | # CONFIG_MACH_SAAR is not set | ||
| 157 | # CONFIG_MACH_ARMCORE is not set | 191 | # CONFIG_MACH_ARMCORE is not set |
| 192 | # CONFIG_MACH_CM_X300 is not set | ||
| 158 | CONFIG_MACH_MAGICIAN=y | 193 | CONFIG_MACH_MAGICIAN=y |
| 194 | # CONFIG_MACH_MIOA701 is not set | ||
| 195 | # CONFIG_MACH_PCM027 is not set | ||
| 196 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 197 | # CONFIG_PXA_EZX is not set | ||
| 159 | CONFIG_PXA27x=y | 198 | CONFIG_PXA27x=y |
| 160 | 199 | CONFIG_PXA_SSP=y | |
| 161 | # | 200 | CONFIG_PXA_PWM=y |
| 162 | # Boot options | 201 | CONFIG_PXA_HAVE_BOARD_IRQS=y |
| 163 | # | ||
| 164 | |||
| 165 | # | ||
| 166 | # Power management | ||
| 167 | # | ||
| 168 | 202 | ||
| 169 | # | 203 | # |
| 170 | # Processor Type | 204 | # Processor Type |
| @@ -173,6 +207,7 @@ CONFIG_CPU_32=y | |||
| 173 | CONFIG_CPU_XSCALE=y | 207 | CONFIG_CPU_XSCALE=y |
| 174 | CONFIG_CPU_32v5=y | 208 | CONFIG_CPU_32v5=y |
| 175 | CONFIG_CPU_ABRT_EV5T=y | 209 | CONFIG_CPU_ABRT_EV5T=y |
| 210 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 176 | CONFIG_CPU_CACHE_VIVT=y | 211 | CONFIG_CPU_CACHE_VIVT=y |
| 177 | CONFIG_CPU_TLB_V4WBI=y | 212 | CONFIG_CPU_TLB_V4WBI=y |
| 178 | CONFIG_CPU_CP15=y | 213 | CONFIG_CPU_CP15=y |
| @@ -186,6 +221,7 @@ CONFIG_ARM_THUMB=y | |||
| 186 | # CONFIG_OUTER_CACHE is not set | 221 | # CONFIG_OUTER_CACHE is not set |
| 187 | CONFIG_IWMMXT=y | 222 | CONFIG_IWMMXT=y |
| 188 | CONFIG_XSCALE_PMU=y | 223 | CONFIG_XSCALE_PMU=y |
| 224 | CONFIG_COMMON_CLKDEV=y | ||
| 189 | 225 | ||
| 190 | # | 226 | # |
| 191 | # Bus support | 227 | # Bus support |
| @@ -197,28 +233,33 @@ CONFIG_XSCALE_PMU=y | |||
| 197 | # | 233 | # |
| 198 | # Kernel Features | 234 | # Kernel Features |
| 199 | # | 235 | # |
| 200 | # CONFIG_TICK_ONESHOT is not set | 236 | CONFIG_TICK_ONESHOT=y |
| 201 | # CONFIG_NO_HZ is not set | 237 | CONFIG_NO_HZ=y |
| 202 | # CONFIG_HIGH_RES_TIMERS is not set | 238 | # CONFIG_HIGH_RES_TIMERS is not set |
| 203 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 239 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 240 | CONFIG_VMSPLIT_3G=y | ||
| 241 | # CONFIG_VMSPLIT_2G is not set | ||
| 242 | # CONFIG_VMSPLIT_1G is not set | ||
| 243 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 204 | CONFIG_PREEMPT=y | 244 | CONFIG_PREEMPT=y |
| 205 | CONFIG_HZ=100 | 245 | CONFIG_HZ=100 |
| 206 | CONFIG_AEABI=y | 246 | CONFIG_AEABI=y |
| 207 | CONFIG_OABI_COMPAT=y | 247 | CONFIG_OABI_COMPAT=y |
| 208 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | 248 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y |
| 249 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 250 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 209 | CONFIG_SELECT_MEMORY_MODEL=y | 251 | CONFIG_SELECT_MEMORY_MODEL=y |
| 210 | CONFIG_FLATMEM_MANUAL=y | 252 | CONFIG_FLATMEM_MANUAL=y |
| 211 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 253 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 212 | # CONFIG_SPARSEMEM_MANUAL is not set | 254 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 213 | CONFIG_FLATMEM=y | 255 | CONFIG_FLATMEM=y |
| 214 | CONFIG_FLAT_NODE_MEM_MAP=y | 256 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 215 | # CONFIG_SPARSEMEM_STATIC is not set | 257 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 216 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 217 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 258 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 218 | # CONFIG_RESOURCES_64BIT is not set | 259 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 219 | CONFIG_ZONE_DMA_FLAG=1 | 260 | CONFIG_ZONE_DMA_FLAG=0 |
| 220 | CONFIG_BOUNCE=y | ||
| 221 | CONFIG_VIRT_TO_BUS=y | 261 | CONFIG_VIRT_TO_BUS=y |
| 262 | CONFIG_UNEVICTABLE_LRU=y | ||
| 222 | CONFIG_ALIGNMENT_TRAP=y | 263 | CONFIG_ALIGNMENT_TRAP=y |
| 223 | 264 | ||
| 224 | # | 265 | # |
| @@ -229,9 +270,10 @@ CONFIG_ZBOOT_ROM_BSS=0x0 | |||
| 229 | CONFIG_CMDLINE="keepinitrd" | 270 | CONFIG_CMDLINE="keepinitrd" |
| 230 | # CONFIG_XIP_KERNEL is not set | 271 | # CONFIG_XIP_KERNEL is not set |
| 231 | CONFIG_KEXEC=y | 272 | CONFIG_KEXEC=y |
| 273 | CONFIG_ATAGS_PROC=y | ||
| 232 | 274 | ||
| 233 | # | 275 | # |
| 234 | # CPU Frequency scaling | 276 | # CPU Power Management |
| 235 | # | 277 | # |
| 236 | CONFIG_CPU_FREQ=y | 278 | CONFIG_CPU_FREQ=y |
| 237 | CONFIG_CPU_FREQ_TABLE=y | 279 | CONFIG_CPU_FREQ_TABLE=y |
| @@ -239,6 +281,7 @@ CONFIG_CPU_FREQ_TABLE=y | |||
| 239 | CONFIG_CPU_FREQ_STAT=y | 281 | CONFIG_CPU_FREQ_STAT=y |
| 240 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | 282 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set |
| 241 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | 283 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y |
| 284 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 242 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | 285 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set |
| 243 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | 286 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set |
| 244 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | 287 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set |
| @@ -247,6 +290,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | |||
| 247 | # CONFIG_CPU_FREQ_GOV_USERSPACE is not set | 290 | # CONFIG_CPU_FREQ_GOV_USERSPACE is not set |
| 248 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | 291 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y |
| 249 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | 292 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set |
| 293 | # CONFIG_CPU_IDLE is not set | ||
| 250 | 294 | ||
| 251 | # | 295 | # |
| 252 | # Floating point emulation | 296 | # Floating point emulation |
| @@ -263,6 +307,8 @@ CONFIG_FPE_NWFPE=y | |||
| 263 | # Userspace binary formats | 307 | # Userspace binary formats |
| 264 | # | 308 | # |
| 265 | CONFIG_BINFMT_ELF=y | 309 | CONFIG_BINFMT_ELF=y |
| 310 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 311 | CONFIG_HAVE_AOUT=y | ||
| 266 | # CONFIG_BINFMT_AOUT is not set | 312 | # CONFIG_BINFMT_AOUT is not set |
| 267 | # CONFIG_BINFMT_MISC is not set | 313 | # CONFIG_BINFMT_MISC is not set |
| 268 | 314 | ||
| @@ -270,21 +316,18 @@ CONFIG_BINFMT_ELF=y | |||
| 270 | # Power management options | 316 | # Power management options |
| 271 | # | 317 | # |
| 272 | CONFIG_PM=y | 318 | CONFIG_PM=y |
| 273 | # CONFIG_PM_LEGACY is not set | ||
| 274 | # CONFIG_PM_DEBUG is not set | 319 | # CONFIG_PM_DEBUG is not set |
| 275 | CONFIG_PM_SLEEP=y | 320 | CONFIG_PM_SLEEP=y |
| 276 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 277 | CONFIG_SUSPEND=y | 321 | CONFIG_SUSPEND=y |
| 278 | CONFIG_APM_EMULATION=y | 322 | CONFIG_SUSPEND_FREEZER=y |
| 279 | 323 | # CONFIG_APM_EMULATION is not set | |
| 280 | # | 324 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 281 | # Networking | ||
| 282 | # | ||
| 283 | CONFIG_NET=y | 325 | CONFIG_NET=y |
| 284 | 326 | ||
| 285 | # | 327 | # |
| 286 | # Networking options | 328 | # Networking options |
| 287 | # | 329 | # |
| 330 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 288 | CONFIG_PACKET=y | 331 | CONFIG_PACKET=y |
| 289 | CONFIG_PACKET_MMAP=y | 332 | CONFIG_PACKET_MMAP=y |
| 290 | CONFIG_UNIX=y | 333 | CONFIG_UNIX=y |
| @@ -316,33 +359,15 @@ CONFIG_IP_PNP=y | |||
| 316 | CONFIG_TCP_CONG_CUBIC=y | 359 | CONFIG_TCP_CONG_CUBIC=y |
| 317 | CONFIG_DEFAULT_TCP_CONG="cubic" | 360 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 318 | # CONFIG_TCP_MD5SIG is not set | 361 | # CONFIG_TCP_MD5SIG is not set |
| 319 | # CONFIG_IP_VS is not set | ||
| 320 | # CONFIG_IPV6 is not set | 362 | # CONFIG_IPV6 is not set |
| 321 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 322 | # CONFIG_INET6_TUNNEL is not set | ||
| 323 | # CONFIG_NETWORK_SECMARK is not set | 363 | # CONFIG_NETWORK_SECMARK is not set |
| 324 | CONFIG_NETFILTER=y | 364 | # CONFIG_NETFILTER is not set |
| 325 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 326 | |||
| 327 | # | ||
| 328 | # Core Netfilter Configuration | ||
| 329 | # | ||
| 330 | # CONFIG_NETFILTER_NETLINK is not set | ||
| 331 | # CONFIG_NF_CONNTRACK_ENABLED is not set | ||
| 332 | # CONFIG_NF_CONNTRACK is not set | ||
| 333 | # CONFIG_NETFILTER_XTABLES is not set | ||
| 334 | |||
| 335 | # | ||
| 336 | # IP: Netfilter Configuration | ||
| 337 | # | ||
| 338 | # CONFIG_IP_NF_QUEUE is not set | ||
| 339 | # CONFIG_IP_NF_IPTABLES is not set | ||
| 340 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 341 | # CONFIG_IP_DCCP is not set | 365 | # CONFIG_IP_DCCP is not set |
| 342 | # CONFIG_IP_SCTP is not set | 366 | # CONFIG_IP_SCTP is not set |
| 343 | # CONFIG_TIPC is not set | 367 | # CONFIG_TIPC is not set |
| 344 | # CONFIG_ATM is not set | 368 | # CONFIG_ATM is not set |
| 345 | # CONFIG_BRIDGE is not set | 369 | # CONFIG_BRIDGE is not set |
| 370 | # CONFIG_NET_DSA is not set | ||
| 346 | # CONFIG_VLAN_8021Q is not set | 371 | # CONFIG_VLAN_8021Q is not set |
| 347 | # CONFIG_DECNET is not set | 372 | # CONFIG_DECNET is not set |
| 348 | # CONFIG_LLC2 is not set | 373 | # CONFIG_LLC2 is not set |
| @@ -353,6 +378,7 @@ CONFIG_NETFILTER=y | |||
| 353 | # CONFIG_ECONET is not set | 378 | # CONFIG_ECONET is not set |
| 354 | # CONFIG_WAN_ROUTER is not set | 379 | # CONFIG_WAN_ROUTER is not set |
| 355 | # CONFIG_NET_SCHED is not set | 380 | # CONFIG_NET_SCHED is not set |
| 381 | # CONFIG_DCB is not set | ||
| 356 | 382 | ||
| 357 | # | 383 | # |
| 358 | # Network testing | 384 | # Network testing |
| @@ -390,20 +416,17 @@ CONFIG_IRTTY_SIR=m | |||
| 390 | # Dongle support | 416 | # Dongle support |
| 391 | # | 417 | # |
| 392 | # CONFIG_DONGLE is not set | 418 | # CONFIG_DONGLE is not set |
| 393 | 419 | # CONFIG_KINGSUN_DONGLE is not set | |
| 394 | # | 420 | # CONFIG_KSDAZZLE_DONGLE is not set |
| 395 | # Old SIR device drivers | 421 | # CONFIG_KS959_DONGLE is not set |
| 396 | # | ||
| 397 | # CONFIG_IRPORT_SIR is not set | ||
| 398 | |||
| 399 | # | ||
| 400 | # Old Serial dongle support | ||
| 401 | # | ||
| 402 | 422 | ||
| 403 | # | 423 | # |
| 404 | # FIR device drivers | 424 | # FIR device drivers |
| 405 | # | 425 | # |
| 426 | # CONFIG_USB_IRDA is not set | ||
| 427 | # CONFIG_SIGMATEL_FIR is not set | ||
| 406 | CONFIG_PXA_FICP=m | 428 | CONFIG_PXA_FICP=m |
| 429 | # CONFIG_MCS_FIR is not set | ||
| 407 | CONFIG_BT=m | 430 | CONFIG_BT=m |
| 408 | CONFIG_BT_L2CAP=m | 431 | CONFIG_BT_L2CAP=m |
| 409 | CONFIG_BT_SCO=m | 432 | CONFIG_BT_SCO=m |
| @@ -417,17 +440,17 @@ CONFIG_BT_HIDP=m | |||
| 417 | # | 440 | # |
| 418 | # Bluetooth device drivers | 441 | # Bluetooth device drivers |
| 419 | # | 442 | # |
| 443 | CONFIG_BT_HCIBTUSB=m | ||
| 444 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 420 | # CONFIG_BT_HCIUART is not set | 445 | # CONFIG_BT_HCIUART is not set |
| 446 | # CONFIG_BT_HCIBCM203X is not set | ||
| 447 | # CONFIG_BT_HCIBPA10X is not set | ||
| 448 | # CONFIG_BT_HCIBFUSB is not set | ||
| 421 | # CONFIG_BT_HCIVHCI is not set | 449 | # CONFIG_BT_HCIVHCI is not set |
| 422 | # CONFIG_AF_RXRPC is not set | 450 | # CONFIG_AF_RXRPC is not set |
| 423 | 451 | # CONFIG_PHONET is not set | |
| 424 | # | 452 | # CONFIG_WIRELESS is not set |
| 425 | # Wireless | 453 | # CONFIG_WIMAX is not set |
| 426 | # | ||
| 427 | # CONFIG_CFG80211 is not set | ||
| 428 | # CONFIG_WIRELESS_EXT is not set | ||
| 429 | # CONFIG_MAC80211 is not set | ||
| 430 | # CONFIG_IEEE80211 is not set | ||
| 431 | # CONFIG_RFKILL is not set | 454 | # CONFIG_RFKILL is not set |
| 432 | # CONFIG_NET_9P is not set | 455 | # CONFIG_NET_9P is not set |
| 433 | 456 | ||
| @@ -442,25 +465,28 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 442 | CONFIG_STANDALONE=y | 465 | CONFIG_STANDALONE=y |
| 443 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 466 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 444 | CONFIG_FW_LOADER=y | 467 | CONFIG_FW_LOADER=y |
| 468 | # CONFIG_FIRMWARE_IN_KERNEL is not set | ||
| 469 | CONFIG_EXTRA_FIRMWARE="" | ||
| 445 | # CONFIG_DEBUG_DRIVER is not set | 470 | # CONFIG_DEBUG_DRIVER is not set |
| 446 | # CONFIG_DEBUG_DEVRES is not set | 471 | # CONFIG_DEBUG_DEVRES is not set |
| 447 | # CONFIG_SYS_HYPERVISOR is not set | 472 | # CONFIG_SYS_HYPERVISOR is not set |
| 448 | # CONFIG_CONNECTOR is not set | 473 | # CONFIG_CONNECTOR is not set |
| 449 | CONFIG_MTD=y | 474 | CONFIG_MTD=y |
| 450 | CONFIG_MTD_DEBUG=y | 475 | # CONFIG_MTD_DEBUG is not set |
| 451 | CONFIG_MTD_DEBUG_VERBOSE=0 | ||
| 452 | # CONFIG_MTD_CONCAT is not set | 476 | # CONFIG_MTD_CONCAT is not set |
| 453 | CONFIG_MTD_PARTITIONS=y | 477 | CONFIG_MTD_PARTITIONS=y |
| 478 | # CONFIG_MTD_TESTS is not set | ||
| 454 | # CONFIG_MTD_REDBOOT_PARTS is not set | 479 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 455 | CONFIG_MTD_CMDLINE_PARTS=y | 480 | CONFIG_MTD_CMDLINE_PARTS=y |
| 456 | # CONFIG_MTD_AFS_PARTS is not set | 481 | # CONFIG_MTD_AFS_PARTS is not set |
| 482 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 457 | 483 | ||
| 458 | # | 484 | # |
| 459 | # User Modules And Translation Layers | 485 | # User Modules And Translation Layers |
| 460 | # | 486 | # |
| 461 | CONFIG_MTD_CHAR=m | 487 | CONFIG_MTD_CHAR=y |
| 462 | CONFIG_MTD_BLKDEVS=m | 488 | CONFIG_MTD_BLKDEVS=y |
| 463 | CONFIG_MTD_BLOCK=m | 489 | CONFIG_MTD_BLOCK=y |
| 464 | # CONFIG_FTL is not set | 490 | # CONFIG_FTL is not set |
| 465 | # CONFIG_NFTL is not set | 491 | # CONFIG_NFTL is not set |
| 466 | # CONFIG_INFTL is not set | 492 | # CONFIG_INFTL is not set |
| @@ -473,6 +499,7 @@ CONFIG_MTD_BLOCK=m | |||
| 473 | # | 499 | # |
| 474 | CONFIG_MTD_CFI=y | 500 | CONFIG_MTD_CFI=y |
| 475 | # CONFIG_MTD_JEDECPROBE is not set | 501 | # CONFIG_MTD_JEDECPROBE is not set |
| 502 | CONFIG_MTD_GEN_PROBE=y | ||
| 476 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | 503 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set |
| 477 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | 504 | CONFIG_MTD_MAP_BANK_WIDTH_1=y |
| 478 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | 505 | CONFIG_MTD_MAP_BANK_WIDTH_2=y |
| @@ -487,6 +514,7 @@ CONFIG_MTD_CFI_I2=y | |||
| 487 | CONFIG_MTD_CFI_INTELEXT=y | 514 | CONFIG_MTD_CFI_INTELEXT=y |
| 488 | # CONFIG_MTD_CFI_AMDSTD is not set | 515 | # CONFIG_MTD_CFI_AMDSTD is not set |
| 489 | # CONFIG_MTD_CFI_STAA is not set | 516 | # CONFIG_MTD_CFI_STAA is not set |
| 517 | CONFIG_MTD_CFI_UTIL=y | ||
| 490 | # CONFIG_MTD_RAM is not set | 518 | # CONFIG_MTD_RAM is not set |
| 491 | # CONFIG_MTD_ROM is not set | 519 | # CONFIG_MTD_ROM is not set |
| 492 | # CONFIG_MTD_ABSENT is not set | 520 | # CONFIG_MTD_ABSENT is not set |
| @@ -497,9 +525,7 @@ CONFIG_MTD_CFI_INTELEXT=y | |||
| 497 | # | 525 | # |
| 498 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 526 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 499 | CONFIG_MTD_PHYSMAP=y | 527 | CONFIG_MTD_PHYSMAP=y |
| 500 | CONFIG_MTD_PHYSMAP_START=0x00000000 | 528 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 501 | CONFIG_MTD_PHYSMAP_LEN=0x04000000 | ||
| 502 | CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | ||
| 503 | # CONFIG_MTD_PXA2XX is not set | 529 | # CONFIG_MTD_PXA2XX is not set |
| 504 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 530 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 505 | # CONFIG_MTD_SHARP_SL is not set | 531 | # CONFIG_MTD_SHARP_SL is not set |
| @@ -523,6 +549,12 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | |||
| 523 | # CONFIG_MTD_ONENAND is not set | 549 | # CONFIG_MTD_ONENAND is not set |
| 524 | 550 | ||
| 525 | # | 551 | # |
| 552 | # LPDDR flash memory drivers | ||
| 553 | # | ||
| 554 | # CONFIG_MTD_LPDDR is not set | ||
| 555 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 556 | |||
| 557 | # | ||
| 526 | # UBI - Unsorted block images | 558 | # UBI - Unsorted block images |
| 527 | # | 559 | # |
| 528 | # CONFIG_MTD_UBI is not set | 560 | # CONFIG_MTD_UBI is not set |
| @@ -531,10 +563,12 @@ CONFIG_BLK_DEV=y | |||
| 531 | # CONFIG_BLK_DEV_COW_COMMON is not set | 563 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 532 | # CONFIG_BLK_DEV_LOOP is not set | 564 | # CONFIG_BLK_DEV_LOOP is not set |
| 533 | # CONFIG_BLK_DEV_NBD is not set | 565 | # CONFIG_BLK_DEV_NBD is not set |
| 566 | # CONFIG_BLK_DEV_UB is not set | ||
| 534 | # CONFIG_BLK_DEV_RAM is not set | 567 | # CONFIG_BLK_DEV_RAM is not set |
| 535 | # CONFIG_CDROM_PKTCDVD is not set | 568 | # CONFIG_CDROM_PKTCDVD is not set |
| 536 | # CONFIG_ATA_OVER_ETH is not set | 569 | # CONFIG_ATA_OVER_ETH is not set |
| 537 | # CONFIG_MISC_DEVICES is not set | 570 | # CONFIG_MISC_DEVICES is not set |
| 571 | CONFIG_HAVE_IDE=y | ||
| 538 | # CONFIG_IDE is not set | 572 | # CONFIG_IDE is not set |
| 539 | 573 | ||
| 540 | # | 574 | # |
| @@ -547,7 +581,6 @@ CONFIG_BLK_DEV=y | |||
| 547 | # CONFIG_ATA is not set | 581 | # CONFIG_ATA is not set |
| 548 | # CONFIG_MD is not set | 582 | # CONFIG_MD is not set |
| 549 | CONFIG_NETDEVICES=y | 583 | CONFIG_NETDEVICES=y |
| 550 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 551 | # CONFIG_DUMMY is not set | 584 | # CONFIG_DUMMY is not set |
| 552 | # CONFIG_BONDING is not set | 585 | # CONFIG_BONDING is not set |
| 553 | # CONFIG_MACVLAN is not set | 586 | # CONFIG_MACVLAN is not set |
| @@ -563,6 +596,20 @@ CONFIG_NETDEVICES=y | |||
| 563 | # | 596 | # |
| 564 | # CONFIG_WLAN_PRE80211 is not set | 597 | # CONFIG_WLAN_PRE80211 is not set |
| 565 | # CONFIG_WLAN_80211 is not set | 598 | # CONFIG_WLAN_80211 is not set |
| 599 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 600 | |||
| 601 | # | ||
| 602 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 603 | # | ||
| 604 | |||
| 605 | # | ||
| 606 | # USB Network Adapters | ||
| 607 | # | ||
| 608 | # CONFIG_USB_CATC is not set | ||
| 609 | # CONFIG_USB_KAWETH is not set | ||
| 610 | # CONFIG_USB_PEGASUS is not set | ||
| 611 | # CONFIG_USB_RTL8150 is not set | ||
| 612 | # CONFIG_USB_USBNET is not set | ||
| 566 | # CONFIG_WAN is not set | 613 | # CONFIG_WAN is not set |
| 567 | CONFIG_PPP=m | 614 | CONFIG_PPP=m |
| 568 | # CONFIG_PPP_MULTILINK is not set | 615 | # CONFIG_PPP_MULTILINK is not set |
| @@ -612,7 +659,26 @@ CONFIG_KEYBOARD_GPIO=y | |||
| 612 | # CONFIG_INPUT_JOYSTICK is not set | 659 | # CONFIG_INPUT_JOYSTICK is not set |
| 613 | # CONFIG_INPUT_TABLET is not set | 660 | # CONFIG_INPUT_TABLET is not set |
| 614 | CONFIG_INPUT_TOUCHSCREEN=y | 661 | CONFIG_INPUT_TOUCHSCREEN=y |
| 662 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 663 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 664 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 665 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 666 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 667 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 668 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 669 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 670 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 671 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 672 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 673 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 674 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 615 | CONFIG_INPUT_MISC=y | 675 | CONFIG_INPUT_MISC=y |
| 676 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 677 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 678 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 679 | # CONFIG_INPUT_POWERMATE is not set | ||
| 680 | # CONFIG_INPUT_YEALINK is not set | ||
| 681 | # CONFIG_INPUT_CM109 is not set | ||
| 616 | CONFIG_INPUT_UINPUT=m | 682 | CONFIG_INPUT_UINPUT=m |
| 617 | 683 | ||
| 618 | # | 684 | # |
| @@ -625,9 +691,11 @@ CONFIG_INPUT_UINPUT=m | |||
| 625 | # Character devices | 691 | # Character devices |
| 626 | # | 692 | # |
| 627 | CONFIG_VT=y | 693 | CONFIG_VT=y |
| 694 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 628 | CONFIG_VT_CONSOLE=y | 695 | CONFIG_VT_CONSOLE=y |
| 629 | CONFIG_HW_CONSOLE=y | 696 | CONFIG_HW_CONSOLE=y |
| 630 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 697 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 698 | # CONFIG_DEVKMEM is not set | ||
| 631 | # CONFIG_SERIAL_NONSTANDARD is not set | 699 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 632 | 700 | ||
| 633 | # | 701 | # |
| @@ -642,6 +710,7 @@ CONFIG_SERIAL_PXA=y | |||
| 642 | # CONFIG_SERIAL_PXA_CONSOLE is not set | 710 | # CONFIG_SERIAL_PXA_CONSOLE is not set |
| 643 | CONFIG_SERIAL_CORE=y | 711 | CONFIG_SERIAL_CORE=y |
| 644 | CONFIG_UNIX98_PTYS=y | 712 | CONFIG_UNIX98_PTYS=y |
| 713 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 645 | # CONFIG_LEGACY_PTYS is not set | 714 | # CONFIG_LEGACY_PTYS is not set |
| 646 | # CONFIG_IPMI_HANDLER is not set | 715 | # CONFIG_IPMI_HANDLER is not set |
| 647 | # CONFIG_HW_RANDOM is not set | 716 | # CONFIG_HW_RANDOM is not set |
| @@ -649,37 +718,45 @@ CONFIG_UNIX98_PTYS=y | |||
| 649 | # CONFIG_R3964 is not set | 718 | # CONFIG_R3964 is not set |
| 650 | # CONFIG_RAW_DRIVER is not set | 719 | # CONFIG_RAW_DRIVER is not set |
| 651 | # CONFIG_TCG_TPM is not set | 720 | # CONFIG_TCG_TPM is not set |
| 652 | CONFIG_I2C=m | 721 | CONFIG_I2C=y |
| 653 | CONFIG_I2C_BOARDINFO=y | 722 | CONFIG_I2C_BOARDINFO=y |
| 654 | CONFIG_I2C_CHARDEV=m | 723 | CONFIG_I2C_CHARDEV=m |
| 724 | CONFIG_I2C_HELPER_AUTO=y | ||
| 655 | 725 | ||
| 656 | # | 726 | # |
| 657 | # I2C Algorithms | 727 | # I2C Hardware Bus support |
| 658 | # | 728 | # |
| 659 | # CONFIG_I2C_ALGOBIT is not set | ||
| 660 | # CONFIG_I2C_ALGOPCF is not set | ||
| 661 | # CONFIG_I2C_ALGOPCA is not set | ||
| 662 | 729 | ||
| 663 | # | 730 | # |
| 664 | # I2C Hardware Bus support | 731 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 665 | # | 732 | # |
| 666 | # CONFIG_I2C_GPIO is not set | 733 | # CONFIG_I2C_GPIO is not set |
| 667 | CONFIG_I2C_PXA=m | ||
| 668 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 669 | # CONFIG_I2C_OCORES is not set | 734 | # CONFIG_I2C_OCORES is not set |
| 670 | # CONFIG_I2C_PARPORT_LIGHT is not set | 735 | CONFIG_I2C_PXA=y |
| 736 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 671 | # CONFIG_I2C_SIMTEC is not set | 737 | # CONFIG_I2C_SIMTEC is not set |
| 738 | |||
| 739 | # | ||
| 740 | # External I2C/SMBus adapter drivers | ||
| 741 | # | ||
| 742 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 672 | # CONFIG_I2C_TAOS_EVM is not set | 743 | # CONFIG_I2C_TAOS_EVM is not set |
| 744 | # CONFIG_I2C_TINY_USB is not set | ||
| 745 | |||
| 746 | # | ||
| 747 | # Other I2C/SMBus bus drivers | ||
| 748 | # | ||
| 749 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 673 | # CONFIG_I2C_STUB is not set | 750 | # CONFIG_I2C_STUB is not set |
| 674 | 751 | ||
| 675 | # | 752 | # |
| 676 | # Miscellaneous I2C Chip support | 753 | # Miscellaneous I2C Chip support |
| 677 | # | 754 | # |
| 678 | # CONFIG_SENSORS_DS1337 is not set | ||
| 679 | # CONFIG_SENSORS_DS1374 is not set | ||
| 680 | # CONFIG_DS1682 is not set | 755 | # CONFIG_DS1682 is not set |
| 756 | # CONFIG_AT24 is not set | ||
| 681 | # CONFIG_EEPROM_LEGACY is not set | 757 | # CONFIG_EEPROM_LEGACY is not set |
| 682 | # CONFIG_SENSORS_PCF8574 is not set | 758 | # CONFIG_SENSORS_PCF8574 is not set |
| 759 | # CONFIG_PCF8575 is not set | ||
| 683 | # CONFIG_SENSORS_PCA9539 is not set | 760 | # CONFIG_SENSORS_PCA9539 is not set |
| 684 | # CONFIG_SENSORS_PCF8591 is not set | 761 | # CONFIG_SENSORS_PCF8591 is not set |
| 685 | # CONFIG_SENSORS_MAX6875 is not set | 762 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -688,19 +765,39 @@ CONFIG_I2C_PXA=m | |||
| 688 | # CONFIG_I2C_DEBUG_ALGO is not set | 765 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 689 | # CONFIG_I2C_DEBUG_BUS is not set | 766 | # CONFIG_I2C_DEBUG_BUS is not set |
| 690 | # CONFIG_I2C_DEBUG_CHIP is not set | 767 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 768 | # CONFIG_SPI is not set | ||
| 769 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 770 | CONFIG_GPIOLIB=y | ||
| 771 | # CONFIG_DEBUG_GPIO is not set | ||
| 772 | # CONFIG_GPIO_SYSFS is not set | ||
| 691 | 773 | ||
| 692 | # | 774 | # |
| 693 | # SPI support | 775 | # Memory mapped GPIO expanders: |
| 776 | # | ||
| 777 | |||
| 778 | # | ||
| 779 | # I2C GPIO expanders: | ||
| 780 | # | ||
| 781 | # CONFIG_GPIO_MAX732X is not set | ||
| 782 | # CONFIG_GPIO_PCA953X is not set | ||
| 783 | # CONFIG_GPIO_PCF857X is not set | ||
| 784 | |||
| 785 | # | ||
| 786 | # PCI GPIO expanders: | ||
| 787 | # | ||
| 788 | |||
| 789 | # | ||
| 790 | # SPI GPIO expanders: | ||
| 694 | # | 791 | # |
| 695 | # CONFIG_SPI is not set | ||
| 696 | # CONFIG_SPI_MASTER is not set | ||
| 697 | CONFIG_W1=y | 792 | CONFIG_W1=y |
| 698 | 793 | ||
| 699 | # | 794 | # |
| 700 | # 1-wire Bus Masters | 795 | # 1-wire Bus Masters |
| 701 | # | 796 | # |
| 797 | # CONFIG_W1_MASTER_DS2490 is not set | ||
| 702 | # CONFIG_W1_MASTER_DS2482 is not set | 798 | # CONFIG_W1_MASTER_DS2482 is not set |
| 703 | CONFIG_W1_MASTER_DS1WM=y | 799 | CONFIG_W1_MASTER_DS1WM=y |
| 800 | # CONFIG_W1_MASTER_GPIO is not set | ||
| 704 | 801 | ||
| 705 | # | 802 | # |
| 706 | # 1-wire Slaves | 803 | # 1-wire Slaves |
| @@ -709,32 +806,56 @@ CONFIG_W1_MASTER_DS1WM=y | |||
| 709 | # CONFIG_W1_SLAVE_SMEM is not set | 806 | # CONFIG_W1_SLAVE_SMEM is not set |
| 710 | # CONFIG_W1_SLAVE_DS2433 is not set | 807 | # CONFIG_W1_SLAVE_DS2433 is not set |
| 711 | CONFIG_W1_SLAVE_DS2760=y | 808 | CONFIG_W1_SLAVE_DS2760=y |
| 809 | # CONFIG_W1_SLAVE_BQ27000 is not set | ||
| 712 | CONFIG_POWER_SUPPLY=y | 810 | CONFIG_POWER_SUPPLY=y |
| 713 | # CONFIG_POWER_SUPPLY_DEBUG is not set | 811 | # CONFIG_POWER_SUPPLY_DEBUG is not set |
| 714 | CONFIG_PDA_POWER=y | 812 | CONFIG_PDA_POWER=y |
| 715 | # CONFIG_APM_POWER is not set | ||
| 716 | CONFIG_BATTERY_DS2760=y | 813 | CONFIG_BATTERY_DS2760=y |
| 814 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 717 | # CONFIG_HWMON is not set | 815 | # CONFIG_HWMON is not set |
| 816 | # CONFIG_THERMAL is not set | ||
| 817 | # CONFIG_THERMAL_HWMON is not set | ||
| 718 | # CONFIG_WATCHDOG is not set | 818 | # CONFIG_WATCHDOG is not set |
| 819 | CONFIG_SSB_POSSIBLE=y | ||
| 719 | 820 | ||
| 720 | # | 821 | # |
| 721 | # Sonics Silicon Backplane | 822 | # Sonics Silicon Backplane |
| 722 | # | 823 | # |
| 723 | CONFIG_SSB_POSSIBLE=y | ||
| 724 | # CONFIG_SSB is not set | 824 | # CONFIG_SSB is not set |
| 725 | 825 | ||
| 726 | # | 826 | # |
| 727 | # Multifunction device drivers | 827 | # Multifunction device drivers |
| 728 | # | 828 | # |
| 829 | # CONFIG_MFD_CORE is not set | ||
| 729 | # CONFIG_MFD_SM501 is not set | 830 | # CONFIG_MFD_SM501 is not set |
| 831 | # CONFIG_MFD_ASIC3 is not set | ||
| 730 | CONFIG_HTC_EGPIO=y | 832 | CONFIG_HTC_EGPIO=y |
| 731 | CONFIG_HTC_PASIC3=y | 833 | CONFIG_HTC_PASIC3=y |
| 834 | # CONFIG_TPS65010 is not set | ||
| 835 | # CONFIG_TWL4030_CORE is not set | ||
| 836 | # CONFIG_MFD_TMIO is not set | ||
| 837 | # CONFIG_MFD_T7L66XB is not set | ||
| 838 | # CONFIG_MFD_TC6387XB is not set | ||
| 839 | # CONFIG_MFD_TC6393XB is not set | ||
| 840 | # CONFIG_PMIC_DA903X is not set | ||
| 841 | # CONFIG_MFD_WM8400 is not set | ||
| 842 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 843 | # CONFIG_MFD_PCF50633 is not set | ||
| 732 | 844 | ||
| 733 | # | 845 | # |
| 734 | # Multimedia devices | 846 | # Multimedia devices |
| 735 | # | 847 | # |
| 848 | |||
| 849 | # | ||
| 850 | # Multimedia core support | ||
| 851 | # | ||
| 736 | # CONFIG_VIDEO_DEV is not set | 852 | # CONFIG_VIDEO_DEV is not set |
| 737 | # CONFIG_DVB_CORE is not set | 853 | # CONFIG_DVB_CORE is not set |
| 854 | # CONFIG_VIDEO_MEDIA is not set | ||
| 855 | |||
| 856 | # | ||
| 857 | # Multimedia drivers | ||
| 858 | # | ||
| 738 | # CONFIG_DAB is not set | 859 | # CONFIG_DAB is not set |
| 739 | 860 | ||
| 740 | # | 861 | # |
| @@ -745,6 +866,7 @@ CONFIG_HTC_PASIC3=y | |||
| 745 | CONFIG_FB=y | 866 | CONFIG_FB=y |
| 746 | # CONFIG_FIRMWARE_EDID is not set | 867 | # CONFIG_FIRMWARE_EDID is not set |
| 747 | # CONFIG_FB_DDC is not set | 868 | # CONFIG_FB_DDC is not set |
| 869 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 748 | CONFIG_FB_CFB_FILLRECT=y | 870 | CONFIG_FB_CFB_FILLRECT=y |
| 749 | CONFIG_FB_CFB_COPYAREA=y | 871 | CONFIG_FB_CFB_COPYAREA=y |
| 750 | CONFIG_FB_CFB_IMAGEBLIT=y | 872 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -752,8 +874,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 752 | # CONFIG_FB_SYS_FILLRECT is not set | 874 | # CONFIG_FB_SYS_FILLRECT is not set |
| 753 | # CONFIG_FB_SYS_COPYAREA is not set | 875 | # CONFIG_FB_SYS_COPYAREA is not set |
| 754 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 876 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 877 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 755 | # CONFIG_FB_SYS_FOPS is not set | 878 | # CONFIG_FB_SYS_FOPS is not set |
| 756 | CONFIG_FB_DEFERRED_IO=y | ||
| 757 | # CONFIG_FB_SVGALIB is not set | 879 | # CONFIG_FB_SVGALIB is not set |
| 758 | # CONFIG_FB_MACMODES is not set | 880 | # CONFIG_FB_MACMODES is not set |
| 759 | # CONFIG_FB_BACKLIGHT is not set | 881 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -765,13 +887,21 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 765 | # | 887 | # |
| 766 | # CONFIG_FB_S1D13XXX is not set | 888 | # CONFIG_FB_S1D13XXX is not set |
| 767 | CONFIG_FB_PXA=y | 889 | CONFIG_FB_PXA=y |
| 890 | CONFIG_FB_PXA_OVERLAY=y | ||
| 891 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 768 | # CONFIG_FB_PXA_PARAMETERS is not set | 892 | # CONFIG_FB_PXA_PARAMETERS is not set |
| 769 | # CONFIG_FB_MBX is not set | 893 | # CONFIG_FB_MBX is not set |
| 894 | # CONFIG_FB_W100 is not set | ||
| 770 | # CONFIG_FB_VIRTUAL is not set | 895 | # CONFIG_FB_VIRTUAL is not set |
| 896 | # CONFIG_FB_METRONOME is not set | ||
| 897 | # CONFIG_FB_MB862XX is not set | ||
| 771 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 898 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 772 | CONFIG_LCD_CLASS_DEVICE=y | 899 | CONFIG_LCD_CLASS_DEVICE=y |
| 900 | # CONFIG_LCD_ILI9320 is not set | ||
| 901 | # CONFIG_LCD_PLATFORM is not set | ||
| 773 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 902 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 774 | CONFIG_BACKLIGHT_CORGI=y | 903 | # CONFIG_BACKLIGHT_GENERIC is not set |
| 904 | CONFIG_BACKLIGHT_PWM=y | ||
| 775 | 905 | ||
| 776 | # | 906 | # |
| 777 | # Display device support | 907 | # Display device support |
| @@ -802,15 +932,8 @@ CONFIG_FONT_MINI_4x6=y | |||
| 802 | # CONFIG_FONT_SUN12x22 is not set | 932 | # CONFIG_FONT_SUN12x22 is not set |
| 803 | # CONFIG_FONT_10x18 is not set | 933 | # CONFIG_FONT_10x18 is not set |
| 804 | # CONFIG_LOGO is not set | 934 | # CONFIG_LOGO is not set |
| 805 | |||
| 806 | # | ||
| 807 | # Sound | ||
| 808 | # | ||
| 809 | CONFIG_SOUND=y | 935 | CONFIG_SOUND=y |
| 810 | 936 | CONFIG_SOUND_OSS_CORE=y | |
| 811 | # | ||
| 812 | # Advanced Linux Sound Architecture | ||
| 813 | # | ||
| 814 | CONFIG_SND=m | 937 | CONFIG_SND=m |
| 815 | CONFIG_SND_TIMER=m | 938 | CONFIG_SND_TIMER=m |
| 816 | CONFIG_SND_PCM=m | 939 | CONFIG_SND_PCM=m |
| @@ -824,53 +947,185 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 824 | CONFIG_SND_VERBOSE_PROCFS=y | 947 | CONFIG_SND_VERBOSE_PROCFS=y |
| 825 | # CONFIG_SND_VERBOSE_PRINTK is not set | 948 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 826 | # CONFIG_SND_DEBUG is not set | 949 | # CONFIG_SND_DEBUG is not set |
| 827 | 950 | CONFIG_SND_DRIVERS=y | |
| 828 | # | ||
| 829 | # Generic devices | ||
| 830 | # | ||
| 831 | # CONFIG_SND_DUMMY is not set | 951 | # CONFIG_SND_DUMMY is not set |
| 832 | # CONFIG_SND_MTPAV is not set | 952 | # CONFIG_SND_MTPAV is not set |
| 833 | # CONFIG_SND_SERIAL_U16550 is not set | 953 | # CONFIG_SND_SERIAL_U16550 is not set |
| 834 | # CONFIG_SND_MPU401 is not set | 954 | # CONFIG_SND_MPU401 is not set |
| 835 | 955 | # CONFIG_SND_ARM is not set | |
| 836 | # | 956 | CONFIG_SND_PXA2XX_LIB=m |
| 837 | # ALSA ARM devices | 957 | # CONFIG_SND_USB is not set |
| 838 | # | ||
| 839 | # CONFIG_SND_PXA2XX_AC97 is not set | ||
| 840 | |||
| 841 | # | ||
| 842 | # System on Chip audio support | ||
| 843 | # | ||
| 844 | CONFIG_SND_SOC=m | 958 | CONFIG_SND_SOC=m |
| 845 | CONFIG_SND_PXA2XX_SOC=m | 959 | CONFIG_SND_PXA2XX_SOC=m |
| 846 | 960 | CONFIG_SND_SOC_I2C_AND_SPI=m | |
| 847 | # | 961 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 848 | # SoC Audio support for SuperH | ||
| 849 | # | ||
| 850 | |||
| 851 | # | ||
| 852 | # Open Sound System | ||
| 853 | # | ||
| 854 | # CONFIG_SOUND_PRIME is not set | 962 | # CONFIG_SOUND_PRIME is not set |
| 855 | # CONFIG_HID_SUPPORT is not set | 963 | # CONFIG_HID_SUPPORT is not set |
| 856 | CONFIG_HID=m | 964 | CONFIG_HID=m |
| 857 | # CONFIG_USB_SUPPORT is not set | 965 | CONFIG_USB_SUPPORT=y |
| 966 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 967 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 968 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 969 | CONFIG_USB=y | ||
| 970 | # CONFIG_USB_DEBUG is not set | ||
| 971 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 972 | |||
| 973 | # | ||
| 974 | # Miscellaneous USB options | ||
| 975 | # | ||
| 976 | # CONFIG_USB_DEVICEFS is not set | ||
| 977 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 978 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 979 | # CONFIG_USB_SUSPEND is not set | ||
| 980 | # CONFIG_USB_OTG is not set | ||
| 981 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 982 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 983 | CONFIG_USB_MON=m | ||
| 984 | # CONFIG_USB_WUSB is not set | ||
| 985 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 986 | |||
| 987 | # | ||
| 988 | # USB Host Controller Drivers | ||
| 989 | # | ||
| 990 | # CONFIG_USB_C67X00_HCD is not set | ||
| 991 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 992 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 993 | CONFIG_USB_OHCI_HCD=y | ||
| 994 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 995 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 996 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 997 | # CONFIG_USB_SL811_HCD is not set | ||
| 998 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 999 | # CONFIG_USB_HWA_HCD is not set | ||
| 1000 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1001 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1002 | |||
| 1003 | # | ||
| 1004 | # USB Device Class drivers | ||
| 1005 | # | ||
| 1006 | # CONFIG_USB_ACM is not set | ||
| 1007 | # CONFIG_USB_PRINTER is not set | ||
| 1008 | # CONFIG_USB_WDM is not set | ||
| 1009 | # CONFIG_USB_TMC is not set | ||
| 1010 | |||
| 1011 | # | ||
| 1012 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1013 | # | ||
| 1014 | |||
| 1015 | # | ||
| 1016 | # see USB_STORAGE Help for more information | ||
| 1017 | # | ||
| 1018 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1019 | |||
| 1020 | # | ||
| 1021 | # USB Imaging devices | ||
| 1022 | # | ||
| 1023 | # CONFIG_USB_MDC800 is not set | ||
| 1024 | |||
| 1025 | # | ||
| 1026 | # USB port drivers | ||
| 1027 | # | ||
| 1028 | # CONFIG_USB_SERIAL is not set | ||
| 1029 | |||
| 1030 | # | ||
| 1031 | # USB Miscellaneous drivers | ||
| 1032 | # | ||
| 1033 | # CONFIG_USB_EMI62 is not set | ||
| 1034 | # CONFIG_USB_EMI26 is not set | ||
| 1035 | # CONFIG_USB_ADUTUX is not set | ||
| 1036 | # CONFIG_USB_SEVSEG is not set | ||
| 1037 | # CONFIG_USB_RIO500 is not set | ||
| 1038 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1039 | # CONFIG_USB_LCD is not set | ||
| 1040 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1041 | # CONFIG_USB_LED is not set | ||
| 1042 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1043 | # CONFIG_USB_CYTHERM is not set | ||
| 1044 | # CONFIG_USB_PHIDGET is not set | ||
| 1045 | # CONFIG_USB_IDMOUSE is not set | ||
| 1046 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1047 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1048 | # CONFIG_USB_LD is not set | ||
| 1049 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1050 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1051 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1052 | # CONFIG_USB_VST is not set | ||
| 1053 | CONFIG_USB_GADGET=y | ||
| 1054 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 1055 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 1056 | CONFIG_USB_GADGET_VBUS_DRAW=500 | ||
| 1057 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1058 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1059 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1060 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1061 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1062 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1063 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1064 | CONFIG_USB_GADGET_PXA27X=y | ||
| 1065 | CONFIG_USB_PXA27X=y | ||
| 1066 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1067 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1068 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1069 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1070 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1071 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1072 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1073 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1074 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1075 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 1076 | # CONFIG_USB_ZERO is not set | ||
| 1077 | CONFIG_USB_ETH=m | ||
| 1078 | # CONFIG_USB_ETH_RNDIS is not set | ||
| 1079 | CONFIG_USB_GADGETFS=m | ||
| 1080 | CONFIG_USB_FILE_STORAGE=m | ||
| 1081 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
| 1082 | CONFIG_USB_G_SERIAL=m | ||
| 1083 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1084 | # CONFIG_USB_G_PRINTER is not set | ||
| 1085 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 1086 | |||
| 1087 | # | ||
| 1088 | # OTG and related infrastructure | ||
| 1089 | # | ||
| 1090 | CONFIG_USB_OTG_UTILS=y | ||
| 1091 | CONFIG_USB_GPIO_VBUS=y | ||
| 858 | CONFIG_MMC=y | 1092 | CONFIG_MMC=y |
| 859 | # CONFIG_MMC_DEBUG is not set | 1093 | # CONFIG_MMC_DEBUG is not set |
| 860 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1094 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 861 | 1095 | ||
| 862 | # | 1096 | # |
| 863 | # MMC/SD Card Drivers | 1097 | # MMC/SD/SDIO Card Drivers |
| 864 | # | 1098 | # |
| 865 | CONFIG_MMC_BLOCK=y | 1099 | CONFIG_MMC_BLOCK=y |
| 866 | CONFIG_MMC_BLOCK_BOUNCE=y | 1100 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 867 | CONFIG_SDIO_UART=m | 1101 | CONFIG_SDIO_UART=m |
| 1102 | # CONFIG_MMC_TEST is not set | ||
| 868 | 1103 | ||
| 869 | # | 1104 | # |
| 870 | # MMC/SD Host Controller Drivers | 1105 | # MMC/SD/SDIO Host Controller Drivers |
| 871 | # | 1106 | # |
| 872 | CONFIG_MMC_PXA=y | 1107 | CONFIG_MMC_PXA=y |
| 1108 | # CONFIG_MMC_SDHCI is not set | ||
| 1109 | # CONFIG_MEMSTICK is not set | ||
| 1110 | # CONFIG_ACCESSIBILITY is not set | ||
| 873 | CONFIG_NEW_LEDS=y | 1111 | CONFIG_NEW_LEDS=y |
| 1112 | CONFIG_LEDS_CLASS=y | ||
| 1113 | |||
| 1114 | # | ||
| 1115 | # LED drivers | ||
| 1116 | # | ||
| 1117 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1118 | CONFIG_LEDS_GPIO=y | ||
| 1119 | # CONFIG_LEDS_PCA955X is not set | ||
| 1120 | |||
| 1121 | # | ||
| 1122 | # LED Triggers | ||
| 1123 | # | ||
| 1124 | CONFIG_LEDS_TRIGGERS=y | ||
| 1125 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1126 | # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set | ||
| 1127 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | ||
| 1128 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 874 | CONFIG_RTC_LIB=y | 1129 | CONFIG_RTC_LIB=y |
| 875 | CONFIG_RTC_CLASS=y | 1130 | CONFIG_RTC_CLASS=y |
| 876 | CONFIG_RTC_HCTOSYS=y | 1131 | CONFIG_RTC_HCTOSYS=y |
| @@ -899,6 +1154,9 @@ CONFIG_RTC_INTF_DEV=y | |||
| 899 | # CONFIG_RTC_DRV_PCF8563 is not set | 1154 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 900 | # CONFIG_RTC_DRV_PCF8583 is not set | 1155 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 901 | # CONFIG_RTC_DRV_M41T80 is not set | 1156 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1157 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1158 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1159 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 902 | 1160 | ||
| 903 | # | 1161 | # |
| 904 | # SPI RTC drivers | 1162 | # SPI RTC drivers |
| @@ -908,17 +1166,26 @@ CONFIG_RTC_INTF_DEV=y | |||
| 908 | # Platform RTC drivers | 1166 | # Platform RTC drivers |
| 909 | # | 1167 | # |
| 910 | # CONFIG_RTC_DRV_CMOS is not set | 1168 | # CONFIG_RTC_DRV_CMOS is not set |
| 1169 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1170 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 911 | # CONFIG_RTC_DRV_DS1553 is not set | 1171 | # CONFIG_RTC_DRV_DS1553 is not set |
| 912 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 913 | # CONFIG_RTC_DRV_DS1742 is not set | 1172 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1173 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 914 | # CONFIG_RTC_DRV_M48T86 is not set | 1174 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1175 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 915 | # CONFIG_RTC_DRV_M48T59 is not set | 1176 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1177 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 916 | # CONFIG_RTC_DRV_V3020 is not set | 1178 | # CONFIG_RTC_DRV_V3020 is not set |
| 917 | 1179 | ||
| 918 | # | 1180 | # |
| 919 | # on-CPU RTC drivers | 1181 | # on-CPU RTC drivers |
| 920 | # | 1182 | # |
| 921 | CONFIG_RTC_DRV_SA1100=y | 1183 | CONFIG_RTC_DRV_SA1100=y |
| 1184 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1185 | # CONFIG_DMADEVICES is not set | ||
| 1186 | # CONFIG_REGULATOR is not set | ||
| 1187 | # CONFIG_UIO is not set | ||
| 1188 | # CONFIG_STAGING is not set | ||
| 922 | 1189 | ||
| 923 | # | 1190 | # |
| 924 | # File systems | 1191 | # File systems |
| @@ -927,19 +1194,18 @@ CONFIG_EXT2_FS=y | |||
| 927 | # CONFIG_EXT2_FS_XATTR is not set | 1194 | # CONFIG_EXT2_FS_XATTR is not set |
| 928 | # CONFIG_EXT2_FS_XIP is not set | 1195 | # CONFIG_EXT2_FS_XIP is not set |
| 929 | # CONFIG_EXT3_FS is not set | 1196 | # CONFIG_EXT3_FS is not set |
| 930 | # CONFIG_EXT4DEV_FS is not set | 1197 | # CONFIG_EXT4_FS is not set |
| 931 | # CONFIG_REISERFS_FS is not set | 1198 | # CONFIG_REISERFS_FS is not set |
| 932 | # CONFIG_JFS_FS is not set | 1199 | # CONFIG_JFS_FS is not set |
| 933 | # CONFIG_FS_POSIX_ACL is not set | 1200 | # CONFIG_FS_POSIX_ACL is not set |
| 1201 | CONFIG_FILE_LOCKING=y | ||
| 934 | # CONFIG_XFS_FS is not set | 1202 | # CONFIG_XFS_FS is not set |
| 935 | # CONFIG_GFS2_FS is not set | ||
| 936 | # CONFIG_OCFS2_FS is not set | 1203 | # CONFIG_OCFS2_FS is not set |
| 937 | # CONFIG_MINIX_FS is not set | 1204 | # CONFIG_BTRFS_FS is not set |
| 938 | # CONFIG_ROMFS_FS is not set | 1205 | CONFIG_DNOTIFY=y |
| 939 | CONFIG_INOTIFY=y | 1206 | CONFIG_INOTIFY=y |
| 940 | CONFIG_INOTIFY_USER=y | 1207 | CONFIG_INOTIFY_USER=y |
| 941 | # CONFIG_QUOTA is not set | 1208 | # CONFIG_QUOTA is not set |
| 942 | CONFIG_DNOTIFY=y | ||
| 943 | # CONFIG_AUTOFS_FS is not set | 1209 | # CONFIG_AUTOFS_FS is not set |
| 944 | # CONFIG_AUTOFS4_FS is not set | 1210 | # CONFIG_AUTOFS4_FS is not set |
| 945 | # CONFIG_FUSE_FS is not set | 1211 | # CONFIG_FUSE_FS is not set |
| @@ -965,15 +1231,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 965 | # | 1231 | # |
| 966 | CONFIG_PROC_FS=y | 1232 | CONFIG_PROC_FS=y |
| 967 | CONFIG_PROC_SYSCTL=y | 1233 | CONFIG_PROC_SYSCTL=y |
| 1234 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 968 | CONFIG_SYSFS=y | 1235 | CONFIG_SYSFS=y |
| 969 | CONFIG_TMPFS=y | 1236 | CONFIG_TMPFS=y |
| 970 | # CONFIG_TMPFS_POSIX_ACL is not set | 1237 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 971 | # CONFIG_HUGETLB_PAGE is not set | 1238 | # CONFIG_HUGETLB_PAGE is not set |
| 972 | # CONFIG_CONFIGFS_FS is not set | 1239 | # CONFIG_CONFIGFS_FS is not set |
| 973 | 1240 | CONFIG_MISC_FILESYSTEMS=y | |
| 974 | # | ||
| 975 | # Miscellaneous filesystems | ||
| 976 | # | ||
| 977 | # CONFIG_ADFS_FS is not set | 1241 | # CONFIG_ADFS_FS is not set |
| 978 | # CONFIG_AFFS_FS is not set | 1242 | # CONFIG_AFFS_FS is not set |
| 979 | # CONFIG_HFS_FS is not set | 1243 | # CONFIG_HFS_FS is not set |
| @@ -997,9 +1261,13 @@ CONFIG_JFFS2_CMODE_PRIORITY=y | |||
| 997 | # CONFIG_JFFS2_CMODE_SIZE is not set | 1261 | # CONFIG_JFFS2_CMODE_SIZE is not set |
| 998 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | 1262 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set |
| 999 | # CONFIG_CRAMFS is not set | 1263 | # CONFIG_CRAMFS is not set |
| 1264 | # CONFIG_SQUASHFS is not set | ||
| 1000 | # CONFIG_VXFS_FS is not set | 1265 | # CONFIG_VXFS_FS is not set |
| 1266 | # CONFIG_MINIX_FS is not set | ||
| 1267 | # CONFIG_OMFS_FS is not set | ||
| 1001 | # CONFIG_HPFS_FS is not set | 1268 | # CONFIG_HPFS_FS is not set |
| 1002 | # CONFIG_QNX4FS_FS is not set | 1269 | # CONFIG_QNX4FS_FS is not set |
| 1270 | # CONFIG_ROMFS_FS is not set | ||
| 1003 | # CONFIG_SYSV_FS is not set | 1271 | # CONFIG_SYSV_FS is not set |
| 1004 | # CONFIG_UFS_FS is not set | 1272 | # CONFIG_UFS_FS is not set |
| 1005 | CONFIG_NETWORK_FILESYSTEMS=y | 1273 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1007,14 +1275,13 @@ CONFIG_NFS_FS=y | |||
| 1007 | CONFIG_NFS_V3=y | 1275 | CONFIG_NFS_V3=y |
| 1008 | # CONFIG_NFS_V3_ACL is not set | 1276 | # CONFIG_NFS_V3_ACL is not set |
| 1009 | # CONFIG_NFS_V4 is not set | 1277 | # CONFIG_NFS_V4 is not set |
| 1010 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1011 | # CONFIG_NFSD is not set | ||
| 1012 | CONFIG_ROOT_NFS=y | 1278 | CONFIG_ROOT_NFS=y |
| 1279 | # CONFIG_NFSD is not set | ||
| 1013 | CONFIG_LOCKD=y | 1280 | CONFIG_LOCKD=y |
| 1014 | CONFIG_LOCKD_V4=y | 1281 | CONFIG_LOCKD_V4=y |
| 1015 | CONFIG_NFS_COMMON=y | 1282 | CONFIG_NFS_COMMON=y |
| 1016 | CONFIG_SUNRPC=y | 1283 | CONFIG_SUNRPC=y |
| 1017 | # CONFIG_SUNRPC_BIND34 is not set | 1284 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1018 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1285 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1019 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1286 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1020 | # CONFIG_SMB_FS is not set | 1287 | # CONFIG_SMB_FS is not set |
| @@ -1076,6 +1343,7 @@ CONFIG_NLS_UTF8=y | |||
| 1076 | CONFIG_PRINTK_TIME=y | 1343 | CONFIG_PRINTK_TIME=y |
| 1077 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1344 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1078 | CONFIG_ENABLE_MUST_CHECK=y | 1345 | CONFIG_ENABLE_MUST_CHECK=y |
| 1346 | CONFIG_FRAME_WARN=1024 | ||
| 1079 | # CONFIG_MAGIC_SYSRQ is not set | 1347 | # CONFIG_MAGIC_SYSRQ is not set |
| 1080 | # CONFIG_UNUSED_SYMBOLS is not set | 1348 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1081 | # CONFIG_DEBUG_FS is not set | 1349 | # CONFIG_DEBUG_FS is not set |
| @@ -1083,15 +1351,18 @@ CONFIG_ENABLE_MUST_CHECK=y | |||
| 1083 | CONFIG_DEBUG_KERNEL=y | 1351 | CONFIG_DEBUG_KERNEL=y |
| 1084 | # CONFIG_DEBUG_SHIRQ is not set | 1352 | # CONFIG_DEBUG_SHIRQ is not set |
| 1085 | CONFIG_DETECT_SOFTLOCKUP=y | 1353 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1354 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1355 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1086 | # CONFIG_SCHED_DEBUG is not set | 1356 | # CONFIG_SCHED_DEBUG is not set |
| 1087 | # CONFIG_SCHEDSTATS is not set | 1357 | # CONFIG_SCHEDSTATS is not set |
| 1088 | CONFIG_TIMER_STATS=y | 1358 | CONFIG_TIMER_STATS=y |
| 1359 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1089 | # CONFIG_DEBUG_SLAB is not set | 1360 | # CONFIG_DEBUG_SLAB is not set |
| 1090 | CONFIG_DEBUG_PREEMPT=y | 1361 | # CONFIG_DEBUG_PREEMPT is not set |
| 1091 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1362 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1092 | # CONFIG_RT_MUTEX_TESTER is not set | 1363 | # CONFIG_RT_MUTEX_TESTER is not set |
| 1093 | # CONFIG_DEBUG_SPINLOCK is not set | 1364 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1094 | CONFIG_DEBUG_MUTEXES=y | 1365 | # CONFIG_DEBUG_MUTEXES is not set |
| 1095 | # CONFIG_DEBUG_LOCK_ALLOC is not set | 1366 | # CONFIG_DEBUG_LOCK_ALLOC is not set |
| 1096 | # CONFIG_PROVE_LOCKING is not set | 1367 | # CONFIG_PROVE_LOCKING is not set |
| 1097 | # CONFIG_LOCK_STAT is not set | 1368 | # CONFIG_LOCK_STAT is not set |
| @@ -1100,17 +1371,41 @@ CONFIG_DEBUG_MUTEXES=y | |||
| 1100 | # CONFIG_DEBUG_KOBJECT is not set | 1371 | # CONFIG_DEBUG_KOBJECT is not set |
| 1101 | CONFIG_DEBUG_BUGVERBOSE=y | 1372 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1102 | # CONFIG_DEBUG_INFO is not set | 1373 | # CONFIG_DEBUG_INFO is not set |
| 1103 | CONFIG_DEBUG_VM=y | 1374 | # CONFIG_DEBUG_VM is not set |
| 1375 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1376 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1104 | # CONFIG_DEBUG_LIST is not set | 1377 | # CONFIG_DEBUG_LIST is not set |
| 1105 | # CONFIG_DEBUG_SG is not set | 1378 | # CONFIG_DEBUG_SG is not set |
| 1379 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1106 | CONFIG_FRAME_POINTER=y | 1380 | CONFIG_FRAME_POINTER=y |
| 1107 | CONFIG_FORCED_INLINING=y | ||
| 1108 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1381 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1109 | # CONFIG_RCU_TORTURE_TEST is not set | 1382 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1383 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1384 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1385 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1110 | # CONFIG_FAULT_INJECTION is not set | 1386 | # CONFIG_FAULT_INJECTION is not set |
| 1387 | # CONFIG_LATENCYTOP is not set | ||
| 1388 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1389 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1390 | |||
| 1391 | # | ||
| 1392 | # Tracers | ||
| 1393 | # | ||
| 1394 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1395 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1396 | # CONFIG_PREEMPT_TRACER is not set | ||
| 1397 | # CONFIG_SCHED_TRACER is not set | ||
| 1398 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1399 | # CONFIG_BOOT_TRACER is not set | ||
| 1400 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1401 | # CONFIG_STACK_TRACER is not set | ||
| 1402 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1111 | # CONFIG_SAMPLES is not set | 1403 | # CONFIG_SAMPLES is not set |
| 1404 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1405 | # CONFIG_KGDB is not set | ||
| 1112 | CONFIG_DEBUG_USER=y | 1406 | CONFIG_DEBUG_USER=y |
| 1113 | CONFIG_DEBUG_ERRORS=y | 1407 | CONFIG_DEBUG_ERRORS=y |
| 1408 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1114 | CONFIG_DEBUG_LL=y | 1409 | CONFIG_DEBUG_LL=y |
| 1115 | # CONFIG_DEBUG_ICEDCC is not set | 1410 | # CONFIG_DEBUG_ICEDCC is not set |
| 1116 | 1411 | ||
| @@ -1119,55 +1414,110 @@ CONFIG_DEBUG_LL=y | |||
| 1119 | # | 1414 | # |
| 1120 | # CONFIG_KEYS is not set | 1415 | # CONFIG_KEYS is not set |
| 1121 | # CONFIG_SECURITY is not set | 1416 | # CONFIG_SECURITY is not set |
| 1417 | # CONFIG_SECURITYFS is not set | ||
| 1122 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1418 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1123 | CONFIG_CRYPTO=y | 1419 | CONFIG_CRYPTO=y |
| 1420 | |||
| 1421 | # | ||
| 1422 | # Crypto core or helper | ||
| 1423 | # | ||
| 1424 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1124 | CONFIG_CRYPTO_ALGAPI=m | 1425 | CONFIG_CRYPTO_ALGAPI=m |
| 1426 | CONFIG_CRYPTO_ALGAPI2=m | ||
| 1427 | CONFIG_CRYPTO_AEAD2=m | ||
| 1125 | CONFIG_CRYPTO_BLKCIPHER=m | 1428 | CONFIG_CRYPTO_BLKCIPHER=m |
| 1429 | CONFIG_CRYPTO_BLKCIPHER2=m | ||
| 1430 | CONFIG_CRYPTO_HASH=m | ||
| 1431 | CONFIG_CRYPTO_HASH2=m | ||
| 1432 | CONFIG_CRYPTO_RNG2=m | ||
| 1126 | CONFIG_CRYPTO_MANAGER=m | 1433 | CONFIG_CRYPTO_MANAGER=m |
| 1434 | CONFIG_CRYPTO_MANAGER2=m | ||
| 1435 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1436 | # CONFIG_CRYPTO_NULL is not set | ||
| 1437 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1438 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1439 | # CONFIG_CRYPTO_TEST is not set | ||
| 1440 | |||
| 1441 | # | ||
| 1442 | # Authenticated Encryption with Associated Data | ||
| 1443 | # | ||
| 1444 | # CONFIG_CRYPTO_CCM is not set | ||
| 1445 | # CONFIG_CRYPTO_GCM is not set | ||
| 1446 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1447 | |||
| 1448 | # | ||
| 1449 | # Block modes | ||
| 1450 | # | ||
| 1451 | # CONFIG_CRYPTO_CBC is not set | ||
| 1452 | # CONFIG_CRYPTO_CTR is not set | ||
| 1453 | # CONFIG_CRYPTO_CTS is not set | ||
| 1454 | CONFIG_CRYPTO_ECB=m | ||
| 1455 | # CONFIG_CRYPTO_LRW is not set | ||
| 1456 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1457 | # CONFIG_CRYPTO_XTS is not set | ||
| 1458 | |||
| 1459 | # | ||
| 1460 | # Hash modes | ||
| 1461 | # | ||
| 1127 | # CONFIG_CRYPTO_HMAC is not set | 1462 | # CONFIG_CRYPTO_HMAC is not set |
| 1128 | # CONFIG_CRYPTO_XCBC is not set | 1463 | # CONFIG_CRYPTO_XCBC is not set |
| 1129 | # CONFIG_CRYPTO_NULL is not set | 1464 | |
| 1465 | # | ||
| 1466 | # Digest | ||
| 1467 | # | ||
| 1468 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1130 | # CONFIG_CRYPTO_MD4 is not set | 1469 | # CONFIG_CRYPTO_MD4 is not set |
| 1131 | # CONFIG_CRYPTO_MD5 is not set | 1470 | # CONFIG_CRYPTO_MD5 is not set |
| 1471 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1472 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1473 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1474 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1475 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1132 | CONFIG_CRYPTO_SHA1=m | 1476 | CONFIG_CRYPTO_SHA1=m |
| 1133 | # CONFIG_CRYPTO_SHA256 is not set | 1477 | # CONFIG_CRYPTO_SHA256 is not set |
| 1134 | # CONFIG_CRYPTO_SHA512 is not set | 1478 | # CONFIG_CRYPTO_SHA512 is not set |
| 1135 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1136 | # CONFIG_CRYPTO_TGR192 is not set | 1479 | # CONFIG_CRYPTO_TGR192 is not set |
| 1137 | # CONFIG_CRYPTO_GF128MUL is not set | 1480 | # CONFIG_CRYPTO_WP512 is not set |
| 1138 | CONFIG_CRYPTO_ECB=m | 1481 | |
| 1139 | # CONFIG_CRYPTO_CBC is not set | 1482 | # |
| 1140 | CONFIG_CRYPTO_PCBC=m | 1483 | # Ciphers |
| 1141 | # CONFIG_CRYPTO_LRW is not set | 1484 | # |
| 1142 | # CONFIG_CRYPTO_XTS is not set | ||
| 1143 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1144 | # CONFIG_CRYPTO_DES is not set | ||
| 1145 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1146 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1147 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1148 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1149 | # CONFIG_CRYPTO_AES is not set | 1485 | # CONFIG_CRYPTO_AES is not set |
| 1486 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1487 | CONFIG_CRYPTO_ARC4=m | ||
| 1488 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1489 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1150 | # CONFIG_CRYPTO_CAST5 is not set | 1490 | # CONFIG_CRYPTO_CAST5 is not set |
| 1151 | # CONFIG_CRYPTO_CAST6 is not set | 1491 | # CONFIG_CRYPTO_CAST6 is not set |
| 1152 | # CONFIG_CRYPTO_TEA is not set | 1492 | # CONFIG_CRYPTO_DES is not set |
| 1153 | CONFIG_CRYPTO_ARC4=m | 1493 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1154 | # CONFIG_CRYPTO_KHAZAD is not set | 1494 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1155 | # CONFIG_CRYPTO_ANUBIS is not set | 1495 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1156 | # CONFIG_CRYPTO_SEED is not set | 1496 | # CONFIG_CRYPTO_SEED is not set |
| 1497 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1498 | # CONFIG_CRYPTO_TEA is not set | ||
| 1499 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1500 | |||
| 1501 | # | ||
| 1502 | # Compression | ||
| 1503 | # | ||
| 1157 | # CONFIG_CRYPTO_DEFLATE is not set | 1504 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1158 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1505 | # CONFIG_CRYPTO_LZO is not set |
| 1159 | # CONFIG_CRYPTO_CRC32C is not set | 1506 | |
| 1160 | # CONFIG_CRYPTO_CAMELLIA is not set | 1507 | # |
| 1161 | # CONFIG_CRYPTO_TEST is not set | 1508 | # Random Number Generation |
| 1162 | # CONFIG_CRYPTO_AUTHENC is not set | 1509 | # |
| 1510 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1163 | # CONFIG_CRYPTO_HW is not set | 1511 | # CONFIG_CRYPTO_HW is not set |
| 1164 | 1512 | ||
| 1165 | # | 1513 | # |
| 1166 | # Library routines | 1514 | # Library routines |
| 1167 | # | 1515 | # |
| 1168 | CONFIG_BITREVERSE=y | 1516 | CONFIG_BITREVERSE=y |
| 1517 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1169 | CONFIG_CRC_CCITT=y | 1518 | CONFIG_CRC_CCITT=y |
| 1170 | # CONFIG_CRC16 is not set | 1519 | # CONFIG_CRC16 is not set |
| 1520 | # CONFIG_CRC_T10DIF is not set | ||
| 1171 | # CONFIG_CRC_ITU_T is not set | 1521 | # CONFIG_CRC_ITU_T is not set |
| 1172 | CONFIG_CRC32=y | 1522 | CONFIG_CRC32=y |
| 1173 | # CONFIG_CRC7 is not set | 1523 | # CONFIG_CRC7 is not set |
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 83c817f31bcc..b0698722e0cb 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig | |||
| @@ -165,6 +165,7 @@ CONFIG_ARCH_MV78XX0=y | |||
| 165 | # Marvell MV78xx0 Implementations | 165 | # Marvell MV78xx0 Implementations |
| 166 | # | 166 | # |
| 167 | CONFIG_MACH_DB78X00_BP=y | 167 | CONFIG_MACH_DB78X00_BP=y |
| 168 | CONFIG_MACH_RD78X00_MASA=y | ||
| 168 | 169 | ||
| 169 | # | 170 | # |
| 170 | # Boot options | 171 | # Boot options |
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig index d81ea219c934..36cd62edd05c 100644 --- a/arch/arm/configs/neponset_defconfig +++ b/arch/arm/configs/neponset_defconfig | |||
| @@ -91,7 +91,6 @@ CONFIG_ASSABET_NEPONSET=y | |||
| 91 | # CONFIG_SA1100_COLLIE is not set | 91 | # CONFIG_SA1100_COLLIE is not set |
| 92 | # CONFIG_SA1100_H3100 is not set | 92 | # CONFIG_SA1100_H3100 is not set |
| 93 | # CONFIG_SA1100_H3600 is not set | 93 | # CONFIG_SA1100_H3600 is not set |
| 94 | # CONFIG_SA1100_H3800 is not set | ||
| 95 | # CONFIG_SA1100_BADGE4 is not set | 94 | # CONFIG_SA1100_BADGE4 is not set |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| 97 | # CONFIG_SA1100_HACKKIT is not set | 96 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig new file mode 100644 index 000000000000..8fb918d9ba65 --- /dev/null +++ b/arch/arm/configs/omap_3430sdp_defconfig | |||
| @@ -0,0 +1,2061 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc8 | ||
| 4 | # Fri Mar 13 14:17:01 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_OPROFILE_ARMV7=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | |||
| 47 | # | ||
| 48 | # RCU Subsystem | ||
| 49 | # | ||
| 50 | CONFIG_CLASSIC_RCU=y | ||
| 51 | # CONFIG_TREE_RCU is not set | ||
| 52 | # CONFIG_PREEMPT_RCU is not set | ||
| 53 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 54 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 55 | CONFIG_IKCONFIG=y | ||
| 56 | CONFIG_IKCONFIG_PROC=y | ||
| 57 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 58 | CONFIG_GROUP_SCHED=y | ||
| 59 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 60 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 61 | CONFIG_USER_SCHED=y | ||
| 62 | # CONFIG_CGROUP_SCHED is not set | ||
| 63 | # CONFIG_CGROUPS is not set | ||
| 64 | CONFIG_SYSFS_DEPRECATED=y | ||
| 65 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 66 | # CONFIG_RELAY is not set | ||
| 67 | # CONFIG_NAMESPACES is not set | ||
| 68 | CONFIG_BLK_DEV_INITRD=y | ||
| 69 | CONFIG_INITRAMFS_SOURCE="" | ||
| 70 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 71 | CONFIG_SYSCTL=y | ||
| 72 | CONFIG_ANON_INODES=y | ||
| 73 | CONFIG_EMBEDDED=y | ||
| 74 | CONFIG_UID16=y | ||
| 75 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 76 | CONFIG_KALLSYMS=y | ||
| 77 | # CONFIG_KALLSYMS_ALL is not set | ||
| 78 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 79 | CONFIG_HOTPLUG=y | ||
| 80 | CONFIG_PRINTK=y | ||
| 81 | CONFIG_BUG=y | ||
| 82 | # CONFIG_ELF_CORE is not set | ||
| 83 | CONFIG_BASE_FULL=y | ||
| 84 | CONFIG_FUTEX=y | ||
| 85 | CONFIG_EPOLL=y | ||
| 86 | CONFIG_SIGNALFD=y | ||
| 87 | CONFIG_TIMERFD=y | ||
| 88 | CONFIG_EVENTFD=y | ||
| 89 | CONFIG_SHMEM=y | ||
| 90 | CONFIG_AIO=y | ||
| 91 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 92 | CONFIG_SLUB_DEBUG=y | ||
| 93 | # CONFIG_COMPAT_BRK is not set | ||
| 94 | # CONFIG_SLAB is not set | ||
| 95 | CONFIG_SLUB=y | ||
| 96 | # CONFIG_SLOB is not set | ||
| 97 | CONFIG_PROFILING=y | ||
| 98 | CONFIG_TRACEPOINTS=y | ||
| 99 | # CONFIG_MARKERS is not set | ||
| 100 | CONFIG_OPROFILE=y | ||
| 101 | CONFIG_HAVE_OPROFILE=y | ||
| 102 | # CONFIG_KPROBES is not set | ||
| 103 | CONFIG_HAVE_KPROBES=y | ||
| 104 | CONFIG_HAVE_KRETPROBES=y | ||
| 105 | CONFIG_HAVE_CLK=y | ||
| 106 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 107 | CONFIG_SLABINFO=y | ||
| 108 | CONFIG_RT_MUTEXES=y | ||
| 109 | CONFIG_BASE_SMALL=0 | ||
| 110 | CONFIG_MODULES=y | ||
| 111 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 112 | CONFIG_MODULE_UNLOAD=y | ||
| 113 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 114 | CONFIG_MODVERSIONS=y | ||
| 115 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 116 | CONFIG_BLOCK=y | ||
| 117 | CONFIG_LBD=y | ||
| 118 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 119 | # CONFIG_BLK_DEV_BSG is not set | ||
| 120 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 121 | |||
| 122 | # | ||
| 123 | # IO Schedulers | ||
| 124 | # | ||
| 125 | CONFIG_IOSCHED_NOOP=y | ||
| 126 | CONFIG_IOSCHED_AS=y | ||
| 127 | CONFIG_IOSCHED_DEADLINE=y | ||
| 128 | CONFIG_IOSCHED_CFQ=y | ||
| 129 | # CONFIG_DEFAULT_AS is not set | ||
| 130 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 131 | CONFIG_DEFAULT_CFQ=y | ||
| 132 | # CONFIG_DEFAULT_NOOP is not set | ||
| 133 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 134 | CONFIG_FREEZER=y | ||
| 135 | |||
| 136 | # | ||
| 137 | # System Type | ||
| 138 | # | ||
| 139 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 140 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 141 | # CONFIG_ARCH_REALVIEW is not set | ||
| 142 | # CONFIG_ARCH_VERSATILE is not set | ||
| 143 | # CONFIG_ARCH_AT91 is not set | ||
| 144 | # CONFIG_ARCH_CLPS711X is not set | ||
| 145 | # CONFIG_ARCH_EBSA110 is not set | ||
| 146 | # CONFIG_ARCH_EP93XX is not set | ||
| 147 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 148 | # CONFIG_ARCH_NETX is not set | ||
| 149 | # CONFIG_ARCH_H720X is not set | ||
| 150 | # CONFIG_ARCH_IMX is not set | ||
| 151 | # CONFIG_ARCH_IOP13XX is not set | ||
| 152 | # CONFIG_ARCH_IOP32X is not set | ||
| 153 | # CONFIG_ARCH_IOP33X is not set | ||
| 154 | # CONFIG_ARCH_IXP23XX is not set | ||
| 155 | # CONFIG_ARCH_IXP2000 is not set | ||
| 156 | # CONFIG_ARCH_IXP4XX is not set | ||
| 157 | # CONFIG_ARCH_L7200 is not set | ||
| 158 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 159 | # CONFIG_ARCH_KS8695 is not set | ||
| 160 | # CONFIG_ARCH_NS9XXX is not set | ||
| 161 | # CONFIG_ARCH_LOKI is not set | ||
| 162 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 163 | # CONFIG_ARCH_MXC is not set | ||
| 164 | # CONFIG_ARCH_ORION5X is not set | ||
| 165 | # CONFIG_ARCH_PNX4008 is not set | ||
| 166 | # CONFIG_ARCH_PXA is not set | ||
| 167 | # CONFIG_ARCH_RPC is not set | ||
| 168 | # CONFIG_ARCH_SA1100 is not set | ||
| 169 | # CONFIG_ARCH_S3C2410 is not set | ||
| 170 | # CONFIG_ARCH_S3C64XX is not set | ||
| 171 | # CONFIG_ARCH_SHARK is not set | ||
| 172 | # CONFIG_ARCH_LH7A40X is not set | ||
| 173 | # CONFIG_ARCH_DAVINCI is not set | ||
| 174 | CONFIG_ARCH_OMAP=y | ||
| 175 | # CONFIG_ARCH_MSM is not set | ||
| 176 | # CONFIG_ARCH_W90X900 is not set | ||
| 177 | |||
| 178 | # | ||
| 179 | # TI OMAP Implementations | ||
| 180 | # | ||
| 181 | CONFIG_ARCH_OMAP_OTG=y | ||
| 182 | # CONFIG_ARCH_OMAP1 is not set | ||
| 183 | # CONFIG_ARCH_OMAP2 is not set | ||
| 184 | CONFIG_ARCH_OMAP3=y | ||
| 185 | |||
| 186 | # | ||
| 187 | # OMAP Feature Selections | ||
| 188 | # | ||
| 189 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | ||
| 190 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | ||
| 191 | # CONFIG_OMAP_RESET_CLOCKS is not set | ||
| 192 | CONFIG_OMAP_MUX=y | ||
| 193 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 194 | CONFIG_OMAP_MUX_WARNINGS=y | ||
| 195 | CONFIG_OMAP_MCBSP=y | ||
| 196 | # CONFIG_OMAP_MPU_TIMER is not set | ||
| 197 | CONFIG_OMAP_32K_TIMER=y | ||
| 198 | CONFIG_OMAP_32K_TIMER_HZ=128 | ||
| 199 | CONFIG_OMAP_DM_TIMER=y | ||
| 200 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | ||
| 201 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | ||
| 202 | CONFIG_OMAP_LL_DEBUG_UART3=y | ||
| 203 | CONFIG_OMAP_SERIAL_WAKE=y | ||
| 204 | CONFIG_ARCH_OMAP34XX=y | ||
| 205 | CONFIG_ARCH_OMAP3430=y | ||
| 206 | |||
| 207 | # | ||
| 208 | # OMAP Board Type | ||
| 209 | # | ||
| 210 | CONFIG_MACH_OMAP3_BEAGLE=y | ||
| 211 | CONFIG_MACH_OMAP_LDP=y | ||
| 212 | CONFIG_MACH_OVERO=y | ||
| 213 | CONFIG_MACH_OMAP3_PANDORA=y | ||
| 214 | CONFIG_MACH_OMAP_3430SDP=y | ||
| 215 | |||
| 216 | # | ||
| 217 | # Processor Type | ||
| 218 | # | ||
| 219 | CONFIG_CPU_32=y | ||
| 220 | CONFIG_CPU_32v6K=y | ||
| 221 | CONFIG_CPU_V7=y | ||
| 222 | CONFIG_CPU_32v7=y | ||
| 223 | CONFIG_CPU_ABRT_EV7=y | ||
| 224 | CONFIG_CPU_PABRT_IFAR=y | ||
| 225 | CONFIG_CPU_CACHE_V7=y | ||
| 226 | CONFIG_CPU_CACHE_VIPT=y | ||
| 227 | CONFIG_CPU_COPY_V6=y | ||
| 228 | CONFIG_CPU_TLB_V7=y | ||
| 229 | CONFIG_CPU_HAS_ASID=y | ||
| 230 | CONFIG_CPU_CP15=y | ||
| 231 | CONFIG_CPU_CP15_MMU=y | ||
| 232 | |||
| 233 | # | ||
| 234 | # Processor Features | ||
| 235 | # | ||
| 236 | CONFIG_ARM_THUMB=y | ||
| 237 | CONFIG_ARM_THUMBEE=y | ||
| 238 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 239 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 240 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 241 | CONFIG_HAS_TLS_REG=y | ||
| 242 | # CONFIG_OUTER_CACHE is not set | ||
| 243 | |||
| 244 | # | ||
| 245 | # Bus support | ||
| 246 | # | ||
| 247 | # CONFIG_PCI_SYSCALL is not set | ||
| 248 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 249 | # CONFIG_PCCARD is not set | ||
| 250 | |||
| 251 | # | ||
| 252 | # Kernel Features | ||
| 253 | # | ||
| 254 | CONFIG_TICK_ONESHOT=y | ||
| 255 | CONFIG_NO_HZ=y | ||
| 256 | CONFIG_HIGH_RES_TIMERS=y | ||
| 257 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 258 | CONFIG_VMSPLIT_3G=y | ||
| 259 | # CONFIG_VMSPLIT_2G is not set | ||
| 260 | # CONFIG_VMSPLIT_1G is not set | ||
| 261 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 262 | # CONFIG_PREEMPT is not set | ||
| 263 | CONFIG_HZ=128 | ||
| 264 | CONFIG_AEABI=y | ||
| 265 | # CONFIG_OABI_COMPAT is not set | ||
| 266 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 267 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 268 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 269 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 270 | CONFIG_FLATMEM_MANUAL=y | ||
| 271 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 272 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 273 | CONFIG_FLATMEM=y | ||
| 274 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 275 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 276 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 277 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 278 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 279 | CONFIG_VIRT_TO_BUS=y | ||
| 280 | CONFIG_UNEVICTABLE_LRU=y | ||
| 281 | CONFIG_LEDS=y | ||
| 282 | CONFIG_ALIGNMENT_TRAP=y | ||
| 283 | |||
| 284 | # | ||
| 285 | # Boot options | ||
| 286 | # | ||
| 287 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 288 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 289 | CONFIG_CMDLINE="console=ttyS2,115200 root=/dev/mmcblk0p3 rootwait debug" | ||
| 290 | # CONFIG_XIP_KERNEL is not set | ||
| 291 | CONFIG_KEXEC=y | ||
| 292 | CONFIG_ATAGS_PROC=y | ||
| 293 | |||
| 294 | # | ||
| 295 | # CPU Power Management | ||
| 296 | # | ||
| 297 | CONFIG_CPU_FREQ=y | ||
| 298 | CONFIG_CPU_FREQ_TABLE=y | ||
| 299 | # CONFIG_CPU_FREQ_DEBUG is not set | ||
| 300 | CONFIG_CPU_FREQ_STAT=y | ||
| 301 | CONFIG_CPU_FREQ_STAT_DETAILS=y | ||
| 302 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
| 303 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 304 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
| 305 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
| 306 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
| 307 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
| 308 | # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set | ||
| 309 | CONFIG_CPU_FREQ_GOV_USERSPACE=y | ||
| 310 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | ||
| 311 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | ||
| 312 | # CONFIG_CPU_IDLE is not set | ||
| 313 | |||
| 314 | # | ||
| 315 | # Floating point emulation | ||
| 316 | # | ||
| 317 | |||
| 318 | # | ||
| 319 | # At least one emulation must be selected | ||
| 320 | # | ||
| 321 | CONFIG_VFP=y | ||
| 322 | CONFIG_VFPv3=y | ||
| 323 | CONFIG_NEON=y | ||
| 324 | |||
| 325 | # | ||
| 326 | # Userspace binary formats | ||
| 327 | # | ||
| 328 | CONFIG_BINFMT_ELF=y | ||
| 329 | CONFIG_HAVE_AOUT=y | ||
| 330 | CONFIG_BINFMT_AOUT=m | ||
| 331 | CONFIG_BINFMT_MISC=y | ||
| 332 | |||
| 333 | # | ||
| 334 | # Power management options | ||
| 335 | # | ||
| 336 | CONFIG_PM=y | ||
| 337 | # CONFIG_PM_DEBUG is not set | ||
| 338 | CONFIG_PM_SLEEP=y | ||
| 339 | CONFIG_SUSPEND=y | ||
| 340 | CONFIG_SUSPEND_FREEZER=y | ||
| 341 | # CONFIG_APM_EMULATION is not set | ||
| 342 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 343 | CONFIG_NET=y | ||
| 344 | |||
| 345 | # | ||
| 346 | # Networking options | ||
| 347 | # | ||
| 348 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 349 | CONFIG_PACKET=y | ||
| 350 | CONFIG_PACKET_MMAP=y | ||
| 351 | CONFIG_UNIX=y | ||
| 352 | CONFIG_XFRM=y | ||
| 353 | # CONFIG_XFRM_USER is not set | ||
| 354 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 355 | # CONFIG_XFRM_MIGRATE is not set | ||
| 356 | # CONFIG_XFRM_STATISTICS is not set | ||
| 357 | CONFIG_NET_KEY=y | ||
| 358 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 359 | CONFIG_INET=y | ||
| 360 | # CONFIG_IP_MULTICAST is not set | ||
| 361 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 362 | CONFIG_IP_FIB_HASH=y | ||
| 363 | CONFIG_IP_PNP=y | ||
| 364 | CONFIG_IP_PNP_DHCP=y | ||
| 365 | CONFIG_IP_PNP_BOOTP=y | ||
| 366 | CONFIG_IP_PNP_RARP=y | ||
| 367 | # CONFIG_NET_IPIP is not set | ||
| 368 | # CONFIG_NET_IPGRE is not set | ||
| 369 | # CONFIG_ARPD is not set | ||
| 370 | # CONFIG_SYN_COOKIES is not set | ||
| 371 | # CONFIG_INET_AH is not set | ||
| 372 | # CONFIG_INET_ESP is not set | ||
| 373 | # CONFIG_INET_IPCOMP is not set | ||
| 374 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 375 | CONFIG_INET_TUNNEL=m | ||
| 376 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 377 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 378 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 379 | # CONFIG_INET_LRO is not set | ||
| 380 | CONFIG_INET_DIAG=y | ||
| 381 | CONFIG_INET_TCP_DIAG=y | ||
| 382 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 383 | CONFIG_TCP_CONG_CUBIC=y | ||
| 384 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 385 | # CONFIG_TCP_MD5SIG is not set | ||
| 386 | CONFIG_IPV6=m | ||
| 387 | # CONFIG_IPV6_PRIVACY is not set | ||
| 388 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 389 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 390 | # CONFIG_INET6_AH is not set | ||
| 391 | # CONFIG_INET6_ESP is not set | ||
| 392 | # CONFIG_INET6_IPCOMP is not set | ||
| 393 | # CONFIG_IPV6_MIP6 is not set | ||
| 394 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 395 | # CONFIG_INET6_TUNNEL is not set | ||
| 396 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
| 397 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
| 398 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
| 399 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 400 | CONFIG_IPV6_SIT=m | ||
| 401 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 402 | # CONFIG_IPV6_TUNNEL is not set | ||
| 403 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 404 | # CONFIG_IPV6_MROUTE is not set | ||
| 405 | # CONFIG_NETWORK_SECMARK is not set | ||
| 406 | # CONFIG_NETFILTER is not set | ||
| 407 | # CONFIG_IP_DCCP is not set | ||
| 408 | # CONFIG_IP_SCTP is not set | ||
| 409 | # CONFIG_TIPC is not set | ||
| 410 | # CONFIG_ATM is not set | ||
| 411 | # CONFIG_BRIDGE is not set | ||
| 412 | # CONFIG_NET_DSA is not set | ||
| 413 | # CONFIG_VLAN_8021Q is not set | ||
| 414 | # CONFIG_DECNET is not set | ||
| 415 | # CONFIG_LLC2 is not set | ||
| 416 | # CONFIG_IPX is not set | ||
| 417 | # CONFIG_ATALK is not set | ||
| 418 | # CONFIG_X25 is not set | ||
| 419 | # CONFIG_LAPB is not set | ||
| 420 | # CONFIG_ECONET is not set | ||
| 421 | # CONFIG_WAN_ROUTER is not set | ||
| 422 | # CONFIG_NET_SCHED is not set | ||
| 423 | # CONFIG_DCB is not set | ||
| 424 | |||
| 425 | # | ||
| 426 | # Network testing | ||
| 427 | # | ||
| 428 | # CONFIG_NET_PKTGEN is not set | ||
| 429 | # CONFIG_HAMRADIO is not set | ||
| 430 | # CONFIG_CAN is not set | ||
| 431 | # CONFIG_IRDA is not set | ||
| 432 | CONFIG_BT=y | ||
| 433 | CONFIG_BT_L2CAP=y | ||
| 434 | CONFIG_BT_SCO=y | ||
| 435 | CONFIG_BT_RFCOMM=y | ||
| 436 | CONFIG_BT_RFCOMM_TTY=y | ||
| 437 | CONFIG_BT_BNEP=y | ||
| 438 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 439 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 440 | CONFIG_BT_HIDP=y | ||
| 441 | |||
| 442 | # | ||
| 443 | # Bluetooth device drivers | ||
| 444 | # | ||
| 445 | # CONFIG_BT_HCIBTUSB is not set | ||
| 446 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 447 | CONFIG_BT_HCIUART=y | ||
| 448 | CONFIG_BT_HCIUART_H4=y | ||
| 449 | CONFIG_BT_HCIUART_BCSP=y | ||
| 450 | # CONFIG_BT_HCIUART_LL is not set | ||
| 451 | CONFIG_BT_HCIBCM203X=y | ||
| 452 | CONFIG_BT_HCIBPA10X=y | ||
| 453 | # CONFIG_BT_HCIBFUSB is not set | ||
| 454 | # CONFIG_BT_HCIVHCI is not set | ||
| 455 | # CONFIG_AF_RXRPC is not set | ||
| 456 | # CONFIG_PHONET is not set | ||
| 457 | CONFIG_WIRELESS=y | ||
| 458 | CONFIG_CFG80211=y | ||
| 459 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 460 | CONFIG_NL80211=y | ||
| 461 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 462 | CONFIG_WIRELESS_EXT=y | ||
| 463 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 464 | CONFIG_LIB80211=y | ||
| 465 | CONFIG_LIB80211_CRYPT_WEP=m | ||
| 466 | CONFIG_LIB80211_CRYPT_CCMP=m | ||
| 467 | CONFIG_LIB80211_CRYPT_TKIP=m | ||
| 468 | CONFIG_MAC80211=y | ||
| 469 | |||
| 470 | # | ||
| 471 | # Rate control algorithm selection | ||
| 472 | # | ||
| 473 | CONFIG_MAC80211_RC_PID=y | ||
| 474 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
| 475 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
| 476 | # CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set | ||
| 477 | CONFIG_MAC80211_RC_DEFAULT="pid" | ||
| 478 | # CONFIG_MAC80211_MESH is not set | ||
| 479 | CONFIG_MAC80211_LEDS=y | ||
| 480 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 481 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 482 | # CONFIG_WIMAX is not set | ||
| 483 | # CONFIG_RFKILL is not set | ||
| 484 | # CONFIG_NET_9P is not set | ||
| 485 | |||
| 486 | # | ||
| 487 | # Device Drivers | ||
| 488 | # | ||
| 489 | |||
| 490 | # | ||
| 491 | # Generic Driver Options | ||
| 492 | # | ||
| 493 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 494 | CONFIG_STANDALONE=y | ||
| 495 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 496 | CONFIG_FW_LOADER=y | ||
| 497 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 498 | CONFIG_EXTRA_FIRMWARE="" | ||
| 499 | # CONFIG_DEBUG_DRIVER is not set | ||
| 500 | # CONFIG_DEBUG_DEVRES is not set | ||
| 501 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 502 | # CONFIG_CONNECTOR is not set | ||
| 503 | CONFIG_MTD=y | ||
| 504 | # CONFIG_MTD_DEBUG is not set | ||
| 505 | CONFIG_MTD_CONCAT=y | ||
| 506 | CONFIG_MTD_PARTITIONS=y | ||
| 507 | # CONFIG_MTD_TESTS is not set | ||
| 508 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 509 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 510 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 511 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 512 | |||
| 513 | # | ||
| 514 | # User Modules And Translation Layers | ||
| 515 | # | ||
| 516 | CONFIG_MTD_CHAR=y | ||
| 517 | CONFIG_MTD_BLKDEVS=y | ||
| 518 | CONFIG_MTD_BLOCK=y | ||
| 519 | # CONFIG_FTL is not set | ||
| 520 | # CONFIG_NFTL is not set | ||
| 521 | # CONFIG_INFTL is not set | ||
| 522 | # CONFIG_RFD_FTL is not set | ||
| 523 | # CONFIG_SSFDC is not set | ||
| 524 | # CONFIG_MTD_OOPS is not set | ||
| 525 | |||
| 526 | # | ||
| 527 | # RAM/ROM/Flash chip drivers | ||
| 528 | # | ||
| 529 | # CONFIG_MTD_CFI is not set | ||
| 530 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 531 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 532 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 533 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 534 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 535 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 536 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 537 | CONFIG_MTD_CFI_I1=y | ||
| 538 | CONFIG_MTD_CFI_I2=y | ||
| 539 | # CONFIG_MTD_CFI_I4 is not set | ||
| 540 | # CONFIG_MTD_CFI_I8 is not set | ||
| 541 | # CONFIG_MTD_RAM is not set | ||
| 542 | # CONFIG_MTD_ROM is not set | ||
| 543 | # CONFIG_MTD_ABSENT is not set | ||
| 544 | |||
| 545 | # | ||
| 546 | # Mapping drivers for chip access | ||
| 547 | # | ||
| 548 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 549 | # CONFIG_MTD_PLATRAM is not set | ||
| 550 | |||
| 551 | # | ||
| 552 | # Self-contained MTD device drivers | ||
| 553 | # | ||
| 554 | # CONFIG_MTD_DATAFLASH is not set | ||
| 555 | # CONFIG_MTD_M25P80 is not set | ||
| 556 | # CONFIG_MTD_SLRAM is not set | ||
| 557 | # CONFIG_MTD_PHRAM is not set | ||
| 558 | # CONFIG_MTD_MTDRAM is not set | ||
| 559 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 560 | |||
| 561 | # | ||
| 562 | # Disk-On-Chip Device Drivers | ||
| 563 | # | ||
| 564 | # CONFIG_MTD_DOC2000 is not set | ||
| 565 | # CONFIG_MTD_DOC2001 is not set | ||
| 566 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 567 | CONFIG_MTD_NAND=y | ||
| 568 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 569 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 570 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 571 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 572 | CONFIG_MTD_NAND_IDS=y | ||
| 573 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 574 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 575 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 576 | # CONFIG_MTD_ALAUDA is not set | ||
| 577 | # CONFIG_MTD_ONENAND is not set | ||
| 578 | |||
| 579 | # | ||
| 580 | # LPDDR flash memory drivers | ||
| 581 | # | ||
| 582 | # CONFIG_MTD_LPDDR is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # UBI - Unsorted block images | ||
| 586 | # | ||
| 587 | # CONFIG_MTD_UBI is not set | ||
| 588 | # CONFIG_PARPORT is not set | ||
| 589 | CONFIG_BLK_DEV=y | ||
| 590 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 591 | CONFIG_BLK_DEV_LOOP=y | ||
| 592 | CONFIG_BLK_DEV_CRYPTOLOOP=m | ||
| 593 | # CONFIG_BLK_DEV_NBD is not set | ||
| 594 | # CONFIG_BLK_DEV_UB is not set | ||
| 595 | CONFIG_BLK_DEV_RAM=y | ||
| 596 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 597 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 598 | # CONFIG_BLK_DEV_XIP is not set | ||
| 599 | CONFIG_CDROM_PKTCDVD=m | ||
| 600 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | ||
| 601 | # CONFIG_CDROM_PKTCDVD_WCACHE is not set | ||
| 602 | # CONFIG_ATA_OVER_ETH is not set | ||
| 603 | CONFIG_MISC_DEVICES=y | ||
| 604 | # CONFIG_ICS932S401 is not set | ||
| 605 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 606 | # CONFIG_C2PORT is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # EEPROM support | ||
| 610 | # | ||
| 611 | # CONFIG_EEPROM_AT24 is not set | ||
| 612 | # CONFIG_EEPROM_AT25 is not set | ||
| 613 | # CONFIG_EEPROM_LEGACY is not set | ||
| 614 | CONFIG_EEPROM_93CX6=m | ||
| 615 | CONFIG_HAVE_IDE=y | ||
| 616 | # CONFIG_IDE is not set | ||
| 617 | |||
| 618 | # | ||
| 619 | # SCSI device support | ||
| 620 | # | ||
| 621 | CONFIG_RAID_ATTRS=m | ||
| 622 | CONFIG_SCSI=y | ||
| 623 | CONFIG_SCSI_DMA=y | ||
| 624 | # CONFIG_SCSI_TGT is not set | ||
| 625 | # CONFIG_SCSI_NETLINK is not set | ||
| 626 | CONFIG_SCSI_PROC_FS=y | ||
| 627 | |||
| 628 | # | ||
| 629 | # SCSI support type (disk, tape, CD-ROM) | ||
| 630 | # | ||
| 631 | CONFIG_BLK_DEV_SD=y | ||
| 632 | # CONFIG_CHR_DEV_ST is not set | ||
| 633 | # CONFIG_CHR_DEV_OSST is not set | ||
| 634 | # CONFIG_BLK_DEV_SR is not set | ||
| 635 | CONFIG_CHR_DEV_SG=m | ||
| 636 | # CONFIG_CHR_DEV_SCH is not set | ||
| 637 | |||
| 638 | # | ||
| 639 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 640 | # | ||
| 641 | CONFIG_SCSI_MULTI_LUN=y | ||
| 642 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 643 | # CONFIG_SCSI_LOGGING is not set | ||
| 644 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 645 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 646 | |||
| 647 | # | ||
| 648 | # SCSI Transports | ||
| 649 | # | ||
| 650 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 651 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 652 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 653 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 654 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 655 | CONFIG_SCSI_LOWLEVEL=y | ||
| 656 | # CONFIG_ISCSI_TCP is not set | ||
| 657 | # CONFIG_LIBFC is not set | ||
| 658 | # CONFIG_SCSI_DEBUG is not set | ||
| 659 | # CONFIG_SCSI_DH is not set | ||
| 660 | # CONFIG_ATA is not set | ||
| 661 | CONFIG_MD=y | ||
| 662 | CONFIG_BLK_DEV_MD=m | ||
| 663 | CONFIG_MD_LINEAR=m | ||
| 664 | CONFIG_MD_RAID0=m | ||
| 665 | CONFIG_MD_RAID1=m | ||
| 666 | CONFIG_MD_RAID10=m | ||
| 667 | CONFIG_MD_RAID456=m | ||
| 668 | CONFIG_MD_RAID5_RESHAPE=y | ||
| 669 | CONFIG_MD_MULTIPATH=m | ||
| 670 | CONFIG_MD_FAULTY=m | ||
| 671 | CONFIG_BLK_DEV_DM=m | ||
| 672 | # CONFIG_DM_DEBUG is not set | ||
| 673 | CONFIG_DM_CRYPT=m | ||
| 674 | CONFIG_DM_SNAPSHOT=m | ||
| 675 | CONFIG_DM_MIRROR=m | ||
| 676 | CONFIG_DM_ZERO=m | ||
| 677 | CONFIG_DM_MULTIPATH=m | ||
| 678 | CONFIG_DM_DELAY=m | ||
| 679 | # CONFIG_DM_UEVENT is not set | ||
| 680 | CONFIG_NETDEVICES=y | ||
| 681 | CONFIG_DUMMY=m | ||
| 682 | # CONFIG_BONDING is not set | ||
| 683 | # CONFIG_MACVLAN is not set | ||
| 684 | # CONFIG_EQUALIZER is not set | ||
| 685 | CONFIG_TUN=m | ||
| 686 | # CONFIG_VETH is not set | ||
| 687 | CONFIG_PHYLIB=y | ||
| 688 | |||
| 689 | # | ||
| 690 | # MII PHY device drivers | ||
| 691 | # | ||
| 692 | # CONFIG_MARVELL_PHY is not set | ||
| 693 | # CONFIG_DAVICOM_PHY is not set | ||
| 694 | # CONFIG_QSEMI_PHY is not set | ||
| 695 | # CONFIG_LXT_PHY is not set | ||
| 696 | # CONFIG_CICADA_PHY is not set | ||
| 697 | # CONFIG_VITESSE_PHY is not set | ||
| 698 | CONFIG_SMSC_PHY=y | ||
| 699 | # CONFIG_BROADCOM_PHY is not set | ||
| 700 | # CONFIG_ICPLUS_PHY is not set | ||
| 701 | # CONFIG_REALTEK_PHY is not set | ||
| 702 | # CONFIG_NATIONAL_PHY is not set | ||
| 703 | # CONFIG_STE10XP is not set | ||
| 704 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 705 | # CONFIG_FIXED_PHY is not set | ||
| 706 | # CONFIG_MDIO_BITBANG is not set | ||
| 707 | CONFIG_NET_ETHERNET=y | ||
| 708 | CONFIG_MII=y | ||
| 709 | # CONFIG_AX88796 is not set | ||
| 710 | CONFIG_SMC91X=y | ||
| 711 | # CONFIG_DM9000 is not set | ||
| 712 | # CONFIG_ENC28J60 is not set | ||
| 713 | CONFIG_SMC911X=m | ||
| 714 | CONFIG_SMSC911X=m | ||
| 715 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 716 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 717 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 718 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 719 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 720 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 721 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 722 | # CONFIG_B44 is not set | ||
| 723 | # CONFIG_NETDEV_1000 is not set | ||
| 724 | # CONFIG_NETDEV_10000 is not set | ||
| 725 | |||
| 726 | # | ||
| 727 | # Wireless LAN | ||
| 728 | # | ||
| 729 | # CONFIG_WLAN_PRE80211 is not set | ||
| 730 | CONFIG_WLAN_80211=y | ||
| 731 | CONFIG_LIBERTAS=y | ||
| 732 | CONFIG_LIBERTAS_USB=y | ||
| 733 | CONFIG_LIBERTAS_SDIO=y | ||
| 734 | CONFIG_LIBERTAS_DEBUG=y | ||
| 735 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 736 | CONFIG_USB_ZD1201=m | ||
| 737 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 738 | CONFIG_RTL8187=m | ||
| 739 | # CONFIG_MAC80211_HWSIM is not set | ||
| 740 | CONFIG_P54_COMMON=m | ||
| 741 | CONFIG_P54_USB=m | ||
| 742 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 743 | CONFIG_HOSTAP=m | ||
| 744 | CONFIG_HOSTAP_FIRMWARE=y | ||
| 745 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | ||
| 746 | # CONFIG_B43 is not set | ||
| 747 | # CONFIG_B43LEGACY is not set | ||
| 748 | # CONFIG_ZD1211RW is not set | ||
| 749 | # CONFIG_RT2X00 is not set | ||
| 750 | |||
| 751 | # | ||
| 752 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 753 | # | ||
| 754 | |||
| 755 | # | ||
| 756 | # USB Network Adapters | ||
| 757 | # | ||
| 758 | CONFIG_USB_CATC=m | ||
| 759 | CONFIG_USB_KAWETH=m | ||
| 760 | CONFIG_USB_PEGASUS=m | ||
| 761 | CONFIG_USB_RTL8150=m | ||
| 762 | CONFIG_USB_USBNET=y | ||
| 763 | CONFIG_USB_NET_AX8817X=y | ||
| 764 | CONFIG_USB_NET_CDCETHER=y | ||
| 765 | CONFIG_USB_NET_DM9601=m | ||
| 766 | # CONFIG_USB_NET_SMSC95XX is not set | ||
| 767 | CONFIG_USB_NET_GL620A=m | ||
| 768 | CONFIG_USB_NET_NET1080=m | ||
| 769 | CONFIG_USB_NET_PLUSB=m | ||
| 770 | CONFIG_USB_NET_MCS7830=m | ||
| 771 | CONFIG_USB_NET_RNDIS_HOST=m | ||
| 772 | CONFIG_USB_NET_CDC_SUBSET=m | ||
| 773 | CONFIG_USB_ALI_M5632=y | ||
| 774 | CONFIG_USB_AN2720=y | ||
| 775 | CONFIG_USB_BELKIN=y | ||
| 776 | CONFIG_USB_ARMLINUX=y | ||
| 777 | CONFIG_USB_EPSON2888=y | ||
| 778 | CONFIG_USB_KC2190=y | ||
| 779 | CONFIG_USB_NET_ZAURUS=m | ||
| 780 | # CONFIG_WAN is not set | ||
| 781 | CONFIG_PPP=m | ||
| 782 | # CONFIG_PPP_MULTILINK is not set | ||
| 783 | # CONFIG_PPP_FILTER is not set | ||
| 784 | CONFIG_PPP_ASYNC=m | ||
| 785 | CONFIG_PPP_SYNC_TTY=m | ||
| 786 | CONFIG_PPP_DEFLATE=m | ||
| 787 | CONFIG_PPP_BSDCOMP=m | ||
| 788 | CONFIG_PPP_MPPE=m | ||
| 789 | CONFIG_PPPOE=m | ||
| 790 | # CONFIG_PPPOL2TP is not set | ||
| 791 | # CONFIG_SLIP is not set | ||
| 792 | CONFIG_SLHC=m | ||
| 793 | # CONFIG_NETCONSOLE is not set | ||
| 794 | # CONFIG_NETPOLL is not set | ||
| 795 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 796 | # CONFIG_ISDN is not set | ||
| 797 | |||
| 798 | # | ||
| 799 | # Input device support | ||
| 800 | # | ||
| 801 | CONFIG_INPUT=y | ||
| 802 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 803 | # CONFIG_INPUT_POLLDEV is not set | ||
| 804 | |||
| 805 | # | ||
| 806 | # Userland interfaces | ||
| 807 | # | ||
| 808 | CONFIG_INPUT_MOUSEDEV=y | ||
| 809 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 810 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 811 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 812 | # CONFIG_INPUT_JOYDEV is not set | ||
| 813 | CONFIG_INPUT_EVDEV=y | ||
| 814 | # CONFIG_INPUT_EVBUG is not set | ||
| 815 | |||
| 816 | # | ||
| 817 | # Input Device Drivers | ||
| 818 | # | ||
| 819 | CONFIG_INPUT_KEYBOARD=y | ||
| 820 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 821 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 822 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 823 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 824 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 825 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 826 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 827 | CONFIG_INPUT_MOUSE=y | ||
| 828 | CONFIG_MOUSE_PS2=y | ||
| 829 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 830 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 831 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 832 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 833 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 834 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 835 | # CONFIG_MOUSE_SERIAL is not set | ||
| 836 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 837 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 838 | # CONFIG_MOUSE_VSXXXAA is not set | ||
| 839 | # CONFIG_MOUSE_GPIO is not set | ||
| 840 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 841 | # CONFIG_INPUT_TABLET is not set | ||
| 842 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 843 | # CONFIG_INPUT_MISC is not set | ||
| 844 | |||
| 845 | # | ||
| 846 | # Hardware I/O ports | ||
| 847 | # | ||
| 848 | CONFIG_SERIO=y | ||
| 849 | CONFIG_SERIO_SERPORT=y | ||
| 850 | CONFIG_SERIO_LIBPS2=y | ||
| 851 | # CONFIG_SERIO_RAW is not set | ||
| 852 | # CONFIG_GAMEPORT is not set | ||
| 853 | |||
| 854 | # | ||
| 855 | # Character devices | ||
| 856 | # | ||
| 857 | CONFIG_VT=y | ||
| 858 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 859 | CONFIG_VT_CONSOLE=y | ||
| 860 | CONFIG_HW_CONSOLE=y | ||
| 861 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 862 | CONFIG_DEVKMEM=y | ||
| 863 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 864 | |||
| 865 | # | ||
| 866 | # Serial drivers | ||
| 867 | # | ||
| 868 | CONFIG_SERIAL_8250=y | ||
| 869 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 870 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 871 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 872 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 873 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 874 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 875 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 876 | CONFIG_SERIAL_8250_RSA=y | ||
| 877 | |||
| 878 | # | ||
| 879 | # Non-8250 serial port support | ||
| 880 | # | ||
| 881 | CONFIG_SERIAL_CORE=y | ||
| 882 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 883 | CONFIG_UNIX98_PTYS=y | ||
| 884 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 885 | # CONFIG_LEGACY_PTYS is not set | ||
| 886 | # CONFIG_IPMI_HANDLER is not set | ||
| 887 | CONFIG_HW_RANDOM=y | ||
| 888 | # CONFIG_R3964 is not set | ||
| 889 | # CONFIG_RAW_DRIVER is not set | ||
| 890 | # CONFIG_TCG_TPM is not set | ||
| 891 | CONFIG_I2C=y | ||
| 892 | CONFIG_I2C_BOARDINFO=y | ||
| 893 | CONFIG_I2C_CHARDEV=y | ||
| 894 | CONFIG_I2C_HELPER_AUTO=y | ||
| 895 | |||
| 896 | # | ||
| 897 | # I2C Hardware Bus support | ||
| 898 | # | ||
| 899 | |||
| 900 | # | ||
| 901 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 902 | # | ||
| 903 | # CONFIG_I2C_GPIO is not set | ||
| 904 | # CONFIG_I2C_OCORES is not set | ||
| 905 | CONFIG_I2C_OMAP=y | ||
| 906 | # CONFIG_I2C_SIMTEC is not set | ||
| 907 | |||
| 908 | # | ||
| 909 | # External I2C/SMBus adapter drivers | ||
| 910 | # | ||
| 911 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 912 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 913 | # CONFIG_I2C_TINY_USB is not set | ||
| 914 | |||
| 915 | # | ||
| 916 | # Other I2C/SMBus bus drivers | ||
| 917 | # | ||
| 918 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 919 | # CONFIG_I2C_STUB is not set | ||
| 920 | |||
| 921 | # | ||
| 922 | # Miscellaneous I2C Chip support | ||
| 923 | # | ||
| 924 | # CONFIG_DS1682 is not set | ||
| 925 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 926 | # CONFIG_PCF8575 is not set | ||
| 927 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 928 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 929 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 930 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 931 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 932 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 933 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 934 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 935 | CONFIG_SPI=y | ||
| 936 | # CONFIG_SPI_DEBUG is not set | ||
| 937 | CONFIG_SPI_MASTER=y | ||
| 938 | |||
| 939 | # | ||
| 940 | # SPI Master Controller Drivers | ||
| 941 | # | ||
| 942 | # CONFIG_SPI_BITBANG is not set | ||
| 943 | # CONFIG_SPI_GPIO is not set | ||
| 944 | CONFIG_SPI_OMAP24XX=y | ||
| 945 | |||
| 946 | # | ||
| 947 | # SPI Protocol Masters | ||
| 948 | # | ||
| 949 | # CONFIG_SPI_SPIDEV is not set | ||
| 950 | # CONFIG_SPI_TLE62X0 is not set | ||
| 951 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 952 | CONFIG_GPIOLIB=y | ||
| 953 | CONFIG_DEBUG_GPIO=y | ||
| 954 | CONFIG_GPIO_SYSFS=y | ||
| 955 | |||
| 956 | # | ||
| 957 | # Memory mapped GPIO expanders: | ||
| 958 | # | ||
| 959 | |||
| 960 | # | ||
| 961 | # I2C GPIO expanders: | ||
| 962 | # | ||
| 963 | # CONFIG_GPIO_MAX732X is not set | ||
| 964 | # CONFIG_GPIO_PCA953X is not set | ||
| 965 | # CONFIG_GPIO_PCF857X is not set | ||
| 966 | CONFIG_GPIO_TWL4030=y | ||
| 967 | |||
| 968 | # | ||
| 969 | # PCI GPIO expanders: | ||
| 970 | # | ||
| 971 | |||
| 972 | # | ||
| 973 | # SPI GPIO expanders: | ||
| 974 | # | ||
| 975 | # CONFIG_GPIO_MAX7301 is not set | ||
| 976 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 977 | # CONFIG_W1 is not set | ||
| 978 | CONFIG_POWER_SUPPLY=m | ||
| 979 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 980 | # CONFIG_PDA_POWER is not set | ||
| 981 | # CONFIG_BATTERY_DS2760 is not set | ||
| 982 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 983 | CONFIG_HWMON=y | ||
| 984 | # CONFIG_HWMON_VID is not set | ||
| 985 | # CONFIG_SENSORS_AD7414 is not set | ||
| 986 | # CONFIG_SENSORS_AD7418 is not set | ||
| 987 | # CONFIG_SENSORS_ADCXX is not set | ||
| 988 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 989 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 990 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 991 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 992 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 993 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 994 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 995 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 996 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 997 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 998 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 999 | # CONFIG_SENSORS_DS1621 is not set | ||
| 1000 | # CONFIG_SENSORS_F71805F is not set | ||
| 1001 | # CONFIG_SENSORS_F71882FG is not set | ||
| 1002 | # CONFIG_SENSORS_F75375S is not set | ||
| 1003 | # CONFIG_SENSORS_GL518SM is not set | ||
| 1004 | # CONFIG_SENSORS_GL520SM is not set | ||
| 1005 | # CONFIG_SENSORS_IT87 is not set | ||
| 1006 | # CONFIG_SENSORS_LM63 is not set | ||
| 1007 | # CONFIG_SENSORS_LM70 is not set | ||
| 1008 | # CONFIG_SENSORS_LM75 is not set | ||
| 1009 | # CONFIG_SENSORS_LM77 is not set | ||
| 1010 | # CONFIG_SENSORS_LM78 is not set | ||
| 1011 | # CONFIG_SENSORS_LM80 is not set | ||
| 1012 | # CONFIG_SENSORS_LM83 is not set | ||
| 1013 | # CONFIG_SENSORS_LM85 is not set | ||
| 1014 | # CONFIG_SENSORS_LM87 is not set | ||
| 1015 | # CONFIG_SENSORS_LM90 is not set | ||
| 1016 | # CONFIG_SENSORS_LM92 is not set | ||
| 1017 | # CONFIG_SENSORS_LM93 is not set | ||
| 1018 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 1019 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 1020 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 1021 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 1022 | # CONFIG_SENSORS_PC87360 is not set | ||
| 1023 | # CONFIG_SENSORS_PC87427 is not set | ||
| 1024 | # CONFIG_SENSORS_DME1737 is not set | ||
| 1025 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 1026 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 1027 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 1028 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 1029 | # CONFIG_SENSORS_THMC50 is not set | ||
| 1030 | # CONFIG_SENSORS_VT1211 is not set | ||
| 1031 | # CONFIG_SENSORS_W83781D is not set | ||
| 1032 | # CONFIG_SENSORS_W83791D is not set | ||
| 1033 | # CONFIG_SENSORS_W83792D is not set | ||
| 1034 | # CONFIG_SENSORS_W83793 is not set | ||
| 1035 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 1036 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 1037 | # CONFIG_SENSORS_W83627HF is not set | ||
| 1038 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 1039 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 1040 | # CONFIG_THERMAL is not set | ||
| 1041 | # CONFIG_THERMAL_HWMON is not set | ||
| 1042 | CONFIG_WATCHDOG=y | ||
| 1043 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 1044 | |||
| 1045 | # | ||
| 1046 | # Watchdog Device Drivers | ||
| 1047 | # | ||
| 1048 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 1049 | # CONFIG_OMAP_WATCHDOG is not set | ||
| 1050 | |||
| 1051 | # | ||
| 1052 | # USB-based Watchdog Cards | ||
| 1053 | # | ||
| 1054 | # CONFIG_USBPCWATCHDOG is not set | ||
| 1055 | CONFIG_SSB_POSSIBLE=y | ||
| 1056 | |||
| 1057 | # | ||
| 1058 | # Sonics Silicon Backplane | ||
| 1059 | # | ||
| 1060 | # CONFIG_SSB is not set | ||
| 1061 | |||
| 1062 | # | ||
| 1063 | # Multifunction device drivers | ||
| 1064 | # | ||
| 1065 | # CONFIG_MFD_CORE is not set | ||
| 1066 | # CONFIG_MFD_SM501 is not set | ||
| 1067 | # CONFIG_MFD_ASIC3 is not set | ||
| 1068 | # CONFIG_HTC_EGPIO is not set | ||
| 1069 | # CONFIG_HTC_PASIC3 is not set | ||
| 1070 | # CONFIG_TPS65010 is not set | ||
| 1071 | CONFIG_TWL4030_CORE=y | ||
| 1072 | # CONFIG_MFD_TMIO is not set | ||
| 1073 | # CONFIG_MFD_T7L66XB is not set | ||
| 1074 | # CONFIG_MFD_TC6387XB is not set | ||
| 1075 | # CONFIG_MFD_TC6393XB is not set | ||
| 1076 | # CONFIG_PMIC_DA903X is not set | ||
| 1077 | # CONFIG_MFD_WM8400 is not set | ||
| 1078 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1079 | # CONFIG_MFD_PCF50633 is not set | ||
| 1080 | |||
| 1081 | # | ||
| 1082 | # Multimedia devices | ||
| 1083 | # | ||
| 1084 | |||
| 1085 | # | ||
| 1086 | # Multimedia core support | ||
| 1087 | # | ||
| 1088 | CONFIG_VIDEO_DEV=m | ||
| 1089 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1090 | CONFIG_VIDEO_ALLOW_V4L1=y | ||
| 1091 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1092 | CONFIG_DVB_CORE=m | ||
| 1093 | CONFIG_VIDEO_MEDIA=m | ||
| 1094 | |||
| 1095 | # | ||
| 1096 | # Multimedia drivers | ||
| 1097 | # | ||
| 1098 | CONFIG_MEDIA_ATTACH=y | ||
| 1099 | CONFIG_MEDIA_TUNER=m | ||
| 1100 | # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set | ||
| 1101 | CONFIG_MEDIA_TUNER_SIMPLE=m | ||
| 1102 | CONFIG_MEDIA_TUNER_TDA8290=m | ||
| 1103 | CONFIG_MEDIA_TUNER_TDA827X=m | ||
| 1104 | CONFIG_MEDIA_TUNER_TDA18271=m | ||
| 1105 | CONFIG_MEDIA_TUNER_TDA9887=m | ||
| 1106 | CONFIG_MEDIA_TUNER_TEA5761=m | ||
| 1107 | CONFIG_MEDIA_TUNER_TEA5767=m | ||
| 1108 | CONFIG_MEDIA_TUNER_MT20XX=m | ||
| 1109 | CONFIG_MEDIA_TUNER_MT2060=m | ||
| 1110 | CONFIG_MEDIA_TUNER_MT2266=m | ||
| 1111 | CONFIG_MEDIA_TUNER_QT1010=m | ||
| 1112 | CONFIG_MEDIA_TUNER_XC2028=m | ||
| 1113 | CONFIG_MEDIA_TUNER_XC5000=m | ||
| 1114 | CONFIG_MEDIA_TUNER_MXL5005S=m | ||
| 1115 | CONFIG_VIDEO_V4L2=m | ||
| 1116 | CONFIG_VIDEO_V4L1=m | ||
| 1117 | CONFIG_VIDEO_TVEEPROM=m | ||
| 1118 | CONFIG_VIDEO_TUNER=m | ||
| 1119 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1120 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1121 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1122 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | ||
| 1123 | CONFIG_VIDEO_MSP3400=m | ||
| 1124 | CONFIG_VIDEO_CS53L32A=m | ||
| 1125 | CONFIG_VIDEO_WM8775=m | ||
| 1126 | CONFIG_VIDEO_SAA711X=m | ||
| 1127 | CONFIG_VIDEO_CX25840=m | ||
| 1128 | CONFIG_VIDEO_CX2341X=m | ||
| 1129 | # CONFIG_VIDEO_VIVI is not set | ||
| 1130 | # CONFIG_VIDEO_CPIA is not set | ||
| 1131 | # CONFIG_VIDEO_CPIA2 is not set | ||
| 1132 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1133 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1134 | # CONFIG_VIDEO_AU0828 is not set | ||
| 1135 | # CONFIG_SOC_CAMERA is not set | ||
| 1136 | CONFIG_V4L_USB_DRIVERS=y | ||
| 1137 | CONFIG_USB_VIDEO_CLASS=m | ||
| 1138 | CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y | ||
| 1139 | # CONFIG_USB_GSPCA is not set | ||
| 1140 | CONFIG_VIDEO_PVRUSB2=m | ||
| 1141 | CONFIG_VIDEO_PVRUSB2_SYSFS=y | ||
| 1142 | CONFIG_VIDEO_PVRUSB2_DVB=y | ||
| 1143 | # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set | ||
| 1144 | # CONFIG_VIDEO_EM28XX is not set | ||
| 1145 | CONFIG_VIDEO_USBVISION=m | ||
| 1146 | CONFIG_VIDEO_USBVIDEO=m | ||
| 1147 | CONFIG_USB_VICAM=m | ||
| 1148 | CONFIG_USB_IBMCAM=m | ||
| 1149 | CONFIG_USB_KONICAWC=m | ||
| 1150 | CONFIG_USB_QUICKCAM_MESSENGER=m | ||
| 1151 | # CONFIG_USB_ET61X251 is not set | ||
| 1152 | CONFIG_VIDEO_OVCAMCHIP=m | ||
| 1153 | CONFIG_USB_W9968CF=m | ||
| 1154 | CONFIG_USB_OV511=m | ||
| 1155 | CONFIG_USB_SE401=m | ||
| 1156 | CONFIG_USB_SN9C102=m | ||
| 1157 | CONFIG_USB_STV680=m | ||
| 1158 | # CONFIG_USB_ZC0301 is not set | ||
| 1159 | CONFIG_USB_PWC=m | ||
| 1160 | # CONFIG_USB_PWC_DEBUG is not set | ||
| 1161 | CONFIG_USB_ZR364XX=m | ||
| 1162 | # CONFIG_USB_STKWEBCAM is not set | ||
| 1163 | # CONFIG_USB_S2255 is not set | ||
| 1164 | CONFIG_RADIO_ADAPTERS=y | ||
| 1165 | # CONFIG_USB_DSBR is not set | ||
| 1166 | # CONFIG_USB_SI470X is not set | ||
| 1167 | # CONFIG_USB_MR800 is not set | ||
| 1168 | # CONFIG_RADIO_TEA5764 is not set | ||
| 1169 | # CONFIG_DVB_DYNAMIC_MINORS is not set | ||
| 1170 | CONFIG_DVB_CAPTURE_DRIVERS=y | ||
| 1171 | # CONFIG_TTPCI_EEPROM is not set | ||
| 1172 | |||
| 1173 | # | ||
| 1174 | # Supported USB Adapters | ||
| 1175 | # | ||
| 1176 | CONFIG_DVB_USB=m | ||
| 1177 | # CONFIG_DVB_USB_DEBUG is not set | ||
| 1178 | CONFIG_DVB_USB_A800=m | ||
| 1179 | CONFIG_DVB_USB_DIBUSB_MB=m | ||
| 1180 | # CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set | ||
| 1181 | CONFIG_DVB_USB_DIBUSB_MC=m | ||
| 1182 | CONFIG_DVB_USB_DIB0700=m | ||
| 1183 | CONFIG_DVB_USB_UMT_010=m | ||
| 1184 | CONFIG_DVB_USB_CXUSB=m | ||
| 1185 | CONFIG_DVB_USB_M920X=m | ||
| 1186 | CONFIG_DVB_USB_GL861=m | ||
| 1187 | CONFIG_DVB_USB_AU6610=m | ||
| 1188 | CONFIG_DVB_USB_DIGITV=m | ||
| 1189 | CONFIG_DVB_USB_VP7045=m | ||
| 1190 | CONFIG_DVB_USB_VP702X=m | ||
| 1191 | CONFIG_DVB_USB_GP8PSK=m | ||
| 1192 | CONFIG_DVB_USB_NOVA_T_USB2=m | ||
| 1193 | CONFIG_DVB_USB_TTUSB2=m | ||
| 1194 | CONFIG_DVB_USB_DTT200U=m | ||
| 1195 | CONFIG_DVB_USB_OPERA1=m | ||
| 1196 | CONFIG_DVB_USB_AF9005=m | ||
| 1197 | CONFIG_DVB_USB_AF9005_REMOTE=m | ||
| 1198 | # CONFIG_DVB_USB_DW2102 is not set | ||
| 1199 | # CONFIG_DVB_USB_CINERGY_T2 is not set | ||
| 1200 | # CONFIG_DVB_USB_ANYSEE is not set | ||
| 1201 | # CONFIG_DVB_USB_DTV5100 is not set | ||
| 1202 | # CONFIG_DVB_USB_AF9015 is not set | ||
| 1203 | # CONFIG_DVB_SIANO_SMS1XXX is not set | ||
| 1204 | |||
| 1205 | # | ||
| 1206 | # Supported FlexCopII (B2C2) Adapters | ||
| 1207 | # | ||
| 1208 | # CONFIG_DVB_B2C2_FLEXCOP is not set | ||
| 1209 | |||
| 1210 | # | ||
| 1211 | # Supported DVB Frontends | ||
| 1212 | # | ||
| 1213 | |||
| 1214 | # | ||
| 1215 | # Customise DVB Frontends | ||
| 1216 | # | ||
| 1217 | # CONFIG_DVB_FE_CUSTOMISE is not set | ||
| 1218 | |||
| 1219 | # | ||
| 1220 | # Multistandard (satellite) frontends | ||
| 1221 | # | ||
| 1222 | # CONFIG_DVB_STB0899 is not set | ||
| 1223 | # CONFIG_DVB_STB6100 is not set | ||
| 1224 | |||
| 1225 | # | ||
| 1226 | # DVB-S (satellite) frontends | ||
| 1227 | # | ||
| 1228 | CONFIG_DVB_CX24110=m | ||
| 1229 | CONFIG_DVB_CX24123=m | ||
| 1230 | CONFIG_DVB_MT312=m | ||
| 1231 | CONFIG_DVB_S5H1420=m | ||
| 1232 | # CONFIG_DVB_STV0288 is not set | ||
| 1233 | # CONFIG_DVB_STB6000 is not set | ||
| 1234 | CONFIG_DVB_STV0299=m | ||
| 1235 | CONFIG_DVB_TDA8083=m | ||
| 1236 | CONFIG_DVB_TDA10086=m | ||
| 1237 | # CONFIG_DVB_TDA8261 is not set | ||
| 1238 | CONFIG_DVB_VES1X93=m | ||
| 1239 | CONFIG_DVB_TUNER_ITD1000=m | ||
| 1240 | # CONFIG_DVB_TUNER_CX24113 is not set | ||
| 1241 | CONFIG_DVB_TDA826X=m | ||
| 1242 | CONFIG_DVB_TUA6100=m | ||
| 1243 | # CONFIG_DVB_CX24116 is not set | ||
| 1244 | # CONFIG_DVB_SI21XX is not set | ||
| 1245 | |||
| 1246 | # | ||
| 1247 | # DVB-T (terrestrial) frontends | ||
| 1248 | # | ||
| 1249 | CONFIG_DVB_SP8870=m | ||
| 1250 | CONFIG_DVB_SP887X=m | ||
| 1251 | CONFIG_DVB_CX22700=m | ||
| 1252 | CONFIG_DVB_CX22702=m | ||
| 1253 | # CONFIG_DVB_DRX397XD is not set | ||
| 1254 | CONFIG_DVB_L64781=m | ||
| 1255 | CONFIG_DVB_TDA1004X=m | ||
| 1256 | CONFIG_DVB_NXT6000=m | ||
| 1257 | CONFIG_DVB_MT352=m | ||
| 1258 | CONFIG_DVB_ZL10353=m | ||
| 1259 | CONFIG_DVB_DIB3000MB=m | ||
| 1260 | CONFIG_DVB_DIB3000MC=m | ||
| 1261 | CONFIG_DVB_DIB7000M=m | ||
| 1262 | CONFIG_DVB_DIB7000P=m | ||
| 1263 | CONFIG_DVB_TDA10048=m | ||
| 1264 | |||
| 1265 | # | ||
| 1266 | # DVB-C (cable) frontends | ||
| 1267 | # | ||
| 1268 | CONFIG_DVB_VES1820=m | ||
| 1269 | CONFIG_DVB_TDA10021=m | ||
| 1270 | CONFIG_DVB_TDA10023=m | ||
| 1271 | CONFIG_DVB_STV0297=m | ||
| 1272 | |||
| 1273 | # | ||
| 1274 | # ATSC (North American/Korean Terrestrial/Cable DTV) frontends | ||
| 1275 | # | ||
| 1276 | CONFIG_DVB_NXT200X=m | ||
| 1277 | # CONFIG_DVB_OR51211 is not set | ||
| 1278 | # CONFIG_DVB_OR51132 is not set | ||
| 1279 | CONFIG_DVB_BCM3510=m | ||
| 1280 | CONFIG_DVB_LGDT330X=m | ||
| 1281 | # CONFIG_DVB_LGDT3304 is not set | ||
| 1282 | CONFIG_DVB_S5H1409=m | ||
| 1283 | CONFIG_DVB_AU8522=m | ||
| 1284 | CONFIG_DVB_S5H1411=m | ||
| 1285 | |||
| 1286 | # | ||
| 1287 | # ISDB-T (terrestrial) frontends | ||
| 1288 | # | ||
| 1289 | # CONFIG_DVB_S921 is not set | ||
| 1290 | |||
| 1291 | # | ||
| 1292 | # Digital terrestrial only tuners/PLL | ||
| 1293 | # | ||
| 1294 | CONFIG_DVB_PLL=m | ||
| 1295 | CONFIG_DVB_TUNER_DIB0070=m | ||
| 1296 | |||
| 1297 | # | ||
| 1298 | # SEC control devices for DVB-S | ||
| 1299 | # | ||
| 1300 | CONFIG_DVB_LNBP21=m | ||
| 1301 | # CONFIG_DVB_ISL6405 is not set | ||
| 1302 | CONFIG_DVB_ISL6421=m | ||
| 1303 | # CONFIG_DVB_LGS8GL5 is not set | ||
| 1304 | |||
| 1305 | # | ||
| 1306 | # Tools to develop new frontends | ||
| 1307 | # | ||
| 1308 | # CONFIG_DVB_DUMMY_FE is not set | ||
| 1309 | # CONFIG_DVB_AF9013 is not set | ||
| 1310 | # CONFIG_DAB is not set | ||
| 1311 | |||
| 1312 | # | ||
| 1313 | # Graphics support | ||
| 1314 | # | ||
| 1315 | # CONFIG_VGASTATE is not set | ||
| 1316 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1317 | # CONFIG_FB is not set | ||
| 1318 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 1319 | |||
| 1320 | # | ||
| 1321 | # Display device support | ||
| 1322 | # | ||
| 1323 | CONFIG_DISPLAY_SUPPORT=y | ||
| 1324 | |||
| 1325 | # | ||
| 1326 | # Display hardware drivers | ||
| 1327 | # | ||
| 1328 | |||
| 1329 | # | ||
| 1330 | # Console display driver support | ||
| 1331 | # | ||
| 1332 | # CONFIG_VGA_CONSOLE is not set | ||
| 1333 | CONFIG_DUMMY_CONSOLE=y | ||
| 1334 | CONFIG_SOUND=y | ||
| 1335 | CONFIG_SOUND_OSS_CORE=y | ||
| 1336 | CONFIG_SND=y | ||
| 1337 | CONFIG_SND_TIMER=y | ||
| 1338 | CONFIG_SND_PCM=y | ||
| 1339 | CONFIG_SND_HWDEP=y | ||
| 1340 | CONFIG_SND_RAWMIDI=y | ||
| 1341 | CONFIG_SND_SEQUENCER=m | ||
| 1342 | # CONFIG_SND_SEQ_DUMMY is not set | ||
| 1343 | CONFIG_SND_OSSEMUL=y | ||
| 1344 | CONFIG_SND_MIXER_OSS=y | ||
| 1345 | CONFIG_SND_PCM_OSS=y | ||
| 1346 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 1347 | CONFIG_SND_SEQUENCER_OSS=y | ||
| 1348 | # CONFIG_SND_HRTIMER is not set | ||
| 1349 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1350 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1351 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1352 | CONFIG_SND_VERBOSE_PRINTK=y | ||
| 1353 | CONFIG_SND_DEBUG=y | ||
| 1354 | # CONFIG_SND_DEBUG_VERBOSE is not set | ||
| 1355 | # CONFIG_SND_PCM_XRUN_DEBUG is not set | ||
| 1356 | CONFIG_SND_DRIVERS=y | ||
| 1357 | # CONFIG_SND_DUMMY is not set | ||
| 1358 | # CONFIG_SND_VIRMIDI is not set | ||
| 1359 | # CONFIG_SND_MTPAV is not set | ||
| 1360 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1361 | # CONFIG_SND_MPU401 is not set | ||
| 1362 | CONFIG_SND_ARM=y | ||
| 1363 | CONFIG_SND_SPI=y | ||
| 1364 | CONFIG_SND_USB=y | ||
| 1365 | CONFIG_SND_USB_AUDIO=y | ||
| 1366 | CONFIG_SND_USB_CAIAQ=m | ||
| 1367 | CONFIG_SND_USB_CAIAQ_INPUT=y | ||
| 1368 | CONFIG_SND_SOC=y | ||
| 1369 | CONFIG_SND_OMAP_SOC=y | ||
| 1370 | CONFIG_SND_OMAP_SOC_MCBSP=y | ||
| 1371 | # CONFIG_SND_OMAP_SOC_OVERO is not set | ||
| 1372 | CONFIG_SND_OMAP_SOC_SDP3430=y | ||
| 1373 | CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y | ||
| 1374 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1375 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1376 | CONFIG_SND_SOC_TWL4030=y | ||
| 1377 | # CONFIG_SOUND_PRIME is not set | ||
| 1378 | CONFIG_HID_SUPPORT=y | ||
| 1379 | CONFIG_HID=y | ||
| 1380 | CONFIG_HID_DEBUG=y | ||
| 1381 | # CONFIG_HIDRAW is not set | ||
| 1382 | |||
| 1383 | # | ||
| 1384 | # USB Input Devices | ||
| 1385 | # | ||
| 1386 | CONFIG_USB_HID=y | ||
| 1387 | # CONFIG_HID_PID is not set | ||
| 1388 | # CONFIG_USB_HIDDEV is not set | ||
| 1389 | |||
| 1390 | # | ||
| 1391 | # Special HID drivers | ||
| 1392 | # | ||
| 1393 | CONFIG_HID_COMPAT=y | ||
| 1394 | CONFIG_HID_A4TECH=y | ||
| 1395 | CONFIG_HID_APPLE=y | ||
| 1396 | CONFIG_HID_BELKIN=y | ||
| 1397 | CONFIG_HID_CHERRY=y | ||
| 1398 | CONFIG_HID_CHICONY=y | ||
| 1399 | CONFIG_HID_CYPRESS=y | ||
| 1400 | CONFIG_HID_EZKEY=y | ||
| 1401 | CONFIG_HID_GYRATION=y | ||
| 1402 | CONFIG_HID_LOGITECH=y | ||
| 1403 | # CONFIG_LOGITECH_FF is not set | ||
| 1404 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1405 | CONFIG_HID_MICROSOFT=y | ||
| 1406 | CONFIG_HID_MONTEREY=y | ||
| 1407 | # CONFIG_HID_NTRIG is not set | ||
| 1408 | CONFIG_HID_PANTHERLORD=y | ||
| 1409 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1410 | CONFIG_HID_PETALYNX=y | ||
| 1411 | CONFIG_HID_SAMSUNG=y | ||
| 1412 | CONFIG_HID_SONY=y | ||
| 1413 | CONFIG_HID_SUNPLUS=y | ||
| 1414 | # CONFIG_GREENASIA_FF is not set | ||
| 1415 | # CONFIG_HID_TOPSEED is not set | ||
| 1416 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1417 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1418 | CONFIG_USB_SUPPORT=y | ||
| 1419 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1420 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1421 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1422 | CONFIG_USB=y | ||
| 1423 | CONFIG_USB_DEBUG=y | ||
| 1424 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 1425 | |||
| 1426 | # | ||
| 1427 | # Miscellaneous USB options | ||
| 1428 | # | ||
| 1429 | CONFIG_USB_DEVICEFS=y | ||
| 1430 | CONFIG_USB_DEVICE_CLASS=y | ||
| 1431 | CONFIG_USB_DYNAMIC_MINORS=y | ||
| 1432 | CONFIG_USB_SUSPEND=y | ||
| 1433 | CONFIG_USB_OTG=y | ||
| 1434 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1435 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1436 | CONFIG_USB_MON=y | ||
| 1437 | # CONFIG_USB_WUSB is not set | ||
| 1438 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1439 | |||
| 1440 | # | ||
| 1441 | # USB Host Controller Drivers | ||
| 1442 | # | ||
| 1443 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1444 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1445 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1446 | # CONFIG_USB_OHCI_HCD is not set | ||
| 1447 | # CONFIG_USB_SL811_HCD is not set | ||
| 1448 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1449 | # CONFIG_USB_HWA_HCD is not set | ||
| 1450 | CONFIG_USB_MUSB_HDRC=y | ||
| 1451 | CONFIG_USB_MUSB_SOC=y | ||
| 1452 | |||
| 1453 | # | ||
| 1454 | # OMAP 343x high speed USB support | ||
| 1455 | # | ||
| 1456 | # CONFIG_USB_MUSB_HOST is not set | ||
| 1457 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
| 1458 | CONFIG_USB_MUSB_OTG=y | ||
| 1459 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 1460 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
| 1461 | CONFIG_MUSB_PIO_ONLY=y | ||
| 1462 | # CONFIG_USB_MUSB_DEBUG is not set | ||
| 1463 | |||
| 1464 | # | ||
| 1465 | # USB Device Class drivers | ||
| 1466 | # | ||
| 1467 | # CONFIG_USB_ACM is not set | ||
| 1468 | CONFIG_USB_PRINTER=y | ||
| 1469 | CONFIG_USB_WDM=y | ||
| 1470 | # CONFIG_USB_TMC is not set | ||
| 1471 | |||
| 1472 | # | ||
| 1473 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1474 | # | ||
| 1475 | |||
| 1476 | # | ||
| 1477 | # see USB_STORAGE Help for more information | ||
| 1478 | # | ||
| 1479 | CONFIG_USB_STORAGE=y | ||
| 1480 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1481 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1482 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1483 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1484 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1485 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1486 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1487 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1488 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1489 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1490 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1491 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1492 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1493 | |||
| 1494 | # | ||
| 1495 | # USB Imaging devices | ||
| 1496 | # | ||
| 1497 | # CONFIG_USB_MDC800 is not set | ||
| 1498 | # CONFIG_USB_MICROTEK is not set | ||
| 1499 | |||
| 1500 | # | ||
| 1501 | # USB port drivers | ||
| 1502 | # | ||
| 1503 | # CONFIG_USB_SERIAL is not set | ||
| 1504 | |||
| 1505 | # | ||
| 1506 | # USB Miscellaneous drivers | ||
| 1507 | # | ||
| 1508 | # CONFIG_USB_EMI62 is not set | ||
| 1509 | # CONFIG_USB_EMI26 is not set | ||
| 1510 | # CONFIG_USB_ADUTUX is not set | ||
| 1511 | # CONFIG_USB_SEVSEG is not set | ||
| 1512 | # CONFIG_USB_RIO500 is not set | ||
| 1513 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1514 | # CONFIG_USB_LCD is not set | ||
| 1515 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1516 | # CONFIG_USB_LED is not set | ||
| 1517 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1518 | # CONFIG_USB_CYTHERM is not set | ||
| 1519 | # CONFIG_USB_PHIDGET is not set | ||
| 1520 | # CONFIG_USB_IDMOUSE is not set | ||
| 1521 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1522 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1523 | # CONFIG_USB_LD is not set | ||
| 1524 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1525 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1526 | # CONFIG_USB_TEST is not set | ||
| 1527 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1528 | # CONFIG_USB_VST is not set | ||
| 1529 | CONFIG_USB_GADGET=y | ||
| 1530 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 1531 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 1532 | # CONFIG_USB_GADGET_DEBUG_FS is not set | ||
| 1533 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1534 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1535 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1536 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1537 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1538 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1539 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1540 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1541 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1542 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1543 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1544 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1545 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1546 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1547 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1548 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1549 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1550 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1551 | CONFIG_USB_GADGET_DUALSPEED=y | ||
| 1552 | # CONFIG_USB_ZERO is not set | ||
| 1553 | CONFIG_USB_ETH=y | ||
| 1554 | CONFIG_USB_ETH_RNDIS=y | ||
| 1555 | # CONFIG_USB_GADGETFS is not set | ||
| 1556 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 1557 | # CONFIG_USB_G_SERIAL is not set | ||
| 1558 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1559 | # CONFIG_USB_G_PRINTER is not set | ||
| 1560 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1561 | |||
| 1562 | # | ||
| 1563 | # OTG and related infrastructure | ||
| 1564 | # | ||
| 1565 | CONFIG_USB_OTG_UTILS=y | ||
| 1566 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1567 | # CONFIG_ISP1301_OMAP is not set | ||
| 1568 | CONFIG_TWL4030_USB=y | ||
| 1569 | CONFIG_MMC=y | ||
| 1570 | # CONFIG_MMC_DEBUG is not set | ||
| 1571 | CONFIG_MMC_UNSAFE_RESUME=y | ||
| 1572 | |||
| 1573 | # | ||
| 1574 | # MMC/SD/SDIO Card Drivers | ||
| 1575 | # | ||
| 1576 | CONFIG_MMC_BLOCK=y | ||
| 1577 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1578 | CONFIG_SDIO_UART=y | ||
| 1579 | # CONFIG_MMC_TEST is not set | ||
| 1580 | |||
| 1581 | # | ||
| 1582 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1583 | # | ||
| 1584 | # CONFIG_MMC_SDHCI is not set | ||
| 1585 | # CONFIG_MMC_OMAP is not set | ||
| 1586 | CONFIG_MMC_OMAP_HS=y | ||
| 1587 | # CONFIG_MMC_SPI is not set | ||
| 1588 | # CONFIG_MEMSTICK is not set | ||
| 1589 | # CONFIG_ACCESSIBILITY is not set | ||
| 1590 | CONFIG_NEW_LEDS=y | ||
| 1591 | CONFIG_LEDS_CLASS=y | ||
| 1592 | |||
| 1593 | # | ||
| 1594 | # LED drivers | ||
| 1595 | # | ||
| 1596 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1597 | CONFIG_LEDS_GPIO=y | ||
| 1598 | # CONFIG_LEDS_PCA955X is not set | ||
| 1599 | |||
| 1600 | # | ||
| 1601 | # LED Triggers | ||
| 1602 | # | ||
| 1603 | CONFIG_LEDS_TRIGGERS=y | ||
| 1604 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1605 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1606 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1607 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1608 | CONFIG_RTC_LIB=y | ||
| 1609 | CONFIG_RTC_CLASS=y | ||
| 1610 | CONFIG_RTC_HCTOSYS=y | ||
| 1611 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1612 | # CONFIG_RTC_DEBUG is not set | ||
| 1613 | |||
| 1614 | # | ||
| 1615 | # RTC interfaces | ||
| 1616 | # | ||
| 1617 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1618 | CONFIG_RTC_INTF_PROC=y | ||
| 1619 | CONFIG_RTC_INTF_DEV=y | ||
| 1620 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1621 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1622 | |||
| 1623 | # | ||
| 1624 | # I2C RTC drivers | ||
| 1625 | # | ||
| 1626 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1627 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1628 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1629 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1630 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1631 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1632 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1633 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1634 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1635 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1636 | CONFIG_RTC_DRV_TWL4030=y | ||
| 1637 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1638 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1639 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1640 | |||
| 1641 | # | ||
| 1642 | # SPI RTC drivers | ||
| 1643 | # | ||
| 1644 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1645 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1646 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1647 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1648 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1649 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1650 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1651 | |||
| 1652 | # | ||
| 1653 | # Platform RTC drivers | ||
| 1654 | # | ||
| 1655 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1656 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1657 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1658 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1659 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1660 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1661 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1662 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1663 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1664 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1665 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1666 | |||
| 1667 | # | ||
| 1668 | # on-CPU RTC drivers | ||
| 1669 | # | ||
| 1670 | # CONFIG_DMADEVICES is not set | ||
| 1671 | # CONFIG_REGULATOR is not set | ||
| 1672 | # CONFIG_UIO is not set | ||
| 1673 | # CONFIG_STAGING is not set | ||
| 1674 | |||
| 1675 | # | ||
| 1676 | # File systems | ||
| 1677 | # | ||
| 1678 | CONFIG_EXT2_FS=y | ||
| 1679 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1680 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1681 | CONFIG_EXT3_FS=y | ||
| 1682 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1683 | # CONFIG_EXT4_FS is not set | ||
| 1684 | CONFIG_JBD=y | ||
| 1685 | # CONFIG_JBD_DEBUG is not set | ||
| 1686 | # CONFIG_REISERFS_FS is not set | ||
| 1687 | # CONFIG_JFS_FS is not set | ||
| 1688 | CONFIG_FS_POSIX_ACL=y | ||
| 1689 | CONFIG_FILE_LOCKING=y | ||
| 1690 | CONFIG_XFS_FS=m | ||
| 1691 | # CONFIG_XFS_QUOTA is not set | ||
| 1692 | # CONFIG_XFS_POSIX_ACL is not set | ||
| 1693 | # CONFIG_XFS_RT is not set | ||
| 1694 | # CONFIG_XFS_DEBUG is not set | ||
| 1695 | # CONFIG_GFS2_FS is not set | ||
| 1696 | # CONFIG_OCFS2_FS is not set | ||
| 1697 | # CONFIG_BTRFS_FS is not set | ||
| 1698 | CONFIG_DNOTIFY=y | ||
| 1699 | CONFIG_INOTIFY=y | ||
| 1700 | CONFIG_INOTIFY_USER=y | ||
| 1701 | CONFIG_QUOTA=y | ||
| 1702 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
| 1703 | CONFIG_PRINT_QUOTA_WARNING=y | ||
| 1704 | CONFIG_QUOTA_TREE=y | ||
| 1705 | # CONFIG_QFMT_V1 is not set | ||
| 1706 | CONFIG_QFMT_V2=y | ||
| 1707 | CONFIG_QUOTACTL=y | ||
| 1708 | # CONFIG_AUTOFS_FS is not set | ||
| 1709 | # CONFIG_AUTOFS4_FS is not set | ||
| 1710 | CONFIG_FUSE_FS=m | ||
| 1711 | |||
| 1712 | # | ||
| 1713 | # CD-ROM/DVD Filesystems | ||
| 1714 | # | ||
| 1715 | CONFIG_ISO9660_FS=m | ||
| 1716 | CONFIG_JOLIET=y | ||
| 1717 | CONFIG_ZISOFS=y | ||
| 1718 | CONFIG_UDF_FS=m | ||
| 1719 | CONFIG_UDF_NLS=y | ||
| 1720 | |||
| 1721 | # | ||
| 1722 | # DOS/FAT/NT Filesystems | ||
| 1723 | # | ||
| 1724 | CONFIG_FAT_FS=y | ||
| 1725 | CONFIG_MSDOS_FS=y | ||
| 1726 | CONFIG_VFAT_FS=y | ||
| 1727 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1728 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1729 | # CONFIG_NTFS_FS is not set | ||
| 1730 | |||
| 1731 | # | ||
| 1732 | # Pseudo filesystems | ||
| 1733 | # | ||
| 1734 | CONFIG_PROC_FS=y | ||
| 1735 | CONFIG_PROC_SYSCTL=y | ||
| 1736 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1737 | CONFIG_SYSFS=y | ||
| 1738 | CONFIG_TMPFS=y | ||
| 1739 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1740 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1741 | # CONFIG_CONFIGFS_FS is not set | ||
| 1742 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1743 | # CONFIG_ADFS_FS is not set | ||
| 1744 | # CONFIG_AFFS_FS is not set | ||
| 1745 | # CONFIG_HFS_FS is not set | ||
| 1746 | # CONFIG_HFSPLUS_FS is not set | ||
| 1747 | # CONFIG_BEFS_FS is not set | ||
| 1748 | # CONFIG_BFS_FS is not set | ||
| 1749 | # CONFIG_EFS_FS is not set | ||
| 1750 | CONFIG_JFFS2_FS=y | ||
| 1751 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1752 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1753 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1754 | CONFIG_JFFS2_SUMMARY=y | ||
| 1755 | CONFIG_JFFS2_FS_XATTR=y | ||
| 1756 | CONFIG_JFFS2_FS_POSIX_ACL=y | ||
| 1757 | CONFIG_JFFS2_FS_SECURITY=y | ||
| 1758 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 1759 | CONFIG_JFFS2_ZLIB=y | ||
| 1760 | CONFIG_JFFS2_LZO=y | ||
| 1761 | CONFIG_JFFS2_RTIME=y | ||
| 1762 | CONFIG_JFFS2_RUBIN=y | ||
| 1763 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 1764 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 1765 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 1766 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 1767 | # CONFIG_CRAMFS is not set | ||
| 1768 | # CONFIG_SQUASHFS is not set | ||
| 1769 | # CONFIG_VXFS_FS is not set | ||
| 1770 | # CONFIG_MINIX_FS is not set | ||
| 1771 | # CONFIG_OMFS_FS is not set | ||
| 1772 | # CONFIG_HPFS_FS is not set | ||
| 1773 | # CONFIG_QNX4FS_FS is not set | ||
| 1774 | # CONFIG_ROMFS_FS is not set | ||
| 1775 | # CONFIG_SYSV_FS is not set | ||
| 1776 | # CONFIG_UFS_FS is not set | ||
| 1777 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1778 | CONFIG_NFS_FS=y | ||
| 1779 | CONFIG_NFS_V3=y | ||
| 1780 | # CONFIG_NFS_V3_ACL is not set | ||
| 1781 | CONFIG_NFS_V4=y | ||
| 1782 | CONFIG_ROOT_NFS=y | ||
| 1783 | # CONFIG_NFSD is not set | ||
| 1784 | CONFIG_LOCKD=y | ||
| 1785 | CONFIG_LOCKD_V4=y | ||
| 1786 | CONFIG_EXPORTFS=m | ||
| 1787 | CONFIG_NFS_COMMON=y | ||
| 1788 | CONFIG_SUNRPC=y | ||
| 1789 | CONFIG_SUNRPC_GSS=y | ||
| 1790 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1791 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 1792 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1793 | # CONFIG_SMB_FS is not set | ||
| 1794 | # CONFIG_CIFS is not set | ||
| 1795 | # CONFIG_NCP_FS is not set | ||
| 1796 | # CONFIG_CODA_FS is not set | ||
| 1797 | # CONFIG_AFS_FS is not set | ||
| 1798 | |||
| 1799 | # | ||
| 1800 | # Partition Types | ||
| 1801 | # | ||
| 1802 | CONFIG_PARTITION_ADVANCED=y | ||
| 1803 | # CONFIG_ACORN_PARTITION is not set | ||
| 1804 | # CONFIG_OSF_PARTITION is not set | ||
| 1805 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1806 | # CONFIG_ATARI_PARTITION is not set | ||
| 1807 | # CONFIG_MAC_PARTITION is not set | ||
| 1808 | CONFIG_MSDOS_PARTITION=y | ||
| 1809 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1810 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1811 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1812 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1813 | # CONFIG_LDM_PARTITION is not set | ||
| 1814 | # CONFIG_SGI_PARTITION is not set | ||
| 1815 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1816 | # CONFIG_SUN_PARTITION is not set | ||
| 1817 | # CONFIG_KARMA_PARTITION is not set | ||
| 1818 | # CONFIG_EFI_PARTITION is not set | ||
| 1819 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1820 | CONFIG_NLS=y | ||
| 1821 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1822 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1823 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1824 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1825 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1826 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1827 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1828 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1829 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1830 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1831 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1832 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1833 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1834 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1835 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1836 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1837 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1838 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1839 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1840 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1841 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1842 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1843 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1844 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1845 | # CONFIG_NLS_ASCII is not set | ||
| 1846 | CONFIG_NLS_ISO8859_1=y | ||
| 1847 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1848 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1849 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1850 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1851 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1852 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1853 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1854 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1855 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1856 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1857 | # CONFIG_NLS_KOI8_R is not set | ||
| 1858 | # CONFIG_NLS_KOI8_U is not set | ||
| 1859 | # CONFIG_NLS_UTF8 is not set | ||
| 1860 | # CONFIG_DLM is not set | ||
| 1861 | |||
| 1862 | # | ||
| 1863 | # Kernel hacking | ||
| 1864 | # | ||
| 1865 | # CONFIG_PRINTK_TIME is not set | ||
| 1866 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1867 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1868 | CONFIG_FRAME_WARN=1024 | ||
| 1869 | CONFIG_MAGIC_SYSRQ=y | ||
| 1870 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1871 | CONFIG_DEBUG_FS=y | ||
| 1872 | # CONFIG_HEADERS_CHECK is not set | ||
| 1873 | CONFIG_DEBUG_KERNEL=y | ||
| 1874 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1875 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1876 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1877 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1878 | CONFIG_SCHED_DEBUG=y | ||
| 1879 | CONFIG_SCHEDSTATS=y | ||
| 1880 | CONFIG_TIMER_STATS=y | ||
| 1881 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1882 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1883 | # CONFIG_SLUB_STATS is not set | ||
| 1884 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1885 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1886 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1887 | CONFIG_DEBUG_MUTEXES=y | ||
| 1888 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1889 | # CONFIG_PROVE_LOCKING is not set | ||
| 1890 | # CONFIG_LOCK_STAT is not set | ||
| 1891 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1892 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1893 | CONFIG_STACKTRACE=y | ||
| 1894 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1895 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1896 | # CONFIG_DEBUG_INFO is not set | ||
| 1897 | # CONFIG_DEBUG_VM is not set | ||
| 1898 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1899 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1900 | # CONFIG_DEBUG_LIST is not set | ||
| 1901 | # CONFIG_DEBUG_SG is not set | ||
| 1902 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1903 | CONFIG_FRAME_POINTER=y | ||
| 1904 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1905 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1906 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1907 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1908 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1909 | # CONFIG_FAULT_INJECTION is not set | ||
| 1910 | # CONFIG_LATENCYTOP is not set | ||
| 1911 | CONFIG_NOP_TRACER=y | ||
| 1912 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1913 | CONFIG_RING_BUFFER=y | ||
| 1914 | CONFIG_TRACING=y | ||
| 1915 | |||
| 1916 | # | ||
| 1917 | # Tracers | ||
| 1918 | # | ||
| 1919 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1920 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1921 | # CONFIG_SCHED_TRACER is not set | ||
| 1922 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1923 | # CONFIG_BOOT_TRACER is not set | ||
| 1924 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1925 | # CONFIG_STACK_TRACER is not set | ||
| 1926 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1927 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1928 | # CONFIG_SAMPLES is not set | ||
| 1929 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1930 | # CONFIG_KGDB is not set | ||
| 1931 | # CONFIG_DEBUG_USER is not set | ||
| 1932 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1933 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1934 | # CONFIG_DEBUG_LL is not set | ||
| 1935 | |||
| 1936 | # | ||
| 1937 | # Security options | ||
| 1938 | # | ||
| 1939 | # CONFIG_KEYS is not set | ||
| 1940 | # CONFIG_SECURITY is not set | ||
| 1941 | # CONFIG_SECURITYFS is not set | ||
| 1942 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1943 | CONFIG_XOR_BLOCKS=m | ||
| 1944 | CONFIG_ASYNC_CORE=m | ||
| 1945 | CONFIG_ASYNC_MEMCPY=m | ||
| 1946 | CONFIG_ASYNC_XOR=m | ||
| 1947 | CONFIG_CRYPTO=y | ||
| 1948 | |||
| 1949 | # | ||
| 1950 | # Crypto core or helper | ||
| 1951 | # | ||
| 1952 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1953 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1954 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1955 | CONFIG_CRYPTO_AEAD2=y | ||
| 1956 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1957 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1958 | CONFIG_CRYPTO_HASH=y | ||
| 1959 | CONFIG_CRYPTO_HASH2=y | ||
| 1960 | CONFIG_CRYPTO_RNG2=y | ||
| 1961 | CONFIG_CRYPTO_MANAGER=y | ||
| 1962 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1963 | CONFIG_CRYPTO_GF128MUL=m | ||
| 1964 | CONFIG_CRYPTO_NULL=m | ||
| 1965 | CONFIG_CRYPTO_CRYPTD=m | ||
| 1966 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1967 | CONFIG_CRYPTO_TEST=m | ||
| 1968 | |||
| 1969 | # | ||
| 1970 | # Authenticated Encryption with Associated Data | ||
| 1971 | # | ||
| 1972 | # CONFIG_CRYPTO_CCM is not set | ||
| 1973 | # CONFIG_CRYPTO_GCM is not set | ||
| 1974 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1975 | |||
| 1976 | # | ||
| 1977 | # Block modes | ||
| 1978 | # | ||
| 1979 | CONFIG_CRYPTO_CBC=y | ||
| 1980 | # CONFIG_CRYPTO_CTR is not set | ||
| 1981 | # CONFIG_CRYPTO_CTS is not set | ||
| 1982 | CONFIG_CRYPTO_ECB=y | ||
| 1983 | CONFIG_CRYPTO_LRW=m | ||
| 1984 | CONFIG_CRYPTO_PCBC=m | ||
| 1985 | # CONFIG_CRYPTO_XTS is not set | ||
| 1986 | |||
| 1987 | # | ||
| 1988 | # Hash modes | ||
| 1989 | # | ||
| 1990 | CONFIG_CRYPTO_HMAC=m | ||
| 1991 | CONFIG_CRYPTO_XCBC=m | ||
| 1992 | |||
| 1993 | # | ||
| 1994 | # Digest | ||
| 1995 | # | ||
| 1996 | CONFIG_CRYPTO_CRC32C=y | ||
| 1997 | CONFIG_CRYPTO_MD4=m | ||
| 1998 | CONFIG_CRYPTO_MD5=y | ||
| 1999 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 2000 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 2001 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 2002 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 2003 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 2004 | CONFIG_CRYPTO_SHA1=m | ||
| 2005 | CONFIG_CRYPTO_SHA256=m | ||
| 2006 | CONFIG_CRYPTO_SHA512=m | ||
| 2007 | CONFIG_CRYPTO_TGR192=m | ||
| 2008 | CONFIG_CRYPTO_WP512=m | ||
| 2009 | |||
| 2010 | # | ||
| 2011 | # Ciphers | ||
| 2012 | # | ||
| 2013 | CONFIG_CRYPTO_AES=y | ||
| 2014 | CONFIG_CRYPTO_ANUBIS=m | ||
| 2015 | CONFIG_CRYPTO_ARC4=y | ||
| 2016 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 2017 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 2018 | CONFIG_CRYPTO_CAST5=m | ||
| 2019 | CONFIG_CRYPTO_CAST6=m | ||
| 2020 | CONFIG_CRYPTO_DES=y | ||
| 2021 | CONFIG_CRYPTO_FCRYPT=m | ||
| 2022 | CONFIG_CRYPTO_KHAZAD=m | ||
| 2023 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 2024 | # CONFIG_CRYPTO_SEED is not set | ||
| 2025 | CONFIG_CRYPTO_SERPENT=m | ||
| 2026 | CONFIG_CRYPTO_TEA=m | ||
| 2027 | CONFIG_CRYPTO_TWOFISH=m | ||
| 2028 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 2029 | |||
| 2030 | # | ||
| 2031 | # Compression | ||
| 2032 | # | ||
| 2033 | CONFIG_CRYPTO_DEFLATE=m | ||
| 2034 | # CONFIG_CRYPTO_LZO is not set | ||
| 2035 | |||
| 2036 | # | ||
| 2037 | # Random Number Generation | ||
| 2038 | # | ||
| 2039 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 2040 | CONFIG_CRYPTO_HW=y | ||
| 2041 | |||
| 2042 | # | ||
| 2043 | # Library routines | ||
| 2044 | # | ||
| 2045 | CONFIG_BITREVERSE=y | ||
| 2046 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 2047 | CONFIG_CRC_CCITT=y | ||
| 2048 | CONFIG_CRC16=m | ||
| 2049 | CONFIG_CRC_T10DIF=y | ||
| 2050 | CONFIG_CRC_ITU_T=y | ||
| 2051 | CONFIG_CRC32=y | ||
| 2052 | CONFIG_CRC7=y | ||
| 2053 | CONFIG_LIBCRC32C=y | ||
| 2054 | CONFIG_ZLIB_INFLATE=y | ||
| 2055 | CONFIG_ZLIB_DEFLATE=y | ||
| 2056 | CONFIG_LZO_COMPRESS=y | ||
| 2057 | CONFIG_LZO_DECOMPRESS=y | ||
| 2058 | CONFIG_PLIST=y | ||
| 2059 | CONFIG_HAS_IOMEM=y | ||
| 2060 | CONFIG_HAS_IOPORT=y | ||
| 2061 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index a8ee6984a09e..020e6a8a9e5c 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig | |||
| @@ -481,7 +481,7 @@ CONFIG_MTD_NAND_IDS=y | |||
| 481 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 481 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 482 | # CONFIG_MTD_NAND_CAFE is not set | 482 | # CONFIG_MTD_NAND_CAFE is not set |
| 483 | # CONFIG_MTD_NAND_NANDSIM is not set | 483 | # CONFIG_MTD_NAND_NANDSIM is not set |
| 484 | # CONFIG_MTD_NAND_PLATFORM is not set | 484 | CONFIG_MTD_NAND_PLATFORM=y |
| 485 | # CONFIG_MTD_ALAUDA is not set | 485 | # CONFIG_MTD_ALAUDA is not set |
| 486 | CONFIG_MTD_NAND_ORION=y | 486 | CONFIG_MTD_NAND_ORION=y |
| 487 | # CONFIG_MTD_ONENAND is not set | 487 | # CONFIG_MTD_ONENAND is not set |
| @@ -1177,7 +1177,7 @@ CONFIG_RTC_DRV_S35390A=y | |||
| 1177 | # CONFIG_RTC_DRV_DS1553 is not set | 1177 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1178 | # CONFIG_RTC_DRV_DS1742 is not set | 1178 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1179 | # CONFIG_RTC_DRV_STK17TA8 is not set | 1179 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 1180 | # CONFIG_RTC_DRV_M48T86 is not set | 1180 | CONFIG_RTC_DRV_M48T86=y |
| 1181 | # CONFIG_RTC_DRV_M48T59 is not set | 1181 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1182 | # CONFIG_RTC_DRV_V3020 is not set | 1182 | # CONFIG_RTC_DRV_V3020 is not set |
| 1183 | 1183 | ||
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig index a6b47ea8e465..f2d2dda25949 100644 --- a/arch/arm/configs/pleb_defconfig +++ b/arch/arm/configs/pleb_defconfig | |||
| @@ -88,7 +88,6 @@ CONFIG_ARCH_SA1100=y | |||
| 88 | # CONFIG_SA1100_COLLIE is not set | 88 | # CONFIG_SA1100_COLLIE is not set |
| 89 | # CONFIG_SA1100_H3100 is not set | 89 | # CONFIG_SA1100_H3100 is not set |
| 90 | # CONFIG_SA1100_H3600 is not set | 90 | # CONFIG_SA1100_H3600 is not set |
| 91 | # CONFIG_SA1100_H3800 is not set | ||
| 92 | # CONFIG_SA1100_BADGE4 is not set | 91 | # CONFIG_SA1100_BADGE4 is not set |
| 93 | # CONFIG_SA1100_JORNADA720 is not set | 92 | # CONFIG_SA1100_JORNADA720 is not set |
| 94 | # CONFIG_SA1100_HACKKIT is not set | 93 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig new file mode 100644 index 000000000000..db5faeaec96c --- /dev/null +++ b/arch/arm/configs/pxa168_defconfig | |||
| @@ -0,0 +1,891 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc3 | ||
| 4 | # Fri Mar 20 13:43:13 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_LOCK_KERNEL=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | # CONFIG_IKCONFIG is not set | ||
| 55 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 56 | # CONFIG_GROUP_SCHED is not set | ||
| 57 | # CONFIG_CGROUPS is not set | ||
| 58 | CONFIG_SYSFS_DEPRECATED=y | ||
| 59 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 60 | # CONFIG_RELAY is not set | ||
| 61 | CONFIG_NAMESPACES=y | ||
| 62 | # CONFIG_UTS_NS is not set | ||
| 63 | # CONFIG_IPC_NS is not set | ||
| 64 | # CONFIG_USER_NS is not set | ||
| 65 | # CONFIG_PID_NS is not set | ||
| 66 | # CONFIG_NET_NS is not set | ||
| 67 | CONFIG_BLK_DEV_INITRD=y | ||
| 68 | CONFIG_INITRAMFS_SOURCE="" | ||
| 69 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 70 | CONFIG_SYSCTL=y | ||
| 71 | # CONFIG_EMBEDDED is not set | ||
| 72 | CONFIG_UID16=y | ||
| 73 | CONFIG_SYSCTL_SYSCALL=y | ||
| 74 | CONFIG_KALLSYMS=y | ||
| 75 | # CONFIG_KALLSYMS_ALL is not set | ||
| 76 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 77 | CONFIG_HOTPLUG=y | ||
| 78 | CONFIG_PRINTK=y | ||
| 79 | CONFIG_BUG=y | ||
| 80 | CONFIG_ELF_CORE=y | ||
| 81 | CONFIG_COMPAT_BRK=y | ||
| 82 | CONFIG_BASE_FULL=y | ||
| 83 | CONFIG_FUTEX=y | ||
| 84 | CONFIG_ANON_INODES=y | ||
| 85 | CONFIG_EPOLL=y | ||
| 86 | CONFIG_SIGNALFD=y | ||
| 87 | CONFIG_TIMERFD=y | ||
| 88 | CONFIG_EVENTFD=y | ||
| 89 | CONFIG_SHMEM=y | ||
| 90 | CONFIG_AIO=y | ||
| 91 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 92 | CONFIG_SLAB=y | ||
| 93 | # CONFIG_SLUB is not set | ||
| 94 | # CONFIG_SLOB is not set | ||
| 95 | # CONFIG_PROFILING is not set | ||
| 96 | CONFIG_HAVE_OPROFILE=y | ||
| 97 | # CONFIG_KPROBES is not set | ||
| 98 | CONFIG_HAVE_KPROBES=y | ||
| 99 | CONFIG_HAVE_KRETPROBES=y | ||
| 100 | CONFIG_HAVE_CLK=y | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 102 | CONFIG_SLABINFO=y | ||
| 103 | CONFIG_RT_MUTEXES=y | ||
| 104 | CONFIG_BASE_SMALL=0 | ||
| 105 | CONFIG_MODULES=y | ||
| 106 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 107 | CONFIG_MODULE_UNLOAD=y | ||
| 108 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 109 | # CONFIG_MODVERSIONS is not set | ||
| 110 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 111 | CONFIG_BLOCK=y | ||
| 112 | # CONFIG_LBD is not set | ||
| 113 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | CONFIG_IOSCHED_AS=y | ||
| 122 | CONFIG_IOSCHED_DEADLINE=y | ||
| 123 | CONFIG_IOSCHED_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_AS is not set | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | CONFIG_DEFAULT_CFQ=y | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 129 | # CONFIG_FREEZER is not set | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | CONFIG_ARCH_MMP=y | ||
| 163 | # CONFIG_ARCH_RPC is not set | ||
| 164 | # CONFIG_ARCH_SA1100 is not set | ||
| 165 | # CONFIG_ARCH_S3C2410 is not set | ||
| 166 | # CONFIG_ARCH_S3C64XX is not set | ||
| 167 | # CONFIG_ARCH_SHARK is not set | ||
| 168 | # CONFIG_ARCH_LH7A40X is not set | ||
| 169 | # CONFIG_ARCH_DAVINCI is not set | ||
| 170 | # CONFIG_ARCH_OMAP is not set | ||
| 171 | # CONFIG_ARCH_MSM is not set | ||
| 172 | # CONFIG_ARCH_W90X900 is not set | ||
| 173 | # CONFIG_MACH_TAVOREVB is not set | ||
| 174 | |||
| 175 | # | ||
| 176 | # Marvell PXA168/910 Implmentations | ||
| 177 | # | ||
| 178 | CONFIG_MACH_ASPENITE=y | ||
| 179 | CONFIG_MACH_ZYLONITE2=y | ||
| 180 | # CONFIG_MACH_TTC_DKB is not set | ||
| 181 | CONFIG_CPU_PXA168=y | ||
| 182 | CONFIG_PLAT_PXA=y | ||
| 183 | |||
| 184 | # | ||
| 185 | # Processor Type | ||
| 186 | # | ||
| 187 | CONFIG_CPU_32=y | ||
| 188 | CONFIG_CPU_MOHAWK=y | ||
| 189 | CONFIG_CPU_32v5=y | ||
| 190 | CONFIG_CPU_ABRT_EV5T=y | ||
| 191 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 192 | CONFIG_CPU_CACHE_VIVT=y | ||
| 193 | CONFIG_CPU_COPY_V4WB=y | ||
| 194 | CONFIG_CPU_TLB_V4WBI=y | ||
| 195 | CONFIG_CPU_CP15=y | ||
| 196 | CONFIG_CPU_CP15_MMU=y | ||
| 197 | |||
| 198 | # | ||
| 199 | # Processor Features | ||
| 200 | # | ||
| 201 | CONFIG_ARM_THUMB=y | ||
| 202 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 203 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 204 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 205 | # CONFIG_OUTER_CACHE is not set | ||
| 206 | CONFIG_IWMMXT=y | ||
| 207 | CONFIG_COMMON_CLKDEV=y | ||
| 208 | |||
| 209 | # | ||
| 210 | # Bus support | ||
| 211 | # | ||
| 212 | # CONFIG_PCI_SYSCALL is not set | ||
| 213 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 214 | # CONFIG_PCCARD is not set | ||
| 215 | |||
| 216 | # | ||
| 217 | # Kernel Features | ||
| 218 | # | ||
| 219 | CONFIG_TICK_ONESHOT=y | ||
| 220 | CONFIG_NO_HZ=y | ||
| 221 | CONFIG_HIGH_RES_TIMERS=y | ||
| 222 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 223 | CONFIG_VMSPLIT_3G=y | ||
| 224 | # CONFIG_VMSPLIT_2G is not set | ||
| 225 | # CONFIG_VMSPLIT_1G is not set | ||
| 226 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 227 | CONFIG_PREEMPT=y | ||
| 228 | CONFIG_HZ=100 | ||
| 229 | CONFIG_AEABI=y | ||
| 230 | CONFIG_OABI_COMPAT=y | ||
| 231 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 232 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 233 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 234 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 235 | CONFIG_FLATMEM_MANUAL=y | ||
| 236 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 237 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 238 | CONFIG_FLATMEM=y | ||
| 239 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 240 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 241 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 242 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 243 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 244 | CONFIG_VIRT_TO_BUS=y | ||
| 245 | CONFIG_UNEVICTABLE_LRU=y | ||
| 246 | CONFIG_ALIGNMENT_TRAP=y | ||
| 247 | |||
| 248 | # | ||
| 249 | # Boot options | ||
| 250 | # | ||
| 251 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 252 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 253 | CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M" | ||
| 254 | # CONFIG_XIP_KERNEL is not set | ||
| 255 | # CONFIG_KEXEC is not set | ||
| 256 | |||
| 257 | # | ||
| 258 | # CPU Power Management | ||
| 259 | # | ||
| 260 | # CONFIG_CPU_IDLE is not set | ||
| 261 | |||
| 262 | # | ||
| 263 | # Floating point emulation | ||
| 264 | # | ||
| 265 | |||
| 266 | # | ||
| 267 | # At least one emulation must be selected | ||
| 268 | # | ||
| 269 | CONFIG_FPE_NWFPE=y | ||
| 270 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 271 | # CONFIG_FPE_FASTFPE is not set | ||
| 272 | |||
| 273 | # | ||
| 274 | # Userspace binary formats | ||
| 275 | # | ||
| 276 | CONFIG_BINFMT_ELF=y | ||
| 277 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 278 | CONFIG_HAVE_AOUT=y | ||
| 279 | # CONFIG_BINFMT_AOUT is not set | ||
| 280 | # CONFIG_BINFMT_MISC is not set | ||
| 281 | |||
| 282 | # | ||
| 283 | # Power management options | ||
| 284 | # | ||
| 285 | # CONFIG_PM is not set | ||
| 286 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 287 | CONFIG_NET=y | ||
| 288 | |||
| 289 | # | ||
| 290 | # Networking options | ||
| 291 | # | ||
| 292 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 293 | CONFIG_PACKET=y | ||
| 294 | # CONFIG_PACKET_MMAP is not set | ||
| 295 | CONFIG_UNIX=y | ||
| 296 | CONFIG_XFRM=y | ||
| 297 | # CONFIG_XFRM_USER is not set | ||
| 298 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 299 | # CONFIG_XFRM_MIGRATE is not set | ||
| 300 | # CONFIG_XFRM_STATISTICS is not set | ||
| 301 | # CONFIG_NET_KEY is not set | ||
| 302 | CONFIG_INET=y | ||
| 303 | # CONFIG_IP_MULTICAST is not set | ||
| 304 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 305 | CONFIG_IP_FIB_HASH=y | ||
| 306 | CONFIG_IP_PNP=y | ||
| 307 | # CONFIG_IP_PNP_DHCP is not set | ||
| 308 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 309 | # CONFIG_IP_PNP_RARP is not set | ||
| 310 | # CONFIG_NET_IPIP is not set | ||
| 311 | # CONFIG_NET_IPGRE is not set | ||
| 312 | # CONFIG_ARPD is not set | ||
| 313 | # CONFIG_SYN_COOKIES is not set | ||
| 314 | # CONFIG_INET_AH is not set | ||
| 315 | # CONFIG_INET_ESP is not set | ||
| 316 | # CONFIG_INET_IPCOMP is not set | ||
| 317 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 318 | # CONFIG_INET_TUNNEL is not set | ||
| 319 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 320 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 321 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 322 | # CONFIG_INET_LRO is not set | ||
| 323 | CONFIG_INET_DIAG=y | ||
| 324 | CONFIG_INET_TCP_DIAG=y | ||
| 325 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 326 | CONFIG_TCP_CONG_CUBIC=y | ||
| 327 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 328 | # CONFIG_TCP_MD5SIG is not set | ||
| 329 | # CONFIG_IPV6 is not set | ||
| 330 | # CONFIG_NETWORK_SECMARK is not set | ||
| 331 | # CONFIG_NETFILTER is not set | ||
| 332 | # CONFIG_IP_DCCP is not set | ||
| 333 | # CONFIG_IP_SCTP is not set | ||
| 334 | # CONFIG_TIPC is not set | ||
| 335 | # CONFIG_ATM is not set | ||
| 336 | # CONFIG_BRIDGE is not set | ||
| 337 | # CONFIG_NET_DSA is not set | ||
| 338 | # CONFIG_VLAN_8021Q is not set | ||
| 339 | # CONFIG_DECNET is not set | ||
| 340 | # CONFIG_LLC2 is not set | ||
| 341 | # CONFIG_IPX is not set | ||
| 342 | # CONFIG_ATALK is not set | ||
| 343 | # CONFIG_X25 is not set | ||
| 344 | # CONFIG_LAPB is not set | ||
| 345 | # CONFIG_ECONET is not set | ||
| 346 | # CONFIG_WAN_ROUTER is not set | ||
| 347 | # CONFIG_NET_SCHED is not set | ||
| 348 | # CONFIG_DCB is not set | ||
| 349 | |||
| 350 | # | ||
| 351 | # Network testing | ||
| 352 | # | ||
| 353 | # CONFIG_NET_PKTGEN is not set | ||
| 354 | # CONFIG_HAMRADIO is not set | ||
| 355 | # CONFIG_CAN is not set | ||
| 356 | # CONFIG_IRDA is not set | ||
| 357 | # CONFIG_BT is not set | ||
| 358 | # CONFIG_AF_RXRPC is not set | ||
| 359 | # CONFIG_PHONET is not set | ||
| 360 | CONFIG_WIRELESS=y | ||
| 361 | # CONFIG_CFG80211 is not set | ||
| 362 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 363 | # CONFIG_WIRELESS_EXT is not set | ||
| 364 | # CONFIG_LIB80211 is not set | ||
| 365 | # CONFIG_MAC80211 is not set | ||
| 366 | # CONFIG_WIMAX is not set | ||
| 367 | # CONFIG_RFKILL is not set | ||
| 368 | # CONFIG_NET_9P is not set | ||
| 369 | |||
| 370 | # | ||
| 371 | # Device Drivers | ||
| 372 | # | ||
| 373 | |||
| 374 | # | ||
| 375 | # Generic Driver Options | ||
| 376 | # | ||
| 377 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 378 | # CONFIG_STANDALONE is not set | ||
| 379 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 380 | CONFIG_FW_LOADER=y | ||
| 381 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 382 | CONFIG_EXTRA_FIRMWARE="" | ||
| 383 | # CONFIG_DEBUG_DRIVER is not set | ||
| 384 | # CONFIG_DEBUG_DEVRES is not set | ||
| 385 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 386 | # CONFIG_CONNECTOR is not set | ||
| 387 | # CONFIG_MTD is not set | ||
| 388 | # CONFIG_PARPORT is not set | ||
| 389 | # CONFIG_BLK_DEV is not set | ||
| 390 | # CONFIG_MISC_DEVICES is not set | ||
| 391 | CONFIG_HAVE_IDE=y | ||
| 392 | # CONFIG_IDE is not set | ||
| 393 | |||
| 394 | # | ||
| 395 | # SCSI device support | ||
| 396 | # | ||
| 397 | # CONFIG_RAID_ATTRS is not set | ||
| 398 | # CONFIG_SCSI is not set | ||
| 399 | # CONFIG_SCSI_DMA is not set | ||
| 400 | # CONFIG_SCSI_NETLINK is not set | ||
| 401 | # CONFIG_ATA is not set | ||
| 402 | # CONFIG_MD is not set | ||
| 403 | CONFIG_NETDEVICES=y | ||
| 404 | # CONFIG_DUMMY is not set | ||
| 405 | # CONFIG_BONDING is not set | ||
| 406 | # CONFIG_MACVLAN is not set | ||
| 407 | # CONFIG_EQUALIZER is not set | ||
| 408 | # CONFIG_TUN is not set | ||
| 409 | # CONFIG_VETH is not set | ||
| 410 | # CONFIG_PHYLIB is not set | ||
| 411 | CONFIG_NET_ETHERNET=y | ||
| 412 | CONFIG_MII=y | ||
| 413 | # CONFIG_AX88796 is not set | ||
| 414 | CONFIG_SMC91X=y | ||
| 415 | # CONFIG_DM9000 is not set | ||
| 416 | # CONFIG_SMC911X is not set | ||
| 417 | # CONFIG_SMSC911X is not set | ||
| 418 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 419 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 420 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 421 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 422 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 423 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 424 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 425 | # CONFIG_B44 is not set | ||
| 426 | # CONFIG_NETDEV_1000 is not set | ||
| 427 | # CONFIG_NETDEV_10000 is not set | ||
| 428 | |||
| 429 | # | ||
| 430 | # Wireless LAN | ||
| 431 | # | ||
| 432 | # CONFIG_WLAN_PRE80211 is not set | ||
| 433 | # CONFIG_WLAN_80211 is not set | ||
| 434 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 435 | |||
| 436 | # | ||
| 437 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 438 | # | ||
| 439 | # CONFIG_WAN is not set | ||
| 440 | # CONFIG_PPP is not set | ||
| 441 | # CONFIG_SLIP is not set | ||
| 442 | # CONFIG_NETCONSOLE is not set | ||
| 443 | # CONFIG_NETPOLL is not set | ||
| 444 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 445 | # CONFIG_ISDN is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Input device support | ||
| 449 | # | ||
| 450 | CONFIG_INPUT=y | ||
| 451 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 452 | # CONFIG_INPUT_POLLDEV is not set | ||
| 453 | |||
| 454 | # | ||
| 455 | # Userland interfaces | ||
| 456 | # | ||
| 457 | CONFIG_INPUT_MOUSEDEV=y | ||
| 458 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 459 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 460 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 461 | # CONFIG_INPUT_JOYDEV is not set | ||
| 462 | # CONFIG_INPUT_EVDEV is not set | ||
| 463 | # CONFIG_INPUT_EVBUG is not set | ||
| 464 | |||
| 465 | # | ||
| 466 | # Input Device Drivers | ||
| 467 | # | ||
| 468 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 469 | # CONFIG_INPUT_MOUSE is not set | ||
| 470 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 471 | # CONFIG_INPUT_TABLET is not set | ||
| 472 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 473 | # CONFIG_INPUT_MISC is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # Hardware I/O ports | ||
| 477 | # | ||
| 478 | # CONFIG_SERIO is not set | ||
| 479 | # CONFIG_GAMEPORT is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # Character devices | ||
| 483 | # | ||
| 484 | CONFIG_VT=y | ||
| 485 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 486 | CONFIG_VT_CONSOLE=y | ||
| 487 | CONFIG_HW_CONSOLE=y | ||
| 488 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 489 | CONFIG_DEVKMEM=y | ||
| 490 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 491 | |||
| 492 | # | ||
| 493 | # Serial drivers | ||
| 494 | # | ||
| 495 | # CONFIG_SERIAL_8250 is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # Non-8250 serial port support | ||
| 499 | # | ||
| 500 | CONFIG_SERIAL_PXA=y | ||
| 501 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 502 | CONFIG_SERIAL_CORE=y | ||
| 503 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 504 | CONFIG_UNIX98_PTYS=y | ||
| 505 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 506 | # CONFIG_LEGACY_PTYS is not set | ||
| 507 | # CONFIG_IPMI_HANDLER is not set | ||
| 508 | # CONFIG_HW_RANDOM is not set | ||
| 509 | # CONFIG_R3964 is not set | ||
| 510 | # CONFIG_RAW_DRIVER is not set | ||
| 511 | # CONFIG_TCG_TPM is not set | ||
| 512 | # CONFIG_I2C is not set | ||
| 513 | # CONFIG_SPI is not set | ||
| 514 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 515 | CONFIG_GPIOLIB=y | ||
| 516 | # CONFIG_DEBUG_GPIO is not set | ||
| 517 | # CONFIG_GPIO_SYSFS is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # Memory mapped GPIO expanders: | ||
| 521 | # | ||
| 522 | |||
| 523 | # | ||
| 524 | # I2C GPIO expanders: | ||
| 525 | # | ||
| 526 | |||
| 527 | # | ||
| 528 | # PCI GPIO expanders: | ||
| 529 | # | ||
| 530 | |||
| 531 | # | ||
| 532 | # SPI GPIO expanders: | ||
| 533 | # | ||
| 534 | # CONFIG_W1 is not set | ||
| 535 | # CONFIG_POWER_SUPPLY is not set | ||
| 536 | # CONFIG_HWMON is not set | ||
| 537 | # CONFIG_THERMAL is not set | ||
| 538 | # CONFIG_THERMAL_HWMON is not set | ||
| 539 | # CONFIG_WATCHDOG is not set | ||
| 540 | CONFIG_SSB_POSSIBLE=y | ||
| 541 | |||
| 542 | # | ||
| 543 | # Sonics Silicon Backplane | ||
| 544 | # | ||
| 545 | # CONFIG_SSB is not set | ||
| 546 | |||
| 547 | # | ||
| 548 | # Multifunction device drivers | ||
| 549 | # | ||
| 550 | # CONFIG_MFD_CORE is not set | ||
| 551 | # CONFIG_MFD_SM501 is not set | ||
| 552 | # CONFIG_MFD_ASIC3 is not set | ||
| 553 | # CONFIG_HTC_EGPIO is not set | ||
| 554 | # CONFIG_HTC_PASIC3 is not set | ||
| 555 | # CONFIG_MFD_TMIO is not set | ||
| 556 | # CONFIG_MFD_T7L66XB is not set | ||
| 557 | # CONFIG_MFD_TC6387XB is not set | ||
| 558 | # CONFIG_MFD_TC6393XB is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Multimedia devices | ||
| 562 | # | ||
| 563 | |||
| 564 | # | ||
| 565 | # Multimedia core support | ||
| 566 | # | ||
| 567 | # CONFIG_VIDEO_DEV is not set | ||
| 568 | # CONFIG_DVB_CORE is not set | ||
| 569 | # CONFIG_VIDEO_MEDIA is not set | ||
| 570 | |||
| 571 | # | ||
| 572 | # Multimedia drivers | ||
| 573 | # | ||
| 574 | # CONFIG_DAB is not set | ||
| 575 | |||
| 576 | # | ||
| 577 | # Graphics support | ||
| 578 | # | ||
| 579 | # CONFIG_VGASTATE is not set | ||
| 580 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 581 | # CONFIG_FB is not set | ||
| 582 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # Display device support | ||
| 586 | # | ||
| 587 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 588 | |||
| 589 | # | ||
| 590 | # Console display driver support | ||
| 591 | # | ||
| 592 | # CONFIG_VGA_CONSOLE is not set | ||
| 593 | CONFIG_DUMMY_CONSOLE=y | ||
| 594 | # CONFIG_SOUND is not set | ||
| 595 | # CONFIG_HID_SUPPORT is not set | ||
| 596 | # CONFIG_USB_SUPPORT is not set | ||
| 597 | # CONFIG_MMC is not set | ||
| 598 | # CONFIG_MEMSTICK is not set | ||
| 599 | # CONFIG_ACCESSIBILITY is not set | ||
| 600 | # CONFIG_NEW_LEDS is not set | ||
| 601 | CONFIG_RTC_LIB=y | ||
| 602 | # CONFIG_RTC_CLASS is not set | ||
| 603 | # CONFIG_DMADEVICES is not set | ||
| 604 | # CONFIG_REGULATOR is not set | ||
| 605 | # CONFIG_UIO is not set | ||
| 606 | # CONFIG_STAGING is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # File systems | ||
| 610 | # | ||
| 611 | # CONFIG_EXT2_FS is not set | ||
| 612 | # CONFIG_EXT3_FS is not set | ||
| 613 | # CONFIG_EXT4_FS is not set | ||
| 614 | # CONFIG_REISERFS_FS is not set | ||
| 615 | # CONFIG_JFS_FS is not set | ||
| 616 | CONFIG_FS_POSIX_ACL=y | ||
| 617 | CONFIG_FILE_LOCKING=y | ||
| 618 | # CONFIG_XFS_FS is not set | ||
| 619 | # CONFIG_OCFS2_FS is not set | ||
| 620 | # CONFIG_BTRFS_FS is not set | ||
| 621 | CONFIG_DNOTIFY=y | ||
| 622 | CONFIG_INOTIFY=y | ||
| 623 | CONFIG_INOTIFY_USER=y | ||
| 624 | # CONFIG_QUOTA is not set | ||
| 625 | # CONFIG_AUTOFS_FS is not set | ||
| 626 | # CONFIG_AUTOFS4_FS is not set | ||
| 627 | # CONFIG_FUSE_FS is not set | ||
| 628 | CONFIG_GENERIC_ACL=y | ||
| 629 | |||
| 630 | # | ||
| 631 | # CD-ROM/DVD Filesystems | ||
| 632 | # | ||
| 633 | # CONFIG_ISO9660_FS is not set | ||
| 634 | # CONFIG_UDF_FS is not set | ||
| 635 | |||
| 636 | # | ||
| 637 | # DOS/FAT/NT Filesystems | ||
| 638 | # | ||
| 639 | # CONFIG_MSDOS_FS is not set | ||
| 640 | # CONFIG_VFAT_FS is not set | ||
| 641 | # CONFIG_NTFS_FS is not set | ||
| 642 | |||
| 643 | # | ||
| 644 | # Pseudo filesystems | ||
| 645 | # | ||
| 646 | CONFIG_PROC_FS=y | ||
| 647 | CONFIG_PROC_SYSCTL=y | ||
| 648 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 649 | CONFIG_SYSFS=y | ||
| 650 | CONFIG_TMPFS=y | ||
| 651 | CONFIG_TMPFS_POSIX_ACL=y | ||
| 652 | # CONFIG_HUGETLB_PAGE is not set | ||
| 653 | # CONFIG_CONFIGFS_FS is not set | ||
| 654 | CONFIG_MISC_FILESYSTEMS=y | ||
| 655 | # CONFIG_ADFS_FS is not set | ||
| 656 | # CONFIG_AFFS_FS is not set | ||
| 657 | # CONFIG_HFS_FS is not set | ||
| 658 | # CONFIG_HFSPLUS_FS is not set | ||
| 659 | # CONFIG_BEFS_FS is not set | ||
| 660 | # CONFIG_BFS_FS is not set | ||
| 661 | # CONFIG_EFS_FS is not set | ||
| 662 | CONFIG_CRAMFS=y | ||
| 663 | # CONFIG_SQUASHFS is not set | ||
| 664 | # CONFIG_VXFS_FS is not set | ||
| 665 | # CONFIG_MINIX_FS is not set | ||
| 666 | # CONFIG_OMFS_FS is not set | ||
| 667 | # CONFIG_HPFS_FS is not set | ||
| 668 | # CONFIG_QNX4FS_FS is not set | ||
| 669 | # CONFIG_ROMFS_FS is not set | ||
| 670 | # CONFIG_SYSV_FS is not set | ||
| 671 | # CONFIG_UFS_FS is not set | ||
| 672 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 673 | CONFIG_NFS_FS=y | ||
| 674 | CONFIG_NFS_V3=y | ||
| 675 | CONFIG_NFS_V3_ACL=y | ||
| 676 | CONFIG_NFS_V4=y | ||
| 677 | CONFIG_ROOT_NFS=y | ||
| 678 | # CONFIG_NFSD is not set | ||
| 679 | CONFIG_LOCKD=y | ||
| 680 | CONFIG_LOCKD_V4=y | ||
| 681 | CONFIG_NFS_ACL_SUPPORT=y | ||
| 682 | CONFIG_NFS_COMMON=y | ||
| 683 | CONFIG_SUNRPC=y | ||
| 684 | CONFIG_SUNRPC_GSS=y | ||
| 685 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 686 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 687 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 688 | # CONFIG_SMB_FS is not set | ||
| 689 | # CONFIG_CIFS is not set | ||
| 690 | # CONFIG_NCP_FS is not set | ||
| 691 | # CONFIG_CODA_FS is not set | ||
| 692 | # CONFIG_AFS_FS is not set | ||
| 693 | |||
| 694 | # | ||
| 695 | # Partition Types | ||
| 696 | # | ||
| 697 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 698 | CONFIG_MSDOS_PARTITION=y | ||
| 699 | # CONFIG_NLS is not set | ||
| 700 | # CONFIG_DLM is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # Kernel hacking | ||
| 704 | # | ||
| 705 | CONFIG_PRINTK_TIME=y | ||
| 706 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 707 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 708 | CONFIG_FRAME_WARN=1024 | ||
| 709 | CONFIG_MAGIC_SYSRQ=y | ||
| 710 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 711 | # CONFIG_DEBUG_FS is not set | ||
| 712 | # CONFIG_HEADERS_CHECK is not set | ||
| 713 | CONFIG_DEBUG_KERNEL=y | ||
| 714 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 715 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 716 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 717 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 718 | CONFIG_SCHED_DEBUG=y | ||
| 719 | # CONFIG_SCHEDSTATS is not set | ||
| 720 | # CONFIG_TIMER_STATS is not set | ||
| 721 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 722 | # CONFIG_DEBUG_SLAB is not set | ||
| 723 | # CONFIG_DEBUG_PREEMPT is not set | ||
| 724 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 725 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 726 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 727 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 728 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 729 | # CONFIG_PROVE_LOCKING is not set | ||
| 730 | # CONFIG_LOCK_STAT is not set | ||
| 731 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 732 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 733 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 734 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 735 | CONFIG_DEBUG_INFO=y | ||
| 736 | # CONFIG_DEBUG_VM is not set | ||
| 737 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 738 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 739 | # CONFIG_DEBUG_LIST is not set | ||
| 740 | # CONFIG_DEBUG_SG is not set | ||
| 741 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 742 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 743 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 744 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 745 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 746 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 747 | # CONFIG_FAULT_INJECTION is not set | ||
| 748 | # CONFIG_LATENCYTOP is not set | ||
| 749 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 750 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 751 | |||
| 752 | # | ||
| 753 | # Tracers | ||
| 754 | # | ||
| 755 | # CONFIG_FUNCTION_TRACER is not set | ||
| 756 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 757 | # CONFIG_PREEMPT_TRACER is not set | ||
| 758 | # CONFIG_SCHED_TRACER is not set | ||
| 759 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 760 | # CONFIG_BOOT_TRACER is not set | ||
| 761 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 762 | # CONFIG_STACK_TRACER is not set | ||
| 763 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 764 | # CONFIG_SAMPLES is not set | ||
| 765 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 766 | # CONFIG_KGDB is not set | ||
| 767 | CONFIG_ARM_UNWIND=y | ||
| 768 | CONFIG_DEBUG_USER=y | ||
| 769 | CONFIG_DEBUG_ERRORS=y | ||
| 770 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 771 | CONFIG_DEBUG_LL=y | ||
| 772 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 773 | |||
| 774 | # | ||
| 775 | # Security options | ||
| 776 | # | ||
| 777 | # CONFIG_KEYS is not set | ||
| 778 | # CONFIG_SECURITY is not set | ||
| 779 | # CONFIG_SECURITYFS is not set | ||
| 780 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 781 | CONFIG_CRYPTO=y | ||
| 782 | |||
| 783 | # | ||
| 784 | # Crypto core or helper | ||
| 785 | # | ||
| 786 | # CONFIG_CRYPTO_FIPS is not set | ||
| 787 | CONFIG_CRYPTO_ALGAPI=y | ||
| 788 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 789 | CONFIG_CRYPTO_AEAD2=y | ||
| 790 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 791 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 792 | CONFIG_CRYPTO_HASH=y | ||
| 793 | CONFIG_CRYPTO_HASH2=y | ||
| 794 | CONFIG_CRYPTO_RNG2=y | ||
| 795 | CONFIG_CRYPTO_MANAGER=y | ||
| 796 | CONFIG_CRYPTO_MANAGER2=y | ||
| 797 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 798 | # CONFIG_CRYPTO_NULL is not set | ||
| 799 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 800 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 801 | # CONFIG_CRYPTO_TEST is not set | ||
| 802 | |||
| 803 | # | ||
| 804 | # Authenticated Encryption with Associated Data | ||
| 805 | # | ||
| 806 | # CONFIG_CRYPTO_CCM is not set | ||
| 807 | # CONFIG_CRYPTO_GCM is not set | ||
| 808 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Block modes | ||
| 812 | # | ||
| 813 | CONFIG_CRYPTO_CBC=y | ||
| 814 | # CONFIG_CRYPTO_CTR is not set | ||
| 815 | # CONFIG_CRYPTO_CTS is not set | ||
| 816 | # CONFIG_CRYPTO_ECB is not set | ||
| 817 | # CONFIG_CRYPTO_LRW is not set | ||
| 818 | # CONFIG_CRYPTO_PCBC is not set | ||
| 819 | # CONFIG_CRYPTO_XTS is not set | ||
| 820 | |||
| 821 | # | ||
| 822 | # Hash modes | ||
| 823 | # | ||
| 824 | # CONFIG_CRYPTO_HMAC is not set | ||
| 825 | # CONFIG_CRYPTO_XCBC is not set | ||
| 826 | |||
| 827 | # | ||
| 828 | # Digest | ||
| 829 | # | ||
| 830 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 831 | # CONFIG_CRYPTO_MD4 is not set | ||
| 832 | CONFIG_CRYPTO_MD5=y | ||
| 833 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 834 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 835 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 836 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 837 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 838 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 839 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 840 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 841 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 842 | # CONFIG_CRYPTO_WP512 is not set | ||
| 843 | |||
| 844 | # | ||
| 845 | # Ciphers | ||
| 846 | # | ||
| 847 | # CONFIG_CRYPTO_AES is not set | ||
| 848 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 849 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 850 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 851 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 852 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 853 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 854 | CONFIG_CRYPTO_DES=y | ||
| 855 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 856 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 857 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 858 | # CONFIG_CRYPTO_SEED is not set | ||
| 859 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 860 | # CONFIG_CRYPTO_TEA is not set | ||
| 861 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # Compression | ||
| 865 | # | ||
| 866 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 867 | # CONFIG_CRYPTO_LZO is not set | ||
| 868 | |||
| 869 | # | ||
| 870 | # Random Number Generation | ||
| 871 | # | ||
| 872 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 873 | CONFIG_CRYPTO_HW=y | ||
| 874 | |||
| 875 | # | ||
| 876 | # Library routines | ||
| 877 | # | ||
| 878 | CONFIG_BITREVERSE=y | ||
| 879 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 880 | CONFIG_CRC_CCITT=y | ||
| 881 | # CONFIG_CRC16 is not set | ||
| 882 | # CONFIG_CRC_T10DIF is not set | ||
| 883 | # CONFIG_CRC_ITU_T is not set | ||
| 884 | CONFIG_CRC32=y | ||
| 885 | # CONFIG_CRC7 is not set | ||
| 886 | # CONFIG_LIBCRC32C is not set | ||
| 887 | CONFIG_ZLIB_INFLATE=y | ||
| 888 | CONFIG_PLIST=y | ||
| 889 | CONFIG_HAS_IOMEM=y | ||
| 890 | CONFIG_HAS_IOPORT=y | ||
| 891 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig new file mode 100644 index 000000000000..8c7e299f1d66 --- /dev/null +++ b/arch/arm/configs/pxa910_defconfig | |||
| @@ -0,0 +1,891 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc3 | ||
| 4 | # Fri Mar 20 13:45:12 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_LOCK_KERNEL=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | # CONFIG_IKCONFIG is not set | ||
| 55 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 56 | # CONFIG_GROUP_SCHED is not set | ||
| 57 | # CONFIG_CGROUPS is not set | ||
| 58 | CONFIG_SYSFS_DEPRECATED=y | ||
| 59 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 60 | # CONFIG_RELAY is not set | ||
| 61 | CONFIG_NAMESPACES=y | ||
| 62 | # CONFIG_UTS_NS is not set | ||
| 63 | # CONFIG_IPC_NS is not set | ||
| 64 | # CONFIG_USER_NS is not set | ||
| 65 | # CONFIG_PID_NS is not set | ||
| 66 | # CONFIG_NET_NS is not set | ||
| 67 | CONFIG_BLK_DEV_INITRD=y | ||
| 68 | CONFIG_INITRAMFS_SOURCE="" | ||
| 69 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 70 | CONFIG_SYSCTL=y | ||
| 71 | # CONFIG_EMBEDDED is not set | ||
| 72 | CONFIG_UID16=y | ||
| 73 | CONFIG_SYSCTL_SYSCALL=y | ||
| 74 | CONFIG_KALLSYMS=y | ||
| 75 | # CONFIG_KALLSYMS_ALL is not set | ||
| 76 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 77 | CONFIG_HOTPLUG=y | ||
| 78 | CONFIG_PRINTK=y | ||
| 79 | CONFIG_BUG=y | ||
| 80 | CONFIG_ELF_CORE=y | ||
| 81 | CONFIG_COMPAT_BRK=y | ||
| 82 | CONFIG_BASE_FULL=y | ||
| 83 | CONFIG_FUTEX=y | ||
| 84 | CONFIG_ANON_INODES=y | ||
| 85 | CONFIG_EPOLL=y | ||
| 86 | CONFIG_SIGNALFD=y | ||
| 87 | CONFIG_TIMERFD=y | ||
| 88 | CONFIG_EVENTFD=y | ||
| 89 | CONFIG_SHMEM=y | ||
| 90 | CONFIG_AIO=y | ||
| 91 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 92 | CONFIG_SLAB=y | ||
| 93 | # CONFIG_SLUB is not set | ||
| 94 | # CONFIG_SLOB is not set | ||
| 95 | # CONFIG_PROFILING is not set | ||
| 96 | CONFIG_HAVE_OPROFILE=y | ||
| 97 | # CONFIG_KPROBES is not set | ||
| 98 | CONFIG_HAVE_KPROBES=y | ||
| 99 | CONFIG_HAVE_KRETPROBES=y | ||
| 100 | CONFIG_HAVE_CLK=y | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 102 | CONFIG_SLABINFO=y | ||
| 103 | CONFIG_RT_MUTEXES=y | ||
| 104 | CONFIG_BASE_SMALL=0 | ||
| 105 | CONFIG_MODULES=y | ||
| 106 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 107 | CONFIG_MODULE_UNLOAD=y | ||
| 108 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 109 | # CONFIG_MODVERSIONS is not set | ||
| 110 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 111 | CONFIG_BLOCK=y | ||
| 112 | # CONFIG_LBD is not set | ||
| 113 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | CONFIG_IOSCHED_AS=y | ||
| 122 | CONFIG_IOSCHED_DEADLINE=y | ||
| 123 | CONFIG_IOSCHED_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_AS is not set | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | CONFIG_DEFAULT_CFQ=y | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 129 | # CONFIG_FREEZER is not set | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | CONFIG_ARCH_MMP=y | ||
| 163 | # CONFIG_ARCH_RPC is not set | ||
| 164 | # CONFIG_ARCH_SA1100 is not set | ||
| 165 | # CONFIG_ARCH_S3C2410 is not set | ||
| 166 | # CONFIG_ARCH_S3C64XX is not set | ||
| 167 | # CONFIG_ARCH_SHARK is not set | ||
| 168 | # CONFIG_ARCH_LH7A40X is not set | ||
| 169 | # CONFIG_ARCH_DAVINCI is not set | ||
| 170 | # CONFIG_ARCH_OMAP is not set | ||
| 171 | # CONFIG_ARCH_MSM is not set | ||
| 172 | # CONFIG_ARCH_W90X900 is not set | ||
| 173 | CONFIG_MACH_TAVOREVB=y | ||
| 174 | |||
| 175 | # | ||
| 176 | # Marvell PXA168/910 Implmentations | ||
| 177 | # | ||
| 178 | # CONFIG_MACH_ASPENITE is not set | ||
| 179 | # CONFIG_MACH_ZYLONITE2 is not set | ||
| 180 | CONFIG_MACH_TTC_DKB=y | ||
| 181 | CONFIG_CPU_PXA910=y | ||
| 182 | CONFIG_PLAT_PXA=y | ||
| 183 | |||
| 184 | # | ||
| 185 | # Processor Type | ||
| 186 | # | ||
| 187 | CONFIG_CPU_32=y | ||
| 188 | CONFIG_CPU_MOHAWK=y | ||
| 189 | CONFIG_CPU_32v5=y | ||
| 190 | CONFIG_CPU_ABRT_EV5T=y | ||
| 191 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 192 | CONFIG_CPU_CACHE_VIVT=y | ||
| 193 | CONFIG_CPU_COPY_V4WB=y | ||
| 194 | CONFIG_CPU_TLB_V4WBI=y | ||
| 195 | CONFIG_CPU_CP15=y | ||
| 196 | CONFIG_CPU_CP15_MMU=y | ||
| 197 | |||
| 198 | # | ||
| 199 | # Processor Features | ||
| 200 | # | ||
| 201 | CONFIG_ARM_THUMB=y | ||
| 202 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 203 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 204 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 205 | # CONFIG_OUTER_CACHE is not set | ||
| 206 | CONFIG_IWMMXT=y | ||
| 207 | CONFIG_COMMON_CLKDEV=y | ||
| 208 | |||
| 209 | # | ||
| 210 | # Bus support | ||
| 211 | # | ||
| 212 | # CONFIG_PCI_SYSCALL is not set | ||
| 213 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 214 | # CONFIG_PCCARD is not set | ||
| 215 | |||
| 216 | # | ||
| 217 | # Kernel Features | ||
| 218 | # | ||
| 219 | CONFIG_TICK_ONESHOT=y | ||
| 220 | CONFIG_NO_HZ=y | ||
| 221 | CONFIG_HIGH_RES_TIMERS=y | ||
| 222 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 223 | CONFIG_VMSPLIT_3G=y | ||
| 224 | # CONFIG_VMSPLIT_2G is not set | ||
| 225 | # CONFIG_VMSPLIT_1G is not set | ||
| 226 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 227 | CONFIG_PREEMPT=y | ||
| 228 | CONFIG_HZ=100 | ||
| 229 | CONFIG_AEABI=y | ||
| 230 | CONFIG_OABI_COMPAT=y | ||
| 231 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 232 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 233 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 234 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 235 | CONFIG_FLATMEM_MANUAL=y | ||
| 236 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 237 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 238 | CONFIG_FLATMEM=y | ||
| 239 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 240 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 241 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 242 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 243 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 244 | CONFIG_VIRT_TO_BUS=y | ||
| 245 | CONFIG_UNEVICTABLE_LRU=y | ||
| 246 | CONFIG_ALIGNMENT_TRAP=y | ||
| 247 | |||
| 248 | # | ||
| 249 | # Boot options | ||
| 250 | # | ||
| 251 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 252 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 253 | CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M" | ||
| 254 | # CONFIG_XIP_KERNEL is not set | ||
| 255 | # CONFIG_KEXEC is not set | ||
| 256 | |||
| 257 | # | ||
| 258 | # CPU Power Management | ||
| 259 | # | ||
| 260 | # CONFIG_CPU_IDLE is not set | ||
| 261 | |||
| 262 | # | ||
| 263 | # Floating point emulation | ||
| 264 | # | ||
| 265 | |||
| 266 | # | ||
| 267 | # At least one emulation must be selected | ||
| 268 | # | ||
| 269 | CONFIG_FPE_NWFPE=y | ||
| 270 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 271 | # CONFIG_FPE_FASTFPE is not set | ||
| 272 | |||
| 273 | # | ||
| 274 | # Userspace binary formats | ||
| 275 | # | ||
| 276 | CONFIG_BINFMT_ELF=y | ||
| 277 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 278 | CONFIG_HAVE_AOUT=y | ||
| 279 | # CONFIG_BINFMT_AOUT is not set | ||
| 280 | # CONFIG_BINFMT_MISC is not set | ||
| 281 | |||
| 282 | # | ||
| 283 | # Power management options | ||
| 284 | # | ||
| 285 | # CONFIG_PM is not set | ||
| 286 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 287 | CONFIG_NET=y | ||
| 288 | |||
| 289 | # | ||
| 290 | # Networking options | ||
| 291 | # | ||
| 292 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 293 | CONFIG_PACKET=y | ||
| 294 | # CONFIG_PACKET_MMAP is not set | ||
| 295 | CONFIG_UNIX=y | ||
| 296 | CONFIG_XFRM=y | ||
| 297 | # CONFIG_XFRM_USER is not set | ||
| 298 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 299 | # CONFIG_XFRM_MIGRATE is not set | ||
| 300 | # CONFIG_XFRM_STATISTICS is not set | ||
| 301 | # CONFIG_NET_KEY is not set | ||
| 302 | CONFIG_INET=y | ||
| 303 | # CONFIG_IP_MULTICAST is not set | ||
| 304 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 305 | CONFIG_IP_FIB_HASH=y | ||
| 306 | CONFIG_IP_PNP=y | ||
| 307 | # CONFIG_IP_PNP_DHCP is not set | ||
| 308 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 309 | # CONFIG_IP_PNP_RARP is not set | ||
| 310 | # CONFIG_NET_IPIP is not set | ||
| 311 | # CONFIG_NET_IPGRE is not set | ||
| 312 | # CONFIG_ARPD is not set | ||
| 313 | # CONFIG_SYN_COOKIES is not set | ||
| 314 | # CONFIG_INET_AH is not set | ||
| 315 | # CONFIG_INET_ESP is not set | ||
| 316 | # CONFIG_INET_IPCOMP is not set | ||
| 317 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 318 | # CONFIG_INET_TUNNEL is not set | ||
| 319 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 320 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 321 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 322 | # CONFIG_INET_LRO is not set | ||
| 323 | CONFIG_INET_DIAG=y | ||
| 324 | CONFIG_INET_TCP_DIAG=y | ||
| 325 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 326 | CONFIG_TCP_CONG_CUBIC=y | ||
| 327 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 328 | # CONFIG_TCP_MD5SIG is not set | ||
| 329 | # CONFIG_IPV6 is not set | ||
| 330 | # CONFIG_NETWORK_SECMARK is not set | ||
| 331 | # CONFIG_NETFILTER is not set | ||
| 332 | # CONFIG_IP_DCCP is not set | ||
| 333 | # CONFIG_IP_SCTP is not set | ||
| 334 | # CONFIG_TIPC is not set | ||
| 335 | # CONFIG_ATM is not set | ||
| 336 | # CONFIG_BRIDGE is not set | ||
| 337 | # CONFIG_NET_DSA is not set | ||
| 338 | # CONFIG_VLAN_8021Q is not set | ||
| 339 | # CONFIG_DECNET is not set | ||
| 340 | # CONFIG_LLC2 is not set | ||
| 341 | # CONFIG_IPX is not set | ||
| 342 | # CONFIG_ATALK is not set | ||
| 343 | # CONFIG_X25 is not set | ||
| 344 | # CONFIG_LAPB is not set | ||
| 345 | # CONFIG_ECONET is not set | ||
| 346 | # CONFIG_WAN_ROUTER is not set | ||
| 347 | # CONFIG_NET_SCHED is not set | ||
| 348 | # CONFIG_DCB is not set | ||
| 349 | |||
| 350 | # | ||
| 351 | # Network testing | ||
| 352 | # | ||
| 353 | # CONFIG_NET_PKTGEN is not set | ||
| 354 | # CONFIG_HAMRADIO is not set | ||
| 355 | # CONFIG_CAN is not set | ||
| 356 | # CONFIG_IRDA is not set | ||
| 357 | # CONFIG_BT is not set | ||
| 358 | # CONFIG_AF_RXRPC is not set | ||
| 359 | # CONFIG_PHONET is not set | ||
| 360 | CONFIG_WIRELESS=y | ||
| 361 | # CONFIG_CFG80211 is not set | ||
| 362 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 363 | # CONFIG_WIRELESS_EXT is not set | ||
| 364 | # CONFIG_LIB80211 is not set | ||
| 365 | # CONFIG_MAC80211 is not set | ||
| 366 | # CONFIG_WIMAX is not set | ||
| 367 | # CONFIG_RFKILL is not set | ||
| 368 | # CONFIG_NET_9P is not set | ||
| 369 | |||
| 370 | # | ||
| 371 | # Device Drivers | ||
| 372 | # | ||
| 373 | |||
| 374 | # | ||
| 375 | # Generic Driver Options | ||
| 376 | # | ||
| 377 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 378 | # CONFIG_STANDALONE is not set | ||
| 379 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 380 | CONFIG_FW_LOADER=y | ||
| 381 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 382 | CONFIG_EXTRA_FIRMWARE="" | ||
| 383 | # CONFIG_DEBUG_DRIVER is not set | ||
| 384 | # CONFIG_DEBUG_DEVRES is not set | ||
| 385 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 386 | # CONFIG_CONNECTOR is not set | ||
| 387 | # CONFIG_MTD is not set | ||
| 388 | # CONFIG_PARPORT is not set | ||
| 389 | # CONFIG_BLK_DEV is not set | ||
| 390 | # CONFIG_MISC_DEVICES is not set | ||
| 391 | CONFIG_HAVE_IDE=y | ||
| 392 | # CONFIG_IDE is not set | ||
| 393 | |||
| 394 | # | ||
| 395 | # SCSI device support | ||
| 396 | # | ||
| 397 | # CONFIG_RAID_ATTRS is not set | ||
| 398 | # CONFIG_SCSI is not set | ||
| 399 | # CONFIG_SCSI_DMA is not set | ||
| 400 | # CONFIG_SCSI_NETLINK is not set | ||
| 401 | # CONFIG_ATA is not set | ||
| 402 | # CONFIG_MD is not set | ||
| 403 | CONFIG_NETDEVICES=y | ||
| 404 | # CONFIG_DUMMY is not set | ||
| 405 | # CONFIG_BONDING is not set | ||
| 406 | # CONFIG_MACVLAN is not set | ||
| 407 | # CONFIG_EQUALIZER is not set | ||
| 408 | # CONFIG_TUN is not set | ||
| 409 | # CONFIG_VETH is not set | ||
| 410 | # CONFIG_PHYLIB is not set | ||
| 411 | CONFIG_NET_ETHERNET=y | ||
| 412 | CONFIG_MII=y | ||
| 413 | # CONFIG_AX88796 is not set | ||
| 414 | CONFIG_SMC91X=y | ||
| 415 | # CONFIG_DM9000 is not set | ||
| 416 | # CONFIG_SMC911X is not set | ||
| 417 | # CONFIG_SMSC911X is not set | ||
| 418 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 419 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 420 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 421 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 422 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 423 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 424 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 425 | # CONFIG_B44 is not set | ||
| 426 | # CONFIG_NETDEV_1000 is not set | ||
| 427 | # CONFIG_NETDEV_10000 is not set | ||
| 428 | |||
| 429 | # | ||
| 430 | # Wireless LAN | ||
| 431 | # | ||
| 432 | # CONFIG_WLAN_PRE80211 is not set | ||
| 433 | # CONFIG_WLAN_80211 is not set | ||
| 434 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 435 | |||
| 436 | # | ||
| 437 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 438 | # | ||
| 439 | # CONFIG_WAN is not set | ||
| 440 | # CONFIG_PPP is not set | ||
| 441 | # CONFIG_SLIP is not set | ||
| 442 | # CONFIG_NETCONSOLE is not set | ||
| 443 | # CONFIG_NETPOLL is not set | ||
| 444 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 445 | # CONFIG_ISDN is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Input device support | ||
| 449 | # | ||
| 450 | CONFIG_INPUT=y | ||
| 451 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 452 | # CONFIG_INPUT_POLLDEV is not set | ||
| 453 | |||
| 454 | # | ||
| 455 | # Userland interfaces | ||
| 456 | # | ||
| 457 | CONFIG_INPUT_MOUSEDEV=y | ||
| 458 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 459 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 460 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 461 | # CONFIG_INPUT_JOYDEV is not set | ||
| 462 | # CONFIG_INPUT_EVDEV is not set | ||
| 463 | # CONFIG_INPUT_EVBUG is not set | ||
| 464 | |||
| 465 | # | ||
| 466 | # Input Device Drivers | ||
| 467 | # | ||
| 468 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 469 | # CONFIG_INPUT_MOUSE is not set | ||
| 470 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 471 | # CONFIG_INPUT_TABLET is not set | ||
| 472 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 473 | # CONFIG_INPUT_MISC is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # Hardware I/O ports | ||
| 477 | # | ||
| 478 | # CONFIG_SERIO is not set | ||
| 479 | # CONFIG_GAMEPORT is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # Character devices | ||
| 483 | # | ||
| 484 | CONFIG_VT=y | ||
| 485 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 486 | CONFIG_VT_CONSOLE=y | ||
| 487 | CONFIG_HW_CONSOLE=y | ||
| 488 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 489 | CONFIG_DEVKMEM=y | ||
| 490 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 491 | |||
| 492 | # | ||
| 493 | # Serial drivers | ||
| 494 | # | ||
| 495 | # CONFIG_SERIAL_8250 is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # Non-8250 serial port support | ||
| 499 | # | ||
| 500 | CONFIG_SERIAL_PXA=y | ||
| 501 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 502 | CONFIG_SERIAL_CORE=y | ||
| 503 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 504 | CONFIG_UNIX98_PTYS=y | ||
| 505 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 506 | # CONFIG_LEGACY_PTYS is not set | ||
| 507 | # CONFIG_IPMI_HANDLER is not set | ||
| 508 | # CONFIG_HW_RANDOM is not set | ||
| 509 | # CONFIG_R3964 is not set | ||
| 510 | # CONFIG_RAW_DRIVER is not set | ||
| 511 | # CONFIG_TCG_TPM is not set | ||
| 512 | # CONFIG_I2C is not set | ||
| 513 | # CONFIG_SPI is not set | ||
| 514 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 515 | CONFIG_GPIOLIB=y | ||
| 516 | # CONFIG_DEBUG_GPIO is not set | ||
| 517 | # CONFIG_GPIO_SYSFS is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # Memory mapped GPIO expanders: | ||
| 521 | # | ||
| 522 | |||
| 523 | # | ||
| 524 | # I2C GPIO expanders: | ||
| 525 | # | ||
| 526 | |||
| 527 | # | ||
| 528 | # PCI GPIO expanders: | ||
| 529 | # | ||
| 530 | |||
| 531 | # | ||
| 532 | # SPI GPIO expanders: | ||
| 533 | # | ||
| 534 | # CONFIG_W1 is not set | ||
| 535 | # CONFIG_POWER_SUPPLY is not set | ||
| 536 | # CONFIG_HWMON is not set | ||
| 537 | # CONFIG_THERMAL is not set | ||
| 538 | # CONFIG_THERMAL_HWMON is not set | ||
| 539 | # CONFIG_WATCHDOG is not set | ||
| 540 | CONFIG_SSB_POSSIBLE=y | ||
| 541 | |||
| 542 | # | ||
| 543 | # Sonics Silicon Backplane | ||
| 544 | # | ||
| 545 | # CONFIG_SSB is not set | ||
| 546 | |||
| 547 | # | ||
| 548 | # Multifunction device drivers | ||
| 549 | # | ||
| 550 | # CONFIG_MFD_CORE is not set | ||
| 551 | # CONFIG_MFD_SM501 is not set | ||
| 552 | # CONFIG_MFD_ASIC3 is not set | ||
| 553 | # CONFIG_HTC_EGPIO is not set | ||
| 554 | # CONFIG_HTC_PASIC3 is not set | ||
| 555 | # CONFIG_MFD_TMIO is not set | ||
| 556 | # CONFIG_MFD_T7L66XB is not set | ||
| 557 | # CONFIG_MFD_TC6387XB is not set | ||
| 558 | # CONFIG_MFD_TC6393XB is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Multimedia devices | ||
| 562 | # | ||
| 563 | |||
| 564 | # | ||
| 565 | # Multimedia core support | ||
| 566 | # | ||
| 567 | # CONFIG_VIDEO_DEV is not set | ||
| 568 | # CONFIG_DVB_CORE is not set | ||
| 569 | # CONFIG_VIDEO_MEDIA is not set | ||
| 570 | |||
| 571 | # | ||
| 572 | # Multimedia drivers | ||
| 573 | # | ||
| 574 | # CONFIG_DAB is not set | ||
| 575 | |||
| 576 | # | ||
| 577 | # Graphics support | ||
| 578 | # | ||
| 579 | # CONFIG_VGASTATE is not set | ||
| 580 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 581 | # CONFIG_FB is not set | ||
| 582 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # Display device support | ||
| 586 | # | ||
| 587 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 588 | |||
| 589 | # | ||
| 590 | # Console display driver support | ||
| 591 | # | ||
| 592 | # CONFIG_VGA_CONSOLE is not set | ||
| 593 | CONFIG_DUMMY_CONSOLE=y | ||
| 594 | # CONFIG_SOUND is not set | ||
| 595 | # CONFIG_HID_SUPPORT is not set | ||
| 596 | # CONFIG_USB_SUPPORT is not set | ||
| 597 | # CONFIG_MMC is not set | ||
| 598 | # CONFIG_MEMSTICK is not set | ||
| 599 | # CONFIG_ACCESSIBILITY is not set | ||
| 600 | # CONFIG_NEW_LEDS is not set | ||
| 601 | CONFIG_RTC_LIB=y | ||
| 602 | # CONFIG_RTC_CLASS is not set | ||
| 603 | # CONFIG_DMADEVICES is not set | ||
| 604 | # CONFIG_REGULATOR is not set | ||
| 605 | # CONFIG_UIO is not set | ||
| 606 | # CONFIG_STAGING is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # File systems | ||
| 610 | # | ||
| 611 | # CONFIG_EXT2_FS is not set | ||
| 612 | # CONFIG_EXT3_FS is not set | ||
| 613 | # CONFIG_EXT4_FS is not set | ||
| 614 | # CONFIG_REISERFS_FS is not set | ||
| 615 | # CONFIG_JFS_FS is not set | ||
| 616 | CONFIG_FS_POSIX_ACL=y | ||
| 617 | CONFIG_FILE_LOCKING=y | ||
| 618 | # CONFIG_XFS_FS is not set | ||
| 619 | # CONFIG_OCFS2_FS is not set | ||
| 620 | # CONFIG_BTRFS_FS is not set | ||
| 621 | CONFIG_DNOTIFY=y | ||
| 622 | CONFIG_INOTIFY=y | ||
| 623 | CONFIG_INOTIFY_USER=y | ||
| 624 | # CONFIG_QUOTA is not set | ||
| 625 | # CONFIG_AUTOFS_FS is not set | ||
| 626 | # CONFIG_AUTOFS4_FS is not set | ||
| 627 | # CONFIG_FUSE_FS is not set | ||
| 628 | CONFIG_GENERIC_ACL=y | ||
| 629 | |||
| 630 | # | ||
| 631 | # CD-ROM/DVD Filesystems | ||
| 632 | # | ||
| 633 | # CONFIG_ISO9660_FS is not set | ||
| 634 | # CONFIG_UDF_FS is not set | ||
| 635 | |||
| 636 | # | ||
| 637 | # DOS/FAT/NT Filesystems | ||
| 638 | # | ||
| 639 | # CONFIG_MSDOS_FS is not set | ||
| 640 | # CONFIG_VFAT_FS is not set | ||
| 641 | # CONFIG_NTFS_FS is not set | ||
| 642 | |||
| 643 | # | ||
| 644 | # Pseudo filesystems | ||
| 645 | # | ||
| 646 | CONFIG_PROC_FS=y | ||
| 647 | CONFIG_PROC_SYSCTL=y | ||
| 648 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 649 | CONFIG_SYSFS=y | ||
| 650 | CONFIG_TMPFS=y | ||
| 651 | CONFIG_TMPFS_POSIX_ACL=y | ||
| 652 | # CONFIG_HUGETLB_PAGE is not set | ||
| 653 | # CONFIG_CONFIGFS_FS is not set | ||
| 654 | CONFIG_MISC_FILESYSTEMS=y | ||
| 655 | # CONFIG_ADFS_FS is not set | ||
| 656 | # CONFIG_AFFS_FS is not set | ||
| 657 | # CONFIG_HFS_FS is not set | ||
| 658 | # CONFIG_HFSPLUS_FS is not set | ||
| 659 | # CONFIG_BEFS_FS is not set | ||
| 660 | # CONFIG_BFS_FS is not set | ||
| 661 | # CONFIG_EFS_FS is not set | ||
| 662 | CONFIG_CRAMFS=y | ||
| 663 | # CONFIG_SQUASHFS is not set | ||
| 664 | # CONFIG_VXFS_FS is not set | ||
| 665 | # CONFIG_MINIX_FS is not set | ||
| 666 | # CONFIG_OMFS_FS is not set | ||
| 667 | # CONFIG_HPFS_FS is not set | ||
| 668 | # CONFIG_QNX4FS_FS is not set | ||
| 669 | # CONFIG_ROMFS_FS is not set | ||
| 670 | # CONFIG_SYSV_FS is not set | ||
| 671 | # CONFIG_UFS_FS is not set | ||
| 672 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 673 | CONFIG_NFS_FS=y | ||
| 674 | CONFIG_NFS_V3=y | ||
| 675 | CONFIG_NFS_V3_ACL=y | ||
| 676 | CONFIG_NFS_V4=y | ||
| 677 | CONFIG_ROOT_NFS=y | ||
| 678 | # CONFIG_NFSD is not set | ||
| 679 | CONFIG_LOCKD=y | ||
| 680 | CONFIG_LOCKD_V4=y | ||
| 681 | CONFIG_NFS_ACL_SUPPORT=y | ||
| 682 | CONFIG_NFS_COMMON=y | ||
| 683 | CONFIG_SUNRPC=y | ||
| 684 | CONFIG_SUNRPC_GSS=y | ||
| 685 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 686 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 687 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 688 | # CONFIG_SMB_FS is not set | ||
| 689 | # CONFIG_CIFS is not set | ||
| 690 | # CONFIG_NCP_FS is not set | ||
| 691 | # CONFIG_CODA_FS is not set | ||
| 692 | # CONFIG_AFS_FS is not set | ||
| 693 | |||
| 694 | # | ||
| 695 | # Partition Types | ||
| 696 | # | ||
| 697 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 698 | CONFIG_MSDOS_PARTITION=y | ||
| 699 | # CONFIG_NLS is not set | ||
| 700 | # CONFIG_DLM is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # Kernel hacking | ||
| 704 | # | ||
| 705 | CONFIG_PRINTK_TIME=y | ||
| 706 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 707 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 708 | CONFIG_FRAME_WARN=1024 | ||
| 709 | CONFIG_MAGIC_SYSRQ=y | ||
| 710 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 711 | # CONFIG_DEBUG_FS is not set | ||
| 712 | # CONFIG_HEADERS_CHECK is not set | ||
| 713 | CONFIG_DEBUG_KERNEL=y | ||
| 714 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 715 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 716 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 717 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 718 | CONFIG_SCHED_DEBUG=y | ||
| 719 | # CONFIG_SCHEDSTATS is not set | ||
| 720 | # CONFIG_TIMER_STATS is not set | ||
| 721 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 722 | # CONFIG_DEBUG_SLAB is not set | ||
| 723 | # CONFIG_DEBUG_PREEMPT is not set | ||
| 724 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 725 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 726 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 727 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 728 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 729 | # CONFIG_PROVE_LOCKING is not set | ||
| 730 | # CONFIG_LOCK_STAT is not set | ||
| 731 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 732 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 733 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 734 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 735 | CONFIG_DEBUG_INFO=y | ||
| 736 | # CONFIG_DEBUG_VM is not set | ||
| 737 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 738 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 739 | # CONFIG_DEBUG_LIST is not set | ||
| 740 | # CONFIG_DEBUG_SG is not set | ||
| 741 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 742 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 743 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 744 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 745 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 746 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 747 | # CONFIG_FAULT_INJECTION is not set | ||
| 748 | # CONFIG_LATENCYTOP is not set | ||
| 749 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 750 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 751 | |||
| 752 | # | ||
| 753 | # Tracers | ||
| 754 | # | ||
| 755 | # CONFIG_FUNCTION_TRACER is not set | ||
| 756 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 757 | # CONFIG_PREEMPT_TRACER is not set | ||
| 758 | # CONFIG_SCHED_TRACER is not set | ||
| 759 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 760 | # CONFIG_BOOT_TRACER is not set | ||
| 761 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 762 | # CONFIG_STACK_TRACER is not set | ||
| 763 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 764 | # CONFIG_SAMPLES is not set | ||
| 765 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 766 | # CONFIG_KGDB is not set | ||
| 767 | CONFIG_ARM_UNWIND=y | ||
| 768 | CONFIG_DEBUG_USER=y | ||
| 769 | CONFIG_DEBUG_ERRORS=y | ||
| 770 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 771 | CONFIG_DEBUG_LL=y | ||
| 772 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 773 | |||
| 774 | # | ||
| 775 | # Security options | ||
| 776 | # | ||
| 777 | # CONFIG_KEYS is not set | ||
| 778 | # CONFIG_SECURITY is not set | ||
| 779 | # CONFIG_SECURITYFS is not set | ||
| 780 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 781 | CONFIG_CRYPTO=y | ||
| 782 | |||
| 783 | # | ||
| 784 | # Crypto core or helper | ||
| 785 | # | ||
| 786 | # CONFIG_CRYPTO_FIPS is not set | ||
| 787 | CONFIG_CRYPTO_ALGAPI=y | ||
| 788 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 789 | CONFIG_CRYPTO_AEAD2=y | ||
| 790 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 791 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 792 | CONFIG_CRYPTO_HASH=y | ||
| 793 | CONFIG_CRYPTO_HASH2=y | ||
| 794 | CONFIG_CRYPTO_RNG2=y | ||
| 795 | CONFIG_CRYPTO_MANAGER=y | ||
| 796 | CONFIG_CRYPTO_MANAGER2=y | ||
| 797 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 798 | # CONFIG_CRYPTO_NULL is not set | ||
| 799 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 800 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 801 | # CONFIG_CRYPTO_TEST is not set | ||
| 802 | |||
| 803 | # | ||
| 804 | # Authenticated Encryption with Associated Data | ||
| 805 | # | ||
| 806 | # CONFIG_CRYPTO_CCM is not set | ||
| 807 | # CONFIG_CRYPTO_GCM is not set | ||
| 808 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Block modes | ||
| 812 | # | ||
| 813 | CONFIG_CRYPTO_CBC=y | ||
| 814 | # CONFIG_CRYPTO_CTR is not set | ||
| 815 | # CONFIG_CRYPTO_CTS is not set | ||
| 816 | # CONFIG_CRYPTO_ECB is not set | ||
| 817 | # CONFIG_CRYPTO_LRW is not set | ||
| 818 | # CONFIG_CRYPTO_PCBC is not set | ||
| 819 | # CONFIG_CRYPTO_XTS is not set | ||
| 820 | |||
| 821 | # | ||
| 822 | # Hash modes | ||
| 823 | # | ||
| 824 | # CONFIG_CRYPTO_HMAC is not set | ||
| 825 | # CONFIG_CRYPTO_XCBC is not set | ||
| 826 | |||
| 827 | # | ||
| 828 | # Digest | ||
| 829 | # | ||
| 830 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 831 | # CONFIG_CRYPTO_MD4 is not set | ||
| 832 | CONFIG_CRYPTO_MD5=y | ||
| 833 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 834 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 835 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 836 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 837 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 838 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 839 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 840 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 841 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 842 | # CONFIG_CRYPTO_WP512 is not set | ||
| 843 | |||
| 844 | # | ||
| 845 | # Ciphers | ||
| 846 | # | ||
| 847 | # CONFIG_CRYPTO_AES is not set | ||
| 848 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 849 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 850 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 851 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 852 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 853 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 854 | CONFIG_CRYPTO_DES=y | ||
| 855 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 856 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 857 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 858 | # CONFIG_CRYPTO_SEED is not set | ||
| 859 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 860 | # CONFIG_CRYPTO_TEA is not set | ||
| 861 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # Compression | ||
| 865 | # | ||
| 866 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 867 | # CONFIG_CRYPTO_LZO is not set | ||
| 868 | |||
| 869 | # | ||
| 870 | # Random Number Generation | ||
| 871 | # | ||
| 872 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 873 | CONFIG_CRYPTO_HW=y | ||
| 874 | |||
| 875 | # | ||
| 876 | # Library routines | ||
| 877 | # | ||
| 878 | CONFIG_BITREVERSE=y | ||
| 879 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 880 | CONFIG_CRC_CCITT=y | ||
| 881 | # CONFIG_CRC16 is not set | ||
| 882 | # CONFIG_CRC_T10DIF is not set | ||
| 883 | # CONFIG_CRC_ITU_T is not set | ||
| 884 | CONFIG_CRC32=y | ||
| 885 | # CONFIG_CRC7 is not set | ||
| 886 | # CONFIG_LIBCRC32C is not set | ||
| 887 | CONFIG_ZLIB_INFLATE=y | ||
| 888 | CONFIG_PLIST=y | ||
| 889 | CONFIG_HAS_IOMEM=y | ||
| 890 | CONFIG_HAS_IOPORT=y | ||
| 891 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig new file mode 100644 index 000000000000..593102da8cd7 --- /dev/null +++ b/arch/arm/configs/rx51_defconfig | |||
| @@ -0,0 +1,1821 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc8 | ||
| 4 | # Fri Mar 13 15:28:56 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 35 | CONFIG_LOCALVERSION="" | ||
| 36 | CONFIG_LOCALVERSION_AUTO=y | ||
| 37 | CONFIG_SWAP=y | ||
| 38 | CONFIG_SYSVIPC=y | ||
| 39 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 40 | CONFIG_POSIX_MQUEUE=y | ||
| 41 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | # CONFIG_IKCONFIG is not set | ||
| 55 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 56 | CONFIG_GROUP_SCHED=y | ||
| 57 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 58 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 59 | CONFIG_USER_SCHED=y | ||
| 60 | # CONFIG_CGROUP_SCHED is not set | ||
| 61 | # CONFIG_CGROUPS is not set | ||
| 62 | CONFIG_SYSFS_DEPRECATED=y | ||
| 63 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 64 | # CONFIG_RELAY is not set | ||
| 65 | # CONFIG_NAMESPACES is not set | ||
| 66 | CONFIG_BLK_DEV_INITRD=y | ||
| 67 | CONFIG_INITRAMFS_SOURCE="" | ||
| 68 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 69 | CONFIG_SYSCTL=y | ||
| 70 | CONFIG_ANON_INODES=y | ||
| 71 | CONFIG_EMBEDDED=y | ||
| 72 | CONFIG_UID16=y | ||
| 73 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 74 | CONFIG_KALLSYMS=y | ||
| 75 | CONFIG_KALLSYMS_ALL=y | ||
| 76 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 77 | CONFIG_HOTPLUG=y | ||
| 78 | CONFIG_PRINTK=y | ||
| 79 | CONFIG_BUG=y | ||
| 80 | CONFIG_ELF_CORE=y | ||
| 81 | CONFIG_BASE_FULL=y | ||
| 82 | CONFIG_FUTEX=y | ||
| 83 | CONFIG_EPOLL=y | ||
| 84 | CONFIG_SIGNALFD=y | ||
| 85 | CONFIG_TIMERFD=y | ||
| 86 | CONFIG_EVENTFD=y | ||
| 87 | CONFIG_SHMEM=y | ||
| 88 | CONFIG_AIO=y | ||
| 89 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 90 | CONFIG_COMPAT_BRK=y | ||
| 91 | CONFIG_SLAB=y | ||
| 92 | # CONFIG_SLUB is not set | ||
| 93 | # CONFIG_SLOB is not set | ||
| 94 | # CONFIG_PROFILING is not set | ||
| 95 | CONFIG_HAVE_OPROFILE=y | ||
| 96 | CONFIG_KPROBES=y | ||
| 97 | CONFIG_KRETPROBES=y | ||
| 98 | CONFIG_HAVE_KPROBES=y | ||
| 99 | CONFIG_HAVE_KRETPROBES=y | ||
| 100 | CONFIG_HAVE_CLK=y | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 102 | CONFIG_SLABINFO=y | ||
| 103 | CONFIG_RT_MUTEXES=y | ||
| 104 | CONFIG_BASE_SMALL=0 | ||
| 105 | CONFIG_MODULES=y | ||
| 106 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 107 | CONFIG_MODULE_UNLOAD=y | ||
| 108 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 109 | CONFIG_MODVERSIONS=y | ||
| 110 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 111 | CONFIG_BLOCK=y | ||
| 112 | # CONFIG_LBD is not set | ||
| 113 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | # CONFIG_IOSCHED_AS is not set | ||
| 122 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 123 | CONFIG_IOSCHED_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_AS is not set | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | CONFIG_DEFAULT_CFQ=y | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 129 | CONFIG_FREEZER=y | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | # CONFIG_ARCH_RPC is not set | ||
| 163 | # CONFIG_ARCH_SA1100 is not set | ||
| 164 | # CONFIG_ARCH_S3C2410 is not set | ||
| 165 | # CONFIG_ARCH_S3C64XX is not set | ||
| 166 | # CONFIG_ARCH_SHARK is not set | ||
| 167 | # CONFIG_ARCH_LH7A40X is not set | ||
| 168 | # CONFIG_ARCH_DAVINCI is not set | ||
| 169 | CONFIG_ARCH_OMAP=y | ||
| 170 | # CONFIG_ARCH_MSM is not set | ||
| 171 | # CONFIG_ARCH_W90X900 is not set | ||
| 172 | |||
| 173 | # | ||
| 174 | # TI OMAP Implementations | ||
| 175 | # | ||
| 176 | CONFIG_ARCH_OMAP_OTG=y | ||
| 177 | # CONFIG_ARCH_OMAP1 is not set | ||
| 178 | # CONFIG_ARCH_OMAP2 is not set | ||
| 179 | CONFIG_ARCH_OMAP3=y | ||
| 180 | |||
| 181 | # | ||
| 182 | # OMAP Feature Selections | ||
| 183 | # | ||
| 184 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | ||
| 185 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | ||
| 186 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 187 | CONFIG_OMAP_MUX=y | ||
| 188 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 189 | CONFIG_OMAP_MUX_WARNINGS=y | ||
| 190 | CONFIG_OMAP_MCBSP=y | ||
| 191 | # CONFIG_OMAP_MPU_TIMER is not set | ||
| 192 | CONFIG_OMAP_32K_TIMER=y | ||
| 193 | CONFIG_OMAP_32K_TIMER_HZ=128 | ||
| 194 | CONFIG_OMAP_DM_TIMER=y | ||
| 195 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | ||
| 196 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | ||
| 197 | CONFIG_OMAP_LL_DEBUG_UART3=y | ||
| 198 | CONFIG_OMAP_SERIAL_WAKE=y | ||
| 199 | CONFIG_ARCH_OMAP34XX=y | ||
| 200 | CONFIG_ARCH_OMAP3430=y | ||
| 201 | |||
| 202 | # | ||
| 203 | # OMAP Board Type | ||
| 204 | # | ||
| 205 | # CONFIG_MACH_OMAP3_BEAGLE is not set | ||
| 206 | # CONFIG_MACH_OMAP_LDP is not set | ||
| 207 | # CONFIG_MACH_OVERO is not set | ||
| 208 | # CONFIG_MACH_OMAP3_PANDORA is not set | ||
| 209 | # CONFIG_MACH_OMAP_3430SDP is not set | ||
| 210 | CONFIG_MACH_NOKIA_RX51=y | ||
| 211 | |||
| 212 | # | ||
| 213 | # Processor Type | ||
| 214 | # | ||
| 215 | CONFIG_CPU_32=y | ||
| 216 | CONFIG_CPU_32v6K=y | ||
| 217 | CONFIG_CPU_V7=y | ||
| 218 | CONFIG_CPU_32v7=y | ||
| 219 | CONFIG_CPU_ABRT_EV7=y | ||
| 220 | CONFIG_CPU_PABRT_IFAR=y | ||
| 221 | CONFIG_CPU_CACHE_V7=y | ||
| 222 | CONFIG_CPU_CACHE_VIPT=y | ||
| 223 | CONFIG_CPU_COPY_V6=y | ||
| 224 | CONFIG_CPU_TLB_V7=y | ||
| 225 | CONFIG_CPU_HAS_ASID=y | ||
| 226 | CONFIG_CPU_CP15=y | ||
| 227 | CONFIG_CPU_CP15_MMU=y | ||
| 228 | |||
| 229 | # | ||
| 230 | # Processor Features | ||
| 231 | # | ||
| 232 | CONFIG_ARM_THUMB=y | ||
| 233 | # CONFIG_ARM_THUMBEE is not set | ||
| 234 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 235 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 236 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 237 | CONFIG_HAS_TLS_REG=y | ||
| 238 | # CONFIG_OUTER_CACHE is not set | ||
| 239 | |||
| 240 | # | ||
| 241 | # Bus support | ||
| 242 | # | ||
| 243 | # CONFIG_PCI_SYSCALL is not set | ||
| 244 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 245 | # CONFIG_PCCARD is not set | ||
| 246 | |||
| 247 | # | ||
| 248 | # Kernel Features | ||
| 249 | # | ||
| 250 | CONFIG_TICK_ONESHOT=y | ||
| 251 | CONFIG_NO_HZ=y | ||
| 252 | CONFIG_HIGH_RES_TIMERS=y | ||
| 253 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 254 | CONFIG_VMSPLIT_3G=y | ||
| 255 | # CONFIG_VMSPLIT_2G is not set | ||
| 256 | # CONFIG_VMSPLIT_1G is not set | ||
| 257 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 258 | # CONFIG_PREEMPT is not set | ||
| 259 | CONFIG_HZ=128 | ||
| 260 | CONFIG_AEABI=y | ||
| 261 | # CONFIG_OABI_COMPAT is not set | ||
| 262 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 263 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 264 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 265 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 266 | CONFIG_FLATMEM_MANUAL=y | ||
| 267 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 268 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 269 | CONFIG_FLATMEM=y | ||
| 270 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 271 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 272 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 273 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 274 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 275 | CONFIG_VIRT_TO_BUS=y | ||
| 276 | CONFIG_UNEVICTABLE_LRU=y | ||
| 277 | # CONFIG_LEDS is not set | ||
| 278 | CONFIG_ALIGNMENT_TRAP=y | ||
| 279 | |||
| 280 | # | ||
| 281 | # Boot options | ||
| 282 | # | ||
| 283 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 284 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 285 | CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw console=ttyMTD5" | ||
| 286 | # CONFIG_XIP_KERNEL is not set | ||
| 287 | # CONFIG_KEXEC is not set | ||
| 288 | |||
| 289 | # | ||
| 290 | # CPU Power Management | ||
| 291 | # | ||
| 292 | # CONFIG_CPU_FREQ is not set | ||
| 293 | # CONFIG_CPU_IDLE is not set | ||
| 294 | |||
| 295 | # | ||
| 296 | # Floating point emulation | ||
| 297 | # | ||
| 298 | |||
| 299 | # | ||
| 300 | # At least one emulation must be selected | ||
| 301 | # | ||
| 302 | CONFIG_VFP=y | ||
| 303 | CONFIG_VFPv3=y | ||
| 304 | CONFIG_NEON=y | ||
| 305 | |||
| 306 | # | ||
| 307 | # Userspace binary formats | ||
| 308 | # | ||
| 309 | CONFIG_BINFMT_ELF=y | ||
| 310 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 311 | CONFIG_HAVE_AOUT=y | ||
| 312 | # CONFIG_BINFMT_AOUT is not set | ||
| 313 | CONFIG_BINFMT_MISC=y | ||
| 314 | |||
| 315 | # | ||
| 316 | # Power management options | ||
| 317 | # | ||
| 318 | CONFIG_PM=y | ||
| 319 | CONFIG_PM_DEBUG=y | ||
| 320 | # CONFIG_PM_VERBOSE is not set | ||
| 321 | CONFIG_CAN_PM_TRACE=y | ||
| 322 | CONFIG_PM_SLEEP=y | ||
| 323 | CONFIG_SUSPEND=y | ||
| 324 | CONFIG_SUSPEND_FREEZER=y | ||
| 325 | # CONFIG_APM_EMULATION is not set | ||
| 326 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 327 | CONFIG_NET=y | ||
| 328 | |||
| 329 | # | ||
| 330 | # Networking options | ||
| 331 | # | ||
| 332 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 333 | CONFIG_PACKET=y | ||
| 334 | # CONFIG_PACKET_MMAP is not set | ||
| 335 | CONFIG_UNIX=y | ||
| 336 | CONFIG_XFRM=y | ||
| 337 | # CONFIG_XFRM_USER is not set | ||
| 338 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 339 | # CONFIG_XFRM_MIGRATE is not set | ||
| 340 | # CONFIG_XFRM_STATISTICS is not set | ||
| 341 | CONFIG_NET_KEY=y | ||
| 342 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 343 | CONFIG_INET=y | ||
| 344 | # CONFIG_IP_MULTICAST is not set | ||
| 345 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 346 | CONFIG_IP_FIB_HASH=y | ||
| 347 | CONFIG_IP_PNP=y | ||
| 348 | CONFIG_IP_PNP_DHCP=y | ||
| 349 | CONFIG_IP_PNP_BOOTP=y | ||
| 350 | CONFIG_IP_PNP_RARP=y | ||
| 351 | # CONFIG_NET_IPIP is not set | ||
| 352 | # CONFIG_NET_IPGRE is not set | ||
| 353 | # CONFIG_ARPD is not set | ||
| 354 | # CONFIG_SYN_COOKIES is not set | ||
| 355 | # CONFIG_INET_AH is not set | ||
| 356 | # CONFIG_INET_ESP is not set | ||
| 357 | # CONFIG_INET_IPCOMP is not set | ||
| 358 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 359 | # CONFIG_INET_TUNNEL is not set | ||
| 360 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 361 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 362 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 363 | # CONFIG_INET_LRO is not set | ||
| 364 | CONFIG_INET_DIAG=y | ||
| 365 | CONFIG_INET_TCP_DIAG=y | ||
| 366 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 367 | CONFIG_TCP_CONG_CUBIC=y | ||
| 368 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 369 | # CONFIG_TCP_MD5SIG is not set | ||
| 370 | # CONFIG_IPV6 is not set | ||
| 371 | # CONFIG_NETLABEL is not set | ||
| 372 | # CONFIG_NETWORK_SECMARK is not set | ||
| 373 | CONFIG_NETFILTER=y | ||
| 374 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 375 | CONFIG_NETFILTER_ADVANCED=y | ||
| 376 | |||
| 377 | # | ||
| 378 | # Core Netfilter Configuration | ||
| 379 | # | ||
| 380 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set | ||
| 381 | # CONFIG_NETFILTER_NETLINK_LOG is not set | ||
| 382 | # CONFIG_NF_CONNTRACK is not set | ||
| 383 | CONFIG_NETFILTER_XTABLES=m | ||
| 384 | # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set | ||
| 385 | # CONFIG_NETFILTER_XT_TARGET_MARK is not set | ||
| 386 | # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set | ||
| 387 | # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set | ||
| 388 | # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set | ||
| 389 | # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set | ||
| 390 | # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set | ||
| 391 | # CONFIG_NETFILTER_XT_MATCH_DCCP is not set | ||
| 392 | # CONFIG_NETFILTER_XT_MATCH_DSCP is not set | ||
| 393 | # CONFIG_NETFILTER_XT_MATCH_ESP is not set | ||
| 394 | # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set | ||
| 395 | # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set | ||
| 396 | # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set | ||
| 397 | # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set | ||
| 398 | # CONFIG_NETFILTER_XT_MATCH_MAC is not set | ||
| 399 | # CONFIG_NETFILTER_XT_MATCH_MARK is not set | ||
| 400 | # CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set | ||
| 401 | # CONFIG_NETFILTER_XT_MATCH_OWNER is not set | ||
| 402 | # CONFIG_NETFILTER_XT_MATCH_POLICY is not set | ||
| 403 | # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set | ||
| 404 | # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set | ||
| 405 | # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set | ||
| 406 | # CONFIG_NETFILTER_XT_MATCH_REALM is not set | ||
| 407 | # CONFIG_NETFILTER_XT_MATCH_RECENT is not set | ||
| 408 | # CONFIG_NETFILTER_XT_MATCH_SCTP is not set | ||
| 409 | # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set | ||
| 410 | # CONFIG_NETFILTER_XT_MATCH_STRING is not set | ||
| 411 | # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set | ||
| 412 | # CONFIG_NETFILTER_XT_MATCH_TIME is not set | ||
| 413 | # CONFIG_NETFILTER_XT_MATCH_U32 is not set | ||
| 414 | # CONFIG_IP_VS is not set | ||
| 415 | |||
| 416 | # | ||
| 417 | # IP: Netfilter Configuration | ||
| 418 | # | ||
| 419 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 420 | # CONFIG_IP_NF_QUEUE is not set | ||
| 421 | CONFIG_IP_NF_IPTABLES=m | ||
| 422 | # CONFIG_IP_NF_MATCH_ADDRTYPE is not set | ||
| 423 | # CONFIG_IP_NF_MATCH_AH is not set | ||
| 424 | # CONFIG_IP_NF_MATCH_ECN is not set | ||
| 425 | # CONFIG_IP_NF_MATCH_TTL is not set | ||
| 426 | CONFIG_IP_NF_FILTER=m | ||
| 427 | # CONFIG_IP_NF_TARGET_REJECT is not set | ||
| 428 | # CONFIG_IP_NF_TARGET_LOG is not set | ||
| 429 | # CONFIG_IP_NF_TARGET_ULOG is not set | ||
| 430 | # CONFIG_IP_NF_MANGLE is not set | ||
| 431 | # CONFIG_IP_NF_RAW is not set | ||
| 432 | # CONFIG_IP_NF_SECURITY is not set | ||
| 433 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 434 | # CONFIG_IP_DCCP is not set | ||
| 435 | # CONFIG_IP_SCTP is not set | ||
| 436 | # CONFIG_TIPC is not set | ||
| 437 | # CONFIG_ATM is not set | ||
| 438 | # CONFIG_BRIDGE is not set | ||
| 439 | # CONFIG_NET_DSA is not set | ||
| 440 | # CONFIG_VLAN_8021Q is not set | ||
| 441 | # CONFIG_DECNET is not set | ||
| 442 | # CONFIG_LLC2 is not set | ||
| 443 | # CONFIG_IPX is not set | ||
| 444 | # CONFIG_ATALK is not set | ||
| 445 | # CONFIG_X25 is not set | ||
| 446 | # CONFIG_LAPB is not set | ||
| 447 | # CONFIG_ECONET is not set | ||
| 448 | # CONFIG_WAN_ROUTER is not set | ||
| 449 | # CONFIG_NET_SCHED is not set | ||
| 450 | # CONFIG_DCB is not set | ||
| 451 | |||
| 452 | # | ||
| 453 | # Network testing | ||
| 454 | # | ||
| 455 | # CONFIG_NET_PKTGEN is not set | ||
| 456 | # CONFIG_NET_TCPPROBE is not set | ||
| 457 | # CONFIG_HAMRADIO is not set | ||
| 458 | # CONFIG_CAN is not set | ||
| 459 | # CONFIG_IRDA is not set | ||
| 460 | CONFIG_BT=m | ||
| 461 | CONFIG_BT_L2CAP=m | ||
| 462 | CONFIG_BT_SCO=m | ||
| 463 | CONFIG_BT_RFCOMM=m | ||
| 464 | CONFIG_BT_RFCOMM_TTY=y | ||
| 465 | CONFIG_BT_BNEP=m | ||
| 466 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 467 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 468 | CONFIG_BT_HIDP=m | ||
| 469 | |||
| 470 | # | ||
| 471 | # Bluetooth device drivers | ||
| 472 | # | ||
| 473 | # CONFIG_BT_HCIBTUSB is not set | ||
| 474 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 475 | # CONFIG_BT_HCIUART is not set | ||
| 476 | # CONFIG_BT_HCIBCM203X is not set | ||
| 477 | # CONFIG_BT_HCIBPA10X is not set | ||
| 478 | # CONFIG_BT_HCIBFUSB is not set | ||
| 479 | # CONFIG_BT_HCIVHCI is not set | ||
| 480 | # CONFIG_AF_RXRPC is not set | ||
| 481 | # CONFIG_PHONET is not set | ||
| 482 | CONFIG_WIRELESS=y | ||
| 483 | CONFIG_CFG80211=y | ||
| 484 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 485 | CONFIG_NL80211=y | ||
| 486 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 487 | CONFIG_WIRELESS_EXT=y | ||
| 488 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 489 | # CONFIG_LIB80211 is not set | ||
| 490 | CONFIG_MAC80211=m | ||
| 491 | |||
| 492 | # | ||
| 493 | # Rate control algorithm selection | ||
| 494 | # | ||
| 495 | CONFIG_MAC80211_RC_PID=y | ||
| 496 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
| 497 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
| 498 | # CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set | ||
| 499 | CONFIG_MAC80211_RC_DEFAULT="pid" | ||
| 500 | # CONFIG_MAC80211_MESH is not set | ||
| 501 | # CONFIG_MAC80211_LEDS is not set | ||
| 502 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 503 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 504 | # CONFIG_WIMAX is not set | ||
| 505 | # CONFIG_RFKILL is not set | ||
| 506 | # CONFIG_NET_9P is not set | ||
| 507 | |||
| 508 | # | ||
| 509 | # Device Drivers | ||
| 510 | # | ||
| 511 | |||
| 512 | # | ||
| 513 | # Generic Driver Options | ||
| 514 | # | ||
| 515 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 516 | CONFIG_STANDALONE=y | ||
| 517 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 518 | CONFIG_FW_LOADER=y | ||
| 519 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 520 | CONFIG_EXTRA_FIRMWARE="" | ||
| 521 | # CONFIG_DEBUG_DRIVER is not set | ||
| 522 | # CONFIG_DEBUG_DEVRES is not set | ||
| 523 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 524 | # CONFIG_CONNECTOR is not set | ||
| 525 | CONFIG_MTD=y | ||
| 526 | # CONFIG_MTD_DEBUG is not set | ||
| 527 | CONFIG_MTD_CONCAT=y | ||
| 528 | CONFIG_MTD_PARTITIONS=y | ||
| 529 | # CONFIG_MTD_TESTS is not set | ||
| 530 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 531 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 532 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 533 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 534 | |||
| 535 | # | ||
| 536 | # User Modules And Translation Layers | ||
| 537 | # | ||
| 538 | CONFIG_MTD_CHAR=y | ||
| 539 | CONFIG_MTD_BLKDEVS=y | ||
| 540 | CONFIG_MTD_BLOCK=y | ||
| 541 | # CONFIG_FTL is not set | ||
| 542 | # CONFIG_NFTL is not set | ||
| 543 | # CONFIG_INFTL is not set | ||
| 544 | # CONFIG_RFD_FTL is not set | ||
| 545 | # CONFIG_SSFDC is not set | ||
| 546 | CONFIG_MTD_OOPS=y | ||
| 547 | |||
| 548 | # | ||
| 549 | # RAM/ROM/Flash chip drivers | ||
| 550 | # | ||
| 551 | CONFIG_MTD_CFI=y | ||
| 552 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 553 | CONFIG_MTD_GEN_PROBE=y | ||
| 554 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 555 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 556 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 557 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 558 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 559 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 560 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 561 | CONFIG_MTD_CFI_I1=y | ||
| 562 | CONFIG_MTD_CFI_I2=y | ||
| 563 | # CONFIG_MTD_CFI_I4 is not set | ||
| 564 | # CONFIG_MTD_CFI_I8 is not set | ||
| 565 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 566 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 567 | # CONFIG_MTD_CFI_STAA is not set | ||
| 568 | CONFIG_MTD_CFI_UTIL=y | ||
| 569 | # CONFIG_MTD_RAM is not set | ||
| 570 | # CONFIG_MTD_ROM is not set | ||
| 571 | # CONFIG_MTD_ABSENT is not set | ||
| 572 | |||
| 573 | # | ||
| 574 | # Mapping drivers for chip access | ||
| 575 | # | ||
| 576 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 577 | # CONFIG_MTD_PHYSMAP is not set | ||
| 578 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 579 | # CONFIG_MTD_OMAP_NOR is not set | ||
| 580 | # CONFIG_MTD_PLATRAM is not set | ||
| 581 | |||
| 582 | # | ||
| 583 | # Self-contained MTD device drivers | ||
| 584 | # | ||
| 585 | # CONFIG_MTD_DATAFLASH is not set | ||
| 586 | # CONFIG_MTD_M25P80 is not set | ||
| 587 | # CONFIG_MTD_SLRAM is not set | ||
| 588 | # CONFIG_MTD_PHRAM is not set | ||
| 589 | # CONFIG_MTD_MTDRAM is not set | ||
| 590 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 591 | |||
| 592 | # | ||
| 593 | # Disk-On-Chip Device Drivers | ||
| 594 | # | ||
| 595 | # CONFIG_MTD_DOC2000 is not set | ||
| 596 | # CONFIG_MTD_DOC2001 is not set | ||
| 597 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 598 | # CONFIG_MTD_NAND is not set | ||
| 599 | CONFIG_MTD_ONENAND=y | ||
| 600 | # CONFIG_MTD_ONENAND_VERIFY_WRITE is not set | ||
| 601 | # CONFIG_MTD_ONENAND_GENERIC is not set | ||
| 602 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 603 | # CONFIG_MTD_ONENAND_OTP is not set | ||
| 604 | # CONFIG_MTD_ONENAND_2X_PROGRAM is not set | ||
| 605 | # CONFIG_MTD_ONENAND_SIM is not set | ||
| 606 | |||
| 607 | # | ||
| 608 | # LPDDR flash memory drivers | ||
| 609 | # | ||
| 610 | # CONFIG_MTD_LPDDR is not set | ||
| 611 | |||
| 612 | # | ||
| 613 | # UBI - Unsorted block images | ||
| 614 | # | ||
| 615 | CONFIG_MTD_UBI=y | ||
| 616 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 617 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
| 618 | # CONFIG_MTD_UBI_GLUEBI is not set | ||
| 619 | |||
| 620 | # | ||
| 621 | # UBI debugging options | ||
| 622 | # | ||
| 623 | # CONFIG_MTD_UBI_DEBUG is not set | ||
| 624 | # CONFIG_PARPORT is not set | ||
| 625 | CONFIG_BLK_DEV=y | ||
| 626 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 627 | CONFIG_BLK_DEV_LOOP=y | ||
| 628 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 629 | # CONFIG_BLK_DEV_NBD is not set | ||
| 630 | # CONFIG_BLK_DEV_UB is not set | ||
| 631 | CONFIG_BLK_DEV_RAM=y | ||
| 632 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 633 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 634 | # CONFIG_BLK_DEV_XIP is not set | ||
| 635 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 636 | # CONFIG_ATA_OVER_ETH is not set | ||
| 637 | CONFIG_MISC_DEVICES=y | ||
| 638 | # CONFIG_ICS932S401 is not set | ||
| 639 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 640 | # CONFIG_C2PORT is not set | ||
| 641 | |||
| 642 | # | ||
| 643 | # EEPROM support | ||
| 644 | # | ||
| 645 | # CONFIG_EEPROM_AT24 is not set | ||
| 646 | # CONFIG_EEPROM_AT25 is not set | ||
| 647 | # CONFIG_EEPROM_LEGACY is not set | ||
| 648 | # CONFIG_EEPROM_93CX6 is not set | ||
| 649 | CONFIG_HAVE_IDE=y | ||
| 650 | # CONFIG_IDE is not set | ||
| 651 | |||
| 652 | # | ||
| 653 | # SCSI device support | ||
| 654 | # | ||
| 655 | # CONFIG_RAID_ATTRS is not set | ||
| 656 | CONFIG_SCSI=m | ||
| 657 | CONFIG_SCSI_DMA=y | ||
| 658 | # CONFIG_SCSI_TGT is not set | ||
| 659 | # CONFIG_SCSI_NETLINK is not set | ||
| 660 | CONFIG_SCSI_PROC_FS=y | ||
| 661 | |||
| 662 | # | ||
| 663 | # SCSI support type (disk, tape, CD-ROM) | ||
| 664 | # | ||
| 665 | CONFIG_BLK_DEV_SD=m | ||
| 666 | # CONFIG_CHR_DEV_ST is not set | ||
| 667 | # CONFIG_CHR_DEV_OSST is not set | ||
| 668 | # CONFIG_BLK_DEV_SR is not set | ||
| 669 | # CONFIG_CHR_DEV_SG is not set | ||
| 670 | # CONFIG_CHR_DEV_SCH is not set | ||
| 671 | |||
| 672 | # | ||
| 673 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 674 | # | ||
| 675 | CONFIG_SCSI_MULTI_LUN=y | ||
| 676 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 677 | # CONFIG_SCSI_LOGGING is not set | ||
| 678 | CONFIG_SCSI_SCAN_ASYNC=y | ||
| 679 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 680 | |||
| 681 | # | ||
| 682 | # SCSI Transports | ||
| 683 | # | ||
| 684 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 685 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 686 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 687 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 688 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 689 | CONFIG_SCSI_LOWLEVEL=y | ||
| 690 | # CONFIG_ISCSI_TCP is not set | ||
| 691 | # CONFIG_LIBFC is not set | ||
| 692 | # CONFIG_SCSI_DEBUG is not set | ||
| 693 | # CONFIG_SCSI_DH is not set | ||
| 694 | # CONFIG_ATA is not set | ||
| 695 | # CONFIG_MD is not set | ||
| 696 | CONFIG_NETDEVICES=y | ||
| 697 | # CONFIG_DUMMY is not set | ||
| 698 | # CONFIG_BONDING is not set | ||
| 699 | # CONFIG_MACVLAN is not set | ||
| 700 | # CONFIG_EQUALIZER is not set | ||
| 701 | CONFIG_TUN=m | ||
| 702 | # CONFIG_VETH is not set | ||
| 703 | # CONFIG_PHYLIB is not set | ||
| 704 | CONFIG_NET_ETHERNET=y | ||
| 705 | CONFIG_MII=m | ||
| 706 | # CONFIG_AX88796 is not set | ||
| 707 | CONFIG_SMC91X=m | ||
| 708 | # CONFIG_DM9000 is not set | ||
| 709 | # CONFIG_ENC28J60 is not set | ||
| 710 | # CONFIG_SMC911X is not set | ||
| 711 | # CONFIG_SMSC911X is not set | ||
| 712 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 713 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 714 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 715 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 716 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 717 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 718 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 719 | # CONFIG_B44 is not set | ||
| 720 | # CONFIG_NETDEV_1000 is not set | ||
| 721 | # CONFIG_NETDEV_10000 is not set | ||
| 722 | |||
| 723 | # | ||
| 724 | # Wireless LAN | ||
| 725 | # | ||
| 726 | # CONFIG_WLAN_PRE80211 is not set | ||
| 727 | CONFIG_WLAN_80211=y | ||
| 728 | # CONFIG_LIBERTAS is not set | ||
| 729 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 730 | # CONFIG_USB_ZD1201 is not set | ||
| 731 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 732 | # CONFIG_RTL8187 is not set | ||
| 733 | # CONFIG_MAC80211_HWSIM is not set | ||
| 734 | # CONFIG_P54_COMMON is not set | ||
| 735 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 736 | # CONFIG_HOSTAP is not set | ||
| 737 | # CONFIG_B43 is not set | ||
| 738 | # CONFIG_B43LEGACY is not set | ||
| 739 | # CONFIG_ZD1211RW is not set | ||
| 740 | # CONFIG_RT2X00 is not set | ||
| 741 | |||
| 742 | # | ||
| 743 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 744 | # | ||
| 745 | |||
| 746 | # | ||
| 747 | # USB Network Adapters | ||
| 748 | # | ||
| 749 | # CONFIG_USB_CATC is not set | ||
| 750 | # CONFIG_USB_KAWETH is not set | ||
| 751 | # CONFIG_USB_PEGASUS is not set | ||
| 752 | # CONFIG_USB_RTL8150 is not set | ||
| 753 | # CONFIG_USB_USBNET is not set | ||
| 754 | # CONFIG_WAN is not set | ||
| 755 | # CONFIG_PPP is not set | ||
| 756 | # CONFIG_SLIP is not set | ||
| 757 | # CONFIG_NETCONSOLE is not set | ||
| 758 | # CONFIG_NETPOLL is not set | ||
| 759 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 760 | # CONFIG_ISDN is not set | ||
| 761 | |||
| 762 | # | ||
| 763 | # Input device support | ||
| 764 | # | ||
| 765 | CONFIG_INPUT=y | ||
| 766 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 767 | # CONFIG_INPUT_POLLDEV is not set | ||
| 768 | |||
| 769 | # | ||
| 770 | # Userland interfaces | ||
| 771 | # | ||
| 772 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 773 | # CONFIG_INPUT_JOYDEV is not set | ||
| 774 | CONFIG_INPUT_EVDEV=y | ||
| 775 | # CONFIG_INPUT_EVBUG is not set | ||
| 776 | |||
| 777 | # | ||
| 778 | # Input Device Drivers | ||
| 779 | # | ||
| 780 | CONFIG_INPUT_KEYBOARD=y | ||
| 781 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 782 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 783 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 784 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 785 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 786 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 787 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 788 | # CONFIG_INPUT_MOUSE is not set | ||
| 789 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 790 | # CONFIG_INPUT_TABLET is not set | ||
| 791 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 792 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 793 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 794 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 795 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 796 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 797 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 798 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 799 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 800 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 801 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 802 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 803 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 804 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 805 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 806 | CONFIG_INPUT_MISC=y | ||
| 807 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 808 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 809 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 810 | # CONFIG_INPUT_POWERMATE is not set | ||
| 811 | # CONFIG_INPUT_YEALINK is not set | ||
| 812 | # CONFIG_INPUT_CM109 is not set | ||
| 813 | CONFIG_INPUT_UINPUT=m | ||
| 814 | |||
| 815 | # | ||
| 816 | # Hardware I/O ports | ||
| 817 | # | ||
| 818 | # CONFIG_SERIO is not set | ||
| 819 | # CONFIG_GAMEPORT is not set | ||
| 820 | |||
| 821 | # | ||
| 822 | # Character devices | ||
| 823 | # | ||
| 824 | CONFIG_VT=y | ||
| 825 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 826 | CONFIG_VT_CONSOLE=y | ||
| 827 | CONFIG_HW_CONSOLE=y | ||
| 828 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 829 | CONFIG_DEVKMEM=y | ||
| 830 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 831 | |||
| 832 | # | ||
| 833 | # Serial drivers | ||
| 834 | # | ||
| 835 | CONFIG_SERIAL_8250=y | ||
| 836 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 837 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
| 838 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 839 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 840 | |||
| 841 | # | ||
| 842 | # Non-8250 serial port support | ||
| 843 | # | ||
| 844 | CONFIG_SERIAL_CORE=y | ||
| 845 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 846 | CONFIG_UNIX98_PTYS=y | ||
| 847 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 848 | # CONFIG_LEGACY_PTYS is not set | ||
| 849 | # CONFIG_IPMI_HANDLER is not set | ||
| 850 | CONFIG_HW_RANDOM=m | ||
| 851 | # CONFIG_R3964 is not set | ||
| 852 | # CONFIG_RAW_DRIVER is not set | ||
| 853 | # CONFIG_TCG_TPM is not set | ||
| 854 | CONFIG_I2C=y | ||
| 855 | CONFIG_I2C_BOARDINFO=y | ||
| 856 | CONFIG_I2C_CHARDEV=y | ||
| 857 | CONFIG_I2C_HELPER_AUTO=y | ||
| 858 | |||
| 859 | # | ||
| 860 | # I2C Hardware Bus support | ||
| 861 | # | ||
| 862 | |||
| 863 | # | ||
| 864 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 865 | # | ||
| 866 | # CONFIG_I2C_GPIO is not set | ||
| 867 | # CONFIG_I2C_OCORES is not set | ||
| 868 | CONFIG_I2C_OMAP=y | ||
| 869 | # CONFIG_I2C_SIMTEC is not set | ||
| 870 | |||
| 871 | # | ||
| 872 | # External I2C/SMBus adapter drivers | ||
| 873 | # | ||
| 874 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 875 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 876 | # CONFIG_I2C_TINY_USB is not set | ||
| 877 | |||
| 878 | # | ||
| 879 | # Other I2C/SMBus bus drivers | ||
| 880 | # | ||
| 881 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 882 | # CONFIG_I2C_STUB is not set | ||
| 883 | |||
| 884 | # | ||
| 885 | # Miscellaneous I2C Chip support | ||
| 886 | # | ||
| 887 | # CONFIG_DS1682 is not set | ||
| 888 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 889 | # CONFIG_PCF8575 is not set | ||
| 890 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 891 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 892 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 893 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 894 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 895 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 896 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 897 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 898 | CONFIG_SPI=y | ||
| 899 | # CONFIG_SPI_DEBUG is not set | ||
| 900 | CONFIG_SPI_MASTER=y | ||
| 901 | |||
| 902 | # | ||
| 903 | # SPI Master Controller Drivers | ||
| 904 | # | ||
| 905 | # CONFIG_SPI_BITBANG is not set | ||
| 906 | # CONFIG_SPI_GPIO is not set | ||
| 907 | CONFIG_SPI_OMAP24XX=y | ||
| 908 | |||
| 909 | # | ||
| 910 | # SPI Protocol Masters | ||
| 911 | # | ||
| 912 | # CONFIG_SPI_SPIDEV is not set | ||
| 913 | # CONFIG_SPI_TLE62X0 is not set | ||
| 914 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 915 | CONFIG_GPIOLIB=y | ||
| 916 | # CONFIG_DEBUG_GPIO is not set | ||
| 917 | CONFIG_GPIO_SYSFS=y | ||
| 918 | |||
| 919 | # | ||
| 920 | # Memory mapped GPIO expanders: | ||
| 921 | # | ||
| 922 | |||
| 923 | # | ||
| 924 | # I2C GPIO expanders: | ||
| 925 | # | ||
| 926 | # CONFIG_GPIO_MAX732X is not set | ||
| 927 | # CONFIG_GPIO_PCA953X is not set | ||
| 928 | # CONFIG_GPIO_PCF857X is not set | ||
| 929 | CONFIG_GPIO_TWL4030=y | ||
| 930 | |||
| 931 | # | ||
| 932 | # PCI GPIO expanders: | ||
| 933 | # | ||
| 934 | |||
| 935 | # | ||
| 936 | # SPI GPIO expanders: | ||
| 937 | # | ||
| 938 | # CONFIG_GPIO_MAX7301 is not set | ||
| 939 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 940 | # CONFIG_W1 is not set | ||
| 941 | # CONFIG_POWER_SUPPLY is not set | ||
| 942 | CONFIG_HWMON=y | ||
| 943 | # CONFIG_HWMON_VID is not set | ||
| 944 | # CONFIG_SENSORS_AD7414 is not set | ||
| 945 | # CONFIG_SENSORS_AD7418 is not set | ||
| 946 | # CONFIG_SENSORS_ADCXX is not set | ||
| 947 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 948 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 949 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 950 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 951 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 952 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 953 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 954 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 955 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 956 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 957 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 958 | # CONFIG_SENSORS_DS1621 is not set | ||
| 959 | # CONFIG_SENSORS_F71805F is not set | ||
| 960 | # CONFIG_SENSORS_F71882FG is not set | ||
| 961 | # CONFIG_SENSORS_F75375S is not set | ||
| 962 | # CONFIG_SENSORS_GL518SM is not set | ||
| 963 | # CONFIG_SENSORS_GL520SM is not set | ||
| 964 | # CONFIG_SENSORS_IT87 is not set | ||
| 965 | # CONFIG_SENSORS_LM63 is not set | ||
| 966 | # CONFIG_SENSORS_LM70 is not set | ||
| 967 | # CONFIG_SENSORS_LM75 is not set | ||
| 968 | # CONFIG_SENSORS_LM77 is not set | ||
| 969 | # CONFIG_SENSORS_LM78 is not set | ||
| 970 | # CONFIG_SENSORS_LM80 is not set | ||
| 971 | # CONFIG_SENSORS_LM83 is not set | ||
| 972 | # CONFIG_SENSORS_LM85 is not set | ||
| 973 | # CONFIG_SENSORS_LM87 is not set | ||
| 974 | # CONFIG_SENSORS_LM90 is not set | ||
| 975 | # CONFIG_SENSORS_LM92 is not set | ||
| 976 | # CONFIG_SENSORS_LM93 is not set | ||
| 977 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 978 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 979 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 980 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 981 | # CONFIG_SENSORS_PC87360 is not set | ||
| 982 | # CONFIG_SENSORS_PC87427 is not set | ||
| 983 | # CONFIG_SENSORS_DME1737 is not set | ||
| 984 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 985 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 986 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 987 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 988 | # CONFIG_SENSORS_THMC50 is not set | ||
| 989 | # CONFIG_SENSORS_VT1211 is not set | ||
| 990 | # CONFIG_SENSORS_W83781D is not set | ||
| 991 | # CONFIG_SENSORS_W83791D is not set | ||
| 992 | # CONFIG_SENSORS_W83792D is not set | ||
| 993 | # CONFIG_SENSORS_W83793 is not set | ||
| 994 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 995 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 996 | # CONFIG_SENSORS_W83627HF is not set | ||
| 997 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 998 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 999 | # CONFIG_THERMAL is not set | ||
| 1000 | # CONFIG_THERMAL_HWMON is not set | ||
| 1001 | CONFIG_WATCHDOG=y | ||
| 1002 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 1003 | |||
| 1004 | # | ||
| 1005 | # Watchdog Device Drivers | ||
| 1006 | # | ||
| 1007 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 1008 | CONFIG_OMAP_WATCHDOG=m | ||
| 1009 | |||
| 1010 | # | ||
| 1011 | # USB-based Watchdog Cards | ||
| 1012 | # | ||
| 1013 | # CONFIG_USBPCWATCHDOG is not set | ||
| 1014 | CONFIG_SSB_POSSIBLE=y | ||
| 1015 | |||
| 1016 | # | ||
| 1017 | # Sonics Silicon Backplane | ||
| 1018 | # | ||
| 1019 | # CONFIG_SSB is not set | ||
| 1020 | |||
| 1021 | # | ||
| 1022 | # Multifunction device drivers | ||
| 1023 | # | ||
| 1024 | # CONFIG_MFD_CORE is not set | ||
| 1025 | # CONFIG_MFD_SM501 is not set | ||
| 1026 | # CONFIG_MFD_ASIC3 is not set | ||
| 1027 | # CONFIG_HTC_EGPIO is not set | ||
| 1028 | # CONFIG_HTC_PASIC3 is not set | ||
| 1029 | # CONFIG_TPS65010 is not set | ||
| 1030 | CONFIG_TWL4030_CORE=y | ||
| 1031 | # CONFIG_MFD_TMIO is not set | ||
| 1032 | # CONFIG_MFD_T7L66XB is not set | ||
| 1033 | # CONFIG_MFD_TC6387XB is not set | ||
| 1034 | # CONFIG_MFD_TC6393XB is not set | ||
| 1035 | # CONFIG_PMIC_DA903X is not set | ||
| 1036 | # CONFIG_MFD_WM8400 is not set | ||
| 1037 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1038 | # CONFIG_MFD_PCF50633 is not set | ||
| 1039 | |||
| 1040 | # | ||
| 1041 | # Multimedia devices | ||
| 1042 | # | ||
| 1043 | |||
| 1044 | # | ||
| 1045 | # Multimedia core support | ||
| 1046 | # | ||
| 1047 | CONFIG_VIDEO_DEV=m | ||
| 1048 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1049 | CONFIG_VIDEO_ALLOW_V4L1=y | ||
| 1050 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1051 | # CONFIG_DVB_CORE is not set | ||
| 1052 | CONFIG_VIDEO_MEDIA=m | ||
| 1053 | |||
| 1054 | # | ||
| 1055 | # Multimedia drivers | ||
| 1056 | # | ||
| 1057 | # CONFIG_MEDIA_ATTACH is not set | ||
| 1058 | CONFIG_MEDIA_TUNER=m | ||
| 1059 | # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set | ||
| 1060 | CONFIG_MEDIA_TUNER_SIMPLE=m | ||
| 1061 | CONFIG_MEDIA_TUNER_TDA8290=m | ||
| 1062 | CONFIG_MEDIA_TUNER_TDA9887=m | ||
| 1063 | CONFIG_MEDIA_TUNER_TEA5761=m | ||
| 1064 | CONFIG_MEDIA_TUNER_TEA5767=m | ||
| 1065 | CONFIG_MEDIA_TUNER_MT20XX=m | ||
| 1066 | CONFIG_MEDIA_TUNER_XC2028=m | ||
| 1067 | CONFIG_MEDIA_TUNER_XC5000=m | ||
| 1068 | CONFIG_VIDEO_V4L2=m | ||
| 1069 | CONFIG_VIDEO_V4L1=m | ||
| 1070 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1071 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1072 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1073 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | ||
| 1074 | # CONFIG_VIDEO_VIVI is not set | ||
| 1075 | # CONFIG_VIDEO_CPIA is not set | ||
| 1076 | # CONFIG_VIDEO_CPIA2 is not set | ||
| 1077 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1078 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1079 | # CONFIG_SOC_CAMERA is not set | ||
| 1080 | CONFIG_V4L_USB_DRIVERS=y | ||
| 1081 | # CONFIG_USB_VIDEO_CLASS is not set | ||
| 1082 | # CONFIG_USB_GSPCA is not set | ||
| 1083 | # CONFIG_VIDEO_PVRUSB2 is not set | ||
| 1084 | # CONFIG_VIDEO_EM28XX is not set | ||
| 1085 | # CONFIG_VIDEO_USBVISION is not set | ||
| 1086 | # CONFIG_USB_VICAM is not set | ||
| 1087 | # CONFIG_USB_IBMCAM is not set | ||
| 1088 | # CONFIG_USB_KONICAWC is not set | ||
| 1089 | # CONFIG_USB_QUICKCAM_MESSENGER is not set | ||
| 1090 | # CONFIG_USB_ET61X251 is not set | ||
| 1091 | # CONFIG_VIDEO_OVCAMCHIP is not set | ||
| 1092 | # CONFIG_USB_OV511 is not set | ||
| 1093 | # CONFIG_USB_SE401 is not set | ||
| 1094 | # CONFIG_USB_SN9C102 is not set | ||
| 1095 | # CONFIG_USB_STV680 is not set | ||
| 1096 | # CONFIG_USB_ZC0301 is not set | ||
| 1097 | # CONFIG_USB_PWC is not set | ||
| 1098 | # CONFIG_USB_ZR364XX is not set | ||
| 1099 | # CONFIG_USB_STKWEBCAM is not set | ||
| 1100 | # CONFIG_USB_S2255 is not set | ||
| 1101 | CONFIG_RADIO_ADAPTERS=y | ||
| 1102 | # CONFIG_USB_DSBR is not set | ||
| 1103 | # CONFIG_USB_SI470X is not set | ||
| 1104 | # CONFIG_USB_MR800 is not set | ||
| 1105 | # CONFIG_RADIO_TEA5764 is not set | ||
| 1106 | # CONFIG_DAB is not set | ||
| 1107 | |||
| 1108 | # | ||
| 1109 | # Graphics support | ||
| 1110 | # | ||
| 1111 | # CONFIG_VGASTATE is not set | ||
| 1112 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1113 | # CONFIG_FB is not set | ||
| 1114 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 1115 | |||
| 1116 | # | ||
| 1117 | # Display device support | ||
| 1118 | # | ||
| 1119 | CONFIG_DISPLAY_SUPPORT=y | ||
| 1120 | |||
| 1121 | # | ||
| 1122 | # Display hardware drivers | ||
| 1123 | # | ||
| 1124 | |||
| 1125 | # | ||
| 1126 | # Console display driver support | ||
| 1127 | # | ||
| 1128 | # CONFIG_VGA_CONSOLE is not set | ||
| 1129 | CONFIG_DUMMY_CONSOLE=y | ||
| 1130 | CONFIG_SOUND=y | ||
| 1131 | # CONFIG_SOUND_OSS_CORE is not set | ||
| 1132 | CONFIG_SND=y | ||
| 1133 | CONFIG_SND_TIMER=y | ||
| 1134 | CONFIG_SND_PCM=y | ||
| 1135 | # CONFIG_SND_SEQUENCER is not set | ||
| 1136 | # CONFIG_SND_MIXER_OSS is not set | ||
| 1137 | # CONFIG_SND_PCM_OSS is not set | ||
| 1138 | # CONFIG_SND_HRTIMER is not set | ||
| 1139 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1140 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1141 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1142 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 1143 | # CONFIG_SND_DEBUG is not set | ||
| 1144 | CONFIG_SND_DRIVERS=y | ||
| 1145 | # CONFIG_SND_DUMMY is not set | ||
| 1146 | # CONFIG_SND_MTPAV is not set | ||
| 1147 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1148 | # CONFIG_SND_MPU401 is not set | ||
| 1149 | CONFIG_SND_ARM=y | ||
| 1150 | CONFIG_SND_SPI=y | ||
| 1151 | # CONFIG_SND_USB is not set | ||
| 1152 | CONFIG_SND_SOC=y | ||
| 1153 | CONFIG_SND_OMAP_SOC=y | ||
| 1154 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1155 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1156 | # CONFIG_SOUND_PRIME is not set | ||
| 1157 | CONFIG_HID_SUPPORT=y | ||
| 1158 | CONFIG_HID=m | ||
| 1159 | # CONFIG_HID_DEBUG is not set | ||
| 1160 | # CONFIG_HIDRAW is not set | ||
| 1161 | |||
| 1162 | # | ||
| 1163 | # USB Input Devices | ||
| 1164 | # | ||
| 1165 | CONFIG_USB_HID=m | ||
| 1166 | # CONFIG_HID_PID is not set | ||
| 1167 | # CONFIG_USB_HIDDEV is not set | ||
| 1168 | |||
| 1169 | # | ||
| 1170 | # USB HID Boot Protocol drivers | ||
| 1171 | # | ||
| 1172 | # CONFIG_USB_KBD is not set | ||
| 1173 | # CONFIG_USB_MOUSE is not set | ||
| 1174 | |||
| 1175 | # | ||
| 1176 | # Special HID drivers | ||
| 1177 | # | ||
| 1178 | CONFIG_HID_COMPAT=y | ||
| 1179 | CONFIG_HID_A4TECH=m | ||
| 1180 | CONFIG_HID_APPLE=m | ||
| 1181 | CONFIG_HID_BELKIN=m | ||
| 1182 | CONFIG_HID_CHERRY=m | ||
| 1183 | CONFIG_HID_CHICONY=m | ||
| 1184 | CONFIG_HID_CYPRESS=m | ||
| 1185 | CONFIG_HID_EZKEY=m | ||
| 1186 | CONFIG_HID_GYRATION=m | ||
| 1187 | CONFIG_HID_LOGITECH=m | ||
| 1188 | # CONFIG_LOGITECH_FF is not set | ||
| 1189 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1190 | CONFIG_HID_MICROSOFT=m | ||
| 1191 | CONFIG_HID_MONTEREY=m | ||
| 1192 | # CONFIG_HID_NTRIG is not set | ||
| 1193 | CONFIG_HID_PANTHERLORD=m | ||
| 1194 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1195 | CONFIG_HID_PETALYNX=m | ||
| 1196 | CONFIG_HID_SAMSUNG=m | ||
| 1197 | CONFIG_HID_SONY=m | ||
| 1198 | CONFIG_HID_SUNPLUS=m | ||
| 1199 | # CONFIG_GREENASIA_FF is not set | ||
| 1200 | # CONFIG_HID_TOPSEED is not set | ||
| 1201 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1202 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1203 | CONFIG_USB_SUPPORT=y | ||
| 1204 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1205 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1206 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1207 | CONFIG_USB=y | ||
| 1208 | CONFIG_USB_DEBUG=y | ||
| 1209 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 1210 | |||
| 1211 | # | ||
| 1212 | # Miscellaneous USB options | ||
| 1213 | # | ||
| 1214 | CONFIG_USB_DEVICEFS=y | ||
| 1215 | CONFIG_USB_DEVICE_CLASS=y | ||
| 1216 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1217 | CONFIG_USB_SUSPEND=y | ||
| 1218 | CONFIG_USB_OTG=y | ||
| 1219 | CONFIG_USB_OTG_WHITELIST=y | ||
| 1220 | CONFIG_USB_OTG_BLACKLIST_HUB=y | ||
| 1221 | CONFIG_USB_MON=y | ||
| 1222 | # CONFIG_USB_WUSB is not set | ||
| 1223 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1224 | |||
| 1225 | # | ||
| 1226 | # USB Host Controller Drivers | ||
| 1227 | # | ||
| 1228 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1229 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1230 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1231 | # CONFIG_USB_OHCI_HCD is not set | ||
| 1232 | # CONFIG_USB_SL811_HCD is not set | ||
| 1233 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1234 | # CONFIG_USB_HWA_HCD is not set | ||
| 1235 | CONFIG_USB_MUSB_HDRC=y | ||
| 1236 | CONFIG_USB_MUSB_SOC=y | ||
| 1237 | |||
| 1238 | # | ||
| 1239 | # OMAP 343x high speed USB support | ||
| 1240 | # | ||
| 1241 | # CONFIG_USB_MUSB_HOST is not set | ||
| 1242 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
| 1243 | CONFIG_USB_MUSB_OTG=y | ||
| 1244 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 1245 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
| 1246 | # CONFIG_MUSB_PIO_ONLY is not set | ||
| 1247 | CONFIG_USB_INVENTRA_DMA=y | ||
| 1248 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
| 1249 | # CONFIG_USB_MUSB_DEBUG is not set | ||
| 1250 | |||
| 1251 | # | ||
| 1252 | # USB Device Class drivers | ||
| 1253 | # | ||
| 1254 | # CONFIG_USB_ACM is not set | ||
| 1255 | # CONFIG_USB_PRINTER is not set | ||
| 1256 | # CONFIG_USB_WDM is not set | ||
| 1257 | # CONFIG_USB_TMC is not set | ||
| 1258 | |||
| 1259 | # | ||
| 1260 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1261 | # | ||
| 1262 | |||
| 1263 | # | ||
| 1264 | # see USB_STORAGE Help for more information | ||
| 1265 | # | ||
| 1266 | CONFIG_USB_STORAGE=m | ||
| 1267 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1268 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1269 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1270 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1271 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1272 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1273 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1274 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1275 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1276 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1277 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1278 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1279 | CONFIG_USB_LIBUSUAL=y | ||
| 1280 | |||
| 1281 | # | ||
| 1282 | # USB Imaging devices | ||
| 1283 | # | ||
| 1284 | # CONFIG_USB_MDC800 is not set | ||
| 1285 | # CONFIG_USB_MICROTEK is not set | ||
| 1286 | |||
| 1287 | # | ||
| 1288 | # USB port drivers | ||
| 1289 | # | ||
| 1290 | # CONFIG_USB_SERIAL is not set | ||
| 1291 | |||
| 1292 | # | ||
| 1293 | # USB Miscellaneous drivers | ||
| 1294 | # | ||
| 1295 | # CONFIG_USB_EMI62 is not set | ||
| 1296 | # CONFIG_USB_EMI26 is not set | ||
| 1297 | # CONFIG_USB_ADUTUX is not set | ||
| 1298 | # CONFIG_USB_SEVSEG is not set | ||
| 1299 | # CONFIG_USB_RIO500 is not set | ||
| 1300 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1301 | # CONFIG_USB_LCD is not set | ||
| 1302 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1303 | # CONFIG_USB_LED is not set | ||
| 1304 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1305 | # CONFIG_USB_CYTHERM is not set | ||
| 1306 | # CONFIG_USB_PHIDGET is not set | ||
| 1307 | # CONFIG_USB_IDMOUSE is not set | ||
| 1308 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1309 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1310 | # CONFIG_USB_LD is not set | ||
| 1311 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1312 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1313 | CONFIG_USB_TEST=m | ||
| 1314 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1315 | # CONFIG_USB_VST is not set | ||
| 1316 | CONFIG_USB_GADGET=m | ||
| 1317 | CONFIG_USB_GADGET_DEBUG=y | ||
| 1318 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 1319 | CONFIG_USB_GADGET_DEBUG_FS=y | ||
| 1320 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1321 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1322 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1323 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1324 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1325 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1326 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1327 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1328 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1329 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1330 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1331 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1332 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1333 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1334 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1335 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1336 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1337 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1338 | CONFIG_USB_GADGET_DUALSPEED=y | ||
| 1339 | CONFIG_USB_ZERO=m | ||
| 1340 | # CONFIG_USB_ZERO_HNPTEST is not set | ||
| 1341 | # CONFIG_USB_ETH is not set | ||
| 1342 | # CONFIG_USB_GADGETFS is not set | ||
| 1343 | CONFIG_USB_FILE_STORAGE=m | ||
| 1344 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
| 1345 | # CONFIG_USB_G_SERIAL is not set | ||
| 1346 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1347 | # CONFIG_USB_G_PRINTER is not set | ||
| 1348 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1349 | |||
| 1350 | # | ||
| 1351 | # OTG and related infrastructure | ||
| 1352 | # | ||
| 1353 | CONFIG_USB_OTG_UTILS=y | ||
| 1354 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1355 | # CONFIG_ISP1301_OMAP is not set | ||
| 1356 | CONFIG_TWL4030_USB=y | ||
| 1357 | CONFIG_MMC=m | ||
| 1358 | # CONFIG_MMC_DEBUG is not set | ||
| 1359 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1360 | |||
| 1361 | # | ||
| 1362 | # MMC/SD/SDIO Card Drivers | ||
| 1363 | # | ||
| 1364 | CONFIG_MMC_BLOCK=m | ||
| 1365 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1366 | # CONFIG_SDIO_UART is not set | ||
| 1367 | # CONFIG_MMC_TEST is not set | ||
| 1368 | |||
| 1369 | # | ||
| 1370 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1371 | # | ||
| 1372 | # CONFIG_MMC_SDHCI is not set | ||
| 1373 | # CONFIG_MMC_OMAP is not set | ||
| 1374 | CONFIG_MMC_OMAP_HS=m | ||
| 1375 | # CONFIG_MMC_SPI is not set | ||
| 1376 | # CONFIG_MEMSTICK is not set | ||
| 1377 | # CONFIG_ACCESSIBILITY is not set | ||
| 1378 | CONFIG_NEW_LEDS=y | ||
| 1379 | CONFIG_LEDS_CLASS=m | ||
| 1380 | |||
| 1381 | # | ||
| 1382 | # LED drivers | ||
| 1383 | # | ||
| 1384 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1385 | # CONFIG_LEDS_GPIO is not set | ||
| 1386 | # CONFIG_LEDS_PCA955X is not set | ||
| 1387 | |||
| 1388 | # | ||
| 1389 | # LED Triggers | ||
| 1390 | # | ||
| 1391 | # CONFIG_LEDS_TRIGGERS is not set | ||
| 1392 | CONFIG_RTC_LIB=y | ||
| 1393 | CONFIG_RTC_CLASS=m | ||
| 1394 | |||
| 1395 | # | ||
| 1396 | # RTC interfaces | ||
| 1397 | # | ||
| 1398 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1399 | CONFIG_RTC_INTF_PROC=y | ||
| 1400 | CONFIG_RTC_INTF_DEV=y | ||
| 1401 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1402 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1403 | |||
| 1404 | # | ||
| 1405 | # I2C RTC drivers | ||
| 1406 | # | ||
| 1407 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1408 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1409 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1410 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1411 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1412 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1413 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1414 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1415 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1416 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1417 | CONFIG_RTC_DRV_TWL4030=m | ||
| 1418 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1419 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1420 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1421 | |||
| 1422 | # | ||
| 1423 | # SPI RTC drivers | ||
| 1424 | # | ||
| 1425 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1426 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1427 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1428 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1429 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1430 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1431 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1432 | |||
| 1433 | # | ||
| 1434 | # Platform RTC drivers | ||
| 1435 | # | ||
| 1436 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1437 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1438 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1439 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1440 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1441 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1442 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1443 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1444 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1445 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1446 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1447 | |||
| 1448 | # | ||
| 1449 | # on-CPU RTC drivers | ||
| 1450 | # | ||
| 1451 | # CONFIG_DMADEVICES is not set | ||
| 1452 | # CONFIG_REGULATOR is not set | ||
| 1453 | # CONFIG_UIO is not set | ||
| 1454 | # CONFIG_STAGING is not set | ||
| 1455 | |||
| 1456 | # | ||
| 1457 | # File systems | ||
| 1458 | # | ||
| 1459 | CONFIG_EXT2_FS=m | ||
| 1460 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1461 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1462 | CONFIG_EXT3_FS=m | ||
| 1463 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1464 | # CONFIG_EXT4_FS is not set | ||
| 1465 | CONFIG_JBD=m | ||
| 1466 | # CONFIG_JBD_DEBUG is not set | ||
| 1467 | # CONFIG_REISERFS_FS is not set | ||
| 1468 | # CONFIG_JFS_FS is not set | ||
| 1469 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1470 | CONFIG_FILE_LOCKING=y | ||
| 1471 | # CONFIG_XFS_FS is not set | ||
| 1472 | # CONFIG_OCFS2_FS is not set | ||
| 1473 | # CONFIG_BTRFS_FS is not set | ||
| 1474 | CONFIG_DNOTIFY=y | ||
| 1475 | CONFIG_INOTIFY=y | ||
| 1476 | CONFIG_INOTIFY_USER=y | ||
| 1477 | CONFIG_QUOTA=y | ||
| 1478 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
| 1479 | CONFIG_PRINT_QUOTA_WARNING=y | ||
| 1480 | CONFIG_QUOTA_TREE=y | ||
| 1481 | # CONFIG_QFMT_V1 is not set | ||
| 1482 | CONFIG_QFMT_V2=y | ||
| 1483 | CONFIG_QUOTACTL=y | ||
| 1484 | # CONFIG_AUTOFS_FS is not set | ||
| 1485 | # CONFIG_AUTOFS4_FS is not set | ||
| 1486 | CONFIG_FUSE_FS=m | ||
| 1487 | |||
| 1488 | # | ||
| 1489 | # CD-ROM/DVD Filesystems | ||
| 1490 | # | ||
| 1491 | # CONFIG_ISO9660_FS is not set | ||
| 1492 | # CONFIG_UDF_FS is not set | ||
| 1493 | |||
| 1494 | # | ||
| 1495 | # DOS/FAT/NT Filesystems | ||
| 1496 | # | ||
| 1497 | CONFIG_FAT_FS=m | ||
| 1498 | CONFIG_MSDOS_FS=m | ||
| 1499 | CONFIG_VFAT_FS=m | ||
| 1500 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1501 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1502 | # CONFIG_NTFS_FS is not set | ||
| 1503 | |||
| 1504 | # | ||
| 1505 | # Pseudo filesystems | ||
| 1506 | # | ||
| 1507 | CONFIG_PROC_FS=y | ||
| 1508 | CONFIG_PROC_SYSCTL=y | ||
| 1509 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1510 | CONFIG_SYSFS=y | ||
| 1511 | CONFIG_TMPFS=y | ||
| 1512 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1513 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1514 | # CONFIG_CONFIGFS_FS is not set | ||
| 1515 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1516 | # CONFIG_ADFS_FS is not set | ||
| 1517 | # CONFIG_AFFS_FS is not set | ||
| 1518 | # CONFIG_HFS_FS is not set | ||
| 1519 | # CONFIG_HFSPLUS_FS is not set | ||
| 1520 | # CONFIG_BEFS_FS is not set | ||
| 1521 | # CONFIG_BFS_FS is not set | ||
| 1522 | # CONFIG_EFS_FS is not set | ||
| 1523 | # CONFIG_JFFS2_FS is not set | ||
| 1524 | CONFIG_UBIFS_FS=y | ||
| 1525 | # CONFIG_UBIFS_FS_XATTR is not set | ||
| 1526 | # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | ||
| 1527 | CONFIG_UBIFS_FS_LZO=y | ||
| 1528 | CONFIG_UBIFS_FS_ZLIB=y | ||
| 1529 | # CONFIG_UBIFS_FS_DEBUG is not set | ||
| 1530 | CONFIG_CRAMFS=y | ||
| 1531 | # CONFIG_SQUASHFS is not set | ||
| 1532 | # CONFIG_VXFS_FS is not set | ||
| 1533 | # CONFIG_MINIX_FS is not set | ||
| 1534 | # CONFIG_OMFS_FS is not set | ||
| 1535 | # CONFIG_HPFS_FS is not set | ||
| 1536 | # CONFIG_QNX4FS_FS is not set | ||
| 1537 | # CONFIG_ROMFS_FS is not set | ||
| 1538 | # CONFIG_SYSV_FS is not set | ||
| 1539 | # CONFIG_UFS_FS is not set | ||
| 1540 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1541 | CONFIG_NFS_FS=m | ||
| 1542 | CONFIG_NFS_V3=y | ||
| 1543 | # CONFIG_NFS_V3_ACL is not set | ||
| 1544 | CONFIG_NFS_V4=y | ||
| 1545 | # CONFIG_NFSD is not set | ||
| 1546 | CONFIG_LOCKD=m | ||
| 1547 | CONFIG_LOCKD_V4=y | ||
| 1548 | CONFIG_NFS_COMMON=y | ||
| 1549 | CONFIG_SUNRPC=m | ||
| 1550 | CONFIG_SUNRPC_GSS=m | ||
| 1551 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1552 | CONFIG_RPCSEC_GSS_KRB5=m | ||
| 1553 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1554 | # CONFIG_SMB_FS is not set | ||
| 1555 | # CONFIG_CIFS is not set | ||
| 1556 | # CONFIG_NCP_FS is not set | ||
| 1557 | # CONFIG_CODA_FS is not set | ||
| 1558 | # CONFIG_AFS_FS is not set | ||
| 1559 | |||
| 1560 | # | ||
| 1561 | # Partition Types | ||
| 1562 | # | ||
| 1563 | CONFIG_PARTITION_ADVANCED=y | ||
| 1564 | # CONFIG_ACORN_PARTITION is not set | ||
| 1565 | # CONFIG_OSF_PARTITION is not set | ||
| 1566 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1567 | # CONFIG_ATARI_PARTITION is not set | ||
| 1568 | # CONFIG_MAC_PARTITION is not set | ||
| 1569 | CONFIG_MSDOS_PARTITION=y | ||
| 1570 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1571 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1572 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1573 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1574 | # CONFIG_LDM_PARTITION is not set | ||
| 1575 | # CONFIG_SGI_PARTITION is not set | ||
| 1576 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1577 | # CONFIG_SUN_PARTITION is not set | ||
| 1578 | # CONFIG_KARMA_PARTITION is not set | ||
| 1579 | # CONFIG_EFI_PARTITION is not set | ||
| 1580 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1581 | CONFIG_NLS=y | ||
| 1582 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1583 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1584 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1585 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1586 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1587 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1588 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1589 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1590 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1591 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1592 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1593 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1594 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1595 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1596 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1597 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1598 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1599 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1600 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1601 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1602 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1603 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1604 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1605 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1606 | # CONFIG_NLS_ASCII is not set | ||
| 1607 | CONFIG_NLS_ISO8859_1=y | ||
| 1608 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1609 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1610 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1611 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1612 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1613 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1614 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1615 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1616 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1617 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1618 | # CONFIG_NLS_KOI8_R is not set | ||
| 1619 | # CONFIG_NLS_KOI8_U is not set | ||
| 1620 | # CONFIG_NLS_UTF8 is not set | ||
| 1621 | # CONFIG_DLM is not set | ||
| 1622 | |||
| 1623 | # | ||
| 1624 | # Kernel hacking | ||
| 1625 | # | ||
| 1626 | CONFIG_PRINTK_TIME=y | ||
| 1627 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1628 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1629 | CONFIG_FRAME_WARN=1024 | ||
| 1630 | CONFIG_MAGIC_SYSRQ=y | ||
| 1631 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1632 | CONFIG_DEBUG_FS=y | ||
| 1633 | # CONFIG_HEADERS_CHECK is not set | ||
| 1634 | CONFIG_DEBUG_KERNEL=y | ||
| 1635 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1636 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1637 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1638 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1639 | CONFIG_SCHED_DEBUG=y | ||
| 1640 | # CONFIG_SCHEDSTATS is not set | ||
| 1641 | CONFIG_TIMER_STATS=y | ||
| 1642 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1643 | # CONFIG_DEBUG_SLAB is not set | ||
| 1644 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1645 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1646 | CONFIG_DEBUG_SPINLOCK=y | ||
| 1647 | CONFIG_DEBUG_MUTEXES=y | ||
| 1648 | CONFIG_DEBUG_LOCK_ALLOC=y | ||
| 1649 | CONFIG_PROVE_LOCKING=y | ||
| 1650 | CONFIG_LOCKDEP=y | ||
| 1651 | CONFIG_LOCK_STAT=y | ||
| 1652 | # CONFIG_DEBUG_LOCKDEP is not set | ||
| 1653 | CONFIG_TRACE_IRQFLAGS=y | ||
| 1654 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
| 1655 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1656 | CONFIG_STACKTRACE=y | ||
| 1657 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1658 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1659 | CONFIG_DEBUG_INFO=y | ||
| 1660 | # CONFIG_DEBUG_VM is not set | ||
| 1661 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1662 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1663 | # CONFIG_DEBUG_LIST is not set | ||
| 1664 | # CONFIG_DEBUG_SG is not set | ||
| 1665 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1666 | CONFIG_FRAME_POINTER=y | ||
| 1667 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1668 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1669 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1670 | # CONFIG_KPROBES_SANITY_TEST is not set | ||
| 1671 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1672 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1673 | # CONFIG_LKDTM is not set | ||
| 1674 | # CONFIG_FAULT_INJECTION is not set | ||
| 1675 | # CONFIG_LATENCYTOP is not set | ||
| 1676 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1677 | |||
| 1678 | # | ||
| 1679 | # Tracers | ||
| 1680 | # | ||
| 1681 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1682 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1683 | # CONFIG_SCHED_TRACER is not set | ||
| 1684 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1685 | # CONFIG_BOOT_TRACER is not set | ||
| 1686 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1687 | # CONFIG_STACK_TRACER is not set | ||
| 1688 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1689 | # CONFIG_SAMPLES is not set | ||
| 1690 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1691 | # CONFIG_KGDB is not set | ||
| 1692 | # CONFIG_DEBUG_USER is not set | ||
| 1693 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1694 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1695 | # CONFIG_DEBUG_LL is not set | ||
| 1696 | |||
| 1697 | # | ||
| 1698 | # Security options | ||
| 1699 | # | ||
| 1700 | # CONFIG_KEYS is not set | ||
| 1701 | CONFIG_SECURITY=y | ||
| 1702 | # CONFIG_SECURITYFS is not set | ||
| 1703 | # CONFIG_SECURITY_NETWORK is not set | ||
| 1704 | # CONFIG_SECURITY_PATH is not set | ||
| 1705 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1706 | # CONFIG_SECURITY_ROOTPLUG is not set | ||
| 1707 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1708 | CONFIG_CRYPTO=y | ||
| 1709 | |||
| 1710 | # | ||
| 1711 | # Crypto core or helper | ||
| 1712 | # | ||
| 1713 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1714 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1715 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1716 | CONFIG_CRYPTO_AEAD2=y | ||
| 1717 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1718 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1719 | CONFIG_CRYPTO_HASH=y | ||
| 1720 | CONFIG_CRYPTO_HASH2=y | ||
| 1721 | CONFIG_CRYPTO_RNG2=y | ||
| 1722 | CONFIG_CRYPTO_MANAGER=y | ||
| 1723 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1724 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1725 | # CONFIG_CRYPTO_NULL is not set | ||
| 1726 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1727 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1728 | # CONFIG_CRYPTO_TEST is not set | ||
| 1729 | |||
| 1730 | # | ||
| 1731 | # Authenticated Encryption with Associated Data | ||
| 1732 | # | ||
| 1733 | # CONFIG_CRYPTO_CCM is not set | ||
| 1734 | # CONFIG_CRYPTO_GCM is not set | ||
| 1735 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1736 | |||
| 1737 | # | ||
| 1738 | # Block modes | ||
| 1739 | # | ||
| 1740 | CONFIG_CRYPTO_CBC=y | ||
| 1741 | # CONFIG_CRYPTO_CTR is not set | ||
| 1742 | # CONFIG_CRYPTO_CTS is not set | ||
| 1743 | CONFIG_CRYPTO_ECB=y | ||
| 1744 | # CONFIG_CRYPTO_LRW is not set | ||
| 1745 | CONFIG_CRYPTO_PCBC=m | ||
| 1746 | # CONFIG_CRYPTO_XTS is not set | ||
| 1747 | |||
| 1748 | # | ||
| 1749 | # Hash modes | ||
| 1750 | # | ||
| 1751 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1752 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1753 | |||
| 1754 | # | ||
| 1755 | # Digest | ||
| 1756 | # | ||
| 1757 | CONFIG_CRYPTO_CRC32C=y | ||
| 1758 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1759 | CONFIG_CRYPTO_MD5=y | ||
| 1760 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1761 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1762 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1763 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1764 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1765 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1766 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1767 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1768 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1769 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1770 | |||
| 1771 | # | ||
| 1772 | # Ciphers | ||
| 1773 | # | ||
| 1774 | CONFIG_CRYPTO_AES=y | ||
| 1775 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1776 | CONFIG_CRYPTO_ARC4=y | ||
| 1777 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1778 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1779 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1780 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1781 | CONFIG_CRYPTO_DES=y | ||
| 1782 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1783 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1784 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1785 | # CONFIG_CRYPTO_SEED is not set | ||
| 1786 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1787 | # CONFIG_CRYPTO_TEA is not set | ||
| 1788 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1789 | |||
| 1790 | # | ||
| 1791 | # Compression | ||
| 1792 | # | ||
| 1793 | CONFIG_CRYPTO_DEFLATE=y | ||
| 1794 | CONFIG_CRYPTO_LZO=y | ||
| 1795 | |||
| 1796 | # | ||
| 1797 | # Random Number Generation | ||
| 1798 | # | ||
| 1799 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1800 | CONFIG_CRYPTO_HW=y | ||
| 1801 | |||
| 1802 | # | ||
| 1803 | # Library routines | ||
| 1804 | # | ||
| 1805 | CONFIG_BITREVERSE=y | ||
| 1806 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1807 | CONFIG_CRC_CCITT=y | ||
| 1808 | CONFIG_CRC16=y | ||
| 1809 | # CONFIG_CRC_T10DIF is not set | ||
| 1810 | # CONFIG_CRC_ITU_T is not set | ||
| 1811 | CONFIG_CRC32=y | ||
| 1812 | CONFIG_CRC7=m | ||
| 1813 | CONFIG_LIBCRC32C=y | ||
| 1814 | CONFIG_ZLIB_INFLATE=y | ||
| 1815 | CONFIG_ZLIB_DEFLATE=y | ||
| 1816 | CONFIG_LZO_COMPRESS=y | ||
| 1817 | CONFIG_LZO_DECOMPRESS=y | ||
| 1818 | CONFIG_PLIST=y | ||
| 1819 | CONFIG_HAS_IOMEM=y | ||
| 1820 | CONFIG_HAS_IOPORT=y | ||
| 1821 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig index d052c8f80515..984f7096a533 100644 --- a/arch/arm/configs/shannon_defconfig +++ b/arch/arm/configs/shannon_defconfig | |||
| @@ -87,7 +87,6 @@ CONFIG_ARCH_SA1100=y | |||
| 87 | # CONFIG_SA1100_COLLIE is not set | 87 | # CONFIG_SA1100_COLLIE is not set |
| 88 | # CONFIG_SA1100_H3100 is not set | 88 | # CONFIG_SA1100_H3100 is not set |
| 89 | # CONFIG_SA1100_H3600 is not set | 89 | # CONFIG_SA1100_H3600 is not set |
| 90 | # CONFIG_SA1100_H3800 is not set | ||
| 91 | # CONFIG_SA1100_BADGE4 is not set | 90 | # CONFIG_SA1100_BADGE4 is not set |
| 92 | # CONFIG_SA1100_JORNADA720 is not set | 91 | # CONFIG_SA1100_JORNADA720 is not set |
| 93 | # CONFIG_SA1100_HACKKIT is not set | 92 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig index 9b6561d119af..90235bf7a1de 100644 --- a/arch/arm/configs/shark_defconfig +++ b/arch/arm/configs/shark_defconfig | |||
| @@ -1,88 +1,174 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.12-git3 | 3 | # Linux kernel version: 2.6.28-git6 |
| 4 | # Sat Jul 16 15:21:47 2005 | 4 | # Thu Jan 8 17:14:47 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | # CONFIG_GENERIC_GPIO is not set | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 7 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 8 | CONFIG_UID16=y | 12 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 9 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 10 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 11 | 29 | ||
| 12 | # | 30 | # |
| 13 | # Code maturity level options | 31 | # General setup |
| 14 | # | 32 | # |
| 15 | CONFIG_EXPERIMENTAL=y | 33 | CONFIG_EXPERIMENTAL=y |
| 16 | CONFIG_CLEAN_COMPILE=y | ||
| 17 | CONFIG_BROKEN_ON_SMP=y | 34 | CONFIG_BROKEN_ON_SMP=y |
| 18 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 19 | |||
| 20 | # | ||
| 21 | # General setup | ||
| 22 | # | ||
| 23 | CONFIG_LOCALVERSION="" | 36 | CONFIG_LOCALVERSION="" |
| 37 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 24 | CONFIG_SWAP=y | 38 | CONFIG_SWAP=y |
| 25 | CONFIG_SYSVIPC=y | 39 | CONFIG_SYSVIPC=y |
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 26 | # CONFIG_POSIX_MQUEUE is not set | 41 | # CONFIG_POSIX_MQUEUE is not set |
| 27 | # CONFIG_BSD_PROCESS_ACCT is not set | 42 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 28 | CONFIG_SYSCTL=y | 43 | # CONFIG_TASKSTATS is not set |
| 29 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 30 | # CONFIG_HOTPLUG is not set | ||
| 31 | CONFIG_KOBJECT_UEVENT=y | ||
| 32 | # CONFIG_IKCONFIG is not set | 45 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | CONFIG_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 50 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 51 | CONFIG_USER_SCHED=y | ||
| 52 | # CONFIG_CGROUP_SCHED is not set | ||
| 53 | CONFIG_SYSFS_DEPRECATED=y | ||
| 54 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 55 | # CONFIG_RELAY is not set | ||
| 56 | CONFIG_NAMESPACES=y | ||
| 57 | # CONFIG_UTS_NS is not set | ||
| 58 | # CONFIG_IPC_NS is not set | ||
| 59 | # CONFIG_USER_NS is not set | ||
| 60 | # CONFIG_PID_NS is not set | ||
| 61 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 62 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 63 | CONFIG_SYSCTL=y | ||
| 33 | # CONFIG_EMBEDDED is not set | 64 | # CONFIG_EMBEDDED is not set |
| 65 | CONFIG_UID16=y | ||
| 66 | CONFIG_SYSCTL_SYSCALL=y | ||
| 34 | CONFIG_KALLSYMS=y | 67 | CONFIG_KALLSYMS=y |
| 35 | # CONFIG_KALLSYMS_ALL is not set | 68 | # CONFIG_KALLSYMS_ALL is not set |
| 36 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 69 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 70 | CONFIG_HOTPLUG=y | ||
| 37 | CONFIG_PRINTK=y | 71 | CONFIG_PRINTK=y |
| 38 | CONFIG_BUG=y | 72 | CONFIG_BUG=y |
| 73 | CONFIG_ELF_CORE=y | ||
| 74 | CONFIG_COMPAT_BRK=y | ||
| 39 | CONFIG_BASE_FULL=y | 75 | CONFIG_BASE_FULL=y |
| 40 | CONFIG_FUTEX=y | 76 | CONFIG_FUTEX=y |
| 77 | CONFIG_ANON_INODES=y | ||
| 41 | CONFIG_EPOLL=y | 78 | CONFIG_EPOLL=y |
| 42 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 79 | CONFIG_SIGNALFD=y |
| 80 | CONFIG_TIMERFD=y | ||
| 81 | CONFIG_EVENTFD=y | ||
| 43 | CONFIG_SHMEM=y | 82 | CONFIG_SHMEM=y |
| 44 | CONFIG_CC_ALIGN_FUNCTIONS=0 | 83 | CONFIG_AIO=y |
| 45 | CONFIG_CC_ALIGN_LABELS=0 | 84 | CONFIG_VM_EVENT_COUNTERS=y |
| 46 | CONFIG_CC_ALIGN_LOOPS=0 | 85 | CONFIG_PCI_QUIRKS=y |
| 47 | CONFIG_CC_ALIGN_JUMPS=0 | 86 | CONFIG_SLAB=y |
| 87 | # CONFIG_SLUB is not set | ||
| 88 | # CONFIG_SLOB is not set | ||
| 89 | # CONFIG_PROFILING is not set | ||
| 90 | CONFIG_HAVE_OPROFILE=y | ||
| 91 | # CONFIG_KPROBES is not set | ||
| 92 | CONFIG_HAVE_KPROBES=y | ||
| 93 | CONFIG_HAVE_KRETPROBES=y | ||
| 94 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 95 | CONFIG_SLABINFO=y | ||
| 96 | CONFIG_RT_MUTEXES=y | ||
| 48 | # CONFIG_TINY_SHMEM is not set | 97 | # CONFIG_TINY_SHMEM is not set |
| 49 | CONFIG_BASE_SMALL=0 | 98 | CONFIG_BASE_SMALL=0 |
| 50 | |||
| 51 | # | ||
| 52 | # Loadable module support | ||
| 53 | # | ||
| 54 | CONFIG_MODULES=y | 99 | CONFIG_MODULES=y |
| 100 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 55 | CONFIG_MODULE_UNLOAD=y | 101 | CONFIG_MODULE_UNLOAD=y |
| 56 | CONFIG_MODULE_FORCE_UNLOAD=y | 102 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 57 | CONFIG_OBSOLETE_MODPARM=y | ||
| 58 | # CONFIG_MODVERSIONS is not set | 103 | # CONFIG_MODVERSIONS is not set |
| 59 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 104 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 60 | CONFIG_KMOD=y | 105 | CONFIG_KMOD=y |
| 106 | CONFIG_BLOCK=y | ||
| 107 | # CONFIG_LBD is not set | ||
| 108 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 109 | # CONFIG_BLK_DEV_BSG is not set | ||
| 110 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 111 | |||
| 112 | # | ||
| 113 | # IO Schedulers | ||
| 114 | # | ||
| 115 | CONFIG_IOSCHED_NOOP=y | ||
| 116 | CONFIG_IOSCHED_AS=y | ||
| 117 | CONFIG_IOSCHED_DEADLINE=y | ||
| 118 | CONFIG_IOSCHED_CFQ=y | ||
| 119 | # CONFIG_DEFAULT_AS is not set | ||
| 120 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 121 | CONFIG_DEFAULT_CFQ=y | ||
| 122 | # CONFIG_DEFAULT_NOOP is not set | ||
| 123 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 124 | CONFIG_CLASSIC_RCU=y | ||
| 125 | # CONFIG_TREE_RCU is not set | ||
| 126 | # CONFIG_PREEMPT_RCU is not set | ||
| 127 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 128 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 129 | # CONFIG_FREEZER is not set | ||
| 61 | 130 | ||
| 62 | # | 131 | # |
| 63 | # System Type | 132 | # System Type |
| 64 | # | 133 | # |
| 65 | # CONFIG_ARCH_CLPS7500 is not set | 134 | # CONFIG_ARCH_AAEC2000 is not set |
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 66 | # CONFIG_ARCH_CLPS711X is not set | 139 | # CONFIG_ARCH_CLPS711X is not set |
| 67 | # CONFIG_ARCH_CO285 is not set | ||
| 68 | # CONFIG_ARCH_EBSA110 is not set | 140 | # CONFIG_ARCH_EBSA110 is not set |
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 69 | # CONFIG_ARCH_FOOTBRIDGE is not set | 142 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 70 | # CONFIG_ARCH_INTEGRATOR is not set | 143 | # CONFIG_ARCH_NETX is not set |
| 71 | # CONFIG_ARCH_IOP3XX is not set | 144 | # CONFIG_ARCH_H720X is not set |
| 72 | # CONFIG_ARCH_IXP4XX is not set | 145 | # CONFIG_ARCH_IMX is not set |
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 73 | # CONFIG_ARCH_IXP2000 is not set | 150 | # CONFIG_ARCH_IXP2000 is not set |
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 74 | # CONFIG_ARCH_L7200 is not set | 152 | # CONFIG_ARCH_L7200 is not set |
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 75 | # CONFIG_ARCH_PXA is not set | 161 | # CONFIG_ARCH_PXA is not set |
| 76 | # CONFIG_ARCH_RPC is not set | 162 | # CONFIG_ARCH_RPC is not set |
| 77 | # CONFIG_ARCH_SA1100 is not set | 163 | # CONFIG_ARCH_SA1100 is not set |
| 78 | # CONFIG_ARCH_S3C2410 is not set | 164 | # CONFIG_ARCH_S3C2410 is not set |
| 165 | # CONFIG_ARCH_S3C64XX is not set | ||
| 79 | CONFIG_ARCH_SHARK=y | 166 | CONFIG_ARCH_SHARK=y |
| 80 | # CONFIG_ARCH_LH7A40X is not set | 167 | # CONFIG_ARCH_LH7A40X is not set |
| 168 | # CONFIG_ARCH_DAVINCI is not set | ||
| 81 | # CONFIG_ARCH_OMAP is not set | 169 | # CONFIG_ARCH_OMAP is not set |
| 82 | # CONFIG_ARCH_VERSATILE is not set | 170 | # CONFIG_ARCH_MSM is not set |
| 83 | # CONFIG_ARCH_IMX is not set | 171 | # CONFIG_ARCH_W90X900 is not set |
| 84 | # CONFIG_ARCH_H720X is not set | ||
| 85 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 86 | 172 | ||
| 87 | # | 173 | # |
| 88 | # Processor Type | 174 | # Processor Type |
| @@ -91,14 +177,20 @@ CONFIG_CPU_32=y | |||
| 91 | CONFIG_CPU_SA110=y | 177 | CONFIG_CPU_SA110=y |
| 92 | CONFIG_CPU_32v4=y | 178 | CONFIG_CPU_32v4=y |
| 93 | CONFIG_CPU_ABRT_EV4=y | 179 | CONFIG_CPU_ABRT_EV4=y |
| 180 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 94 | CONFIG_CPU_CACHE_V4WB=y | 181 | CONFIG_CPU_CACHE_V4WB=y |
| 95 | CONFIG_CPU_CACHE_VIVT=y | 182 | CONFIG_CPU_CACHE_VIVT=y |
| 96 | CONFIG_CPU_COPY_V4WB=y | 183 | CONFIG_CPU_COPY_V4WB=y |
| 97 | CONFIG_CPU_TLB_V4WB=y | 184 | CONFIG_CPU_TLB_V4WB=y |
| 185 | CONFIG_CPU_CP15=y | ||
| 186 | CONFIG_CPU_CP15_MMU=y | ||
| 98 | 187 | ||
| 99 | # | 188 | # |
| 100 | # Processor Features | 189 | # Processor Features |
| 101 | # | 190 | # |
| 191 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 192 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 193 | # CONFIG_OUTER_CACHE is not set | ||
| 102 | 194 | ||
| 103 | # | 195 | # |
| 104 | # Bus support | 196 | # Bus support |
| @@ -107,22 +199,40 @@ CONFIG_ISA=y | |||
| 107 | CONFIG_ISA_DMA=y | 199 | CONFIG_ISA_DMA=y |
| 108 | CONFIG_ISA_DMA_API=y | 200 | CONFIG_ISA_DMA_API=y |
| 109 | CONFIG_PCI=y | 201 | CONFIG_PCI=y |
| 202 | CONFIG_PCI_SYSCALL=y | ||
| 110 | CONFIG_PCI_HOST_VIA82C505=y | 203 | CONFIG_PCI_HOST_VIA82C505=y |
| 111 | CONFIG_PCI_LEGACY_PROC=y | 204 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 112 | # CONFIG_PCI_NAMES is not set | 205 | CONFIG_PCI_LEGACY=y |
| 113 | # CONFIG_PCI_DEBUG is not set | 206 | # CONFIG_PCI_DEBUG is not set |
| 114 | |||
| 115 | # | ||
| 116 | # PCCARD (PCMCIA/CardBus) support | ||
| 117 | # | ||
| 118 | # CONFIG_PCCARD is not set | 207 | # CONFIG_PCCARD is not set |
| 119 | 208 | ||
| 120 | # | 209 | # |
| 121 | # Kernel Features | 210 | # Kernel Features |
| 122 | # | 211 | # |
| 123 | # CONFIG_SMP is not set | 212 | CONFIG_VMSPLIT_3G=y |
| 213 | # CONFIG_VMSPLIT_2G is not set | ||
| 214 | # CONFIG_VMSPLIT_1G is not set | ||
| 215 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 124 | # CONFIG_PREEMPT is not set | 216 | # CONFIG_PREEMPT is not set |
| 125 | # CONFIG_DISCONTIGMEM is not set | 217 | CONFIG_HZ=100 |
| 218 | # CONFIG_AEABI is not set | ||
| 219 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 220 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 221 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 222 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 223 | CONFIG_FLATMEM_MANUAL=y | ||
| 224 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 225 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 226 | CONFIG_FLATMEM=y | ||
| 227 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 228 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 229 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 230 | # CONFIG_RESOURCES_64BIT is not set | ||
| 231 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 232 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 233 | CONFIG_BOUNCE=y | ||
| 234 | CONFIG_VIRT_TO_BUS=y | ||
| 235 | CONFIG_UNEVICTABLE_LRU=y | ||
| 126 | CONFIG_LEDS=y | 236 | CONFIG_LEDS=y |
| 127 | CONFIG_LEDS_TIMER=y | 237 | CONFIG_LEDS_TIMER=y |
| 128 | # CONFIG_LEDS_CPU is not set | 238 | # CONFIG_LEDS_CPU is not set |
| @@ -135,6 +245,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 135 | CONFIG_ZBOOT_ROM_BSS=0x0 | 245 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 136 | CONFIG_CMDLINE="" | 246 | CONFIG_CMDLINE="" |
| 137 | # CONFIG_XIP_KERNEL is not set | 247 | # CONFIG_XIP_KERNEL is not set |
| 248 | # CONFIG_KEXEC is not set | ||
| 249 | |||
| 250 | # | ||
| 251 | # CPU Power Management | ||
| 252 | # | ||
| 253 | # CONFIG_CPU_IDLE is not set | ||
| 138 | 254 | ||
| 139 | # | 255 | # |
| 140 | # Floating point emulation | 256 | # Floating point emulation |
| @@ -143,13 +259,16 @@ CONFIG_CMDLINE="" | |||
| 143 | # | 259 | # |
| 144 | # At least one emulation must be selected | 260 | # At least one emulation must be selected |
| 145 | # | 261 | # |
| 146 | # CONFIG_FPE_NWFPE is not set | 262 | CONFIG_FPE_NWFPE=y |
| 147 | CONFIG_FPE_FASTFPE=y | 263 | # CONFIG_FPE_NWFPE_XP is not set |
| 264 | # CONFIG_FPE_FASTFPE is not set | ||
| 148 | 265 | ||
| 149 | # | 266 | # |
| 150 | # Userspace binary formats | 267 | # Userspace binary formats |
| 151 | # | 268 | # |
| 152 | CONFIG_BINFMT_ELF=y | 269 | CONFIG_BINFMT_ELF=y |
| 270 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 271 | CONFIG_HAVE_AOUT=y | ||
| 153 | # CONFIG_BINFMT_AOUT is not set | 272 | # CONFIG_BINFMT_AOUT is not set |
| 154 | # CONFIG_BINFMT_MISC is not set | 273 | # CONFIG_BINFMT_MISC is not set |
| 155 | # CONFIG_ARTHUR is not set | 274 | # CONFIG_ARTHUR is not set |
| @@ -158,44 +277,104 @@ CONFIG_BINFMT_ELF=y | |||
| 158 | # Power management options | 277 | # Power management options |
| 159 | # | 278 | # |
| 160 | # CONFIG_PM is not set | 279 | # CONFIG_PM is not set |
| 280 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 281 | CONFIG_NET=y | ||
| 161 | 282 | ||
| 162 | # | 283 | # |
| 163 | # Device Drivers | 284 | # Networking options |
| 164 | # | 285 | # |
| 286 | # CONFIG_NET_NS is not set | ||
| 287 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 288 | CONFIG_PACKET=y | ||
| 289 | # CONFIG_PACKET_MMAP is not set | ||
| 290 | CONFIG_UNIX=y | ||
| 291 | # CONFIG_NET_KEY is not set | ||
| 292 | CONFIG_INET=y | ||
| 293 | # CONFIG_IP_MULTICAST is not set | ||
| 294 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 295 | CONFIG_IP_FIB_HASH=y | ||
| 296 | # CONFIG_IP_PNP is not set | ||
| 297 | # CONFIG_NET_IPIP is not set | ||
| 298 | # CONFIG_NET_IPGRE is not set | ||
| 299 | # CONFIG_ARPD is not set | ||
| 300 | # CONFIG_SYN_COOKIES is not set | ||
| 301 | # CONFIG_INET_AH is not set | ||
| 302 | # CONFIG_INET_ESP is not set | ||
| 303 | # CONFIG_INET_IPCOMP is not set | ||
| 304 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 305 | # CONFIG_INET_TUNNEL is not set | ||
| 306 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 307 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 308 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 309 | # CONFIG_INET_LRO is not set | ||
| 310 | # CONFIG_INET_DIAG is not set | ||
| 311 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 312 | CONFIG_TCP_CONG_CUBIC=y | ||
| 313 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 314 | # CONFIG_TCP_MD5SIG is not set | ||
| 315 | # CONFIG_IPV6 is not set | ||
| 316 | # CONFIG_NETWORK_SECMARK is not set | ||
| 317 | # CONFIG_NETFILTER is not set | ||
| 318 | # CONFIG_IP_DCCP is not set | ||
| 319 | # CONFIG_IP_SCTP is not set | ||
| 320 | # CONFIG_TIPC is not set | ||
| 321 | # CONFIG_ATM is not set | ||
| 322 | # CONFIG_BRIDGE is not set | ||
| 323 | # CONFIG_NET_DSA is not set | ||
| 324 | # CONFIG_VLAN_8021Q is not set | ||
| 325 | # CONFIG_DECNET is not set | ||
| 326 | # CONFIG_LLC2 is not set | ||
| 327 | # CONFIG_IPX is not set | ||
| 328 | # CONFIG_ATALK is not set | ||
| 329 | # CONFIG_X25 is not set | ||
| 330 | # CONFIG_LAPB is not set | ||
| 331 | # CONFIG_ECONET is not set | ||
| 332 | # CONFIG_WAN_ROUTER is not set | ||
| 333 | # CONFIG_NET_SCHED is not set | ||
| 334 | # CONFIG_DCB is not set | ||
| 165 | 335 | ||
| 166 | # | 336 | # |
| 167 | # Generic Driver Options | 337 | # Network testing |
| 168 | # | 338 | # |
| 169 | # CONFIG_STANDALONE is not set | 339 | # CONFIG_NET_PKTGEN is not set |
| 170 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 340 | # CONFIG_HAMRADIO is not set |
| 171 | # CONFIG_FW_LOADER is not set | 341 | # CONFIG_CAN is not set |
| 172 | # CONFIG_DEBUG_DRIVER is not set | 342 | # CONFIG_IRDA is not set |
| 343 | # CONFIG_BT is not set | ||
| 344 | # CONFIG_AF_RXRPC is not set | ||
| 345 | # CONFIG_PHONET is not set | ||
| 346 | # CONFIG_WIRELESS is not set | ||
| 347 | # CONFIG_RFKILL is not set | ||
| 348 | # CONFIG_NET_9P is not set | ||
| 173 | 349 | ||
| 174 | # | 350 | # |
| 175 | # Memory Technology Devices (MTD) | 351 | # Device Drivers |
| 176 | # | 352 | # |
| 177 | # CONFIG_MTD is not set | ||
| 178 | 353 | ||
| 179 | # | 354 | # |
| 180 | # Parallel port support | 355 | # Generic Driver Options |
| 181 | # | 356 | # |
| 357 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 358 | # CONFIG_STANDALONE is not set | ||
| 359 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 360 | CONFIG_FW_LOADER=y | ||
| 361 | # CONFIG_FIRMWARE_IN_KERNEL is not set | ||
| 362 | CONFIG_EXTRA_FIRMWARE="" | ||
| 363 | # CONFIG_DEBUG_DRIVER is not set | ||
| 364 | # CONFIG_DEBUG_DEVRES is not set | ||
| 365 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 366 | # CONFIG_CONNECTOR is not set | ||
| 367 | # CONFIG_MTD is not set | ||
| 182 | CONFIG_PARPORT=m | 368 | CONFIG_PARPORT=m |
| 183 | CONFIG_PARPORT_PC=m | 369 | CONFIG_PARPORT_PC=m |
| 184 | # CONFIG_PARPORT_SERIAL is not set | 370 | # CONFIG_PARPORT_SERIAL is not set |
| 185 | # CONFIG_PARPORT_PC_FIFO is not set | 371 | # CONFIG_PARPORT_PC_FIFO is not set |
| 186 | # CONFIG_PARPORT_PC_SUPERIO is not set | 372 | # CONFIG_PARPORT_PC_SUPERIO is not set |
| 187 | # CONFIG_PARPORT_ARC is not set | ||
| 188 | # CONFIG_PARPORT_GSC is not set | 373 | # CONFIG_PARPORT_GSC is not set |
| 374 | # CONFIG_PARPORT_AX88796 is not set | ||
| 189 | # CONFIG_PARPORT_1284 is not set | 375 | # CONFIG_PARPORT_1284 is not set |
| 190 | |||
| 191 | # | ||
| 192 | # Plug and Play support | ||
| 193 | # | ||
| 194 | # CONFIG_PNP is not set | 376 | # CONFIG_PNP is not set |
| 195 | 377 | CONFIG_BLK_DEV=y | |
| 196 | # | ||
| 197 | # Block devices | ||
| 198 | # | ||
| 199 | # CONFIG_BLK_DEV_XD is not set | 378 | # CONFIG_BLK_DEV_XD is not set |
| 200 | # CONFIG_PARIDE is not set | 379 | # CONFIG_PARIDE is not set |
| 201 | # CONFIG_BLK_CPQ_DA is not set | 380 | # CONFIG_BLK_CPQ_DA is not set |
| @@ -210,52 +389,78 @@ CONFIG_BLK_DEV_LOOP=y | |||
| 210 | CONFIG_BLK_DEV_RAM=y | 389 | CONFIG_BLK_DEV_RAM=y |
| 211 | CONFIG_BLK_DEV_RAM_COUNT=16 | 390 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 212 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 391 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 213 | # CONFIG_BLK_DEV_INITRD is not set | 392 | # CONFIG_BLK_DEV_XIP is not set |
| 214 | CONFIG_INITRAMFS_SOURCE="" | ||
| 215 | # CONFIG_CDROM_PKTCDVD is not set | 393 | # CONFIG_CDROM_PKTCDVD is not set |
| 216 | |||
| 217 | # | ||
| 218 | # IO Schedulers | ||
| 219 | # | ||
| 220 | CONFIG_IOSCHED_NOOP=y | ||
| 221 | CONFIG_IOSCHED_AS=y | ||
| 222 | CONFIG_IOSCHED_DEADLINE=y | ||
| 223 | CONFIG_IOSCHED_CFQ=y | ||
| 224 | # CONFIG_ATA_OVER_ETH is not set | 394 | # CONFIG_ATA_OVER_ETH is not set |
| 225 | 395 | # CONFIG_BLK_DEV_HD is not set | |
| 226 | # | 396 | CONFIG_MISC_DEVICES=y |
| 227 | # ATA/ATAPI/MFM/RLL support | 397 | # CONFIG_PHANTOM is not set |
| 228 | # | 398 | # CONFIG_EEPROM_93CX6 is not set |
| 399 | # CONFIG_SGI_IOC4 is not set | ||
| 400 | # CONFIG_TIFM_CORE is not set | ||
| 401 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 402 | # CONFIG_HP_ILO is not set | ||
| 403 | # CONFIG_C2PORT is not set | ||
| 404 | CONFIG_HAVE_IDE=y | ||
| 229 | CONFIG_IDE=y | 405 | CONFIG_IDE=y |
| 230 | CONFIG_BLK_DEV_IDE=y | ||
| 231 | 406 | ||
| 232 | # | 407 | # |
| 233 | # Please see Documentation/ide.txt for help/info on IDE drives | 408 | # Please see Documentation/ide/ide.txt for help/info on IDE drives |
| 234 | # | 409 | # |
| 410 | CONFIG_IDE_ATAPI=y | ||
| 235 | # CONFIG_BLK_DEV_IDE_SATA is not set | 411 | # CONFIG_BLK_DEV_IDE_SATA is not set |
| 236 | CONFIG_BLK_DEV_IDEDISK=y | 412 | CONFIG_IDE_GD=y |
| 237 | # CONFIG_IDEDISK_MULTI_MODE is not set | 413 | CONFIG_IDE_GD_ATA=y |
| 414 | # CONFIG_IDE_GD_ATAPI is not set | ||
| 238 | CONFIG_BLK_DEV_IDECD=m | 415 | CONFIG_BLK_DEV_IDECD=m |
| 416 | CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y | ||
| 239 | # CONFIG_BLK_DEV_IDETAPE is not set | 417 | # CONFIG_BLK_DEV_IDETAPE is not set |
| 240 | CONFIG_BLK_DEV_IDEFLOPPY=y | ||
| 241 | # CONFIG_BLK_DEV_IDESCSI is not set | ||
| 242 | # CONFIG_IDE_TASK_IOCTL is not set | 418 | # CONFIG_IDE_TASK_IOCTL is not set |
| 419 | CONFIG_IDE_PROC_FS=y | ||
| 243 | 420 | ||
| 244 | # | 421 | # |
| 245 | # IDE chipset support/bugfixes | 422 | # IDE chipset support/bugfixes |
| 246 | # | 423 | # |
| 247 | CONFIG_IDE_GENERIC=y | 424 | # CONFIG_BLK_DEV_PLATFORM is not set |
| 248 | # CONFIG_BLK_DEV_IDEPCI is not set | 425 | |
| 426 | # | ||
| 427 | # PCI IDE chipsets support | ||
| 428 | # | ||
| 429 | # CONFIG_BLK_DEV_GENERIC is not set | ||
| 430 | # CONFIG_BLK_DEV_OPTI621 is not set | ||
| 431 | # CONFIG_BLK_DEV_AEC62XX is not set | ||
| 432 | # CONFIG_BLK_DEV_ALI15X3 is not set | ||
| 433 | # CONFIG_BLK_DEV_CMD64X is not set | ||
| 434 | # CONFIG_BLK_DEV_TRIFLEX is not set | ||
| 435 | # CONFIG_BLK_DEV_CS5520 is not set | ||
| 436 | # CONFIG_BLK_DEV_CS5530 is not set | ||
| 437 | # CONFIG_BLK_DEV_HPT366 is not set | ||
| 438 | # CONFIG_BLK_DEV_JMICRON is not set | ||
| 439 | # CONFIG_BLK_DEV_SC1200 is not set | ||
| 440 | # CONFIG_BLK_DEV_PIIX is not set | ||
| 441 | # CONFIG_BLK_DEV_IT8213 is not set | ||
| 442 | # CONFIG_BLK_DEV_IT821X is not set | ||
| 443 | # CONFIG_BLK_DEV_NS87415 is not set | ||
| 444 | # CONFIG_BLK_DEV_PDC202XX_OLD is not set | ||
| 445 | # CONFIG_BLK_DEV_PDC202XX_NEW is not set | ||
| 446 | # CONFIG_BLK_DEV_SVWKS is not set | ||
| 447 | # CONFIG_BLK_DEV_SIIMAGE is not set | ||
| 448 | # CONFIG_BLK_DEV_SL82C105 is not set | ||
| 449 | # CONFIG_BLK_DEV_SLC90E66 is not set | ||
| 450 | # CONFIG_BLK_DEV_TRM290 is not set | ||
| 451 | # CONFIG_BLK_DEV_VIA82CXXX is not set | ||
| 452 | # CONFIG_BLK_DEV_TC86C001 is not set | ||
| 249 | CONFIG_IDE_ARM=y | 453 | CONFIG_IDE_ARM=y |
| 250 | # CONFIG_IDE_CHIPSETS is not set | ||
| 251 | # CONFIG_BLK_DEV_IDEDMA is not set | 454 | # CONFIG_BLK_DEV_IDEDMA is not set |
| 252 | # CONFIG_IDEDMA_AUTO is not set | ||
| 253 | # CONFIG_BLK_DEV_HD is not set | ||
| 254 | 455 | ||
| 255 | # | 456 | # |
| 256 | # SCSI device support | 457 | # SCSI device support |
| 257 | # | 458 | # |
| 459 | # CONFIG_RAID_ATTRS is not set | ||
| 258 | CONFIG_SCSI=m | 460 | CONFIG_SCSI=m |
| 461 | CONFIG_SCSI_DMA=y | ||
| 462 | # CONFIG_SCSI_TGT is not set | ||
| 463 | # CONFIG_SCSI_NETLINK is not set | ||
| 259 | CONFIG_SCSI_PROC_FS=y | 464 | CONFIG_SCSI_PROC_FS=y |
| 260 | 465 | ||
| 261 | # | 466 | # |
| @@ -275,17 +480,20 @@ CONFIG_CHR_DEV_SG=m | |||
| 275 | # CONFIG_SCSI_MULTI_LUN is not set | 480 | # CONFIG_SCSI_MULTI_LUN is not set |
| 276 | # CONFIG_SCSI_CONSTANTS is not set | 481 | # CONFIG_SCSI_CONSTANTS is not set |
| 277 | # CONFIG_SCSI_LOGGING is not set | 482 | # CONFIG_SCSI_LOGGING is not set |
| 483 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 484 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 278 | 485 | ||
| 279 | # | 486 | # |
| 280 | # SCSI Transport Attributes | 487 | # SCSI Transports |
| 281 | # | 488 | # |
| 282 | # CONFIG_SCSI_SPI_ATTRS is not set | 489 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 283 | # CONFIG_SCSI_FC_ATTRS is not set | 490 | # CONFIG_SCSI_FC_ATTRS is not set |
| 284 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 491 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 285 | 492 | # CONFIG_SCSI_SAS_LIBSAS is not set | |
| 286 | # | 493 | # CONFIG_SCSI_SRP_ATTRS is not set |
| 287 | # SCSI low-level drivers | 494 | CONFIG_SCSI_LOWLEVEL=y |
| 288 | # | 495 | # CONFIG_ISCSI_TCP is not set |
| 496 | # CONFIG_SCSI_CXGB3_ISCSI is not set | ||
| 289 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 497 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 290 | # CONFIG_SCSI_3W_9XXX is not set | 498 | # CONFIG_SCSI_3W_9XXX is not set |
| 291 | # CONFIG_SCSI_7000FASST is not set | 499 | # CONFIG_SCSI_7000FASST is not set |
| @@ -296,12 +504,18 @@ CONFIG_CHR_DEV_SG=m | |||
| 296 | # CONFIG_SCSI_AIC7XXX is not set | 504 | # CONFIG_SCSI_AIC7XXX is not set |
| 297 | # CONFIG_SCSI_AIC7XXX_OLD is not set | 505 | # CONFIG_SCSI_AIC7XXX_OLD is not set |
| 298 | # CONFIG_SCSI_AIC79XX is not set | 506 | # CONFIG_SCSI_AIC79XX is not set |
| 507 | # CONFIG_SCSI_AIC94XX is not set | ||
| 299 | # CONFIG_SCSI_DPT_I2O is not set | 508 | # CONFIG_SCSI_DPT_I2O is not set |
| 509 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 300 | # CONFIG_SCSI_IN2000 is not set | 510 | # CONFIG_SCSI_IN2000 is not set |
| 511 | # CONFIG_SCSI_ARCMSR is not set | ||
| 301 | # CONFIG_MEGARAID_NEWGEN is not set | 512 | # CONFIG_MEGARAID_NEWGEN is not set |
| 302 | # CONFIG_MEGARAID_LEGACY is not set | 513 | # CONFIG_MEGARAID_LEGACY is not set |
| 303 | # CONFIG_SCSI_SATA is not set | 514 | # CONFIG_MEGARAID_SAS is not set |
| 515 | # CONFIG_SCSI_HPTIOP is not set | ||
| 304 | # CONFIG_SCSI_BUSLOGIC is not set | 516 | # CONFIG_SCSI_BUSLOGIC is not set |
| 517 | # CONFIG_LIBFC is not set | ||
| 518 | # CONFIG_FCOE is not set | ||
| 305 | # CONFIG_SCSI_DMX3191D is not set | 519 | # CONFIG_SCSI_DMX3191D is not set |
| 306 | # CONFIG_SCSI_DTC3280 is not set | 520 | # CONFIG_SCSI_DTC3280 is not set |
| 307 | # CONFIG_SCSI_EATA is not set | 521 | # CONFIG_SCSI_EATA is not set |
| @@ -314,20 +528,15 @@ CONFIG_CHR_DEV_SG=m | |||
| 314 | # CONFIG_SCSI_INIA100 is not set | 528 | # CONFIG_SCSI_INIA100 is not set |
| 315 | # CONFIG_SCSI_PPA is not set | 529 | # CONFIG_SCSI_PPA is not set |
| 316 | # CONFIG_SCSI_IMM is not set | 530 | # CONFIG_SCSI_IMM is not set |
| 531 | # CONFIG_SCSI_MVSAS is not set | ||
| 317 | # CONFIG_SCSI_NCR53C406A is not set | 532 | # CONFIG_SCSI_NCR53C406A is not set |
| 533 | # CONFIG_SCSI_STEX is not set | ||
| 318 | # CONFIG_SCSI_SYM53C8XX_2 is not set | 534 | # CONFIG_SCSI_SYM53C8XX_2 is not set |
| 319 | # CONFIG_SCSI_IPR is not set | ||
| 320 | # CONFIG_SCSI_PAS16 is not set | 535 | # CONFIG_SCSI_PAS16 is not set |
| 321 | # CONFIG_SCSI_PSI240I is not set | ||
| 322 | # CONFIG_SCSI_QLOGIC_FAS is not set | 536 | # CONFIG_SCSI_QLOGIC_FAS is not set |
| 323 | # CONFIG_SCSI_QLOGIC_FC is not set | ||
| 324 | # CONFIG_SCSI_QLOGIC_1280 is not set | 537 | # CONFIG_SCSI_QLOGIC_1280 is not set |
| 325 | CONFIG_SCSI_QLA2XXX=m | 538 | # CONFIG_SCSI_QLA_FC is not set |
| 326 | # CONFIG_SCSI_QLA21XX is not set | 539 | # CONFIG_SCSI_QLA_ISCSI is not set |
| 327 | # CONFIG_SCSI_QLA22XX is not set | ||
| 328 | # CONFIG_SCSI_QLA2300 is not set | ||
| 329 | # CONFIG_SCSI_QLA2322 is not set | ||
| 330 | # CONFIG_SCSI_QLA6312 is not set | ||
| 331 | # CONFIG_SCSI_LPFC is not set | 540 | # CONFIG_SCSI_LPFC is not set |
| 332 | # CONFIG_SCSI_SYM53C416 is not set | 541 | # CONFIG_SCSI_SYM53C416 is not set |
| 333 | # CONFIG_SCSI_DC395x is not set | 542 | # CONFIG_SCSI_DC395x is not set |
| @@ -336,123 +545,57 @@ CONFIG_SCSI_QLA2XXX=m | |||
| 336 | # CONFIG_SCSI_U14_34F is not set | 545 | # CONFIG_SCSI_U14_34F is not set |
| 337 | # CONFIG_SCSI_NSP32 is not set | 546 | # CONFIG_SCSI_NSP32 is not set |
| 338 | # CONFIG_SCSI_DEBUG is not set | 547 | # CONFIG_SCSI_DEBUG is not set |
| 339 | 548 | # CONFIG_SCSI_SRP is not set | |
| 340 | # | 549 | # CONFIG_SCSI_DH is not set |
| 341 | # Multi-device support (RAID and LVM) | 550 | # CONFIG_ATA is not set |
| 342 | # | ||
| 343 | # CONFIG_MD is not set | 551 | # CONFIG_MD is not set |
| 344 | |||
| 345 | # | ||
| 346 | # Fusion MPT device support | ||
| 347 | # | ||
| 348 | # CONFIG_FUSION is not set | 552 | # CONFIG_FUSION is not set |
| 349 | # CONFIG_FUSION_SPI is not set | ||
| 350 | # CONFIG_FUSION_FC is not set | ||
| 351 | 553 | ||
| 352 | # | 554 | # |
| 353 | # IEEE 1394 (FireWire) support | 555 | # IEEE 1394 (FireWire) support |
| 354 | # | 556 | # |
| 355 | # CONFIG_IEEE1394 is not set | ||
| 356 | 557 | ||
| 357 | # | 558 | # |
| 358 | # I2O device support | 559 | # Enable only one of the two stacks, unless you know what you are doing |
| 359 | # | 560 | # |
| 561 | # CONFIG_FIREWIRE is not set | ||
| 562 | # CONFIG_IEEE1394 is not set | ||
| 360 | # CONFIG_I2O is not set | 563 | # CONFIG_I2O is not set |
| 361 | |||
| 362 | # | ||
| 363 | # Networking support | ||
| 364 | # | ||
| 365 | CONFIG_NET=y | ||
| 366 | |||
| 367 | # | ||
| 368 | # Networking options | ||
| 369 | # | ||
| 370 | CONFIG_PACKET=y | ||
| 371 | # CONFIG_PACKET_MMAP is not set | ||
| 372 | CONFIG_UNIX=y | ||
| 373 | # CONFIG_NET_KEY is not set | ||
| 374 | CONFIG_INET=y | ||
| 375 | # CONFIG_IP_MULTICAST is not set | ||
| 376 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 377 | # CONFIG_IP_PNP is not set | ||
| 378 | # CONFIG_NET_IPIP is not set | ||
| 379 | # CONFIG_NET_IPGRE is not set | ||
| 380 | # CONFIG_ARPD is not set | ||
| 381 | # CONFIG_SYN_COOKIES is not set | ||
| 382 | # CONFIG_INET_AH is not set | ||
| 383 | # CONFIG_INET_ESP is not set | ||
| 384 | # CONFIG_INET_IPCOMP is not set | ||
| 385 | # CONFIG_INET_TUNNEL is not set | ||
| 386 | CONFIG_IP_TCPDIAG=y | ||
| 387 | # CONFIG_IP_TCPDIAG_IPV6 is not set | ||
| 388 | # CONFIG_IPV6 is not set | ||
| 389 | # CONFIG_NETFILTER is not set | ||
| 390 | |||
| 391 | # | ||
| 392 | # SCTP Configuration (EXPERIMENTAL) | ||
| 393 | # | ||
| 394 | # CONFIG_IP_SCTP is not set | ||
| 395 | # CONFIG_ATM is not set | ||
| 396 | # CONFIG_BRIDGE is not set | ||
| 397 | # CONFIG_VLAN_8021Q is not set | ||
| 398 | # CONFIG_DECNET is not set | ||
| 399 | # CONFIG_LLC2 is not set | ||
| 400 | # CONFIG_IPX is not set | ||
| 401 | # CONFIG_ATALK is not set | ||
| 402 | # CONFIG_X25 is not set | ||
| 403 | # CONFIG_LAPB is not set | ||
| 404 | # CONFIG_NET_DIVERT is not set | ||
| 405 | # CONFIG_ECONET is not set | ||
| 406 | # CONFIG_WAN_ROUTER is not set | ||
| 407 | |||
| 408 | # | ||
| 409 | # QoS and/or fair queueing | ||
| 410 | # | ||
| 411 | # CONFIG_NET_SCHED is not set | ||
| 412 | # CONFIG_NET_CLS_ROUTE is not set | ||
| 413 | |||
| 414 | # | ||
| 415 | # Network testing | ||
| 416 | # | ||
| 417 | # CONFIG_NET_PKTGEN is not set | ||
| 418 | # CONFIG_NETPOLL is not set | ||
| 419 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 420 | # CONFIG_HAMRADIO is not set | ||
| 421 | # CONFIG_IRDA is not set | ||
| 422 | # CONFIG_BT is not set | ||
| 423 | CONFIG_NETDEVICES=y | 564 | CONFIG_NETDEVICES=y |
| 424 | # CONFIG_DUMMY is not set | 565 | # CONFIG_DUMMY is not set |
| 425 | # CONFIG_BONDING is not set | 566 | # CONFIG_BONDING is not set |
| 567 | # CONFIG_MACVLAN is not set | ||
| 426 | # CONFIG_EQUALIZER is not set | 568 | # CONFIG_EQUALIZER is not set |
| 427 | # CONFIG_TUN is not set | 569 | # CONFIG_TUN is not set |
| 428 | 570 | # CONFIG_VETH is not set | |
| 429 | # | ||
| 430 | # ARCnet devices | ||
| 431 | # | ||
| 432 | # CONFIG_ARCNET is not set | 571 | # CONFIG_ARCNET is not set |
| 433 | 572 | # CONFIG_PHYLIB is not set | |
| 434 | # | ||
| 435 | # Ethernet (10 or 100Mbit) | ||
| 436 | # | ||
| 437 | CONFIG_NET_ETHERNET=y | 573 | CONFIG_NET_ETHERNET=y |
| 438 | # CONFIG_MII is not set | 574 | # CONFIG_MII is not set |
| 575 | # CONFIG_AX88796 is not set | ||
| 439 | # CONFIG_HAPPYMEAL is not set | 576 | # CONFIG_HAPPYMEAL is not set |
| 440 | # CONFIG_SUNGEM is not set | 577 | # CONFIG_SUNGEM is not set |
| 578 | # CONFIG_CASSINI is not set | ||
| 441 | # CONFIG_NET_VENDOR_3COM is not set | 579 | # CONFIG_NET_VENDOR_3COM is not set |
| 442 | # CONFIG_LANCE is not set | 580 | # CONFIG_LANCE is not set |
| 443 | # CONFIG_NET_VENDOR_SMC is not set | 581 | # CONFIG_NET_VENDOR_SMC is not set |
| 444 | # CONFIG_SMC91X is not set | 582 | # CONFIG_SMC91X is not set |
| 445 | # CONFIG_DM9000 is not set | 583 | # CONFIG_DM9000 is not set |
| 584 | # CONFIG_SMC911X is not set | ||
| 585 | # CONFIG_SMSC911X is not set | ||
| 446 | # CONFIG_NET_VENDOR_RACAL is not set | 586 | # CONFIG_NET_VENDOR_RACAL is not set |
| 447 | |||
| 448 | # | ||
| 449 | # Tulip family network device support | ||
| 450 | # | ||
| 451 | # CONFIG_NET_TULIP is not set | 587 | # CONFIG_NET_TULIP is not set |
| 452 | # CONFIG_AT1700 is not set | 588 | # CONFIG_AT1700 is not set |
| 453 | # CONFIG_DEPCA is not set | 589 | # CONFIG_DEPCA is not set |
| 454 | # CONFIG_HP100 is not set | 590 | # CONFIG_HP100 is not set |
| 455 | # CONFIG_NET_ISA is not set | 591 | # CONFIG_NET_ISA is not set |
| 592 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 593 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 594 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 595 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 596 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 597 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 598 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 456 | CONFIG_NET_PCI=y | 599 | CONFIG_NET_PCI=y |
| 457 | # CONFIG_PCNET32 is not set | 600 | # CONFIG_PCNET32 is not set |
| 458 | # CONFIG_AMD8111_ETH is not set | 601 | # CONFIG_AMD8111_ETH is not set |
| @@ -462,56 +605,69 @@ CONFIG_NET_PCI=y | |||
| 462 | # CONFIG_B44 is not set | 605 | # CONFIG_B44 is not set |
| 463 | # CONFIG_FORCEDETH is not set | 606 | # CONFIG_FORCEDETH is not set |
| 464 | CONFIG_CS89x0=y | 607 | CONFIG_CS89x0=y |
| 465 | # CONFIG_DGRS is not set | 608 | CONFIG_CS89x0_NOEEPROM=y |
| 466 | # CONFIG_EEPRO100 is not set | ||
| 467 | # CONFIG_E100 is not set | 609 | # CONFIG_E100 is not set |
| 468 | # CONFIG_FEALNX is not set | 610 | # CONFIG_FEALNX is not set |
| 469 | # CONFIG_NATSEMI is not set | 611 | # CONFIG_NATSEMI is not set |
| 470 | # CONFIG_NE2K_PCI is not set | 612 | # CONFIG_NE2K_PCI is not set |
| 471 | # CONFIG_8139CP is not set | 613 | # CONFIG_8139CP is not set |
| 472 | # CONFIG_8139TOO is not set | 614 | # CONFIG_8139TOO is not set |
| 615 | # CONFIG_R6040 is not set | ||
| 473 | # CONFIG_SIS900 is not set | 616 | # CONFIG_SIS900 is not set |
| 474 | # CONFIG_EPIC100 is not set | 617 | # CONFIG_EPIC100 is not set |
| 618 | # CONFIG_SMSC9420 is not set | ||
| 475 | # CONFIG_SUNDANCE is not set | 619 | # CONFIG_SUNDANCE is not set |
| 476 | # CONFIG_TLAN is not set | 620 | # CONFIG_TLAN is not set |
| 477 | # CONFIG_VIA_RHINE is not set | 621 | # CONFIG_VIA_RHINE is not set |
| 622 | # CONFIG_SC92031 is not set | ||
| 478 | # CONFIG_NET_POCKET is not set | 623 | # CONFIG_NET_POCKET is not set |
| 479 | 624 | # CONFIG_ATL2 is not set | |
| 480 | # | 625 | CONFIG_NETDEV_1000=y |
| 481 | # Ethernet (1000 Mbit) | ||
| 482 | # | ||
| 483 | # CONFIG_ACENIC is not set | 626 | # CONFIG_ACENIC is not set |
| 484 | # CONFIG_DL2K is not set | 627 | # CONFIG_DL2K is not set |
| 485 | # CONFIG_E1000 is not set | 628 | # CONFIG_E1000 is not set |
| 629 | # CONFIG_E1000E is not set | ||
| 630 | # CONFIG_IP1000 is not set | ||
| 631 | # CONFIG_IGB is not set | ||
| 486 | # CONFIG_NS83820 is not set | 632 | # CONFIG_NS83820 is not set |
| 487 | # CONFIG_HAMACHI is not set | 633 | # CONFIG_HAMACHI is not set |
| 488 | # CONFIG_YELLOWFIN is not set | 634 | # CONFIG_YELLOWFIN is not set |
| 489 | # CONFIG_R8169 is not set | 635 | # CONFIG_R8169 is not set |
| 636 | # CONFIG_SIS190 is not set | ||
| 490 | # CONFIG_SKGE is not set | 637 | # CONFIG_SKGE is not set |
| 491 | # CONFIG_SK98LIN is not set | 638 | # CONFIG_SKY2 is not set |
| 492 | # CONFIG_VIA_VELOCITY is not set | 639 | # CONFIG_VIA_VELOCITY is not set |
| 493 | # CONFIG_TIGON3 is not set | 640 | # CONFIG_TIGON3 is not set |
| 494 | # CONFIG_BNX2 is not set | 641 | # CONFIG_BNX2 is not set |
| 495 | 642 | # CONFIG_QLA3XXX is not set | |
| 496 | # | 643 | # CONFIG_ATL1 is not set |
| 497 | # Ethernet (10000 Mbit) | 644 | # CONFIG_ATL1E is not set |
| 498 | # | 645 | # CONFIG_JME is not set |
| 646 | CONFIG_NETDEV_10000=y | ||
| 647 | # CONFIG_CHELSIO_T1 is not set | ||
| 648 | CONFIG_CHELSIO_T3_DEPENDS=y | ||
| 649 | # CONFIG_CHELSIO_T3 is not set | ||
| 650 | # CONFIG_ENIC is not set | ||
| 651 | # CONFIG_IXGBE is not set | ||
| 499 | # CONFIG_IXGB is not set | 652 | # CONFIG_IXGB is not set |
| 500 | # CONFIG_S2IO is not set | 653 | # CONFIG_S2IO is not set |
| 501 | 654 | # CONFIG_MYRI10GE is not set | |
| 502 | # | 655 | # CONFIG_NETXEN_NIC is not set |
| 503 | # Token Ring devices | 656 | # CONFIG_NIU is not set |
| 504 | # | 657 | # CONFIG_MLX4_EN is not set |
| 658 | # CONFIG_MLX4_CORE is not set | ||
| 659 | # CONFIG_TEHUTI is not set | ||
| 660 | # CONFIG_BNX2X is not set | ||
| 661 | # CONFIG_QLGE is not set | ||
| 662 | # CONFIG_SFC is not set | ||
| 505 | # CONFIG_TR is not set | 663 | # CONFIG_TR is not set |
| 506 | 664 | ||
| 507 | # | 665 | # |
| 508 | # Wireless LAN (non-hamradio) | 666 | # Wireless LAN |
| 509 | # | ||
| 510 | # CONFIG_NET_RADIO is not set | ||
| 511 | |||
| 512 | # | ||
| 513 | # Wan interfaces | ||
| 514 | # | 667 | # |
| 668 | # CONFIG_WLAN_PRE80211 is not set | ||
| 669 | # CONFIG_WLAN_80211 is not set | ||
| 670 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 515 | # CONFIG_WAN is not set | 671 | # CONFIG_WAN is not set |
| 516 | # CONFIG_FDDI is not set | 672 | # CONFIG_FDDI is not set |
| 517 | # CONFIG_HIPPI is not set | 673 | # CONFIG_HIPPI is not set |
| @@ -519,18 +675,17 @@ CONFIG_CS89x0=y | |||
| 519 | # CONFIG_PPP is not set | 675 | # CONFIG_PPP is not set |
| 520 | # CONFIG_SLIP is not set | 676 | # CONFIG_SLIP is not set |
| 521 | # CONFIG_NET_FC is not set | 677 | # CONFIG_NET_FC is not set |
| 522 | # CONFIG_SHAPER is not set | ||
| 523 | # CONFIG_NETCONSOLE is not set | 678 | # CONFIG_NETCONSOLE is not set |
| 524 | 679 | # CONFIG_NETPOLL is not set | |
| 525 | # | 680 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 526 | # ISDN subsystem | ||
| 527 | # | ||
| 528 | # CONFIG_ISDN is not set | 681 | # CONFIG_ISDN is not set |
| 529 | 682 | ||
| 530 | # | 683 | # |
| 531 | # Input device support | 684 | # Input device support |
| 532 | # | 685 | # |
| 533 | CONFIG_INPUT=y | 686 | CONFIG_INPUT=y |
| 687 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 688 | # CONFIG_INPUT_POLLDEV is not set | ||
| 534 | 689 | ||
| 535 | # | 690 | # |
| 536 | # Userland interfaces | 691 | # Userland interfaces |
| @@ -540,7 +695,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 540 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 695 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 541 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 696 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 542 | # CONFIG_INPUT_JOYDEV is not set | 697 | # CONFIG_INPUT_JOYDEV is not set |
| 543 | # CONFIG_INPUT_TSDEV is not set | ||
| 544 | # CONFIG_INPUT_EVDEV is not set | 698 | # CONFIG_INPUT_EVDEV is not set |
| 545 | # CONFIG_INPUT_EVBUG is not set | 699 | # CONFIG_INPUT_EVBUG is not set |
| 546 | 700 | ||
| @@ -553,14 +707,25 @@ CONFIG_KEYBOARD_ATKBD=y | |||
| 553 | # CONFIG_KEYBOARD_LKKBD is not set | 707 | # CONFIG_KEYBOARD_LKKBD is not set |
| 554 | # CONFIG_KEYBOARD_XTKBD is not set | 708 | # CONFIG_KEYBOARD_XTKBD is not set |
| 555 | # CONFIG_KEYBOARD_NEWTON is not set | 709 | # CONFIG_KEYBOARD_NEWTON is not set |
| 710 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 556 | CONFIG_INPUT_MOUSE=y | 711 | CONFIG_INPUT_MOUSE=y |
| 557 | CONFIG_MOUSE_PS2=y | 712 | CONFIG_MOUSE_PS2=y |
| 713 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 714 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 715 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 716 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 717 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 718 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 719 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 558 | # CONFIG_MOUSE_SERIAL is not set | 720 | # CONFIG_MOUSE_SERIAL is not set |
| 721 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 722 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 559 | # CONFIG_MOUSE_INPORT is not set | 723 | # CONFIG_MOUSE_INPORT is not set |
| 560 | # CONFIG_MOUSE_LOGIBM is not set | 724 | # CONFIG_MOUSE_LOGIBM is not set |
| 561 | # CONFIG_MOUSE_PC110PAD is not set | 725 | # CONFIG_MOUSE_PC110PAD is not set |
| 562 | # CONFIG_MOUSE_VSXXXAA is not set | 726 | # CONFIG_MOUSE_VSXXXAA is not set |
| 563 | # CONFIG_INPUT_JOYSTICK is not set | 727 | # CONFIG_INPUT_JOYSTICK is not set |
| 728 | # CONFIG_INPUT_TABLET is not set | ||
| 564 | # CONFIG_INPUT_TOUCHSCREEN is not set | 729 | # CONFIG_INPUT_TOUCHSCREEN is not set |
| 565 | # CONFIG_INPUT_MISC is not set | 730 | # CONFIG_INPUT_MISC is not set |
| 566 | 731 | ||
| @@ -580,16 +745,22 @@ CONFIG_SERIO_LIBPS2=y | |||
| 580 | # Character devices | 745 | # Character devices |
| 581 | # | 746 | # |
| 582 | CONFIG_VT=y | 747 | CONFIG_VT=y |
| 748 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 583 | CONFIG_VT_CONSOLE=y | 749 | CONFIG_VT_CONSOLE=y |
| 584 | CONFIG_HW_CONSOLE=y | 750 | CONFIG_HW_CONSOLE=y |
| 751 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 752 | CONFIG_DEVKMEM=y | ||
| 585 | # CONFIG_SERIAL_NONSTANDARD is not set | 753 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 754 | # CONFIG_NOZOMI is not set | ||
| 586 | 755 | ||
| 587 | # | 756 | # |
| 588 | # Serial drivers | 757 | # Serial drivers |
| 589 | # | 758 | # |
| 590 | CONFIG_SERIAL_8250=y | 759 | CONFIG_SERIAL_8250=y |
| 591 | CONFIG_SERIAL_8250_CONSOLE=y | 760 | CONFIG_SERIAL_8250_CONSOLE=y |
| 761 | CONFIG_SERIAL_8250_PCI=y | ||
| 592 | CONFIG_SERIAL_8250_NR_UARTS=4 | 762 | CONFIG_SERIAL_8250_NR_UARTS=4 |
| 763 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 593 | # CONFIG_SERIAL_8250_EXTENDED is not set | 764 | # CONFIG_SERIAL_8250_EXTENDED is not set |
| 594 | 765 | ||
| 595 | # | 766 | # |
| @@ -599,90 +770,122 @@ CONFIG_SERIAL_CORE=y | |||
| 599 | CONFIG_SERIAL_CORE_CONSOLE=y | 770 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 600 | # CONFIG_SERIAL_JSM is not set | 771 | # CONFIG_SERIAL_JSM is not set |
| 601 | CONFIG_UNIX98_PTYS=y | 772 | CONFIG_UNIX98_PTYS=y |
| 773 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 602 | CONFIG_LEGACY_PTYS=y | 774 | CONFIG_LEGACY_PTYS=y |
| 603 | CONFIG_LEGACY_PTY_COUNT=256 | 775 | CONFIG_LEGACY_PTY_COUNT=256 |
| 604 | CONFIG_PRINTER=m | 776 | CONFIG_PRINTER=m |
| 605 | # CONFIG_LP_CONSOLE is not set | 777 | # CONFIG_LP_CONSOLE is not set |
| 606 | # CONFIG_PPDEV is not set | 778 | # CONFIG_PPDEV is not set |
| 607 | # CONFIG_TIPAR is not set | ||
| 608 | |||
| 609 | # | ||
| 610 | # IPMI | ||
| 611 | # | ||
| 612 | # CONFIG_IPMI_HANDLER is not set | 779 | # CONFIG_IPMI_HANDLER is not set |
| 613 | 780 | CONFIG_HW_RANDOM=m | |
| 614 | # | ||
| 615 | # Watchdog Cards | ||
| 616 | # | ||
| 617 | # CONFIG_WATCHDOG is not set | ||
| 618 | # CONFIG_NVRAM is not set | 781 | # CONFIG_NVRAM is not set |
| 619 | CONFIG_RTC=y | ||
| 620 | # CONFIG_DTLK is not set | 782 | # CONFIG_DTLK is not set |
| 621 | # CONFIG_R3964 is not set | 783 | # CONFIG_R3964 is not set |
| 622 | # CONFIG_APPLICOM is not set | 784 | # CONFIG_APPLICOM is not set |
| 623 | |||
| 624 | # | ||
| 625 | # Ftape, the floppy tape device driver | ||
| 626 | # | ||
| 627 | # CONFIG_DRM is not set | ||
| 628 | # CONFIG_RAW_DRIVER is not set | 785 | # CONFIG_RAW_DRIVER is not set |
| 786 | # CONFIG_TCG_TPM is not set | ||
| 787 | CONFIG_DEVPORT=y | ||
| 788 | # CONFIG_I2C is not set | ||
| 789 | # CONFIG_SPI is not set | ||
| 790 | # CONFIG_W1 is not set | ||
| 791 | # CONFIG_POWER_SUPPLY is not set | ||
| 792 | # CONFIG_HWMON is not set | ||
| 793 | # CONFIG_THERMAL is not set | ||
| 794 | # CONFIG_THERMAL_HWMON is not set | ||
| 795 | # CONFIG_WATCHDOG is not set | ||
| 796 | CONFIG_SSB_POSSIBLE=y | ||
| 629 | 797 | ||
| 630 | # | 798 | # |
| 631 | # TPM devices | 799 | # Sonics Silicon Backplane |
| 632 | # | 800 | # |
| 633 | # CONFIG_TCG_TPM is not set | 801 | # CONFIG_SSB is not set |
| 634 | 802 | ||
| 635 | # | 803 | # |
| 636 | # I2C support | 804 | # Multifunction device drivers |
| 637 | # | 805 | # |
| 638 | # CONFIG_I2C is not set | 806 | # CONFIG_MFD_CORE is not set |
| 807 | # CONFIG_MFD_SM501 is not set | ||
| 808 | # CONFIG_HTC_PASIC3 is not set | ||
| 809 | # CONFIG_MFD_TMIO is not set | ||
| 639 | 810 | ||
| 640 | # | 811 | # |
| 641 | # Misc devices | 812 | # Multimedia devices |
| 642 | # | 813 | # |
| 643 | 814 | ||
| 644 | # | 815 | # |
| 645 | # Multimedia devices | 816 | # Multimedia core support |
| 646 | # | 817 | # |
| 647 | # CONFIG_VIDEO_DEV is not set | 818 | # CONFIG_VIDEO_DEV is not set |
| 819 | # CONFIG_DVB_CORE is not set | ||
| 820 | # CONFIG_VIDEO_MEDIA is not set | ||
| 648 | 821 | ||
| 649 | # | 822 | # |
| 650 | # Digital Video Broadcasting Devices | 823 | # Multimedia drivers |
| 651 | # | 824 | # |
| 652 | # CONFIG_DVB is not set | 825 | # CONFIG_DAB is not set |
| 653 | 826 | ||
| 654 | # | 827 | # |
| 655 | # Graphics support | 828 | # Graphics support |
| 656 | # | 829 | # |
| 830 | # CONFIG_DRM is not set | ||
| 831 | # CONFIG_VGASTATE is not set | ||
| 832 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 657 | CONFIG_FB=y | 833 | CONFIG_FB=y |
| 834 | # CONFIG_FIRMWARE_EDID is not set | ||
| 835 | # CONFIG_FB_DDC is not set | ||
| 836 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 658 | CONFIG_FB_CFB_FILLRECT=y | 837 | CONFIG_FB_CFB_FILLRECT=y |
| 659 | CONFIG_FB_CFB_COPYAREA=y | 838 | CONFIG_FB_CFB_COPYAREA=y |
| 660 | CONFIG_FB_CFB_IMAGEBLIT=y | 839 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 661 | CONFIG_FB_SOFT_CURSOR=y | 840 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set |
| 841 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 842 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 843 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 844 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 845 | # CONFIG_FB_SYS_FOPS is not set | ||
| 846 | # CONFIG_FB_SVGALIB is not set | ||
| 662 | # CONFIG_FB_MACMODES is not set | 847 | # CONFIG_FB_MACMODES is not set |
| 848 | # CONFIG_FB_BACKLIGHT is not set | ||
| 663 | # CONFIG_FB_MODE_HELPERS is not set | 849 | # CONFIG_FB_MODE_HELPERS is not set |
| 664 | # CONFIG_FB_TILEBLITTING is not set | 850 | # CONFIG_FB_TILEBLITTING is not set |
| 851 | |||
| 852 | # | ||
| 853 | # Frame buffer hardware drivers | ||
| 854 | # | ||
| 665 | # CONFIG_FB_CIRRUS is not set | 855 | # CONFIG_FB_CIRRUS is not set |
| 666 | # CONFIG_FB_PM2 is not set | 856 | # CONFIG_FB_PM2 is not set |
| 667 | CONFIG_FB_CYBER2000=y | 857 | CONFIG_FB_CYBER2000=y |
| 668 | # CONFIG_FB_ASILIANT is not set | 858 | # CONFIG_FB_ASILIANT is not set |
| 669 | # CONFIG_FB_IMSTT is not set | 859 | # CONFIG_FB_IMSTT is not set |
| 860 | # CONFIG_FB_S1D13XXX is not set | ||
| 670 | # CONFIG_FB_NVIDIA is not set | 861 | # CONFIG_FB_NVIDIA is not set |
| 671 | # CONFIG_FB_RIVA is not set | 862 | # CONFIG_FB_RIVA is not set |
| 672 | # CONFIG_FB_MATROX is not set | 863 | # CONFIG_FB_MATROX is not set |
| 673 | # CONFIG_FB_RADEON_OLD is not set | ||
| 674 | # CONFIG_FB_RADEON is not set | 864 | # CONFIG_FB_RADEON is not set |
| 675 | # CONFIG_FB_ATY128 is not set | 865 | # CONFIG_FB_ATY128 is not set |
| 676 | # CONFIG_FB_ATY is not set | 866 | # CONFIG_FB_ATY is not set |
| 867 | # CONFIG_FB_S3 is not set | ||
| 677 | # CONFIG_FB_SAVAGE is not set | 868 | # CONFIG_FB_SAVAGE is not set |
| 678 | # CONFIG_FB_SIS is not set | 869 | # CONFIG_FB_SIS is not set |
| 870 | # CONFIG_FB_VIA is not set | ||
| 679 | # CONFIG_FB_NEOMAGIC is not set | 871 | # CONFIG_FB_NEOMAGIC is not set |
| 680 | # CONFIG_FB_KYRO is not set | 872 | # CONFIG_FB_KYRO is not set |
| 681 | # CONFIG_FB_3DFX is not set | 873 | # CONFIG_FB_3DFX is not set |
| 682 | # CONFIG_FB_VOODOO1 is not set | 874 | # CONFIG_FB_VOODOO1 is not set |
| 875 | # CONFIG_FB_VT8623 is not set | ||
| 683 | # CONFIG_FB_TRIDENT is not set | 876 | # CONFIG_FB_TRIDENT is not set |
| 684 | # CONFIG_FB_S1D13XXX is not set | 877 | # CONFIG_FB_ARK is not set |
| 878 | # CONFIG_FB_PM3 is not set | ||
| 879 | # CONFIG_FB_CARMINE is not set | ||
| 685 | # CONFIG_FB_VIRTUAL is not set | 880 | # CONFIG_FB_VIRTUAL is not set |
| 881 | # CONFIG_FB_METRONOME is not set | ||
| 882 | # CONFIG_FB_MB862XX is not set | ||
| 883 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 884 | |||
| 885 | # | ||
| 886 | # Display device support | ||
| 887 | # | ||
| 888 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 686 | 889 | ||
| 687 | # | 890 | # |
| 688 | # Console display driver support | 891 | # Console display driver support |
| @@ -691,126 +894,132 @@ CONFIG_FB_CYBER2000=y | |||
| 691 | # CONFIG_MDA_CONSOLE is not set | 894 | # CONFIG_MDA_CONSOLE is not set |
| 692 | CONFIG_DUMMY_CONSOLE=y | 895 | CONFIG_DUMMY_CONSOLE=y |
| 693 | CONFIG_FRAMEBUFFER_CONSOLE=y | 896 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 897 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 898 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 694 | # CONFIG_FONTS is not set | 899 | # CONFIG_FONTS is not set |
| 695 | CONFIG_FONT_8x8=y | 900 | CONFIG_FONT_8x8=y |
| 696 | CONFIG_FONT_8x16=y | 901 | CONFIG_FONT_8x16=y |
| 697 | |||
| 698 | # | ||
| 699 | # Logo configuration | ||
| 700 | # | ||
| 701 | CONFIG_LOGO=y | 902 | CONFIG_LOGO=y |
| 702 | # CONFIG_LOGO_LINUX_MONO is not set | 903 | # CONFIG_LOGO_LINUX_MONO is not set |
| 703 | # CONFIG_LOGO_LINUX_VGA16 is not set | 904 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 704 | CONFIG_LOGO_LINUX_CLUT224=y | 905 | CONFIG_LOGO_LINUX_CLUT224=y |
| 705 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 706 | |||
| 707 | # | ||
| 708 | # Sound | ||
| 709 | # | ||
| 710 | CONFIG_SOUND=m | 906 | CONFIG_SOUND=m |
| 711 | 907 | CONFIG_SOUND_OSS_CORE=y | |
| 712 | # | ||
| 713 | # Advanced Linux Sound Architecture | ||
| 714 | # | ||
| 715 | # CONFIG_SND is not set | 908 | # CONFIG_SND is not set |
| 716 | |||
| 717 | # | ||
| 718 | # Open Sound System | ||
| 719 | # | ||
| 720 | CONFIG_SOUND_PRIME=m | 909 | CONFIG_SOUND_PRIME=m |
| 721 | # CONFIG_SOUND_BT878 is not set | ||
| 722 | # CONFIG_SOUND_CMPCI is not set | ||
| 723 | # CONFIG_SOUND_EMU10K1 is not set | ||
| 724 | # CONFIG_SOUND_FUSION is not set | ||
| 725 | # CONFIG_SOUND_CS4281 is not set | ||
| 726 | # CONFIG_SOUND_ES1370 is not set | ||
| 727 | # CONFIG_SOUND_ES1371 is not set | ||
| 728 | # CONFIG_SOUND_ESSSOLO1 is not set | ||
| 729 | # CONFIG_SOUND_MAESTRO is not set | ||
| 730 | # CONFIG_SOUND_MAESTRO3 is not set | ||
| 731 | # CONFIG_SOUND_ICH is not set | ||
| 732 | # CONFIG_SOUND_SONICVIBES is not set | ||
| 733 | # CONFIG_SOUND_TRIDENT is not set | ||
| 734 | # CONFIG_SOUND_MSNDCLAS is not set | 910 | # CONFIG_SOUND_MSNDCLAS is not set |
| 735 | # CONFIG_SOUND_MSNDPIN is not set | 911 | # CONFIG_SOUND_MSNDPIN is not set |
| 736 | # CONFIG_SOUND_VIA82CXXX is not set | ||
| 737 | CONFIG_SOUND_OSS=m | 912 | CONFIG_SOUND_OSS=m |
| 738 | # CONFIG_SOUND_TRACEINIT is not set | 913 | # CONFIG_SOUND_TRACEINIT is not set |
| 739 | # CONFIG_SOUND_DMAP is not set | 914 | # CONFIG_SOUND_DMAP is not set |
| 740 | # CONFIG_SOUND_AD1816 is not set | ||
| 741 | # CONFIG_SOUND_AD1889 is not set | ||
| 742 | # CONFIG_SOUND_SGALAXY is not set | ||
| 743 | CONFIG_SOUND_ADLIB=m | ||
| 744 | # CONFIG_SOUND_ACI_MIXER is not set | ||
| 745 | # CONFIG_SOUND_CS4232 is not set | ||
| 746 | # CONFIG_SOUND_SSCAPE is not set | 915 | # CONFIG_SOUND_SSCAPE is not set |
| 747 | # CONFIG_SOUND_GUS is not set | ||
| 748 | # CONFIG_SOUND_VMIDI is not set | 916 | # CONFIG_SOUND_VMIDI is not set |
| 749 | # CONFIG_SOUND_TRIX is not set | 917 | # CONFIG_SOUND_TRIX is not set |
| 750 | # CONFIG_SOUND_MSS is not set | 918 | # CONFIG_SOUND_MSS is not set |
| 751 | # CONFIG_SOUND_MPU401 is not set | 919 | # CONFIG_SOUND_MPU401 is not set |
| 752 | # CONFIG_SOUND_NM256 is not set | ||
| 753 | # CONFIG_SOUND_MAD16 is not set | ||
| 754 | # CONFIG_SOUND_PAS is not set | 920 | # CONFIG_SOUND_PAS is not set |
| 755 | # CONFIG_SOUND_PSS is not set | 921 | # CONFIG_SOUND_PSS is not set |
| 756 | CONFIG_SOUND_SB=m | 922 | CONFIG_SOUND_SB=m |
| 757 | # CONFIG_SOUND_AWE32_SYNTH is not set | ||
| 758 | # CONFIG_SOUND_WAVEFRONT is not set | ||
| 759 | # CONFIG_SOUND_MAUI is not set | ||
| 760 | # CONFIG_SOUND_YM3812 is not set | 923 | # CONFIG_SOUND_YM3812 is not set |
| 761 | # CONFIG_SOUND_OPL3SA1 is not set | ||
| 762 | # CONFIG_SOUND_OPL3SA2 is not set | ||
| 763 | # CONFIG_SOUND_YMFPCI is not set | ||
| 764 | # CONFIG_SOUND_UART6850 is not set | 924 | # CONFIG_SOUND_UART6850 is not set |
| 765 | # CONFIG_SOUND_AEDSP16 is not set | 925 | # CONFIG_SOUND_AEDSP16 is not set |
| 766 | # CONFIG_SOUND_KAHLUA is not set | 926 | # CONFIG_SOUND_KAHLUA is not set |
| 767 | # CONFIG_SOUND_ALI5455 is not set | 927 | CONFIG_HID_SUPPORT=y |
| 768 | # CONFIG_SOUND_FORTE is not set | 928 | CONFIG_HID=y |
| 769 | # CONFIG_SOUND_RME96XX is not set | 929 | # CONFIG_HID_DEBUG is not set |
| 770 | # CONFIG_SOUND_AD1980 is not set | 930 | # CONFIG_HIDRAW is not set |
| 931 | # CONFIG_HID_PID is not set | ||
| 771 | 932 | ||
| 772 | # | 933 | # |
| 773 | # USB support | 934 | # Special HID drivers |
| 774 | # | 935 | # |
| 936 | CONFIG_HID_COMPAT=y | ||
| 937 | CONFIG_USB_SUPPORT=y | ||
| 775 | CONFIG_USB_ARCH_HAS_HCD=y | 938 | CONFIG_USB_ARCH_HAS_HCD=y |
| 776 | CONFIG_USB_ARCH_HAS_OHCI=y | 939 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 940 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 777 | # CONFIG_USB is not set | 941 | # CONFIG_USB is not set |
| 778 | 942 | ||
| 779 | # | 943 | # |
| 780 | # USB Gadget Support | 944 | # Enable Host or Gadget support to see Inventra options |
| 781 | # | 945 | # |
| 782 | # CONFIG_USB_GADGET is not set | ||
| 783 | 946 | ||
| 784 | # | 947 | # |
| 785 | # MMC/SD Card support | 948 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 786 | # | 949 | # |
| 950 | # CONFIG_USB_GADGET is not set | ||
| 951 | # CONFIG_UWB is not set | ||
| 787 | # CONFIG_MMC is not set | 952 | # CONFIG_MMC is not set |
| 953 | # CONFIG_MEMSTICK is not set | ||
| 954 | # CONFIG_ACCESSIBILITY is not set | ||
| 955 | # CONFIG_NEW_LEDS is not set | ||
| 956 | CONFIG_RTC_LIB=y | ||
| 957 | CONFIG_RTC_CLASS=y | ||
| 958 | CONFIG_RTC_HCTOSYS=y | ||
| 959 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 960 | # CONFIG_RTC_DEBUG is not set | ||
| 961 | |||
| 962 | # | ||
| 963 | # RTC interfaces | ||
| 964 | # | ||
| 965 | CONFIG_RTC_INTF_SYSFS=y | ||
| 966 | CONFIG_RTC_INTF_PROC=y | ||
| 967 | CONFIG_RTC_INTF_DEV=y | ||
| 968 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 969 | # CONFIG_RTC_DRV_TEST is not set | ||
| 970 | |||
| 971 | # | ||
| 972 | # SPI RTC drivers | ||
| 973 | # | ||
| 974 | |||
| 975 | # | ||
| 976 | # Platform RTC drivers | ||
| 977 | # | ||
| 978 | CONFIG_RTC_DRV_CMOS=y | ||
| 979 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 980 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 981 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 982 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 983 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 984 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 985 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 986 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 987 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 988 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 989 | |||
| 990 | # | ||
| 991 | # on-CPU RTC drivers | ||
| 992 | # | ||
| 993 | # CONFIG_DMADEVICES is not set | ||
| 994 | # CONFIG_AUXDISPLAY is not set | ||
| 995 | # CONFIG_REGULATOR is not set | ||
| 996 | # CONFIG_UIO is not set | ||
| 788 | 997 | ||
| 789 | # | 998 | # |
| 790 | # File systems | 999 | # File systems |
| 791 | # | 1000 | # |
| 792 | CONFIG_EXT2_FS=y | 1001 | CONFIG_EXT2_FS=y |
| 793 | # CONFIG_EXT2_FS_XATTR is not set | 1002 | # CONFIG_EXT2_FS_XATTR is not set |
| 1003 | # CONFIG_EXT2_FS_XIP is not set | ||
| 794 | CONFIG_EXT3_FS=y | 1004 | CONFIG_EXT3_FS=y |
| 795 | CONFIG_EXT3_FS_XATTR=y | 1005 | CONFIG_EXT3_FS_XATTR=y |
| 796 | # CONFIG_EXT3_FS_POSIX_ACL is not set | 1006 | # CONFIG_EXT3_FS_POSIX_ACL is not set |
| 797 | # CONFIG_EXT3_FS_SECURITY is not set | 1007 | # CONFIG_EXT3_FS_SECURITY is not set |
| 1008 | # CONFIG_EXT4_FS is not set | ||
| 798 | CONFIG_JBD=y | 1009 | CONFIG_JBD=y |
| 799 | # CONFIG_JBD_DEBUG is not set | ||
| 800 | CONFIG_FS_MBCACHE=y | 1010 | CONFIG_FS_MBCACHE=y |
| 801 | # CONFIG_REISERFS_FS is not set | 1011 | # CONFIG_REISERFS_FS is not set |
| 802 | # CONFIG_JFS_FS is not set | 1012 | # CONFIG_JFS_FS is not set |
| 803 | 1013 | # CONFIG_FS_POSIX_ACL is not set | |
| 804 | # | 1014 | CONFIG_FILE_LOCKING=y |
| 805 | # XFS support | ||
| 806 | # | ||
| 807 | # CONFIG_XFS_FS is not set | 1015 | # CONFIG_XFS_FS is not set |
| 808 | # CONFIG_MINIX_FS is not set | 1016 | # CONFIG_OCFS2_FS is not set |
| 809 | # CONFIG_ROMFS_FS is not set | ||
| 810 | # CONFIG_QUOTA is not set | ||
| 811 | CONFIG_DNOTIFY=y | 1017 | CONFIG_DNOTIFY=y |
| 1018 | # CONFIG_INOTIFY is not set | ||
| 1019 | # CONFIG_QUOTA is not set | ||
| 812 | # CONFIG_AUTOFS_FS is not set | 1020 | # CONFIG_AUTOFS_FS is not set |
| 813 | # CONFIG_AUTOFS4_FS is not set | 1021 | # CONFIG_AUTOFS4_FS is not set |
| 1022 | # CONFIG_FUSE_FS is not set | ||
| 814 | 1023 | ||
| 815 | # | 1024 | # |
| 816 | # CD-ROM/DVD Filesystems | 1025 | # CD-ROM/DVD Filesystems |
| @@ -834,14 +1043,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 834 | # Pseudo filesystems | 1043 | # Pseudo filesystems |
| 835 | # | 1044 | # |
| 836 | CONFIG_PROC_FS=y | 1045 | CONFIG_PROC_FS=y |
| 1046 | CONFIG_PROC_SYSCTL=y | ||
| 1047 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 837 | CONFIG_SYSFS=y | 1048 | CONFIG_SYSFS=y |
| 838 | CONFIG_DEVFS_FS=y | ||
| 839 | CONFIG_DEVFS_MOUNT=y | ||
| 840 | # CONFIG_DEVFS_DEBUG is not set | ||
| 841 | # CONFIG_DEVPTS_FS_XATTR is not set | ||
| 842 | # CONFIG_TMPFS is not set | 1049 | # CONFIG_TMPFS is not set |
| 843 | # CONFIG_HUGETLB_PAGE is not set | 1050 | # CONFIG_HUGETLB_PAGE is not set |
| 844 | CONFIG_RAMFS=y | 1051 | # CONFIG_CONFIGFS_FS is not set |
| 845 | 1052 | ||
| 846 | # | 1053 | # |
| 847 | # Miscellaneous filesystems | 1054 | # Miscellaneous filesystems |
| @@ -855,22 +1062,27 @@ CONFIG_RAMFS=y | |||
| 855 | # CONFIG_EFS_FS is not set | 1062 | # CONFIG_EFS_FS is not set |
| 856 | # CONFIG_CRAMFS is not set | 1063 | # CONFIG_CRAMFS is not set |
| 857 | # CONFIG_VXFS_FS is not set | 1064 | # CONFIG_VXFS_FS is not set |
| 1065 | # CONFIG_MINIX_FS is not set | ||
| 1066 | # CONFIG_OMFS_FS is not set | ||
| 858 | # CONFIG_HPFS_FS is not set | 1067 | # CONFIG_HPFS_FS is not set |
| 859 | # CONFIG_QNX4FS_FS is not set | 1068 | # CONFIG_QNX4FS_FS is not set |
| 1069 | # CONFIG_ROMFS_FS is not set | ||
| 860 | # CONFIG_SYSV_FS is not set | 1070 | # CONFIG_SYSV_FS is not set |
| 861 | # CONFIG_UFS_FS is not set | 1071 | # CONFIG_UFS_FS is not set |
| 862 | 1072 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 863 | # | 1073 | CONFIG_NFS_FS=y |
| 864 | # Network File Systems | ||
| 865 | # | ||
| 866 | CONFIG_NFS_FS=m | ||
| 867 | CONFIG_NFS_V3=y | 1074 | CONFIG_NFS_V3=y |
| 1075 | # CONFIG_NFS_V3_ACL is not set | ||
| 868 | # CONFIG_NFS_V4 is not set | 1076 | # CONFIG_NFS_V4 is not set |
| 869 | # CONFIG_NFS_DIRECTIO is not set | 1077 | CONFIG_NFSD=m |
| 870 | # CONFIG_NFSD is not set | 1078 | # CONFIG_NFSD_V3 is not set |
| 871 | CONFIG_LOCKD=m | 1079 | # CONFIG_NFSD_V4 is not set |
| 1080 | CONFIG_LOCKD=y | ||
| 872 | CONFIG_LOCKD_V4=y | 1081 | CONFIG_LOCKD_V4=y |
| 873 | CONFIG_SUNRPC=m | 1082 | CONFIG_EXPORTFS=m |
| 1083 | CONFIG_NFS_COMMON=y | ||
| 1084 | CONFIG_SUNRPC=y | ||
| 1085 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 874 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1086 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 875 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1087 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 876 | # CONFIG_SMB_FS is not set | 1088 | # CONFIG_SMB_FS is not set |
| @@ -897,11 +1109,9 @@ CONFIG_MSDOS_PARTITION=y | |||
| 897 | # CONFIG_SGI_PARTITION is not set | 1109 | # CONFIG_SGI_PARTITION is not set |
| 898 | # CONFIG_ULTRIX_PARTITION is not set | 1110 | # CONFIG_ULTRIX_PARTITION is not set |
| 899 | # CONFIG_SUN_PARTITION is not set | 1111 | # CONFIG_SUN_PARTITION is not set |
| 1112 | # CONFIG_KARMA_PARTITION is not set | ||
| 900 | # CONFIG_EFI_PARTITION is not set | 1113 | # CONFIG_EFI_PARTITION is not set |
| 901 | 1114 | # CONFIG_SYSV68_PARTITION is not set | |
| 902 | # | ||
| 903 | # Native Language Support | ||
| 904 | # | ||
| 905 | CONFIG_NLS=m | 1115 | CONFIG_NLS=m |
| 906 | CONFIG_NLS_DEFAULT="iso8859-1" | 1116 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 907 | CONFIG_NLS_CODEPAGE_437=m | 1117 | CONFIG_NLS_CODEPAGE_437=m |
| @@ -942,30 +1152,74 @@ CONFIG_NLS_ISO8859_1=m | |||
| 942 | # CONFIG_NLS_KOI8_R is not set | 1152 | # CONFIG_NLS_KOI8_R is not set |
| 943 | # CONFIG_NLS_KOI8_U is not set | 1153 | # CONFIG_NLS_KOI8_U is not set |
| 944 | # CONFIG_NLS_UTF8 is not set | 1154 | # CONFIG_NLS_UTF8 is not set |
| 945 | 1155 | # CONFIG_DLM is not set | |
| 946 | # | ||
| 947 | # Profiling support | ||
| 948 | # | ||
| 949 | # CONFIG_PROFILING is not set | ||
| 950 | 1156 | ||
| 951 | # | 1157 | # |
| 952 | # Kernel hacking | 1158 | # Kernel hacking |
| 953 | # | 1159 | # |
| 954 | # CONFIG_PRINTK_TIME is not set | 1160 | # CONFIG_PRINTK_TIME is not set |
| 955 | CONFIG_DEBUG_KERNEL=y | 1161 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 1162 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 1163 | CONFIG_FRAME_WARN=1024 | ||
| 956 | # CONFIG_MAGIC_SYSRQ is not set | 1164 | # CONFIG_MAGIC_SYSRQ is not set |
| 957 | CONFIG_LOG_BUF_SHIFT=14 | 1165 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1166 | # CONFIG_DEBUG_FS is not set | ||
| 1167 | # CONFIG_HEADERS_CHECK is not set | ||
| 1168 | CONFIG_DEBUG_KERNEL=y | ||
| 1169 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1170 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1171 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1172 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1173 | # CONFIG_SCHED_DEBUG is not set | ||
| 958 | # CONFIG_SCHEDSTATS is not set | 1174 | # CONFIG_SCHEDSTATS is not set |
| 1175 | # CONFIG_TIMER_STATS is not set | ||
| 1176 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 959 | # CONFIG_DEBUG_SLAB is not set | 1177 | # CONFIG_DEBUG_SLAB is not set |
| 1178 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1179 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 960 | # CONFIG_DEBUG_SPINLOCK is not set | 1180 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1181 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1182 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1183 | # CONFIG_PROVE_LOCKING is not set | ||
| 1184 | # CONFIG_LOCK_STAT is not set | ||
| 961 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1185 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1186 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 962 | # CONFIG_DEBUG_KOBJECT is not set | 1187 | # CONFIG_DEBUG_KOBJECT is not set |
| 963 | CONFIG_DEBUG_BUGVERBOSE=y | 1188 | CONFIG_DEBUG_BUGVERBOSE=y |
| 964 | # CONFIG_DEBUG_INFO is not set | 1189 | # CONFIG_DEBUG_INFO is not set |
| 965 | # CONFIG_DEBUG_FS is not set | 1190 | # CONFIG_DEBUG_VM is not set |
| 1191 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1192 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1193 | # CONFIG_DEBUG_LIST is not set | ||
| 1194 | # CONFIG_DEBUG_SG is not set | ||
| 1195 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 966 | CONFIG_FRAME_POINTER=y | 1196 | CONFIG_FRAME_POINTER=y |
| 1197 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1198 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1199 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1200 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1201 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1202 | # CONFIG_FAULT_INJECTION is not set | ||
| 1203 | # CONFIG_LATENCYTOP is not set | ||
| 1204 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1205 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1206 | |||
| 1207 | # | ||
| 1208 | # Tracers | ||
| 1209 | # | ||
| 1210 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1211 | # CONFIG_SCHED_TRACER is not set | ||
| 1212 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1213 | # CONFIG_BOOT_TRACER is not set | ||
| 1214 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1215 | # CONFIG_STACK_TRACER is not set | ||
| 1216 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1217 | # CONFIG_SAMPLES is not set | ||
| 1218 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1219 | # CONFIG_KGDB is not set | ||
| 967 | CONFIG_DEBUG_USER=y | 1220 | CONFIG_DEBUG_USER=y |
| 968 | # CONFIG_DEBUG_ERRORS is not set | 1221 | # CONFIG_DEBUG_ERRORS is not set |
| 1222 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 969 | # CONFIG_DEBUG_LL is not set | 1223 | # CONFIG_DEBUG_LL is not set |
| 970 | 1224 | ||
| 971 | # | 1225 | # |
| @@ -973,19 +1227,23 @@ CONFIG_DEBUG_USER=y | |||
| 973 | # | 1227 | # |
| 974 | # CONFIG_KEYS is not set | 1228 | # CONFIG_KEYS is not set |
| 975 | # CONFIG_SECURITY is not set | 1229 | # CONFIG_SECURITY is not set |
| 976 | 1230 | # CONFIG_SECURITYFS is not set | |
| 977 | # | 1231 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 978 | # Cryptographic options | ||
| 979 | # | ||
| 980 | # CONFIG_CRYPTO is not set | 1232 | # CONFIG_CRYPTO is not set |
| 981 | 1233 | ||
| 982 | # | 1234 | # |
| 983 | # Hardware crypto devices | ||
| 984 | # | ||
| 985 | |||
| 986 | # | ||
| 987 | # Library routines | 1235 | # Library routines |
| 988 | # | 1236 | # |
| 1237 | CONFIG_BITREVERSE=y | ||
| 1238 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 989 | # CONFIG_CRC_CCITT is not set | 1239 | # CONFIG_CRC_CCITT is not set |
| 1240 | # CONFIG_CRC16 is not set | ||
| 1241 | # CONFIG_CRC_T10DIF is not set | ||
| 1242 | # CONFIG_CRC_ITU_T is not set | ||
| 990 | CONFIG_CRC32=y | 1243 | CONFIG_CRC32=y |
| 1244 | # CONFIG_CRC7 is not set | ||
| 991 | # CONFIG_LIBCRC32C is not set | 1245 | # CONFIG_LIBCRC32C is not set |
| 1246 | CONFIG_PLIST=y | ||
| 1247 | CONFIG_HAS_IOMEM=y | ||
| 1248 | CONFIG_HAS_IOPORT=y | ||
| 1249 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig index 03f783e696b3..685d2b513206 100644 --- a/arch/arm/configs/simpad_defconfig +++ b/arch/arm/configs/simpad_defconfig | |||
| @@ -89,7 +89,6 @@ CONFIG_ARCH_SA1100=y | |||
| 89 | # CONFIG_SA1100_COLLIE is not set | 89 | # CONFIG_SA1100_COLLIE is not set |
| 90 | # CONFIG_SA1100_H3100 is not set | 90 | # CONFIG_SA1100_H3100 is not set |
| 91 | # CONFIG_SA1100_H3600 is not set | 91 | # CONFIG_SA1100_H3600 is not set |
| 92 | # CONFIG_SA1100_H3800 is not set | ||
| 93 | # CONFIG_SA1100_BADGE4 is not set | 92 | # CONFIG_SA1100_BADGE4 is not set |
| 94 | # CONFIG_SA1100_JORNADA720 is not set | 93 | # CONFIG_SA1100_JORNADA720 is not set |
| 95 | # CONFIG_SA1100_HACKKIT is not set | 94 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 6cbd8fdc9f1f..bb7d695f3900 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h | |||
| @@ -46,6 +46,14 @@ | |||
| 46 | # define MULTI_CACHE 1 | 46 | # define MULTI_CACHE 1 |
| 47 | #endif | 47 | #endif |
| 48 | 48 | ||
| 49 | #if defined(CONFIG_CPU_FA526) | ||
| 50 | # ifdef _CACHE | ||
| 51 | # define MULTI_CACHE 1 | ||
| 52 | # else | ||
| 53 | # define _CACHE fa | ||
| 54 | # endif | ||
| 55 | #endif | ||
| 56 | |||
| 49 | #if defined(CONFIG_CPU_ARM926T) | 57 | #if defined(CONFIG_CPU_ARM926T) |
| 50 | # ifdef _CACHE | 58 | # ifdef _CACHE |
| 51 | # define MULTI_CACHE 1 | 59 | # define MULTI_CACHE 1 |
| @@ -94,6 +102,14 @@ | |||
| 94 | # endif | 102 | # endif |
| 95 | #endif | 103 | #endif |
| 96 | 104 | ||
| 105 | #if defined(CONFIG_CPU_MOHAWK) | ||
| 106 | # ifdef _CACHE | ||
| 107 | # define MULTI_CACHE 1 | ||
| 108 | # else | ||
| 109 | # define _CACHE mohawk | ||
| 110 | # endif | ||
| 111 | #endif | ||
| 112 | |||
| 97 | #if defined(CONFIG_CPU_FEROCEON) | 113 | #if defined(CONFIG_CPU_FEROCEON) |
| 98 | # define MULTI_CACHE 1 | 114 | # define MULTI_CACHE 1 |
| 99 | #endif | 115 | #endif |
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 22cb14ec3438..ff46dfa68a97 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h | |||
| @@ -15,10 +15,20 @@ | |||
| 15 | * must not be used by drivers. | 15 | * must not be used by drivers. |
| 16 | */ | 16 | */ |
| 17 | #ifndef __arch_page_to_dma | 17 | #ifndef __arch_page_to_dma |
| 18 | |||
| 19 | #if !defined(CONFIG_HIGHMEM) | ||
| 18 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) | 20 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) |
| 19 | { | 21 | { |
| 20 | return (dma_addr_t)__virt_to_bus((unsigned long)page_address(page)); | 22 | return (dma_addr_t)__virt_to_bus((unsigned long)page_address(page)); |
| 21 | } | 23 | } |
| 24 | #elif defined(__pfn_to_bus) | ||
| 25 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) | ||
| 26 | { | ||
| 27 | return (dma_addr_t)__pfn_to_bus(page_to_pfn(page)); | ||
| 28 | } | ||
| 29 | #else | ||
| 30 | #error "this machine class needs to define __arch_page_to_dma to use HIGHMEM" | ||
| 31 | #endif | ||
| 22 | 32 | ||
| 23 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) | 33 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) |
| 24 | { | 34 | { |
| @@ -57,6 +67,8 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) | |||
| 57 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | 67 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) |
| 58 | */ | 68 | */ |
| 59 | extern void dma_cache_maint(const void *kaddr, size_t size, int rw); | 69 | extern void dma_cache_maint(const void *kaddr, size_t size, int rw); |
| 70 | extern void dma_cache_maint_page(struct page *page, unsigned long offset, | ||
| 71 | size_t size, int rw); | ||
| 60 | 72 | ||
| 61 | /* | 73 | /* |
| 62 | * Return whether the given device DMA address mask can be supported | 74 | * Return whether the given device DMA address mask can be supported |
| @@ -316,7 +328,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
| 316 | BUG_ON(!valid_dma_direction(dir)); | 328 | BUG_ON(!valid_dma_direction(dir)); |
| 317 | 329 | ||
| 318 | if (!arch_is_coherent()) | 330 | if (!arch_is_coherent()) |
| 319 | dma_cache_maint(page_address(page) + offset, size, dir); | 331 | dma_cache_maint_page(page, offset, size, dir); |
| 320 | 332 | ||
| 321 | return page_to_dma(dev, page) + offset; | 333 | return page_to_dma(dev, page) + offset; |
| 322 | } | 334 | } |
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index df5638f3643a..7edf3536df24 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h | |||
| @@ -19,21 +19,17 @@ | |||
| 19 | #include <asm/system.h> | 19 | #include <asm/system.h> |
| 20 | #include <asm/scatterlist.h> | 20 | #include <asm/scatterlist.h> |
| 21 | 21 | ||
| 22 | typedef unsigned int dmach_t; | ||
| 23 | |||
| 24 | #include <mach/isa-dma.h> | 22 | #include <mach/isa-dma.h> |
| 25 | 23 | ||
| 26 | /* | 24 | /* |
| 27 | * DMA modes | 25 | * The DMA modes reflect the settings for the ISA DMA controller |
| 28 | */ | 26 | */ |
| 29 | typedef unsigned int dmamode_t; | 27 | #define DMA_MODE_MASK 0xcc |
| 30 | |||
| 31 | #define DMA_MODE_MASK 3 | ||
| 32 | 28 | ||
| 33 | #define DMA_MODE_READ 0 | 29 | #define DMA_MODE_READ 0x44 |
| 34 | #define DMA_MODE_WRITE 1 | 30 | #define DMA_MODE_WRITE 0x48 |
| 35 | #define DMA_MODE_CASCADE 2 | 31 | #define DMA_MODE_CASCADE 0xc0 |
| 36 | #define DMA_AUTOINIT 4 | 32 | #define DMA_AUTOINIT 0x10 |
| 37 | 33 | ||
| 38 | extern spinlock_t dma_spin_lock; | 34 | extern spinlock_t dma_spin_lock; |
| 39 | 35 | ||
| @@ -52,44 +48,44 @@ static inline void release_dma_lock(unsigned long flags) | |||
| 52 | /* Clear the 'DMA Pointer Flip Flop'. | 48 | /* Clear the 'DMA Pointer Flip Flop'. |
| 53 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | 49 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. |
| 54 | */ | 50 | */ |
| 55 | #define clear_dma_ff(channel) | 51 | #define clear_dma_ff(chan) |
| 56 | 52 | ||
| 57 | /* Set only the page register bits of the transfer address. | 53 | /* Set only the page register bits of the transfer address. |
| 58 | * | 54 | * |
| 59 | * NOTE: This is an architecture specific function, and should | 55 | * NOTE: This is an architecture specific function, and should |
| 60 | * be hidden from the drivers | 56 | * be hidden from the drivers |
| 61 | */ | 57 | */ |
| 62 | extern void set_dma_page(dmach_t channel, char pagenr); | 58 | extern void set_dma_page(unsigned int chan, char pagenr); |
| 63 | 59 | ||
| 64 | /* Request a DMA channel | 60 | /* Request a DMA channel |
| 65 | * | 61 | * |
| 66 | * Some architectures may need to do allocate an interrupt | 62 | * Some architectures may need to do allocate an interrupt |
| 67 | */ | 63 | */ |
| 68 | extern int request_dma(dmach_t channel, const char * device_id); | 64 | extern int request_dma(unsigned int chan, const char * device_id); |
| 69 | 65 | ||
| 70 | /* Free a DMA channel | 66 | /* Free a DMA channel |
| 71 | * | 67 | * |
| 72 | * Some architectures may need to do free an interrupt | 68 | * Some architectures may need to do free an interrupt |
| 73 | */ | 69 | */ |
| 74 | extern void free_dma(dmach_t channel); | 70 | extern void free_dma(unsigned int chan); |
| 75 | 71 | ||
| 76 | /* Enable DMA for this channel | 72 | /* Enable DMA for this channel |
| 77 | * | 73 | * |
| 78 | * On some architectures, this may have other side effects like | 74 | * On some architectures, this may have other side effects like |
| 79 | * enabling an interrupt and setting the DMA registers. | 75 | * enabling an interrupt and setting the DMA registers. |
| 80 | */ | 76 | */ |
| 81 | extern void enable_dma(dmach_t channel); | 77 | extern void enable_dma(unsigned int chan); |
| 82 | 78 | ||
| 83 | /* Disable DMA for this channel | 79 | /* Disable DMA for this channel |
| 84 | * | 80 | * |
| 85 | * On some architectures, this may have other side effects like | 81 | * On some architectures, this may have other side effects like |
| 86 | * disabling an interrupt or whatever. | 82 | * disabling an interrupt or whatever. |
| 87 | */ | 83 | */ |
| 88 | extern void disable_dma(dmach_t channel); | 84 | extern void disable_dma(unsigned int chan); |
| 89 | 85 | ||
| 90 | /* Test whether the specified channel has an active DMA transfer | 86 | /* Test whether the specified channel has an active DMA transfer |
| 91 | */ | 87 | */ |
| 92 | extern int dma_channel_active(dmach_t channel); | 88 | extern int dma_channel_active(unsigned int chan); |
| 93 | 89 | ||
| 94 | /* Set the DMA scatter gather list for this channel | 90 | /* Set the DMA scatter gather list for this channel |
| 95 | * | 91 | * |
| @@ -97,7 +93,7 @@ extern int dma_channel_active(dmach_t channel); | |||
| 97 | * especially since some DMA architectures don't update the | 93 | * especially since some DMA architectures don't update the |
| 98 | * DMA address immediately, but defer it to the enable_dma(). | 94 | * DMA address immediately, but defer it to the enable_dma(). |
| 99 | */ | 95 | */ |
| 100 | extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg); | 96 | extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg); |
| 101 | 97 | ||
| 102 | /* Set the DMA address for this channel | 98 | /* Set the DMA address for this channel |
| 103 | * | 99 | * |
| @@ -105,9 +101,9 @@ extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg); | |||
| 105 | * especially since some DMA architectures don't update the | 101 | * especially since some DMA architectures don't update the |
| 106 | * DMA address immediately, but defer it to the enable_dma(). | 102 | * DMA address immediately, but defer it to the enable_dma(). |
| 107 | */ | 103 | */ |
| 108 | extern void __set_dma_addr(dmach_t channel, void *addr); | 104 | extern void __set_dma_addr(unsigned int chan, void *addr); |
| 109 | #define set_dma_addr(channel, addr) \ | 105 | #define set_dma_addr(chan, addr) \ |
| 110 | __set_dma_addr(channel, bus_to_virt(addr)) | 106 | __set_dma_addr(chan, bus_to_virt(addr)) |
| 111 | 107 | ||
| 112 | /* Set the DMA byte count for this channel | 108 | /* Set the DMA byte count for this channel |
| 113 | * | 109 | * |
| @@ -115,7 +111,7 @@ extern void __set_dma_addr(dmach_t channel, void *addr); | |||
| 115 | * especially since some DMA architectures don't update the | 111 | * especially since some DMA architectures don't update the |
| 116 | * DMA count immediately, but defer it to the enable_dma(). | 112 | * DMA count immediately, but defer it to the enable_dma(). |
| 117 | */ | 113 | */ |
| 118 | extern void set_dma_count(dmach_t channel, unsigned long count); | 114 | extern void set_dma_count(unsigned int chan, unsigned long count); |
| 119 | 115 | ||
| 120 | /* Set the transfer direction for this channel | 116 | /* Set the transfer direction for this channel |
| 121 | * | 117 | * |
| @@ -124,11 +120,11 @@ extern void set_dma_count(dmach_t channel, unsigned long count); | |||
| 124 | * DMA transfer direction immediately, but defer it to the | 120 | * DMA transfer direction immediately, but defer it to the |
| 125 | * enable_dma(). | 121 | * enable_dma(). |
| 126 | */ | 122 | */ |
| 127 | extern void set_dma_mode(dmach_t channel, dmamode_t mode); | 123 | extern void set_dma_mode(unsigned int chan, unsigned int mode); |
| 128 | 124 | ||
| 129 | /* Set the transfer speed for this channel | 125 | /* Set the transfer speed for this channel |
| 130 | */ | 126 | */ |
| 131 | extern void set_dma_speed(dmach_t channel, int cycle_ns); | 127 | extern void set_dma_speed(unsigned int chan, int cycle_ns); |
| 132 | 128 | ||
| 133 | /* Get DMA residue count. After a DMA transfer, this | 129 | /* Get DMA residue count. After a DMA transfer, this |
| 134 | * should return zero. Reading this while a DMA transfer is | 130 | * should return zero. Reading this while a DMA transfer is |
| @@ -136,7 +132,7 @@ extern void set_dma_speed(dmach_t channel, int cycle_ns); | |||
| 136 | * If called before the channel has been used, it may return 1. | 132 | * If called before the channel has been used, it may return 1. |
| 137 | * Otherwise, it returns the number of _bytes_ left to transfer. | 133 | * Otherwise, it returns the number of _bytes_ left to transfer. |
| 138 | */ | 134 | */ |
| 139 | extern int get_dma_residue(dmach_t channel); | 135 | extern int get_dma_residue(unsigned int chan); |
| 140 | 136 | ||
| 141 | #ifndef NO_DMA | 137 | #ifndef NO_DMA |
| 142 | #define NO_DMA 255 | 138 | #define NO_DMA 255 |
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index a58378c343b9..d7da19bcf928 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h | |||
| @@ -50,6 +50,8 @@ typedef struct user_fp elf_fpregset_t; | |||
| 50 | #define R_ARM_ABS32 2 | 50 | #define R_ARM_ABS32 2 |
| 51 | #define R_ARM_CALL 28 | 51 | #define R_ARM_CALL 28 |
| 52 | #define R_ARM_JUMP24 29 | 52 | #define R_ARM_JUMP24 29 |
| 53 | #define R_ARM_V4BX 40 | ||
| 54 | #define R_ARM_PREL31 42 | ||
| 53 | 55 | ||
| 54 | /* | 56 | /* |
| 55 | * These are used to set parameters in the core dumps. | 57 | * These are used to set parameters in the core dumps. |
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h new file mode 100644 index 000000000000..bbae919bceb4 --- /dev/null +++ b/arch/arm/include/asm/fixmap.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | #ifndef _ASM_FIXMAP_H | ||
| 2 | #define _ASM_FIXMAP_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Nothing too fancy for now. | ||
| 6 | * | ||
| 7 | * On ARM we already have well known fixed virtual addresses imposed by | ||
| 8 | * the architecture such as the vector page which is located at 0xffff0000, | ||
| 9 | * therefore a second level page table is already allocated covering | ||
| 10 | * 0xfff00000 upwards. | ||
| 11 | * | ||
| 12 | * The cache flushing code in proc-xscale.S uses the virtual area between | ||
| 13 | * 0xfffe0000 and 0xfffeffff. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define FIXADDR_START 0xfff00000UL | ||
| 17 | #define FIXADDR_TOP 0xfffe0000UL | ||
| 18 | #define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START) | ||
| 19 | |||
| 20 | #define FIX_KMAP_BEGIN 0 | ||
| 21 | #define FIX_KMAP_END (FIXADDR_SIZE >> PAGE_SHIFT) | ||
| 22 | |||
| 23 | #define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT)) | ||
| 24 | #define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT) | ||
| 25 | |||
| 26 | extern void __this_fixmap_does_not_exist(void); | ||
| 27 | |||
| 28 | static inline unsigned long fix_to_virt(const unsigned int idx) | ||
| 29 | { | ||
| 30 | if (idx >= FIX_KMAP_END) | ||
| 31 | __this_fixmap_does_not_exist(); | ||
| 32 | return __fix_to_virt(idx); | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline unsigned int virt_to_fix(const unsigned long vaddr) | ||
| 36 | { | ||
| 37 | BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START); | ||
| 38 | return __virt_to_fix(vaddr); | ||
| 39 | } | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h index dfb8330599f9..46492a63a7c4 100644 --- a/arch/arm/include/asm/hardware/scoop.h +++ b/arch/arm/include/asm/hardware/scoop.h | |||
| @@ -63,7 +63,5 @@ struct scoop_pcmcia_config { | |||
| 63 | extern struct scoop_pcmcia_config *platform_scoop_config; | 63 | extern struct scoop_pcmcia_config *platform_scoop_config; |
| 64 | 64 | ||
| 65 | void reset_scoop(struct device *dev); | 65 | void reset_scoop(struct device *dev); |
| 66 | unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit); | ||
| 67 | unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit); | ||
| 68 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg); | 66 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg); |
| 69 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); | 67 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); |
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h new file mode 100644 index 000000000000..7f36d00600b4 --- /dev/null +++ b/arch/arm/include/asm/highmem.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _ASM_HIGHMEM_H | ||
| 2 | #define _ASM_HIGHMEM_H | ||
| 3 | |||
| 4 | #include <asm/kmap_types.h> | ||
| 5 | |||
| 6 | #define PKMAP_BASE (PAGE_OFFSET - PMD_SIZE) | ||
| 7 | #define LAST_PKMAP PTRS_PER_PTE | ||
| 8 | #define LAST_PKMAP_MASK (LAST_PKMAP - 1) | ||
| 9 | #define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT) | ||
| 10 | #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) | ||
| 11 | |||
| 12 | #define kmap_prot PAGE_KERNEL | ||
| 13 | |||
| 14 | #define flush_cache_kmaps() flush_cache_all() | ||
| 15 | |||
| 16 | extern pte_t *pkmap_page_table; | ||
| 17 | |||
| 18 | #define ARCH_NEEDS_KMAP_HIGH_GET | ||
| 19 | |||
| 20 | extern void *kmap_high(struct page *page); | ||
| 21 | extern void *kmap_high_get(struct page *page); | ||
| 22 | extern void kunmap_high(struct page *page); | ||
| 23 | |||
| 24 | extern void *kmap(struct page *page); | ||
| 25 | extern void kunmap(struct page *page); | ||
| 26 | extern void *kmap_atomic(struct page *page, enum km_type type); | ||
| 27 | extern void kunmap_atomic(void *kvaddr, enum km_type type); | ||
| 28 | extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); | ||
| 29 | extern struct page *kmap_atomic_to_page(const void *ptr); | ||
| 30 | |||
| 31 | #endif | ||
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h index bda489f9f017..f7bd52b1c365 100644 --- a/arch/arm/include/asm/hwcap.h +++ b/arch/arm/include/asm/hwcap.h | |||
| @@ -17,6 +17,8 @@ | |||
| 17 | #define HWCAP_CRUNCH 1024 | 17 | #define HWCAP_CRUNCH 1024 |
| 18 | #define HWCAP_THUMBEE 2048 | 18 | #define HWCAP_THUMBEE 2048 |
| 19 | #define HWCAP_NEON 4096 | 19 | #define HWCAP_NEON 4096 |
| 20 | #define HWCAP_VFPv3 8192 | ||
| 21 | #define HWCAP_VFPv3D16 16384 | ||
| 20 | 22 | ||
| 21 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | 23 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 22 | /* | 24 | /* |
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h index 45def13ee17a..d16ec97ec9a9 100644 --- a/arch/arm/include/asm/kmap_types.h +++ b/arch/arm/include/asm/kmap_types.h | |||
| @@ -18,6 +18,7 @@ enum km_type { | |||
| 18 | KM_IRQ1, | 18 | KM_IRQ1, |
| 19 | KM_SOFTIRQ0, | 19 | KM_SOFTIRQ0, |
| 20 | KM_SOFTIRQ1, | 20 | KM_SOFTIRQ1, |
| 21 | KM_L2_CACHE, | ||
| 21 | KM_TYPE_NR | 22 | KM_TYPE_NR |
| 22 | }; | 23 | }; |
| 23 | 24 | ||
diff --git a/arch/arm/include/asm/mach/dma.h b/arch/arm/include/asm/mach/dma.h index fc7278ea7146..9e614a18e680 100644 --- a/arch/arm/include/asm/mach/dma.h +++ b/arch/arm/include/asm/mach/dma.h | |||
| @@ -15,13 +15,13 @@ struct dma_struct; | |||
| 15 | typedef struct dma_struct dma_t; | 15 | typedef struct dma_struct dma_t; |
| 16 | 16 | ||
| 17 | struct dma_ops { | 17 | struct dma_ops { |
| 18 | int (*request)(dmach_t, dma_t *); /* optional */ | 18 | int (*request)(unsigned int, dma_t *); /* optional */ |
| 19 | void (*free)(dmach_t, dma_t *); /* optional */ | 19 | void (*free)(unsigned int, dma_t *); /* optional */ |
| 20 | void (*enable)(dmach_t, dma_t *); /* mandatory */ | 20 | void (*enable)(unsigned int, dma_t *); /* mandatory */ |
| 21 | void (*disable)(dmach_t, dma_t *); /* mandatory */ | 21 | void (*disable)(unsigned int, dma_t *); /* mandatory */ |
| 22 | int (*residue)(dmach_t, dma_t *); /* optional */ | 22 | int (*residue)(unsigned int, dma_t *); /* optional */ |
| 23 | int (*setspeed)(dmach_t, dma_t *, int); /* optional */ | 23 | int (*setspeed)(unsigned int, dma_t *, int); /* optional */ |
| 24 | char *type; | 24 | const char *type; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | struct dma_struct { | 27 | struct dma_struct { |
| @@ -34,24 +34,21 @@ struct dma_struct { | |||
| 34 | unsigned int active:1; /* Transfer active */ | 34 | unsigned int active:1; /* Transfer active */ |
| 35 | unsigned int invalid:1; /* Address/Count changed */ | 35 | unsigned int invalid:1; /* Address/Count changed */ |
| 36 | 36 | ||
| 37 | dmamode_t dma_mode; /* DMA mode */ | 37 | unsigned int dma_mode; /* DMA mode */ |
| 38 | int speed; /* DMA speed */ | 38 | int speed; /* DMA speed */ |
| 39 | 39 | ||
| 40 | unsigned int lock; /* Device is allocated */ | 40 | unsigned int lock; /* Device is allocated */ |
| 41 | const char *device_id; /* Device name */ | 41 | const char *device_id; /* Device name */ |
| 42 | 42 | ||
| 43 | unsigned int dma_base; /* Controller base address */ | 43 | const struct dma_ops *d_ops; |
| 44 | int dma_irq; /* Controller IRQ */ | ||
| 45 | struct scatterlist cur_sg; /* Current controller buffer */ | ||
| 46 | unsigned int state; | ||
| 47 | |||
| 48 | struct dma_ops *d_ops; | ||
| 49 | }; | 44 | }; |
| 50 | 45 | ||
| 51 | /* Prototype: void arch_dma_init(dma) | 46 | /* |
| 52 | * Purpose : Initialise architecture specific DMA | 47 | * isa_dma_add - add an ISA-style DMA channel |
| 53 | * Params : dma - pointer to array of DMA structures | ||
| 54 | */ | 48 | */ |
| 55 | extern void arch_dma_init(dma_t *dma); | 49 | extern int isa_dma_add(unsigned int, dma_t *dma); |
| 56 | 50 | ||
| 57 | extern void isa_init_dma(dma_t *dma); | 51 | /* |
| 52 | * Add the ISA DMA controller. Always takes channels 0-7. | ||
| 53 | */ | ||
| 54 | extern void isa_init_dma(void); | ||
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index 39d949b63e80..58cf91f38e6f 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h | |||
| @@ -26,6 +26,7 @@ struct map_desc { | |||
| 26 | #define MT_HIGH_VECTORS 8 | 26 | #define MT_HIGH_VECTORS 8 |
| 27 | #define MT_MEMORY 9 | 27 | #define MT_MEMORY 9 |
| 28 | #define MT_ROM 10 | 28 | #define MT_ROM 10 |
| 29 | #define MT_MEMORY_NONCACHED 11 | ||
| 29 | 30 | ||
| 30 | #ifdef CONFIG_MMU | 31 | #ifdef CONFIG_MMU |
| 31 | extern void iotable_init(struct map_desc *, int); | 32 | extern void iotable_init(struct map_desc *, int); |
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 0202a7c20e62..85763db87449 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h | |||
| @@ -44,14 +44,21 @@ | |||
| 44 | * The module space lives between the addresses given by TASK_SIZE | 44 | * The module space lives between the addresses given by TASK_SIZE |
| 45 | * and PAGE_OFFSET - it must be within 32MB of the kernel text. | 45 | * and PAGE_OFFSET - it must be within 32MB of the kernel text. |
| 46 | */ | 46 | */ |
| 47 | #define MODULES_END (PAGE_OFFSET) | 47 | #define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024) |
| 48 | #define MODULES_VADDR (MODULES_END - 16*1048576) | ||
| 49 | |||
| 50 | #if TASK_SIZE > MODULES_VADDR | 48 | #if TASK_SIZE > MODULES_VADDR |
| 51 | #error Top of user space clashes with start of module space | 49 | #error Top of user space clashes with start of module space |
| 52 | #endif | 50 | #endif |
| 53 | 51 | ||
| 54 | /* | 52 | /* |
| 53 | * The highmem pkmap virtual space shares the end of the module area. | ||
| 54 | */ | ||
| 55 | #ifdef CONFIG_HIGHMEM | ||
| 56 | #define MODULES_END (PAGE_OFFSET - PMD_SIZE) | ||
| 57 | #else | ||
| 58 | #define MODULES_END (PAGE_OFFSET) | ||
| 59 | #endif | ||
| 60 | |||
| 61 | /* | ||
| 55 | * The XIP kernel gets mapped at the bottom of the module vm area. | 62 | * The XIP kernel gets mapped at the bottom of the module vm area. |
| 56 | * Since we use sections to map it, this macro replaces the physical address | 63 | * Since we use sections to map it, this macro replaces the physical address |
| 57 | * with its virtual address while keeping offset from the base section. | 64 | * with its virtual address while keeping offset from the base section. |
| @@ -181,6 +188,7 @@ static inline void *phys_to_virt(unsigned long x) | |||
| 181 | #ifndef __virt_to_bus | 188 | #ifndef __virt_to_bus |
| 182 | #define __virt_to_bus __virt_to_phys | 189 | #define __virt_to_bus __virt_to_phys |
| 183 | #define __bus_to_virt __phys_to_virt | 190 | #define __bus_to_virt __phys_to_virt |
| 191 | #define __pfn_to_bus(x) ((x) << PAGE_SHIFT) | ||
| 184 | #endif | 192 | #endif |
| 185 | 193 | ||
| 186 | static inline __deprecated unsigned long virt_to_bus(void *x) | 194 | static inline __deprecated unsigned long virt_to_bus(void *x) |
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 24b168dc31a3..e4dfa69abb68 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h | |||
| @@ -1,15 +1,27 @@ | |||
| 1 | #ifndef _ASM_ARM_MODULE_H | 1 | #ifndef _ASM_ARM_MODULE_H |
| 2 | #define _ASM_ARM_MODULE_H | 2 | #define _ASM_ARM_MODULE_H |
| 3 | 3 | ||
| 4 | struct mod_arch_specific | ||
| 5 | { | ||
| 6 | int foo; | ||
| 7 | }; | ||
| 8 | |||
| 9 | #define Elf_Shdr Elf32_Shdr | 4 | #define Elf_Shdr Elf32_Shdr |
| 10 | #define Elf_Sym Elf32_Sym | 5 | #define Elf_Sym Elf32_Sym |
| 11 | #define Elf_Ehdr Elf32_Ehdr | 6 | #define Elf_Ehdr Elf32_Ehdr |
| 12 | 7 | ||
| 8 | struct unwind_table; | ||
| 9 | |||
| 10 | struct mod_arch_specific | ||
| 11 | { | ||
| 12 | #ifdef CONFIG_ARM_UNWIND | ||
| 13 | Elf_Shdr *unw_sec_init; | ||
| 14 | Elf_Shdr *unw_sec_devinit; | ||
| 15 | Elf_Shdr *unw_sec_core; | ||
| 16 | Elf_Shdr *sec_init_text; | ||
| 17 | Elf_Shdr *sec_devinit_text; | ||
| 18 | Elf_Shdr *sec_core_text; | ||
| 19 | struct unwind_table *unwind_init; | ||
| 20 | struct unwind_table *unwind_devinit; | ||
| 21 | struct unwind_table *unwind_core; | ||
| 22 | #endif | ||
| 23 | }; | ||
| 24 | |||
| 13 | /* | 25 | /* |
| 14 | * Include the ARM architecture version. | 26 | * Include the ARM architecture version. |
| 15 | */ | 27 | */ |
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index f341c9dbd662..e6eb8a67b807 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h | |||
| @@ -76,6 +76,14 @@ | |||
| 76 | # endif | 76 | # endif |
| 77 | #endif | 77 | #endif |
| 78 | 78 | ||
| 79 | #ifdef CONFIG_CPU_COPY_FA | ||
| 80 | # ifdef _USER | ||
| 81 | # define MULTI_USER 1 | ||
| 82 | # else | ||
| 83 | # define _USER fa | ||
| 84 | # endif | ||
| 85 | #endif | ||
| 86 | |||
| 79 | #ifdef CONFIG_CPU_SA1100 | 87 | #ifdef CONFIG_CPU_SA1100 |
| 80 | # ifdef _USER | 88 | # ifdef _USER |
| 81 | # define MULTI_USER 1 | 89 | # define MULTI_USER 1 |
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index db80203b68e0..3976412685f8 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h | |||
| @@ -89,6 +89,14 @@ | |||
| 89 | # define CPU_NAME cpu_arm922 | 89 | # define CPU_NAME cpu_arm922 |
| 90 | # endif | 90 | # endif |
| 91 | # endif | 91 | # endif |
| 92 | # ifdef CONFIG_CPU_FA526 | ||
| 93 | # ifdef CPU_NAME | ||
| 94 | # undef MULTI_CPU | ||
| 95 | # define MULTI_CPU | ||
| 96 | # else | ||
| 97 | # define CPU_NAME cpu_fa526 | ||
| 98 | # endif | ||
| 99 | # endif | ||
| 92 | # ifdef CONFIG_CPU_ARM925T | 100 | # ifdef CONFIG_CPU_ARM925T |
| 93 | # ifdef CPU_NAME | 101 | # ifdef CPU_NAME |
| 94 | # undef MULTI_CPU | 102 | # undef MULTI_CPU |
| @@ -185,6 +193,14 @@ | |||
| 185 | # define CPU_NAME cpu_xsc3 | 193 | # define CPU_NAME cpu_xsc3 |
| 186 | # endif | 194 | # endif |
| 187 | # endif | 195 | # endif |
| 196 | # ifdef CONFIG_CPU_MOHAWK | ||
| 197 | # ifdef CPU_NAME | ||
| 198 | # undef MULTI_CPU | ||
| 199 | # define MULTI_CPU | ||
| 200 | # else | ||
| 201 | # define CPU_NAME cpu_mohawk | ||
| 202 | # endif | ||
| 203 | # endif | ||
| 188 | # ifdef CONFIG_CPU_FEROCEON | 204 | # ifdef CONFIG_CPU_FEROCEON |
| 189 | # ifdef CPU_NAME | 205 | # ifdef CPU_NAME |
| 190 | # undef MULTI_CPU | 206 | # undef MULTI_CPU |
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 73192618f1c2..236a06b9b7ce 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | /* PTRACE_SYSCALL is 24 */ | 27 | /* PTRACE_SYSCALL is 24 */ |
| 28 | #define PTRACE_GETCRUNCHREGS 25 | 28 | #define PTRACE_GETCRUNCHREGS 25 |
| 29 | #define PTRACE_SETCRUNCHREGS 26 | 29 | #define PTRACE_SETCRUNCHREGS 26 |
| 30 | #define PTRACE_GETVFPREGS 27 | ||
| 31 | #define PTRACE_SETVFPREGS 28 | ||
| 30 | 32 | ||
| 31 | /* | 33 | /* |
| 32 | * PSR bits | 34 | * PSR bits |
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index 503843db1565..c10d1aa4b487 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | #define SZ_8M 0x00800000 | 43 | #define SZ_8M 0x00800000 |
| 44 | #define SZ_16M 0x01000000 | 44 | #define SZ_16M 0x01000000 |
| 45 | #define SZ_32M 0x02000000 | 45 | #define SZ_32M 0x02000000 |
| 46 | #define SZ_48M 0x03000000 | ||
| 46 | #define SZ_64M 0x04000000 | 47 | #define SZ_64M 0x04000000 |
| 47 | #define SZ_128M 0x08000000 | 48 | #define SZ_128M 0x08000000 |
| 48 | #define SZ_256M 0x10000000 | 49 | #define SZ_256M 0x10000000 |
diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h new file mode 100644 index 000000000000..4d0a16441b29 --- /dev/null +++ b/arch/arm/include/asm/stacktrace.h | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | #ifndef __ASM_STACKTRACE_H | ||
| 2 | #define __ASM_STACKTRACE_H | ||
| 3 | |||
| 4 | struct stackframe { | ||
| 5 | unsigned long fp; | ||
| 6 | unsigned long sp; | ||
| 7 | unsigned long lr; | ||
| 8 | unsigned long pc; | ||
| 9 | }; | ||
| 10 | |||
| 11 | extern int unwind_frame(struct stackframe *frame); | ||
| 12 | extern void walk_stackframe(struct stackframe *frame, | ||
| 13 | int (*fn)(struct stackframe *, void *), void *data); | ||
| 14 | |||
| 15 | #endif /* __ASM_STACKTRACE_H */ | ||
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 811be55f338e..bd4dc8ed53d5 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h | |||
| @@ -97,8 +97,8 @@ extern void __show_regs(struct pt_regs *); | |||
| 97 | extern int cpu_architecture(void); | 97 | extern int cpu_architecture(void); |
| 98 | extern void cpu_init(void); | 98 | extern void cpu_init(void); |
| 99 | 99 | ||
| 100 | void arm_machine_restart(char mode); | 100 | void arm_machine_restart(char mode, const char *cmd); |
| 101 | extern void (*arm_pm_restart)(char str); | 101 | extern void (*arm_pm_restart)(char str, const char *cmd); |
| 102 | 102 | ||
| 103 | #define UDBG_UNDEFINED (1 << 0) | 103 | #define UDBG_UNDEFINED (1 << 0) |
| 104 | #define UDBG_SYSCALL (1 << 1) | 104 | #define UDBG_SYSCALL (1 << 1) |
| @@ -125,6 +125,12 @@ extern unsigned int user_debug; | |||
| 125 | : : "r" (0) : "memory") | 125 | : : "r" (0) : "memory") |
| 126 | #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ | 126 | #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ |
| 127 | : : "r" (0) : "memory") | 127 | : : "r" (0) : "memory") |
| 128 | #elif defined(CONFIG_CPU_FA526) | ||
| 129 | #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ | ||
| 130 | : : "r" (0) : "memory") | ||
| 131 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | ||
| 132 | : : "r" (0) : "memory") | ||
| 133 | #define dmb() __asm__ __volatile__ ("" : : : "memory") | ||
| 128 | #else | 134 | #else |
| 129 | #define isb() __asm__ __volatile__ ("" : : : "memory") | 135 | #define isb() __asm__ __volatile__ ("" : : : "memory") |
| 130 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | 136 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ |
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 68b9ec82a37f..4f8848260ee2 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h | |||
| @@ -99,6 +99,8 @@ static inline struct thread_info *current_thread_info(void) | |||
| 99 | 99 | ||
| 100 | #define thread_saved_pc(tsk) \ | 100 | #define thread_saved_pc(tsk) \ |
| 101 | ((unsigned long)(task_thread_info(tsk)->cpu_context.pc)) | 101 | ((unsigned long)(task_thread_info(tsk)->cpu_context.pc)) |
| 102 | #define thread_saved_sp(tsk) \ | ||
| 103 | ((unsigned long)(task_thread_info(tsk)->cpu_context.sp)) | ||
| 102 | #define thread_saved_fp(tsk) \ | 104 | #define thread_saved_fp(tsk) \ |
| 103 | ((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) | 105 | ((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) |
| 104 | 106 | ||
| @@ -113,6 +115,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *); | |||
| 113 | extern void iwmmxt_task_release(struct thread_info *); | 115 | extern void iwmmxt_task_release(struct thread_info *); |
| 114 | extern void iwmmxt_task_switch(struct thread_info *); | 116 | extern void iwmmxt_task_switch(struct thread_info *); |
| 115 | 117 | ||
| 118 | extern void vfp_sync_state(struct thread_info *thread); | ||
| 119 | |||
| 116 | #endif | 120 | #endif |
| 117 | 121 | ||
| 118 | /* | 122 | /* |
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index b543a054a17e..a62218013c78 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | #define TLB_V6_D_ASID (1 << 17) | 39 | #define TLB_V6_D_ASID (1 << 17) |
| 40 | #define TLB_V6_I_ASID (1 << 18) | 40 | #define TLB_V6_I_ASID (1 << 18) |
| 41 | 41 | ||
| 42 | #define TLB_BTB (1 << 28) | ||
| 42 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ | 43 | #define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ |
| 43 | #define TLB_DCLEAN (1 << 30) | 44 | #define TLB_DCLEAN (1 << 30) |
| 44 | #define TLB_WB (1 << 31) | 45 | #define TLB_WB (1 << 31) |
| @@ -53,6 +54,7 @@ | |||
| 53 | * v4wb - ARMv4 with write buffer without I TLB flush entry instruction | 54 | * v4wb - ARMv4 with write buffer without I TLB flush entry instruction |
| 54 | * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction | 55 | * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction |
| 55 | * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) | 56 | * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) |
| 57 | * fa - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB)) | ||
| 56 | * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction | 58 | * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction |
| 57 | * v7wbi - identical to v6wbi | 59 | * v7wbi - identical to v6wbi |
| 58 | */ | 60 | */ |
| @@ -89,6 +91,22 @@ | |||
| 89 | # define v4_always_flags (-1UL) | 91 | # define v4_always_flags (-1UL) |
| 90 | #endif | 92 | #endif |
| 91 | 93 | ||
| 94 | #define fa_tlb_flags (TLB_WB | TLB_BTB | TLB_DCLEAN | \ | ||
| 95 | TLB_V4_U_FULL | TLB_V4_U_PAGE) | ||
| 96 | |||
| 97 | #ifdef CONFIG_CPU_TLB_FA | ||
| 98 | # define fa_possible_flags fa_tlb_flags | ||
| 99 | # define fa_always_flags fa_tlb_flags | ||
| 100 | # ifdef _TLB | ||
| 101 | # define MULTI_TLB 1 | ||
| 102 | # else | ||
| 103 | # define _TLB fa | ||
| 104 | # endif | ||
| 105 | #else | ||
| 106 | # define fa_possible_flags 0 | ||
| 107 | # define fa_always_flags (-1UL) | ||
| 108 | #endif | ||
| 109 | |||
| 92 | #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ | 110 | #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ |
| 93 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ | 111 | TLB_V4_I_FULL | TLB_V4_D_FULL | \ |
| 94 | TLB_V4_I_PAGE | TLB_V4_D_PAGE) | 112 | TLB_V4_I_PAGE | TLB_V4_D_PAGE) |
| @@ -140,7 +158,7 @@ | |||
| 140 | # define v4wb_always_flags (-1UL) | 158 | # define v4wb_always_flags (-1UL) |
| 141 | #endif | 159 | #endif |
| 142 | 160 | ||
| 143 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \ | 161 | #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ |
| 144 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ | 162 | TLB_V6_I_FULL | TLB_V6_D_FULL | \ |
| 145 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ | 163 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | \ |
| 146 | TLB_V6_I_ASID | TLB_V6_D_ASID) | 164 | TLB_V6_I_ASID | TLB_V6_D_ASID) |
| @@ -267,6 +285,7 @@ extern struct cpu_tlb_fns cpu_tlb; | |||
| 267 | v4wbi_possible_flags | \ | 285 | v4wbi_possible_flags | \ |
| 268 | fr_possible_flags | \ | 286 | fr_possible_flags | \ |
| 269 | v4wb_possible_flags | \ | 287 | v4wb_possible_flags | \ |
| 288 | fa_possible_flags | \ | ||
| 270 | v6wbi_possible_flags | \ | 289 | v6wbi_possible_flags | \ |
| 271 | v7wbi_possible_flags) | 290 | v7wbi_possible_flags) |
| 272 | 291 | ||
| @@ -275,6 +294,7 @@ extern struct cpu_tlb_fns cpu_tlb; | |||
| 275 | v4wbi_always_flags & \ | 294 | v4wbi_always_flags & \ |
| 276 | fr_always_flags & \ | 295 | fr_always_flags & \ |
| 277 | v4wb_always_flags & \ | 296 | v4wb_always_flags & \ |
| 297 | fa_always_flags & \ | ||
| 278 | v6wbi_always_flags & \ | 298 | v6wbi_always_flags & \ |
| 279 | v7wbi_always_flags) | 299 | v7wbi_always_flags) |
| 280 | 300 | ||
| @@ -297,9 +317,7 @@ static inline void local_flush_tlb_all(void) | |||
| 297 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) | 317 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) |
| 298 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | 318 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
| 299 | 319 | ||
| 300 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 320 | if (tlb_flag(TLB_BTB)) { |
| 301 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
| 302 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
| 303 | /* flush the branch target cache */ | 321 | /* flush the branch target cache */ |
| 304 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 322 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
| 305 | dsb(); | 323 | dsb(); |
| @@ -334,9 +352,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) | |||
| 334 | if (tlb_flag(TLB_V6_I_ASID)) | 352 | if (tlb_flag(TLB_V6_I_ASID)) |
| 335 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); | 353 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); |
| 336 | 354 | ||
| 337 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 355 | if (tlb_flag(TLB_BTB)) { |
| 338 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
| 339 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
| 340 | /* flush the branch target cache */ | 356 | /* flush the branch target cache */ |
| 341 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 357 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
| 342 | dsb(); | 358 | dsb(); |
| @@ -374,9 +390,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |||
| 374 | if (tlb_flag(TLB_V6_I_PAGE)) | 390 | if (tlb_flag(TLB_V6_I_PAGE)) |
| 375 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); | 391 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); |
| 376 | 392 | ||
| 377 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 393 | if (tlb_flag(TLB_BTB)) { |
| 378 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
| 379 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
| 380 | /* flush the branch target cache */ | 394 | /* flush the branch target cache */ |
| 381 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 395 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
| 382 | dsb(); | 396 | dsb(); |
| @@ -411,9 +425,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
| 411 | if (tlb_flag(TLB_V6_I_PAGE)) | 425 | if (tlb_flag(TLB_V6_I_PAGE)) |
| 412 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); | 426 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); |
| 413 | 427 | ||
| 414 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | 428 | if (tlb_flag(TLB_BTB)) { |
| 415 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
| 416 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
| 417 | /* flush the branch target cache */ | 429 | /* flush the branch target cache */ |
| 418 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | 430 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
| 419 | dsb(); | 431 | dsb(); |
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h index aa399aec568e..491960bf4260 100644 --- a/arch/arm/include/asm/traps.h +++ b/arch/arm/include/asm/traps.h | |||
| @@ -25,5 +25,6 @@ static inline int in_exception_text(unsigned long ptr) | |||
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | extern void __init early_trap_init(void); | 27 | extern void __init early_trap_init(void); |
| 28 | extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame); | ||
| 28 | 29 | ||
| 29 | #endif | 30 | #endif |
diff --git a/arch/arm/include/asm/unwind.h b/arch/arm/include/asm/unwind.h new file mode 100644 index 000000000000..a5edf421005c --- /dev/null +++ b/arch/arm/include/asm/unwind.h | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/include/asm/unwind.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_UNWIND_H | ||
| 21 | #define __ASM_UNWIND_H | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | |||
| 25 | /* Unwind reason code according the the ARM EABI documents */ | ||
| 26 | enum unwind_reason_code { | ||
| 27 | URC_OK = 0, /* operation completed successfully */ | ||
| 28 | URC_CONTINUE_UNWIND = 8, | ||
| 29 | URC_FAILURE = 9 /* unspecified failure of some kind */ | ||
| 30 | }; | ||
| 31 | |||
| 32 | struct unwind_idx { | ||
| 33 | unsigned long addr; | ||
| 34 | unsigned long insn; | ||
| 35 | }; | ||
| 36 | |||
| 37 | struct unwind_table { | ||
| 38 | struct list_head list; | ||
| 39 | struct unwind_idx *start; | ||
| 40 | struct unwind_idx *stop; | ||
| 41 | unsigned long begin_addr; | ||
| 42 | unsigned long end_addr; | ||
| 43 | }; | ||
| 44 | |||
| 45 | extern struct unwind_table *unwind_table_add(unsigned long start, | ||
| 46 | unsigned long size, | ||
| 47 | unsigned long text_addr, | ||
| 48 | unsigned long text_size); | ||
| 49 | extern void unwind_table_del(struct unwind_table *tab); | ||
| 50 | extern void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk); | ||
| 51 | |||
| 52 | #ifdef CONFIG_ARM_UNWIND | ||
| 53 | extern int __init unwind_init(void); | ||
| 54 | #else | ||
| 55 | static inline int __init unwind_init(void) | ||
| 56 | { | ||
| 57 | return 0; | ||
| 58 | } | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #endif /* !__ASSEMBLY__ */ | ||
| 62 | |||
| 63 | #ifdef CONFIG_ARM_UNWIND | ||
| 64 | #define UNWIND(code...) code | ||
| 65 | #else | ||
| 66 | #define UNWIND(code...) | ||
| 67 | #endif | ||
| 68 | |||
| 69 | #endif /* __ASM_UNWIND_H */ | ||
diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h index 825c1e7c582d..df95e050f9dd 100644 --- a/arch/arm/include/asm/user.h +++ b/arch/arm/include/asm/user.h | |||
| @@ -81,4 +81,13 @@ struct user{ | |||
| 81 | #define HOST_TEXT_START_ADDR (u.start_code) | 81 | #define HOST_TEXT_START_ADDR (u.start_code) |
| 82 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | 82 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) |
| 83 | 83 | ||
| 84 | /* | ||
| 85 | * User specific VFP registers. If only VFPv2 is present, registers 16 to 31 | ||
| 86 | * are ignored by the ptrace system call. | ||
| 87 | */ | ||
| 88 | struct user_vfp { | ||
| 89 | unsigned long long fpregs[32]; | ||
| 90 | unsigned long fpscr; | ||
| 91 | }; | ||
| 92 | |||
| 84 | #endif /* _ARM_USER_H */ | 93 | #endif /* _ARM_USER_H */ |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 4305345987d3..11a5197a221f 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
| @@ -29,12 +29,14 @@ obj-$(CONFIG_ATAGS_PROC) += atags.o | |||
| 29 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o | 29 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o |
| 30 | obj-$(CONFIG_ARM_THUMBEE) += thumbee.o | 30 | obj-$(CONFIG_ARM_THUMBEE) += thumbee.o |
| 31 | obj-$(CONFIG_KGDB) += kgdb.o | 31 | obj-$(CONFIG_KGDB) += kgdb.o |
| 32 | obj-$(CONFIG_ARM_UNWIND) += unwind.o | ||
| 32 | 33 | ||
| 33 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o | 34 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o |
| 34 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 | 35 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 |
| 35 | 36 | ||
| 36 | obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o | 37 | obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o |
| 37 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o | 38 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o |
| 39 | obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o | ||
| 38 | obj-$(CONFIG_IWMMXT) += iwmmxt.o | 40 | obj-$(CONFIG_IWMMXT) += iwmmxt.o |
| 39 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt | 41 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt |
| 40 | 42 | ||
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index f53c58290543..b121b6053cce 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S | |||
| @@ -49,6 +49,33 @@ | |||
| 49 | 1002: | 49 | 1002: |
| 50 | .endm | 50 | .endm |
| 51 | 51 | ||
| 52 | #elif defined(CONFIG_CPU_XSCALE) | ||
| 53 | |||
| 54 | .macro addruart, rx | ||
| 55 | .endm | ||
| 56 | |||
| 57 | .macro senduart, rd, rx | ||
| 58 | mcr p14, 0, \rd, c8, c0, 0 | ||
| 59 | .endm | ||
| 60 | |||
| 61 | .macro busyuart, rd, rx | ||
| 62 | 1001: | ||
| 63 | mrc p14, 0, \rx, c14, c0, 0 | ||
| 64 | tst \rx, #0x10000000 | ||
| 65 | beq 1001b | ||
| 66 | .endm | ||
| 67 | |||
| 68 | .macro waituart, rd, rx | ||
| 69 | mov \rd, #0x10000000 | ||
| 70 | 1001: | ||
| 71 | subs \rd, \rd, #1 | ||
| 72 | bmi 1002f | ||
| 73 | mrc p14, 0, \rx, c14, c0, 0 | ||
| 74 | tst \rx, #0x10000000 | ||
| 75 | bne 1001b | ||
| 76 | 1002: | ||
| 77 | .endm | ||
| 78 | |||
| 52 | #else | 79 | #else |
| 53 | 80 | ||
| 54 | .macro addruart, rx | 81 | .macro addruart, rx |
diff --git a/arch/arm/kernel/dma-isa.c b/arch/arm/kernel/dma-isa.c index 4a3a50495c60..0e88e46fc732 100644 --- a/arch/arm/kernel/dma-isa.c +++ b/arch/arm/kernel/dma-isa.c | |||
| @@ -24,11 +24,6 @@ | |||
| 24 | #include <asm/dma.h> | 24 | #include <asm/dma.h> |
| 25 | #include <asm/mach/dma.h> | 25 | #include <asm/mach/dma.h> |
| 26 | 26 | ||
| 27 | #define ISA_DMA_MODE_READ 0x44 | ||
| 28 | #define ISA_DMA_MODE_WRITE 0x48 | ||
| 29 | #define ISA_DMA_MODE_CASCADE 0xc0 | ||
| 30 | #define ISA_DMA_AUTOINIT 0x10 | ||
| 31 | |||
| 32 | #define ISA_DMA_MASK 0 | 27 | #define ISA_DMA_MASK 0 |
| 33 | #define ISA_DMA_MODE 1 | 28 | #define ISA_DMA_MODE 1 |
| 34 | #define ISA_DMA_CLRFF 2 | 29 | #define ISA_DMA_CLRFF 2 |
| @@ -49,38 +44,35 @@ static unsigned int isa_dma_port[8][7] = { | |||
| 49 | { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce } | 44 | { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce } |
| 50 | }; | 45 | }; |
| 51 | 46 | ||
| 52 | static int isa_get_dma_residue(dmach_t channel, dma_t *dma) | 47 | static int isa_get_dma_residue(unsigned int chan, dma_t *dma) |
| 53 | { | 48 | { |
| 54 | unsigned int io_port = isa_dma_port[channel][ISA_DMA_COUNT]; | 49 | unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT]; |
| 55 | int count; | 50 | int count; |
| 56 | 51 | ||
| 57 | count = 1 + inb(io_port); | 52 | count = 1 + inb(io_port); |
| 58 | count |= inb(io_port) << 8; | 53 | count |= inb(io_port) << 8; |
| 59 | 54 | ||
| 60 | return channel < 4 ? count : (count << 1); | 55 | return chan < 4 ? count : (count << 1); |
| 61 | } | 56 | } |
| 62 | 57 | ||
| 63 | static void isa_enable_dma(dmach_t channel, dma_t *dma) | 58 | static void isa_enable_dma(unsigned int chan, dma_t *dma) |
| 64 | { | 59 | { |
| 65 | if (dma->invalid) { | 60 | if (dma->invalid) { |
| 66 | unsigned long address, length; | 61 | unsigned long address, length; |
| 67 | unsigned int mode; | 62 | unsigned int mode; |
| 68 | enum dma_data_direction direction; | 63 | enum dma_data_direction direction; |
| 69 | 64 | ||
| 70 | mode = channel & 3; | 65 | mode = (chan & 3) | dma->dma_mode; |
| 71 | switch (dma->dma_mode & DMA_MODE_MASK) { | 66 | switch (dma->dma_mode & DMA_MODE_MASK) { |
| 72 | case DMA_MODE_READ: | 67 | case DMA_MODE_READ: |
| 73 | mode |= ISA_DMA_MODE_READ; | ||
| 74 | direction = DMA_FROM_DEVICE; | 68 | direction = DMA_FROM_DEVICE; |
| 75 | break; | 69 | break; |
| 76 | 70 | ||
| 77 | case DMA_MODE_WRITE: | 71 | case DMA_MODE_WRITE: |
| 78 | mode |= ISA_DMA_MODE_WRITE; | ||
| 79 | direction = DMA_TO_DEVICE; | 72 | direction = DMA_TO_DEVICE; |
| 80 | break; | 73 | break; |
| 81 | 74 | ||
| 82 | case DMA_MODE_CASCADE: | 75 | case DMA_MODE_CASCADE: |
| 83 | mode |= ISA_DMA_MODE_CASCADE; | ||
| 84 | direction = DMA_BIDIRECTIONAL; | 76 | direction = DMA_BIDIRECTIONAL; |
| 85 | break; | 77 | break; |
| 86 | 78 | ||
| @@ -105,34 +97,31 @@ static void isa_enable_dma(dmach_t channel, dma_t *dma) | |||
| 105 | address = dma->buf.dma_address; | 97 | address = dma->buf.dma_address; |
| 106 | length = dma->buf.length - 1; | 98 | length = dma->buf.length - 1; |
| 107 | 99 | ||
| 108 | outb(address >> 16, isa_dma_port[channel][ISA_DMA_PGLO]); | 100 | outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]); |
| 109 | outb(address >> 24, isa_dma_port[channel][ISA_DMA_PGHI]); | 101 | outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]); |
| 110 | 102 | ||
| 111 | if (channel >= 4) { | 103 | if (chan >= 4) { |
| 112 | address >>= 1; | 104 | address >>= 1; |
| 113 | length >>= 1; | 105 | length >>= 1; |
| 114 | } | 106 | } |
| 115 | 107 | ||
| 116 | outb(0, isa_dma_port[channel][ISA_DMA_CLRFF]); | 108 | outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]); |
| 117 | |||
| 118 | outb(address, isa_dma_port[channel][ISA_DMA_ADDR]); | ||
| 119 | outb(address >> 8, isa_dma_port[channel][ISA_DMA_ADDR]); | ||
| 120 | 109 | ||
| 121 | outb(length, isa_dma_port[channel][ISA_DMA_COUNT]); | 110 | outb(address, isa_dma_port[chan][ISA_DMA_ADDR]); |
| 122 | outb(length >> 8, isa_dma_port[channel][ISA_DMA_COUNT]); | 111 | outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]); |
| 123 | 112 | ||
| 124 | if (dma->dma_mode & DMA_AUTOINIT) | 113 | outb(length, isa_dma_port[chan][ISA_DMA_COUNT]); |
| 125 | mode |= ISA_DMA_AUTOINIT; | 114 | outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]); |
| 126 | 115 | ||
| 127 | outb(mode, isa_dma_port[channel][ISA_DMA_MODE]); | 116 | outb(mode, isa_dma_port[chan][ISA_DMA_MODE]); |
| 128 | dma->invalid = 0; | 117 | dma->invalid = 0; |
| 129 | } | 118 | } |
| 130 | outb(channel & 3, isa_dma_port[channel][ISA_DMA_MASK]); | 119 | outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]); |
| 131 | } | 120 | } |
| 132 | 121 | ||
| 133 | static void isa_disable_dma(dmach_t channel, dma_t *dma) | 122 | static void isa_disable_dma(unsigned int chan, dma_t *dma) |
| 134 | { | 123 | { |
| 135 | outb(channel | 4, isa_dma_port[channel][ISA_DMA_MASK]); | 124 | outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]); |
| 136 | } | 125 | } |
| 137 | 126 | ||
| 138 | static struct dma_ops isa_dma_ops = { | 127 | static struct dma_ops isa_dma_ops = { |
| @@ -160,7 +149,12 @@ static struct resource dma_resources[] = { { | |||
| 160 | .end = 0x048f | 149 | .end = 0x048f |
| 161 | } }; | 150 | } }; |
| 162 | 151 | ||
| 163 | void __init isa_init_dma(dma_t *dma) | 152 | static dma_t isa_dma[8]; |
| 153 | |||
| 154 | /* | ||
| 155 | * ISA DMA always starts at channel 0 | ||
| 156 | */ | ||
| 157 | void __init isa_init_dma(void) | ||
| 164 | { | 158 | { |
| 165 | /* | 159 | /* |
| 166 | * Try to autodetect presence of an ISA DMA controller. | 160 | * Try to autodetect presence of an ISA DMA controller. |
| @@ -178,11 +172,11 @@ void __init isa_init_dma(dma_t *dma) | |||
| 178 | outb(0xaa, 0x00); | 172 | outb(0xaa, 0x00); |
| 179 | 173 | ||
| 180 | if (inb(0) == 0x55 && inb(0) == 0xaa) { | 174 | if (inb(0) == 0x55 && inb(0) == 0xaa) { |
| 181 | int channel, i; | 175 | unsigned int chan, i; |
| 182 | 176 | ||
| 183 | for (channel = 0; channel < 8; channel++) { | 177 | for (chan = 0; chan < 8; chan++) { |
| 184 | dma[channel].d_ops = &isa_dma_ops; | 178 | isa_dma[chan].d_ops = &isa_dma_ops; |
| 185 | isa_disable_dma(channel, NULL); | 179 | isa_disable_dma(chan, NULL); |
| 186 | } | 180 | } |
| 187 | 181 | ||
| 188 | outb(0x40, 0x0b); | 182 | outb(0x40, 0x0b); |
| @@ -217,5 +211,12 @@ void __init isa_init_dma(dma_t *dma) | |||
| 217 | 211 | ||
| 218 | for (i = 0; i < ARRAY_SIZE(dma_resources); i++) | 212 | for (i = 0; i < ARRAY_SIZE(dma_resources); i++) |
| 219 | request_resource(&ioport_resource, dma_resources + i); | 213 | request_resource(&ioport_resource, dma_resources + i); |
| 214 | |||
| 215 | for (chan = 0; chan < 8; chan++) { | ||
| 216 | int ret = isa_dma_add(chan, &isa_dma[chan]); | ||
| 217 | if (ret) | ||
| 218 | printk(KERN_ERR "ISADMA%u: unable to register: %d\n", | ||
| 219 | chan, ret); | ||
| 220 | } | ||
| 220 | } | 221 | } |
| 221 | } | 222 | } |
diff --git a/arch/arm/kernel/dma.c b/arch/arm/kernel/dma.c index d006085ed7e7..7d5b9fb01e71 100644 --- a/arch/arm/kernel/dma.c +++ b/arch/arm/kernel/dma.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/spinlock.h> | 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/errno.h> | 17 | #include <linux/errno.h> |
| 18 | #include <linux/scatterlist.h> | ||
| 18 | 19 | ||
| 19 | #include <asm/dma.h> | 20 | #include <asm/dma.h> |
| 20 | 21 | ||
| @@ -23,19 +24,40 @@ | |||
| 23 | DEFINE_SPINLOCK(dma_spin_lock); | 24 | DEFINE_SPINLOCK(dma_spin_lock); |
| 24 | EXPORT_SYMBOL(dma_spin_lock); | 25 | EXPORT_SYMBOL(dma_spin_lock); |
| 25 | 26 | ||
| 26 | static dma_t dma_chan[MAX_DMA_CHANNELS]; | 27 | static dma_t *dma_chan[MAX_DMA_CHANNELS]; |
| 28 | |||
| 29 | static inline dma_t *dma_channel(unsigned int chan) | ||
| 30 | { | ||
| 31 | if (chan >= MAX_DMA_CHANNELS) | ||
| 32 | return NULL; | ||
| 33 | |||
| 34 | return dma_chan[chan]; | ||
| 35 | } | ||
| 36 | |||
| 37 | int __init isa_dma_add(unsigned int chan, dma_t *dma) | ||
| 38 | { | ||
| 39 | if (!dma->d_ops) | ||
| 40 | return -EINVAL; | ||
| 41 | |||
| 42 | sg_init_table(&dma->buf, 1); | ||
| 43 | |||
| 44 | if (dma_chan[chan]) | ||
| 45 | return -EBUSY; | ||
| 46 | dma_chan[chan] = dma; | ||
| 47 | return 0; | ||
| 48 | } | ||
| 27 | 49 | ||
| 28 | /* | 50 | /* |
| 29 | * Request DMA channel | 51 | * Request DMA channel |
| 30 | * | 52 | * |
| 31 | * On certain platforms, we have to allocate an interrupt as well... | 53 | * On certain platforms, we have to allocate an interrupt as well... |
| 32 | */ | 54 | */ |
| 33 | int request_dma(dmach_t channel, const char *device_id) | 55 | int request_dma(unsigned int chan, const char *device_id) |
| 34 | { | 56 | { |
| 35 | dma_t *dma = dma_chan + channel; | 57 | dma_t *dma = dma_channel(chan); |
| 36 | int ret; | 58 | int ret; |
| 37 | 59 | ||
| 38 | if (channel >= MAX_DMA_CHANNELS || !dma->d_ops) | 60 | if (!dma) |
| 39 | goto bad_dma; | 61 | goto bad_dma; |
| 40 | 62 | ||
| 41 | if (xchg(&dma->lock, 1) != 0) | 63 | if (xchg(&dma->lock, 1) != 0) |
| @@ -47,7 +69,7 @@ int request_dma(dmach_t channel, const char *device_id) | |||
| 47 | 69 | ||
| 48 | ret = 0; | 70 | ret = 0; |
| 49 | if (dma->d_ops->request) | 71 | if (dma->d_ops->request) |
| 50 | ret = dma->d_ops->request(channel, dma); | 72 | ret = dma->d_ops->request(chan, dma); |
| 51 | 73 | ||
| 52 | if (ret) | 74 | if (ret) |
| 53 | xchg(&dma->lock, 0); | 75 | xchg(&dma->lock, 0); |
| @@ -55,7 +77,7 @@ int request_dma(dmach_t channel, const char *device_id) | |||
| 55 | return ret; | 77 | return ret; |
| 56 | 78 | ||
| 57 | bad_dma: | 79 | bad_dma: |
| 58 | printk(KERN_ERR "dma: trying to allocate DMA%d\n", channel); | 80 | printk(KERN_ERR "dma: trying to allocate DMA%d\n", chan); |
| 59 | return -EINVAL; | 81 | return -EINVAL; |
| 60 | 82 | ||
| 61 | busy: | 83 | busy: |
| @@ -68,42 +90,42 @@ EXPORT_SYMBOL(request_dma); | |||
| 68 | * | 90 | * |
| 69 | * On certain platforms, we have to free interrupt as well... | 91 | * On certain platforms, we have to free interrupt as well... |
| 70 | */ | 92 | */ |
| 71 | void free_dma(dmach_t channel) | 93 | void free_dma(unsigned int chan) |
| 72 | { | 94 | { |
| 73 | dma_t *dma = dma_chan + channel; | 95 | dma_t *dma = dma_channel(chan); |
| 74 | 96 | ||
| 75 | if (channel >= MAX_DMA_CHANNELS || !dma->d_ops) | 97 | if (!dma) |
| 76 | goto bad_dma; | 98 | goto bad_dma; |
| 77 | 99 | ||
| 78 | if (dma->active) { | 100 | if (dma->active) { |
| 79 | printk(KERN_ERR "dma%d: freeing active DMA\n", channel); | 101 | printk(KERN_ERR "dma%d: freeing active DMA\n", chan); |
| 80 | dma->d_ops->disable(channel, dma); | 102 | dma->d_ops->disable(chan, dma); |
| 81 | dma->active = 0; | 103 | dma->active = 0; |
| 82 | } | 104 | } |
| 83 | 105 | ||
| 84 | if (xchg(&dma->lock, 0) != 0) { | 106 | if (xchg(&dma->lock, 0) != 0) { |
| 85 | if (dma->d_ops->free) | 107 | if (dma->d_ops->free) |
| 86 | dma->d_ops->free(channel, dma); | 108 | dma->d_ops->free(chan, dma); |
| 87 | return; | 109 | return; |
| 88 | } | 110 | } |
| 89 | 111 | ||
| 90 | printk(KERN_ERR "dma%d: trying to free free DMA\n", channel); | 112 | printk(KERN_ERR "dma%d: trying to free free DMA\n", chan); |
| 91 | return; | 113 | return; |
| 92 | 114 | ||
| 93 | bad_dma: | 115 | bad_dma: |
| 94 | printk(KERN_ERR "dma: trying to free DMA%d\n", channel); | 116 | printk(KERN_ERR "dma: trying to free DMA%d\n", chan); |
| 95 | } | 117 | } |
| 96 | EXPORT_SYMBOL(free_dma); | 118 | EXPORT_SYMBOL(free_dma); |
| 97 | 119 | ||
| 98 | /* Set DMA Scatter-Gather list | 120 | /* Set DMA Scatter-Gather list |
| 99 | */ | 121 | */ |
| 100 | void set_dma_sg (dmach_t channel, struct scatterlist *sg, int nr_sg) | 122 | void set_dma_sg (unsigned int chan, struct scatterlist *sg, int nr_sg) |
| 101 | { | 123 | { |
| 102 | dma_t *dma = dma_chan + channel; | 124 | dma_t *dma = dma_channel(chan); |
| 103 | 125 | ||
| 104 | if (dma->active) | 126 | if (dma->active) |
| 105 | printk(KERN_ERR "dma%d: altering DMA SG while " | 127 | printk(KERN_ERR "dma%d: altering DMA SG while " |
| 106 | "DMA active\n", channel); | 128 | "DMA active\n", chan); |
| 107 | 129 | ||
| 108 | dma->sg = sg; | 130 | dma->sg = sg; |
| 109 | dma->sgcount = nr_sg; | 131 | dma->sgcount = nr_sg; |
| @@ -115,13 +137,13 @@ EXPORT_SYMBOL(set_dma_sg); | |||
| 115 | * | 137 | * |
| 116 | * Copy address to the structure, and set the invalid bit | 138 | * Copy address to the structure, and set the invalid bit |
| 117 | */ | 139 | */ |
| 118 | void __set_dma_addr (dmach_t channel, void *addr) | 140 | void __set_dma_addr (unsigned int chan, void *addr) |
| 119 | { | 141 | { |
| 120 | dma_t *dma = dma_chan + channel; | 142 | dma_t *dma = dma_channel(chan); |
| 121 | 143 | ||
| 122 | if (dma->active) | 144 | if (dma->active) |
| 123 | printk(KERN_ERR "dma%d: altering DMA address while " | 145 | printk(KERN_ERR "dma%d: altering DMA address while " |
| 124 | "DMA active\n", channel); | 146 | "DMA active\n", chan); |
| 125 | 147 | ||
| 126 | dma->sg = NULL; | 148 | dma->sg = NULL; |
| 127 | dma->addr = addr; | 149 | dma->addr = addr; |
| @@ -133,13 +155,13 @@ EXPORT_SYMBOL(__set_dma_addr); | |||
| 133 | * | 155 | * |
| 134 | * Copy address to the structure, and set the invalid bit | 156 | * Copy address to the structure, and set the invalid bit |
| 135 | */ | 157 | */ |
| 136 | void set_dma_count (dmach_t channel, unsigned long count) | 158 | void set_dma_count (unsigned int chan, unsigned long count) |
| 137 | { | 159 | { |
| 138 | dma_t *dma = dma_chan + channel; | 160 | dma_t *dma = dma_channel(chan); |
| 139 | 161 | ||
| 140 | if (dma->active) | 162 | if (dma->active) |
| 141 | printk(KERN_ERR "dma%d: altering DMA count while " | 163 | printk(KERN_ERR "dma%d: altering DMA count while " |
| 142 | "DMA active\n", channel); | 164 | "DMA active\n", chan); |
| 143 | 165 | ||
| 144 | dma->sg = NULL; | 166 | dma->sg = NULL; |
| 145 | dma->count = count; | 167 | dma->count = count; |
| @@ -149,13 +171,13 @@ EXPORT_SYMBOL(set_dma_count); | |||
| 149 | 171 | ||
| 150 | /* Set DMA direction mode | 172 | /* Set DMA direction mode |
| 151 | */ | 173 | */ |
| 152 | void set_dma_mode (dmach_t channel, dmamode_t mode) | 174 | void set_dma_mode (unsigned int chan, unsigned int mode) |
| 153 | { | 175 | { |
| 154 | dma_t *dma = dma_chan + channel; | 176 | dma_t *dma = dma_channel(chan); |
| 155 | 177 | ||
| 156 | if (dma->active) | 178 | if (dma->active) |
| 157 | printk(KERN_ERR "dma%d: altering DMA mode while " | 179 | printk(KERN_ERR "dma%d: altering DMA mode while " |
| 158 | "DMA active\n", channel); | 180 | "DMA active\n", chan); |
| 159 | 181 | ||
| 160 | dma->dma_mode = mode; | 182 | dma->dma_mode = mode; |
| 161 | dma->invalid = 1; | 183 | dma->invalid = 1; |
| @@ -164,42 +186,42 @@ EXPORT_SYMBOL(set_dma_mode); | |||
| 164 | 186 | ||
| 165 | /* Enable DMA channel | 187 | /* Enable DMA channel |
| 166 | */ | 188 | */ |
| 167 | void enable_dma (dmach_t channel) | 189 | void enable_dma (unsigned int chan) |
| 168 | { | 190 | { |
| 169 | dma_t *dma = dma_chan + channel; | 191 | dma_t *dma = dma_channel(chan); |
| 170 | 192 | ||
| 171 | if (!dma->lock) | 193 | if (!dma->lock) |
| 172 | goto free_dma; | 194 | goto free_dma; |
| 173 | 195 | ||
| 174 | if (dma->active == 0) { | 196 | if (dma->active == 0) { |
| 175 | dma->active = 1; | 197 | dma->active = 1; |
| 176 | dma->d_ops->enable(channel, dma); | 198 | dma->d_ops->enable(chan, dma); |
| 177 | } | 199 | } |
| 178 | return; | 200 | return; |
| 179 | 201 | ||
| 180 | free_dma: | 202 | free_dma: |
| 181 | printk(KERN_ERR "dma%d: trying to enable free DMA\n", channel); | 203 | printk(KERN_ERR "dma%d: trying to enable free DMA\n", chan); |
| 182 | BUG(); | 204 | BUG(); |
| 183 | } | 205 | } |
| 184 | EXPORT_SYMBOL(enable_dma); | 206 | EXPORT_SYMBOL(enable_dma); |
| 185 | 207 | ||
| 186 | /* Disable DMA channel | 208 | /* Disable DMA channel |
| 187 | */ | 209 | */ |
| 188 | void disable_dma (dmach_t channel) | 210 | void disable_dma (unsigned int chan) |
| 189 | { | 211 | { |
| 190 | dma_t *dma = dma_chan + channel; | 212 | dma_t *dma = dma_channel(chan); |
| 191 | 213 | ||
| 192 | if (!dma->lock) | 214 | if (!dma->lock) |
| 193 | goto free_dma; | 215 | goto free_dma; |
| 194 | 216 | ||
| 195 | if (dma->active == 1) { | 217 | if (dma->active == 1) { |
| 196 | dma->active = 0; | 218 | dma->active = 0; |
| 197 | dma->d_ops->disable(channel, dma); | 219 | dma->d_ops->disable(chan, dma); |
| 198 | } | 220 | } |
| 199 | return; | 221 | return; |
| 200 | 222 | ||
| 201 | free_dma: | 223 | free_dma: |
| 202 | printk(KERN_ERR "dma%d: trying to disable free DMA\n", channel); | 224 | printk(KERN_ERR "dma%d: trying to disable free DMA\n", chan); |
| 203 | BUG(); | 225 | BUG(); |
| 204 | } | 226 | } |
| 205 | EXPORT_SYMBOL(disable_dma); | 227 | EXPORT_SYMBOL(disable_dma); |
| @@ -207,45 +229,38 @@ EXPORT_SYMBOL(disable_dma); | |||
| 207 | /* | 229 | /* |
| 208 | * Is the specified DMA channel active? | 230 | * Is the specified DMA channel active? |
| 209 | */ | 231 | */ |
| 210 | int dma_channel_active(dmach_t channel) | 232 | int dma_channel_active(unsigned int chan) |
| 211 | { | 233 | { |
| 212 | return dma_chan[channel].active; | 234 | dma_t *dma = dma_channel(chan); |
| 235 | return dma->active; | ||
| 213 | } | 236 | } |
| 214 | EXPORT_SYMBOL(dma_channel_active); | 237 | EXPORT_SYMBOL(dma_channel_active); |
| 215 | 238 | ||
| 216 | void set_dma_page(dmach_t channel, char pagenr) | 239 | void set_dma_page(unsigned int chan, char pagenr) |
| 217 | { | 240 | { |
| 218 | printk(KERN_ERR "dma%d: trying to set_dma_page\n", channel); | 241 | printk(KERN_ERR "dma%d: trying to set_dma_page\n", chan); |
| 219 | } | 242 | } |
| 220 | EXPORT_SYMBOL(set_dma_page); | 243 | EXPORT_SYMBOL(set_dma_page); |
| 221 | 244 | ||
| 222 | void set_dma_speed(dmach_t channel, int cycle_ns) | 245 | void set_dma_speed(unsigned int chan, int cycle_ns) |
| 223 | { | 246 | { |
| 224 | dma_t *dma = dma_chan + channel; | 247 | dma_t *dma = dma_channel(chan); |
| 225 | int ret = 0; | 248 | int ret = 0; |
| 226 | 249 | ||
| 227 | if (dma->d_ops->setspeed) | 250 | if (dma->d_ops->setspeed) |
| 228 | ret = dma->d_ops->setspeed(channel, dma, cycle_ns); | 251 | ret = dma->d_ops->setspeed(chan, dma, cycle_ns); |
| 229 | dma->speed = ret; | 252 | dma->speed = ret; |
| 230 | } | 253 | } |
| 231 | EXPORT_SYMBOL(set_dma_speed); | 254 | EXPORT_SYMBOL(set_dma_speed); |
| 232 | 255 | ||
| 233 | int get_dma_residue(dmach_t channel) | 256 | int get_dma_residue(unsigned int chan) |
| 234 | { | 257 | { |
| 235 | dma_t *dma = dma_chan + channel; | 258 | dma_t *dma = dma_channel(chan); |
| 236 | int ret = 0; | 259 | int ret = 0; |
| 237 | 260 | ||
| 238 | if (dma->d_ops->residue) | 261 | if (dma->d_ops->residue) |
| 239 | ret = dma->d_ops->residue(channel, dma); | 262 | ret = dma->d_ops->residue(chan, dma); |
| 240 | 263 | ||
| 241 | return ret; | 264 | return ret; |
| 242 | } | 265 | } |
| 243 | EXPORT_SYMBOL(get_dma_residue); | 266 | EXPORT_SYMBOL(get_dma_residue); |
| 244 | |||
| 245 | static int __init init_dma(void) | ||
| 246 | { | ||
| 247 | arch_dma_init(dma_chan); | ||
| 248 | return 0; | ||
| 249 | } | ||
| 250 | |||
| 251 | core_initcall(init_dma); | ||
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 85040cfeb5e5..d662a2f1fd85 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <asm/vfpmacros.h> | 20 | #include <asm/vfpmacros.h> |
| 21 | #include <mach/entry-macro.S> | 21 | #include <mach/entry-macro.S> |
| 22 | #include <asm/thread_notify.h> | 22 | #include <asm/thread_notify.h> |
| 23 | #include <asm/unwind.h> | ||
| 23 | 24 | ||
| 24 | #include "entry-header.S" | 25 | #include "entry-header.S" |
| 25 | 26 | ||
| @@ -123,6 +124,8 @@ ENDPROC(__und_invalid) | |||
| 123 | #endif | 124 | #endif |
| 124 | 125 | ||
| 125 | .macro svc_entry, stack_hole=0 | 126 | .macro svc_entry, stack_hole=0 |
| 127 | UNWIND(.fnstart ) | ||
| 128 | UNWIND(.save {r0 - pc} ) | ||
| 126 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole) | 129 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole) |
| 127 | SPFIX( tst sp, #4 ) | 130 | SPFIX( tst sp, #4 ) |
| 128 | SPFIX( bicne sp, sp, #4 ) | 131 | SPFIX( bicne sp, sp, #4 ) |
| @@ -196,6 +199,7 @@ __dabt_svc: | |||
| 196 | ldr r0, [sp, #S_PSR] | 199 | ldr r0, [sp, #S_PSR] |
| 197 | msr spsr_cxsf, r0 | 200 | msr spsr_cxsf, r0 |
| 198 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | 201 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
| 202 | UNWIND(.fnend ) | ||
| 199 | ENDPROC(__dabt_svc) | 203 | ENDPROC(__dabt_svc) |
| 200 | 204 | ||
| 201 | .align 5 | 205 | .align 5 |
| @@ -228,6 +232,7 @@ __irq_svc: | |||
| 228 | bleq trace_hardirqs_on | 232 | bleq trace_hardirqs_on |
| 229 | #endif | 233 | #endif |
| 230 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | 234 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
| 235 | UNWIND(.fnend ) | ||
| 231 | ENDPROC(__irq_svc) | 236 | ENDPROC(__irq_svc) |
| 232 | 237 | ||
| 233 | .ltorg | 238 | .ltorg |
| @@ -278,6 +283,7 @@ __und_svc: | |||
| 278 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | 283 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr |
| 279 | msr spsr_cxsf, lr | 284 | msr spsr_cxsf, lr |
| 280 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | 285 | ldmia sp, {r0 - pc}^ @ Restore SVC registers |
| 286 | UNWIND(.fnend ) | ||
| 281 | ENDPROC(__und_svc) | 287 | ENDPROC(__und_svc) |
| 282 | 288 | ||
| 283 | .align 5 | 289 | .align 5 |
| @@ -320,6 +326,7 @@ __pabt_svc: | |||
| 320 | ldr r0, [sp, #S_PSR] | 326 | ldr r0, [sp, #S_PSR] |
| 321 | msr spsr_cxsf, r0 | 327 | msr spsr_cxsf, r0 |
| 322 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | 328 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
| 329 | UNWIND(.fnend ) | ||
| 323 | ENDPROC(__pabt_svc) | 330 | ENDPROC(__pabt_svc) |
| 324 | 331 | ||
| 325 | .align 5 | 332 | .align 5 |
| @@ -343,6 +350,8 @@ ENDPROC(__pabt_svc) | |||
| 343 | #endif | 350 | #endif |
| 344 | 351 | ||
| 345 | .macro usr_entry | 352 | .macro usr_entry |
| 353 | UNWIND(.fnstart ) | ||
| 354 | UNWIND(.cantunwind ) @ don't unwind the user space | ||
| 346 | sub sp, sp, #S_FRAME_SIZE | 355 | sub sp, sp, #S_FRAME_SIZE |
| 347 | stmib sp, {r1 - r12} | 356 | stmib sp, {r1 - r12} |
| 348 | 357 | ||
| @@ -420,6 +429,7 @@ __dabt_usr: | |||
| 420 | mov r2, sp | 429 | mov r2, sp |
| 421 | adr lr, ret_from_exception | 430 | adr lr, ret_from_exception |
| 422 | b do_DataAbort | 431 | b do_DataAbort |
| 432 | UNWIND(.fnend ) | ||
| 423 | ENDPROC(__dabt_usr) | 433 | ENDPROC(__dabt_usr) |
| 424 | 434 | ||
| 425 | .align 5 | 435 | .align 5 |
| @@ -450,6 +460,7 @@ __irq_usr: | |||
| 450 | 460 | ||
| 451 | mov why, #0 | 461 | mov why, #0 |
| 452 | b ret_to_user | 462 | b ret_to_user |
| 463 | UNWIND(.fnend ) | ||
| 453 | ENDPROC(__irq_usr) | 464 | ENDPROC(__irq_usr) |
| 454 | 465 | ||
| 455 | .ltorg | 466 | .ltorg |
| @@ -484,6 +495,7 @@ __und_usr: | |||
| 484 | #else | 495 | #else |
| 485 | b __und_usr_unknown | 496 | b __und_usr_unknown |
| 486 | #endif | 497 | #endif |
| 498 | UNWIND(.fnend ) | ||
| 487 | ENDPROC(__und_usr) | 499 | ENDPROC(__und_usr) |
| 488 | 500 | ||
| 489 | @ | 501 | @ |
| @@ -671,14 +683,18 @@ __pabt_usr: | |||
| 671 | enable_irq @ Enable interrupts | 683 | enable_irq @ Enable interrupts |
| 672 | mov r1, sp @ regs | 684 | mov r1, sp @ regs |
| 673 | bl do_PrefetchAbort @ call abort handler | 685 | bl do_PrefetchAbort @ call abort handler |
| 686 | UNWIND(.fnend ) | ||
| 674 | /* fall through */ | 687 | /* fall through */ |
| 675 | /* | 688 | /* |
| 676 | * This is the return code to user mode for abort handlers | 689 | * This is the return code to user mode for abort handlers |
| 677 | */ | 690 | */ |
| 678 | ENTRY(ret_from_exception) | 691 | ENTRY(ret_from_exception) |
| 692 | UNWIND(.fnstart ) | ||
| 693 | UNWIND(.cantunwind ) | ||
| 679 | get_thread_info tsk | 694 | get_thread_info tsk |
| 680 | mov why, #0 | 695 | mov why, #0 |
| 681 | b ret_to_user | 696 | b ret_to_user |
| 697 | UNWIND(.fnend ) | ||
| 682 | ENDPROC(__pabt_usr) | 698 | ENDPROC(__pabt_usr) |
| 683 | ENDPROC(ret_from_exception) | 699 | ENDPROC(ret_from_exception) |
| 684 | 700 | ||
| @@ -688,6 +704,8 @@ ENDPROC(ret_from_exception) | |||
| 688 | * previous and next are guaranteed not to be the same. | 704 | * previous and next are guaranteed not to be the same. |
| 689 | */ | 705 | */ |
| 690 | ENTRY(__switch_to) | 706 | ENTRY(__switch_to) |
| 707 | UNWIND(.fnstart ) | ||
| 708 | UNWIND(.cantunwind ) | ||
| 691 | add ip, r1, #TI_CPU_SAVE | 709 | add ip, r1, #TI_CPU_SAVE |
| 692 | ldr r3, [r2, #TI_TP_VALUE] | 710 | ldr r3, [r2, #TI_TP_VALUE] |
| 693 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | 711 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack |
| @@ -717,6 +735,7 @@ ENTRY(__switch_to) | |||
| 717 | bl atomic_notifier_call_chain | 735 | bl atomic_notifier_call_chain |
| 718 | mov r0, r5 | 736 | mov r0, r5 |
| 719 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | 737 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously |
| 738 | UNWIND(.fnend ) | ||
| 720 | ENDPROC(__switch_to) | 739 | ENDPROC(__switch_to) |
| 721 | 740 | ||
| 722 | __INIT | 741 | __INIT |
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 159d0416f270..b55cb0331809 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #include <asm/unistd.h> | 11 | #include <asm/unistd.h> |
| 12 | #include <asm/ftrace.h> | 12 | #include <asm/ftrace.h> |
| 13 | #include <mach/entry-macro.S> | 13 | #include <mach/entry-macro.S> |
| 14 | #include <asm/unwind.h> | ||
| 14 | 15 | ||
| 15 | #include "entry-header.S" | 16 | #include "entry-header.S" |
| 16 | 17 | ||
| @@ -22,6 +23,8 @@ | |||
| 22 | * stack. | 23 | * stack. |
| 23 | */ | 24 | */ |
| 24 | ret_fast_syscall: | 25 | ret_fast_syscall: |
| 26 | UNWIND(.fnstart ) | ||
| 27 | UNWIND(.cantunwind ) | ||
| 25 | disable_irq @ disable interrupts | 28 | disable_irq @ disable interrupts |
| 26 | ldr r1, [tsk, #TI_FLAGS] | 29 | ldr r1, [tsk, #TI_FLAGS] |
| 27 | tst r1, #_TIF_WORK_MASK | 30 | tst r1, #_TIF_WORK_MASK |
| @@ -38,6 +41,7 @@ ret_fast_syscall: | |||
| 38 | mov r0, r0 | 41 | mov r0, r0 |
| 39 | add sp, sp, #S_FRAME_SIZE - S_PC | 42 | add sp, sp, #S_FRAME_SIZE - S_PC |
| 40 | movs pc, lr @ return & move spsr_svc into cpsr | 43 | movs pc, lr @ return & move spsr_svc into cpsr |
| 44 | UNWIND(.fnend ) | ||
| 41 | 45 | ||
| 42 | /* | 46 | /* |
| 43 | * Ok, we need to do extra processing, enter the slow path. | 47 | * Ok, we need to do extra processing, enter the slow path. |
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index dab48f27263f..d1731e39b496 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | 22 | ||
| 23 | #include <asm/pgtable.h> | 23 | #include <asm/pgtable.h> |
| 24 | #include <asm/sections.h> | 24 | #include <asm/sections.h> |
| 25 | #include <asm/unwind.h> | ||
| 25 | 26 | ||
| 26 | #ifdef CONFIG_XIP_KERNEL | 27 | #ifdef CONFIG_XIP_KERNEL |
| 27 | /* | 28 | /* |
| @@ -66,6 +67,24 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, | |||
| 66 | char *secstrings, | 67 | char *secstrings, |
| 67 | struct module *mod) | 68 | struct module *mod) |
| 68 | { | 69 | { |
| 70 | #ifdef CONFIG_ARM_UNWIND | ||
| 71 | Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; | ||
| 72 | |||
| 73 | for (s = sechdrs; s < sechdrs_end; s++) { | ||
| 74 | if (strcmp(".ARM.exidx.init.text", secstrings + s->sh_name) == 0) | ||
| 75 | mod->arch.unw_sec_init = s; | ||
| 76 | else if (strcmp(".ARM.exidx.devinit.text", secstrings + s->sh_name) == 0) | ||
| 77 | mod->arch.unw_sec_devinit = s; | ||
| 78 | else if (strcmp(".ARM.exidx", secstrings + s->sh_name) == 0) | ||
| 79 | mod->arch.unw_sec_core = s; | ||
| 80 | else if (strcmp(".init.text", secstrings + s->sh_name) == 0) | ||
| 81 | mod->arch.sec_init_text = s; | ||
| 82 | else if (strcmp(".devinit.text", secstrings + s->sh_name) == 0) | ||
| 83 | mod->arch.sec_devinit_text = s; | ||
| 84 | else if (strcmp(".text", secstrings + s->sh_name) == 0) | ||
| 85 | mod->arch.sec_core_text = s; | ||
| 86 | } | ||
| 87 | #endif | ||
| 69 | return 0; | 88 | return 0; |
| 70 | } | 89 | } |
| 71 | 90 | ||
| @@ -104,6 +123,10 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, | |||
| 104 | loc = dstsec->sh_addr + rel->r_offset; | 123 | loc = dstsec->sh_addr + rel->r_offset; |
| 105 | 124 | ||
| 106 | switch (ELF32_R_TYPE(rel->r_info)) { | 125 | switch (ELF32_R_TYPE(rel->r_info)) { |
| 126 | case R_ARM_NONE: | ||
| 127 | /* ignore */ | ||
| 128 | break; | ||
| 129 | |||
| 107 | case R_ARM_ABS32: | 130 | case R_ARM_ABS32: |
| 108 | *(u32 *)loc += sym->st_value; | 131 | *(u32 *)loc += sym->st_value; |
| 109 | break; | 132 | break; |
| @@ -132,6 +155,20 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, | |||
| 132 | *(u32 *)loc |= offset & 0x00ffffff; | 155 | *(u32 *)loc |= offset & 0x00ffffff; |
| 133 | break; | 156 | break; |
| 134 | 157 | ||
| 158 | case R_ARM_V4BX: | ||
| 159 | /* Preserve Rm and the condition code. Alter | ||
| 160 | * other bits to re-code instruction as | ||
| 161 | * MOV PC,Rm. | ||
| 162 | */ | ||
| 163 | *(u32 *)loc &= 0xf000000f; | ||
| 164 | *(u32 *)loc |= 0x01a0f000; | ||
| 165 | break; | ||
| 166 | |||
| 167 | case R_ARM_PREL31: | ||
| 168 | offset = *(u32 *)loc + sym->st_value - loc; | ||
| 169 | *(u32 *)loc = offset & 0x7fffffff; | ||
| 170 | break; | ||
| 171 | |||
| 135 | default: | 172 | default: |
| 136 | printk(KERN_ERR "%s: unknown relocation: %u\n", | 173 | printk(KERN_ERR "%s: unknown relocation: %u\n", |
| 137 | module->name, ELF32_R_TYPE(rel->r_info)); | 174 | module->name, ELF32_R_TYPE(rel->r_info)); |
| @@ -150,14 +187,50 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab, | |||
| 150 | return -ENOEXEC; | 187 | return -ENOEXEC; |
| 151 | } | 188 | } |
| 152 | 189 | ||
| 190 | #ifdef CONFIG_ARM_UNWIND | ||
| 191 | static void register_unwind_tables(struct module *mod) | ||
| 192 | { | ||
| 193 | if (mod->arch.unw_sec_init && mod->arch.sec_init_text) | ||
| 194 | mod->arch.unwind_init = | ||
| 195 | unwind_table_add(mod->arch.unw_sec_init->sh_addr, | ||
| 196 | mod->arch.unw_sec_init->sh_size, | ||
| 197 | mod->arch.sec_init_text->sh_addr, | ||
| 198 | mod->arch.sec_init_text->sh_size); | ||
| 199 | if (mod->arch.unw_sec_devinit && mod->arch.sec_devinit_text) | ||
| 200 | mod->arch.unwind_devinit = | ||
| 201 | unwind_table_add(mod->arch.unw_sec_devinit->sh_addr, | ||
| 202 | mod->arch.unw_sec_devinit->sh_size, | ||
| 203 | mod->arch.sec_devinit_text->sh_addr, | ||
| 204 | mod->arch.sec_devinit_text->sh_size); | ||
| 205 | if (mod->arch.unw_sec_core && mod->arch.sec_core_text) | ||
| 206 | mod->arch.unwind_core = | ||
| 207 | unwind_table_add(mod->arch.unw_sec_core->sh_addr, | ||
| 208 | mod->arch.unw_sec_core->sh_size, | ||
| 209 | mod->arch.sec_core_text->sh_addr, | ||
| 210 | mod->arch.sec_core_text->sh_size); | ||
| 211 | } | ||
| 212 | |||
| 213 | static void unregister_unwind_tables(struct module *mod) | ||
| 214 | { | ||
| 215 | unwind_table_del(mod->arch.unwind_init); | ||
| 216 | unwind_table_del(mod->arch.unwind_devinit); | ||
| 217 | unwind_table_del(mod->arch.unwind_core); | ||
| 218 | } | ||
| 219 | #else | ||
| 220 | static inline void register_unwind_tables(struct module *mod) { } | ||
| 221 | static inline void unregister_unwind_tables(struct module *mod) { } | ||
| 222 | #endif | ||
| 223 | |||
| 153 | int | 224 | int |
| 154 | module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, | 225 | module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, |
| 155 | struct module *module) | 226 | struct module *module) |
| 156 | { | 227 | { |
| 228 | register_unwind_tables(module); | ||
| 157 | return 0; | 229 | return 0; |
| 158 | } | 230 | } |
| 159 | 231 | ||
| 160 | void | 232 | void |
| 161 | module_arch_cleanup(struct module *mod) | 233 | module_arch_cleanup(struct module *mod) |
| 162 | { | 234 | { |
| 235 | unregister_unwind_tables(mod); | ||
| 163 | } | 236 | } |
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index d3ea6fa89521..2de14e2afdc5 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | #include <asm/processor.h> | 34 | #include <asm/processor.h> |
| 35 | #include <asm/system.h> | 35 | #include <asm/system.h> |
| 36 | #include <asm/thread_notify.h> | 36 | #include <asm/thread_notify.h> |
| 37 | #include <asm/stacktrace.h> | ||
| 37 | #include <asm/mach/time.h> | 38 | #include <asm/mach/time.h> |
| 38 | 39 | ||
| 39 | static const char *processor_modes[] = { | 40 | static const char *processor_modes[] = { |
| @@ -82,7 +83,7 @@ static int __init hlt_setup(char *__unused) | |||
| 82 | __setup("nohlt", nohlt_setup); | 83 | __setup("nohlt", nohlt_setup); |
| 83 | __setup("hlt", hlt_setup); | 84 | __setup("hlt", hlt_setup); |
| 84 | 85 | ||
| 85 | void arm_machine_restart(char mode) | 86 | void arm_machine_restart(char mode, const char *cmd) |
| 86 | { | 87 | { |
| 87 | /* | 88 | /* |
| 88 | * Clean and disable cache, and turn off interrupts | 89 | * Clean and disable cache, and turn off interrupts |
| @@ -99,7 +100,7 @@ void arm_machine_restart(char mode) | |||
| 99 | /* | 100 | /* |
| 100 | * Now call the architecture specific reboot code. | 101 | * Now call the architecture specific reboot code. |
| 101 | */ | 102 | */ |
| 102 | arch_reset(mode); | 103 | arch_reset(mode, cmd); |
| 103 | 104 | ||
| 104 | /* | 105 | /* |
| 105 | * Whoops - the architecture was unable to reboot. | 106 | * Whoops - the architecture was unable to reboot. |
| @@ -119,7 +120,7 @@ EXPORT_SYMBOL(pm_idle); | |||
| 119 | void (*pm_power_off)(void); | 120 | void (*pm_power_off)(void); |
| 120 | EXPORT_SYMBOL(pm_power_off); | 121 | EXPORT_SYMBOL(pm_power_off); |
| 121 | 122 | ||
| 122 | void (*arm_pm_restart)(char str) = arm_machine_restart; | 123 | void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart; |
| 123 | EXPORT_SYMBOL_GPL(arm_pm_restart); | 124 | EXPORT_SYMBOL_GPL(arm_pm_restart); |
| 124 | 125 | ||
| 125 | 126 | ||
| @@ -194,9 +195,9 @@ void machine_power_off(void) | |||
| 194 | pm_power_off(); | 195 | pm_power_off(); |
| 195 | } | 196 | } |
| 196 | 197 | ||
| 197 | void machine_restart(char * __unused) | 198 | void machine_restart(char *cmd) |
| 198 | { | 199 | { |
| 199 | arm_pm_restart(reboot_mode); | 200 | arm_pm_restart(reboot_mode, cmd); |
| 200 | } | 201 | } |
| 201 | 202 | ||
| 202 | void __show_regs(struct pt_regs *regs) | 203 | void __show_regs(struct pt_regs *regs) |
| @@ -372,23 +373,21 @@ EXPORT_SYMBOL(kernel_thread); | |||
| 372 | 373 | ||
| 373 | unsigned long get_wchan(struct task_struct *p) | 374 | unsigned long get_wchan(struct task_struct *p) |
| 374 | { | 375 | { |
| 375 | unsigned long fp, lr; | 376 | struct stackframe frame; |
| 376 | unsigned long stack_start, stack_end; | ||
| 377 | int count = 0; | 377 | int count = 0; |
| 378 | if (!p || p == current || p->state == TASK_RUNNING) | 378 | if (!p || p == current || p->state == TASK_RUNNING) |
| 379 | return 0; | 379 | return 0; |
| 380 | 380 | ||
| 381 | stack_start = (unsigned long)end_of_stack(p); | 381 | frame.fp = thread_saved_fp(p); |
| 382 | stack_end = (unsigned long)task_stack_page(p) + THREAD_SIZE; | 382 | frame.sp = thread_saved_sp(p); |
| 383 | 383 | frame.lr = 0; /* recovered from the stack */ | |
| 384 | fp = thread_saved_fp(p); | 384 | frame.pc = thread_saved_pc(p); |
| 385 | do { | 385 | do { |
| 386 | if (fp < stack_start || fp > stack_end) | 386 | int ret = unwind_frame(&frame); |
| 387 | if (ret < 0) | ||
| 387 | return 0; | 388 | return 0; |
| 388 | lr = ((unsigned long *)fp)[-1]; | 389 | if (!in_sched_functions(frame.pc)) |
| 389 | if (!in_sched_functions(lr)) | 390 | return frame.pc; |
| 390 | return lr; | ||
| 391 | fp = *(unsigned long *) (fp - 12); | ||
| 392 | } while (count ++ < 16); | 391 | } while (count ++ < 16); |
| 393 | return 0; | 392 | return 0; |
| 394 | } | 393 | } |
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index df653ea59250..89882a1d0187 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c | |||
| @@ -653,6 +653,54 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp) | |||
| 653 | } | 653 | } |
| 654 | #endif | 654 | #endif |
| 655 | 655 | ||
| 656 | #ifdef CONFIG_VFP | ||
| 657 | /* | ||
| 658 | * Get the child VFP state. | ||
| 659 | */ | ||
| 660 | static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data) | ||
| 661 | { | ||
| 662 | struct thread_info *thread = task_thread_info(tsk); | ||
| 663 | union vfp_state *vfp = &thread->vfpstate; | ||
| 664 | struct user_vfp __user *ufp = data; | ||
| 665 | |||
| 666 | vfp_sync_state(thread); | ||
| 667 | |||
| 668 | /* copy the floating point registers */ | ||
| 669 | if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs, | ||
| 670 | sizeof(vfp->hard.fpregs))) | ||
| 671 | return -EFAULT; | ||
| 672 | |||
| 673 | /* copy the status and control register */ | ||
| 674 | if (put_user(vfp->hard.fpscr, &ufp->fpscr)) | ||
| 675 | return -EFAULT; | ||
| 676 | |||
| 677 | return 0; | ||
| 678 | } | ||
| 679 | |||
| 680 | /* | ||
| 681 | * Set the child VFP state. | ||
| 682 | */ | ||
| 683 | static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) | ||
| 684 | { | ||
| 685 | struct thread_info *thread = task_thread_info(tsk); | ||
| 686 | union vfp_state *vfp = &thread->vfpstate; | ||
| 687 | struct user_vfp __user *ufp = data; | ||
| 688 | |||
| 689 | vfp_sync_state(thread); | ||
| 690 | |||
| 691 | /* copy the floating point registers */ | ||
| 692 | if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs, | ||
| 693 | sizeof(vfp->hard.fpregs))) | ||
| 694 | return -EFAULT; | ||
| 695 | |||
| 696 | /* copy the status and control register */ | ||
| 697 | if (get_user(vfp->hard.fpscr, &ufp->fpscr)) | ||
| 698 | return -EFAULT; | ||
| 699 | |||
| 700 | return 0; | ||
| 701 | } | ||
| 702 | #endif | ||
| 703 | |||
| 656 | long arch_ptrace(struct task_struct *child, long request, long addr, long data) | 704 | long arch_ptrace(struct task_struct *child, long request, long addr, long data) |
| 657 | { | 705 | { |
| 658 | int ret; | 706 | int ret; |
| @@ -775,6 +823,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
| 775 | break; | 823 | break; |
| 776 | #endif | 824 | #endif |
| 777 | 825 | ||
| 826 | #ifdef CONFIG_VFP | ||
| 827 | case PTRACE_GETVFPREGS: | ||
| 828 | ret = ptrace_getvfpregs(child, (void __user *)data); | ||
| 829 | break; | ||
| 830 | |||
| 831 | case PTRACE_SETVFPREGS: | ||
| 832 | ret = ptrace_setvfpregs(child, (void __user *)data); | ||
| 833 | break; | ||
| 834 | #endif | ||
| 835 | |||
| 778 | default: | 836 | default: |
| 779 | ret = ptrace_request(child, request, addr, data); | 837 | ret = ptrace_request(child, request, addr, data); |
| 780 | break; | 838 | break; |
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 68d6494c0389..bc5e4128f9f3 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | #include <asm/mach/irq.h> | 40 | #include <asm/mach/irq.h> |
| 41 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
| 42 | #include <asm/traps.h> | 42 | #include <asm/traps.h> |
| 43 | #include <asm/unwind.h> | ||
| 43 | 44 | ||
| 44 | #include "compat.h" | 45 | #include "compat.h" |
| 45 | #include "atags.h" | 46 | #include "atags.h" |
| @@ -685,6 +686,8 @@ void __init setup_arch(char **cmdline_p) | |||
| 685 | struct machine_desc *mdesc; | 686 | struct machine_desc *mdesc; |
| 686 | char *from = default_command_line; | 687 | char *from = default_command_line; |
| 687 | 688 | ||
| 689 | unwind_init(); | ||
| 690 | |||
| 688 | setup_processor(); | 691 | setup_processor(); |
| 689 | mdesc = setup_machine(machine_arch_type); | 692 | mdesc = setup_machine(machine_arch_type); |
| 690 | machine_name = mdesc->name; | 693 | machine_name = mdesc->name; |
| @@ -780,6 +783,8 @@ static const char *hwcap_str[] = { | |||
| 780 | "crunch", | 783 | "crunch", |
| 781 | "thumbee", | 784 | "thumbee", |
| 782 | "neon", | 785 | "neon", |
| 786 | "vfpv3", | ||
| 787 | "vfpv3d16", | ||
| 783 | NULL | 788 | NULL |
| 784 | }; | 789 | }; |
| 785 | 790 | ||
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 55fa7ff96a3e..7801aac3c043 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
| @@ -93,6 +93,7 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 93 | pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET); | 93 | pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET); |
| 94 | *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | | 94 | *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | |
| 95 | PMD_TYPE_SECT | PMD_SECT_AP_WRITE); | 95 | PMD_TYPE_SECT | PMD_SECT_AP_WRITE); |
| 96 | flush_pmd_entry(pmd); | ||
| 96 | 97 | ||
| 97 | /* | 98 | /* |
| 98 | * We need to tell the secondary core where to find | 99 | * We need to tell the secondary core where to find |
| @@ -130,6 +131,7 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 130 | secondary_data.pgdir = 0; | 131 | secondary_data.pgdir = 0; |
| 131 | 132 | ||
| 132 | *pmd = __pmd(0); | 133 | *pmd = __pmd(0); |
| 134 | clean_pmd_entry(pmd); | ||
| 133 | pgd_free(&init_mm, pgd); | 135 | pgd_free(&init_mm, pgd); |
| 134 | 136 | ||
| 135 | if (ret) { | 137 | if (ret) { |
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index fc650f64df43..9f444e5cc165 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c | |||
| @@ -2,35 +2,60 @@ | |||
| 2 | #include <linux/sched.h> | 2 | #include <linux/sched.h> |
| 3 | #include <linux/stacktrace.h> | 3 | #include <linux/stacktrace.h> |
| 4 | 4 | ||
| 5 | #include "stacktrace.h" | 5 | #include <asm/stacktrace.h> |
| 6 | 6 | ||
| 7 | int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high, | 7 | #if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) |
| 8 | int (*fn)(struct stackframe *, void *), void *data) | 8 | /* |
| 9 | * Unwind the current stack frame and store the new register values in the | ||
| 10 | * structure passed as argument. Unwinding is equivalent to a function return, | ||
| 11 | * hence the new PC value rather than LR should be used for backtrace. | ||
| 12 | * | ||
| 13 | * With framepointer enabled, a simple function prologue looks like this: | ||
| 14 | * mov ip, sp | ||
| 15 | * stmdb sp!, {fp, ip, lr, pc} | ||
| 16 | * sub fp, ip, #4 | ||
| 17 | * | ||
| 18 | * A simple function epilogue looks like this: | ||
| 19 | * ldm sp, {fp, sp, pc} | ||
| 20 | * | ||
| 21 | * Note that with framepointer enabled, even the leaf functions have the same | ||
| 22 | * prologue and epilogue, therefore we can ignore the LR value in this case. | ||
| 23 | */ | ||
| 24 | int unwind_frame(struct stackframe *frame) | ||
| 9 | { | 25 | { |
| 10 | struct stackframe *frame; | 26 | unsigned long high, low; |
| 11 | 27 | unsigned long fp = frame->fp; | |
| 12 | do { | ||
| 13 | /* | ||
| 14 | * Check current frame pointer is within bounds | ||
| 15 | */ | ||
| 16 | if (fp < (low + 12) || fp + 4 >= high) | ||
| 17 | break; | ||
| 18 | 28 | ||
| 19 | frame = (struct stackframe *)(fp - 12); | 29 | /* only go to a higher address on the stack */ |
| 30 | low = frame->sp; | ||
| 31 | high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE; | ||
| 20 | 32 | ||
| 21 | if (fn(frame, data)) | 33 | /* check current frame pointer is within bounds */ |
| 22 | break; | 34 | if (fp < (low + 12) || fp + 4 >= high) |
| 35 | return -EINVAL; | ||
| 23 | 36 | ||
| 24 | /* | 37 | /* restore the registers from the stack frame */ |
| 25 | * Update the low bound - the next frame must always | 38 | frame->fp = *(unsigned long *)(fp - 12); |
| 26 | * be at a higher address than the current frame. | 39 | frame->sp = *(unsigned long *)(fp - 8); |
| 27 | */ | 40 | frame->pc = *(unsigned long *)(fp - 4); |
| 28 | low = fp + 4; | ||
| 29 | fp = frame->fp; | ||
| 30 | } while (fp); | ||
| 31 | 41 | ||
| 32 | return 0; | 42 | return 0; |
| 33 | } | 43 | } |
| 44 | #endif | ||
| 45 | |||
| 46 | void walk_stackframe(struct stackframe *frame, | ||
| 47 | int (*fn)(struct stackframe *, void *), void *data) | ||
| 48 | { | ||
| 49 | while (1) { | ||
| 50 | int ret; | ||
| 51 | |||
| 52 | if (fn(frame, data)) | ||
| 53 | break; | ||
| 54 | ret = unwind_frame(frame); | ||
| 55 | if (ret < 0) | ||
| 56 | break; | ||
| 57 | } | ||
| 58 | } | ||
| 34 | EXPORT_SYMBOL(walk_stackframe); | 59 | EXPORT_SYMBOL(walk_stackframe); |
| 35 | 60 | ||
| 36 | #ifdef CONFIG_STACKTRACE | 61 | #ifdef CONFIG_STACKTRACE |
| @@ -44,7 +69,7 @@ static int save_trace(struct stackframe *frame, void *d) | |||
| 44 | { | 69 | { |
| 45 | struct stack_trace_data *data = d; | 70 | struct stack_trace_data *data = d; |
| 46 | struct stack_trace *trace = data->trace; | 71 | struct stack_trace *trace = data->trace; |
| 47 | unsigned long addr = frame->lr; | 72 | unsigned long addr = frame->pc; |
| 48 | 73 | ||
| 49 | if (data->no_sched_functions && in_sched_functions(addr)) | 74 | if (data->no_sched_functions && in_sched_functions(addr)) |
| 50 | return 0; | 75 | return 0; |
| @@ -61,11 +86,10 @@ static int save_trace(struct stackframe *frame, void *d) | |||
| 61 | void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) | 86 | void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) |
| 62 | { | 87 | { |
| 63 | struct stack_trace_data data; | 88 | struct stack_trace_data data; |
| 64 | unsigned long fp, base; | 89 | struct stackframe frame; |
| 65 | 90 | ||
| 66 | data.trace = trace; | 91 | data.trace = trace; |
| 67 | data.skip = trace->skip; | 92 | data.skip = trace->skip; |
| 68 | base = (unsigned long)task_stack_page(tsk); | ||
| 69 | 93 | ||
| 70 | if (tsk != current) { | 94 | if (tsk != current) { |
| 71 | #ifdef CONFIG_SMP | 95 | #ifdef CONFIG_SMP |
| @@ -76,14 +100,22 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) | |||
| 76 | BUG(); | 100 | BUG(); |
| 77 | #else | 101 | #else |
| 78 | data.no_sched_functions = 1; | 102 | data.no_sched_functions = 1; |
| 79 | fp = thread_saved_fp(tsk); | 103 | frame.fp = thread_saved_fp(tsk); |
| 104 | frame.sp = thread_saved_sp(tsk); | ||
| 105 | frame.lr = 0; /* recovered from the stack */ | ||
| 106 | frame.pc = thread_saved_pc(tsk); | ||
| 80 | #endif | 107 | #endif |
| 81 | } else { | 108 | } else { |
| 109 | register unsigned long current_sp asm ("sp"); | ||
| 110 | |||
| 82 | data.no_sched_functions = 0; | 111 | data.no_sched_functions = 0; |
| 83 | asm("mov %0, fp" : "=r" (fp)); | 112 | frame.fp = (unsigned long)__builtin_frame_address(0); |
| 113 | frame.sp = current_sp; | ||
| 114 | frame.lr = (unsigned long)__builtin_return_address(0); | ||
| 115 | frame.pc = (unsigned long)save_stack_trace_tsk; | ||
| 84 | } | 116 | } |
| 85 | 117 | ||
| 86 | walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data); | 118 | walk_stackframe(&frame, save_trace, &data); |
| 87 | if (trace->nr_entries < trace->max_entries) | 119 | if (trace->nr_entries < trace->max_entries) |
| 88 | trace->entries[trace->nr_entries++] = ULONG_MAX; | 120 | trace->entries[trace->nr_entries++] = ULONG_MAX; |
| 89 | } | 121 | } |
diff --git a/arch/arm/kernel/stacktrace.h b/arch/arm/kernel/stacktrace.h deleted file mode 100644 index e9fd20cb5662..000000000000 --- a/arch/arm/kernel/stacktrace.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | struct stackframe { | ||
| 2 | unsigned long fp; | ||
| 3 | unsigned long sp; | ||
| 4 | unsigned long lr; | ||
| 5 | unsigned long pc; | ||
| 6 | }; | ||
| 7 | |||
| 8 | int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high, | ||
| 9 | int (*fn)(struct stackframe *, void *), void *data); | ||
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index c68b44aa88d2..4cdc4a0bd02d 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | 33 | ||
| 34 | #include <asm/leds.h> | 34 | #include <asm/leds.h> |
| 35 | #include <asm/thread_info.h> | 35 | #include <asm/thread_info.h> |
| 36 | #include <asm/stacktrace.h> | ||
| 36 | #include <asm/mach/time.h> | 37 | #include <asm/mach/time.h> |
| 37 | 38 | ||
| 38 | /* | 39 | /* |
| @@ -55,14 +56,22 @@ EXPORT_SYMBOL(rtc_lock); | |||
| 55 | #ifdef CONFIG_SMP | 56 | #ifdef CONFIG_SMP |
| 56 | unsigned long profile_pc(struct pt_regs *regs) | 57 | unsigned long profile_pc(struct pt_regs *regs) |
| 57 | { | 58 | { |
| 58 | unsigned long fp, pc = instruction_pointer(regs); | 59 | struct stackframe frame; |
| 59 | 60 | ||
| 60 | if (in_lock_functions(pc)) { | 61 | if (!in_lock_functions(regs->ARM_pc)) |
| 61 | fp = regs->ARM_fp; | 62 | return regs->ARM_pc; |
| 62 | pc = ((unsigned long *)fp)[-1]; | 63 | |
| 63 | } | 64 | frame.fp = regs->ARM_fp; |
| 65 | frame.sp = regs->ARM_sp; | ||
| 66 | frame.lr = regs->ARM_lr; | ||
| 67 | frame.pc = regs->ARM_pc; | ||
| 68 | do { | ||
| 69 | int ret = unwind_frame(&frame); | ||
| 70 | if (ret < 0) | ||
| 71 | return 0; | ||
| 72 | } while (in_lock_functions(frame.pc)); | ||
| 64 | 73 | ||
| 65 | return pc; | 74 | return frame.pc; |
| 66 | } | 75 | } |
| 67 | EXPORT_SYMBOL(profile_pc); | 76 | EXPORT_SYMBOL(profile_pc); |
| 68 | #endif | 77 | #endif |
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 79abc4ddc0cf..57eb0f6f6005 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <asm/system.h> | 27 | #include <asm/system.h> |
| 28 | #include <asm/unistd.h> | 28 | #include <asm/unistd.h> |
| 29 | #include <asm/traps.h> | 29 | #include <asm/traps.h> |
| 30 | #include <asm/unwind.h> | ||
| 30 | 31 | ||
| 31 | #include "ptrace.h" | 32 | #include "ptrace.h" |
| 32 | #include "signal.h" | 33 | #include "signal.h" |
| @@ -61,6 +62,7 @@ void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long | |||
| 61 | dump_mem("Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs)); | 62 | dump_mem("Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs)); |
| 62 | } | 63 | } |
| 63 | 64 | ||
| 65 | #ifndef CONFIG_ARM_UNWIND | ||
| 64 | /* | 66 | /* |
| 65 | * Stack pointers should always be within the kernels view of | 67 | * Stack pointers should always be within the kernels view of |
| 66 | * physical memory. If it is not there, then we can't dump | 68 | * physical memory. If it is not there, then we can't dump |
| @@ -74,6 +76,7 @@ static int verify_stack(unsigned long sp) | |||
| 74 | 76 | ||
| 75 | return 0; | 77 | return 0; |
| 76 | } | 78 | } |
| 79 | #endif | ||
| 77 | 80 | ||
| 78 | /* | 81 | /* |
| 79 | * Dump out the contents of some memory nicely... | 82 | * Dump out the contents of some memory nicely... |
| @@ -150,13 +153,33 @@ static void dump_instr(struct pt_regs *regs) | |||
| 150 | set_fs(fs); | 153 | set_fs(fs); |
| 151 | } | 154 | } |
| 152 | 155 | ||
| 156 | #ifdef CONFIG_ARM_UNWIND | ||
| 157 | static inline void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) | ||
| 158 | { | ||
| 159 | unwind_backtrace(regs, tsk); | ||
| 160 | } | ||
| 161 | #else | ||
| 153 | static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) | 162 | static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) |
| 154 | { | 163 | { |
| 155 | unsigned int fp; | 164 | unsigned int fp, mode; |
| 156 | int ok = 1; | 165 | int ok = 1; |
| 157 | 166 | ||
| 158 | printk("Backtrace: "); | 167 | printk("Backtrace: "); |
| 159 | fp = regs->ARM_fp; | 168 | |
| 169 | if (!tsk) | ||
| 170 | tsk = current; | ||
| 171 | |||
| 172 | if (regs) { | ||
| 173 | fp = regs->ARM_fp; | ||
| 174 | mode = processor_mode(regs); | ||
| 175 | } else if (tsk != current) { | ||
| 176 | fp = thread_saved_fp(tsk); | ||
| 177 | mode = 0x10; | ||
| 178 | } else { | ||
| 179 | asm("mov %0, fp" : "=r" (fp) : : "cc"); | ||
| 180 | mode = 0x10; | ||
| 181 | } | ||
| 182 | |||
| 160 | if (!fp) { | 183 | if (!fp) { |
| 161 | printk("no frame pointer"); | 184 | printk("no frame pointer"); |
| 162 | ok = 0; | 185 | ok = 0; |
| @@ -168,29 +191,20 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) | |||
| 168 | printk("\n"); | 191 | printk("\n"); |
| 169 | 192 | ||
| 170 | if (ok) | 193 | if (ok) |
| 171 | c_backtrace(fp, processor_mode(regs)); | 194 | c_backtrace(fp, mode); |
| 172 | } | 195 | } |
| 196 | #endif | ||
| 173 | 197 | ||
| 174 | void dump_stack(void) | 198 | void dump_stack(void) |
| 175 | { | 199 | { |
| 176 | __backtrace(); | 200 | dump_backtrace(NULL, NULL); |
| 177 | } | 201 | } |
| 178 | 202 | ||
| 179 | EXPORT_SYMBOL(dump_stack); | 203 | EXPORT_SYMBOL(dump_stack); |
| 180 | 204 | ||
| 181 | void show_stack(struct task_struct *tsk, unsigned long *sp) | 205 | void show_stack(struct task_struct *tsk, unsigned long *sp) |
| 182 | { | 206 | { |
| 183 | unsigned long fp; | 207 | dump_backtrace(NULL, tsk); |
| 184 | |||
| 185 | if (!tsk) | ||
| 186 | tsk = current; | ||
| 187 | |||
| 188 | if (tsk != current) | ||
| 189 | fp = thread_saved_fp(tsk); | ||
| 190 | else | ||
| 191 | asm("mov %0, fp" : "=r" (fp) : : "cc"); | ||
| 192 | |||
| 193 | c_backtrace(fp, 0x10); | ||
| 194 | barrier(); | 208 | barrier(); |
| 195 | } | 209 | } |
| 196 | 210 | ||
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c new file mode 100644 index 000000000000..1dedc2c7ff49 --- /dev/null +++ b/arch/arm/kernel/unwind.c | |||
| @@ -0,0 +1,434 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/kernel/unwind.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | * | ||
| 19 | * | ||
| 20 | * Stack unwinding support for ARM | ||
| 21 | * | ||
| 22 | * An ARM EABI version of gcc is required to generate the unwind | ||
| 23 | * tables. For information about the structure of the unwind tables, | ||
| 24 | * see "Exception Handling ABI for the ARM Architecture" at: | ||
| 25 | * | ||
| 26 | * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/kernel.h> | ||
| 30 | #include <linux/init.h> | ||
| 31 | #include <linux/module.h> | ||
| 32 | #include <linux/sched.h> | ||
| 33 | #include <linux/slab.h> | ||
| 34 | #include <linux/spinlock.h> | ||
| 35 | #include <linux/list.h> | ||
| 36 | |||
| 37 | #include <asm/stacktrace.h> | ||
| 38 | #include <asm/traps.h> | ||
| 39 | #include <asm/unwind.h> | ||
| 40 | |||
| 41 | /* Dummy functions to avoid linker complaints */ | ||
| 42 | void __aeabi_unwind_cpp_pr0(void) | ||
| 43 | { | ||
| 44 | }; | ||
| 45 | EXPORT_SYMBOL(__aeabi_unwind_cpp_pr0); | ||
| 46 | |||
| 47 | void __aeabi_unwind_cpp_pr1(void) | ||
| 48 | { | ||
| 49 | }; | ||
| 50 | EXPORT_SYMBOL(__aeabi_unwind_cpp_pr1); | ||
| 51 | |||
| 52 | void __aeabi_unwind_cpp_pr2(void) | ||
| 53 | { | ||
| 54 | }; | ||
| 55 | EXPORT_SYMBOL(__aeabi_unwind_cpp_pr2); | ||
| 56 | |||
| 57 | struct unwind_ctrl_block { | ||
| 58 | unsigned long vrs[16]; /* virtual register set */ | ||
| 59 | unsigned long *insn; /* pointer to the current instructions word */ | ||
| 60 | int entries; /* number of entries left to interpret */ | ||
| 61 | int byte; /* current byte number in the instructions word */ | ||
| 62 | }; | ||
| 63 | |||
| 64 | enum regs { | ||
| 65 | FP = 11, | ||
| 66 | SP = 13, | ||
| 67 | LR = 14, | ||
| 68 | PC = 15 | ||
| 69 | }; | ||
| 70 | |||
| 71 | extern struct unwind_idx __start_unwind_idx[]; | ||
| 72 | extern struct unwind_idx __stop_unwind_idx[]; | ||
| 73 | |||
| 74 | static DEFINE_SPINLOCK(unwind_lock); | ||
| 75 | static LIST_HEAD(unwind_tables); | ||
| 76 | |||
| 77 | /* Convert a prel31 symbol to an absolute address */ | ||
| 78 | #define prel31_to_addr(ptr) \ | ||
| 79 | ({ \ | ||
| 80 | /* sign-extend to 32 bits */ \ | ||
| 81 | long offset = (((long)*(ptr)) << 1) >> 1; \ | ||
| 82 | (unsigned long)(ptr) + offset; \ | ||
| 83 | }) | ||
| 84 | |||
| 85 | /* | ||
| 86 | * Binary search in the unwind index. The entries entries are | ||
| 87 | * guaranteed to be sorted in ascending order by the linker. | ||
| 88 | */ | ||
| 89 | static struct unwind_idx *search_index(unsigned long addr, | ||
| 90 | struct unwind_idx *first, | ||
| 91 | struct unwind_idx *last) | ||
| 92 | { | ||
| 93 | pr_debug("%s(%08lx, %p, %p)\n", __func__, addr, first, last); | ||
| 94 | |||
| 95 | if (addr < first->addr) { | ||
| 96 | pr_warning("unwind: Unknown symbol address %08lx\n", addr); | ||
| 97 | return NULL; | ||
| 98 | } else if (addr >= last->addr) | ||
| 99 | return last; | ||
| 100 | |||
| 101 | while (first < last - 1) { | ||
| 102 | struct unwind_idx *mid = first + ((last - first + 1) >> 1); | ||
| 103 | |||
| 104 | if (addr < mid->addr) | ||
| 105 | last = mid; | ||
| 106 | else | ||
| 107 | first = mid; | ||
| 108 | } | ||
| 109 | |||
| 110 | return first; | ||
| 111 | } | ||
| 112 | |||
| 113 | static struct unwind_idx *unwind_find_idx(unsigned long addr) | ||
| 114 | { | ||
| 115 | struct unwind_idx *idx = NULL; | ||
| 116 | unsigned long flags; | ||
| 117 | |||
| 118 | pr_debug("%s(%08lx)\n", __func__, addr); | ||
| 119 | |||
| 120 | if (core_kernel_text(addr)) | ||
| 121 | /* main unwind table */ | ||
| 122 | idx = search_index(addr, __start_unwind_idx, | ||
| 123 | __stop_unwind_idx - 1); | ||
| 124 | else { | ||
| 125 | /* module unwind tables */ | ||
| 126 | struct unwind_table *table; | ||
| 127 | |||
| 128 | spin_lock_irqsave(&unwind_lock, flags); | ||
| 129 | list_for_each_entry(table, &unwind_tables, list) { | ||
| 130 | if (addr >= table->begin_addr && | ||
| 131 | addr < table->end_addr) { | ||
| 132 | idx = search_index(addr, table->start, | ||
| 133 | table->stop - 1); | ||
| 134 | break; | ||
| 135 | } | ||
| 136 | } | ||
| 137 | spin_unlock_irqrestore(&unwind_lock, flags); | ||
| 138 | } | ||
| 139 | |||
| 140 | pr_debug("%s: idx = %p\n", __func__, idx); | ||
| 141 | return idx; | ||
| 142 | } | ||
| 143 | |||
| 144 | static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl) | ||
| 145 | { | ||
| 146 | unsigned long ret; | ||
| 147 | |||
| 148 | if (ctrl->entries <= 0) { | ||
| 149 | pr_warning("unwind: Corrupt unwind table\n"); | ||
| 150 | return 0; | ||
| 151 | } | ||
| 152 | |||
| 153 | ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; | ||
| 154 | |||
| 155 | if (ctrl->byte == 0) { | ||
| 156 | ctrl->insn++; | ||
| 157 | ctrl->entries--; | ||
| 158 | ctrl->byte = 3; | ||
| 159 | } else | ||
| 160 | ctrl->byte--; | ||
| 161 | |||
| 162 | return ret; | ||
| 163 | } | ||
| 164 | |||
| 165 | /* | ||
| 166 | * Execute the current unwind instruction. | ||
| 167 | */ | ||
| 168 | static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) | ||
| 169 | { | ||
| 170 | unsigned long insn = unwind_get_byte(ctrl); | ||
| 171 | |||
| 172 | pr_debug("%s: insn = %08lx\n", __func__, insn); | ||
| 173 | |||
| 174 | if ((insn & 0xc0) == 0x00) | ||
| 175 | ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; | ||
| 176 | else if ((insn & 0xc0) == 0x40) | ||
| 177 | ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; | ||
| 178 | else if ((insn & 0xf0) == 0x80) { | ||
| 179 | unsigned long mask; | ||
| 180 | unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; | ||
| 181 | int load_sp, reg = 4; | ||
| 182 | |||
| 183 | insn = (insn << 8) | unwind_get_byte(ctrl); | ||
| 184 | mask = insn & 0x0fff; | ||
| 185 | if (mask == 0) { | ||
| 186 | pr_warning("unwind: 'Refuse to unwind' instruction %04lx\n", | ||
| 187 | insn); | ||
| 188 | return -URC_FAILURE; | ||
| 189 | } | ||
| 190 | |||
| 191 | /* pop R4-R15 according to mask */ | ||
| 192 | load_sp = mask & (1 << (13 - 4)); | ||
| 193 | while (mask) { | ||
| 194 | if (mask & 1) | ||
| 195 | ctrl->vrs[reg] = *vsp++; | ||
| 196 | mask >>= 1; | ||
| 197 | reg++; | ||
| 198 | } | ||
| 199 | if (!load_sp) | ||
| 200 | ctrl->vrs[SP] = (unsigned long)vsp; | ||
| 201 | } else if ((insn & 0xf0) == 0x90 && | ||
| 202 | (insn & 0x0d) != 0x0d) | ||
| 203 | ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; | ||
| 204 | else if ((insn & 0xf0) == 0xa0) { | ||
| 205 | unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; | ||
| 206 | int reg; | ||
| 207 | |||
| 208 | /* pop R4-R[4+bbb] */ | ||
| 209 | for (reg = 4; reg <= 4 + (insn & 7); reg++) | ||
| 210 | ctrl->vrs[reg] = *vsp++; | ||
| 211 | if (insn & 0x80) | ||
| 212 | ctrl->vrs[14] = *vsp++; | ||
| 213 | ctrl->vrs[SP] = (unsigned long)vsp; | ||
| 214 | } else if (insn == 0xb0) { | ||
| 215 | ctrl->vrs[PC] = ctrl->vrs[LR]; | ||
| 216 | /* no further processing */ | ||
| 217 | ctrl->entries = 0; | ||
| 218 | } else if (insn == 0xb1) { | ||
| 219 | unsigned long mask = unwind_get_byte(ctrl); | ||
| 220 | unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; | ||
| 221 | int reg = 0; | ||
| 222 | |||
| 223 | if (mask == 0 || mask & 0xf0) { | ||
| 224 | pr_warning("unwind: Spare encoding %04lx\n", | ||
| 225 | (insn << 8) | mask); | ||
| 226 | return -URC_FAILURE; | ||
| 227 | } | ||
| 228 | |||
| 229 | /* pop R0-R3 according to mask */ | ||
| 230 | while (mask) { | ||
| 231 | if (mask & 1) | ||
| 232 | ctrl->vrs[reg] = *vsp++; | ||
| 233 | mask >>= 1; | ||
| 234 | reg++; | ||
| 235 | } | ||
| 236 | ctrl->vrs[SP] = (unsigned long)vsp; | ||
| 237 | } else if (insn == 0xb2) { | ||
| 238 | unsigned long uleb128 = unwind_get_byte(ctrl); | ||
| 239 | |||
| 240 | ctrl->vrs[SP] += 0x204 + (uleb128 << 2); | ||
| 241 | } else { | ||
| 242 | pr_warning("unwind: Unhandled instruction %02lx\n", insn); | ||
| 243 | return -URC_FAILURE; | ||
| 244 | } | ||
| 245 | |||
| 246 | pr_debug("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx\n", __func__, | ||
| 247 | ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); | ||
| 248 | |||
| 249 | return URC_OK; | ||
| 250 | } | ||
| 251 | |||
| 252 | /* | ||
| 253 | * Unwind a single frame starting with *sp for the symbol at *pc. It | ||
| 254 | * updates the *pc and *sp with the new values. | ||
| 255 | */ | ||
| 256 | int unwind_frame(struct stackframe *frame) | ||
| 257 | { | ||
| 258 | unsigned long high, low; | ||
| 259 | struct unwind_idx *idx; | ||
| 260 | struct unwind_ctrl_block ctrl; | ||
| 261 | |||
| 262 | /* only go to a higher address on the stack */ | ||
| 263 | low = frame->sp; | ||
| 264 | high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE; | ||
| 265 | |||
| 266 | pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__, | ||
| 267 | frame->pc, frame->lr, frame->sp); | ||
| 268 | |||
| 269 | if (!kernel_text_address(frame->pc)) | ||
| 270 | return -URC_FAILURE; | ||
| 271 | |||
| 272 | idx = unwind_find_idx(frame->pc); | ||
| 273 | if (!idx) { | ||
| 274 | pr_warning("unwind: Index not found %08lx\n", frame->pc); | ||
| 275 | return -URC_FAILURE; | ||
| 276 | } | ||
| 277 | |||
| 278 | ctrl.vrs[FP] = frame->fp; | ||
| 279 | ctrl.vrs[SP] = frame->sp; | ||
| 280 | ctrl.vrs[LR] = frame->lr; | ||
| 281 | ctrl.vrs[PC] = 0; | ||
| 282 | |||
| 283 | if (idx->insn == 1) | ||
| 284 | /* can't unwind */ | ||
| 285 | return -URC_FAILURE; | ||
| 286 | else if ((idx->insn & 0x80000000) == 0) | ||
| 287 | /* prel31 to the unwind table */ | ||
| 288 | ctrl.insn = (unsigned long *)prel31_to_addr(&idx->insn); | ||
| 289 | else if ((idx->insn & 0xff000000) == 0x80000000) | ||
| 290 | /* only personality routine 0 supported in the index */ | ||
| 291 | ctrl.insn = &idx->insn; | ||
| 292 | else { | ||
| 293 | pr_warning("unwind: Unsupported personality routine %08lx in the index at %p\n", | ||
| 294 | idx->insn, idx); | ||
| 295 | return -URC_FAILURE; | ||
| 296 | } | ||
| 297 | |||
| 298 | /* check the personality routine */ | ||
| 299 | if ((*ctrl.insn & 0xff000000) == 0x80000000) { | ||
| 300 | ctrl.byte = 2; | ||
| 301 | ctrl.entries = 1; | ||
| 302 | } else if ((*ctrl.insn & 0xff000000) == 0x81000000) { | ||
| 303 | ctrl.byte = 1; | ||
| 304 | ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16); | ||
| 305 | } else { | ||
| 306 | pr_warning("unwind: Unsupported personality routine %08lx at %p\n", | ||
| 307 | *ctrl.insn, ctrl.insn); | ||
| 308 | return -URC_FAILURE; | ||
| 309 | } | ||
| 310 | |||
| 311 | while (ctrl.entries > 0) { | ||
| 312 | int urc; | ||
| 313 | |||
| 314 | if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) | ||
| 315 | return -URC_FAILURE; | ||
| 316 | urc = unwind_exec_insn(&ctrl); | ||
| 317 | if (urc < 0) | ||
| 318 | return urc; | ||
| 319 | } | ||
| 320 | |||
| 321 | if (ctrl.vrs[PC] == 0) | ||
| 322 | ctrl.vrs[PC] = ctrl.vrs[LR]; | ||
| 323 | |||
| 324 | frame->fp = ctrl.vrs[FP]; | ||
| 325 | frame->sp = ctrl.vrs[SP]; | ||
| 326 | frame->lr = ctrl.vrs[LR]; | ||
| 327 | frame->pc = ctrl.vrs[PC]; | ||
| 328 | |||
| 329 | return URC_OK; | ||
| 330 | } | ||
| 331 | |||
| 332 | void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) | ||
| 333 | { | ||
| 334 | struct stackframe frame; | ||
| 335 | unsigned long high, low; | ||
| 336 | register unsigned long current_sp asm ("sp"); | ||
| 337 | |||
| 338 | pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); | ||
| 339 | |||
| 340 | if (!tsk) | ||
| 341 | tsk = current; | ||
| 342 | |||
| 343 | if (regs) { | ||
| 344 | frame.fp = regs->ARM_fp; | ||
| 345 | frame.sp = regs->ARM_sp; | ||
| 346 | frame.lr = regs->ARM_lr; | ||
| 347 | frame.pc = regs->ARM_pc; | ||
| 348 | } else if (tsk == current) { | ||
| 349 | frame.fp = (unsigned long)__builtin_frame_address(0); | ||
| 350 | frame.sp = current_sp; | ||
| 351 | frame.lr = (unsigned long)__builtin_return_address(0); | ||
| 352 | frame.pc = (unsigned long)unwind_backtrace; | ||
| 353 | } else { | ||
| 354 | /* task blocked in __switch_to */ | ||
| 355 | frame.fp = thread_saved_fp(tsk); | ||
| 356 | frame.sp = thread_saved_sp(tsk); | ||
| 357 | /* | ||
| 358 | * The function calling __switch_to cannot be a leaf function | ||
| 359 | * so LR is recovered from the stack. | ||
| 360 | */ | ||
| 361 | frame.lr = 0; | ||
| 362 | frame.pc = thread_saved_pc(tsk); | ||
| 363 | } | ||
| 364 | |||
| 365 | low = frame.sp & ~(THREAD_SIZE - 1); | ||
| 366 | high = low + THREAD_SIZE; | ||
| 367 | |||
| 368 | while (1) { | ||
| 369 | int urc; | ||
| 370 | unsigned long where = frame.pc; | ||
| 371 | |||
| 372 | urc = unwind_frame(&frame); | ||
| 373 | if (urc < 0) | ||
| 374 | break; | ||
| 375 | dump_backtrace_entry(where, frame.pc, frame.sp - 4); | ||
| 376 | } | ||
| 377 | } | ||
| 378 | |||
| 379 | struct unwind_table *unwind_table_add(unsigned long start, unsigned long size, | ||
| 380 | unsigned long text_addr, | ||
| 381 | unsigned long text_size) | ||
| 382 | { | ||
| 383 | unsigned long flags; | ||
| 384 | struct unwind_idx *idx; | ||
| 385 | struct unwind_table *tab = kmalloc(sizeof(*tab), GFP_KERNEL); | ||
| 386 | |||
| 387 | pr_debug("%s(%08lx, %08lx, %08lx, %08lx)\n", __func__, start, size, | ||
| 388 | text_addr, text_size); | ||
| 389 | |||
| 390 | if (!tab) | ||
| 391 | return tab; | ||
| 392 | |||
| 393 | tab->start = (struct unwind_idx *)start; | ||
| 394 | tab->stop = (struct unwind_idx *)(start + size); | ||
| 395 | tab->begin_addr = text_addr; | ||
| 396 | tab->end_addr = text_addr + text_size; | ||
| 397 | |||
| 398 | /* Convert the symbol addresses to absolute values */ | ||
| 399 | for (idx = tab->start; idx < tab->stop; idx++) | ||
| 400 | idx->addr = prel31_to_addr(&idx->addr); | ||
| 401 | |||
| 402 | spin_lock_irqsave(&unwind_lock, flags); | ||
| 403 | list_add_tail(&tab->list, &unwind_tables); | ||
| 404 | spin_unlock_irqrestore(&unwind_lock, flags); | ||
| 405 | |||
| 406 | return tab; | ||
| 407 | } | ||
| 408 | |||
| 409 | void unwind_table_del(struct unwind_table *tab) | ||
| 410 | { | ||
| 411 | unsigned long flags; | ||
| 412 | |||
| 413 | if (!tab) | ||
| 414 | return; | ||
| 415 | |||
| 416 | spin_lock_irqsave(&unwind_lock, flags); | ||
| 417 | list_del(&tab->list); | ||
| 418 | spin_unlock_irqrestore(&unwind_lock, flags); | ||
| 419 | |||
| 420 | kfree(tab); | ||
| 421 | } | ||
| 422 | |||
| 423 | int __init unwind_init(void) | ||
| 424 | { | ||
| 425 | struct unwind_idx *idx; | ||
| 426 | |||
| 427 | /* Convert the symbol addresses to absolute values */ | ||
| 428 | for (idx = __start_unwind_idx; idx < __stop_unwind_idx; idx++) | ||
| 429 | idx->addr = prel31_to_addr(&idx->addr); | ||
| 430 | |||
| 431 | pr_debug("unwind: ARM stack unwinding initialised\n"); | ||
| 432 | |||
| 433 | return 0; | ||
| 434 | } | ||
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 1602373e539c..c90f27250ead 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S | |||
| @@ -82,6 +82,8 @@ SECTIONS | |||
| 82 | EXIT_TEXT | 82 | EXIT_TEXT |
| 83 | EXIT_DATA | 83 | EXIT_DATA |
| 84 | *(.exitcall.exit) | 84 | *(.exitcall.exit) |
| 85 | *(.ARM.exidx.exit.text) | ||
| 86 | *(.ARM.extab.exit.text) | ||
| 85 | #ifndef CONFIG_MMU | 87 | #ifndef CONFIG_MMU |
| 86 | *(.fixup) | 88 | *(.fixup) |
| 87 | *(__ex_table) | 89 | *(__ex_table) |
| @@ -112,6 +114,23 @@ SECTIONS | |||
| 112 | 114 | ||
| 113 | _etext = .; /* End of text and rodata section */ | 115 | _etext = .; /* End of text and rodata section */ |
| 114 | 116 | ||
| 117 | #ifdef CONFIG_ARM_UNWIND | ||
| 118 | /* | ||
| 119 | * Stack unwinding tables | ||
| 120 | */ | ||
| 121 | . = ALIGN(8); | ||
| 122 | .ARM.unwind_idx : { | ||
| 123 | __start_unwind_idx = .; | ||
| 124 | *(.ARM.exidx*) | ||
| 125 | __stop_unwind_idx = .; | ||
| 126 | } | ||
| 127 | .ARM.unwind_tab : { | ||
| 128 | __start_unwind_tab = .; | ||
| 129 | *(.ARM.extab*) | ||
| 130 | __stop_unwind_tab = .; | ||
| 131 | } | ||
| 132 | #endif | ||
| 133 | |||
| 115 | #ifdef CONFIG_XIP_KERNEL | 134 | #ifdef CONFIG_XIP_KERNEL |
| 116 | __data_loc = ALIGN(4); /* location in binary */ | 135 | __data_loc = ALIGN(4); /* location in binary */ |
| 117 | . = PAGE_OFFSET + TEXT_OFFSET; | 136 | . = PAGE_OFFSET + TEXT_OFFSET; |
diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h index 8f4115d734ce..fe08ca1add6f 100644 --- a/arch/arm/mach-aaec2000/include/mach/system.h +++ b/arch/arm/mach-aaec2000/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static inline void arch_idle(void) | |||
| 16 | cpu_do_idle(); | 16 | cpu_do_idle(); |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static inline void arch_reset(char mode) | 19 | static inline void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | cpu_reset(0); | 21 | cpu_reset(0); |
| 22 | } | 22 | } |
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 81439fe6fb3d..438efbb17482 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c | |||
| @@ -238,6 +238,10 @@ static void __init ek_board_init(void) | |||
| 238 | at91_add_device_i2c(NULL, 0); | 238 | at91_add_device_i2c(NULL, 0); |
| 239 | /* LEDs */ | 239 | /* LEDs */ |
| 240 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | 240 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); |
| 241 | /* PCK0 provides MCLK to the WM8731 */ | ||
| 242 | at91_set_B_periph(AT91_PIN_PC1, 0); | ||
| 243 | /* SSC (for WM8731) */ | ||
| 244 | at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); | ||
| 241 | } | 245 | } |
| 242 | 246 | ||
| 243 | MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") | 247 | MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 7b9ce7a336b0..b5daf7f5e011 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
| @@ -47,9 +47,6 @@ extern void at91_irq_resume(void); | |||
| 47 | #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ | 47 | #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ |
| 48 | 48 | ||
| 49 | struct at91_gpio_bank { | 49 | struct at91_gpio_bank { |
| 50 | unsigned chipbase; /* bank's first GPIO number */ | ||
| 51 | void __iomem *regbase; /* base of register bank */ | ||
| 52 | struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */ | ||
| 53 | unsigned short id; /* peripheral ID */ | 50 | unsigned short id; /* peripheral ID */ |
| 54 | unsigned long offset; /* offset from system peripheral base */ | 51 | unsigned long offset; /* offset from system peripheral base */ |
| 55 | struct clk *clock; /* associated clock */ | 52 | struct clk *clock; /* associated clock */ |
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index 2f7d4977dce9..f2236f0e101f 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
| @@ -24,19 +24,59 @@ | |||
| 24 | #include <mach/at91_pio.h> | 24 | #include <mach/at91_pio.h> |
| 25 | #include <mach/gpio.h> | 25 | #include <mach/gpio.h> |
| 26 | 26 | ||
| 27 | #include <asm/gpio.h> | ||
| 28 | |||
| 27 | #include "generic.h" | 29 | #include "generic.h" |
| 28 | 30 | ||
| 31 | struct at91_gpio_chip { | ||
| 32 | struct gpio_chip chip; | ||
| 33 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | ||
| 34 | struct at91_gpio_bank *bank; /* Bank definition */ | ||
| 35 | void __iomem *regbase; /* Base of register bank */ | ||
| 36 | }; | ||
| 29 | 37 | ||
| 30 | static struct at91_gpio_bank *gpio; | 38 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) |
| 31 | static int gpio_banks; | 39 | |
| 40 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); | ||
| 41 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); | ||
| 42 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); | ||
| 43 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | ||
| 44 | unsigned offset, int val); | ||
| 45 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | ||
| 46 | unsigned offset); | ||
| 47 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset); | ||
| 48 | |||
| 49 | #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ | ||
| 50 | { \ | ||
| 51 | .chip = { \ | ||
| 52 | .label = name, \ | ||
| 53 | .request = at91_gpiolib_request, \ | ||
| 54 | .direction_input = at91_gpiolib_direction_input, \ | ||
| 55 | .direction_output = at91_gpiolib_direction_output, \ | ||
| 56 | .get = at91_gpiolib_get, \ | ||
| 57 | .set = at91_gpiolib_set, \ | ||
| 58 | .dbg_show = at91_gpiolib_dbg_show, \ | ||
| 59 | .base = base_gpio, \ | ||
| 60 | .ngpio = nr_gpio, \ | ||
| 61 | }, \ | ||
| 62 | } | ||
| 63 | |||
| 64 | static struct at91_gpio_chip gpio_chip[] = { | ||
| 65 | AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32), | ||
| 66 | AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32), | ||
| 67 | AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32), | ||
| 68 | AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32), | ||
| 69 | AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32), | ||
| 70 | }; | ||
| 32 | 71 | ||
| 72 | static int gpio_banks; | ||
| 33 | 73 | ||
| 34 | static inline void __iomem *pin_to_controller(unsigned pin) | 74 | static inline void __iomem *pin_to_controller(unsigned pin) |
| 35 | { | 75 | { |
| 36 | pin -= PIN_BASE; | 76 | pin -= PIN_BASE; |
| 37 | pin /= 32; | 77 | pin /= 32; |
| 38 | if (likely(pin < gpio_banks)) | 78 | if (likely(pin < gpio_banks)) |
| 39 | return gpio[pin].regbase; | 79 | return gpio_chip[pin].regbase; |
| 40 | 80 | ||
| 41 | return NULL; | 81 | return NULL; |
| 42 | } | 82 | } |
| @@ -197,39 +237,6 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) | |||
| 197 | } | 237 | } |
| 198 | EXPORT_SYMBOL(at91_set_multi_drive); | 238 | EXPORT_SYMBOL(at91_set_multi_drive); |
| 199 | 239 | ||
| 200 | /*--------------------------------------------------------------------------*/ | ||
| 201 | |||
| 202 | /* new-style GPIO calls; these expect at91_set_GPIO_periph to have been | ||
| 203 | * called, and maybe at91_set_multi_drive() for putout pins. | ||
| 204 | */ | ||
| 205 | |||
| 206 | int gpio_direction_input(unsigned pin) | ||
| 207 | { | ||
| 208 | void __iomem *pio = pin_to_controller(pin); | ||
| 209 | unsigned mask = pin_to_mask(pin); | ||
| 210 | |||
| 211 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) | ||
| 212 | return -EINVAL; | ||
| 213 | __raw_writel(mask, pio + PIO_ODR); | ||
| 214 | return 0; | ||
| 215 | } | ||
| 216 | EXPORT_SYMBOL(gpio_direction_input); | ||
| 217 | |||
| 218 | int gpio_direction_output(unsigned pin, int value) | ||
| 219 | { | ||
| 220 | void __iomem *pio = pin_to_controller(pin); | ||
| 221 | unsigned mask = pin_to_mask(pin); | ||
| 222 | |||
| 223 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) | ||
| 224 | return -EINVAL; | ||
| 225 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | ||
| 226 | __raw_writel(mask, pio + PIO_OER); | ||
| 227 | return 0; | ||
| 228 | } | ||
| 229 | EXPORT_SYMBOL(gpio_direction_output); | ||
| 230 | |||
| 231 | /*--------------------------------------------------------------------------*/ | ||
| 232 | |||
| 233 | /* | 240 | /* |
| 234 | * assuming the pin is muxed as a gpio output, set its value. | 241 | * assuming the pin is muxed as a gpio output, set its value. |
| 235 | */ | 242 | */ |
| @@ -282,7 +289,7 @@ static int gpio_irq_set_wake(unsigned pin, unsigned state) | |||
| 282 | else | 289 | else |
| 283 | wakeups[bank] &= ~mask; | 290 | wakeups[bank] &= ~mask; |
| 284 | 291 | ||
| 285 | set_irq_wake(gpio[bank].id, state); | 292 | set_irq_wake(gpio_chip[bank].bank->id, state); |
| 286 | 293 | ||
| 287 | return 0; | 294 | return 0; |
| 288 | } | 295 | } |
| @@ -292,14 +299,14 @@ void at91_gpio_suspend(void) | |||
| 292 | int i; | 299 | int i; |
| 293 | 300 | ||
| 294 | for (i = 0; i < gpio_banks; i++) { | 301 | for (i = 0; i < gpio_banks; i++) { |
| 295 | void __iomem *pio = gpio[i].regbase; | 302 | void __iomem *pio = gpio_chip[i].regbase; |
| 296 | 303 | ||
| 297 | backups[i] = __raw_readl(pio + PIO_IMR); | 304 | backups[i] = __raw_readl(pio + PIO_IMR); |
| 298 | __raw_writel(backups[i], pio + PIO_IDR); | 305 | __raw_writel(backups[i], pio + PIO_IDR); |
| 299 | __raw_writel(wakeups[i], pio + PIO_IER); | 306 | __raw_writel(wakeups[i], pio + PIO_IER); |
| 300 | 307 | ||
| 301 | if (!wakeups[i]) | 308 | if (!wakeups[i]) |
| 302 | clk_disable(gpio[i].clock); | 309 | clk_disable(gpio_chip[i].bank->clock); |
| 303 | else { | 310 | else { |
| 304 | #ifdef CONFIG_PM_DEBUG | 311 | #ifdef CONFIG_PM_DEBUG |
| 305 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); | 312 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); |
| @@ -313,10 +320,10 @@ void at91_gpio_resume(void) | |||
| 313 | int i; | 320 | int i; |
| 314 | 321 | ||
| 315 | for (i = 0; i < gpio_banks; i++) { | 322 | for (i = 0; i < gpio_banks; i++) { |
| 316 | void __iomem *pio = gpio[i].regbase; | 323 | void __iomem *pio = gpio_chip[i].regbase; |
| 317 | 324 | ||
| 318 | if (!wakeups[i]) | 325 | if (!wakeups[i]) |
| 319 | clk_enable(gpio[i].clock); | 326 | clk_enable(gpio_chip[i].bank->clock); |
| 320 | 327 | ||
| 321 | __raw_writel(wakeups[i], pio + PIO_IDR); | 328 | __raw_writel(wakeups[i], pio + PIO_IDR); |
| 322 | __raw_writel(backups[i], pio + PIO_IER); | 329 | __raw_writel(backups[i], pio + PIO_IER); |
| @@ -380,12 +387,12 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
| 380 | { | 387 | { |
| 381 | unsigned pin; | 388 | unsigned pin; |
| 382 | struct irq_desc *gpio; | 389 | struct irq_desc *gpio; |
| 383 | struct at91_gpio_bank *bank; | 390 | struct at91_gpio_chip *at91_gpio; |
| 384 | void __iomem *pio; | 391 | void __iomem *pio; |
| 385 | u32 isr; | 392 | u32 isr; |
| 386 | 393 | ||
| 387 | bank = get_irq_chip_data(irq); | 394 | at91_gpio = get_irq_chip_data(irq); |
| 388 | pio = bank->regbase; | 395 | pio = at91_gpio->regbase; |
| 389 | 396 | ||
| 390 | /* temporarily mask (level sensitive) parent IRQ */ | 397 | /* temporarily mask (level sensitive) parent IRQ */ |
| 391 | desc->chip->ack(irq); | 398 | desc->chip->ack(irq); |
| @@ -396,14 +403,14 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
| 396 | */ | 403 | */ |
| 397 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); | 404 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); |
| 398 | if (!isr) { | 405 | if (!isr) { |
| 399 | if (!bank->next) | 406 | if (!at91_gpio->next) |
| 400 | break; | 407 | break; |
| 401 | bank = bank->next; | 408 | at91_gpio = at91_gpio->next; |
| 402 | pio = bank->regbase; | 409 | pio = at91_gpio->regbase; |
| 403 | continue; | 410 | continue; |
| 404 | } | 411 | } |
| 405 | 412 | ||
| 406 | pin = bank->chipbase; | 413 | pin = at91_gpio->chip.base; |
| 407 | gpio = &irq_desc[pin]; | 414 | gpio = &irq_desc[pin]; |
| 408 | 415 | ||
| 409 | while (isr) { | 416 | while (isr) { |
| @@ -502,17 +509,17 @@ static struct lock_class_key gpio_lock_class; | |||
| 502 | void __init at91_gpio_irq_setup(void) | 509 | void __init at91_gpio_irq_setup(void) |
| 503 | { | 510 | { |
| 504 | unsigned pioc, pin; | 511 | unsigned pioc, pin; |
| 505 | struct at91_gpio_bank *this, *prev; | 512 | struct at91_gpio_chip *this, *prev; |
| 506 | 513 | ||
| 507 | for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL; | 514 | for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL; |
| 508 | pioc++ < gpio_banks; | 515 | pioc++ < gpio_banks; |
| 509 | prev = this, this++) { | 516 | prev = this, this++) { |
| 510 | unsigned id = this->id; | 517 | unsigned id = this->bank->id; |
| 511 | unsigned i; | 518 | unsigned i; |
| 512 | 519 | ||
| 513 | __raw_writel(~0, this->regbase + PIO_IDR); | 520 | __raw_writel(~0, this->regbase + PIO_IDR); |
| 514 | 521 | ||
| 515 | for (i = 0, pin = this->chipbase; i < 32; i++, pin++) { | 522 | for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { |
| 516 | lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); | 523 | lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); |
| 517 | 524 | ||
| 518 | /* | 525 | /* |
| @@ -537,32 +544,117 @@ void __init at91_gpio_irq_setup(void) | |||
| 537 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); | 544 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); |
| 538 | } | 545 | } |
| 539 | 546 | ||
| 547 | /* gpiolib support */ | ||
| 548 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | ||
| 549 | unsigned offset) | ||
| 550 | { | ||
| 551 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 552 | void __iomem *pio = at91_gpio->regbase; | ||
| 553 | unsigned mask = 1 << offset; | ||
| 554 | |||
| 555 | __raw_writel(mask, pio + PIO_ODR); | ||
| 556 | return 0; | ||
| 557 | } | ||
| 558 | |||
| 559 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | ||
| 560 | unsigned offset, int val) | ||
| 561 | { | ||
| 562 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 563 | void __iomem *pio = at91_gpio->regbase; | ||
| 564 | unsigned mask = 1 << offset; | ||
| 565 | |||
| 566 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | ||
| 567 | __raw_writel(mask, pio + PIO_OER); | ||
| 568 | return 0; | ||
| 569 | } | ||
| 570 | |||
| 571 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset) | ||
| 572 | { | ||
| 573 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 574 | void __iomem *pio = at91_gpio->regbase; | ||
| 575 | unsigned mask = 1 << offset; | ||
| 576 | u32 pdsr; | ||
| 577 | |||
| 578 | pdsr = __raw_readl(pio + PIO_PDSR); | ||
| 579 | return (pdsr & mask) != 0; | ||
| 580 | } | ||
| 581 | |||
| 582 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) | ||
| 583 | { | ||
| 584 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 585 | void __iomem *pio = at91_gpio->regbase; | ||
| 586 | unsigned mask = 1 << offset; | ||
| 587 | |||
| 588 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | ||
| 589 | } | ||
| 590 | |||
| 591 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset) | ||
| 592 | { | ||
| 593 | unsigned pin = chip->base + offset; | ||
| 594 | void __iomem *pio = pin_to_controller(pin); | ||
| 595 | unsigned mask = pin_to_mask(pin); | ||
| 596 | |||
| 597 | /* Cannot request GPIOs that are in alternate function mode */ | ||
| 598 | if (!(__raw_readl(pio + PIO_PSR) & mask)) | ||
| 599 | return -EPERM; | ||
| 600 | |||
| 601 | return 0; | ||
| 602 | } | ||
| 603 | |||
| 604 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) | ||
| 605 | { | ||
| 606 | int i; | ||
| 607 | |||
| 608 | for (i = 0; i < chip->ngpio; i++) { | ||
| 609 | unsigned pin = chip->base + i; | ||
| 610 | void __iomem *pio = pin_to_controller(pin); | ||
| 611 | unsigned mask = pin_to_mask(pin); | ||
| 612 | const char *gpio_label; | ||
| 613 | |||
| 614 | gpio_label = gpiochip_is_requested(chip, i); | ||
| 615 | if (gpio_label) { | ||
| 616 | seq_printf(s, "[%s] GPIO%s%d: ", | ||
| 617 | gpio_label, chip->label, i); | ||
| 618 | if (__raw_readl(pio + PIO_PSR) & mask) | ||
| 619 | seq_printf(s, "[gpio] %s\n", | ||
| 620 | at91_get_gpio_value(pin) ? | ||
| 621 | "set" : "clear"); | ||
| 622 | else | ||
| 623 | seq_printf(s, "[periph %s]\n", | ||
| 624 | __raw_readl(pio + PIO_ABSR) & | ||
| 625 | mask ? "B" : "A"); | ||
| 626 | } | ||
| 627 | } | ||
| 628 | } | ||
| 629 | |||
| 540 | /* | 630 | /* |
| 541 | * Called from the processor-specific init to enable GPIO pin support. | 631 | * Called from the processor-specific init to enable GPIO pin support. |
| 542 | */ | 632 | */ |
| 543 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) | 633 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) |
| 544 | { | 634 | { |
| 545 | unsigned i; | 635 | unsigned i; |
| 546 | struct at91_gpio_bank *last; | 636 | struct at91_gpio_chip *at91_gpio, *last = NULL; |
| 547 | 637 | ||
| 548 | BUG_ON(nr_banks > MAX_GPIO_BANKS); | 638 | BUG_ON(nr_banks > MAX_GPIO_BANKS); |
| 549 | 639 | ||
| 550 | gpio = data; | ||
| 551 | gpio_banks = nr_banks; | 640 | gpio_banks = nr_banks; |
| 552 | 641 | ||
| 553 | for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) { | 642 | for (i = 0; i < nr_banks; i++) { |
| 554 | data->chipbase = PIN_BASE + i * 32; | 643 | at91_gpio = &gpio_chip[i]; |
| 555 | data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS; | 644 | |
| 645 | at91_gpio->bank = &data[i]; | ||
| 646 | at91_gpio->chip.base = PIN_BASE + i * 32; | ||
| 647 | at91_gpio->regbase = at91_gpio->bank->offset + | ||
| 648 | (void __iomem *)AT91_VA_BASE_SYS; | ||
| 556 | 649 | ||
| 557 | /* enable PIO controller's clock */ | 650 | /* enable PIO controller's clock */ |
| 558 | clk_enable(data->clock); | 651 | clk_enable(at91_gpio->bank->clock); |
| 559 | 652 | ||
| 560 | /* | 653 | /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ |
| 561 | * Some processors share peripheral ID between multiple GPIO banks. | 654 | if (last && last->bank->id == at91_gpio->bank->id) |
| 562 | * SAM9263 (PIOC, PIOD, PIOE) | 655 | last->next = at91_gpio; |
| 563 | * CAP9 (PIOA, PIOB, PIOC, PIOD) | 656 | last = at91_gpio; |
| 564 | */ | 657 | |
| 565 | if (last && last->id == data->id) | 658 | gpiochip_add(&at91_gpio->chip); |
| 566 | last->next = data; | ||
| 567 | } | 659 | } |
| 568 | } | 660 | } |
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index bffa6741a751..04c91e31c9c5 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h | |||
| @@ -213,32 +213,12 @@ extern void at91_gpio_resume(void); | |||
| 213 | */ | 213 | */ |
| 214 | 214 | ||
| 215 | #include <asm/errno.h> | 215 | #include <asm/errno.h> |
| 216 | |||
| 217 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 218 | { | ||
| 219 | return 0; | ||
| 220 | } | ||
| 221 | |||
| 222 | static inline void gpio_free(unsigned gpio) | ||
| 223 | { | ||
| 224 | might_sleep(); | ||
| 225 | } | ||
| 226 | |||
| 227 | extern int gpio_direction_input(unsigned gpio); | ||
| 228 | extern int gpio_direction_output(unsigned gpio, int value); | ||
| 229 | |||
| 230 | static inline int gpio_get_value(unsigned gpio) | ||
| 231 | { | ||
| 232 | return at91_get_gpio_value(gpio); | ||
| 233 | } | ||
| 234 | |||
| 235 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 236 | { | ||
| 237 | at91_set_gpio_value(gpio, value); | ||
| 238 | } | ||
| 239 | |||
| 240 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 216 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
| 241 | 217 | ||
| 218 | #define gpio_get_value __gpio_get_value | ||
| 219 | #define gpio_set_value __gpio_set_value | ||
| 220 | #define gpio_cansleep __gpio_cansleep | ||
| 221 | |||
| 242 | static inline int gpio_to_irq(unsigned gpio) | 222 | static inline int gpio_to_irq(unsigned gpio) |
| 243 | { | 223 | { |
| 244 | return gpio; | 224 | return gpio; |
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h index e712658d966c..5268af3933c2 100644 --- a/arch/arm/mach-at91/include/mach/system.h +++ b/arch/arm/mach-at91/include/mach/system.h | |||
| @@ -43,7 +43,7 @@ static inline void arch_idle(void) | |||
| 43 | 43 | ||
| 44 | void (*at91_arch_reset)(void); | 44 | void (*at91_arch_reset)(void); |
| 45 | 45 | ||
| 46 | static inline void arch_reset(char mode) | 46 | static inline void arch_reset(char mode, const char *cmd) |
| 47 | { | 47 | { |
| 48 | /* call the CPU-specific reset function */ | 48 | /* call the CPU-specific reset function */ |
| 49 | if (at91_arch_reset) | 49 | if (at91_arch_reset) |
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h index 24e96159e3e7..f916cd7a477d 100644 --- a/arch/arm/mach-clps711x/include/mach/system.h +++ b/arch/arm/mach-clps711x/include/mach/system.h | |||
| @@ -32,7 +32,7 @@ static inline void arch_idle(void) | |||
| 32 | mov r0, r0"); | 32 | mov r0, r0"); |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | static inline void arch_reset(char mode) | 35 | static inline void arch_reset(char mode, const char *cmd) |
| 36 | { | 36 | { |
| 37 | cpu_reset(0); | 37 | cpu_reset(0); |
| 38 | } | 38 | } |
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h index 17ca41dc2c53..b7e7036674fa 100644 --- a/arch/arm/mach-davinci/include/mach/system.h +++ b/arch/arm/mach-davinci/include/mach/system.h | |||
| @@ -21,7 +21,7 @@ static void arch_idle(void) | |||
| 21 | cpu_do_idle(); | 21 | cpu_do_idle(); |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static void arch_reset(char mode) | 24 | static void arch_reset(char mode, const char *cmd) |
| 25 | { | 25 | { |
| 26 | davinci_watchdog_reset(); | 26 | davinci_watchdog_reset(); |
| 27 | } | 27 | } |
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h index 350a028997ef..9a26245bf1fc 100644 --- a/arch/arm/mach-ebsa110/include/mach/system.h +++ b/arch/arm/mach-ebsa110/include/mach/system.h | |||
| @@ -34,6 +34,6 @@ static inline void arch_idle(void) | |||
| 34 | asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); | 34 | asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | #define arch_reset(mode) cpu_reset(0x80000000) | 37 | #define arch_reset(mode, cmd) cpu_reset(0x80000000) |
| 38 | 38 | ||
| 39 | #endif | 39 | #endif |
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 944e42d51646..9522e205b73f 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Makefile for the linux kernel. | 2 | # Makefile for the linux kernel. |
| 3 | # | 3 | # |
| 4 | obj-y := core.o clock.o gpio.o | 4 | obj-y := core.o clock.o dma-m2p.o gpio.o |
| 5 | obj-m := | 5 | obj-m := |
| 6 | obj-n := | 6 | obj-n := |
| 7 | obj- := | 7 | obj- := |
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 96049283a10a..e8ebeaea6c48 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
| @@ -41,6 +41,56 @@ static struct clk clk_usb_host = { | |||
| 41 | .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, | 41 | .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | /* DMA Clocks */ | ||
| 45 | static struct clk clk_m2p0 = { | ||
| 46 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 47 | .enable_mask = 0x00020000, | ||
| 48 | }; | ||
| 49 | static struct clk clk_m2p1 = { | ||
| 50 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 51 | .enable_mask = 0x00010000, | ||
| 52 | }; | ||
| 53 | static struct clk clk_m2p2 = { | ||
| 54 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 55 | .enable_mask = 0x00080000, | ||
| 56 | }; | ||
| 57 | static struct clk clk_m2p3 = { | ||
| 58 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 59 | .enable_mask = 0x00040000, | ||
| 60 | }; | ||
| 61 | static struct clk clk_m2p4 = { | ||
| 62 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 63 | .enable_mask = 0x00200000, | ||
| 64 | }; | ||
| 65 | static struct clk clk_m2p5 = { | ||
| 66 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 67 | .enable_mask = 0x00100000, | ||
| 68 | }; | ||
| 69 | static struct clk clk_m2p6 = { | ||
| 70 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 71 | .enable_mask = 0x00800000, | ||
| 72 | }; | ||
| 73 | static struct clk clk_m2p7 = { | ||
| 74 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 75 | .enable_mask = 0x00400000, | ||
| 76 | }; | ||
| 77 | static struct clk clk_m2p8 = { | ||
| 78 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 79 | .enable_mask = 0x02000000, | ||
| 80 | }; | ||
| 81 | static struct clk clk_m2p9 = { | ||
| 82 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 83 | .enable_mask = 0x01000000, | ||
| 84 | }; | ||
| 85 | static struct clk clk_m2m0 = { | ||
| 86 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 87 | .enable_mask = 0x04000000, | ||
| 88 | }; | ||
| 89 | static struct clk clk_m2m1 = { | ||
| 90 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 91 | .enable_mask = 0x08000000, | ||
| 92 | }; | ||
| 93 | |||
| 44 | #define INIT_CK(dev,con,ck) \ | 94 | #define INIT_CK(dev,con,ck) \ |
| 45 | { .dev_id = dev, .con_id = con, .clk = ck } | 95 | { .dev_id = dev, .con_id = con, .clk = ck } |
| 46 | 96 | ||
| @@ -54,6 +104,18 @@ static struct clk_lookup clocks[] = { | |||
| 54 | INIT_CK(NULL, "pclk", &clk_p), | 104 | INIT_CK(NULL, "pclk", &clk_p), |
| 55 | INIT_CK(NULL, "pll2", &clk_pll2), | 105 | INIT_CK(NULL, "pll2", &clk_pll2), |
| 56 | INIT_CK(NULL, "usb_host", &clk_usb_host), | 106 | INIT_CK(NULL, "usb_host", &clk_usb_host), |
| 107 | INIT_CK(NULL, "m2p0", &clk_m2p0), | ||
| 108 | INIT_CK(NULL, "m2p1", &clk_m2p1), | ||
| 109 | INIT_CK(NULL, "m2p2", &clk_m2p2), | ||
| 110 | INIT_CK(NULL, "m2p3", &clk_m2p3), | ||
| 111 | INIT_CK(NULL, "m2p4", &clk_m2p4), | ||
| 112 | INIT_CK(NULL, "m2p5", &clk_m2p5), | ||
| 113 | INIT_CK(NULL, "m2p6", &clk_m2p6), | ||
| 114 | INIT_CK(NULL, "m2p7", &clk_m2p7), | ||
| 115 | INIT_CK(NULL, "m2p8", &clk_m2p8), | ||
| 116 | INIT_CK(NULL, "m2p9", &clk_m2p9), | ||
| 117 | INIT_CK(NULL, "m2m0", &clk_m2m0), | ||
| 118 | INIT_CK(NULL, "m2m1", &clk_m2m1), | ||
| 57 | }; | 119 | }; |
| 58 | 120 | ||
| 59 | 121 | ||
| @@ -110,6 +172,22 @@ static unsigned long calc_pll_rate(u32 config_word) | |||
| 110 | return (unsigned long)rate; | 172 | return (unsigned long)rate; |
| 111 | } | 173 | } |
| 112 | 174 | ||
| 175 | static void __init ep93xx_dma_clock_init(void) | ||
| 176 | { | ||
| 177 | clk_m2p0.rate = clk_h.rate; | ||
| 178 | clk_m2p1.rate = clk_h.rate; | ||
| 179 | clk_m2p2.rate = clk_h.rate; | ||
| 180 | clk_m2p3.rate = clk_h.rate; | ||
| 181 | clk_m2p4.rate = clk_h.rate; | ||
| 182 | clk_m2p5.rate = clk_h.rate; | ||
| 183 | clk_m2p6.rate = clk_h.rate; | ||
| 184 | clk_m2p7.rate = clk_h.rate; | ||
| 185 | clk_m2p8.rate = clk_h.rate; | ||
| 186 | clk_m2p9.rate = clk_h.rate; | ||
| 187 | clk_m2m0.rate = clk_h.rate; | ||
| 188 | clk_m2m1.rate = clk_h.rate; | ||
| 189 | } | ||
| 190 | |||
| 113 | static int __init ep93xx_clock_init(void) | 191 | static int __init ep93xx_clock_init(void) |
| 114 | { | 192 | { |
| 115 | u32 value; | 193 | u32 value; |
| @@ -124,6 +202,7 @@ static int __init ep93xx_clock_init(void) | |||
| 124 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; | 202 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; |
| 125 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; | 203 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; |
| 126 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; | 204 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; |
| 205 | ep93xx_dma_clock_init(); | ||
| 127 | 206 | ||
| 128 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); | 207 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); |
| 129 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ | 208 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ |
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c new file mode 100644 index 000000000000..a2df5bb7dff0 --- /dev/null +++ b/arch/arm/mach-ep93xx/dma-m2p.c | |||
| @@ -0,0 +1,408 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ep93xx/dma-m2p.c | ||
| 3 | * M2P DMA handling for Cirrus EP93xx chips. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 6 | * Copyright (C) 2006 Applied Data Systems | ||
| 7 | * | ||
| 8 | * Copyright (C) 2009 Ryan Mallon <ryan@bluewatersys.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or (at | ||
| 13 | * your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | /* | ||
| 17 | * On the EP93xx chip the following peripherals my be allocated to the 10 | ||
| 18 | * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive). | ||
| 19 | * | ||
| 20 | * I2S contains 3 Tx and 3 Rx DMA Channels | ||
| 21 | * AAC contains 3 Tx and 3 Rx DMA Channels | ||
| 22 | * UART1 contains 1 Tx and 1 Rx DMA Channels | ||
| 23 | * UART2 contains 1 Tx and 1 Rx DMA Channels | ||
| 24 | * UART3 contains 1 Tx and 1 Rx DMA Channels | ||
| 25 | * IrDA contains 1 Tx and 1 Rx DMA Channels | ||
| 26 | * | ||
| 27 | * SSP and IDE use the Memory to Memory (M2M) channels and are not covered | ||
| 28 | * with this implementation. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/kernel.h> | ||
| 32 | #include <linux/clk.h> | ||
| 33 | #include <linux/err.h> | ||
| 34 | #include <linux/interrupt.h> | ||
| 35 | #include <linux/module.h> | ||
| 36 | |||
| 37 | #include <mach/dma.h> | ||
| 38 | #include <mach/hardware.h> | ||
| 39 | |||
| 40 | #define M2P_CONTROL 0x00 | ||
| 41 | #define M2P_CONTROL_STALL_IRQ_EN (1 << 0) | ||
| 42 | #define M2P_CONTROL_NFB_IRQ_EN (1 << 1) | ||
| 43 | #define M2P_CONTROL_ERROR_IRQ_EN (1 << 3) | ||
| 44 | #define M2P_CONTROL_ENABLE (1 << 4) | ||
| 45 | #define M2P_INTERRUPT 0x04 | ||
| 46 | #define M2P_INTERRUPT_STALL (1 << 0) | ||
| 47 | #define M2P_INTERRUPT_NFB (1 << 1) | ||
| 48 | #define M2P_INTERRUPT_ERROR (1 << 3) | ||
| 49 | #define M2P_PPALLOC 0x08 | ||
| 50 | #define M2P_STATUS 0x0c | ||
| 51 | #define M2P_REMAIN 0x14 | ||
| 52 | #define M2P_MAXCNT0 0x20 | ||
| 53 | #define M2P_BASE0 0x24 | ||
| 54 | #define M2P_MAXCNT1 0x30 | ||
| 55 | #define M2P_BASE1 0x34 | ||
| 56 | |||
| 57 | #define STATE_IDLE 0 /* Channel is inactive. */ | ||
| 58 | #define STATE_STALL 1 /* Channel is active, no buffers pending. */ | ||
| 59 | #define STATE_ON 2 /* Channel is active, one buffer pending. */ | ||
| 60 | #define STATE_NEXT 3 /* Channel is active, two buffers pending. */ | ||
| 61 | |||
| 62 | struct m2p_channel { | ||
| 63 | char *name; | ||
| 64 | void __iomem *base; | ||
| 65 | int irq; | ||
| 66 | |||
| 67 | struct clk *clk; | ||
| 68 | spinlock_t lock; | ||
| 69 | |||
| 70 | void *client; | ||
| 71 | unsigned next_slot:1; | ||
| 72 | struct ep93xx_dma_buffer *buffer_xfer; | ||
| 73 | struct ep93xx_dma_buffer *buffer_next; | ||
| 74 | struct list_head buffers_pending; | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct m2p_channel m2p_rx[] = { | ||
| 78 | {"m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1}, | ||
| 79 | {"m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3}, | ||
| 80 | {"m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5}, | ||
| 81 | {"m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7}, | ||
| 82 | {"m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9}, | ||
| 83 | {NULL}, | ||
| 84 | }; | ||
| 85 | |||
| 86 | static struct m2p_channel m2p_tx[] = { | ||
| 87 | {"m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0}, | ||
| 88 | {"m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2}, | ||
| 89 | {"m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4}, | ||
| 90 | {"m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6}, | ||
| 91 | {"m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8}, | ||
| 92 | {NULL}, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static void feed_buf(struct m2p_channel *ch, struct ep93xx_dma_buffer *buf) | ||
| 96 | { | ||
| 97 | if (ch->next_slot == 0) { | ||
| 98 | writel(buf->size, ch->base + M2P_MAXCNT0); | ||
| 99 | writel(buf->bus_addr, ch->base + M2P_BASE0); | ||
| 100 | } else { | ||
| 101 | writel(buf->size, ch->base + M2P_MAXCNT1); | ||
| 102 | writel(buf->bus_addr, ch->base + M2P_BASE1); | ||
| 103 | } | ||
| 104 | ch->next_slot ^= 1; | ||
| 105 | } | ||
| 106 | |||
| 107 | static void choose_buffer_xfer(struct m2p_channel *ch) | ||
| 108 | { | ||
| 109 | struct ep93xx_dma_buffer *buf; | ||
| 110 | |||
| 111 | ch->buffer_xfer = NULL; | ||
| 112 | if (!list_empty(&ch->buffers_pending)) { | ||
| 113 | buf = list_entry(ch->buffers_pending.next, | ||
| 114 | struct ep93xx_dma_buffer, list); | ||
| 115 | list_del(&buf->list); | ||
| 116 | feed_buf(ch, buf); | ||
| 117 | ch->buffer_xfer = buf; | ||
| 118 | } | ||
| 119 | } | ||
| 120 | |||
| 121 | static void choose_buffer_next(struct m2p_channel *ch) | ||
| 122 | { | ||
| 123 | struct ep93xx_dma_buffer *buf; | ||
| 124 | |||
| 125 | ch->buffer_next = NULL; | ||
| 126 | if (!list_empty(&ch->buffers_pending)) { | ||
| 127 | buf = list_entry(ch->buffers_pending.next, | ||
| 128 | struct ep93xx_dma_buffer, list); | ||
| 129 | list_del(&buf->list); | ||
| 130 | feed_buf(ch, buf); | ||
| 131 | ch->buffer_next = buf; | ||
| 132 | } | ||
| 133 | } | ||
| 134 | |||
| 135 | static inline void m2p_set_control(struct m2p_channel *ch, u32 v) | ||
| 136 | { | ||
| 137 | /* | ||
| 138 | * The control register must be read immediately after being written so | ||
| 139 | * that the internal state machine is correctly updated. See the ep93xx | ||
| 140 | * users' guide for details. | ||
| 141 | */ | ||
| 142 | writel(v, ch->base + M2P_CONTROL); | ||
| 143 | readl(ch->base + M2P_CONTROL); | ||
| 144 | } | ||
| 145 | |||
| 146 | static inline int m2p_channel_state(struct m2p_channel *ch) | ||
| 147 | { | ||
| 148 | return (readl(ch->base + M2P_STATUS) >> 4) & 0x3; | ||
| 149 | } | ||
| 150 | |||
| 151 | static irqreturn_t m2p_irq(int irq, void *dev_id) | ||
| 152 | { | ||
| 153 | struct m2p_channel *ch = dev_id; | ||
| 154 | struct ep93xx_dma_m2p_client *cl; | ||
| 155 | u32 irq_status, v; | ||
| 156 | int error = 0; | ||
| 157 | |||
| 158 | cl = ch->client; | ||
| 159 | |||
| 160 | spin_lock(&ch->lock); | ||
| 161 | irq_status = readl(ch->base + M2P_INTERRUPT); | ||
| 162 | |||
| 163 | if (irq_status & M2P_INTERRUPT_ERROR) { | ||
| 164 | writel(M2P_INTERRUPT_ERROR, ch->base + M2P_INTERRUPT); | ||
| 165 | error = 1; | ||
| 166 | } | ||
| 167 | |||
| 168 | if ((irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)) == 0) { | ||
| 169 | spin_unlock(&ch->lock); | ||
| 170 | return IRQ_NONE; | ||
| 171 | } | ||
| 172 | |||
| 173 | switch (m2p_channel_state(ch)) { | ||
| 174 | case STATE_IDLE: | ||
| 175 | pr_crit("m2p_irq: dma interrupt without a dma buffer\n"); | ||
| 176 | BUG(); | ||
| 177 | break; | ||
| 178 | |||
| 179 | case STATE_STALL: | ||
| 180 | cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error); | ||
| 181 | if (ch->buffer_next != NULL) { | ||
| 182 | cl->buffer_finished(cl->cookie, ch->buffer_next, | ||
| 183 | 0, error); | ||
| 184 | } | ||
| 185 | choose_buffer_xfer(ch); | ||
| 186 | choose_buffer_next(ch); | ||
| 187 | if (ch->buffer_xfer != NULL) | ||
| 188 | cl->buffer_started(cl->cookie, ch->buffer_xfer); | ||
| 189 | break; | ||
| 190 | |||
| 191 | case STATE_ON: | ||
| 192 | cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error); | ||
| 193 | ch->buffer_xfer = ch->buffer_next; | ||
| 194 | choose_buffer_next(ch); | ||
| 195 | cl->buffer_started(cl->cookie, ch->buffer_xfer); | ||
| 196 | break; | ||
| 197 | |||
| 198 | case STATE_NEXT: | ||
| 199 | pr_crit("m2p_irq: dma interrupt while next\n"); | ||
| 200 | BUG(); | ||
| 201 | break; | ||
| 202 | } | ||
| 203 | |||
| 204 | v = readl(ch->base + M2P_CONTROL) & ~(M2P_CONTROL_STALL_IRQ_EN | | ||
| 205 | M2P_CONTROL_NFB_IRQ_EN); | ||
| 206 | if (ch->buffer_xfer != NULL) | ||
| 207 | v |= M2P_CONTROL_STALL_IRQ_EN; | ||
| 208 | if (ch->buffer_next != NULL) | ||
| 209 | v |= M2P_CONTROL_NFB_IRQ_EN; | ||
| 210 | m2p_set_control(ch, v); | ||
| 211 | |||
| 212 | spin_unlock(&ch->lock); | ||
| 213 | return IRQ_HANDLED; | ||
| 214 | } | ||
| 215 | |||
| 216 | static struct m2p_channel *find_free_channel(struct ep93xx_dma_m2p_client *cl) | ||
| 217 | { | ||
| 218 | struct m2p_channel *ch; | ||
| 219 | int i; | ||
| 220 | |||
| 221 | if (cl->flags & EP93XX_DMA_M2P_RX) | ||
| 222 | ch = m2p_rx; | ||
| 223 | else | ||
| 224 | ch = m2p_tx; | ||
| 225 | |||
| 226 | for (i = 0; ch[i].base; i++) { | ||
| 227 | struct ep93xx_dma_m2p_client *client; | ||
| 228 | |||
| 229 | client = ch[i].client; | ||
| 230 | if (client != NULL) { | ||
| 231 | int port; | ||
| 232 | |||
| 233 | port = cl->flags & EP93XX_DMA_M2P_PORT_MASK; | ||
| 234 | if (port == (client->flags & | ||
| 235 | EP93XX_DMA_M2P_PORT_MASK)) { | ||
| 236 | pr_warning("DMA channel already used by %s\n", | ||
| 237 | cl->name ? : "unknown client"); | ||
| 238 | return ERR_PTR(-EBUSY); | ||
| 239 | } | ||
| 240 | } | ||
| 241 | } | ||
| 242 | |||
| 243 | for (i = 0; ch[i].base; i++) { | ||
| 244 | if (ch[i].client == NULL) | ||
| 245 | return ch + i; | ||
| 246 | } | ||
| 247 | |||
| 248 | pr_warning("No free DMA channel for %s\n", | ||
| 249 | cl->name ? : "unknown client"); | ||
| 250 | return ERR_PTR(-ENODEV); | ||
| 251 | } | ||
| 252 | |||
| 253 | static void channel_enable(struct m2p_channel *ch) | ||
| 254 | { | ||
| 255 | struct ep93xx_dma_m2p_client *cl = ch->client; | ||
| 256 | u32 v; | ||
| 257 | |||
| 258 | clk_enable(ch->clk); | ||
| 259 | |||
| 260 | v = cl->flags & EP93XX_DMA_M2P_PORT_MASK; | ||
| 261 | writel(v, ch->base + M2P_PPALLOC); | ||
| 262 | |||
| 263 | v = cl->flags & EP93XX_DMA_M2P_ERROR_MASK; | ||
| 264 | v |= M2P_CONTROL_ENABLE | M2P_CONTROL_ERROR_IRQ_EN; | ||
| 265 | m2p_set_control(ch, v); | ||
| 266 | } | ||
| 267 | |||
| 268 | static void channel_disable(struct m2p_channel *ch) | ||
| 269 | { | ||
| 270 | u32 v; | ||
| 271 | |||
| 272 | v = readl(ch->base + M2P_CONTROL); | ||
| 273 | v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN); | ||
| 274 | m2p_set_control(ch, v); | ||
| 275 | |||
| 276 | while (m2p_channel_state(ch) == STATE_ON) | ||
| 277 | cpu_relax(); | ||
| 278 | |||
| 279 | m2p_set_control(ch, 0x0); | ||
| 280 | |||
| 281 | while (m2p_channel_state(ch) == STATE_STALL) | ||
| 282 | cpu_relax(); | ||
| 283 | |||
| 284 | clk_disable(ch->clk); | ||
| 285 | } | ||
| 286 | |||
| 287 | int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *cl) | ||
| 288 | { | ||
| 289 | struct m2p_channel *ch; | ||
| 290 | int err; | ||
| 291 | |||
| 292 | ch = find_free_channel(cl); | ||
| 293 | if (IS_ERR(ch)) | ||
| 294 | return PTR_ERR(ch); | ||
| 295 | |||
| 296 | err = request_irq(ch->irq, m2p_irq, 0, cl->name ? : "dma-m2p", ch); | ||
| 297 | if (err) | ||
| 298 | return err; | ||
| 299 | |||
| 300 | ch->client = cl; | ||
| 301 | ch->next_slot = 0; | ||
| 302 | ch->buffer_xfer = NULL; | ||
| 303 | ch->buffer_next = NULL; | ||
| 304 | INIT_LIST_HEAD(&ch->buffers_pending); | ||
| 305 | |||
| 306 | cl->channel = ch; | ||
| 307 | |||
| 308 | channel_enable(ch); | ||
| 309 | |||
| 310 | return 0; | ||
| 311 | } | ||
| 312 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_register); | ||
| 313 | |||
| 314 | void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *cl) | ||
| 315 | { | ||
| 316 | struct m2p_channel *ch = cl->channel; | ||
| 317 | |||
| 318 | channel_disable(ch); | ||
| 319 | free_irq(ch->irq, ch); | ||
| 320 | ch->client = NULL; | ||
| 321 | } | ||
| 322 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_unregister); | ||
| 323 | |||
| 324 | void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *cl, | ||
| 325 | struct ep93xx_dma_buffer *buf) | ||
| 326 | { | ||
| 327 | struct m2p_channel *ch = cl->channel; | ||
| 328 | unsigned long flags; | ||
| 329 | u32 v; | ||
| 330 | |||
| 331 | spin_lock_irqsave(&ch->lock, flags); | ||
| 332 | v = readl(ch->base + M2P_CONTROL); | ||
| 333 | if (ch->buffer_xfer == NULL) { | ||
| 334 | ch->buffer_xfer = buf; | ||
| 335 | feed_buf(ch, buf); | ||
| 336 | cl->buffer_started(cl->cookie, buf); | ||
| 337 | |||
| 338 | v |= M2P_CONTROL_STALL_IRQ_EN; | ||
| 339 | m2p_set_control(ch, v); | ||
| 340 | |||
| 341 | } else if (ch->buffer_next == NULL) { | ||
| 342 | ch->buffer_next = buf; | ||
| 343 | feed_buf(ch, buf); | ||
| 344 | |||
| 345 | v |= M2P_CONTROL_NFB_IRQ_EN; | ||
| 346 | m2p_set_control(ch, v); | ||
| 347 | } else { | ||
| 348 | list_add_tail(&buf->list, &ch->buffers_pending); | ||
| 349 | } | ||
| 350 | spin_unlock_irqrestore(&ch->lock, flags); | ||
| 351 | } | ||
| 352 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit); | ||
| 353 | |||
| 354 | void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *cl, | ||
| 355 | struct ep93xx_dma_buffer *buf) | ||
| 356 | { | ||
| 357 | struct m2p_channel *ch = cl->channel; | ||
| 358 | |||
| 359 | list_add_tail(&buf->list, &ch->buffers_pending); | ||
| 360 | } | ||
| 361 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit_recursive); | ||
| 362 | |||
| 363 | void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *cl) | ||
| 364 | { | ||
| 365 | struct m2p_channel *ch = cl->channel; | ||
| 366 | |||
| 367 | channel_disable(ch); | ||
| 368 | ch->next_slot = 0; | ||
| 369 | ch->buffer_xfer = NULL; | ||
| 370 | ch->buffer_next = NULL; | ||
| 371 | INIT_LIST_HEAD(&ch->buffers_pending); | ||
| 372 | channel_enable(ch); | ||
| 373 | } | ||
| 374 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_flush); | ||
| 375 | |||
| 376 | static int init_channel(struct m2p_channel *ch) | ||
| 377 | { | ||
| 378 | ch->clk = clk_get(NULL, ch->name); | ||
| 379 | if (IS_ERR(ch->clk)) | ||
| 380 | return PTR_ERR(ch->clk); | ||
| 381 | |||
| 382 | spin_lock_init(&ch->lock); | ||
| 383 | ch->client = NULL; | ||
| 384 | |||
| 385 | return 0; | ||
| 386 | } | ||
| 387 | |||
| 388 | static int __init ep93xx_dma_m2p_init(void) | ||
| 389 | { | ||
| 390 | int i; | ||
| 391 | int ret; | ||
| 392 | |||
| 393 | for (i = 0; m2p_rx[i].base; i++) { | ||
| 394 | ret = init_channel(m2p_rx + i); | ||
| 395 | if (ret) | ||
| 396 | return ret; | ||
| 397 | } | ||
| 398 | |||
| 399 | for (i = 0; m2p_tx[i].base; i++) { | ||
| 400 | ret = init_channel(m2p_tx + i); | ||
| 401 | if (ret) | ||
| 402 | return ret; | ||
| 403 | } | ||
| 404 | |||
| 405 | pr_info("M2P DMA subsystem initialized\n"); | ||
| 406 | return 0; | ||
| 407 | } | ||
| 408 | arch_initcall(ep93xx_dma_m2p_init); | ||
diff --git a/arch/arm/mach-ep93xx/edb9307a.c b/arch/arm/mach-ep93xx/edb9307a.c index 5b5c22b681be..6171167d3315 100644 --- a/arch/arm/mach-ep93xx/edb9307a.c +++ b/arch/arm/mach-ep93xx/edb9307a.c | |||
| @@ -48,12 +48,24 @@ static struct ep93xx_eth_data edb9307a_eth_data = { | |||
| 48 | .phy_id = 1, | 48 | .phy_id = 1, |
| 49 | }; | 49 | }; |
| 50 | 50 | ||
| 51 | static struct i2c_board_info __initdata edb9307a_i2c_data[] = { | ||
| 52 | { | ||
| 53 | /* On-board battery backed RTC */ | ||
| 54 | I2C_BOARD_INFO("isl1208", 0x6f), | ||
| 55 | }, | ||
| 56 | /* | ||
| 57 | * The I2C signals are also routed to the Expansion Connector (J4) | ||
| 58 | */ | ||
| 59 | }; | ||
| 60 | |||
| 51 | static void __init edb9307a_init_machine(void) | 61 | static void __init edb9307a_init_machine(void) |
| 52 | { | 62 | { |
| 53 | ep93xx_init_devices(); | 63 | ep93xx_init_devices(); |
| 54 | platform_device_register(&edb9307a_flash); | 64 | platform_device_register(&edb9307a_flash); |
| 55 | 65 | ||
| 56 | ep93xx_register_eth(&edb9307a_eth_data, 1); | 66 | ep93xx_register_eth(&edb9307a_eth_data, 1); |
| 67 | |||
| 68 | ep93xx_init_i2c(edb9307a_i2c_data, ARRAY_SIZE(edb9307a_i2c_data)); | ||
| 57 | } | 69 | } |
| 58 | 70 | ||
| 59 | MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") | 71 | MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") |
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h new file mode 100644 index 000000000000..ef6bd9d13148 --- /dev/null +++ b/arch/arm/mach-ep93xx/include/mach/dma.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | #ifndef __ASM_ARCH_DMA_H | ||
| 2 | #define __ASM_ARCH_DMA_H | ||
| 3 | |||
| 4 | #include <linux/list.h> | ||
| 5 | #include <linux/types.h> | ||
| 6 | |||
| 7 | struct ep93xx_dma_buffer { | ||
| 8 | struct list_head list; | ||
| 9 | u32 bus_addr; | ||
| 10 | u16 size; | ||
| 11 | }; | ||
| 12 | |||
| 13 | struct ep93xx_dma_m2p_client { | ||
| 14 | char *name; | ||
| 15 | u8 flags; | ||
| 16 | void *cookie; | ||
| 17 | void (*buffer_started)(void *cookie, | ||
| 18 | struct ep93xx_dma_buffer *buf); | ||
| 19 | void (*buffer_finished)(void *cookie, | ||
| 20 | struct ep93xx_dma_buffer *buf, | ||
| 21 | int bytes, int error); | ||
| 22 | |||
| 23 | /* Internal to the DMA code. */ | ||
| 24 | void *channel; | ||
| 25 | }; | ||
| 26 | |||
| 27 | #define EP93XX_DMA_M2P_PORT_I2S1 0x00 | ||
| 28 | #define EP93XX_DMA_M2P_PORT_I2S2 0x01 | ||
| 29 | #define EP93XX_DMA_M2P_PORT_AAC1 0x02 | ||
| 30 | #define EP93XX_DMA_M2P_PORT_AAC2 0x03 | ||
| 31 | #define EP93XX_DMA_M2P_PORT_AAC3 0x04 | ||
| 32 | #define EP93XX_DMA_M2P_PORT_I2S3 0x05 | ||
| 33 | #define EP93XX_DMA_M2P_PORT_UART1 0x06 | ||
| 34 | #define EP93XX_DMA_M2P_PORT_UART2 0x07 | ||
| 35 | #define EP93XX_DMA_M2P_PORT_UART3 0x08 | ||
| 36 | #define EP93XX_DMA_M2P_PORT_IRDA 0x09 | ||
| 37 | #define EP93XX_DMA_M2P_PORT_MASK 0x0f | ||
| 38 | #define EP93XX_DMA_M2P_TX 0x00 | ||
| 39 | #define EP93XX_DMA_M2P_RX 0x10 | ||
| 40 | #define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20 | ||
| 41 | #define EP93XX_DMA_M2P_IGNORE_ERROR 0x40 | ||
| 42 | #define EP93XX_DMA_M2P_ERROR_MASK 0x60 | ||
| 43 | |||
| 44 | int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p); | ||
| 45 | void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p); | ||
| 46 | void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p, | ||
| 47 | struct ep93xx_dma_buffer *buf); | ||
| 48 | void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p, | ||
| 49 | struct ep93xx_dma_buffer *buf); | ||
| 50 | void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p); | ||
| 51 | |||
| 52 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index 22d6c9a6e4ca..f66be12b856e 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | |||
| @@ -58,7 +58,8 @@ | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | /* AHB peripherals */ | 60 | /* AHB peripherals */ |
| 61 | #define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) | 61 | #define EP93XX_DMA_BASE ((void __iomem *) \ |
| 62 | (EP93XX_AHB_VIRT_BASE + 0x00000000)) | ||
| 62 | 63 | ||
| 63 | #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) | 64 | #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) |
| 64 | #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) | 65 | #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) |
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h index 67789d0f329e..ed8f35e4f068 100644 --- a/arch/arm/mach-ep93xx/include/mach/system.h +++ b/arch/arm/mach-ep93xx/include/mach/system.h | |||
| @@ -9,7 +9,7 @@ static inline void arch_idle(void) | |||
| 9 | cpu_do_idle(); | 9 | cpu_do_idle(); |
| 10 | } | 10 | } |
| 11 | 11 | ||
| 12 | static inline void arch_reset(char mode) | 12 | static inline void arch_reset(char mode, const char *cmd) |
| 13 | { | 13 | { |
| 14 | u32 devicecfg; | 14 | u32 devicecfg; |
| 15 | 15 | ||
diff --git a/arch/arm/mach-footbridge/dma.c b/arch/arm/mach-footbridge/dma.c index 4f3506346969..e2e0df8bcee2 100644 --- a/arch/arm/mach-footbridge/dma.c +++ b/arch/arm/mach-footbridge/dma.c | |||
| @@ -21,16 +21,16 @@ | |||
| 21 | #include <asm/hardware/dec21285.h> | 21 | #include <asm/hardware/dec21285.h> |
| 22 | 22 | ||
| 23 | #if 0 | 23 | #if 0 |
| 24 | static int fb_dma_request(dmach_t channel, dma_t *dma) | 24 | static int fb_dma_request(unsigned int chan, dma_t *dma) |
| 25 | { | 25 | { |
| 26 | return -EINVAL; | 26 | return -EINVAL; |
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | static void fb_dma_enable(dmach_t channel, dma_t *dma) | 29 | static void fb_dma_enable(unsigned int chan, dma_t *dma) |
| 30 | { | 30 | { |
| 31 | } | 31 | } |
| 32 | 32 | ||
| 33 | static void fb_dma_disable(dmach_t channel, dma_t *dma) | 33 | static void fb_dma_disable(unsigned int chan, dma_t *dma) |
| 34 | { | 34 | { |
| 35 | } | 35 | } |
| 36 | 36 | ||
| @@ -42,7 +42,7 @@ static struct dma_ops fb_dma_ops = { | |||
| 42 | }; | 42 | }; |
| 43 | #endif | 43 | #endif |
| 44 | 44 | ||
| 45 | void __init arch_dma_init(dma_t *dma) | 45 | static int __init fb_dma_init(void) |
| 46 | { | 46 | { |
| 47 | #if 0 | 47 | #if 0 |
| 48 | dma[_DC21285_DMA(0)].d_ops = &fb_dma_ops; | 48 | dma[_DC21285_DMA(0)].d_ops = &fb_dma_ops; |
| @@ -50,6 +50,8 @@ void __init arch_dma_init(dma_t *dma) | |||
| 50 | #endif | 50 | #endif |
| 51 | #ifdef CONFIG_ISA_DMA | 51 | #ifdef CONFIG_ISA_DMA |
| 52 | if (footbridge_cfn_mode()) | 52 | if (footbridge_cfn_mode()) |
| 53 | isa_init_dma(dma + _ISA_DMA(0)); | 53 | isa_init_dma(); |
| 54 | #endif | 54 | #endif |
| 55 | return 0; | ||
| 55 | } | 56 | } |
| 57 | core_initcall(fb_dma_init); | ||
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h index 2db7f36bd6ca..0b2931566209 100644 --- a/arch/arm/mach-footbridge/include/mach/system.h +++ b/arch/arm/mach-footbridge/include/mach/system.h | |||
| @@ -18,7 +18,7 @@ static inline void arch_idle(void) | |||
| 18 | cpu_do_idle(); | 18 | cpu_do_idle(); |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | static inline void arch_reset(char mode) | 21 | static inline void arch_reset(char mode, const char *cmd) |
| 22 | { | 22 | { |
| 23 | if (mode == 's') { | 23 | if (mode == 's') { |
| 24 | /* | 24 | /* |
diff --git a/arch/arm/mach-gemini/Kconfig b/arch/arm/mach-gemini/Kconfig new file mode 100644 index 000000000000..515b75cf2e8b --- /dev/null +++ b/arch/arm/mach-gemini/Kconfig | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | if ARCH_GEMINI | ||
| 2 | |||
| 3 | menu "Cortina Systems Gemini Implementations" | ||
| 4 | |||
| 5 | config MACH_RUT100 | ||
| 6 | bool "Teltonika RUT100" | ||
| 7 | select GEMINI_MEM_SWAP | ||
| 8 | help | ||
| 9 | Say Y here if you intend to run this kernel on a | ||
| 10 | Teltonika 3G Router RUT100. | ||
| 11 | |||
| 12 | endmenu | ||
| 13 | |||
| 14 | config GEMINI_MEM_SWAP | ||
| 15 | bool "Gemini memory is swapped" | ||
| 16 | help | ||
| 17 | Say Y here if Gemini memory is swapped by bootloader. | ||
| 18 | |||
| 19 | endif | ||
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile new file mode 100644 index 000000000000..719505b81821 --- /dev/null +++ b/arch/arm/mach-gemini/Makefile | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | # | ||
| 2 | # Makefile for the linux kernel. | ||
| 3 | # | ||
| 4 | |||
| 5 | # Object file lists. | ||
| 6 | |||
| 7 | obj-y := irq.o mm.o time.o devices.o gpio.o | ||
| 8 | |||
| 9 | # Board-specific support | ||
| 10 | obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o | ||
diff --git a/arch/arm/mach-gemini/Makefile.boot b/arch/arm/mach-gemini/Makefile.boot new file mode 100644 index 000000000000..22a52c228d93 --- /dev/null +++ b/arch/arm/mach-gemini/Makefile.boot | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | ifeq ($(CONFIG_GEMINI_MEM_SWAP),y) | ||
| 2 | zreladdr-y := 0x00008000 | ||
| 3 | params_phys-y := 0x00000100 | ||
| 4 | initrd_phys-y := 0x00800000 | ||
| 5 | else | ||
| 6 | zreladdr-y := 0x10008000 | ||
| 7 | params_phys-y := 0x10000100 | ||
| 8 | initrd_phys-y := 0x10800000 | ||
| 9 | endif | ||
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c new file mode 100644 index 000000000000..e0de968e32a6 --- /dev/null +++ b/arch/arm/mach-gemini/board-rut1xx.c | |||
| @@ -0,0 +1,95 @@ | |||
| 1 | /* | ||
| 2 | * Support for Teltonika RUT1xx | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/leds.h> | ||
| 15 | #include <linux/input.h> | ||
| 16 | #include <linux/gpio_keys.h> | ||
| 17 | |||
| 18 | #include <asm/mach-types.h> | ||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include <asm/mach/time.h> | ||
| 21 | |||
| 22 | #include "common.h" | ||
| 23 | |||
| 24 | static struct gpio_keys_button rut1xx_keys[] = { | ||
| 25 | { | ||
| 26 | .code = KEY_SETUP, | ||
| 27 | .gpio = 60, | ||
| 28 | .active_low = 1, | ||
| 29 | .desc = "Reset to defaults", | ||
| 30 | .type = EV_KEY, | ||
| 31 | }, | ||
| 32 | }; | ||
| 33 | |||
| 34 | static struct gpio_keys_platform_data rut1xx_keys_data = { | ||
| 35 | .buttons = rut1xx_keys, | ||
| 36 | .nbuttons = ARRAY_SIZE(rut1xx_keys), | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct platform_device rut1xx_keys_device = { | ||
| 40 | .name = "gpio-keys", | ||
| 41 | .id = -1, | ||
| 42 | .dev = { | ||
| 43 | .platform_data = &rut1xx_keys_data, | ||
| 44 | }, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct gpio_led rut100_leds[] = { | ||
| 48 | { | ||
| 49 | .name = "Power", | ||
| 50 | .default_trigger = "heartbeat", | ||
| 51 | .gpio = 17, | ||
| 52 | }, | ||
| 53 | { | ||
| 54 | .name = "GSM", | ||
| 55 | .default_trigger = "default-on", | ||
| 56 | .gpio = 7, | ||
| 57 | .active_low = 1, | ||
| 58 | }, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct gpio_led_platform_data rut100_leds_data = { | ||
| 62 | .num_leds = ARRAY_SIZE(rut100_leds), | ||
| 63 | .leds = rut100_leds, | ||
| 64 | }; | ||
| 65 | |||
| 66 | static struct platform_device rut1xx_leds = { | ||
| 67 | .name = "leds-gpio", | ||
| 68 | .id = -1, | ||
| 69 | .dev = { | ||
| 70 | .platform_data = &rut100_leds_data, | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static struct sys_timer rut1xx_timer = { | ||
| 75 | .init = gemini_timer_init, | ||
| 76 | }; | ||
| 77 | |||
| 78 | static void __init rut1xx_init(void) | ||
| 79 | { | ||
| 80 | gemini_gpio_init(); | ||
| 81 | platform_register_uart(); | ||
| 82 | platform_register_pflash(SZ_8M, NULL, 0); | ||
| 83 | platform_device_register(&rut1xx_leds); | ||
| 84 | platform_device_register(&rut1xx_keys_device); | ||
| 85 | } | ||
| 86 | |||
| 87 | MACHINE_START(RUT100, "Teltonika RUT100") | ||
| 88 | .phys_io = 0x7fffc000, | ||
| 89 | .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc, | ||
| 90 | .boot_params = 0x100, | ||
| 91 | .map_io = gemini_map_io, | ||
| 92 | .init_irq = gemini_init_irq, | ||
| 93 | .timer = &rut1xx_timer, | ||
| 94 | .init_machine = rut1xx_init, | ||
| 95 | MACHINE_END | ||
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h new file mode 100644 index 000000000000..9392834a214f --- /dev/null +++ b/arch/arm/mach-gemini/common.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* | ||
| 2 | * Common Gemini architecture functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __GEMINI_COMMON_H__ | ||
| 13 | #define __GEMINI_COMMON_H__ | ||
| 14 | |||
| 15 | struct mtd_partition; | ||
| 16 | |||
| 17 | extern void gemini_map_io(void); | ||
| 18 | extern void gemini_init_irq(void); | ||
| 19 | extern void gemini_timer_init(void); | ||
| 20 | extern void gemini_gpio_init(void); | ||
| 21 | |||
| 22 | /* Common platform devices registration functions */ | ||
| 23 | extern int platform_register_uart(void); | ||
| 24 | extern int platform_register_pflash(unsigned int size, | ||
| 25 | struct mtd_partition *parts, | ||
| 26 | unsigned int nr_parts); | ||
| 27 | |||
| 28 | #endif /* __GEMINI_COMMON_H__ */ | ||
diff --git a/arch/arm/mach-gemini/devices.c b/arch/arm/mach-gemini/devices.c new file mode 100644 index 000000000000..6b525253d027 --- /dev/null +++ b/arch/arm/mach-gemini/devices.c | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | /* | ||
| 2 | * Common devices definition for Gemini | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/io.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/serial_8250.h> | ||
| 15 | #include <linux/mtd/physmap.h> | ||
| 16 | |||
| 17 | #include <mach/irqs.h> | ||
| 18 | #include <mach/hardware.h> | ||
| 19 | #include <mach/global_reg.h> | ||
| 20 | |||
| 21 | static struct plat_serial8250_port serial_platform_data[] = { | ||
| 22 | { | ||
| 23 | .membase = (void *)IO_ADDRESS(GEMINI_UART_BASE), | ||
| 24 | .mapbase = GEMINI_UART_BASE, | ||
| 25 | .irq = IRQ_UART, | ||
| 26 | .uartclk = UART_CLK, | ||
| 27 | .regshift = 2, | ||
| 28 | .iotype = UPIO_MEM, | ||
| 29 | .type = PORT_16550A, | ||
| 30 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_FIXED_TYPE, | ||
| 31 | }, | ||
| 32 | {}, | ||
| 33 | }; | ||
| 34 | |||
| 35 | static struct platform_device serial_device = { | ||
| 36 | .name = "serial8250", | ||
| 37 | .id = PLAT8250_DEV_PLATFORM, | ||
| 38 | .dev = { | ||
| 39 | .platform_data = serial_platform_data, | ||
| 40 | }, | ||
| 41 | }; | ||
| 42 | |||
| 43 | int platform_register_uart(void) | ||
| 44 | { | ||
| 45 | return platform_device_register(&serial_device); | ||
| 46 | } | ||
| 47 | |||
| 48 | static struct resource flash_resource = { | ||
| 49 | .start = GEMINI_FLASH_BASE, | ||
| 50 | .flags = IORESOURCE_MEM, | ||
| 51 | }; | ||
| 52 | |||
| 53 | static struct physmap_flash_data pflash_platform_data = {}; | ||
| 54 | |||
| 55 | static struct platform_device pflash_device = { | ||
| 56 | .name = "physmap-flash", | ||
| 57 | .id = 0, | ||
| 58 | .dev = { | ||
| 59 | .platform_data = &pflash_platform_data, | ||
| 60 | }, | ||
| 61 | .resource = &flash_resource, | ||
| 62 | .num_resources = 1, | ||
| 63 | }; | ||
| 64 | |||
| 65 | int platform_register_pflash(unsigned int size, struct mtd_partition *parts, | ||
| 66 | unsigned int nr_parts) | ||
| 67 | { | ||
| 68 | unsigned int reg; | ||
| 69 | |||
| 70 | reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_STATUS); | ||
| 71 | |||
| 72 | if ((reg & FLASH_TYPE_MASK) != FLASH_TYPE_PARALLEL) | ||
| 73 | return -ENXIO; | ||
| 74 | |||
| 75 | if (reg & FLASH_WIDTH_16BIT) | ||
| 76 | pflash_platform_data.width = 2; | ||
| 77 | else | ||
| 78 | pflash_platform_data.width = 1; | ||
| 79 | |||
| 80 | /* enable parallel flash pins and disable others */ | ||
| 81 | reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL); | ||
| 82 | reg &= ~PFLASH_PADS_DISABLE; | ||
| 83 | reg |= SFLASH_PADS_DISABLE | NAND_PADS_DISABLE; | ||
| 84 | __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL); | ||
| 85 | |||
| 86 | flash_resource.end = flash_resource.start + size - 1; | ||
| 87 | |||
| 88 | pflash_platform_data.parts = parts; | ||
| 89 | pflash_platform_data.nr_parts = nr_parts; | ||
| 90 | |||
| 91 | return platform_device_register(&pflash_device); | ||
| 92 | } | ||
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c new file mode 100644 index 000000000000..e7263854bc7b --- /dev/null +++ b/arch/arm/mach-gemini/gpio.c | |||
| @@ -0,0 +1,232 @@ | |||
| 1 | /* | ||
| 2 | * Gemini gpiochip and interrupt routines | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * Based on plat-mxc/gpio.c: | ||
| 7 | * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | ||
| 8 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/gpio.h> | ||
| 21 | |||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/irqs.h> | ||
| 24 | |||
| 25 | #define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x)) | ||
| 26 | |||
| 27 | /* GPIO registers definition */ | ||
| 28 | #define GPIO_DATA_OUT 0x0 | ||
| 29 | #define GPIO_DATA_IN 0x4 | ||
| 30 | #define GPIO_DIR 0x8 | ||
| 31 | #define GPIO_DATA_SET 0x10 | ||
| 32 | #define GPIO_DATA_CLR 0x14 | ||
| 33 | #define GPIO_PULL_EN 0x18 | ||
| 34 | #define GPIO_PULL_TYPE 0x1C | ||
| 35 | #define GPIO_INT_EN 0x20 | ||
| 36 | #define GPIO_INT_STAT 0x24 | ||
| 37 | #define GPIO_INT_MASK 0x2C | ||
| 38 | #define GPIO_INT_CLR 0x30 | ||
| 39 | #define GPIO_INT_TYPE 0x34 | ||
| 40 | #define GPIO_INT_BOTH_EDGE 0x38 | ||
| 41 | #define GPIO_INT_LEVEL 0x3C | ||
| 42 | #define GPIO_DEBOUNCE_EN 0x40 | ||
| 43 | #define GPIO_DEBOUNCE_PRESCALE 0x44 | ||
| 44 | |||
| 45 | #define GPIO_PORT_NUM 3 | ||
| 46 | |||
| 47 | static void _set_gpio_irqenable(unsigned int base, unsigned int index, | ||
| 48 | int enable) | ||
| 49 | { | ||
| 50 | unsigned int reg; | ||
| 51 | |||
| 52 | reg = __raw_readl(base + GPIO_INT_EN); | ||
| 53 | reg = (reg & (~(1 << index))) | (!!enable << index); | ||
| 54 | __raw_writel(reg, base + GPIO_INT_EN); | ||
| 55 | } | ||
| 56 | |||
| 57 | static void gpio_ack_irq(unsigned int irq) | ||
| 58 | { | ||
| 59 | unsigned int gpio = irq_to_gpio(irq); | ||
| 60 | unsigned int base = GPIO_BASE(gpio / 32); | ||
| 61 | |||
| 62 | __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); | ||
| 63 | } | ||
| 64 | |||
| 65 | static void gpio_mask_irq(unsigned int irq) | ||
| 66 | { | ||
| 67 | unsigned int gpio = irq_to_gpio(irq); | ||
| 68 | unsigned int base = GPIO_BASE(gpio / 32); | ||
| 69 | |||
| 70 | _set_gpio_irqenable(base, gpio % 32, 0); | ||
| 71 | } | ||
| 72 | |||
| 73 | static void gpio_unmask_irq(unsigned int irq) | ||
| 74 | { | ||
| 75 | unsigned int gpio = irq_to_gpio(irq); | ||
| 76 | unsigned int base = GPIO_BASE(gpio / 32); | ||
| 77 | |||
| 78 | _set_gpio_irqenable(base, gpio % 32, 1); | ||
| 79 | } | ||
| 80 | |||
| 81 | static int gpio_set_irq_type(unsigned int irq, unsigned int type) | ||
| 82 | { | ||
| 83 | unsigned int gpio = irq_to_gpio(irq); | ||
| 84 | unsigned int gpio_mask = 1 << (gpio % 32); | ||
| 85 | unsigned int base = GPIO_BASE(gpio / 32); | ||
| 86 | unsigned int reg_both, reg_level, reg_type; | ||
| 87 | |||
| 88 | reg_type = __raw_readl(base + GPIO_INT_TYPE); | ||
| 89 | reg_level = __raw_readl(base + GPIO_INT_BOTH_EDGE); | ||
| 90 | reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE); | ||
| 91 | |||
| 92 | switch (type) { | ||
| 93 | case IRQ_TYPE_EDGE_BOTH: | ||
| 94 | reg_type &= ~gpio_mask; | ||
| 95 | reg_both |= gpio_mask; | ||
| 96 | break; | ||
| 97 | case IRQ_TYPE_EDGE_RISING: | ||
| 98 | reg_type &= ~gpio_mask; | ||
| 99 | reg_both &= ~gpio_mask; | ||
| 100 | reg_level &= ~gpio_mask; | ||
| 101 | break; | ||
| 102 | case IRQ_TYPE_EDGE_FALLING: | ||
| 103 | reg_type &= ~gpio_mask; | ||
| 104 | reg_both &= ~gpio_mask; | ||
| 105 | reg_level |= gpio_mask; | ||
| 106 | break; | ||
| 107 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 108 | reg_type |= gpio_mask; | ||
| 109 | reg_level &= ~gpio_mask; | ||
| 110 | break; | ||
| 111 | case IRQ_TYPE_LEVEL_LOW: | ||
| 112 | reg_type |= gpio_mask; | ||
| 113 | reg_level |= gpio_mask; | ||
| 114 | break; | ||
| 115 | default: | ||
| 116 | return -EINVAL; | ||
| 117 | } | ||
| 118 | |||
| 119 | __raw_writel(reg_type, base + GPIO_INT_TYPE); | ||
| 120 | __raw_writel(reg_level, base + GPIO_INT_BOTH_EDGE); | ||
| 121 | __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); | ||
| 122 | |||
| 123 | gpio_ack_irq(irq); | ||
| 124 | |||
| 125 | return 0; | ||
| 126 | } | ||
| 127 | |||
| 128 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
| 129 | { | ||
| 130 | unsigned int gpio_irq_no, irq_stat; | ||
| 131 | unsigned int port = (unsigned int)get_irq_data(irq); | ||
| 132 | |||
| 133 | irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); | ||
| 134 | |||
| 135 | gpio_irq_no = GPIO_IRQ_BASE + port * 32; | ||
| 136 | for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { | ||
| 137 | |||
| 138 | if ((irq_stat & 1) == 0) | ||
| 139 | continue; | ||
| 140 | |||
| 141 | BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); | ||
| 142 | irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, | ||
| 143 | &irq_desc[gpio_irq_no]); | ||
| 144 | } | ||
| 145 | } | ||
| 146 | |||
| 147 | static struct irq_chip gpio_irq_chip = { | ||
| 148 | .name = "GPIO", | ||
| 149 | .ack = gpio_ack_irq, | ||
| 150 | .mask = gpio_mask_irq, | ||
| 151 | .unmask = gpio_unmask_irq, | ||
| 152 | .set_type = gpio_set_irq_type, | ||
| 153 | }; | ||
| 154 | |||
| 155 | static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset, | ||
| 156 | int dir) | ||
| 157 | { | ||
| 158 | unsigned int base = GPIO_BASE(offset / 32); | ||
| 159 | unsigned int reg; | ||
| 160 | |||
| 161 | reg = __raw_readl(base + GPIO_DIR); | ||
| 162 | if (dir) | ||
| 163 | reg |= 1 << (offset % 32); | ||
| 164 | else | ||
| 165 | reg &= ~(1 << (offset % 32)); | ||
| 166 | __raw_writel(reg, base + GPIO_DIR); | ||
| 167 | } | ||
| 168 | |||
| 169 | static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 170 | { | ||
| 171 | unsigned int base = GPIO_BASE(offset / 32); | ||
| 172 | |||
| 173 | if (value) | ||
| 174 | __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET); | ||
| 175 | else | ||
| 176 | __raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR); | ||
| 177 | } | ||
| 178 | |||
| 179 | static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 180 | { | ||
| 181 | unsigned int base = GPIO_BASE(offset / 32); | ||
| 182 | |||
| 183 | return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1; | ||
| 184 | } | ||
| 185 | |||
| 186 | static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 187 | { | ||
| 188 | _set_gpio_direction(chip, offset, 0); | ||
| 189 | return 0; | ||
| 190 | } | ||
| 191 | |||
| 192 | static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | ||
| 193 | int value) | ||
| 194 | { | ||
| 195 | _set_gpio_direction(chip, offset, 1); | ||
| 196 | gemini_gpio_set(chip, offset, value); | ||
| 197 | return 0; | ||
| 198 | } | ||
| 199 | |||
| 200 | static struct gpio_chip gemini_gpio_chip = { | ||
| 201 | .label = "Gemini", | ||
| 202 | .direction_input = gemini_gpio_direction_input, | ||
| 203 | .get = gemini_gpio_get, | ||
| 204 | .direction_output = gemini_gpio_direction_output, | ||
| 205 | .set = gemini_gpio_set, | ||
| 206 | .base = 0, | ||
| 207 | .ngpio = GPIO_PORT_NUM * 32, | ||
| 208 | }; | ||
| 209 | |||
| 210 | void __init gemini_gpio_init(void) | ||
| 211 | { | ||
| 212 | int i, j; | ||
| 213 | |||
| 214 | for (i = 0; i < GPIO_PORT_NUM; i++) { | ||
| 215 | /* disable, unmask and clear all interrupts */ | ||
| 216 | __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN); | ||
| 217 | __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK); | ||
| 218 | __raw_writel(~0x0, GPIO_BASE(i) + GPIO_INT_CLR); | ||
| 219 | |||
| 220 | for (j = GPIO_IRQ_BASE + i * 32; | ||
| 221 | j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { | ||
| 222 | set_irq_chip(j, &gpio_irq_chip); | ||
| 223 | set_irq_handler(j, handle_edge_irq); | ||
| 224 | set_irq_flags(j, IRQF_VALID); | ||
| 225 | } | ||
| 226 | |||
| 227 | set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); | ||
| 228 | set_irq_data(IRQ_GPIO(i), (void *)i); | ||
| 229 | } | ||
| 230 | |||
| 231 | BUG_ON(gpiochip_add(&gemini_gpio_chip)); | ||
| 232 | } | ||
diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S new file mode 100644 index 000000000000..d04a6eaeae14 --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/debug-macro.S | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Debugging macro include header | ||
| 3 | * | ||
| 4 | * Copyright (C) 1994-1999 Russell King | ||
| 5 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 6 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | #include <mach/hardware.h> | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | ldreq \rx, =GEMINI_UART_BASE @ physical | ||
| 18 | ldrne \rx, =IO_ADDRESS(GEMINI_UART_BASE) @ virtual | ||
| 19 | .endm | ||
| 20 | |||
| 21 | #define UART_SHIFT 2 | ||
| 22 | #define FLOW_CONTROL | ||
| 23 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/arch/arm/mach-gemini/include/mach/entry-macro.S b/arch/arm/mach-gemini/include/mach/entry-macro.S new file mode 100644 index 000000000000..1624f91a2b8b --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/entry-macro.S | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * Low-level IRQ helper macros for Gemini platform. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | #include <mach/hardware.h> | ||
| 12 | |||
| 13 | #define IRQ_STATUS 0x14 | ||
| 14 | |||
| 15 | .macro disable_fiq | ||
| 16 | .endm | ||
| 17 | |||
| 18 | .macro get_irqnr_preamble, base, tmp | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 25 | ldr \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS) | ||
| 26 | ldr \irqnr, [\irqstat] | ||
| 27 | cmp \irqnr, #0 | ||
| 28 | beq 2313f | ||
| 29 | mov \tmp, \irqnr | ||
| 30 | mov \irqnr, #0 | ||
| 31 | 2312: | ||
| 32 | tst \tmp, #1 | ||
| 33 | bne 2313f | ||
| 34 | add \irqnr, \irqnr, #1 | ||
| 35 | mov \tmp, \tmp, lsr #1 | ||
| 36 | cmp \irqnr, #31 | ||
| 37 | bcc 2312b | ||
| 38 | 2313: | ||
| 39 | .endm | ||
diff --git a/arch/arm/mach-gemini/include/mach/global_reg.h b/arch/arm/mach-gemini/include/mach/global_reg.h new file mode 100644 index 000000000000..de7ff7e849fc --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/global_reg.h | |||
| @@ -0,0 +1,278 @@ | |||
| 1 | /* | ||
| 2 | * This file contains the hardware definitions for Gemini. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | #ifndef __MACH_GLOBAL_REG_H | ||
| 12 | #define __MACH_GLOBAL_REG_H | ||
| 13 | |||
| 14 | /* Global Word ID Register*/ | ||
| 15 | #define GLOBAL_ID 0x00 | ||
| 16 | |||
| 17 | #define CHIP_ID(reg) ((reg) >> 8) | ||
| 18 | #define CHIP_REVISION(reg) ((reg) & 0xFF) | ||
| 19 | |||
| 20 | /* Global Status Register */ | ||
| 21 | #define GLOBAL_STATUS 0x04 | ||
| 22 | |||
| 23 | #define CPU_BIG_ENDIAN (1 << 31) | ||
| 24 | #define PLL_OSC_30M (1 << 30) /* else 60MHz */ | ||
| 25 | |||
| 26 | #define OPERATION_MODE_MASK (0xF << 26) | ||
| 27 | #define OPM_IDDQ (0xF << 26) | ||
| 28 | #define OPM_NAND (0xE << 26) | ||
| 29 | #define OPM_RING (0xD << 26) | ||
| 30 | #define OPM_DIRECT_BOOT (0xC << 26) | ||
| 31 | #define OPM_USB1_PHY_TEST (0xB << 26) | ||
| 32 | #define OPM_USB0_PHY_TEST (0xA << 26) | ||
| 33 | #define OPM_SATA1_PHY_TEST (0x9 << 26) | ||
| 34 | #define OPM_SATA0_PHY_TEST (0x8 << 26) | ||
| 35 | #define OPM_ICE_ARM (0x7 << 26) | ||
| 36 | #define OPM_ICE_FARADAY (0x6 << 26) | ||
| 37 | #define OPM_PLL_BYPASS (0x5 << 26) | ||
| 38 | #define OPM_DEBUG (0x4 << 26) | ||
| 39 | #define OPM_BURN_IN (0x3 << 26) | ||
| 40 | #define OPM_MBIST (0x2 << 26) | ||
| 41 | #define OPM_SCAN (0x1 << 26) | ||
| 42 | #define OPM_REAL (0x0 << 26) | ||
| 43 | |||
| 44 | #define FLASH_TYPE_MASK (0x3 << 24) | ||
| 45 | #define FLASH_TYPE_NAND_2K (0x3 << 24) | ||
| 46 | #define FLASH_TYPE_NAND_512 (0x2 << 24) | ||
| 47 | #define FLASH_TYPE_PARALLEL (0x1 << 24) | ||
| 48 | #define FLASH_TYPE_SERIAL (0x0 << 24) | ||
| 49 | /* if parallel */ | ||
| 50 | #define FLASH_WIDTH_16BIT (1 << 23) /* else 8 bit */ | ||
| 51 | /* if serial */ | ||
| 52 | #define FLASH_ATMEL (1 << 23) /* else STM */ | ||
| 53 | |||
| 54 | #define FLASH_SIZE_MASK (0x3 << 21) | ||
| 55 | #define NAND_256M (0x3 << 21) /* and more */ | ||
| 56 | #define NAND_128M (0x2 << 21) | ||
| 57 | #define NAND_64M (0x1 << 21) | ||
| 58 | #define NAND_32M (0x0 << 21) | ||
| 59 | #define ATMEL_16M (0x3 << 21) /* and more */ | ||
| 60 | #define ATMEL_8M (0x2 << 21) | ||
| 61 | #define ATMEL_4M_2M (0x1 << 21) | ||
| 62 | #define ATMEL_1M (0x0 << 21) /* and less */ | ||
| 63 | #define STM_32M (1 << 22) /* and more */ | ||
| 64 | #define STM_16M (0 << 22) /* and less */ | ||
| 65 | |||
| 66 | #define FLASH_PARALLEL_HIGH_PIN_CNT (1 << 20) /* else low pin cnt */ | ||
| 67 | |||
| 68 | #define CPU_AHB_RATIO_MASK (0x3 << 18) | ||
| 69 | #define CPU_AHB_1_1 (0x0 << 18) | ||
| 70 | #define CPU_AHB_3_2 (0x1 << 18) | ||
| 71 | #define CPU_AHB_24_13 (0x2 << 18) | ||
| 72 | #define CPU_AHB_2_1 (0x3 << 18) | ||
| 73 | |||
| 74 | #define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130) | ||
| 75 | #define AHB_SPEED_TO_REG(x) ((((x - 130)) / 10) << 15) | ||
| 76 | |||
| 77 | /* it is posible to override some settings, use >> OVERRIDE_xxxx_SHIFT */ | ||
| 78 | #define OVERRIDE_FLASH_TYPE_SHIFT 16 | ||
| 79 | #define OVERRIDE_FLASH_WIDTH_SHIFT 16 | ||
| 80 | #define OVERRIDE_FLASH_SIZE_SHIFT 16 | ||
| 81 | #define OVERRIDE_CPU_AHB_RATIO_SHIFT 15 | ||
| 82 | #define OVERRIDE_AHB_SPEED_SHIFT 15 | ||
| 83 | |||
| 84 | /* Global PLL Control Register */ | ||
| 85 | #define GLOBAL_PLL_CTRL 0x08 | ||
| 86 | |||
| 87 | #define PLL_BYPASS (1 << 31) | ||
| 88 | #define PLL_POWER_DOWN (1 << 8) | ||
| 89 | #define PLL_CONTROL_Q (0x1F << 0) | ||
| 90 | |||
| 91 | /* Global Soft Reset Control Register */ | ||
| 92 | #define GLOBAL_RESET 0x0C | ||
| 93 | |||
| 94 | #define RESET_GLOBAL (1 << 31) | ||
| 95 | #define RESET_CPU1 (1 << 30) | ||
| 96 | #define RESET_TVE (1 << 28) | ||
| 97 | #define RESET_SATA1 (1 << 27) | ||
| 98 | #define RESET_SATA0 (1 << 26) | ||
| 99 | #define RESET_CIR (1 << 25) | ||
| 100 | #define RESET_EXT_DEV (1 << 24) | ||
| 101 | #define RESET_WD (1 << 23) | ||
| 102 | #define RESET_GPIO2 (1 << 22) | ||
| 103 | #define RESET_GPIO1 (1 << 21) | ||
| 104 | #define RESET_GPIO0 (1 << 20) | ||
| 105 | #define RESET_SSP (1 << 19) | ||
| 106 | #define RESET_UART (1 << 18) | ||
| 107 | #define RESET_TIMER (1 << 17) | ||
| 108 | #define RESET_RTC (1 << 16) | ||
| 109 | #define RESET_INT1 (1 << 15) | ||
| 110 | #define RESET_INT0 (1 << 14) | ||
| 111 | #define RESET_LCD (1 << 13) | ||
| 112 | #define RESET_LPC (1 << 12) | ||
| 113 | #define RESET_APB (1 << 11) | ||
| 114 | #define RESET_DMA (1 << 10) | ||
| 115 | #define RESET_USB1 (1 << 9) | ||
| 116 | #define RESET_USB0 (1 << 8) | ||
| 117 | #define RESET_PCI (1 << 7) | ||
| 118 | #define RESET_GMAC1 (1 << 6) | ||
| 119 | #define RESET_GMAC0 (1 << 5) | ||
| 120 | #define RESET_SECURITY (1 << 4) | ||
| 121 | #define RESET_RAID (1 << 3) | ||
| 122 | #define RESET_IDE (1 << 2) | ||
| 123 | #define RESET_FLASH (1 << 1) | ||
| 124 | #define RESET_DRAM (1 << 0) | ||
| 125 | |||
| 126 | /* Global IO Pad Driving Capability Control Register */ | ||
| 127 | #define GLOBAL_IO_DRIVING_CTRL 0x10 | ||
| 128 | |||
| 129 | #define DRIVING_CURRENT_MASK 0x3 | ||
| 130 | |||
| 131 | /* here 00-4mA, 01-8mA, 10-12mA, 11-16mA */ | ||
| 132 | #define GPIO1_PADS_31_28_SHIFT 28 | ||
| 133 | #define GPIO0_PADS_31_16_SHIFT 26 | ||
| 134 | #define GPIO0_PADS_15_0_SHIFT 24 | ||
| 135 | #define PCI_AND_EXT_RESET_PADS_SHIFT 22 | ||
| 136 | #define IDE_PADS_SHIFT 20 | ||
| 137 | #define GMAC1_PADS_SHIFT 18 | ||
| 138 | #define GMAC0_PADS_SHIFT 16 | ||
| 139 | /* DRAM is not in mA and poorly documented */ | ||
| 140 | #define DRAM_CLOCK_PADS_SHIFT 8 | ||
| 141 | #define DRAM_DATA_PADS_SHIFT 4 | ||
| 142 | #define DRAM_CONTROL_PADS_SHIFT 0 | ||
| 143 | |||
| 144 | /* Global IO Pad Slew Rate Control Register */ | ||
| 145 | #define GLOBAL_IO_SLEW_RATE_CTRL 0x14 | ||
| 146 | |||
| 147 | #define GPIO1_PADS_31_28_SLOW (1 << 10) | ||
| 148 | #define GPIO0_PADS_31_16_SLOW (1 << 9) | ||
| 149 | #define GPIO0_PADS_15_0_SLOW (1 << 8) | ||
| 150 | #define PCI_PADS_SLOW (1 << 7) | ||
| 151 | #define IDE_PADS_SLOW (1 << 6) | ||
| 152 | #define GMAC1_PADS_SLOW (1 << 5) | ||
| 153 | #define GMAC0_PADS_SLOW (1 << 4) | ||
| 154 | #define DRAM_CLOCK_PADS_SLOW (1 << 1) | ||
| 155 | #define DRAM_IO_PADS_SLOW (1 << 0) | ||
| 156 | |||
| 157 | /* | ||
| 158 | * General skew control defines | ||
| 159 | * 16 steps, each step is around 0.2ns | ||
| 160 | */ | ||
| 161 | #define SKEW_MASK 0xF | ||
| 162 | |||
| 163 | /* Global IDE PAD Skew Control Register */ | ||
| 164 | #define GLOBAL_IDE_SKEW_CTRL 0x18 | ||
| 165 | |||
| 166 | #define IDE1_HOST_STROBE_DELAY_SHIFT 28 | ||
| 167 | #define IDE1_DEVICE_STROBE_DELAY_SHIFT 24 | ||
| 168 | #define IDE1_OUTPUT_IO_SKEW_SHIFT 20 | ||
| 169 | #define IDE1_INPUT_IO_SKEW_SHIFT 16 | ||
| 170 | #define IDE0_HOST_STROBE_DELAY_SHIFT 12 | ||
| 171 | #define IDE0_DEVICE_STROBE_DELAY_SHIFT 8 | ||
| 172 | #define IDE0_OUTPUT_IO_SKEW_SHIFT 4 | ||
| 173 | #define IDE0_INPUT_IO_SKEW_SHIFT 0 | ||
| 174 | |||
| 175 | /* Global GMAC Control Pad Skew Control Register */ | ||
| 176 | #define GLOBAL_GMAC_CTRL_SKEW_CTRL 0x1C | ||
| 177 | |||
| 178 | #define GMAC1_TXC_SKEW_SHIFT 28 | ||
| 179 | #define GMAC1_TXEN_SKEW_SHIFT 24 | ||
| 180 | #define GMAC1_RXC_SKEW_SHIFT 20 | ||
| 181 | #define GMAC1_RXDV_SKEW_SHIFT 16 | ||
| 182 | #define GMAC0_TXC_SKEW_SHIFT 12 | ||
| 183 | #define GMAC0_TXEN_SKEW_SHIFT 8 | ||
| 184 | #define GMAC0_RXC_SKEW_SHIFT 4 | ||
| 185 | #define GMAC0_RXDV_SKEW_SHIFT 0 | ||
| 186 | |||
| 187 | /* Global GMAC0 Data PAD Skew Control Register */ | ||
| 188 | #define GLOBAL_GMAC0_DATA_SKEW_CTRL 0x20 | ||
| 189 | /* Global GMAC1 Data PAD Skew Control Register */ | ||
| 190 | #define GLOBAL_GMAC1_DATA_SKEW_CTRL 0x24 | ||
| 191 | |||
| 192 | #define GMAC_TXD_SKEW_SHIFT(x) (((x) * 4) + 16) | ||
| 193 | #define GMAC_RXD_SKEW_SHIFT(x) ((x) * 4) | ||
| 194 | |||
| 195 | /* CPU has two AHB busses. */ | ||
| 196 | |||
| 197 | /* Global Arbitration0 Control Register */ | ||
| 198 | #define GLOBAL_ARBITRATION0_CTRL 0x28 | ||
| 199 | |||
| 200 | #define BOOT_CONTROLLER_HIGH_PRIO (1 << 3) | ||
| 201 | #define DMA_BUS1_HIGH_PRIO (1 << 2) | ||
| 202 | #define CPU0_HIGH_PRIO (1 << 0) | ||
| 203 | |||
| 204 | /* Global Arbitration1 Control Register */ | ||
| 205 | #define GLOBAL_ARBITRATION1_CTRL 0x2C | ||
| 206 | |||
| 207 | #define TVE_HIGH_PRIO (1 << 9) | ||
| 208 | #define PCI_HIGH_PRIO (1 << 8) | ||
| 209 | #define USB1_HIGH_PRIO (1 << 7) | ||
| 210 | #define USB0_HIGH_PRIO (1 << 6) | ||
| 211 | #define GMAC1_HIGH_PRIO (1 << 5) | ||
| 212 | #define GMAC0_HIGH_PRIO (1 << 4) | ||
| 213 | #define SECURITY_HIGH_PRIO (1 << 3) | ||
| 214 | #define RAID_HIGH_PRIO (1 << 2) | ||
| 215 | #define IDE_HIGH_PRIO (1 << 1) | ||
| 216 | #define DMA_BUS2_HIGH_PRIO (1 << 0) | ||
| 217 | |||
| 218 | /* Common bits for both arbitration registers */ | ||
| 219 | #define BURST_LENGTH_SHIFT 16 | ||
| 220 | #define BURST_LENGTH_MASK (0x3F << 16) | ||
| 221 | |||
| 222 | /* Miscellaneous Control Register */ | ||
| 223 | #define GLOBAL_MISC_CTRL 0x30 | ||
| 224 | |||
| 225 | #define MEMORY_SPACE_SWAP (1 << 31) | ||
| 226 | #define USB1_PLUG_MINIB (1 << 30) /* else plug is mini-A */ | ||
| 227 | #define USB0_PLUG_MINIB (1 << 29) | ||
| 228 | #define GMAC_GMII (1 << 28) | ||
| 229 | #define GMAC_1_ENABLE (1 << 27) | ||
| 230 | /* TODO: define ATA/SATA bits */ | ||
| 231 | #define USB1_VBUS_ON (1 << 23) | ||
| 232 | #define USB0_VBUS_ON (1 << 22) | ||
| 233 | #define APB_CLKOUT_ENABLE (1 << 21) | ||
| 234 | #define TVC_CLKOUT_ENABLE (1 << 20) | ||
| 235 | #define EXT_CLKIN_ENABLE (1 << 19) | ||
| 236 | #define PCI_66MHZ (1 << 18) /* else 33 MHz */ | ||
| 237 | #define PCI_CLKOUT_ENABLE (1 << 17) | ||
| 238 | #define LPC_CLKOUT_ENABLE (1 << 16) | ||
| 239 | #define USB1_WAKEUP_ON (1 << 15) | ||
| 240 | #define USB0_WAKEUP_ON (1 << 14) | ||
| 241 | /* TODO: define PCI idle detect bits */ | ||
| 242 | #define TVC_PADS_ENABLE (1 << 9) | ||
| 243 | #define SSP_PADS_ENABLE (1 << 8) | ||
| 244 | #define LCD_PADS_ENABLE (1 << 7) | ||
| 245 | #define LPC_PADS_ENABLE (1 << 6) | ||
| 246 | #define PCI_PADS_ENABLE (1 << 5) | ||
| 247 | #define IDE_PADS_ENABLE (1 << 4) | ||
| 248 | #define DRAM_PADS_POWER_DOWN (1 << 3) | ||
| 249 | #define NAND_PADS_DISABLE (1 << 2) | ||
| 250 | #define PFLASH_PADS_DISABLE (1 << 1) | ||
| 251 | #define SFLASH_PADS_DISABLE (1 << 0) | ||
| 252 | |||
| 253 | /* Global Clock Control Register */ | ||
| 254 | #define GLOBAL_CLOCK_CTRL 0x34 | ||
| 255 | |||
| 256 | #define POWER_STATE_G0 (1 << 31) | ||
| 257 | #define POWER_STATE_S1 (1 << 30) /* else it is S3/S4 state */ | ||
| 258 | #define SECURITY_APB_AHB (1 << 29) | ||
| 259 | /* else Security APB clk will be 0.75xAHB */ | ||
| 260 | /* TODO: TVC clock divider */ | ||
| 261 | #define PCI_CLKRUN_ENABLE (1 << 16) | ||
| 262 | #define BOOT_CLK_DISABLE (1 << 13) | ||
| 263 | #define TVC_CLK_DISABLE (1 << 12) | ||
| 264 | #define FLASH_CLK_DISABLE (1 << 11) | ||
| 265 | #define DDR_CLK_DISABLE (1 << 10) | ||
| 266 | #define PCI_CLK_DISABLE (1 << 9) | ||
| 267 | #define IDE_CLK_DISABLE (1 << 8) | ||
| 268 | #define USB1_CLK_DISABLE (1 << 7) | ||
| 269 | #define USB0_CLK_DISABLE (1 << 6) | ||
| 270 | #define SATA1_CLK_DISABLE (1 << 5) | ||
| 271 | #define SATA0_CLK_DISABLE (1 << 4) | ||
| 272 | #define GMAC1_CLK_DISABLE (1 << 3) | ||
| 273 | #define GMAC0_CLK_DISABLE (1 << 2) | ||
| 274 | #define SECURITY_CLK_DISABLE (1 << 1) | ||
| 275 | |||
| 276 | /* TODO: other registers definitions if needed */ | ||
| 277 | |||
| 278 | #endif /* __MACH_GLOBAL_REG_H */ | ||
diff --git a/arch/arm/mach-gemini/include/mach/gpio.h b/arch/arm/mach-gemini/include/mach/gpio.h new file mode 100644 index 000000000000..3bc2c70f2989 --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/gpio.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * Gemini gpiolib specific defines | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __MACH_GPIO_H__ | ||
| 13 | #define __MACH_GPIO_H__ | ||
| 14 | |||
| 15 | #include <mach/irqs.h> | ||
| 16 | #include <asm-generic/gpio.h> | ||
| 17 | |||
| 18 | #define gpio_get_value __gpio_get_value | ||
| 19 | #define gpio_set_value __gpio_set_value | ||
| 20 | #define gpio_cansleep __gpio_cansleep | ||
| 21 | |||
| 22 | #define gpio_to_irq(x) ((x) + GPIO_IRQ_BASE) | ||
| 23 | #define irq_to_gpio(x) ((x) - GPIO_IRQ_BASE) | ||
| 24 | |||
| 25 | #endif /* __MACH_GPIO_H__ */ | ||
diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h new file mode 100644 index 000000000000..de6752674c05 --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/hardware.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * This file contains the hardware definitions for Gemini. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #ifndef __MACH_HARDWARE_H | ||
| 13 | #define __MACH_HARDWARE_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Memory Map definitions | ||
| 17 | */ | ||
| 18 | /* FIXME: Does it really swap SRAM like this? */ | ||
| 19 | #ifdef CONFIG_GEMINI_MEM_SWAP | ||
| 20 | # define GEMINI_DRAM_BASE 0x00000000 | ||
| 21 | # define GEMINI_SRAM_BASE 0x20000000 | ||
| 22 | #else | ||
| 23 | # define GEMINI_SRAM_BASE 0x00000000 | ||
| 24 | # define GEMINI_DRAM_BASE 0x10000000 | ||
| 25 | #endif | ||
| 26 | #define GEMINI_FLASH_BASE 0x30000000 | ||
| 27 | #define GEMINI_GLOBAL_BASE 0x40000000 | ||
| 28 | #define GEMINI_WAQTCHDOG_BASE 0x41000000 | ||
| 29 | #define GEMINI_UART_BASE 0x42000000 | ||
| 30 | #define GEMINI_TIMER_BASE 0x43000000 | ||
| 31 | #define GEMINI_LCD_BASE 0x44000000 | ||
| 32 | #define GEMINI_RTC_BASE 0x45000000 | ||
| 33 | #define GEMINI_SATA_BASE 0x46000000 | ||
| 34 | #define GEMINI_LPC_HOST_BASE 0x47000000 | ||
| 35 | #define GEMINI_LPC_IO_BASE 0x47800000 | ||
| 36 | #define GEMINI_INTERRUPT_BASE 0x48000000 | ||
| 37 | /* TODO: Different interrupt controlers when SMP | ||
| 38 | * #define GEMINI_INTERRUPT0_BASE 0x48000000 | ||
| 39 | * #define GEMINI_INTERRUPT1_BASE 0x49000000 | ||
| 40 | */ | ||
| 41 | #define GEMINI_SSP_CTRL_BASE 0x4A000000 | ||
| 42 | #define GEMINI_POWER_CTRL_BASE 0x4B000000 | ||
| 43 | #define GEMINI_CIR_BASE 0x4C000000 | ||
| 44 | #define GEMINI_GPIO_BASE(x) (0x4D000000 + (x) * 0x1000000) | ||
| 45 | #define GEMINI_PCI_IO_BASE 0x50000000 | ||
| 46 | #define GEMINI_PCI_MEM_BASE 0x58000000 | ||
| 47 | #define GEMINI_TOE_BASE 0x60000000 | ||
| 48 | #define GEMINI_GMAC0_BASE 0x6000A000 | ||
| 49 | #define GEMINI_GMAC1_BASE 0x6000E000 | ||
| 50 | #define GEMINI_SECURITY_BASE 0x62000000 | ||
| 51 | #define GEMINI_IDE0_BASE 0x63000000 | ||
| 52 | #define GEMINI_IDE1_BASE 0x63400000 | ||
| 53 | #define GEMINI_RAID_BASE 0x64000000 | ||
| 54 | #define GEMINI_FLASH_CTRL_BASE 0x65000000 | ||
| 55 | #define GEMINI_DRAM_CTRL_BASE 0x66000000 | ||
| 56 | #define GEMINI_GENERAL_DMA_BASE 0x67000000 | ||
| 57 | #define GEMINI_USB0_BASE 0x68000000 | ||
| 58 | #define GEMINI_USB1_BASE 0x69000000 | ||
| 59 | #define GEMINI_BIG_ENDIAN_BASE 0x80000000 | ||
| 60 | |||
| 61 | #define GEMINI_TIMER1_BASE GEMINI_TIMER_BASE | ||
| 62 | #define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10) | ||
| 63 | #define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20) | ||
| 64 | |||
| 65 | /* | ||
| 66 | * UART Clock when System clk is 150MHz | ||
| 67 | */ | ||
| 68 | #define UART_CLK 48000000 | ||
| 69 | |||
| 70 | /* | ||
| 71 | * macro to get at IO space when running virtually | ||
| 72 | */ | ||
| 73 | #define IO_ADDRESS(x) ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000) | ||
| 74 | |||
| 75 | #endif | ||
diff --git a/arch/arm/mach-gemini/include/mach/io.h b/arch/arm/mach-gemini/include/mach/io.h new file mode 100644 index 000000000000..c548056b98b2 --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/io.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 3 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | */ | ||
| 10 | #ifndef __MACH_IO_H | ||
| 11 | #define __MACH_IO_H | ||
| 12 | |||
| 13 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 14 | |||
| 15 | #define __io(a) __typesafe_io(a) | ||
| 16 | #define __mem_pci(a) (a) | ||
| 17 | |||
| 18 | #endif /* __MACH_IO_H */ | ||
diff --git a/arch/arm/mach-gemini/include/mach/irqs.h b/arch/arm/mach-gemini/include/mach/irqs.h new file mode 100644 index 000000000000..06bc47e77e8b --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/irqs.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 3 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __MACH_IRQS_H__ | ||
| 12 | #define __MACH_IRQS_H__ | ||
| 13 | |||
| 14 | #define IRQ_SERIRQ1 31 | ||
| 15 | #define IRQ_SERIRQ0 30 | ||
| 16 | #define IRQ_PCID 29 | ||
| 17 | #define IRQ_PCIC 28 | ||
| 18 | #define IRQ_PCIB 27 | ||
| 19 | #define IRQ_PWR 26 | ||
| 20 | #define IRQ_CIR 25 | ||
| 21 | #define IRQ_GPIO(x) (22 + (x)) | ||
| 22 | #define IRQ_SSP 21 | ||
| 23 | #define IRQ_LPC 20 | ||
| 24 | #define IRQ_LCD 19 | ||
| 25 | #define IRQ_UART 18 | ||
| 26 | #define IRQ_RTC 17 | ||
| 27 | #define IRQ_TIMER3 16 | ||
| 28 | #define IRQ_TIMER2 15 | ||
| 29 | #define IRQ_TIMER1 14 | ||
| 30 | #define IRQ_FLASH 12 | ||
| 31 | #define IRQ_USB1 11 | ||
| 32 | #define IRQ_USB0 10 | ||
| 33 | #define IRQ_DMA 9 | ||
| 34 | #define IRQ_PCI 8 | ||
| 35 | #define IRQ_IPSEC 7 | ||
| 36 | #define IRQ_RAID 6 | ||
| 37 | #define IRQ_IDE1 5 | ||
| 38 | #define IRQ_IDE0 4 | ||
| 39 | #define IRQ_WATCHDOG 3 | ||
| 40 | #define IRQ_GMAC1 2 | ||
| 41 | #define IRQ_GMAC0 1 | ||
| 42 | #define IRQ_IPI 0 | ||
| 43 | |||
| 44 | #define NORMAL_IRQ_NUM 32 | ||
| 45 | |||
| 46 | #define GPIO_IRQ_BASE NORMAL_IRQ_NUM | ||
| 47 | #define GPIO_IRQ_NUM (3 * 32) | ||
| 48 | |||
| 49 | #define ARCH_TIMER_IRQ IRQ_TIMER2 | ||
| 50 | |||
| 51 | #define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM) | ||
| 52 | |||
| 53 | #endif /* __MACH_IRQS_H__ */ | ||
diff --git a/arch/arm/mach-gemini/include/mach/memory.h b/arch/arm/mach-gemini/include/mach/memory.h new file mode 100644 index 000000000000..2d14d5bf1f9f --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/memory.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 3 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | */ | ||
| 10 | #ifndef __MACH_MEMORY_H | ||
| 11 | #define __MACH_MEMORY_H | ||
| 12 | |||
| 13 | #ifdef CONFIG_GEMINI_MEM_SWAP | ||
| 14 | # define PHYS_OFFSET UL(0x00000000) | ||
| 15 | #else | ||
| 16 | # define PHYS_OFFSET UL(0x10000000) | ||
| 17 | #endif | ||
| 18 | |||
| 19 | #endif /* __MACH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/include/mach/system.h new file mode 100644 index 000000000000..bbbd72767a02 --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/system.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 3 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | */ | ||
| 10 | #ifndef __MACH_SYSTEM_H | ||
| 11 | #define __MACH_SYSTEM_H | ||
| 12 | |||
| 13 | #include <linux/io.h> | ||
| 14 | #include <mach/hardware.h> | ||
| 15 | #include <mach/global_reg.h> | ||
| 16 | |||
| 17 | static inline void arch_idle(void) | ||
| 18 | { | ||
| 19 | /* | ||
| 20 | * Because of broken hardware we have to enable interrupts or the CPU | ||
| 21 | * will never wakeup... Acctualy it is not very good to enable | ||
| 22 | * interrupts here since scheduler can miss a tick, but there is | ||
| 23 | * no other way around this. Platforms that needs it for power saving | ||
| 24 | * should call enable_hlt() in init code, since by default it is | ||
| 25 | * disabled. | ||
| 26 | */ | ||
| 27 | local_irq_enable(); | ||
| 28 | cpu_do_idle(); | ||
| 29 | } | ||
| 30 | |||
| 31 | static inline void arch_reset(char mode) | ||
| 32 | { | ||
| 33 | __raw_writel(RESET_GLOBAL | RESET_CPU1, | ||
| 34 | IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET); | ||
| 35 | } | ||
| 36 | |||
| 37 | #endif /* __MACH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-gemini/include/mach/timex.h b/arch/arm/mach-gemini/include/mach/timex.h new file mode 100644 index 000000000000..dc5690ba975c --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/timex.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * Gemini timex specifications | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* When AHB bus frequency is 150MHz */ | ||
| 13 | #define CLOCK_TICK_RATE 38000000 | ||
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h new file mode 100644 index 000000000000..59c5df7e716c --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/uncompress.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 3 | * | ||
| 4 | * Based on mach-pxa/include/mach/uncompress.h: | ||
| 5 | * Copyright: (C) 2001 MontaVista Software Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_UNCOMPRESS_H | ||
| 14 | #define __MACH_UNCOMPRESS_H | ||
| 15 | |||
| 16 | #include <linux/serial_reg.h> | ||
| 17 | #include <mach/hardware.h> | ||
| 18 | |||
| 19 | static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE; | ||
| 20 | |||
| 21 | /* | ||
| 22 | * The following code assumes the serial port has already been | ||
| 23 | * initialized by the bootloader. If you didn't setup a port in | ||
| 24 | * your bootloader then nothing will appear (which might be desired). | ||
| 25 | */ | ||
| 26 | static inline void putc(char c) | ||
| 27 | { | ||
| 28 | while (!(UART[UART_LSR] & UART_LSR_THRE)) | ||
| 29 | barrier(); | ||
| 30 | UART[UART_TX] = c; | ||
| 31 | } | ||
| 32 | |||
| 33 | #define flush() do { } while (0) | ||
| 34 | |||
| 35 | /* | ||
| 36 | * nothing to do | ||
| 37 | */ | ||
| 38 | #define arch_decomp_setup() | ||
| 39 | |||
| 40 | #define arch_decomp_wdog() | ||
| 41 | |||
| 42 | #endif /* __MACH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h new file mode 100644 index 000000000000..83e536d9436c --- /dev/null +++ b/arch/arm/mach-gemini/include/mach/vmalloc.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define VMALLOC_END 0xF0000000 | ||
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c new file mode 100644 index 000000000000..9e613ca8120d --- /dev/null +++ b/arch/arm/mach-gemini/irq.c | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | /* | ||
| 2 | * Interrupt routines for Gemini | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/ioport.h> | ||
| 15 | #include <linux/stddef.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/sched.h> | ||
| 18 | #include <asm/irq.h> | ||
| 19 | #include <asm/mach/irq.h> | ||
| 20 | #include <mach/hardware.h> | ||
| 21 | |||
| 22 | #define IRQ_SOURCE(base_addr) (base_addr + 0x00) | ||
| 23 | #define IRQ_MASK(base_addr) (base_addr + 0x04) | ||
| 24 | #define IRQ_CLEAR(base_addr) (base_addr + 0x08) | ||
| 25 | #define IRQ_TMODE(base_addr) (base_addr + 0x0C) | ||
| 26 | #define IRQ_TLEVEL(base_addr) (base_addr + 0x10) | ||
| 27 | #define IRQ_STATUS(base_addr) (base_addr + 0x14) | ||
| 28 | #define FIQ_SOURCE(base_addr) (base_addr + 0x20) | ||
| 29 | #define FIQ_MASK(base_addr) (base_addr + 0x24) | ||
| 30 | #define FIQ_CLEAR(base_addr) (base_addr + 0x28) | ||
| 31 | #define FIQ_TMODE(base_addr) (base_addr + 0x2C) | ||
| 32 | #define FIQ_LEVEL(base_addr) (base_addr + 0x30) | ||
| 33 | #define FIQ_STATUS(base_addr) (base_addr + 0x34) | ||
| 34 | |||
| 35 | static void gemini_ack_irq(unsigned int irq) | ||
| 36 | { | ||
| 37 | __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 38 | } | ||
| 39 | |||
| 40 | static void gemini_mask_irq(unsigned int irq) | ||
| 41 | { | ||
| 42 | unsigned int mask; | ||
| 43 | |||
| 44 | mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 45 | mask &= ~(1 << irq); | ||
| 46 | __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 47 | } | ||
| 48 | |||
| 49 | static void gemini_unmask_irq(unsigned int irq) | ||
| 50 | { | ||
| 51 | unsigned int mask; | ||
| 52 | |||
| 53 | mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 54 | mask |= (1 << irq); | ||
| 55 | __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 56 | } | ||
| 57 | |||
| 58 | static struct irq_chip gemini_irq_chip = { | ||
| 59 | .name = "INTC", | ||
| 60 | .ack = gemini_ack_irq, | ||
| 61 | .mask = gemini_mask_irq, | ||
| 62 | .unmask = gemini_unmask_irq, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct resource irq_resource = { | ||
| 66 | .name = "irq_handler", | ||
| 67 | .start = IO_ADDRESS(GEMINI_INTERRUPT_BASE), | ||
| 68 | .end = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4, | ||
| 69 | }; | ||
| 70 | |||
| 71 | void __init gemini_init_irq(void) | ||
| 72 | { | ||
| 73 | unsigned int i, mode = 0, level = 0; | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Disable arch_idle() by default since it is buggy | ||
| 77 | * For more info see arch/arm/mach-gemini/include/mach/system.h | ||
| 78 | */ | ||
| 79 | disable_hlt(); | ||
| 80 | |||
| 81 | request_resource(&iomem_resource, &irq_resource); | ||
| 82 | |||
| 83 | for (i = 0; i < NR_IRQS; i++) { | ||
| 84 | set_irq_chip(i, &gemini_irq_chip); | ||
| 85 | if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { | ||
| 86 | set_irq_handler(i, handle_edge_irq); | ||
| 87 | mode |= 1 << i; | ||
| 88 | level |= 1 << i; | ||
| 89 | } else { | ||
| 90 | set_irq_handler(i, handle_level_irq); | ||
| 91 | } | ||
| 92 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | ||
| 93 | } | ||
| 94 | |||
| 95 | /* Disable all interrupts */ | ||
| 96 | __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 97 | __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 98 | |||
| 99 | /* Set interrupt mode */ | ||
| 100 | __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 101 | __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); | ||
| 102 | } | ||
diff --git a/arch/arm/mach-gemini/mm.c b/arch/arm/mach-gemini/mm.c new file mode 100644 index 000000000000..51948242ec09 --- /dev/null +++ b/arch/arm/mach-gemini/mm.c | |||
| @@ -0,0 +1,82 @@ | |||
| 1 | /* | ||
| 2 | * Static mappings for Gemini | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #include <linux/mm.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | |||
| 15 | #include <asm/mach/map.h> | ||
| 16 | |||
| 17 | #include <mach/hardware.h> | ||
| 18 | |||
| 19 | /* Page table mapping for I/O region */ | ||
| 20 | static struct map_desc gemini_io_desc[] __initdata = { | ||
| 21 | { | ||
| 22 | .virtual = IO_ADDRESS(GEMINI_GLOBAL_BASE), | ||
| 23 | .pfn =__phys_to_pfn(GEMINI_GLOBAL_BASE), | ||
| 24 | .length = SZ_512K, | ||
| 25 | .type = MT_DEVICE, | ||
| 26 | }, { | ||
| 27 | .virtual = IO_ADDRESS(GEMINI_UART_BASE), | ||
| 28 | .pfn = __phys_to_pfn(GEMINI_UART_BASE), | ||
| 29 | .length = SZ_512K, | ||
| 30 | .type = MT_DEVICE, | ||
| 31 | }, { | ||
| 32 | .virtual = IO_ADDRESS(GEMINI_TIMER_BASE), | ||
| 33 | .pfn = __phys_to_pfn(GEMINI_TIMER_BASE), | ||
| 34 | .length = SZ_512K, | ||
| 35 | .type = MT_DEVICE, | ||
| 36 | }, { | ||
| 37 | .virtual = IO_ADDRESS(GEMINI_INTERRUPT_BASE), | ||
| 38 | .pfn = __phys_to_pfn(GEMINI_INTERRUPT_BASE), | ||
| 39 | .length = SZ_512K, | ||
| 40 | .type = MT_DEVICE, | ||
| 41 | }, { | ||
| 42 | .virtual = IO_ADDRESS(GEMINI_POWER_CTRL_BASE), | ||
| 43 | .pfn = __phys_to_pfn(GEMINI_POWER_CTRL_BASE), | ||
| 44 | .length = SZ_512K, | ||
| 45 | .type = MT_DEVICE, | ||
| 46 | }, { | ||
| 47 | .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(0)), | ||
| 48 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(0)), | ||
| 49 | .length = SZ_512K, | ||
| 50 | .type = MT_DEVICE, | ||
| 51 | }, { | ||
| 52 | .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(1)), | ||
| 53 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(1)), | ||
| 54 | .length = SZ_512K, | ||
| 55 | .type = MT_DEVICE, | ||
| 56 | }, { | ||
| 57 | .virtual = IO_ADDRESS(GEMINI_GPIO_BASE(2)), | ||
| 58 | .pfn = __phys_to_pfn(GEMINI_GPIO_BASE(2)), | ||
| 59 | .length = SZ_512K, | ||
| 60 | .type = MT_DEVICE, | ||
| 61 | }, { | ||
| 62 | .virtual = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE), | ||
| 63 | .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE), | ||
| 64 | .length = SZ_512K, | ||
| 65 | .type = MT_DEVICE, | ||
| 66 | }, { | ||
| 67 | .virtual = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE), | ||
| 68 | .pfn = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE), | ||
| 69 | .length = SZ_512K, | ||
| 70 | .type = MT_DEVICE, | ||
| 71 | }, { | ||
| 72 | .virtual = IO_ADDRESS(GEMINI_GENERAL_DMA_BASE), | ||
| 73 | .pfn = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE), | ||
| 74 | .length = SZ_512K, | ||
| 75 | .type = MT_DEVICE, | ||
| 76 | }, | ||
| 77 | }; | ||
| 78 | |||
| 79 | void __init gemini_map_io(void) | ||
| 80 | { | ||
| 81 | iotable_init(gemini_io_desc, ARRAY_SIZE(gemini_io_desc)); | ||
| 82 | } | ||
diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c new file mode 100644 index 000000000000..21dc5a89d1c4 --- /dev/null +++ b/arch/arm/mach-gemini/time.c | |||
| @@ -0,0 +1,89 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2001-2006 Storlink, Corp. | ||
| 3 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | */ | ||
| 10 | #include <linux/interrupt.h> | ||
| 11 | #include <linux/irq.h> | ||
| 12 | #include <linux/io.h> | ||
| 13 | #include <mach/hardware.h> | ||
| 14 | #include <mach/global_reg.h> | ||
| 15 | #include <asm/mach/time.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Register definitions for the timers | ||
| 19 | */ | ||
| 20 | #define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00) | ||
| 21 | #define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04) | ||
| 22 | #define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08) | ||
| 23 | #define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C) | ||
| 24 | #define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30) | ||
| 25 | |||
| 26 | #define TIMER_1_CR_ENABLE (1 << 0) | ||
| 27 | #define TIMER_1_CR_CLOCK (1 << 1) | ||
| 28 | #define TIMER_1_CR_INT (1 << 2) | ||
| 29 | #define TIMER_2_CR_ENABLE (1 << 3) | ||
| 30 | #define TIMER_2_CR_CLOCK (1 << 4) | ||
| 31 | #define TIMER_2_CR_INT (1 << 5) | ||
| 32 | #define TIMER_3_CR_ENABLE (1 << 6) | ||
| 33 | #define TIMER_3_CR_CLOCK (1 << 7) | ||
| 34 | #define TIMER_3_CR_INT (1 << 8) | ||
| 35 | |||
| 36 | /* | ||
| 37 | * IRQ handler for the timer | ||
| 38 | */ | ||
| 39 | static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id) | ||
| 40 | { | ||
| 41 | timer_tick(); | ||
| 42 | |||
| 43 | return IRQ_HANDLED; | ||
| 44 | } | ||
| 45 | |||
| 46 | static struct irqaction gemini_timer_irq = { | ||
| 47 | .name = "Gemini Timer Tick", | ||
| 48 | .flags = IRQF_DISABLED | IRQF_TIMER, | ||
| 49 | .handler = gemini_timer_interrupt, | ||
| 50 | }; | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Set up timer interrupt, and return the current time in seconds. | ||
| 54 | */ | ||
| 55 | void __init gemini_timer_init(void) | ||
| 56 | { | ||
| 57 | unsigned int tick_rate, reg_v; | ||
| 58 | |||
| 59 | reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); | ||
| 60 | tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000; | ||
| 61 | |||
| 62 | printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000); | ||
| 63 | |||
| 64 | tick_rate /= 6; /* APB bus run AHB*(1/6) */ | ||
| 65 | |||
| 66 | switch(reg_v & CPU_AHB_RATIO_MASK) { | ||
| 67 | case CPU_AHB_1_1: | ||
| 68 | printk(KERN_CONT "(1/1)\n"); | ||
| 69 | break; | ||
| 70 | case CPU_AHB_3_2: | ||
| 71 | printk(KERN_CONT "(3/2)\n"); | ||
| 72 | break; | ||
| 73 | case CPU_AHB_24_13: | ||
| 74 | printk(KERN_CONT "(24/13)\n"); | ||
| 75 | break; | ||
| 76 | case CPU_AHB_2_1: | ||
| 77 | printk(KERN_CONT "(2/1)\n"); | ||
| 78 | break; | ||
| 79 | } | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Make irqs happen for the system timer | ||
| 83 | */ | ||
| 84 | setup_irq(IRQ_TIMER2, &gemini_timer_irq); | ||
| 85 | /* Start the timer */ | ||
| 86 | __raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); | ||
| 87 | __raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); | ||
| 88 | __raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); | ||
| 89 | } | ||
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h index e4a7c760d52a..a708d24ee46d 100644 --- a/arch/arm/mach-h720x/include/mach/system.h +++ b/arch/arm/mach-h720x/include/mach/system.h | |||
| @@ -25,7 +25,7 @@ static void arch_idle(void) | |||
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | 27 | ||
| 28 | static __inline__ void arch_reset(char mode) | 28 | static __inline__ void arch_reset(char mode, const char *cmd) |
| 29 | { | 29 | { |
| 30 | CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET; | 30 | CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET; |
| 31 | } | 31 | } |
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c index 887cb21f75b0..05f1739ee127 100644 --- a/arch/arm/mach-imx/generic.c +++ b/arch/arm/mach-imx/generic.c | |||
| @@ -29,7 +29,6 @@ | |||
| 29 | #include <linux/string.h> | 29 | #include <linux/string.h> |
| 30 | 30 | ||
| 31 | #include <asm/errno.h> | 31 | #include <asm/errno.h> |
| 32 | #include <mach/imxfb.h> | ||
| 33 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 34 | #include <mach/imx-regs.h> | 33 | #include <mach/imx-regs.h> |
| 35 | 34 | ||
| @@ -245,43 +244,8 @@ void __init imx_set_mmc_info(struct imxmmc_platform_data *info) | |||
| 245 | imx_mmc_device.dev.platform_data = info; | 244 | imx_mmc_device.dev.platform_data = info; |
| 246 | } | 245 | } |
| 247 | 246 | ||
| 248 | static struct imx_fb_platform_data imx_fb_info; | ||
| 249 | |||
| 250 | void __init set_imx_fb_info(struct imx_fb_platform_data *hard_imx_fb_info) | ||
| 251 | { | ||
| 252 | memcpy(&imx_fb_info,hard_imx_fb_info,sizeof(struct imx_fb_platform_data)); | ||
| 253 | } | ||
| 254 | |||
| 255 | static struct resource imxfb_resources[] = { | ||
| 256 | [0] = { | ||
| 257 | .start = 0x00205000, | ||
| 258 | .end = 0x002050FF, | ||
| 259 | .flags = IORESOURCE_MEM, | ||
| 260 | }, | ||
| 261 | [1] = { | ||
| 262 | .start = LCDC_INT, | ||
| 263 | .end = LCDC_INT, | ||
| 264 | .flags = IORESOURCE_IRQ, | ||
| 265 | }, | ||
| 266 | }; | ||
| 267 | |||
| 268 | static u64 fb_dma_mask = ~(u64)0; | ||
| 269 | |||
| 270 | static struct platform_device imxfb_device = { | ||
| 271 | .name = "imx-fb", | ||
| 272 | .id = 0, | ||
| 273 | .dev = { | ||
| 274 | .platform_data = &imx_fb_info, | ||
| 275 | .dma_mask = &fb_dma_mask, | ||
| 276 | .coherent_dma_mask = 0xffffffff, | ||
| 277 | }, | ||
| 278 | .num_resources = ARRAY_SIZE(imxfb_resources), | ||
| 279 | .resource = imxfb_resources, | ||
| 280 | }; | ||
| 281 | |||
| 282 | static struct platform_device *devices[] __initdata = { | 247 | static struct platform_device *devices[] __initdata = { |
| 283 | &imx_mmc_device, | 248 | &imx_mmc_device, |
| 284 | &imxfb_device, | ||
| 285 | }; | 249 | }; |
| 286 | 250 | ||
| 287 | static struct map_desc imx_io_desc[] __initdata = { | 251 | static struct map_desc imx_io_desc[] __initdata = { |
diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-imx/include/mach/system.h index adee7e51bab2..46d4ca91af79 100644 --- a/arch/arm/mach-imx/include/mach/system.h +++ b/arch/arm/mach-imx/include/mach/system.h | |||
| @@ -32,7 +32,7 @@ arch_idle(void) | |||
| 32 | } | 32 | } |
| 33 | 33 | ||
| 34 | static inline void | 34 | static inline void |
| 35 | arch_reset(char mode) | 35 | arch_reset(char mode, const char *cmd) |
| 36 | { | 36 | { |
| 37 | cpu_reset(0); | 37 | cpu_reset(0); |
| 38 | } | 38 | } |
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h index c485345c8c77..e1551b8dab77 100644 --- a/arch/arm/mach-integrator/include/mach/system.h +++ b/arch/arm/mach-integrator/include/mach/system.h | |||
| @@ -32,7 +32,7 @@ static inline void arch_idle(void) | |||
| 32 | cpu_do_idle(); | 32 | cpu_do_idle(); |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | static inline void arch_reset(char mode) | 35 | static inline void arch_reset(char mode, const char *cmd) |
| 36 | { | 36 | { |
| 37 | /* | 37 | /* |
| 38 | * To reset, we hit the on-board reset register | 38 | * To reset, we hit the on-board reset register |
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index e012bf13c955..42ae29b288a1 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h | |||
| @@ -59,7 +59,10 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) | |||
| 59 | }) | 59 | }) |
| 60 | 60 | ||
| 61 | #define __arch_page_to_dma(dev, page) \ | 61 | #define __arch_page_to_dma(dev, page) \ |
| 62 | __arch_virt_to_dma(dev, page_address(page)) | 62 | ({ \ |
| 63 | /* __is_lbus_virt() can never be true for RAM pages */ \ | ||
| 64 | (dma_addr_t)page_to_phys(page); \ | ||
| 65 | }) | ||
| 63 | 66 | ||
| 64 | #endif /* CONFIG_ARCH_IOP13XX */ | 67 | #endif /* CONFIG_ARCH_IOP13XX */ |
| 65 | #endif /* !ASSEMBLY */ | 68 | #endif /* !ASSEMBLY */ |
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h index c7127f416e1f..d0c66ef450a7 100644 --- a/arch/arm/mach-iop13xx/include/mach/system.h +++ b/arch/arm/mach-iop13xx/include/mach/system.h | |||
| @@ -13,7 +13,7 @@ static inline void arch_idle(void) | |||
| 13 | cpu_do_idle(); | 13 | cpu_do_idle(); |
| 14 | } | 14 | } |
| 15 | 15 | ||
| 16 | static inline void arch_reset(char mode) | 16 | static inline void arch_reset(char mode, const char *cmd) |
| 17 | { | 17 | { |
| 18 | /* | 18 | /* |
| 19 | * Reset the internal bus (warning both cores are reset) | 19 | * Reset the internal bus (warning both cores are reset) |
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 673b0db22034..4873f26a42e1 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c | |||
| @@ -1026,8 +1026,10 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
| 1026 | which_atu = 0; | 1026 | which_atu = 0; |
| 1027 | } | 1027 | } |
| 1028 | 1028 | ||
| 1029 | if (!which_atu) | 1029 | if (!which_atu) { |
| 1030 | kfree(res); | ||
| 1030 | return 0; | 1031 | return 0; |
| 1032 | } | ||
| 1031 | 1033 | ||
| 1032 | switch(which_atu) { | 1034 | switch(which_atu) { |
| 1033 | case IOP13XX_INIT_ATU_ATUX: | 1035 | case IOP13XX_INIT_ATU_ATUX: |
| @@ -1074,6 +1076,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) | |||
| 1074 | sys->map_irq = iop13xx_pcie_map_irq; | 1076 | sys->map_irq = iop13xx_pcie_map_irq; |
| 1075 | break; | 1077 | break; |
| 1076 | default: | 1078 | default: |
| 1079 | kfree(res); | ||
| 1077 | return 0; | 1080 | return 0; |
| 1078 | } | 1081 | } |
| 1079 | 1082 | ||
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h index 32d9e5b0a28d..a4b808fe0d81 100644 --- a/arch/arm/mach-iop32x/include/mach/system.h +++ b/arch/arm/mach-iop32x/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static inline void arch_idle(void) | |||
| 16 | cpu_do_idle(); | 16 | cpu_do_idle(); |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static inline void arch_reset(char mode) | 19 | static inline void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | local_irq_disable(); | 21 | local_irq_disable(); |
| 22 | 22 | ||
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h index 0cb3ad862acd..f192a34be073 100644 --- a/arch/arm/mach-iop33x/include/mach/system.h +++ b/arch/arm/mach-iop33x/include/mach/system.h | |||
| @@ -14,7 +14,7 @@ static inline void arch_idle(void) | |||
| 14 | cpu_do_idle(); | 14 | cpu_do_idle(); |
| 15 | } | 15 | } |
| 16 | 16 | ||
| 17 | static inline void arch_reset(char mode) | 17 | static inline void arch_reset(char mode, const char *cmd) |
| 18 | { | 18 | { |
| 19 | *IOP3XX_PCSR = 0x30; | 19 | *IOP3XX_PCSR = 0x30; |
| 20 | 20 | ||
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h index 2e9c68f95a24..de370992c848 100644 --- a/arch/arm/mach-ixp2000/include/mach/system.h +++ b/arch/arm/mach-ixp2000/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | local_irq_disable(); | 22 | local_irq_disable(); |
| 23 | 23 | ||
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h index d57c3fc10f1f..8920ff2dff1f 100644 --- a/arch/arm/mach-ixp23xx/include/mach/system.h +++ b/arch/arm/mach-ixp23xx/include/mach/system.h | |||
| @@ -19,7 +19,7 @@ static inline void arch_idle(void) | |||
| 19 | #endif | 19 | #endif |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | static inline void arch_reset(char mode) | 22 | static inline void arch_reset(char mode, const char *cmd) |
| 23 | { | 23 | { |
| 24 | /* First try machine specific support */ | 24 | /* First try machine specific support */ |
| 25 | if (machine_is_ixdp2351()) { | 25 | if (machine_is_ixdp2351()) { |
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index d816c51320c7..70afcfe5b881 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c | |||
| @@ -366,7 +366,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, | |||
| 366 | } | 366 | } |
| 367 | 367 | ||
| 368 | void __init ixp4xx_pci_preinit(void) | 368 | void __init ixp4xx_pci_preinit(void) |
| 369 | { | 369 | { |
| 370 | unsigned long cpuid = read_cpuid_id(); | 370 | unsigned long cpuid = read_cpuid_id(); |
| 371 | 371 | ||
| 372 | /* | 372 | /* |
| @@ -386,17 +386,17 @@ void __init ixp4xx_pci_preinit(void) | |||
| 386 | 386 | ||
| 387 | pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); | 387 | pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); |
| 388 | 388 | ||
| 389 | /* | 389 | /* |
| 390 | * We use identity AHB->PCI address translation | 390 | * We use identity AHB->PCI address translation |
| 391 | * in the 0x48000000 to 0x4bffffff address space | 391 | * in the 0x48000000 to 0x4bffffff address space |
| 392 | */ | 392 | */ |
| 393 | *PCI_PCIMEMBASE = 0x48494A4B; | 393 | *PCI_PCIMEMBASE = 0x48494A4B; |
| 394 | 394 | ||
| 395 | /* | 395 | /* |
| 396 | * We also use identity PCI->AHB address translation | 396 | * We also use identity PCI->AHB address translation |
| 397 | * in 4 16MB BARs that begin at the physical memory start | 397 | * in 4 16MB BARs that begin at the physical memory start |
| 398 | */ | 398 | */ |
| 399 | *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + | 399 | *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + |
| 400 | ((PHYS_OFFSET & 0xFF000000) >> 8) + | 400 | ((PHYS_OFFSET & 0xFF000000) >> 8) + |
| 401 | ((PHYS_OFFSET & 0xFF000000) >> 16) + | 401 | ((PHYS_OFFSET & 0xFF000000) >> 16) + |
| 402 | ((PHYS_OFFSET & 0xFF000000) >> 24) + | 402 | ((PHYS_OFFSET & 0xFF000000) >> 24) + |
| @@ -408,18 +408,19 @@ void __init ixp4xx_pci_preinit(void) | |||
| 408 | pr_debug("setup BARs in controller\n"); | 408 | pr_debug("setup BARs in controller\n"); |
| 409 | 409 | ||
| 410 | /* | 410 | /* |
| 411 | * We configure the PCI inbound memory windows to be | 411 | * We configure the PCI inbound memory windows to be |
| 412 | * 1:1 mapped to SDRAM | 412 | * 1:1 mapped to SDRAM |
| 413 | */ | 413 | */ |
| 414 | local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000); | 414 | local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); |
| 415 | local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000); | 415 | local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); |
| 416 | local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000); | 416 | local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); |
| 417 | local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000); | 417 | local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M); |
| 418 | 418 | ||
| 419 | /* | 419 | /* |
| 420 | * Enable CSR window at 0xff000000. | 420 | * Enable CSR window at 64 MiB to allow PCI masters |
| 421 | * to continue prefetching past 64 MiB boundary. | ||
| 421 | */ | 422 | */ |
| 422 | local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008); | 423 | local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M); |
| 423 | 424 | ||
| 424 | /* | 425 | /* |
| 425 | * Enable the IO window to be way up high, at 0xfffffc00 | 426 | * Enable the IO window to be way up high, at 0xfffffc00 |
| @@ -500,7 +501,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) | |||
| 500 | return 1; | 501 | return 1; |
| 501 | } | 502 | } |
| 502 | 503 | ||
| 503 | struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) | 504 | struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) |
| 504 | { | 505 | { |
| 505 | return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); | 506 | return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); |
| 506 | } | 507 | } |
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h index 51bd69c46d94..def7773be67c 100644 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h | |||
| @@ -17,26 +17,31 @@ | |||
| 17 | #include <asm/cputype.h> | 17 | #include <asm/cputype.h> |
| 18 | 18 | ||
| 19 | /* Processor id value in CP15 Register 0 */ | 19 | /* Processor id value in CP15 Register 0 */ |
| 20 | #define IXP425_PROCESSOR_ID_VALUE 0x690541c0 | 20 | #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */ |
| 21 | #define IXP435_PROCESSOR_ID_VALUE 0x69054040 | 21 | #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0 |
| 22 | #define IXP465_PROCESSOR_ID_VALUE 0x69054200 | 22 | |
| 23 | #define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 | 23 | #define IXP43X_PROCESSOR_ID_VALUE 0x69054040 |
| 24 | 24 | #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0 | |
| 25 | #define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 25 | |
| 26 | IXP425_PROCESSOR_ID_VALUE) | 26 | #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ |
| 27 | #define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 27 | #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 |
| 28 | IXP435_PROCESSOR_ID_VALUE) | 28 | |
| 29 | #define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 29 | #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ |
| 30 | IXP465_PROCESSOR_ID_VALUE) | 30 | IXP42X_PROCESSOR_ID_VALUE) |
| 31 | #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ | ||
| 32 | IXP43X_PROCESSOR_ID_VALUE) | ||
| 33 | #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ | ||
| 34 | IXP46X_PROCESSOR_ID_VALUE) | ||
| 31 | 35 | ||
| 32 | static inline u32 ixp4xx_read_feature_bits(void) | 36 | static inline u32 ixp4xx_read_feature_bits(void) |
| 33 | { | 37 | { |
| 34 | unsigned int val = ~*IXP4XX_EXP_CFG2; | 38 | unsigned int val = ~*IXP4XX_EXP_CFG2; |
| 35 | val &= ~IXP4XX_FEATURE_RESERVED; | ||
| 36 | if (!cpu_is_ixp46x()) | ||
| 37 | val &= ~IXP4XX_FEATURE_IXP46X_ONLY; | ||
| 38 | 39 | ||
| 39 | return val; | 40 | if (cpu_is_ixp42x()) |
| 41 | return val & IXP42X_FEATURE_MASK; | ||
| 42 | if (cpu_is_ixp43x()) | ||
| 43 | return val & IXP43X_FEATURE_MASK; | ||
| 44 | return val & IXP46X_FEATURE_MASK; | ||
| 40 | } | 45 | } |
| 41 | 46 | ||
| 42 | static inline void ixp4xx_write_feature_bits(u32 value) | 47 | static inline void ixp4xx_write_feature_bits(u32 value) |
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index ad9c888dd850..97c530f66e78 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | |||
| @@ -604,6 +604,7 @@ | |||
| 604 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | 604 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
| 605 | 605 | ||
| 606 | /* "fuse" bits of IXP_EXP_CFG2 */ | 606 | /* "fuse" bits of IXP_EXP_CFG2 */ |
| 607 | /* All IXP4xx CPUs */ | ||
| 607 | #define IXP4XX_FEATURE_RCOMP (1 << 0) | 608 | #define IXP4XX_FEATURE_RCOMP (1 << 0) |
| 608 | #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) | 609 | #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) |
| 609 | #define IXP4XX_FEATURE_HASH (1 << 2) | 610 | #define IXP4XX_FEATURE_HASH (1 << 2) |
| @@ -619,20 +620,41 @@ | |||
| 619 | #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) | 620 | #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) |
| 620 | #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) | 621 | #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) |
| 621 | #define IXP4XX_FEATURE_PCI (1 << 14) | 622 | #define IXP4XX_FEATURE_PCI (1 << 14) |
| 622 | #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) | ||
| 623 | #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) | 623 | #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) |
| 624 | #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) | ||
| 625 | #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ | ||
| 626 | IXP4XX_FEATURE_USB_DEVICE | \ | ||
| 627 | IXP4XX_FEATURE_HASH | \ | ||
| 628 | IXP4XX_FEATURE_AES | \ | ||
| 629 | IXP4XX_FEATURE_DES | \ | ||
| 630 | IXP4XX_FEATURE_HDLC | \ | ||
| 631 | IXP4XX_FEATURE_AAL | \ | ||
| 632 | IXP4XX_FEATURE_HSS | \ | ||
| 633 | IXP4XX_FEATURE_UTOPIA | \ | ||
| 634 | IXP4XX_FEATURE_NPEB_ETH0 | \ | ||
| 635 | IXP4XX_FEATURE_NPEC_ETH | \ | ||
| 636 | IXP4XX_FEATURE_RESET_NPEA | \ | ||
| 637 | IXP4XX_FEATURE_RESET_NPEB | \ | ||
| 638 | IXP4XX_FEATURE_RESET_NPEC | \ | ||
| 639 | IXP4XX_FEATURE_PCI | \ | ||
| 640 | IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ | ||
| 641 | IXP4XX_FEATURE_XSCALE_MAX_FREQ) | ||
| 642 | |||
| 643 | |||
| 644 | /* IXP43x/46x CPUs */ | ||
| 645 | #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) | ||
| 624 | #define IXP4XX_FEATURE_USB_HOST (1 << 18) | 646 | #define IXP4XX_FEATURE_USB_HOST (1 << 18) |
| 625 | #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) | 647 | #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) |
| 648 | #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ | ||
| 649 | IXP4XX_FEATURE_ECC_TIMESYNC | \ | ||
| 650 | IXP4XX_FEATURE_USB_HOST | \ | ||
| 651 | IXP4XX_FEATURE_NPEA_ETH) | ||
| 652 | |||
| 653 | /* IXP46x CPU (including IXP455) only */ | ||
| 626 | #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) | 654 | #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) |
| 627 | #define IXP4XX_FEATURE_RSA (1 << 21) | 655 | #define IXP4XX_FEATURE_RSA (1 << 21) |
| 628 | #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) | 656 | #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ |
| 629 | #define IXP4XX_FEATURE_RESERVED (0xFF << 24) | 657 | IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ |
| 630 | 658 | IXP4XX_FEATURE_RSA) | |
| 631 | #define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ | ||
| 632 | IXP4XX_FEATURE_USB_HOST | \ | ||
| 633 | IXP4XX_FEATURE_NPEA_ETH | \ | ||
| 634 | IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ | ||
| 635 | IXP4XX_FEATURE_RSA | \ | ||
| 636 | IXP4XX_FEATURE_XSCALE_MAX_FREQ) | ||
| 637 | 659 | ||
| 638 | #endif | 660 | #endif |
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h index 92a7e8ddf69a..d2aa26f5acd7 100644 --- a/arch/arm/mach-ixp4xx/include/mach/system.h +++ b/arch/arm/mach-ixp4xx/include/mach/system.h | |||
| @@ -20,7 +20,7 @@ static inline void arch_idle(void) | |||
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | 22 | ||
| 23 | static inline void arch_reset(char mode) | 23 | static inline void arch_reset(char mode, const char *cmd) |
| 24 | { | 24 | { |
| 25 | if ( 1 && mode == 's') { | 25 | if ( 1 && mode == 's') { |
| 26 | /* Jump into ROM at address 0 */ | 26 | /* Jump into ROM at address 0 */ |
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c index c73a94d0ca2b..252310234903 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c | |||
| @@ -575,8 +575,8 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) | |||
| 575 | for (i = 0; i < image->size; i++) | 575 | for (i = 0; i < image->size; i++) |
| 576 | image->data[i] = swab32(image->data[i]); | 576 | image->data[i] = swab32(image->data[i]); |
| 577 | 577 | ||
| 578 | if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) { | 578 | if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) { |
| 579 | print_npe(KERN_INFO, npe, "IXP46x firmware ignored on " | 579 | print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on " |
| 580 | "IXP42x\n"); | 580 | "IXP42x\n"); |
| 581 | goto err; | 581 | goto err; |
| 582 | } | 582 | } |
| @@ -596,7 +596,7 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) | |||
| 596 | "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, | 596 | "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, |
| 597 | (image->id >> 8) & 0xFF, image->id & 0xFF); | 597 | (image->id >> 8) & 0xFF, image->id & 0xFF); |
| 598 | 598 | ||
| 599 | if (!cpu_is_ixp46x()) { | 599 | if (cpu_is_ixp42x()) { |
| 600 | if (!npe->id) | 600 | if (!npe->id) |
| 601 | instr_size = NPE_A_42X_INSTR_SIZE; | 601 | instr_size = NPE_A_42X_INSTR_SIZE; |
| 602 | else | 602 | else |
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 3600cd9f0519..b5421cccd7e1 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig | |||
| @@ -20,6 +20,18 @@ config MACH_RD88F6281 | |||
| 20 | Say 'Y' here if you want your kernel to support the | 20 | Say 'Y' here if you want your kernel to support the |
| 21 | Marvell RD-88F6281 Reference Board. | 21 | Marvell RD-88F6281 Reference Board. |
| 22 | 22 | ||
| 23 | config MACH_SHEEVAPLUG | ||
| 24 | bool "Marvell SheevaPlug Reference Board" | ||
| 25 | help | ||
| 26 | Say 'Y' here if you want your kernel to support the | ||
| 27 | Marvell SheevaPlug Reference Board. | ||
| 28 | |||
| 29 | config MACH_TS219 | ||
| 30 | bool "QNAP TS-119 and TS-219 Turbo NAS" | ||
| 31 | help | ||
| 32 | Say 'Y' here if you want your kernel to support the | ||
| 33 | QNAP TS-119 and TS-219 Turbo NAS devices. | ||
| 34 | |||
| 23 | endmenu | 35 | endmenu |
| 24 | 36 | ||
| 25 | endif | 37 | endif |
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index b96c55dad343..8f03c9b9bdd9 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile | |||
| @@ -1,5 +1,7 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o pcie.o | 1 | obj-y += common.o addr-map.o irq.o pcie.o mpp.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o | 3 | obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o |
| 4 | obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o | 4 | obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o |
| 5 | obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o | 5 | obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o |
| 6 | obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o | ||
| 7 | obj-$(CONFIG_MACH_TS219) += ts219-setup.o | ||
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 0d2074f51a59..3d2fae846512 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/serial_8250.h> | 14 | #include <linux/serial_8250.h> |
| 15 | #include <linux/mbus.h> | 15 | #include <linux/mbus.h> |
| 16 | #include <linux/mv643xx_eth.h> | 16 | #include <linux/mv643xx_eth.h> |
| 17 | #include <linux/mv643xx_i2c.h> | ||
| 17 | #include <linux/ata_platform.h> | 18 | #include <linux/ata_platform.h> |
| 18 | #include <linux/spi/orion_spi.h> | 19 | #include <linux/spi/orion_spi.h> |
| 19 | #include <net/dsa.h> | 20 | #include <net/dsa.h> |
| @@ -24,6 +25,7 @@ | |||
| 24 | #include <mach/kirkwood.h> | 25 | #include <mach/kirkwood.h> |
| 25 | #include <plat/cache-feroceon-l2.h> | 26 | #include <plat/cache-feroceon-l2.h> |
| 26 | #include <plat/ehci-orion.h> | 27 | #include <plat/ehci-orion.h> |
| 28 | #include <plat/mvsdio.h> | ||
| 27 | #include <plat/mv_xor.h> | 29 | #include <plat/mv_xor.h> |
| 28 | #include <plat/orion_nand.h> | 30 | #include <plat/orion_nand.h> |
| 29 | #include <plat/time.h> | 31 | #include <plat/time.h> |
| @@ -257,7 +259,7 @@ static struct resource kirkwood_rtc_resource = { | |||
| 257 | .flags = IORESOURCE_MEM, | 259 | .flags = IORESOURCE_MEM, |
| 258 | }; | 260 | }; |
| 259 | 261 | ||
| 260 | void __init kirkwood_rtc_init(void) | 262 | static void __init kirkwood_rtc_init(void) |
| 261 | { | 263 | { |
| 262 | platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); | 264 | platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); |
| 263 | } | 265 | } |
| @@ -299,6 +301,50 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) | |||
| 299 | 301 | ||
| 300 | 302 | ||
| 301 | /***************************************************************************** | 303 | /***************************************************************************** |
| 304 | * SD/SDIO/MMC | ||
| 305 | ****************************************************************************/ | ||
| 306 | static struct resource mvsdio_resources[] = { | ||
| 307 | [0] = { | ||
| 308 | .start = SDIO_PHYS_BASE, | ||
| 309 | .end = SDIO_PHYS_BASE + SZ_1K - 1, | ||
| 310 | .flags = IORESOURCE_MEM, | ||
| 311 | }, | ||
| 312 | [1] = { | ||
| 313 | .start = IRQ_KIRKWOOD_SDIO, | ||
| 314 | .end = IRQ_KIRKWOOD_SDIO, | ||
| 315 | .flags = IORESOURCE_IRQ, | ||
| 316 | }, | ||
| 317 | }; | ||
| 318 | |||
| 319 | static u64 mvsdio_dmamask = 0xffffffffUL; | ||
| 320 | |||
| 321 | static struct platform_device kirkwood_sdio = { | ||
| 322 | .name = "mvsdio", | ||
| 323 | .id = -1, | ||
| 324 | .dev = { | ||
| 325 | .dma_mask = &mvsdio_dmamask, | ||
| 326 | .coherent_dma_mask = 0xffffffff, | ||
| 327 | }, | ||
| 328 | .num_resources = ARRAY_SIZE(mvsdio_resources), | ||
| 329 | .resource = mvsdio_resources, | ||
| 330 | }; | ||
| 331 | |||
| 332 | void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) | ||
| 333 | { | ||
| 334 | u32 dev, rev; | ||
| 335 | |||
| 336 | kirkwood_pcie_id(&dev, &rev); | ||
| 337 | if (rev == 0) /* catch all Kirkwood Z0's */ | ||
| 338 | mvsdio_data->clock = 100000000; | ||
| 339 | else | ||
| 340 | mvsdio_data->clock = 200000000; | ||
| 341 | mvsdio_data->dram = &kirkwood_mbus_dram_info; | ||
| 342 | kirkwood_sdio.dev.platform_data = mvsdio_data; | ||
| 343 | platform_device_register(&kirkwood_sdio); | ||
| 344 | } | ||
| 345 | |||
| 346 | |||
| 347 | /***************************************************************************** | ||
| 302 | * SPI | 348 | * SPI |
| 303 | ****************************************************************************/ | 349 | ****************************************************************************/ |
| 304 | static struct orion_spi_info kirkwood_spi_plat_data = { | 350 | static struct orion_spi_info kirkwood_spi_plat_data = { |
| @@ -329,6 +375,45 @@ void __init kirkwood_spi_init() | |||
| 329 | 375 | ||
| 330 | 376 | ||
| 331 | /***************************************************************************** | 377 | /***************************************************************************** |
| 378 | * I2C | ||
| 379 | ****************************************************************************/ | ||
| 380 | static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = { | ||
| 381 | .freq_m = 8, /* assumes 166 MHz TCLK */ | ||
| 382 | .freq_n = 3, | ||
| 383 | .timeout = 1000, /* Default timeout of 1 second */ | ||
| 384 | }; | ||
| 385 | |||
| 386 | static struct resource kirkwood_i2c_resources[] = { | ||
| 387 | { | ||
| 388 | .name = "i2c", | ||
| 389 | .start = I2C_PHYS_BASE, | ||
| 390 | .end = I2C_PHYS_BASE + 0x1f, | ||
| 391 | .flags = IORESOURCE_MEM, | ||
| 392 | }, { | ||
| 393 | .name = "i2c", | ||
| 394 | .start = IRQ_KIRKWOOD_TWSI, | ||
| 395 | .end = IRQ_KIRKWOOD_TWSI, | ||
| 396 | .flags = IORESOURCE_IRQ, | ||
| 397 | }, | ||
| 398 | }; | ||
| 399 | |||
| 400 | static struct platform_device kirkwood_i2c = { | ||
| 401 | .name = MV64XXX_I2C_CTLR_NAME, | ||
| 402 | .id = 0, | ||
| 403 | .num_resources = ARRAY_SIZE(kirkwood_i2c_resources), | ||
| 404 | .resource = kirkwood_i2c_resources, | ||
| 405 | .dev = { | ||
| 406 | .platform_data = &kirkwood_i2c_pdata, | ||
| 407 | }, | ||
| 408 | }; | ||
| 409 | |||
| 410 | void __init kirkwood_i2c_init(void) | ||
| 411 | { | ||
| 412 | platform_device_register(&kirkwood_i2c); | ||
| 413 | } | ||
| 414 | |||
| 415 | |||
| 416 | /***************************************************************************** | ||
| 332 | * UART0 | 417 | * UART0 |
| 333 | ****************************************************************************/ | 418 | ****************************************************************************/ |
| 334 | static struct plat_serial8250_port kirkwood_uart0_data[] = { | 419 | static struct plat_serial8250_port kirkwood_uart0_data[] = { |
| @@ -505,7 +590,7 @@ static struct platform_device kirkwood_xor01_channel = { | |||
| 505 | }, | 590 | }, |
| 506 | }; | 591 | }; |
| 507 | 592 | ||
| 508 | void __init kirkwood_xor0_init(void) | 593 | static void __init kirkwood_xor0_init(void) |
| 509 | { | 594 | { |
| 510 | platform_device_register(&kirkwood_xor0_shared); | 595 | platform_device_register(&kirkwood_xor0_shared); |
| 511 | 596 | ||
| @@ -603,7 +688,7 @@ static struct platform_device kirkwood_xor11_channel = { | |||
| 603 | }, | 688 | }, |
| 604 | }; | 689 | }; |
| 605 | 690 | ||
| 606 | void __init kirkwood_xor1_init(void) | 691 | static void __init kirkwood_xor1_init(void) |
| 607 | { | 692 | { |
| 608 | platform_device_register(&kirkwood_xor1_shared); | 693 | platform_device_register(&kirkwood_xor1_shared); |
| 609 | 694 | ||
| @@ -711,4 +796,9 @@ void __init kirkwood_init(void) | |||
| 711 | #ifdef CONFIG_CACHE_FEROCEON_L2 | 796 | #ifdef CONFIG_CACHE_FEROCEON_L2 |
| 712 | kirkwood_l2_init(); | 797 | kirkwood_l2_init(); |
| 713 | #endif | 798 | #endif |
| 799 | |||
| 800 | /* internal devices that every board has */ | ||
| 801 | kirkwood_rtc_init(); | ||
| 802 | kirkwood_xor0_init(); | ||
| 803 | kirkwood_xor1_init(); | ||
| 714 | } | 804 | } |
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index fe367c18e722..6ee88406f381 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | struct dsa_platform_data; | 14 | struct dsa_platform_data; |
| 15 | struct mv643xx_eth_platform_data; | 15 | struct mv643xx_eth_platform_data; |
| 16 | struct mv_sata_platform_data; | 16 | struct mv_sata_platform_data; |
| 17 | struct mvsdio_platform_data; | ||
| 17 | 18 | ||
| 18 | /* | 19 | /* |
| 19 | * Basic Kirkwood init functions used early by machine-setup. | 20 | * Basic Kirkwood init functions used early by machine-setup. |
| @@ -33,14 +34,14 @@ void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); | |||
| 33 | void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); | 34 | void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); |
| 34 | void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); | 35 | void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); |
| 35 | void kirkwood_pcie_init(void); | 36 | void kirkwood_pcie_init(void); |
| 36 | void kirkwood_rtc_init(void); | ||
| 37 | void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); | 37 | void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); |
| 38 | void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data); | ||
| 38 | void kirkwood_spi_init(void); | 39 | void kirkwood_spi_init(void); |
| 40 | void kirkwood_i2c_init(void); | ||
| 39 | void kirkwood_uart0_init(void); | 41 | void kirkwood_uart0_init(void); |
| 40 | void kirkwood_uart1_init(void); | 42 | void kirkwood_uart1_init(void); |
| 41 | void kirkwood_xor0_init(void); | ||
| 42 | void kirkwood_xor1_init(void); | ||
| 43 | 43 | ||
| 44 | extern int kirkwood_tclk; | ||
| 44 | extern struct sys_timer kirkwood_timer; | 45 | extern struct sys_timer kirkwood_timer; |
| 45 | 46 | ||
| 46 | 47 | ||
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index a14c2948c62a..5505d5837752 100644 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c | |||
| @@ -11,18 +11,59 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/nand.h> | 14 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/timer.h> | 15 | #include <linux/mtd/partitions.h> |
| 19 | #include <linux/ata_platform.h> | 16 | #include <linux/ata_platform.h> |
| 20 | #include <linux/mv643xx_eth.h> | 17 | #include <linux/mv643xx_eth.h> |
| 21 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 22 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/pci.h> | ||
| 24 | #include <mach/kirkwood.h> | 20 | #include <mach/kirkwood.h> |
| 21 | #include <plat/orion_nand.h> | ||
| 22 | #include <plat/mvsdio.h> | ||
| 25 | #include "common.h" | 23 | #include "common.h" |
| 24 | #include "mpp.h" | ||
| 25 | |||
| 26 | static struct mtd_partition db88f6281_nand_parts[] = { | ||
| 27 | { | ||
| 28 | .name = "u-boot", | ||
| 29 | .offset = 0, | ||
| 30 | .size = SZ_1M | ||
| 31 | }, { | ||
| 32 | .name = "uImage", | ||
| 33 | .offset = MTDPART_OFS_NXTBLK, | ||
| 34 | .size = SZ_4M | ||
| 35 | }, { | ||
| 36 | .name = "root", | ||
| 37 | .offset = MTDPART_OFS_NXTBLK, | ||
| 38 | .size = MTDPART_SIZ_FULL | ||
| 39 | }, | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct resource db88f6281_nand_resource = { | ||
| 43 | .flags = IORESOURCE_MEM, | ||
| 44 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | ||
| 45 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | ||
| 46 | KIRKWOOD_NAND_MEM_SIZE - 1, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct orion_nand_data db88f6281_nand_data = { | ||
| 50 | .parts = db88f6281_nand_parts, | ||
| 51 | .nr_parts = ARRAY_SIZE(db88f6281_nand_parts), | ||
| 52 | .cle = 0, | ||
| 53 | .ale = 1, | ||
| 54 | .width = 8, | ||
| 55 | .chip_delay = 25, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct platform_device db88f6281_nand_flash = { | ||
| 59 | .name = "orion_nand", | ||
| 60 | .id = -1, | ||
| 61 | .dev = { | ||
| 62 | .platform_data = &db88f6281_nand_data, | ||
| 63 | }, | ||
| 64 | .resource = &db88f6281_nand_resource, | ||
| 65 | .num_resources = 1, | ||
| 66 | }; | ||
| 26 | 67 | ||
| 27 | static struct mv643xx_eth_platform_data db88f6281_ge00_data = { | 68 | static struct mv643xx_eth_platform_data db88f6281_ge00_data = { |
| 28 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | 69 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), |
| @@ -32,18 +73,32 @@ static struct mv_sata_platform_data db88f6281_sata_data = { | |||
| 32 | .n_ports = 2, | 73 | .n_ports = 2, |
| 33 | }; | 74 | }; |
| 34 | 75 | ||
| 76 | static struct mvsdio_platform_data db88f6281_mvsdio_data = { | ||
| 77 | .gpio_write_protect = 37, | ||
| 78 | .gpio_card_detect = 38, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static unsigned int db88f6281_mpp_config[] __initdata = { | ||
| 82 | MPP37_GPIO, | ||
| 83 | MPP38_GPIO, | ||
| 84 | 0 | ||
| 85 | }; | ||
| 86 | |||
| 35 | static void __init db88f6281_init(void) | 87 | static void __init db88f6281_init(void) |
| 36 | { | 88 | { |
| 37 | /* | 89 | /* |
| 38 | * Basic setup. Needs to be called early. | 90 | * Basic setup. Needs to be called early. |
| 39 | */ | 91 | */ |
| 40 | kirkwood_init(); | 92 | kirkwood_init(); |
| 93 | kirkwood_mpp_conf(db88f6281_mpp_config); | ||
| 41 | 94 | ||
| 42 | kirkwood_ehci_init(); | 95 | kirkwood_ehci_init(); |
| 43 | kirkwood_ge00_init(&db88f6281_ge00_data); | 96 | kirkwood_ge00_init(&db88f6281_ge00_data); |
| 44 | kirkwood_rtc_init(); | ||
| 45 | kirkwood_sata_init(&db88f6281_sata_data); | 97 | kirkwood_sata_init(&db88f6281_sata_data); |
| 46 | kirkwood_uart0_init(); | 98 | kirkwood_uart0_init(); |
| 99 | kirkwood_sdio_init(&db88f6281_mvsdio_data); | ||
| 100 | |||
| 101 | platform_device_register(&db88f6281_nand_flash); | ||
| 47 | } | 102 | } |
| 48 | 103 | ||
| 49 | static int __init db88f6281_pci_init(void) | 104 | static int __init db88f6281_pci_init(void) |
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index ada480c0e197..38c986853590 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h | |||
| @@ -93,6 +93,7 @@ | |||
| 93 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) | 93 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) |
| 94 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) | 94 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) |
| 95 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) | 95 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) |
| 96 | #define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) | ||
| 96 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | 97 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 97 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | 98 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) |
| 98 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 99 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
| @@ -116,5 +117,7 @@ | |||
| 116 | 117 | ||
| 117 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) | 118 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) |
| 118 | 119 | ||
| 120 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) | ||
| 121 | |||
| 119 | 122 | ||
| 120 | #endif | 123 | #endif |
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h index 8510f6cfdabf..23a1914c1da8 100644 --- a/arch/arm/mach-kirkwood/include/mach/system.h +++ b/arch/arm/mach-kirkwood/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | /* | 22 | /* |
| 23 | * Enable soft reset to assert RSTOUTn. | 23 | * Enable soft reset to assert RSTOUTn. |
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c new file mode 100644 index 000000000000..63c44934391a --- /dev/null +++ b/arch/arm/mach-kirkwood/mpp.c | |||
| @@ -0,0 +1,97 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-kirkwood/mpp.c | ||
| 3 | * | ||
| 4 | * MPP functions for Marvell Kirkwood SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <asm/gpio.h> | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include "common.h" | ||
| 18 | #include "mpp.h" | ||
| 19 | |||
| 20 | static unsigned int __init kirkwood_variant(void) | ||
| 21 | { | ||
| 22 | u32 dev, rev; | ||
| 23 | |||
| 24 | kirkwood_pcie_id(&dev, &rev); | ||
| 25 | |||
| 26 | if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) | ||
| 27 | return MPP_F6281_MASK; | ||
| 28 | if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) | ||
| 29 | return MPP_F6192_MASK; | ||
| 30 | if (dev == MV88F6180_DEV_ID) | ||
| 31 | return MPP_F6180_MASK; | ||
| 32 | |||
| 33 | printk(KERN_ERR "MPP setup: unknown kirkwood variant " | ||
| 34 | "(dev %#x rev %#x)\n", dev, rev); | ||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | |||
| 38 | #define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) | ||
| 39 | #define MPP_NR_REGS (1 + MPP_MAX/8) | ||
| 40 | |||
| 41 | void __init kirkwood_mpp_conf(unsigned int *mpp_list) | ||
| 42 | { | ||
| 43 | u32 mpp_ctrl[MPP_NR_REGS]; | ||
| 44 | unsigned int variant_mask; | ||
| 45 | int i; | ||
| 46 | |||
| 47 | variant_mask = kirkwood_variant(); | ||
| 48 | if (!variant_mask) | ||
| 49 | return; | ||
| 50 | |||
| 51 | printk(KERN_DEBUG "initial MPP regs:"); | ||
| 52 | for (i = 0; i < MPP_NR_REGS; i++) { | ||
| 53 | mpp_ctrl[i] = readl(MPP_CTRL(i)); | ||
| 54 | printk(" %08x", mpp_ctrl[i]); | ||
| 55 | } | ||
| 56 | printk("\n"); | ||
| 57 | |||
| 58 | while (*mpp_list) { | ||
| 59 | unsigned int num = MPP_NUM(*mpp_list); | ||
| 60 | unsigned int sel = MPP_SEL(*mpp_list); | ||
| 61 | int shift, gpio_mode; | ||
| 62 | |||
| 63 | if (num > MPP_MAX) { | ||
| 64 | printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP " | ||
| 65 | "number (%u)\n", num); | ||
| 66 | continue; | ||
| 67 | } | ||
| 68 | if (!(*mpp_list & variant_mask)) { | ||
| 69 | printk(KERN_WARNING | ||
| 70 | "kirkwood_mpp_conf: requested MPP%u config " | ||
| 71 | "unavailable on this hardware\n", num); | ||
| 72 | continue; | ||
| 73 | } | ||
| 74 | |||
| 75 | shift = (num & 7) << 2; | ||
| 76 | mpp_ctrl[num / 8] &= ~(0xf << shift); | ||
| 77 | mpp_ctrl[num / 8] |= sel << shift; | ||
| 78 | |||
| 79 | gpio_mode = 0; | ||
| 80 | if (*mpp_list & MPP_INPUT_MASK) | ||
| 81 | gpio_mode |= GPIO_INPUT_OK; | ||
| 82 | if (*mpp_list & MPP_OUTPUT_MASK) | ||
| 83 | gpio_mode |= GPIO_OUTPUT_OK; | ||
| 84 | if (sel != 0) | ||
| 85 | gpio_mode = 0; | ||
| 86 | orion_gpio_set_valid(num, gpio_mode); | ||
| 87 | |||
| 88 | mpp_list++; | ||
| 89 | } | ||
| 90 | |||
| 91 | printk(KERN_DEBUG " final MPP regs:"); | ||
| 92 | for (i = 0; i < MPP_NR_REGS; i++) { | ||
| 93 | writel(mpp_ctrl[i], MPP_CTRL(i)); | ||
| 94 | printk(" %08x", mpp_ctrl[i]); | ||
| 95 | } | ||
| 96 | printk("\n"); | ||
| 97 | } | ||
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h new file mode 100644 index 000000000000..e021a80c2caf --- /dev/null +++ b/arch/arm/mach-kirkwood/mpp.h | |||
| @@ -0,0 +1,303 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins | ||
| 3 | * | ||
| 4 | * Copyright 2009: Marvell Technology Group Ltd. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __KIRKWOOD_MPP_H | ||
| 12 | #define __KIRKWOOD_MPP_H | ||
| 13 | |||
| 14 | #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ | ||
| 15 | /* MPP number */ ((_num) & 0xff) | \ | ||
| 16 | /* MPP select value */ (((_sel) & 0xf) << 8) | \ | ||
| 17 | /* may be input signal */ ((!!(_in)) << 12) | \ | ||
| 18 | /* may be output signal */ ((!!(_out)) << 13) | \ | ||
| 19 | /* available on F6180 */ ((!!(_F6180)) << 14) | \ | ||
| 20 | /* available on F6190 */ ((!!(_F6190)) << 15) | \ | ||
| 21 | /* available on F6192 */ ((!!(_F6192)) << 16) | \ | ||
| 22 | /* available on F6281 */ ((!!(_F6281)) << 17)) | ||
| 23 | |||
| 24 | #define MPP_NUM(x) ((x) & 0xff) | ||
| 25 | #define MPP_SEL(x) (((x) >> 8) & 0xf) | ||
| 26 | |||
| 27 | /* num sel i o 6180 6190 6192 6281 */ | ||
| 28 | |||
| 29 | #define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) | ||
| 30 | #define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) | ||
| 31 | |||
| 32 | #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) | ||
| 33 | #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) | ||
| 34 | #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) | ||
| 35 | #define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) | ||
| 36 | |||
| 37 | #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 38 | #define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 39 | #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 40 | |||
| 41 | #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 42 | #define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 43 | #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 44 | |||
| 45 | #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 46 | #define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 47 | #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 48 | |||
| 49 | #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 50 | #define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 51 | #define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 52 | |||
| 53 | #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 54 | #define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 55 | #define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 56 | #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 57 | #define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 58 | |||
| 59 | #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 60 | #define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 61 | #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 62 | #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) | ||
| 63 | #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 64 | |||
| 65 | #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) | ||
| 66 | #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 67 | #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 68 | |||
| 69 | #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 70 | #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) | ||
| 71 | #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 72 | #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 73 | |||
| 74 | #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 75 | #define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 76 | #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 77 | #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 78 | #define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) | ||
| 79 | #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 80 | #define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) | ||
| 81 | #define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 82 | |||
| 83 | #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 84 | #define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 85 | #define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 86 | #define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 87 | #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 88 | #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) | ||
| 89 | #define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 90 | |||
| 91 | #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 92 | #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 93 | #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) | ||
| 94 | #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 95 | #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) | ||
| 96 | |||
| 97 | #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 98 | #define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 99 | #define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 100 | #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) | ||
| 101 | #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) | ||
| 102 | #define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 103 | #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 104 | |||
| 105 | #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 106 | #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) | ||
| 107 | |||
| 108 | #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 109 | #define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 110 | #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 111 | |||
| 112 | #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 113 | #define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 114 | #define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 115 | #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 116 | #define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 117 | |||
| 118 | #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 119 | #define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 120 | #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 121 | #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 122 | #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) | ||
| 123 | |||
| 124 | #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 125 | #define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 126 | #define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 127 | #define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 128 | #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 129 | #define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 130 | |||
| 131 | #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 132 | #define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 133 | #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) | ||
| 134 | |||
| 135 | #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 136 | #define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 137 | |||
| 138 | #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 139 | #define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 140 | |||
| 141 | #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 142 | #define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 143 | #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 144 | #define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 145 | #define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) | ||
| 146 | #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 147 | |||
| 148 | #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 149 | #define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 150 | #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 151 | #define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 152 | #define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 153 | #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 154 | |||
| 155 | #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 156 | #define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 157 | #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 158 | #define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 159 | #define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 160 | #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 161 | |||
| 162 | #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 163 | #define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 164 | #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) | ||
| 165 | #define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 166 | #define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 167 | #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 168 | |||
| 169 | #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 170 | #define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 171 | #define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 172 | #define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 173 | #define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 174 | |||
| 175 | #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 176 | #define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 177 | #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 178 | #define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 179 | #define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 180 | |||
| 181 | #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 182 | #define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 183 | #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) | ||
| 184 | #define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 185 | #define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 186 | |||
| 187 | #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 188 | #define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 189 | #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 190 | #define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 191 | #define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) | ||
| 192 | |||
| 193 | #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 194 | #define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 195 | #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) | ||
| 196 | #define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 197 | #define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) | ||
| 198 | |||
| 199 | #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 200 | #define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 201 | #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) | ||
| 202 | #define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 203 | |||
| 204 | #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 205 | #define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 206 | #define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) | ||
| 207 | #define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 208 | |||
| 209 | #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 210 | #define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 211 | #define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) | ||
| 212 | #define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 213 | |||
| 214 | #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 215 | #define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 216 | #define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) | ||
| 217 | #define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 218 | |||
| 219 | #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 220 | #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 221 | #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 222 | |||
| 223 | #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 224 | #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 225 | #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 226 | |||
| 227 | #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 228 | #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 229 | #define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 230 | #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 231 | #define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) | ||
| 232 | |||
| 233 | #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 234 | #define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 235 | #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 236 | #define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) | ||
| 237 | |||
| 238 | #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 239 | #define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 240 | #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 241 | #define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 242 | |||
| 243 | #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 244 | #define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 245 | #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 246 | #define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 247 | |||
| 248 | #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 249 | #define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 250 | #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 251 | #define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 252 | |||
| 253 | #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 254 | #define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 255 | #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 256 | #define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 257 | |||
| 258 | #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 259 | #define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 260 | #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) | ||
| 261 | #define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 262 | |||
| 263 | #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 264 | #define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 265 | #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 266 | #define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 267 | |||
| 268 | #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 269 | #define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 270 | #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) | ||
| 271 | #define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) | ||
| 272 | |||
| 273 | #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 274 | #define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 275 | #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) | ||
| 276 | #define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) | ||
| 277 | |||
| 278 | #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 279 | #define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 280 | #define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) | ||
| 281 | |||
| 282 | #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 283 | #define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 284 | #define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) | ||
| 285 | |||
| 286 | #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 287 | #define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 288 | #define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) | ||
| 289 | |||
| 290 | #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 291 | #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 292 | #define MPP48_TDM_DTX MPP( 48. 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 293 | |||
| 294 | #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 295 | #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 296 | #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 297 | #define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) | ||
| 298 | |||
| 299 | #define MPP_MAX 49 | ||
| 300 | |||
| 301 | void kirkwood_mpp_conf(unsigned int *mpp_list); | ||
| 302 | |||
| 303 | #endif | ||
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index b1d1a87a6821..2f0e4ef3db0f 100644 --- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c | |||
| @@ -11,11 +11,8 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/nand.h> | 14 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/timer.h> | 15 | #include <linux/mtd/partitions.h> |
| 19 | #include <linux/ata_platform.h> | 16 | #include <linux/ata_platform.h> |
| 20 | #include <linux/mv643xx_eth.h> | 17 | #include <linux/mv643xx_eth.h> |
| 21 | #include <linux/spi/flash.h> | 18 | #include <linux/spi/flash.h> |
| @@ -23,7 +20,6 @@ | |||
| 23 | #include <linux/spi/orion_spi.h> | 20 | #include <linux/spi/orion_spi.h> |
| 24 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/pci.h> | ||
| 27 | #include <mach/kirkwood.h> | 23 | #include <mach/kirkwood.h> |
| 28 | #include "common.h" | 24 | #include "common.h" |
| 29 | 25 | ||
| @@ -61,14 +57,11 @@ static void __init rd88f6192_init(void) | |||
| 61 | 57 | ||
| 62 | kirkwood_ehci_init(); | 58 | kirkwood_ehci_init(); |
| 63 | kirkwood_ge00_init(&rd88f6192_ge00_data); | 59 | kirkwood_ge00_init(&rd88f6192_ge00_data); |
| 64 | kirkwood_rtc_init(); | ||
| 65 | kirkwood_sata_init(&rd88f6192_sata_data); | 60 | kirkwood_sata_init(&rd88f6192_sata_data); |
| 66 | spi_register_board_info(rd88F6192_spi_slave_info, | 61 | spi_register_board_info(rd88F6192_spi_slave_info, |
| 67 | ARRAY_SIZE(rd88F6192_spi_slave_info)); | 62 | ARRAY_SIZE(rd88F6192_spi_slave_info)); |
| 68 | kirkwood_spi_init(); | 63 | kirkwood_spi_init(); |
| 69 | kirkwood_uart0_init(); | 64 | kirkwood_uart0_init(); |
| 70 | kirkwood_xor0_init(); | ||
| 71 | kirkwood_xor1_init(); | ||
| 72 | } | 65 | } |
| 73 | 66 | ||
| 74 | static int __init rd88f6192_pci_init(void) | 67 | static int __init rd88f6192_pci_init(void) |
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index e1c0516c4df3..31e996d65fc4 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c | |||
| @@ -11,21 +11,20 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/nand.h> | 15 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/timer.h> | 16 | #include <linux/mtd/partitions.h> |
| 19 | #include <linux/ata_platform.h> | 17 | #include <linux/ata_platform.h> |
| 20 | #include <linux/mv643xx_eth.h> | 18 | #include <linux/mv643xx_eth.h> |
| 21 | #include <linux/ethtool.h> | 19 | #include <linux/ethtool.h> |
| 22 | #include <net/dsa.h> | 20 | #include <net/dsa.h> |
| 23 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach/pci.h> | ||
| 26 | #include <mach/kirkwood.h> | 23 | #include <mach/kirkwood.h> |
| 24 | #include <plat/mvsdio.h> | ||
| 27 | #include <plat/orion_nand.h> | 25 | #include <plat/orion_nand.h> |
| 28 | #include "common.h" | 26 | #include "common.h" |
| 27 | #include "mpp.h" | ||
| 29 | 28 | ||
| 30 | static struct mtd_partition rd88f6281_nand_parts[] = { | 29 | static struct mtd_partition rd88f6281_nand_parts[] = { |
| 31 | { | 30 | { |
| @@ -96,6 +95,15 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { | |||
| 96 | .n_ports = 2, | 95 | .n_ports = 2, |
| 97 | }; | 96 | }; |
| 98 | 97 | ||
| 98 | static struct mvsdio_platform_data rd88f6281_mvsdio_data = { | ||
| 99 | .gpio_card_detect = 28, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static unsigned int rd88f6281_mpp_config[] __initdata = { | ||
| 103 | MPP28_GPIO, | ||
| 104 | 0 | ||
| 105 | }; | ||
| 106 | |||
| 99 | static void __init rd88f6281_init(void) | 107 | static void __init rd88f6281_init(void) |
| 100 | { | 108 | { |
| 101 | u32 dev, rev; | 109 | u32 dev, rev; |
| @@ -104,6 +112,7 @@ static void __init rd88f6281_init(void) | |||
| 104 | * Basic setup. Needs to be called early. | 112 | * Basic setup. Needs to be called early. |
| 105 | */ | 113 | */ |
| 106 | kirkwood_init(); | 114 | kirkwood_init(); |
| 115 | kirkwood_mpp_conf(rd88f6281_mpp_config); | ||
| 107 | 116 | ||
| 108 | kirkwood_ehci_init(); | 117 | kirkwood_ehci_init(); |
| 109 | 118 | ||
| @@ -117,8 +126,8 @@ static void __init rd88f6281_init(void) | |||
| 117 | } | 126 | } |
| 118 | kirkwood_ge00_switch_init(&rd88f6281_switch_plat_data, NO_IRQ); | 127 | kirkwood_ge00_switch_init(&rd88f6281_switch_plat_data, NO_IRQ); |
| 119 | 128 | ||
| 120 | kirkwood_rtc_init(); | ||
| 121 | kirkwood_sata_init(&rd88f6281_sata_data); | 129 | kirkwood_sata_init(&rd88f6281_sata_data); |
| 130 | kirkwood_sdio_init(&rd88f6281_mvsdio_data); | ||
| 122 | kirkwood_uart0_init(); | 131 | kirkwood_uart0_init(); |
| 123 | 132 | ||
| 124 | platform_device_register(&rd88f6281_nand_flash); | 133 | platform_device_register(&rd88f6281_nand_flash); |
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c new file mode 100644 index 000000000000..831e4a56cae1 --- /dev/null +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-kirkwood/sheevaplug-setup.c | ||
| 3 | * | ||
| 4 | * Marvell SheevaPlug Reference Board Setup | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/mtd/nand.h> | ||
| 15 | #include <linux/mtd/partitions.h> | ||
| 16 | #include <linux/mv643xx_eth.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/leds.h> | ||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <mach/kirkwood.h> | ||
| 22 | #include <plat/mvsdio.h> | ||
| 23 | #include <plat/orion_nand.h> | ||
| 24 | #include "common.h" | ||
| 25 | #include "mpp.h" | ||
| 26 | |||
| 27 | static struct mtd_partition sheevaplug_nand_parts[] = { | ||
| 28 | { | ||
| 29 | .name = "u-boot", | ||
| 30 | .offset = 0, | ||
| 31 | .size = SZ_1M | ||
| 32 | }, { | ||
| 33 | .name = "uImage", | ||
| 34 | .offset = MTDPART_OFS_NXTBLK, | ||
| 35 | .size = SZ_4M | ||
| 36 | }, { | ||
| 37 | .name = "root", | ||
| 38 | .offset = MTDPART_OFS_NXTBLK, | ||
| 39 | .size = MTDPART_SIZ_FULL | ||
| 40 | }, | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct resource sheevaplug_nand_resource = { | ||
| 44 | .flags = IORESOURCE_MEM, | ||
| 45 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | ||
| 46 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | ||
| 47 | KIRKWOOD_NAND_MEM_SIZE - 1, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct orion_nand_data sheevaplug_nand_data = { | ||
| 51 | .parts = sheevaplug_nand_parts, | ||
| 52 | .nr_parts = ARRAY_SIZE(sheevaplug_nand_parts), | ||
| 53 | .cle = 0, | ||
| 54 | .ale = 1, | ||
| 55 | .width = 8, | ||
| 56 | .chip_delay = 25, | ||
| 57 | }; | ||
| 58 | |||
| 59 | static struct platform_device sheevaplug_nand_flash = { | ||
| 60 | .name = "orion_nand", | ||
| 61 | .id = -1, | ||
| 62 | .dev = { | ||
| 63 | .platform_data = &sheevaplug_nand_data, | ||
| 64 | }, | ||
| 65 | .resource = &sheevaplug_nand_resource, | ||
| 66 | .num_resources = 1, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { | ||
| 70 | .phy_addr = MV643XX_ETH_PHY_ADDR(0), | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct mvsdio_platform_data sheevaplug_mvsdio_data = { | ||
| 74 | // unfortunately the CD signal has not been connected */ | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct gpio_led sheevaplug_led_pins[] = { | ||
| 78 | { | ||
| 79 | .name = "plug:green:health", | ||
| 80 | .default_trigger = "default-on", | ||
| 81 | .gpio = 49, | ||
| 82 | .active_low = 1, | ||
| 83 | }, | ||
| 84 | }; | ||
| 85 | |||
| 86 | static struct gpio_led_platform_data sheevaplug_led_data = { | ||
| 87 | .leds = sheevaplug_led_pins, | ||
| 88 | .num_leds = ARRAY_SIZE(sheevaplug_led_pins), | ||
| 89 | }; | ||
| 90 | |||
| 91 | static struct platform_device sheevaplug_leds = { | ||
| 92 | .name = "leds-gpio", | ||
| 93 | .id = -1, | ||
| 94 | .dev = { | ||
| 95 | .platform_data = &sheevaplug_led_data, | ||
| 96 | } | ||
| 97 | }; | ||
| 98 | |||
| 99 | static unsigned int sheevaplug_mpp_config[] __initdata = { | ||
| 100 | MPP29_GPIO, /* USB Power Enable */ | ||
| 101 | MPP49_GPIO, /* LED */ | ||
| 102 | 0 | ||
| 103 | }; | ||
| 104 | |||
| 105 | static void __init sheevaplug_init(void) | ||
| 106 | { | ||
| 107 | /* | ||
| 108 | * Basic setup. Needs to be called early. | ||
| 109 | */ | ||
| 110 | kirkwood_init(); | ||
| 111 | kirkwood_mpp_conf(sheevaplug_mpp_config); | ||
| 112 | |||
| 113 | kirkwood_uart0_init(); | ||
| 114 | |||
| 115 | if (gpio_request(29, "USB Power Enable") != 0 || | ||
| 116 | gpio_direction_output(29, 1) != 0) | ||
| 117 | printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n"); | ||
| 118 | kirkwood_ehci_init(); | ||
| 119 | |||
| 120 | kirkwood_ge00_init(&sheevaplug_ge00_data); | ||
| 121 | kirkwood_sdio_init(&sheevaplug_mvsdio_data); | ||
| 122 | |||
| 123 | platform_device_register(&sheevaplug_nand_flash); | ||
| 124 | platform_device_register(&sheevaplug_leds); | ||
| 125 | } | ||
| 126 | |||
| 127 | MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") | ||
| 128 | /* Maintainer: shadi Ammouri <shadi@marvell.com> */ | ||
| 129 | .phys_io = KIRKWOOD_REGS_PHYS_BASE, | ||
| 130 | .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 131 | .boot_params = 0x00000100, | ||
| 132 | .init_machine = sheevaplug_init, | ||
| 133 | .map_io = kirkwood_map_io, | ||
| 134 | .init_irq = kirkwood_init_irq, | ||
| 135 | .timer = &kirkwood_timer, | ||
| 136 | MACHINE_END | ||
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c new file mode 100644 index 000000000000..dda5743cf3e0 --- /dev/null +++ b/arch/arm/mach-kirkwood/ts219-setup.c | |||
| @@ -0,0 +1,220 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * QNAP TS-119/TS-219 Turbo NAS Board Setup | ||
| 4 | * | ||
| 5 | * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> | ||
| 6 | * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version | ||
| 11 | * 2 of the License, or (at your option) any later version. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/mtd/physmap.h> | ||
| 18 | #include <linux/spi/flash.h> | ||
| 19 | #include <linux/spi/spi.h> | ||
| 20 | #include <linux/spi/orion_spi.h> | ||
| 21 | #include <linux/i2c.h> | ||
| 22 | #include <linux/mv643xx_eth.h> | ||
| 23 | #include <linux/ata_platform.h> | ||
| 24 | #include <linux/gpio_keys.h> | ||
| 25 | #include <linux/input.h> | ||
| 26 | #include <linux/timex.h> | ||
| 27 | #include <linux/serial_reg.h> | ||
| 28 | #include <linux/pci.h> | ||
| 29 | #include <asm/mach-types.h> | ||
| 30 | #include <asm/mach/arch.h> | ||
| 31 | #include <mach/kirkwood.h> | ||
| 32 | #include "common.h" | ||
| 33 | #include "mpp.h" | ||
| 34 | |||
| 35 | /**************************************************************************** | ||
| 36 | * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the | ||
| 37 | * partitions on the device because we want to keep compatability with | ||
| 38 | * the QNAP firmware. | ||
| 39 | * Layout as used by QNAP: | ||
| 40 | * 0x00000000-0x00080000 : "U-Boot" | ||
| 41 | * 0x00200000-0x00400000 : "Kernel" | ||
| 42 | * 0x00400000-0x00d00000 : "RootFS" | ||
| 43 | * 0x00d00000-0x01000000 : "RootFS2" | ||
| 44 | * 0x00080000-0x000c0000 : "U-Boot Config" | ||
| 45 | * 0x000c0000-0x00200000 : "NAS Config" | ||
| 46 | * | ||
| 47 | * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout | ||
| 48 | * used by the QNAP TS-109/TS-209. | ||
| 49 | * | ||
| 50 | ***************************************************************************/ | ||
| 51 | |||
| 52 | static struct mtd_partition qnap_ts219_partitions[] = { | ||
| 53 | { | ||
| 54 | .name = "U-Boot", | ||
| 55 | .size = 0x00080000, | ||
| 56 | .offset = 0, | ||
| 57 | .mask_flags = MTD_WRITEABLE, | ||
| 58 | }, { | ||
| 59 | .name = "Kernel", | ||
| 60 | .size = 0x00200000, | ||
| 61 | .offset = 0x00200000, | ||
| 62 | }, { | ||
| 63 | .name = "RootFS1", | ||
| 64 | .size = 0x00900000, | ||
| 65 | .offset = 0x00400000, | ||
| 66 | }, { | ||
| 67 | .name = "RootFS2", | ||
| 68 | .size = 0x00300000, | ||
| 69 | .offset = 0x00d00000, | ||
| 70 | }, { | ||
| 71 | .name = "U-Boot Config", | ||
| 72 | .size = 0x00040000, | ||
| 73 | .offset = 0x00080000, | ||
| 74 | }, { | ||
| 75 | .name = "NAS Config", | ||
| 76 | .size = 0x00140000, | ||
| 77 | .offset = 0x000c0000, | ||
| 78 | }, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static const struct flash_platform_data qnap_ts219_flash = { | ||
| 82 | .type = "m25p128", | ||
| 83 | .name = "spi_flash", | ||
| 84 | .parts = qnap_ts219_partitions, | ||
| 85 | .nr_parts = ARRAY_SIZE(qnap_ts219_partitions), | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = { | ||
| 89 | { | ||
| 90 | .modalias = "m25p80", | ||
| 91 | .platform_data = &qnap_ts219_flash, | ||
| 92 | .irq = -1, | ||
| 93 | .max_speed_hz = 20000000, | ||
| 94 | .bus_num = 0, | ||
| 95 | .chip_select = 0, | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = { | ||
| 100 | I2C_BOARD_INFO("s35390a", 0x30), | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = { | ||
| 104 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | ||
| 105 | }; | ||
| 106 | |||
| 107 | static struct mv_sata_platform_data qnap_ts219_sata_data = { | ||
| 108 | .n_ports = 2, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct gpio_keys_button qnap_ts219_buttons[] = { | ||
| 112 | { | ||
| 113 | .code = KEY_COPY, | ||
| 114 | .gpio = 15, | ||
| 115 | .desc = "USB Copy", | ||
| 116 | .active_low = 1, | ||
| 117 | }, | ||
| 118 | { | ||
| 119 | .code = KEY_RESTART, | ||
| 120 | .gpio = 16, | ||
| 121 | .desc = "Reset", | ||
| 122 | .active_low = 1, | ||
| 123 | }, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct gpio_keys_platform_data qnap_ts219_button_data = { | ||
| 127 | .buttons = qnap_ts219_buttons, | ||
| 128 | .nbuttons = ARRAY_SIZE(qnap_ts219_buttons), | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct platform_device qnap_ts219_button_device = { | ||
| 132 | .name = "gpio-keys", | ||
| 133 | .id = -1, | ||
| 134 | .num_resources = 0, | ||
| 135 | .dev = { | ||
| 136 | .platform_data = &qnap_ts219_button_data, | ||
| 137 | } | ||
| 138 | }; | ||
| 139 | |||
| 140 | static unsigned int qnap_ts219_mpp_config[] __initdata = { | ||
| 141 | MPP0_SPI_SCn, | ||
| 142 | MPP1_SPI_MOSI, | ||
| 143 | MPP2_SPI_SCK, | ||
| 144 | MPP3_SPI_MISO, | ||
| 145 | MPP8_TW_SDA, | ||
| 146 | MPP9_TW_SCK, | ||
| 147 | MPP10_UART0_TXD, | ||
| 148 | MPP11_UART0_RXD, | ||
| 149 | MPP13_UART1_TXD, /* PIC controller */ | ||
| 150 | MPP14_UART1_RXD, /* PIC controller */ | ||
| 151 | MPP15_GPIO, /* USB Copy button */ | ||
| 152 | MPP16_GPIO, /* Reset button */ | ||
| 153 | MPP20_SATA1_ACTn, | ||
| 154 | MPP21_SATA0_ACTn, | ||
| 155 | MPP22_SATA1_PRESENTn, | ||
| 156 | MPP23_SATA0_PRESENTn, | ||
| 157 | 0 | ||
| 158 | }; | ||
| 159 | |||
| 160 | |||
| 161 | /***************************************************************************** | ||
| 162 | * QNAP TS-x19 specific power off method via UART1-attached PIC | ||
| 163 | ****************************************************************************/ | ||
| 164 | |||
| 165 | #define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) | ||
| 166 | |||
| 167 | void qnap_ts219_power_off(void) | ||
| 168 | { | ||
| 169 | /* 19200 baud divisor */ | ||
| 170 | const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); | ||
| 171 | |||
| 172 | pr_info("%s: triggering power-off...\n", __func__); | ||
| 173 | |||
| 174 | /* hijack UART1 and reset into sane state (19200,8n1) */ | ||
| 175 | writel(0x83, UART1_REG(LCR)); | ||
| 176 | writel(divisor & 0xff, UART1_REG(DLL)); | ||
| 177 | writel((divisor >> 8) & 0xff, UART1_REG(DLM)); | ||
| 178 | writel(0x03, UART1_REG(LCR)); | ||
| 179 | writel(0x00, UART1_REG(IER)); | ||
| 180 | writel(0x00, UART1_REG(FCR)); | ||
| 181 | writel(0x00, UART1_REG(MCR)); | ||
| 182 | |||
| 183 | /* send the power-off command 'A' to PIC */ | ||
| 184 | writel('A', UART1_REG(TX)); | ||
| 185 | } | ||
| 186 | |||
| 187 | static void __init qnap_ts219_init(void) | ||
| 188 | { | ||
| 189 | /* | ||
| 190 | * Basic setup. Needs to be called early. | ||
| 191 | */ | ||
| 192 | kirkwood_init(); | ||
| 193 | kirkwood_mpp_conf(qnap_ts219_mpp_config); | ||
| 194 | |||
| 195 | kirkwood_uart0_init(); | ||
| 196 | kirkwood_uart1_init(); /* A PIC controller is connected here. */ | ||
| 197 | spi_register_board_info(qnap_ts219_spi_slave_info, | ||
| 198 | ARRAY_SIZE(qnap_ts219_spi_slave_info)); | ||
| 199 | kirkwood_spi_init(); | ||
| 200 | kirkwood_i2c_init(); | ||
| 201 | i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); | ||
| 202 | kirkwood_ge00_init(&qnap_ts219_ge00_data); | ||
| 203 | kirkwood_sata_init(&qnap_ts219_sata_data); | ||
| 204 | kirkwood_ehci_init(); | ||
| 205 | platform_device_register(&qnap_ts219_button_device); | ||
| 206 | |||
| 207 | pm_power_off = qnap_ts219_power_off; | ||
| 208 | |||
| 209 | } | ||
| 210 | |||
| 211 | MACHINE_START(TS219, "QNAP TS-119/TS-219") | ||
| 212 | /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ | ||
| 213 | .phys_io = KIRKWOOD_REGS_PHYS_BASE, | ||
| 214 | .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 215 | .boot_params = 0x00000100, | ||
| 216 | .init_machine = qnap_ts219_init, | ||
| 217 | .map_io = kirkwood_map_io, | ||
| 218 | .init_irq = kirkwood_init_irq, | ||
| 219 | .timer = &kirkwood_timer, | ||
| 220 | MACHINE_END | ||
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig index 2754daabda55..fe0c82e30b2d 100644 --- a/arch/arm/mach-ks8695/Kconfig +++ b/arch/arm/mach-ks8695/Kconfig | |||
| @@ -14,6 +14,12 @@ config MACH_DSM320 | |||
| 14 | Say 'Y' here if you want your kernel to run on the D-Link | 14 | Say 'Y' here if you want your kernel to run on the D-Link |
| 15 | DSM-320 Wireless Media Player. | 15 | DSM-320 Wireless Media Player. |
| 16 | 16 | ||
| 17 | config MACH_ACS5K | ||
| 18 | bool "Brivo Systems LLC, ACS-5000 Master board" | ||
| 19 | help | ||
| 20 | say 'Y' here if you want your kernel to run on the Brivo | ||
| 21 | Systems LLC, ACS-5000 Master board. | ||
| 22 | |||
| 17 | endmenu | 23 | endmenu |
| 18 | 24 | ||
| 19 | endif | 25 | endif |
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile index f735d2cc0294..7e3e8160ed30 100644 --- a/arch/arm/mach-ks8695/Makefile +++ b/arch/arm/mach-ks8695/Makefile | |||
| @@ -17,3 +17,4 @@ obj-$(CONFIG_LEDS) += leds.o | |||
| 17 | # Board-specific support | 17 | # Board-specific support |
| 18 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o | 18 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o |
| 19 | obj-$(CONFIG_MACH_DSM320) += board-dsm320.o | 19 | obj-$(CONFIG_MACH_DSM320) += board-dsm320.o |
| 20 | obj-$(CONFIG_MACH_ACS5K) += board-acs5k.o | ||
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c new file mode 100644 index 000000000000..9e3e5a640ad2 --- /dev/null +++ b/arch/arm/mach-ks8695/board-acs5k.c | |||
| @@ -0,0 +1,233 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ks8695/board-acs5k.c | ||
| 3 | * | ||
| 4 | * Brivo Systems LLC, ACS-5000 Master Board | ||
| 5 | * | ||
| 6 | * Copyright 2008 Simtec Electronics | ||
| 7 | * Daniel Silverstone <dsilvers@simtec.co.uk> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | |||
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/i2c-algo-bit.h> | ||
| 22 | #include <linux/i2c-gpio.h> | ||
| 23 | #include <linux/i2c/pca953x.h> | ||
| 24 | |||
| 25 | #include <linux/mtd/mtd.h> | ||
| 26 | #include <linux/mtd/map.h> | ||
| 27 | #include <linux/mtd/physmap.h> | ||
| 28 | #include <linux/mtd/partitions.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | |||
| 32 | #include <asm/mach/arch.h> | ||
| 33 | #include <asm/mach/map.h> | ||
| 34 | #include <asm/mach/irq.h> | ||
| 35 | |||
| 36 | #include <mach/devices.h> | ||
| 37 | #include <mach/gpio.h> | ||
| 38 | |||
| 39 | #include "generic.h" | ||
| 40 | |||
| 41 | static struct i2c_gpio_platform_data acs5k_i2c_device_platdata = { | ||
| 42 | .sda_pin = 4, | ||
| 43 | .scl_pin = 5, | ||
| 44 | .udelay = 10, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct platform_device acs5k_i2c_device = { | ||
| 48 | .name = "i2c-gpio", | ||
| 49 | .id = -1, | ||
| 50 | .num_resources = 0, | ||
| 51 | .resource = NULL, | ||
| 52 | .dev = { | ||
| 53 | .platform_data = &acs5k_i2c_device_platdata, | ||
| 54 | }, | ||
| 55 | }; | ||
| 56 | |||
| 57 | static int acs5k_pca9555_setup(struct i2c_client *client, | ||
| 58 | unsigned gpio_base, unsigned ngpio, | ||
| 59 | void *context) | ||
| 60 | { | ||
| 61 | static int acs5k_gpio_value[] = { | ||
| 62 | -1, -1, -1, -1, -1, -1, -1, 0, 1, 1, -1, 0, 1, 0, -1, -1 | ||
| 63 | }; | ||
| 64 | int n; | ||
| 65 | |||
| 66 | for (n = 0; n < ARRAY_SIZE(acs5k_gpio_value); ++n) { | ||
| 67 | gpio_request(gpio_base + n, "ACS-5000 GPIO Expander"); | ||
| 68 | if (acs5k_gpio_value[n] < 0) | ||
| 69 | gpio_direction_input(gpio_base + n); | ||
| 70 | else | ||
| 71 | gpio_direction_output(gpio_base + n, | ||
| 72 | acs5k_gpio_value[n]); | ||
| 73 | gpio_export(gpio_base + n, 0); /* Export, direction locked down */ | ||
| 74 | } | ||
| 75 | |||
| 76 | return 0; | ||
| 77 | } | ||
| 78 | |||
| 79 | static struct pca953x_platform_data acs5k_i2c_pca9555_platdata = { | ||
| 80 | .gpio_base = 16, /* Start directly after the CPU's GPIO */ | ||
| 81 | .invert = 0, /* Do not invert */ | ||
| 82 | .setup = acs5k_pca9555_setup, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct i2c_board_info acs5k_i2c_devs[] __initdata = { | ||
| 86 | { | ||
| 87 | I2C_BOARD_INFO("pcf8563", 0x51), | ||
| 88 | }, | ||
| 89 | { | ||
| 90 | I2C_BOARD_INFO("pca9555", 0x20), | ||
| 91 | .platform_data = &acs5k_i2c_pca9555_platdata, | ||
| 92 | }, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static void __devinit acs5k_i2c_init(void) | ||
| 96 | { | ||
| 97 | /* The gpio interface */ | ||
| 98 | platform_device_register(&acs5k_i2c_device); | ||
| 99 | /* I2C devices */ | ||
| 100 | i2c_register_board_info(0, acs5k_i2c_devs, | ||
| 101 | ARRAY_SIZE(acs5k_i2c_devs)); | ||
| 102 | } | ||
| 103 | |||
| 104 | static struct mtd_partition acs5k_nor_partitions[] = { | ||
| 105 | [0] = { | ||
| 106 | .name = "Boot Agent and config", | ||
| 107 | .size = SZ_256K, | ||
| 108 | .offset = 0, | ||
| 109 | .mask_flags = MTD_WRITEABLE, | ||
| 110 | }, | ||
| 111 | [1] = { | ||
| 112 | .name = "Kernel", | ||
| 113 | .size = SZ_1M, | ||
| 114 | .offset = SZ_256K, | ||
| 115 | }, | ||
| 116 | [2] = { | ||
| 117 | .name = "SquashFS1", | ||
| 118 | .size = SZ_2M, | ||
| 119 | .offset = SZ_256K + SZ_1M, | ||
| 120 | }, | ||
| 121 | [3] = { | ||
| 122 | .name = "SquashFS2", | ||
| 123 | .size = SZ_4M + SZ_2M, | ||
| 124 | .offset = SZ_256K + SZ_1M + SZ_2M, | ||
| 125 | }, | ||
| 126 | [4] = { | ||
| 127 | .name = "Data", | ||
| 128 | .size = SZ_16M + SZ_4M + SZ_2M + SZ_512K, /* 22.5 MB */ | ||
| 129 | .offset = SZ_256K + SZ_8M + SZ_1M, | ||
| 130 | } | ||
| 131 | }; | ||
| 132 | |||
| 133 | static struct physmap_flash_data acs5k_nor_pdata = { | ||
| 134 | .width = 4, | ||
| 135 | .nr_parts = ARRAY_SIZE(acs5k_nor_partitions), | ||
| 136 | .parts = acs5k_nor_partitions, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static struct resource acs5k_nor_resource[] = { | ||
| 140 | [0] = { | ||
| 141 | .start = SZ_32M, /* We expect the bootloader to map | ||
| 142 | * the flash here. | ||
| 143 | */ | ||
| 144 | .end = SZ_32M + SZ_16M - 1, | ||
| 145 | .flags = IORESOURCE_MEM, | ||
| 146 | }, | ||
| 147 | [1] = { | ||
| 148 | .start = SZ_32M + SZ_16M, | ||
| 149 | .end = SZ_32M + SZ_32M - SZ_256K - 1, | ||
| 150 | .flags = IORESOURCE_MEM, | ||
| 151 | } | ||
| 152 | }; | ||
| 153 | |||
| 154 | static struct platform_device acs5k_device_nor = { | ||
| 155 | .name = "physmap-flash", | ||
| 156 | .id = -1, | ||
| 157 | .num_resources = ARRAY_SIZE(acs5k_nor_resource), | ||
| 158 | .resource = acs5k_nor_resource, | ||
| 159 | .dev = { | ||
| 160 | .platform_data = &acs5k_nor_pdata, | ||
| 161 | }, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static void __init acs5k_register_nor(void) | ||
| 165 | { | ||
| 166 | int ret; | ||
| 167 | |||
| 168 | if (acs5k_nor_partitions[0].mask_flags == 0) | ||
| 169 | printk(KERN_WARNING "Warning: Unprotecting bootloader and configuration partition\n"); | ||
| 170 | |||
| 171 | ret = platform_device_register(&acs5k_device_nor); | ||
| 172 | if (ret < 0) | ||
| 173 | printk(KERN_ERR "failed to register physmap-flash device\n"); | ||
| 174 | } | ||
| 175 | |||
| 176 | static int __init acs5k_protection_setup(char *s) | ||
| 177 | { | ||
| 178 | /* We can't allocate anything here but we should be able | ||
| 179 | * to trivially parse s and decide if we can protect the | ||
| 180 | * bootloader partition or not | ||
| 181 | */ | ||
| 182 | if (strcmp(s, "no") == 0) | ||
| 183 | acs5k_nor_partitions[0].mask_flags = 0; | ||
| 184 | |||
| 185 | return 1; | ||
| 186 | } | ||
| 187 | |||
| 188 | __setup("protect_bootloader=", acs5k_protection_setup); | ||
| 189 | |||
| 190 | static void __init acs5k_init_gpio(void) | ||
| 191 | { | ||
| 192 | int i; | ||
| 193 | |||
| 194 | ks8695_register_gpios(); | ||
| 195 | for (i = 0; i < 4; ++i) | ||
| 196 | gpio_request(i, "ACS5K IRQ"); | ||
| 197 | gpio_request(7, "ACS5K KS_FRDY"); | ||
| 198 | for (i = 8; i < 16; ++i) | ||
| 199 | gpio_request(i, "ACS5K Unused"); | ||
| 200 | |||
| 201 | gpio_request(3, "ACS5K CAN Control"); | ||
| 202 | gpio_request(6, "ACS5K Heartbeat"); | ||
| 203 | gpio_direction_output(3, 1); /* Default CAN_RESET high */ | ||
| 204 | gpio_direction_output(6, 0); /* Default KS8695_ACTIVE low */ | ||
| 205 | gpio_export(3, 0); /* export CAN_RESET as output only */ | ||
| 206 | gpio_export(6, 0); /* export KS8695_ACTIVE as output only */ | ||
| 207 | } | ||
| 208 | |||
| 209 | static void __init acs5k_init(void) | ||
| 210 | { | ||
| 211 | acs5k_init_gpio(); | ||
| 212 | |||
| 213 | /* Network device */ | ||
| 214 | ks8695_add_device_lan(); /* eth0 = LAN */ | ||
| 215 | ks8695_add_device_wan(); /* ethX = WAN */ | ||
| 216 | |||
| 217 | /* NOR devices */ | ||
| 218 | acs5k_register_nor(); | ||
| 219 | |||
| 220 | /* I2C bus */ | ||
| 221 | acs5k_i2c_init(); | ||
| 222 | } | ||
| 223 | |||
| 224 | MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board") | ||
| 225 | /* Maintainer: Simtec Electronics. */ | ||
| 226 | .phys_io = KS8695_IO_PA, | ||
| 227 | .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc, | ||
| 228 | .boot_params = KS8695_SDRAM_PA + 0x100, | ||
| 229 | .map_io = ks8695_map_io, | ||
| 230 | .init_irq = ks8695_init_irq, | ||
| 231 | .init_machine = acs5k_init, | ||
| 232 | .timer = &ks8695_timer, | ||
| 233 | MACHINE_END | ||
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h index 6d5887cf5742..76e5308685a4 100644 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ b/arch/arm/mach-ks8695/include/mach/memory.h | |||
| @@ -35,7 +35,11 @@ extern struct bus_type platform_bus_type; | |||
| 35 | __phys_to_virt(x) : __bus_to_virt(x)); }) | 35 | __phys_to_virt(x) : __bus_to_virt(x)); }) |
| 36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ | 36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ |
| 37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) | 37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) |
| 38 | #define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) | 38 | #define __arch_page_to_dma(dev, x) \ |
| 39 | ({ dma_addr_t __dma = page_to_phys(page); \ | ||
| 40 | if (!is_lbus_device(dev)) \ | ||
| 41 | __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \ | ||
| 42 | __dma; }) | ||
| 39 | 43 | ||
| 40 | #endif | 44 | #endif |
| 41 | 45 | ||
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h index 5a9b032bdbeb..fb1dda9be2d0 100644 --- a/arch/arm/mach-ks8695/include/mach/system.h +++ b/arch/arm/mach-ks8695/include/mach/system.h | |||
| @@ -27,7 +27,7 @@ static void arch_idle(void) | |||
| 27 | 27 | ||
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | static void arch_reset(char mode) | 30 | static void arch_reset(char mode, const char *cmd) |
| 31 | { | 31 | { |
| 32 | unsigned int reg; | 32 | unsigned int reg; |
| 33 | 33 | ||
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h index 5272abee0d0e..e0dd3b6ae4aa 100644 --- a/arch/arm/mach-l7200/include/mach/system.h +++ b/arch/arm/mach-l7200/include/mach/system.h | |||
| @@ -19,7 +19,7 @@ static inline void arch_idle(void) | |||
| 19 | *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */ | 19 | *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */ |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | static inline void arch_reset(char mode) | 22 | static inline void arch_reset(char mode, const char *cmd) |
| 23 | { | 23 | { |
| 24 | if (mode == 's') { | 24 | if (mode == 's') { |
| 25 | cpu_reset(0); | 25 | cpu_reset(0); |
diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h index fa46bb1ef07b..45a56d3b93d7 100644 --- a/arch/arm/mach-lh7a40x/include/mach/system.h +++ b/arch/arm/mach-lh7a40x/include/mach/system.h | |||
| @@ -13,7 +13,7 @@ static inline void arch_idle(void) | |||
| 13 | cpu_do_idle (); | 13 | cpu_do_idle (); |
| 14 | } | 14 | } |
| 15 | 15 | ||
| 16 | static inline void arch_reset(char mode) | 16 | static inline void arch_reset(char mode, const char *cmd) |
| 17 | { | 17 | { |
| 18 | cpu_reset (0); | 18 | cpu_reset (0); |
| 19 | } | 19 | } |
diff --git a/arch/arm/mach-loki/include/mach/system.h b/arch/arm/mach-loki/include/mach/system.h index 8db1147d4ec5..c1de36fe9b37 100644 --- a/arch/arm/mach-loki/include/mach/system.h +++ b/arch/arm/mach-loki/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | /* | 22 | /* |
| 23 | * Enable soft reset to assert RSTOUTn. | 23 | * Enable soft reset to assert RSTOUTn. |
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig new file mode 100644 index 000000000000..c6a564fc4a7c --- /dev/null +++ b/arch/arm/mach-mmp/Kconfig | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | if ARCH_MMP | ||
| 2 | |||
| 3 | menu "Marvell PXA168/910 Implmentations" | ||
| 4 | |||
| 5 | config MACH_ASPENITE | ||
| 6 | bool "Marvell's PXA168 Aspenite Development Board" | ||
| 7 | select CPU_PXA168 | ||
| 8 | help | ||
| 9 | Say 'Y' here if you want to support the Marvell PXA168-based | ||
| 10 | Aspenite Development Board. | ||
| 11 | |||
| 12 | config MACH_ZYLONITE2 | ||
| 13 | bool "Marvell's PXA168 Zylonite2 Development Board" | ||
| 14 | select CPU_PXA168 | ||
| 15 | help | ||
| 16 | Say 'Y' here if you want to support the Marvell PXA168-based | ||
| 17 | Zylonite2 Development Board. | ||
| 18 | |||
| 19 | config MACH_TAVOREVB | ||
| 20 | bool "Marvell's PXA910 TavorEVB Development Board" | ||
| 21 | select CPU_PXA910 | ||
| 22 | help | ||
| 23 | Say 'Y' here if you want to support the Marvell PXA910-based | ||
| 24 | TavorEVB Development Board. | ||
| 25 | |||
| 26 | config MACH_TTC_DKB | ||
| 27 | bool "Marvell's PXA910 TavorEVB Development Board" | ||
| 28 | select CPU_PXA910 | ||
| 29 | help | ||
| 30 | Say 'Y' here if you want to support the Marvell PXA910-based | ||
| 31 | TTC_DKB Development Board. | ||
| 32 | |||
| 33 | endmenu | ||
| 34 | |||
| 35 | config CPU_PXA168 | ||
| 36 | bool | ||
| 37 | select CPU_MOHAWK | ||
| 38 | help | ||
| 39 | Select code specific to PXA168 | ||
| 40 | |||
| 41 | config CPU_PXA910 | ||
| 42 | bool | ||
| 43 | select CPU_MOHAWK | ||
| 44 | help | ||
| 45 | Select code specific to PXA910 | ||
| 46 | |||
| 47 | endif | ||
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile new file mode 100644 index 000000000000..6883e6584883 --- /dev/null +++ b/arch/arm/mach-mmp/Makefile | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | # | ||
| 2 | # Makefile for Marvell's PXA168 processors line | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += common.o clock.o devices.o irq.o time.o | ||
| 6 | |||
| 7 | # SoC support | ||
| 8 | obj-$(CONFIG_CPU_PXA168) += pxa168.o | ||
| 9 | obj-$(CONFIG_CPU_PXA910) += pxa910.o | ||
| 10 | |||
| 11 | # board support | ||
| 12 | obj-$(CONFIG_MACH_ASPENITE) += aspenite.o | ||
| 13 | obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o | ||
| 14 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o | ||
| 15 | obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o | ||
diff --git a/arch/arm/mach-mmp/Makefile.boot b/arch/arm/mach-mmp/Makefile.boot new file mode 100644 index 000000000000..574a4aa8321a --- /dev/null +++ b/arch/arm/mach-mmp/Makefile.boot | |||
| @@ -0,0 +1 @@ | |||
| zreladdr-y := 0x00008000 | |||
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c new file mode 100644 index 000000000000..4562452d4074 --- /dev/null +++ b/arch/arm/mach-mmp/aspenite.c | |||
| @@ -0,0 +1,117 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/aspenite.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell PXA168-based Aspenite and Zylonite2 | ||
| 5 | * Development Platform. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * publishhed by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/smc91x.h> | ||
| 16 | |||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | #include <mach/addr-map.h> | ||
| 20 | #include <mach/mfp-pxa168.h> | ||
| 21 | #include <mach/pxa168.h> | ||
| 22 | #include <mach/gpio.h> | ||
| 23 | |||
| 24 | #include "common.h" | ||
| 25 | |||
| 26 | static unsigned long common_pin_config[] __initdata = { | ||
| 27 | /* Data Flash Interface */ | ||
| 28 | GPIO0_DFI_D15, | ||
| 29 | GPIO1_DFI_D14, | ||
| 30 | GPIO2_DFI_D13, | ||
| 31 | GPIO3_DFI_D12, | ||
| 32 | GPIO4_DFI_D11, | ||
| 33 | GPIO5_DFI_D10, | ||
| 34 | GPIO6_DFI_D9, | ||
| 35 | GPIO7_DFI_D8, | ||
| 36 | GPIO8_DFI_D7, | ||
| 37 | GPIO9_DFI_D6, | ||
| 38 | GPIO10_DFI_D5, | ||
| 39 | GPIO11_DFI_D4, | ||
| 40 | GPIO12_DFI_D3, | ||
| 41 | GPIO13_DFI_D2, | ||
| 42 | GPIO14_DFI_D1, | ||
| 43 | GPIO15_DFI_D0, | ||
| 44 | |||
| 45 | /* Static Memory Controller */ | ||
| 46 | GPIO18_SMC_nCS0, | ||
| 47 | GPIO34_SMC_nCS1, | ||
| 48 | GPIO23_SMC_nLUA, | ||
| 49 | GPIO25_SMC_nLLA, | ||
| 50 | GPIO28_SMC_RDY, | ||
| 51 | GPIO29_SMC_SCLK, | ||
| 52 | GPIO35_SMC_BE1, | ||
| 53 | GPIO36_SMC_BE2, | ||
| 54 | GPIO27_GPIO, /* Ethernet IRQ */ | ||
| 55 | |||
| 56 | /* UART1 */ | ||
| 57 | GPIO107_UART1_RXD, | ||
| 58 | GPIO108_UART1_TXD, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct smc91x_platdata smc91x_info = { | ||
| 62 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct resource smc91x_resources[] = { | ||
| 66 | [0] = { | ||
| 67 | .start = SMC_CS1_PHYS_BASE + 0x300, | ||
| 68 | .end = SMC_CS1_PHYS_BASE + 0xfffff, | ||
| 69 | .flags = IORESOURCE_MEM, | ||
| 70 | }, | ||
| 71 | [1] = { | ||
| 72 | .start = gpio_to_irq(27), | ||
| 73 | .end = gpio_to_irq(27), | ||
| 74 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 75 | } | ||
| 76 | }; | ||
| 77 | |||
| 78 | static struct platform_device smc91x_device = { | ||
| 79 | .name = "smc91x", | ||
| 80 | .id = 0, | ||
| 81 | .dev = { | ||
| 82 | .platform_data = &smc91x_info, | ||
| 83 | }, | ||
| 84 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 85 | .resource = smc91x_resources, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static void __init common_init(void) | ||
| 89 | { | ||
| 90 | mfp_config(ARRAY_AND_SIZE(common_pin_config)); | ||
| 91 | |||
| 92 | /* on-chip devices */ | ||
| 93 | pxa168_add_uart(1); | ||
| 94 | |||
| 95 | /* off-chip devices */ | ||
| 96 | platform_device_register(&smc91x_device); | ||
| 97 | } | ||
| 98 | |||
| 99 | MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") | ||
| 100 | .phys_io = APB_PHYS_BASE, | ||
| 101 | .boot_params = 0x00000100, | ||
| 102 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 103 | .map_io = pxa_map_io, | ||
| 104 | .init_irq = pxa168_init_irq, | ||
| 105 | .timer = &pxa168_timer, | ||
| 106 | .init_machine = common_init, | ||
| 107 | MACHINE_END | ||
| 108 | |||
| 109 | MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform") | ||
| 110 | .phys_io = APB_PHYS_BASE, | ||
| 111 | .boot_params = 0x00000100, | ||
| 112 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 113 | .map_io = pxa_map_io, | ||
| 114 | .init_irq = pxa168_init_irq, | ||
| 115 | .timer = &pxa168_timer, | ||
| 116 | .init_machine = common_init, | ||
| 117 | MACHINE_END | ||
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c new file mode 100644 index 000000000000..2d9cc5a7122f --- /dev/null +++ b/arch/arm/mach-mmp/clock.c | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/clock.c | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/list.h> | ||
| 12 | #include <linux/spinlock.h> | ||
| 13 | #include <linux/clk.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | |||
| 16 | #include <mach/regs-apbc.h> | ||
| 17 | #include "clock.h" | ||
| 18 | |||
| 19 | static void apbc_clk_enable(struct clk *clk) | ||
| 20 | { | ||
| 21 | uint32_t clk_rst; | ||
| 22 | |||
| 23 | clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); | ||
| 24 | __raw_writel(clk_rst, clk->clk_rst); | ||
| 25 | } | ||
| 26 | |||
| 27 | static void apbc_clk_disable(struct clk *clk) | ||
| 28 | { | ||
| 29 | __raw_writel(0, clk->clk_rst); | ||
| 30 | } | ||
| 31 | |||
| 32 | struct clkops apbc_clk_ops = { | ||
| 33 | .enable = apbc_clk_enable, | ||
| 34 | .disable = apbc_clk_disable, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static DEFINE_SPINLOCK(clocks_lock); | ||
| 38 | |||
| 39 | int clk_enable(struct clk *clk) | ||
| 40 | { | ||
| 41 | unsigned long flags; | ||
| 42 | |||
| 43 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 44 | if (clk->enabled++ == 0) | ||
| 45 | clk->ops->enable(clk); | ||
| 46 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 47 | return 0; | ||
| 48 | } | ||
| 49 | EXPORT_SYMBOL(clk_enable); | ||
| 50 | |||
| 51 | void clk_disable(struct clk *clk) | ||
| 52 | { | ||
| 53 | unsigned long flags; | ||
| 54 | |||
| 55 | WARN_ON(clk->enabled == 0); | ||
| 56 | |||
| 57 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 58 | if (--clk->enabled == 0) | ||
| 59 | clk->ops->disable(clk); | ||
| 60 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 61 | } | ||
| 62 | EXPORT_SYMBOL(clk_disable); | ||
| 63 | |||
| 64 | unsigned long clk_get_rate(struct clk *clk) | ||
| 65 | { | ||
| 66 | unsigned long rate; | ||
| 67 | |||
| 68 | if (clk->ops->getrate) | ||
| 69 | rate = clk->ops->getrate(clk); | ||
| 70 | else | ||
| 71 | rate = clk->rate; | ||
| 72 | |||
| 73 | return rate; | ||
| 74 | } | ||
| 75 | EXPORT_SYMBOL(clk_get_rate); | ||
| 76 | |||
| 77 | void clks_register(struct clk_lookup *clks, size_t num) | ||
| 78 | { | ||
| 79 | int i; | ||
| 80 | |||
| 81 | for (i = 0; i < num; i++) | ||
| 82 | clkdev_add(&clks[i]); | ||
| 83 | } | ||
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h new file mode 100644 index 000000000000..ed967e78e6a8 --- /dev/null +++ b/arch/arm/mach-mmp/clock.h | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/clock.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/clkdev.h> | ||
| 10 | |||
| 11 | struct clkops { | ||
| 12 | void (*enable)(struct clk *); | ||
| 13 | void (*disable)(struct clk *); | ||
| 14 | unsigned long (*getrate)(struct clk *); | ||
| 15 | }; | ||
| 16 | |||
| 17 | struct clk { | ||
| 18 | const struct clkops *ops; | ||
| 19 | |||
| 20 | void __iomem *clk_rst; /* clock reset control register */ | ||
| 21 | int fnclksel; /* functional clock select (APBC) */ | ||
| 22 | uint32_t enable_val; /* value for clock enable (APMU) */ | ||
| 23 | unsigned long rate; | ||
| 24 | int enabled; | ||
| 25 | }; | ||
| 26 | |||
| 27 | extern struct clkops apbc_clk_ops; | ||
| 28 | |||
| 29 | #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ | ||
| 30 | struct clk clk_##_name = { \ | ||
| 31 | .clk_rst = (void __iomem *)APBC_##_reg, \ | ||
| 32 | .fnclksel = _fnclksel, \ | ||
| 33 | .rate = _rate, \ | ||
| 34 | .ops = &apbc_clk_ops, \ | ||
| 35 | } | ||
| 36 | |||
| 37 | #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ | ||
| 38 | struct clk clk_##_name = { \ | ||
| 39 | .clk_rst = (void __iomem *)APBC_##_reg, \ | ||
| 40 | .fnclksel = _fnclksel, \ | ||
| 41 | .rate = _rate, \ | ||
| 42 | .ops = _ops, \ | ||
| 43 | } | ||
| 44 | |||
| 45 | #define APMU_CLK(_name, _reg, _eval, _rate) \ | ||
| 46 | struct clk clk_##_name = { \ | ||
| 47 | .clk_rst = (void __iomem *)APMU_##_reg, \ | ||
| 48 | .enable_val = _eval, \ | ||
| 49 | .rate = _rate, \ | ||
| 50 | .ops = &apmu_clk_ops, \ | ||
| 51 | } | ||
| 52 | |||
| 53 | #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ | ||
| 54 | struct clk clk_##_name = { \ | ||
| 55 | .clk_rst = (void __iomem *)APMU_##_reg, \ | ||
| 56 | .enable_val = _eval, \ | ||
| 57 | .rate = _rate, \ | ||
| 58 | .ops = _ops, \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define INIT_CLKREG(_clk, _devname, _conname) \ | ||
| 62 | { \ | ||
| 63 | .clk = _clk, \ | ||
| 64 | .dev_id = _devname, \ | ||
| 65 | .con_id = _conname, \ | ||
| 66 | } | ||
| 67 | |||
| 68 | extern struct clk clk_pxa168_gpio; | ||
| 69 | extern struct clk clk_pxa168_timers; | ||
| 70 | |||
| 71 | extern void clks_register(struct clk_lookup *, size_t); | ||
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c new file mode 100644 index 000000000000..e1e66c18b446 --- /dev/null +++ b/arch/arm/mach-mmp/common.c | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/common.c | ||
| 3 | * | ||
| 4 | * Code common to PXA168 processor lines | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | |||
| 14 | #include <asm/page.h> | ||
| 15 | #include <asm/mach/map.h> | ||
| 16 | #include <mach/addr-map.h> | ||
| 17 | |||
| 18 | #include "common.h" | ||
| 19 | |||
| 20 | static struct map_desc standard_io_desc[] __initdata = { | ||
| 21 | { | ||
| 22 | .pfn = __phys_to_pfn(APB_PHYS_BASE), | ||
| 23 | .virtual = APB_VIRT_BASE, | ||
| 24 | .length = APB_PHYS_SIZE, | ||
| 25 | .type = MT_DEVICE, | ||
| 26 | }, { | ||
| 27 | .pfn = __phys_to_pfn(AXI_PHYS_BASE), | ||
| 28 | .virtual = AXI_VIRT_BASE, | ||
| 29 | .length = AXI_PHYS_SIZE, | ||
| 30 | .type = MT_DEVICE, | ||
| 31 | }, | ||
| 32 | }; | ||
| 33 | |||
| 34 | void __init pxa_map_io(void) | ||
| 35 | { | ||
| 36 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | ||
| 37 | } | ||
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h new file mode 100644 index 000000000000..c33fbbc49417 --- /dev/null +++ b/arch/arm/mach-mmp/common.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
| 2 | |||
| 3 | struct sys_timer; | ||
| 4 | |||
| 5 | extern void timer_init(int irq); | ||
| 6 | |||
| 7 | extern struct sys_timer pxa168_timer; | ||
| 8 | extern struct sys_timer pxa910_timer; | ||
| 9 | extern void __init pxa168_init_irq(void); | ||
| 10 | extern void __init pxa910_init_irq(void); | ||
| 11 | |||
| 12 | extern void __init icu_init_irq(void); | ||
| 13 | extern void __init pxa_map_io(void); | ||
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c new file mode 100644 index 000000000000..191d9dea8731 --- /dev/null +++ b/arch/arm/mach-mmp/devices.c | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/devices.c | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/platform_device.h> | ||
| 11 | #include <linux/dma-mapping.h> | ||
| 12 | |||
| 13 | #include <asm/irq.h> | ||
| 14 | #include <mach/devices.h> | ||
| 15 | |||
| 16 | int __init pxa_register_device(struct pxa_device_desc *desc, | ||
| 17 | void *data, size_t size) | ||
| 18 | { | ||
| 19 | struct platform_device *pdev; | ||
| 20 | struct resource res[2 + MAX_RESOURCE_DMA]; | ||
| 21 | int i, ret = 0, nres = 0; | ||
| 22 | |||
| 23 | pdev = platform_device_alloc(desc->drv_name, desc->id); | ||
| 24 | if (pdev == NULL) | ||
| 25 | return -ENOMEM; | ||
| 26 | |||
| 27 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | ||
| 28 | |||
| 29 | memset(res, 0, sizeof(res)); | ||
| 30 | |||
| 31 | if (desc->start != -1ul && desc->size > 0) { | ||
| 32 | res[nres].start = desc->start; | ||
| 33 | res[nres].end = desc->start + desc->size - 1; | ||
| 34 | res[nres].flags = IORESOURCE_MEM; | ||
| 35 | nres++; | ||
| 36 | } | ||
| 37 | |||
| 38 | if (desc->irq != NO_IRQ) { | ||
| 39 | res[nres].start = desc->irq; | ||
| 40 | res[nres].end = desc->irq; | ||
| 41 | res[nres].flags = IORESOURCE_IRQ; | ||
| 42 | nres++; | ||
| 43 | } | ||
| 44 | |||
| 45 | for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) { | ||
| 46 | if (desc->dma[i] == 0) | ||
| 47 | break; | ||
| 48 | |||
| 49 | res[nres].start = desc->dma[i]; | ||
| 50 | res[nres].end = desc->dma[i]; | ||
| 51 | res[nres].flags = IORESOURCE_DMA; | ||
| 52 | } | ||
| 53 | |||
| 54 | ret = platform_device_add_resources(pdev, res, nres); | ||
| 55 | if (ret) { | ||
| 56 | platform_device_put(pdev); | ||
| 57 | return ret; | ||
| 58 | } | ||
| 59 | |||
| 60 | if (data && size) { | ||
| 61 | ret = platform_device_add_data(pdev, data, size); | ||
| 62 | if (ret) { | ||
| 63 | platform_device_put(pdev); | ||
| 64 | return ret; | ||
| 65 | } | ||
| 66 | } | ||
| 67 | |||
| 68 | return platform_device_add(pdev); | ||
| 69 | } | ||
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h new file mode 100644 index 000000000000..3254089a644d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/addr-map.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/addr-map.h | ||
| 3 | * | ||
| 4 | * Common address map definitions | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_ADDR_MAP_H | ||
| 12 | #define __ASM_MACH_ADDR_MAP_H | ||
| 13 | |||
| 14 | /* APB - Application Subsystem Peripheral Bus | ||
| 15 | * | ||
| 16 | * NOTE: the DMA controller registers are actually on the AXI fabric #1 | ||
| 17 | * slave port to AHB/APB bridge, due to its close relationship to those | ||
| 18 | * peripherals on APB, let's count it into the ABP mapping area. | ||
| 19 | */ | ||
| 20 | #define APB_PHYS_BASE 0xd4000000 | ||
| 21 | #define APB_VIRT_BASE 0xfe000000 | ||
| 22 | #define APB_PHYS_SIZE 0x00200000 | ||
| 23 | |||
| 24 | #define AXI_PHYS_BASE 0xd4200000 | ||
| 25 | #define AXI_VIRT_BASE 0xfe200000 | ||
| 26 | #define AXI_PHYS_SIZE 0x00200000 | ||
| 27 | |||
| 28 | /* Static Memory Controller - Chip Select 0 and 1 */ | ||
| 29 | #define SMC_CS0_PHYS_BASE 0x80000000 | ||
| 30 | #define SMC_CS0_PHYS_SIZE 0x10000000 | ||
| 31 | #define SMC_CS1_PHYS_BASE 0x90000000 | ||
| 32 | #define SMC_CS1_PHYS_SIZE 0x10000000 | ||
| 33 | |||
| 34 | #endif /* __ASM_MACH_ADDR_MAP_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/clkdev.h b/arch/arm/mach-mmp/include/mach/clkdev.h new file mode 100644 index 000000000000..2fb354e54e0d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/clkdev.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #define __clk_get(clk) ({ 1; }) | ||
| 5 | #define __clk_put(clk) do { } while (0) | ||
| 6 | |||
| 7 | #endif /* __ASM_MACH_CLKDEV_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h new file mode 100644 index 000000000000..25e797b09083 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/cputype.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | #ifndef __ASM_MACH_CPUTYPE_H | ||
| 2 | #define __ASM_MACH_CPUTYPE_H | ||
| 3 | |||
| 4 | #include <asm/cputype.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * CPU Stepping OLD_ID CPU_ID CHIP_ID | ||
| 8 | * | ||
| 9 | * PXA168 A0 0x41159263 0x56158400 0x00A0A333 | ||
| 10 | * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifdef CONFIG_CPU_PXA168 | ||
| 14 | # define __cpu_is_pxa168(id) \ | ||
| 15 | ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; }) | ||
| 16 | #else | ||
| 17 | # define __cpu_is_pxa168(id) (0) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifdef CONFIG_CPU_PXA910 | ||
| 21 | # define __cpu_is_pxa910(id) \ | ||
| 22 | ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; }) | ||
| 23 | #else | ||
| 24 | # define __cpu_is_pxa910(id) (0) | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) | ||
| 28 | #define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) | ||
| 29 | |||
| 30 | #endif /* __ASM_MACH_CPUTYPE_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S new file mode 100644 index 000000000000..a850f87de51d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* arch/arm/mach-mmp/include/mach/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copied from arch/arm/mach-pxa/include/mach/debug.S | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <mach/addr-map.h> | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | ldreq \rx, =APB_PHYS_BASE @ physical | ||
| 18 | ldrne \rx, =APB_VIRT_BASE @ virtual | ||
| 19 | orr \rx, \rx, #0x00017000 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | #define UART_SHIFT 2 | ||
| 23 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h new file mode 100644 index 000000000000..24585397217e --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/devices.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | #include <linux/types.h> | ||
| 2 | |||
| 3 | #define MAX_RESOURCE_DMA 2 | ||
| 4 | |||
| 5 | /* structure for describing the on-chip devices */ | ||
| 6 | struct pxa_device_desc { | ||
| 7 | const char *dev_name; | ||
| 8 | const char *drv_name; | ||
| 9 | int id; | ||
| 10 | int irq; | ||
| 11 | unsigned long start; | ||
| 12 | unsigned long size; | ||
| 13 | int dma[MAX_RESOURCE_DMA]; | ||
| 14 | }; | ||
| 15 | |||
| 16 | #define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ | ||
| 17 | struct pxa_device_desc pxa168_device_##_name __initdata = { \ | ||
| 18 | .dev_name = "pxa168-" #_name, \ | ||
| 19 | .drv_name = _drv, \ | ||
| 20 | .id = _id, \ | ||
| 21 | .irq = IRQ_PXA168_##_irq, \ | ||
| 22 | .start = _start, \ | ||
| 23 | .size = _size, \ | ||
| 24 | .dma = { _dma }, \ | ||
| 25 | }; | ||
| 26 | |||
| 27 | #define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ | ||
| 28 | struct pxa_device_desc pxa910_device_##_name __initdata = { \ | ||
| 29 | .dev_name = "pxa910-" #_name, \ | ||
| 30 | .drv_name = _drv, \ | ||
| 31 | .id = _id, \ | ||
| 32 | .irq = IRQ_PXA910_##_irq, \ | ||
| 33 | .start = _start, \ | ||
| 34 | .size = _size, \ | ||
| 35 | .dma = { _dma }, \ | ||
| 36 | }; | ||
| 37 | extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); | ||
diff --git a/arch/arm/mach-mmp/include/mach/dma.h b/arch/arm/mach-mmp/include/mach/dma.h new file mode 100644 index 000000000000..1d6914544da4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/dma.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/dma.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_MACH_DMA_H | ||
| 6 | #define __ASM_MACH_DMA_H | ||
| 7 | |||
| 8 | #include <mach/addr-map.h> | ||
| 9 | |||
| 10 | #define DMAC_REGS_VIRT (APB_VIRT_BASE + 0x00000) | ||
| 11 | |||
| 12 | #include <plat/dma.h> | ||
| 13 | #endif /* __ASM_MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S new file mode 100644 index 000000000000..6d3cd35478b5 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/entry-macro.S | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <mach/regs-icu.h> | ||
| 10 | |||
| 11 | .macro disable_fiq | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 15 | .endm | ||
| 16 | |||
| 17 | .macro get_irqnr_preamble, base, tmp | ||
| 18 | ldr \base, =ICU_AP_IRQ_SEL_INT_NUM | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 22 | ldr \tmp, [\base, #0] | ||
| 23 | and \irqnr, \tmp, #0x3f | ||
| 24 | tst \tmp, #(1 << 6) | ||
| 25 | .endm | ||
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h new file mode 100644 index 000000000000..ab26d13295c4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/gpio.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | #ifndef __ASM_MACH_GPIO_H | ||
| 2 | #define __ASM_MACH_GPIO_H | ||
| 3 | |||
| 4 | #include <mach/addr-map.h> | ||
| 5 | #include <mach/irqs.h> | ||
| 6 | #include <asm-generic/gpio.h> | ||
| 7 | |||
| 8 | #define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) | ||
| 9 | |||
| 10 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | ||
| 11 | #define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) | ||
| 12 | |||
| 13 | #define NR_BUILTIN_GPIO (128) | ||
| 14 | |||
| 15 | #define gpio_to_bank(gpio) ((gpio) >> 5) | ||
| 16 | #define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) | ||
| 17 | #define irq_to_gpio(irq) ((irq) - IRQ_GPIO_START) | ||
| 18 | |||
| 19 | |||
| 20 | #define __gpio_is_inverted(gpio) (0) | ||
| 21 | #define __gpio_is_occupied(gpio) (0) | ||
| 22 | |||
| 23 | /* NOTE: these macros are defined here to make optimization of | ||
| 24 | * gpio_{get,set}_value() to work when 'gpio' is a constant. | ||
| 25 | * Usage of these macros otherwise is no longer recommended, | ||
| 26 | * use generic GPIO API whenever possible. | ||
| 27 | */ | ||
| 28 | #define GPIO_bit(gpio) (1 << ((gpio) & 0x1f)) | ||
| 29 | |||
| 30 | #define GPLR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00) | ||
| 31 | #define GPDR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c) | ||
| 32 | #define GPSR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18) | ||
| 33 | #define GPCR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24) | ||
| 34 | |||
| 35 | #include <plat/gpio.h> | ||
| 36 | #endif /* __ASM_MACH_GPIO_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/hardware.h b/arch/arm/mach-mmp/include/mach/hardware.h new file mode 100644 index 000000000000..99264a5ce5e4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/hardware.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef __ASM_MACH_HARDWARE_H | ||
| 2 | #define __ASM_MACH_HARDWARE_H | ||
| 3 | |||
| 4 | #endif /* __ASM_MACH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h new file mode 100644 index 000000000000..e7adf3d012c1 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/io.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/io.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_MACH_IO_H | ||
| 10 | #define __ASM_MACH_IO_H | ||
| 11 | |||
| 12 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 13 | |||
| 14 | /* | ||
| 15 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 16 | * drivers out there that might just work if we fake them... | ||
| 17 | */ | ||
| 18 | #define __io(a) __typesafe_io(a) | ||
| 19 | #define __mem_pci(a) (a) | ||
| 20 | |||
| 21 | #endif /* __ASM_MACH_IO_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h new file mode 100644 index 000000000000..e83e45ebf7a4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/irqs.h | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | #ifndef __ASM_MACH_IRQS_H | ||
| 2 | #define __ASM_MACH_IRQS_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Interrupt numbers for PXA168 | ||
| 6 | */ | ||
| 7 | #define IRQ_PXA168_NONE (-1) | ||
| 8 | #define IRQ_PXA168_SSP3 0 | ||
| 9 | #define IRQ_PXA168_SSP2 1 | ||
| 10 | #define IRQ_PXA168_SSP1 2 | ||
| 11 | #define IRQ_PXA168_SSP0 3 | ||
| 12 | #define IRQ_PXA168_PMIC_INT 4 | ||
| 13 | #define IRQ_PXA168_RTC_INT 5 | ||
| 14 | #define IRQ_PXA168_RTC_ALARM 6 | ||
| 15 | #define IRQ_PXA168_TWSI0 7 | ||
| 16 | #define IRQ_PXA168_GPU 8 | ||
| 17 | #define IRQ_PXA168_KEYPAD 9 | ||
| 18 | #define IRQ_PXA168_ONEWIRE 12 | ||
| 19 | #define IRQ_PXA168_TIMER1 13 | ||
| 20 | #define IRQ_PXA168_TIMER2 14 | ||
| 21 | #define IRQ_PXA168_TIMER3 15 | ||
| 22 | #define IRQ_PXA168_CMU 16 | ||
| 23 | #define IRQ_PXA168_SSP4 17 | ||
| 24 | #define IRQ_PXA168_MSP_WAKEUP 19 | ||
| 25 | #define IRQ_PXA168_CF_WAKEUP 20 | ||
| 26 | #define IRQ_PXA168_XD_WAKEUP 21 | ||
| 27 | #define IRQ_PXA168_MFU 22 | ||
| 28 | #define IRQ_PXA168_MSP 23 | ||
| 29 | #define IRQ_PXA168_CF 24 | ||
| 30 | #define IRQ_PXA168_XD 25 | ||
| 31 | #define IRQ_PXA168_DDR_INT 26 | ||
| 32 | #define IRQ_PXA168_UART1 27 | ||
| 33 | #define IRQ_PXA168_UART2 28 | ||
| 34 | #define IRQ_PXA168_WDT 35 | ||
| 35 | #define IRQ_PXA168_FRQ_CHANGE 38 | ||
| 36 | #define IRQ_PXA168_SDH1 39 | ||
| 37 | #define IRQ_PXA168_SDH2 40 | ||
| 38 | #define IRQ_PXA168_LCD 41 | ||
| 39 | #define IRQ_PXA168_CI 42 | ||
| 40 | #define IRQ_PXA168_USB1 44 | ||
| 41 | #define IRQ_PXA168_NAND 45 | ||
| 42 | #define IRQ_PXA168_HIFI_DMA 46 | ||
| 43 | #define IRQ_PXA168_DMA_INT0 47 | ||
| 44 | #define IRQ_PXA168_DMA_INT1 48 | ||
| 45 | #define IRQ_PXA168_GPIOX 49 | ||
| 46 | #define IRQ_PXA168_USB2 51 | ||
| 47 | #define IRQ_PXA168_AC97 57 | ||
| 48 | #define IRQ_PXA168_TWSI1 58 | ||
| 49 | #define IRQ_PXA168_PMU 60 | ||
| 50 | #define IRQ_PXA168_SM_INT 63 | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Interrupt numbers for PXA910 | ||
| 54 | */ | ||
| 55 | #define IRQ_PXA910_AIRQ 0 | ||
| 56 | #define IRQ_PXA910_SSP3 1 | ||
| 57 | #define IRQ_PXA910_SSP2 2 | ||
| 58 | #define IRQ_PXA910_SSP1 3 | ||
| 59 | #define IRQ_PXA910_PMIC_INT 4 | ||
| 60 | #define IRQ_PXA910_RTC_INT 5 | ||
| 61 | #define IRQ_PXA910_RTC_ALARM 6 | ||
| 62 | #define IRQ_PXA910_TWSI0 7 | ||
| 63 | #define IRQ_PXA910_GPU 8 | ||
| 64 | #define IRQ_PXA910_KEYPAD 9 | ||
| 65 | #define IRQ_PXA910_ROTARY 10 | ||
| 66 | #define IRQ_PXA910_TRACKBALL 11 | ||
| 67 | #define IRQ_PXA910_ONEWIRE 12 | ||
| 68 | #define IRQ_PXA910_AP1_TIMER1 13 | ||
| 69 | #define IRQ_PXA910_AP1_TIMER2 14 | ||
| 70 | #define IRQ_PXA910_AP1_TIMER3 15 | ||
| 71 | #define IRQ_PXA910_IPC_AP0 16 | ||
| 72 | #define IRQ_PXA910_IPC_AP1 17 | ||
| 73 | #define IRQ_PXA910_IPC_AP2 18 | ||
| 74 | #define IRQ_PXA910_IPC_AP3 19 | ||
| 75 | #define IRQ_PXA910_IPC_AP4 20 | ||
| 76 | #define IRQ_PXA910_IPC_CP0 21 | ||
| 77 | #define IRQ_PXA910_IPC_CP1 22 | ||
| 78 | #define IRQ_PXA910_IPC_CP2 23 | ||
| 79 | #define IRQ_PXA910_IPC_CP3 24 | ||
| 80 | #define IRQ_PXA910_IPC_CP4 25 | ||
| 81 | #define IRQ_PXA910_L2_DDR 26 | ||
| 82 | #define IRQ_PXA910_UART2 27 | ||
| 83 | #define IRQ_PXA910_UART3 28 | ||
| 84 | #define IRQ_PXA910_AP2_TIMER1 29 | ||
| 85 | #define IRQ_PXA910_AP2_TIMER2 30 | ||
| 86 | #define IRQ_PXA910_CP2_TIMER1 31 | ||
| 87 | #define IRQ_PXA910_CP2_TIMER2 32 | ||
| 88 | #define IRQ_PXA910_CP2_TIMER3 33 | ||
| 89 | #define IRQ_PXA910_GSSP 34 | ||
| 90 | #define IRQ_PXA910_CP2_WDT 35 | ||
| 91 | #define IRQ_PXA910_MAIN_PMU 36 | ||
| 92 | #define IRQ_PXA910_CP_FREQ_CHG 37 | ||
| 93 | #define IRQ_PXA910_AP_FREQ_CHG 38 | ||
| 94 | #define IRQ_PXA910_MMC 39 | ||
| 95 | #define IRQ_PXA910_AEU 40 | ||
| 96 | #define IRQ_PXA910_LCD 41 | ||
| 97 | #define IRQ_PXA910_CCIC 42 | ||
| 98 | #define IRQ_PXA910_IRE 43 | ||
| 99 | #define IRQ_PXA910_USB1 44 | ||
| 100 | #define IRQ_PXA910_NAND 45 | ||
| 101 | #define IRQ_PXA910_HIFI_DMA 46 | ||
| 102 | #define IRQ_PXA910_DMA_INT0 47 | ||
| 103 | #define IRQ_PXA910_DMA_INT1 48 | ||
| 104 | #define IRQ_PXA910_AP_GPIO 49 | ||
| 105 | #define IRQ_PXA910_AP2_TIMER3 50 | ||
| 106 | #define IRQ_PXA910_USB2 51 | ||
| 107 | #define IRQ_PXA910_TWSI1 54 | ||
| 108 | #define IRQ_PXA910_CP_GPIO 55 | ||
| 109 | #define IRQ_PXA910_UART1 59 /* Slow UART */ | ||
| 110 | #define IRQ_PXA910_AP_PMU 60 | ||
| 111 | #define IRQ_PXA910_SM_INT 63 /* from PinMux */ | ||
| 112 | |||
| 113 | #define IRQ_GPIO_START 64 | ||
| 114 | #define IRQ_GPIO_NUM 128 | ||
| 115 | #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) | ||
| 116 | |||
| 117 | #define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) | ||
| 118 | |||
| 119 | #endif /* __ASM_MACH_IRQS_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h new file mode 100644 index 000000000000..bdb21d70714c --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/memory.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/memory.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_MACH_MEMORY_H | ||
| 10 | #define __ASM_MACH_MEMORY_H | ||
| 11 | |||
| 12 | #define PHYS_OFFSET UL(0x00000000) | ||
| 13 | |||
| 14 | #endif /* __ASM_MACH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h new file mode 100644 index 000000000000..d0bdb6e3682b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h | |||
| @@ -0,0 +1,258 @@ | |||
| 1 | #ifndef __ASM_MACH_MFP_PXA168_H | ||
| 2 | #define __ASM_MACH_MFP_PXA168_H | ||
| 3 | |||
| 4 | #include <mach/mfp.h> | ||
| 5 | |||
| 6 | /* GPIO */ | ||
| 7 | #define GPIO0_GPIO MFP_CFG(GPIO0, AF5) | ||
| 8 | #define GPIO1_GPIO MFP_CFG(GPIO1, AF5) | ||
| 9 | #define GPIO2_GPIO MFP_CFG(GPIO2, AF5) | ||
| 10 | #define GPIO3_GPIO MFP_CFG(GPIO3, AF5) | ||
| 11 | #define GPIO4_GPIO MFP_CFG(GPIO4, AF5) | ||
| 12 | #define GPIO5_GPIO MFP_CFG(GPIO5, AF5) | ||
| 13 | #define GPIO6_GPIO MFP_CFG(GPIO6, AF5) | ||
| 14 | #define GPIO7_GPIO MFP_CFG(GPIO7, AF5) | ||
| 15 | #define GPIO8_GPIO MFP_CFG(GPIO8, AF5) | ||
| 16 | #define GPIO9_GPIO MFP_CFG(GPIO9, AF5) | ||
| 17 | #define GPIO10_GPIO MFP_CFG(GPIO10, AF5) | ||
| 18 | #define GPIO11_GPIO MFP_CFG(GPIO11, AF5) | ||
| 19 | #define GPIO12_GPIO MFP_CFG(GPIO12, AF5) | ||
| 20 | #define GPIO13_GPIO MFP_CFG(GPIO13, AF5) | ||
| 21 | #define GPIO14_GPIO MFP_CFG(GPIO14, AF5) | ||
| 22 | #define GPIO15_GPIO MFP_CFG(GPIO15, AF5) | ||
| 23 | #define GPIO16_GPIO MFP_CFG(GPIO16, AF0) | ||
| 24 | #define GPIO17_GPIO MFP_CFG(GPIO17, AF5) | ||
| 25 | #define GPIO18_GPIO MFP_CFG(GPIO18, AF0) | ||
| 26 | #define GPIO19_GPIO MFP_CFG(GPIO19, AF5) | ||
| 27 | #define GPIO20_GPIO MFP_CFG(GPIO20, AF0) | ||
| 28 | #define GPIO21_GPIO MFP_CFG(GPIO21, AF5) | ||
| 29 | #define GPIO22_GPIO MFP_CFG(GPIO22, AF5) | ||
| 30 | #define GPIO23_GPIO MFP_CFG(GPIO23, AF5) | ||
| 31 | #define GPIO24_GPIO MFP_CFG(GPIO24, AF5) | ||
| 32 | #define GPIO25_GPIO MFP_CFG(GPIO25, AF5) | ||
| 33 | #define GPIO26_GPIO MFP_CFG(GPIO26, AF0) | ||
| 34 | #define GPIO27_GPIO MFP_CFG(GPIO27, AF5) | ||
| 35 | #define GPIO28_GPIO MFP_CFG(GPIO28, AF5) | ||
| 36 | #define GPIO29_GPIO MFP_CFG(GPIO29, AF5) | ||
| 37 | #define GPIO30_GPIO MFP_CFG(GPIO30, AF5) | ||
| 38 | #define GPIO31_GPIO MFP_CFG(GPIO31, AF5) | ||
| 39 | #define GPIO32_GPIO MFP_CFG(GPIO32, AF5) | ||
| 40 | #define GPIO33_GPIO MFP_CFG(GPIO33, AF5) | ||
| 41 | #define GPIO34_GPIO MFP_CFG(GPIO34, AF0) | ||
| 42 | #define GPIO35_GPIO MFP_CFG(GPIO35, AF0) | ||
| 43 | #define GPIO36_GPIO MFP_CFG(GPIO36, AF0) | ||
| 44 | #define GPIO37_GPIO MFP_CFG(GPIO37, AF0) | ||
| 45 | #define GPIO38_GPIO MFP_CFG(GPIO38, AF0) | ||
| 46 | #define GPIO39_GPIO MFP_CFG(GPIO39, AF0) | ||
| 47 | #define GPIO40_GPIO MFP_CFG(GPIO40, AF0) | ||
| 48 | #define GPIO41_GPIO MFP_CFG(GPIO41, AF0) | ||
| 49 | #define GPIO42_GPIO MFP_CFG(GPIO42, AF0) | ||
| 50 | #define GPIO43_GPIO MFP_CFG(GPIO43, AF0) | ||
| 51 | #define GPIO44_GPIO MFP_CFG(GPIO44, AF0) | ||
| 52 | #define GPIO45_GPIO MFP_CFG(GPIO45, AF0) | ||
| 53 | #define GPIO46_GPIO MFP_CFG(GPIO46, AF0) | ||
| 54 | #define GPIO47_GPIO MFP_CFG(GPIO47, AF0) | ||
| 55 | #define GPIO48_GPIO MFP_CFG(GPIO48, AF0) | ||
| 56 | #define GPIO49_GPIO MFP_CFG(GPIO49, AF0) | ||
| 57 | #define GPIO50_GPIO MFP_CFG(GPIO50, AF0) | ||
| 58 | #define GPIO51_GPIO MFP_CFG(GPIO51, AF0) | ||
| 59 | #define GPIO52_GPIO MFP_CFG(GPIO52, AF0) | ||
| 60 | #define GPIO53_GPIO MFP_CFG(GPIO53, AF0) | ||
| 61 | #define GPIO54_GPIO MFP_CFG(GPIO54, AF0) | ||
| 62 | #define GPIO55_GPIO MFP_CFG(GPIO55, AF0) | ||
| 63 | #define GPIO56_GPIO MFP_CFG(GPIO56, AF0) | ||
| 64 | #define GPIO57_GPIO MFP_CFG(GPIO57, AF0) | ||
| 65 | #define GPIO58_GPIO MFP_CFG(GPIO58, AF0) | ||
| 66 | #define GPIO59_GPIO MFP_CFG(GPIO59, AF0) | ||
| 67 | #define GPIO60_GPIO MFP_CFG(GPIO60, AF0) | ||
| 68 | #define GPIO61_GPIO MFP_CFG(GPIO61, AF0) | ||
| 69 | #define GPIO62_GPIO MFP_CFG(GPIO62, AF0) | ||
| 70 | #define GPIO63_GPIO MFP_CFG(GPIO63, AF0) | ||
| 71 | #define GPIO64_GPIO MFP_CFG(GPIO64, AF0) | ||
| 72 | #define GPIO65_GPIO MFP_CFG(GPIO65, AF0) | ||
| 73 | #define GPIO66_GPIO MFP_CFG(GPIO66, AF0) | ||
| 74 | #define GPIO67_GPIO MFP_CFG(GPIO67, AF0) | ||
| 75 | #define GPIO68_GPIO MFP_CFG(GPIO68, AF0) | ||
| 76 | #define GPIO69_GPIO MFP_CFG(GPIO69, AF0) | ||
| 77 | #define GPIO70_GPIO MFP_CFG(GPIO70, AF0) | ||
| 78 | #define GPIO71_GPIO MFP_CFG(GPIO71, AF0) | ||
| 79 | #define GPIO72_GPIO MFP_CFG(GPIO72, AF0) | ||
| 80 | #define GPIO73_GPIO MFP_CFG(GPIO73, AF0) | ||
| 81 | #define GPIO74_GPIO MFP_CFG(GPIO74, AF0) | ||
| 82 | #define GPIO75_GPIO MFP_CFG(GPIO75, AF0) | ||
| 83 | #define GPIO76_GPIO MFP_CFG(GPIO76, AF0) | ||
| 84 | #define GPIO77_GPIO MFP_CFG(GPIO77, AF0) | ||
| 85 | #define GPIO78_GPIO MFP_CFG(GPIO78, AF0) | ||
| 86 | #define GPIO79_GPIO MFP_CFG(GPIO79, AF0) | ||
| 87 | #define GPIO80_GPIO MFP_CFG(GPIO80, AF0) | ||
| 88 | #define GPIO81_GPIO MFP_CFG(GPIO81, AF0) | ||
| 89 | #define GPIO82_GPIO MFP_CFG(GPIO82, AF0) | ||
| 90 | #define GPIO83_GPIO MFP_CFG(GPIO83, AF0) | ||
| 91 | #define GPIO84_GPIO MFP_CFG(GPIO84, AF0) | ||
| 92 | #define GPIO85_GPIO MFP_CFG(GPIO85, AF0) | ||
| 93 | #define GPIO86_GPIO MFP_CFG(GPIO86, AF0) | ||
| 94 | #define GPIO87_GPIO MFP_CFG(GPIO87, AF0) | ||
| 95 | #define GPIO88_GPIO MFP_CFG(GPIO88, AF0) | ||
| 96 | #define GPIO89_GPIO MFP_CFG(GPIO89, AF0) | ||
| 97 | #define GPIO90_GPIO MFP_CFG(GPIO90, AF0) | ||
| 98 | #define GPIO91_GPIO MFP_CFG(GPIO91, AF0) | ||
| 99 | #define GPIO92_GPIO MFP_CFG(GPIO92, AF0) | ||
| 100 | #define GPIO93_GPIO MFP_CFG(GPIO93, AF0) | ||
| 101 | #define GPIO94_GPIO MFP_CFG(GPIO94, AF0) | ||
| 102 | #define GPIO95_GPIO MFP_CFG(GPIO95, AF0) | ||
| 103 | #define GPIO96_GPIO MFP_CFG(GPIO96, AF0) | ||
| 104 | #define GPIO97_GPIO MFP_CFG(GPIO97, AF0) | ||
| 105 | #define GPIO98_GPIO MFP_CFG(GPIO98, AF0) | ||
| 106 | #define GPIO99_GPIO MFP_CFG(GPIO99, AF0) | ||
| 107 | #define GPIO100_GPIO MFP_CFG(GPIO100, AF0) | ||
| 108 | #define GPIO101_GPIO MFP_CFG(GPIO101, AF0) | ||
| 109 | #define GPIO102_GPIO MFP_CFG(GPIO102, AF0) | ||
| 110 | #define GPIO103_GPIO MFP_CFG(GPIO103, AF0) | ||
| 111 | #define GPIO104_GPIO MFP_CFG(GPIO104, AF0) | ||
| 112 | #define GPIO105_GPIO MFP_CFG(GPIO105, AF0) | ||
| 113 | #define GPIO106_GPIO MFP_CFG(GPIO106, AF0) | ||
| 114 | #define GPIO107_GPIO MFP_CFG(GPIO107, AF0) | ||
| 115 | #define GPIO108_GPIO MFP_CFG(GPIO108, AF0) | ||
| 116 | #define GPIO109_GPIO MFP_CFG(GPIO109, AF0) | ||
| 117 | #define GPIO110_GPIO MFP_CFG(GPIO110, AF0) | ||
| 118 | #define GPIO111_GPIO MFP_CFG(GPIO111, AF0) | ||
| 119 | #define GPIO112_GPIO MFP_CFG(GPIO112, AF0) | ||
| 120 | #define GPIO113_GPIO MFP_CFG(GPIO113, AF0) | ||
| 121 | #define GPIO114_GPIO MFP_CFG(GPIO114, AF0) | ||
| 122 | #define GPIO115_GPIO MFP_CFG(GPIO115, AF0) | ||
| 123 | #define GPIO116_GPIO MFP_CFG(GPIO116, AF0) | ||
| 124 | #define GPIO117_GPIO MFP_CFG(GPIO117, AF0) | ||
| 125 | #define GPIO118_GPIO MFP_CFG(GPIO118, AF0) | ||
| 126 | #define GPIO119_GPIO MFP_CFG(GPIO119, AF0) | ||
| 127 | #define GPIO120_GPIO MFP_CFG(GPIO120, AF0) | ||
| 128 | #define GPIO121_GPIO MFP_CFG(GPIO121, AF0) | ||
| 129 | #define GPIO122_GPIO MFP_CFG(GPIO122, AF0) | ||
| 130 | |||
| 131 | /* DFI */ | ||
| 132 | #define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0) | ||
| 133 | #define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0) | ||
| 134 | #define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0) | ||
| 135 | #define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0) | ||
| 136 | #define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0) | ||
| 137 | #define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0) | ||
| 138 | #define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0) | ||
| 139 | #define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0) | ||
| 140 | #define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0) | ||
| 141 | #define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0) | ||
| 142 | #define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0) | ||
| 143 | #define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0) | ||
| 144 | #define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0) | ||
| 145 | #define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0) | ||
| 146 | #define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0) | ||
| 147 | #define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0) | ||
| 148 | |||
| 149 | #define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0) | ||
| 150 | #define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0) | ||
| 151 | #define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0) | ||
| 152 | #define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0) | ||
| 153 | |||
| 154 | /* NAND */ | ||
| 155 | #define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1) | ||
| 156 | #define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0) | ||
| 157 | #define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0) | ||
| 158 | #define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0) | ||
| 159 | #define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0) | ||
| 160 | #define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1) | ||
| 161 | #define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1) | ||
| 162 | |||
| 163 | /* Static Memory Controller */ | ||
| 164 | #define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3) | ||
| 165 | #define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2) | ||
| 166 | #define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2) | ||
| 167 | #define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3) | ||
| 168 | #define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0) | ||
| 169 | #define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2) | ||
| 170 | #define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0) | ||
| 171 | #define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0) | ||
| 172 | #define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0) | ||
| 173 | #define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0) | ||
| 174 | #define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0) | ||
| 175 | #define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2) | ||
| 176 | #define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2) | ||
| 177 | #define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2) | ||
| 178 | |||
| 179 | /* Compact Flash */ | ||
| 180 | #define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3) | ||
| 181 | #define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3) | ||
| 182 | #define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3) | ||
| 183 | #define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3) | ||
| 184 | #define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3) | ||
| 185 | #define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3) | ||
| 186 | #define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3) | ||
| 187 | #define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3) | ||
| 188 | #define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3) | ||
| 189 | #define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3) | ||
| 190 | |||
| 191 | /* UART1 */ | ||
| 192 | #define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST) | ||
| 193 | #define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST) | ||
| 194 | #define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST) | ||
| 195 | #define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST) | ||
| 196 | #define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1) | ||
| 197 | #define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2) | ||
| 198 | #define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1) | ||
| 199 | #define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2) | ||
| 200 | #define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1) | ||
| 201 | #define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2) | ||
| 202 | #define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1) | ||
| 203 | #define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2) | ||
| 204 | |||
| 205 | /* MMC1 */ | ||
| 206 | #define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1) | ||
| 207 | #define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1) | ||
| 208 | #define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1) | ||
| 209 | #define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1) | ||
| 210 | #define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1) | ||
| 211 | #define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1) | ||
| 212 | #define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1) | ||
| 213 | #define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1) | ||
| 214 | #define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1) | ||
| 215 | #define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1) | ||
| 216 | #define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1) | ||
| 217 | #define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1) | ||
| 218 | |||
| 219 | /* LCD */ | ||
| 220 | #define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1) | ||
| 221 | #define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1) | ||
| 222 | #define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1) | ||
| 223 | #define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1) | ||
| 224 | #define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1) | ||
| 225 | #define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1) | ||
| 226 | #define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1) | ||
| 227 | #define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1) | ||
| 228 | #define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1) | ||
| 229 | #define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1) | ||
| 230 | #define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1) | ||
| 231 | #define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1) | ||
| 232 | #define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1) | ||
| 233 | #define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1) | ||
| 234 | #define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1) | ||
| 235 | #define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1) | ||
| 236 | #define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1) | ||
| 237 | #define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1) | ||
| 238 | #define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1) | ||
| 239 | #define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1) | ||
| 240 | #define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1) | ||
| 241 | #define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1) | ||
| 242 | #define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1) | ||
| 243 | #define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1) | ||
| 244 | #define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1) | ||
| 245 | #define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1) | ||
| 246 | #define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1) | ||
| 247 | #define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1) | ||
| 248 | #define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1) | ||
| 249 | #define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1) | ||
| 250 | |||
| 251 | /* I2S */ | ||
| 252 | #define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6) | ||
| 253 | #define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1) | ||
| 254 | #define GPIO115_I2S_BCLK MFP_CFG(GPIO115,AF1) | ||
| 255 | #define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2) | ||
| 256 | #define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2) | ||
| 257 | |||
| 258 | #endif /* __ASM_MACH_MFP_PXA168_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h new file mode 100644 index 000000000000..48a1cbc7c56b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h | |||
| @@ -0,0 +1,157 @@ | |||
| 1 | #ifndef __ASM_MACH_MFP_PXA910_H | ||
| 2 | #define __ASM_MACH_MFP_PXA910_H | ||
| 3 | |||
| 4 | #include <mach/mfp.h> | ||
| 5 | |||
| 6 | /* UART2 */ | ||
| 7 | #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) | ||
| 8 | #define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6) | ||
| 9 | |||
| 10 | /* UART3 */ | ||
| 11 | #define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4) | ||
| 12 | #define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4) | ||
| 13 | |||
| 14 | /*IRDA*/ | ||
| 15 | #define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0) | ||
| 16 | |||
| 17 | /* SMC */ | ||
| 18 | #define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0) | ||
| 19 | #define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0) | ||
| 20 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | ||
| 21 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | ||
| 22 | #define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1) | ||
| 23 | #define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1) | ||
| 24 | |||
| 25 | /* I2C */ | ||
| 26 | #define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2) | ||
| 27 | #define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2) | ||
| 28 | |||
| 29 | /* SSP1 (I2S) */ | ||
| 30 | #define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM) | ||
| 31 | #define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM) | ||
| 32 | #define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM) | ||
| 33 | #define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM) | ||
| 34 | #define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM) | ||
| 35 | #define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM) | ||
| 36 | #define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM) | ||
| 37 | |||
| 38 | /* DFI */ | ||
| 39 | #define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0) | ||
| 40 | #define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0) | ||
| 41 | #define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0) | ||
| 42 | #define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0) | ||
| 43 | #define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0) | ||
| 44 | #define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0) | ||
| 45 | #define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0) | ||
| 46 | #define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0) | ||
| 47 | #define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0) | ||
| 48 | #define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0) | ||
| 49 | #define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0) | ||
| 50 | #define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0) | ||
| 51 | #define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0) | ||
| 52 | #define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0) | ||
| 53 | #define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0) | ||
| 54 | #define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0) | ||
| 55 | #define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0) | ||
| 56 | #define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1) | ||
| 57 | #define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0) | ||
| 58 | #define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1) | ||
| 59 | #define DF_REn_DF_REn MFP_CFG(DF_REn, AF1) | ||
| 60 | #define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0) | ||
| 61 | |||
| 62 | /*keypad*/ | ||
| 63 | #define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) | ||
| 64 | #define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) | ||
| 65 | #define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) | ||
| 66 | #define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) | ||
| 67 | #define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) | ||
| 68 | #define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) | ||
| 69 | #define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) | ||
| 70 | #define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) | ||
| 71 | #define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) | ||
| 72 | #define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) | ||
| 73 | #define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) | ||
| 74 | #define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) | ||
| 75 | #define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) | ||
| 76 | #define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) | ||
| 77 | #define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) | ||
| 78 | #define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) | ||
| 79 | #define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) | ||
| 80 | #define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) | ||
| 81 | #define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) | ||
| 82 | #define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) | ||
| 83 | |||
| 84 | /* LCD */ | ||
| 85 | #define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1) | ||
| 86 | #define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1) | ||
| 87 | #define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1) | ||
| 88 | #define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1) | ||
| 89 | #define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1) | ||
| 90 | #define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1) | ||
| 91 | #define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1) | ||
| 92 | #define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1) | ||
| 93 | #define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1) | ||
| 94 | #define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1) | ||
| 95 | #define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1) | ||
| 96 | #define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1) | ||
| 97 | #define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1) | ||
| 98 | #define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1) | ||
| 99 | #define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1) | ||
| 100 | #define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1) | ||
| 101 | #define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1) | ||
| 102 | #define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1) | ||
| 103 | #define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1) | ||
| 104 | #define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1) | ||
| 105 | #define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1) | ||
| 106 | #define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1) | ||
| 107 | #define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1) | ||
| 108 | #define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1) | ||
| 109 | #define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1) | ||
| 110 | #define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1) | ||
| 111 | #define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1) | ||
| 112 | #define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1) | ||
| 113 | |||
| 114 | #define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3) | ||
| 115 | #define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3) | ||
| 116 | #define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3) | ||
| 117 | #define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3) | ||
| 118 | |||
| 119 | #define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0) | ||
| 120 | |||
| 121 | /*smart panel*/ | ||
| 122 | #define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0) | ||
| 123 | #define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0) | ||
| 124 | #define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0) | ||
| 125 | |||
| 126 | /*1wire*/ | ||
| 127 | #define GPIO106_1WIRE MFP_CFG(GPIO106, AF3) | ||
| 128 | |||
| 129 | /*CCIC*/ | ||
| 130 | #define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM) | ||
| 131 | #define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM) | ||
| 132 | #define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM) | ||
| 133 | #define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM) | ||
| 134 | #define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM) | ||
| 135 | #define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM) | ||
| 136 | #define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM) | ||
| 137 | #define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM) | ||
| 138 | #define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM) | ||
| 139 | #define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM) | ||
| 140 | #define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM) | ||
| 141 | #define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM) | ||
| 142 | |||
| 143 | /* MMC1 */ | ||
| 144 | #define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM) | ||
| 145 | #define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM) | ||
| 146 | #define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM) | ||
| 147 | #define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM) | ||
| 148 | #define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM) | ||
| 149 | #define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM) | ||
| 150 | #define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM) | ||
| 151 | #define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM) | ||
| 152 | #define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM) | ||
| 153 | #define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM) | ||
| 154 | #define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM) | ||
| 155 | #define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM) | ||
| 156 | |||
| 157 | #endif /* __ASM_MACH MFP_PXA910_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h new file mode 100644 index 000000000000..277ea4cd0f9f --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | #ifndef __ASM_MACH_MFP_H | ||
| 2 | #define __ASM_MACH_MFP_H | ||
| 3 | |||
| 4 | #include <plat/mfp.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * NOTE: the MFPR register bit definitions on PXA168 processor lines are a | ||
| 8 | * bit different from those on PXA3xx. Bit [7:10] are now reserved, which | ||
| 9 | * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits. | ||
| 10 | * | ||
| 11 | * To cope with this difference and re-use the pxa3xx mfp code as much as | ||
| 12 | * possible, we make the following compromise: | ||
| 13 | * | ||
| 14 | * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT) | ||
| 15 | * 2. DRIVE strength definitions redefined to include the reserved bit10 | ||
| 16 | * 3. Override MFP_CFG() and MFP_CFG_DRV() | ||
| 17 | * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X() | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define MFP_DRIVE_VERY_SLOW (0x0 << 13) | ||
| 21 | #define MFP_DRIVE_SLOW (0x2 << 13) | ||
| 22 | #define MFP_DRIVE_MEDIUM (0x4 << 13) | ||
| 23 | #define MFP_DRIVE_FAST (0x8 << 13) | ||
| 24 | |||
| 25 | #undef MFP_CFG | ||
| 26 | #undef MFP_CFG_DRV | ||
| 27 | #undef MFP_CFG_LPM | ||
| 28 | #undef MFP_CFG_X | ||
| 29 | #undef MFP_CFG_DEFAULT | ||
| 30 | |||
| 31 | #define MFP_CFG(pin, af) \ | ||
| 32 | (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) | ||
| 33 | |||
| 34 | #define MFP_CFG_DRV(pin, af, drv) \ | ||
| 35 | (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) | ||
| 36 | |||
| 37 | #endif /* __ASM_MACH_MFP_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h new file mode 100644 index 000000000000..ef0a8a2076e9 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pxa168.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_PXA168_H | ||
| 2 | #define __ASM_MACH_PXA168_H | ||
| 3 | |||
| 4 | #include <mach/devices.h> | ||
| 5 | |||
| 6 | extern struct pxa_device_desc pxa168_device_uart1; | ||
| 7 | extern struct pxa_device_desc pxa168_device_uart2; | ||
| 8 | |||
| 9 | static inline int pxa168_add_uart(int id) | ||
| 10 | { | ||
| 11 | struct pxa_device_desc *d = NULL; | ||
| 12 | |||
| 13 | switch (id) { | ||
| 14 | case 1: d = &pxa168_device_uart1; break; | ||
| 15 | case 2: d = &pxa168_device_uart2; break; | ||
| 16 | } | ||
| 17 | |||
| 18 | if (d == NULL) | ||
| 19 | return -EINVAL; | ||
| 20 | |||
| 21 | return pxa_register_device(d, NULL, 0); | ||
| 22 | } | ||
| 23 | #endif /* __ASM_MACH_PXA168_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h new file mode 100644 index 000000000000..b7aeaf574c36 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pxa910.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_PXA910_H | ||
| 2 | #define __ASM_MACH_PXA910_H | ||
| 3 | |||
| 4 | #include <mach/devices.h> | ||
| 5 | |||
| 6 | extern struct pxa_device_desc pxa910_device_uart1; | ||
| 7 | extern struct pxa_device_desc pxa910_device_uart2; | ||
| 8 | |||
| 9 | static inline int pxa910_add_uart(int id) | ||
| 10 | { | ||
| 11 | struct pxa_device_desc *d = NULL; | ||
| 12 | |||
| 13 | switch (id) { | ||
| 14 | case 1: d = &pxa910_device_uart1; break; | ||
| 15 | case 2: d = &pxa910_device_uart2; break; | ||
| 16 | } | ||
| 17 | |||
| 18 | if (d == NULL) | ||
| 19 | return -EINVAL; | ||
| 20 | |||
| 21 | return pxa_register_device(d, NULL, 0); | ||
| 22 | } | ||
| 23 | #endif /* __ASM_MACH_PXA910_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h new file mode 100644 index 000000000000..c6b8c9dc2026 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h | ||
| 3 | * | ||
| 4 | * Application Peripheral Bus Clock Unit | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_REGS_APBC_H | ||
| 12 | #define __ASM_MACH_REGS_APBC_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) | ||
| 17 | #define APBC_REG(x) (APBC_VIRT_BASE + (x)) | ||
| 18 | |||
| 19 | /* | ||
| 20 | * APB clock register offsets for PXA168 | ||
| 21 | */ | ||
| 22 | #define APBC_PXA168_UART1 APBC_REG(0x000) | ||
| 23 | #define APBC_PXA168_UART2 APBC_REG(0x004) | ||
| 24 | #define APBC_PXA168_GPIO APBC_REG(0x008) | ||
| 25 | #define APBC_PXA168_PWM0 APBC_REG(0x00c) | ||
| 26 | #define APBC_PXA168_PWM1 APBC_REG(0x010) | ||
| 27 | #define APBC_PXA168_SSP1 APBC_REG(0x01c) | ||
| 28 | #define APBC_PXA168_SSP2 APBC_REG(0x020) | ||
| 29 | #define APBC_PXA168_RTC APBC_REG(0x028) | ||
| 30 | #define APBC_PXA168_TWSI0 APBC_REG(0x02c) | ||
| 31 | #define APBC_PXA168_KPC APBC_REG(0x030) | ||
| 32 | #define APBC_PXA168_TIMERS APBC_REG(0x034) | ||
| 33 | #define APBC_PXA168_AIB APBC_REG(0x03c) | ||
| 34 | #define APBC_PXA168_SW_JTAG APBC_REG(0x040) | ||
| 35 | #define APBC_PXA168_ONEWIRE APBC_REG(0x048) | ||
| 36 | #define APBC_PXA168_SSP3 APBC_REG(0x04c) | ||
| 37 | #define APBC_PXA168_ASFAR APBC_REG(0x050) | ||
| 38 | #define APBC_PXA168_ASSAR APBC_REG(0x054) | ||
| 39 | #define APBC_PXA168_SSP4 APBC_REG(0x058) | ||
| 40 | #define APBC_PXA168_SSP5 APBC_REG(0x05c) | ||
| 41 | #define APBC_PXA168_TWSI1 APBC_REG(0x06c) | ||
| 42 | #define APBC_PXA168_UART3 APBC_REG(0x070) | ||
| 43 | #define APBC_PXA168_AC97 APBC_REG(0x084) | ||
| 44 | |||
| 45 | /* | ||
| 46 | * APB Clock register offsets for PXA910 | ||
| 47 | */ | ||
| 48 | #define APBC_PXA910_UART0 APBC_REG(0x000) | ||
| 49 | #define APBC_PXA910_UART1 APBC_REG(0x004) | ||
| 50 | #define APBC_PXA910_GPIO APBC_REG(0x008) | ||
| 51 | #define APBC_PXA910_PWM0 APBC_REG(0x00c) | ||
| 52 | #define APBC_PXA910_PWM1 APBC_REG(0x010) | ||
| 53 | #define APBC_PXA910_PWM2 APBC_REG(0x014) | ||
| 54 | #define APBC_PXA910_PWM3 APBC_REG(0x018) | ||
| 55 | #define APBC_PXA910_SSP1 APBC_REG(0x01c) | ||
| 56 | #define APBC_PXA910_SSP2 APBC_REG(0x020) | ||
| 57 | #define APBC_PXA910_IPC APBC_REG(0x024) | ||
| 58 | #define APBC_PXA910_TWSI0 APBC_REG(0x02c) | ||
| 59 | #define APBC_PXA910_KPC APBC_REG(0x030) | ||
| 60 | #define APBC_PXA910_TIMERS APBC_REG(0x034) | ||
| 61 | #define APBC_PXA910_TBROT APBC_REG(0x038) | ||
| 62 | #define APBC_PXA910_AIB APBC_REG(0x03c) | ||
| 63 | #define APBC_PXA910_SW_JTAG APBC_REG(0x040) | ||
| 64 | #define APBC_PXA910_TIMERS1 APBC_REG(0x044) | ||
| 65 | #define APBC_PXA910_ONEWIRE APBC_REG(0x048) | ||
| 66 | #define APBC_PXA910_SSP3 APBC_REG(0x04c) | ||
| 67 | #define APBC_PXA910_ASFAR APBC_REG(0x050) | ||
| 68 | #define APBC_PXA910_ASSAR APBC_REG(0x054) | ||
| 69 | |||
| 70 | /* Common APB clock register bit definitions */ | ||
| 71 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ | ||
| 72 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ | ||
| 73 | #define APBC_RST (1 << 2) /* Reset Generation */ | ||
| 74 | |||
| 75 | /* Functional Clock Selection Mask */ | ||
| 76 | #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) | ||
| 77 | |||
| 78 | #endif /* __ASM_MACH_REGS_APBC_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h new file mode 100644 index 000000000000..919030514120 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-apmu.h | ||
| 3 | * | ||
| 4 | * Application Subsystem Power Management Unit | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_REGS_APMU_H | ||
| 12 | #define __ASM_MACH_REGS_APMU_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) | ||
| 17 | #define APMU_REG(x) (APMU_VIRT_BASE + (x)) | ||
| 18 | |||
| 19 | /* Clock Reset Control */ | ||
| 20 | #define APMU_IRE APMU_REG(0x048) | ||
| 21 | #define APMU_LCD APMU_REG(0x04c) | ||
| 22 | #define APMU_CCIC APMU_REG(0x050) | ||
| 23 | #define APMU_SDH0 APMU_REG(0x054) | ||
| 24 | #define APMU_SDH1 APMU_REG(0x058) | ||
| 25 | #define APMU_USB APMU_REG(0x05c) | ||
| 26 | #define APMU_NAND APMU_REG(0x060) | ||
| 27 | #define APMU_DMA APMU_REG(0x064) | ||
| 28 | #define APMU_GEU APMU_REG(0x068) | ||
| 29 | #define APMU_BUS APMU_REG(0x06c) | ||
| 30 | |||
| 31 | #define APMU_FNCLK_EN (1 << 4) | ||
| 32 | #define APMU_AXICLK_EN (1 << 3) | ||
| 33 | #define APMU_FNRST_DIS (1 << 1) | ||
| 34 | #define APMU_AXIRST_DIS (1 << 0) | ||
| 35 | |||
| 36 | #endif /* __ASM_MACH_REGS_APMU_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h new file mode 100644 index 000000000000..e5f08723e0cc --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-icu.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-icu.h | ||
| 3 | * | ||
| 4 | * Interrupt Control Unit | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_ICU_H | ||
| 12 | #define __ASM_MACH_ICU_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000) | ||
| 17 | #define ICU_REG(x) (ICU_VIRT_BASE + (x)) | ||
| 18 | |||
| 19 | #define ICU_INT_CONF(n) ICU_REG((n) << 2) | ||
| 20 | #define ICU_INT_CONF_AP_INT (1 << 6) | ||
| 21 | #define ICU_INT_CONF_CP_INT (1 << 5) | ||
| 22 | #define ICU_INT_CONF_IRQ (1 << 4) | ||
| 23 | #define ICU_INT_CONF_MASK (0xf) | ||
| 24 | |||
| 25 | #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ | ||
| 26 | #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ | ||
| 27 | #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */ | ||
| 28 | #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ | ||
| 29 | #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ | ||
| 30 | |||
| 31 | #endif /* __ASM_MACH_ICU_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h new file mode 100644 index 000000000000..45589fec9fc7 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-timers.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-timers.h | ||
| 3 | * | ||
| 4 | * Timers Module | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_REGS_TIMERS_H | ||
| 12 | #define __ASM_MACH_REGS_TIMERS_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000) | ||
| 17 | #define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000) | ||
| 18 | |||
| 19 | #define TMR_CCR (0x0000) | ||
| 20 | #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2)) | ||
| 21 | #define TMR_CR(n) (0x0028 + ((n) << 2)) | ||
| 22 | #define TMR_SR(n) (0x0034 + ((n) << 2)) | ||
| 23 | #define TMR_IER(n) (0x0040 + ((n) << 2)) | ||
| 24 | #define TMR_PLVR(n) (0x004c + ((n) << 2)) | ||
| 25 | #define TMR_PLCR(n) (0x0058 + ((n) << 2)) | ||
| 26 | #define TMR_WMER (0x0064) | ||
| 27 | #define TMR_WMR (0x0068) | ||
| 28 | #define TMR_WVR (0x006c) | ||
| 29 | #define TMR_WSR (0x0070) | ||
| 30 | #define TMR_ICR(n) (0x0074 + ((n) << 2)) | ||
| 31 | #define TMR_WICR (0x0080) | ||
| 32 | #define TMR_CER (0x0084) | ||
| 33 | #define TMR_CMR (0x0088) | ||
| 34 | #define TMR_ILR(n) (0x008c + ((n) << 2)) | ||
| 35 | #define TMR_WCR (0x0098) | ||
| 36 | #define TMR_WFAR (0x009c) | ||
| 37 | #define TMR_WSAR (0x00A0) | ||
| 38 | #define TMR_CVWR(n) (0x00A4 + ((n) << 2)) | ||
| 39 | |||
| 40 | #define TMR_CCR_CS_0(x) (((x) & 0x3) << 0) | ||
| 41 | #define TMR_CCR_CS_1(x) (((x) & 0x7) << 2) | ||
| 42 | #define TMR_CCR_CS_2(x) (((x) & 0x3) << 5) | ||
| 43 | |||
| 44 | #endif /* __ASM_MACH_REGS_TIMERS_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h new file mode 100644 index 000000000000..001edfefec19 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/system.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/system.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_MACH_SYSTEM_H | ||
| 10 | #define __ASM_MACH_SYSTEM_H | ||
| 11 | |||
| 12 | static inline void arch_idle(void) | ||
| 13 | { | ||
| 14 | cpu_do_idle(); | ||
| 15 | } | ||
| 16 | |||
| 17 | static inline void arch_reset(char mode) | ||
| 18 | { | ||
| 19 | cpu_reset(0); | ||
| 20 | } | ||
| 21 | #endif /* __ASM_MACH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h new file mode 100644 index 000000000000..6cebbd0ca8f4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/timex.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE 3250000 | ||
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h new file mode 100644 index 000000000000..c93d5fa5865c --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/uncompress.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mmp/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/serial_reg.h> | ||
| 10 | #include <mach/addr-map.h> | ||
| 11 | |||
| 12 | #define UART1_BASE (APB_PHYS_BASE + 0x36000) | ||
| 13 | #define UART2_BASE (APB_PHYS_BASE + 0x17000) | ||
| 14 | #define UART3_BASE (APB_PHYS_BASE + 0x18000) | ||
| 15 | |||
| 16 | static inline void putc(char c) | ||
| 17 | { | ||
| 18 | volatile unsigned long *UART = (unsigned long *)UART2_BASE; | ||
| 19 | |||
| 20 | /* UART enabled? */ | ||
| 21 | if (!(UART[UART_IER] & UART_IER_UUE)) | ||
| 22 | return; | ||
| 23 | |||
| 24 | while (!(UART[UART_LSR] & UART_LSR_THRE)) | ||
| 25 | barrier(); | ||
| 26 | |||
| 27 | UART[UART_TX] = c; | ||
| 28 | } | ||
| 29 | |||
| 30 | /* | ||
| 31 | * This does not append a newline | ||
| 32 | */ | ||
| 33 | static inline void flush(void) | ||
| 34 | { | ||
| 35 | } | ||
| 36 | |||
| 37 | /* | ||
| 38 | * nothing to do | ||
| 39 | */ | ||
| 40 | #define arch_decomp_setup() | ||
| 41 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h new file mode 100644 index 000000000000..b60ccaf9fee7 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/vmalloc.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe000000 | ||
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c new file mode 100644 index 000000000000..52ff2f065eba --- /dev/null +++ b/arch/arm/mach-mmp/irq.c | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/irq.c | ||
| 3 | * | ||
| 4 | * Generic IRQ handling, GPIO IRQ demultiplexing, etc. | ||
| 5 | * | ||
| 6 | * Author: Bin Yang <bin.yang@marvell.com> | ||
| 7 | * Created: Sep 30, 2008 | ||
| 8 | * Copyright: Marvell International Ltd. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | |||
| 19 | #include <mach/regs-icu.h> | ||
| 20 | |||
| 21 | #include "common.h" | ||
| 22 | |||
| 23 | #define IRQ_ROUTE_TO_AP (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ) | ||
| 24 | |||
| 25 | #define PRIORITY_DEFAULT 0x1 | ||
| 26 | #define PRIORITY_NONE 0x0 /* means IRQ disabled */ | ||
| 27 | |||
| 28 | static void icu_mask_irq(unsigned int irq) | ||
| 29 | { | ||
| 30 | __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq)); | ||
| 31 | } | ||
| 32 | |||
| 33 | static void icu_unmask_irq(unsigned int irq) | ||
| 34 | { | ||
| 35 | __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq)); | ||
| 36 | } | ||
| 37 | |||
| 38 | static struct irq_chip icu_irq_chip = { | ||
| 39 | .name = "icu_irq", | ||
| 40 | .ack = icu_mask_irq, | ||
| 41 | .mask = icu_mask_irq, | ||
| 42 | .unmask = icu_unmask_irq, | ||
| 43 | }; | ||
| 44 | |||
| 45 | void __init icu_init_irq(void) | ||
| 46 | { | ||
| 47 | int irq; | ||
| 48 | |||
| 49 | for (irq = 0; irq < 64; irq++) { | ||
| 50 | icu_mask_irq(irq); | ||
| 51 | set_irq_chip(irq, &icu_irq_chip); | ||
| 52 | set_irq_handler(irq, handle_level_irq); | ||
| 53 | set_irq_flags(irq, IRQF_VALID); | ||
| 54 | } | ||
| 55 | } | ||
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c new file mode 100644 index 000000000000..ae924468658c --- /dev/null +++ b/arch/arm/mach-mmp/pxa168.c | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/pxa168.c | ||
| 3 | * | ||
| 4 | * Code specific to PXA168 | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/list.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/clk.h> | ||
| 17 | |||
| 18 | #include <asm/mach/time.h> | ||
| 19 | #include <mach/addr-map.h> | ||
| 20 | #include <mach/cputype.h> | ||
| 21 | #include <mach/regs-apbc.h> | ||
| 22 | #include <mach/irqs.h> | ||
| 23 | #include <mach/gpio.h> | ||
| 24 | #include <mach/dma.h> | ||
| 25 | #include <mach/devices.h> | ||
| 26 | #include <mach/mfp.h> | ||
| 27 | |||
| 28 | #include "common.h" | ||
| 29 | #include "clock.h" | ||
| 30 | |||
| 31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | ||
| 32 | |||
| 33 | static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = | ||
| 34 | { | ||
| 35 | MFP_ADDR_X(GPIO0, GPIO36, 0x04c), | ||
| 36 | MFP_ADDR_X(GPIO37, GPIO55, 0x000), | ||
| 37 | MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), | ||
| 38 | MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), | ||
| 39 | |||
| 40 | MFP_ADDR_END, | ||
| 41 | }; | ||
| 42 | |||
| 43 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) | ||
| 44 | |||
| 45 | static void __init pxa168_init_gpio(void) | ||
| 46 | { | ||
| 47 | int i; | ||
| 48 | |||
| 49 | /* enable GPIO clock */ | ||
| 50 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); | ||
| 51 | |||
| 52 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ | ||
| 53 | for (i = 0; i < 4; i++) | ||
| 54 | __raw_writel(0xffffffff, APMASK(i)); | ||
| 55 | |||
| 56 | pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); | ||
| 57 | } | ||
| 58 | |||
| 59 | void __init pxa168_init_irq(void) | ||
| 60 | { | ||
| 61 | icu_init_irq(); | ||
| 62 | pxa168_init_gpio(); | ||
| 63 | } | ||
| 64 | |||
| 65 | /* APB peripheral clocks */ | ||
| 66 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); | ||
| 67 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); | ||
| 68 | |||
| 69 | /* device and clock bindings */ | ||
| 70 | static struct clk_lookup pxa168_clkregs[] = { | ||
| 71 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
| 72 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
| 73 | }; | ||
| 74 | |||
| 75 | static int __init pxa168_init(void) | ||
| 76 | { | ||
| 77 | if (cpu_is_pxa168()) { | ||
| 78 | mfp_init_base(MFPR_VIRT_BASE); | ||
| 79 | mfp_init_addr(pxa168_mfp_addr_map); | ||
| 80 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); | ||
| 81 | clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); | ||
| 82 | } | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | postcore_initcall(pxa168_init); | ||
| 87 | |||
| 88 | /* system timer - clock enabled, 3.25MHz */ | ||
| 89 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | ||
| 90 | |||
| 91 | static void __init pxa168_timer_init(void) | ||
| 92 | { | ||
| 93 | /* this is early, we have to initialize the CCU registers by | ||
| 94 | * ourselves instead of using clk_* API. Clock rate is defined | ||
| 95 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running | ||
| 96 | */ | ||
| 97 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); | ||
| 98 | |||
| 99 | /* 3.25MHz, bus/functional clock enabled, release reset */ | ||
| 100 | __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); | ||
| 101 | |||
| 102 | timer_init(IRQ_PXA168_TIMER1); | ||
| 103 | } | ||
| 104 | |||
| 105 | struct sys_timer pxa168_timer = { | ||
| 106 | .init = pxa168_timer_init, | ||
| 107 | }; | ||
| 108 | |||
| 109 | /* on-chip devices */ | ||
| 110 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); | ||
| 111 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); | ||
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c new file mode 100644 index 000000000000..453f8f7758bf --- /dev/null +++ b/arch/arm/mach-mmp/pxa910.c | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/pxa910.c | ||
| 3 | * | ||
| 4 | * Code specific to PXA910 | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/list.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | |||
| 17 | #include <asm/mach/time.h> | ||
| 18 | #include <mach/addr-map.h> | ||
| 19 | #include <mach/regs-apbc.h> | ||
| 20 | #include <mach/regs-apmu.h> | ||
| 21 | #include <mach/cputype.h> | ||
| 22 | #include <mach/irqs.h> | ||
| 23 | #include <mach/gpio.h> | ||
| 24 | #include <mach/dma.h> | ||
| 25 | #include <mach/mfp.h> | ||
| 26 | #include <mach/devices.h> | ||
| 27 | |||
| 28 | #include "common.h" | ||
| 29 | #include "clock.h" | ||
| 30 | |||
| 31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | ||
| 32 | |||
| 33 | static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = | ||
| 34 | { | ||
| 35 | MFP_ADDR_X(GPIO0, GPIO54, 0xdc), | ||
| 36 | MFP_ADDR_X(GPIO67, GPIO98, 0x1b8), | ||
| 37 | MFP_ADDR_X(GPIO100, GPIO109, 0x238), | ||
| 38 | |||
| 39 | MFP_ADDR(GPIO123, 0xcc), | ||
| 40 | MFP_ADDR(GPIO124, 0xd0), | ||
| 41 | |||
| 42 | MFP_ADDR(DF_IO0, 0x40), | ||
| 43 | MFP_ADDR(DF_IO1, 0x3c), | ||
| 44 | MFP_ADDR(DF_IO2, 0x38), | ||
| 45 | MFP_ADDR(DF_IO3, 0x34), | ||
| 46 | MFP_ADDR(DF_IO4, 0x30), | ||
| 47 | MFP_ADDR(DF_IO5, 0x2c), | ||
| 48 | MFP_ADDR(DF_IO6, 0x28), | ||
| 49 | MFP_ADDR(DF_IO7, 0x24), | ||
| 50 | MFP_ADDR(DF_IO8, 0x20), | ||
| 51 | MFP_ADDR(DF_IO9, 0x1c), | ||
| 52 | MFP_ADDR(DF_IO10, 0x18), | ||
| 53 | MFP_ADDR(DF_IO11, 0x14), | ||
| 54 | MFP_ADDR(DF_IO12, 0x10), | ||
| 55 | MFP_ADDR(DF_IO13, 0xc), | ||
| 56 | MFP_ADDR(DF_IO14, 0x8), | ||
| 57 | MFP_ADDR(DF_IO15, 0x4), | ||
| 58 | |||
| 59 | MFP_ADDR(DF_nCS0_SM_nCS2, 0x44), | ||
| 60 | MFP_ADDR(DF_nCS1_SM_nCS3, 0x48), | ||
| 61 | MFP_ADDR(SM_nCS0, 0x4c), | ||
| 62 | MFP_ADDR(SM_nCS1, 0x50), | ||
| 63 | MFP_ADDR(DF_WEn, 0x54), | ||
| 64 | MFP_ADDR(DF_REn, 0x58), | ||
| 65 | MFP_ADDR(DF_CLE_SM_OEn, 0x5c), | ||
| 66 | MFP_ADDR(DF_ALE_SM_WEn, 0x60), | ||
| 67 | MFP_ADDR(SM_SCLK, 0x64), | ||
| 68 | MFP_ADDR(DF_RDY0, 0x68), | ||
| 69 | MFP_ADDR(SM_BE0, 0x6c), | ||
| 70 | MFP_ADDR(SM_BE1, 0x70), | ||
| 71 | MFP_ADDR(SM_ADV, 0x74), | ||
| 72 | MFP_ADDR(DF_RDY1, 0x78), | ||
| 73 | MFP_ADDR(SM_ADVMUX, 0x7c), | ||
| 74 | MFP_ADDR(SM_RDY, 0x80), | ||
| 75 | |||
| 76 | MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84), | ||
| 77 | |||
| 78 | MFP_ADDR_END, | ||
| 79 | }; | ||
| 80 | |||
| 81 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) | ||
| 82 | |||
| 83 | static void __init pxa910_init_gpio(void) | ||
| 84 | { | ||
| 85 | int i; | ||
| 86 | |||
| 87 | /* enable GPIO clock */ | ||
| 88 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO); | ||
| 89 | |||
| 90 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ | ||
| 91 | for (i = 0; i < 4; i++) | ||
| 92 | __raw_writel(0xffffffff, APMASK(i)); | ||
| 93 | |||
| 94 | pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL); | ||
| 95 | } | ||
| 96 | |||
| 97 | void __init pxa910_init_irq(void) | ||
| 98 | { | ||
| 99 | icu_init_irq(); | ||
| 100 | pxa910_init_gpio(); | ||
| 101 | } | ||
| 102 | |||
| 103 | /* APB peripheral clocks */ | ||
| 104 | static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); | ||
| 105 | static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); | ||
| 106 | |||
| 107 | /* device and clock bindings */ | ||
| 108 | static struct clk_lookup pxa910_clkregs[] = { | ||
| 109 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
| 110 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
| 111 | }; | ||
| 112 | |||
| 113 | static int __init pxa910_init(void) | ||
| 114 | { | ||
| 115 | if (cpu_is_pxa910()) { | ||
| 116 | mfp_init_base(MFPR_VIRT_BASE); | ||
| 117 | mfp_init_addr(pxa910_mfp_addr_map); | ||
| 118 | pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); | ||
| 119 | clks_register(ARRAY_AND_SIZE(pxa910_clkregs)); | ||
| 120 | } | ||
| 121 | |||
| 122 | return 0; | ||
| 123 | } | ||
| 124 | postcore_initcall(pxa910_init); | ||
| 125 | |||
| 126 | /* system timer - clock enabled, 3.25MHz */ | ||
| 127 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | ||
| 128 | |||
| 129 | static void __init pxa910_timer_init(void) | ||
| 130 | { | ||
| 131 | /* reset and configure */ | ||
| 132 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); | ||
| 133 | __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); | ||
| 134 | |||
| 135 | timer_init(IRQ_PXA910_AP1_TIMER1); | ||
| 136 | } | ||
| 137 | |||
| 138 | struct sys_timer pxa910_timer = { | ||
| 139 | .init = pxa910_timer_init, | ||
| 140 | }; | ||
| 141 | |||
| 142 | /* on-chip devices */ | ||
| 143 | |||
| 144 | /* NOTE: there are totally 3 UARTs on PXA910: | ||
| 145 | * | ||
| 146 | * UART1 - Slow UART (can be used both by AP and CP) | ||
| 147 | * UART2/3 - Fast UART | ||
| 148 | * | ||
| 149 | * To be backward compatible with the legacy FFUART/BTUART/STUART sequence, | ||
| 150 | * they are re-ordered as: | ||
| 151 | * | ||
| 152 | * pxa910_device_uart1 - UART2 as FFUART | ||
| 153 | * pxa910_device_uart2 - UART3 as BTUART | ||
| 154 | * | ||
| 155 | * UART1 is not used by AP for the moment. | ||
| 156 | */ | ||
| 157 | PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); | ||
| 158 | PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); | ||
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c new file mode 100644 index 000000000000..0e0c9220eaba --- /dev/null +++ b/arch/arm/mach-mmp/tavorevb.c | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/tavorevb.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell PXA910-based TavorEVB Development Platform. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * publishhed by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/smc91x.h> | ||
| 15 | |||
| 16 | #include <asm/mach-types.h> | ||
| 17 | #include <asm/mach/arch.h> | ||
| 18 | #include <mach/addr-map.h> | ||
| 19 | #include <mach/mfp-pxa910.h> | ||
| 20 | #include <mach/pxa910.h> | ||
| 21 | #include <mach/gpio.h> | ||
| 22 | |||
| 23 | #include "common.h" | ||
| 24 | |||
| 25 | static unsigned long tavorevb_pin_config[] __initdata = { | ||
| 26 | /* UART2 */ | ||
| 27 | GPIO47_UART2_RXD, | ||
| 28 | GPIO48_UART2_TXD, | ||
| 29 | |||
| 30 | /* SMC */ | ||
| 31 | SM_nCS0_nCS0, | ||
| 32 | SM_ADV_SM_ADV, | ||
| 33 | SM_SCLK_SM_SCLK, | ||
| 34 | SM_SCLK_SM_SCLK, | ||
| 35 | SM_BE0_SM_BE0, | ||
| 36 | SM_BE1_SM_BE1, | ||
| 37 | |||
| 38 | /* DFI */ | ||
| 39 | DF_IO0_ND_IO0, | ||
| 40 | DF_IO1_ND_IO1, | ||
| 41 | DF_IO2_ND_IO2, | ||
| 42 | DF_IO3_ND_IO3, | ||
| 43 | DF_IO4_ND_IO4, | ||
| 44 | DF_IO5_ND_IO5, | ||
| 45 | DF_IO6_ND_IO6, | ||
| 46 | DF_IO7_ND_IO7, | ||
| 47 | DF_IO8_ND_IO8, | ||
| 48 | DF_IO9_ND_IO9, | ||
| 49 | DF_IO10_ND_IO10, | ||
| 50 | DF_IO11_ND_IO11, | ||
| 51 | DF_IO12_ND_IO12, | ||
| 52 | DF_IO13_ND_IO13, | ||
| 53 | DF_IO14_ND_IO14, | ||
| 54 | DF_IO15_ND_IO15, | ||
| 55 | DF_nCS0_SM_nCS2_nCS0, | ||
| 56 | DF_ALE_SM_WEn_ND_ALE, | ||
| 57 | DF_CLE_SM_OEn_ND_CLE, | ||
| 58 | DF_WEn_DF_WEn, | ||
| 59 | DF_REn_DF_REn, | ||
| 60 | DF_RDY0_DF_RDY0, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static struct smc91x_platdata tavorevb_smc91x_info = { | ||
| 64 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct resource smc91x_resources[] = { | ||
| 68 | [0] = { | ||
| 69 | .start = SMC_CS1_PHYS_BASE + 0x300, | ||
| 70 | .end = SMC_CS1_PHYS_BASE + 0xfffff, | ||
| 71 | .flags = IORESOURCE_MEM, | ||
| 72 | }, | ||
| 73 | [1] = { | ||
| 74 | .start = gpio_to_irq(80), | ||
| 75 | .end = gpio_to_irq(80), | ||
| 76 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 77 | } | ||
| 78 | }; | ||
| 79 | |||
| 80 | static struct platform_device smc91x_device = { | ||
| 81 | .name = "smc91x", | ||
| 82 | .id = 0, | ||
| 83 | .dev = { | ||
| 84 | .platform_data = &tavorevb_smc91x_info, | ||
| 85 | }, | ||
| 86 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 87 | .resource = smc91x_resources, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static void __init tavorevb_init(void) | ||
| 91 | { | ||
| 92 | mfp_config(ARRAY_AND_SIZE(tavorevb_pin_config)); | ||
| 93 | |||
| 94 | /* on-chip devices */ | ||
| 95 | pxa910_add_uart(1); | ||
| 96 | |||
| 97 | /* off-chip devices */ | ||
| 98 | platform_device_register(&smc91x_device); | ||
| 99 | } | ||
| 100 | |||
| 101 | MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)") | ||
| 102 | .phys_io = APB_PHYS_BASE, | ||
| 103 | .boot_params = 0x00000100, | ||
| 104 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 105 | .map_io = pxa_map_io, | ||
| 106 | .init_irq = pxa910_init_irq, | ||
| 107 | .timer = &pxa910_timer, | ||
| 108 | .init_machine = tavorevb_init, | ||
| 109 | MACHINE_END | ||
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c new file mode 100644 index 000000000000..b03a6eda7419 --- /dev/null +++ b/arch/arm/mach-mmp/time.c | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/time.c | ||
| 3 | * | ||
| 4 | * Support for clocksource and clockevents | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Marvell International Ltd. | ||
| 7 | * All rights reserved. | ||
| 8 | * | ||
| 9 | * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> | ||
| 10 | * 2008-10-08: Bin Yang <bin.yang@marvell.com> | ||
| 11 | * | ||
| 12 | * The timers module actually includes three timers, each timer with upto | ||
| 13 | * three match comparators. Timer #0 is used here in free-running mode as | ||
| 14 | * the clock source, and match comparator #1 used as clock event device. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/interrupt.h> | ||
| 24 | #include <linux/clockchips.h> | ||
| 25 | |||
| 26 | #include <linux/io.h> | ||
| 27 | #include <linux/irq.h> | ||
| 28 | #include <linux/sched.h> | ||
| 29 | #include <linux/cnt32_to_63.h> | ||
| 30 | |||
| 31 | #include <mach/addr-map.h> | ||
| 32 | #include <mach/regs-timers.h> | ||
| 33 | #include <mach/irqs.h> | ||
| 34 | |||
| 35 | #include "clock.h" | ||
| 36 | |||
| 37 | #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE | ||
| 38 | |||
| 39 | #define MAX_DELTA (0xfffffffe) | ||
| 40 | #define MIN_DELTA (16) | ||
| 41 | |||
| 42 | #define TCR2NS_SCALE_FACTOR 10 | ||
| 43 | |||
| 44 | static unsigned long tcr2ns_scale; | ||
| 45 | |||
| 46 | static void __init set_tcr2ns_scale(unsigned long tcr_rate) | ||
| 47 | { | ||
| 48 | unsigned long long v = 1000000000ULL << TCR2NS_SCALE_FACTOR; | ||
| 49 | do_div(v, tcr_rate); | ||
| 50 | tcr2ns_scale = v; | ||
| 51 | /* | ||
| 52 | * We want an even value to automatically clear the top bit | ||
| 53 | * returned by cnt32_to_63() without an additional run time | ||
| 54 | * instruction. So if the LSB is 1 then round it up. | ||
| 55 | */ | ||
| 56 | if (tcr2ns_scale & 1) | ||
| 57 | tcr2ns_scale++; | ||
| 58 | } | ||
| 59 | |||
| 60 | /* | ||
| 61 | * FIXME: the timer needs some delay to stablize the counter capture | ||
| 62 | */ | ||
| 63 | static inline uint32_t timer_read(void) | ||
| 64 | { | ||
| 65 | int delay = 100; | ||
| 66 | |||
| 67 | __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(0)); | ||
| 68 | |||
| 69 | while (delay--) | ||
| 70 | cpu_relax(); | ||
| 71 | |||
| 72 | return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0)); | ||
| 73 | } | ||
| 74 | |||
| 75 | unsigned long long sched_clock(void) | ||
| 76 | { | ||
| 77 | unsigned long long v = cnt32_to_63(timer_read()); | ||
| 78 | return (v * tcr2ns_scale) >> TCR2NS_SCALE_FACTOR; | ||
| 79 | } | ||
| 80 | |||
| 81 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | ||
| 82 | { | ||
| 83 | struct clock_event_device *c = dev_id; | ||
| 84 | |||
| 85 | /* disable and clear pending interrupt status */ | ||
| 86 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 87 | __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_ICR(0)); | ||
| 88 | c->event_handler(c); | ||
| 89 | return IRQ_HANDLED; | ||
| 90 | } | ||
| 91 | |||
| 92 | static int timer_set_next_event(unsigned long delta, | ||
| 93 | struct clock_event_device *dev) | ||
| 94 | { | ||
| 95 | unsigned long flags, next; | ||
| 96 | |||
| 97 | local_irq_save(flags); | ||
| 98 | |||
| 99 | /* clear pending interrupt status and enable */ | ||
| 100 | __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0)); | ||
| 101 | __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 102 | |||
| 103 | next = timer_read() + delta; | ||
| 104 | __raw_writel(next, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0)); | ||
| 105 | |||
| 106 | local_irq_restore(flags); | ||
| 107 | return 0; | ||
| 108 | } | ||
| 109 | |||
| 110 | static void timer_set_mode(enum clock_event_mode mode, | ||
| 111 | struct clock_event_device *dev) | ||
| 112 | { | ||
| 113 | unsigned long flags; | ||
| 114 | |||
| 115 | local_irq_save(flags); | ||
| 116 | switch (mode) { | ||
| 117 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 118 | case CLOCK_EVT_MODE_UNUSED: | ||
| 119 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 120 | /* disable the matching interrupt */ | ||
| 121 | __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 122 | break; | ||
| 123 | case CLOCK_EVT_MODE_RESUME: | ||
| 124 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 125 | break; | ||
| 126 | } | ||
| 127 | local_irq_restore(flags); | ||
| 128 | } | ||
| 129 | |||
| 130 | static struct clock_event_device ckevt = { | ||
| 131 | .name = "clockevent", | ||
| 132 | .features = CLOCK_EVT_FEAT_ONESHOT, | ||
| 133 | .shift = 32, | ||
| 134 | .rating = 200, | ||
| 135 | .set_next_event = timer_set_next_event, | ||
| 136 | .set_mode = timer_set_mode, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static cycle_t clksrc_read(void) | ||
| 140 | { | ||
| 141 | return timer_read(); | ||
| 142 | } | ||
| 143 | |||
| 144 | static struct clocksource cksrc = { | ||
| 145 | .name = "clocksource", | ||
| 146 | .shift = 20, | ||
| 147 | .rating = 200, | ||
| 148 | .read = clksrc_read, | ||
| 149 | .mask = CLOCKSOURCE_MASK(32), | ||
| 150 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static void __init timer_config(void) | ||
| 154 | { | ||
| 155 | uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR); | ||
| 156 | uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER); | ||
| 157 | uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR); | ||
| 158 | |||
| 159 | __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ | ||
| 160 | |||
| 161 | ccr &= TMR_CCR_CS_0(0x3); | ||
| 162 | __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); | ||
| 163 | |||
| 164 | /* free-running mode */ | ||
| 165 | __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR); | ||
| 166 | |||
| 167 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */ | ||
| 168 | __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */ | ||
| 169 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 170 | |||
| 171 | /* enable timer counter */ | ||
| 172 | __raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER); | ||
| 173 | } | ||
| 174 | |||
| 175 | static struct irqaction timer_irq = { | ||
| 176 | .name = "timer", | ||
| 177 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 178 | .handler = timer_interrupt, | ||
| 179 | .dev_id = &ckevt, | ||
| 180 | }; | ||
| 181 | |||
| 182 | void __init timer_init(int irq) | ||
| 183 | { | ||
| 184 | timer_config(); | ||
| 185 | |||
| 186 | set_tcr2ns_scale(CLOCK_TICK_RATE); | ||
| 187 | |||
| 188 | ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); | ||
| 189 | ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); | ||
| 190 | ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); | ||
| 191 | ckevt.cpumask = cpumask_of(0); | ||
| 192 | |||
| 193 | cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift); | ||
| 194 | |||
| 195 | setup_irq(irq, &timer_irq); | ||
| 196 | |||
| 197 | clocksource_register(&cksrc); | ||
| 198 | clockevents_register_device(&ckevt); | ||
| 199 | } | ||
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c new file mode 100644 index 000000000000..08cfef6c92a2 --- /dev/null +++ b/arch/arm/mach-mmp/ttc_dkb.c | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/ttc_dkb.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell PXA910-based TTC_DKB Development Platform. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * publishhed by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | |||
| 15 | #include <asm/mach-types.h> | ||
| 16 | #include <asm/mach/arch.h> | ||
| 17 | #include <mach/addr-map.h> | ||
| 18 | #include <mach/mfp-pxa910.h> | ||
| 19 | #include <mach/pxa910.h> | ||
| 20 | |||
| 21 | #include "common.h" | ||
| 22 | |||
| 23 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
| 24 | |||
| 25 | static unsigned long ttc_dkb_pin_config[] __initdata = { | ||
| 26 | /* UART2 */ | ||
| 27 | GPIO47_UART2_RXD, | ||
| 28 | GPIO48_UART2_TXD, | ||
| 29 | }; | ||
| 30 | |||
| 31 | static void __init ttc_dkb_init(void) | ||
| 32 | { | ||
| 33 | mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); | ||
| 34 | |||
| 35 | /* on-chip devices */ | ||
| 36 | pxa910_add_uart(1); | ||
| 37 | } | ||
| 38 | |||
| 39 | MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") | ||
| 40 | .phys_io = APB_PHYS_BASE, | ||
| 41 | .boot_params = 0x00000100, | ||
| 42 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 43 | .map_io = pxa_map_io, | ||
| 44 | .init_irq = pxa910_init_irq, | ||
| 45 | .timer = &pxa910_timer, | ||
| 46 | .init_machine = ttc_dkb_init, | ||
| 47 | MACHINE_END | ||
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h index f05ad2e0f235..574ccc493daf 100644 --- a/arch/arm/mach-msm/include/mach/system.h +++ b/arch/arm/mach-msm/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | 17 | ||
| 18 | void arch_idle(void); | 18 | void arch_idle(void); |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | for (;;) ; /* depends on IPC w/ other core */ | 22 | for (;;) ; /* depends on IPC w/ other core */ |
| 23 | } | 23 | } |
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index d83cb86837db..6fbe68fe4412 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig | |||
| @@ -8,6 +8,12 @@ config MACH_DB78X00_BP | |||
| 8 | Say 'Y' here if you want your kernel to support the | 8 | Say 'Y' here if you want your kernel to support the |
| 9 | Marvell DB-78x00-BP Development Board. | 9 | Marvell DB-78x00-BP Development Board. |
| 10 | 10 | ||
| 11 | config MACH_RD78X00_MASA | ||
| 12 | bool "Marvell RD-78x00-mASA Reference Design" | ||
| 13 | help | ||
| 14 | Say 'Y' here if you want your kernel to support the | ||
| 15 | Marvell RD-78x00-mASA Reference Design. | ||
| 16 | |||
| 11 | endmenu | 17 | endmenu |
| 12 | 18 | ||
| 13 | endif | 19 | endif |
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index ec16c05c3b1b..da628b7f3bb6 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile | |||
| @@ -1,2 +1,3 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o pcie.o | 1 | obj-y += common.o addr-map.o irq.o pcie.o |
| 2 | obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o | 2 | obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o |
| 3 | obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o | ||
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index b0e4e0d8f506..a575daaa62d1 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
| @@ -14,7 +14,9 @@ | |||
| 14 | #include <linux/serial_8250.h> | 14 | #include <linux/serial_8250.h> |
| 15 | #include <linux/mbus.h> | 15 | #include <linux/mbus.h> |
| 16 | #include <linux/mv643xx_eth.h> | 16 | #include <linux/mv643xx_eth.h> |
| 17 | #include <linux/mv643xx_i2c.h> | ||
| 17 | #include <linux/ata_platform.h> | 18 | #include <linux/ata_platform.h> |
| 19 | #include <linux/ethtool.h> | ||
| 18 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
| 19 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 20 | #include <mach/mv78xx0.h> | 22 | #include <mach/mv78xx0.h> |
| @@ -430,9 +432,22 @@ static struct platform_device mv78xx0_ge10 = { | |||
| 430 | 432 | ||
| 431 | void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) | 433 | void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) |
| 432 | { | 434 | { |
| 435 | u32 dev, rev; | ||
| 436 | |||
| 433 | eth_data->shared = &mv78xx0_ge10_shared; | 437 | eth_data->shared = &mv78xx0_ge10_shared; |
| 434 | mv78xx0_ge10.dev.platform_data = eth_data; | 438 | mv78xx0_ge10.dev.platform_data = eth_data; |
| 435 | 439 | ||
| 440 | /* | ||
| 441 | * On the Z0, ge10 and ge11 are internally connected back | ||
| 442 | * to back, and not brought out. | ||
| 443 | */ | ||
| 444 | mv78xx0_pcie_id(&dev, &rev); | ||
| 445 | if (dev == MV78X00_Z0_DEV_ID) { | ||
| 446 | eth_data->phy_addr = MV643XX_ETH_PHY_NONE; | ||
| 447 | eth_data->speed = SPEED_1000; | ||
| 448 | eth_data->duplex = DUPLEX_FULL; | ||
| 449 | } | ||
| 450 | |||
| 436 | platform_device_register(&mv78xx0_ge10_shared); | 451 | platform_device_register(&mv78xx0_ge10_shared); |
| 437 | platform_device_register(&mv78xx0_ge10); | 452 | platform_device_register(&mv78xx0_ge10); |
| 438 | } | 453 | } |
| @@ -484,13 +499,101 @@ static struct platform_device mv78xx0_ge11 = { | |||
| 484 | 499 | ||
| 485 | void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) | 500 | void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) |
| 486 | { | 501 | { |
| 502 | u32 dev, rev; | ||
| 503 | |||
| 487 | eth_data->shared = &mv78xx0_ge11_shared; | 504 | eth_data->shared = &mv78xx0_ge11_shared; |
| 488 | mv78xx0_ge11.dev.platform_data = eth_data; | 505 | mv78xx0_ge11.dev.platform_data = eth_data; |
| 489 | 506 | ||
| 507 | /* | ||
| 508 | * On the Z0, ge10 and ge11 are internally connected back | ||
| 509 | * to back, and not brought out. | ||
| 510 | */ | ||
| 511 | mv78xx0_pcie_id(&dev, &rev); | ||
| 512 | if (dev == MV78X00_Z0_DEV_ID) { | ||
| 513 | eth_data->phy_addr = MV643XX_ETH_PHY_NONE; | ||
| 514 | eth_data->speed = SPEED_1000; | ||
| 515 | eth_data->duplex = DUPLEX_FULL; | ||
| 516 | } | ||
| 517 | |||
| 490 | platform_device_register(&mv78xx0_ge11_shared); | 518 | platform_device_register(&mv78xx0_ge11_shared); |
| 491 | platform_device_register(&mv78xx0_ge11); | 519 | platform_device_register(&mv78xx0_ge11); |
| 492 | } | 520 | } |
| 493 | 521 | ||
| 522 | /***************************************************************************** | ||
| 523 | * I2C bus 0 | ||
| 524 | ****************************************************************************/ | ||
| 525 | |||
| 526 | static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = { | ||
| 527 | .freq_m = 8, /* assumes 166 MHz TCLK */ | ||
| 528 | .freq_n = 3, | ||
| 529 | .timeout = 1000, /* Default timeout of 1 second */ | ||
| 530 | }; | ||
| 531 | |||
| 532 | static struct resource mv78xx0_i2c_0_resources[] = { | ||
| 533 | { | ||
| 534 | .name = "i2c 0 base", | ||
| 535 | .start = I2C_0_PHYS_BASE, | ||
| 536 | .end = I2C_0_PHYS_BASE + 0x1f, | ||
| 537 | .flags = IORESOURCE_MEM, | ||
| 538 | }, { | ||
| 539 | .name = "i2c 0 irq", | ||
| 540 | .start = IRQ_MV78XX0_I2C_0, | ||
| 541 | .end = IRQ_MV78XX0_I2C_0, | ||
| 542 | .flags = IORESOURCE_IRQ, | ||
| 543 | }, | ||
| 544 | }; | ||
| 545 | |||
| 546 | |||
| 547 | static struct platform_device mv78xx0_i2c_0 = { | ||
| 548 | .name = MV64XXX_I2C_CTLR_NAME, | ||
| 549 | .id = 0, | ||
| 550 | .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources), | ||
| 551 | .resource = mv78xx0_i2c_0_resources, | ||
| 552 | .dev = { | ||
| 553 | .platform_data = &mv78xx0_i2c_0_pdata, | ||
| 554 | }, | ||
| 555 | }; | ||
| 556 | |||
| 557 | /***************************************************************************** | ||
| 558 | * I2C bus 1 | ||
| 559 | ****************************************************************************/ | ||
| 560 | |||
| 561 | static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = { | ||
| 562 | .freq_m = 8, /* assumes 166 MHz TCLK */ | ||
| 563 | .freq_n = 3, | ||
| 564 | .timeout = 1000, /* Default timeout of 1 second */ | ||
| 565 | }; | ||
| 566 | |||
| 567 | static struct resource mv78xx0_i2c_1_resources[] = { | ||
| 568 | { | ||
| 569 | .name = "i2c 1 base", | ||
| 570 | .start = I2C_1_PHYS_BASE, | ||
| 571 | .end = I2C_1_PHYS_BASE + 0x1f, | ||
| 572 | .flags = IORESOURCE_MEM, | ||
| 573 | }, { | ||
| 574 | .name = "i2c 1 irq", | ||
| 575 | .start = IRQ_MV78XX0_I2C_1, | ||
| 576 | .end = IRQ_MV78XX0_I2C_1, | ||
| 577 | .flags = IORESOURCE_IRQ, | ||
| 578 | }, | ||
| 579 | }; | ||
| 580 | |||
| 581 | |||
| 582 | static struct platform_device mv78xx0_i2c_1 = { | ||
| 583 | .name = MV64XXX_I2C_CTLR_NAME, | ||
| 584 | .id = 1, | ||
| 585 | .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources), | ||
| 586 | .resource = mv78xx0_i2c_1_resources, | ||
| 587 | .dev = { | ||
| 588 | .platform_data = &mv78xx0_i2c_1_pdata, | ||
| 589 | }, | ||
| 590 | }; | ||
| 591 | |||
| 592 | void __init mv78xx0_i2c_init(void) | ||
| 593 | { | ||
| 594 | platform_device_register(&mv78xx0_i2c_0); | ||
| 595 | platform_device_register(&mv78xx0_i2c_1); | ||
| 596 | } | ||
| 494 | 597 | ||
| 495 | /***************************************************************************** | 598 | /***************************************************************************** |
| 496 | * SATA | 599 | * SATA |
| @@ -719,6 +822,32 @@ struct sys_timer mv78xx0_timer = { | |||
| 719 | /***************************************************************************** | 822 | /***************************************************************************** |
| 720 | * General | 823 | * General |
| 721 | ****************************************************************************/ | 824 | ****************************************************************************/ |
| 825 | static char * __init mv78xx0_id(void) | ||
| 826 | { | ||
| 827 | u32 dev, rev; | ||
| 828 | |||
| 829 | mv78xx0_pcie_id(&dev, &rev); | ||
| 830 | |||
| 831 | if (dev == MV78X00_Z0_DEV_ID) { | ||
| 832 | if (rev == MV78X00_REV_Z0) | ||
| 833 | return "MV78X00-Z0"; | ||
| 834 | else | ||
| 835 | return "MV78X00-Rev-Unsupported"; | ||
| 836 | } else if (dev == MV78100_DEV_ID) { | ||
| 837 | if (rev == MV78100_REV_A0) | ||
| 838 | return "MV78100-A0"; | ||
| 839 | else | ||
| 840 | return "MV78100-Rev-Unsupported"; | ||
| 841 | } else if (dev == MV78200_DEV_ID) { | ||
| 842 | if (rev == MV78100_REV_A0) | ||
| 843 | return "MV78200-A0"; | ||
| 844 | else | ||
| 845 | return "MV78200-Rev-Unsupported"; | ||
| 846 | } else { | ||
| 847 | return "Device-Unknown"; | ||
| 848 | } | ||
| 849 | } | ||
| 850 | |||
| 722 | static int __init is_l2_writethrough(void) | 851 | static int __init is_l2_writethrough(void) |
| 723 | { | 852 | { |
| 724 | return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); | 853 | return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); |
| @@ -737,7 +866,8 @@ void __init mv78xx0_init(void) | |||
| 737 | get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); | 866 | get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); |
| 738 | tclk = get_tclk(); | 867 | tclk = get_tclk(); |
| 739 | 868 | ||
| 740 | printk(KERN_INFO "MV78xx0 core #%d, ", core_index); | 869 | printk(KERN_INFO "%s ", mv78xx0_id()); |
| 870 | printk("core #%d, ", core_index); | ||
| 741 | printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); | 871 | printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); |
| 742 | printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); | 872 | printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); |
| 743 | printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); | 873 | printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); |
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index 78af5de319dd..befc22475469 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h | |||
| @@ -29,6 +29,8 @@ void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, | |||
| 29 | void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, | 29 | void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, |
| 30 | int maj, int min); | 30 | int maj, int min); |
| 31 | 31 | ||
| 32 | void mv78xx0_pcie_id(u32 *dev, u32 *rev); | ||
| 33 | |||
| 32 | void mv78xx0_ehci0_init(void); | 34 | void mv78xx0_ehci0_init(void); |
| 33 | void mv78xx0_ehci1_init(void); | 35 | void mv78xx0_ehci1_init(void); |
| 34 | void mv78xx0_ehci2_init(void); | 36 | void mv78xx0_ehci2_init(void); |
| @@ -42,6 +44,7 @@ void mv78xx0_uart0_init(void); | |||
| 42 | void mv78xx0_uart1_init(void); | 44 | void mv78xx0_uart1_init(void); |
| 43 | void mv78xx0_uart2_init(void); | 45 | void mv78xx0_uart2_init(void); |
| 44 | void mv78xx0_uart3_init(void); | 46 | void mv78xx0_uart3_init(void); |
| 47 | void mv78xx0_i2c_init(void); | ||
| 45 | 48 | ||
| 46 | extern struct sys_timer mv78xx0_timer; | 49 | extern struct sys_timer mv78xx0_timer; |
| 47 | 50 | ||
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c index 2e285bbb7bbd..efdabe04c69e 100644 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/ata_platform.h> | 14 | #include <linux/ata_platform.h> |
| 15 | #include <linux/mv643xx_eth.h> | 15 | #include <linux/mv643xx_eth.h> |
| 16 | #include <linux/ethtool.h> | 16 | #include <linux/ethtool.h> |
| 17 | #include <linux/i2c.h> | ||
| 17 | #include <mach/mv78xx0.h> | 18 | #include <mach/mv78xx0.h> |
| 18 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
| 19 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| @@ -28,21 +29,22 @@ static struct mv643xx_eth_platform_data db78x00_ge01_data = { | |||
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | static struct mv643xx_eth_platform_data db78x00_ge10_data = { | 31 | static struct mv643xx_eth_platform_data db78x00_ge10_data = { |
| 31 | .phy_addr = MV643XX_ETH_PHY_NONE, | 32 | .phy_addr = MV643XX_ETH_PHY_ADDR(10), |
| 32 | .speed = SPEED_1000, | ||
| 33 | .duplex = DUPLEX_FULL, | ||
| 34 | }; | 33 | }; |
| 35 | 34 | ||
| 36 | static struct mv643xx_eth_platform_data db78x00_ge11_data = { | 35 | static struct mv643xx_eth_platform_data db78x00_ge11_data = { |
| 37 | .phy_addr = MV643XX_ETH_PHY_NONE, | 36 | .phy_addr = MV643XX_ETH_PHY_ADDR(11), |
| 38 | .speed = SPEED_1000, | ||
| 39 | .duplex = DUPLEX_FULL, | ||
| 40 | }; | 37 | }; |
| 41 | 38 | ||
| 42 | static struct mv_sata_platform_data db78x00_sata_data = { | 39 | static struct mv_sata_platform_data db78x00_sata_data = { |
| 43 | .n_ports = 2, | 40 | .n_ports = 2, |
| 44 | }; | 41 | }; |
| 45 | 42 | ||
| 43 | static struct i2c_board_info __initdata db78x00_i2c_rtc = { | ||
| 44 | I2C_BOARD_INFO("ds1338", 0x68), | ||
| 45 | }; | ||
| 46 | |||
| 47 | |||
| 46 | static void __init db78x00_init(void) | 48 | static void __init db78x00_init(void) |
| 47 | { | 49 | { |
| 48 | /* | 50 | /* |
| @@ -64,6 +66,8 @@ static void __init db78x00_init(void) | |||
| 64 | mv78xx0_sata_init(&db78x00_sata_data); | 66 | mv78xx0_sata_init(&db78x00_sata_data); |
| 65 | mv78xx0_uart0_init(); | 67 | mv78xx0_uart0_init(); |
| 66 | mv78xx0_uart2_init(); | 68 | mv78xx0_uart2_init(); |
| 69 | mv78xx0_i2c_init(); | ||
| 70 | i2c_register_board_info(0, &db78x00_i2c_rtc, 1); | ||
| 67 | } else { | 71 | } else { |
| 68 | mv78xx0_uart1_init(); | 72 | mv78xx0_uart1_init(); |
| 69 | mv78xx0_uart3_init(); | 73 | mv78xx0_uart3_init(); |
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e930ea5330a2..582cffc733ad 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
| @@ -80,6 +80,18 @@ | |||
| 80 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | 80 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) |
| 81 | 81 | ||
| 82 | /* | 82 | /* |
| 83 | * Supported devices and revisions. | ||
| 84 | */ | ||
| 85 | #define MV78X00_Z0_DEV_ID 0x6381 | ||
| 86 | #define MV78X00_REV_Z0 1 | ||
| 87 | |||
| 88 | #define MV78100_DEV_ID 0x7810 | ||
| 89 | #define MV78100_REV_A0 1 | ||
| 90 | |||
| 91 | #define MV78200_DEV_ID 0x7820 | ||
| 92 | #define MV78200_REV_A0 1 | ||
| 93 | |||
| 94 | /* | ||
| 83 | * Register Map | 95 | * Register Map |
| 84 | */ | 96 | */ |
| 85 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) | 97 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) |
| @@ -90,6 +102,8 @@ | |||
| 90 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) | 102 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) |
| 91 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) | 103 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) |
| 92 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) | 104 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) |
| 105 | #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) | ||
| 106 | #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) | ||
| 93 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | 107 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 94 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | 108 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) |
| 95 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 109 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h index 7d5179408832..1d6350b22d0b 100644 --- a/arch/arm/mach-mv78xx0/include/mach/system.h +++ b/arch/arm/mach-mv78xx0/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | /* | 22 | /* |
| 23 | * Enable soft reset to assert RSTOUTn. | 23 | * Enable soft reset to assert RSTOUTn. |
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index aad3a7a2f830..a560439dcc3c 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c | |||
| @@ -33,6 +33,12 @@ static struct resource pcie_io_space; | |||
| 33 | static struct resource pcie_mem_space; | 33 | static struct resource pcie_mem_space; |
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) | ||
| 37 | { | ||
| 38 | *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); | ||
| 39 | *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); | ||
| 40 | } | ||
| 41 | |||
| 36 | static void __init mv78xx0_pcie_preinit(void) | 42 | static void __init mv78xx0_pcie_preinit(void) |
| 37 | { | 43 | { |
| 38 | int i; | 44 | int i; |
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c new file mode 100644 index 000000000000..e136b7a03355 --- /dev/null +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | |||
| @@ -0,0 +1,88 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mv78x00/rd78x00-masa-setup.c | ||
| 3 | * | ||
| 4 | * Marvell RD-78x00-mASA Development Board Setup | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/ata_platform.h> | ||
| 15 | #include <linux/mv643xx_eth.h> | ||
| 16 | #include <linux/ethtool.h> | ||
| 17 | #include <mach/mv78xx0.h> | ||
| 18 | #include <asm/mach-types.h> | ||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include "common.h" | ||
| 21 | |||
| 22 | static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { | ||
| 23 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | ||
| 24 | }; | ||
| 25 | |||
| 26 | static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = { | ||
| 27 | .phy_addr = MV643XX_ETH_PHY_ADDR(9), | ||
| 28 | }; | ||
| 29 | |||
| 30 | static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = { | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = { | ||
| 34 | }; | ||
| 35 | |||
| 36 | static struct mv_sata_platform_data rd78x00_masa_sata_data = { | ||
| 37 | .n_ports = 2, | ||
| 38 | }; | ||
| 39 | |||
| 40 | static void __init rd78x00_masa_init(void) | ||
| 41 | { | ||
| 42 | /* | ||
| 43 | * Basic MV78x00 setup. Needs to be called early. | ||
| 44 | */ | ||
| 45 | mv78xx0_init(); | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Partition on-chip peripherals between the two CPU cores. | ||
| 49 | */ | ||
| 50 | if (mv78xx0_core_index() == 0) { | ||
| 51 | mv78xx0_ehci0_init(); | ||
| 52 | mv78xx0_ehci1_init(); | ||
| 53 | mv78xx0_ge00_init(&rd78x00_masa_ge00_data); | ||
| 54 | mv78xx0_ge10_init(&rd78x00_masa_ge10_data); | ||
| 55 | mv78xx0_sata_init(&rd78x00_masa_sata_data); | ||
| 56 | mv78xx0_uart0_init(); | ||
| 57 | mv78xx0_uart2_init(); | ||
| 58 | } else { | ||
| 59 | mv78xx0_ehci2_init(); | ||
| 60 | mv78xx0_ge01_init(&rd78x00_masa_ge01_data); | ||
| 61 | mv78xx0_ge11_init(&rd78x00_masa_ge11_data); | ||
| 62 | mv78xx0_uart1_init(); | ||
| 63 | mv78xx0_uart3_init(); | ||
| 64 | } | ||
| 65 | } | ||
| 66 | |||
| 67 | static int __init rd78x00_pci_init(void) | ||
| 68 | { | ||
| 69 | /* | ||
| 70 | * Assign all PCIe devices to CPU core #0. | ||
| 71 | */ | ||
| 72 | if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0) | ||
| 73 | mv78xx0_pcie_init(1, 1); | ||
| 74 | |||
| 75 | return 0; | ||
| 76 | } | ||
| 77 | subsys_initcall(rd78x00_pci_init); | ||
| 78 | |||
| 79 | MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") | ||
| 80 | /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ | ||
| 81 | .phys_io = MV78XX0_REGS_PHYS_BASE, | ||
| 82 | .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 83 | .boot_params = 0x00000100, | ||
| 84 | .init_machine = rd78x00_masa_init, | ||
| 85 | .map_io = mv78xx0_map_io, | ||
| 86 | .init_irq = mv78xx0_init_irq, | ||
| 87 | .timer = &mv78xx0_timer, | ||
| 88 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig index 2b59fc74784f..eb7660f5d4b7 100644 --- a/arch/arm/mach-mx1/Kconfig +++ b/arch/arm/mach-mx1/Kconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | if ARCH_MX1 | 1 | if ARCH_MX1 |
| 2 | 2 | ||
| 3 | comment "MX1 Platforms" | 3 | comment "MX1 platforms:" |
| 4 | 4 | ||
| 5 | config MACH_MXLADS | 5 | config MACH_MXLADS |
| 6 | bool | 6 | bool |
| @@ -11,4 +11,9 @@ config ARCH_MX1ADS | |||
| 11 | help | 11 | help |
| 12 | Say Y here if you are using Motorola MX1ADS/MXLADS boards | 12 | Say Y here if you are using Motorola MX1ADS/MXLADS boards |
| 13 | 13 | ||
| 14 | config MACH_SCB9328 | ||
| 15 | bool "Synertronixx scb9328" | ||
| 16 | help | ||
| 17 | Say Y here if you are using a Synertronixx scb9328 board | ||
| 18 | |||
| 14 | endif | 19 | endif |
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile index b969719011fa..82f1309568ef 100644 --- a/arch/arm/mach-mx1/Makefile +++ b/arch/arm/mach-mx1/Makefile | |||
| @@ -8,3 +8,4 @@ obj-y += generic.o clock.o devices.o | |||
| 8 | 8 | ||
| 9 | # Specific board support | 9 | # Specific board support |
| 10 | obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o | 10 | obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o |
| 11 | obj-$(CONFIG_MACH_SCB9328) += scb9328.o \ No newline at end of file | ||
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c index 4bcd1ece55f5..0d0f306851d0 100644 --- a/arch/arm/mach-mx1/clock.c +++ b/arch/arm/mach-mx1/clock.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include <mach/clock.h> | 26 | #include <mach/clock.h> |
| 27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/common.h> | ||
| 28 | #include "crm_regs.h" | 29 | #include "crm_regs.h" |
| 29 | 30 | ||
| 30 | static int _clk_enable(struct clk *clk) | 31 | static int _clk_enable(struct clk *clk) |
| @@ -87,33 +88,6 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | |||
| 87 | return clk->parent->set_rate(clk->parent, rate); | 88 | return clk->parent->set_rate(clk->parent, rate); |
| 88 | } | 89 | } |
| 89 | 90 | ||
| 90 | /* | ||
| 91 | * get the system pll clock in Hz | ||
| 92 | * | ||
| 93 | * mfi + mfn / (mfd +1) | ||
| 94 | * f = 2 * f_ref * -------------------- | ||
| 95 | * pd + 1 | ||
| 96 | */ | ||
| 97 | static unsigned long mx1_decode_pll(unsigned int pll, u32 f_ref) | ||
| 98 | { | ||
| 99 | unsigned long long ll; | ||
| 100 | unsigned long quot; | ||
| 101 | |||
| 102 | u32 mfi = (pll >> 10) & 0xf; | ||
| 103 | u32 mfn = pll & 0x3ff; | ||
| 104 | u32 mfd = (pll >> 16) & 0x3ff; | ||
| 105 | u32 pd = (pll >> 26) & 0xf; | ||
| 106 | |||
| 107 | mfi = mfi <= 5 ? 5 : mfi; | ||
| 108 | |||
| 109 | ll = 2 * (unsigned long long)f_ref * | ||
| 110 | ((mfi << 16) + (mfn << 16) / (mfd + 1)); | ||
| 111 | quot = (pd + 1) * (1 << 16); | ||
| 112 | ll += quot / 2; | ||
| 113 | do_div(ll, quot); | ||
| 114 | return (unsigned long)ll; | ||
| 115 | } | ||
| 116 | |||
| 117 | static unsigned long clk16m_get_rate(struct clk *clk) | 91 | static unsigned long clk16m_get_rate(struct clk *clk) |
| 118 | { | 92 | { |
| 119 | return 16000000; | 93 | return 16000000; |
| @@ -188,7 +162,7 @@ static struct clk prem_clk = { | |||
| 188 | 162 | ||
| 189 | static unsigned long system_clk_get_rate(struct clk *clk) | 163 | static unsigned long system_clk_get_rate(struct clk *clk) |
| 190 | { | 164 | { |
| 191 | return mx1_decode_pll(__raw_readl(CCM_SPCTL0), | 165 | return mxc_decode_pll(__raw_readl(CCM_SPCTL0), |
| 192 | clk_get_rate(clk->parent)); | 166 | clk_get_rate(clk->parent)); |
| 193 | } | 167 | } |
| 194 | 168 | ||
| @@ -200,7 +174,7 @@ static struct clk system_clk = { | |||
| 200 | 174 | ||
| 201 | static unsigned long mcu_clk_get_rate(struct clk *clk) | 175 | static unsigned long mcu_clk_get_rate(struct clk *clk) |
| 202 | { | 176 | { |
| 203 | return mx1_decode_pll(__raw_readl(CCM_MPCTL0), | 177 | return mxc_decode_pll(__raw_readl(CCM_MPCTL0), |
| 204 | clk_get_rate(clk->parent)); | 178 | clk_get_rate(clk->parent)); |
| 205 | } | 179 | } |
| 206 | 180 | ||
| @@ -488,7 +462,7 @@ static struct clk clko_clk = { | |||
| 488 | }; | 462 | }; |
| 489 | 463 | ||
| 490 | static struct clk dma_clk = { | 464 | static struct clk dma_clk = { |
| 491 | .name = "dma_clk", | 465 | .name = "dma", |
| 492 | .parent = &hclk, | 466 | .parent = &hclk, |
| 493 | .round_rate = _clk_parent_round_rate, | 467 | .round_rate = _clk_parent_round_rate, |
| 494 | .set_rate = _clk_parent_set_rate, | 468 | .set_rate = _clk_parent_set_rate, |
| @@ -539,7 +513,7 @@ static struct clk gpt_clk = { | |||
| 539 | }; | 513 | }; |
| 540 | 514 | ||
| 541 | static struct clk uart_clk = { | 515 | static struct clk uart_clk = { |
| 542 | .name = "uart_clk", | 516 | .name = "uart", |
| 543 | .parent = &perclk[0], | 517 | .parent = &perclk[0], |
| 544 | .round_rate = _clk_parent_round_rate, | 518 | .round_rate = _clk_parent_round_rate, |
| 545 | .set_rate = _clk_parent_set_rate, | 519 | .set_rate = _clk_parent_set_rate, |
| @@ -621,7 +595,7 @@ static struct clk *mxc_clks[] = { | |||
| 621 | &rtc_clk, | 595 | &rtc_clk, |
| 622 | }; | 596 | }; |
| 623 | 597 | ||
| 624 | int __init mxc_clocks_init(unsigned long fref) | 598 | int __init mx1_clocks_init(unsigned long fref) |
| 625 | { | 599 | { |
| 626 | struct clk **clkp; | 600 | struct clk **clkp; |
| 627 | unsigned int reg; | 601 | unsigned int reg; |
| @@ -652,5 +626,7 @@ int __init mxc_clocks_init(unsigned long fref) | |||
| 652 | clk_enable(&hclk); | 626 | clk_enable(&hclk); |
| 653 | clk_enable(&fclk); | 627 | clk_enable(&fclk); |
| 654 | 628 | ||
| 629 | mxc_timer_init(&gpt_clk); | ||
| 630 | |||
| 655 | return 0; | 631 | return 0; |
| 656 | } | 632 | } |
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c index a95644193f3f..97f42d96d7a1 100644 --- a/arch/arm/mach-mx1/devices.c +++ b/arch/arm/mach-mx1/devices.c | |||
| @@ -23,10 +23,11 @@ | |||
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
| 26 | |||
| 27 | #include <mach/irqs.h> | 26 | #include <mach/irqs.h> |
| 28 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 29 | 28 | ||
| 29 | #include "devices.h" | ||
| 30 | |||
| 30 | static struct resource imx_csi_resources[] = { | 31 | static struct resource imx_csi_resources[] = { |
| 31 | [0] = { | 32 | [0] = { |
| 32 | .start = 0x00224000, | 33 | .start = 0x00224000, |
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c index 3200cf60e384..7ae229bc1b79 100644 --- a/arch/arm/mach-mx1/mx1ads.c +++ b/arch/arm/mach-mx1/mx1ads.c | |||
| @@ -16,6 +16,8 @@ | |||
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/mtd/physmap.h> | 18 | #include <linux/mtd/physmap.h> |
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/i2c/pcf857x.h> | ||
| 19 | 21 | ||
| 20 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 21 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| @@ -25,7 +27,11 @@ | |||
| 25 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 26 | #include <mach/common.h> | 28 | #include <mach/common.h> |
| 27 | #include <mach/imx-uart.h> | 29 | #include <mach/imx-uart.h> |
| 28 | #include <mach/iomux-mx1-mx2.h> | 30 | #include <mach/irqs.h> |
| 31 | #ifdef CONFIG_I2C_IMX | ||
| 32 | #include <mach/i2c.h> | ||
| 33 | #endif | ||
| 34 | #include <mach/iomux.h> | ||
| 29 | #include "devices.h" | 35 | #include "devices.h" |
| 30 | 36 | ||
| 31 | /* | 37 | /* |
| @@ -105,6 +111,55 @@ static struct platform_device flash_device = { | |||
| 105 | }; | 111 | }; |
| 106 | 112 | ||
| 107 | /* | 113 | /* |
| 114 | * I2C | ||
| 115 | */ | ||
| 116 | |||
| 117 | #ifdef CONFIG_I2C_IMX | ||
| 118 | static int i2c_pins[] = { | ||
| 119 | PA15_PF_I2C_SDA, | ||
| 120 | PA16_PF_I2C_SCL, | ||
| 121 | }; | ||
| 122 | |||
| 123 | static int i2c_init(struct device *dev) | ||
| 124 | { | ||
| 125 | return mxc_gpio_setup_multiple_pins(i2c_pins, | ||
| 126 | ARRAY_SIZE(i2c_pins), "I2C"); | ||
| 127 | } | ||
| 128 | |||
| 129 | static void i2c_exit(struct device *dev) | ||
| 130 | { | ||
| 131 | mxc_gpio_release_multiple_pins(i2c_pins, | ||
| 132 | ARRAY_SIZE(i2c_pins)); | ||
| 133 | } | ||
| 134 | |||
| 135 | static struct pcf857x_platform_data pcf857x_data[] = { | ||
| 136 | { | ||
| 137 | .gpio_base = 4 * 32, | ||
| 138 | }, { | ||
| 139 | .gpio_base = 4 * 32 + 16, | ||
| 140 | } | ||
| 141 | }; | ||
| 142 | |||
| 143 | static struct imxi2c_platform_data mx1ads_i2c_data = { | ||
| 144 | .bitrate = 100000, | ||
| 145 | .init = i2c_init, | ||
| 146 | .exit = i2c_exit, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct i2c_board_info mx1ads_i2c_devices[] = { | ||
| 150 | { | ||
| 151 | I2C_BOARD_INFO("pcf857x", 0x22), | ||
| 152 | .type = "pcf8575", | ||
| 153 | .platform_data = &pcf857x_data[0], | ||
| 154 | }, { | ||
| 155 | I2C_BOARD_INFO("pcf857x", 0x24), | ||
| 156 | .type = "pcf8575", | ||
| 157 | .platform_data = &pcf857x_data[1], | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | #endif | ||
| 161 | |||
| 162 | /* | ||
| 108 | * Board init | 163 | * Board init |
| 109 | */ | 164 | */ |
| 110 | static void __init mx1ads_init(void) | 165 | static void __init mx1ads_init(void) |
| @@ -115,12 +170,19 @@ static void __init mx1ads_init(void) | |||
| 115 | 170 | ||
| 116 | /* Physmap flash */ | 171 | /* Physmap flash */ |
| 117 | mxc_register_device(&flash_device, &mx1ads_flash_data); | 172 | mxc_register_device(&flash_device, &mx1ads_flash_data); |
| 173 | |||
| 174 | /* I2C */ | ||
| 175 | #ifdef CONFIG_I2C_IMX | ||
| 176 | i2c_register_board_info(0, mx1ads_i2c_devices, | ||
| 177 | ARRAY_SIZE(mx1ads_i2c_devices)); | ||
| 178 | |||
| 179 | mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data); | ||
| 180 | #endif | ||
| 118 | } | 181 | } |
| 119 | 182 | ||
| 120 | static void __init mx1ads_timer_init(void) | 183 | static void __init mx1ads_timer_init(void) |
| 121 | { | 184 | { |
| 122 | mxc_clocks_init(32000); | 185 | mx1_clocks_init(32000); |
| 123 | mxc_timer_init("gpt_clk"); | ||
| 124 | } | 186 | } |
| 125 | 187 | ||
| 126 | struct sys_timer mx1ads_timer = { | 188 | struct sys_timer mx1ads_timer = { |
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c new file mode 100644 index 000000000000..0e71f3fa28bf --- /dev/null +++ b/arch/arm/mach-mx1/scb9328.c | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mx1/scb9328.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> | ||
| 5 | * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/mtd/physmap.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/dm9000.h> | ||
| 17 | |||
| 18 | #include <asm/mach-types.h> | ||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include <asm/mach/time.h> | ||
| 21 | |||
| 22 | #include <mach/common.h> | ||
| 23 | #include <mach/hardware.h> | ||
| 24 | #include <mach/irqs.h> | ||
| 25 | #include <mach/imx-uart.h> | ||
| 26 | #include <mach/iomux.h> | ||
| 27 | |||
| 28 | #include "devices.h" | ||
| 29 | |||
| 30 | /* | ||
| 31 | * This scb9328 has a 32MiB flash | ||
| 32 | */ | ||
| 33 | static struct resource flash_resource = { | ||
| 34 | .start = IMX_CS0_PHYS, | ||
| 35 | .end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1, | ||
| 36 | .flags = IORESOURCE_MEM, | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct physmap_flash_data scb_flash_data = { | ||
| 40 | .width = 2, | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct platform_device scb_flash_device = { | ||
| 44 | .name = "physmap-flash", | ||
| 45 | .id = 0, | ||
| 46 | .dev = { | ||
| 47 | .platform_data = &scb_flash_data, | ||
| 48 | }, | ||
| 49 | .resource = &flash_resource, | ||
| 50 | .num_resources = 1, | ||
| 51 | }; | ||
| 52 | |||
| 53 | /* | ||
| 54 | * scb9328 has a DM9000 network controller | ||
| 55 | * connected to CS5, with 16 bit data path | ||
| 56 | * and interrupt connected to GPIO 3 | ||
| 57 | */ | ||
| 58 | |||
| 59 | /* | ||
| 60 | * internal datapath is fixed 16 bit | ||
| 61 | */ | ||
| 62 | static struct dm9000_plat_data dm9000_platdata = { | ||
| 63 | .flags = DM9000_PLATF_16BITONLY, | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* | ||
| 67 | * the DM9000 drivers wants two defined address spaces | ||
| 68 | * to gain access to address latch registers and the data path. | ||
| 69 | */ | ||
| 70 | static struct resource dm9000x_resources[] = { | ||
| 71 | [0] = { | ||
| 72 | .name = "address area", | ||
| 73 | .start = IMX_CS5_PHYS, | ||
| 74 | .end = IMX_CS5_PHYS + 1, | ||
| 75 | .flags = IORESOURCE_MEM /* address access */ | ||
| 76 | }, | ||
| 77 | [1] = { | ||
| 78 | .name = "data area", | ||
| 79 | .start = IMX_CS5_PHYS + 4, | ||
| 80 | .end = IMX_CS5_PHYS + 5, | ||
| 81 | .flags = IORESOURCE_MEM /* data access */ | ||
| 82 | }, | ||
| 83 | [2] = { | ||
| 84 | .start = IRQ_GPIOC(3), | ||
| 85 | .end = IRQ_GPIOC(3), | ||
| 86 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL | ||
| 87 | }, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static struct platform_device dm9000x_device = { | ||
| 91 | .name = "dm9000", | ||
| 92 | .id = 0, | ||
| 93 | .num_resources = ARRAY_SIZE(dm9000x_resources), | ||
| 94 | .resource = dm9000x_resources, | ||
| 95 | .dev = { | ||
| 96 | .platform_data = &dm9000_platdata, | ||
| 97 | } | ||
| 98 | }; | ||
| 99 | |||
| 100 | static int mxc_uart1_pins[] = { | ||
| 101 | PC9_PF_UART1_CTS, | ||
| 102 | PC10_PF_UART1_RTS, | ||
| 103 | PC11_PF_UART1_TXD, | ||
| 104 | PC12_PF_UART1_RXD, | ||
| 105 | }; | ||
| 106 | |||
| 107 | static int uart1_mxc_init(struct platform_device *pdev) | ||
| 108 | { | ||
| 109 | return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, | ||
| 110 | ARRAY_SIZE(mxc_uart1_pins), "UART1"); | ||
| 111 | } | ||
| 112 | |||
| 113 | static int uart1_mxc_exit(struct platform_device *pdev) | ||
| 114 | { | ||
| 115 | mxc_gpio_release_multiple_pins(mxc_uart1_pins, | ||
| 116 | ARRAY_SIZE(mxc_uart1_pins)); | ||
| 117 | return 0; | ||
| 118 | } | ||
| 119 | |||
| 120 | static struct imxuart_platform_data uart_pdata = { | ||
| 121 | .init = uart1_mxc_init, | ||
| 122 | .exit = uart1_mxc_exit, | ||
| 123 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct platform_device *devices[] __initdata = { | ||
| 127 | &scb_flash_device, | ||
| 128 | &dm9000x_device, | ||
| 129 | }; | ||
| 130 | |||
| 131 | /* | ||
| 132 | * scb9328_init - Init the CPU card itself | ||
| 133 | */ | ||
| 134 | static void __init scb9328_init(void) | ||
| 135 | { | ||
| 136 | mxc_register_device(&imx_uart1_device, &uart_pdata); | ||
| 137 | |||
| 138 | printk(KERN_INFO"Scb9328: Adding devices\n"); | ||
| 139 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 140 | } | ||
| 141 | |||
| 142 | static void __init scb9328_timer_init(void) | ||
| 143 | { | ||
| 144 | mx1_clocks_init(32000); | ||
| 145 | } | ||
| 146 | |||
| 147 | static struct sys_timer scb9328_timer = { | ||
| 148 | .init = scb9328_timer_init, | ||
| 149 | }; | ||
| 150 | |||
| 151 | MACHINE_START(SCB9328, "Synertronixx scb9328") | ||
| 152 | /* Sascha Hauer */ | ||
| 153 | .phys_io = 0x00200000, | ||
| 154 | .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc, | ||
| 155 | .boot_params = 0x08000100, | ||
| 156 | .map_io = mxc_map_io, | ||
| 157 | .init_irq = mxc_init_irq, | ||
| 158 | .timer = &scb9328_timer, | ||
| 159 | .init_machine = scb9328_init, | ||
| 160 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index 1eaa97cb716d..42a788842f49 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig | |||
| @@ -1,14 +1,22 @@ | |||
| 1 | comment "MX2 family CPU support" | 1 | if ARCH_MX2 |
| 2 | depends on ARCH_MX2 | 2 | |
| 3 | choice | ||
| 4 | prompt "CPUs:" | ||
| 5 | default MACH_MX21 | ||
| 6 | |||
| 7 | config MACH_MX21 | ||
| 8 | bool "i.MX21 support" | ||
| 9 | help | ||
| 10 | This enables support for Freescale's MX2 based i.MX21 processor. | ||
| 3 | 11 | ||
| 4 | config MACH_MX27 | 12 | config MACH_MX27 |
| 5 | bool "i.MX27 support" | 13 | bool "i.MX27 support" |
| 6 | depends on ARCH_MX2 | ||
| 7 | help | 14 | help |
| 8 | This enables support for Freescale's MX2 based i.MX27 processor. | 15 | This enables support for Freescale's MX2 based i.MX27 processor. |
| 9 | 16 | ||
| 10 | comment "MX2 Platforms" | 17 | endchoice |
| 11 | depends on ARCH_MX2 | 18 | |
| 19 | comment "MX2 platforms:" | ||
| 12 | 20 | ||
| 13 | config MACH_MX27ADS | 21 | config MACH_MX27ADS |
| 14 | bool "MX27ADS platform" | 22 | bool "MX27ADS platform" |
| @@ -37,3 +45,5 @@ config MACH_PCM970_BASEBOARD | |||
| 37 | PCM970 evaluation board. | 45 | PCM970 evaluation board. |
| 38 | 46 | ||
| 39 | endchoice | 47 | endchoice |
| 48 | |||
| 49 | endif | ||
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 382d86080e86..950649a91540 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile | |||
| @@ -4,7 +4,9 @@ | |||
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | 6 | ||
| 7 | obj-y := system.o generic.o devices.o serial.o | 7 | obj-y := generic.o devices.o serial.o |
| 8 | |||
| 9 | obj-$(CONFIG_MACH_MX21) += clock_imx21.o | ||
| 8 | 10 | ||
| 9 | obj-$(CONFIG_MACH_MX27) += cpu_imx27.o | 11 | obj-$(CONFIG_MACH_MX27) += cpu_imx27.o |
| 10 | obj-$(CONFIG_MACH_MX27) += clock_imx27.o | 12 | obj-$(CONFIG_MACH_MX27) += clock_imx27.o |
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot index 696831dcd485..e867398a8fdb 100644 --- a/arch/arm/mach-mx2/Makefile.boot +++ b/arch/arm/mach-mx2/Makefile.boot | |||
| @@ -1,3 +1,7 @@ | |||
| 1 | zreladdr-y := 0xA0008000 | 1 | zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 |
| 2 | params_phys-y := 0xA0000100 | 2 | params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 |
| 3 | initrd_phys-y := 0xA0800000 | 3 | initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 |
| 4 | |||
| 5 | zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 | ||
| 6 | params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 | ||
| 7 | initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 | ||
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c new file mode 100644 index 000000000000..2dee5c87614c --- /dev/null +++ b/arch/arm/mach-mx2/clock_imx21.c | |||
| @@ -0,0 +1,984 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version 2 | ||
| 9 | * of the License, or (at your option) any later version. | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/module.h> | ||
| 24 | |||
| 25 | #include <mach/clock.h> | ||
| 26 | #include <mach/common.h> | ||
| 27 | #include <asm/clkdev.h> | ||
| 28 | #include <asm/div64.h> | ||
| 29 | |||
| 30 | #include "crm_regs.h" | ||
| 31 | |||
| 32 | static int _clk_enable(struct clk *clk) | ||
| 33 | { | ||
| 34 | u32 reg; | ||
| 35 | |||
| 36 | reg = __raw_readl(clk->enable_reg); | ||
| 37 | reg |= 1 << clk->enable_shift; | ||
| 38 | __raw_writel(reg, clk->enable_reg); | ||
| 39 | return 0; | ||
| 40 | } | ||
| 41 | |||
| 42 | static void _clk_disable(struct clk *clk) | ||
| 43 | { | ||
| 44 | u32 reg; | ||
| 45 | |||
| 46 | reg = __raw_readl(clk->enable_reg); | ||
| 47 | reg &= ~(1 << clk->enable_shift); | ||
| 48 | __raw_writel(reg, clk->enable_reg); | ||
| 49 | } | ||
| 50 | |||
| 51 | static int _clk_spll_enable(struct clk *clk) | ||
| 52 | { | ||
| 53 | u32 reg; | ||
| 54 | |||
| 55 | reg = __raw_readl(CCM_CSCR); | ||
| 56 | reg |= CCM_CSCR_SPEN; | ||
| 57 | __raw_writel(reg, CCM_CSCR); | ||
| 58 | |||
| 59 | while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) | ||
| 60 | ; | ||
| 61 | return 0; | ||
| 62 | } | ||
| 63 | |||
| 64 | static void _clk_spll_disable(struct clk *clk) | ||
| 65 | { | ||
| 66 | u32 reg; | ||
| 67 | |||
| 68 | reg = __raw_readl(CCM_CSCR); | ||
| 69 | reg &= ~CCM_CSCR_SPEN; | ||
| 70 | __raw_writel(reg, CCM_CSCR); | ||
| 71 | } | ||
| 72 | |||
| 73 | |||
| 74 | #define CSCR() (__raw_readl(CCM_CSCR)) | ||
| 75 | #define PCDR0() (__raw_readl(CCM_PCDR0)) | ||
| 76 | #define PCDR1() (__raw_readl(CCM_PCDR1)) | ||
| 77 | |||
| 78 | static unsigned long _clk_perclkx_round_rate(struct clk *clk, | ||
| 79 | unsigned long rate) | ||
| 80 | { | ||
| 81 | u32 div; | ||
| 82 | unsigned long parent_rate; | ||
| 83 | |||
| 84 | parent_rate = clk_get_rate(clk->parent); | ||
| 85 | |||
| 86 | div = parent_rate / rate; | ||
| 87 | if (parent_rate % rate) | ||
| 88 | div++; | ||
| 89 | |||
| 90 | if (div > 64) | ||
| 91 | div = 64; | ||
| 92 | |||
| 93 | return parent_rate / div; | ||
| 94 | } | ||
| 95 | |||
| 96 | static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) | ||
| 97 | { | ||
| 98 | u32 reg; | ||
| 99 | u32 div; | ||
| 100 | unsigned long parent_rate; | ||
| 101 | |||
| 102 | parent_rate = clk_get_rate(clk->parent); | ||
| 103 | |||
| 104 | if (clk->id < 0 || clk->id > 3) | ||
| 105 | return -EINVAL; | ||
| 106 | |||
| 107 | div = parent_rate / rate; | ||
| 108 | if (div > 64 || div < 1 || ((parent_rate / div) != rate)) | ||
| 109 | return -EINVAL; | ||
| 110 | div--; | ||
| 111 | |||
| 112 | reg = | ||
| 113 | __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK << | ||
| 114 | (clk->id << 3)); | ||
| 115 | reg |= div << (clk->id << 3); | ||
| 116 | __raw_writel(reg, CCM_PCDR1); | ||
| 117 | |||
| 118 | return 0; | ||
| 119 | } | ||
| 120 | |||
| 121 | static unsigned long _clk_usb_recalc(struct clk *clk) | ||
| 122 | { | ||
| 123 | unsigned long usb_pdf; | ||
| 124 | unsigned long parent_rate; | ||
| 125 | |||
| 126 | parent_rate = clk_get_rate(clk->parent); | ||
| 127 | |||
| 128 | usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; | ||
| 129 | |||
| 130 | return parent_rate / (usb_pdf + 1U); | ||
| 131 | } | ||
| 132 | |||
| 133 | static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf) | ||
| 134 | { | ||
| 135 | unsigned long parent_rate; | ||
| 136 | |||
| 137 | parent_rate = clk_get_rate(clk->parent); | ||
| 138 | |||
| 139 | pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ | ||
| 140 | |||
| 141 | return 2UL * parent_rate / pdf; | ||
| 142 | } | ||
| 143 | |||
| 144 | static unsigned long _clk_ssi1_recalc(struct clk *clk) | ||
| 145 | { | ||
| 146 | return _clk_ssix_recalc(clk, | ||
| 147 | (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) | ||
| 148 | >> CCM_PCDR0_SSI1BAUDDIV_OFFSET); | ||
| 149 | } | ||
| 150 | |||
| 151 | static unsigned long _clk_ssi2_recalc(struct clk *clk) | ||
| 152 | { | ||
| 153 | return _clk_ssix_recalc(clk, | ||
| 154 | (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >> | ||
| 155 | CCM_PCDR0_SSI2BAUDDIV_OFFSET); | ||
| 156 | } | ||
| 157 | |||
| 158 | static unsigned long _clk_nfc_recalc(struct clk *clk) | ||
| 159 | { | ||
| 160 | unsigned long nfc_pdf; | ||
| 161 | unsigned long parent_rate; | ||
| 162 | |||
| 163 | parent_rate = clk_get_rate(clk->parent); | ||
| 164 | |||
| 165 | nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK) | ||
| 166 | >> CCM_PCDR0_NFCDIV_OFFSET; | ||
| 167 | |||
| 168 | return parent_rate / (nfc_pdf + 1); | ||
| 169 | } | ||
| 170 | |||
| 171 | static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) | ||
| 172 | { | ||
| 173 | return clk->parent->round_rate(clk->parent, rate); | ||
| 174 | } | ||
| 175 | |||
| 176 | static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | ||
| 177 | { | ||
| 178 | return clk->parent->set_rate(clk->parent, rate); | ||
| 179 | } | ||
| 180 | |||
| 181 | static unsigned long external_high_reference; /* in Hz */ | ||
| 182 | |||
| 183 | static unsigned long get_high_reference_clock_rate(struct clk *clk) | ||
| 184 | { | ||
| 185 | return external_high_reference; | ||
| 186 | } | ||
| 187 | |||
| 188 | /* | ||
| 189 | * the high frequency external clock reference | ||
| 190 | * Default case is 26MHz. | ||
| 191 | */ | ||
| 192 | static struct clk ckih_clk = { | ||
| 193 | .get_rate = get_high_reference_clock_rate, | ||
| 194 | }; | ||
| 195 | |||
| 196 | static unsigned long external_low_reference; /* in Hz */ | ||
| 197 | |||
| 198 | static unsigned long get_low_reference_clock_rate(struct clk *clk) | ||
| 199 | { | ||
| 200 | return external_low_reference; | ||
| 201 | } | ||
| 202 | |||
| 203 | /* | ||
| 204 | * the low frequency external clock reference | ||
| 205 | * Default case is 32.768kHz. | ||
| 206 | */ | ||
| 207 | static struct clk ckil_clk = { | ||
| 208 | .get_rate = get_low_reference_clock_rate, | ||
| 209 | }; | ||
| 210 | |||
| 211 | |||
| 212 | static unsigned long _clk_fpm_recalc(struct clk *clk) | ||
| 213 | { | ||
| 214 | return clk_get_rate(clk->parent) * 512; | ||
| 215 | } | ||
| 216 | |||
| 217 | /* Output of frequency pre multiplier */ | ||
| 218 | static struct clk fpm_clk = { | ||
| 219 | .parent = &ckil_clk, | ||
| 220 | .get_rate = _clk_fpm_recalc, | ||
| 221 | }; | ||
| 222 | |||
| 223 | static unsigned long get_mpll_clk(struct clk *clk) | ||
| 224 | { | ||
| 225 | uint32_t reg; | ||
| 226 | unsigned long ref_clk; | ||
| 227 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 228 | unsigned long long temp; | ||
| 229 | |||
| 230 | ref_clk = clk_get_rate(clk->parent); | ||
| 231 | |||
| 232 | reg = __raw_readl(CCM_MPCTL0); | ||
| 233 | pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; | ||
| 234 | mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; | ||
| 235 | mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; | ||
| 236 | mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; | ||
| 237 | |||
| 238 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 239 | temp = 2LL * ref_clk * mfn; | ||
| 240 | do_div(temp, mfd + 1); | ||
| 241 | temp = 2LL * ref_clk * mfi + temp; | ||
| 242 | do_div(temp, pdf + 1); | ||
| 243 | |||
| 244 | return (unsigned long)temp; | ||
| 245 | } | ||
| 246 | |||
| 247 | static struct clk mpll_clk = { | ||
| 248 | .parent = &ckih_clk, | ||
| 249 | .get_rate = get_mpll_clk, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static unsigned long _clk_fclk_get_rate(struct clk *clk) | ||
| 253 | { | ||
| 254 | unsigned long parent_rate; | ||
| 255 | u32 div; | ||
| 256 | |||
| 257 | div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; | ||
| 258 | parent_rate = clk_get_rate(clk->parent); | ||
| 259 | |||
| 260 | return parent_rate / (div+1); | ||
| 261 | } | ||
| 262 | |||
| 263 | static struct clk fclk_clk = { | ||
| 264 | .parent = &mpll_clk, | ||
| 265 | .get_rate = _clk_fclk_get_rate | ||
| 266 | }; | ||
| 267 | |||
| 268 | static unsigned long get_spll_clk(struct clk *clk) | ||
| 269 | { | ||
| 270 | uint32_t reg; | ||
| 271 | unsigned long ref_clk; | ||
| 272 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 273 | unsigned long long temp; | ||
| 274 | |||
| 275 | ref_clk = clk_get_rate(clk->parent); | ||
| 276 | |||
| 277 | reg = __raw_readl(CCM_SPCTL0); | ||
| 278 | pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; | ||
| 279 | mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; | ||
| 280 | mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; | ||
| 281 | mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; | ||
| 282 | |||
| 283 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 284 | temp = 2LL * ref_clk * mfn; | ||
| 285 | do_div(temp, mfd + 1); | ||
| 286 | temp = 2LL * ref_clk * mfi + temp; | ||
| 287 | do_div(temp, pdf + 1); | ||
| 288 | |||
| 289 | return (unsigned long)temp; | ||
| 290 | } | ||
| 291 | |||
| 292 | static struct clk spll_clk = { | ||
| 293 | .parent = &ckih_clk, | ||
| 294 | .get_rate = get_spll_clk, | ||
| 295 | .enable = _clk_spll_enable, | ||
| 296 | .disable = _clk_spll_disable, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static unsigned long get_hclk_clk(struct clk *clk) | ||
| 300 | { | ||
| 301 | unsigned long rate; | ||
| 302 | unsigned long bclk_pdf; | ||
| 303 | |||
| 304 | bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) | ||
| 305 | >> CCM_CSCR_BCLK_OFFSET; | ||
| 306 | |||
| 307 | rate = clk_get_rate(clk->parent); | ||
| 308 | return rate / (bclk_pdf + 1); | ||
| 309 | } | ||
| 310 | |||
| 311 | static struct clk hclk_clk = { | ||
| 312 | .parent = &fclk_clk, | ||
| 313 | .get_rate = get_hclk_clk, | ||
| 314 | }; | ||
| 315 | |||
| 316 | static unsigned long get_ipg_clk(struct clk *clk) | ||
| 317 | { | ||
| 318 | unsigned long rate; | ||
| 319 | unsigned long ipg_pdf; | ||
| 320 | |||
| 321 | ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; | ||
| 322 | |||
| 323 | rate = clk_get_rate(clk->parent); | ||
| 324 | return rate / (ipg_pdf + 1); | ||
| 325 | } | ||
| 326 | |||
| 327 | static struct clk ipg_clk = { | ||
| 328 | .parent = &hclk_clk, | ||
| 329 | .get_rate = get_ipg_clk, | ||
| 330 | }; | ||
| 331 | |||
| 332 | static unsigned long _clk_perclkx_recalc(struct clk *clk) | ||
| 333 | { | ||
| 334 | unsigned long perclk_pdf; | ||
| 335 | unsigned long parent_rate; | ||
| 336 | |||
| 337 | parent_rate = clk_get_rate(clk->parent); | ||
| 338 | |||
| 339 | if (clk->id < 0 || clk->id > 3) | ||
| 340 | return 0; | ||
| 341 | |||
| 342 | perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; | ||
| 343 | |||
| 344 | return parent_rate / (perclk_pdf + 1); | ||
| 345 | } | ||
| 346 | |||
| 347 | static struct clk per_clk[] = { | ||
| 348 | { | ||
| 349 | .id = 0, | ||
| 350 | .parent = &mpll_clk, | ||
| 351 | .get_rate = _clk_perclkx_recalc, | ||
| 352 | }, { | ||
| 353 | .id = 1, | ||
| 354 | .parent = &mpll_clk, | ||
| 355 | .get_rate = _clk_perclkx_recalc, | ||
| 356 | }, { | ||
| 357 | .id = 2, | ||
| 358 | .parent = &mpll_clk, | ||
| 359 | .round_rate = _clk_perclkx_round_rate, | ||
| 360 | .set_rate = _clk_perclkx_set_rate, | ||
| 361 | .get_rate = _clk_perclkx_recalc, | ||
| 362 | /* Enable/Disable done via lcd_clkc[1] */ | ||
| 363 | }, { | ||
| 364 | .id = 3, | ||
| 365 | .parent = &mpll_clk, | ||
| 366 | .round_rate = _clk_perclkx_round_rate, | ||
| 367 | .set_rate = _clk_perclkx_set_rate, | ||
| 368 | .get_rate = _clk_perclkx_recalc, | ||
| 369 | /* Enable/Disable done via csi_clk[1] */ | ||
| 370 | }, | ||
| 371 | }; | ||
| 372 | |||
| 373 | static struct clk uart_ipg_clk[]; | ||
| 374 | |||
| 375 | static struct clk uart_clk[] = { | ||
| 376 | { | ||
| 377 | .id = 0, | ||
| 378 | .parent = &per_clk[0], | ||
| 379 | .secondary = &uart_ipg_clk[0], | ||
| 380 | }, { | ||
| 381 | .id = 1, | ||
| 382 | .parent = &per_clk[0], | ||
| 383 | .secondary = &uart_ipg_clk[1], | ||
| 384 | }, { | ||
| 385 | .id = 2, | ||
| 386 | .parent = &per_clk[0], | ||
| 387 | .secondary = &uart_ipg_clk[2], | ||
| 388 | }, { | ||
| 389 | .id = 3, | ||
| 390 | .parent = &per_clk[0], | ||
| 391 | .secondary = &uart_ipg_clk[3], | ||
| 392 | }, | ||
| 393 | }; | ||
| 394 | |||
| 395 | static struct clk uart_ipg_clk[] = { | ||
| 396 | { | ||
| 397 | .id = 0, | ||
| 398 | .parent = &ipg_clk, | ||
| 399 | .enable = _clk_enable, | ||
| 400 | .enable_reg = CCM_PCCR_UART1_REG, | ||
| 401 | .enable_shift = CCM_PCCR_UART1_OFFSET, | ||
| 402 | .disable = _clk_disable, | ||
| 403 | }, { | ||
| 404 | .id = 1, | ||
| 405 | .parent = &ipg_clk, | ||
| 406 | .enable = _clk_enable, | ||
| 407 | .enable_reg = CCM_PCCR_UART2_REG, | ||
| 408 | .enable_shift = CCM_PCCR_UART2_OFFSET, | ||
| 409 | .disable = _clk_disable, | ||
| 410 | }, { | ||
| 411 | .id = 2, | ||
| 412 | .parent = &ipg_clk, | ||
| 413 | .enable = _clk_enable, | ||
| 414 | .enable_reg = CCM_PCCR_UART3_REG, | ||
| 415 | .enable_shift = CCM_PCCR_UART3_OFFSET, | ||
| 416 | .disable = _clk_disable, | ||
| 417 | }, { | ||
| 418 | .id = 3, | ||
| 419 | .parent = &ipg_clk, | ||
| 420 | .enable = _clk_enable, | ||
| 421 | .enable_reg = CCM_PCCR_UART4_REG, | ||
| 422 | .enable_shift = CCM_PCCR_UART4_OFFSET, | ||
| 423 | .disable = _clk_disable, | ||
| 424 | }, | ||
| 425 | }; | ||
| 426 | |||
| 427 | static struct clk gpt_ipg_clk[]; | ||
| 428 | |||
| 429 | static struct clk gpt_clk[] = { | ||
| 430 | { | ||
| 431 | .id = 0, | ||
| 432 | .parent = &per_clk[0], | ||
| 433 | .secondary = &gpt_ipg_clk[0], | ||
| 434 | }, { | ||
| 435 | .id = 1, | ||
| 436 | .parent = &per_clk[0], | ||
| 437 | .secondary = &gpt_ipg_clk[1], | ||
| 438 | }, { | ||
| 439 | .id = 2, | ||
| 440 | .parent = &per_clk[0], | ||
| 441 | .secondary = &gpt_ipg_clk[2], | ||
| 442 | }, | ||
| 443 | }; | ||
| 444 | |||
| 445 | static struct clk gpt_ipg_clk[] = { | ||
| 446 | { | ||
| 447 | .id = 0, | ||
| 448 | .parent = &ipg_clk, | ||
| 449 | .enable = _clk_enable, | ||
| 450 | .enable_reg = CCM_PCCR_GPT1_REG, | ||
| 451 | .enable_shift = CCM_PCCR_GPT1_OFFSET, | ||
| 452 | .disable = _clk_disable, | ||
| 453 | }, { | ||
| 454 | .id = 1, | ||
| 455 | .parent = &ipg_clk, | ||
| 456 | .enable = _clk_enable, | ||
| 457 | .enable_reg = CCM_PCCR_GPT2_REG, | ||
| 458 | .enable_shift = CCM_PCCR_GPT2_OFFSET, | ||
| 459 | .disable = _clk_disable, | ||
| 460 | }, { | ||
| 461 | .id = 2, | ||
| 462 | .parent = &ipg_clk, | ||
| 463 | .enable = _clk_enable, | ||
| 464 | .enable_reg = CCM_PCCR_GPT3_REG, | ||
| 465 | .enable_shift = CCM_PCCR_GPT3_OFFSET, | ||
| 466 | .disable = _clk_disable, | ||
| 467 | }, | ||
| 468 | }; | ||
| 469 | |||
| 470 | static struct clk pwm_clk[] = { | ||
| 471 | { | ||
| 472 | .parent = &per_clk[0], | ||
| 473 | .secondary = &pwm_clk[1], | ||
| 474 | }, { | ||
| 475 | .parent = &ipg_clk, | ||
| 476 | .enable = _clk_enable, | ||
| 477 | .enable_reg = CCM_PCCR_PWM_REG, | ||
| 478 | .enable_shift = CCM_PCCR_PWM_OFFSET, | ||
| 479 | .disable = _clk_disable, | ||
| 480 | }, | ||
| 481 | }; | ||
| 482 | |||
| 483 | static struct clk sdhc_ipg_clk[]; | ||
| 484 | |||
| 485 | static struct clk sdhc_clk[] = { | ||
| 486 | { | ||
| 487 | .id = 0, | ||
| 488 | .parent = &per_clk[1], | ||
| 489 | .secondary = &sdhc_ipg_clk[0], | ||
| 490 | }, { | ||
| 491 | .id = 1, | ||
| 492 | .parent = &per_clk[1], | ||
| 493 | .secondary = &sdhc_ipg_clk[1], | ||
| 494 | }, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static struct clk sdhc_ipg_clk[] = { | ||
| 498 | { | ||
| 499 | .id = 0, | ||
| 500 | .parent = &ipg_clk, | ||
| 501 | .enable = _clk_enable, | ||
| 502 | .enable_reg = CCM_PCCR_SDHC1_REG, | ||
| 503 | .enable_shift = CCM_PCCR_SDHC1_OFFSET, | ||
| 504 | .disable = _clk_disable, | ||
| 505 | }, { | ||
| 506 | .id = 1, | ||
| 507 | .parent = &ipg_clk, | ||
| 508 | .enable = _clk_enable, | ||
| 509 | .enable_reg = CCM_PCCR_SDHC2_REG, | ||
| 510 | .enable_shift = CCM_PCCR_SDHC2_OFFSET, | ||
| 511 | .disable = _clk_disable, | ||
| 512 | }, | ||
| 513 | }; | ||
| 514 | |||
| 515 | static struct clk cspi_ipg_clk[]; | ||
| 516 | |||
| 517 | static struct clk cspi_clk[] = { | ||
| 518 | { | ||
| 519 | .id = 0, | ||
| 520 | .parent = &per_clk[1], | ||
| 521 | .secondary = &cspi_ipg_clk[0], | ||
| 522 | }, { | ||
| 523 | .id = 1, | ||
| 524 | .parent = &per_clk[1], | ||
| 525 | .secondary = &cspi_ipg_clk[1], | ||
| 526 | }, { | ||
| 527 | .id = 2, | ||
| 528 | .parent = &per_clk[1], | ||
| 529 | .secondary = &cspi_ipg_clk[2], | ||
| 530 | }, | ||
| 531 | }; | ||
| 532 | |||
| 533 | static struct clk cspi_ipg_clk[] = { | ||
| 534 | { | ||
| 535 | .id = 0, | ||
| 536 | .parent = &ipg_clk, | ||
| 537 | .enable = _clk_enable, | ||
| 538 | .enable_reg = CCM_PCCR_CSPI1_REG, | ||
| 539 | .enable_shift = CCM_PCCR_CSPI1_OFFSET, | ||
| 540 | .disable = _clk_disable, | ||
| 541 | }, { | ||
| 542 | .id = 1, | ||
| 543 | .parent = &ipg_clk, | ||
| 544 | .enable = _clk_enable, | ||
| 545 | .enable_reg = CCM_PCCR_CSPI2_REG, | ||
| 546 | .enable_shift = CCM_PCCR_CSPI2_OFFSET, | ||
| 547 | .disable = _clk_disable, | ||
| 548 | }, { | ||
| 549 | .id = 3, | ||
| 550 | .parent = &ipg_clk, | ||
| 551 | .enable = _clk_enable, | ||
| 552 | .enable_reg = CCM_PCCR_CSPI3_REG, | ||
| 553 | .enable_shift = CCM_PCCR_CSPI3_OFFSET, | ||
| 554 | .disable = _clk_disable, | ||
| 555 | }, | ||
| 556 | }; | ||
| 557 | |||
| 558 | static struct clk lcdc_clk[] = { | ||
| 559 | { | ||
| 560 | .parent = &per_clk[2], | ||
| 561 | .secondary = &lcdc_clk[1], | ||
| 562 | .round_rate = _clk_parent_round_rate, | ||
| 563 | .set_rate = _clk_parent_set_rate, | ||
| 564 | }, { | ||
| 565 | .parent = &ipg_clk, | ||
| 566 | .secondary = &lcdc_clk[2], | ||
| 567 | .enable = _clk_enable, | ||
| 568 | .enable_reg = CCM_PCCR_LCDC_REG, | ||
| 569 | .enable_shift = CCM_PCCR_LCDC_OFFSET, | ||
| 570 | .disable = _clk_disable, | ||
| 571 | }, { | ||
| 572 | .parent = &hclk_clk, | ||
| 573 | .enable = _clk_enable, | ||
| 574 | .enable_reg = CCM_PCCR_HCLK_LCDC_REG, | ||
| 575 | .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET, | ||
| 576 | .disable = _clk_disable, | ||
| 577 | }, | ||
| 578 | }; | ||
| 579 | |||
| 580 | static struct clk csi_clk[] = { | ||
| 581 | { | ||
| 582 | .parent = &per_clk[3], | ||
| 583 | .secondary = &csi_clk[1], | ||
| 584 | .round_rate = _clk_parent_round_rate, | ||
| 585 | .set_rate = _clk_parent_set_rate, | ||
| 586 | }, { | ||
| 587 | .parent = &hclk_clk, | ||
| 588 | .enable = _clk_enable, | ||
| 589 | .enable_reg = CCM_PCCR_HCLK_CSI_REG, | ||
| 590 | .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET, | ||
| 591 | .disable = _clk_disable, | ||
| 592 | }, | ||
| 593 | }; | ||
| 594 | |||
| 595 | static struct clk usb_clk[] = { | ||
| 596 | { | ||
| 597 | .parent = &spll_clk, | ||
| 598 | .get_rate = _clk_usb_recalc, | ||
| 599 | .enable = _clk_enable, | ||
| 600 | .enable_reg = CCM_PCCR_USBOTG_REG, | ||
| 601 | .enable_shift = CCM_PCCR_USBOTG_OFFSET, | ||
| 602 | .disable = _clk_disable, | ||
| 603 | }, { | ||
| 604 | .parent = &hclk_clk, | ||
| 605 | .enable = _clk_enable, | ||
| 606 | .enable_reg = CCM_PCCR_HCLK_USBOTG_REG, | ||
| 607 | .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET, | ||
| 608 | .disable = _clk_disable, | ||
| 609 | } | ||
| 610 | }; | ||
| 611 | |||
| 612 | static struct clk ssi_ipg_clk[]; | ||
| 613 | |||
| 614 | static struct clk ssi_clk[] = { | ||
| 615 | { | ||
| 616 | .id = 0, | ||
| 617 | .parent = &mpll_clk, | ||
| 618 | .secondary = &ssi_ipg_clk[0], | ||
| 619 | .get_rate = _clk_ssi1_recalc, | ||
| 620 | .enable = _clk_enable, | ||
| 621 | .enable_reg = CCM_PCCR_SSI1_BAUD_REG, | ||
| 622 | .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET, | ||
| 623 | .disable = _clk_disable, | ||
| 624 | }, { | ||
| 625 | .id = 1, | ||
| 626 | .parent = &mpll_clk, | ||
| 627 | .secondary = &ssi_ipg_clk[1], | ||
| 628 | .get_rate = _clk_ssi2_recalc, | ||
| 629 | .enable = _clk_enable, | ||
| 630 | .enable_reg = CCM_PCCR_SSI2_BAUD_REG, | ||
| 631 | .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET, | ||
| 632 | .disable = _clk_disable, | ||
| 633 | }, | ||
| 634 | }; | ||
| 635 | |||
| 636 | static struct clk ssi_ipg_clk[] = { | ||
| 637 | { | ||
| 638 | .id = 0, | ||
| 639 | .parent = &ipg_clk, | ||
| 640 | .enable = _clk_enable, | ||
| 641 | .enable_reg = CCM_PCCR_SSI1_REG, | ||
| 642 | .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET, | ||
| 643 | .disable = _clk_disable, | ||
| 644 | }, { | ||
| 645 | .id = 1, | ||
| 646 | .parent = &ipg_clk, | ||
| 647 | .enable = _clk_enable, | ||
| 648 | .enable_reg = CCM_PCCR_SSI2_REG, | ||
| 649 | .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET, | ||
| 650 | .disable = _clk_disable, | ||
| 651 | }, | ||
| 652 | }; | ||
| 653 | |||
| 654 | |||
| 655 | static struct clk nfc_clk = { | ||
| 656 | .parent = &fclk_clk, | ||
| 657 | .get_rate = _clk_nfc_recalc, | ||
| 658 | .enable = _clk_enable, | ||
| 659 | .enable_reg = CCM_PCCR_NFC_REG, | ||
| 660 | .enable_shift = CCM_PCCR_NFC_OFFSET, | ||
| 661 | .disable = _clk_disable, | ||
| 662 | }; | ||
| 663 | |||
| 664 | static struct clk dma_clk[] = { | ||
| 665 | { | ||
| 666 | .parent = &hclk_clk, | ||
| 667 | .enable = _clk_enable, | ||
| 668 | .enable_reg = CCM_PCCR_DMA_REG, | ||
| 669 | .enable_shift = CCM_PCCR_DMA_OFFSET, | ||
| 670 | .disable = _clk_disable, | ||
| 671 | .secondary = &dma_clk[1], | ||
| 672 | }, { | ||
| 673 | .enable = _clk_enable, | ||
| 674 | .enable_reg = CCM_PCCR_HCLK_DMA_REG, | ||
| 675 | .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET, | ||
| 676 | .disable = _clk_disable, | ||
| 677 | }, | ||
| 678 | }; | ||
| 679 | |||
| 680 | static struct clk brom_clk = { | ||
| 681 | .parent = &hclk_clk, | ||
| 682 | .enable = _clk_enable, | ||
| 683 | .enable_reg = CCM_PCCR_HCLK_BROM_REG, | ||
| 684 | .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET, | ||
| 685 | .disable = _clk_disable, | ||
| 686 | }; | ||
| 687 | |||
| 688 | static struct clk emma_clk[] = { | ||
| 689 | { | ||
| 690 | .parent = &hclk_clk, | ||
| 691 | .enable = _clk_enable, | ||
| 692 | .enable_reg = CCM_PCCR_EMMA_REG, | ||
| 693 | .enable_shift = CCM_PCCR_EMMA_OFFSET, | ||
| 694 | .disable = _clk_disable, | ||
| 695 | .secondary = &emma_clk[1], | ||
| 696 | }, { | ||
| 697 | .enable = _clk_enable, | ||
| 698 | .enable_reg = CCM_PCCR_HCLK_EMMA_REG, | ||
| 699 | .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET, | ||
| 700 | .disable = _clk_disable, | ||
| 701 | } | ||
| 702 | }; | ||
| 703 | |||
| 704 | static struct clk slcdc_clk[] = { | ||
| 705 | { | ||
| 706 | .parent = &hclk_clk, | ||
| 707 | .enable = _clk_enable, | ||
| 708 | .enable_reg = CCM_PCCR_SLCDC_REG, | ||
| 709 | .enable_shift = CCM_PCCR_SLCDC_OFFSET, | ||
| 710 | .disable = _clk_disable, | ||
| 711 | .secondary = &slcdc_clk[1], | ||
| 712 | }, { | ||
| 713 | .enable = _clk_enable, | ||
| 714 | .enable_reg = CCM_PCCR_HCLK_SLCDC_REG, | ||
| 715 | .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET, | ||
| 716 | .disable = _clk_disable, | ||
| 717 | } | ||
| 718 | }; | ||
| 719 | |||
| 720 | static struct clk wdog_clk = { | ||
| 721 | .parent = &ipg_clk, | ||
| 722 | .enable = _clk_enable, | ||
| 723 | .enable_reg = CCM_PCCR_WDT_REG, | ||
| 724 | .enable_shift = CCM_PCCR_WDT_OFFSET, | ||
| 725 | .disable = _clk_disable, | ||
| 726 | }; | ||
| 727 | |||
| 728 | static struct clk gpio_clk = { | ||
| 729 | .parent = &ipg_clk, | ||
| 730 | .enable = _clk_enable, | ||
| 731 | .enable_reg = CCM_PCCR_GPIO_REG, | ||
| 732 | .enable_shift = CCM_PCCR_GPIO_OFFSET, | ||
| 733 | .disable = _clk_disable, | ||
| 734 | }; | ||
| 735 | |||
| 736 | static struct clk i2c_clk = { | ||
| 737 | .id = 0, | ||
| 738 | .parent = &ipg_clk, | ||
| 739 | .enable = _clk_enable, | ||
| 740 | .enable_reg = CCM_PCCR_I2C1_REG, | ||
| 741 | .enable_shift = CCM_PCCR_I2C1_OFFSET, | ||
| 742 | .disable = _clk_disable, | ||
| 743 | }; | ||
| 744 | |||
| 745 | static struct clk kpp_clk = { | ||
| 746 | .parent = &ipg_clk, | ||
| 747 | .enable = _clk_enable, | ||
| 748 | .enable_reg = CCM_PCCR_KPP_REG, | ||
| 749 | .enable_shift = CCM_PCCR_KPP_OFFSET, | ||
| 750 | .disable = _clk_disable, | ||
| 751 | }; | ||
| 752 | |||
| 753 | static struct clk owire_clk = { | ||
| 754 | .parent = &ipg_clk, | ||
| 755 | .enable = _clk_enable, | ||
| 756 | .enable_reg = CCM_PCCR_OWIRE_REG, | ||
| 757 | .enable_shift = CCM_PCCR_OWIRE_OFFSET, | ||
| 758 | .disable = _clk_disable, | ||
| 759 | }; | ||
| 760 | |||
| 761 | static struct clk rtc_clk = { | ||
| 762 | .parent = &ipg_clk, | ||
| 763 | .enable = _clk_enable, | ||
| 764 | .enable_reg = CCM_PCCR_RTC_REG, | ||
| 765 | .enable_shift = CCM_PCCR_RTC_OFFSET, | ||
| 766 | .disable = _clk_disable, | ||
| 767 | }; | ||
| 768 | |||
| 769 | static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) | ||
| 770 | { | ||
| 771 | u32 div; | ||
| 772 | unsigned long parent_rate; | ||
| 773 | |||
| 774 | parent_rate = clk_get_rate(clk->parent); | ||
| 775 | div = parent_rate / rate; | ||
| 776 | if (parent_rate % rate) | ||
| 777 | div++; | ||
| 778 | |||
| 779 | if (div > 8) | ||
| 780 | div = 8; | ||
| 781 | |||
| 782 | return parent_rate / div; | ||
| 783 | } | ||
| 784 | |||
| 785 | static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) | ||
| 786 | { | ||
| 787 | u32 reg; | ||
| 788 | u32 div; | ||
| 789 | unsigned long parent_rate; | ||
| 790 | |||
| 791 | parent_rate = clk_get_rate(clk->parent); | ||
| 792 | |||
| 793 | div = parent_rate / rate; | ||
| 794 | |||
| 795 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) | ||
| 796 | return -EINVAL; | ||
| 797 | div--; | ||
| 798 | |||
| 799 | reg = __raw_readl(CCM_PCDR0); | ||
| 800 | |||
| 801 | if (clk->parent == &usb_clk[0]) { | ||
| 802 | reg &= ~CCM_PCDR0_48MDIV_MASK; | ||
| 803 | reg |= div << CCM_PCDR0_48MDIV_OFFSET; | ||
| 804 | } | ||
| 805 | __raw_writel(reg, CCM_PCDR0); | ||
| 806 | |||
| 807 | return 0; | ||
| 808 | } | ||
| 809 | |||
| 810 | static unsigned long _clk_clko_recalc(struct clk *clk) | ||
| 811 | { | ||
| 812 | u32 div = 0; | ||
| 813 | unsigned long parent_rate; | ||
| 814 | |||
| 815 | parent_rate = clk_get_rate(clk->parent); | ||
| 816 | |||
| 817 | if (clk->parent == &usb_clk[0]) /* 48M */ | ||
| 818 | div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK | ||
| 819 | >> CCM_PCDR0_48MDIV_OFFSET; | ||
| 820 | div++; | ||
| 821 | |||
| 822 | return parent_rate / div; | ||
| 823 | } | ||
| 824 | |||
| 825 | static struct clk clko_clk; | ||
| 826 | |||
| 827 | static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) | ||
| 828 | { | ||
| 829 | u32 reg; | ||
| 830 | |||
| 831 | reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK; | ||
| 832 | |||
| 833 | if (parent == &ckil_clk) | ||
| 834 | reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 835 | else if (parent == &fpm_clk) | ||
| 836 | reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 837 | else if (parent == &ckih_clk) | ||
| 838 | reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 839 | else if (parent == mpll_clk.parent) | ||
| 840 | reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 841 | else if (parent == spll_clk.parent) | ||
| 842 | reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 843 | else if (parent == &mpll_clk) | ||
| 844 | reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 845 | else if (parent == &spll_clk) | ||
| 846 | reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 847 | else if (parent == &fclk_clk) | ||
| 848 | reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 849 | else if (parent == &hclk_clk) | ||
| 850 | reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 851 | else if (parent == &ipg_clk) | ||
| 852 | reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 853 | else if (parent == &per_clk[0]) | ||
| 854 | reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 855 | else if (parent == &per_clk[1]) | ||
| 856 | reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 857 | else if (parent == &per_clk[2]) | ||
| 858 | reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 859 | else if (parent == &per_clk[3]) | ||
| 860 | reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 861 | else if (parent == &ssi_clk[0]) | ||
| 862 | reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 863 | else if (parent == &ssi_clk[1]) | ||
| 864 | reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 865 | else if (parent == &nfc_clk) | ||
| 866 | reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 867 | else if (parent == &usb_clk[0]) | ||
| 868 | reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 869 | else if (parent == &clko_clk) | ||
| 870 | reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 871 | else | ||
| 872 | return -EINVAL; | ||
| 873 | |||
| 874 | __raw_writel(reg, CCM_CCSR); | ||
| 875 | |||
| 876 | return 0; | ||
| 877 | } | ||
| 878 | |||
| 879 | static struct clk clko_clk = { | ||
| 880 | .get_rate = _clk_clko_recalc, | ||
| 881 | .set_rate = _clk_clko_set_rate, | ||
| 882 | .round_rate = _clk_clko_round_rate, | ||
| 883 | .set_parent = _clk_clko_set_parent, | ||
| 884 | }; | ||
| 885 | |||
| 886 | |||
| 887 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 888 | { \ | ||
| 889 | .dev_id = d, \ | ||
| 890 | .con_id = n, \ | ||
| 891 | .clk = &c, \ | ||
| 892 | }, | ||
| 893 | static struct clk_lookup lookups[] __initdata = { | ||
| 894 | /* It's unlikely that any driver wants one of them directly: | ||
| 895 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) | ||
| 896 | _REGISTER_CLOCK(NULL, "ckil", ckil_clk) | ||
| 897 | _REGISTER_CLOCK(NULL, "fpm", fpm_clk) | ||
| 898 | _REGISTER_CLOCK(NULL, "mpll", mpll_clk) | ||
| 899 | _REGISTER_CLOCK(NULL, "spll", spll_clk) | ||
| 900 | _REGISTER_CLOCK(NULL, "fclk", fclk_clk) | ||
| 901 | _REGISTER_CLOCK(NULL, "hclk", hclk_clk) | ||
| 902 | _REGISTER_CLOCK(NULL, "ipg", ipg_clk) | ||
| 903 | */ | ||
| 904 | _REGISTER_CLOCK(NULL, "perclk1", per_clk[0]) | ||
| 905 | _REGISTER_CLOCK(NULL, "perclk2", per_clk[1]) | ||
| 906 | _REGISTER_CLOCK(NULL, "perclk3", per_clk[2]) | ||
| 907 | _REGISTER_CLOCK(NULL, "perclk4", per_clk[3]) | ||
| 908 | _REGISTER_CLOCK(NULL, "clko", clko_clk) | ||
| 909 | _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]) | ||
| 910 | _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1]) | ||
| 911 | _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2]) | ||
| 912 | _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3]) | ||
| 913 | _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0]) | ||
| 914 | _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1]) | ||
| 915 | _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2]) | ||
| 916 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0]) | ||
| 917 | _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0]) | ||
| 918 | _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1]) | ||
| 919 | _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0]) | ||
| 920 | _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1]) | ||
| 921 | _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) | ||
| 922 | _REGISTER_CLOCK(NULL, "lcdc", lcdc_clk[0]) | ||
| 923 | _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) | ||
| 924 | _REGISTER_CLOCK(NULL, "usb", usb_clk[0]) | ||
| 925 | _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0]) | ||
| 926 | _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1]) | ||
| 927 | _REGISTER_CLOCK(NULL, "nfc", nfc_clk) | ||
| 928 | _REGISTER_CLOCK(NULL, "dma", dma_clk[0]) | ||
| 929 | _REGISTER_CLOCK(NULL, "brom", brom_clk) | ||
| 930 | _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) | ||
| 931 | _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) | ||
| 932 | _REGISTER_CLOCK(NULL, "wdog", wdog_clk) | ||
| 933 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) | ||
| 934 | _REGISTER_CLOCK(NULL, "i2c", i2c_clk) | ||
| 935 | _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) | ||
| 936 | _REGISTER_CLOCK(NULL, "owire", owire_clk) | ||
| 937 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | ||
| 938 | }; | ||
| 939 | |||
| 940 | /* | ||
| 941 | * must be called very early to get information about the | ||
| 942 | * available clock rate when the timer framework starts | ||
| 943 | */ | ||
| 944 | int __init mx21_clocks_init(unsigned long lref, unsigned long href) | ||
| 945 | { | ||
| 946 | int i; | ||
| 947 | u32 cscr; | ||
| 948 | |||
| 949 | external_low_reference = lref; | ||
| 950 | external_high_reference = href; | ||
| 951 | |||
| 952 | /* detect clock reference for both system PLL */ | ||
| 953 | cscr = CSCR(); | ||
| 954 | if (cscr & CCM_CSCR_MCU) | ||
| 955 | mpll_clk.parent = &ckih_clk; | ||
| 956 | else | ||
| 957 | mpll_clk.parent = &fpm_clk; | ||
| 958 | |||
| 959 | if (cscr & CCM_CSCR_SP) | ||
| 960 | spll_clk.parent = &ckih_clk; | ||
| 961 | else | ||
| 962 | spll_clk.parent = &fpm_clk; | ||
| 963 | |||
| 964 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | ||
| 965 | clkdev_add(&lookups[i]); | ||
| 966 | |||
| 967 | /* Turn off all clock gates */ | ||
| 968 | __raw_writel(0, CCM_PCCR0); | ||
| 969 | __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1); | ||
| 970 | |||
| 971 | /* This turns of the serial PLL as well */ | ||
| 972 | spll_clk.disable(&spll_clk); | ||
| 973 | |||
| 974 | /* This will propagate to all children and init all the clock rates. */ | ||
| 975 | clk_enable(&per_clk[0]); | ||
| 976 | clk_enable(&gpio_clk); | ||
| 977 | |||
| 978 | #ifdef CONFIG_DEBUG_LL_CONSOLE | ||
| 979 | clk_enable(&uart_clk[0]); | ||
| 980 | #endif | ||
| 981 | |||
| 982 | mxc_timer_init(&gpt_clk[0]); | ||
| 983 | return 0; | ||
| 984 | } | ||
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index c69896d011a1..3f7280c490f0 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com | ||
| 4 | * | 5 | * |
| 5 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License | 7 | * modify it under the terms of the GNU General Public License |
| @@ -20,23 +21,60 @@ | |||
| 20 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 21 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 22 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 23 | #include <linux/spinlock.h> | ||
| 24 | 24 | ||
| 25 | #include <mach/clock.h> | 25 | #include <asm/clkdev.h> |
| 26 | #include <mach/common.h> | ||
| 27 | #include <asm/div64.h> | 26 | #include <asm/div64.h> |
| 28 | 27 | ||
| 29 | #include "crm_regs.h" | 28 | #include <mach/clock.h> |
| 30 | 29 | #include <mach/common.h> | |
| 31 | static struct clk ckil_clk; | 30 | #include <mach/hardware.h> |
| 32 | static struct clk mpll_clk; | 31 | |
| 33 | static struct clk mpll_main_clk[]; | 32 | /* Register offsets */ |
| 34 | static struct clk spll_clk; | 33 | #define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) |
| 35 | 34 | #define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) | |
| 36 | static int _clk_enable(struct clk *clk) | 35 | #define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) |
| 36 | #define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) | ||
| 37 | #define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) | ||
| 38 | #define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) | ||
| 39 | #define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) | ||
| 40 | #define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) | ||
| 41 | #define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) | ||
| 42 | #define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) | ||
| 43 | #define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) | ||
| 44 | #define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) | ||
| 45 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) | ||
| 46 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) | ||
| 47 | |||
| 48 | #define CCM_CSCR_UPDATE_DIS (1 << 31) | ||
| 49 | #define CCM_CSCR_SSI2 (1 << 23) | ||
| 50 | #define CCM_CSCR_SSI1 (1 << 22) | ||
| 51 | #define CCM_CSCR_VPU (1 << 21) | ||
| 52 | #define CCM_CSCR_MSHC (1 << 20) | ||
| 53 | #define CCM_CSCR_SPLLRES (1 << 19) | ||
| 54 | #define CCM_CSCR_MPLLRES (1 << 18) | ||
| 55 | #define CCM_CSCR_SP (1 << 17) | ||
| 56 | #define CCM_CSCR_MCU (1 << 16) | ||
| 57 | #define CCM_CSCR_OSC26MDIV (1 << 4) | ||
| 58 | #define CCM_CSCR_OSC26M (1 << 3) | ||
| 59 | #define CCM_CSCR_FPM (1 << 2) | ||
| 60 | #define CCM_CSCR_SPEN (1 << 1) | ||
| 61 | #define CCM_CSCR_MPEN (1 << 0) | ||
| 62 | |||
| 63 | /* i.MX27 TO 2+ */ | ||
| 64 | #define CCM_CSCR_ARM_SRC (1 << 15) | ||
| 65 | |||
| 66 | #define CCM_SPCTL1_LF (1 << 15) | ||
| 67 | #define CCM_SPCTL1_BRMO (1 << 6) | ||
| 68 | |||
| 69 | static struct clk mpll_main1_clk, mpll_main2_clk; | ||
| 70 | |||
| 71 | static int clk_pccr_enable(struct clk *clk) | ||
| 37 | { | 72 | { |
| 38 | unsigned long reg; | 73 | unsigned long reg; |
| 39 | 74 | ||
| 75 | if (!clk->enable_reg) | ||
| 76 | return 0; | ||
| 77 | |||
| 40 | reg = __raw_readl(clk->enable_reg); | 78 | reg = __raw_readl(clk->enable_reg); |
| 41 | reg |= 1 << clk->enable_shift; | 79 | reg |= 1 << clk->enable_shift; |
| 42 | __raw_writel(reg, clk->enable_reg); | 80 | __raw_writel(reg, clk->enable_reg); |
| @@ -44,16 +82,19 @@ static int _clk_enable(struct clk *clk) | |||
| 44 | return 0; | 82 | return 0; |
| 45 | } | 83 | } |
| 46 | 84 | ||
| 47 | static void _clk_disable(struct clk *clk) | 85 | static void clk_pccr_disable(struct clk *clk) |
| 48 | { | 86 | { |
| 49 | unsigned long reg; | 87 | unsigned long reg; |
| 50 | 88 | ||
| 89 | if (!clk->enable_reg) | ||
| 90 | return; | ||
| 91 | |||
| 51 | reg = __raw_readl(clk->enable_reg); | 92 | reg = __raw_readl(clk->enable_reg); |
| 52 | reg &= ~(1 << clk->enable_shift); | 93 | reg &= ~(1 << clk->enable_shift); |
| 53 | __raw_writel(reg, clk->enable_reg); | 94 | __raw_writel(reg, clk->enable_reg); |
| 54 | } | 95 | } |
| 55 | 96 | ||
| 56 | static int _clk_spll_enable(struct clk *clk) | 97 | static int clk_spll_enable(struct clk *clk) |
| 57 | { | 98 | { |
| 58 | unsigned long reg; | 99 | unsigned long reg; |
| 59 | 100 | ||
| @@ -61,13 +102,12 @@ static int _clk_spll_enable(struct clk *clk) | |||
| 61 | reg |= CCM_CSCR_SPEN; | 102 | reg |= CCM_CSCR_SPEN; |
| 62 | __raw_writel(reg, CCM_CSCR); | 103 | __raw_writel(reg, CCM_CSCR); |
| 63 | 104 | ||
| 64 | while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) | 105 | while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF)); |
| 65 | ; | ||
| 66 | 106 | ||
| 67 | return 0; | 107 | return 0; |
| 68 | } | 108 | } |
| 69 | 109 | ||
| 70 | static void _clk_spll_disable(struct clk *clk) | 110 | static void clk_spll_disable(struct clk *clk) |
| 71 | { | 111 | { |
| 72 | unsigned long reg; | 112 | unsigned long reg; |
| 73 | 113 | ||
| @@ -76,192 +116,30 @@ static void _clk_spll_disable(struct clk *clk) | |||
| 76 | __raw_writel(reg, CCM_CSCR); | 116 | __raw_writel(reg, CCM_CSCR); |
| 77 | } | 117 | } |
| 78 | 118 | ||
| 79 | static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1) | 119 | static int clk_cpu_set_parent(struct clk *clk, struct clk *parent) |
| 80 | { | ||
| 81 | unsigned long reg; | ||
| 82 | |||
| 83 | reg = __raw_readl(CCM_PCCR0); | ||
| 84 | reg |= mask0; | ||
| 85 | __raw_writel(reg, CCM_PCCR0); | ||
| 86 | |||
| 87 | reg = __raw_readl(CCM_PCCR1); | ||
| 88 | reg |= mask1; | ||
| 89 | __raw_writel(reg, CCM_PCCR1); | ||
| 90 | |||
| 91 | } | ||
| 92 | |||
| 93 | static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1) | ||
| 94 | { | ||
| 95 | unsigned long reg; | ||
| 96 | |||
| 97 | reg = __raw_readl(CCM_PCCR0); | ||
| 98 | reg &= ~mask0; | ||
| 99 | __raw_writel(reg, CCM_PCCR0); | ||
| 100 | |||
| 101 | reg = __raw_readl(CCM_PCCR1); | ||
| 102 | reg &= ~mask1; | ||
| 103 | __raw_writel(reg, CCM_PCCR1); | ||
| 104 | } | ||
| 105 | |||
| 106 | static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0) | ||
| 107 | { | ||
| 108 | unsigned long reg; | ||
| 109 | |||
| 110 | reg = __raw_readl(CCM_PCCR1); | ||
| 111 | reg |= mask1; | ||
| 112 | __raw_writel(reg, CCM_PCCR1); | ||
| 113 | |||
| 114 | reg = __raw_readl(CCM_PCCR0); | ||
| 115 | reg |= mask0; | ||
| 116 | __raw_writel(reg, CCM_PCCR0); | ||
| 117 | } | ||
| 118 | |||
| 119 | static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0) | ||
| 120 | { | ||
| 121 | unsigned long reg; | ||
| 122 | |||
| 123 | reg = __raw_readl(CCM_PCCR1); | ||
| 124 | reg &= ~mask1; | ||
| 125 | __raw_writel(reg, CCM_PCCR1); | ||
| 126 | |||
| 127 | reg = __raw_readl(CCM_PCCR0); | ||
| 128 | reg &= ~mask0; | ||
| 129 | __raw_writel(reg, CCM_PCCR0); | ||
| 130 | } | ||
| 131 | |||
| 132 | static int _clk_dma_enable(struct clk *clk) | ||
| 133 | { | ||
| 134 | _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK); | ||
| 135 | |||
| 136 | return 0; | ||
| 137 | } | ||
| 138 | |||
| 139 | static void _clk_dma_disable(struct clk *clk) | ||
| 140 | { | ||
| 141 | _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK); | ||
| 142 | } | ||
| 143 | |||
| 144 | static int _clk_rtic_enable(struct clk *clk) | ||
| 145 | { | ||
| 146 | _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK); | ||
| 147 | |||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | |||
| 151 | static void _clk_rtic_disable(struct clk *clk) | ||
| 152 | { | ||
| 153 | _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK); | ||
| 154 | } | ||
| 155 | |||
| 156 | static int _clk_emma_enable(struct clk *clk) | ||
| 157 | { | ||
| 158 | _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK); | ||
| 159 | |||
| 160 | return 0; | ||
| 161 | } | ||
| 162 | |||
| 163 | static void _clk_emma_disable(struct clk *clk) | ||
| 164 | { | ||
| 165 | _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK); | ||
| 166 | } | ||
| 167 | |||
| 168 | static int _clk_slcdc_enable(struct clk *clk) | ||
| 169 | { | ||
| 170 | _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK); | ||
| 171 | |||
| 172 | return 0; | ||
| 173 | } | ||
| 174 | |||
| 175 | static void _clk_slcdc_disable(struct clk *clk) | ||
| 176 | { | ||
| 177 | _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK); | ||
| 178 | } | ||
| 179 | |||
| 180 | static int _clk_fec_enable(struct clk *clk) | ||
| 181 | { | ||
| 182 | _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK); | ||
| 183 | |||
| 184 | return 0; | ||
| 185 | } | ||
| 186 | |||
| 187 | static void _clk_fec_disable(struct clk *clk) | ||
| 188 | { | ||
| 189 | _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK); | ||
| 190 | } | ||
| 191 | |||
| 192 | static int _clk_vpu_enable(struct clk *clk) | ||
| 193 | { | ||
| 194 | unsigned long reg; | ||
| 195 | |||
| 196 | reg = __raw_readl(CCM_PCCR1); | ||
| 197 | reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK; | ||
| 198 | __raw_writel(reg, CCM_PCCR1); | ||
| 199 | |||
| 200 | return 0; | ||
| 201 | } | ||
| 202 | |||
| 203 | static void _clk_vpu_disable(struct clk *clk) | ||
| 204 | { | 120 | { |
| 205 | unsigned long reg; | 121 | int cscr = __raw_readl(CCM_CSCR); |
| 206 | |||
| 207 | reg = __raw_readl(CCM_PCCR1); | ||
| 208 | reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK); | ||
| 209 | __raw_writel(reg, CCM_PCCR1); | ||
| 210 | } | ||
| 211 | |||
| 212 | static int _clk_sahara2_enable(struct clk *clk) | ||
| 213 | { | ||
| 214 | _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK); | ||
| 215 | |||
| 216 | return 0; | ||
| 217 | } | ||
| 218 | |||
| 219 | static void _clk_sahara2_disable(struct clk *clk) | ||
| 220 | { | ||
| 221 | _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK); | ||
| 222 | } | ||
| 223 | |||
| 224 | static int _clk_mstick1_enable(struct clk *clk) | ||
| 225 | { | ||
| 226 | _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK); | ||
| 227 | |||
| 228 | return 0; | ||
| 229 | } | ||
| 230 | |||
| 231 | static void _clk_mstick1_disable(struct clk *clk) | ||
| 232 | { | ||
| 233 | _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK); | ||
| 234 | } | ||
| 235 | |||
| 236 | #define CSCR() (__raw_readl(CCM_CSCR)) | ||
| 237 | #define PCDR0() (__raw_readl(CCM_PCDR0)) | ||
| 238 | #define PCDR1() (__raw_readl(CCM_PCDR1)) | ||
| 239 | |||
| 240 | static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent) | ||
| 241 | { | ||
| 242 | int cscr = CSCR(); | ||
| 243 | 122 | ||
| 244 | if (clk->parent == parent) | 123 | if (clk->parent == parent) |
| 245 | return 0; | 124 | return 0; |
| 246 | 125 | ||
| 247 | if (mx27_revision() >= CHIP_REV_2_0) { | 126 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 248 | if (parent == &mpll_main_clk[0]) { | 127 | if (parent == &mpll_main1_clk) { |
| 249 | cscr |= CCM_CSCR_ARM_SRC; | 128 | cscr |= CCM_CSCR_ARM_SRC; |
| 250 | } else { | 129 | } else { |
| 251 | if (parent == &mpll_main_clk[1]) | 130 | if (parent == &mpll_main2_clk) |
| 252 | cscr &= ~CCM_CSCR_ARM_SRC; | 131 | cscr &= ~CCM_CSCR_ARM_SRC; |
| 253 | else | 132 | else |
| 254 | return -EINVAL; | 133 | return -EINVAL; |
| 255 | } | 134 | } |
| 256 | __raw_writel(cscr, CCM_CSCR); | 135 | __raw_writel(cscr, CCM_CSCR); |
| 257 | } else | 136 | clk->parent = parent; |
| 258 | return -ENODEV; | 137 | return 0; |
| 259 | 138 | } | |
| 260 | clk->parent = parent; | 139 | return -ENODEV; |
| 261 | return 0; | ||
| 262 | } | 140 | } |
| 263 | 141 | ||
| 264 | static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) | 142 | static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate) |
| 265 | { | 143 | { |
| 266 | int div; | 144 | int div; |
| 267 | unsigned long parent_rate; | 145 | unsigned long parent_rate; |
| @@ -278,7 +156,7 @@ static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) | |||
| 278 | return parent_rate / div; | 156 | return parent_rate / div; |
| 279 | } | 157 | } |
| 280 | 158 | ||
| 281 | static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) | 159 | static int set_rate_cpu(struct clk *clk, unsigned long rate) |
| 282 | { | 160 | { |
| 283 | unsigned int div; | 161 | unsigned int div; |
| 284 | uint32_t reg; | 162 | uint32_t reg; |
| @@ -295,19 +173,18 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) | |||
| 295 | 173 | ||
| 296 | reg = __raw_readl(CCM_CSCR); | 174 | reg = __raw_readl(CCM_CSCR); |
| 297 | if (mx27_revision() >= CHIP_REV_2_0) { | 175 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 298 | reg &= ~CCM_CSCR_ARM_MASK; | 176 | reg &= ~(3 << 12); |
| 299 | reg |= div << CCM_CSCR_ARM_OFFSET; | 177 | reg |= div << 12; |
| 300 | reg &= ~0x06; | 178 | reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); |
| 301 | __raw_writel(reg | 0x80000000, CCM_CSCR); | 179 | __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR); |
| 302 | } else { | 180 | } else { |
| 303 | printk(KERN_ERR "Cant set CPU frequency!\n"); | 181 | printk(KERN_ERR "Can't set CPU frequency!\n"); |
| 304 | } | 182 | } |
| 305 | 183 | ||
| 306 | return 0; | 184 | return 0; |
| 307 | } | 185 | } |
| 308 | 186 | ||
| 309 | static unsigned long _clk_perclkx_round_rate(struct clk *clk, | 187 | static unsigned long round_rate_per(struct clk *clk, unsigned long rate) |
| 310 | unsigned long rate) | ||
| 311 | { | 188 | { |
| 312 | u32 div; | 189 | u32 div; |
| 313 | unsigned long parent_rate; | 190 | unsigned long parent_rate; |
| @@ -324,7 +201,7 @@ static unsigned long _clk_perclkx_round_rate(struct clk *clk, | |||
| 324 | return parent_rate / div; | 201 | return parent_rate / div; |
| 325 | } | 202 | } |
| 326 | 203 | ||
| 327 | static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) | 204 | static int set_rate_per(struct clk *clk, unsigned long rate) |
| 328 | { | 205 | { |
| 329 | u32 reg; | 206 | u32 reg; |
| 330 | u32 div; | 207 | u32 div; |
| @@ -340,84 +217,65 @@ static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) | |||
| 340 | return -EINVAL; | 217 | return -EINVAL; |
| 341 | div--; | 218 | div--; |
| 342 | 219 | ||
| 343 | reg = | 220 | reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3)); |
| 344 | __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK << | ||
| 345 | (clk->id << 3)); | ||
| 346 | reg |= div << (clk->id << 3); | 221 | reg |= div << (clk->id << 3); |
| 347 | __raw_writel(reg, CCM_PCDR1); | 222 | __raw_writel(reg, CCM_PCDR1); |
| 348 | 223 | ||
| 349 | return 0; | 224 | return 0; |
| 350 | } | 225 | } |
| 351 | 226 | ||
| 352 | static unsigned long _clk_usb_recalc(struct clk *clk) | 227 | static unsigned long get_rate_usb(struct clk *clk) |
| 353 | { | 228 | { |
| 354 | unsigned long usb_pdf; | 229 | unsigned long usb_pdf; |
| 355 | unsigned long parent_rate; | 230 | unsigned long parent_rate; |
| 356 | 231 | ||
| 357 | parent_rate = clk_get_rate(clk->parent); | 232 | parent_rate = clk_get_rate(clk->parent); |
| 358 | 233 | ||
| 359 | usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; | 234 | usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7; |
| 360 | 235 | ||
| 361 | return parent_rate / (usb_pdf + 1U); | 236 | return parent_rate / (usb_pdf + 1U); |
| 362 | } | 237 | } |
| 363 | 238 | ||
| 364 | static unsigned long _clk_ssi1_recalc(struct clk *clk) | 239 | static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf) |
| 365 | { | 240 | { |
| 366 | unsigned long ssi1_pdf; | ||
| 367 | unsigned long parent_rate; | 241 | unsigned long parent_rate; |
| 368 | 242 | ||
| 369 | parent_rate = clk_get_rate(clk->parent); | 243 | parent_rate = clk_get_rate(clk->parent); |
| 370 | 244 | ||
| 371 | ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >> | ||
| 372 | CCM_PCDR0_SSI1BAUDDIV_OFFSET; | ||
| 373 | |||
| 374 | if (mx27_revision() >= CHIP_REV_2_0) | 245 | if (mx27_revision() >= CHIP_REV_2_0) |
| 375 | ssi1_pdf += 4; | 246 | pdf += 4; /* MX27 TO2+ */ |
| 376 | else | 247 | else |
| 377 | ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf; | 248 | pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ |
| 378 | 249 | ||
| 379 | return 2UL * parent_rate / ssi1_pdf; | 250 | return 2UL * parent_rate / pdf; |
| 380 | } | 251 | } |
| 381 | 252 | ||
| 382 | static unsigned long _clk_ssi2_recalc(struct clk *clk) | 253 | static unsigned long get_rate_ssi1(struct clk *clk) |
| 383 | { | 254 | { |
| 384 | unsigned long ssi2_pdf; | 255 | return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f); |
| 385 | unsigned long parent_rate; | 256 | } |
| 386 | |||
| 387 | parent_rate = clk_get_rate(clk->parent); | ||
| 388 | |||
| 389 | ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >> | ||
| 390 | CCM_PCDR0_SSI2BAUDDIV_OFFSET; | ||
| 391 | |||
| 392 | if (mx27_revision() >= CHIP_REV_2_0) | ||
| 393 | ssi2_pdf += 4; | ||
| 394 | else | ||
| 395 | ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf; | ||
| 396 | 257 | ||
| 397 | return 2UL * parent_rate / ssi2_pdf; | 258 | static unsigned long get_rate_ssi2(struct clk *clk) |
| 259 | { | ||
| 260 | return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f); | ||
| 398 | } | 261 | } |
| 399 | 262 | ||
| 400 | static unsigned long _clk_nfc_recalc(struct clk *clk) | 263 | static unsigned long get_rate_nfc(struct clk *clk) |
| 401 | { | 264 | { |
| 402 | unsigned long nfc_pdf; | 265 | unsigned long nfc_pdf; |
| 403 | unsigned long parent_rate; | 266 | unsigned long parent_rate; |
| 404 | 267 | ||
| 405 | parent_rate = clk_get_rate(clk->parent); | 268 | parent_rate = clk_get_rate(clk->parent); |
| 406 | 269 | ||
| 407 | if (mx27_revision() >= CHIP_REV_2_0) { | 270 | if (mx27_revision() >= CHIP_REV_2_0) |
| 408 | nfc_pdf = | 271 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; |
| 409 | (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >> | 272 | else |
| 410 | CCM_PCDR0_NFCDIV2_OFFSET; | 273 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; |
| 411 | } else { | ||
| 412 | nfc_pdf = | ||
| 413 | (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >> | ||
| 414 | CCM_PCDR0_NFCDIV_OFFSET; | ||
| 415 | } | ||
| 416 | 274 | ||
| 417 | return parent_rate / (nfc_pdf + 1); | 275 | return parent_rate / (nfc_pdf + 1); |
| 418 | } | 276 | } |
| 419 | 277 | ||
| 420 | static unsigned long _clk_vpu_recalc(struct clk *clk) | 278 | static unsigned long get_rate_vpu(struct clk *clk) |
| 421 | { | 279 | { |
| 422 | unsigned long vpu_pdf; | 280 | unsigned long vpu_pdf; |
| 423 | unsigned long parent_rate; | 281 | unsigned long parent_rate; |
| @@ -425,25 +283,27 @@ static unsigned long _clk_vpu_recalc(struct clk *clk) | |||
| 425 | parent_rate = clk_get_rate(clk->parent); | 283 | parent_rate = clk_get_rate(clk->parent); |
| 426 | 284 | ||
| 427 | if (mx27_revision() >= CHIP_REV_2_0) { | 285 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 428 | vpu_pdf = | 286 | vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; |
| 429 | (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >> | ||
| 430 | CCM_PCDR0_VPUDIV2_OFFSET; | ||
| 431 | vpu_pdf += 4; | 287 | vpu_pdf += 4; |
| 432 | } else { | 288 | } else { |
| 433 | vpu_pdf = | 289 | vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf; |
| 434 | (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >> | ||
| 435 | CCM_PCDR0_VPUDIV_OFFSET; | ||
| 436 | vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; | 290 | vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; |
| 437 | } | 291 | } |
| 292 | |||
| 438 | return 2UL * parent_rate / vpu_pdf; | 293 | return 2UL * parent_rate / vpu_pdf; |
| 439 | } | 294 | } |
| 440 | 295 | ||
| 441 | static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) | 296 | static unsigned long round_rate_parent(struct clk *clk, unsigned long rate) |
| 442 | { | 297 | { |
| 443 | return clk->parent->round_rate(clk->parent, rate); | 298 | return clk->parent->round_rate(clk->parent, rate); |
| 444 | } | 299 | } |
| 445 | 300 | ||
| 446 | static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | 301 | static unsigned long get_rate_parent(struct clk *clk) |
| 302 | { | ||
| 303 | return clk_get_rate(clk->parent); | ||
| 304 | } | ||
| 305 | |||
| 306 | static int set_rate_parent(struct clk *clk, unsigned long rate) | ||
| 447 | { | 307 | { |
| 448 | return clk->parent->set_rate(clk->parent, rate); | 308 | return clk->parent->set_rate(clk->parent, rate); |
| 449 | } | 309 | } |
| @@ -451,1112 +311,380 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | |||
| 451 | /* in Hz */ | 311 | /* in Hz */ |
| 452 | static unsigned long external_high_reference = 26000000; | 312 | static unsigned long external_high_reference = 26000000; |
| 453 | 313 | ||
| 454 | static unsigned long get_high_reference_clock_rate(struct clk *clk) | 314 | static unsigned long get_rate_high_reference(struct clk *clk) |
| 455 | { | 315 | { |
| 456 | return external_high_reference; | 316 | return external_high_reference; |
| 457 | } | 317 | } |
| 458 | 318 | ||
| 459 | /* | ||
| 460 | * the high frequency external clock reference | ||
| 461 | * Default case is 26MHz. Could be changed at runtime | ||
| 462 | * with a call to change_external_high_reference() | ||
| 463 | */ | ||
| 464 | static struct clk ckih_clk = { | ||
| 465 | .name = "ckih", | ||
| 466 | .get_rate = get_high_reference_clock_rate, | ||
| 467 | }; | ||
| 468 | |||
| 469 | /* in Hz */ | 319 | /* in Hz */ |
| 470 | static unsigned long external_low_reference = 32768; | 320 | static unsigned long external_low_reference = 32768; |
| 471 | 321 | ||
| 472 | static unsigned long get_low_reference_clock_rate(struct clk *clk) | 322 | static unsigned long get_rate_low_reference(struct clk *clk) |
| 473 | { | 323 | { |
| 474 | return external_low_reference; | 324 | return external_low_reference; |
| 475 | } | 325 | } |
| 476 | 326 | ||
| 477 | /* | 327 | static unsigned long get_rate_fpm(struct clk *clk) |
| 478 | * the low frequency external clock reference | ||
| 479 | * Default case is 32.768kHz Could be changed at runtime | ||
| 480 | * with a call to change_external_low_reference() | ||
| 481 | */ | ||
| 482 | static struct clk ckil_clk = { | ||
| 483 | .name = "ckil", | ||
| 484 | .get_rate = get_low_reference_clock_rate, | ||
| 485 | }; | ||
| 486 | |||
| 487 | static unsigned long get_mpll_clk(struct clk *clk) | ||
| 488 | { | 328 | { |
| 489 | uint32_t reg; | 329 | return clk_get_rate(clk->parent) * 1024; |
| 490 | unsigned long ref_clk; | ||
| 491 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 492 | unsigned long long temp; | ||
| 493 | |||
| 494 | ref_clk = clk_get_rate(clk->parent); | ||
| 495 | |||
| 496 | reg = __raw_readl(CCM_MPCTL0); | ||
| 497 | pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; | ||
| 498 | mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; | ||
| 499 | mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; | ||
| 500 | mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; | ||
| 501 | |||
| 502 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 503 | temp = 2LL * ref_clk * mfn; | ||
| 504 | do_div(temp, mfd + 1); | ||
| 505 | temp = 2LL * ref_clk * mfi + temp; | ||
| 506 | do_div(temp, pdf + 1); | ||
| 507 | |||
| 508 | return (unsigned long)temp; | ||
| 509 | } | 330 | } |
| 510 | 331 | ||
| 511 | static struct clk mpll_clk = { | 332 | static unsigned long get_rate_mpll(struct clk *clk) |
| 512 | .name = "mpll", | 333 | { |
| 513 | .parent = &ckih_clk, | 334 | return mxc_decode_pll(__raw_readl(CCM_MPCTL0), |
| 514 | .get_rate = get_mpll_clk, | 335 | clk_get_rate(clk->parent)); |
| 515 | }; | 336 | } |
| 516 | 337 | ||
| 517 | static unsigned long _clk_mpll_main_get_rate(struct clk *clk) | 338 | static unsigned long get_rate_mpll_main(struct clk *clk) |
| 518 | { | 339 | { |
| 519 | unsigned long parent_rate; | 340 | unsigned long parent_rate; |
| 520 | 341 | ||
| 521 | parent_rate = clk_get_rate(clk->parent); | 342 | parent_rate = clk_get_rate(clk->parent); |
| 522 | 343 | ||
| 523 | /* i.MX27 TO2: | 344 | /* i.MX27 TO2: |
| 524 | * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2 | 345 | * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 |
| 525 | * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3 | 346 | * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 |
| 526 | */ | 347 | */ |
| 527 | |||
| 528 | if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) | 348 | if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) |
| 529 | return 2UL * parent_rate / 3UL; | 349 | return 2UL * parent_rate / 3UL; |
| 530 | 350 | ||
| 531 | return parent_rate; | 351 | return parent_rate; |
| 532 | } | 352 | } |
| 533 | 353 | ||
| 534 | static struct clk mpll_main_clk[] = { | 354 | static unsigned long get_rate_spll(struct clk *clk) |
| 535 | { | ||
| 536 | /* For i.MX27 TO2, it is the MPLL path 1 of ARM core | ||
| 537 | * It provide the clock source whose rate is same as MPLL | ||
| 538 | */ | ||
| 539 | .name = "mpll_main", | ||
| 540 | .id = 0, | ||
| 541 | .parent = &mpll_clk, | ||
| 542 | .get_rate = _clk_mpll_main_get_rate | ||
| 543 | }, { | ||
| 544 | /* For i.MX27 TO2, it is the MPLL path 2 of ARM core | ||
| 545 | * It provide the clock source whose rate is same MPLL * 2/3 | ||
| 546 | */ | ||
| 547 | .name = "mpll_main", | ||
| 548 | .id = 1, | ||
| 549 | .parent = &mpll_clk, | ||
| 550 | .get_rate = _clk_mpll_main_get_rate | ||
| 551 | } | ||
| 552 | }; | ||
| 553 | |||
| 554 | static unsigned long get_spll_clk(struct clk *clk) | ||
| 555 | { | 355 | { |
| 556 | uint32_t reg; | 356 | uint32_t reg; |
| 557 | unsigned long ref_clk; | 357 | unsigned long rate; |
| 558 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 559 | unsigned long long temp; | ||
| 560 | 358 | ||
| 561 | ref_clk = clk_get_rate(clk->parent); | 359 | rate = clk_get_rate(clk->parent); |
| 562 | 360 | ||
| 563 | reg = __raw_readl(CCM_SPCTL0); | 361 | reg = __raw_readl(CCM_SPCTL0); |
| 564 | /*TODO: This is TO2 Bug */ | 362 | |
| 363 | /* On TO2 we have to write the value back. Otherwise we | ||
| 364 | * read 0 from this register the next time. | ||
| 365 | */ | ||
| 565 | if (mx27_revision() >= CHIP_REV_2_0) | 366 | if (mx27_revision() >= CHIP_REV_2_0) |
| 566 | __raw_writel(reg, CCM_SPCTL0); | 367 | __raw_writel(reg, CCM_SPCTL0); |
| 567 | 368 | ||
| 568 | pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; | 369 | return mxc_decode_pll(reg, rate); |
| 569 | mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; | ||
| 570 | mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; | ||
| 571 | mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; | ||
| 572 | |||
| 573 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 574 | temp = 2LL * ref_clk * mfn; | ||
| 575 | do_div(temp, mfd + 1); | ||
| 576 | temp = 2LL * ref_clk * mfi + temp; | ||
| 577 | do_div(temp, pdf + 1); | ||
| 578 | |||
| 579 | return (unsigned long)temp; | ||
| 580 | } | 370 | } |
| 581 | 371 | ||
| 582 | static struct clk spll_clk = { | 372 | static unsigned long get_rate_cpu(struct clk *clk) |
| 583 | .name = "spll", | ||
| 584 | .parent = &ckih_clk, | ||
| 585 | .get_rate = get_spll_clk, | ||
| 586 | .enable = _clk_spll_enable, | ||
| 587 | .disable = _clk_spll_disable, | ||
| 588 | }; | ||
| 589 | |||
| 590 | static unsigned long get_cpu_clk(struct clk *clk) | ||
| 591 | { | 373 | { |
| 592 | u32 div; | 374 | u32 div; |
| 593 | unsigned long rate; | 375 | unsigned long rate; |
| 594 | 376 | ||
| 595 | if (mx27_revision() >= CHIP_REV_2_0) | 377 | if (mx27_revision() >= CHIP_REV_2_0) |
| 596 | div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET; | 378 | div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; |
| 597 | else | 379 | else |
| 598 | div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; | 380 | div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; |
| 599 | 381 | ||
| 600 | rate = clk_get_rate(clk->parent); | 382 | rate = clk_get_rate(clk->parent); |
| 601 | return rate / (div + 1); | 383 | return rate / (div + 1); |
| 602 | } | 384 | } |
| 603 | 385 | ||
| 604 | static struct clk cpu_clk = { | 386 | static unsigned long get_rate_ahb(struct clk *clk) |
| 605 | .name = "cpu_clk", | ||
| 606 | .parent = &mpll_main_clk[1], | ||
| 607 | .set_parent = _clk_cpu_set_parent, | ||
| 608 | .round_rate = _clk_cpu_round_rate, | ||
| 609 | .get_rate = get_cpu_clk, | ||
| 610 | .set_rate = _clk_cpu_set_rate, | ||
| 611 | }; | ||
| 612 | |||
| 613 | static unsigned long get_ahb_clk(struct clk *clk) | ||
| 614 | { | 387 | { |
| 615 | unsigned long rate; | 388 | unsigned long rate, bclk_pdf; |
| 616 | unsigned long bclk_pdf; | ||
| 617 | 389 | ||
| 618 | if (mx27_revision() >= CHIP_REV_2_0) | 390 | if (mx27_revision() >= CHIP_REV_2_0) |
| 619 | bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK) | 391 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; |
| 620 | >> CCM_CSCR_AHB_OFFSET; | ||
| 621 | else | 392 | else |
| 622 | bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) | 393 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; |
| 623 | >> CCM_CSCR_BCLK_OFFSET; | ||
| 624 | 394 | ||
| 625 | rate = clk_get_rate(clk->parent); | 395 | rate = clk_get_rate(clk->parent); |
| 626 | return rate / (bclk_pdf + 1); | 396 | return rate / (bclk_pdf + 1); |
| 627 | } | 397 | } |
| 628 | 398 | ||
| 629 | static struct clk ahb_clk = { | 399 | static unsigned long get_rate_ipg(struct clk *clk) |
| 630 | .name = "ahb_clk", | ||
| 631 | .parent = &mpll_main_clk[1], | ||
| 632 | .get_rate = get_ahb_clk, | ||
| 633 | }; | ||
| 634 | |||
| 635 | static unsigned long get_ipg_clk(struct clk *clk) | ||
| 636 | { | 400 | { |
| 637 | unsigned long rate; | 401 | unsigned long rate, ipg_pdf; |
| 638 | unsigned long ipg_pdf; | ||
| 639 | 402 | ||
| 640 | if (mx27_revision() >= CHIP_REV_2_0) | 403 | if (mx27_revision() >= CHIP_REV_2_0) |
| 641 | return clk_get_rate(clk->parent); | 404 | return clk_get_rate(clk->parent); |
| 642 | else | 405 | else |
| 643 | ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; | 406 | ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; |
| 644 | 407 | ||
| 645 | rate = clk_get_rate(clk->parent); | 408 | rate = clk_get_rate(clk->parent); |
| 646 | return rate / (ipg_pdf + 1); | 409 | return rate / (ipg_pdf + 1); |
| 647 | } | 410 | } |
| 648 | 411 | ||
| 649 | static struct clk ipg_clk = { | 412 | static unsigned long get_rate_per(struct clk *clk) |
| 650 | .name = "ipg_clk", | ||
| 651 | .parent = &ahb_clk, | ||
| 652 | .get_rate = get_ipg_clk, | ||
| 653 | }; | ||
| 654 | |||
| 655 | static unsigned long _clk_perclkx_recalc(struct clk *clk) | ||
| 656 | { | 413 | { |
| 657 | unsigned long perclk_pdf; | 414 | unsigned long perclk_pdf, parent_rate; |
| 658 | unsigned long parent_rate; | ||
| 659 | 415 | ||
| 660 | parent_rate = clk_get_rate(clk->parent); | 416 | parent_rate = clk_get_rate(clk->parent); |
| 661 | 417 | ||
| 662 | if (clk->id < 0 || clk->id > 3) | 418 | if (clk->id < 0 || clk->id > 3) |
| 663 | return 0; | 419 | return 0; |
| 664 | 420 | ||
| 665 | perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; | 421 | perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f; |
| 666 | 422 | ||
| 667 | return parent_rate / (perclk_pdf + 1); | 423 | return parent_rate / (perclk_pdf + 1); |
| 668 | } | 424 | } |
| 669 | 425 | ||
| 670 | static struct clk per_clk[] = { | 426 | /* |
| 671 | { | 427 | * the high frequency external clock reference |
| 672 | .name = "per_clk", | 428 | * Default case is 26MHz. Could be changed at runtime |
| 673 | .id = 0, | 429 | * with a call to change_external_high_reference() |
| 674 | .parent = &mpll_main_clk[1], | 430 | */ |
| 675 | .get_rate = _clk_perclkx_recalc, | 431 | static struct clk ckih_clk = { |
| 676 | .enable = _clk_enable, | 432 | .get_rate = get_rate_high_reference, |
| 677 | .enable_reg = CCM_PCCR1, | ||
| 678 | .enable_shift = CCM_PCCR1_PERCLK1_OFFSET, | ||
| 679 | .disable = _clk_disable, | ||
| 680 | }, { | ||
| 681 | .name = "per_clk", | ||
| 682 | .id = 1, | ||
| 683 | .parent = &mpll_main_clk[1], | ||
| 684 | .get_rate = _clk_perclkx_recalc, | ||
| 685 | .enable = _clk_enable, | ||
| 686 | .enable_reg = CCM_PCCR1, | ||
| 687 | .enable_shift = CCM_PCCR1_PERCLK2_OFFSET, | ||
| 688 | .disable = _clk_disable, | ||
| 689 | }, { | ||
| 690 | .name = "per_clk", | ||
| 691 | .id = 2, | ||
| 692 | .parent = &mpll_main_clk[1], | ||
| 693 | .round_rate = _clk_perclkx_round_rate, | ||
| 694 | .set_rate = _clk_perclkx_set_rate, | ||
| 695 | .get_rate = _clk_perclkx_recalc, | ||
| 696 | .enable = _clk_enable, | ||
| 697 | .enable_reg = CCM_PCCR1, | ||
| 698 | .enable_shift = CCM_PCCR1_PERCLK3_OFFSET, | ||
| 699 | .disable = _clk_disable, | ||
| 700 | }, { | ||
| 701 | .name = "per_clk", | ||
| 702 | .id = 3, | ||
| 703 | .parent = &mpll_main_clk[1], | ||
| 704 | .round_rate = _clk_perclkx_round_rate, | ||
| 705 | .set_rate = _clk_perclkx_set_rate, | ||
| 706 | .get_rate = _clk_perclkx_recalc, | ||
| 707 | .enable = _clk_enable, | ||
| 708 | .enable_reg = CCM_PCCR1, | ||
| 709 | .enable_shift = CCM_PCCR1_PERCLK4_OFFSET, | ||
| 710 | .disable = _clk_disable, | ||
| 711 | }, | ||
| 712 | }; | ||
| 713 | |||
| 714 | struct clk uart1_clk[] = { | ||
| 715 | { | ||
| 716 | .name = "uart_clk", | ||
| 717 | .id = 0, | ||
| 718 | .parent = &per_clk[0], | ||
| 719 | .secondary = &uart1_clk[1], | ||
| 720 | }, { | ||
| 721 | .name = "uart_ipg_clk", | ||
| 722 | .id = 0, | ||
| 723 | .parent = &ipg_clk, | ||
| 724 | .enable = _clk_enable, | ||
| 725 | .enable_reg = CCM_PCCR1, | ||
| 726 | .enable_shift = CCM_PCCR1_UART1_OFFSET, | ||
| 727 | .disable = _clk_disable, | ||
| 728 | }, | ||
| 729 | }; | ||
| 730 | |||
| 731 | struct clk uart2_clk[] = { | ||
| 732 | { | ||
| 733 | .name = "uart_clk", | ||
| 734 | .id = 1, | ||
| 735 | .parent = &per_clk[0], | ||
| 736 | .secondary = &uart2_clk[1], | ||
| 737 | }, { | ||
| 738 | .name = "uart_ipg_clk", | ||
| 739 | .id = 1, | ||
| 740 | .parent = &ipg_clk, | ||
| 741 | .enable = _clk_enable, | ||
| 742 | .enable_reg = CCM_PCCR1, | ||
| 743 | .enable_shift = CCM_PCCR1_UART2_OFFSET, | ||
| 744 | .disable = _clk_disable, | ||
| 745 | }, | ||
| 746 | }; | ||
| 747 | |||
| 748 | struct clk uart3_clk[] = { | ||
| 749 | { | ||
| 750 | .name = "uart_clk", | ||
| 751 | .id = 2, | ||
| 752 | .parent = &per_clk[0], | ||
| 753 | .secondary = &uart3_clk[1], | ||
| 754 | }, { | ||
| 755 | .name = "uart_ipg_clk", | ||
| 756 | .id = 2, | ||
| 757 | .parent = &ipg_clk, | ||
| 758 | .enable = _clk_enable, | ||
| 759 | .enable_reg = CCM_PCCR1, | ||
| 760 | .enable_shift = CCM_PCCR1_UART3_OFFSET, | ||
| 761 | .disable = _clk_disable, | ||
| 762 | }, | ||
| 763 | }; | ||
| 764 | |||
| 765 | struct clk uart4_clk[] = { | ||
| 766 | { | ||
| 767 | .name = "uart_clk", | ||
| 768 | .id = 3, | ||
| 769 | .parent = &per_clk[0], | ||
| 770 | .secondary = &uart4_clk[1], | ||
| 771 | }, { | ||
| 772 | .name = "uart_ipg_clk", | ||
| 773 | .id = 3, | ||
| 774 | .parent = &ipg_clk, | ||
| 775 | .enable = _clk_enable, | ||
| 776 | .enable_reg = CCM_PCCR1, | ||
| 777 | .enable_shift = CCM_PCCR1_UART4_OFFSET, | ||
| 778 | .disable = _clk_disable, | ||
| 779 | }, | ||
| 780 | }; | ||
| 781 | |||
| 782 | struct clk uart5_clk[] = { | ||
| 783 | { | ||
| 784 | .name = "uart_clk", | ||
| 785 | .id = 4, | ||
| 786 | .parent = &per_clk[0], | ||
| 787 | .secondary = &uart5_clk[1], | ||
| 788 | }, { | ||
| 789 | .name = "uart_ipg_clk", | ||
| 790 | .id = 4, | ||
| 791 | .parent = &ipg_clk, | ||
| 792 | .enable = _clk_enable, | ||
| 793 | .enable_reg = CCM_PCCR1, | ||
| 794 | .enable_shift = CCM_PCCR1_UART5_OFFSET, | ||
| 795 | .disable = _clk_disable, | ||
| 796 | }, | ||
| 797 | }; | ||
| 798 | |||
| 799 | struct clk uart6_clk[] = { | ||
| 800 | { | ||
| 801 | .name = "uart_clk", | ||
| 802 | .id = 5, | ||
| 803 | .parent = &per_clk[0], | ||
| 804 | .secondary = &uart6_clk[1], | ||
| 805 | }, { | ||
| 806 | .name = "uart_ipg_clk", | ||
| 807 | .id = 5, | ||
| 808 | .parent = &ipg_clk, | ||
| 809 | .enable = _clk_enable, | ||
| 810 | .enable_reg = CCM_PCCR1, | ||
| 811 | .enable_shift = CCM_PCCR1_UART6_OFFSET, | ||
| 812 | .disable = _clk_disable, | ||
| 813 | }, | ||
| 814 | }; | ||
| 815 | |||
| 816 | static struct clk gpt1_clk[] = { | ||
| 817 | { | ||
| 818 | .name = "gpt_clk", | ||
| 819 | .id = 0, | ||
| 820 | .parent = &per_clk[0], | ||
| 821 | .secondary = &gpt1_clk[1], | ||
| 822 | }, { | ||
| 823 | .name = "gpt_ipg_clk", | ||
| 824 | .id = 0, | ||
| 825 | .parent = &ipg_clk, | ||
| 826 | .enable = _clk_enable, | ||
| 827 | .enable_reg = CCM_PCCR0, | ||
| 828 | .enable_shift = CCM_PCCR0_GPT1_OFFSET, | ||
| 829 | .disable = _clk_disable, | ||
| 830 | }, | ||
| 831 | }; | ||
| 832 | |||
| 833 | static struct clk gpt2_clk[] = { | ||
| 834 | { | ||
| 835 | .name = "gpt_clk", | ||
| 836 | .id = 1, | ||
| 837 | .parent = &per_clk[0], | ||
| 838 | .secondary = &gpt2_clk[1], | ||
| 839 | }, { | ||
| 840 | .name = "gpt_ipg_clk", | ||
| 841 | .id = 1, | ||
| 842 | .parent = &ipg_clk, | ||
| 843 | .enable = _clk_enable, | ||
| 844 | .enable_reg = CCM_PCCR0, | ||
| 845 | .enable_shift = CCM_PCCR0_GPT2_OFFSET, | ||
| 846 | .disable = _clk_disable, | ||
| 847 | }, | ||
| 848 | }; | ||
| 849 | |||
| 850 | static struct clk gpt3_clk[] = { | ||
| 851 | { | ||
| 852 | .name = "gpt_clk", | ||
| 853 | .id = 2, | ||
| 854 | .parent = &per_clk[0], | ||
| 855 | .secondary = &gpt3_clk[1], | ||
| 856 | }, { | ||
| 857 | .name = "gpt_ipg_clk", | ||
| 858 | .id = 2, | ||
| 859 | .parent = &ipg_clk, | ||
| 860 | .enable = _clk_enable, | ||
| 861 | .enable_reg = CCM_PCCR0, | ||
| 862 | .enable_shift = CCM_PCCR0_GPT3_OFFSET, | ||
| 863 | .disable = _clk_disable, | ||
| 864 | }, | ||
| 865 | }; | ||
| 866 | |||
| 867 | static struct clk gpt4_clk[] = { | ||
| 868 | { | ||
| 869 | .name = "gpt_clk", | ||
| 870 | .id = 3, | ||
| 871 | .parent = &per_clk[0], | ||
| 872 | .secondary = &gpt4_clk[1], | ||
| 873 | }, { | ||
| 874 | .name = "gpt_ipg_clk", | ||
| 875 | .id = 3, | ||
| 876 | .parent = &ipg_clk, | ||
| 877 | .enable = _clk_enable, | ||
| 878 | .enable_reg = CCM_PCCR0, | ||
| 879 | .enable_shift = CCM_PCCR0_GPT4_OFFSET, | ||
| 880 | .disable = _clk_disable, | ||
| 881 | }, | ||
| 882 | }; | ||
| 883 | |||
| 884 | static struct clk gpt5_clk[] = { | ||
| 885 | { | ||
| 886 | .name = "gpt_clk", | ||
| 887 | .id = 4, | ||
| 888 | .parent = &per_clk[0], | ||
| 889 | .secondary = &gpt5_clk[1], | ||
| 890 | }, { | ||
| 891 | .name = "gpt_ipg_clk", | ||
| 892 | .id = 4, | ||
| 893 | .parent = &ipg_clk, | ||
| 894 | .enable = _clk_enable, | ||
| 895 | .enable_reg = CCM_PCCR0, | ||
| 896 | .enable_shift = CCM_PCCR0_GPT5_OFFSET, | ||
| 897 | .disable = _clk_disable, | ||
| 898 | }, | ||
| 899 | }; | 433 | }; |
| 900 | 434 | ||
| 901 | static struct clk gpt6_clk[] = { | 435 | static struct clk mpll_clk = { |
| 902 | { | 436 | .parent = &ckih_clk, |
| 903 | .name = "gpt_clk", | 437 | .get_rate = get_rate_mpll, |
| 904 | .id = 5, | ||
| 905 | .parent = &per_clk[0], | ||
| 906 | .secondary = &gpt6_clk[1], | ||
| 907 | }, { | ||
| 908 | .name = "gpt_ipg_clk", | ||
| 909 | .id = 5, | ||
| 910 | .parent = &ipg_clk, | ||
| 911 | .enable = _clk_enable, | ||
| 912 | .enable_reg = CCM_PCCR0, | ||
| 913 | .enable_shift = CCM_PCCR0_GPT6_OFFSET, | ||
| 914 | .disable = _clk_disable, | ||
| 915 | }, | ||
| 916 | }; | 438 | }; |
| 917 | 439 | ||
| 918 | static struct clk pwm_clk[] = { | 440 | /* For i.MX27 TO2, it is the MPLL path 1 of ARM core |
| 919 | { | 441 | * It provides the clock source whose rate is same as MPLL |
| 920 | .name = "pwm_clk", | 442 | */ |
| 921 | .parent = &per_clk[0], | 443 | static struct clk mpll_main1_clk = { |
| 922 | .secondary = &pwm_clk[1], | 444 | .id = 0, |
| 923 | }, { | 445 | .parent = &mpll_clk, |
| 924 | .name = "pwm_clk", | 446 | .get_rate = get_rate_mpll_main, |
| 925 | .parent = &ipg_clk, | ||
| 926 | .enable = _clk_enable, | ||
| 927 | .enable_reg = CCM_PCCR0, | ||
| 928 | .enable_shift = CCM_PCCR0_PWM_OFFSET, | ||
| 929 | .disable = _clk_disable, | ||
| 930 | }, | ||
| 931 | }; | 447 | }; |
| 932 | 448 | ||
| 933 | static struct clk sdhc1_clk[] = { | 449 | /* For i.MX27 TO2, it is the MPLL path 2 of ARM core |
| 934 | { | 450 | * It provides the clock source whose rate is same MPLL * 2 / 3 |
| 935 | .name = "sdhc_clk", | 451 | */ |
| 936 | .id = 0, | 452 | static struct clk mpll_main2_clk = { |
| 937 | .parent = &per_clk[1], | 453 | .id = 1, |
| 938 | .secondary = &sdhc1_clk[1], | 454 | .parent = &mpll_clk, |
| 939 | }, { | 455 | .get_rate = get_rate_mpll_main, |
| 940 | .name = "sdhc_ipg_clk", | ||
| 941 | .id = 0, | ||
| 942 | .parent = &ipg_clk, | ||
| 943 | .enable = _clk_enable, | ||
| 944 | .enable_reg = CCM_PCCR0, | ||
| 945 | .enable_shift = CCM_PCCR0_SDHC1_OFFSET, | ||
| 946 | .disable = _clk_disable, | ||
| 947 | }, | ||
| 948 | }; | 456 | }; |
| 949 | 457 | ||
| 950 | static struct clk sdhc2_clk[] = { | 458 | static struct clk ahb_clk = { |
| 951 | { | 459 | .parent = &mpll_main2_clk, |
| 952 | .name = "sdhc_clk", | 460 | .get_rate = get_rate_ahb, |
| 953 | .id = 1, | ||
| 954 | .parent = &per_clk[1], | ||
| 955 | .secondary = &sdhc2_clk[1], | ||
| 956 | }, { | ||
| 957 | .name = "sdhc_ipg_clk", | ||
| 958 | .id = 1, | ||
| 959 | .parent = &ipg_clk, | ||
| 960 | .enable = _clk_enable, | ||
| 961 | .enable_reg = CCM_PCCR0, | ||
| 962 | .enable_shift = CCM_PCCR0_SDHC2_OFFSET, | ||
| 963 | .disable = _clk_disable, | ||
| 964 | }, | ||
| 965 | }; | 461 | }; |
| 966 | 462 | ||
| 967 | static struct clk sdhc3_clk[] = { | 463 | static struct clk ipg_clk = { |
| 968 | { | 464 | .parent = &ahb_clk, |
| 969 | .name = "sdhc_clk", | 465 | .get_rate = get_rate_ipg, |
| 970 | .id = 2, | ||
| 971 | .parent = &per_clk[1], | ||
| 972 | .secondary = &sdhc3_clk[1], | ||
| 973 | }, { | ||
| 974 | .name = "sdhc_ipg_clk", | ||
| 975 | .id = 2, | ||
| 976 | .parent = &ipg_clk, | ||
| 977 | .enable = _clk_enable, | ||
| 978 | .enable_reg = CCM_PCCR0, | ||
| 979 | .enable_shift = CCM_PCCR0_SDHC3_OFFSET, | ||
| 980 | .disable = _clk_disable, | ||
| 981 | }, | ||
| 982 | }; | 466 | }; |
| 983 | 467 | ||
| 984 | static struct clk cspi1_clk[] = { | 468 | static struct clk cpu_clk = { |
| 985 | { | 469 | .parent = &mpll_main2_clk, |
| 986 | .name = "cspi_clk", | 470 | .set_parent = clk_cpu_set_parent, |
| 987 | .id = 0, | 471 | .round_rate = round_rate_cpu, |
| 988 | .parent = &per_clk[1], | 472 | .get_rate = get_rate_cpu, |
| 989 | .secondary = &cspi1_clk[1], | 473 | .set_rate = set_rate_cpu, |
| 990 | }, { | ||
| 991 | .name = "cspi_ipg_clk", | ||
| 992 | .id = 0, | ||
| 993 | .parent = &ipg_clk, | ||
| 994 | .enable = _clk_enable, | ||
| 995 | .enable_reg = CCM_PCCR0, | ||
| 996 | .enable_shift = CCM_PCCR0_CSPI1_OFFSET, | ||
| 997 | .disable = _clk_disable, | ||
| 998 | }, | ||
| 999 | }; | 474 | }; |
| 1000 | 475 | ||
| 1001 | static struct clk cspi2_clk[] = { | 476 | static struct clk spll_clk = { |
| 1002 | { | 477 | .parent = &ckih_clk, |
| 1003 | .name = "cspi_clk", | 478 | .get_rate = get_rate_spll, |
| 1004 | .id = 1, | 479 | .enable = clk_spll_enable, |
| 1005 | .parent = &per_clk[1], | 480 | .disable = clk_spll_disable, |
| 1006 | .secondary = &cspi2_clk[1], | ||
| 1007 | }, { | ||
| 1008 | .name = "cspi_ipg_clk", | ||
| 1009 | .id = 1, | ||
| 1010 | .parent = &ipg_clk, | ||
| 1011 | .enable = _clk_enable, | ||
| 1012 | .enable_reg = CCM_PCCR0, | ||
| 1013 | .enable_shift = CCM_PCCR0_CSPI2_OFFSET, | ||
| 1014 | .disable = _clk_disable, | ||
| 1015 | }, | ||
| 1016 | }; | 481 | }; |
| 1017 | 482 | ||
| 1018 | static struct clk cspi3_clk[] = { | 483 | /* |
| 1019 | { | 484 | * the low frequency external clock reference |
| 1020 | .name = "cspi_clk", | 485 | * Default case is 32.768kHz. |
| 1021 | .id = 2, | 486 | */ |
| 1022 | .parent = &per_clk[1], | 487 | static struct clk ckil_clk = { |
| 1023 | .secondary = &cspi3_clk[1], | 488 | .get_rate = get_rate_low_reference, |
| 1024 | }, { | ||
| 1025 | .name = "cspi_ipg_clk", | ||
| 1026 | .id = 2, | ||
| 1027 | .parent = &ipg_clk, | ||
| 1028 | .enable = _clk_enable, | ||
| 1029 | .enable_reg = CCM_PCCR0, | ||
| 1030 | .enable_shift = CCM_PCCR0_CSPI3_OFFSET, | ||
| 1031 | .disable = _clk_disable, | ||
| 1032 | }, | ||
| 1033 | }; | 489 | }; |
| 1034 | 490 | ||
| 1035 | static struct clk lcdc_clk[] = { | 491 | /* Output of frequency pre multiplier */ |
| 1036 | { | 492 | static struct clk fpm_clk = { |
| 1037 | .name = "lcdc_clk", | 493 | .parent = &ckil_clk, |
| 1038 | .parent = &per_clk[2], | 494 | .get_rate = get_rate_fpm, |
| 1039 | .secondary = &lcdc_clk[1], | ||
| 1040 | .round_rate = _clk_parent_round_rate, | ||
| 1041 | .set_rate = _clk_parent_set_rate, | ||
| 1042 | }, { | ||
| 1043 | .name = "lcdc_ipg_clk", | ||
| 1044 | .parent = &ipg_clk, | ||
| 1045 | .secondary = &lcdc_clk[2], | ||
| 1046 | .enable = _clk_enable, | ||
| 1047 | .enable_reg = CCM_PCCR0, | ||
| 1048 | .enable_shift = CCM_PCCR0_LCDC_OFFSET, | ||
| 1049 | .disable = _clk_disable, | ||
| 1050 | }, { | ||
| 1051 | .name = "lcdc_ahb_clk", | ||
| 1052 | .parent = &ahb_clk, | ||
| 1053 | .enable = _clk_enable, | ||
| 1054 | .enable_reg = CCM_PCCR1, | ||
| 1055 | .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET, | ||
| 1056 | .disable = _clk_disable, | ||
| 1057 | }, | ||
| 1058 | }; | 495 | }; |
| 1059 | 496 | ||
| 1060 | static struct clk csi_clk[] = { | 497 | #define PCCR0 CCM_PCCR0 |
| 1061 | { | 498 | #define PCCR1 CCM_PCCR1 |
| 1062 | .name = "csi_perclk", | ||
| 1063 | .parent = &per_clk[3], | ||
| 1064 | .secondary = &csi_clk[1], | ||
| 1065 | .round_rate = _clk_parent_round_rate, | ||
| 1066 | .set_rate = _clk_parent_set_rate, | ||
| 1067 | }, { | ||
| 1068 | .name = "csi_ahb_clk", | ||
| 1069 | .parent = &ahb_clk, | ||
| 1070 | .enable = _clk_enable, | ||
| 1071 | .enable_reg = CCM_PCCR1, | ||
| 1072 | .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET, | ||
| 1073 | .disable = _clk_disable, | ||
| 1074 | }, | ||
| 1075 | }; | ||
| 1076 | 499 | ||
| 1077 | static struct clk usb_clk[] = { | 500 | #define DEFINE_CLOCK(name, i, er, es, gr, s, p) \ |
| 1078 | { | 501 | static struct clk name = { \ |
| 1079 | .name = "usb_clk", | 502 | .id = i, \ |
| 1080 | .parent = &spll_clk, | 503 | .enable_reg = er, \ |
| 1081 | .get_rate = _clk_usb_recalc, | 504 | .enable_shift = es, \ |
| 1082 | .enable = _clk_enable, | 505 | .get_rate = gr, \ |
| 1083 | .enable_reg = CCM_PCCR1, | 506 | .enable = clk_pccr_enable, \ |
| 1084 | .enable_shift = CCM_PCCR1_USBOTG_OFFSET, | 507 | .disable = clk_pccr_disable, \ |
| 1085 | .disable = _clk_disable, | 508 | .secondary = s, \ |
| 1086 | }, { | 509 | .parent = p, \ |
| 1087 | .name = "usb_ahb_clk", | ||
| 1088 | .parent = &ahb_clk, | ||
| 1089 | .enable = _clk_enable, | ||
| 1090 | .enable_reg = CCM_PCCR1, | ||
| 1091 | .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET, | ||
| 1092 | .disable = _clk_disable, | ||
| 1093 | } | 510 | } |
| 1094 | }; | ||
| 1095 | 511 | ||
| 1096 | static struct clk ssi1_clk[] = { | 512 | #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \ |
| 1097 | { | 513 | static struct clk name = { \ |
| 1098 | .name = "ssi_clk", | 514 | .id = i, \ |
| 1099 | .id = 0, | 515 | .enable_reg = er, \ |
| 1100 | .parent = &mpll_main_clk[1], | 516 | .enable_shift = es, \ |
| 1101 | .secondary = &ssi1_clk[1], | 517 | .get_rate = get_rate_##getsetround, \ |
| 1102 | .get_rate = _clk_ssi1_recalc, | 518 | .set_rate = set_rate_##getsetround, \ |
| 1103 | .enable = _clk_enable, | 519 | .round_rate = round_rate_##getsetround, \ |
| 1104 | .enable_reg = CCM_PCCR1, | 520 | .enable = clk_pccr_enable, \ |
| 1105 | .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET, | 521 | .disable = clk_pccr_disable, \ |
| 1106 | .disable = _clk_disable, | 522 | .secondary = s, \ |
| 1107 | }, { | 523 | .parent = p, \ |
| 1108 | .name = "ssi_ipg_clk", | 524 | } |
| 1109 | .id = 0, | ||
| 1110 | .parent = &ipg_clk, | ||
| 1111 | .enable = _clk_enable, | ||
| 1112 | .enable_reg = CCM_PCCR0, | ||
| 1113 | .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET, | ||
| 1114 | .disable = _clk_disable, | ||
| 1115 | }, | ||
| 1116 | }; | ||
| 1117 | 525 | ||
| 1118 | static struct clk ssi2_clk[] = { | 526 | /* Forward declaration to keep the following list in order */ |
| 1119 | { | 527 | static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1, |
| 1120 | .name = "ssi_clk", | 528 | dma_clk1, lcdc_clk2, vpu_clk1; |
| 1121 | .id = 1, | 529 | |
| 1122 | .parent = &mpll_main_clk[1], | 530 | /* All clocks we can gate through PCCRx in the order of PCCRx bits */ |
| 1123 | .secondary = &ssi2_clk[1], | 531 | DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk); |
| 1124 | .get_rate = _clk_ssi2_recalc, | 532 | DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk); |
| 1125 | .enable = _clk_enable, | 533 | DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk); |
| 1126 | .enable_reg = CCM_PCCR1, | 534 | DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk); |
| 1127 | .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET, | 535 | DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk); |
| 1128 | .disable = _clk_disable, | 536 | DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk); |
| 1129 | }, { | 537 | DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk); |
| 1130 | .name = "ssi_ipg_clk", | 538 | DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk); |
| 1131 | .id = 1, | 539 | DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk); |
| 1132 | .parent = &ipg_clk, | 540 | DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk); |
| 1133 | .enable = _clk_enable, | 541 | DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk); |
| 1134 | .enable_reg = CCM_PCCR0, | 542 | DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk); |
| 1135 | .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET, | 543 | DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk); |
| 1136 | .disable = _clk_disable, | 544 | DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk); |
| 545 | DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk); | ||
| 546 | DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk); | ||
| 547 | DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk); | ||
| 548 | DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk); | ||
| 549 | DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); | ||
| 550 | DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk); | ||
| 551 | DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk); | ||
| 552 | DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk); | ||
| 553 | DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk); | ||
| 554 | DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk); | ||
| 555 | DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk); | ||
| 556 | DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk); | ||
| 557 | DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk); | ||
| 558 | DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk); | ||
| 559 | DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); | ||
| 560 | DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk); | ||
| 561 | DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk); | ||
| 562 | |||
| 563 | DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk); | ||
| 564 | DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk); | ||
| 565 | DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk); | ||
| 566 | DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk); | ||
| 567 | DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk); | ||
| 568 | DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk); | ||
| 569 | DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk); | ||
| 570 | DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk); | ||
| 571 | DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk); | ||
| 572 | DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk); | ||
| 573 | DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk); | ||
| 574 | DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk); | ||
| 575 | DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk); | ||
| 576 | DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk); | ||
| 577 | DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk); | ||
| 578 | DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk); | ||
| 579 | DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk); | ||
| 580 | DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk); | ||
| 581 | DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk); | ||
| 582 | DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk); | ||
| 583 | DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk); | ||
| 584 | DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); | ||
| 585 | DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk); | ||
| 586 | DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk); | ||
| 587 | DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk); | ||
| 588 | DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk); | ||
| 589 | DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk); | ||
| 590 | DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk); | ||
| 591 | DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk); | ||
| 592 | DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk); | ||
| 593 | |||
| 594 | /* Clocks we cannot directly gate, but drivers need their rates */ | ||
| 595 | DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk); | ||
| 596 | DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk); | ||
| 597 | DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk); | ||
| 598 | DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk); | ||
| 599 | DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk); | ||
| 600 | DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk); | ||
| 601 | DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk); | ||
| 602 | DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk); | ||
| 603 | DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk); | ||
| 604 | DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk); | ||
| 605 | DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk); | ||
| 606 | DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk); | ||
| 607 | DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk); | ||
| 608 | DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk); | ||
| 609 | DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk); | ||
| 610 | DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk); | ||
| 611 | DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk); | ||
| 612 | DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk); | ||
| 613 | DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk); | ||
| 614 | DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk); | ||
| 615 | DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); | ||
| 616 | |||
| 617 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 618 | { \ | ||
| 619 | .dev_id = d, \ | ||
| 620 | .con_id = n, \ | ||
| 621 | .clk = &c, \ | ||
| 1137 | }, | 622 | }, |
| 1138 | }; | ||
| 1139 | |||
| 1140 | static struct clk nfc_clk = { | ||
| 1141 | .name = "nfc_clk", | ||
| 1142 | .parent = &cpu_clk, | ||
| 1143 | .get_rate = _clk_nfc_recalc, | ||
| 1144 | .enable = _clk_enable, | ||
| 1145 | .enable_reg = CCM_PCCR1, | ||
| 1146 | .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET, | ||
| 1147 | .disable = _clk_disable, | ||
| 1148 | }; | ||
| 1149 | |||
| 1150 | static struct clk vpu_clk = { | ||
| 1151 | .name = "vpu_clk", | ||
| 1152 | .parent = &mpll_main_clk[1], | ||
| 1153 | .get_rate = _clk_vpu_recalc, | ||
| 1154 | .enable = _clk_vpu_enable, | ||
| 1155 | .disable = _clk_vpu_disable, | ||
| 1156 | }; | ||
| 1157 | |||
| 1158 | static struct clk dma_clk = { | ||
| 1159 | .name = "dma_clk", | ||
| 1160 | .parent = &ahb_clk, | ||
| 1161 | .enable = _clk_dma_enable, | ||
| 1162 | .disable = _clk_dma_disable, | ||
| 1163 | }; | ||
| 1164 | |||
| 1165 | static struct clk rtic_clk = { | ||
| 1166 | .name = "rtic_clk", | ||
| 1167 | .parent = &ahb_clk, | ||
| 1168 | .enable = _clk_rtic_enable, | ||
| 1169 | .disable = _clk_rtic_disable, | ||
| 1170 | }; | ||
| 1171 | 623 | ||
| 1172 | static struct clk brom_clk = { | 624 | static struct clk_lookup lookups[] __initdata = { |
| 1173 | .name = "brom_clk", | 625 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 1174 | .parent = &ahb_clk, | 626 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 1175 | .enable = _clk_enable, | 627 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| 1176 | .enable_reg = CCM_PCCR1, | 628 | _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) |
| 1177 | .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET, | 629 | _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) |
| 1178 | .disable = _clk_disable, | 630 | _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk) |
| 1179 | }; | 631 | _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk) |
| 1180 | 632 | _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk) | |
| 1181 | static struct clk emma_clk = { | 633 | _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk) |
| 1182 | .name = "emma_clk", | 634 | _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk) |
| 1183 | .parent = &ahb_clk, | 635 | _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk) |
| 1184 | .enable = _clk_emma_enable, | 636 | _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk) |
| 1185 | .disable = _clk_emma_disable, | 637 | _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk) |
| 1186 | }; | 638 | _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) |
| 1187 | 639 | _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) | |
| 1188 | static struct clk slcdc_clk = { | 640 | _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk) |
| 1189 | .name = "slcdc_clk", | 641 | _REGISTER_CLOCK(NULL, "cspi1", cspi1_clk) |
| 1190 | .parent = &ahb_clk, | 642 | _REGISTER_CLOCK(NULL, "cspi2", cspi2_clk) |
| 1191 | .enable = _clk_slcdc_enable, | 643 | _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk) |
| 1192 | .disable = _clk_slcdc_disable, | 644 | _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) |
| 1193 | }; | 645 | _REGISTER_CLOCK(NULL, "csi", csi_clk) |
| 1194 | 646 | _REGISTER_CLOCK(NULL, "usb", usb_clk) | |
| 1195 | static struct clk fec_clk = { | 647 | _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk) |
| 1196 | .name = "fec_clk", | 648 | _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk) |
| 1197 | .parent = &ahb_clk, | 649 | _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) |
| 1198 | .enable = _clk_fec_enable, | 650 | _REGISTER_CLOCK(NULL, "vpu", vpu_clk) |
| 1199 | .disable = _clk_fec_disable, | 651 | _REGISTER_CLOCK(NULL, "dma", dma_clk) |
| 1200 | }; | 652 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) |
| 1201 | 653 | _REGISTER_CLOCK(NULL, "brom", brom_clk) | |
| 1202 | static struct clk emi_clk = { | 654 | _REGISTER_CLOCK(NULL, "emma", emma_clk) |
| 1203 | .name = "emi_clk", | 655 | _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk) |
| 1204 | .parent = &ahb_clk, | 656 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
| 1205 | .enable = _clk_enable, | 657 | _REGISTER_CLOCK(NULL, "emi", emi_clk) |
| 1206 | .enable_reg = CCM_PCCR1, | 658 | _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) |
| 1207 | .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET, | 659 | _REGISTER_CLOCK(NULL, "ata", ata_clk) |
| 1208 | .disable = _clk_disable, | 660 | _REGISTER_CLOCK(NULL, "mstick", mstick_clk) |
| 1209 | }; | 661 | _REGISTER_CLOCK(NULL, "wdog", wdog_clk) |
| 1210 | 662 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) | |
| 1211 | static struct clk sahara2_clk = { | 663 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
| 1212 | .name = "sahara_clk", | 664 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
| 1213 | .parent = &ahb_clk, | 665 | _REGISTER_CLOCK(NULL, "iim", iim_clk) |
| 1214 | .enable = _clk_sahara2_enable, | 666 | _REGISTER_CLOCK(NULL, "kpp", kpp_clk) |
| 1215 | .disable = _clk_sahara2_disable, | 667 | _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) |
| 1216 | }; | 668 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) |
| 1217 | 669 | _REGISTER_CLOCK(NULL, "scc", scc_clk) | |
| 1218 | static struct clk ata_clk = { | 670 | }; |
| 1219 | .name = "ata_clk", | 671 | |
| 1220 | .parent = &ahb_clk, | 672 | /* Adjust the clock path for TO2 and later */ |
| 1221 | .enable = _clk_enable, | 673 | static void __init to2_adjust_clocks(void) |
| 1222 | .enable_reg = CCM_PCCR1, | 674 | { |
| 1223 | .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET, | 675 | unsigned long cscr = __raw_readl(CCM_CSCR); |
| 1224 | .disable = _clk_disable, | ||
| 1225 | }; | ||
| 1226 | |||
| 1227 | static struct clk mstick1_clk = { | ||
| 1228 | .name = "mstick1_clk", | ||
| 1229 | .parent = &ipg_clk, | ||
| 1230 | .enable = _clk_mstick1_enable, | ||
| 1231 | .disable = _clk_mstick1_disable, | ||
| 1232 | }; | ||
| 1233 | |||
| 1234 | static struct clk wdog_clk = { | ||
| 1235 | .name = "wdog_clk", | ||
| 1236 | .parent = &ipg_clk, | ||
| 1237 | .enable = _clk_enable, | ||
| 1238 | .enable_reg = CCM_PCCR1, | ||
| 1239 | .enable_shift = CCM_PCCR1_WDT_OFFSET, | ||
| 1240 | .disable = _clk_disable, | ||
| 1241 | }; | ||
| 1242 | |||
| 1243 | static struct clk gpio_clk = { | ||
| 1244 | .name = "gpio_clk", | ||
| 1245 | .parent = &ipg_clk, | ||
| 1246 | .enable = _clk_enable, | ||
| 1247 | .enable_reg = CCM_PCCR1, | ||
| 1248 | .enable_shift = CCM_PCCR0_GPIO_OFFSET, | ||
| 1249 | .disable = _clk_disable, | ||
| 1250 | }; | ||
| 1251 | |||
| 1252 | static struct clk i2c_clk[] = { | ||
| 1253 | { | ||
| 1254 | .name = "i2c_clk", | ||
| 1255 | .id = 0, | ||
| 1256 | .parent = &ipg_clk, | ||
| 1257 | .enable = _clk_enable, | ||
| 1258 | .enable_reg = CCM_PCCR0, | ||
| 1259 | .enable_shift = CCM_PCCR0_I2C1_OFFSET, | ||
| 1260 | .disable = _clk_disable, | ||
| 1261 | }, { | ||
| 1262 | .name = "i2c_clk", | ||
| 1263 | .id = 1, | ||
| 1264 | .parent = &ipg_clk, | ||
| 1265 | .enable = _clk_enable, | ||
| 1266 | .enable_reg = CCM_PCCR0, | ||
| 1267 | .enable_shift = CCM_PCCR0_I2C2_OFFSET, | ||
| 1268 | .disable = _clk_disable, | ||
| 1269 | }, | ||
| 1270 | }; | ||
| 1271 | |||
| 1272 | static struct clk iim_clk = { | ||
| 1273 | .name = "iim_clk", | ||
| 1274 | .parent = &ipg_clk, | ||
| 1275 | .enable = _clk_enable, | ||
| 1276 | .enable_reg = CCM_PCCR0, | ||
| 1277 | .enable_shift = CCM_PCCR0_IIM_OFFSET, | ||
| 1278 | .disable = _clk_disable, | ||
| 1279 | }; | ||
| 1280 | |||
| 1281 | static struct clk kpp_clk = { | ||
| 1282 | .name = "kpp_clk", | ||
| 1283 | .parent = &ipg_clk, | ||
| 1284 | .enable = _clk_enable, | ||
| 1285 | .enable_reg = CCM_PCCR0, | ||
| 1286 | .enable_shift = CCM_PCCR0_KPP_OFFSET, | ||
| 1287 | .disable = _clk_disable, | ||
| 1288 | }; | ||
| 1289 | |||
| 1290 | static struct clk owire_clk = { | ||
| 1291 | .name = "owire_clk", | ||
| 1292 | .parent = &ipg_clk, | ||
| 1293 | .enable = _clk_enable, | ||
| 1294 | .enable_reg = CCM_PCCR0, | ||
| 1295 | .enable_shift = CCM_PCCR0_OWIRE_OFFSET, | ||
| 1296 | .disable = _clk_disable, | ||
| 1297 | }; | ||
| 1298 | |||
| 1299 | static struct clk rtc_clk = { | ||
| 1300 | .name = "rtc_clk", | ||
| 1301 | .parent = &ipg_clk, | ||
| 1302 | .enable = _clk_enable, | ||
| 1303 | .enable_reg = CCM_PCCR0, | ||
| 1304 | .enable_shift = CCM_PCCR0_RTC_OFFSET, | ||
| 1305 | .disable = _clk_disable, | ||
| 1306 | }; | ||
| 1307 | |||
| 1308 | static struct clk scc_clk = { | ||
| 1309 | .name = "scc_clk", | ||
| 1310 | .parent = &ipg_clk, | ||
| 1311 | .enable = _clk_enable, | ||
| 1312 | .enable_reg = CCM_PCCR0, | ||
| 1313 | .enable_shift = CCM_PCCR0_SCC_OFFSET, | ||
| 1314 | .disable = _clk_disable, | ||
| 1315 | }; | ||
| 1316 | |||
| 1317 | static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) | ||
| 1318 | { | ||
| 1319 | u32 div; | ||
| 1320 | unsigned long parent_rate; | ||
| 1321 | |||
| 1322 | parent_rate = clk_get_rate(clk->parent); | ||
| 1323 | div = parent_rate / rate; | ||
| 1324 | if (parent_rate % rate) | ||
| 1325 | div++; | ||
| 1326 | |||
| 1327 | if (div > 8) | ||
| 1328 | div = 8; | ||
| 1329 | |||
| 1330 | return parent_rate / div; | ||
| 1331 | } | ||
| 1332 | |||
| 1333 | static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) | ||
| 1334 | { | ||
| 1335 | u32 reg; | ||
| 1336 | u32 div; | ||
| 1337 | unsigned long parent_rate; | ||
| 1338 | |||
| 1339 | parent_rate = clk_get_rate(clk->parent); | ||
| 1340 | |||
| 1341 | div = parent_rate / rate; | ||
| 1342 | |||
| 1343 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) | ||
| 1344 | return -EINVAL; | ||
| 1345 | div--; | ||
| 1346 | |||
| 1347 | reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK; | ||
| 1348 | reg |= div << CCM_PCDR0_CLKODIV_OFFSET; | ||
| 1349 | __raw_writel(reg, CCM_PCDR0); | ||
| 1350 | |||
| 1351 | return 0; | ||
| 1352 | } | ||
| 1353 | |||
| 1354 | static unsigned long _clk_clko_recalc(struct clk *clk) | ||
| 1355 | { | ||
| 1356 | u32 div; | ||
| 1357 | unsigned long parent_rate; | ||
| 1358 | |||
| 1359 | parent_rate = clk_get_rate(clk->parent); | ||
| 1360 | |||
| 1361 | div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >> | ||
| 1362 | CCM_PCDR0_CLKODIV_OFFSET; | ||
| 1363 | div++; | ||
| 1364 | |||
| 1365 | return parent_rate / div; | ||
| 1366 | } | ||
| 1367 | |||
| 1368 | static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) | ||
| 1369 | { | ||
| 1370 | u32 reg; | ||
| 1371 | |||
| 1372 | reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK; | ||
| 1373 | |||
| 1374 | if (parent == &ckil_clk) | ||
| 1375 | reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1376 | else if (parent == &ckih_clk) | ||
| 1377 | reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1378 | else if (parent == mpll_clk.parent) | ||
| 1379 | reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1380 | else if (parent == spll_clk.parent) | ||
| 1381 | reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1382 | else if (parent == &mpll_clk) | ||
| 1383 | reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1384 | else if (parent == &spll_clk) | ||
| 1385 | reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1386 | else if (parent == &cpu_clk) | ||
| 1387 | reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1388 | else if (parent == &ahb_clk) | ||
| 1389 | reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1390 | else if (parent == &ipg_clk) | ||
| 1391 | reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1392 | else if (parent == &per_clk[0]) | ||
| 1393 | reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1394 | else if (parent == &per_clk[1]) | ||
| 1395 | reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1396 | else if (parent == &per_clk[2]) | ||
| 1397 | reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1398 | else if (parent == &per_clk[3]) | ||
| 1399 | reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1400 | else if (parent == &ssi1_clk[0]) | ||
| 1401 | reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1402 | else if (parent == &ssi2_clk[0]) | ||
| 1403 | reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1404 | else if (parent == &nfc_clk) | ||
| 1405 | reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1406 | else if (parent == &mstick1_clk) | ||
| 1407 | reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1408 | else if (parent == &vpu_clk) | ||
| 1409 | reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1410 | else if (parent == &usb_clk[0]) | ||
| 1411 | reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1412 | else | ||
| 1413 | return -EINVAL; | ||
| 1414 | |||
| 1415 | __raw_writel(reg, CCM_CCSR); | ||
| 1416 | |||
| 1417 | return 0; | ||
| 1418 | } | ||
| 1419 | |||
| 1420 | static int _clk_clko_enable(struct clk *clk) | ||
| 1421 | { | ||
| 1422 | u32 reg; | ||
| 1423 | |||
| 1424 | reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN; | ||
| 1425 | __raw_writel(reg, CCM_PCDR0); | ||
| 1426 | |||
| 1427 | return 0; | ||
| 1428 | } | ||
| 1429 | |||
| 1430 | static void _clk_clko_disable(struct clk *clk) | ||
| 1431 | { | ||
| 1432 | u32 reg; | ||
| 1433 | |||
| 1434 | reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN; | ||
| 1435 | __raw_writel(reg, CCM_PCDR0); | ||
| 1436 | } | ||
| 1437 | |||
| 1438 | static struct clk clko_clk = { | ||
| 1439 | .name = "clko_clk", | ||
| 1440 | .get_rate = _clk_clko_recalc, | ||
| 1441 | .set_rate = _clk_clko_set_rate, | ||
| 1442 | .round_rate = _clk_clko_round_rate, | ||
| 1443 | .set_parent = _clk_clko_set_parent, | ||
| 1444 | .enable = _clk_clko_enable, | ||
| 1445 | .disable = _clk_clko_disable, | ||
| 1446 | }; | ||
| 1447 | |||
| 1448 | static struct clk *mxc_clks[] = { | ||
| 1449 | &ckih_clk, | ||
| 1450 | &ckil_clk, | ||
| 1451 | &mpll_clk, | ||
| 1452 | &mpll_main_clk[0], | ||
| 1453 | &mpll_main_clk[1], | ||
| 1454 | &spll_clk, | ||
| 1455 | &cpu_clk, | ||
| 1456 | &ahb_clk, | ||
| 1457 | &ipg_clk, | ||
| 1458 | &per_clk[0], | ||
| 1459 | &per_clk[1], | ||
| 1460 | &per_clk[2], | ||
| 1461 | &per_clk[3], | ||
| 1462 | &clko_clk, | ||
| 1463 | &uart1_clk[0], | ||
| 1464 | &uart1_clk[1], | ||
| 1465 | &uart2_clk[0], | ||
| 1466 | &uart2_clk[1], | ||
| 1467 | &uart3_clk[0], | ||
| 1468 | &uart3_clk[1], | ||
| 1469 | &uart4_clk[0], | ||
| 1470 | &uart4_clk[1], | ||
| 1471 | &uart5_clk[0], | ||
| 1472 | &uart5_clk[1], | ||
| 1473 | &uart6_clk[0], | ||
| 1474 | &uart6_clk[1], | ||
| 1475 | &gpt1_clk[0], | ||
| 1476 | &gpt1_clk[1], | ||
| 1477 | &gpt2_clk[0], | ||
| 1478 | &gpt2_clk[1], | ||
| 1479 | &gpt3_clk[0], | ||
| 1480 | &gpt3_clk[1], | ||
| 1481 | &gpt4_clk[0], | ||
| 1482 | &gpt4_clk[1], | ||
| 1483 | &gpt5_clk[0], | ||
| 1484 | &gpt5_clk[1], | ||
| 1485 | &gpt6_clk[0], | ||
| 1486 | &gpt6_clk[1], | ||
| 1487 | &pwm_clk[0], | ||
| 1488 | &pwm_clk[1], | ||
| 1489 | &sdhc1_clk[0], | ||
| 1490 | &sdhc1_clk[1], | ||
| 1491 | &sdhc2_clk[0], | ||
| 1492 | &sdhc2_clk[1], | ||
| 1493 | &sdhc3_clk[0], | ||
| 1494 | &sdhc3_clk[1], | ||
| 1495 | &cspi1_clk[0], | ||
| 1496 | &cspi1_clk[1], | ||
| 1497 | &cspi2_clk[0], | ||
| 1498 | &cspi2_clk[1], | ||
| 1499 | &cspi3_clk[0], | ||
| 1500 | &cspi3_clk[1], | ||
| 1501 | &lcdc_clk[0], | ||
| 1502 | &lcdc_clk[1], | ||
| 1503 | &lcdc_clk[2], | ||
| 1504 | &csi_clk[0], | ||
| 1505 | &csi_clk[1], | ||
| 1506 | &usb_clk[0], | ||
| 1507 | &usb_clk[1], | ||
| 1508 | &ssi1_clk[0], | ||
| 1509 | &ssi1_clk[1], | ||
| 1510 | &ssi2_clk[0], | ||
| 1511 | &ssi2_clk[1], | ||
| 1512 | &nfc_clk, | ||
| 1513 | &vpu_clk, | ||
| 1514 | &dma_clk, | ||
| 1515 | &rtic_clk, | ||
| 1516 | &brom_clk, | ||
| 1517 | &emma_clk, | ||
| 1518 | &slcdc_clk, | ||
| 1519 | &fec_clk, | ||
| 1520 | &emi_clk, | ||
| 1521 | &sahara2_clk, | ||
| 1522 | &ata_clk, | ||
| 1523 | &mstick1_clk, | ||
| 1524 | &wdog_clk, | ||
| 1525 | &gpio_clk, | ||
| 1526 | &i2c_clk[0], | ||
| 1527 | &i2c_clk[1], | ||
| 1528 | &iim_clk, | ||
| 1529 | &kpp_clk, | ||
| 1530 | &owire_clk, | ||
| 1531 | &rtc_clk, | ||
| 1532 | &scc_clk, | ||
| 1533 | }; | ||
| 1534 | |||
| 1535 | void __init change_external_low_reference(unsigned long new_ref) | ||
| 1536 | { | ||
| 1537 | external_low_reference = new_ref; | ||
| 1538 | } | ||
| 1539 | |||
| 1540 | unsigned long __init clk_early_get_timer_rate(void) | ||
| 1541 | { | ||
| 1542 | return clk_get_rate(&per_clk[0]); | ||
| 1543 | } | ||
| 1544 | |||
| 1545 | static void __init probe_mxc_clocks(void) | ||
| 1546 | { | ||
| 1547 | int i; | ||
| 1548 | 676 | ||
| 1549 | if (mx27_revision() >= CHIP_REV_2_0) { | 677 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 1550 | if (CSCR() & 0x8000) | 678 | if (cscr & CCM_CSCR_ARM_SRC) |
| 1551 | cpu_clk.parent = &mpll_main_clk[0]; | 679 | cpu_clk.parent = &mpll_main1_clk; |
| 1552 | 680 | ||
| 1553 | if (!(CSCR() & 0x00800000)) | 681 | if (!(cscr & CCM_CSCR_SSI2)) |
| 1554 | ssi2_clk[0].parent = &spll_clk; | 682 | ssi1_clk.parent = &spll_clk; |
| 1555 | 683 | ||
| 1556 | if (!(CSCR() & 0x00400000)) | 684 | if (!(cscr & CCM_CSCR_SSI1)) |
| 1557 | ssi1_clk[0].parent = &spll_clk; | 685 | ssi1_clk.parent = &spll_clk; |
| 1558 | 686 | ||
| 1559 | if (!(CSCR() & 0x00200000)) | 687 | if (!(cscr & CCM_CSCR_VPU)) |
| 1560 | vpu_clk.parent = &spll_clk; | 688 | vpu_clk.parent = &spll_clk; |
| 1561 | } else { | 689 | } else { |
| 1562 | cpu_clk.parent = &mpll_clk; | 690 | cpu_clk.parent = &mpll_clk; |
| @@ -1565,11 +693,13 @@ static void __init probe_mxc_clocks(void) | |||
| 1565 | cpu_clk.set_rate = NULL; | 693 | cpu_clk.set_rate = NULL; |
| 1566 | ahb_clk.parent = &mpll_clk; | 694 | ahb_clk.parent = &mpll_clk; |
| 1567 | 695 | ||
| 1568 | for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++) | 696 | per1_clk.parent = &mpll_clk; |
| 1569 | per_clk[i].parent = &mpll_clk; | 697 | per2_clk.parent = &mpll_clk; |
| 698 | per3_clk.parent = &mpll_clk; | ||
| 699 | per4_clk.parent = &mpll_clk; | ||
| 1570 | 700 | ||
| 1571 | ssi1_clk[0].parent = &mpll_clk; | 701 | ssi1_clk.parent = &mpll_clk; |
| 1572 | ssi2_clk[0].parent = &mpll_clk; | 702 | ssi2_clk.parent = &mpll_clk; |
| 1573 | 703 | ||
| 1574 | vpu_clk.parent = &mpll_clk; | 704 | vpu_clk.parent = &mpll_clk; |
| 1575 | } | 705 | } |
| @@ -1579,47 +709,47 @@ static void __init probe_mxc_clocks(void) | |||
| 1579 | * must be called very early to get information about the | 709 | * must be called very early to get information about the |
| 1580 | * available clock rate when the timer framework starts | 710 | * available clock rate when the timer framework starts |
| 1581 | */ | 711 | */ |
| 1582 | int __init mxc_clocks_init(unsigned long fref) | 712 | int __init mx27_clocks_init(unsigned long fref) |
| 1583 | { | 713 | { |
| 1584 | u32 cscr; | 714 | u32 cscr = __raw_readl(CCM_CSCR); |
| 1585 | struct clk **clkp; | 715 | int i; |
| 1586 | 716 | ||
| 1587 | external_high_reference = fref; | 717 | external_high_reference = fref; |
| 1588 | 718 | ||
| 1589 | /* detect clock reference for both system PLL */ | 719 | /* detect clock reference for both system PLLs */ |
| 1590 | cscr = CSCR(); | ||
| 1591 | if (cscr & CCM_CSCR_MCU) | 720 | if (cscr & CCM_CSCR_MCU) |
| 1592 | mpll_clk.parent = &ckih_clk; | 721 | mpll_clk.parent = &ckih_clk; |
| 1593 | else | 722 | else |
| 1594 | mpll_clk.parent = &ckil_clk; | 723 | mpll_clk.parent = &fpm_clk; |
| 1595 | 724 | ||
| 1596 | if (cscr & CCM_CSCR_SP) | 725 | if (cscr & CCM_CSCR_SP) |
| 1597 | spll_clk.parent = &ckih_clk; | 726 | spll_clk.parent = &ckih_clk; |
| 1598 | else | 727 | else |
| 1599 | spll_clk.parent = &ckil_clk; | 728 | spll_clk.parent = &fpm_clk; |
| 1600 | 729 | ||
| 1601 | probe_mxc_clocks(); | 730 | to2_adjust_clocks(); |
| 1602 | 731 | ||
| 1603 | per_clk[0].enable(&per_clk[0]); | 732 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
| 1604 | gpt1_clk[1].enable(&gpt1_clk[1]); | 733 | clkdev_add(&lookups[i]); |
| 1605 | 734 | ||
| 1606 | for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) | 735 | /* Turn off all clocks we do not need */ |
| 1607 | clk_register(*clkp); | 736 | __raw_writel(0, CCM_PCCR0); |
| 737 | __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1); | ||
| 1608 | 738 | ||
| 1609 | /* Turn off all possible clocks */ | ||
| 1610 | __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0); | ||
| 1611 | __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK, | ||
| 1612 | CCM_PCCR1); | ||
| 1613 | spll_clk.disable(&spll_clk); | 739 | spll_clk.disable(&spll_clk); |
| 1614 | 740 | ||
| 1615 | /* This will propagate to all children and init all the clock rates */ | 741 | /* enable basic clocks */ |
| 1616 | 742 | clk_enable(&per1_clk); | |
| 1617 | clk_enable(&emi_clk); | ||
| 1618 | clk_enable(&gpio_clk); | 743 | clk_enable(&gpio_clk); |
| 744 | clk_enable(&emi_clk); | ||
| 1619 | clk_enable(&iim_clk); | 745 | clk_enable(&iim_clk); |
| 1620 | clk_enable(&gpt1_clk[0]); | 746 | |
| 1621 | #ifdef CONFIG_DEBUG_LL_CONSOLE | 747 | #ifdef CONFIG_DEBUG_LL_CONSOLE |
| 1622 | clk_enable(&uart1_clk[0]); | 748 | clk_enable(&uart1_clk); |
| 1623 | #endif | 749 | #endif |
| 750 | |||
| 751 | mxc_timer_init(&gpt1_clk); | ||
| 752 | |||
| 1624 | return 0; | 753 | return 0; |
| 1625 | } | 754 | } |
| 755 | |||
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c index 239308fe6652..d9e3bf9644c9 100644 --- a/arch/arm/mach-mx2/cpu_imx27.c +++ b/arch/arm/mach-mx2/cpu_imx27.c | |||
| @@ -26,11 +26,11 @@ | |||
| 26 | 26 | ||
| 27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 28 | 28 | ||
| 29 | #include "crm_regs.h" | ||
| 30 | |||
| 31 | static int cpu_silicon_rev = -1; | 29 | static int cpu_silicon_rev = -1; |
| 32 | static int cpu_partnumber; | 30 | static int cpu_partnumber; |
| 33 | 31 | ||
| 32 | #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ | ||
| 33 | |||
| 34 | static void query_silicon_parameter(void) | 34 | static void query_silicon_parameter(void) |
| 35 | { | 35 | { |
| 36 | u32 val; | 36 | u32 val; |
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h index 94644cd0a0fc..749de76b3f95 100644 --- a/arch/arm/mach-mx2/crm_regs.h +++ b/arch/arm/mach-mx2/crm_regs.h | |||
| @@ -38,42 +38,36 @@ | |||
| 38 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) | 38 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) |
| 39 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) | 39 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) |
| 40 | 40 | ||
| 41 | #define CCM_CSCR_USB_OFFSET 28 | 41 | #define CCM_CSCR_PRESC_OFFSET 29 |
| 42 | #define CCM_CSCR_USB_MASK (0x7 << 28) | 42 | #define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) |
| 43 | |||
| 44 | #define CCM_CSCR_USB_OFFSET 26 | ||
| 45 | #define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) | ||
| 43 | #define CCM_CSCR_SD_OFFSET 24 | 46 | #define CCM_CSCR_SD_OFFSET 24 |
| 44 | #define CCM_CSCR_SD_MASK (0x3 << 24) | 47 | #define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) |
| 45 | #define CCM_CSCR_SSI2 (1 << 23) | 48 | #define CCM_CSCR_SPLLRES (1 << 22) |
| 46 | #define CCM_CSCR_SSI2_OFFSET 23 | 49 | #define CCM_CSCR_MPLLRES (1 << 21) |
| 47 | #define CCM_CSCR_SSI1 (1 << 22) | 50 | #define CCM_CSCR_SSI2_OFFSET 20 |
| 48 | #define CCM_CSCR_SSI1_OFFSET 22 | 51 | #define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) |
| 49 | #define CCM_CSCR_VPU (1 << 21) | 52 | #define CCM_CSCR_SSI1_OFFSET 19 |
| 50 | #define CCM_CSCR_VPU_OFFSET 21 | 53 | #define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) |
| 51 | #define CCM_CSCR_MSHC (1 << 20) | 54 | #define CCM_CSCR_FIR_OFFSET 18 |
| 52 | #define CCM_CSCR_SPLLRES (1 << 19) | 55 | #define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) |
| 53 | #define CCM_CSCR_MPLLRES (1 << 18) | ||
| 54 | #define CCM_CSCR_SP (1 << 17) | 56 | #define CCM_CSCR_SP (1 << 17) |
| 55 | #define CCM_CSCR_MCU (1 << 16) | 57 | #define CCM_CSCR_MCU (1 << 16) |
| 56 | /* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ | 58 | #define CCM_CSCR_BCLK_OFFSET 10 |
| 57 | #define CCM_CSCR_ARM_SRC (1 << 15) | 59 | #define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) |
| 58 | #define CCM_CSCR_ARM_OFFSET 12 | 60 | #define CCM_CSCR_IPDIV_OFFSET 9 |
| 59 | #define CCM_CSCR_ARM_MASK (0x3 << 12) | 61 | #define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) |
| 60 | /* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ | 62 | |
| 61 | #define CCM_CSCR_PRESC_OFFSET 13 | ||
| 62 | #define CCM_CSCR_PRESC_MASK (0x7 << 13) | ||
| 63 | #define CCM_CSCR_BCLK_OFFSET 9 | ||
| 64 | #define CCM_CSCR_BCLK_MASK (0xf << 9) | ||
| 65 | #define CCM_CSCR_IPDIV_OFFSET 8 | ||
| 66 | #define CCM_CSCR_IPDIV (1 << 8) | ||
| 67 | /* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ | ||
| 68 | #define CCM_CSCR_AHB_OFFSET 8 | ||
| 69 | #define CCM_CSCR_AHB_MASK (0x3 << 8) | ||
| 70 | /* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ | ||
| 71 | #define CCM_CSCR_OSC26MDIV (1 << 4) | 63 | #define CCM_CSCR_OSC26MDIV (1 << 4) |
| 72 | #define CCM_CSCR_OSC26M (1 << 3) | 64 | #define CCM_CSCR_OSC26M (1 << 3) |
| 73 | #define CCM_CSCR_FPM (1 << 2) | 65 | #define CCM_CSCR_FPM (1 << 2) |
| 74 | #define CCM_CSCR_SPEN (1 << 1) | 66 | #define CCM_CSCR_SPEN (1 << 1) |
| 75 | #define CCM_CSCR_MPEN 1 | 67 | #define CCM_CSCR_MPEN 1 |
| 76 | 68 | ||
| 69 | |||
| 70 | |||
| 77 | #define CCM_MPCTL0_CPLM (1 << 31) | 71 | #define CCM_MPCTL0_CPLM (1 << 31) |
| 78 | #define CCM_MPCTL0_PD_OFFSET 26 | 72 | #define CCM_MPCTL0_PD_OFFSET 26 |
| 79 | #define CCM_MPCTL0_PD_MASK (0xf << 26) | 73 | #define CCM_MPCTL0_PD_MASK (0xf << 26) |
| @@ -109,25 +103,14 @@ | |||
| 109 | 103 | ||
| 110 | #define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 | 104 | #define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 |
| 111 | #define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) | 105 | #define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) |
| 112 | #define CCM_PCDR0_CLKO_EN 25 | ||
| 113 | #define CCM_PCDR0_CLKODIV_OFFSET 22 | ||
| 114 | #define CCM_PCDR0_CLKODIV_MASK (0x7 << 22) | ||
| 115 | #define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 | 106 | #define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 |
| 116 | #define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) | 107 | #define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) |
| 117 | /*The difinition for i.MX27 TO2*/ | ||
| 118 | #define CCM_PCDR0_VPUDIV2_OFFSET 10 | ||
| 119 | #define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10) | ||
| 120 | #define CCM_PCDR0_NFCDIV2_OFFSET 6 | ||
| 121 | #define CCM_PCDR0_NFCDIV2_MASK (0xf << 6) | ||
| 122 | #define CCM_PCDR0_MSHCDIV2_MASK 0x3f | ||
| 123 | /*The difinition for i.MX27 TO2*/ | ||
| 124 | #define CCM_PCDR0_NFCDIV_OFFSET 12 | 108 | #define CCM_PCDR0_NFCDIV_OFFSET 12 |
| 125 | #define CCM_PCDR0_NFCDIV_MASK (0xf << 12) | 109 | #define CCM_PCDR0_NFCDIV_MASK (0xf << 12) |
| 126 | #define CCM_PCDR0_VPUDIV_OFFSET 8 | 110 | #define CCM_PCDR0_48MDIV_OFFSET 5 |
| 127 | #define CCM_PCDR0_VPUDIV_MASK (0xf << 8) | 111 | #define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) |
| 128 | #define CCM_PCDR0_MSHCDIV_OFFSET 0 | 112 | #define CCM_PCDR0_FIRIDIV_OFFSET 0 |
| 129 | #define CCM_PCDR0_MSHCDIV_MASK 0x1f | 113 | #define CCM_PCDR0_FIRIDIV_MASK 0x1f |
| 130 | |||
| 131 | #define CCM_PCDR1_PERDIV4_OFFSET 24 | 114 | #define CCM_PCDR1_PERDIV4_OFFSET 24 |
| 132 | #define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) | 115 | #define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) |
| 133 | #define CCM_PCDR1_PERDIV3_OFFSET 16 | 116 | #define CCM_PCDR1_PERDIV3_OFFSET 16 |
| @@ -137,133 +120,135 @@ | |||
| 137 | #define CCM_PCDR1_PERDIV1_OFFSET 0 | 120 | #define CCM_PCDR1_PERDIV1_OFFSET 0 |
| 138 | #define CCM_PCDR1_PERDIV1_MASK 0x3f | 121 | #define CCM_PCDR1_PERDIV1_MASK 0x3f |
| 139 | 122 | ||
| 140 | #define CCM_PCCR0_CSPI1_OFFSET 31 | 123 | #define CCM_PCCR_HCLK_CSI_OFFSET 31 |
| 141 | #define CCM_PCCR0_CSPI1_MASK (1 << 31) | 124 | #define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 |
| 142 | #define CCM_PCCR0_CSPI2_OFFSET 30 | 125 | #define CCM_PCCR_HCLK_DMA_OFFSET 30 |
| 143 | #define CCM_PCCR0_CSPI2_MASK (1 << 30) | 126 | #define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 |
| 144 | #define CCM_PCCR0_CSPI3_OFFSET 29 | 127 | #define CCM_PCCR_HCLK_BROM_OFFSET 28 |
| 145 | #define CCM_PCCR0_CSPI3_MASK (1 << 29) | 128 | #define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 |
| 146 | #define CCM_PCCR0_DMA_OFFSET 28 | 129 | #define CCM_PCCR_HCLK_EMMA_OFFSET 27 |
| 147 | #define CCM_PCCR0_DMA_MASK (1 << 28) | 130 | #define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 |
| 148 | #define CCM_PCCR0_EMMA_OFFSET 27 | 131 | #define CCM_PCCR_HCLK_LCDC_OFFSET 26 |
| 149 | #define CCM_PCCR0_EMMA_MASK (1 << 27) | 132 | #define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 |
| 150 | #define CCM_PCCR0_FEC_OFFSET 26 | 133 | #define CCM_PCCR_HCLK_SLCDC_OFFSET 25 |
| 151 | #define CCM_PCCR0_FEC_MASK (1 << 26) | 134 | #define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 |
| 152 | #define CCM_PCCR0_GPIO_OFFSET 25 | 135 | #define CCM_PCCR_HCLK_USBOTG_OFFSET 24 |
| 153 | #define CCM_PCCR0_GPIO_MASK (1 << 25) | 136 | #define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 |
| 154 | #define CCM_PCCR0_GPT1_OFFSET 24 | 137 | #define CCM_PCCR_HCLK_BMI_OFFSET 23 |
| 155 | #define CCM_PCCR0_GPT1_MASK (1 << 24) | 138 | #define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) |
| 156 | #define CCM_PCCR0_GPT2_OFFSET 23 | 139 | #define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 |
| 157 | #define CCM_PCCR0_GPT2_MASK (1 << 23) | 140 | #define CCM_PCCR_PERCLK4_OFFSET 22 |
| 158 | #define CCM_PCCR0_GPT3_OFFSET 22 | 141 | #define CCM_PCCR_PERCLK4_REG CCM_PCCR0 |
| 159 | #define CCM_PCCR0_GPT3_MASK (1 << 22) | 142 | #define CCM_PCCR_SLCDC_OFFSET 21 |
| 160 | #define CCM_PCCR0_GPT4_OFFSET 21 | 143 | #define CCM_PCCR_SLCDC_REG CCM_PCCR0 |
| 161 | #define CCM_PCCR0_GPT4_MASK (1 << 21) | 144 | #define CCM_PCCR_FIRI_BAUD_OFFSET 20 |
| 162 | #define CCM_PCCR0_GPT5_OFFSET 20 | 145 | #define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) |
| 163 | #define CCM_PCCR0_GPT5_MASK (1 << 20) | 146 | #define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 |
| 164 | #define CCM_PCCR0_GPT6_OFFSET 19 | 147 | #define CCM_PCCR_NFC_OFFSET 19 |
| 165 | #define CCM_PCCR0_GPT6_MASK (1 << 19) | 148 | #define CCM_PCCR_NFC_REG CCM_PCCR0 |
| 166 | #define CCM_PCCR0_I2C1_OFFSET 18 | 149 | #define CCM_PCCR_LCDC_OFFSET 18 |
| 167 | #define CCM_PCCR0_I2C1_MASK (1 << 18) | 150 | #define CCM_PCCR_LCDC_REG CCM_PCCR0 |
| 168 | #define CCM_PCCR0_I2C2_OFFSET 17 | 151 | #define CCM_PCCR_SSI1_BAUD_OFFSET 17 |
| 169 | #define CCM_PCCR0_I2C2_MASK (1 << 17) | 152 | #define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 |
| 170 | #define CCM_PCCR0_IIM_OFFSET 16 | 153 | #define CCM_PCCR_SSI2_BAUD_OFFSET 16 |
| 171 | #define CCM_PCCR0_IIM_MASK (1 << 16) | 154 | #define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 |
| 172 | #define CCM_PCCR0_KPP_OFFSET 15 | 155 | #define CCM_PCCR_EMMA_OFFSET 15 |
| 173 | #define CCM_PCCR0_KPP_MASK (1 << 15) | 156 | #define CCM_PCCR_EMMA_REG CCM_PCCR0 |
| 174 | #define CCM_PCCR0_LCDC_OFFSET 14 | 157 | #define CCM_PCCR_USBOTG_OFFSET 14 |
| 175 | #define CCM_PCCR0_LCDC_MASK (1 << 14) | 158 | #define CCM_PCCR_USBOTG_REG CCM_PCCR0 |
| 176 | #define CCM_PCCR0_MSHC_OFFSET 13 | 159 | #define CCM_PCCR_DMA_OFFSET 13 |
| 177 | #define CCM_PCCR0_MSHC_MASK (1 << 13) | 160 | #define CCM_PCCR_DMA_REG CCM_PCCR0 |
| 178 | #define CCM_PCCR0_OWIRE_OFFSET 12 | 161 | #define CCM_PCCR_I2C1_OFFSET 12 |
| 179 | #define CCM_PCCR0_OWIRE_MASK (1 << 12) | 162 | #define CCM_PCCR_I2C1_REG CCM_PCCR0 |
| 180 | #define CCM_PCCR0_PWM_OFFSET 11 | 163 | #define CCM_PCCR_GPIO_OFFSET 11 |
| 181 | #define CCM_PCCR0_PWM_MASK (1 << 11) | 164 | #define CCM_PCCR_GPIO_REG CCM_PCCR0 |
| 182 | #define CCM_PCCR0_RTC_OFFSET 9 | 165 | #define CCM_PCCR_SDHC2_OFFSET 10 |
| 183 | #define CCM_PCCR0_RTC_MASK (1 << 9) | 166 | #define CCM_PCCR_SDHC2_REG CCM_PCCR0 |
| 184 | #define CCM_PCCR0_RTIC_OFFSET 8 | 167 | #define CCM_PCCR_SDHC1_OFFSET 9 |
| 185 | #define CCM_PCCR0_RTIC_MASK (1 << 8) | 168 | #define CCM_PCCR_SDHC1_REG CCM_PCCR0 |
| 186 | #define CCM_PCCR0_SAHARA_OFFSET 7 | 169 | #define CCM_PCCR_FIRI_OFFSET 8 |
| 187 | #define CCM_PCCR0_SAHARA_MASK (1 << 7) | 170 | #define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) |
| 188 | #define CCM_PCCR0_SCC_OFFSET 6 | 171 | #define CCM_PCCR_FIRI_REG CCM_PCCR0 |
| 189 | #define CCM_PCCR0_SCC_MASK (1 << 6) | 172 | #define CCM_PCCR_SSI2_IPG_OFFSET 7 |
| 190 | #define CCM_PCCR0_SDHC1_OFFSET 5 | 173 | #define CCM_PCCR_SSI2_REG CCM_PCCR0 |
| 191 | #define CCM_PCCR0_SDHC1_MASK (1 << 5) | 174 | #define CCM_PCCR_SSI1_IPG_OFFSET 6 |
| 192 | #define CCM_PCCR0_SDHC2_OFFSET 4 | 175 | #define CCM_PCCR_SSI1_REG CCM_PCCR0 |
| 193 | #define CCM_PCCR0_SDHC2_MASK (1 << 4) | 176 | #define CCM_PCCR_CSPI2_OFFSET 5 |
| 194 | #define CCM_PCCR0_SDHC3_OFFSET 3 | 177 | #define CCM_PCCR_CSPI2_REG CCM_PCCR0 |
| 195 | #define CCM_PCCR0_SDHC3_MASK (1 << 3) | 178 | #define CCM_PCCR_CSPI1_OFFSET 4 |
| 196 | #define CCM_PCCR0_SLCDC_OFFSET 2 | 179 | #define CCM_PCCR_CSPI1_REG CCM_PCCR0 |
| 197 | #define CCM_PCCR0_SLCDC_MASK (1 << 2) | 180 | #define CCM_PCCR_UART4_OFFSET 3 |
| 198 | #define CCM_PCCR0_SSI1_IPG_OFFSET 1 | 181 | #define CCM_PCCR_UART4_REG CCM_PCCR0 |
| 199 | #define CCM_PCCR0_SSI1_IPG_MASK (1 << 1) | 182 | #define CCM_PCCR_UART3_OFFSET 2 |
| 200 | #define CCM_PCCR0_SSI2_IPG_OFFSET 0 | 183 | #define CCM_PCCR_UART3_REG CCM_PCCR0 |
| 201 | #define CCM_PCCR0_SSI2_IPG_MASK (1 << 0) | 184 | #define CCM_PCCR_UART2_OFFSET 1 |
| 185 | #define CCM_PCCR_UART2_REG CCM_PCCR0 | ||
| 186 | #define CCM_PCCR_UART1_OFFSET 0 | ||
| 187 | #define CCM_PCCR_UART1_REG CCM_PCCR0 | ||
| 188 | |||
| 189 | #define CCM_PCCR_OWIRE_OFFSET 31 | ||
| 190 | #define CCM_PCCR_OWIRE_REG CCM_PCCR1 | ||
| 191 | #define CCM_PCCR_KPP_OFFSET 30 | ||
| 192 | #define CCM_PCCR_KPP_REG CCM_PCCR1 | ||
| 193 | #define CCM_PCCR_RTC_OFFSET 29 | ||
| 194 | #define CCM_PCCR_RTC_REG CCM_PCCR1 | ||
| 195 | #define CCM_PCCR_PWM_OFFSET 28 | ||
| 196 | #define CCM_PCCR_PWM_REG CCM_PCCR1 | ||
| 197 | #define CCM_PCCR_GPT3_OFFSET 27 | ||
| 198 | #define CCM_PCCR_GPT3_REG CCM_PCCR1 | ||
| 199 | #define CCM_PCCR_GPT2_OFFSET 26 | ||
| 200 | #define CCM_PCCR_GPT2_REG CCM_PCCR1 | ||
| 201 | #define CCM_PCCR_GPT1_OFFSET 25 | ||
| 202 | #define CCM_PCCR_GPT1_REG CCM_PCCR1 | ||
| 203 | #define CCM_PCCR_WDT_OFFSET 24 | ||
| 204 | #define CCM_PCCR_WDT_REG CCM_PCCR1 | ||
| 205 | #define CCM_PCCR_CSPI3_OFFSET 23 | ||
| 206 | #define CCM_PCCR_CSPI3_REG CCM_PCCR1 | ||
| 207 | |||
| 208 | #define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) | ||
| 209 | #define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) | ||
| 210 | #define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) | ||
| 211 | #define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) | ||
| 212 | #define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) | ||
| 213 | #define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) | ||
| 214 | #define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) | ||
| 215 | #define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) | ||
| 216 | #define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) | ||
| 217 | #define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) | ||
| 218 | #define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) | ||
| 219 | #define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) | ||
| 220 | #define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) | ||
| 221 | #define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) | ||
| 222 | #define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) | ||
| 223 | #define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) | ||
| 224 | #define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) | ||
| 225 | #define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) | ||
| 226 | #define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) | ||
| 227 | #define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) | ||
| 228 | #define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) | ||
| 229 | #define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) | ||
| 230 | #define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) | ||
| 231 | #define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) | ||
| 232 | #define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) | ||
| 233 | #define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) | ||
| 234 | #define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) | ||
| 235 | #define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) | ||
| 236 | #define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) | ||
| 237 | #define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) | ||
| 238 | #define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) | ||
| 239 | #define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) | ||
| 240 | #define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) | ||
| 241 | #define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) | ||
| 242 | #define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) | ||
| 243 | #define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) | ||
| 244 | #define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) | ||
| 202 | 245 | ||
| 203 | #define CCM_PCCR1_UART1_OFFSET 31 | ||
| 204 | #define CCM_PCCR1_UART1_MASK (1 << 31) | ||
| 205 | #define CCM_PCCR1_UART2_OFFSET 30 | ||
| 206 | #define CCM_PCCR1_UART2_MASK (1 << 30) | ||
| 207 | #define CCM_PCCR1_UART3_OFFSET 29 | ||
| 208 | #define CCM_PCCR1_UART3_MASK (1 << 29) | ||
| 209 | #define CCM_PCCR1_UART4_OFFSET 28 | ||
| 210 | #define CCM_PCCR1_UART4_MASK (1 << 28) | ||
| 211 | #define CCM_PCCR1_UART5_OFFSET 27 | ||
| 212 | #define CCM_PCCR1_UART5_MASK (1 << 27) | ||
| 213 | #define CCM_PCCR1_UART6_OFFSET 26 | ||
| 214 | #define CCM_PCCR1_UART6_MASK (1 << 26) | ||
| 215 | #define CCM_PCCR1_USBOTG_OFFSET 25 | ||
| 216 | #define CCM_PCCR1_USBOTG_MASK (1 << 25) | ||
| 217 | #define CCM_PCCR1_WDT_OFFSET 24 | ||
| 218 | #define CCM_PCCR1_WDT_MASK (1 << 24) | ||
| 219 | #define CCM_PCCR1_HCLK_ATA_OFFSET 23 | ||
| 220 | #define CCM_PCCR1_HCLK_ATA_MASK (1 << 23) | ||
| 221 | #define CCM_PCCR1_HCLK_BROM_OFFSET 22 | ||
| 222 | #define CCM_PCCR1_HCLK_BROM_MASK (1 << 22) | ||
| 223 | #define CCM_PCCR1_HCLK_CSI_OFFSET 21 | ||
| 224 | #define CCM_PCCR1_HCLK_CSI_MASK (1 << 21) | ||
| 225 | #define CCM_PCCR1_HCLK_DMA_OFFSET 20 | ||
| 226 | #define CCM_PCCR1_HCLK_DMA_MASK (1 << 20) | ||
| 227 | #define CCM_PCCR1_HCLK_EMI_OFFSET 19 | ||
| 228 | #define CCM_PCCR1_HCLK_EMI_MASK (1 << 19) | ||
| 229 | #define CCM_PCCR1_HCLK_EMMA_OFFSET 18 | ||
| 230 | #define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18) | ||
| 231 | #define CCM_PCCR1_HCLK_FEC_OFFSET 17 | ||
| 232 | #define CCM_PCCR1_HCLK_FEC_MASK (1 << 17) | ||
| 233 | #define CCM_PCCR1_HCLK_VPU_OFFSET 16 | ||
| 234 | #define CCM_PCCR1_HCLK_VPU_MASK (1 << 16) | ||
| 235 | #define CCM_PCCR1_HCLK_LCDC_OFFSET 15 | ||
| 236 | #define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15) | ||
| 237 | #define CCM_PCCR1_HCLK_RTIC_OFFSET 14 | ||
| 238 | #define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14) | ||
| 239 | #define CCM_PCCR1_HCLK_SAHARA_OFFSET 13 | ||
| 240 | #define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13) | ||
| 241 | #define CCM_PCCR1_HCLK_SLCDC_OFFSET 12 | ||
| 242 | #define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12) | ||
| 243 | #define CCM_PCCR1_HCLK_USBOTG_OFFSET 11 | ||
| 244 | #define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11) | ||
| 245 | #define CCM_PCCR1_PERCLK1_OFFSET 10 | ||
| 246 | #define CCM_PCCR1_PERCLK1_MASK (1 << 10) | ||
| 247 | #define CCM_PCCR1_PERCLK2_OFFSET 9 | ||
| 248 | #define CCM_PCCR1_PERCLK2_MASK (1 << 9) | ||
| 249 | #define CCM_PCCR1_PERCLK3_OFFSET 8 | ||
| 250 | #define CCM_PCCR1_PERCLK3_MASK (1 << 8) | ||
| 251 | #define CCM_PCCR1_PERCLK4_OFFSET 7 | ||
| 252 | #define CCM_PCCR1_PERCLK4_MASK (1 << 7) | ||
| 253 | #define CCM_PCCR1_VPU_BAUD_OFFSET 6 | ||
| 254 | #define CCM_PCCR1_VPU_BAUD_MASK (1 << 6) | ||
| 255 | #define CCM_PCCR1_SSI1_BAUD_OFFSET 5 | ||
| 256 | #define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5) | ||
| 257 | #define CCM_PCCR1_SSI2_BAUD_OFFSET 4 | ||
| 258 | #define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4) | ||
| 259 | #define CCM_PCCR1_NFC_BAUD_OFFSET 3 | ||
| 260 | #define CCM_PCCR1_NFC_BAUD_MASK (1 << 3) | ||
| 261 | #define CCM_PCCR1_MSHC_BAUD_OFFSET 2 | ||
| 262 | #define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2) | ||
| 263 | 246 | ||
| 264 | #define CCM_CCSR_32KSR (1 << 15) | 247 | #define CCM_CCSR_32KSR (1 << 15) |
| 248 | |||
| 265 | #define CCM_CCSR_CLKMODE1 (1 << 9) | 249 | #define CCM_CCSR_CLKMODE1 (1 << 9) |
| 266 | #define CCM_CCSR_CLKMODE0 (1 << 8) | 250 | #define CCM_CCSR_CLKMODE0 (1 << 8) |
| 251 | |||
| 267 | #define CCM_CCSR_CLKOSEL_OFFSET 0 | 252 | #define CCM_CCSR_CLKOSEL_OFFSET 0 |
| 268 | #define CCM_CCSR_CLKOSEL_MASK 0x1f | 253 | #define CCM_CCSR_CLKOSEL_MASK 0x1f |
| 269 | 254 | ||
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 2f9240be1c76..a0f1b3674327 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c | |||
| @@ -34,6 +34,10 @@ | |||
| 34 | 34 | ||
| 35 | #include <mach/irqs.h> | 35 | #include <mach/irqs.h> |
| 36 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 37 | #include <mach/common.h> | ||
| 38 | #include <mach/mmc.h> | ||
| 39 | |||
| 40 | #include "devices.h" | ||
| 37 | 41 | ||
| 38 | /* | 42 | /* |
| 39 | * Resource definition for the MXC IrDA | 43 | * Resource definition for the MXC IrDA |
| @@ -225,37 +229,215 @@ struct platform_device mxc_nand_device = { | |||
| 225 | .resource = mxc_nand_resources, | 229 | .resource = mxc_nand_resources, |
| 226 | }; | 230 | }; |
| 227 | 231 | ||
| 232 | /* | ||
| 233 | * lcdc: | ||
| 234 | * - i.MX1: the basic controller | ||
| 235 | * - i.MX21: to be checked | ||
| 236 | * - i.MX27: like i.MX1, with slightly variations | ||
| 237 | */ | ||
| 238 | static struct resource mxc_fb[] = { | ||
| 239 | { | ||
| 240 | .start = LCDC_BASE_ADDR, | ||
| 241 | .end = LCDC_BASE_ADDR + 0xFFF, | ||
| 242 | .flags = IORESOURCE_MEM, | ||
| 243 | }, | ||
| 244 | { | ||
| 245 | .start = MXC_INT_LCDC, | ||
| 246 | .end = MXC_INT_LCDC, | ||
| 247 | .flags = IORESOURCE_IRQ, | ||
| 248 | } | ||
| 249 | }; | ||
| 250 | |||
| 251 | /* mxc lcd driver */ | ||
| 252 | struct platform_device mxc_fb_device = { | ||
| 253 | .name = "imx-fb", | ||
| 254 | .id = 0, | ||
| 255 | .num_resources = ARRAY_SIZE(mxc_fb), | ||
| 256 | .resource = mxc_fb, | ||
| 257 | .dev = { | ||
| 258 | .coherent_dma_mask = 0xFFFFFFFF, | ||
| 259 | }, | ||
| 260 | }; | ||
| 261 | |||
| 262 | #ifdef CONFIG_MACH_MX27 | ||
| 263 | static struct resource mxc_fec_resources[] = { | ||
| 264 | { | ||
| 265 | .start = FEC_BASE_ADDR, | ||
| 266 | .end = FEC_BASE_ADDR + 0xfff, | ||
| 267 | .flags = IORESOURCE_MEM | ||
| 268 | }, { | ||
| 269 | .start = MXC_INT_FEC, | ||
| 270 | .end = MXC_INT_FEC, | ||
| 271 | .flags = IORESOURCE_IRQ | ||
| 272 | }, | ||
| 273 | }; | ||
| 274 | |||
| 275 | struct platform_device mxc_fec_device = { | ||
| 276 | .name = "fec", | ||
| 277 | .id = 0, | ||
| 278 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | ||
| 279 | .resource = mxc_fec_resources, | ||
| 280 | }; | ||
| 281 | #endif | ||
| 282 | |||
| 283 | static struct resource mxc_i2c_1_resources[] = { | ||
| 284 | [0] = { | ||
| 285 | .start = I2C_BASE_ADDR, | ||
| 286 | .end = I2C_BASE_ADDR + 0x0fff, | ||
| 287 | .flags = IORESOURCE_MEM | ||
| 288 | }, | ||
| 289 | [1] = { | ||
| 290 | .start = MXC_INT_I2C, | ||
| 291 | .end = MXC_INT_I2C, | ||
| 292 | .flags = IORESOURCE_IRQ | ||
| 293 | } | ||
| 294 | }; | ||
| 295 | |||
| 296 | struct platform_device mxc_i2c_device0 = { | ||
| 297 | .name = "imx-i2c", | ||
| 298 | .id = 0, | ||
| 299 | .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), | ||
| 300 | .resource = mxc_i2c_1_resources | ||
| 301 | }; | ||
| 302 | |||
| 303 | #ifdef CONFIG_MACH_MX27 | ||
| 304 | static struct resource mxc_i2c_2_resources[] = { | ||
| 305 | [0] = { | ||
| 306 | .start = I2C2_BASE_ADDR, | ||
| 307 | .end = I2C2_BASE_ADDR + 0x0fff, | ||
| 308 | .flags = IORESOURCE_MEM | ||
| 309 | }, | ||
| 310 | [1] = { | ||
| 311 | .start = MXC_INT_I2C2, | ||
| 312 | .end = MXC_INT_I2C2, | ||
| 313 | .flags = IORESOURCE_IRQ | ||
| 314 | } | ||
| 315 | }; | ||
| 316 | |||
| 317 | struct platform_device mxc_i2c_device1 = { | ||
| 318 | .name = "imx-i2c", | ||
| 319 | .id = 1, | ||
| 320 | .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), | ||
| 321 | .resource = mxc_i2c_2_resources | ||
| 322 | }; | ||
| 323 | #endif | ||
| 324 | |||
| 325 | static struct resource mxc_pwm_resources[] = { | ||
| 326 | [0] = { | ||
| 327 | .start = PWM_BASE_ADDR, | ||
| 328 | .end = PWM_BASE_ADDR + 0x0fff, | ||
| 329 | .flags = IORESOURCE_MEM | ||
| 330 | }, | ||
| 331 | [1] = { | ||
| 332 | .start = MXC_INT_PWM, | ||
| 333 | .end = MXC_INT_PWM, | ||
| 334 | .flags = IORESOURCE_IRQ, | ||
| 335 | } | ||
| 336 | }; | ||
| 337 | |||
| 338 | struct platform_device mxc_pwm_device = { | ||
| 339 | .name = "mxc_pwm", | ||
| 340 | .id = 0, | ||
| 341 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | ||
| 342 | .resource = mxc_pwm_resources | ||
| 343 | }; | ||
| 344 | |||
| 345 | /* | ||
| 346 | * Resource definition for the MXC SDHC | ||
| 347 | */ | ||
| 348 | static struct resource mxc_sdhc1_resources[] = { | ||
| 349 | [0] = { | ||
| 350 | .start = SDHC1_BASE_ADDR, | ||
| 351 | .end = SDHC1_BASE_ADDR + SZ_4K - 1, | ||
| 352 | .flags = IORESOURCE_MEM, | ||
| 353 | }, | ||
| 354 | [1] = { | ||
| 355 | .start = MXC_INT_SDHC1, | ||
| 356 | .end = MXC_INT_SDHC1, | ||
| 357 | .flags = IORESOURCE_IRQ, | ||
| 358 | }, | ||
| 359 | [2] = { | ||
| 360 | .start = DMA_REQ_SDHC1, | ||
| 361 | .end = DMA_REQ_SDHC1, | ||
| 362 | .flags = IORESOURCE_DMA | ||
| 363 | }, | ||
| 364 | }; | ||
| 365 | |||
| 366 | static u64 mxc_sdhc1_dmamask = 0xffffffffUL; | ||
| 367 | |||
| 368 | struct platform_device mxc_sdhc_device0 = { | ||
| 369 | .name = "mxc-mmc", | ||
| 370 | .id = 0, | ||
| 371 | .dev = { | ||
| 372 | .dma_mask = &mxc_sdhc1_dmamask, | ||
| 373 | .coherent_dma_mask = 0xffffffff, | ||
| 374 | }, | ||
| 375 | .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), | ||
| 376 | .resource = mxc_sdhc1_resources, | ||
| 377 | }; | ||
| 378 | |||
| 379 | static struct resource mxc_sdhc2_resources[] = { | ||
| 380 | [0] = { | ||
| 381 | .start = SDHC2_BASE_ADDR, | ||
| 382 | .end = SDHC2_BASE_ADDR + SZ_4K - 1, | ||
| 383 | .flags = IORESOURCE_MEM, | ||
| 384 | }, | ||
| 385 | [1] = { | ||
| 386 | .start = MXC_INT_SDHC2, | ||
| 387 | .end = MXC_INT_SDHC2, | ||
| 388 | .flags = IORESOURCE_IRQ, | ||
| 389 | }, | ||
| 390 | [2] = { | ||
| 391 | .start = DMA_REQ_SDHC2, | ||
| 392 | .end = DMA_REQ_SDHC2, | ||
| 393 | .flags = IORESOURCE_DMA | ||
| 394 | }, | ||
| 395 | }; | ||
| 396 | |||
| 397 | static u64 mxc_sdhc2_dmamask = 0xffffffffUL; | ||
| 398 | |||
| 399 | struct platform_device mxc_sdhc_device1 = { | ||
| 400 | .name = "mxc-mmc", | ||
| 401 | .id = 1, | ||
| 402 | .dev = { | ||
| 403 | .dma_mask = &mxc_sdhc2_dmamask, | ||
| 404 | .coherent_dma_mask = 0xffffffff, | ||
| 405 | }, | ||
| 406 | .num_resources = ARRAY_SIZE(mxc_sdhc2_resources), | ||
| 407 | .resource = mxc_sdhc2_resources, | ||
| 408 | }; | ||
| 409 | |||
| 228 | /* GPIO port description */ | 410 | /* GPIO port description */ |
| 229 | static struct mxc_gpio_port imx_gpio_ports[] = { | 411 | static struct mxc_gpio_port imx_gpio_ports[] = { |
| 230 | [0] = { | 412 | [0] = { |
| 231 | .chip.label = "gpio-0", | 413 | .chip.label = "gpio-0", |
| 232 | .irq = MXC_INT_GPIO, | 414 | .irq = MXC_INT_GPIO, |
| 233 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0), | 415 | .base = IO_ADDRESS(GPIO_BASE_ADDR), |
| 234 | .virtual_irq_start = MXC_GPIO_IRQ_START, | 416 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
| 235 | }, | 417 | }, |
| 236 | [1] = { | 418 | [1] = { |
| 237 | .chip.label = "gpio-1", | 419 | .chip.label = "gpio-1", |
| 238 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1), | 420 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), |
| 239 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | 421 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
| 240 | }, | 422 | }, |
| 241 | [2] = { | 423 | [2] = { |
| 242 | .chip.label = "gpio-2", | 424 | .chip.label = "gpio-2", |
| 243 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2), | 425 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), |
| 244 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | 426 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
| 245 | }, | 427 | }, |
| 246 | [3] = { | 428 | [3] = { |
| 247 | .chip.label = "gpio-3", | 429 | .chip.label = "gpio-3", |
| 248 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3), | 430 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), |
| 249 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | 431 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, |
| 250 | }, | 432 | }, |
| 251 | [4] = { | 433 | [4] = { |
| 252 | .chip.label = "gpio-4", | 434 | .chip.label = "gpio-4", |
| 253 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4), | 435 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), |
| 254 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, | 436 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, |
| 255 | }, | 437 | }, |
| 256 | [5] = { | 438 | [5] = { |
| 257 | .chip.label = "gpio-5", | 439 | .chip.label = "gpio-5", |
| 258 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5), | 440 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), |
| 259 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, | 441 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |
| 260 | } | 442 | } |
| 261 | }; | 443 | }; |
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index 1e8cb577a642..049005bb6aa9 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | |||
| 2 | extern struct platform_device mxc_gpt1; | 1 | extern struct platform_device mxc_gpt1; |
| 3 | extern struct platform_device mxc_gpt2; | 2 | extern struct platform_device mxc_gpt2; |
| 4 | extern struct platform_device mxc_gpt3; | 3 | extern struct platform_device mxc_gpt3; |
| @@ -14,3 +13,10 @@ extern struct platform_device mxc_uart_device4; | |||
| 14 | extern struct platform_device mxc_uart_device5; | 13 | extern struct platform_device mxc_uart_device5; |
| 15 | extern struct platform_device mxc_w1_master_device; | 14 | extern struct platform_device mxc_w1_master_device; |
| 16 | extern struct platform_device mxc_nand_device; | 15 | extern struct platform_device mxc_nand_device; |
| 16 | extern struct platform_device mxc_fb_device; | ||
| 17 | extern struct platform_device mxc_fec_device; | ||
| 18 | extern struct platform_device mxc_pwm_device; | ||
| 19 | extern struct platform_device mxc_i2c_device0; | ||
| 20 | extern struct platform_device mxc_i2c_device1; | ||
| 21 | extern struct platform_device mxc_sdhc_device0; | ||
| 22 | extern struct platform_device mxc_sdhc_device1; | ||
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c index dea6521d4d5c..bd51dd04948e 100644 --- a/arch/arm/mach-mx2/generic.c +++ b/arch/arm/mach-mx2/generic.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/mm.h> | 21 | #include <linux/mm.h> |
| 22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/common.h> | ||
| 24 | #include <asm/pgtable.h> | 25 | #include <asm/pgtable.h> |
| 25 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 26 | 27 | ||
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c index 2b5c67f54571..4a3b097adc12 100644 --- a/arch/arm/mach-mx2/mx27ads.c +++ b/arch/arm/mach-mx2/mx27ads.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| 32 | #include <mach/gpio.h> | 32 | #include <mach/gpio.h> |
| 33 | #include <mach/imx-uart.h> | 33 | #include <mach/imx-uart.h> |
| 34 | #include <mach/iomux-mx1-mx2.h> | 34 | #include <mach/iomux.h> |
| 35 | #include <mach/board-mx27ads.h> | 35 | #include <mach/board-mx27ads.h> |
| 36 | 36 | ||
| 37 | #include "devices.h" | 37 | #include "devices.h" |
| @@ -135,6 +135,7 @@ static int uart_mxc_port3_exit(struct platform_device *pdev) | |||
| 135 | { | 135 | { |
| 136 | mxc_gpio_release_multiple_pins(mxc_uart3_pins, | 136 | mxc_gpio_release_multiple_pins(mxc_uart3_pins, |
| 137 | ARRAY_SIZE(mxc_uart3_pins)); | 137 | ARRAY_SIZE(mxc_uart3_pins)); |
| 138 | return 0; | ||
| 138 | } | 139 | } |
| 139 | 140 | ||
| 140 | static int mxc_uart4_pins[] = { | 141 | static int mxc_uart4_pins[] = { |
| @@ -179,6 +180,7 @@ static int uart_mxc_port5_exit(struct platform_device *pdev) | |||
| 179 | 180 | ||
| 180 | static struct platform_device *platform_devices[] __initdata = { | 181 | static struct platform_device *platform_devices[] __initdata = { |
| 181 | &mx27ads_nor_mtd_device, | 182 | &mx27ads_nor_mtd_device, |
| 183 | &mxc_fec_device, | ||
| 182 | }; | 184 | }; |
| 183 | 185 | ||
| 184 | static int mxc_fec_pins[] = { | 186 | static int mxc_fec_pins[] = { |
| @@ -196,7 +198,7 @@ static int mxc_fec_pins[] = { | |||
| 196 | PD11_AOUT_FEC_TX_CLK, | 198 | PD11_AOUT_FEC_TX_CLK, |
| 197 | PD12_AOUT_FEC_RXD0, | 199 | PD12_AOUT_FEC_RXD0, |
| 198 | PD13_AOUT_FEC_RX_DV, | 200 | PD13_AOUT_FEC_RX_DV, |
| 199 | PD14_AOUT_FEC_CLR, | 201 | PD14_AOUT_FEC_RX_CLK, |
| 200 | PD15_AOUT_FEC_COL, | 202 | PD15_AOUT_FEC_COL, |
| 201 | PD16_AIN_FEC_TX_ER, | 203 | PD16_AIN_FEC_TX_ER, |
| 202 | PF23_AIN_FEC_TX_EN | 204 | PF23_AIN_FEC_TX_EN |
| @@ -208,12 +210,6 @@ static void gpio_fec_active(void) | |||
| 208 | ARRAY_SIZE(mxc_fec_pins), "FEC"); | 210 | ARRAY_SIZE(mxc_fec_pins), "FEC"); |
| 209 | } | 211 | } |
| 210 | 212 | ||
| 211 | static void gpio_fec_inactive(void) | ||
| 212 | { | ||
| 213 | mxc_gpio_release_multiple_pins(mxc_fec_pins, | ||
| 214 | ARRAY_SIZE(mxc_fec_pins)); | ||
| 215 | } | ||
| 216 | |||
| 217 | static struct imxuart_platform_data uart_pdata[] = { | 213 | static struct imxuart_platform_data uart_pdata[] = { |
| 218 | { | 214 | { |
| 219 | .init = uart_mxc_port0_init, | 215 | .init = uart_mxc_port0_init, |
| @@ -263,11 +259,10 @@ static void __init mx27ads_timer_init(void) | |||
| 263 | if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) | 259 | if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) |
| 264 | fref = 27000000; | 260 | fref = 27000000; |
| 265 | 261 | ||
| 266 | mxc_clocks_init(fref); | 262 | mx27_clocks_init(fref); |
| 267 | mxc_timer_init("gpt_clk.0"); | ||
| 268 | } | 263 | } |
| 269 | 264 | ||
| 270 | struct sys_timer mx27ads_timer = { | 265 | static struct sys_timer mx27ads_timer = { |
| 271 | .init = mx27ads_timer_init, | 266 | .init = mx27ads_timer_init, |
| 272 | }; | 267 | }; |
| 273 | 268 | ||
| @@ -280,7 +275,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = { | |||
| 280 | }, | 275 | }, |
| 281 | }; | 276 | }; |
| 282 | 277 | ||
| 283 | void __init mx27ads_map_io(void) | 278 | static void __init mx27ads_map_io(void) |
| 284 | { | 279 | { |
| 285 | mxc_map_io(); | 280 | mxc_map_io(); |
| 286 | iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); | 281 | iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); |
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c index dfd4156da7d5..aa4eaa61d1b5 100644 --- a/arch/arm/mach-mx2/pcm038.c +++ b/arch/arm/mach-mx2/pcm038.c | |||
| @@ -20,11 +20,18 @@ | |||
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/mtd/physmap.h> | 21 | #include <linux/mtd/physmap.h> |
| 22 | #include <linux/mtd/plat-ram.h> | 22 | #include <linux/mtd/plat-ram.h> |
| 23 | #include <linux/io.h> | ||
| 24 | #include <linux/i2c.h> | ||
| 25 | #include <linux/i2c/at24.h> | ||
| 26 | |||
| 23 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 25 | #include <mach/common.h> | 29 | #include <mach/common.h> |
| 26 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 27 | #include <mach/iomux-mx1-mx2.h> | 31 | #include <mach/iomux.h> |
| 32 | #ifdef CONFIG_I2C_IMX | ||
| 33 | #include <mach/i2c.h> | ||
| 34 | #endif | ||
| 28 | #include <asm/mach/time.h> | 35 | #include <asm/mach/time.h> |
| 29 | #include <mach/imx-uart.h> | 36 | #include <mach/imx-uart.h> |
| 30 | #include <mach/board-pcm038.h> | 37 | #include <mach/board-pcm038.h> |
| @@ -121,10 +128,10 @@ static int uart_mxc_port1_exit(struct platform_device *pdev) | |||
| 121 | return 0; | 128 | return 0; |
| 122 | } | 129 | } |
| 123 | 130 | ||
| 124 | static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, | 131 | static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD, |
| 125 | PE9_PF_UART3_RXD, | 132 | PE9_PF_UART3_RXD, |
| 126 | PE10_PF_UART3_CTS, | 133 | PE10_PF_UART3_CTS, |
| 127 | PE9_PF_UART3_RXD }; | 134 | PE11_PF_UART3_RTS }; |
| 128 | 135 | ||
| 129 | static int uart_mxc_port2_init(struct platform_device *pdev) | 136 | static int uart_mxc_port2_init(struct platform_device *pdev) |
| 130 | { | 137 | { |
| @@ -170,7 +177,7 @@ static int mxc_fec_pins[] = { | |||
| 170 | PD11_AOUT_FEC_TX_CLK, | 177 | PD11_AOUT_FEC_TX_CLK, |
| 171 | PD12_AOUT_FEC_RXD0, | 178 | PD12_AOUT_FEC_RXD0, |
| 172 | PD13_AOUT_FEC_RX_DV, | 179 | PD13_AOUT_FEC_RX_DV, |
| 173 | PD14_AOUT_FEC_CLR, | 180 | PD14_AOUT_FEC_RX_CLK, |
| 174 | PD15_AOUT_FEC_COL, | 181 | PD15_AOUT_FEC_COL, |
| 175 | PD16_AIN_FEC_TX_ER, | 182 | PD16_AIN_FEC_TX_ER, |
| 176 | PF23_AIN_FEC_TX_EN | 183 | PF23_AIN_FEC_TX_EN |
| @@ -182,12 +189,6 @@ static void gpio_fec_active(void) | |||
| 182 | ARRAY_SIZE(mxc_fec_pins), "FEC"); | 189 | ARRAY_SIZE(mxc_fec_pins), "FEC"); |
| 183 | } | 190 | } |
| 184 | 191 | ||
| 185 | static void gpio_fec_inactive(void) | ||
| 186 | { | ||
| 187 | mxc_gpio_release_multiple_pins(mxc_fec_pins, | ||
| 188 | ARRAY_SIZE(mxc_fec_pins)); | ||
| 189 | } | ||
| 190 | |||
| 191 | static struct mxc_nand_platform_data pcm038_nand_board_info = { | 192 | static struct mxc_nand_platform_data pcm038_nand_board_info = { |
| 192 | .width = 1, | 193 | .width = 1, |
| 193 | .hw_ecc = 1, | 194 | .hw_ecc = 1, |
| @@ -196,6 +197,7 @@ static struct mxc_nand_platform_data pcm038_nand_board_info = { | |||
| 196 | static struct platform_device *platform_devices[] __initdata = { | 197 | static struct platform_device *platform_devices[] __initdata = { |
| 197 | &pcm038_nor_mtd_device, | 198 | &pcm038_nor_mtd_device, |
| 198 | &mxc_w1_master_device, | 199 | &mxc_w1_master_device, |
| 200 | &mxc_fec_device, | ||
| 199 | &pcm038_sram_mtd_device, | 201 | &pcm038_sram_mtd_device, |
| 200 | }; | 202 | }; |
| 201 | 203 | ||
| @@ -208,6 +210,51 @@ static void __init pcm038_init_sram(void) | |||
| 208 | __raw_writel(0x22220a00, CSCR_A(1)); | 210 | __raw_writel(0x22220a00, CSCR_A(1)); |
| 209 | } | 211 | } |
| 210 | 212 | ||
| 213 | #ifdef CONFIG_I2C_IMX | ||
| 214 | static int mxc_i2c1_pins[] = { | ||
| 215 | PC5_PF_I2C2_SDA, | ||
| 216 | PC6_PF_I2C2_SCL | ||
| 217 | }; | ||
| 218 | |||
| 219 | static int pcm038_i2c_1_init(struct device *dev) | ||
| 220 | { | ||
| 221 | return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins), | ||
| 222 | "I2C1"); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void pcm038_i2c_1_exit(struct device *dev) | ||
| 226 | { | ||
| 227 | mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins)); | ||
| 228 | } | ||
| 229 | |||
| 230 | static struct imxi2c_platform_data pcm038_i2c_1_data = { | ||
| 231 | .bitrate = 100000, | ||
| 232 | .init = pcm038_i2c_1_init, | ||
| 233 | .exit = pcm038_i2c_1_exit, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static struct at24_platform_data board_eeprom = { | ||
| 237 | .byte_len = 4096, | ||
| 238 | .page_size = 32, | ||
| 239 | .flags = AT24_FLAG_ADDR16, | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct i2c_board_info pcm038_i2c_devices[] = { | ||
| 243 | [0] = { | ||
| 244 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ | ||
| 245 | .platform_data = &board_eeprom, | ||
| 246 | }, | ||
| 247 | [1] = { | ||
| 248 | I2C_BOARD_INFO("rtc-pcf8563", 0x51), | ||
| 249 | .type = "pcf8563" | ||
| 250 | }, | ||
| 251 | [2] = { | ||
| 252 | I2C_BOARD_INFO("lm75", 0x4a), | ||
| 253 | .type = "lm75" | ||
| 254 | } | ||
| 255 | }; | ||
| 256 | #endif | ||
| 257 | |||
| 211 | static void __init pcm038_init(void) | 258 | static void __init pcm038_init(void) |
| 212 | { | 259 | { |
| 213 | gpio_fec_active(); | 260 | gpio_fec_active(); |
| @@ -217,9 +264,17 @@ static void __init pcm038_init(void) | |||
| 217 | mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); | 264 | mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); |
| 218 | mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); | 265 | mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); |
| 219 | 266 | ||
| 220 | mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */ | 267 | mxc_gpio_mode(PE16_AF_OWIRE); |
| 221 | mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); | 268 | mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); |
| 222 | 269 | ||
| 270 | #ifdef CONFIG_I2C_IMX | ||
| 271 | /* only the i2c master 1 is used on this CPU card */ | ||
| 272 | i2c_register_board_info(1, pcm038_i2c_devices, | ||
| 273 | ARRAY_SIZE(pcm038_i2c_devices)); | ||
| 274 | |||
| 275 | mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); | ||
| 276 | #endif | ||
| 277 | |||
| 223 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 278 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 224 | 279 | ||
| 225 | #ifdef CONFIG_MACH_PCM970_BASEBOARD | 280 | #ifdef CONFIG_MACH_PCM970_BASEBOARD |
| @@ -229,11 +284,10 @@ static void __init pcm038_init(void) | |||
| 229 | 284 | ||
| 230 | static void __init pcm038_timer_init(void) | 285 | static void __init pcm038_timer_init(void) |
| 231 | { | 286 | { |
| 232 | mxc_clocks_init(26000000); | 287 | mx27_clocks_init(26000000); |
| 233 | mxc_timer_init("gpt_clk.0"); | ||
| 234 | } | 288 | } |
| 235 | 289 | ||
| 236 | struct sys_timer pcm038_timer = { | 290 | static struct sys_timer pcm038_timer = { |
| 237 | .init = pcm038_timer_init, | 291 | .init = pcm038_timer_init, |
| 238 | }; | 292 | }; |
| 239 | 293 | ||
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c index a560cd6ad23d..bf4e520bc1bc 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-mx2/pcm970-baseboard.c | |||
| @@ -17,9 +17,138 @@ | |||
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
| 20 | #include <mach/hardware.h> | 20 | #include <linux/gpio.h> |
| 21 | #include <linux/irq.h> | ||
| 22 | |||
| 21 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 22 | 24 | ||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/mmc.h> | ||
| 28 | #include <mach/imxfb.h> | ||
| 29 | #include <mach/iomux.h> | ||
| 30 | |||
| 31 | #include "devices.h" | ||
| 32 | |||
| 33 | static int pcm970_sdhc2_get_ro(struct device *dev) | ||
| 34 | { | ||
| 35 | return gpio_get_value(GPIO_PORTC + 28); | ||
| 36 | } | ||
| 37 | |||
| 38 | static int pcm970_sdhc2_pins[] = { | ||
| 39 | PB4_PF_SD2_D0, | ||
| 40 | PB5_PF_SD2_D1, | ||
| 41 | PB6_PF_SD2_D2, | ||
| 42 | PB7_PF_SD2_D3, | ||
| 43 | PB8_PF_SD2_CMD, | ||
| 44 | PB9_PF_SD2_CLK, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) | ||
| 48 | { | ||
| 49 | int ret; | ||
| 50 | |||
| 51 | ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins, | ||
| 52 | ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2"); | ||
| 53 | if(ret) | ||
| 54 | return ret; | ||
| 55 | |||
| 56 | ret = request_irq(IRQ_GPIOC(29), detect_irq, 0, | ||
| 57 | "imx-mmc-detect", data); | ||
| 58 | if (ret) | ||
| 59 | goto out_release_gpio; | ||
| 60 | |||
| 61 | set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING); | ||
| 62 | |||
| 63 | ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro"); | ||
| 64 | if (ret) | ||
| 65 | goto out_release_gpio; | ||
| 66 | |||
| 67 | mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN); | ||
| 68 | gpio_direction_input(GPIO_PORTC + 28); | ||
| 69 | |||
| 70 | return 0; | ||
| 71 | |||
| 72 | out_release_gpio: | ||
| 73 | mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, | ||
| 74 | ARRAY_SIZE(pcm970_sdhc2_pins)); | ||
| 75 | return ret; | ||
| 76 | } | ||
| 77 | |||
| 78 | static void pcm970_sdhc2_exit(struct device *dev, void *data) | ||
| 79 | { | ||
| 80 | free_irq(IRQ_GPIOC(29), data); | ||
| 81 | gpio_free(GPIO_PORTC + 28); | ||
| 82 | mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, | ||
| 83 | ARRAY_SIZE(pcm970_sdhc2_pins)); | ||
| 84 | } | ||
| 85 | |||
| 86 | static struct imxmmc_platform_data sdhc_pdata = { | ||
| 87 | .get_ro = pcm970_sdhc2_get_ro, | ||
| 88 | .init = pcm970_sdhc2_init, | ||
| 89 | .exit = pcm970_sdhc2_exit, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static int mxc_fb_pins[] = { | ||
| 93 | PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, | ||
| 94 | PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, | ||
| 95 | PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, | ||
| 96 | PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, | ||
| 97 | PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV, | ||
| 98 | PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC, | ||
| 99 | PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD | ||
| 100 | }; | ||
| 101 | |||
| 102 | static int pcm038_fb_init(struct platform_device *pdev) | ||
| 103 | { | ||
| 104 | return mxc_gpio_setup_multiple_pins(mxc_fb_pins, | ||
| 105 | ARRAY_SIZE(mxc_fb_pins), "FB"); | ||
| 106 | } | ||
| 107 | |||
| 108 | static int pcm038_fb_exit(struct platform_device *pdev) | ||
| 109 | { | ||
| 110 | mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins)); | ||
| 111 | |||
| 112 | return 0; | ||
| 113 | } | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Connected is a portrait Sharp-QVGA display | ||
| 117 | * of type: LQ035Q7DH06 | ||
| 118 | */ | ||
| 119 | static struct imx_fb_platform_data pcm038_fb_data = { | ||
| 120 | .pixclock = 188679, /* in ps (5.3MHz) */ | ||
| 121 | .xres = 240, | ||
| 122 | .yres = 320, | ||
| 123 | |||
| 124 | .bpp = 16, | ||
| 125 | .hsync_len = 7, | ||
| 126 | .left_margin = 5, | ||
| 127 | .right_margin = 16, | ||
| 128 | |||
| 129 | .vsync_len = 1, | ||
| 130 | .upper_margin = 7, | ||
| 131 | .lower_margin = 9, | ||
| 132 | .fixed_screen_cpu = 0, | ||
| 133 | |||
| 134 | /* | ||
| 135 | * - HSYNC active high | ||
| 136 | * - VSYNC active high | ||
| 137 | * - clk notenabled while idle | ||
| 138 | * - clock not inverted | ||
| 139 | * - data not inverted | ||
| 140 | * - data enable low active | ||
| 141 | * - enable sharp mode | ||
| 142 | */ | ||
| 143 | .pcr = 0xFA0080C0, | ||
| 144 | .pwmr = 0x00A903FF, | ||
| 145 | .lscr1 = 0x00120300, | ||
| 146 | .dmacr = 0x00020010, | ||
| 147 | |||
| 148 | .init = pcm038_fb_init, | ||
| 149 | .exit = pcm038_fb_exit, | ||
| 150 | }; | ||
| 151 | |||
| 23 | /* | 152 | /* |
| 24 | * system init for baseboard usage. Will be called by pcm038 init. | 153 | * system init for baseboard usage. Will be called by pcm038 init. |
| 25 | * | 154 | * |
| @@ -28,4 +157,6 @@ | |||
| 28 | */ | 157 | */ |
| 29 | void __init pcm970_baseboard_init(void) | 158 | void __init pcm970_baseboard_init(void) |
| 30 | { | 159 | { |
| 160 | mxc_register_device(&mxc_fb_device, &pcm038_fb_data); | ||
| 161 | mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); | ||
| 31 | } | 162 | } |
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c index 16debc296dad..40a485cdc10e 100644 --- a/arch/arm/mach-mx2/serial.c +++ b/arch/arm/mach-mx2/serial.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/serial.h> | 22 | #include <linux/serial.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/imx-uart.h> | 24 | #include <mach/imx-uart.h> |
| 25 | #include "devices.h" | ||
| 25 | 26 | ||
| 26 | static struct resource uart0[] = { | 27 | static struct resource uart0[] = { |
| 27 | { | 28 | { |
| @@ -99,6 +100,7 @@ struct platform_device mxc_uart_device3 = { | |||
| 99 | .num_resources = ARRAY_SIZE(uart3), | 100 | .num_resources = ARRAY_SIZE(uart3), |
| 100 | }; | 101 | }; |
| 101 | 102 | ||
| 103 | #ifdef CONFIG_MACH_MX27 | ||
| 102 | static struct resource uart4[] = { | 104 | static struct resource uart4[] = { |
| 103 | { | 105 | { |
| 104 | .start = UART5_BASE_ADDR, | 106 | .start = UART5_BASE_ADDR, |
| @@ -136,3 +138,4 @@ struct platform_device mxc_uart_device5 = { | |||
| 136 | .resource = uart5, | 138 | .resource = uart5, |
| 137 | .num_resources = ARRAY_SIZE(uart5), | 139 | .num_resources = ARRAY_SIZE(uart5), |
| 138 | }; | 140 | }; |
| 141 | #endif | ||
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index e79659e8176e..d6235583e979 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig | |||
| @@ -1,21 +1,40 @@ | |||
| 1 | menu "MX3 Options" | 1 | if ARCH_MX3 |
| 2 | depends on ARCH_MX3 | 2 | |
| 3 | config ARCH_MX31 | ||
| 4 | bool | ||
| 5 | |||
| 6 | config ARCH_MX35 | ||
| 7 | bool | ||
| 8 | |||
| 9 | comment "MX3 platforms:" | ||
| 3 | 10 | ||
| 4 | config MACH_MX31ADS | 11 | config MACH_MX31ADS |
| 5 | bool "Support MX31ADS platforms" | 12 | bool "Support MX31ADS platforms" |
| 13 | select ARCH_MX31 | ||
| 6 | default y | 14 | default y |
| 7 | help | 15 | help |
| 8 | Include support for MX31ADS platform. This includes specific | 16 | Include support for MX31ADS platform. This includes specific |
| 9 | configurations for the board and its peripherals. | 17 | configurations for the board and its peripherals. |
| 10 | 18 | ||
| 19 | config MACH_MX31ADS_WM1133_EV1 | ||
| 20 | bool "Support Wolfson Microelectronics 1133-EV1 module" | ||
| 21 | depends on MACH_MX31ADS | ||
| 22 | select MFD_WM8350_CONFIG_MODE_0 | ||
| 23 | select MFD_WM8352_CONFIG_MODE_0 | ||
| 24 | help | ||
| 25 | Include support for the Wolfson Microelectronics 1133-EV1 PMU | ||
| 26 | and audio module for the MX31ADS platform. | ||
| 27 | |||
| 11 | config MACH_PCM037 | 28 | config MACH_PCM037 |
| 12 | bool "Support Phytec pcm037 platforms" | 29 | bool "Support Phytec pcm037 (i.MX31) platforms" |
| 30 | select ARCH_MX31 | ||
| 13 | help | 31 | help |
| 14 | Include support for Phytec pcm037 platform. This includes | 32 | Include support for Phytec pcm037 platform. This includes |
| 15 | specific configurations for the board and its peripherals. | 33 | specific configurations for the board and its peripherals. |
| 16 | 34 | ||
| 17 | config MACH_MX31LITE | 35 | config MACH_MX31LITE |
| 18 | bool "Support MX31 LITEKIT (LogicPD)" | 36 | bool "Support MX31 LITEKIT (LogicPD)" |
| 37 | select ARCH_MX31 | ||
| 19 | default n | 38 | default n |
| 20 | help | 39 | help |
| 21 | Include support for MX31 LITEKIT platform. This includes specific | 40 | Include support for MX31 LITEKIT platform. This includes specific |
| @@ -23,6 +42,7 @@ config MACH_MX31LITE | |||
| 23 | 42 | ||
| 24 | config MACH_MX31_3DS | 43 | config MACH_MX31_3DS |
| 25 | bool "Support MX31PDK (3DS)" | 44 | bool "Support MX31PDK (3DS)" |
| 45 | select ARCH_MX31 | ||
| 26 | default n | 46 | default n |
| 27 | help | 47 | help |
| 28 | Include support for MX31PDK (3DS) platform. This includes specific | 48 | Include support for MX31PDK (3DS) platform. This includes specific |
| @@ -30,10 +50,18 @@ config MACH_MX31_3DS | |||
| 30 | 50 | ||
| 31 | config MACH_MX31MOBOARD | 51 | config MACH_MX31MOBOARD |
| 32 | bool "Support mx31moboard platforms (EPFL Mobots group)" | 52 | bool "Support mx31moboard platforms (EPFL Mobots group)" |
| 53 | select ARCH_MX31 | ||
| 33 | default n | 54 | default n |
| 34 | help | 55 | help |
| 35 | Include support for mx31moboard platform. This includes specific | 56 | Include support for mx31moboard platform. This includes specific |
| 36 | configurations for the board and its peripherals. | 57 | configurations for the board and its peripherals. |
| 37 | 58 | ||
| 38 | endmenu | 59 | config MACH_QONG |
| 60 | bool "Support Dave/DENX QongEVB-LITE platform" | ||
| 61 | select ARCH_MX31 | ||
| 62 | default n | ||
| 63 | help | ||
| 64 | Include support for Dave/DENX QongEVB-LITE platform. This includes | ||
| 65 | specific configurations for the board and its peripherals. | ||
| 39 | 66 | ||
| 67 | endif | ||
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 5a151540fe83..272c8a953b30 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile | |||
| @@ -4,9 +4,13 @@ | |||
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | 6 | ||
| 7 | obj-y := mm.o clock.o devices.o iomux.o | 7 | obj-y := mm.o devices.o |
| 8 | obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o | ||
| 9 | obj-$(CONFIG_ARCH_MX35) += clock-imx35.o | ||
| 8 | obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o | 10 | obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o |
| 9 | obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o | 11 | obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o |
| 10 | obj-$(CONFIG_MACH_PCM037) += pcm037.o | 12 | obj-$(CONFIG_MACH_PCM037) += pcm037.o |
| 11 | obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o | 13 | obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o |
| 12 | obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o | 14 | obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ |
| 15 | mx31moboard-marxbot.o | ||
| 16 | obj-$(CONFIG_MACH_QONG) += qong.o | ||
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c new file mode 100644 index 000000000000..53a112d4e04a --- /dev/null +++ b/arch/arm/mach-mx3/clock-imx35.c | |||
| @@ -0,0 +1,487 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 by Sascha Hauer, Pengutronix | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/list.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include <asm/clkdev.h> | ||
| 26 | |||
| 27 | #include <mach/clock.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/common.h> | ||
| 30 | |||
| 31 | #define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) | ||
| 32 | |||
| 33 | #define CCM_CCMR 0x00 | ||
| 34 | #define CCM_PDR0 0x04 | ||
| 35 | #define CCM_PDR1 0x08 | ||
| 36 | #define CCM_PDR2 0x0C | ||
| 37 | #define CCM_PDR3 0x10 | ||
| 38 | #define CCM_PDR4 0x14 | ||
| 39 | #define CCM_RCSR 0x18 | ||
| 40 | #define CCM_MPCTL 0x1C | ||
| 41 | #define CCM_PPCTL 0x20 | ||
| 42 | #define CCM_ACMR 0x24 | ||
| 43 | #define CCM_COSR 0x28 | ||
| 44 | #define CCM_CGR0 0x2C | ||
| 45 | #define CCM_CGR1 0x30 | ||
| 46 | #define CCM_CGR2 0x34 | ||
| 47 | #define CCM_CGR3 0x38 | ||
| 48 | |||
| 49 | #ifdef HAVE_SET_RATE_SUPPORT | ||
| 50 | static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost) | ||
| 51 | { | ||
| 52 | u32 min_pre, temp_pre, old_err, err; | ||
| 53 | |||
| 54 | min_pre = (div - 1) / maxpost + 1; | ||
| 55 | old_err = 8; | ||
| 56 | |||
| 57 | for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { | ||
| 58 | if (div > (temp_pre * maxpost)) | ||
| 59 | break; | ||
| 60 | |||
| 61 | if (div < (temp_pre * temp_pre)) | ||
| 62 | continue; | ||
| 63 | |||
| 64 | err = div % temp_pre; | ||
| 65 | |||
| 66 | if (err == 0) { | ||
| 67 | *pre = temp_pre; | ||
| 68 | break; | ||
| 69 | } | ||
| 70 | |||
| 71 | err = temp_pre - err; | ||
| 72 | |||
| 73 | if (err < old_err) { | ||
| 74 | old_err = err; | ||
| 75 | *pre = temp_pre; | ||
| 76 | } | ||
| 77 | } | ||
| 78 | |||
| 79 | *post = (div + *pre - 1) / *pre; | ||
| 80 | } | ||
| 81 | |||
| 82 | /* get the best values for a 3-bit divider combined with a 6-bit divider */ | ||
| 83 | static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post) | ||
| 84 | { | ||
| 85 | if (div >= 512) { | ||
| 86 | *pre = 8; | ||
| 87 | *post = 64; | ||
| 88 | } else if (div >= 64) { | ||
| 89 | calc_dividers(div, pre, post, 64); | ||
| 90 | } else if (div <= 8) { | ||
| 91 | *pre = div; | ||
| 92 | *post = 1; | ||
| 93 | } else { | ||
| 94 | *pre = 1; | ||
| 95 | *post = div; | ||
| 96 | } | ||
| 97 | } | ||
| 98 | |||
| 99 | /* get the best values for two cascaded 3-bit dividers */ | ||
| 100 | static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post) | ||
| 101 | { | ||
| 102 | if (div >= 64) { | ||
| 103 | *pre = *post = 8; | ||
| 104 | } else if (div > 8) { | ||
| 105 | calc_dividers(div, pre, post, 8); | ||
| 106 | } else { | ||
| 107 | *pre = 1; | ||
| 108 | *post = div; | ||
| 109 | } | ||
| 110 | } | ||
| 111 | #endif | ||
| 112 | |||
| 113 | static unsigned long get_rate_mpll(void) | ||
| 114 | { | ||
| 115 | ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL); | ||
| 116 | |||
| 117 | return mxc_decode_pll(mpctl, 24000000); | ||
| 118 | } | ||
| 119 | |||
| 120 | static unsigned long get_rate_ppll(void) | ||
| 121 | { | ||
| 122 | ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL); | ||
| 123 | |||
| 124 | return mxc_decode_pll(ppctl, 24000000); | ||
| 125 | } | ||
| 126 | |||
| 127 | struct arm_ahb_div { | ||
| 128 | unsigned char arm, ahb, sel; | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct arm_ahb_div clk_consumer[] = { | ||
| 132 | { .arm = 1, .ahb = 4, .sel = 0}, | ||
| 133 | { .arm = 1, .ahb = 3, .sel = 1}, | ||
| 134 | { .arm = 2, .ahb = 2, .sel = 0}, | ||
| 135 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 136 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 137 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 138 | { .arm = 4, .ahb = 1, .sel = 0}, | ||
| 139 | { .arm = 1, .ahb = 5, .sel = 0}, | ||
| 140 | { .arm = 1, .ahb = 8, .sel = 0}, | ||
| 141 | { .arm = 1, .ahb = 6, .sel = 1}, | ||
| 142 | { .arm = 2, .ahb = 4, .sel = 0}, | ||
| 143 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 144 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 145 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 146 | { .arm = 4, .ahb = 2, .sel = 0}, | ||
| 147 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static struct arm_ahb_div clk_automotive[] = { | ||
| 151 | { .arm = 1, .ahb = 3, .sel = 0}, | ||
| 152 | { .arm = 1, .ahb = 2, .sel = 1}, | ||
| 153 | { .arm = 2, .ahb = 1, .sel = 1}, | ||
| 154 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 155 | { .arm = 1, .ahb = 6, .sel = 0}, | ||
| 156 | { .arm = 1, .ahb = 4, .sel = 1}, | ||
| 157 | { .arm = 2, .ahb = 2, .sel = 1}, | ||
| 158 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static unsigned long get_rate_arm(void) | ||
| 162 | { | ||
| 163 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | ||
| 164 | struct arm_ahb_div *aad; | ||
| 165 | unsigned long fref = get_rate_mpll(); | ||
| 166 | |||
| 167 | if (pdr0 & 1) { | ||
| 168 | /* consumer path */ | ||
| 169 | aad = &clk_consumer[(pdr0 >> 16) & 0xf]; | ||
| 170 | if (aad->sel) | ||
| 171 | fref = fref * 2 / 3; | ||
| 172 | } else { | ||
| 173 | /* auto path */ | ||
| 174 | aad = &clk_automotive[(pdr0 >> 9) & 0x7]; | ||
| 175 | if (aad->sel) | ||
| 176 | fref = fref * 3 / 4; | ||
| 177 | } | ||
| 178 | return fref / aad->arm; | ||
| 179 | } | ||
| 180 | |||
| 181 | static unsigned long get_rate_ahb(struct clk *clk) | ||
| 182 | { | ||
| 183 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | ||
| 184 | struct arm_ahb_div *aad; | ||
| 185 | unsigned long fref = get_rate_mpll(); | ||
| 186 | |||
| 187 | if (pdr0 & 1) | ||
| 188 | /* consumer path */ | ||
| 189 | aad = &clk_consumer[(pdr0 >> 16) & 0xf]; | ||
| 190 | else | ||
| 191 | /* auto path */ | ||
| 192 | aad = &clk_automotive[(pdr0 >> 9) & 0x7]; | ||
| 193 | |||
| 194 | return fref / aad->ahb; | ||
| 195 | } | ||
| 196 | |||
| 197 | static unsigned long get_rate_ipg(struct clk *clk) | ||
| 198 | { | ||
| 199 | return get_rate_ahb(NULL) >> 1; | ||
| 200 | } | ||
| 201 | |||
| 202 | static unsigned long get_3_3_div(unsigned long in) | ||
| 203 | { | ||
| 204 | return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1); | ||
| 205 | } | ||
| 206 | |||
| 207 | static unsigned long get_rate_uart(struct clk *clk) | ||
| 208 | { | ||
| 209 | unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); | ||
| 210 | unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); | ||
| 211 | unsigned long div = get_3_3_div(pdr4 >> 10); | ||
| 212 | |||
| 213 | if (pdr3 & (1 << 14)) | ||
| 214 | return get_rate_arm() / div; | ||
| 215 | else | ||
| 216 | return get_rate_ppll() / div; | ||
| 217 | } | ||
| 218 | |||
| 219 | static unsigned long get_rate_sdhc(struct clk *clk) | ||
| 220 | { | ||
| 221 | unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); | ||
| 222 | unsigned long div, rate; | ||
| 223 | |||
| 224 | if (pdr3 & (1 << 6)) | ||
| 225 | rate = get_rate_arm(); | ||
| 226 | else | ||
| 227 | rate = get_rate_ppll(); | ||
| 228 | |||
| 229 | switch (clk->id) { | ||
| 230 | default: | ||
| 231 | case 0: | ||
| 232 | div = pdr3 & 0x3f; | ||
| 233 | break; | ||
| 234 | case 1: | ||
| 235 | div = (pdr3 >> 8) & 0x3f; | ||
| 236 | break; | ||
| 237 | case 2: | ||
| 238 | div = (pdr3 >> 16) & 0x3f; | ||
| 239 | break; | ||
| 240 | } | ||
| 241 | |||
| 242 | return rate / get_3_3_div(div); | ||
| 243 | } | ||
| 244 | |||
| 245 | static unsigned long get_rate_mshc(struct clk *clk) | ||
| 246 | { | ||
| 247 | unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1); | ||
| 248 | unsigned long div1, div2, rate; | ||
| 249 | |||
| 250 | if (pdr1 & (1 << 7)) | ||
| 251 | rate = get_rate_arm(); | ||
| 252 | else | ||
| 253 | rate = get_rate_ppll(); | ||
| 254 | |||
| 255 | div1 = (pdr1 >> 29) & 0x7; | ||
| 256 | div2 = (pdr1 >> 22) & 0x3f; | ||
| 257 | |||
| 258 | return rate / ((div1 + 1) * (div2 + 1)); | ||
| 259 | } | ||
| 260 | |||
| 261 | static unsigned long get_rate_ssi(struct clk *clk) | ||
| 262 | { | ||
| 263 | unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); | ||
| 264 | unsigned long div1, div2, rate; | ||
| 265 | |||
| 266 | if (pdr2 & (1 << 6)) | ||
| 267 | rate = get_rate_arm(); | ||
| 268 | else | ||
| 269 | rate = get_rate_ppll(); | ||
| 270 | |||
| 271 | switch (clk->id) { | ||
| 272 | default: | ||
| 273 | case 0: | ||
| 274 | div1 = pdr2 & 0x3f; | ||
| 275 | div2 = (pdr2 >> 24) & 0x7; | ||
| 276 | break; | ||
| 277 | case 1: | ||
| 278 | div1 = (pdr2 >> 8) & 0x3f; | ||
| 279 | div2 = (pdr2 >> 27) & 0x7; | ||
| 280 | break; | ||
| 281 | } | ||
| 282 | |||
| 283 | return rate / ((div1 + 1) * (div2 + 1)); | ||
| 284 | } | ||
| 285 | |||
| 286 | static unsigned long get_rate_csi(struct clk *clk) | ||
| 287 | { | ||
| 288 | unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); | ||
| 289 | unsigned long rate; | ||
| 290 | |||
| 291 | if (pdr2 & (1 << 7)) | ||
| 292 | rate = get_rate_arm(); | ||
| 293 | else | ||
| 294 | rate = get_rate_ppll(); | ||
| 295 | |||
| 296 | return rate / get_3_3_div((pdr2 >> 16) & 0x3f); | ||
| 297 | } | ||
| 298 | |||
| 299 | static unsigned long get_rate_ipg_per(struct clk *clk) | ||
| 300 | { | ||
| 301 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | ||
| 302 | unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); | ||
| 303 | unsigned long div1, div2; | ||
| 304 | |||
| 305 | if (pdr0 & (1 << 26)) { | ||
| 306 | div1 = (pdr4 >> 19) & 0x7; | ||
| 307 | div2 = (pdr4 >> 16) & 0x7; | ||
| 308 | return get_rate_arm() / ((div1 + 1) * (div2 + 1)); | ||
| 309 | } else { | ||
| 310 | div1 = (pdr0 >> 12) & 0x7; | ||
| 311 | return get_rate_ahb(NULL) / div1; | ||
| 312 | } | ||
| 313 | } | ||
| 314 | |||
| 315 | static int clk_cgr_enable(struct clk *clk) | ||
| 316 | { | ||
| 317 | u32 reg; | ||
| 318 | |||
| 319 | reg = __raw_readl(clk->enable_reg); | ||
| 320 | reg |= 3 << clk->enable_shift; | ||
| 321 | __raw_writel(reg, clk->enable_reg); | ||
| 322 | |||
| 323 | return 0; | ||
| 324 | } | ||
| 325 | |||
| 326 | static void clk_cgr_disable(struct clk *clk) | ||
| 327 | { | ||
| 328 | u32 reg; | ||
| 329 | |||
| 330 | reg = __raw_readl(clk->enable_reg); | ||
| 331 | reg &= ~(3 << clk->enable_shift); | ||
| 332 | __raw_writel(reg, clk->enable_reg); | ||
| 333 | } | ||
| 334 | |||
| 335 | #define DEFINE_CLOCK(name, i, er, es, gr, sr) \ | ||
| 336 | static struct clk name = { \ | ||
| 337 | .id = i, \ | ||
| 338 | .enable_reg = CCM_BASE + er, \ | ||
| 339 | .enable_shift = es, \ | ||
| 340 | .get_rate = gr, \ | ||
| 341 | .set_rate = sr, \ | ||
| 342 | .enable = clk_cgr_enable, \ | ||
| 343 | .disable = clk_cgr_disable, \ | ||
| 344 | } | ||
| 345 | |||
| 346 | DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); | ||
| 347 | DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); | ||
| 348 | DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); | ||
| 349 | DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); | ||
| 350 | DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); | ||
| 351 | DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); | ||
| 352 | DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL); | ||
| 353 | DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); | ||
| 354 | DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); | ||
| 355 | DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); | ||
| 356 | DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL); | ||
| 357 | DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL); | ||
| 358 | DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); | ||
| 359 | DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); | ||
| 360 | DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); | ||
| 361 | DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL); | ||
| 362 | |||
| 363 | DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL); | ||
| 364 | DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL); | ||
| 365 | DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL); | ||
| 366 | DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL); | ||
| 367 | DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL); | ||
| 368 | DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL); | ||
| 369 | DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); | ||
| 370 | DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); | ||
| 371 | DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); | ||
| 372 | DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL); | ||
| 373 | DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); | ||
| 374 | DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); | ||
| 375 | DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); | ||
| 376 | DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL); | ||
| 377 | DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL); | ||
| 378 | DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL); | ||
| 379 | |||
| 380 | DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL); | ||
| 381 | DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL); | ||
| 382 | DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL); | ||
| 383 | DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL); | ||
| 384 | DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL); | ||
| 385 | DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL); | ||
| 386 | DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL); | ||
| 387 | DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL); | ||
| 388 | DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL); | ||
| 389 | DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL); | ||
| 390 | DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL); | ||
| 391 | DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL); | ||
| 392 | DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); | ||
| 393 | DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); | ||
| 394 | DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); | ||
| 395 | |||
| 396 | DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); | ||
| 397 | DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); | ||
| 398 | DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); | ||
| 399 | |||
| 400 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 401 | { \ | ||
| 402 | .dev_id = d, \ | ||
| 403 | .con_id = n, \ | ||
| 404 | .clk = &c, \ | ||
| 405 | }, | ||
| 406 | |||
| 407 | static struct clk_lookup lookups[] __initdata = { | ||
| 408 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) | ||
| 409 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | ||
| 410 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) | ||
| 411 | _REGISTER_CLOCK(NULL, "can", can1_clk) | ||
| 412 | _REGISTER_CLOCK(NULL, "can", can2_clk) | ||
| 413 | _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) | ||
| 414 | _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) | ||
| 415 | _REGISTER_CLOCK(NULL, "ect", ect_clk) | ||
| 416 | _REGISTER_CLOCK(NULL, "edio", edio_clk) | ||
| 417 | _REGISTER_CLOCK(NULL, "emi", emi_clk) | ||
| 418 | _REGISTER_CLOCK(NULL, "epit", epit1_clk) | ||
| 419 | _REGISTER_CLOCK(NULL, "epit", epit2_clk) | ||
| 420 | _REGISTER_CLOCK(NULL, "esai", esai_clk) | ||
| 421 | _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) | ||
| 422 | _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) | ||
| 423 | _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk) | ||
| 424 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | ||
| 425 | _REGISTER_CLOCK(NULL, "gpio", gpio1_clk) | ||
| 426 | _REGISTER_CLOCK(NULL, "gpio", gpio2_clk) | ||
| 427 | _REGISTER_CLOCK(NULL, "gpio", gpio3_clk) | ||
| 428 | _REGISTER_CLOCK("gpt.0", NULL, gpt_clk) | ||
| 429 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) | ||
| 430 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | ||
| 431 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) | ||
| 432 | _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk) | ||
| 433 | _REGISTER_CLOCK(NULL, "ipu", ipu_clk) | ||
| 434 | _REGISTER_CLOCK(NULL, "kpp", kpp_clk) | ||
| 435 | _REGISTER_CLOCK(NULL, "mlb", mlb_clk) | ||
| 436 | _REGISTER_CLOCK(NULL, "mshc", mshc_clk) | ||
| 437 | _REGISTER_CLOCK("mxc_w1", NULL, owire_clk) | ||
| 438 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | ||
| 439 | _REGISTER_CLOCK(NULL, "rngc", rngc_clk) | ||
| 440 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | ||
| 441 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) | ||
| 442 | _REGISTER_CLOCK(NULL, "scc", scc_clk) | ||
| 443 | _REGISTER_CLOCK(NULL, "sdma", sdma_clk) | ||
| 444 | _REGISTER_CLOCK(NULL, "spba", spba_clk) | ||
| 445 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) | ||
| 446 | _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) | ||
| 447 | _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) | ||
| 448 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | ||
| 449 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | ||
| 450 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | ||
| 451 | _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk) | ||
| 452 | _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk) | ||
| 453 | _REGISTER_CLOCK(NULL, "max", max_clk) | ||
| 454 | _REGISTER_CLOCK(NULL, "admux", admux_clk) | ||
| 455 | _REGISTER_CLOCK(NULL, "csi", csi_clk) | ||
| 456 | _REGISTER_CLOCK(NULL, "iim", iim_clk) | ||
| 457 | _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) | ||
| 458 | }; | ||
| 459 | |||
| 460 | int __init mx35_clocks_init() | ||
| 461 | { | ||
| 462 | int i; | ||
| 463 | unsigned int ll = 0; | ||
| 464 | |||
| 465 | mxc_set_cpu_type(MXC_CPU_MX35); | ||
| 466 | |||
| 467 | #ifdef CONFIG_DEBUG_LL_CONSOLE | ||
| 468 | ll = (3 << 16); | ||
| 469 | #endif | ||
| 470 | |||
| 471 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | ||
| 472 | clkdev_add(&lookups[i]); | ||
| 473 | |||
| 474 | /* Turn off all clocks except the ones we need to survive, namely: | ||
| 475 | * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart | ||
| 476 | */ | ||
| 477 | __raw_writel((3 << 18), CCM_BASE + CCM_CGR0); | ||
| 478 | __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16), | ||
| 479 | CCM_BASE + CCM_CGR1); | ||
| 480 | __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); | ||
| 481 | __raw_writel(0, CCM_BASE + CCM_CGR3); | ||
| 482 | |||
| 483 | mxc_timer_init(&gpt_clk); | ||
| 484 | |||
| 485 | return 0; | ||
| 486 | } | ||
| 487 | |||
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index b1746aae1f89..ca46f4801c3d 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c | |||
| @@ -23,9 +23,13 @@ | |||
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/err.h> | 24 | #include <linux/err.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | |||
| 27 | #include <asm/clkdev.h> | ||
| 28 | #include <asm/div64.h> | ||
| 29 | |||
| 26 | #include <mach/clock.h> | 30 | #include <mach/clock.h> |
| 27 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 28 | #include <asm/div64.h> | 32 | #include <mach/common.h> |
| 29 | 33 | ||
| 30 | #include "crm_regs.h" | 34 | #include "crm_regs.h" |
| 31 | 35 | ||
| @@ -64,17 +68,17 @@ static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) | |||
| 64 | } | 68 | } |
| 65 | 69 | ||
| 66 | static struct clk mcu_pll_clk; | 70 | static struct clk mcu_pll_clk; |
| 67 | static struct clk mcu_main_clk; | ||
| 68 | static struct clk usb_pll_clk; | ||
| 69 | static struct clk serial_pll_clk; | 71 | static struct clk serial_pll_clk; |
| 70 | static struct clk ipg_clk; | 72 | static struct clk ipg_clk; |
| 71 | static struct clk ckih_clk; | 73 | static struct clk ckih_clk; |
| 72 | static struct clk ahb_clk; | ||
| 73 | 74 | ||
| 74 | static int _clk_enable(struct clk *clk) | 75 | static int cgr_enable(struct clk *clk) |
| 75 | { | 76 | { |
| 76 | u32 reg; | 77 | u32 reg; |
| 77 | 78 | ||
| 79 | if (!clk->enable_reg) | ||
| 80 | return 0; | ||
| 81 | |||
| 78 | reg = __raw_readl(clk->enable_reg); | 82 | reg = __raw_readl(clk->enable_reg); |
| 79 | reg |= 3 << clk->enable_shift; | 83 | reg |= 3 << clk->enable_shift; |
| 80 | __raw_writel(reg, clk->enable_reg); | 84 | __raw_writel(reg, clk->enable_reg); |
| @@ -82,133 +86,69 @@ static int _clk_enable(struct clk *clk) | |||
| 82 | return 0; | 86 | return 0; |
| 83 | } | 87 | } |
| 84 | 88 | ||
| 85 | static void _clk_disable(struct clk *clk) | 89 | static void cgr_disable(struct clk *clk) |
| 86 | { | 90 | { |
| 87 | u32 reg; | 91 | u32 reg; |
| 88 | 92 | ||
| 93 | if (!clk->enable_reg) | ||
| 94 | return; | ||
| 95 | |||
| 89 | reg = __raw_readl(clk->enable_reg); | 96 | reg = __raw_readl(clk->enable_reg); |
| 90 | reg &= ~(3 << clk->enable_shift); | 97 | reg &= ~(3 << clk->enable_shift); |
| 98 | |||
| 99 | /* special case for EMI clock */ | ||
| 100 | if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8) | ||
| 101 | reg |= (1 << clk->enable_shift); | ||
| 102 | |||
| 91 | __raw_writel(reg, clk->enable_reg); | 103 | __raw_writel(reg, clk->enable_reg); |
| 92 | } | 104 | } |
| 93 | 105 | ||
| 94 | static void _clk_emi_disable(struct clk *clk) | 106 | static unsigned long pll_ref_get_rate(void) |
| 95 | { | 107 | { |
| 96 | u32 reg; | 108 | unsigned long ccmr; |
| 109 | unsigned int prcs; | ||
| 97 | 110 | ||
| 98 | reg = __raw_readl(clk->enable_reg); | 111 | ccmr = __raw_readl(MXC_CCM_CCMR); |
| 99 | reg &= ~(3 << clk->enable_shift); | 112 | prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET; |
| 100 | reg |= (1 << clk->enable_shift); | 113 | if (prcs == 0x1) |
| 101 | __raw_writel(reg, clk->enable_reg); | 114 | return CKIL_CLK_FREQ * 1024; |
| 115 | else | ||
| 116 | return clk_get_rate(&ckih_clk); | ||
| 102 | } | 117 | } |
| 103 | 118 | ||
| 104 | static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) | 119 | static unsigned long usb_pll_get_rate(struct clk *clk) |
| 105 | { | 120 | { |
| 106 | u32 reg; | 121 | unsigned long reg; |
| 107 | signed long pd = 1; /* Pre-divider */ | ||
| 108 | signed long mfi; /* Multiplication Factor (Integer part) */ | ||
| 109 | signed long mfn; /* Multiplication Factor (Integer part) */ | ||
| 110 | signed long mfd; /* Multiplication Factor (Denominator Part) */ | ||
| 111 | signed long tmp; | ||
| 112 | u32 ref_freq = clk_get_rate(clk->parent); | ||
| 113 | 122 | ||
| 114 | while (((ref_freq / pd) * 10) > rate) | 123 | reg = __raw_readl(MXC_CCM_UPCTL); |
| 115 | pd++; | ||
| 116 | 124 | ||
| 117 | if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) | 125 | return mxc_decode_pll(reg, pll_ref_get_rate()); |
| 118 | return -EINVAL; | 126 | } |
| 119 | 127 | ||
| 120 | /* the ref_freq/2 in the following is to round up */ | 128 | static unsigned long serial_pll_get_rate(struct clk *clk) |
| 121 | mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; | 129 | { |
| 122 | if (mfi < 5 || mfi > 15) | 130 | unsigned long reg; |
| 123 | return -EINVAL; | ||
| 124 | 131 | ||
| 125 | /* pick a mfd value that will work | 132 | reg = __raw_readl(MXC_CCM_SRPCTL); |
| 126 | * then solve for mfn */ | ||
| 127 | mfd = ref_freq / 50000; | ||
| 128 | |||
| 129 | /* | ||
| 130 | * pll_freq * pd * mfd | ||
| 131 | * mfn = -------------------- - (mfi * mfd) | ||
| 132 | * 2 * ref_freq | ||
| 133 | */ | ||
| 134 | /* the tmp/2 is for rounding */ | ||
| 135 | tmp = ref_freq / 10000; | ||
| 136 | mfn = | ||
| 137 | ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) - | ||
| 138 | (mfi * mfd); | ||
| 139 | |||
| 140 | mfn = mfn & 0x3ff; | ||
| 141 | pd--; | ||
| 142 | mfd--; | ||
| 143 | |||
| 144 | /* Change the Pll value */ | ||
| 145 | reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) | | ||
| 146 | (mfn << MXC_CCM_PCTL_MFN_OFFSET) | | ||
| 147 | (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET); | ||
| 148 | |||
| 149 | if (clk == &mcu_pll_clk) | ||
| 150 | __raw_writel(reg, MXC_CCM_MPCTL); | ||
| 151 | else if (clk == &usb_pll_clk) | ||
| 152 | __raw_writel(reg, MXC_CCM_UPCTL); | ||
| 153 | else if (clk == &serial_pll_clk) | ||
| 154 | __raw_writel(reg, MXC_CCM_SRPCTL); | ||
| 155 | 133 | ||
| 156 | return 0; | 134 | return mxc_decode_pll(reg, pll_ref_get_rate()); |
| 157 | } | 135 | } |
| 158 | 136 | ||
| 159 | static unsigned long _clk_pll_get_rate(struct clk *clk) | 137 | static unsigned long mcu_pll_get_rate(struct clk *clk) |
| 160 | { | 138 | { |
| 161 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; | ||
| 162 | unsigned long reg, ccmr; | 139 | unsigned long reg, ccmr; |
| 163 | s64 temp; | ||
| 164 | unsigned int prcs; | ||
| 165 | 140 | ||
| 166 | ccmr = __raw_readl(MXC_CCM_CCMR); | 141 | ccmr = __raw_readl(MXC_CCM_CCMR); |
| 167 | prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET; | ||
| 168 | if (prcs == 0x1) | ||
| 169 | ref_clk = CKIL_CLK_FREQ * 1024; | ||
| 170 | else | ||
| 171 | ref_clk = clk_get_rate(&ckih_clk); | ||
| 172 | |||
| 173 | if (clk == &mcu_pll_clk) { | ||
| 174 | if ((ccmr & MXC_CCM_CCMR_MPE) == 0) | ||
| 175 | return ref_clk; | ||
| 176 | if ((ccmr & MXC_CCM_CCMR_MDS) != 0) | ||
| 177 | return ref_clk; | ||
| 178 | reg = __raw_readl(MXC_CCM_MPCTL); | ||
| 179 | } else if (clk == &usb_pll_clk) | ||
| 180 | reg = __raw_readl(MXC_CCM_UPCTL); | ||
| 181 | else if (clk == &serial_pll_clk) | ||
| 182 | reg = __raw_readl(MXC_CCM_SRPCTL); | ||
| 183 | else { | ||
| 184 | BUG(); | ||
| 185 | return 0; | ||
| 186 | } | ||
| 187 | |||
| 188 | pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET; | ||
| 189 | mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET; | ||
| 190 | mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET; | ||
| 191 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 192 | mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK; | ||
| 193 | 142 | ||
| 194 | if (mfn >= 0x200) { | 143 | if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS)) |
| 195 | mfn |= 0xFFFFFE00; | 144 | return clk_get_rate(&ckih_clk); |
| 196 | mfn_abs = -mfn; | ||
| 197 | } | ||
| 198 | |||
| 199 | ref_clk *= 2; | ||
| 200 | ref_clk /= pdf + 1; | ||
| 201 | 145 | ||
| 202 | temp = (u64) ref_clk * mfn_abs; | 146 | reg = __raw_readl(MXC_CCM_MPCTL); |
| 203 | do_div(temp, mfd + 1); | ||
| 204 | if (mfn < 0) | ||
| 205 | temp = -temp; | ||
| 206 | temp = (ref_clk * mfi) + temp; | ||
| 207 | 147 | ||
| 208 | return temp; | 148 | return mxc_decode_pll(reg, pll_ref_get_rate()); |
| 209 | } | 149 | } |
| 210 | 150 | ||
| 211 | static int _clk_usb_pll_enable(struct clk *clk) | 151 | static int usb_pll_enable(struct clk *clk) |
| 212 | { | 152 | { |
| 213 | u32 reg; | 153 | u32 reg; |
| 214 | 154 | ||
| @@ -222,7 +162,7 @@ static int _clk_usb_pll_enable(struct clk *clk) | |||
| 222 | return 0; | 162 | return 0; |
| 223 | } | 163 | } |
| 224 | 164 | ||
| 225 | static void _clk_usb_pll_disable(struct clk *clk) | 165 | static void usb_pll_disable(struct clk *clk) |
| 226 | { | 166 | { |
| 227 | u32 reg; | 167 | u32 reg; |
| 228 | 168 | ||
| @@ -231,7 +171,7 @@ static void _clk_usb_pll_disable(struct clk *clk) | |||
| 231 | __raw_writel(reg, MXC_CCM_CCMR); | 171 | __raw_writel(reg, MXC_CCM_CCMR); |
| 232 | } | 172 | } |
| 233 | 173 | ||
| 234 | static int _clk_serial_pll_enable(struct clk *clk) | 174 | static int serial_pll_enable(struct clk *clk) |
| 235 | { | 175 | { |
| 236 | u32 reg; | 176 | u32 reg; |
| 237 | 177 | ||
| @@ -245,7 +185,7 @@ static int _clk_serial_pll_enable(struct clk *clk) | |||
| 245 | return 0; | 185 | return 0; |
| 246 | } | 186 | } |
| 247 | 187 | ||
| 248 | static void _clk_serial_pll_disable(struct clk *clk) | 188 | static void serial_pll_disable(struct clk *clk) |
| 249 | { | 189 | { |
| 250 | u32 reg; | 190 | u32 reg; |
| 251 | 191 | ||
| @@ -258,7 +198,7 @@ static void _clk_serial_pll_disable(struct clk *clk) | |||
| 258 | #define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) | 198 | #define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) |
| 259 | #define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) | 199 | #define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) |
| 260 | 200 | ||
| 261 | static unsigned long _clk_mcu_main_get_rate(struct clk *clk) | 201 | static unsigned long mcu_main_get_rate(struct clk *clk) |
| 262 | { | 202 | { |
| 263 | u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); | 203 | u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); |
| 264 | 204 | ||
| @@ -268,7 +208,7 @@ static unsigned long _clk_mcu_main_get_rate(struct clk *clk) | |||
| 268 | return clk_get_rate(&mcu_pll_clk); | 208 | return clk_get_rate(&mcu_pll_clk); |
| 269 | } | 209 | } |
| 270 | 210 | ||
| 271 | static unsigned long _clk_hclk_get_rate(struct clk *clk) | 211 | static unsigned long ahb_get_rate(struct clk *clk) |
| 272 | { | 212 | { |
| 273 | unsigned long max_pdf; | 213 | unsigned long max_pdf; |
| 274 | 214 | ||
| @@ -277,7 +217,7 @@ static unsigned long _clk_hclk_get_rate(struct clk *clk) | |||
| 277 | return clk_get_rate(clk->parent) / (max_pdf + 1); | 217 | return clk_get_rate(clk->parent) / (max_pdf + 1); |
| 278 | } | 218 | } |
| 279 | 219 | ||
| 280 | static unsigned long _clk_ipg_get_rate(struct clk *clk) | 220 | static unsigned long ipg_get_rate(struct clk *clk) |
| 281 | { | 221 | { |
| 282 | unsigned long ipg_pdf; | 222 | unsigned long ipg_pdf; |
| 283 | 223 | ||
| @@ -286,7 +226,7 @@ static unsigned long _clk_ipg_get_rate(struct clk *clk) | |||
| 286 | return clk_get_rate(clk->parent) / (ipg_pdf + 1); | 226 | return clk_get_rate(clk->parent) / (ipg_pdf + 1); |
| 287 | } | 227 | } |
| 288 | 228 | ||
| 289 | static unsigned long _clk_nfc_get_rate(struct clk *clk) | 229 | static unsigned long nfc_get_rate(struct clk *clk) |
| 290 | { | 230 | { |
| 291 | unsigned long nfc_pdf; | 231 | unsigned long nfc_pdf; |
| 292 | 232 | ||
| @@ -295,7 +235,7 @@ static unsigned long _clk_nfc_get_rate(struct clk *clk) | |||
| 295 | return clk_get_rate(clk->parent) / (nfc_pdf + 1); | 235 | return clk_get_rate(clk->parent) / (nfc_pdf + 1); |
| 296 | } | 236 | } |
| 297 | 237 | ||
| 298 | static unsigned long _clk_hsp_get_rate(struct clk *clk) | 238 | static unsigned long hsp_get_rate(struct clk *clk) |
| 299 | { | 239 | { |
| 300 | unsigned long hsp_pdf; | 240 | unsigned long hsp_pdf; |
| 301 | 241 | ||
| @@ -304,7 +244,7 @@ static unsigned long _clk_hsp_get_rate(struct clk *clk) | |||
| 304 | return clk_get_rate(clk->parent) / (hsp_pdf + 1); | 244 | return clk_get_rate(clk->parent) / (hsp_pdf + 1); |
| 305 | } | 245 | } |
| 306 | 246 | ||
| 307 | static unsigned long _clk_usb_get_rate(struct clk *clk) | 247 | static unsigned long usb_get_rate(struct clk *clk) |
| 308 | { | 248 | { |
| 309 | unsigned long usb_pdf, usb_prepdf; | 249 | unsigned long usb_pdf, usb_prepdf; |
| 310 | 250 | ||
| @@ -315,7 +255,7 @@ static unsigned long _clk_usb_get_rate(struct clk *clk) | |||
| 315 | return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); | 255 | return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); |
| 316 | } | 256 | } |
| 317 | 257 | ||
| 318 | static unsigned long _clk_csi_get_rate(struct clk *clk) | 258 | static unsigned long csi_get_rate(struct clk *clk) |
| 319 | { | 259 | { |
| 320 | u32 reg, pre, post; | 260 | u32 reg, pre, post; |
| 321 | 261 | ||
| @@ -329,7 +269,7 @@ static unsigned long _clk_csi_get_rate(struct clk *clk) | |||
| 329 | return clk_get_rate(clk->parent) / (pre * post); | 269 | return clk_get_rate(clk->parent) / (pre * post); |
| 330 | } | 270 | } |
| 331 | 271 | ||
| 332 | static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) | 272 | static unsigned long csi_round_rate(struct clk *clk, unsigned long rate) |
| 333 | { | 273 | { |
| 334 | u32 pre, post, parent = clk_get_rate(clk->parent); | 274 | u32 pre, post, parent = clk_get_rate(clk->parent); |
| 335 | u32 div = parent / rate; | 275 | u32 div = parent / rate; |
| @@ -342,7 +282,7 @@ static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) | |||
| 342 | return parent / (pre * post); | 282 | return parent / (pre * post); |
| 343 | } | 283 | } |
| 344 | 284 | ||
| 345 | static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) | 285 | static int csi_set_rate(struct clk *clk, unsigned long rate) |
| 346 | { | 286 | { |
| 347 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); | 287 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); |
| 348 | 288 | ||
| @@ -363,16 +303,7 @@ static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) | |||
| 363 | return 0; | 303 | return 0; |
| 364 | } | 304 | } |
| 365 | 305 | ||
| 366 | static unsigned long _clk_per_get_rate(struct clk *clk) | 306 | static unsigned long ssi1_get_rate(struct clk *clk) |
| 367 | { | ||
| 368 | unsigned long per_pdf; | ||
| 369 | |||
| 370 | per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK, | ||
| 371 | MXC_CCM_PDR0_PER_PODF_OFFSET); | ||
| 372 | return clk_get_rate(clk->parent) / (per_pdf + 1); | ||
| 373 | } | ||
| 374 | |||
| 375 | static unsigned long _clk_ssi1_get_rate(struct clk *clk) | ||
| 376 | { | 307 | { |
| 377 | unsigned long ssi1_pdf, ssi1_prepdf; | 308 | unsigned long ssi1_pdf, ssi1_prepdf; |
| 378 | 309 | ||
| @@ -383,7 +314,7 @@ static unsigned long _clk_ssi1_get_rate(struct clk *clk) | |||
| 383 | return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); | 314 | return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); |
| 384 | } | 315 | } |
| 385 | 316 | ||
| 386 | static unsigned long _clk_ssi2_get_rate(struct clk *clk) | 317 | static unsigned long ssi2_get_rate(struct clk *clk) |
| 387 | { | 318 | { |
| 388 | unsigned long ssi2_pdf, ssi2_prepdf; | 319 | unsigned long ssi2_pdf, ssi2_prepdf; |
| 389 | 320 | ||
| @@ -394,7 +325,7 @@ static unsigned long _clk_ssi2_get_rate(struct clk *clk) | |||
| 394 | return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); | 325 | return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); |
| 395 | } | 326 | } |
| 396 | 327 | ||
| 397 | static unsigned long _clk_firi_get_rate(struct clk *clk) | 328 | static unsigned long firi_get_rate(struct clk *clk) |
| 398 | { | 329 | { |
| 399 | unsigned long firi_pdf, firi_prepdf; | 330 | unsigned long firi_pdf, firi_prepdf; |
| 400 | 331 | ||
| @@ -405,7 +336,7 @@ static unsigned long _clk_firi_get_rate(struct clk *clk) | |||
| 405 | return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); | 336 | return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); |
| 406 | } | 337 | } |
| 407 | 338 | ||
| 408 | static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) | 339 | static unsigned long firi_round_rate(struct clk *clk, unsigned long rate) |
| 409 | { | 340 | { |
| 410 | u32 pre, post; | 341 | u32 pre, post; |
| 411 | u32 parent = clk_get_rate(clk->parent); | 342 | u32 parent = clk_get_rate(clk->parent); |
| @@ -420,7 +351,7 @@ static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) | |||
| 420 | 351 | ||
| 421 | } | 352 | } |
| 422 | 353 | ||
| 423 | static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) | 354 | static int firi_set_rate(struct clk *clk, unsigned long rate) |
| 424 | { | 355 | { |
| 425 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); | 356 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); |
| 426 | 357 | ||
| @@ -441,12 +372,12 @@ static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) | |||
| 441 | return 0; | 372 | return 0; |
| 442 | } | 373 | } |
| 443 | 374 | ||
| 444 | static unsigned long _clk_mbx_get_rate(struct clk *clk) | 375 | static unsigned long mbx_get_rate(struct clk *clk) |
| 445 | { | 376 | { |
| 446 | return clk_get_rate(clk->parent) / 2; | 377 | return clk_get_rate(clk->parent) / 2; |
| 447 | } | 378 | } |
| 448 | 379 | ||
| 449 | static unsigned long _clk_mstick1_get_rate(struct clk *clk) | 380 | static unsigned long mstick1_get_rate(struct clk *clk) |
| 450 | { | 381 | { |
| 451 | unsigned long msti_pdf; | 382 | unsigned long msti_pdf; |
| 452 | 383 | ||
| @@ -455,7 +386,7 @@ static unsigned long _clk_mstick1_get_rate(struct clk *clk) | |||
| 455 | return clk_get_rate(clk->parent) / (msti_pdf + 1); | 386 | return clk_get_rate(clk->parent) / (msti_pdf + 1); |
| 456 | } | 387 | } |
| 457 | 388 | ||
| 458 | static unsigned long _clk_mstick2_get_rate(struct clk *clk) | 389 | static unsigned long mstick2_get_rate(struct clk *clk) |
| 459 | { | 390 | { |
| 460 | unsigned long msti_pdf; | 391 | unsigned long msti_pdf; |
| 461 | 392 | ||
| @@ -472,661 +403,185 @@ static unsigned long clk_ckih_get_rate(struct clk *clk) | |||
| 472 | } | 403 | } |
| 473 | 404 | ||
| 474 | static struct clk ckih_clk = { | 405 | static struct clk ckih_clk = { |
| 475 | .name = "ckih", | ||
| 476 | .get_rate = clk_ckih_get_rate, | 406 | .get_rate = clk_ckih_get_rate, |
| 477 | }; | 407 | }; |
| 478 | 408 | ||
| 479 | static unsigned long clk_ckil_get_rate(struct clk *clk) | ||
| 480 | { | ||
| 481 | return CKIL_CLK_FREQ; | ||
| 482 | } | ||
| 483 | |||
| 484 | static struct clk ckil_clk = { | ||
| 485 | .name = "ckil", | ||
| 486 | .get_rate = clk_ckil_get_rate, | ||
| 487 | }; | ||
| 488 | |||
| 489 | static struct clk mcu_pll_clk = { | 409 | static struct clk mcu_pll_clk = { |
| 490 | .name = "mcu_pll", | ||
| 491 | .parent = &ckih_clk, | 410 | .parent = &ckih_clk, |
| 492 | .set_rate = _clk_pll_set_rate, | 411 | .get_rate = mcu_pll_get_rate, |
| 493 | .get_rate = _clk_pll_get_rate, | ||
| 494 | }; | 412 | }; |
| 495 | 413 | ||
| 496 | static struct clk mcu_main_clk = { | 414 | static struct clk mcu_main_clk = { |
| 497 | .name = "mcu_main_clk", | ||
| 498 | .parent = &mcu_pll_clk, | 415 | .parent = &mcu_pll_clk, |
| 499 | .get_rate = _clk_mcu_main_get_rate, | 416 | .get_rate = mcu_main_get_rate, |
| 500 | }; | 417 | }; |
| 501 | 418 | ||
| 502 | static struct clk serial_pll_clk = { | 419 | static struct clk serial_pll_clk = { |
| 503 | .name = "serial_pll", | ||
| 504 | .parent = &ckih_clk, | 420 | .parent = &ckih_clk, |
| 505 | .set_rate = _clk_pll_set_rate, | 421 | .get_rate = serial_pll_get_rate, |
| 506 | .get_rate = _clk_pll_get_rate, | 422 | .enable = serial_pll_enable, |
| 507 | .enable = _clk_serial_pll_enable, | 423 | .disable = serial_pll_disable, |
| 508 | .disable = _clk_serial_pll_disable, | ||
| 509 | }; | 424 | }; |
| 510 | 425 | ||
| 511 | static struct clk usb_pll_clk = { | 426 | static struct clk usb_pll_clk = { |
| 512 | .name = "usb_pll", | ||
| 513 | .parent = &ckih_clk, | 427 | .parent = &ckih_clk, |
| 514 | .set_rate = _clk_pll_set_rate, | 428 | .get_rate = usb_pll_get_rate, |
| 515 | .get_rate = _clk_pll_get_rate, | 429 | .enable = usb_pll_enable, |
| 516 | .enable = _clk_usb_pll_enable, | 430 | .disable = usb_pll_disable, |
| 517 | .disable = _clk_usb_pll_disable, | ||
| 518 | }; | 431 | }; |
| 519 | 432 | ||
| 520 | static struct clk ahb_clk = { | 433 | static struct clk ahb_clk = { |
| 521 | .name = "ahb_clk", | ||
| 522 | .parent = &mcu_main_clk, | 434 | .parent = &mcu_main_clk, |
| 523 | .get_rate = _clk_hclk_get_rate, | 435 | .get_rate = ahb_get_rate, |
| 524 | }; | 436 | }; |
| 525 | 437 | ||
| 526 | static struct clk per_clk = { | 438 | #define DEFINE_CLOCK(name, i, er, es, gr, s, p) \ |
| 527 | .name = "per_clk", | 439 | static struct clk name = { \ |
| 528 | .parent = &usb_pll_clk, | 440 | .id = i, \ |
| 529 | .get_rate = _clk_per_get_rate, | 441 | .enable_reg = er, \ |
| 530 | }; | 442 | .enable_shift = es, \ |
| 531 | 443 | .get_rate = gr, \ | |
| 532 | static struct clk perclk_clk = { | 444 | .enable = cgr_enable, \ |
| 533 | .name = "perclk_clk", | 445 | .disable = cgr_disable, \ |
| 534 | .parent = &ipg_clk, | 446 | .secondary = s, \ |
| 535 | }; | 447 | .parent = p, \ |
| 536 | 448 | } | |
| 537 | static struct clk cspi_clk[] = { | ||
| 538 | { | ||
| 539 | .name = "cspi_clk", | ||
| 540 | .id = 0, | ||
| 541 | .parent = &ipg_clk, | ||
| 542 | .enable = _clk_enable, | ||
| 543 | .enable_reg = MXC_CCM_CGR2, | ||
| 544 | .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET, | ||
| 545 | .disable = _clk_disable,}, | ||
| 546 | { | ||
| 547 | .name = "cspi_clk", | ||
| 548 | .id = 1, | ||
| 549 | .parent = &ipg_clk, | ||
| 550 | .enable = _clk_enable, | ||
| 551 | .enable_reg = MXC_CCM_CGR2, | ||
| 552 | .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET, | ||
| 553 | .disable = _clk_disable,}, | ||
| 554 | { | ||
| 555 | .name = "cspi_clk", | ||
| 556 | .id = 2, | ||
| 557 | .parent = &ipg_clk, | ||
| 558 | .enable = _clk_enable, | ||
| 559 | .enable_reg = MXC_CCM_CGR0, | ||
| 560 | .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET, | ||
| 561 | .disable = _clk_disable,}, | ||
| 562 | }; | ||
| 563 | |||
| 564 | static struct clk ipg_clk = { | ||
| 565 | .name = "ipg_clk", | ||
| 566 | .parent = &ahb_clk, | ||
| 567 | .get_rate = _clk_ipg_get_rate, | ||
| 568 | }; | ||
| 569 | |||
| 570 | static struct clk emi_clk = { | ||
| 571 | .name = "emi_clk", | ||
| 572 | .parent = &ahb_clk, | ||
| 573 | .enable = _clk_enable, | ||
| 574 | .enable_reg = MXC_CCM_CGR2, | ||
| 575 | .enable_shift = MXC_CCM_CGR2_EMI_OFFSET, | ||
| 576 | .disable = _clk_emi_disable, | ||
| 577 | }; | ||
| 578 | |||
| 579 | static struct clk gpt_clk = { | ||
| 580 | .name = "gpt_clk", | ||
| 581 | .parent = &perclk_clk, | ||
| 582 | .enable = _clk_enable, | ||
| 583 | .enable_reg = MXC_CCM_CGR0, | ||
| 584 | .enable_shift = MXC_CCM_CGR0_GPT_OFFSET, | ||
| 585 | .disable = _clk_disable, | ||
| 586 | }; | ||
| 587 | |||
| 588 | static struct clk pwm_clk = { | ||
| 589 | .name = "pwm_clk", | ||
| 590 | .parent = &perclk_clk, | ||
| 591 | .enable = _clk_enable, | ||
| 592 | .enable_reg = MXC_CCM_CGR0, | ||
| 593 | .enable_shift = MXC_CCM_CGR1_PWM_OFFSET, | ||
| 594 | .disable = _clk_disable, | ||
| 595 | }; | ||
| 596 | |||
| 597 | static struct clk epit_clk[] = { | ||
| 598 | { | ||
| 599 | .name = "epit_clk", | ||
| 600 | .id = 0, | ||
| 601 | .parent = &perclk_clk, | ||
| 602 | .enable = _clk_enable, | ||
| 603 | .enable_reg = MXC_CCM_CGR0, | ||
| 604 | .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET, | ||
| 605 | .disable = _clk_disable,}, | ||
| 606 | { | ||
| 607 | .name = "epit_clk", | ||
| 608 | .id = 1, | ||
| 609 | .parent = &perclk_clk, | ||
| 610 | .enable = _clk_enable, | ||
| 611 | .enable_reg = MXC_CCM_CGR0, | ||
| 612 | .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET, | ||
| 613 | .disable = _clk_disable,}, | ||
| 614 | }; | ||
| 615 | |||
| 616 | static struct clk nfc_clk = { | ||
| 617 | .name = "nfc_clk", | ||
| 618 | .parent = &ahb_clk, | ||
| 619 | .get_rate = _clk_nfc_get_rate, | ||
| 620 | }; | ||
| 621 | |||
| 622 | static struct clk scc_clk = { | ||
| 623 | .name = "scc_clk", | ||
| 624 | .parent = &ipg_clk, | ||
| 625 | }; | ||
| 626 | |||
| 627 | static struct clk ipu_clk = { | ||
| 628 | .name = "ipu_clk", | ||
| 629 | .parent = &mcu_main_clk, | ||
| 630 | .get_rate = _clk_hsp_get_rate, | ||
| 631 | .enable = _clk_enable, | ||
| 632 | .enable_reg = MXC_CCM_CGR1, | ||
| 633 | .enable_shift = MXC_CCM_CGR1_IPU_OFFSET, | ||
| 634 | .disable = _clk_disable, | ||
| 635 | }; | ||
| 636 | |||
| 637 | static struct clk kpp_clk = { | ||
| 638 | .name = "kpp_clk", | ||
| 639 | .parent = &ipg_clk, | ||
| 640 | .enable = _clk_enable, | ||
| 641 | .enable_reg = MXC_CCM_CGR1, | ||
| 642 | .enable_shift = MXC_CCM_CGR1_KPP_OFFSET, | ||
| 643 | .disable = _clk_disable, | ||
| 644 | }; | ||
| 645 | |||
| 646 | static struct clk wdog_clk = { | ||
| 647 | .name = "wdog_clk", | ||
| 648 | .parent = &ipg_clk, | ||
| 649 | .enable = _clk_enable, | ||
| 650 | .enable_reg = MXC_CCM_CGR1, | ||
| 651 | .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET, | ||
| 652 | .disable = _clk_disable, | ||
| 653 | }; | ||
| 654 | static struct clk rtc_clk = { | ||
| 655 | .name = "rtc_clk", | ||
| 656 | .parent = &ipg_clk, | ||
| 657 | .enable = _clk_enable, | ||
| 658 | .enable_reg = MXC_CCM_CGR1, | ||
| 659 | .enable_shift = MXC_CCM_CGR1_RTC_OFFSET, | ||
| 660 | .disable = _clk_disable, | ||
| 661 | }; | ||
| 662 | |||
| 663 | static struct clk usb_clk[] = { | ||
| 664 | { | ||
| 665 | .name = "usb_clk", | ||
| 666 | .parent = &usb_pll_clk, | ||
| 667 | .get_rate = _clk_usb_get_rate,}, | ||
| 668 | { | ||
| 669 | .name = "usb_ahb_clk", | ||
| 670 | .parent = &ahb_clk, | ||
| 671 | .enable = _clk_enable, | ||
| 672 | .enable_reg = MXC_CCM_CGR1, | ||
| 673 | .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET, | ||
| 674 | .disable = _clk_disable,}, | ||
| 675 | }; | ||
| 676 | |||
| 677 | static struct clk csi_clk = { | ||
| 678 | .name = "csi_clk", | ||
| 679 | .parent = &serial_pll_clk, | ||
| 680 | .get_rate = _clk_csi_get_rate, | ||
| 681 | .round_rate = _clk_csi_round_rate, | ||
| 682 | .set_rate = _clk_csi_set_rate, | ||
| 683 | .enable = _clk_enable, | ||
| 684 | .enable_reg = MXC_CCM_CGR1, | ||
| 685 | .enable_shift = MXC_CCM_CGR1_CSI_OFFSET, | ||
| 686 | .disable = _clk_disable, | ||
| 687 | }; | ||
| 688 | |||
| 689 | static struct clk uart_clk[] = { | ||
| 690 | { | ||
| 691 | .name = "uart_clk", | ||
| 692 | .id = 0, | ||
| 693 | .parent = &perclk_clk, | ||
| 694 | .enable = _clk_enable, | ||
| 695 | .enable_reg = MXC_CCM_CGR0, | ||
| 696 | .enable_shift = MXC_CCM_CGR0_UART1_OFFSET, | ||
| 697 | .disable = _clk_disable,}, | ||
| 698 | { | ||
| 699 | .name = "uart_clk", | ||
| 700 | .id = 1, | ||
| 701 | .parent = &perclk_clk, | ||
| 702 | .enable = _clk_enable, | ||
| 703 | .enable_reg = MXC_CCM_CGR0, | ||
| 704 | .enable_shift = MXC_CCM_CGR0_UART2_OFFSET, | ||
| 705 | .disable = _clk_disable,}, | ||
| 706 | { | ||
| 707 | .name = "uart_clk", | ||
| 708 | .id = 2, | ||
| 709 | .parent = &perclk_clk, | ||
| 710 | .enable = _clk_enable, | ||
| 711 | .enable_reg = MXC_CCM_CGR1, | ||
| 712 | .enable_shift = MXC_CCM_CGR1_UART3_OFFSET, | ||
| 713 | .disable = _clk_disable,}, | ||
| 714 | { | ||
| 715 | .name = "uart_clk", | ||
| 716 | .id = 3, | ||
| 717 | .parent = &perclk_clk, | ||
| 718 | .enable = _clk_enable, | ||
| 719 | .enable_reg = MXC_CCM_CGR1, | ||
| 720 | .enable_shift = MXC_CCM_CGR1_UART4_OFFSET, | ||
| 721 | .disable = _clk_disable,}, | ||
| 722 | { | ||
| 723 | .name = "uart_clk", | ||
| 724 | .id = 4, | ||
| 725 | .parent = &perclk_clk, | ||
| 726 | .enable = _clk_enable, | ||
| 727 | .enable_reg = MXC_CCM_CGR1, | ||
| 728 | .enable_shift = MXC_CCM_CGR1_UART5_OFFSET, | ||
| 729 | .disable = _clk_disable,}, | ||
| 730 | }; | ||
| 731 | |||
| 732 | static struct clk i2c_clk[] = { | ||
| 733 | { | ||
| 734 | .name = "i2c_clk", | ||
| 735 | .id = 0, | ||
| 736 | .parent = &perclk_clk, | ||
| 737 | .enable = _clk_enable, | ||
| 738 | .enable_reg = MXC_CCM_CGR0, | ||
| 739 | .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET, | ||
| 740 | .disable = _clk_disable,}, | ||
| 741 | { | ||
| 742 | .name = "i2c_clk", | ||
| 743 | .id = 1, | ||
| 744 | .parent = &perclk_clk, | ||
| 745 | .enable = _clk_enable, | ||
| 746 | .enable_reg = MXC_CCM_CGR0, | ||
| 747 | .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET, | ||
| 748 | .disable = _clk_disable,}, | ||
| 749 | { | ||
| 750 | .name = "i2c_clk", | ||
| 751 | .id = 2, | ||
| 752 | .parent = &perclk_clk, | ||
| 753 | .enable = _clk_enable, | ||
| 754 | .enable_reg = MXC_CCM_CGR0, | ||
| 755 | .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET, | ||
| 756 | .disable = _clk_disable,}, | ||
| 757 | }; | ||
| 758 | |||
| 759 | static struct clk owire_clk = { | ||
| 760 | .name = "owire_clk", | ||
| 761 | .parent = &perclk_clk, | ||
| 762 | .enable_reg = MXC_CCM_CGR1, | ||
| 763 | .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET, | ||
| 764 | .enable = _clk_enable, | ||
| 765 | .disable = _clk_disable, | ||
| 766 | }; | ||
| 767 | |||
| 768 | static struct clk sdhc_clk[] = { | ||
| 769 | { | ||
| 770 | .name = "sdhc_clk", | ||
| 771 | .id = 0, | ||
| 772 | .parent = &perclk_clk, | ||
| 773 | .enable = _clk_enable, | ||
| 774 | .enable_reg = MXC_CCM_CGR0, | ||
| 775 | .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET, | ||
| 776 | .disable = _clk_disable,}, | ||
| 777 | { | ||
| 778 | .name = "sdhc_clk", | ||
| 779 | .id = 1, | ||
| 780 | .parent = &perclk_clk, | ||
| 781 | .enable = _clk_enable, | ||
| 782 | .enable_reg = MXC_CCM_CGR0, | ||
| 783 | .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET, | ||
| 784 | .disable = _clk_disable,}, | ||
| 785 | }; | ||
| 786 | |||
| 787 | static struct clk ssi_clk[] = { | ||
| 788 | { | ||
| 789 | .name = "ssi_clk", | ||
| 790 | .parent = &serial_pll_clk, | ||
| 791 | .get_rate = _clk_ssi1_get_rate, | ||
| 792 | .enable = _clk_enable, | ||
| 793 | .enable_reg = MXC_CCM_CGR0, | ||
| 794 | .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET, | ||
| 795 | .disable = _clk_disable,}, | ||
| 796 | { | ||
| 797 | .name = "ssi_clk", | ||
| 798 | .id = 1, | ||
| 799 | .parent = &serial_pll_clk, | ||
| 800 | .get_rate = _clk_ssi2_get_rate, | ||
| 801 | .enable = _clk_enable, | ||
| 802 | .enable_reg = MXC_CCM_CGR2, | ||
| 803 | .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET, | ||
| 804 | .disable = _clk_disable,}, | ||
| 805 | }; | ||
| 806 | |||
| 807 | static struct clk firi_clk = { | ||
| 808 | .name = "firi_clk", | ||
| 809 | .parent = &usb_pll_clk, | ||
| 810 | .round_rate = _clk_firi_round_rate, | ||
| 811 | .set_rate = _clk_firi_set_rate, | ||
| 812 | .get_rate = _clk_firi_get_rate, | ||
| 813 | .enable = _clk_enable, | ||
| 814 | .enable_reg = MXC_CCM_CGR2, | ||
| 815 | .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET, | ||
| 816 | .disable = _clk_disable, | ||
| 817 | }; | ||
| 818 | |||
| 819 | static struct clk ata_clk = { | ||
| 820 | .name = "ata_clk", | ||
| 821 | .parent = &ipg_clk, | ||
| 822 | .enable = _clk_enable, | ||
| 823 | .enable_reg = MXC_CCM_CGR0, | ||
| 824 | .enable_shift = MXC_CCM_CGR0_ATA_OFFSET, | ||
| 825 | .disable = _clk_disable, | ||
| 826 | }; | ||
| 827 | |||
| 828 | static struct clk mbx_clk = { | ||
| 829 | .name = "mbx_clk", | ||
| 830 | .parent = &ahb_clk, | ||
| 831 | .enable = _clk_enable, | ||
| 832 | .enable_reg = MXC_CCM_CGR2, | ||
| 833 | .enable_shift = MXC_CCM_CGR2_GACC_OFFSET, | ||
| 834 | .get_rate = _clk_mbx_get_rate, | ||
| 835 | }; | ||
| 836 | |||
| 837 | static struct clk vpu_clk = { | ||
| 838 | .name = "vpu_clk", | ||
| 839 | .parent = &ahb_clk, | ||
| 840 | .enable = _clk_enable, | ||
| 841 | .enable_reg = MXC_CCM_CGR2, | ||
| 842 | .enable_shift = MXC_CCM_CGR2_GACC_OFFSET, | ||
| 843 | .get_rate = _clk_mbx_get_rate, | ||
| 844 | }; | ||
| 845 | |||
| 846 | static struct clk rtic_clk = { | ||
| 847 | .name = "rtic_clk", | ||
| 848 | .parent = &ahb_clk, | ||
| 849 | .enable = _clk_enable, | ||
| 850 | .enable_reg = MXC_CCM_CGR2, | ||
| 851 | .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET, | ||
| 852 | .disable = _clk_disable, | ||
| 853 | }; | ||
| 854 | |||
| 855 | static struct clk rng_clk = { | ||
| 856 | .name = "rng_clk", | ||
| 857 | .parent = &ipg_clk, | ||
| 858 | .enable = _clk_enable, | ||
| 859 | .enable_reg = MXC_CCM_CGR0, | ||
| 860 | .enable_shift = MXC_CCM_CGR0_RNG_OFFSET, | ||
| 861 | .disable = _clk_disable, | ||
| 862 | }; | ||
| 863 | |||
| 864 | static struct clk sdma_clk[] = { | ||
| 865 | { | ||
| 866 | .name = "sdma_ahb_clk", | ||
| 867 | .parent = &ahb_clk, | ||
| 868 | .enable = _clk_enable, | ||
| 869 | .enable_reg = MXC_CCM_CGR0, | ||
| 870 | .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET, | ||
| 871 | .disable = _clk_disable,}, | ||
| 872 | { | ||
| 873 | .name = "sdma_ipg_clk", | ||
| 874 | .parent = &ipg_clk,} | ||
| 875 | }; | ||
| 876 | |||
| 877 | static struct clk mpeg4_clk = { | ||
| 878 | .name = "mpeg4_clk", | ||
| 879 | .parent = &ahb_clk, | ||
| 880 | .enable = _clk_enable, | ||
| 881 | .enable_reg = MXC_CCM_CGR1, | ||
| 882 | .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET, | ||
| 883 | .disable = _clk_disable, | ||
| 884 | }; | ||
| 885 | |||
| 886 | static struct clk vl2cc_clk = { | ||
| 887 | .name = "vl2cc_clk", | ||
| 888 | .parent = &ahb_clk, | ||
| 889 | .enable = _clk_enable, | ||
| 890 | .enable_reg = MXC_CCM_CGR1, | ||
| 891 | .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET, | ||
| 892 | .disable = _clk_disable, | ||
| 893 | }; | ||
| 894 | |||
| 895 | static struct clk mstick_clk[] = { | ||
| 896 | { | ||
| 897 | .name = "mstick_clk", | ||
| 898 | .id = 0, | ||
| 899 | .parent = &usb_pll_clk, | ||
| 900 | .get_rate = _clk_mstick1_get_rate, | ||
| 901 | .enable = _clk_enable, | ||
| 902 | .enable_reg = MXC_CCM_CGR1, | ||
| 903 | .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET, | ||
| 904 | .disable = _clk_disable,}, | ||
| 905 | { | ||
| 906 | .name = "mstick_clk", | ||
| 907 | .id = 1, | ||
| 908 | .parent = &usb_pll_clk, | ||
| 909 | .get_rate = _clk_mstick2_get_rate, | ||
| 910 | .enable = _clk_enable, | ||
| 911 | .enable_reg = MXC_CCM_CGR1, | ||
| 912 | .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET, | ||
| 913 | .disable = _clk_disable,}, | ||
| 914 | }; | ||
| 915 | |||
| 916 | static struct clk iim_clk = { | ||
| 917 | .name = "iim_clk", | ||
| 918 | .parent = &ipg_clk, | ||
| 919 | .enable = _clk_enable, | ||
| 920 | .enable_reg = MXC_CCM_CGR0, | ||
| 921 | .enable_shift = MXC_CCM_CGR0_IIM_OFFSET, | ||
| 922 | .disable = _clk_disable, | ||
| 923 | }; | ||
| 924 | |||
| 925 | static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate) | ||
| 926 | { | ||
| 927 | u32 div, parent = clk_get_rate(clk->parent); | ||
| 928 | |||
| 929 | div = parent / rate; | ||
| 930 | if (parent % rate) | ||
| 931 | div++; | ||
| 932 | |||
| 933 | if (div > 8) | ||
| 934 | div = 16; | ||
| 935 | else if (div > 4) | ||
| 936 | div = 8; | ||
| 937 | else if (div > 2) | ||
| 938 | div = 4; | ||
| 939 | |||
| 940 | return parent / div; | ||
| 941 | } | ||
| 942 | |||
| 943 | static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate) | ||
| 944 | { | ||
| 945 | u32 reg, div, parent = clk_get_rate(clk->parent); | ||
| 946 | |||
| 947 | div = parent / rate; | ||
| 948 | |||
| 949 | if (div == 16) | ||
| 950 | div = 4; | ||
| 951 | else if (div == 8) | ||
| 952 | div = 3; | ||
| 953 | else if (div == 4) | ||
| 954 | div = 2; | ||
| 955 | else if (div == 2) | ||
| 956 | div = 1; | ||
| 957 | else if (div == 1) | ||
| 958 | div = 0; | ||
| 959 | else | ||
| 960 | return -EINVAL; | ||
| 961 | |||
| 962 | reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK; | ||
| 963 | reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET; | ||
| 964 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 965 | |||
| 966 | return 0; | ||
| 967 | } | ||
| 968 | |||
| 969 | static unsigned long _clk_cko1_get_rate(struct clk *clk) | ||
| 970 | { | ||
| 971 | u32 div; | ||
| 972 | |||
| 973 | div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >> | ||
| 974 | MXC_CCM_COSR_CLKOUTDIV_OFFSET; | ||
| 975 | |||
| 976 | return clk_get_rate(clk->parent) / (1 << div); | ||
| 977 | } | ||
| 978 | |||
| 979 | static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent) | ||
| 980 | { | ||
| 981 | u32 reg; | ||
| 982 | |||
| 983 | reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK; | ||
| 984 | |||
| 985 | if (parent == &mcu_main_clk) | ||
| 986 | reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 987 | else if (parent == &ipg_clk) | ||
| 988 | reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 989 | else if (parent == &usb_pll_clk) | ||
| 990 | reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 991 | else if (parent == mcu_main_clk.parent) | ||
| 992 | reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 993 | else if (parent == &ahb_clk) | ||
| 994 | reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 995 | else if (parent == &serial_pll_clk) | ||
| 996 | reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 997 | else if (parent == &ckih_clk) | ||
| 998 | reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 999 | else if (parent == &emi_clk) | ||
| 1000 | reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1001 | else if (parent == &ipu_clk) | ||
| 1002 | reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1003 | else if (parent == &nfc_clk) | ||
| 1004 | reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1005 | else if (parent == &uart_clk[0]) | ||
| 1006 | reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1007 | else | ||
| 1008 | return -EINVAL; | ||
| 1009 | |||
| 1010 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 1011 | |||
| 1012 | return 0; | ||
| 1013 | } | ||
| 1014 | |||
| 1015 | static int _clk_cko1_enable(struct clk *clk) | ||
| 1016 | { | ||
| 1017 | u32 reg; | ||
| 1018 | |||
| 1019 | reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN; | ||
| 1020 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 1021 | 449 | ||
| 1022 | return 0; | 450 | #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \ |
| 1023 | } | 451 | static struct clk name = { \ |
| 452 | .id = i, \ | ||
| 453 | .enable_reg = er, \ | ||
| 454 | .enable_shift = es, \ | ||
| 455 | .get_rate = getsetround##_get_rate, \ | ||
| 456 | .set_rate = getsetround##_set_rate, \ | ||
| 457 | .round_rate = getsetround##_round_rate, \ | ||
| 458 | .enable = cgr_enable, \ | ||
| 459 | .disable = cgr_disable, \ | ||
| 460 | .secondary = s, \ | ||
| 461 | .parent = p, \ | ||
| 462 | } | ||
| 1024 | 463 | ||
| 1025 | static void _clk_cko1_disable(struct clk *clk) | 464 | DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); |
| 465 | |||
| 466 | DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk); | ||
| 467 | DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk); | ||
| 468 | DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk); | ||
| 469 | DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk); | ||
| 470 | DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); | ||
| 471 | DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); | ||
| 472 | DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); | ||
| 473 | DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk); | ||
| 474 | DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); | ||
| 475 | DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); | ||
| 476 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk); | ||
| 477 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk); | ||
| 478 | DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk); | ||
| 479 | DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk); | ||
| 480 | DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk); | ||
| 481 | DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk); | ||
| 482 | |||
| 483 | DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk); | ||
| 484 | DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk); | ||
| 485 | DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk); | ||
| 486 | DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &ahb_clk); | ||
| 487 | DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk); | ||
| 488 | DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk); | ||
| 489 | DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk); | ||
| 490 | DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk); | ||
| 491 | DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk); | ||
| 492 | DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk); | ||
| 493 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk); | ||
| 494 | DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk); | ||
| 495 | DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk); | ||
| 496 | DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk); | ||
| 497 | |||
| 498 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk); | ||
| 499 | DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk); | ||
| 500 | DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk); | ||
| 501 | DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk); | ||
| 502 | DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk); | ||
| 503 | DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk); | ||
| 504 | DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk); | ||
| 505 | |||
| 506 | DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk); | ||
| 507 | DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk); | ||
| 508 | DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk); | ||
| 509 | DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); | ||
| 510 | DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); | ||
| 511 | |||
| 512 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 513 | { \ | ||
| 514 | .dev_id = d, \ | ||
| 515 | .con_id = n, \ | ||
| 516 | .clk = &c, \ | ||
| 517 | }, | ||
| 518 | |||
| 519 | static struct clk_lookup lookups[] __initdata = { | ||
| 520 | _REGISTER_CLOCK(NULL, "emi", emi_clk) | ||
| 521 | _REGISTER_CLOCK(NULL, "cspi", cspi1_clk) | ||
| 522 | _REGISTER_CLOCK(NULL, "cspi", cspi2_clk) | ||
| 523 | _REGISTER_CLOCK(NULL, "cspi", cspi3_clk) | ||
| 524 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | ||
| 525 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | ||
| 526 | _REGISTER_CLOCK(NULL, "wdog", wdog_clk) | ||
| 527 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | ||
| 528 | _REGISTER_CLOCK(NULL, "epit", epit1_clk) | ||
| 529 | _REGISTER_CLOCK(NULL, "epit", epit2_clk) | ||
| 530 | _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) | ||
| 531 | _REGISTER_CLOCK("ipu-core", NULL, ipu_clk) | ||
| 532 | _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk) | ||
| 533 | _REGISTER_CLOCK(NULL, "kpp", kpp_clk) | ||
| 534 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1) | ||
| 535 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2) | ||
| 536 | _REGISTER_CLOCK("mx3-camera.0", "csi", csi_clk) | ||
| 537 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | ||
| 538 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | ||
| 539 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | ||
| 540 | _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) | ||
| 541 | _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) | ||
| 542 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) | ||
| 543 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | ||
| 544 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) | ||
| 545 | _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) | ||
| 546 | _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) | ||
| 547 | _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) | ||
| 548 | _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) | ||
| 549 | _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) | ||
| 550 | _REGISTER_CLOCK(NULL, "firi", firi_clk) | ||
| 551 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | ||
| 552 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) | ||
| 553 | _REGISTER_CLOCK(NULL, "rng", rng_clk) | ||
| 554 | _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1) | ||
| 555 | _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2) | ||
| 556 | _REGISTER_CLOCK(NULL, "mstick", mstick1_clk) | ||
| 557 | _REGISTER_CLOCK(NULL, "mstick", mstick2_clk) | ||
| 558 | _REGISTER_CLOCK(NULL, "scc", scc_clk) | ||
| 559 | _REGISTER_CLOCK(NULL, "iim", iim_clk) | ||
| 560 | _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk) | ||
| 561 | _REGISTER_CLOCK(NULL, "mbx", mbx_clk) | ||
| 562 | }; | ||
| 563 | |||
| 564 | int __init mx31_clocks_init(unsigned long fref) | ||
| 1026 | { | 565 | { |
| 1027 | u32 reg; | 566 | u32 reg; |
| 567 | int i; | ||
| 1028 | 568 | ||
| 1029 | reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN; | 569 | mxc_set_cpu_type(MXC_CPU_MX31); |
| 1030 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 1031 | } | ||
| 1032 | |||
| 1033 | static struct clk cko1_clk = { | ||
| 1034 | .name = "cko1_clk", | ||
| 1035 | .get_rate = _clk_cko1_get_rate, | ||
| 1036 | .set_rate = _clk_cko1_set_rate, | ||
| 1037 | .round_rate = _clk_cko1_round_rate, | ||
| 1038 | .set_parent = _clk_cko1_set_parent, | ||
| 1039 | .enable = _clk_cko1_enable, | ||
| 1040 | .disable = _clk_cko1_disable, | ||
| 1041 | }; | ||
| 1042 | |||
| 1043 | static struct clk *mxc_clks[] = { | ||
| 1044 | &ckih_clk, | ||
| 1045 | &ckil_clk, | ||
| 1046 | &mcu_pll_clk, | ||
| 1047 | &usb_pll_clk, | ||
| 1048 | &serial_pll_clk, | ||
| 1049 | &mcu_main_clk, | ||
| 1050 | &ahb_clk, | ||
| 1051 | &per_clk, | ||
| 1052 | &perclk_clk, | ||
| 1053 | &cko1_clk, | ||
| 1054 | &emi_clk, | ||
| 1055 | &cspi_clk[0], | ||
| 1056 | &cspi_clk[1], | ||
| 1057 | &cspi_clk[2], | ||
| 1058 | &ipg_clk, | ||
| 1059 | &gpt_clk, | ||
| 1060 | &pwm_clk, | ||
| 1061 | &wdog_clk, | ||
| 1062 | &rtc_clk, | ||
| 1063 | &epit_clk[0], | ||
| 1064 | &epit_clk[1], | ||
| 1065 | &nfc_clk, | ||
| 1066 | &ipu_clk, | ||
| 1067 | &kpp_clk, | ||
| 1068 | &usb_clk[0], | ||
| 1069 | &usb_clk[1], | ||
| 1070 | &csi_clk, | ||
| 1071 | &uart_clk[0], | ||
| 1072 | &uart_clk[1], | ||
| 1073 | &uart_clk[2], | ||
| 1074 | &uart_clk[3], | ||
| 1075 | &uart_clk[4], | ||
| 1076 | &i2c_clk[0], | ||
| 1077 | &i2c_clk[1], | ||
| 1078 | &i2c_clk[2], | ||
| 1079 | &owire_clk, | ||
| 1080 | &sdhc_clk[0], | ||
| 1081 | &sdhc_clk[1], | ||
| 1082 | &ssi_clk[0], | ||
| 1083 | &ssi_clk[1], | ||
| 1084 | &firi_clk, | ||
| 1085 | &ata_clk, | ||
| 1086 | &rtic_clk, | ||
| 1087 | &rng_clk, | ||
| 1088 | &sdma_clk[0], | ||
| 1089 | &sdma_clk[1], | ||
| 1090 | &mstick_clk[0], | ||
| 1091 | &mstick_clk[1], | ||
| 1092 | &scc_clk, | ||
| 1093 | &iim_clk, | ||
| 1094 | }; | ||
| 1095 | |||
| 1096 | int __init mxc_clocks_init(unsigned long fref) | ||
| 1097 | { | ||
| 1098 | u32 reg; | ||
| 1099 | struct clk **clkp; | ||
| 1100 | 570 | ||
| 1101 | ckih_rate = fref; | 571 | ckih_rate = fref; |
| 1102 | 572 | ||
| 1103 | for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) | 573 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
| 1104 | clk_register(*clkp); | 574 | clkdev_add(&lookups[i]); |
| 1105 | |||
| 1106 | if (cpu_is_mx31()) { | ||
| 1107 | clk_register(&mpeg4_clk); | ||
| 1108 | clk_register(&mbx_clk); | ||
| 1109 | } else { | ||
| 1110 | clk_register(&vpu_clk); | ||
| 1111 | clk_register(&vl2cc_clk); | ||
| 1112 | } | ||
| 1113 | 575 | ||
| 1114 | /* Turn off all possible clocks */ | 576 | /* Turn off all possible clocks */ |
| 1115 | __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0); | 577 | __raw_writel((3 << 4), MXC_CCM_CGR0); |
| 1116 | __raw_writel(0, MXC_CCM_CGR1); | 578 | __raw_writel(0, MXC_CCM_CGR1); |
| 1117 | 579 | __raw_writel((3 << 8) | (3 << 14) | (3 << 16)| | |
| 1118 | __raw_writel(MXC_CCM_CGR2_EMI_MASK | | ||
| 1119 | MXC_CCM_CGR2_IPMUX1_MASK | | ||
| 1120 | MXC_CCM_CGR2_IPMUX2_MASK | | ||
| 1121 | MXC_CCM_CGR2_MXCCLKENSEL_MASK | /* for MX32 */ | ||
| 1122 | MXC_CCM_CGR2_CHIKCAMPEN_MASK | /* for MX32 */ | ||
| 1123 | MXC_CCM_CGR2_OVRVPUBUSY_MASK | /* for MX32 */ | ||
| 1124 | 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for | 580 | 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for |
| 1125 | MX32, but still required to be set */ | 581 | MX32, but still required to be set */ |
| 1126 | MXC_CCM_CGR2); | 582 | MXC_CCM_CGR2); |
| 1127 | 583 | ||
| 1128 | clk_disable(&cko1_clk); | 584 | usb_pll_disable(&usb_pll_clk); |
| 1129 | clk_disable(&usb_pll_clk); | ||
| 1130 | 585 | ||
| 1131 | pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); | 586 | pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); |
| 1132 | 587 | ||
| @@ -1143,6 +598,8 @@ int __init mxc_clocks_init(unsigned long fref) | |||
| 1143 | __raw_writel(reg, MXC_CCM_PMCR1); | 598 | __raw_writel(reg, MXC_CCM_PMCR1); |
| 1144 | } | 599 | } |
| 1145 | 600 | ||
| 601 | mxc_timer_init(&ipg_clk); | ||
| 602 | |||
| 1146 | return 0; | 603 | return 0; |
| 1147 | } | 604 | } |
| 1148 | 605 | ||
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h index 4a0e0ede23bb..adfa3627ad84 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-mx3/crm_regs.h | |||
| @@ -91,47 +91,6 @@ | |||
| 91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 | 91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 |
| 92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 | 92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 |
| 93 | 93 | ||
| 94 | #define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11) | ||
| 95 | #define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11) | ||
| 96 | #define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11) | ||
| 97 | #define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11) | ||
| 98 | #define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11) | ||
| 99 | #define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11) | ||
| 100 | #define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11) | ||
| 101 | #define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11) | ||
| 102 | |||
| 103 | #define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6) | ||
| 104 | #define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6) | ||
| 105 | #define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6) | ||
| 106 | #define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6) | ||
| 107 | |||
| 108 | #define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3) | ||
| 109 | #define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3) | ||
| 110 | #define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3) | ||
| 111 | #define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3) | ||
| 112 | #define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3) | ||
| 113 | #define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3) | ||
| 114 | #define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3) | ||
| 115 | #define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3) | ||
| 116 | |||
| 117 | #define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8) | ||
| 118 | #define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8) | ||
| 119 | #define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8) | ||
| 120 | #define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8) | ||
| 121 | #define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8) | ||
| 122 | #define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8) | ||
| 123 | #define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8) | ||
| 124 | #define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8) | ||
| 125 | |||
| 126 | #define MXC_CCM_PDR0_MCU_DIV_1 0x0 | ||
| 127 | #define MXC_CCM_PDR0_MCU_DIV_2 0x1 | ||
| 128 | #define MXC_CCM_PDR0_MCU_DIV_3 0x2 | ||
| 129 | #define MXC_CCM_PDR0_MCU_DIV_4 0x3 | ||
| 130 | #define MXC_CCM_PDR0_MCU_DIV_5 0x4 | ||
| 131 | #define MXC_CCM_PDR0_MCU_DIV_6 0x5 | ||
| 132 | #define MXC_CCM_PDR0_MCU_DIV_7 0x6 | ||
| 133 | #define MXC_CCM_PDR0_MCU_DIV_8 0x7 | ||
| 134 | |||
| 135 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 | 94 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 |
| 136 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) | 95 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) |
| 137 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 | 96 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 |
| @@ -152,118 +111,6 @@ | |||
| 152 | /* Bit definitions for RCSR */ | 111 | /* Bit definitions for RCSR */ |
| 153 | #define MXC_CCM_RCSR_NF16B 0x80000000 | 112 | #define MXC_CCM_RCSR_NF16B 0x80000000 |
| 154 | 113 | ||
| 155 | /* Bit definitions for both MCU, USB and SR PLL control registers */ | ||
| 156 | #define MXC_CCM_PCTL_BRM 0x80000000 | ||
| 157 | #define MXC_CCM_PCTL_PD_OFFSET 26 | ||
| 158 | #define MXC_CCM_PCTL_PD_MASK (0xF << 26) | ||
| 159 | #define MXC_CCM_PCTL_MFD_OFFSET 16 | ||
| 160 | #define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) | ||
| 161 | #define MXC_CCM_PCTL_MFI_OFFSET 10 | ||
| 162 | #define MXC_CCM_PCTL_MFI_MASK (0xF << 10) | ||
| 163 | #define MXC_CCM_PCTL_MFN_OFFSET 0 | ||
| 164 | #define MXC_CCM_PCTL_MFN_MASK 0x3FF | ||
| 165 | |||
| 166 | #define MXC_CCM_CGR0_SD_MMC1_OFFSET 0 | ||
| 167 | #define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0) | ||
| 168 | #define MXC_CCM_CGR0_SD_MMC2_OFFSET 2 | ||
| 169 | #define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2) | ||
| 170 | #define MXC_CCM_CGR0_GPT_OFFSET 4 | ||
| 171 | #define MXC_CCM_CGR0_GPT_MASK (0x3 << 4) | ||
| 172 | #define MXC_CCM_CGR0_EPIT1_OFFSET 6 | ||
| 173 | #define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6) | ||
| 174 | #define MXC_CCM_CGR0_EPIT2_OFFSET 8 | ||
| 175 | #define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8) | ||
| 176 | #define MXC_CCM_CGR0_IIM_OFFSET 10 | ||
| 177 | #define MXC_CCM_CGR0_IIM_MASK (0x3 << 10) | ||
| 178 | #define MXC_CCM_CGR0_ATA_OFFSET 12 | ||
| 179 | #define MXC_CCM_CGR0_ATA_MASK (0x3 << 12) | ||
| 180 | #define MXC_CCM_CGR0_SDMA_OFFSET 14 | ||
| 181 | #define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14) | ||
| 182 | #define MXC_CCM_CGR0_CSPI3_OFFSET 16 | ||
| 183 | #define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16) | ||
| 184 | #define MXC_CCM_CGR0_RNG_OFFSET 18 | ||
| 185 | #define MXC_CCM_CGR0_RNG_MASK (0x3 << 18) | ||
| 186 | #define MXC_CCM_CGR0_UART1_OFFSET 20 | ||
| 187 | #define MXC_CCM_CGR0_UART1_MASK (0x3 << 20) | ||
| 188 | #define MXC_CCM_CGR0_UART2_OFFSET 22 | ||
| 189 | #define MXC_CCM_CGR0_UART2_MASK (0x3 << 22) | ||
| 190 | #define MXC_CCM_CGR0_SSI1_OFFSET 24 | ||
| 191 | #define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24) | ||
| 192 | #define MXC_CCM_CGR0_I2C1_OFFSET 26 | ||
| 193 | #define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26) | ||
| 194 | #define MXC_CCM_CGR0_I2C2_OFFSET 28 | ||
| 195 | #define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28) | ||
| 196 | #define MXC_CCM_CGR0_I2C3_OFFSET 30 | ||
| 197 | #define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30) | ||
| 198 | |||
| 199 | #define MXC_CCM_CGR1_HANTRO_OFFSET 0 | ||
| 200 | #define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0) | ||
| 201 | #define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2 | ||
| 202 | #define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2) | ||
| 203 | #define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4 | ||
| 204 | #define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4) | ||
| 205 | #define MXC_CCM_CGR1_CSI_OFFSET 6 | ||
| 206 | #define MXC_CCM_CGR1_CSI_MASK (0x3 << 6) | ||
| 207 | #define MXC_CCM_CGR1_RTC_OFFSET 8 | ||
| 208 | #define MXC_CCM_CGR1_RTC_MASK (0x3 << 8) | ||
| 209 | #define MXC_CCM_CGR1_WDOG_OFFSET 10 | ||
| 210 | #define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10) | ||
| 211 | #define MXC_CCM_CGR1_PWM_OFFSET 12 | ||
| 212 | #define MXC_CCM_CGR1_PWM_MASK (0x3 << 12) | ||
| 213 | #define MXC_CCM_CGR1_SIM_OFFSET 14 | ||
| 214 | #define MXC_CCM_CGR1_SIM_MASK (0x3 << 14) | ||
| 215 | #define MXC_CCM_CGR1_ECT_OFFSET 16 | ||
| 216 | #define MXC_CCM_CGR1_ECT_MASK (0x3 << 16) | ||
| 217 | #define MXC_CCM_CGR1_USBOTG_OFFSET 18 | ||
| 218 | #define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18) | ||
| 219 | #define MXC_CCM_CGR1_KPP_OFFSET 20 | ||
| 220 | #define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) | ||
| 221 | #define MXC_CCM_CGR1_IPU_OFFSET 22 | ||
| 222 | #define MXC_CCM_CGR1_IPU_MASK (0x3 << 22) | ||
| 223 | #define MXC_CCM_CGR1_UART3_OFFSET 24 | ||
| 224 | #define MXC_CCM_CGR1_UART3_MASK (0x3 << 24) | ||
| 225 | #define MXC_CCM_CGR1_UART4_OFFSET 26 | ||
| 226 | #define MXC_CCM_CGR1_UART4_MASK (0x3 << 26) | ||
| 227 | #define MXC_CCM_CGR1_UART5_OFFSET 28 | ||
| 228 | #define MXC_CCM_CGR1_UART5_MASK (0x3 << 28) | ||
| 229 | #define MXC_CCM_CGR1_OWIRE_OFFSET 30 | ||
| 230 | #define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30) | ||
| 231 | |||
| 232 | #define MXC_CCM_CGR2_SSI2_OFFSET 0 | ||
| 233 | #define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0) | ||
| 234 | #define MXC_CCM_CGR2_CSPI1_OFFSET 2 | ||
| 235 | #define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2) | ||
| 236 | #define MXC_CCM_CGR2_CSPI2_OFFSET 4 | ||
| 237 | #define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4) | ||
| 238 | #define MXC_CCM_CGR2_GACC_OFFSET 6 | ||
| 239 | #define MXC_CCM_CGR2_GACC_MASK (0x3 << 6) | ||
| 240 | #define MXC_CCM_CGR2_EMI_OFFSET 8 | ||
| 241 | #define MXC_CCM_CGR2_EMI_MASK (0x3 << 8) | ||
| 242 | #define MXC_CCM_CGR2_RTIC_OFFSET 10 | ||
| 243 | #define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10) | ||
| 244 | #define MXC_CCM_CGR2_FIRI_OFFSET 12 | ||
| 245 | #define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12) | ||
| 246 | #define MXC_CCM_CGR2_IPMUX1_OFFSET 14 | ||
| 247 | #define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14) | ||
| 248 | #define MXC_CCM_CGR2_IPMUX2_OFFSET 16 | ||
| 249 | #define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16) | ||
| 250 | |||
| 251 | /* These new CGR2 bits are added in MX32 */ | ||
| 252 | #define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18 | ||
| 253 | #define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18) | ||
| 254 | #define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20 | ||
| 255 | #define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20) | ||
| 256 | #define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22 | ||
| 257 | #define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22) | ||
| 258 | #define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24 | ||
| 259 | #define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24) | ||
| 260 | #define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25 | ||
| 261 | #define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25) | ||
| 262 | #define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26 | ||
| 263 | #define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26) | ||
| 264 | #define MXC_CCM_CGR2_APMENA_OFFSET 30 | ||
| 265 | #define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30) | ||
| 266 | |||
| 267 | /* | 114 | /* |
| 268 | * LTR0 register offsets | 115 | * LTR0 register offsets |
| 269 | */ | 116 | */ |
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index f8428800f286..380be0c9b213 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | #include <mach/irqs.h> | 25 | #include <mach/irqs.h> |
| 26 | #include <mach/imx-uart.h> | 26 | #include <mach/imx-uart.h> |
| 27 | 27 | ||
| 28 | #include "devices.h" | ||
| 29 | |||
| 28 | static struct resource uart0[] = { | 30 | static struct resource uart0[] = { |
| 29 | { | 31 | { |
| 30 | .start = UART1_BASE_ADDR, | 32 | .start = UART1_BASE_ADDR, |
| @@ -82,6 +84,7 @@ struct platform_device mxc_uart_device2 = { | |||
| 82 | .num_resources = ARRAY_SIZE(uart2), | 84 | .num_resources = ARRAY_SIZE(uart2), |
| 83 | }; | 85 | }; |
| 84 | 86 | ||
| 87 | #ifdef CONFIG_ARCH_MX31 | ||
| 85 | static struct resource uart3[] = { | 88 | static struct resource uart3[] = { |
| 86 | { | 89 | { |
| 87 | .start = UART4_BASE_ADDR, | 90 | .start = UART4_BASE_ADDR, |
| @@ -119,6 +122,7 @@ struct platform_device mxc_uart_device4 = { | |||
| 119 | .resource = uart4, | 122 | .resource = uart4, |
| 120 | .num_resources = ARRAY_SIZE(uart4), | 123 | .num_resources = ARRAY_SIZE(uart4), |
| 121 | }; | 124 | }; |
| 125 | #endif /* CONFIG_ARCH_MX31 */ | ||
| 122 | 126 | ||
| 123 | /* GPIO port description */ | 127 | /* GPIO port description */ |
| 124 | static struct mxc_gpio_port imx_gpio_ports[] = { | 128 | static struct mxc_gpio_port imx_gpio_ports[] = { |
| @@ -164,8 +168,8 @@ struct platform_device mxc_w1_master_device = { | |||
| 164 | 168 | ||
| 165 | static struct resource mxc_nand_resources[] = { | 169 | static struct resource mxc_nand_resources[] = { |
| 166 | { | 170 | { |
| 167 | .start = NFC_BASE_ADDR, | 171 | .start = 0, /* runtime dependent */ |
| 168 | .end = NFC_BASE_ADDR + 0xfff, | 172 | .end = 0, |
| 169 | .flags = IORESOURCE_MEM | 173 | .flags = IORESOURCE_MEM |
| 170 | }, { | 174 | }, { |
| 171 | .start = MXC_INT_NANDFC, | 175 | .start = MXC_INT_NANDFC, |
| @@ -180,3 +184,188 @@ struct platform_device mxc_nand_device = { | |||
| 180 | .num_resources = ARRAY_SIZE(mxc_nand_resources), | 184 | .num_resources = ARRAY_SIZE(mxc_nand_resources), |
| 181 | .resource = mxc_nand_resources, | 185 | .resource = mxc_nand_resources, |
| 182 | }; | 186 | }; |
| 187 | |||
| 188 | static struct resource mxc_i2c0_resources[] = { | ||
| 189 | { | ||
| 190 | .start = I2C_BASE_ADDR, | ||
| 191 | .end = I2C_BASE_ADDR + SZ_4K - 1, | ||
| 192 | .flags = IORESOURCE_MEM, | ||
| 193 | }, | ||
| 194 | { | ||
| 195 | .start = MXC_INT_I2C, | ||
| 196 | .end = MXC_INT_I2C, | ||
| 197 | .flags = IORESOURCE_IRQ, | ||
| 198 | }, | ||
| 199 | }; | ||
| 200 | |||
| 201 | struct platform_device mxc_i2c_device0 = { | ||
| 202 | .name = "imx-i2c", | ||
| 203 | .id = 0, | ||
| 204 | .num_resources = ARRAY_SIZE(mxc_i2c0_resources), | ||
| 205 | .resource = mxc_i2c0_resources, | ||
| 206 | }; | ||
| 207 | |||
| 208 | static struct resource mxc_i2c1_resources[] = { | ||
| 209 | { | ||
| 210 | .start = I2C2_BASE_ADDR, | ||
| 211 | .end = I2C2_BASE_ADDR + SZ_4K - 1, | ||
| 212 | .flags = IORESOURCE_MEM, | ||
| 213 | }, | ||
| 214 | { | ||
| 215 | .start = MXC_INT_I2C2, | ||
| 216 | .end = MXC_INT_I2C2, | ||
| 217 | .flags = IORESOURCE_IRQ, | ||
| 218 | }, | ||
| 219 | }; | ||
| 220 | |||
| 221 | struct platform_device mxc_i2c_device1 = { | ||
| 222 | .name = "imx-i2c", | ||
| 223 | .id = 1, | ||
| 224 | .num_resources = ARRAY_SIZE(mxc_i2c1_resources), | ||
| 225 | .resource = mxc_i2c1_resources, | ||
| 226 | }; | ||
| 227 | |||
| 228 | static struct resource mxc_i2c2_resources[] = { | ||
| 229 | { | ||
| 230 | .start = I2C3_BASE_ADDR, | ||
| 231 | .end = I2C3_BASE_ADDR + SZ_4K - 1, | ||
| 232 | .flags = IORESOURCE_MEM, | ||
| 233 | }, | ||
| 234 | { | ||
| 235 | .start = MXC_INT_I2C3, | ||
| 236 | .end = MXC_INT_I2C3, | ||
| 237 | .flags = IORESOURCE_IRQ, | ||
| 238 | }, | ||
| 239 | }; | ||
| 240 | |||
| 241 | struct platform_device mxc_i2c_device2 = { | ||
| 242 | .name = "imx-i2c", | ||
| 243 | .id = 2, | ||
| 244 | .num_resources = ARRAY_SIZE(mxc_i2c2_resources), | ||
| 245 | .resource = mxc_i2c2_resources, | ||
| 246 | }; | ||
| 247 | |||
| 248 | #ifdef CONFIG_ARCH_MX31 | ||
| 249 | static struct resource mxcsdhc0_resources[] = { | ||
| 250 | { | ||
| 251 | .start = MMC_SDHC1_BASE_ADDR, | ||
| 252 | .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1, | ||
| 253 | .flags = IORESOURCE_MEM, | ||
| 254 | }, { | ||
| 255 | .start = MXC_INT_MMC_SDHC1, | ||
| 256 | .end = MXC_INT_MMC_SDHC1, | ||
| 257 | .flags = IORESOURCE_IRQ, | ||
| 258 | }, | ||
| 259 | }; | ||
| 260 | |||
| 261 | static struct resource mxcsdhc1_resources[] = { | ||
| 262 | { | ||
| 263 | .start = MMC_SDHC2_BASE_ADDR, | ||
| 264 | .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1, | ||
| 265 | .flags = IORESOURCE_MEM, | ||
| 266 | }, { | ||
| 267 | .start = MXC_INT_MMC_SDHC2, | ||
| 268 | .end = MXC_INT_MMC_SDHC2, | ||
| 269 | .flags = IORESOURCE_IRQ, | ||
| 270 | }, | ||
| 271 | }; | ||
| 272 | |||
| 273 | struct platform_device mxcsdhc_device0 = { | ||
| 274 | .name = "mxc-mmc", | ||
| 275 | .id = 0, | ||
| 276 | .num_resources = ARRAY_SIZE(mxcsdhc0_resources), | ||
| 277 | .resource = mxcsdhc0_resources, | ||
| 278 | }; | ||
| 279 | |||
| 280 | struct platform_device mxcsdhc_device1 = { | ||
| 281 | .name = "mxc-mmc", | ||
| 282 | .id = 1, | ||
| 283 | .num_resources = ARRAY_SIZE(mxcsdhc1_resources), | ||
| 284 | .resource = mxcsdhc1_resources, | ||
| 285 | }; | ||
| 286 | #endif /* CONFIG_ARCH_MX31 */ | ||
| 287 | |||
| 288 | /* i.MX31 Image Processing Unit */ | ||
| 289 | |||
| 290 | /* The resource order is important! */ | ||
| 291 | static struct resource mx3_ipu_rsrc[] = { | ||
| 292 | { | ||
| 293 | .start = IPU_CTRL_BASE_ADDR, | ||
| 294 | .end = IPU_CTRL_BASE_ADDR + 0x5F, | ||
| 295 | .flags = IORESOURCE_MEM, | ||
| 296 | }, { | ||
| 297 | .start = IPU_CTRL_BASE_ADDR + 0x88, | ||
| 298 | .end = IPU_CTRL_BASE_ADDR + 0xB3, | ||
| 299 | .flags = IORESOURCE_MEM, | ||
| 300 | }, { | ||
| 301 | .start = MXC_INT_IPU_SYN, | ||
| 302 | .end = MXC_INT_IPU_SYN, | ||
| 303 | .flags = IORESOURCE_IRQ, | ||
| 304 | }, { | ||
| 305 | .start = MXC_INT_IPU_ERR, | ||
| 306 | .end = MXC_INT_IPU_ERR, | ||
| 307 | .flags = IORESOURCE_IRQ, | ||
| 308 | }, | ||
| 309 | }; | ||
| 310 | |||
| 311 | struct platform_device mx3_ipu = { | ||
| 312 | .name = "ipu-core", | ||
| 313 | .id = -1, | ||
| 314 | .num_resources = ARRAY_SIZE(mx3_ipu_rsrc), | ||
| 315 | .resource = mx3_ipu_rsrc, | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct resource fb_resources[] = { | ||
| 319 | { | ||
| 320 | .start = IPU_CTRL_BASE_ADDR + 0xB4, | ||
| 321 | .end = IPU_CTRL_BASE_ADDR + 0x1BF, | ||
| 322 | .flags = IORESOURCE_MEM, | ||
| 323 | }, | ||
| 324 | }; | ||
| 325 | |||
| 326 | struct platform_device mx3_fb = { | ||
| 327 | .name = "mx3_sdc_fb", | ||
| 328 | .id = -1, | ||
| 329 | .num_resources = ARRAY_SIZE(fb_resources), | ||
| 330 | .resource = fb_resources, | ||
| 331 | .dev = { | ||
| 332 | .coherent_dma_mask = 0xffffffff, | ||
| 333 | }, | ||
| 334 | }; | ||
| 335 | |||
| 336 | #ifdef CONFIG_ARCH_MX35 | ||
| 337 | static struct resource mxc_fec_resources[] = { | ||
| 338 | { | ||
| 339 | .start = MXC_FEC_BASE_ADDR, | ||
| 340 | .end = MXC_FEC_BASE_ADDR + 0xfff, | ||
| 341 | .flags = IORESOURCE_MEM | ||
| 342 | }, { | ||
| 343 | .start = MXC_INT_FEC, | ||
| 344 | .end = MXC_INT_FEC, | ||
| 345 | .flags = IORESOURCE_IRQ | ||
| 346 | }, | ||
| 347 | }; | ||
| 348 | |||
| 349 | struct platform_device mxc_fec_device = { | ||
| 350 | .name = "fec", | ||
| 351 | .id = 0, | ||
| 352 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | ||
| 353 | .resource = mxc_fec_resources, | ||
| 354 | }; | ||
| 355 | #endif | ||
| 356 | |||
| 357 | static int mx3_devices_init(void) | ||
| 358 | { | ||
| 359 | if (cpu_is_mx31()) { | ||
| 360 | mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; | ||
| 361 | mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; | ||
| 362 | } | ||
| 363 | if (cpu_is_mx35()) { | ||
| 364 | mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; | ||
| 365 | mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; | ||
| 366 | } | ||
| 367 | |||
| 368 | return 0; | ||
| 369 | } | ||
| 370 | |||
| 371 | subsys_initcall(mx3_devices_init); | ||
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 9949ef4e0694..88c04b296fab 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h | |||
| @@ -6,3 +6,11 @@ extern struct platform_device mxc_uart_device3; | |||
| 6 | extern struct platform_device mxc_uart_device4; | 6 | extern struct platform_device mxc_uart_device4; |
| 7 | extern struct platform_device mxc_w1_master_device; | 7 | extern struct platform_device mxc_w1_master_device; |
| 8 | extern struct platform_device mxc_nand_device; | 8 | extern struct platform_device mxc_nand_device; |
| 9 | extern struct platform_device mxc_i2c_device0; | ||
| 10 | extern struct platform_device mxc_i2c_device1; | ||
| 11 | extern struct platform_device mxc_i2c_device2; | ||
| 12 | extern struct platform_device mx3_ipu; | ||
| 13 | extern struct platform_device mx3_fb; | ||
| 14 | extern struct platform_device mxc_fec_device; | ||
| 15 | extern struct platform_device mxcsdhc_device0; | ||
| 16 | extern struct platform_device mxcsdhc_device1; | ||
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c index 7a5088b519a8..40ffc5a664d9 100644 --- a/arch/arm/mach-mx3/iomux.c +++ b/arch/arm/mach-mx3/iomux.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> |
| 4 | * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch> | ||
| 4 | * | 5 | * |
| 5 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License | 7 | * modify it under the terms of the GNU General Public License |
| @@ -21,6 +22,7 @@ | |||
| 21 | #include <linux/spinlock.h> | 22 | #include <linux/spinlock.h> |
| 22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 23 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
| 25 | #include <linux/kernel.h> | ||
| 24 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 25 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
| 26 | #include <mach/iomux-mx3.h> | 28 | #include <mach/iomux-mx3.h> |
| @@ -38,6 +40,8 @@ | |||
| 38 | static DEFINE_SPINLOCK(gpio_mux_lock); | 40 | static DEFINE_SPINLOCK(gpio_mux_lock); |
| 39 | 41 | ||
| 40 | #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) | 42 | #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) |
| 43 | |||
| 44 | unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; | ||
| 41 | /* | 45 | /* |
| 42 | * set the mode for a IOMUX pin. | 46 | * set the mode for a IOMUX pin. |
| 43 | */ | 47 | */ |
| @@ -50,9 +54,6 @@ int mxc_iomux_mode(unsigned int pin_mode) | |||
| 50 | field = pin_mode & 0x3; | 54 | field = pin_mode & 0x3; |
| 51 | mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; | 55 | mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; |
| 52 | 56 | ||
| 53 | pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n", | ||
| 54 | __func__, (pin_mode & IOMUX_REG_MASK), field, mode); | ||
| 55 | |||
| 56 | spin_lock(&gpio_mux_lock); | 57 | spin_lock(&gpio_mux_lock); |
| 57 | 58 | ||
| 58 | l = __raw_readl(reg); | 59 | l = __raw_readl(reg); |
| @@ -93,6 +94,86 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) | |||
| 93 | EXPORT_SYMBOL(mxc_iomux_set_pad); | 94 | EXPORT_SYMBOL(mxc_iomux_set_pad); |
| 94 | 95 | ||
| 95 | /* | 96 | /* |
| 97 | * setups a single pin: | ||
| 98 | * - reserves the pin so that it is not claimed by another driver | ||
| 99 | * - setups the iomux according to the configuration | ||
| 100 | * - if the pin is configured as a GPIO, we claim it through kernel gpiolib | ||
| 101 | */ | ||
| 102 | int mxc_iomux_setup_pin(const unsigned int pin, const char *label) | ||
| 103 | { | ||
| 104 | unsigned pad = pin & IOMUX_PADNUM_MASK; | ||
| 105 | unsigned gpio; | ||
| 106 | |||
| 107 | if (pad >= (PIN_MAX + 1)) { | ||
| 108 | printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", | ||
| 109 | pad, label ? label : "?"); | ||
| 110 | return -EINVAL; | ||
| 111 | } | ||
| 112 | |||
| 113 | if (test_and_set_bit(pad, mxc_pin_alloc_map)) { | ||
| 114 | printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", | ||
| 115 | pad, label ? label : "?"); | ||
| 116 | return -EINVAL; | ||
| 117 | } | ||
| 118 | mxc_iomux_mode(pin); | ||
| 119 | |||
| 120 | /* if we have a gpio, we can allocate it */ | ||
| 121 | gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; | ||
| 122 | if (gpio < (GPIO_PORT_MAX + 1) * 32) | ||
| 123 | if (gpio_request(gpio, label)) | ||
| 124 | return -EINVAL; | ||
| 125 | |||
| 126 | return 0; | ||
| 127 | } | ||
| 128 | EXPORT_SYMBOL(mxc_iomux_setup_pin); | ||
| 129 | |||
| 130 | int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, | ||
| 131 | const char *label) | ||
| 132 | { | ||
| 133 | unsigned int *p = pin_list; | ||
| 134 | int i; | ||
| 135 | int ret = -EINVAL; | ||
| 136 | |||
| 137 | for (i = 0; i < count; i++) { | ||
| 138 | if (mxc_iomux_setup_pin(*p, label)) | ||
| 139 | goto setup_error; | ||
| 140 | p++; | ||
| 141 | } | ||
| 142 | return 0; | ||
| 143 | |||
| 144 | setup_error: | ||
| 145 | mxc_iomux_release_multiple_pins(pin_list, i); | ||
| 146 | return ret; | ||
| 147 | } | ||
| 148 | EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); | ||
| 149 | |||
| 150 | void mxc_iomux_release_pin(const unsigned int pin) | ||
| 151 | { | ||
| 152 | unsigned pad = pin & IOMUX_PADNUM_MASK; | ||
| 153 | unsigned gpio; | ||
| 154 | |||
| 155 | if (pad < (PIN_MAX + 1)) | ||
| 156 | clear_bit(pad, mxc_pin_alloc_map); | ||
| 157 | |||
| 158 | gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; | ||
| 159 | if (gpio < (GPIO_PORT_MAX + 1) * 32) | ||
| 160 | gpio_free(gpio); | ||
| 161 | } | ||
| 162 | EXPORT_SYMBOL(mxc_iomux_release_pin); | ||
| 163 | |||
| 164 | void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) | ||
| 165 | { | ||
| 166 | unsigned int *p = pin_list; | ||
| 167 | int i; | ||
| 168 | |||
| 169 | for (i = 0; i < count; i++) { | ||
| 170 | mxc_iomux_release_pin(*p); | ||
| 171 | p++; | ||
| 172 | } | ||
| 173 | } | ||
| 174 | EXPORT_SYMBOL(mxc_iomux_release_multiple_pins); | ||
| 175 | |||
| 176 | /* | ||
| 96 | * This function enables/disables the general purpose function for a particular | 177 | * This function enables/disables the general purpose function for a particular |
| 97 | * signal. | 178 | * signal. |
| 98 | */ | 179 | */ |
| @@ -111,4 +192,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en) | |||
| 111 | spin_unlock(&gpio_mux_lock); | 192 | spin_unlock(&gpio_mux_lock); |
| 112 | } | 193 | } |
| 113 | EXPORT_SYMBOL(mxc_iomux_set_gpr); | 194 | EXPORT_SYMBOL(mxc_iomux_set_gpr); |
| 114 | |||
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 0589b5cd33c7..9e1459cb4b74 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c | |||
| @@ -22,10 +22,14 @@ | |||
| 22 | 22 | ||
| 23 | #include <linux/mm.h> | 23 | #include <linux/mm.h> |
| 24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
| 25 | #include <mach/hardware.h> | 25 | #include <linux/err.h> |
| 26 | |||
| 26 | #include <asm/pgtable.h> | 27 | #include <asm/pgtable.h> |
| 27 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | #include <asm/hardware/cache-l2x0.h> | ||
| 30 | |||
| 28 | #include <mach/common.h> | 31 | #include <mach/common.h> |
| 32 | #include <mach/hardware.h> | ||
| 29 | 33 | ||
| 30 | /*! | 34 | /*! |
| 31 | * @file mm.c | 35 | * @file mm.c |
| @@ -50,6 +54,16 @@ static struct map_desc mxc_io_desc[] __initdata = { | |||
| 50 | .pfn = __phys_to_pfn(AVIC_BASE_ADDR), | 54 | .pfn = __phys_to_pfn(AVIC_BASE_ADDR), |
| 51 | .length = AVIC_SIZE, | 55 | .length = AVIC_SIZE, |
| 52 | .type = MT_DEVICE_NONSHARED | 56 | .type = MT_DEVICE_NONSHARED |
| 57 | }, { | ||
| 58 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 59 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 60 | .length = AIPS1_SIZE, | ||
| 61 | .type = MT_DEVICE_NONSHARED | ||
| 62 | }, { | ||
| 63 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 64 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 65 | .length = AIPS2_SIZE, | ||
| 66 | .type = MT_DEVICE_NONSHARED | ||
| 53 | }, | 67 | }, |
| 54 | }; | 68 | }; |
| 55 | 69 | ||
| @@ -62,3 +76,24 @@ void __init mxc_map_io(void) | |||
| 62 | { | 76 | { |
| 63 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 77 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); |
| 64 | } | 78 | } |
| 79 | |||
| 80 | #ifdef CONFIG_CACHE_L2X0 | ||
| 81 | static int mxc_init_l2x0(void) | ||
| 82 | { | ||
| 83 | void __iomem *l2x0_base; | ||
| 84 | |||
| 85 | l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); | ||
| 86 | if (IS_ERR(l2x0_base)) { | ||
| 87 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", | ||
| 88 | PTR_ERR(l2x0_base)); | ||
| 89 | return 0; | ||
| 90 | } | ||
| 91 | |||
| 92 | l2x0_init(l2x0_base, 0x00030024, 0x00000000); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
| 96 | |||
| 97 | arch_initcall(mxc_init_l2x0); | ||
| 98 | #endif | ||
| 99 | |||
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index f902a7c37c31..83e5e8e1276f 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c | |||
| @@ -22,6 +22,8 @@ | |||
| 22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/serial_8250.h> | 24 | #include <linux/serial_8250.h> |
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/i2c.h> | ||
| 25 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
| 26 | 28 | ||
| 27 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| @@ -35,6 +37,12 @@ | |||
| 35 | #include <mach/imx-uart.h> | 37 | #include <mach/imx-uart.h> |
| 36 | #include <mach/iomux-mx3.h> | 38 | #include <mach/iomux-mx3.h> |
| 37 | 39 | ||
| 40 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | ||
| 41 | #include <linux/mfd/wm8350/audio.h> | ||
| 42 | #include <linux/mfd/wm8350/core.h> | ||
| 43 | #include <linux/mfd/wm8350/pmic.h> | ||
| 44 | #endif | ||
| 45 | |||
| 38 | #include "devices.h" | 46 | #include "devices.h" |
| 39 | 47 | ||
| 40 | /*! | 48 | /*! |
| @@ -94,13 +102,16 @@ static struct imxuart_platform_data uart_pdata = { | |||
| 94 | .flags = IMXUART_HAVE_RTSCTS, | 102 | .flags = IMXUART_HAVE_RTSCTS, |
| 95 | }; | 103 | }; |
| 96 | 104 | ||
| 105 | static int uart_pins[] = { | ||
| 106 | MX31_PIN_CTS1__CTS1, | ||
| 107 | MX31_PIN_RTS1__RTS1, | ||
| 108 | MX31_PIN_TXD1__TXD1, | ||
| 109 | MX31_PIN_RXD1__RXD1 | ||
| 110 | }; | ||
| 111 | |||
| 97 | static inline void mxc_init_imx_uart(void) | 112 | static inline void mxc_init_imx_uart(void) |
| 98 | { | 113 | { |
| 99 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 114 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); |
| 100 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | ||
| 101 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | ||
| 102 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 103 | |||
| 104 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 115 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 105 | } | 116 | } |
| 106 | #else /* !SERIAL_IMX */ | 117 | #else /* !SERIAL_IMX */ |
| @@ -176,7 +187,7 @@ static void __init mx31ads_init_expio(void) | |||
| 176 | /* | 187 | /* |
| 177 | * Configure INT line as GPIO input | 188 | * Configure INT line as GPIO input |
| 178 | */ | 189 | */ |
| 179 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO)); | 190 | mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); |
| 180 | 191 | ||
| 181 | /* disable the interrupt and clear the status */ | 192 | /* disable the interrupt and clear the status */ |
| 182 | __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); | 193 | __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); |
| @@ -191,26 +202,301 @@ static void __init mx31ads_init_expio(void) | |||
| 191 | set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); | 202 | set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); |
| 192 | } | 203 | } |
| 193 | 204 | ||
| 205 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | ||
| 206 | /* This section defines setup for the Wolfson Microelectronics | ||
| 207 | * 1133-EV1 PMU/audio board. When other PMU boards are supported the | ||
| 208 | * regulator definitions may be shared with them, but for now they can | ||
| 209 | * only be used with this board so would generate warnings about | ||
| 210 | * unused statics and some of the configuration is specific to this | ||
| 211 | * module. | ||
| 212 | */ | ||
| 213 | |||
| 214 | /* CPU */ | ||
| 215 | static struct regulator_consumer_supply sw1a_consumers[] = { | ||
| 216 | { | ||
| 217 | .supply = "cpu_vcc", | ||
| 218 | } | ||
| 219 | }; | ||
| 220 | |||
| 221 | static struct regulator_init_data sw1a_data = { | ||
| 222 | .constraints = { | ||
| 223 | .name = "SW1A", | ||
| 224 | .min_uV = 1275000, | ||
| 225 | .max_uV = 1600000, | ||
| 226 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | ||
| 227 | REGULATOR_CHANGE_MODE, | ||
| 228 | .valid_modes_mask = REGULATOR_MODE_NORMAL | | ||
| 229 | REGULATOR_MODE_FAST, | ||
| 230 | .state_mem = { | ||
| 231 | .uV = 1400000, | ||
| 232 | .mode = REGULATOR_MODE_NORMAL, | ||
| 233 | .enabled = 1, | ||
| 234 | }, | ||
| 235 | .initial_state = PM_SUSPEND_MEM, | ||
| 236 | .always_on = 1, | ||
| 237 | .boot_on = 1, | ||
| 238 | }, | ||
| 239 | .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers), | ||
| 240 | .consumer_supplies = sw1a_consumers, | ||
| 241 | }; | ||
| 242 | |||
| 243 | /* System IO - High */ | ||
| 244 | static struct regulator_init_data viohi_data = { | ||
| 245 | .constraints = { | ||
| 246 | .name = "VIOHO", | ||
| 247 | .min_uV = 2800000, | ||
| 248 | .max_uV = 2800000, | ||
| 249 | .state_mem = { | ||
| 250 | .uV = 2800000, | ||
| 251 | .mode = REGULATOR_MODE_NORMAL, | ||
| 252 | .enabled = 1, | ||
| 253 | }, | ||
| 254 | .initial_state = PM_SUSPEND_MEM, | ||
| 255 | .always_on = 1, | ||
| 256 | .boot_on = 1, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | |||
| 260 | /* System IO - Low */ | ||
| 261 | static struct regulator_init_data violo_data = { | ||
| 262 | .constraints = { | ||
| 263 | .name = "VIOLO", | ||
| 264 | .min_uV = 1800000, | ||
| 265 | .max_uV = 1800000, | ||
| 266 | .state_mem = { | ||
| 267 | .uV = 1800000, | ||
| 268 | .mode = REGULATOR_MODE_NORMAL, | ||
| 269 | .enabled = 1, | ||
| 270 | }, | ||
| 271 | .initial_state = PM_SUSPEND_MEM, | ||
| 272 | .always_on = 1, | ||
| 273 | .boot_on = 1, | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | /* DDR RAM */ | ||
| 278 | static struct regulator_init_data sw2a_data = { | ||
| 279 | .constraints = { | ||
| 280 | .name = "SW2A", | ||
| 281 | .min_uV = 1800000, | ||
| 282 | .max_uV = 1800000, | ||
| 283 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 284 | .state_mem = { | ||
| 285 | .uV = 1800000, | ||
| 286 | .mode = REGULATOR_MODE_NORMAL, | ||
| 287 | .enabled = 1, | ||
| 288 | }, | ||
| 289 | .state_disk = { | ||
| 290 | .mode = REGULATOR_MODE_NORMAL, | ||
| 291 | .enabled = 0, | ||
| 292 | }, | ||
| 293 | .always_on = 1, | ||
| 294 | .boot_on = 1, | ||
| 295 | .initial_state = PM_SUSPEND_MEM, | ||
| 296 | }, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct regulator_init_data ldo1_data = { | ||
| 300 | .constraints = { | ||
| 301 | .name = "VCAM/VMMC1/VMMC2", | ||
| 302 | .min_uV = 2800000, | ||
| 303 | .max_uV = 2800000, | ||
| 304 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 305 | .apply_uV = 1, | ||
| 306 | }, | ||
| 307 | }; | ||
| 308 | |||
| 309 | static struct regulator_consumer_supply ldo2_consumers[] = { | ||
| 310 | { | ||
| 311 | .supply = "AVDD", | ||
| 312 | }, | ||
| 313 | { | ||
| 314 | .supply = "HPVDD", | ||
| 315 | }, | ||
| 316 | }; | ||
| 317 | |||
| 318 | /* CODEC and SIM */ | ||
| 319 | static struct regulator_init_data ldo2_data = { | ||
| 320 | .constraints = { | ||
| 321 | .name = "VESIM/VSIM/AVDD", | ||
| 322 | .min_uV = 3300000, | ||
| 323 | .max_uV = 3300000, | ||
| 324 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 325 | .apply_uV = 1, | ||
| 326 | }, | ||
| 327 | .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), | ||
| 328 | .consumer_supplies = ldo2_consumers, | ||
| 329 | }; | ||
| 330 | |||
| 331 | /* General */ | ||
| 332 | static struct regulator_init_data vdig_data = { | ||
| 333 | .constraints = { | ||
| 334 | .name = "VDIG", | ||
| 335 | .min_uV = 1500000, | ||
| 336 | .max_uV = 1500000, | ||
| 337 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 338 | .apply_uV = 1, | ||
| 339 | .always_on = 1, | ||
| 340 | .boot_on = 1, | ||
| 341 | }, | ||
| 342 | }; | ||
| 343 | |||
| 344 | /* Tranceivers */ | ||
| 345 | static struct regulator_init_data ldo4_data = { | ||
| 346 | .constraints = { | ||
| 347 | .name = "VRF1/CVDD_2.775", | ||
| 348 | .min_uV = 2500000, | ||
| 349 | .max_uV = 2500000, | ||
| 350 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 351 | .apply_uV = 1, | ||
| 352 | .always_on = 1, | ||
| 353 | .boot_on = 1, | ||
| 354 | }, | ||
| 355 | }; | ||
| 356 | |||
| 357 | static struct wm8350_led_platform_data wm8350_led_data = { | ||
| 358 | .name = "wm8350:white", | ||
| 359 | .default_trigger = "heartbeat", | ||
| 360 | .max_uA = 27899, | ||
| 361 | }; | ||
| 362 | |||
| 363 | static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { | ||
| 364 | .vmid_discharge_msecs = 1000, | ||
| 365 | .drain_msecs = 30, | ||
| 366 | .cap_discharge_msecs = 700, | ||
| 367 | .vmid_charge_msecs = 700, | ||
| 368 | .vmid_s_curve = WM8350_S_CURVE_SLOW, | ||
| 369 | .dis_out4 = WM8350_DISCHARGE_SLOW, | ||
| 370 | .dis_out3 = WM8350_DISCHARGE_SLOW, | ||
| 371 | .dis_out2 = WM8350_DISCHARGE_SLOW, | ||
| 372 | .dis_out1 = WM8350_DISCHARGE_SLOW, | ||
| 373 | .vroi_out4 = WM8350_TIE_OFF_500R, | ||
| 374 | .vroi_out3 = WM8350_TIE_OFF_500R, | ||
| 375 | .vroi_out2 = WM8350_TIE_OFF_500R, | ||
| 376 | .vroi_out1 = WM8350_TIE_OFF_500R, | ||
| 377 | .vroi_enable = 0, | ||
| 378 | .codec_current_on = WM8350_CODEC_ISEL_1_0, | ||
| 379 | .codec_current_standby = WM8350_CODEC_ISEL_0_5, | ||
| 380 | .codec_current_charge = WM8350_CODEC_ISEL_1_5, | ||
| 381 | }; | ||
| 382 | |||
| 383 | static int mx31_wm8350_init(struct wm8350 *wm8350) | ||
| 384 | { | ||
| 385 | int i; | ||
| 386 | |||
| 387 | wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, | ||
| 388 | WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, | ||
| 389 | WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, | ||
| 390 | WM8350_GPIO_DEBOUNCE_ON); | ||
| 391 | |||
| 392 | wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN, | ||
| 393 | WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH, | ||
| 394 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, | ||
| 395 | WM8350_GPIO_DEBOUNCE_ON); | ||
| 396 | |||
| 397 | wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, | ||
| 398 | WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, | ||
| 399 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, | ||
| 400 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 401 | |||
| 402 | wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, | ||
| 403 | WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH, | ||
| 404 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, | ||
| 405 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 406 | |||
| 407 | wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT, | ||
| 408 | WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH, | ||
| 409 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, | ||
| 410 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 411 | |||
| 412 | wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT, | ||
| 413 | WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, | ||
| 414 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, | ||
| 415 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 416 | |||
| 417 | wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, | ||
| 418 | WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, | ||
| 419 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, | ||
| 420 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 421 | |||
| 422 | /* Fix up for our own supplies. */ | ||
| 423 | for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++) | ||
| 424 | ldo2_consumers[i].dev = wm8350->dev; | ||
| 425 | |||
| 426 | wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); | ||
| 427 | wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); | ||
| 428 | wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); | ||
| 429 | wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data); | ||
| 430 | wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data); | ||
| 431 | wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data); | ||
| 432 | wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data); | ||
| 433 | wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data); | ||
| 434 | |||
| 435 | /* LEDs */ | ||
| 436 | wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1, | ||
| 437 | WM8350_DC5_ERRACT_SHUTDOWN_CONV); | ||
| 438 | wm8350_isink_set_flash(wm8350, WM8350_ISINK_A, | ||
| 439 | WM8350_ISINK_FLASH_DISABLE, | ||
| 440 | WM8350_ISINK_FLASH_TRIG_BIT, | ||
| 441 | WM8350_ISINK_FLASH_DUR_32MS, | ||
| 442 | WM8350_ISINK_FLASH_ON_INSTANT, | ||
| 443 | WM8350_ISINK_FLASH_OFF_INSTANT, | ||
| 444 | WM8350_ISINK_FLASH_MODE_EN); | ||
| 445 | wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5, | ||
| 446 | WM8350_ISINK_MODE_BOOST, | ||
| 447 | WM8350_ISINK_ILIM_NORMAL, | ||
| 448 | WM8350_DC5_RMP_20V, | ||
| 449 | WM8350_DC5_FBSRC_ISINKA); | ||
| 450 | wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A, | ||
| 451 | &wm8350_led_data); | ||
| 452 | |||
| 453 | wm8350->codec.platform_data = &imx32ads_wm8350_setup; | ||
| 454 | |||
| 455 | return 0; | ||
| 456 | } | ||
| 457 | |||
| 458 | static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { | ||
| 459 | .init = mx31_wm8350_init, | ||
| 460 | }; | ||
| 461 | #endif | ||
| 462 | |||
| 463 | #if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE) | ||
| 464 | static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { | ||
| 465 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | ||
| 466 | { | ||
| 467 | I2C_BOARD_INFO("wm8350", 0x1a), | ||
| 468 | .platform_data = &mx31_wm8350_pdata, | ||
| 469 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), | ||
| 470 | }, | ||
| 471 | #endif | ||
| 472 | }; | ||
| 473 | |||
| 474 | static void mxc_init_i2c(void) | ||
| 475 | { | ||
| 476 | i2c_register_board_info(1, mx31ads_i2c1_devices, | ||
| 477 | ARRAY_SIZE(mx31ads_i2c1_devices)); | ||
| 478 | |||
| 479 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); | ||
| 480 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); | ||
| 481 | |||
| 482 | mxc_register_device(&mxc_i2c_device1, NULL); | ||
| 483 | } | ||
| 484 | #else | ||
| 485 | static void mxc_init_i2c(void) | ||
| 486 | { | ||
| 487 | } | ||
| 488 | #endif | ||
| 489 | |||
| 194 | /*! | 490 | /*! |
| 195 | * This structure defines static mappings for the i.MX31ADS board. | 491 | * This structure defines static mappings for the i.MX31ADS board. |
| 196 | */ | 492 | */ |
| 197 | static struct map_desc mx31ads_io_desc[] __initdata = { | 493 | static struct map_desc mx31ads_io_desc[] __initdata = { |
| 198 | { | 494 | { |
| 199 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 200 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 201 | .length = AIPS1_SIZE, | ||
| 202 | .type = MT_DEVICE_NONSHARED | ||
| 203 | }, { | ||
| 204 | .virtual = SPBA0_BASE_ADDR_VIRT, | 495 | .virtual = SPBA0_BASE_ADDR_VIRT, |
| 205 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), | 496 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), |
| 206 | .length = SPBA0_SIZE, | 497 | .length = SPBA0_SIZE, |
| 207 | .type = MT_DEVICE_NONSHARED | 498 | .type = MT_DEVICE_NONSHARED |
| 208 | }, { | 499 | }, { |
| 209 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 210 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 211 | .length = AIPS2_SIZE, | ||
| 212 | .type = MT_DEVICE_NONSHARED | ||
| 213 | }, { | ||
| 214 | .virtual = CS4_BASE_ADDR_VIRT, | 500 | .virtual = CS4_BASE_ADDR_VIRT, |
| 215 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), | 501 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), |
| 216 | .length = CS4_SIZE / 2, | 502 | .length = CS4_SIZE / 2, |
| @@ -221,13 +507,13 @@ static struct map_desc mx31ads_io_desc[] __initdata = { | |||
| 221 | /*! | 507 | /*! |
| 222 | * Set up static virtual mappings. | 508 | * Set up static virtual mappings. |
| 223 | */ | 509 | */ |
| 224 | void __init mx31ads_map_io(void) | 510 | static void __init mx31ads_map_io(void) |
| 225 | { | 511 | { |
| 226 | mxc_map_io(); | 512 | mxc_map_io(); |
| 227 | iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); | 513 | iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); |
| 228 | } | 514 | } |
| 229 | 515 | ||
| 230 | void __init mx31ads_init_irq(void) | 516 | static void __init mx31ads_init_irq(void) |
| 231 | { | 517 | { |
| 232 | mxc_init_irq(); | 518 | mxc_init_irq(); |
| 233 | mx31ads_init_expio(); | 519 | mx31ads_init_expio(); |
| @@ -240,15 +526,15 @@ static void __init mxc_board_init(void) | |||
| 240 | { | 526 | { |
| 241 | mxc_init_extuart(); | 527 | mxc_init_extuart(); |
| 242 | mxc_init_imx_uart(); | 528 | mxc_init_imx_uart(); |
| 529 | mxc_init_i2c(); | ||
| 243 | } | 530 | } |
| 244 | 531 | ||
| 245 | static void __init mx31ads_timer_init(void) | 532 | static void __init mx31ads_timer_init(void) |
| 246 | { | 533 | { |
| 247 | mxc_clocks_init(26000000); | 534 | mx31_clocks_init(26000000); |
| 248 | mxc_timer_init("ipg_clk.0"); | ||
| 249 | } | 535 | } |
| 250 | 536 | ||
| 251 | struct sys_timer mx31ads_timer = { | 537 | static struct sys_timer mx31ads_timer = { |
| 252 | .init = mx31ads_timer_init, | 538 | .init = mx31ads_timer_init, |
| 253 | }; | 539 | }; |
| 254 | 540 | ||
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index c43440070143..894d98cd9941 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c | |||
| @@ -42,21 +42,11 @@ | |||
| 42 | */ | 42 | */ |
| 43 | static struct map_desc mx31lite_io_desc[] __initdata = { | 43 | static struct map_desc mx31lite_io_desc[] __initdata = { |
| 44 | { | 44 | { |
| 45 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 46 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 47 | .length = AIPS1_SIZE, | ||
| 48 | .type = MT_DEVICE_NONSHARED | ||
| 49 | }, { | ||
| 50 | .virtual = SPBA0_BASE_ADDR_VIRT, | 45 | .virtual = SPBA0_BASE_ADDR_VIRT, |
| 51 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), | 46 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), |
| 52 | .length = SPBA0_SIZE, | 47 | .length = SPBA0_SIZE, |
| 53 | .type = MT_DEVICE_NONSHARED | 48 | .type = MT_DEVICE_NONSHARED |
| 54 | }, { | 49 | }, { |
| 55 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 56 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 57 | .length = AIPS2_SIZE, | ||
| 58 | .type = MT_DEVICE_NONSHARED | ||
| 59 | }, { | ||
| 60 | .virtual = CS4_BASE_ADDR_VIRT, | 50 | .virtual = CS4_BASE_ADDR_VIRT, |
| 61 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), | 51 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), |
| 62 | .length = CS4_SIZE, | 52 | .length = CS4_SIZE, |
| @@ -82,8 +72,7 @@ static void __init mxc_board_init(void) | |||
| 82 | 72 | ||
| 83 | static void __init mx31lite_timer_init(void) | 73 | static void __init mx31lite_timer_init(void) |
| 84 | { | 74 | { |
| 85 | mxc_clocks_init(26000000); | 75 | mx31_clocks_init(26000000); |
| 86 | mxc_timer_init("ipg_clk.0"); | ||
| 87 | } | 76 | } |
| 88 | 77 | ||
| 89 | struct sys_timer mx31lite_timer = { | 78 | struct sys_timer mx31lite_timer = { |
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c new file mode 100644 index 000000000000..d080b4add79c --- /dev/null +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | |||
| 22 | #include <linux/platform_device.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/common.h> | ||
| 26 | #include <mach/imx-uart.h> | ||
| 27 | #include <mach/iomux-mx3.h> | ||
| 28 | |||
| 29 | #include "devices.h" | ||
| 30 | |||
| 31 | static struct imxuart_platform_data uart_pdata = { | ||
| 32 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 33 | }; | ||
| 34 | |||
| 35 | static int mxc_uart1_pins[] = { | ||
| 36 | MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, | ||
| 37 | MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* | ||
| 41 | * system init for baseboard usage. Will be called by mx31moboard init. | ||
| 42 | */ | ||
| 43 | void __init mx31moboard_devboard_init(void) | ||
| 44 | { | ||
| 45 | printk(KERN_INFO "Initializing mx31devboard peripherals\n"); | ||
| 46 | mxc_iomux_setup_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins), "uart1"); | ||
| 47 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | ||
| 48 | } | ||
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c new file mode 100644 index 000000000000..9ef9566823fb --- /dev/null +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | |||
| 22 | #include <linux/platform_device.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/common.h> | ||
| 26 | #include <mach/imx-uart.h> | ||
| 27 | #include <mach/iomux-mx3.h> | ||
| 28 | |||
| 29 | #include "devices.h" | ||
| 30 | |||
| 31 | /* | ||
| 32 | * system init for baseboard usage. Will be called by mx31moboard init. | ||
| 33 | */ | ||
| 34 | void __init mx31moboard_marxbot_init(void) | ||
| 35 | { | ||
| 36 | printk(KERN_INFO "Initializing mx31marxbot peripherals\n"); | ||
| 37 | } | ||
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index c29098af7394..34c2a1b99d4f 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <mach/common.h> | 32 | #include <mach/common.h> |
| 33 | #include <mach/imx-uart.h> | 33 | #include <mach/imx-uart.h> |
| 34 | #include <mach/iomux-mx3.h> | 34 | #include <mach/iomux-mx3.h> |
| 35 | #include <mach/board-mx31moboard.h> | ||
| 35 | 36 | ||
| 36 | #include "devices.h" | 37 | #include "devices.h" |
| 37 | 38 | ||
| @@ -63,6 +64,18 @@ static struct platform_device *devices[] __initdata = { | |||
| 63 | &mx31moboard_flash, | 64 | &mx31moboard_flash, |
| 64 | }; | 65 | }; |
| 65 | 66 | ||
| 67 | static int mxc_uart0_pins[] = { | ||
| 68 | MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, | ||
| 69 | MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, | ||
| 70 | }; | ||
| 71 | static int mxc_uart4_pins[] = { | ||
| 72 | MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, | ||
| 73 | MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static int mx31moboard_baseboard; | ||
| 77 | core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); | ||
| 78 | |||
| 66 | /* | 79 | /* |
| 67 | * Board specific initialization. | 80 | * Board specific initialization. |
| 68 | */ | 81 | */ |
| @@ -70,58 +83,29 @@ static void __init mxc_board_init(void) | |||
| 70 | { | 83 | { |
| 71 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 84 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 72 | 85 | ||
| 73 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 86 | mxc_iomux_setup_multiple_pins(mxc_uart0_pins, ARRAY_SIZE(mxc_uart0_pins), "uart0"); |
| 74 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | ||
| 75 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | ||
| 76 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 77 | |||
| 78 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 87 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 79 | 88 | ||
| 80 | mxc_iomux_mode(MX31_PIN_CTS2__CTS2); | 89 | mxc_iomux_setup_multiple_pins(mxc_uart4_pins, ARRAY_SIZE(mxc_uart4_pins), "uart4"); |
| 81 | mxc_iomux_mode(MX31_PIN_RTS2__RTS2); | ||
| 82 | mxc_iomux_mode(MX31_PIN_TXD2__TXD2); | ||
| 83 | mxc_iomux_mode(MX31_PIN_RXD2__RXD2); | ||
| 84 | |||
| 85 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | ||
| 86 | |||
| 87 | mxc_iomux_mode(MX31_PIN_PC_RST__CTS5); | ||
| 88 | mxc_iomux_mode(MX31_PIN_PC_VS2__RTS5); | ||
| 89 | mxc_iomux_mode(MX31_PIN_PC_BVD2__TXD5); | ||
| 90 | mxc_iomux_mode(MX31_PIN_PC_BVD1__RXD5); | ||
| 91 | |||
| 92 | mxc_register_device(&mxc_uart_device4, &uart_pdata); | 90 | mxc_register_device(&mxc_uart_device4, &uart_pdata); |
| 93 | } | ||
| 94 | 91 | ||
| 95 | /* | 92 | switch (mx31moboard_baseboard) { |
| 96 | * This structure defines static mappings for the mx31moboard. | 93 | case MX31NOBOARD: |
| 97 | */ | 94 | break; |
| 98 | static struct map_desc mx31moboard_io_desc[] __initdata = { | 95 | case MX31DEVBOARD: |
| 99 | { | 96 | mx31moboard_devboard_init(); |
| 100 | .virtual = AIPS1_BASE_ADDR_VIRT, | 97 | break; |
| 101 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | 98 | case MX31MARXBOT: |
| 102 | .length = AIPS1_SIZE, | 99 | mx31moboard_marxbot_init(); |
| 103 | .type = MT_DEVICE_NONSHARED | 100 | break; |
| 104 | }, { | 101 | default: |
| 105 | .virtual = AIPS2_BASE_ADDR_VIRT, | 102 | printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard); |
| 106 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | 103 | } |
| 107 | .length = AIPS2_SIZE, | ||
| 108 | .type = MT_DEVICE_NONSHARED | ||
| 109 | }, | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* | ||
| 113 | * Set up static virtual mappings. | ||
| 114 | */ | ||
| 115 | void __init mx31moboard_map_io(void) | ||
| 116 | { | ||
| 117 | mxc_map_io(); | ||
| 118 | iotable_init(mx31moboard_io_desc, ARRAY_SIZE(mx31moboard_io_desc)); | ||
| 119 | } | 104 | } |
| 120 | 105 | ||
| 121 | static void __init mx31moboard_timer_init(void) | 106 | static void __init mx31moboard_timer_init(void) |
| 122 | { | 107 | { |
| 123 | mxc_clocks_init(26000000); | 108 | mx31_clocks_init(26000000); |
| 124 | mxc_timer_init("ipg_clk.0"); | ||
| 125 | } | 109 | } |
| 126 | 110 | ||
| 127 | struct sys_timer mx31moboard_timer = { | 111 | struct sys_timer mx31moboard_timer = { |
| @@ -133,7 +117,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") | |||
| 133 | .phys_io = AIPS1_BASE_ADDR, | 117 | .phys_io = AIPS1_BASE_ADDR, |
| 134 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 118 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
| 135 | .boot_params = PHYS_OFFSET + 0x100, | 119 | .boot_params = PHYS_OFFSET + 0x100, |
| 136 | .map_io = mx31moboard_map_io, | 120 | .map_io = mxc_map_io, |
| 137 | .init_irq = mxc_init_irq, | 121 | .init_irq = mxc_init_irq, |
| 138 | .init_machine = mxc_board_init, | 122 | .init_machine = mxc_board_init, |
| 139 | .timer = &mx31moboard_timer, | 123 | .timer = &mx31moboard_timer, |
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c index d464d068a4a6..bc63f1785691 100644 --- a/arch/arm/mach-mx3/mx31pdk.c +++ b/arch/arm/mach-mx3/mx31pdk.c | |||
| @@ -45,40 +45,17 @@ static struct imxuart_platform_data uart_pdata = { | |||
| 45 | .flags = IMXUART_HAVE_RTSCTS, | 45 | .flags = IMXUART_HAVE_RTSCTS, |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | static inline void mxc_init_imx_uart(void) | 48 | static int uart_pins[] = { |
| 49 | { | 49 | MX31_PIN_CTS1__CTS1, |
| 50 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 50 | MX31_PIN_RTS1__RTS1, |
| 51 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | 51 | MX31_PIN_TXD1__TXD1, |
| 52 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | 52 | MX31_PIN_RXD1__RXD1 |
| 53 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 54 | |||
| 55 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | ||
| 56 | } | ||
| 57 | |||
| 58 | /*! | ||
| 59 | * This structure defines static mappings for the i.MX31PDK board. | ||
| 60 | */ | ||
| 61 | static struct map_desc mx31pdk_io_desc[] __initdata = { | ||
| 62 | { | ||
| 63 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 64 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 65 | .length = AIPS1_SIZE, | ||
| 66 | .type = MT_DEVICE_NONSHARED | ||
| 67 | }, { | ||
| 68 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 69 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 70 | .length = AIPS2_SIZE, | ||
| 71 | .type = MT_DEVICE_NONSHARED | ||
| 72 | }, | ||
| 73 | }; | 53 | }; |
| 74 | 54 | ||
| 75 | /*! | 55 | static inline void mxc_init_imx_uart(void) |
| 76 | * Set up static virtual mappings. | ||
| 77 | */ | ||
| 78 | static void __init mx31pdk_map_io(void) | ||
| 79 | { | 56 | { |
| 80 | mxc_map_io(); | 57 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); |
| 81 | iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); | 58 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 82 | } | 59 | } |
| 83 | 60 | ||
| 84 | /*! | 61 | /*! |
| @@ -91,8 +68,7 @@ static void __init mxc_board_init(void) | |||
| 91 | 68 | ||
| 92 | static void __init mx31pdk_timer_init(void) | 69 | static void __init mx31pdk_timer_init(void) |
| 93 | { | 70 | { |
| 94 | mxc_clocks_init(26000000); | 71 | mx31_clocks_init(26000000); |
| 95 | mxc_timer_init("ipg_clk.0"); | ||
| 96 | } | 72 | } |
| 97 | 73 | ||
| 98 | static struct sys_timer mx31pdk_timer = { | 74 | static struct sys_timer mx31pdk_timer = { |
| @@ -108,7 +84,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") | |||
| 108 | .phys_io = AIPS1_BASE_ADDR, | 84 | .phys_io = AIPS1_BASE_ADDR, |
| 109 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 85 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
| 110 | .boot_params = PHYS_OFFSET + 0x100, | 86 | .boot_params = PHYS_OFFSET + 0x100, |
| 111 | .map_io = mx31pdk_map_io, | 87 | .map_io = mxc_map_io, |
| 112 | .init_irq = mxc_init_irq, | 88 | .init_irq = mxc_init_irq, |
| 113 | .init_machine = mxc_board_init, | 89 | .init_machine = mxc_board_init, |
| 114 | .timer = &mx31pdk_timer, | 90 | .timer = &mx31pdk_timer, |
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index 8cea82587222..5fce022114de 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c | |||
| @@ -26,6 +26,8 @@ | |||
| 26 | #include <linux/gpio.h> | 26 | #include <linux/gpio.h> |
| 27 | #include <linux/smc911x.h> | 27 | #include <linux/smc911x.h> |
| 28 | #include <linux/interrupt.h> | 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/i2c.h> | ||
| 30 | #include <linux/i2c/at24.h> | ||
| 29 | 31 | ||
| 30 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 31 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| @@ -37,6 +39,10 @@ | |||
| 37 | #include <mach/iomux-mx3.h> | 39 | #include <mach/iomux-mx3.h> |
| 38 | #include <mach/board-pcm037.h> | 40 | #include <mach/board-pcm037.h> |
| 39 | #include <mach/mxc_nand.h> | 41 | #include <mach/mxc_nand.h> |
| 42 | #include <mach/mmc.h> | ||
| 43 | #ifdef CONFIG_I2C_IMX | ||
| 44 | #include <mach/i2c.h> | ||
| 45 | #endif | ||
| 40 | 46 | ||
| 41 | #include "devices.h" | 47 | #include "devices.h" |
| 42 | 48 | ||
| @@ -117,12 +123,90 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = { | |||
| 117 | .hw_ecc = 1, | 123 | .hw_ecc = 1, |
| 118 | }; | 124 | }; |
| 119 | 125 | ||
| 126 | #ifdef CONFIG_I2C_IMX | ||
| 127 | static int i2c_1_pins[] = { | ||
| 128 | MX31_PIN_CSPI2_MOSI__SCL, | ||
| 129 | MX31_PIN_CSPI2_MISO__SDA, | ||
| 130 | }; | ||
| 131 | |||
| 132 | static int pcm037_i2c_1_init(struct device *dev) | ||
| 133 | { | ||
| 134 | return mxc_iomux_setup_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins), | ||
| 135 | "i2c-1"); | ||
| 136 | } | ||
| 137 | |||
| 138 | static void pcm037_i2c_1_exit(struct device *dev) | ||
| 139 | { | ||
| 140 | mxc_iomux_release_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins)); | ||
| 141 | } | ||
| 142 | |||
| 143 | static struct imxi2c_platform_data pcm037_i2c_1_data = { | ||
| 144 | .bitrate = 100000, | ||
| 145 | .init = pcm037_i2c_1_init, | ||
| 146 | .exit = pcm037_i2c_1_exit, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct at24_platform_data board_eeprom = { | ||
| 150 | .byte_len = 4096, | ||
| 151 | .page_size = 32, | ||
| 152 | .flags = AT24_FLAG_ADDR16, | ||
| 153 | }; | ||
| 154 | |||
| 155 | static struct i2c_board_info pcm037_i2c_devices[] = { | ||
| 156 | { | ||
| 157 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ | ||
| 158 | .platform_data = &board_eeprom, | ||
| 159 | }, { | ||
| 160 | I2C_BOARD_INFO("rtc-pcf8563", 0x51), | ||
| 161 | .type = "pcf8563", | ||
| 162 | } | ||
| 163 | }; | ||
| 164 | #endif | ||
| 165 | |||
| 166 | static int sdhc1_pins[] = { | ||
| 167 | MX31_PIN_SD1_DATA3__SD1_DATA3, | ||
| 168 | MX31_PIN_SD1_DATA2__SD1_DATA2, | ||
| 169 | MX31_PIN_SD1_DATA1__SD1_DATA1, | ||
| 170 | MX31_PIN_SD1_DATA0__SD1_DATA0, | ||
| 171 | MX31_PIN_SD1_CLK__SD1_CLK, | ||
| 172 | MX31_PIN_SD1_CMD__SD1_CMD, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static int pcm970_sdhc1_init(struct device *dev, irq_handler_t h, void *data) | ||
| 176 | { | ||
| 177 | return mxc_iomux_setup_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins), | ||
| 178 | "sdhc-1"); | ||
| 179 | } | ||
| 180 | |||
| 181 | static void pcm970_sdhc1_exit(struct device *dev, void *data) | ||
| 182 | { | ||
| 183 | mxc_iomux_release_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins)); | ||
| 184 | } | ||
| 185 | |||
| 186 | /* No card and rw detection at the moment */ | ||
| 187 | static struct imxmmc_platform_data sdhc_pdata = { | ||
| 188 | .init = pcm970_sdhc1_init, | ||
| 189 | .exit = pcm970_sdhc1_exit, | ||
| 190 | }; | ||
| 191 | |||
| 120 | static struct platform_device *devices[] __initdata = { | 192 | static struct platform_device *devices[] __initdata = { |
| 121 | &pcm037_flash, | 193 | &pcm037_flash, |
| 122 | &pcm037_eth, | 194 | &pcm037_eth, |
| 123 | &pcm037_sram_device, | 195 | &pcm037_sram_device, |
| 124 | }; | 196 | }; |
| 125 | 197 | ||
| 198 | static int uart0_pins[] = { | ||
| 199 | MX31_PIN_CTS1__CTS1, | ||
| 200 | MX31_PIN_RTS1__RTS1, | ||
| 201 | MX31_PIN_TXD1__TXD1, | ||
| 202 | MX31_PIN_RXD1__RXD1 | ||
| 203 | }; | ||
| 204 | |||
| 205 | static int uart2_pins[] = { | ||
| 206 | MX31_PIN_CSPI3_MOSI__RXD3, | ||
| 207 | MX31_PIN_CSPI3_MISO__TXD3 | ||
| 208 | }; | ||
| 209 | |||
| 126 | /* | 210 | /* |
| 127 | * Board specific initialization. | 211 | * Board specific initialization. |
| 128 | */ | 212 | */ |
| @@ -130,59 +214,33 @@ static void __init mxc_board_init(void) | |||
| 130 | { | 214 | { |
| 131 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 215 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 132 | 216 | ||
| 133 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 217 | mxc_iomux_setup_multiple_pins(uart0_pins, ARRAY_SIZE(uart0_pins), "uart-0"); |
| 134 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | ||
| 135 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | ||
| 136 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 137 | |||
| 138 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 218 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 139 | 219 | ||
| 140 | mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3); | 220 | mxc_iomux_setup_multiple_pins(uart2_pins, ARRAY_SIZE(uart2_pins), "uart-2"); |
| 141 | mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3); | ||
| 142 | |||
| 143 | mxc_register_device(&mxc_uart_device2, &uart_pdata); | 221 | mxc_register_device(&mxc_uart_device2, &uart_pdata); |
| 144 | 222 | ||
| 145 | mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE); | 223 | mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire"); |
| 146 | mxc_register_device(&mxc_w1_master_device, NULL); | 224 | mxc_register_device(&mxc_w1_master_device, NULL); |
| 147 | 225 | ||
| 148 | /* SMSC9215 IRQ pin */ | 226 | /* SMSC9215 IRQ pin */ |
| 149 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)); | 227 | if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), |
| 150 | if (!gpio_request(MX31_PIN_GPIO3_1, "pcm037-eth")) | 228 | "pcm037-eth")) |
| 151 | gpio_direction_input(MX31_PIN_GPIO3_1); | 229 | gpio_direction_input(MX31_PIN_GPIO3_1); |
| 152 | 230 | ||
| 153 | mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); | 231 | #ifdef CONFIG_I2C_IMX |
| 154 | } | 232 | i2c_register_board_info(1, pcm037_i2c_devices, |
| 233 | ARRAY_SIZE(pcm037_i2c_devices)); | ||
| 155 | 234 | ||
| 156 | /* | 235 | mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data); |
| 157 | * This structure defines static mappings for the pcm037 board. | 236 | #endif |
| 158 | */ | 237 | mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); |
| 159 | static struct map_desc pcm037_io_desc[] __initdata = { | 238 | mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); |
| 160 | { | ||
| 161 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 162 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 163 | .length = AIPS1_SIZE, | ||
| 164 | .type = MT_DEVICE_NONSHARED | ||
| 165 | }, { | ||
| 166 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 167 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 168 | .length = AIPS2_SIZE, | ||
| 169 | .type = MT_DEVICE_NONSHARED | ||
| 170 | }, | ||
| 171 | }; | ||
| 172 | |||
| 173 | /* | ||
| 174 | * Set up static virtual mappings. | ||
| 175 | */ | ||
| 176 | void __init pcm037_map_io(void) | ||
| 177 | { | ||
| 178 | mxc_map_io(); | ||
| 179 | iotable_init(pcm037_io_desc, ARRAY_SIZE(pcm037_io_desc)); | ||
| 180 | } | 239 | } |
| 181 | 240 | ||
| 182 | static void __init pcm037_timer_init(void) | 241 | static void __init pcm037_timer_init(void) |
| 183 | { | 242 | { |
| 184 | mxc_clocks_init(26000000); | 243 | mx31_clocks_init(26000000); |
| 185 | mxc_timer_init("ipg_clk.0"); | ||
| 186 | } | 244 | } |
| 187 | 245 | ||
| 188 | struct sys_timer pcm037_timer = { | 246 | struct sys_timer pcm037_timer = { |
| @@ -194,7 +252,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") | |||
| 194 | .phys_io = AIPS1_BASE_ADDR, | 252 | .phys_io = AIPS1_BASE_ADDR, |
| 195 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 253 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
| 196 | .boot_params = PHYS_OFFSET + 0x100, | 254 | .boot_params = PHYS_OFFSET + 0x100, |
| 197 | .map_io = pcm037_map_io, | 255 | .map_io = mxc_map_io, |
| 198 | .init_irq = mxc_init_irq, | 256 | .init_irq = mxc_init_irq, |
| 199 | .init_machine = mxc_board_init, | 257 | .init_machine = mxc_board_init, |
| 200 | .timer = &pcm037_timer, | 258 | .timer = &pcm037_timer, |
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c new file mode 100644 index 000000000000..6c4283cec6f4 --- /dev/null +++ b/arch/arm/mach-mx3/qong.c | |||
| @@ -0,0 +1,312 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/memory.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/mtd/physmap.h> | ||
| 25 | #include <linux/mtd/nand.h> | ||
| 26 | #include <linux/gpio.h> | ||
| 27 | |||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/irqs.h> | ||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | #include <asm/mach/map.h> | ||
| 34 | #include <mach/common.h> | ||
| 35 | #include <asm/page.h> | ||
| 36 | #include <asm/setup.h> | ||
| 37 | #include <mach/board-qong.h> | ||
| 38 | #include <mach/imx-uart.h> | ||
| 39 | #include <mach/iomux-mx3.h> | ||
| 40 | #include "devices.h" | ||
| 41 | |||
| 42 | /* FPGA defines */ | ||
| 43 | #define QONG_FPGA_VERSION(major, minor, rev) \ | ||
| 44 | (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) | ||
| 45 | |||
| 46 | #define QONG_FPGA_BASEADDR CS1_BASE_ADDR | ||
| 47 | #define QONG_FPGA_PERIPH_SIZE (1 << 24) | ||
| 48 | |||
| 49 | #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR | ||
| 50 | #define QONG_FPGA_CTRL_SIZE 0x10 | ||
| 51 | /* FPGA control registers */ | ||
| 52 | #define QONG_FPGA_CTRL_VERSION 0x00 | ||
| 53 | |||
| 54 | #define QONG_DNET_ID 1 | ||
| 55 | #define QONG_DNET_BASEADDR \ | ||
| 56 | (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE) | ||
| 57 | #define QONG_DNET_SIZE 0x00001000 | ||
| 58 | |||
| 59 | #define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * This file contains the board-specific initialization routines. | ||
| 63 | */ | ||
| 64 | |||
| 65 | static struct imxuart_platform_data uart_pdata = { | ||
| 66 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static int uart_pins[] = { | ||
| 70 | MX31_PIN_CTS1__CTS1, | ||
| 71 | MX31_PIN_RTS1__RTS1, | ||
| 72 | MX31_PIN_TXD1__TXD1, | ||
| 73 | MX31_PIN_RXD1__RXD1 | ||
| 74 | }; | ||
| 75 | |||
| 76 | static inline void mxc_init_imx_uart(void) | ||
| 77 | { | ||
| 78 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), | ||
| 79 | "uart-0"); | ||
| 80 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | ||
| 81 | } | ||
| 82 | |||
| 83 | static struct resource dnet_resources[] = { | ||
| 84 | [0] = { | ||
| 85 | .name = "dnet-memory", | ||
| 86 | .start = QONG_DNET_BASEADDR, | ||
| 87 | .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1, | ||
| 88 | .flags = IORESOURCE_MEM, | ||
| 89 | }, | ||
| 90 | [1] = { | ||
| 91 | .start = QONG_FPGA_IRQ, | ||
| 92 | .end = QONG_FPGA_IRQ, | ||
| 93 | .flags = IORESOURCE_IRQ, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static struct platform_device dnet_device = { | ||
| 98 | .name = "dnet", | ||
| 99 | .id = -1, | ||
| 100 | .num_resources = ARRAY_SIZE(dnet_resources), | ||
| 101 | .resource = dnet_resources, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static int __init qong_init_dnet(void) | ||
| 105 | { | ||
| 106 | int ret; | ||
| 107 | |||
| 108 | ret = platform_device_register(&dnet_device); | ||
| 109 | return ret; | ||
| 110 | } | ||
| 111 | |||
| 112 | /* MTD NOR flash */ | ||
| 113 | |||
| 114 | static struct physmap_flash_data qong_flash_data = { | ||
| 115 | .width = 2, | ||
| 116 | }; | ||
| 117 | |||
| 118 | static struct resource qong_flash_resource = { | ||
| 119 | .start = CS0_BASE_ADDR, | ||
| 120 | .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1, | ||
| 121 | .flags = IORESOURCE_MEM, | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct platform_device qong_nor_mtd_device = { | ||
| 125 | .name = "physmap-flash", | ||
| 126 | .id = 0, | ||
| 127 | .dev = { | ||
| 128 | .platform_data = &qong_flash_data, | ||
| 129 | }, | ||
| 130 | .resource = &qong_flash_resource, | ||
| 131 | .num_resources = 1, | ||
| 132 | }; | ||
| 133 | |||
| 134 | static void qong_init_nor_mtd(void) | ||
| 135 | { | ||
| 136 | (void)platform_device_register(&qong_nor_mtd_device); | ||
| 137 | } | ||
| 138 | |||
| 139 | /* | ||
| 140 | * Hardware specific access to control-lines | ||
| 141 | */ | ||
| 142 | static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | ||
| 143 | { | ||
| 144 | struct nand_chip *nand_chip = mtd->priv; | ||
| 145 | |||
| 146 | if (cmd == NAND_CMD_NONE) | ||
| 147 | return; | ||
| 148 | |||
| 149 | if (ctrl & NAND_CLE) | ||
| 150 | writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24)); | ||
| 151 | else | ||
| 152 | writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23)); | ||
| 153 | } | ||
| 154 | |||
| 155 | /* | ||
| 156 | * Read the Device Ready pin. | ||
| 157 | */ | ||
| 158 | static int qong_nand_device_ready(struct mtd_info *mtd) | ||
| 159 | { | ||
| 160 | return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB)); | ||
| 161 | } | ||
| 162 | |||
| 163 | static void qong_nand_select_chip(struct mtd_info *mtd, int chip) | ||
| 164 | { | ||
| 165 | if (chip >= 0) | ||
| 166 | gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); | ||
| 167 | else | ||
| 168 | gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1); | ||
| 169 | } | ||
| 170 | |||
| 171 | static struct platform_nand_data qong_nand_data = { | ||
| 172 | .chip = { | ||
| 173 | .chip_delay = 20, | ||
| 174 | .options = 0, | ||
| 175 | }, | ||
| 176 | .ctrl = { | ||
| 177 | .cmd_ctrl = qong_nand_cmd_ctrl, | ||
| 178 | .dev_ready = qong_nand_device_ready, | ||
| 179 | .select_chip = qong_nand_select_chip, | ||
| 180 | } | ||
| 181 | }; | ||
| 182 | |||
| 183 | static struct resource qong_nand_resource = { | ||
| 184 | .start = CS3_BASE_ADDR, | ||
| 185 | .end = CS3_BASE_ADDR + SZ_32M - 1, | ||
| 186 | .flags = IORESOURCE_MEM, | ||
| 187 | }; | ||
| 188 | |||
| 189 | static struct platform_device qong_nand_device = { | ||
| 190 | .name = "gen_nand", | ||
| 191 | .id = -1, | ||
| 192 | .dev = { | ||
| 193 | .platform_data = &qong_nand_data, | ||
| 194 | }, | ||
| 195 | .num_resources = 1, | ||
| 196 | .resource = &qong_nand_resource, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static void __init qong_init_nand_mtd(void) | ||
| 200 | { | ||
| 201 | /* init CS */ | ||
| 202 | __raw_writel(0x00004f00, CSCR_U(3)); | ||
| 203 | __raw_writel(0x20013b31, CSCR_L(3)); | ||
| 204 | __raw_writel(0x00020800, CSCR_A(3)); | ||
| 205 | mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); | ||
| 206 | |||
| 207 | /* enable pin */ | ||
| 208 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO)); | ||
| 209 | if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable")) | ||
| 210 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); | ||
| 211 | |||
| 212 | /* ready/busy pin */ | ||
| 213 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO)); | ||
| 214 | if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy")) | ||
| 215 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB)); | ||
| 216 | |||
| 217 | /* write protect pin */ | ||
| 218 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO)); | ||
| 219 | if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp")) | ||
| 220 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B)); | ||
| 221 | |||
| 222 | platform_device_register(&qong_nand_device); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void __init qong_init_fpga(void) | ||
| 226 | { | ||
| 227 | void __iomem *regs; | ||
| 228 | u32 fpga_ver; | ||
| 229 | |||
| 230 | regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE); | ||
| 231 | if (!regs) { | ||
| 232 | printk(KERN_ERR "%s: failed to map registers, aborting.\n", | ||
| 233 | __func__); | ||
| 234 | return; | ||
| 235 | } | ||
| 236 | |||
| 237 | fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION); | ||
| 238 | iounmap(regs); | ||
| 239 | printk(KERN_INFO "Qong FPGA version %d.%d.%d\n", | ||
| 240 | (fpga_ver & 0xF000) >> 12, | ||
| 241 | (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF); | ||
| 242 | if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) { | ||
| 243 | printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based " | ||
| 244 | "devices won't be registered!\n"); | ||
| 245 | return; | ||
| 246 | } | ||
| 247 | |||
| 248 | /* register FPGA-based devices */ | ||
| 249 | qong_init_nand_mtd(); | ||
| 250 | qong_init_dnet(); | ||
| 251 | } | ||
| 252 | |||
| 253 | /* | ||
| 254 | * This structure defines the MX31 memory map. | ||
| 255 | */ | ||
| 256 | static struct map_desc qong_io_desc[] __initdata = { | ||
| 257 | { | ||
| 258 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 259 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 260 | .length = AIPS1_SIZE, | ||
| 261 | .type = MT_DEVICE_NONSHARED | ||
| 262 | }, { | ||
| 263 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 264 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 265 | .length = AIPS2_SIZE, | ||
| 266 | .type = MT_DEVICE_NONSHARED | ||
| 267 | } | ||
| 268 | }; | ||
| 269 | |||
| 270 | /* | ||
| 271 | * Set up static virtual mappings. | ||
| 272 | */ | ||
| 273 | static void __init qong_map_io(void) | ||
| 274 | { | ||
| 275 | mxc_map_io(); | ||
| 276 | iotable_init(qong_io_desc, ARRAY_SIZE(qong_io_desc)); | ||
| 277 | } | ||
| 278 | |||
| 279 | /* | ||
| 280 | * Board specific initialization. | ||
| 281 | */ | ||
| 282 | static void __init mxc_board_init(void) | ||
| 283 | { | ||
| 284 | mxc_init_imx_uart(); | ||
| 285 | qong_init_nor_mtd(); | ||
| 286 | qong_init_fpga(); | ||
| 287 | } | ||
| 288 | |||
| 289 | static void __init qong_timer_init(void) | ||
| 290 | { | ||
| 291 | mx31_clocks_init(26000000); | ||
| 292 | } | ||
| 293 | |||
| 294 | static struct sys_timer qong_timer = { | ||
| 295 | .init = qong_timer_init, | ||
| 296 | }; | ||
| 297 | |||
| 298 | /* | ||
| 299 | * The following uses standard kernel macros defined in arch.h in order to | ||
| 300 | * initialize __mach_desc_QONG data structure. | ||
| 301 | */ | ||
| 302 | |||
| 303 | MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") | ||
| 304 | /* Maintainer: DENX Software Engineering GmbH */ | ||
| 305 | .phys_io = AIPS1_BASE_ADDR, | ||
| 306 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | ||
| 307 | .boot_params = PHYS_OFFSET + 0x100, | ||
| 308 | .map_io = qong_map_io, | ||
| 309 | .init_irq = mxc_init_irq, | ||
| 310 | .init_machine = mxc_board_init, | ||
| 311 | .timer = &qong_timer, | ||
| 312 | MACHINE_END | ||
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h index 6c1023b8a9ab..dc7b4bc003c5 100644 --- a/arch/arm/mach-netx/include/mach/system.h +++ b/arch/arm/mach-netx/include/mach/system.h | |||
| @@ -28,7 +28,7 @@ static inline void arch_idle(void) | |||
| 28 | cpu_do_idle(); | 28 | cpu_do_idle(); |
| 29 | } | 29 | } |
| 30 | 30 | ||
| 31 | static inline void arch_reset(char mode) | 31 | static inline void arch_reset(char mode, const char *cmd) |
| 32 | { | 32 | { |
| 33 | writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, | 33 | writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, |
| 34 | NETX_SYSTEM_RES_CR); | 34 | NETX_SYSTEM_RES_CR); |
diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h index e2068c57415f..1561588ca364 100644 --- a/arch/arm/mach-ns9xxx/include/mach/system.h +++ b/arch/arm/mach-ns9xxx/include/mach/system.h | |||
| @@ -20,7 +20,7 @@ static inline void arch_idle(void) | |||
| 20 | cpu_do_idle(); | 20 | cpu_do_idle(); |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | static inline void arch_reset(char mode) | 23 | static inline void arch_reset(char mode, const char *cmd) |
| 24 | { | 24 | { |
| 25 | #ifdef CONFIG_PROCESSOR_NS9360 | 25 | #ifdef CONFIG_PROCESSOR_NS9360 |
| 26 | if (processor_is_ns9360()) | 26 | if (processor_is_ns9360()) |
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 10a301e32434..3f325d3718a9 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig | |||
| @@ -7,6 +7,11 @@ config ARCH_OMAP730 | |||
| 7 | select CPU_ARM926T | 7 | select CPU_ARM926T |
| 8 | select ARCH_OMAP_OTG | 8 | select ARCH_OMAP_OTG |
| 9 | 9 | ||
| 10 | config ARCH_OMAP850 | ||
| 11 | depends on ARCH_OMAP1 | ||
| 12 | bool "OMAP850 Based System" | ||
| 13 | select CPU_ARM926T | ||
| 14 | |||
| 10 | config ARCH_OMAP15XX | 15 | config ARCH_OMAP15XX |
| 11 | depends on ARCH_OMAP1 | 16 | depends on ARCH_OMAP1 |
| 12 | default y | 17 | default y |
| @@ -46,6 +51,12 @@ config MACH_OMAP_H3 | |||
| 46 | TI OMAP 1710 H3 board support. Say Y here if you have such | 51 | TI OMAP 1710 H3 board support. Say Y here if you have such |
| 47 | a board. | 52 | a board. |
| 48 | 53 | ||
| 54 | config MACH_OMAP_HTCWIZARD | ||
| 55 | bool "HTC Wizard" | ||
| 56 | depends on ARCH_OMAP850 | ||
| 57 | help | ||
| 58 | HTC Wizard smartphone support (AKA QTEK 9100, ...) | ||
| 59 | |||
| 49 | config MACH_OMAP_OSK | 60 | config MACH_OMAP_OSK |
| 50 | bool "TI OSK Support" | 61 | bool "TI OSK Support" |
| 51 | depends on ARCH_OMAP1 && ARCH_OMAP16XX | 62 | depends on ARCH_OMAP1 && ARCH_OMAP16XX |
| @@ -163,7 +174,7 @@ config OMAP_ARM_216MHZ | |||
| 163 | 174 | ||
| 164 | config OMAP_ARM_195MHZ | 175 | config OMAP_ARM_195MHZ |
| 165 | bool "OMAP ARM 195 MHz CPU" | 176 | bool "OMAP ARM 195 MHz CPU" |
| 166 | depends on ARCH_OMAP1 && ARCH_OMAP730 | 177 | depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) |
| 167 | help | 178 | help |
| 168 | Enable 195MHz clock for OMAP CPU. If unsure, say N. | 179 | Enable 195MHz clock for OMAP CPU. If unsure, say N. |
| 169 | 180 | ||
| @@ -175,13 +186,13 @@ config OMAP_ARM_192MHZ | |||
| 175 | 186 | ||
| 176 | config OMAP_ARM_182MHZ | 187 | config OMAP_ARM_182MHZ |
| 177 | bool "OMAP ARM 182 MHz CPU" | 188 | bool "OMAP ARM 182 MHz CPU" |
| 178 | depends on ARCH_OMAP1 && ARCH_OMAP730 | 189 | depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) |
| 179 | help | 190 | help |
| 180 | Enable 182MHz clock for OMAP CPU. If unsure, say N. | 191 | Enable 182MHz clock for OMAP CPU. If unsure, say N. |
| 181 | 192 | ||
| 182 | config OMAP_ARM_168MHZ | 193 | config OMAP_ARM_168MHZ |
| 183 | bool "OMAP ARM 168 MHz CPU" | 194 | bool "OMAP ARM 168 MHz CPU" |
| 184 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 195 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 185 | help | 196 | help |
| 186 | Enable 168MHz clock for OMAP CPU. If unsure, say N. | 197 | Enable 168MHz clock for OMAP CPU. If unsure, say N. |
| 187 | 198 | ||
| @@ -193,20 +204,20 @@ config OMAP_ARM_150MHZ | |||
| 193 | 204 | ||
| 194 | config OMAP_ARM_120MHZ | 205 | config OMAP_ARM_120MHZ |
| 195 | bool "OMAP ARM 120 MHz CPU" | 206 | bool "OMAP ARM 120 MHz CPU" |
| 196 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 207 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 197 | help | 208 | help |
| 198 | Enable 120MHz clock for OMAP CPU. If unsure, say N. | 209 | Enable 120MHz clock for OMAP CPU. If unsure, say N. |
| 199 | 210 | ||
| 200 | config OMAP_ARM_60MHZ | 211 | config OMAP_ARM_60MHZ |
| 201 | bool "OMAP ARM 60 MHz CPU" | 212 | bool "OMAP ARM 60 MHz CPU" |
| 202 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 213 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 203 | default y | 214 | default y |
| 204 | help | 215 | help |
| 205 | Enable 60MHz clock for OMAP CPU. If unsure, say Y. | 216 | Enable 60MHz clock for OMAP CPU. If unsure, say Y. |
| 206 | 217 | ||
| 207 | config OMAP_ARM_30MHZ | 218 | config OMAP_ARM_30MHZ |
| 208 | bool "OMAP ARM 30 MHz CPU" | 219 | bool "OMAP ARM 30 MHz CPU" |
| 209 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 220 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 210 | help | 221 | help |
| 211 | Enable 30MHz clock for OMAP CPU. If unsure, say N. | 222 | Enable 30MHz clock for OMAP CPU. If unsure, say N. |
| 212 | 223 | ||
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 2e618391cc51..8b40aace9db4 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
| @@ -175,7 +175,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = { | |||
| 175 | static struct omap_board_config_kernel ams_delta_config[] = { | 175 | static struct omap_board_config_kernel ams_delta_config[] = { |
| 176 | { OMAP_TAG_LCD, &ams_delta_lcd_config }, | 176 | { OMAP_TAG_LCD, &ams_delta_lcd_config }, |
| 177 | { OMAP_TAG_UART, &ams_delta_uart_config }, | 177 | { OMAP_TAG_UART, &ams_delta_uart_config }, |
| 178 | { OMAP_TAG_USB, &ams_delta_usb_config }, | ||
| 179 | }; | 178 | }; |
| 180 | 179 | ||
| 181 | static struct resource ams_delta_kp_resources[] = { | 180 | static struct resource ams_delta_kp_resources[] = { |
| @@ -232,6 +231,7 @@ static void __init ams_delta_init(void) | |||
| 232 | /* Clear latch2 (NAND, LCD, modem enable) */ | 231 | /* Clear latch2 (NAND, LCD, modem enable) */ |
| 233 | ams_delta_latch2_write(~0, 0); | 232 | ams_delta_latch2_write(~0, 0); |
| 234 | 233 | ||
| 234 | omap_usb_init(&ams_delta_usb_config); | ||
| 235 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); | 235 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); |
| 236 | } | 236 | } |
| 237 | 237 | ||
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 30308294e7c1..19e0e9232336 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
| @@ -34,7 +34,39 @@ | |||
| 34 | #include <mach/keypad.h> | 34 | #include <mach/keypad.h> |
| 35 | #include <mach/common.h> | 35 | #include <mach/common.h> |
| 36 | #include <mach/board.h> | 36 | #include <mach/board.h> |
| 37 | #include <mach/board-fsample.h> | 37 | |
| 38 | /* fsample is pretty close to p2-sample */ | ||
| 39 | |||
| 40 | #define fsample_cpld_read(reg) __raw_readb(reg) | ||
| 41 | #define fsample_cpld_write(val, reg) __raw_writeb(val, reg) | ||
| 42 | |||
| 43 | #define FSAMPLE_CPLD_BASE 0xE8100000 | ||
| 44 | #define FSAMPLE_CPLD_SIZE SZ_4K | ||
| 45 | #define FSAMPLE_CPLD_START 0x05080000 | ||
| 46 | |||
| 47 | #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00) | ||
| 48 | #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02) | ||
| 49 | #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02) | ||
| 50 | #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04) | ||
| 51 | #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06) | ||
| 52 | #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06) | ||
| 53 | |||
| 54 | #define FSAMPLE_CPLD_BIT_BT_RESET 0 | ||
| 55 | #define FSAMPLE_CPLD_BIT_LCD_RESET 1 | ||
| 56 | #define FSAMPLE_CPLD_BIT_CAM_PWDN 2 | ||
| 57 | #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3 | ||
| 58 | #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4 | ||
| 59 | #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5 | ||
| 60 | #define FSAMPLE_CPLD_BIT_BACKLIGHT 6 | ||
| 61 | #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7 | ||
| 62 | #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8 | ||
| 63 | #define FSAMPLE_CPLD_BIT_OTG_RESET 9 | ||
| 64 | |||
| 65 | #define fsample_cpld_set(bit) \ | ||
| 66 | fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR) | ||
| 67 | |||
| 68 | #define fsample_cpld_clear(bit) \ | ||
| 69 | fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) | ||
| 38 | 70 | ||
| 39 | static int fsample_keymap[] = { | 71 | static int fsample_keymap[] = { |
| 40 | KEY(0,0,KEY_UP), | 72 | KEY(0,0,KEY_UP), |
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 7d2670205373..e724940e86f2 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c | |||
| @@ -62,7 +62,6 @@ static struct omap_uart_config generic_uart_config __initdata = { | |||
| 62 | }; | 62 | }; |
| 63 | 63 | ||
| 64 | static struct omap_board_config_kernel generic_config[] __initdata = { | 64 | static struct omap_board_config_kernel generic_config[] __initdata = { |
| 65 | { OMAP_TAG_USB, NULL }, | ||
| 66 | { OMAP_TAG_UART, &generic_uart_config }, | 65 | { OMAP_TAG_UART, &generic_uart_config }, |
| 67 | }; | 66 | }; |
| 68 | 67 | ||
| @@ -70,12 +69,12 @@ static void __init omap_generic_init(void) | |||
| 70 | { | 69 | { |
| 71 | #ifdef CONFIG_ARCH_OMAP15XX | 70 | #ifdef CONFIG_ARCH_OMAP15XX |
| 72 | if (cpu_is_omap15xx()) { | 71 | if (cpu_is_omap15xx()) { |
| 73 | generic_config[0].data = &generic1510_usb_config; | 72 | omap_usb_init(&generic1510_usb_config); |
| 74 | } | 73 | } |
| 75 | #endif | 74 | #endif |
| 76 | #if defined(CONFIG_ARCH_OMAP16XX) | 75 | #if defined(CONFIG_ARCH_OMAP16XX) |
| 77 | if (!cpu_is_omap1510()) { | 76 | if (!cpu_is_omap1510()) { |
| 78 | generic_config[0].data = &generic1610_usb_config; | 77 | omap_usb_init(&generic1610_usb_config); |
| 79 | } | 78 | } |
| 80 | #endif | 79 | #endif |
| 81 | 80 | ||
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index 409fa56d0a87..44d4a966bed9 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c | |||
| @@ -19,6 +19,8 @@ | |||
| 19 | #include <mach/mmc.h> | 19 | #include <mach/mmc.h> |
| 20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
| 21 | 21 | ||
| 22 | #include "board-h2.h" | ||
| 23 | |||
| 22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 24 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
| 23 | 25 | ||
| 24 | static int mmc_set_power(struct device *dev, int slot, int power_on, | 26 | static int mmc_set_power(struct device *dev, int slot, int power_on, |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 0d784a795092..f695aa053ac8 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
| @@ -46,6 +46,11 @@ | |||
| 46 | #include <mach/keypad.h> | 46 | #include <mach/keypad.h> |
| 47 | #include <mach/common.h> | 47 | #include <mach/common.h> |
| 48 | 48 | ||
| 49 | #include "board-h2.h" | ||
| 50 | |||
| 51 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 52 | #define OMAP1610_ETHR_START 0x04000300 | ||
| 53 | |||
| 49 | static int h2_keymap[] = { | 54 | static int h2_keymap[] = { |
| 50 | KEY(0, 0, KEY_LEFT), | 55 | KEY(0, 0, KEY_LEFT), |
| 51 | KEY(0, 1, KEY_RIGHT), | 56 | KEY(0, 1, KEY_RIGHT), |
| @@ -364,7 +369,6 @@ static struct omap_lcd_config h2_lcd_config __initdata = { | |||
| 364 | }; | 369 | }; |
| 365 | 370 | ||
| 366 | static struct omap_board_config_kernel h2_config[] __initdata = { | 371 | static struct omap_board_config_kernel h2_config[] __initdata = { |
| 367 | { OMAP_TAG_USB, &h2_usb_config }, | ||
| 368 | { OMAP_TAG_UART, &h2_uart_config }, | 372 | { OMAP_TAG_UART, &h2_uart_config }, |
| 369 | { OMAP_TAG_LCD, &h2_lcd_config }, | 373 | { OMAP_TAG_LCD, &h2_lcd_config }, |
| 370 | }; | 374 | }; |
| @@ -413,6 +417,7 @@ static void __init h2_init(void) | |||
| 413 | omap_serial_init(); | 417 | omap_serial_init(); |
| 414 | omap_register_i2c_bus(1, 100, h2_i2c_board_info, | 418 | omap_register_i2c_bus(1, 100, h2_i2c_board_info, |
| 415 | ARRAY_SIZE(h2_i2c_board_info)); | 419 | ARRAY_SIZE(h2_i2c_board_info)); |
| 420 | omap_usb_init(&h2_usb_config); | ||
| 416 | h2_mmc_init(); | 421 | h2_mmc_init(); |
| 417 | } | 422 | } |
| 418 | 423 | ||
diff --git a/arch/arm/plat-omap/include/mach/board-h2.h b/arch/arm/mach-omap1/board-h2.h index 15531c8dc0e6..315e2662547e 100644 --- a/arch/arm/plat-omap/include/mach/board-h2.h +++ b/arch/arm/mach-omap1/board-h2.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/board-h2.h | 2 | * arch/arm/mach-omap1/board-h2.h |
| 3 | * | 3 | * |
| 4 | * Hardware definitions for TI OMAP1610 H2 board. | 4 | * Hardware definitions for TI OMAP1610 H2 board. |
| 5 | * | 5 | * |
| @@ -29,9 +29,6 @@ | |||
| 29 | #ifndef __ASM_ARCH_OMAP_H2_H | 29 | #ifndef __ASM_ARCH_OMAP_H2_H |
| 30 | #define __ASM_ARCH_OMAP_H2_H | 30 | #define __ASM_ARCH_OMAP_H2_H |
| 31 | 31 | ||
| 32 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 33 | #define OMAP1610_ETHR_START 0x04000300 | ||
| 34 | |||
| 35 | #define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | 32 | #define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) |
| 36 | # define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3) | 33 | # define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3) |
| 37 | 34 | ||
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index fdfe793d56f2..0d8a3c195e2e 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c | |||
| @@ -19,6 +19,8 @@ | |||
| 19 | #include <mach/mmc.h> | 19 | #include <mach/mmc.h> |
| 20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
| 21 | 21 | ||
| 22 | #include "board-h3.h" | ||
| 23 | |||
| 22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 24 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
| 23 | 25 | ||
| 24 | static int mmc_set_power(struct device *dev, int slot, int power_on, | 26 | static int mmc_set_power(struct device *dev, int slot, int power_on, |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index bf08b6ad22ee..4695965114c4 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
| @@ -50,6 +50,11 @@ | |||
| 50 | #include <mach/dma.h> | 50 | #include <mach/dma.h> |
| 51 | #include <mach/common.h> | 51 | #include <mach/common.h> |
| 52 | 52 | ||
| 53 | #include "board-h3.h" | ||
| 54 | |||
| 55 | /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ | ||
| 56 | #define OMAP1710_ETHR_START 0x04000300 | ||
| 57 | |||
| 53 | #define H3_TS_GPIO 48 | 58 | #define H3_TS_GPIO 48 |
| 54 | 59 | ||
| 55 | static int h3_keymap[] = { | 60 | static int h3_keymap[] = { |
| @@ -418,7 +423,6 @@ static struct omap_lcd_config h3_lcd_config __initdata = { | |||
| 418 | }; | 423 | }; |
| 419 | 424 | ||
| 420 | static struct omap_board_config_kernel h3_config[] __initdata = { | 425 | static struct omap_board_config_kernel h3_config[] __initdata = { |
| 421 | { OMAP_TAG_USB, &h3_usb_config }, | ||
| 422 | { OMAP_TAG_UART, &h3_uart_config }, | 426 | { OMAP_TAG_UART, &h3_uart_config }, |
| 423 | { OMAP_TAG_LCD, &h3_lcd_config }, | 427 | { OMAP_TAG_LCD, &h3_lcd_config }, |
| 424 | }; | 428 | }; |
| @@ -472,6 +476,7 @@ static void __init h3_init(void) | |||
| 472 | omap_serial_init(); | 476 | omap_serial_init(); |
| 473 | omap_register_i2c_bus(1, 100, h3_i2c_board_info, | 477 | omap_register_i2c_bus(1, 100, h3_i2c_board_info, |
| 474 | ARRAY_SIZE(h3_i2c_board_info)); | 478 | ARRAY_SIZE(h3_i2c_board_info)); |
| 479 | omap_usb_init(&h3_usb_config); | ||
| 475 | h3_mmc_init(); | 480 | h3_mmc_init(); |
| 476 | } | 481 | } |
| 477 | 482 | ||
diff --git a/arch/arm/plat-omap/include/mach/board-h3.h b/arch/arm/mach-omap1/board-h3.h index 1888326da7ea..78de535be3c5 100644 --- a/arch/arm/plat-omap/include/mach/board-h3.h +++ b/arch/arm/mach-omap1/board-h3.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/board-h3.h | 2 | * arch/arm/mach-omap1/board-h3.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2001 RidgeRun, Inc. | 4 | * Copyright (C) 2001 RidgeRun, Inc. |
| 5 | * Copyright (C) 2004 Texas Instruments, Inc. | 5 | * Copyright (C) 2004 Texas Instruments, Inc. |
| @@ -27,9 +27,6 @@ | |||
| 27 | #ifndef __ASM_ARCH_OMAP_H3_H | 27 | #ifndef __ASM_ARCH_OMAP_H3_H |
| 28 | #define __ASM_ARCH_OMAP_H3_H | 28 | #define __ASM_ARCH_OMAP_H3_H |
| 29 | 29 | ||
| 30 | /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ | ||
| 31 | #define OMAP1710_ETHR_START 0x04000300 | ||
| 32 | |||
| 33 | #define H3_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | 30 | #define H3_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) |
| 34 | # define H3_TPS_GPIO_MMC_PWR_EN (H3_TPS_GPIO_BASE + 4) | 31 | # define H3_TPS_GPIO_MMC_PWR_EN (H3_TPS_GPIO_BASE + 4) |
| 35 | 32 | ||
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 071cd02a734e..2fd98260ea49 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
| @@ -39,6 +39,9 @@ | |||
| 39 | #include <mach/common.h> | 39 | #include <mach/common.h> |
| 40 | #include <mach/mmc.h> | 40 | #include <mach/mmc.h> |
| 41 | 41 | ||
| 42 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 43 | #define INNOVATOR1610_ETHR_START 0x04000300 | ||
| 44 | |||
| 42 | static int innovator_keymap[] = { | 45 | static int innovator_keymap[] = { |
| 43 | KEY(0, 0, KEY_F1), | 46 | KEY(0, 0, KEY_F1), |
| 44 | KEY(0, 3, KEY_DOWN), | 47 | KEY(0, 3, KEY_DOWN), |
| @@ -370,7 +373,6 @@ static struct omap_uart_config innovator_uart_config __initdata = { | |||
| 370 | }; | 373 | }; |
| 371 | 374 | ||
| 372 | static struct omap_board_config_kernel innovator_config[] = { | 375 | static struct omap_board_config_kernel innovator_config[] = { |
| 373 | { OMAP_TAG_USB, NULL }, | ||
| 374 | { OMAP_TAG_LCD, NULL }, | 376 | { OMAP_TAG_LCD, NULL }, |
| 375 | { OMAP_TAG_UART, &innovator_uart_config }, | 377 | { OMAP_TAG_UART, &innovator_uart_config }, |
| 376 | }; | 378 | }; |
| @@ -392,13 +394,13 @@ static void __init innovator_init(void) | |||
| 392 | 394 | ||
| 393 | #ifdef CONFIG_ARCH_OMAP15XX | 395 | #ifdef CONFIG_ARCH_OMAP15XX |
| 394 | if (cpu_is_omap1510()) { | 396 | if (cpu_is_omap1510()) { |
| 395 | innovator_config[0].data = &innovator1510_usb_config; | 397 | omap_usb_init(&innovator1510_usb_config); |
| 396 | innovator_config[1].data = &innovator1510_lcd_config; | 398 | innovator_config[1].data = &innovator1510_lcd_config; |
| 397 | } | 399 | } |
| 398 | #endif | 400 | #endif |
| 399 | #ifdef CONFIG_ARCH_OMAP16XX | 401 | #ifdef CONFIG_ARCH_OMAP16XX |
| 400 | if (cpu_is_omap1610()) { | 402 | if (cpu_is_omap1610()) { |
| 401 | innovator_config[0].data = &h2_usb_config; | 403 | omap_usb_init(&h2_usb_config); |
| 402 | innovator_config[1].data = &innovator1610_lcd_config; | 404 | innovator_config[1].data = &innovator1610_lcd_config; |
| 403 | } | 405 | } |
| 404 | #endif | 406 | #endif |
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index af51e0b180f2..7bc7a3cb9c51 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
| @@ -233,10 +233,6 @@ static inline void nokia770_mmc_init(void) | |||
| 233 | } | 233 | } |
| 234 | #endif | 234 | #endif |
| 235 | 235 | ||
| 236 | static struct omap_board_config_kernel nokia770_config[] __initdata = { | ||
| 237 | { OMAP_TAG_USB, NULL }, | ||
| 238 | }; | ||
| 239 | |||
| 240 | #if defined(CONFIG_OMAP_DSP) | 236 | #if defined(CONFIG_OMAP_DSP) |
| 241 | /* | 237 | /* |
| 242 | * audio power control | 238 | * audio power control |
| @@ -371,19 +367,16 @@ static __init int omap_dsp_init(void) | |||
| 371 | 367 | ||
| 372 | static void __init omap_nokia770_init(void) | 368 | static void __init omap_nokia770_init(void) |
| 373 | { | 369 | { |
| 374 | nokia770_config[0].data = &nokia770_usb_config; | ||
| 375 | |||
| 376 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); | 370 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); |
| 377 | spi_register_board_info(nokia770_spi_board_info, | 371 | spi_register_board_info(nokia770_spi_board_info, |
| 378 | ARRAY_SIZE(nokia770_spi_board_info)); | 372 | ARRAY_SIZE(nokia770_spi_board_info)); |
| 379 | omap_board_config = nokia770_config; | ||
| 380 | omap_board_config_size = ARRAY_SIZE(nokia770_config); | ||
| 381 | omap_gpio_init(); | 373 | omap_gpio_init(); |
| 382 | omap_serial_init(); | 374 | omap_serial_init(); |
| 383 | omap_register_i2c_bus(1, 100, NULL, 0); | 375 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 384 | omap_dsp_init(); | 376 | omap_dsp_init(); |
| 385 | ads7846_dev_init(); | 377 | ads7846_dev_init(); |
| 386 | mipid_dev_init(); | 378 | mipid_dev_init(); |
| 379 | omap_usb_init(&nokia770_usb_config); | ||
| 387 | nokia770_mmc_init(); | 380 | nokia770_mmc_init(); |
| 388 | } | 381 | } |
| 389 | 382 | ||
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 1a16ecb2ccc8..cf3247b15f87 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -52,6 +52,20 @@ | |||
| 52 | #include <mach/tc.h> | 52 | #include <mach/tc.h> |
| 53 | #include <mach/common.h> | 53 | #include <mach/common.h> |
| 54 | 54 | ||
| 55 | /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ | ||
| 56 | #define OMAP_OSK_ETHR_START 0x04800300 | ||
| 57 | |||
| 58 | /* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with | ||
| 59 | * alternate pin configurations for hardware-controlled blinking. | ||
| 60 | */ | ||
| 61 | #define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | ||
| 62 | # define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0) | ||
| 63 | # define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1) | ||
| 64 | # define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2) | ||
| 65 | # define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3) | ||
| 66 | # define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4) | ||
| 67 | # define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5) | ||
| 68 | |||
| 55 | static struct mtd_partition osk_partitions[] = { | 69 | static struct mtd_partition osk_partitions[] = { |
| 56 | /* bootloader (U-Boot, etc) in first sector */ | 70 | /* bootloader (U-Boot, etc) in first sector */ |
| 57 | { | 71 | { |
| @@ -290,7 +304,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = { | |||
| 290 | #endif | 304 | #endif |
| 291 | 305 | ||
| 292 | static struct omap_board_config_kernel osk_config[] __initdata = { | 306 | static struct omap_board_config_kernel osk_config[] __initdata = { |
| 293 | { OMAP_TAG_USB, &osk_usb_config }, | ||
| 294 | { OMAP_TAG_UART, &osk_uart_config }, | 307 | { OMAP_TAG_UART, &osk_uart_config }, |
| 295 | #ifdef CONFIG_OMAP_OSK_MISTRAL | 308 | #ifdef CONFIG_OMAP_OSK_MISTRAL |
| 296 | { OMAP_TAG_LCD, &osk_lcd_config }, | 309 | { OMAP_TAG_LCD, &osk_lcd_config }, |
| @@ -541,6 +554,8 @@ static void __init osk_init(void) | |||
| 541 | l |= (3 << 1); | 554 | l |= (3 << 1); |
| 542 | omap_writel(l, USB_TRANSCEIVER_CTRL); | 555 | omap_writel(l, USB_TRANSCEIVER_CTRL); |
| 543 | 556 | ||
| 557 | omap_usb_init(&osk_usb_config); | ||
| 558 | |||
| 544 | /* irq for tps65010 chip */ | 559 | /* irq for tps65010 chip */ |
| 545 | /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ | 560 | /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ |
| 546 | if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0) | 561 | if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0) |
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 99f2b43f2541..886b4c0569bd 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
| @@ -43,6 +43,21 @@ | |||
| 43 | #include <mach/keypad.h> | 43 | #include <mach/keypad.h> |
| 44 | #include <mach/common.h> | 44 | #include <mach/common.h> |
| 45 | 45 | ||
| 46 | #define PALMTE_USBDETECT_GPIO 0 | ||
| 47 | #define PALMTE_USB_OR_DC_GPIO 1 | ||
| 48 | #define PALMTE_TSC_GPIO 4 | ||
| 49 | #define PALMTE_PINTDAV_GPIO 6 | ||
| 50 | #define PALMTE_MMC_WP_GPIO 8 | ||
| 51 | #define PALMTE_MMC_POWER_GPIO 9 | ||
| 52 | #define PALMTE_HDQ_GPIO 11 | ||
| 53 | #define PALMTE_HEADPHONES_GPIO 14 | ||
| 54 | #define PALMTE_SPEAKER_GPIO 15 | ||
| 55 | #define PALMTE_DC_GPIO OMAP_MPUIO(2) | ||
| 56 | #define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4) | ||
| 57 | #define PALMTE_MMC1_GPIO OMAP_MPUIO(6) | ||
| 58 | #define PALMTE_MMC2_GPIO OMAP_MPUIO(7) | ||
| 59 | #define PALMTE_MMC3_GPIO OMAP_MPUIO(11) | ||
| 60 | |||
| 46 | static void __init omap_palmte_init_irq(void) | 61 | static void __init omap_palmte_init_irq(void) |
| 47 | { | 62 | { |
| 48 | omap1_init_common_hw(); | 63 | omap1_init_common_hw(); |
| @@ -286,7 +301,6 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery) | |||
| 286 | #endif | 301 | #endif |
| 287 | 302 | ||
| 288 | static struct omap_board_config_kernel palmte_config[] __initdata = { | 303 | static struct omap_board_config_kernel palmte_config[] __initdata = { |
| 289 | { OMAP_TAG_USB, &palmte_usb_config }, | ||
| 290 | { OMAP_TAG_LCD, &palmte_lcd_config }, | 304 | { OMAP_TAG_LCD, &palmte_lcd_config }, |
| 291 | { OMAP_TAG_UART, &palmte_uart_config }, | 305 | { OMAP_TAG_UART, &palmte_uart_config }, |
| 292 | }; | 306 | }; |
| @@ -341,6 +355,7 @@ static void __init omap_palmte_init(void) | |||
| 341 | spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); | 355 | spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); |
| 342 | palmte_misc_gpio_setup(); | 356 | palmte_misc_gpio_setup(); |
| 343 | omap_serial_init(); | 357 | omap_serial_init(); |
| 358 | omap_usb_init(&palmte_usb_config); | ||
| 344 | omap_register_i2c_bus(1, 100, NULL, 0); | 359 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 345 | } | 360 | } |
| 346 | 361 | ||
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 1cbc1275c95f..4f1b44831d37 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
| @@ -43,6 +43,13 @@ | |||
| 43 | #include <linux/spi/spi.h> | 43 | #include <linux/spi/spi.h> |
| 44 | #include <linux/spi/ads7846.h> | 44 | #include <linux/spi/ads7846.h> |
| 45 | 45 | ||
| 46 | #define PALMTT_USBDETECT_GPIO 0 | ||
| 47 | #define PALMTT_CABLE_GPIO 1 | ||
| 48 | #define PALMTT_LED_GPIO 3 | ||
| 49 | #define PALMTT_PENIRQ_GPIO 6 | ||
| 50 | #define PALMTT_MMC_WP_GPIO 8 | ||
| 51 | #define PALMTT_HDQ_GPIO 11 | ||
| 52 | |||
| 46 | static int palmtt_keymap[] = { | 53 | static int palmtt_keymap[] = { |
| 47 | KEY(0, 0, KEY_ESC), | 54 | KEY(0, 0, KEY_ESC), |
| 48 | KEY(0, 1, KEY_SPACE), | 55 | KEY(0, 1, KEY_SPACE), |
| @@ -272,7 +279,6 @@ static struct omap_uart_config palmtt_uart_config __initdata = { | |||
| 272 | }; | 279 | }; |
| 273 | 280 | ||
| 274 | static struct omap_board_config_kernel palmtt_config[] __initdata = { | 281 | static struct omap_board_config_kernel palmtt_config[] __initdata = { |
| 275 | { OMAP_TAG_USB, &palmtt_usb_config }, | ||
| 276 | { OMAP_TAG_LCD, &palmtt_lcd_config }, | 282 | { OMAP_TAG_LCD, &palmtt_lcd_config }, |
| 277 | { OMAP_TAG_UART, &palmtt_uart_config }, | 283 | { OMAP_TAG_UART, &palmtt_uart_config }, |
| 278 | }; | 284 | }; |
| @@ -297,6 +303,7 @@ static void __init omap_palmtt_init(void) | |||
| 297 | 303 | ||
| 298 | spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); | 304 | spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); |
| 299 | omap_serial_init(); | 305 | omap_serial_init(); |
| 306 | omap_usb_init(&palmtt_usb_config); | ||
| 300 | omap_register_i2c_bus(1, 100, NULL, 0); | 307 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 301 | } | 308 | } |
| 302 | 309 | ||
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index baf5efbfe3e8..9a55c3c58218 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
| @@ -46,6 +46,16 @@ | |||
| 46 | #include <linux/spi/spi.h> | 46 | #include <linux/spi/spi.h> |
| 47 | #include <linux/spi/ads7846.h> | 47 | #include <linux/spi/ads7846.h> |
| 48 | 48 | ||
| 49 | #define PALMZ71_USBDETECT_GPIO 0 | ||
| 50 | #define PALMZ71_PENIRQ_GPIO 6 | ||
| 51 | #define PALMZ71_MMC_WP_GPIO 8 | ||
| 52 | #define PALMZ71_HDQ_GPIO 11 | ||
| 53 | |||
| 54 | #define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) | ||
| 55 | #define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) | ||
| 56 | #define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) | ||
| 57 | #define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) | ||
| 58 | |||
| 49 | static void __init | 59 | static void __init |
| 50 | omap_palmz71_init_irq(void) | 60 | omap_palmz71_init_irq(void) |
| 51 | { | 61 | { |
| @@ -239,7 +249,6 @@ static struct omap_uart_config palmz71_uart_config __initdata = { | |||
| 239 | }; | 249 | }; |
| 240 | 250 | ||
| 241 | static struct omap_board_config_kernel palmz71_config[] __initdata = { | 251 | static struct omap_board_config_kernel palmz71_config[] __initdata = { |
| 242 | {OMAP_TAG_USB, &palmz71_usb_config}, | ||
| 243 | {OMAP_TAG_LCD, &palmz71_lcd_config}, | 252 | {OMAP_TAG_LCD, &palmz71_lcd_config}, |
| 244 | {OMAP_TAG_UART, &palmz71_uart_config}, | 253 | {OMAP_TAG_UART, &palmz71_uart_config}, |
| 245 | }; | 254 | }; |
| @@ -313,6 +322,7 @@ omap_palmz71_init(void) | |||
| 313 | 322 | ||
| 314 | spi_register_board_info(palmz71_boardinfo, | 323 | spi_register_board_info(palmz71_boardinfo, |
| 315 | ARRAY_SIZE(palmz71_boardinfo)); | 324 | ARRAY_SIZE(palmz71_boardinfo)); |
| 325 | omap_usb_init(&palmz71_usb_config); | ||
| 316 | omap_serial_init(); | 326 | omap_serial_init(); |
| 317 | omap_register_i2c_bus(1, 100, NULL, 0); | 327 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 318 | palmz71_gpio_setup(0); | 328 | palmz71_gpio_setup(0); |
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 66a4d7d5255d..58a46e4e45c3 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 18 | #include <mach/mmc.h> | 18 | #include <mach/mmc.h> |
| 19 | #include <mach/gpio.h> | 19 | #include <mach/gpio.h> |
| 20 | #include <mach/board-sx1.h> | ||
| 20 | 21 | ||
| 21 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
| 22 | 23 | ||
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 28c76a1e71c0..c096577695fe 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | #include <mach/board.h> | 41 | #include <mach/board.h> |
| 42 | #include <mach/common.h> | 42 | #include <mach/common.h> |
| 43 | #include <mach/keypad.h> | 43 | #include <mach/keypad.h> |
| 44 | #include <mach/board-sx1.h> | ||
| 44 | 45 | ||
| 45 | /* Write to I2C device */ | 46 | /* Write to I2C device */ |
| 46 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) | 47 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) |
| @@ -373,7 +374,6 @@ static struct omap_uart_config sx1_uart_config __initdata = { | |||
| 373 | }; | 374 | }; |
| 374 | 375 | ||
| 375 | static struct omap_board_config_kernel sx1_config[] __initdata = { | 376 | static struct omap_board_config_kernel sx1_config[] __initdata = { |
| 376 | { OMAP_TAG_USB, &sx1_usb_config }, | ||
| 377 | { OMAP_TAG_LCD, &sx1_lcd_config }, | 377 | { OMAP_TAG_LCD, &sx1_lcd_config }, |
| 378 | { OMAP_TAG_UART, &sx1_uart_config }, | 378 | { OMAP_TAG_UART, &sx1_uart_config }, |
| 379 | }; | 379 | }; |
| @@ -388,6 +388,7 @@ static void __init omap_sx1_init(void) | |||
| 388 | omap_board_config_size = ARRAY_SIZE(sx1_config); | 388 | omap_board_config_size = ARRAY_SIZE(sx1_config); |
| 389 | omap_serial_init(); | 389 | omap_serial_init(); |
| 390 | omap_register_i2c_bus(1, 100, NULL, 0); | 390 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 391 | omap_usb_init(&sx1_usb_config); | ||
| 391 | sx1_mmc_init(); | 392 | sx1_mmc_init(); |
| 392 | 393 | ||
| 393 | /* turn on USB power */ | 394 | /* turn on USB power */ |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index a7653542a2b0..98275e03dad1 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
| @@ -145,7 +145,6 @@ static struct omap_uart_config voiceblue_uart_config __initdata = { | |||
| 145 | }; | 145 | }; |
| 146 | 146 | ||
| 147 | static struct omap_board_config_kernel voiceblue_config[] = { | 147 | static struct omap_board_config_kernel voiceblue_config[] = { |
| 148 | { OMAP_TAG_USB, &voiceblue_usb_config }, | ||
| 149 | { OMAP_TAG_UART, &voiceblue_uart_config }, | 148 | { OMAP_TAG_UART, &voiceblue_uart_config }, |
| 150 | }; | 149 | }; |
| 151 | 150 | ||
| @@ -185,6 +184,7 @@ static void __init voiceblue_init(void) | |||
| 185 | omap_board_config = voiceblue_config; | 184 | omap_board_config = voiceblue_config; |
| 186 | omap_board_config_size = ARRAY_SIZE(voiceblue_config); | 185 | omap_board_config_size = ARRAY_SIZE(voiceblue_config); |
| 187 | omap_serial_init(); | 186 | omap_serial_init(); |
| 187 | omap_usb_init(&voiceblue_usb_config); | ||
| 188 | omap_register_i2c_bus(1, 100, NULL, 0); | 188 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 189 | 189 | ||
| 190 | /* There is a good chance board is going up, so enable power LED | 190 | /* There is a good chance board is going up, so enable power LED |
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 5fba20731710..dafe4f71d15f 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
| @@ -20,41 +20,161 @@ | |||
| 20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 21 | 21 | ||
| 22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/clkdev.h> | ||
| 23 | 24 | ||
| 24 | #include <mach/cpu.h> | 25 | #include <mach/cpu.h> |
| 25 | #include <mach/usb.h> | 26 | #include <mach/usb.h> |
| 26 | #include <mach/clock.h> | 27 | #include <mach/clock.h> |
| 27 | #include <mach/sram.h> | 28 | #include <mach/sram.h> |
| 28 | 29 | ||
| 30 | static const struct clkops clkops_generic; | ||
| 31 | static const struct clkops clkops_uart; | ||
| 32 | static const struct clkops clkops_dspck; | ||
| 33 | |||
| 29 | #include "clock.h" | 34 | #include "clock.h" |
| 30 | 35 | ||
| 36 | static int clk_omap1_dummy_enable(struct clk *clk) | ||
| 37 | { | ||
| 38 | return 0; | ||
| 39 | } | ||
| 40 | |||
| 41 | static void clk_omap1_dummy_disable(struct clk *clk) | ||
| 42 | { | ||
| 43 | } | ||
| 44 | |||
| 45 | static const struct clkops clkops_dummy = { | ||
| 46 | .enable = clk_omap1_dummy_enable, | ||
| 47 | .disable = clk_omap1_dummy_disable, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct clk dummy_ck = { | ||
| 51 | .name = "dummy", | ||
| 52 | .ops = &clkops_dummy, | ||
| 53 | .flags = RATE_FIXED, | ||
| 54 | }; | ||
| 55 | |||
| 56 | struct omap_clk { | ||
| 57 | u32 cpu; | ||
| 58 | struct clk_lookup lk; | ||
| 59 | }; | ||
| 60 | |||
| 61 | #define CLK(dev, con, ck, cp) \ | ||
| 62 | { \ | ||
| 63 | .cpu = cp, \ | ||
| 64 | .lk = { \ | ||
| 65 | .dev_id = dev, \ | ||
| 66 | .con_id = con, \ | ||
| 67 | .clk = ck, \ | ||
| 68 | }, \ | ||
| 69 | } | ||
| 70 | |||
| 71 | #define CK_310 (1 << 0) | ||
| 72 | #define CK_730 (1 << 1) | ||
| 73 | #define CK_1510 (1 << 2) | ||
| 74 | #define CK_16XX (1 << 3) | ||
| 75 | |||
| 76 | static struct omap_clk omap_clks[] = { | ||
| 77 | /* non-ULPD clocks */ | ||
| 78 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310), | ||
| 79 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), | ||
| 80 | /* CK_GEN1 clocks */ | ||
| 81 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | ||
| 82 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | ||
| 83 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | ||
| 84 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 85 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | ||
| 86 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 87 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 88 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 89 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | ||
| 90 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 91 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | ||
| 92 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | ||
| 93 | /* CK_GEN2 clocks */ | ||
| 94 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | ||
| 95 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | ||
| 96 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | ||
| 97 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
| 98 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | ||
| 99 | /* CK_GEN3 clocks */ | ||
| 100 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730), | ||
| 101 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | ||
| 102 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), | ||
| 103 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | ||
| 104 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | ||
| 105 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | ||
| 106 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | ||
| 107 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 108 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), | ||
| 109 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | ||
| 110 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | ||
| 111 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730), | ||
| 112 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | ||
| 113 | /* ULPD clocks */ | ||
| 114 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | ||
| 115 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | ||
| 116 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | ||
| 117 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | ||
| 118 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | ||
| 119 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | ||
| 120 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | ||
| 121 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | ||
| 122 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | ||
| 123 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | ||
| 124 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | ||
| 125 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | ||
| 126 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | ||
| 127 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | ||
| 128 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 129 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | ||
| 130 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | ||
| 131 | /* Virtual clocks */ | ||
| 132 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | ||
| 133 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), | ||
| 134 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), | ||
| 135 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 136 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 137 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | ||
| 138 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 139 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | ||
| 140 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 141 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | ||
| 142 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 143 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
| 144 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 145 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
| 146 | }; | ||
| 147 | |||
| 148 | static int omap1_clk_enable_generic(struct clk * clk); | ||
| 149 | static int omap1_clk_enable(struct clk *clk); | ||
| 150 | static void omap1_clk_disable_generic(struct clk * clk); | ||
| 151 | static void omap1_clk_disable(struct clk *clk); | ||
| 152 | |||
| 31 | __u32 arm_idlect1_mask; | 153 | __u32 arm_idlect1_mask; |
| 32 | 154 | ||
| 33 | /*------------------------------------------------------------------------- | 155 | /*------------------------------------------------------------------------- |
| 34 | * Omap1 specific clock functions | 156 | * Omap1 specific clock functions |
| 35 | *-------------------------------------------------------------------------*/ | 157 | *-------------------------------------------------------------------------*/ |
| 36 | 158 | ||
| 37 | static void omap1_watchdog_recalc(struct clk * clk) | 159 | static unsigned long omap1_watchdog_recalc(struct clk *clk) |
| 38 | { | 160 | { |
| 39 | clk->rate = clk->parent->rate / 14; | 161 | return clk->parent->rate / 14; |
| 40 | } | 162 | } |
| 41 | 163 | ||
| 42 | static void omap1_uart_recalc(struct clk * clk) | 164 | static unsigned long omap1_uart_recalc(struct clk *clk) |
| 43 | { | 165 | { |
| 44 | unsigned int val = omap_readl(clk->enable_reg); | 166 | unsigned int val = __raw_readl(clk->enable_reg); |
| 45 | if (val & clk->enable_bit) | 167 | return val & clk->enable_bit ? 48000000 : 12000000; |
| 46 | clk->rate = 48000000; | ||
| 47 | else | ||
| 48 | clk->rate = 12000000; | ||
| 49 | } | 168 | } |
| 50 | 169 | ||
| 51 | static void omap1_sossi_recalc(struct clk *clk) | 170 | static unsigned long omap1_sossi_recalc(struct clk *clk) |
| 52 | { | 171 | { |
| 53 | u32 div = omap_readl(MOD_CONF_CTRL_1); | 172 | u32 div = omap_readl(MOD_CONF_CTRL_1); |
| 54 | 173 | ||
| 55 | div = (div >> 17) & 0x7; | 174 | div = (div >> 17) & 0x7; |
| 56 | div++; | 175 | div++; |
| 57 | clk->rate = clk->parent->rate / div; | 176 | |
| 177 | return clk->parent->rate / div; | ||
| 58 | } | 178 | } |
| 59 | 179 | ||
| 60 | static int omap1_clk_enable_dsp_domain(struct clk *clk) | 180 | static int omap1_clk_enable_dsp_domain(struct clk *clk) |
| @@ -78,6 +198,11 @@ static void omap1_clk_disable_dsp_domain(struct clk *clk) | |||
| 78 | } | 198 | } |
| 79 | } | 199 | } |
| 80 | 200 | ||
| 201 | static const struct clkops clkops_dspck = { | ||
| 202 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 203 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 204 | }; | ||
| 205 | |||
| 81 | static int omap1_clk_enable_uart_functional(struct clk *clk) | 206 | static int omap1_clk_enable_uart_functional(struct clk *clk) |
| 82 | { | 207 | { |
| 83 | int ret; | 208 | int ret; |
| @@ -105,6 +230,11 @@ static void omap1_clk_disable_uart_functional(struct clk *clk) | |||
| 105 | omap1_clk_disable_generic(clk); | 230 | omap1_clk_disable_generic(clk); |
| 106 | } | 231 | } |
| 107 | 232 | ||
| 233 | static const struct clkops clkops_uart = { | ||
| 234 | .enable = &omap1_clk_enable_uart_functional, | ||
| 235 | .disable = &omap1_clk_disable_uart_functional, | ||
| 236 | }; | ||
| 237 | |||
| 108 | static void omap1_clk_allow_idle(struct clk *clk) | 238 | static void omap1_clk_allow_idle(struct clk *clk) |
| 109 | { | 239 | { |
| 110 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | 240 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; |
| @@ -197,9 +327,6 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |||
| 197 | struct clk * parent; | 327 | struct clk * parent; |
| 198 | unsigned dsor_exp; | 328 | unsigned dsor_exp; |
| 199 | 329 | ||
| 200 | if (unlikely(!(clk->flags & RATE_CKCTL))) | ||
| 201 | return -EINVAL; | ||
| 202 | |||
| 203 | parent = clk->parent; | 330 | parent = clk->parent; |
| 204 | if (unlikely(parent == NULL)) | 331 | if (unlikely(parent == NULL)) |
| 205 | return -EIO; | 332 | return -EIO; |
| @@ -215,22 +342,15 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |||
| 215 | return dsor_exp; | 342 | return dsor_exp; |
| 216 | } | 343 | } |
| 217 | 344 | ||
| 218 | static void omap1_ckctl_recalc(struct clk * clk) | 345 | static unsigned long omap1_ckctl_recalc(struct clk *clk) |
| 219 | { | 346 | { |
| 220 | int dsor; | ||
| 221 | |||
| 222 | /* Calculate divisor encoded as 2-bit exponent */ | 347 | /* Calculate divisor encoded as 2-bit exponent */ |
| 223 | dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); | 348 | int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); |
| 224 | 349 | ||
| 225 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | 350 | return clk->parent->rate / dsor; |
| 226 | return; /* No change, quick exit */ | ||
| 227 | clk->rate = clk->parent->rate / dsor; | ||
| 228 | |||
| 229 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 230 | propagate_rate(clk); | ||
| 231 | } | 351 | } |
| 232 | 352 | ||
| 233 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) | 353 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) |
| 234 | { | 354 | { |
| 235 | int dsor; | 355 | int dsor; |
| 236 | 356 | ||
| @@ -245,12 +365,7 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) | |||
| 245 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); | 365 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); |
| 246 | omap1_clk_disable(&api_ck.clk); | 366 | omap1_clk_disable(&api_ck.clk); |
| 247 | 367 | ||
| 248 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | 368 | return clk->parent->rate / dsor; |
| 249 | return; /* No change, quick exit */ | ||
| 250 | clk->rate = clk->parent->rate / dsor; | ||
| 251 | |||
| 252 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 253 | propagate_rate(clk); | ||
| 254 | } | 369 | } |
| 255 | 370 | ||
| 256 | /* MPU virtual clock functions */ | 371 | /* MPU virtual clock functions */ |
| @@ -289,35 +404,57 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |||
| 289 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | 404 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); |
| 290 | 405 | ||
| 291 | ck_dpll1.rate = ptr->pll_rate; | 406 | ck_dpll1.rate = ptr->pll_rate; |
| 292 | propagate_rate(&ck_dpll1); | ||
| 293 | return 0; | 407 | return 0; |
| 294 | } | 408 | } |
| 295 | 409 | ||
| 296 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | 410 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) |
| 297 | { | 411 | { |
| 298 | int ret = -EINVAL; | 412 | int dsor_exp; |
| 299 | int dsor_exp; | 413 | u16 regval; |
| 300 | __u16 regval; | ||
| 301 | |||
| 302 | if (clk->flags & RATE_CKCTL) { | ||
| 303 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 304 | if (dsor_exp > 3) | ||
| 305 | dsor_exp = -EINVAL; | ||
| 306 | if (dsor_exp < 0) | ||
| 307 | return dsor_exp; | ||
| 308 | |||
| 309 | regval = __raw_readw(DSP_CKCTL); | ||
| 310 | regval &= ~(3 << clk->rate_offset); | ||
| 311 | regval |= dsor_exp << clk->rate_offset; | ||
| 312 | __raw_writew(regval, DSP_CKCTL); | ||
| 313 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 314 | ret = 0; | ||
| 315 | } | ||
| 316 | 414 | ||
| 317 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | 415 | dsor_exp = calc_dsor_exp(clk, rate); |
| 318 | propagate_rate(clk); | 416 | if (dsor_exp > 3) |
| 417 | dsor_exp = -EINVAL; | ||
| 418 | if (dsor_exp < 0) | ||
| 419 | return dsor_exp; | ||
| 319 | 420 | ||
| 320 | return ret; | 421 | regval = __raw_readw(DSP_CKCTL); |
| 422 | regval &= ~(3 << clk->rate_offset); | ||
| 423 | regval |= dsor_exp << clk->rate_offset; | ||
| 424 | __raw_writew(regval, DSP_CKCTL); | ||
| 425 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 426 | |||
| 427 | return 0; | ||
| 428 | } | ||
| 429 | |||
| 430 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) | ||
| 431 | { | ||
| 432 | int dsor_exp = calc_dsor_exp(clk, rate); | ||
| 433 | if (dsor_exp < 0) | ||
| 434 | return dsor_exp; | ||
| 435 | if (dsor_exp > 3) | ||
| 436 | dsor_exp = 3; | ||
| 437 | return clk->parent->rate / (1 << dsor_exp); | ||
| 438 | } | ||
| 439 | |||
| 440 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) | ||
| 441 | { | ||
| 442 | int dsor_exp; | ||
| 443 | u16 regval; | ||
| 444 | |||
| 445 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 446 | if (dsor_exp > 3) | ||
| 447 | dsor_exp = -EINVAL; | ||
| 448 | if (dsor_exp < 0) | ||
| 449 | return dsor_exp; | ||
| 450 | |||
| 451 | regval = omap_readw(ARM_CKCTL); | ||
| 452 | regval &= ~(3 << clk->rate_offset); | ||
| 453 | regval |= dsor_exp << clk->rate_offset; | ||
| 454 | regval = verify_ckctl_value(regval); | ||
| 455 | omap_writew(regval, ARM_CKCTL); | ||
| 456 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 457 | return 0; | ||
| 321 | } | 458 | } |
| 322 | 459 | ||
| 323 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) | 460 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) |
| @@ -372,14 +509,14 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | |||
| 372 | { | 509 | { |
| 373 | unsigned int val; | 510 | unsigned int val; |
| 374 | 511 | ||
| 375 | val = omap_readl(clk->enable_reg); | 512 | val = __raw_readl(clk->enable_reg); |
| 376 | if (rate == 12000000) | 513 | if (rate == 12000000) |
| 377 | val &= ~(1 << clk->enable_bit); | 514 | val &= ~(1 << clk->enable_bit); |
| 378 | else if (rate == 48000000) | 515 | else if (rate == 48000000) |
| 379 | val |= (1 << clk->enable_bit); | 516 | val |= (1 << clk->enable_bit); |
| 380 | else | 517 | else |
| 381 | return -EINVAL; | 518 | return -EINVAL; |
| 382 | omap_writel(val, clk->enable_reg); | 519 | __raw_writel(val, clk->enable_reg); |
| 383 | clk->rate = rate; | 520 | clk->rate = rate; |
| 384 | 521 | ||
| 385 | return 0; | 522 | return 0; |
| @@ -398,8 +535,8 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | |||
| 398 | else | 535 | else |
| 399 | ratio_bits = (dsor - 2) << 2; | 536 | ratio_bits = (dsor - 2) << 2; |
| 400 | 537 | ||
| 401 | ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; | 538 | ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; |
| 402 | omap_writew(ratio_bits, clk->enable_reg); | 539 | __raw_writew(ratio_bits, clk->enable_reg); |
| 403 | 540 | ||
| 404 | return 0; | 541 | return 0; |
| 405 | } | 542 | } |
| @@ -423,8 +560,6 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) | |||
| 423 | omap_writel(l, MOD_CONF_CTRL_1); | 560 | omap_writel(l, MOD_CONF_CTRL_1); |
| 424 | 561 | ||
| 425 | clk->rate = p_rate / (div + 1); | 562 | clk->rate = p_rate / (div + 1); |
| 426 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 427 | propagate_rate(clk); | ||
| 428 | 563 | ||
| 429 | return 0; | 564 | return 0; |
| 430 | } | 565 | } |
| @@ -440,8 +575,8 @@ static void omap1_init_ext_clk(struct clk * clk) | |||
| 440 | __u16 ratio_bits; | 575 | __u16 ratio_bits; |
| 441 | 576 | ||
| 442 | /* Determine current rate and ensure clock is based on 96MHz APLL */ | 577 | /* Determine current rate and ensure clock is based on 96MHz APLL */ |
| 443 | ratio_bits = omap_readw(clk->enable_reg) & ~1; | 578 | ratio_bits = __raw_readw(clk->enable_reg) & ~1; |
| 444 | omap_writew(ratio_bits, clk->enable_reg); | 579 | __raw_writew(ratio_bits, clk->enable_reg); |
| 445 | 580 | ||
| 446 | ratio_bits = (ratio_bits & 0xfc) >> 2; | 581 | ratio_bits = (ratio_bits & 0xfc) >> 2; |
| 447 | if (ratio_bits > 6) | 582 | if (ratio_bits > 6) |
| @@ -468,7 +603,7 @@ static int omap1_clk_enable(struct clk *clk) | |||
| 468 | omap1_clk_deny_idle(clk->parent); | 603 | omap1_clk_deny_idle(clk->parent); |
| 469 | } | 604 | } |
| 470 | 605 | ||
| 471 | ret = clk->enable(clk); | 606 | ret = clk->ops->enable(clk); |
| 472 | 607 | ||
| 473 | if (unlikely(ret != 0) && clk->parent) { | 608 | if (unlikely(ret != 0) && clk->parent) { |
| 474 | omap1_clk_disable(clk->parent); | 609 | omap1_clk_disable(clk->parent); |
| @@ -482,7 +617,7 @@ static int omap1_clk_enable(struct clk *clk) | |||
| 482 | static void omap1_clk_disable(struct clk *clk) | 617 | static void omap1_clk_disable(struct clk *clk) |
| 483 | { | 618 | { |
| 484 | if (clk->usecount > 0 && !(--clk->usecount)) { | 619 | if (clk->usecount > 0 && !(--clk->usecount)) { |
| 485 | clk->disable(clk); | 620 | clk->ops->disable(clk); |
| 486 | if (likely(clk->parent)) { | 621 | if (likely(clk->parent)) { |
| 487 | omap1_clk_disable(clk->parent); | 622 | omap1_clk_disable(clk->parent); |
| 488 | if (clk->flags & CLOCK_NO_IDLE_PARENT) | 623 | if (clk->flags & CLOCK_NO_IDLE_PARENT) |
| @@ -496,9 +631,6 @@ static int omap1_clk_enable_generic(struct clk *clk) | |||
| 496 | __u16 regval16; | 631 | __u16 regval16; |
| 497 | __u32 regval32; | 632 | __u32 regval32; |
| 498 | 633 | ||
| 499 | if (clk->flags & ALWAYS_ENABLED) | ||
| 500 | return 0; | ||
| 501 | |||
| 502 | if (unlikely(clk->enable_reg == NULL)) { | 634 | if (unlikely(clk->enable_reg == NULL)) { |
| 503 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | 635 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 504 | clk->name); | 636 | clk->name); |
| @@ -506,25 +638,13 @@ static int omap1_clk_enable_generic(struct clk *clk) | |||
| 506 | } | 638 | } |
| 507 | 639 | ||
| 508 | if (clk->flags & ENABLE_REG_32BIT) { | 640 | if (clk->flags & ENABLE_REG_32BIT) { |
| 509 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 641 | regval32 = __raw_readl(clk->enable_reg); |
| 510 | regval32 = __raw_readl(clk->enable_reg); | 642 | regval32 |= (1 << clk->enable_bit); |
| 511 | regval32 |= (1 << clk->enable_bit); | 643 | __raw_writel(regval32, clk->enable_reg); |
| 512 | __raw_writel(regval32, clk->enable_reg); | ||
| 513 | } else { | ||
| 514 | regval32 = omap_readl(clk->enable_reg); | ||
| 515 | regval32 |= (1 << clk->enable_bit); | ||
| 516 | omap_writel(regval32, clk->enable_reg); | ||
| 517 | } | ||
| 518 | } else { | 644 | } else { |
| 519 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 645 | regval16 = __raw_readw(clk->enable_reg); |
| 520 | regval16 = __raw_readw(clk->enable_reg); | 646 | regval16 |= (1 << clk->enable_bit); |
| 521 | regval16 |= (1 << clk->enable_bit); | 647 | __raw_writew(regval16, clk->enable_reg); |
| 522 | __raw_writew(regval16, clk->enable_reg); | ||
| 523 | } else { | ||
| 524 | regval16 = omap_readw(clk->enable_reg); | ||
| 525 | regval16 |= (1 << clk->enable_bit); | ||
| 526 | omap_writew(regval16, clk->enable_reg); | ||
| 527 | } | ||
| 528 | } | 648 | } |
| 529 | 649 | ||
| 530 | return 0; | 650 | return 0; |
| @@ -539,44 +659,26 @@ static void omap1_clk_disable_generic(struct clk *clk) | |||
| 539 | return; | 659 | return; |
| 540 | 660 | ||
| 541 | if (clk->flags & ENABLE_REG_32BIT) { | 661 | if (clk->flags & ENABLE_REG_32BIT) { |
| 542 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 662 | regval32 = __raw_readl(clk->enable_reg); |
| 543 | regval32 = __raw_readl(clk->enable_reg); | 663 | regval32 &= ~(1 << clk->enable_bit); |
| 544 | regval32 &= ~(1 << clk->enable_bit); | 664 | __raw_writel(regval32, clk->enable_reg); |
| 545 | __raw_writel(regval32, clk->enable_reg); | ||
| 546 | } else { | ||
| 547 | regval32 = omap_readl(clk->enable_reg); | ||
| 548 | regval32 &= ~(1 << clk->enable_bit); | ||
| 549 | omap_writel(regval32, clk->enable_reg); | ||
| 550 | } | ||
| 551 | } else { | 665 | } else { |
| 552 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 666 | regval16 = __raw_readw(clk->enable_reg); |
| 553 | regval16 = __raw_readw(clk->enable_reg); | 667 | regval16 &= ~(1 << clk->enable_bit); |
| 554 | regval16 &= ~(1 << clk->enable_bit); | 668 | __raw_writew(regval16, clk->enable_reg); |
| 555 | __raw_writew(regval16, clk->enable_reg); | ||
| 556 | } else { | ||
| 557 | regval16 = omap_readw(clk->enable_reg); | ||
| 558 | regval16 &= ~(1 << clk->enable_bit); | ||
| 559 | omap_writew(regval16, clk->enable_reg); | ||
| 560 | } | ||
| 561 | } | 669 | } |
| 562 | } | 670 | } |
| 563 | 671 | ||
| 672 | static const struct clkops clkops_generic = { | ||
| 673 | .enable = &omap1_clk_enable_generic, | ||
| 674 | .disable = &omap1_clk_disable_generic, | ||
| 675 | }; | ||
| 676 | |||
| 564 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | 677 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) |
| 565 | { | 678 | { |
| 566 | int dsor_exp; | ||
| 567 | |||
| 568 | if (clk->flags & RATE_FIXED) | 679 | if (clk->flags & RATE_FIXED) |
| 569 | return clk->rate; | 680 | return clk->rate; |
| 570 | 681 | ||
| 571 | if (clk->flags & RATE_CKCTL) { | ||
| 572 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 573 | if (dsor_exp < 0) | ||
| 574 | return dsor_exp; | ||
| 575 | if (dsor_exp > 3) | ||
| 576 | dsor_exp = 3; | ||
| 577 | return clk->parent->rate / (1 << dsor_exp); | ||
| 578 | } | ||
| 579 | |||
| 580 | if (clk->round_rate != NULL) | 682 | if (clk->round_rate != NULL) |
| 581 | return clk->round_rate(clk, rate); | 683 | return clk->round_rate(clk, rate); |
| 582 | 684 | ||
| @@ -586,30 +688,9 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | |||
| 586 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | 688 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) |
| 587 | { | 689 | { |
| 588 | int ret = -EINVAL; | 690 | int ret = -EINVAL; |
| 589 | int dsor_exp; | ||
| 590 | __u16 regval; | ||
| 591 | 691 | ||
| 592 | if (clk->set_rate) | 692 | if (clk->set_rate) |
| 593 | ret = clk->set_rate(clk, rate); | 693 | ret = clk->set_rate(clk, rate); |
| 594 | else if (clk->flags & RATE_CKCTL) { | ||
| 595 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 596 | if (dsor_exp > 3) | ||
| 597 | dsor_exp = -EINVAL; | ||
| 598 | if (dsor_exp < 0) | ||
| 599 | return dsor_exp; | ||
| 600 | |||
| 601 | regval = omap_readw(ARM_CKCTL); | ||
| 602 | regval &= ~(3 << clk->rate_offset); | ||
| 603 | regval |= dsor_exp << clk->rate_offset; | ||
| 604 | regval = verify_ckctl_value(regval); | ||
| 605 | omap_writew(regval, ARM_CKCTL); | ||
| 606 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 607 | ret = 0; | ||
| 608 | } | ||
| 609 | |||
| 610 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | ||
| 611 | propagate_rate(clk); | ||
| 612 | |||
| 613 | return ret; | 694 | return ret; |
| 614 | } | 695 | } |
| 615 | 696 | ||
| @@ -632,17 +713,10 @@ static void __init omap1_clk_disable_unused(struct clk *clk) | |||
| 632 | } | 713 | } |
| 633 | 714 | ||
| 634 | /* Is the clock already disabled? */ | 715 | /* Is the clock already disabled? */ |
| 635 | if (clk->flags & ENABLE_REG_32BIT) { | 716 | if (clk->flags & ENABLE_REG_32BIT) |
| 636 | if (clk->flags & VIRTUAL_IO_ADDRESS) | 717 | regval32 = __raw_readl(clk->enable_reg); |
| 637 | regval32 = __raw_readl(clk->enable_reg); | 718 | else |
| 638 | else | 719 | regval32 = __raw_readw(clk->enable_reg); |
| 639 | regval32 = omap_readl(clk->enable_reg); | ||
| 640 | } else { | ||
| 641 | if (clk->flags & VIRTUAL_IO_ADDRESS) | ||
| 642 | regval32 = __raw_readw(clk->enable_reg); | ||
| 643 | else | ||
| 644 | regval32 = omap_readw(clk->enable_reg); | ||
| 645 | } | ||
| 646 | 720 | ||
| 647 | if ((regval32 & (1 << clk->enable_bit)) == 0) | 721 | if ((regval32 & (1 << clk->enable_bit)) == 0) |
| 648 | return; | 722 | return; |
| @@ -659,7 +733,7 @@ static void __init omap1_clk_disable_unused(struct clk *clk) | |||
| 659 | } | 733 | } |
| 660 | 734 | ||
| 661 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); | 735 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); |
| 662 | clk->disable(clk); | 736 | clk->ops->disable(clk); |
| 663 | printk(" done\n"); | 737 | printk(" done\n"); |
| 664 | } | 738 | } |
| 665 | 739 | ||
| @@ -677,10 +751,10 @@ static struct clk_functions omap1_clk_functions = { | |||
| 677 | 751 | ||
| 678 | int __init omap1_clk_init(void) | 752 | int __init omap1_clk_init(void) |
| 679 | { | 753 | { |
| 680 | struct clk ** clkp; | 754 | struct omap_clk *c; |
| 681 | const struct omap_clock_config *info; | 755 | const struct omap_clock_config *info; |
| 682 | int crystal_type = 0; /* Default 12 MHz */ | 756 | int crystal_type = 0; /* Default 12 MHz */ |
| 683 | u32 reg; | 757 | u32 reg, cpu_mask; |
| 684 | 758 | ||
| 685 | #ifdef CONFIG_DEBUG_LL | 759 | #ifdef CONFIG_DEBUG_LL |
| 686 | /* Resets some clocks that may be left on from bootloader, | 760 | /* Resets some clocks that may be left on from bootloader, |
| @@ -700,27 +774,24 @@ int __init omap1_clk_init(void) | |||
| 700 | /* By default all idlect1 clocks are allowed to idle */ | 774 | /* By default all idlect1 clocks are allowed to idle */ |
| 701 | arm_idlect1_mask = ~0; | 775 | arm_idlect1_mask = ~0; |
| 702 | 776 | ||
| 703 | for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { | 777 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) |
| 704 | if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { | 778 | clk_init_one(c->lk.clk); |
| 705 | clk_register(*clkp); | ||
| 706 | continue; | ||
| 707 | } | ||
| 708 | |||
| 709 | if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { | ||
| 710 | clk_register(*clkp); | ||
| 711 | continue; | ||
| 712 | } | ||
| 713 | |||
| 714 | if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { | ||
| 715 | clk_register(*clkp); | ||
| 716 | continue; | ||
| 717 | } | ||
| 718 | 779 | ||
| 719 | if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) { | 780 | cpu_mask = 0; |
| 720 | clk_register(*clkp); | 781 | if (cpu_is_omap16xx()) |
| 721 | continue; | 782 | cpu_mask |= CK_16XX; |
| 783 | if (cpu_is_omap1510()) | ||
| 784 | cpu_mask |= CK_1510; | ||
| 785 | if (cpu_is_omap730()) | ||
| 786 | cpu_mask |= CK_730; | ||
| 787 | if (cpu_is_omap310()) | ||
| 788 | cpu_mask |= CK_310; | ||
| 789 | |||
| 790 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
| 791 | if (c->cpu & cpu_mask) { | ||
| 792 | clkdev_add(&c->lk); | ||
| 793 | clk_register(c->lk.clk); | ||
| 722 | } | 794 | } |
| 723 | } | ||
| 724 | 795 | ||
| 725 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | 796 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); |
| 726 | if (info != NULL) { | 797 | if (info != NULL) { |
| @@ -769,7 +840,6 @@ int __init omap1_clk_init(void) | |||
| 769 | } | 840 | } |
| 770 | } | 841 | } |
| 771 | } | 842 | } |
| 772 | propagate_rate(&ck_dpll1); | ||
| 773 | #else | 843 | #else |
| 774 | /* Find the highest supported frequency and enable it */ | 844 | /* Find the highest supported frequency and enable it */ |
| 775 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | 845 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { |
| @@ -778,9 +848,9 @@ int __init omap1_clk_init(void) | |||
| 778 | omap_writew(0x2290, DPLL_CTL); | 848 | omap_writew(0x2290, DPLL_CTL); |
| 779 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); | 849 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); |
| 780 | ck_dpll1.rate = 60000000; | 850 | ck_dpll1.rate = 60000000; |
| 781 | propagate_rate(&ck_dpll1); | ||
| 782 | } | 851 | } |
| 783 | #endif | 852 | #endif |
| 853 | propagate_rate(&ck_dpll1); | ||
| 784 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | 854 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ |
| 785 | propagate_rate(&ck_ref); | 855 | propagate_rate(&ck_ref); |
| 786 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | 856 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " |
| @@ -832,4 +902,3 @@ int __init omap1_clk_init(void) | |||
| 832 | 902 | ||
| 833 | return 0; | 903 | return 0; |
| 834 | } | 904 | } |
| 835 | |||
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index c1dcdf18d8dd..17f874271255 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h | |||
| @@ -13,27 +13,22 @@ | |||
| 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H |
| 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H |
| 15 | 15 | ||
| 16 | static int omap1_clk_enable_generic(struct clk * clk); | 16 | static unsigned long omap1_ckctl_recalc(struct clk *clk); |
| 17 | static void omap1_clk_disable_generic(struct clk * clk); | 17 | static unsigned long omap1_watchdog_recalc(struct clk *clk); |
| 18 | static void omap1_ckctl_recalc(struct clk * clk); | ||
| 19 | static void omap1_watchdog_recalc(struct clk * clk); | ||
| 20 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); | 18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
| 21 | static void omap1_sossi_recalc(struct clk *clk); | 19 | static unsigned long omap1_sossi_recalc(struct clk *clk); |
| 22 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); | 20 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); |
| 23 | static int omap1_clk_enable_dsp_domain(struct clk * clk); | ||
| 24 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); | 21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); |
| 25 | static void omap1_clk_disable_dsp_domain(struct clk * clk); | ||
| 26 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); | 22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); |
| 27 | static void omap1_uart_recalc(struct clk * clk); | 23 | static unsigned long omap1_uart_recalc(struct clk *clk); |
| 28 | static int omap1_clk_enable_uart_functional(struct clk * clk); | ||
| 29 | static void omap1_clk_disable_uart_functional(struct clk * clk); | ||
| 30 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); | 24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 31 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); | 25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 32 | static void omap1_init_ext_clk(struct clk * clk); | 26 | static void omap1_init_ext_clk(struct clk * clk); |
| 33 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); | 27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); |
| 34 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); | 28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); |
| 35 | static int omap1_clk_enable(struct clk *clk); | 29 | |
| 36 | static void omap1_clk_disable(struct clk *clk); | 30 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
| 31 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | ||
| 37 | 32 | ||
| 38 | struct mpu_rate { | 33 | struct mpu_rate { |
| 39 | unsigned long rate; | 34 | unsigned long rate; |
| @@ -152,101 +147,84 @@ static struct mpu_rate rate_table[] = { | |||
| 152 | 147 | ||
| 153 | static struct clk ck_ref = { | 148 | static struct clk ck_ref = { |
| 154 | .name = "ck_ref", | 149 | .name = "ck_ref", |
| 150 | .ops = &clkops_null, | ||
| 155 | .rate = 12000000, | 151 | .rate = 12000000, |
| 156 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 157 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, | ||
| 158 | .enable = &omap1_clk_enable_generic, | ||
| 159 | .disable = &omap1_clk_disable_generic, | ||
| 160 | }; | 152 | }; |
| 161 | 153 | ||
| 162 | static struct clk ck_dpll1 = { | 154 | static struct clk ck_dpll1 = { |
| 163 | .name = "ck_dpll1", | 155 | .name = "ck_dpll1", |
| 156 | .ops = &clkops_null, | ||
| 164 | .parent = &ck_ref, | 157 | .parent = &ck_ref, |
| 165 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 166 | CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 167 | .enable = &omap1_clk_enable_generic, | ||
| 168 | .disable = &omap1_clk_disable_generic, | ||
| 169 | }; | 158 | }; |
| 170 | 159 | ||
| 171 | static struct arm_idlect1_clk ck_dpll1out = { | 160 | static struct arm_idlect1_clk ck_dpll1out = { |
| 172 | .clk = { | 161 | .clk = { |
| 173 | .name = "ck_dpll1out", | 162 | .name = "ck_dpll1out", |
| 163 | .ops = &clkops_generic, | ||
| 174 | .parent = &ck_dpll1, | 164 | .parent = &ck_dpll1, |
| 175 | .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | | 165 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, |
| 176 | ENABLE_REG_32BIT | RATE_PROPAGATES, | 166 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 177 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 178 | .enable_bit = EN_CKOUT_ARM, | 167 | .enable_bit = EN_CKOUT_ARM, |
| 179 | .recalc = &followparent_recalc, | 168 | .recalc = &followparent_recalc, |
| 180 | .enable = &omap1_clk_enable_generic, | ||
| 181 | .disable = &omap1_clk_disable_generic, | ||
| 182 | }, | 169 | }, |
| 183 | .idlect_shift = 12, | 170 | .idlect_shift = 12, |
| 184 | }; | 171 | }; |
| 185 | 172 | ||
| 186 | static struct clk sossi_ck = { | 173 | static struct clk sossi_ck = { |
| 187 | .name = "ck_sossi", | 174 | .name = "ck_sossi", |
| 175 | .ops = &clkops_generic, | ||
| 188 | .parent = &ck_dpll1out.clk, | 176 | .parent = &ck_dpll1out.clk, |
| 189 | .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | | 177 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, |
| 190 | ENABLE_REG_32BIT, | 178 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), |
| 191 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, | ||
| 192 | .enable_bit = 16, | 179 | .enable_bit = 16, |
| 193 | .recalc = &omap1_sossi_recalc, | 180 | .recalc = &omap1_sossi_recalc, |
| 194 | .set_rate = &omap1_set_sossi_rate, | 181 | .set_rate = &omap1_set_sossi_rate, |
| 195 | .enable = &omap1_clk_enable_generic, | ||
| 196 | .disable = &omap1_clk_disable_generic, | ||
| 197 | }; | 182 | }; |
| 198 | 183 | ||
| 199 | static struct clk arm_ck = { | 184 | static struct clk arm_ck = { |
| 200 | .name = "arm_ck", | 185 | .name = "arm_ck", |
| 186 | .ops = &clkops_null, | ||
| 201 | .parent = &ck_dpll1, | 187 | .parent = &ck_dpll1, |
| 202 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 203 | CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES | | ||
| 204 | ALWAYS_ENABLED, | ||
| 205 | .rate_offset = CKCTL_ARMDIV_OFFSET, | 188 | .rate_offset = CKCTL_ARMDIV_OFFSET, |
| 206 | .recalc = &omap1_ckctl_recalc, | 189 | .recalc = &omap1_ckctl_recalc, |
| 207 | .enable = &omap1_clk_enable_generic, | 190 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 208 | .disable = &omap1_clk_disable_generic, | 191 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 209 | }; | 192 | }; |
| 210 | 193 | ||
| 211 | static struct arm_idlect1_clk armper_ck = { | 194 | static struct arm_idlect1_clk armper_ck = { |
| 212 | .clk = { | 195 | .clk = { |
| 213 | .name = "armper_ck", | 196 | .name = "armper_ck", |
| 197 | .ops = &clkops_generic, | ||
| 214 | .parent = &ck_dpll1, | 198 | .parent = &ck_dpll1, |
| 215 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 199 | .flags = CLOCK_IDLE_CONTROL, |
| 216 | CLOCK_IN_OMAP310 | RATE_CKCTL | | 200 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 217 | CLOCK_IDLE_CONTROL, | ||
| 218 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 219 | .enable_bit = EN_PERCK, | 201 | .enable_bit = EN_PERCK, |
| 220 | .rate_offset = CKCTL_PERDIV_OFFSET, | 202 | .rate_offset = CKCTL_PERDIV_OFFSET, |
| 221 | .recalc = &omap1_ckctl_recalc, | 203 | .recalc = &omap1_ckctl_recalc, |
| 222 | .enable = &omap1_clk_enable_generic, | 204 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 223 | .disable = &omap1_clk_disable_generic, | 205 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 224 | }, | 206 | }, |
| 225 | .idlect_shift = 2, | 207 | .idlect_shift = 2, |
| 226 | }; | 208 | }; |
| 227 | 209 | ||
| 228 | static struct clk arm_gpio_ck = { | 210 | static struct clk arm_gpio_ck = { |
| 229 | .name = "arm_gpio_ck", | 211 | .name = "arm_gpio_ck", |
| 212 | .ops = &clkops_generic, | ||
| 230 | .parent = &ck_dpll1, | 213 | .parent = &ck_dpll1, |
| 231 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, | 214 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 232 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 233 | .enable_bit = EN_GPIOCK, | 215 | .enable_bit = EN_GPIOCK, |
| 234 | .recalc = &followparent_recalc, | 216 | .recalc = &followparent_recalc, |
| 235 | .enable = &omap1_clk_enable_generic, | ||
| 236 | .disable = &omap1_clk_disable_generic, | ||
| 237 | }; | 217 | }; |
| 238 | 218 | ||
| 239 | static struct arm_idlect1_clk armxor_ck = { | 219 | static struct arm_idlect1_clk armxor_ck = { |
| 240 | .clk = { | 220 | .clk = { |
| 241 | .name = "armxor_ck", | 221 | .name = "armxor_ck", |
| 222 | .ops = &clkops_generic, | ||
| 242 | .parent = &ck_ref, | 223 | .parent = &ck_ref, |
| 243 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 224 | .flags = CLOCK_IDLE_CONTROL, |
| 244 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 225 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 245 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 246 | .enable_bit = EN_XORPCK, | 226 | .enable_bit = EN_XORPCK, |
| 247 | .recalc = &followparent_recalc, | 227 | .recalc = &followparent_recalc, |
| 248 | .enable = &omap1_clk_enable_generic, | ||
| 249 | .disable = &omap1_clk_disable_generic, | ||
| 250 | }, | 228 | }, |
| 251 | .idlect_shift = 1, | 229 | .idlect_shift = 1, |
| 252 | }; | 230 | }; |
| @@ -254,14 +232,12 @@ static struct arm_idlect1_clk armxor_ck = { | |||
| 254 | static struct arm_idlect1_clk armtim_ck = { | 232 | static struct arm_idlect1_clk armtim_ck = { |
| 255 | .clk = { | 233 | .clk = { |
| 256 | .name = "armtim_ck", | 234 | .name = "armtim_ck", |
| 235 | .ops = &clkops_generic, | ||
| 257 | .parent = &ck_ref, | 236 | .parent = &ck_ref, |
| 258 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 237 | .flags = CLOCK_IDLE_CONTROL, |
| 259 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 238 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 260 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 261 | .enable_bit = EN_TIMCK, | 239 | .enable_bit = EN_TIMCK, |
| 262 | .recalc = &followparent_recalc, | 240 | .recalc = &followparent_recalc, |
| 263 | .enable = &omap1_clk_enable_generic, | ||
| 264 | .disable = &omap1_clk_disable_generic, | ||
| 265 | }, | 241 | }, |
| 266 | .idlect_shift = 9, | 242 | .idlect_shift = 9, |
| 267 | }; | 243 | }; |
| @@ -269,201 +245,166 @@ static struct arm_idlect1_clk armtim_ck = { | |||
| 269 | static struct arm_idlect1_clk armwdt_ck = { | 245 | static struct arm_idlect1_clk armwdt_ck = { |
| 270 | .clk = { | 246 | .clk = { |
| 271 | .name = "armwdt_ck", | 247 | .name = "armwdt_ck", |
| 248 | .ops = &clkops_generic, | ||
| 272 | .parent = &ck_ref, | 249 | .parent = &ck_ref, |
| 273 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 250 | .flags = CLOCK_IDLE_CONTROL, |
| 274 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 251 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 275 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 276 | .enable_bit = EN_WDTCK, | 252 | .enable_bit = EN_WDTCK, |
| 277 | .recalc = &omap1_watchdog_recalc, | 253 | .recalc = &omap1_watchdog_recalc, |
| 278 | .enable = &omap1_clk_enable_generic, | ||
| 279 | .disable = &omap1_clk_disable_generic, | ||
| 280 | }, | 254 | }, |
| 281 | .idlect_shift = 0, | 255 | .idlect_shift = 0, |
| 282 | }; | 256 | }; |
| 283 | 257 | ||
| 284 | static struct clk arminth_ck16xx = { | 258 | static struct clk arminth_ck16xx = { |
| 285 | .name = "arminth_ck", | 259 | .name = "arminth_ck", |
| 260 | .ops = &clkops_null, | ||
| 286 | .parent = &arm_ck, | 261 | .parent = &arm_ck, |
| 287 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 288 | .recalc = &followparent_recalc, | 262 | .recalc = &followparent_recalc, |
| 289 | /* Note: On 16xx the frequency can be divided by 2 by programming | 263 | /* Note: On 16xx the frequency can be divided by 2 by programming |
| 290 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | 264 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 |
| 291 | * | 265 | * |
| 292 | * 1510 version is in TC clocks. | 266 | * 1510 version is in TC clocks. |
| 293 | */ | 267 | */ |
| 294 | .enable = &omap1_clk_enable_generic, | ||
| 295 | .disable = &omap1_clk_disable_generic, | ||
| 296 | }; | 268 | }; |
| 297 | 269 | ||
| 298 | static struct clk dsp_ck = { | 270 | static struct clk dsp_ck = { |
| 299 | .name = "dsp_ck", | 271 | .name = "dsp_ck", |
| 272 | .ops = &clkops_generic, | ||
| 300 | .parent = &ck_dpll1, | 273 | .parent = &ck_dpll1, |
| 301 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 274 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), |
| 302 | RATE_CKCTL, | ||
| 303 | .enable_reg = (void __iomem *)ARM_CKCTL, | ||
| 304 | .enable_bit = EN_DSPCK, | 275 | .enable_bit = EN_DSPCK, |
| 305 | .rate_offset = CKCTL_DSPDIV_OFFSET, | 276 | .rate_offset = CKCTL_DSPDIV_OFFSET, |
| 306 | .recalc = &omap1_ckctl_recalc, | 277 | .recalc = &omap1_ckctl_recalc, |
| 307 | .enable = &omap1_clk_enable_generic, | 278 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 308 | .disable = &omap1_clk_disable_generic, | 279 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 309 | }; | 280 | }; |
| 310 | 281 | ||
| 311 | static struct clk dspmmu_ck = { | 282 | static struct clk dspmmu_ck = { |
| 312 | .name = "dspmmu_ck", | 283 | .name = "dspmmu_ck", |
| 284 | .ops = &clkops_null, | ||
| 313 | .parent = &ck_dpll1, | 285 | .parent = &ck_dpll1, |
| 314 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 315 | RATE_CKCTL | ALWAYS_ENABLED, | ||
| 316 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | 286 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, |
| 317 | .recalc = &omap1_ckctl_recalc, | 287 | .recalc = &omap1_ckctl_recalc, |
| 318 | .enable = &omap1_clk_enable_generic, | 288 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 319 | .disable = &omap1_clk_disable_generic, | 289 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 320 | }; | 290 | }; |
| 321 | 291 | ||
| 322 | static struct clk dspper_ck = { | 292 | static struct clk dspper_ck = { |
| 323 | .name = "dspper_ck", | 293 | .name = "dspper_ck", |
| 294 | .ops = &clkops_dspck, | ||
| 324 | .parent = &ck_dpll1, | 295 | .parent = &ck_dpll1, |
| 325 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 326 | RATE_CKCTL | VIRTUAL_IO_ADDRESS, | ||
| 327 | .enable_reg = DSP_IDLECT2, | 296 | .enable_reg = DSP_IDLECT2, |
| 328 | .enable_bit = EN_PERCK, | 297 | .enable_bit = EN_PERCK, |
| 329 | .rate_offset = CKCTL_PERDIV_OFFSET, | 298 | .rate_offset = CKCTL_PERDIV_OFFSET, |
| 330 | .recalc = &omap1_ckctl_recalc_dsp_domain, | 299 | .recalc = &omap1_ckctl_recalc_dsp_domain, |
| 300 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
| 331 | .set_rate = &omap1_clk_set_rate_dsp_domain, | 301 | .set_rate = &omap1_clk_set_rate_dsp_domain, |
| 332 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 333 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 334 | }; | 302 | }; |
| 335 | 303 | ||
| 336 | static struct clk dspxor_ck = { | 304 | static struct clk dspxor_ck = { |
| 337 | .name = "dspxor_ck", | 305 | .name = "dspxor_ck", |
| 306 | .ops = &clkops_dspck, | ||
| 338 | .parent = &ck_ref, | 307 | .parent = &ck_ref, |
| 339 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 340 | VIRTUAL_IO_ADDRESS, | ||
| 341 | .enable_reg = DSP_IDLECT2, | 308 | .enable_reg = DSP_IDLECT2, |
| 342 | .enable_bit = EN_XORPCK, | 309 | .enable_bit = EN_XORPCK, |
| 343 | .recalc = &followparent_recalc, | 310 | .recalc = &followparent_recalc, |
| 344 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 345 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 346 | }; | 311 | }; |
| 347 | 312 | ||
| 348 | static struct clk dsptim_ck = { | 313 | static struct clk dsptim_ck = { |
| 349 | .name = "dsptim_ck", | 314 | .name = "dsptim_ck", |
| 315 | .ops = &clkops_dspck, | ||
| 350 | .parent = &ck_ref, | 316 | .parent = &ck_ref, |
| 351 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 352 | VIRTUAL_IO_ADDRESS, | ||
| 353 | .enable_reg = DSP_IDLECT2, | 317 | .enable_reg = DSP_IDLECT2, |
| 354 | .enable_bit = EN_DSPTIMCK, | 318 | .enable_bit = EN_DSPTIMCK, |
| 355 | .recalc = &followparent_recalc, | 319 | .recalc = &followparent_recalc, |
| 356 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 357 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 358 | }; | 320 | }; |
| 359 | 321 | ||
| 360 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | 322 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ |
| 361 | static struct arm_idlect1_clk tc_ck = { | 323 | static struct arm_idlect1_clk tc_ck = { |
| 362 | .clk = { | 324 | .clk = { |
| 363 | .name = "tc_ck", | 325 | .name = "tc_ck", |
| 326 | .ops = &clkops_null, | ||
| 364 | .parent = &ck_dpll1, | 327 | .parent = &ck_dpll1, |
| 365 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 328 | .flags = CLOCK_IDLE_CONTROL, |
| 366 | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | | ||
| 367 | RATE_CKCTL | RATE_PROPAGATES | | ||
| 368 | ALWAYS_ENABLED | CLOCK_IDLE_CONTROL, | ||
| 369 | .rate_offset = CKCTL_TCDIV_OFFSET, | 329 | .rate_offset = CKCTL_TCDIV_OFFSET, |
| 370 | .recalc = &omap1_ckctl_recalc, | 330 | .recalc = &omap1_ckctl_recalc, |
| 371 | .enable = &omap1_clk_enable_generic, | 331 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 372 | .disable = &omap1_clk_disable_generic, | 332 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 373 | }, | 333 | }, |
| 374 | .idlect_shift = 6, | 334 | .idlect_shift = 6, |
| 375 | }; | 335 | }; |
| 376 | 336 | ||
| 377 | static struct clk arminth_ck1510 = { | 337 | static struct clk arminth_ck1510 = { |
| 378 | .name = "arminth_ck", | 338 | .name = "arminth_ck", |
| 339 | .ops = &clkops_null, | ||
| 379 | .parent = &tc_ck.clk, | 340 | .parent = &tc_ck.clk, |
| 380 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | ||
| 381 | ALWAYS_ENABLED, | ||
| 382 | .recalc = &followparent_recalc, | 341 | .recalc = &followparent_recalc, |
| 383 | /* Note: On 1510 the frequency follows TC_CK | 342 | /* Note: On 1510 the frequency follows TC_CK |
| 384 | * | 343 | * |
| 385 | * 16xx version is in MPU clocks. | 344 | * 16xx version is in MPU clocks. |
| 386 | */ | 345 | */ |
| 387 | .enable = &omap1_clk_enable_generic, | ||
| 388 | .disable = &omap1_clk_disable_generic, | ||
| 389 | }; | 346 | }; |
| 390 | 347 | ||
| 391 | static struct clk tipb_ck = { | 348 | static struct clk tipb_ck = { |
| 392 | /* No-idle controlled by "tc_ck" */ | 349 | /* No-idle controlled by "tc_ck" */ |
| 393 | .name = "tipb_ck", | 350 | .name = "tipb_ck", |
| 351 | .ops = &clkops_null, | ||
| 394 | .parent = &tc_ck.clk, | 352 | .parent = &tc_ck.clk, |
| 395 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | ||
| 396 | ALWAYS_ENABLED, | ||
| 397 | .recalc = &followparent_recalc, | 353 | .recalc = &followparent_recalc, |
| 398 | .enable = &omap1_clk_enable_generic, | ||
| 399 | .disable = &omap1_clk_disable_generic, | ||
| 400 | }; | 354 | }; |
| 401 | 355 | ||
| 402 | static struct clk l3_ocpi_ck = { | 356 | static struct clk l3_ocpi_ck = { |
| 403 | /* No-idle controlled by "tc_ck" */ | 357 | /* No-idle controlled by "tc_ck" */ |
| 404 | .name = "l3_ocpi_ck", | 358 | .name = "l3_ocpi_ck", |
| 359 | .ops = &clkops_generic, | ||
| 405 | .parent = &tc_ck.clk, | 360 | .parent = &tc_ck.clk, |
| 406 | .flags = CLOCK_IN_OMAP16XX, | 361 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
| 407 | .enable_reg = (void __iomem *)ARM_IDLECT3, | ||
| 408 | .enable_bit = EN_OCPI_CK, | 362 | .enable_bit = EN_OCPI_CK, |
| 409 | .recalc = &followparent_recalc, | 363 | .recalc = &followparent_recalc, |
| 410 | .enable = &omap1_clk_enable_generic, | ||
| 411 | .disable = &omap1_clk_disable_generic, | ||
| 412 | }; | 364 | }; |
| 413 | 365 | ||
| 414 | static struct clk tc1_ck = { | 366 | static struct clk tc1_ck = { |
| 415 | .name = "tc1_ck", | 367 | .name = "tc1_ck", |
| 368 | .ops = &clkops_generic, | ||
| 416 | .parent = &tc_ck.clk, | 369 | .parent = &tc_ck.clk, |
| 417 | .flags = CLOCK_IN_OMAP16XX, | 370 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
| 418 | .enable_reg = (void __iomem *)ARM_IDLECT3, | ||
| 419 | .enable_bit = EN_TC1_CK, | 371 | .enable_bit = EN_TC1_CK, |
| 420 | .recalc = &followparent_recalc, | 372 | .recalc = &followparent_recalc, |
| 421 | .enable = &omap1_clk_enable_generic, | ||
| 422 | .disable = &omap1_clk_disable_generic, | ||
| 423 | }; | 373 | }; |
| 424 | 374 | ||
| 425 | static struct clk tc2_ck = { | 375 | static struct clk tc2_ck = { |
| 426 | .name = "tc2_ck", | 376 | .name = "tc2_ck", |
| 377 | .ops = &clkops_generic, | ||
| 427 | .parent = &tc_ck.clk, | 378 | .parent = &tc_ck.clk, |
| 428 | .flags = CLOCK_IN_OMAP16XX, | 379 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
| 429 | .enable_reg = (void __iomem *)ARM_IDLECT3, | ||
| 430 | .enable_bit = EN_TC2_CK, | 380 | .enable_bit = EN_TC2_CK, |
| 431 | .recalc = &followparent_recalc, | 381 | .recalc = &followparent_recalc, |
| 432 | .enable = &omap1_clk_enable_generic, | ||
| 433 | .disable = &omap1_clk_disable_generic, | ||
| 434 | }; | 382 | }; |
| 435 | 383 | ||
| 436 | static struct clk dma_ck = { | 384 | static struct clk dma_ck = { |
| 437 | /* No-idle controlled by "tc_ck" */ | 385 | /* No-idle controlled by "tc_ck" */ |
| 438 | .name = "dma_ck", | 386 | .name = "dma_ck", |
| 387 | .ops = &clkops_null, | ||
| 439 | .parent = &tc_ck.clk, | 388 | .parent = &tc_ck.clk, |
| 440 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 441 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, | ||
| 442 | .recalc = &followparent_recalc, | 389 | .recalc = &followparent_recalc, |
| 443 | .enable = &omap1_clk_enable_generic, | ||
| 444 | .disable = &omap1_clk_disable_generic, | ||
| 445 | }; | 390 | }; |
| 446 | 391 | ||
| 447 | static struct clk dma_lcdfree_ck = { | 392 | static struct clk dma_lcdfree_ck = { |
| 448 | .name = "dma_lcdfree_ck", | 393 | .name = "dma_lcdfree_ck", |
| 394 | .ops = &clkops_null, | ||
| 449 | .parent = &tc_ck.clk, | 395 | .parent = &tc_ck.clk, |
| 450 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 451 | .recalc = &followparent_recalc, | 396 | .recalc = &followparent_recalc, |
| 452 | .enable = &omap1_clk_enable_generic, | ||
| 453 | .disable = &omap1_clk_disable_generic, | ||
| 454 | }; | 397 | }; |
| 455 | 398 | ||
| 456 | static struct arm_idlect1_clk api_ck = { | 399 | static struct arm_idlect1_clk api_ck = { |
| 457 | .clk = { | 400 | .clk = { |
| 458 | .name = "api_ck", | 401 | .name = "api_ck", |
| 402 | .ops = &clkops_generic, | ||
| 459 | .parent = &tc_ck.clk, | 403 | .parent = &tc_ck.clk, |
| 460 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 404 | .flags = CLOCK_IDLE_CONTROL, |
| 461 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 405 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 462 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 463 | .enable_bit = EN_APICK, | 406 | .enable_bit = EN_APICK, |
| 464 | .recalc = &followparent_recalc, | 407 | .recalc = &followparent_recalc, |
| 465 | .enable = &omap1_clk_enable_generic, | ||
| 466 | .disable = &omap1_clk_disable_generic, | ||
| 467 | }, | 408 | }, |
| 468 | .idlect_shift = 8, | 409 | .idlect_shift = 8, |
| 469 | }; | 410 | }; |
| @@ -471,276 +412,238 @@ static struct arm_idlect1_clk api_ck = { | |||
| 471 | static struct arm_idlect1_clk lb_ck = { | 412 | static struct arm_idlect1_clk lb_ck = { |
| 472 | .clk = { | 413 | .clk = { |
| 473 | .name = "lb_ck", | 414 | .name = "lb_ck", |
| 415 | .ops = &clkops_generic, | ||
| 474 | .parent = &tc_ck.clk, | 416 | .parent = &tc_ck.clk, |
| 475 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 417 | .flags = CLOCK_IDLE_CONTROL, |
| 476 | CLOCK_IDLE_CONTROL, | 418 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 477 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 478 | .enable_bit = EN_LBCK, | 419 | .enable_bit = EN_LBCK, |
| 479 | .recalc = &followparent_recalc, | 420 | .recalc = &followparent_recalc, |
| 480 | .enable = &omap1_clk_enable_generic, | ||
| 481 | .disable = &omap1_clk_disable_generic, | ||
| 482 | }, | 421 | }, |
| 483 | .idlect_shift = 4, | 422 | .idlect_shift = 4, |
| 484 | }; | 423 | }; |
| 485 | 424 | ||
| 486 | static struct clk rhea1_ck = { | 425 | static struct clk rhea1_ck = { |
| 487 | .name = "rhea1_ck", | 426 | .name = "rhea1_ck", |
| 427 | .ops = &clkops_null, | ||
| 488 | .parent = &tc_ck.clk, | 428 | .parent = &tc_ck.clk, |
| 489 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 490 | .recalc = &followparent_recalc, | 429 | .recalc = &followparent_recalc, |
| 491 | .enable = &omap1_clk_enable_generic, | ||
| 492 | .disable = &omap1_clk_disable_generic, | ||
| 493 | }; | 430 | }; |
| 494 | 431 | ||
| 495 | static struct clk rhea2_ck = { | 432 | static struct clk rhea2_ck = { |
| 496 | .name = "rhea2_ck", | 433 | .name = "rhea2_ck", |
| 434 | .ops = &clkops_null, | ||
| 497 | .parent = &tc_ck.clk, | 435 | .parent = &tc_ck.clk, |
| 498 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 499 | .recalc = &followparent_recalc, | 436 | .recalc = &followparent_recalc, |
| 500 | .enable = &omap1_clk_enable_generic, | ||
| 501 | .disable = &omap1_clk_disable_generic, | ||
| 502 | }; | 437 | }; |
| 503 | 438 | ||
| 504 | static struct clk lcd_ck_16xx = { | 439 | static struct clk lcd_ck_16xx = { |
| 505 | .name = "lcd_ck", | 440 | .name = "lcd_ck", |
| 441 | .ops = &clkops_generic, | ||
| 506 | .parent = &ck_dpll1, | 442 | .parent = &ck_dpll1, |
| 507 | .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, | 443 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 508 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 509 | .enable_bit = EN_LCDCK, | 444 | .enable_bit = EN_LCDCK, |
| 510 | .rate_offset = CKCTL_LCDDIV_OFFSET, | 445 | .rate_offset = CKCTL_LCDDIV_OFFSET, |
| 511 | .recalc = &omap1_ckctl_recalc, | 446 | .recalc = &omap1_ckctl_recalc, |
| 512 | .enable = &omap1_clk_enable_generic, | 447 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 513 | .disable = &omap1_clk_disable_generic, | 448 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 514 | }; | 449 | }; |
| 515 | 450 | ||
| 516 | static struct arm_idlect1_clk lcd_ck_1510 = { | 451 | static struct arm_idlect1_clk lcd_ck_1510 = { |
| 517 | .clk = { | 452 | .clk = { |
| 518 | .name = "lcd_ck", | 453 | .name = "lcd_ck", |
| 454 | .ops = &clkops_generic, | ||
| 519 | .parent = &ck_dpll1, | 455 | .parent = &ck_dpll1, |
| 520 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 456 | .flags = CLOCK_IDLE_CONTROL, |
| 521 | RATE_CKCTL | CLOCK_IDLE_CONTROL, | 457 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 522 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 523 | .enable_bit = EN_LCDCK, | 458 | .enable_bit = EN_LCDCK, |
| 524 | .rate_offset = CKCTL_LCDDIV_OFFSET, | 459 | .rate_offset = CKCTL_LCDDIV_OFFSET, |
| 525 | .recalc = &omap1_ckctl_recalc, | 460 | .recalc = &omap1_ckctl_recalc, |
| 526 | .enable = &omap1_clk_enable_generic, | 461 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 527 | .disable = &omap1_clk_disable_generic, | 462 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 528 | }, | 463 | }, |
| 529 | .idlect_shift = 3, | 464 | .idlect_shift = 3, |
| 530 | }; | 465 | }; |
| 531 | 466 | ||
| 532 | static struct clk uart1_1510 = { | 467 | static struct clk uart1_1510 = { |
| 533 | .name = "uart1_ck", | 468 | .name = "uart1_ck", |
| 469 | .ops = &clkops_null, | ||
| 534 | /* Direct from ULPD, no real parent */ | 470 | /* Direct from ULPD, no real parent */ |
| 535 | .parent = &armper_ck.clk, | 471 | .parent = &armper_ck.clk, |
| 536 | .rate = 12000000, | 472 | .rate = 12000000, |
| 537 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 473 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 538 | ENABLE_REG_32BIT | ALWAYS_ENABLED | | 474 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 539 | CLOCK_NO_IDLE_PARENT, | ||
| 540 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 541 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | 475 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ |
| 542 | .set_rate = &omap1_set_uart_rate, | 476 | .set_rate = &omap1_set_uart_rate, |
| 543 | .recalc = &omap1_uart_recalc, | 477 | .recalc = &omap1_uart_recalc, |
| 544 | .enable = &omap1_clk_enable_generic, | ||
| 545 | .disable = &omap1_clk_disable_generic, | ||
| 546 | }; | 478 | }; |
| 547 | 479 | ||
| 548 | static struct uart_clk uart1_16xx = { | 480 | static struct uart_clk uart1_16xx = { |
| 549 | .clk = { | 481 | .clk = { |
| 550 | .name = "uart1_ck", | 482 | .name = "uart1_ck", |
| 483 | .ops = &clkops_uart, | ||
| 551 | /* Direct from ULPD, no real parent */ | 484 | /* Direct from ULPD, no real parent */ |
| 552 | .parent = &armper_ck.clk, | 485 | .parent = &armper_ck.clk, |
| 553 | .rate = 48000000, | 486 | .rate = 48000000, |
| 554 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | | 487 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
| 555 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 488 | CLOCK_NO_IDLE_PARENT, |
| 556 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | 489 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 557 | .enable_bit = 29, | 490 | .enable_bit = 29, |
| 558 | .enable = &omap1_clk_enable_uart_functional, | ||
| 559 | .disable = &omap1_clk_disable_uart_functional, | ||
| 560 | }, | 491 | }, |
| 561 | .sysc_addr = 0xfffb0054, | 492 | .sysc_addr = 0xfffb0054, |
| 562 | }; | 493 | }; |
| 563 | 494 | ||
| 564 | static struct clk uart2_ck = { | 495 | static struct clk uart2_ck = { |
| 565 | .name = "uart2_ck", | 496 | .name = "uart2_ck", |
| 497 | .ops = &clkops_null, | ||
| 566 | /* Direct from ULPD, no real parent */ | 498 | /* Direct from ULPD, no real parent */ |
| 567 | .parent = &armper_ck.clk, | 499 | .parent = &armper_ck.clk, |
| 568 | .rate = 12000000, | 500 | .rate = 12000000, |
| 569 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 501 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 570 | CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | | 502 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 571 | ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, | ||
| 572 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 573 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | 503 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ |
| 574 | .set_rate = &omap1_set_uart_rate, | 504 | .set_rate = &omap1_set_uart_rate, |
| 575 | .recalc = &omap1_uart_recalc, | 505 | .recalc = &omap1_uart_recalc, |
| 576 | .enable = &omap1_clk_enable_generic, | ||
| 577 | .disable = &omap1_clk_disable_generic, | ||
| 578 | }; | 506 | }; |
| 579 | 507 | ||
| 580 | static struct clk uart3_1510 = { | 508 | static struct clk uart3_1510 = { |
| 581 | .name = "uart3_ck", | 509 | .name = "uart3_ck", |
| 510 | .ops = &clkops_null, | ||
| 582 | /* Direct from ULPD, no real parent */ | 511 | /* Direct from ULPD, no real parent */ |
| 583 | .parent = &armper_ck.clk, | 512 | .parent = &armper_ck.clk, |
| 584 | .rate = 12000000, | 513 | .rate = 12000000, |
| 585 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 514 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 586 | ENABLE_REG_32BIT | ALWAYS_ENABLED | | 515 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 587 | CLOCK_NO_IDLE_PARENT, | ||
| 588 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 589 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | 516 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ |
| 590 | .set_rate = &omap1_set_uart_rate, | 517 | .set_rate = &omap1_set_uart_rate, |
| 591 | .recalc = &omap1_uart_recalc, | 518 | .recalc = &omap1_uart_recalc, |
| 592 | .enable = &omap1_clk_enable_generic, | ||
| 593 | .disable = &omap1_clk_disable_generic, | ||
| 594 | }; | 519 | }; |
| 595 | 520 | ||
| 596 | static struct uart_clk uart3_16xx = { | 521 | static struct uart_clk uart3_16xx = { |
| 597 | .clk = { | 522 | .clk = { |
| 598 | .name = "uart3_ck", | 523 | .name = "uart3_ck", |
| 524 | .ops = &clkops_uart, | ||
| 599 | /* Direct from ULPD, no real parent */ | 525 | /* Direct from ULPD, no real parent */ |
| 600 | .parent = &armper_ck.clk, | 526 | .parent = &armper_ck.clk, |
| 601 | .rate = 48000000, | 527 | .rate = 48000000, |
| 602 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | | 528 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
| 603 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 529 | CLOCK_NO_IDLE_PARENT, |
| 604 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | 530 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 605 | .enable_bit = 31, | 531 | .enable_bit = 31, |
| 606 | .enable = &omap1_clk_enable_uart_functional, | ||
| 607 | .disable = &omap1_clk_disable_uart_functional, | ||
| 608 | }, | 532 | }, |
| 609 | .sysc_addr = 0xfffb9854, | 533 | .sysc_addr = 0xfffb9854, |
| 610 | }; | 534 | }; |
| 611 | 535 | ||
| 612 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | 536 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ |
| 613 | .name = "usb_clko", | 537 | .name = "usb_clko", |
| 538 | .ops = &clkops_generic, | ||
| 614 | /* Direct from ULPD, no parent */ | 539 | /* Direct from ULPD, no parent */ |
| 615 | .rate = 6000000, | 540 | .rate = 6000000, |
| 616 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 541 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
| 617 | CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT, | 542 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
| 618 | .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, | ||
| 619 | .enable_bit = USB_MCLK_EN_BIT, | 543 | .enable_bit = USB_MCLK_EN_BIT, |
| 620 | .enable = &omap1_clk_enable_generic, | ||
| 621 | .disable = &omap1_clk_disable_generic, | ||
| 622 | }; | 544 | }; |
| 623 | 545 | ||
| 624 | static struct clk usb_hhc_ck1510 = { | 546 | static struct clk usb_hhc_ck1510 = { |
| 625 | .name = "usb_hhc_ck", | 547 | .name = "usb_hhc_ck", |
| 548 | .ops = &clkops_generic, | ||
| 626 | /* Direct from ULPD, no parent */ | 549 | /* Direct from ULPD, no parent */ |
| 627 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | 550 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
| 628 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 551 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
| 629 | RATE_FIXED | ENABLE_REG_32BIT, | 552 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 630 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 631 | .enable_bit = USB_HOST_HHC_UHOST_EN, | 553 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
| 632 | .enable = &omap1_clk_enable_generic, | ||
| 633 | .disable = &omap1_clk_disable_generic, | ||
| 634 | }; | 554 | }; |
| 635 | 555 | ||
| 636 | static struct clk usb_hhc_ck16xx = { | 556 | static struct clk usb_hhc_ck16xx = { |
| 637 | .name = "usb_hhc_ck", | 557 | .name = "usb_hhc_ck", |
| 558 | .ops = &clkops_generic, | ||
| 638 | /* Direct from ULPD, no parent */ | 559 | /* Direct from ULPD, no parent */ |
| 639 | .rate = 48000000, | 560 | .rate = 48000000, |
| 640 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | 561 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
| 641 | .flags = CLOCK_IN_OMAP16XX | | 562 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
| 642 | RATE_FIXED | ENABLE_REG_32BIT, | 563 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
| 643 | .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, | ||
| 644 | .enable_bit = 8 /* UHOST_EN */, | 564 | .enable_bit = 8 /* UHOST_EN */, |
| 645 | .enable = &omap1_clk_enable_generic, | ||
| 646 | .disable = &omap1_clk_disable_generic, | ||
| 647 | }; | 565 | }; |
| 648 | 566 | ||
| 649 | static struct clk usb_dc_ck = { | 567 | static struct clk usb_dc_ck = { |
| 650 | .name = "usb_dc_ck", | 568 | .name = "usb_dc_ck", |
| 569 | .ops = &clkops_generic, | ||
| 651 | /* Direct from ULPD, no parent */ | 570 | /* Direct from ULPD, no parent */ |
| 652 | .rate = 48000000, | 571 | .rate = 48000000, |
| 653 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, | 572 | .flags = RATE_FIXED, |
| 654 | .enable_reg = (void __iomem *)SOFT_REQ_REG, | 573 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 655 | .enable_bit = 4, | 574 | .enable_bit = 4, |
| 656 | .enable = &omap1_clk_enable_generic, | ||
| 657 | .disable = &omap1_clk_disable_generic, | ||
| 658 | }; | 575 | }; |
| 659 | 576 | ||
| 660 | static struct clk mclk_1510 = { | 577 | static struct clk mclk_1510 = { |
| 661 | .name = "mclk", | 578 | .name = "mclk", |
| 579 | .ops = &clkops_generic, | ||
| 662 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 580 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 663 | .rate = 12000000, | 581 | .rate = 12000000, |
| 664 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, | 582 | .flags = RATE_FIXED, |
| 665 | .enable_reg = (void __iomem *)SOFT_REQ_REG, | 583 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 666 | .enable_bit = 6, | 584 | .enable_bit = 6, |
| 667 | .enable = &omap1_clk_enable_generic, | ||
| 668 | .disable = &omap1_clk_disable_generic, | ||
| 669 | }; | 585 | }; |
| 670 | 586 | ||
| 671 | static struct clk mclk_16xx = { | 587 | static struct clk mclk_16xx = { |
| 672 | .name = "mclk", | 588 | .name = "mclk", |
| 589 | .ops = &clkops_generic, | ||
| 673 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 590 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 674 | .flags = CLOCK_IN_OMAP16XX, | 591 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), |
| 675 | .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, | ||
| 676 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | 592 | .enable_bit = COM_ULPD_PLL_CLK_REQ, |
| 677 | .set_rate = &omap1_set_ext_clk_rate, | 593 | .set_rate = &omap1_set_ext_clk_rate, |
| 678 | .round_rate = &omap1_round_ext_clk_rate, | 594 | .round_rate = &omap1_round_ext_clk_rate, |
| 679 | .init = &omap1_init_ext_clk, | 595 | .init = &omap1_init_ext_clk, |
| 680 | .enable = &omap1_clk_enable_generic, | ||
| 681 | .disable = &omap1_clk_disable_generic, | ||
| 682 | }; | 596 | }; |
| 683 | 597 | ||
| 684 | static struct clk bclk_1510 = { | 598 | static struct clk bclk_1510 = { |
| 685 | .name = "bclk", | 599 | .name = "bclk", |
| 600 | .ops = &clkops_generic, | ||
| 686 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 601 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 687 | .rate = 12000000, | 602 | .rate = 12000000, |
| 688 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, | 603 | .flags = RATE_FIXED, |
| 689 | .enable = &omap1_clk_enable_generic, | ||
| 690 | .disable = &omap1_clk_disable_generic, | ||
| 691 | }; | 604 | }; |
| 692 | 605 | ||
| 693 | static struct clk bclk_16xx = { | 606 | static struct clk bclk_16xx = { |
| 694 | .name = "bclk", | 607 | .name = "bclk", |
| 608 | .ops = &clkops_generic, | ||
| 695 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 609 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 696 | .flags = CLOCK_IN_OMAP16XX, | 610 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), |
| 697 | .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, | ||
| 698 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | 611 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, |
| 699 | .set_rate = &omap1_set_ext_clk_rate, | 612 | .set_rate = &omap1_set_ext_clk_rate, |
| 700 | .round_rate = &omap1_round_ext_clk_rate, | 613 | .round_rate = &omap1_round_ext_clk_rate, |
| 701 | .init = &omap1_init_ext_clk, | 614 | .init = &omap1_init_ext_clk, |
| 702 | .enable = &omap1_clk_enable_generic, | ||
| 703 | .disable = &omap1_clk_disable_generic, | ||
| 704 | }; | 615 | }; |
| 705 | 616 | ||
| 706 | static struct clk mmc1_ck = { | 617 | static struct clk mmc1_ck = { |
| 707 | .name = "mmc_ck", | 618 | .name = "mmc_ck", |
| 619 | .ops = &clkops_generic, | ||
| 708 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 620 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 709 | .parent = &armper_ck.clk, | 621 | .parent = &armper_ck.clk, |
| 710 | .rate = 48000000, | 622 | .rate = 48000000, |
| 711 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 623 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 712 | CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT | | 624 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 713 | CLOCK_NO_IDLE_PARENT, | ||
| 714 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 715 | .enable_bit = 23, | 625 | .enable_bit = 23, |
| 716 | .enable = &omap1_clk_enable_generic, | ||
| 717 | .disable = &omap1_clk_disable_generic, | ||
| 718 | }; | 626 | }; |
| 719 | 627 | ||
| 720 | static struct clk mmc2_ck = { | 628 | static struct clk mmc2_ck = { |
| 721 | .name = "mmc_ck", | 629 | .name = "mmc_ck", |
| 722 | .id = 1, | 630 | .id = 1, |
| 631 | .ops = &clkops_generic, | ||
| 723 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 632 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 724 | .parent = &armper_ck.clk, | 633 | .parent = &armper_ck.clk, |
| 725 | .rate = 48000000, | 634 | .rate = 48000000, |
| 726 | .flags = CLOCK_IN_OMAP16XX | | 635 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 727 | RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 636 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 728 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 729 | .enable_bit = 20, | 637 | .enable_bit = 20, |
| 730 | .enable = &omap1_clk_enable_generic, | ||
| 731 | .disable = &omap1_clk_disable_generic, | ||
| 732 | }; | 638 | }; |
| 733 | 639 | ||
| 734 | static struct clk virtual_ck_mpu = { | 640 | static struct clk virtual_ck_mpu = { |
| 735 | .name = "mpu", | 641 | .name = "mpu", |
| 736 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 642 | .ops = &clkops_null, |
| 737 | CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED, | ||
| 738 | .parent = &arm_ck, /* Is smarter alias for */ | 643 | .parent = &arm_ck, /* Is smarter alias for */ |
| 739 | .recalc = &followparent_recalc, | 644 | .recalc = &followparent_recalc, |
| 740 | .set_rate = &omap1_select_table_rate, | 645 | .set_rate = &omap1_select_table_rate, |
| 741 | .round_rate = &omap1_round_to_table_rate, | 646 | .round_rate = &omap1_round_to_table_rate, |
| 742 | .enable = &omap1_clk_enable_generic, | ||
| 743 | .disable = &omap1_clk_disable_generic, | ||
| 744 | }; | 647 | }; |
| 745 | 648 | ||
| 746 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | 649 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK |
| @@ -748,78 +651,19 @@ remains active during MPU idle whenever this is enabled */ | |||
| 748 | static struct clk i2c_fck = { | 651 | static struct clk i2c_fck = { |
| 749 | .name = "i2c_fck", | 652 | .name = "i2c_fck", |
| 750 | .id = 1, | 653 | .id = 1, |
| 751 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 654 | .ops = &clkops_null, |
| 752 | VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | | 655 | .flags = CLOCK_NO_IDLE_PARENT, |
| 753 | ALWAYS_ENABLED, | ||
| 754 | .parent = &armxor_ck.clk, | 656 | .parent = &armxor_ck.clk, |
| 755 | .recalc = &followparent_recalc, | 657 | .recalc = &followparent_recalc, |
| 756 | .enable = &omap1_clk_enable_generic, | ||
| 757 | .disable = &omap1_clk_disable_generic, | ||
| 758 | }; | 658 | }; |
| 759 | 659 | ||
| 760 | static struct clk i2c_ick = { | 660 | static struct clk i2c_ick = { |
| 761 | .name = "i2c_ick", | 661 | .name = "i2c_ick", |
| 762 | .id = 1, | 662 | .id = 1, |
| 763 | .flags = CLOCK_IN_OMAP16XX | | 663 | .ops = &clkops_null, |
| 764 | VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | | 664 | .flags = CLOCK_NO_IDLE_PARENT, |
| 765 | ALWAYS_ENABLED, | ||
| 766 | .parent = &armper_ck.clk, | 665 | .parent = &armper_ck.clk, |
| 767 | .recalc = &followparent_recalc, | 666 | .recalc = &followparent_recalc, |
| 768 | .enable = &omap1_clk_enable_generic, | ||
| 769 | .disable = &omap1_clk_disable_generic, | ||
| 770 | }; | ||
| 771 | |||
| 772 | static struct clk * onchip_clks[] = { | ||
| 773 | /* non-ULPD clocks */ | ||
| 774 | &ck_ref, | ||
| 775 | &ck_dpll1, | ||
| 776 | /* CK_GEN1 clocks */ | ||
| 777 | &ck_dpll1out.clk, | ||
| 778 | &sossi_ck, | ||
| 779 | &arm_ck, | ||
| 780 | &armper_ck.clk, | ||
| 781 | &arm_gpio_ck, | ||
| 782 | &armxor_ck.clk, | ||
| 783 | &armtim_ck.clk, | ||
| 784 | &armwdt_ck.clk, | ||
| 785 | &arminth_ck1510, &arminth_ck16xx, | ||
| 786 | /* CK_GEN2 clocks */ | ||
| 787 | &dsp_ck, | ||
| 788 | &dspmmu_ck, | ||
| 789 | &dspper_ck, | ||
| 790 | &dspxor_ck, | ||
| 791 | &dsptim_ck, | ||
| 792 | /* CK_GEN3 clocks */ | ||
| 793 | &tc_ck.clk, | ||
| 794 | &tipb_ck, | ||
| 795 | &l3_ocpi_ck, | ||
| 796 | &tc1_ck, | ||
| 797 | &tc2_ck, | ||
| 798 | &dma_ck, | ||
| 799 | &dma_lcdfree_ck, | ||
| 800 | &api_ck.clk, | ||
| 801 | &lb_ck.clk, | ||
| 802 | &rhea1_ck, | ||
| 803 | &rhea2_ck, | ||
| 804 | &lcd_ck_16xx, | ||
| 805 | &lcd_ck_1510.clk, | ||
| 806 | /* ULPD clocks */ | ||
| 807 | &uart1_1510, | ||
| 808 | &uart1_16xx.clk, | ||
| 809 | &uart2_ck, | ||
| 810 | &uart3_1510, | ||
| 811 | &uart3_16xx.clk, | ||
| 812 | &usb_clko, | ||
| 813 | &usb_hhc_ck1510, &usb_hhc_ck16xx, | ||
| 814 | &usb_dc_ck, | ||
| 815 | &mclk_1510, &mclk_16xx, | ||
| 816 | &bclk_1510, &bclk_16xx, | ||
| 817 | &mmc1_ck, | ||
| 818 | &mmc2_ck, | ||
| 819 | /* Virtual clocks */ | ||
| 820 | &virtual_ck_mpu, | ||
| 821 | &i2c_fck, | ||
| 822 | &i2c_ick, | ||
| 823 | }; | 667 | }; |
| 824 | 668 | ||
| 825 | #endif | 669 | #endif |
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index ba5d7c08dc17..bbbaeb0abcd3 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c | |||
| @@ -86,7 +86,7 @@ static struct resource mbox_resources[] = { | |||
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | static struct platform_device mbox_device = { | 88 | static struct platform_device mbox_device = { |
| 89 | .name = "mailbox", | 89 | .name = "omap1-mailbox", |
| 90 | .id = -1, | 90 | .id = -1, |
| 91 | .num_resources = ARRAY_SIZE(mbox_resources), | 91 | .num_resources = ARRAY_SIZE(mbox_resources), |
| 92 | .resource = mbox_resources, | 92 | .resource = mbox_resources, |
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index 89bb8756f450..4ef26faf083e 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c | |||
| @@ -38,6 +38,7 @@ static struct omap_id omap_ids[] __initdata = { | |||
| 38 | { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, | 38 | { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, |
| 39 | { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, | 39 | { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, |
| 40 | { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, | 40 | { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, |
| 41 | { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320500, .type = 0x08500000}, | ||
| 41 | { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, | 42 | { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, |
| 42 | { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, | 43 | { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, |
| 43 | { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, | 44 | { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, |
| @@ -77,7 +78,7 @@ static u16 __init omap_get_jtag_id(void) | |||
| 77 | prod_id = omap_readl(OMAP_PRODUCTION_ID_1); | 78 | prod_id = omap_readl(OMAP_PRODUCTION_ID_1); |
| 78 | omap_id = omap_readl(OMAP32_ID_1); | 79 | omap_id = omap_readl(OMAP32_ID_1); |
| 79 | 80 | ||
| 80 | /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */ | 81 | /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730/850 */ |
| 81 | if (((prod_id >> 20) == 0) || (prod_id == omap_id)) | 82 | if (((prod_id >> 20) == 0) || (prod_id == omap_id)) |
| 82 | prod_id = 0; | 83 | prod_id = 0; |
| 83 | else | 84 | else |
| @@ -178,6 +179,7 @@ void __init omap_check_revision(void) | |||
| 178 | 179 | ||
| 179 | switch (cpu_type) { | 180 | switch (cpu_type) { |
| 180 | case 0x07: | 181 | case 0x07: |
| 182 | case 0x08: | ||
| 181 | omap_revision |= 0x07; | 183 | omap_revision |= 0x07; |
| 182 | break; | 184 | break; |
| 183 | case 0x03: | 185 | case 0x03: |
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 4c3e582f3d3c..3afe540149f7 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c | |||
| @@ -52,6 +52,22 @@ static struct map_desc omap730_io_desc[] __initdata = { | |||
| 52 | }; | 52 | }; |
| 53 | #endif | 53 | #endif |
| 54 | 54 | ||
| 55 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 56 | static struct map_desc omap850_io_desc[] __initdata = { | ||
| 57 | { | ||
| 58 | .virtual = OMAP850_DSP_BASE, | ||
| 59 | .pfn = __phys_to_pfn(OMAP850_DSP_START), | ||
| 60 | .length = OMAP850_DSP_SIZE, | ||
| 61 | .type = MT_DEVICE | ||
| 62 | }, { | ||
| 63 | .virtual = OMAP850_DSPREG_BASE, | ||
| 64 | .pfn = __phys_to_pfn(OMAP850_DSPREG_START), | ||
| 65 | .length = OMAP850_DSPREG_SIZE, | ||
| 66 | .type = MT_DEVICE | ||
| 67 | } | ||
| 68 | }; | ||
| 69 | #endif | ||
| 70 | |||
| 55 | #ifdef CONFIG_ARCH_OMAP15XX | 71 | #ifdef CONFIG_ARCH_OMAP15XX |
| 56 | static struct map_desc omap1510_io_desc[] __initdata = { | 72 | static struct map_desc omap1510_io_desc[] __initdata = { |
| 57 | { | 73 | { |
| @@ -109,6 +125,13 @@ void __init omap1_map_common_io(void) | |||
| 109 | iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); | 125 | iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); |
| 110 | } | 126 | } |
| 111 | #endif | 127 | #endif |
| 128 | |||
| 129 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 130 | if (cpu_is_omap850()) { | ||
| 131 | iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc)); | ||
| 132 | } | ||
| 133 | #endif | ||
| 134 | |||
| 112 | #ifdef CONFIG_ARCH_OMAP15XX | 135 | #ifdef CONFIG_ARCH_OMAP15XX |
| 113 | if (cpu_is_omap15xx()) { | 136 | if (cpu_is_omap15xx()) { |
| 114 | iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); | 137 | iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); |
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 9ad5197075ff..de03c8448994 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
| @@ -145,6 +145,14 @@ static struct omap_irq_bank omap730_irq_banks[] = { | |||
| 145 | }; | 145 | }; |
| 146 | #endif | 146 | #endif |
| 147 | 147 | ||
| 148 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 149 | static struct omap_irq_bank omap850_irq_banks[] = { | ||
| 150 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, | ||
| 151 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, | ||
| 152 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, | ||
| 153 | }; | ||
| 154 | #endif | ||
| 155 | |||
| 148 | #ifdef CONFIG_ARCH_OMAP15XX | 156 | #ifdef CONFIG_ARCH_OMAP15XX |
| 149 | static struct omap_irq_bank omap1510_irq_banks[] = { | 157 | static struct omap_irq_bank omap1510_irq_banks[] = { |
| 150 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, | 158 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, |
| @@ -184,6 +192,12 @@ void __init omap_init_irq(void) | |||
| 184 | irq_bank_count = ARRAY_SIZE(omap730_irq_banks); | 192 | irq_bank_count = ARRAY_SIZE(omap730_irq_banks); |
| 185 | } | 193 | } |
| 186 | #endif | 194 | #endif |
| 195 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 196 | if (cpu_is_omap850()) { | ||
| 197 | irq_banks = omap850_irq_banks; | ||
| 198 | irq_bank_count = ARRAY_SIZE(omap850_irq_banks); | ||
| 199 | } | ||
| 200 | #endif | ||
| 187 | #ifdef CONFIG_ARCH_OMAP15XX | 201 | #ifdef CONFIG_ARCH_OMAP15XX |
| 188 | if (cpu_is_omap1510()) { | 202 | if (cpu_is_omap1510()) { |
| 189 | irq_banks = omap1510_irq_banks; | 203 | irq_banks = omap1510_irq_banks; |
| @@ -214,9 +228,8 @@ void __init omap_init_irq(void) | |||
| 214 | irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); | 228 | irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); |
| 215 | 229 | ||
| 216 | /* Enable interrupts in global mask */ | 230 | /* Enable interrupts in global mask */ |
| 217 | if (cpu_is_omap730()) { | 231 | if (cpu_is_omap7xx()) |
| 218 | irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); | 232 | irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); |
| 219 | } | ||
| 220 | 233 | ||
| 221 | /* Install the interrupt handlers for each bank */ | 234 | /* Install the interrupt handlers for each bank */ |
| 222 | for (i = 0; i < irq_bank_count; i++) { | 235 | for (i = 0; i < irq_bank_count; i++) { |
| @@ -236,6 +249,8 @@ void __init omap_init_irq(void) | |||
| 236 | 249 | ||
| 237 | if (cpu_is_omap730()) | 250 | if (cpu_is_omap730()) |
| 238 | omap_unmask_irq(INT_730_IH2_IRQ); | 251 | omap_unmask_irq(INT_730_IH2_IRQ); |
| 252 | else if (cpu_is_omap850()) | ||
| 253 | omap_unmask_irq(INT_850_IH2_IRQ); | ||
| 239 | else if (cpu_is_omap15xx()) | 254 | else if (cpu_is_omap15xx()) |
| 240 | omap_unmask_irq(INT_1510_IH2_IRQ); | 255 | omap_unmask_irq(INT_1510_IH2_IRQ); |
| 241 | else if (cpu_is_omap16xx()) | 256 | else if (cpu_is_omap16xx()) |
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 59abbf331a96..0af4d6c85b47 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Mailbox reservation modules for DSP | 2 | * Mailbox reservation modules for DSP |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 Nokia Corporation | 4 | * Copyright (C) 2006-2009 Nokia Corporation |
| 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| 6 | * | 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public | 7 | * This file is subject to the terms and conditions of the GNU General Public |
| @@ -27,7 +27,7 @@ | |||
| 27 | #define MAILBOX_DSP2ARM1_Flag 0x1c | 27 | #define MAILBOX_DSP2ARM1_Flag 0x1c |
| 28 | #define MAILBOX_DSP2ARM2_Flag 0x20 | 28 | #define MAILBOX_DSP2ARM2_Flag 0x20 |
| 29 | 29 | ||
| 30 | unsigned long mbox_base; | 30 | static void __iomem *mbox_base; |
| 31 | 31 | ||
| 32 | struct omap_mbox1_fifo { | 32 | struct omap_mbox1_fifo { |
| 33 | unsigned long cmd; | 33 | unsigned long cmd; |
| @@ -40,14 +40,14 @@ struct omap_mbox1_priv { | |||
| 40 | struct omap_mbox1_fifo rx_fifo; | 40 | struct omap_mbox1_fifo rx_fifo; |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | static inline int mbox_read_reg(unsigned int reg) | 43 | static inline int mbox_read_reg(size_t ofs) |
| 44 | { | 44 | { |
| 45 | return __raw_readw(mbox_base + reg); | 45 | return __raw_readw(mbox_base + ofs); |
| 46 | } | 46 | } |
| 47 | 47 | ||
| 48 | static inline void mbox_write_reg(unsigned int val, unsigned int reg) | 48 | static inline void mbox_write_reg(u32 val, size_t ofs) |
| 49 | { | 49 | { |
| 50 | __raw_writew(val, mbox_base + reg); | 50 | __raw_writew(val, mbox_base + ofs); |
| 51 | } | 51 | } |
| 52 | 52 | ||
| 53 | /* msg */ | 53 | /* msg */ |
| @@ -143,7 +143,7 @@ struct omap_mbox mbox_dsp_info = { | |||
| 143 | }; | 143 | }; |
| 144 | EXPORT_SYMBOL(mbox_dsp_info); | 144 | EXPORT_SYMBOL(mbox_dsp_info); |
| 145 | 145 | ||
| 146 | static int __init omap1_mbox_probe(struct platform_device *pdev) | 146 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) |
| 147 | { | 147 | { |
| 148 | struct resource *res; | 148 | struct resource *res; |
| 149 | int ret = 0; | 149 | int ret = 0; |
| @@ -170,12 +170,10 @@ static int __init omap1_mbox_probe(struct platform_device *pdev) | |||
| 170 | } | 170 | } |
| 171 | mbox_dsp_info.irq = res->start; | 171 | mbox_dsp_info.irq = res->start; |
| 172 | 172 | ||
| 173 | ret = omap_mbox_register(&mbox_dsp_info); | 173 | return omap_mbox_register(&pdev->dev, &mbox_dsp_info); |
| 174 | |||
| 175 | return ret; | ||
| 176 | } | 174 | } |
| 177 | 175 | ||
| 178 | static int omap1_mbox_remove(struct platform_device *pdev) | 176 | static int __devexit omap1_mbox_remove(struct platform_device *pdev) |
| 179 | { | 177 | { |
| 180 | omap_mbox_unregister(&mbox_dsp_info); | 178 | omap_mbox_unregister(&mbox_dsp_info); |
| 181 | 179 | ||
| @@ -184,9 +182,9 @@ static int omap1_mbox_remove(struct platform_device *pdev) | |||
| 184 | 182 | ||
| 185 | static struct platform_driver omap1_mbox_driver = { | 183 | static struct platform_driver omap1_mbox_driver = { |
| 186 | .probe = omap1_mbox_probe, | 184 | .probe = omap1_mbox_probe, |
| 187 | .remove = omap1_mbox_remove, | 185 | .remove = __devexit_p(omap1_mbox_remove), |
| 188 | .driver = { | 186 | .driver = { |
| 189 | .name = "mailbox", | 187 | .name = "omap1-mailbox", |
| 190 | }, | 188 | }, |
| 191 | }; | 189 | }; |
| 192 | 190 | ||
| @@ -203,4 +201,7 @@ static void __exit omap1_mbox_exit(void) | |||
| 203 | module_init(omap1_mbox_init); | 201 | module_init(omap1_mbox_init); |
| 204 | module_exit(omap1_mbox_exit); | 202 | module_exit(omap1_mbox_exit); |
| 205 | 203 | ||
| 206 | MODULE_LICENSE("GPL"); | 204 | MODULE_LICENSE("GPL v2"); |
| 205 | MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions"); | ||
| 206 | MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>); | ||
| 207 | MODULE_ALIAS("platform:omap1-mailbox"); | ||
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 575ba31295cf..d040c3f1027f 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #define DPS_RSTCT2_PER_EN (1 << 0) | 28 | #define DPS_RSTCT2_PER_EN (1 << 0) |
| 29 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) | 29 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) |
| 30 | 30 | ||
| 31 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | 31 | static int dsp_use; |
| 32 | const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" }; | 32 | static struct clk *api_clk; |
| 33 | #endif | 33 | static struct clk *dsp_clk; |
| 34 | 34 | ||
| 35 | static void omap1_mcbsp_request(unsigned int id) | 35 | static void omap1_mcbsp_request(unsigned int id) |
| 36 | { | 36 | { |
| @@ -39,20 +39,40 @@ static void omap1_mcbsp_request(unsigned int id) | |||
| 39 | * are DSP public peripherals. | 39 | * are DSP public peripherals. |
| 40 | */ | 40 | */ |
| 41 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { | 41 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { |
| 42 | omap_dsp_request_mem(); | 42 | if (dsp_use++ == 0) { |
| 43 | /* | 43 | api_clk = clk_get(NULL, "api_clk"); |
| 44 | * DSP external peripheral reset | 44 | dsp_clk = clk_get(NULL, "dsp_clk"); |
| 45 | * FIXME: This should be moved to dsp code | 45 | if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) { |
| 46 | */ | 46 | clk_enable(api_clk); |
| 47 | __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN | | 47 | clk_enable(dsp_clk); |
| 48 | DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2); | 48 | |
| 49 | omap_dsp_request_mem(); | ||
| 50 | /* | ||
| 51 | * DSP external peripheral reset | ||
| 52 | * FIXME: This should be moved to dsp code | ||
| 53 | */ | ||
| 54 | __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN | | ||
| 55 | DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2); | ||
| 56 | } | ||
| 57 | } | ||
| 49 | } | 58 | } |
| 50 | } | 59 | } |
| 51 | 60 | ||
| 52 | static void omap1_mcbsp_free(unsigned int id) | 61 | static void omap1_mcbsp_free(unsigned int id) |
| 53 | { | 62 | { |
| 54 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) | 63 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { |
| 55 | omap_dsp_release_mem(); | 64 | if (--dsp_use == 0) { |
| 65 | omap_dsp_release_mem(); | ||
| 66 | if (!IS_ERR(api_clk)) { | ||
| 67 | clk_disable(api_clk); | ||
| 68 | clk_put(api_clk); | ||
| 69 | } | ||
| 70 | if (!IS_ERR(dsp_clk)) { | ||
| 71 | clk_disable(dsp_clk); | ||
| 72 | clk_put(dsp_clk); | ||
| 73 | } | ||
| 74 | } | ||
| 75 | } | ||
| 56 | } | 76 | } |
| 57 | 77 | ||
| 58 | static struct omap_mcbsp_ops omap1_mcbsp_ops = { | 78 | static struct omap_mcbsp_ops omap1_mcbsp_ops = { |
| @@ -94,8 +114,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { | |||
| 94 | .rx_irq = INT_McBSP1RX, | 114 | .rx_irq = INT_McBSP1RX, |
| 95 | .tx_irq = INT_McBSP1TX, | 115 | .tx_irq = INT_McBSP1TX, |
| 96 | .ops = &omap1_mcbsp_ops, | 116 | .ops = &omap1_mcbsp_ops, |
| 97 | .clk_names = clk_names, | ||
| 98 | .num_clks = 3, | ||
| 99 | }, | 117 | }, |
| 100 | { | 118 | { |
| 101 | .phys_base = OMAP1510_MCBSP2_BASE, | 119 | .phys_base = OMAP1510_MCBSP2_BASE, |
| @@ -112,8 +130,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { | |||
| 112 | .rx_irq = INT_McBSP3RX, | 130 | .rx_irq = INT_McBSP3RX, |
| 113 | .tx_irq = INT_McBSP3TX, | 131 | .tx_irq = INT_McBSP3TX, |
| 114 | .ops = &omap1_mcbsp_ops, | 132 | .ops = &omap1_mcbsp_ops, |
| 115 | .clk_names = clk_names, | ||
| 116 | .num_clks = 3, | ||
| 117 | }, | 133 | }, |
| 118 | }; | 134 | }; |
| 119 | #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) | 135 | #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) |
| @@ -131,8 +147,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { | |||
| 131 | .rx_irq = INT_McBSP1RX, | 147 | .rx_irq = INT_McBSP1RX, |
| 132 | .tx_irq = INT_McBSP1TX, | 148 | .tx_irq = INT_McBSP1TX, |
| 133 | .ops = &omap1_mcbsp_ops, | 149 | .ops = &omap1_mcbsp_ops, |
| 134 | .clk_names = clk_names, | ||
| 135 | .num_clks = 3, | ||
| 136 | }, | 150 | }, |
| 137 | { | 151 | { |
| 138 | .phys_base = OMAP1610_MCBSP2_BASE, | 152 | .phys_base = OMAP1610_MCBSP2_BASE, |
| @@ -149,8 +163,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { | |||
| 149 | .rx_irq = INT_McBSP3RX, | 163 | .rx_irq = INT_McBSP3RX, |
| 150 | .tx_irq = INT_McBSP3TX, | 164 | .tx_irq = INT_McBSP3TX, |
| 151 | .ops = &omap1_mcbsp_ops, | 165 | .ops = &omap1_mcbsp_ops, |
| 152 | .clk_names = clk_names, | ||
| 153 | .num_clks = 3, | ||
| 154 | }, | 166 | }, |
| 155 | }; | 167 | }; |
| 156 | #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) | 168 | #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) |
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 062c905c2ba6..721e0d9d8b1d 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c | |||
| @@ -58,6 +58,25 @@ MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) | |||
| 58 | #define OMAP730_PINS_SZ 0 | 58 | #define OMAP730_PINS_SZ 0 |
| 59 | #endif /* CONFIG_ARCH_OMAP730 */ | 59 | #endif /* CONFIG_ARCH_OMAP730 */ |
| 60 | 60 | ||
| 61 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 62 | struct pin_config __initdata_or_module omap850_pins[] = { | ||
| 63 | MUX_CFG_850("E2_850_KBR0", 12, 21, 0, 20, 1, 0) | ||
| 64 | MUX_CFG_850("J7_850_KBR1", 12, 25, 0, 24, 1, 0) | ||
| 65 | MUX_CFG_850("E1_850_KBR2", 12, 29, 0, 28, 1, 0) | ||
| 66 | MUX_CFG_850("F3_850_KBR3", 13, 1, 0, 0, 1, 0) | ||
| 67 | MUX_CFG_850("D2_850_KBR4", 13, 5, 0, 4, 1, 0) | ||
| 68 | MUX_CFG_850("C2_850_KBC0", 13, 9, 0, 8, 1, 0) | ||
| 69 | MUX_CFG_850("D3_850_KBC1", 13, 13, 0, 12, 1, 0) | ||
| 70 | MUX_CFG_850("E4_850_KBC2", 13, 17, 0, 16, 1, 0) | ||
| 71 | MUX_CFG_850("F4_850_KBC3", 13, 21, 0, 20, 1, 0) | ||
| 72 | MUX_CFG_850("E3_850_KBC4", 13, 25, 0, 24, 1, 0) | ||
| 73 | |||
| 74 | MUX_CFG_850("AA17_850_USB_DM", 2, 21, 0, 20, 0, 0) | ||
| 75 | MUX_CFG_850("W16_850_USB_PU_EN", 2, 25, 0, 24, 0, 0) | ||
| 76 | MUX_CFG_850("W17_850_USB_VBUSI", 2, 29, 0, 28, 0, 0) | ||
| 77 | }; | ||
| 78 | #endif | ||
| 79 | |||
| 61 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | 80 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) |
| 62 | static struct pin_config __initdata_or_module omap1xxx_pins[] = { | 81 | static struct pin_config __initdata_or_module omap1xxx_pins[] = { |
| 63 | /* | 82 | /* |
| @@ -419,6 +438,11 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) | |||
| 419 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | 438 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", |
| 420 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); | 439 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); |
| 421 | } | 440 | } |
| 441 | |||
| 442 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 443 | omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins)); | ||
| 444 | #endif | ||
| 445 | |||
| 422 | #endif | 446 | #endif |
| 423 | 447 | ||
| 424 | #ifdef CONFIG_OMAP_MUX_ERRORS | 448 | #ifdef CONFIG_OMAP_MUX_ERRORS |
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 0002084e0655..842090b148f1 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c | |||
| @@ -121,6 +121,13 @@ void __init omap_serial_init(void) | |||
| 121 | serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; | 121 | serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | if (cpu_is_omap850()) { | ||
| 125 | serial_platform_data[0].regshift = 0; | ||
| 126 | serial_platform_data[1].regshift = 0; | ||
| 127 | serial_platform_data[0].irq = INT_850_UART_MODEM_1; | ||
| 128 | serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2; | ||
| 129 | } | ||
| 130 | |||
| 124 | if (cpu_is_omap15xx()) { | 131 | if (cpu_is_omap15xx()) { |
| 125 | serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; | 132 | serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; |
| 126 | serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; | 133 | serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3754b79092ab..64ab386a65c7 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -58,4 +58,12 @@ config MACH_OVERO | |||
| 58 | 58 | ||
| 59 | config MACH_OMAP3_PANDORA | 59 | config MACH_OMAP3_PANDORA |
| 60 | bool "OMAP3 Pandora" | 60 | bool "OMAP3 Pandora" |
| 61 | depends on ARCH_OMAP3 && ARCH_OMAP34XX \ No newline at end of file | 61 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
| 62 | |||
| 63 | config MACH_OMAP_3430SDP | ||
| 64 | bool "OMAP 3430 SDP board" | ||
| 65 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | ||
| 66 | |||
| 67 | config MACH_NOKIA_RX51 | ||
| 68 | bool "Nokia RX-51 board" | ||
| 69 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | ||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index bbd12bc10fdc..a2c3fcc27a22 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ | 6 | obj-y := irq.o id.o io.o sdrc.o control.o prcm.o clock.o mux.o \ |
| 7 | devices.o serial.o gpmc.o timer-gp.o powerdomain.o \ | 7 | devices.o serial.o gpmc.o timer-gp.o powerdomain.o \ |
| 8 | clockdomain.o | 8 | clockdomain.o |
| 9 | 9 | ||
| @@ -14,6 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o | |||
| 14 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o | 14 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o |
| 15 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o | 15 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o |
| 16 | 16 | ||
| 17 | # SMS/SDRC | ||
| 18 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o | ||
| 19 | # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o | ||
| 20 | |||
| 17 | # Power Management | 21 | # Power Management |
| 18 | ifeq ($(CONFIG_PM),y) | 22 | ifeq ($(CONFIG_PM),y) |
| 19 | obj-y += pm.o | 23 | obj-y += pm.o |
| @@ -38,4 +42,12 @@ obj-$(CONFIG_MACH_OVERO) += board-overo.o \ | |||
| 38 | mmc-twl4030.o | 42 | mmc-twl4030.o |
| 39 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ | 43 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ |
| 40 | mmc-twl4030.o | 44 | mmc-twl4030.o |
| 45 | obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ | ||
| 46 | mmc-twl4030.o | ||
| 41 | 47 | ||
| 48 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ | ||
| 49 | board-rx51-peripherals.o \ | ||
| 50 | # Platform specific device init code | ||
| 51 | ifeq ($(CONFIG_USB_MUSB_SOC),y) | ||
| 52 | obj-y += usb-musb.o | ||
| 53 | endif | ||
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 83fa37211d77..22143651037e 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -35,12 +35,16 @@ | |||
| 35 | #include <mach/board.h> | 35 | #include <mach/board.h> |
| 36 | #include <mach/common.h> | 36 | #include <mach/common.h> |
| 37 | #include <mach/gpmc.h> | 37 | #include <mach/gpmc.h> |
| 38 | #include <mach/usb.h> | ||
| 38 | 39 | ||
| 39 | #include "mmc-twl4030.h" | 40 | #include "mmc-twl4030.h" |
| 40 | 41 | ||
| 42 | #define SDP2430_CS0_BASE 0x04000000 | ||
| 41 | #define SDP2430_FLASH_CS 0 | 43 | #define SDP2430_FLASH_CS 0 |
| 42 | #define SDP2430_SMC91X_CS 5 | 44 | #define SDP2430_SMC91X_CS 5 |
| 43 | 45 | ||
| 46 | #define SDP2430_ETHR_GPIO_IRQ 149 | ||
| 47 | |||
| 44 | static struct mtd_partition sdp2430_partitions[] = { | 48 | static struct mtd_partition sdp2430_partitions[] = { |
| 45 | /* bootloader (U-Boot, etc) in first sector */ | 49 | /* bootloader (U-Boot, etc) in first sector */ |
| 46 | { | 50 | { |
| @@ -102,8 +106,8 @@ static struct resource sdp2430_smc91x_resources[] = { | |||
| 102 | .flags = IORESOURCE_MEM, | 106 | .flags = IORESOURCE_MEM, |
| 103 | }, | 107 | }, |
| 104 | [1] = { | 108 | [1] = { |
| 105 | .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), | 109 | .start = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ), |
| 106 | .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), | 110 | .end = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ), |
| 107 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | 111 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
| 108 | }, | 112 | }, |
| 109 | }; | 113 | }; |
| @@ -170,13 +174,13 @@ static inline void __init sdp2430_init_smc91x(void) | |||
| 170 | sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; | 174 | sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; |
| 171 | udelay(100); | 175 | udelay(100); |
| 172 | 176 | ||
| 173 | if (gpio_request(OMAP24XX_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { | 177 | if (gpio_request(SDP2430_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { |
| 174 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", | 178 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", |
| 175 | OMAP24XX_ETHR_GPIO_IRQ); | 179 | SDP2430_ETHR_GPIO_IRQ); |
| 176 | gpmc_cs_free(eth_cs); | 180 | gpmc_cs_free(eth_cs); |
| 177 | goto out; | 181 | goto out; |
| 178 | } | 182 | } |
| 179 | gpio_direction_input(OMAP24XX_ETHR_GPIO_IRQ); | 183 | gpio_direction_input(SDP2430_ETHR_GPIO_IRQ); |
| 180 | 184 | ||
| 181 | out: | 185 | out: |
| 182 | clk_disable(gpmc_fck); | 186 | clk_disable(gpmc_fck); |
| @@ -185,7 +189,7 @@ out: | |||
| 185 | 189 | ||
| 186 | static void __init omap_2430sdp_init_irq(void) | 190 | static void __init omap_2430sdp_init_irq(void) |
| 187 | { | 191 | { |
| 188 | omap2_init_common_hw(); | 192 | omap2_init_common_hw(NULL); |
| 189 | omap_init_irq(); | 193 | omap_init_irq(); |
| 190 | omap_gpio_init(); | 194 | omap_gpio_init(); |
| 191 | sdp2430_init_smc91x(); | 195 | sdp2430_init_smc91x(); |
| @@ -251,6 +255,7 @@ static void __init omap_2430sdp_init(void) | |||
| 251 | omap_board_config_size = ARRAY_SIZE(sdp2430_config); | 255 | omap_board_config_size = ARRAY_SIZE(sdp2430_config); |
| 252 | omap_serial_init(); | 256 | omap_serial_init(); |
| 253 | twl4030_mmc_init(mmc); | 257 | twl4030_mmc_init(mmc); |
| 258 | usb_musb_init(); | ||
| 254 | } | 259 | } |
| 255 | 260 | ||
| 256 | static void __init omap_2430sdp_map_io(void) | 261 | static void __init omap_2430sdp_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c new file mode 100644 index 000000000000..ed9274972122 --- /dev/null +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
| @@ -0,0 +1,542 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/board-3430sdp.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Texas Instruments | ||
| 5 | * | ||
| 6 | * Modified from mach-omap2/board-generic.c | ||
| 7 | * | ||
| 8 | * Initial code: Syed Mohammed Khasim | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/input.h> | ||
| 20 | #include <linux/spi/spi.h> | ||
| 21 | #include <linux/spi/ads7846.h> | ||
| 22 | #include <linux/i2c/twl4030.h> | ||
| 23 | #include <linux/regulator/machine.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | |||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/map.h> | ||
| 31 | |||
| 32 | #include <mach/mcspi.h> | ||
| 33 | #include <mach/mux.h> | ||
| 34 | #include <mach/board.h> | ||
| 35 | #include <mach/usb.h> | ||
| 36 | #include <mach/common.h> | ||
| 37 | #include <mach/dma.h> | ||
| 38 | #include <mach/gpmc.h> | ||
| 39 | |||
| 40 | #include <mach/control.h> | ||
| 41 | #include <mach/keypad.h> | ||
| 42 | |||
| 43 | #include "mmc-twl4030.h" | ||
| 44 | |||
| 45 | #define CONFIG_DISABLE_HFCLK 1 | ||
| 46 | |||
| 47 | #define SDP3430_ETHR_GPIO_IRQ_SDPV1 29 | ||
| 48 | #define SDP3430_ETHR_GPIO_IRQ_SDPV2 6 | ||
| 49 | #define SDP3430_SMC91X_CS 3 | ||
| 50 | |||
| 51 | #define SDP3430_TS_GPIO_IRQ_SDPV1 3 | ||
| 52 | #define SDP3430_TS_GPIO_IRQ_SDPV2 2 | ||
| 53 | |||
| 54 | #define ENABLE_VAUX3_DEDICATED 0x03 | ||
| 55 | #define ENABLE_VAUX3_DEV_GRP 0x20 | ||
| 56 | |||
| 57 | #define TWL4030_MSECURE_GPIO 22 | ||
| 58 | |||
| 59 | static struct resource sdp3430_smc91x_resources[] = { | ||
| 60 | [0] = { | ||
| 61 | .flags = IORESOURCE_MEM, | ||
| 62 | }, | ||
| 63 | [1] = { | ||
| 64 | .start = 0, | ||
| 65 | .end = 0, | ||
| 66 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | ||
| 67 | }, | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct platform_device sdp3430_smc91x_device = { | ||
| 71 | .name = "smc91x", | ||
| 72 | .id = -1, | ||
| 73 | .num_resources = ARRAY_SIZE(sdp3430_smc91x_resources), | ||
| 74 | .resource = sdp3430_smc91x_resources, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static int sdp3430_keymap[] = { | ||
| 78 | KEY(0, 0, KEY_LEFT), | ||
| 79 | KEY(0, 1, KEY_RIGHT), | ||
| 80 | KEY(0, 2, KEY_A), | ||
| 81 | KEY(0, 3, KEY_B), | ||
| 82 | KEY(0, 4, KEY_C), | ||
| 83 | KEY(1, 0, KEY_DOWN), | ||
| 84 | KEY(1, 1, KEY_UP), | ||
| 85 | KEY(1, 2, KEY_E), | ||
| 86 | KEY(1, 3, KEY_F), | ||
| 87 | KEY(1, 4, KEY_G), | ||
| 88 | KEY(2, 0, KEY_ENTER), | ||
| 89 | KEY(2, 1, KEY_I), | ||
| 90 | KEY(2, 2, KEY_J), | ||
| 91 | KEY(2, 3, KEY_K), | ||
| 92 | KEY(2, 4, KEY_3), | ||
| 93 | KEY(3, 0, KEY_M), | ||
| 94 | KEY(3, 1, KEY_N), | ||
| 95 | KEY(3, 2, KEY_O), | ||
| 96 | KEY(3, 3, KEY_P), | ||
| 97 | KEY(3, 4, KEY_Q), | ||
| 98 | KEY(4, 0, KEY_R), | ||
| 99 | KEY(4, 1, KEY_4), | ||
| 100 | KEY(4, 2, KEY_T), | ||
| 101 | KEY(4, 3, KEY_U), | ||
| 102 | KEY(4, 4, KEY_D), | ||
| 103 | KEY(5, 0, KEY_V), | ||
| 104 | KEY(5, 1, KEY_W), | ||
| 105 | KEY(5, 2, KEY_L), | ||
| 106 | KEY(5, 3, KEY_S), | ||
| 107 | KEY(5, 4, KEY_H), | ||
| 108 | 0 | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct twl4030_keypad_data sdp3430_kp_data = { | ||
| 112 | .rows = 5, | ||
| 113 | .cols = 6, | ||
| 114 | .keymap = sdp3430_keymap, | ||
| 115 | .keymapsize = ARRAY_SIZE(sdp3430_keymap), | ||
| 116 | .rep = 1, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static int ts_gpio; /* Needed for ads7846_get_pendown_state */ | ||
| 120 | |||
| 121 | /** | ||
| 122 | * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq | ||
| 123 | * | ||
| 124 | * @return - void. If request gpio fails then Flag KERN_ERR. | ||
| 125 | */ | ||
| 126 | static void ads7846_dev_init(void) | ||
| 127 | { | ||
| 128 | if (gpio_request(ts_gpio, "ADS7846 pendown") < 0) { | ||
| 129 | printk(KERN_ERR "can't get ads746 pen down GPIO\n"); | ||
| 130 | return; | ||
| 131 | } | ||
| 132 | |||
| 133 | gpio_direction_input(ts_gpio); | ||
| 134 | |||
| 135 | omap_set_gpio_debounce(ts_gpio, 1); | ||
| 136 | omap_set_gpio_debounce_time(ts_gpio, 0xa); | ||
| 137 | } | ||
| 138 | |||
| 139 | static int ads7846_get_pendown_state(void) | ||
| 140 | { | ||
| 141 | return !gpio_get_value(ts_gpio); | ||
| 142 | } | ||
| 143 | |||
| 144 | static struct ads7846_platform_data tsc2046_config __initdata = { | ||
| 145 | .get_pendown_state = ads7846_get_pendown_state, | ||
| 146 | .keep_vref_on = 1, | ||
| 147 | }; | ||
| 148 | |||
| 149 | |||
| 150 | static struct omap2_mcspi_device_config tsc2046_mcspi_config = { | ||
| 151 | .turbo_mode = 0, | ||
| 152 | .single_channel = 1, /* 0: slave, 1: master */ | ||
| 153 | }; | ||
| 154 | |||
| 155 | static struct spi_board_info sdp3430_spi_board_info[] __initdata = { | ||
| 156 | [0] = { | ||
| 157 | /* | ||
| 158 | * TSC2046 operates at a max freqency of 2MHz, so | ||
| 159 | * operate slightly below at 1.5MHz | ||
| 160 | */ | ||
| 161 | .modalias = "ads7846", | ||
| 162 | .bus_num = 1, | ||
| 163 | .chip_select = 0, | ||
| 164 | .max_speed_hz = 1500000, | ||
| 165 | .controller_data = &tsc2046_mcspi_config, | ||
| 166 | .irq = 0, | ||
| 167 | .platform_data = &tsc2046_config, | ||
| 168 | }, | ||
| 169 | }; | ||
| 170 | |||
| 171 | static struct platform_device sdp3430_lcd_device = { | ||
| 172 | .name = "sdp2430_lcd", | ||
| 173 | .id = -1, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct regulator_consumer_supply sdp3430_vdac_supply = { | ||
| 177 | .supply = "vdac", | ||
| 178 | .dev = &sdp3430_lcd_device.dev, | ||
| 179 | }; | ||
| 180 | |||
| 181 | static struct regulator_consumer_supply sdp3430_vdvi_supply = { | ||
| 182 | .supply = "vdvi", | ||
| 183 | .dev = &sdp3430_lcd_device.dev, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static struct platform_device *sdp3430_devices[] __initdata = { | ||
| 187 | &sdp3430_smc91x_device, | ||
| 188 | &sdp3430_lcd_device, | ||
| 189 | }; | ||
| 190 | |||
| 191 | static inline void __init sdp3430_init_smc91x(void) | ||
| 192 | { | ||
| 193 | int eth_cs; | ||
| 194 | unsigned long cs_mem_base; | ||
| 195 | int eth_gpio = 0; | ||
| 196 | |||
| 197 | eth_cs = SDP3430_SMC91X_CS; | ||
| 198 | |||
| 199 | if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { | ||
| 200 | printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); | ||
| 201 | return; | ||
| 202 | } | ||
| 203 | |||
| 204 | sdp3430_smc91x_resources[0].start = cs_mem_base + 0x300; | ||
| 205 | sdp3430_smc91x_resources[0].end = cs_mem_base + 0x30f; | ||
| 206 | udelay(100); | ||
| 207 | |||
| 208 | if (omap_rev() > OMAP3430_REV_ES1_0) | ||
| 209 | eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV2; | ||
| 210 | else | ||
| 211 | eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV1; | ||
| 212 | |||
| 213 | sdp3430_smc91x_resources[1].start = gpio_to_irq(eth_gpio); | ||
| 214 | |||
| 215 | if (gpio_request(eth_gpio, "SMC91x irq") < 0) { | ||
| 216 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", | ||
| 217 | eth_gpio); | ||
| 218 | return; | ||
| 219 | } | ||
| 220 | gpio_direction_input(eth_gpio); | ||
| 221 | } | ||
| 222 | |||
| 223 | static void __init omap_3430sdp_init_irq(void) | ||
| 224 | { | ||
| 225 | omap2_init_common_hw(NULL); | ||
| 226 | omap_init_irq(); | ||
| 227 | omap_gpio_init(); | ||
| 228 | sdp3430_init_smc91x(); | ||
| 229 | } | ||
| 230 | |||
| 231 | static struct omap_uart_config sdp3430_uart_config __initdata = { | ||
| 232 | .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), | ||
| 233 | }; | ||
| 234 | |||
| 235 | static struct omap_lcd_config sdp3430_lcd_config __initdata = { | ||
| 236 | .ctrl_name = "internal", | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct omap_board_config_kernel sdp3430_config[] __initdata = { | ||
| 240 | { OMAP_TAG_UART, &sdp3430_uart_config }, | ||
| 241 | { OMAP_TAG_LCD, &sdp3430_lcd_config }, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static int sdp3430_batt_table[] = { | ||
| 245 | /* 0 C*/ | ||
| 246 | 30800, 29500, 28300, 27100, | ||
| 247 | 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900, | ||
| 248 | 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100, | ||
| 249 | 11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310, | ||
| 250 | 8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830, | ||
| 251 | 5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170, | ||
| 252 | 4040, 3910, 3790, 3670, 3550 | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct twl4030_bci_platform_data sdp3430_bci_data = { | ||
| 256 | .battery_tmp_tbl = sdp3430_batt_table, | ||
| 257 | .tblsize = ARRAY_SIZE(sdp3430_batt_table), | ||
| 258 | }; | ||
| 259 | |||
| 260 | static struct twl4030_hsmmc_info mmc[] = { | ||
| 261 | { | ||
| 262 | .mmc = 1, | ||
| 263 | /* 8 bits (default) requires S6.3 == ON, | ||
| 264 | * so the SIM card isn't used; else 4 bits. | ||
| 265 | */ | ||
| 266 | .wires = 8, | ||
| 267 | .gpio_wp = 4, | ||
| 268 | }, | ||
| 269 | { | ||
| 270 | .mmc = 2, | ||
| 271 | .wires = 8, | ||
| 272 | .gpio_wp = 7, | ||
| 273 | }, | ||
| 274 | {} /* Terminator */ | ||
| 275 | }; | ||
| 276 | |||
| 277 | static struct regulator_consumer_supply sdp3430_vmmc1_supply = { | ||
| 278 | .supply = "vmmc", | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct regulator_consumer_supply sdp3430_vsim_supply = { | ||
| 282 | .supply = "vmmc_aux", | ||
| 283 | }; | ||
| 284 | |||
| 285 | static struct regulator_consumer_supply sdp3430_vmmc2_supply = { | ||
| 286 | .supply = "vmmc", | ||
| 287 | }; | ||
| 288 | |||
| 289 | static int sdp3430_twl_gpio_setup(struct device *dev, | ||
| 290 | unsigned gpio, unsigned ngpio) | ||
| 291 | { | ||
| 292 | /* gpio + 0 is "mmc0_cd" (input/IRQ), | ||
| 293 | * gpio + 1 is "mmc1_cd" (input/IRQ) | ||
| 294 | */ | ||
| 295 | mmc[0].gpio_cd = gpio + 0; | ||
| 296 | mmc[1].gpio_cd = gpio + 1; | ||
| 297 | twl4030_mmc_init(mmc); | ||
| 298 | |||
| 299 | /* link regulators to MMC adapters ... we "know" the | ||
| 300 | * regulators will be set up only *after* we return. | ||
| 301 | */ | ||
| 302 | sdp3430_vmmc1_supply.dev = mmc[0].dev; | ||
| 303 | sdp3430_vsim_supply.dev = mmc[0].dev; | ||
| 304 | sdp3430_vmmc2_supply.dev = mmc[1].dev; | ||
| 305 | |||
| 306 | /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ | ||
| 307 | gpio_request(gpio + 7, "sub_lcd_en_bkl"); | ||
| 308 | gpio_direction_output(gpio + 7, 0); | ||
| 309 | |||
| 310 | /* gpio + 15 is "sub_lcd_nRST" (output) */ | ||
| 311 | gpio_request(gpio + 15, "sub_lcd_nRST"); | ||
| 312 | gpio_direction_output(gpio + 15, 0); | ||
| 313 | |||
| 314 | return 0; | ||
| 315 | } | ||
| 316 | |||
| 317 | static struct twl4030_gpio_platform_data sdp3430_gpio_data = { | ||
| 318 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 319 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 320 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 321 | .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) | ||
| 322 | | BIT(16) | BIT(17), | ||
| 323 | .setup = sdp3430_twl_gpio_setup, | ||
| 324 | }; | ||
| 325 | |||
| 326 | static struct twl4030_usb_data sdp3430_usb_data = { | ||
| 327 | .usb_mode = T2_USB_MODE_ULPI, | ||
| 328 | }; | ||
| 329 | |||
| 330 | static struct twl4030_madc_platform_data sdp3430_madc_data = { | ||
| 331 | .irq_line = 1, | ||
| 332 | }; | ||
| 333 | |||
| 334 | /* | ||
| 335 | * Apply all the fixed voltages since most versions of U-Boot | ||
| 336 | * don't bother with that initialization. | ||
| 337 | */ | ||
| 338 | |||
| 339 | /* VAUX1 for mainboard (irda and sub-lcd) */ | ||
| 340 | static struct regulator_init_data sdp3430_vaux1 = { | ||
| 341 | .constraints = { | ||
| 342 | .min_uV = 2800000, | ||
| 343 | .max_uV = 2800000, | ||
| 344 | .apply_uV = true, | ||
| 345 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 346 | | REGULATOR_MODE_STANDBY, | ||
| 347 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 348 | | REGULATOR_CHANGE_STATUS, | ||
| 349 | }, | ||
| 350 | }; | ||
| 351 | |||
| 352 | /* VAUX2 for camera module */ | ||
| 353 | static struct regulator_init_data sdp3430_vaux2 = { | ||
| 354 | .constraints = { | ||
| 355 | .min_uV = 2800000, | ||
| 356 | .max_uV = 2800000, | ||
| 357 | .apply_uV = true, | ||
| 358 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 359 | | REGULATOR_MODE_STANDBY, | ||
| 360 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 361 | | REGULATOR_CHANGE_STATUS, | ||
| 362 | }, | ||
| 363 | }; | ||
| 364 | |||
| 365 | /* VAUX3 for LCD board */ | ||
| 366 | static struct regulator_init_data sdp3430_vaux3 = { | ||
| 367 | .constraints = { | ||
| 368 | .min_uV = 2800000, | ||
| 369 | .max_uV = 2800000, | ||
| 370 | .apply_uV = true, | ||
| 371 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 372 | | REGULATOR_MODE_STANDBY, | ||
| 373 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 374 | | REGULATOR_CHANGE_STATUS, | ||
| 375 | }, | ||
| 376 | }; | ||
| 377 | |||
| 378 | /* VAUX4 for OMAP VDD_CSI2 (camera) */ | ||
| 379 | static struct regulator_init_data sdp3430_vaux4 = { | ||
| 380 | .constraints = { | ||
| 381 | .min_uV = 1800000, | ||
| 382 | .max_uV = 1800000, | ||
| 383 | .apply_uV = true, | ||
| 384 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 385 | | REGULATOR_MODE_STANDBY, | ||
| 386 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 387 | | REGULATOR_CHANGE_STATUS, | ||
| 388 | }, | ||
| 389 | }; | ||
| 390 | |||
| 391 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ | ||
| 392 | static struct regulator_init_data sdp3430_vmmc1 = { | ||
| 393 | .constraints = { | ||
| 394 | .min_uV = 1850000, | ||
| 395 | .max_uV = 3150000, | ||
| 396 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 397 | | REGULATOR_MODE_STANDBY, | ||
| 398 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 399 | | REGULATOR_CHANGE_MODE | ||
| 400 | | REGULATOR_CHANGE_STATUS, | ||
| 401 | }, | ||
| 402 | .num_consumer_supplies = 1, | ||
| 403 | .consumer_supplies = &sdp3430_vmmc1_supply, | ||
| 404 | }; | ||
| 405 | |||
| 406 | /* VMMC2 for MMC2 card */ | ||
| 407 | static struct regulator_init_data sdp3430_vmmc2 = { | ||
| 408 | .constraints = { | ||
| 409 | .min_uV = 1850000, | ||
| 410 | .max_uV = 1850000, | ||
| 411 | .apply_uV = true, | ||
| 412 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 413 | | REGULATOR_MODE_STANDBY, | ||
| 414 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 415 | | REGULATOR_CHANGE_STATUS, | ||
| 416 | }, | ||
| 417 | .num_consumer_supplies = 1, | ||
| 418 | .consumer_supplies = &sdp3430_vmmc2_supply, | ||
| 419 | }; | ||
| 420 | |||
| 421 | /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ | ||
| 422 | static struct regulator_init_data sdp3430_vsim = { | ||
| 423 | .constraints = { | ||
| 424 | .min_uV = 1800000, | ||
| 425 | .max_uV = 3000000, | ||
| 426 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 427 | | REGULATOR_MODE_STANDBY, | ||
| 428 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 429 | | REGULATOR_CHANGE_MODE | ||
| 430 | | REGULATOR_CHANGE_STATUS, | ||
| 431 | }, | ||
| 432 | .num_consumer_supplies = 1, | ||
| 433 | .consumer_supplies = &sdp3430_vsim_supply, | ||
| 434 | }; | ||
| 435 | |||
| 436 | /* VDAC for DSS driving S-Video */ | ||
| 437 | static struct regulator_init_data sdp3430_vdac = { | ||
| 438 | .constraints = { | ||
| 439 | .min_uV = 1800000, | ||
| 440 | .max_uV = 1800000, | ||
| 441 | .apply_uV = true, | ||
| 442 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 443 | | REGULATOR_MODE_STANDBY, | ||
| 444 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 445 | | REGULATOR_CHANGE_STATUS, | ||
| 446 | }, | ||
| 447 | .num_consumer_supplies = 1, | ||
| 448 | .consumer_supplies = &sdp3430_vdac_supply, | ||
| 449 | }; | ||
| 450 | |||
| 451 | /* VPLL2 for digital video outputs */ | ||
| 452 | static struct regulator_init_data sdp3430_vpll2 = { | ||
| 453 | .constraints = { | ||
| 454 | .name = "VDVI", | ||
| 455 | .min_uV = 1800000, | ||
| 456 | .max_uV = 1800000, | ||
| 457 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 458 | | REGULATOR_MODE_STANDBY, | ||
| 459 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 460 | | REGULATOR_CHANGE_STATUS, | ||
| 461 | }, | ||
| 462 | .num_consumer_supplies = 1, | ||
| 463 | .consumer_supplies = &sdp3430_vdvi_supply, | ||
| 464 | }; | ||
| 465 | |||
| 466 | static struct twl4030_platform_data sdp3430_twldata = { | ||
| 467 | .irq_base = TWL4030_IRQ_BASE, | ||
| 468 | .irq_end = TWL4030_IRQ_END, | ||
| 469 | |||
| 470 | /* platform_data for children goes here */ | ||
| 471 | .bci = &sdp3430_bci_data, | ||
| 472 | .gpio = &sdp3430_gpio_data, | ||
| 473 | .madc = &sdp3430_madc_data, | ||
| 474 | .keypad = &sdp3430_kp_data, | ||
| 475 | .usb = &sdp3430_usb_data, | ||
| 476 | |||
| 477 | .vaux1 = &sdp3430_vaux1, | ||
| 478 | .vaux2 = &sdp3430_vaux2, | ||
| 479 | .vaux3 = &sdp3430_vaux3, | ||
| 480 | .vaux4 = &sdp3430_vaux4, | ||
| 481 | .vmmc1 = &sdp3430_vmmc1, | ||
| 482 | .vmmc2 = &sdp3430_vmmc2, | ||
| 483 | .vsim = &sdp3430_vsim, | ||
| 484 | .vdac = &sdp3430_vdac, | ||
| 485 | .vpll2 = &sdp3430_vpll2, | ||
| 486 | }; | ||
| 487 | |||
| 488 | static struct i2c_board_info __initdata sdp3430_i2c_boardinfo[] = { | ||
| 489 | { | ||
| 490 | I2C_BOARD_INFO("twl4030", 0x48), | ||
| 491 | .flags = I2C_CLIENT_WAKE, | ||
| 492 | .irq = INT_34XX_SYS_NIRQ, | ||
| 493 | .platform_data = &sdp3430_twldata, | ||
| 494 | }, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static int __init omap3430_i2c_init(void) | ||
| 498 | { | ||
| 499 | /* i2c1 for PMIC only */ | ||
| 500 | omap_register_i2c_bus(1, 2600, sdp3430_i2c_boardinfo, | ||
| 501 | ARRAY_SIZE(sdp3430_i2c_boardinfo)); | ||
| 502 | /* i2c2 on camera connector (for sensor control) and optional isp1301 */ | ||
| 503 | omap_register_i2c_bus(2, 400, NULL, 0); | ||
| 504 | /* i2c3 on display connector (for DVI, tfp410) */ | ||
| 505 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 506 | return 0; | ||
| 507 | } | ||
| 508 | |||
| 509 | static void __init omap_3430sdp_init(void) | ||
| 510 | { | ||
| 511 | omap3430_i2c_init(); | ||
| 512 | platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); | ||
| 513 | omap_board_config = sdp3430_config; | ||
| 514 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); | ||
| 515 | if (omap_rev() > OMAP3430_REV_ES1_0) | ||
| 516 | ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2; | ||
| 517 | else | ||
| 518 | ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV1; | ||
| 519 | sdp3430_spi_board_info[0].irq = gpio_to_irq(ts_gpio); | ||
| 520 | spi_register_board_info(sdp3430_spi_board_info, | ||
| 521 | ARRAY_SIZE(sdp3430_spi_board_info)); | ||
| 522 | ads7846_dev_init(); | ||
| 523 | omap_serial_init(); | ||
| 524 | usb_musb_init(); | ||
| 525 | } | ||
| 526 | |||
| 527 | static void __init omap_3430sdp_map_io(void) | ||
| 528 | { | ||
| 529 | omap2_set_globals_343x(); | ||
| 530 | omap2_map_common_io(); | ||
| 531 | } | ||
| 532 | |||
| 533 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") | ||
| 534 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | ||
| 535 | .phys_io = 0x48000000, | ||
| 536 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | ||
| 537 | .boot_params = 0x80000100, | ||
| 538 | .map_io = omap_3430sdp_map_io, | ||
| 539 | .init_irq = omap_3430sdp_init_irq, | ||
| 540 | .init_machine = omap_3430sdp_init, | ||
| 541 | .timer = &omap_timer, | ||
| 542 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 0a7b24ba1652..06dfba888b0c 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -51,6 +51,7 @@ | |||
| 51 | 51 | ||
| 52 | #define APOLLON_FLASH_CS 0 | 52 | #define APOLLON_FLASH_CS 0 |
| 53 | #define APOLLON_ETH_CS 1 | 53 | #define APOLLON_ETH_CS 1 |
| 54 | #define APOLLON_ETHR_GPIO_IRQ 74 | ||
| 54 | 55 | ||
| 55 | static struct mtd_partition apollon_partitions[] = { | 56 | static struct mtd_partition apollon_partitions[] = { |
| 56 | { | 57 | { |
| @@ -249,7 +250,7 @@ out: | |||
| 249 | 250 | ||
| 250 | static void __init omap_apollon_init_irq(void) | 251 | static void __init omap_apollon_init_irq(void) |
| 251 | { | 252 | { |
| 252 | omap2_init_common_hw(); | 253 | omap2_init_common_hw(NULL); |
| 253 | omap_init_irq(); | 254 | omap_init_irq(); |
| 254 | omap_gpio_init(); | 255 | omap_gpio_init(); |
| 255 | apollon_init_smc91x(); | 256 | apollon_init_smc91x(); |
| @@ -272,7 +273,6 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { | |||
| 272 | 273 | ||
| 273 | static struct omap_board_config_kernel apollon_config[] = { | 274 | static struct omap_board_config_kernel apollon_config[] = { |
| 274 | { OMAP_TAG_UART, &apollon_uart_config }, | 275 | { OMAP_TAG_UART, &apollon_uart_config }, |
| 275 | { OMAP_TAG_USB, &apollon_usb_config }, | ||
| 276 | { OMAP_TAG_LCD, &apollon_lcd_config }, | 276 | { OMAP_TAG_LCD, &apollon_lcd_config }, |
| 277 | }; | 277 | }; |
| 278 | 278 | ||
| @@ -299,6 +299,7 @@ static void __init apollon_usb_init(void) | |||
| 299 | omap_cfg_reg(P21_242X_GPIO12); | 299 | omap_cfg_reg(P21_242X_GPIO12); |
| 300 | gpio_request(12, "USB suspend"); | 300 | gpio_request(12, "USB suspend"); |
| 301 | gpio_direction_output(12, 0); | 301 | gpio_direction_output(12, 0); |
| 302 | omap_usb_init(&apollon_usb_config); | ||
| 302 | } | 303 | } |
| 303 | 304 | ||
| 304 | static void __init omap_apollon_init(void) | 305 | static void __init omap_apollon_init(void) |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 3b34c20d1df4..3492162a65c3 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -33,7 +33,7 @@ | |||
| 33 | 33 | ||
| 34 | static void __init omap_generic_init_irq(void) | 34 | static void __init omap_generic_init_irq(void) |
| 35 | { | 35 | { |
| 36 | omap2_init_common_hw(); | 36 | omap2_init_common_hw(NULL); |
| 37 | omap_init_irq(); | 37 | omap_init_irq(); |
| 38 | } | 38 | } |
| 39 | 39 | ||
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 5e9b14675b1e..a0267a9ab466 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -47,6 +47,8 @@ | |||
| 47 | #define H4_FLASH_CS 0 | 47 | #define H4_FLASH_CS 0 |
| 48 | #define H4_SMC91X_CS 1 | 48 | #define H4_SMC91X_CS 1 |
| 49 | 49 | ||
| 50 | #define H4_ETHR_GPIO_IRQ 92 | ||
| 51 | |||
| 50 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; | 52 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; |
| 51 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; | 53 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; |
| 52 | 54 | ||
| @@ -341,7 +343,7 @@ static inline void __init h4_init_debug(void) | |||
| 341 | udelay(100); | 343 | udelay(100); |
| 342 | 344 | ||
| 343 | omap_cfg_reg(M15_24XX_GPIO92); | 345 | omap_cfg_reg(M15_24XX_GPIO92); |
| 344 | if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) | 346 | if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0) |
| 345 | gpmc_cs_free(eth_cs); | 347 | gpmc_cs_free(eth_cs); |
| 346 | 348 | ||
| 347 | out: | 349 | out: |
| @@ -363,7 +365,7 @@ static void __init h4_init_flash(void) | |||
| 363 | 365 | ||
| 364 | static void __init omap_h4_init_irq(void) | 366 | static void __init omap_h4_init_irq(void) |
| 365 | { | 367 | { |
| 366 | omap2_init_common_hw(); | 368 | omap2_init_common_hw(NULL); |
| 367 | omap_init_irq(); | 369 | omap_init_irq(); |
| 368 | omap_gpio_init(); | 370 | omap_gpio_init(); |
| 369 | h4_init_flash(); | 371 | h4_init_flash(); |
| @@ -377,6 +379,39 @@ static struct omap_lcd_config h4_lcd_config __initdata = { | |||
| 377 | .ctrl_name = "internal", | 379 | .ctrl_name = "internal", |
| 378 | }; | 380 | }; |
| 379 | 381 | ||
| 382 | static struct omap_usb_config h4_usb_config __initdata = { | ||
| 383 | #ifdef CONFIG_MACH_OMAP2_H4_USB1 | ||
| 384 | /* NOTE: usb1 could also be used with 3 wire signaling */ | ||
| 385 | .pins[1] = 4, | ||
| 386 | #endif | ||
| 387 | |||
| 388 | #ifdef CONFIG_MACH_OMAP_H4_OTG | ||
| 389 | /* S1.10 ON -- USB OTG port | ||
| 390 | * usb0 switched to Mini-AB port and isp1301 transceiver; | ||
| 391 | * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging | ||
| 392 | */ | ||
| 393 | .otg = 1, | ||
| 394 | .pins[0] = 4, | ||
| 395 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 396 | /* use OTG cable, or standard A-to-MiniB */ | ||
| 397 | .hmc_mode = 0x14, /* 0:dev/otg 1:host 2:disable */ | ||
| 398 | #elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 399 | /* use OTG cable, or NONSTANDARD (B-to-MiniB) */ | ||
| 400 | .hmc_mode = 0x11, /* 0:host 1:host 2:disable */ | ||
| 401 | #endif /* XX */ | ||
| 402 | |||
| 403 | #else | ||
| 404 | /* S1.10 OFF -- usb "download port" | ||
| 405 | * usb0 switched to Mini-B port and isp1105 transceiver; | ||
| 406 | * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging | ||
| 407 | */ | ||
| 408 | .register_dev = 1, | ||
| 409 | .pins[0] = 3, | ||
| 410 | /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ | ||
| 411 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ | ||
| 412 | #endif | ||
| 413 | }; | ||
| 414 | |||
| 380 | static struct omap_board_config_kernel h4_config[] = { | 415 | static struct omap_board_config_kernel h4_config[] = { |
| 381 | { OMAP_TAG_UART, &h4_uart_config }, | 416 | { OMAP_TAG_UART, &h4_uart_config }, |
| 382 | { OMAP_TAG_LCD, &h4_lcd_config }, | 417 | { OMAP_TAG_LCD, &h4_lcd_config }, |
| @@ -428,6 +463,7 @@ static void __init omap_h4_init(void) | |||
| 428 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); | 463 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); |
| 429 | omap_board_config = h4_config; | 464 | omap_board_config = h4_config; |
| 430 | omap_board_config_size = ARRAY_SIZE(h4_config); | 465 | omap_board_config_size = ARRAY_SIZE(h4_config); |
| 466 | omap_usb_init(&h4_usb_config); | ||
| 431 | omap_serial_init(); | 467 | omap_serial_init(); |
| 432 | } | 468 | } |
| 433 | 469 | ||
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 6031e179926b..e096f776f996 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
| @@ -22,31 +22,34 @@ | |||
| 22 | #include <linux/spi/spi.h> | 22 | #include <linux/spi/spi.h> |
| 23 | #include <linux/spi/ads7846.h> | 23 | #include <linux/spi/ads7846.h> |
| 24 | #include <linux/i2c/twl4030.h> | 24 | #include <linux/i2c/twl4030.h> |
| 25 | #include <linux/io.h> | ||
| 25 | 26 | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| 30 | 31 | ||
| 31 | #include <mach/board-ldp.h> | ||
| 32 | #include <mach/mcspi.h> | 32 | #include <mach/mcspi.h> |
| 33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
| 34 | #include <mach/board.h> | 34 | #include <mach/board.h> |
| 35 | #include <mach/common.h> | 35 | #include <mach/common.h> |
| 36 | #include <mach/gpmc.h> | 36 | #include <mach/gpmc.h> |
| 37 | 37 | ||
| 38 | #include <asm/io.h> | ||
| 39 | #include <asm/delay.h> | 38 | #include <asm/delay.h> |
| 40 | #include <mach/control.h> | 39 | #include <mach/control.h> |
| 40 | #include <mach/usb.h> | ||
| 41 | 41 | ||
| 42 | #include "mmc-twl4030.h" | 42 | #include "mmc-twl4030.h" |
| 43 | 43 | ||
| 44 | #define SDP3430_SMC91X_CS 3 | 44 | #define LDP_SMC911X_CS 1 |
| 45 | #define LDP_SMC911X_GPIO 152 | ||
| 46 | #define DEBUG_BASE 0x08000000 | ||
| 47 | #define LDP_ETHR_START DEBUG_BASE | ||
| 45 | 48 | ||
| 46 | static struct resource ldp_smc911x_resources[] = { | 49 | static struct resource ldp_smc911x_resources[] = { |
| 47 | [0] = { | 50 | [0] = { |
| 48 | .start = OMAP34XX_ETHR_START, | 51 | .start = LDP_ETHR_START, |
| 49 | .end = OMAP34XX_ETHR_START + SZ_4K, | 52 | .end = LDP_ETHR_START + SZ_4K, |
| 50 | .flags = IORESOURCE_MEM, | 53 | .flags = IORESOURCE_MEM, |
| 51 | }, | 54 | }, |
| 52 | [1] = { | 55 | [1] = { |
| @@ -98,7 +101,7 @@ static inline void __init ldp_init_smc911x(void) | |||
| 98 | 101 | ||
| 99 | static void __init omap_ldp_init_irq(void) | 102 | static void __init omap_ldp_init_irq(void) |
| 100 | { | 103 | { |
| 101 | omap2_init_common_hw(); | 104 | omap2_init_common_hw(NULL); |
| 102 | omap_init_irq(); | 105 | omap_init_irq(); |
| 103 | omap_gpio_init(); | 106 | omap_gpio_init(); |
| 104 | ldp_init_smc911x(); | 107 | ldp_init_smc911x(); |
| @@ -162,6 +165,7 @@ static void __init omap_ldp_init(void) | |||
| 162 | omap_board_config_size = ARRAY_SIZE(ldp_config); | 165 | omap_board_config_size = ARRAY_SIZE(ldp_config); |
| 163 | omap_serial_init(); | 166 | omap_serial_init(); |
| 164 | twl4030_mmc_init(mmc); | 167 | twl4030_mmc_init(mmc); |
| 168 | usb_musb_init(); | ||
| 165 | } | 169 | } |
| 166 | 170 | ||
| 167 | static void __init omap_ldp_map_io(void) | 171 | static void __init omap_ldp_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index e39cd2c46cfa..744740ae1b9c 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | #include <mach/gpmc.h> | 41 | #include <mach/gpmc.h> |
| 42 | #include <mach/nand.h> | 42 | #include <mach/nand.h> |
| 43 | #include <mach/mux.h> | 43 | #include <mach/mux.h> |
| 44 | #include <mach/usb.h> | ||
| 44 | 45 | ||
| 45 | #include "mmc-twl4030.h" | 46 | #include "mmc-twl4030.h" |
| 46 | 47 | ||
| @@ -175,9 +176,6 @@ static int __init omap3_beagle_i2c_init(void) | |||
| 175 | { | 176 | { |
| 176 | omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, | 177 | omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, |
| 177 | ARRAY_SIZE(beagle_i2c_boardinfo)); | 178 | ARRAY_SIZE(beagle_i2c_boardinfo)); |
| 178 | #ifdef CONFIG_I2C2_OMAP_BEAGLE | ||
| 179 | omap_register_i2c_bus(2, 400, NULL, 0); | ||
| 180 | #endif | ||
| 181 | /* Bus 3 is attached to the DVI port where devices like the pico DLP | 179 | /* Bus 3 is attached to the DVI port where devices like the pico DLP |
| 182 | * projector don't work reliably with 400kHz */ | 180 | * projector don't work reliably with 400kHz */ |
| 183 | omap_register_i2c_bus(3, 100, NULL, 0); | 181 | omap_register_i2c_bus(3, 100, NULL, 0); |
| @@ -186,7 +184,7 @@ static int __init omap3_beagle_i2c_init(void) | |||
| 186 | 184 | ||
| 187 | static void __init omap3_beagle_init_irq(void) | 185 | static void __init omap3_beagle_init_irq(void) |
| 188 | { | 186 | { |
| 189 | omap2_init_common_hw(); | 187 | omap2_init_common_hw(NULL); |
| 190 | omap_init_irq(); | 188 | omap_init_irq(); |
| 191 | omap_gpio_init(); | 189 | omap_gpio_init(); |
| 192 | } | 190 | } |
| @@ -316,6 +314,7 @@ static void __init omap3_beagle_init(void) | |||
| 316 | /* REVISIT leave DVI powered down until it's needed ... */ | 314 | /* REVISIT leave DVI powered down until it's needed ... */ |
| 317 | gpio_direction_output(170, true); | 315 | gpio_direction_output(170, true); |
| 318 | 316 | ||
| 317 | usb_musb_init(); | ||
| 319 | omap3beagle_flash_init(); | 318 | omap3beagle_flash_init(); |
| 320 | } | 319 | } |
| 321 | 320 | ||
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index b3196107afdb..402f09c6cf10 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | #include <mach/gpio.h> | 34 | #include <mach/gpio.h> |
| 35 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 36 | #include <mach/mcspi.h> | 36 | #include <mach/mcspi.h> |
| 37 | #include <mach/usb.h> | ||
| 37 | 38 | ||
| 38 | #include "mmc-twl4030.h" | 39 | #include "mmc-twl4030.h" |
| 39 | 40 | ||
| @@ -53,6 +54,13 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = { | |||
| 53 | .gpio_cd = -EINVAL, | 54 | .gpio_cd = -EINVAL, |
| 54 | .gpio_wp = 127, | 55 | .gpio_wp = 127, |
| 55 | .ext_clock = 1, | 56 | .ext_clock = 1, |
| 57 | .transceiver = true, | ||
| 58 | }, | ||
| 59 | { | ||
| 60 | .mmc = 3, | ||
| 61 | .wires = 4, | ||
| 62 | .gpio_cd = -EINVAL, | ||
| 63 | .gpio_wp = -EINVAL, | ||
| 56 | }, | 64 | }, |
| 57 | {} /* Terminator */ | 65 | {} /* Terminator */ |
| 58 | }; | 66 | }; |
| @@ -110,7 +118,7 @@ static int __init omap3pandora_i2c_init(void) | |||
| 110 | 118 | ||
| 111 | static void __init omap3pandora_init_irq(void) | 119 | static void __init omap3pandora_init_irq(void) |
| 112 | { | 120 | { |
| 113 | omap2_init_common_hw(); | 121 | omap2_init_common_hw(NULL); |
| 114 | omap_init_irq(); | 122 | omap_init_irq(); |
| 115 | omap_gpio_init(); | 123 | omap_gpio_init(); |
| 116 | } | 124 | } |
| @@ -193,6 +201,7 @@ static void __init omap3pandora_init(void) | |||
| 193 | spi_register_board_info(omap3pandora_spi_board_info, | 201 | spi_register_board_info(omap3pandora_spi_board_info, |
| 194 | ARRAY_SIZE(omap3pandora_spi_board_info)); | 202 | ARRAY_SIZE(omap3pandora_spi_board_info)); |
| 195 | omap3pandora_ads7846_init(); | 203 | omap3pandora_ads7846_init(); |
| 204 | usb_musb_init(); | ||
| 196 | } | 205 | } |
| 197 | 206 | ||
| 198 | static void __init omap3pandora_map_io(void) | 207 | static void __init omap3pandora_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 82b3dc557c96..b3f6e9d81807 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
| @@ -37,20 +37,85 @@ | |||
| 37 | #include <asm/mach/flash.h> | 37 | #include <asm/mach/flash.h> |
| 38 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 39 | 39 | ||
| 40 | #include <mach/board-overo.h> | ||
| 41 | #include <mach/board.h> | 40 | #include <mach/board.h> |
| 42 | #include <mach/common.h> | 41 | #include <mach/common.h> |
| 43 | #include <mach/gpio.h> | 42 | #include <mach/gpio.h> |
| 44 | #include <mach/gpmc.h> | 43 | #include <mach/gpmc.h> |
| 45 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
| 46 | #include <mach/nand.h> | 45 | #include <mach/nand.h> |
| 46 | #include <mach/usb.h> | ||
| 47 | 47 | ||
| 48 | #include "mmc-twl4030.h" | 48 | #include "mmc-twl4030.h" |
| 49 | 49 | ||
| 50 | #define OVERO_GPIO_BT_XGATE 15 | ||
| 51 | #define OVERO_GPIO_W2W_NRESET 16 | ||
| 52 | #define OVERO_GPIO_BT_NRESET 164 | ||
| 53 | #define OVERO_GPIO_USBH_CPEN 168 | ||
| 54 | #define OVERO_GPIO_USBH_NRESET 183 | ||
| 55 | |||
| 50 | #define NAND_BLOCK_SIZE SZ_128K | 56 | #define NAND_BLOCK_SIZE SZ_128K |
| 51 | #define GPMC_CS0_BASE 0x60 | 57 | #define GPMC_CS0_BASE 0x60 |
| 52 | #define GPMC_CS_SIZE 0x30 | 58 | #define GPMC_CS_SIZE 0x30 |
| 53 | 59 | ||
| 60 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ | ||
| 61 | defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | ||
| 62 | |||
| 63 | #include <mach/mcspi.h> | ||
| 64 | #include <linux/spi/spi.h> | ||
| 65 | #include <linux/spi/ads7846.h> | ||
| 66 | |||
| 67 | static struct omap2_mcspi_device_config ads7846_mcspi_config = { | ||
| 68 | .turbo_mode = 0, | ||
| 69 | .single_channel = 1, /* 0: slave, 1: master */ | ||
| 70 | }; | ||
| 71 | |||
| 72 | static int ads7846_get_pendown_state(void) | ||
| 73 | { | ||
| 74 | return !gpio_get_value(OVERO_GPIO_PENDOWN); | ||
| 75 | } | ||
| 76 | |||
| 77 | static struct ads7846_platform_data ads7846_config = { | ||
| 78 | .x_max = 0x0fff, | ||
| 79 | .y_max = 0x0fff, | ||
| 80 | .x_plate_ohms = 180, | ||
| 81 | .pressure_max = 255, | ||
| 82 | .debounce_max = 10, | ||
| 83 | .debounce_tol = 3, | ||
| 84 | .debounce_rep = 1, | ||
| 85 | .get_pendown_state = ads7846_get_pendown_state, | ||
| 86 | .keep_vref_on = 1, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct spi_board_info overo_spi_board_info[] __initdata = { | ||
| 90 | { | ||
| 91 | .modalias = "ads7846", | ||
| 92 | .bus_num = 1, | ||
| 93 | .chip_select = 0, | ||
| 94 | .max_speed_hz = 1500000, | ||
| 95 | .controller_data = &ads7846_mcspi_config, | ||
| 96 | .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), | ||
| 97 | .platform_data = &ads7846_config, | ||
| 98 | } | ||
| 99 | }; | ||
| 100 | |||
| 101 | static void __init overo_ads7846_init(void) | ||
| 102 | { | ||
| 103 | if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) && | ||
| 104 | (gpio_direction_input(OVERO_GPIO_PENDOWN) == 0)) { | ||
| 105 | gpio_export(OVERO_GPIO_PENDOWN, 0); | ||
| 106 | } else { | ||
| 107 | printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n"); | ||
| 108 | return; | ||
| 109 | } | ||
| 110 | |||
| 111 | spi_register_board_info(overo_spi_board_info, | ||
| 112 | ARRAY_SIZE(overo_spi_board_info)); | ||
| 113 | } | ||
| 114 | |||
| 115 | #else | ||
| 116 | static inline void __init overo_ads7846_init(void) { return; } | ||
| 117 | #endif | ||
| 118 | |||
| 54 | static struct mtd_partition overo_nand_partitions[] = { | 119 | static struct mtd_partition overo_nand_partitions[] = { |
| 55 | { | 120 | { |
| 56 | .name = "xloader", | 121 | .name = "xloader", |
| @@ -174,7 +239,7 @@ static int __init overo_i2c_init(void) | |||
| 174 | 239 | ||
| 175 | static void __init overo_init_irq(void) | 240 | static void __init overo_init_irq(void) |
| 176 | { | 241 | { |
| 177 | omap2_init_common_hw(); | 242 | omap2_init_common_hw(NULL); |
| 178 | omap_init_irq(); | 243 | omap_init_irq(); |
| 179 | omap_gpio_init(); | 244 | omap_gpio_init(); |
| 180 | } | 245 | } |
| @@ -209,6 +274,7 @@ static struct twl4030_hsmmc_info mmc[] __initdata = { | |||
| 209 | .wires = 4, | 274 | .wires = 4, |
| 210 | .gpio_cd = -EINVAL, | 275 | .gpio_cd = -EINVAL, |
| 211 | .gpio_wp = -EINVAL, | 276 | .gpio_wp = -EINVAL, |
| 277 | .transceiver = true, | ||
| 212 | }, | 278 | }, |
| 213 | {} /* Terminator */ | 279 | {} /* Terminator */ |
| 214 | }; | 280 | }; |
| @@ -222,6 +288,8 @@ static void __init overo_init(void) | |||
| 222 | omap_serial_init(); | 288 | omap_serial_init(); |
| 223 | twl4030_mmc_init(mmc); | 289 | twl4030_mmc_init(mmc); |
| 224 | overo_flash_init(); | 290 | overo_flash_init(); |
| 291 | usb_musb_init(); | ||
| 292 | overo_ads7846_init(); | ||
| 225 | 293 | ||
| 226 | if ((gpio_request(OVERO_GPIO_W2W_NRESET, | 294 | if ((gpio_request(OVERO_GPIO_W2W_NRESET, |
| 227 | "OVERO_GPIO_W2W_NRESET") == 0) && | 295 | "OVERO_GPIO_W2W_NRESET") == 0) && |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c new file mode 100644 index 000000000000..a7381729645c --- /dev/null +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
| @@ -0,0 +1,419 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/board-rx51-flash.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Nokia | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/input.h> | ||
| 15 | #include <linux/spi/spi.h> | ||
| 16 | #include <linux/i2c.h> | ||
| 17 | #include <linux/i2c/twl4030.h> | ||
| 18 | #include <linux/clk.h> | ||
| 19 | #include <linux/delay.h> | ||
| 20 | #include <linux/regulator/machine.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | |||
| 23 | #include <mach/mcspi.h> | ||
| 24 | #include <mach/mux.h> | ||
| 25 | #include <mach/board.h> | ||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/dma.h> | ||
| 28 | #include <mach/gpmc.h> | ||
| 29 | #include <mach/keypad.h> | ||
| 30 | |||
| 31 | #include "mmc-twl4030.h" | ||
| 32 | |||
| 33 | |||
| 34 | #define SMC91X_CS 1 | ||
| 35 | #define SMC91X_GPIO_IRQ 54 | ||
| 36 | #define SMC91X_GPIO_RESET 164 | ||
| 37 | #define SMC91X_GPIO_PWRDWN 86 | ||
| 38 | |||
| 39 | static struct resource rx51_smc91x_resources[] = { | ||
| 40 | [0] = { | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, | ||
| 43 | [1] = { | ||
| 44 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | static struct platform_device rx51_smc91x_device = { | ||
| 49 | .name = "smc91x", | ||
| 50 | .id = -1, | ||
| 51 | .num_resources = ARRAY_SIZE(rx51_smc91x_resources), | ||
| 52 | .resource = rx51_smc91x_resources, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static int rx51_keymap[] = { | ||
| 56 | KEY(0, 0, KEY_Q), | ||
| 57 | KEY(0, 1, KEY_W), | ||
| 58 | KEY(0, 2, KEY_E), | ||
| 59 | KEY(0, 3, KEY_R), | ||
| 60 | KEY(0, 4, KEY_T), | ||
| 61 | KEY(0, 5, KEY_Y), | ||
| 62 | KEY(0, 6, KEY_U), | ||
| 63 | KEY(0, 7, KEY_I), | ||
| 64 | KEY(1, 0, KEY_O), | ||
| 65 | KEY(1, 1, KEY_D), | ||
| 66 | KEY(1, 2, KEY_DOT), | ||
| 67 | KEY(1, 3, KEY_V), | ||
| 68 | KEY(1, 4, KEY_DOWN), | ||
| 69 | KEY(2, 0, KEY_P), | ||
| 70 | KEY(2, 1, KEY_F), | ||
| 71 | KEY(2, 2, KEY_UP), | ||
| 72 | KEY(2, 3, KEY_B), | ||
| 73 | KEY(2, 4, KEY_RIGHT), | ||
| 74 | KEY(3, 0, KEY_COMMA), | ||
| 75 | KEY(3, 1, KEY_G), | ||
| 76 | KEY(3, 2, KEY_ENTER), | ||
| 77 | KEY(3, 3, KEY_N), | ||
| 78 | KEY(4, 0, KEY_BACKSPACE), | ||
| 79 | KEY(4, 1, KEY_H), | ||
| 80 | KEY(4, 3, KEY_M), | ||
| 81 | KEY(4, 4, KEY_LEFTCTRL), | ||
| 82 | KEY(5, 1, KEY_J), | ||
| 83 | KEY(5, 2, KEY_Z), | ||
| 84 | KEY(5, 3, KEY_SPACE), | ||
| 85 | KEY(5, 4, KEY_LEFTSHIFT), | ||
| 86 | KEY(6, 0, KEY_A), | ||
| 87 | KEY(6, 1, KEY_K), | ||
| 88 | KEY(6, 2, KEY_X), | ||
| 89 | KEY(6, 3, KEY_SPACE), | ||
| 90 | KEY(6, 4, KEY_FN), | ||
| 91 | KEY(7, 0, KEY_S), | ||
| 92 | KEY(7, 1, KEY_L), | ||
| 93 | KEY(7, 2, KEY_C), | ||
| 94 | KEY(7, 3, KEY_LEFT), | ||
| 95 | KEY(0xff, 0, KEY_F6), | ||
| 96 | KEY(0xff, 1, KEY_F7), | ||
| 97 | KEY(0xff, 2, KEY_F8), | ||
| 98 | KEY(0xff, 4, KEY_F9), | ||
| 99 | KEY(0xff, 5, KEY_F10), | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct twl4030_keypad_data rx51_kp_data = { | ||
| 103 | .rows = 8, | ||
| 104 | .cols = 8, | ||
| 105 | .keymap = rx51_keymap, | ||
| 106 | .keymapsize = ARRAY_SIZE(rx51_keymap), | ||
| 107 | .rep = 1, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static struct platform_device *rx51_peripherals_devices[] = { | ||
| 111 | &rx51_smc91x_device, | ||
| 112 | }; | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Timings are taken from smsc-lan91c96-ms.pdf | ||
| 116 | */ | ||
| 117 | static int smc91x_init_gpmc(int cs) | ||
| 118 | { | ||
| 119 | struct gpmc_timings t; | ||
| 120 | const int t2_r = 45; /* t2 in Figure 12.10 */ | ||
| 121 | const int t2_w = 30; /* t2 in Figure 12.11 */ | ||
| 122 | const int t3 = 15; /* t3 in Figure 12.10 */ | ||
| 123 | const int t5_r = 0; /* t5 in Figure 12.10 */ | ||
| 124 | const int t6_r = 45; /* t6 in Figure 12.10 */ | ||
| 125 | const int t6_w = 0; /* t6 in Figure 12.11 */ | ||
| 126 | const int t7_w = 15; /* t7 in Figure 12.11 */ | ||
| 127 | const int t15 = 12; /* t15 in Figure 12.2 */ | ||
| 128 | const int t20 = 185; /* t20 in Figure 12.2 */ | ||
| 129 | |||
| 130 | memset(&t, 0, sizeof(t)); | ||
| 131 | |||
| 132 | t.cs_on = t15; | ||
| 133 | t.cs_rd_off = t3 + t2_r + t5_r; /* Figure 12.10 */ | ||
| 134 | t.cs_wr_off = t3 + t2_w + t6_w; /* Figure 12.11 */ | ||
| 135 | t.adv_on = t3; /* Figure 12.10 */ | ||
| 136 | t.adv_rd_off = t3 + t2_r; /* Figure 12.10 */ | ||
| 137 | t.adv_wr_off = t3 + t2_w; /* Figure 12.11 */ | ||
| 138 | t.oe_off = t3 + t2_r + t5_r; /* Figure 12.10 */ | ||
| 139 | t.oe_on = t.oe_off - t6_r; /* Figure 12.10 */ | ||
| 140 | t.we_off = t3 + t2_w + t6_w; /* Figure 12.11 */ | ||
| 141 | t.we_on = t.we_off - t7_w; /* Figure 12.11 */ | ||
| 142 | t.rd_cycle = t20; /* Figure 12.2 */ | ||
| 143 | t.wr_cycle = t20; /* Figure 12.4 */ | ||
| 144 | t.access = t3 + t2_r + t5_r; /* Figure 12.10 */ | ||
| 145 | t.wr_access = t3 + t2_w + t6_w; /* Figure 12.11 */ | ||
| 146 | |||
| 147 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16); | ||
| 148 | |||
| 149 | return gpmc_cs_set_timings(cs, &t); | ||
| 150 | } | ||
| 151 | |||
| 152 | static void __init rx51_init_smc91x(void) | ||
| 153 | { | ||
| 154 | unsigned long cs_mem_base; | ||
| 155 | int ret; | ||
| 156 | |||
| 157 | omap_cfg_reg(U8_34XX_GPIO54_DOWN); | ||
| 158 | omap_cfg_reg(G25_34XX_GPIO86_OUT); | ||
| 159 | omap_cfg_reg(H19_34XX_GPIO164_OUT); | ||
| 160 | |||
| 161 | if (gpmc_cs_request(SMC91X_CS, SZ_16M, &cs_mem_base) < 0) { | ||
| 162 | printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); | ||
| 163 | return; | ||
| 164 | } | ||
| 165 | |||
| 166 | rx51_smc91x_resources[0].start = cs_mem_base + 0x300; | ||
| 167 | rx51_smc91x_resources[0].end = cs_mem_base + 0x30f; | ||
| 168 | |||
| 169 | smc91x_init_gpmc(SMC91X_CS); | ||
| 170 | |||
| 171 | if (gpio_request(SMC91X_GPIO_IRQ, "SMC91X irq") < 0) | ||
| 172 | goto free1; | ||
| 173 | |||
| 174 | gpio_direction_input(SMC91X_GPIO_IRQ); | ||
| 175 | rx51_smc91x_resources[1].start = gpio_to_irq(SMC91X_GPIO_IRQ); | ||
| 176 | |||
| 177 | ret = gpio_request(SMC91X_GPIO_PWRDWN, "SMC91X powerdown"); | ||
| 178 | if (ret) | ||
| 179 | goto free2; | ||
| 180 | gpio_direction_output(SMC91X_GPIO_PWRDWN, 0); | ||
| 181 | |||
| 182 | ret = gpio_request(SMC91X_GPIO_RESET, "SMC91X reset"); | ||
| 183 | if (ret) | ||
| 184 | goto free3; | ||
| 185 | gpio_direction_output(SMC91X_GPIO_RESET, 0); | ||
| 186 | gpio_set_value(SMC91X_GPIO_RESET, 1); | ||
| 187 | msleep(100); | ||
| 188 | gpio_set_value(SMC91X_GPIO_RESET, 0); | ||
| 189 | |||
| 190 | return; | ||
| 191 | |||
| 192 | free3: | ||
| 193 | gpio_free(SMC91X_GPIO_PWRDWN); | ||
| 194 | free2: | ||
| 195 | gpio_free(SMC91X_GPIO_IRQ); | ||
| 196 | free1: | ||
| 197 | gpmc_cs_free(SMC91X_CS); | ||
| 198 | |||
| 199 | printk(KERN_ERR "Could not initialize smc91x\n"); | ||
| 200 | } | ||
| 201 | |||
| 202 | static struct twl4030_madc_platform_data rx51_madc_data = { | ||
| 203 | .irq_line = 1, | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct twl4030_hsmmc_info mmc[] = { | ||
| 207 | { | ||
| 208 | .name = "external", | ||
| 209 | .mmc = 1, | ||
| 210 | .wires = 4, | ||
| 211 | .cover_only = true, | ||
| 212 | .gpio_cd = 160, | ||
| 213 | .gpio_wp = -EINVAL, | ||
| 214 | }, | ||
| 215 | { | ||
| 216 | .name = "internal", | ||
| 217 | .mmc = 2, | ||
| 218 | .wires = 8, | ||
| 219 | .gpio_cd = -EINVAL, | ||
| 220 | .gpio_wp = -EINVAL, | ||
| 221 | }, | ||
| 222 | {} /* Terminator */ | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct regulator_consumer_supply rx51_vmmc1_supply = { | ||
| 226 | .supply = "vmmc", | ||
| 227 | }; | ||
| 228 | |||
| 229 | static struct regulator_consumer_supply rx51_vmmc2_supply = { | ||
| 230 | .supply = "vmmc", | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct regulator_consumer_supply rx51_vsim_supply = { | ||
| 234 | .supply = "vmmc_aux", | ||
| 235 | }; | ||
| 236 | |||
| 237 | static struct regulator_init_data rx51_vaux1 = { | ||
| 238 | .constraints = { | ||
| 239 | .name = "V28", | ||
| 240 | .min_uV = 2800000, | ||
| 241 | .max_uV = 2800000, | ||
| 242 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 243 | | REGULATOR_MODE_STANDBY, | ||
| 244 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 245 | | REGULATOR_CHANGE_STATUS, | ||
| 246 | }, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct regulator_init_data rx51_vaux2 = { | ||
| 250 | .constraints = { | ||
| 251 | .name = "VCSI", | ||
| 252 | .min_uV = 1800000, | ||
| 253 | .max_uV = 1800000, | ||
| 254 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 255 | | REGULATOR_MODE_STANDBY, | ||
| 256 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 257 | | REGULATOR_CHANGE_STATUS, | ||
| 258 | }, | ||
| 259 | }; | ||
| 260 | |||
| 261 | /* VAUX3 - adds more power to VIO_18 rail */ | ||
| 262 | static struct regulator_init_data rx51_vaux3 = { | ||
| 263 | .constraints = { | ||
| 264 | .name = "VCAM_DIG_18", | ||
| 265 | .min_uV = 1800000, | ||
| 266 | .max_uV = 1800000, | ||
| 267 | .apply_uV = true, | ||
| 268 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 269 | | REGULATOR_MODE_STANDBY, | ||
| 270 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 271 | | REGULATOR_CHANGE_STATUS, | ||
| 272 | }, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct regulator_init_data rx51_vaux4 = { | ||
| 276 | .constraints = { | ||
| 277 | .name = "VCAM_ANA_28", | ||
| 278 | .min_uV = 2800000, | ||
| 279 | .max_uV = 2800000, | ||
| 280 | .apply_uV = true, | ||
| 281 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 282 | | REGULATOR_MODE_STANDBY, | ||
| 283 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 284 | | REGULATOR_CHANGE_STATUS, | ||
| 285 | }, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static struct regulator_init_data rx51_vmmc1 = { | ||
| 289 | .constraints = { | ||
| 290 | .min_uV = 1850000, | ||
| 291 | .max_uV = 3150000, | ||
| 292 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 293 | | REGULATOR_MODE_STANDBY, | ||
| 294 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 295 | | REGULATOR_CHANGE_MODE | ||
| 296 | | REGULATOR_CHANGE_STATUS, | ||
| 297 | }, | ||
| 298 | .num_consumer_supplies = 1, | ||
| 299 | .consumer_supplies = &rx51_vmmc1_supply, | ||
| 300 | }; | ||
| 301 | |||
| 302 | static struct regulator_init_data rx51_vmmc2 = { | ||
| 303 | .constraints = { | ||
| 304 | .name = "VMMC2_30", | ||
| 305 | .min_uV = 1850000, | ||
| 306 | .max_uV = 3150000, | ||
| 307 | .apply_uV = true, | ||
| 308 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 309 | | REGULATOR_MODE_STANDBY, | ||
| 310 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 311 | | REGULATOR_CHANGE_MODE | ||
| 312 | | REGULATOR_CHANGE_STATUS, | ||
| 313 | }, | ||
| 314 | .num_consumer_supplies = 1, | ||
| 315 | .consumer_supplies = &rx51_vmmc2_supply, | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct regulator_init_data rx51_vsim = { | ||
| 319 | .constraints = { | ||
| 320 | .name = "VMMC2_IO_18", | ||
| 321 | .min_uV = 1800000, | ||
| 322 | .max_uV = 1800000, | ||
| 323 | .apply_uV = true, | ||
| 324 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 325 | | REGULATOR_MODE_STANDBY, | ||
| 326 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 327 | | REGULATOR_CHANGE_STATUS, | ||
| 328 | }, | ||
| 329 | .num_consumer_supplies = 1, | ||
| 330 | .consumer_supplies = &rx51_vsim_supply, | ||
| 331 | }; | ||
| 332 | |||
| 333 | static struct regulator_init_data rx51_vdac = { | ||
| 334 | .constraints = { | ||
| 335 | .min_uV = 1800000, | ||
| 336 | .max_uV = 1800000, | ||
| 337 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 338 | | REGULATOR_MODE_STANDBY, | ||
| 339 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 340 | | REGULATOR_CHANGE_MODE | ||
| 341 | | REGULATOR_CHANGE_STATUS, | ||
| 342 | }, | ||
| 343 | }; | ||
| 344 | |||
| 345 | static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) | ||
| 346 | { | ||
| 347 | /* FIXME this gpio setup is just a placeholder for now */ | ||
| 348 | gpio_request(gpio + 6, "backlight_pwm"); | ||
| 349 | gpio_direction_output(gpio + 6, 0); | ||
| 350 | gpio_request(gpio + 7, "speaker_en"); | ||
| 351 | gpio_direction_output(gpio + 7, 1); | ||
| 352 | |||
| 353 | /* set up MMC adapters, linking their regulators to them */ | ||
| 354 | twl4030_mmc_init(mmc); | ||
| 355 | rx51_vmmc1_supply.dev = mmc[0].dev; | ||
| 356 | rx51_vmmc2_supply.dev = mmc[1].dev; | ||
| 357 | rx51_vsim_supply.dev = mmc[1].dev; | ||
| 358 | |||
| 359 | return 0; | ||
| 360 | } | ||
| 361 | |||
| 362 | static struct twl4030_gpio_platform_data rx51_gpio_data = { | ||
| 363 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 364 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 365 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 366 | .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3) | ||
| 367 | | BIT(4) | BIT(5) | ||
| 368 | | BIT(8) | BIT(9) | BIT(10) | BIT(11) | ||
| 369 | | BIT(12) | BIT(13) | BIT(14) | BIT(15) | ||
| 370 | | BIT(16) | BIT(17) , | ||
| 371 | .setup = rx51_twlgpio_setup, | ||
| 372 | }; | ||
| 373 | |||
| 374 | static struct twl4030_platform_data rx51_twldata = { | ||
| 375 | .irq_base = TWL4030_IRQ_BASE, | ||
| 376 | .irq_end = TWL4030_IRQ_END, | ||
| 377 | |||
| 378 | /* platform_data for children goes here */ | ||
| 379 | .gpio = &rx51_gpio_data, | ||
| 380 | .keypad = &rx51_kp_data, | ||
| 381 | .madc = &rx51_madc_data, | ||
| 382 | |||
| 383 | .vaux1 = &rx51_vaux1, | ||
| 384 | .vaux2 = &rx51_vaux2, | ||
| 385 | .vaux3 = &rx51_vaux3, | ||
| 386 | .vaux4 = &rx51_vaux4, | ||
| 387 | .vmmc1 = &rx51_vmmc1, | ||
| 388 | .vmmc2 = &rx51_vmmc2, | ||
| 389 | .vsim = &rx51_vsim, | ||
| 390 | .vdac = &rx51_vdac, | ||
| 391 | }; | ||
| 392 | |||
| 393 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { | ||
| 394 | { | ||
| 395 | I2C_BOARD_INFO("twl5030", 0x48), | ||
| 396 | .flags = I2C_CLIENT_WAKE, | ||
| 397 | .irq = INT_34XX_SYS_NIRQ, | ||
| 398 | .platform_data = &rx51_twldata, | ||
| 399 | }, | ||
| 400 | }; | ||
| 401 | |||
| 402 | static int __init rx51_i2c_init(void) | ||
| 403 | { | ||
| 404 | omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1, | ||
| 405 | ARRAY_SIZE(rx51_peripherals_i2c_board_info_1)); | ||
| 406 | omap_register_i2c_bus(2, 100, NULL, 0); | ||
| 407 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 408 | return 0; | ||
| 409 | } | ||
| 410 | |||
| 411 | |||
| 412 | void __init rx51_peripherals_init(void) | ||
| 413 | { | ||
| 414 | platform_add_devices(rx51_peripherals_devices, | ||
| 415 | ARRAY_SIZE(rx51_peripherals_devices)); | ||
| 416 | rx51_i2c_init(); | ||
| 417 | rx51_init_smc91x(); | ||
| 418 | } | ||
| 419 | |||
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c new file mode 100644 index 000000000000..3a0daac6c839 --- /dev/null +++ b/arch/arm/mach-omap2/board-rx51.c | |||
| @@ -0,0 +1,96 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/board-rx51.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007, 2008 Nokia | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/delay.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include <linux/clk.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/gpio.h> | ||
| 20 | |||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <asm/mach-types.h> | ||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | #include <asm/mach/map.h> | ||
| 25 | |||
| 26 | #include <mach/mcspi.h> | ||
| 27 | #include <mach/mux.h> | ||
| 28 | #include <mach/board.h> | ||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/keypad.h> | ||
| 31 | #include <mach/dma.h> | ||
| 32 | #include <mach/gpmc.h> | ||
| 33 | #include <mach/usb.h> | ||
| 34 | |||
| 35 | static struct omap_uart_config rx51_uart_config = { | ||
| 36 | .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct omap_lcd_config rx51_lcd_config = { | ||
| 40 | .ctrl_name = "internal", | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct omap_fbmem_config rx51_fbmem0_config = { | ||
| 44 | .size = 752 * 1024, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct omap_fbmem_config rx51_fbmem1_config = { | ||
| 48 | .size = 752 * 1024, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct omap_fbmem_config rx51_fbmem2_config = { | ||
| 52 | .size = 752 * 1024, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct omap_board_config_kernel rx51_config[] = { | ||
| 56 | { OMAP_TAG_UART, &rx51_uart_config }, | ||
| 57 | { OMAP_TAG_FBMEM, &rx51_fbmem0_config }, | ||
| 58 | { OMAP_TAG_FBMEM, &rx51_fbmem1_config }, | ||
| 59 | { OMAP_TAG_FBMEM, &rx51_fbmem2_config }, | ||
| 60 | { OMAP_TAG_LCD, &rx51_lcd_config }, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static void __init rx51_init_irq(void) | ||
| 64 | { | ||
| 65 | omap2_init_common_hw(NULL); | ||
| 66 | omap_init_irq(); | ||
| 67 | omap_gpio_init(); | ||
| 68 | } | ||
| 69 | |||
| 70 | extern void __init rx51_peripherals_init(void); | ||
| 71 | |||
| 72 | static void __init rx51_init(void) | ||
| 73 | { | ||
| 74 | omap_board_config = rx51_config; | ||
| 75 | omap_board_config_size = ARRAY_SIZE(rx51_config); | ||
| 76 | omap_serial_init(); | ||
| 77 | usb_musb_init(); | ||
| 78 | rx51_peripherals_init(); | ||
| 79 | } | ||
| 80 | |||
| 81 | static void __init rx51_map_io(void) | ||
| 82 | { | ||
| 83 | omap2_set_globals_343x(); | ||
| 84 | omap2_map_common_io(); | ||
| 85 | } | ||
| 86 | |||
| 87 | MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") | ||
| 88 | /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ | ||
| 89 | .phys_io = 0x48000000, | ||
| 90 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | ||
| 91 | .boot_params = 0x80000100, | ||
| 92 | .map_io = rx51_map_io, | ||
| 93 | .init_irq = rx51_init_irq, | ||
| 94 | .init_machine = rx51_init, | ||
| 95 | .timer = &omap_timer, | ||
| 96 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ce4d46a4a838..4247a1534411 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
| @@ -26,11 +26,10 @@ | |||
| 26 | 26 | ||
| 27 | #include <mach/clock.h> | 27 | #include <mach/clock.h> |
| 28 | #include <mach/clockdomain.h> | 28 | #include <mach/clockdomain.h> |
| 29 | #include <mach/sram.h> | ||
| 30 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
| 31 | #include <asm/div64.h> | 30 | #include <asm/div64.h> |
| 32 | 31 | ||
| 33 | #include "memory.h" | 32 | #include <mach/sdrc.h> |
| 34 | #include "sdrc.h" | 33 | #include "sdrc.h" |
| 35 | #include "clock.h" | 34 | #include "clock.h" |
| 36 | #include "prm.h" | 35 | #include "prm.h" |
| @@ -46,7 +45,7 @@ | |||
| 46 | #define DPLL_MIN_DIVIDER 1 | 45 | #define DPLL_MIN_DIVIDER 1 |
| 47 | 46 | ||
| 48 | /* Possible error results from _dpll_test_mult */ | 47 | /* Possible error results from _dpll_test_mult */ |
| 49 | #define DPLL_MULT_UNDERFLOW (1 << 0) | 48 | #define DPLL_MULT_UNDERFLOW -1 |
| 50 | 49 | ||
| 51 | /* | 50 | /* |
| 52 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. | 51 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. |
| @@ -59,6 +58,16 @@ | |||
| 59 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ | 58 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ |
| 60 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) | 59 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) |
| 61 | 60 | ||
| 61 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ | ||
| 62 | #define DPLL_FINT_BAND1_MIN 750000 | ||
| 63 | #define DPLL_FINT_BAND1_MAX 2100000 | ||
| 64 | #define DPLL_FINT_BAND2_MIN 7500000 | ||
| 65 | #define DPLL_FINT_BAND2_MAX 21000000 | ||
| 66 | |||
| 67 | /* _dpll_test_fint() return codes */ | ||
| 68 | #define DPLL_FINT_UNDERFLOW -1 | ||
| 69 | #define DPLL_FINT_INVALID -2 | ||
| 70 | |||
| 62 | u8 cpu_mask; | 71 | u8 cpu_mask; |
| 63 | 72 | ||
| 64 | /*------------------------------------------------------------------------- | 73 | /*------------------------------------------------------------------------- |
| @@ -66,6 +75,74 @@ u8 cpu_mask; | |||
| 66 | *-------------------------------------------------------------------------*/ | 75 | *-------------------------------------------------------------------------*/ |
| 67 | 76 | ||
| 68 | /** | 77 | /** |
| 78 | * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware | ||
| 79 | * @clk: struct clk * | ||
| 80 | * | ||
| 81 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | ||
| 82 | * don't take effect until the VALID_CONFIG bit is written, write the | ||
| 83 | * VALID_CONFIG bit and wait for the write to complete. No return value. | ||
| 84 | */ | ||
| 85 | static void _omap2xxx_clk_commit(struct clk *clk) | ||
| 86 | { | ||
| 87 | if (!cpu_is_omap24xx()) | ||
| 88 | return; | ||
| 89 | |||
| 90 | if (!(clk->flags & DELAYED_APP)) | ||
| 91 | return; | ||
| 92 | |||
| 93 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | ||
| 94 | OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 95 | /* OCP barrier */ | ||
| 96 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 97 | } | ||
| 98 | |||
| 99 | /* | ||
| 100 | * _dpll_test_fint - test whether an Fint value is valid for the DPLL | ||
| 101 | * @clk: DPLL struct clk to test | ||
| 102 | * @n: divider value (N) to test | ||
| 103 | * | ||
| 104 | * Tests whether a particular divider @n will result in a valid DPLL | ||
| 105 | * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter | ||
| 106 | * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate | ||
| 107 | * (assuming that it is counting N upwards), or -2 if the enclosing loop | ||
| 108 | * should skip to the next iteration (again assuming N is increasing). | ||
| 109 | */ | ||
| 110 | static int _dpll_test_fint(struct clk *clk, u8 n) | ||
| 111 | { | ||
| 112 | struct dpll_data *dd; | ||
| 113 | long fint; | ||
| 114 | int ret = 0; | ||
| 115 | |||
| 116 | dd = clk->dpll_data; | ||
| 117 | |||
| 118 | /* DPLL divider must result in a valid jitter correction val */ | ||
| 119 | fint = clk->parent->rate / (n + 1); | ||
| 120 | if (fint < DPLL_FINT_BAND1_MIN) { | ||
| 121 | |||
| 122 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 123 | "lowering max_divider\n", n); | ||
| 124 | dd->max_divider = n; | ||
| 125 | ret = DPLL_FINT_UNDERFLOW; | ||
| 126 | |||
| 127 | } else if (fint > DPLL_FINT_BAND1_MAX && | ||
| 128 | fint < DPLL_FINT_BAND2_MIN) { | ||
| 129 | |||
| 130 | pr_debug("rejecting n=%d due to Fint failure\n", n); | ||
| 131 | ret = DPLL_FINT_INVALID; | ||
| 132 | |||
| 133 | } else if (fint > DPLL_FINT_BAND2_MAX) { | ||
| 134 | |||
| 135 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 136 | "boosting min_divider\n", n); | ||
| 137 | dd->min_divider = n; | ||
| 138 | ret = DPLL_FINT_INVALID; | ||
| 139 | |||
| 140 | } | ||
| 141 | |||
| 142 | return ret; | ||
| 143 | } | ||
| 144 | |||
| 145 | /** | ||
| 69 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | 146 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk |
| 70 | * @clk: OMAP clock struct ptr to use | 147 | * @clk: OMAP clock struct ptr to use |
| 71 | * | 148 | * |
| @@ -120,7 +197,7 @@ void omap2_init_clksel_parent(struct clk *clk) | |||
| 120 | clk->name, clks->parent->name, | 197 | clk->name, clks->parent->name, |
| 121 | ((clk->parent) ? | 198 | ((clk->parent) ? |
| 122 | clk->parent->name : "NULL")); | 199 | clk->parent->name : "NULL")); |
| 123 | clk->parent = clks->parent; | 200 | clk_reparent(clk, clks->parent); |
| 124 | }; | 201 | }; |
| 125 | found = 1; | 202 | found = 1; |
| 126 | } | 203 | } |
| @@ -134,25 +211,52 @@ void omap2_init_clksel_parent(struct clk *clk) | |||
| 134 | return; | 211 | return; |
| 135 | } | 212 | } |
| 136 | 213 | ||
| 137 | /* Returns the DPLL rate */ | 214 | /** |
| 215 | * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate | ||
| 216 | * @clk: struct clk * of a DPLL | ||
| 217 | * | ||
| 218 | * DPLLs can be locked or bypassed - basically, enabled or disabled. | ||
| 219 | * When locked, the DPLL output depends on the M and N values. When | ||
| 220 | * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock | ||
| 221 | * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and | ||
| 222 | * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively | ||
| 223 | * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. | ||
| 224 | * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is | ||
| 225 | * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 | ||
| 226 | * if the clock @clk is not a DPLL. | ||
| 227 | */ | ||
| 138 | u32 omap2_get_dpll_rate(struct clk *clk) | 228 | u32 omap2_get_dpll_rate(struct clk *clk) |
| 139 | { | 229 | { |
| 140 | long long dpll_clk; | 230 | long long dpll_clk; |
| 141 | u32 dpll_mult, dpll_div, dpll; | 231 | u32 dpll_mult, dpll_div, v; |
| 142 | struct dpll_data *dd; | 232 | struct dpll_data *dd; |
| 143 | 233 | ||
| 144 | dd = clk->dpll_data; | 234 | dd = clk->dpll_data; |
| 145 | /* REVISIT: What do we return on error? */ | ||
| 146 | if (!dd) | 235 | if (!dd) |
| 147 | return 0; | 236 | return 0; |
| 148 | 237 | ||
| 149 | dpll = __raw_readl(dd->mult_div1_reg); | 238 | /* Return bypass rate if DPLL is bypassed */ |
| 150 | dpll_mult = dpll & dd->mult_mask; | 239 | v = __raw_readl(dd->control_reg); |
| 240 | v &= dd->enable_mask; | ||
| 241 | v >>= __ffs(dd->enable_mask); | ||
| 242 | |||
| 243 | if (cpu_is_omap24xx()) { | ||
| 244 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | ||
| 245 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
| 246 | return dd->clk_bypass->rate; | ||
| 247 | } else if (cpu_is_omap34xx()) { | ||
| 248 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
| 249 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
| 250 | return dd->clk_bypass->rate; | ||
| 251 | } | ||
| 252 | |||
| 253 | v = __raw_readl(dd->mult_div1_reg); | ||
| 254 | dpll_mult = v & dd->mult_mask; | ||
| 151 | dpll_mult >>= __ffs(dd->mult_mask); | 255 | dpll_mult >>= __ffs(dd->mult_mask); |
| 152 | dpll_div = dpll & dd->div1_mask; | 256 | dpll_div = v & dd->div1_mask; |
| 153 | dpll_div >>= __ffs(dd->div1_mask); | 257 | dpll_div >>= __ffs(dd->div1_mask); |
| 154 | 258 | ||
| 155 | dpll_clk = (long long)clk->parent->rate * dpll_mult; | 259 | dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; |
| 156 | do_div(dpll_clk, dpll_div + 1); | 260 | do_div(dpll_clk, dpll_div + 1); |
| 157 | 261 | ||
| 158 | return dpll_clk; | 262 | return dpll_clk; |
| @@ -162,14 +266,11 @@ u32 omap2_get_dpll_rate(struct clk *clk) | |||
| 162 | * Used for clocks that have the same value as the parent clock, | 266 | * Used for clocks that have the same value as the parent clock, |
| 163 | * divided by some factor | 267 | * divided by some factor |
| 164 | */ | 268 | */ |
| 165 | void omap2_fixed_divisor_recalc(struct clk *clk) | 269 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk) |
| 166 | { | 270 | { |
| 167 | WARN_ON(!clk->fixed_div); | 271 | WARN_ON(!clk->fixed_div); |
| 168 | 272 | ||
| 169 | clk->rate = clk->parent->rate / clk->fixed_div; | 273 | return clk->parent->rate / clk->fixed_div; |
| 170 | |||
| 171 | if (clk->flags & RATE_PROPAGATES) | ||
| 172 | propagate_rate(clk); | ||
| 173 | } | 274 | } |
| 174 | 275 | ||
| 175 | /** | 276 | /** |
| @@ -190,11 +291,10 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) | |||
| 190 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | 291 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. |
| 191 | * 34xx reverses this, just to keep us on our toes | 292 | * 34xx reverses this, just to keep us on our toes |
| 192 | */ | 293 | */ |
| 193 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { | 294 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) |
| 194 | ena = mask; | 295 | ena = mask; |
| 195 | } else if (cpu_mask & RATE_IN_343X) { | 296 | else if (cpu_mask & RATE_IN_343X) |
| 196 | ena = 0; | 297 | ena = 0; |
| 197 | } | ||
| 198 | 298 | ||
| 199 | /* Wait for lock */ | 299 | /* Wait for lock */ |
| 200 | while (((__raw_readl(reg) & mask) != ena) && | 300 | while (((__raw_readl(reg) & mask) != ena) && |
| @@ -228,31 +328,12 @@ static void omap2_clk_wait_ready(struct clk *clk) | |||
| 228 | * it and pull it into struct clk itself somehow. | 328 | * it and pull it into struct clk itself somehow. |
| 229 | */ | 329 | */ |
| 230 | reg = clk->enable_reg; | 330 | reg = clk->enable_reg; |
| 231 | if ((((u32)reg & 0xff) >= CM_FCLKEN1) && | ||
| 232 | (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) | ||
| 233 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ | ||
| 234 | else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && | ||
| 235 | (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) | ||
| 236 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ | ||
| 237 | else | ||
| 238 | return; | ||
| 239 | 331 | ||
| 240 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | 332 | /* |
| 241 | /* No check for DSS or cam clocks */ | 333 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
| 242 | if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ | 334 | * it's just a matter of XORing the bits. |
| 243 | if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || | 335 | */ |
| 244 | clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || | 336 | other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
| 245 | clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) | ||
| 246 | return; | ||
| 247 | } | ||
| 248 | |||
| 249 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | ||
| 250 | /* OMAP3: ignore DSS-mod clocks */ | ||
| 251 | if (cpu_is_omap34xx() && | ||
| 252 | (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) || | ||
| 253 | ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) && | ||
| 254 | clk->enable_bit == OMAP3430_EN_SSI_SHIFT))) | ||
| 255 | return; | ||
| 256 | 337 | ||
| 257 | /* Check if both functional and interface clocks | 338 | /* Check if both functional and interface clocks |
| 258 | * are running. */ | 339 | * are running. */ |
| @@ -264,18 +345,9 @@ static void omap2_clk_wait_ready(struct clk *clk) | |||
| 264 | omap2_wait_clock_ready(st_reg, bit, clk->name); | 345 | omap2_wait_clock_ready(st_reg, bit, clk->name); |
| 265 | } | 346 | } |
| 266 | 347 | ||
| 267 | /* Enables clock without considering parent dependencies or use count | 348 | static int omap2_dflt_clk_enable(struct clk *clk) |
| 268 | * REVISIT: Maybe change this to use clk->enable like on omap1? | ||
| 269 | */ | ||
| 270 | int _omap2_clk_enable(struct clk *clk) | ||
| 271 | { | 349 | { |
| 272 | u32 regval32; | 350 | u32 v; |
| 273 | |||
| 274 | if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) | ||
| 275 | return 0; | ||
| 276 | |||
| 277 | if (clk->enable) | ||
| 278 | return clk->enable(clk); | ||
| 279 | 351 | ||
| 280 | if (unlikely(clk->enable_reg == NULL)) { | 352 | if (unlikely(clk->enable_reg == NULL)) { |
| 281 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | 353 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| @@ -283,33 +355,38 @@ int _omap2_clk_enable(struct clk *clk) | |||
| 283 | return 0; /* REVISIT: -EINVAL */ | 355 | return 0; /* REVISIT: -EINVAL */ |
| 284 | } | 356 | } |
| 285 | 357 | ||
| 286 | regval32 = __raw_readl(clk->enable_reg); | 358 | v = __raw_readl(clk->enable_reg); |
| 287 | if (clk->flags & INVERT_ENABLE) | 359 | if (clk->flags & INVERT_ENABLE) |
| 288 | regval32 &= ~(1 << clk->enable_bit); | 360 | v &= ~(1 << clk->enable_bit); |
| 289 | else | 361 | else |
| 290 | regval32 |= (1 << clk->enable_bit); | 362 | v |= (1 << clk->enable_bit); |
| 291 | __raw_writel(regval32, clk->enable_reg); | 363 | __raw_writel(v, clk->enable_reg); |
| 292 | wmb(); | 364 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
| 293 | |||
| 294 | omap2_clk_wait_ready(clk); | ||
| 295 | 365 | ||
| 296 | return 0; | 366 | return 0; |
| 297 | } | 367 | } |
| 298 | 368 | ||
| 299 | /* Disables clock without considering parent dependencies or use count */ | 369 | static int omap2_dflt_clk_enable_wait(struct clk *clk) |
| 300 | void _omap2_clk_disable(struct clk *clk) | ||
| 301 | { | 370 | { |
| 302 | u32 regval32; | 371 | int ret; |
| 303 | |||
| 304 | if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) | ||
| 305 | return; | ||
| 306 | 372 | ||
| 307 | if (clk->disable) { | 373 | if (!clk->enable_reg) { |
| 308 | clk->disable(clk); | 374 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 309 | return; | 375 | clk->name); |
| 376 | return 0; /* REVISIT: -EINVAL */ | ||
| 310 | } | 377 | } |
| 311 | 378 | ||
| 312 | if (clk->enable_reg == NULL) { | 379 | ret = omap2_dflt_clk_enable(clk); |
| 380 | if (ret == 0) | ||
| 381 | omap2_clk_wait_ready(clk); | ||
| 382 | return ret; | ||
| 383 | } | ||
| 384 | |||
| 385 | static void omap2_dflt_clk_disable(struct clk *clk) | ||
| 386 | { | ||
| 387 | u32 v; | ||
| 388 | |||
| 389 | if (!clk->enable_reg) { | ||
| 313 | /* | 390 | /* |
| 314 | * 'Independent' here refers to a clock which is not | 391 | * 'Independent' here refers to a clock which is not |
| 315 | * controlled by its parent. | 392 | * controlled by its parent. |
| @@ -319,20 +396,44 @@ void _omap2_clk_disable(struct clk *clk) | |||
| 319 | return; | 396 | return; |
| 320 | } | 397 | } |
| 321 | 398 | ||
| 322 | regval32 = __raw_readl(clk->enable_reg); | 399 | v = __raw_readl(clk->enable_reg); |
| 323 | if (clk->flags & INVERT_ENABLE) | 400 | if (clk->flags & INVERT_ENABLE) |
| 324 | regval32 |= (1 << clk->enable_bit); | 401 | v |= (1 << clk->enable_bit); |
| 325 | else | 402 | else |
| 326 | regval32 &= ~(1 << clk->enable_bit); | 403 | v &= ~(1 << clk->enable_bit); |
| 327 | __raw_writel(regval32, clk->enable_reg); | 404 | __raw_writel(v, clk->enable_reg); |
| 328 | wmb(); | 405 | /* No OCP barrier needed here since it is a disable operation */ |
| 406 | } | ||
| 407 | |||
| 408 | const struct clkops clkops_omap2_dflt_wait = { | ||
| 409 | .enable = omap2_dflt_clk_enable_wait, | ||
| 410 | .disable = omap2_dflt_clk_disable, | ||
| 411 | }; | ||
| 412 | |||
| 413 | const struct clkops clkops_omap2_dflt = { | ||
| 414 | .enable = omap2_dflt_clk_enable, | ||
| 415 | .disable = omap2_dflt_clk_disable, | ||
| 416 | }; | ||
| 417 | |||
| 418 | /* Enables clock without considering parent dependencies or use count | ||
| 419 | * REVISIT: Maybe change this to use clk->enable like on omap1? | ||
| 420 | */ | ||
| 421 | static int _omap2_clk_enable(struct clk *clk) | ||
| 422 | { | ||
| 423 | return clk->ops->enable(clk); | ||
| 424 | } | ||
| 425 | |||
| 426 | /* Disables clock without considering parent dependencies or use count */ | ||
| 427 | static void _omap2_clk_disable(struct clk *clk) | ||
| 428 | { | ||
| 429 | clk->ops->disable(clk); | ||
| 329 | } | 430 | } |
| 330 | 431 | ||
| 331 | void omap2_clk_disable(struct clk *clk) | 432 | void omap2_clk_disable(struct clk *clk) |
| 332 | { | 433 | { |
| 333 | if (clk->usecount > 0 && !(--clk->usecount)) { | 434 | if (clk->usecount > 0 && !(--clk->usecount)) { |
| 334 | _omap2_clk_disable(clk); | 435 | _omap2_clk_disable(clk); |
| 335 | if (likely((u32)clk->parent)) | 436 | if (clk->parent) |
| 336 | omap2_clk_disable(clk->parent); | 437 | omap2_clk_disable(clk->parent); |
| 337 | if (clk->clkdm) | 438 | if (clk->clkdm) |
| 338 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 439 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
| @@ -345,30 +446,29 @@ int omap2_clk_enable(struct clk *clk) | |||
| 345 | int ret = 0; | 446 | int ret = 0; |
| 346 | 447 | ||
| 347 | if (clk->usecount++ == 0) { | 448 | if (clk->usecount++ == 0) { |
| 348 | if (likely((u32)clk->parent)) | ||
| 349 | ret = omap2_clk_enable(clk->parent); | ||
| 350 | |||
| 351 | if (unlikely(ret != 0)) { | ||
| 352 | clk->usecount--; | ||
| 353 | return ret; | ||
| 354 | } | ||
| 355 | |||
| 356 | if (clk->clkdm) | 449 | if (clk->clkdm) |
| 357 | omap2_clkdm_clk_enable(clk->clkdm, clk); | 450 | omap2_clkdm_clk_enable(clk->clkdm, clk); |
| 358 | 451 | ||
| 359 | ret = _omap2_clk_enable(clk); | 452 | if (clk->parent) { |
| 360 | 453 | ret = omap2_clk_enable(clk->parent); | |
| 361 | if (unlikely(ret != 0)) { | 454 | if (ret) |
| 362 | if (clk->clkdm) | 455 | goto err; |
| 363 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 456 | } |
| 364 | 457 | ||
| 365 | if (clk->parent) { | 458 | ret = _omap2_clk_enable(clk); |
| 459 | if (ret) { | ||
| 460 | if (clk->parent) | ||
| 366 | omap2_clk_disable(clk->parent); | 461 | omap2_clk_disable(clk->parent); |
| 367 | clk->usecount--; | 462 | |
| 368 | } | 463 | goto err; |
| 369 | } | 464 | } |
| 370 | } | 465 | } |
| 466 | return ret; | ||
| 371 | 467 | ||
| 468 | err: | ||
| 469 | if (clk->clkdm) | ||
| 470 | omap2_clkdm_clk_disable(clk->clkdm, clk); | ||
| 471 | clk->usecount--; | ||
| 372 | return ret; | 472 | return ret; |
| 373 | } | 473 | } |
| 374 | 474 | ||
| @@ -376,24 +476,22 @@ int omap2_clk_enable(struct clk *clk) | |||
| 376 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | 476 | * Used for clocks that are part of CLKSEL_xyz governed clocks. |
| 377 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | 477 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? |
| 378 | */ | 478 | */ |
| 379 | void omap2_clksel_recalc(struct clk *clk) | 479 | unsigned long omap2_clksel_recalc(struct clk *clk) |
| 380 | { | 480 | { |
| 481 | unsigned long rate; | ||
| 381 | u32 div = 0; | 482 | u32 div = 0; |
| 382 | 483 | ||
| 383 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); | 484 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); |
| 384 | 485 | ||
| 385 | div = omap2_clksel_get_divisor(clk); | 486 | div = omap2_clksel_get_divisor(clk); |
| 386 | if (div == 0) | 487 | if (div == 0) |
| 387 | return; | 488 | return clk->rate; |
| 388 | 489 | ||
| 389 | if (unlikely(clk->rate == clk->parent->rate / div)) | 490 | rate = clk->parent->rate / div; |
| 390 | return; | ||
| 391 | clk->rate = clk->parent->rate / div; | ||
| 392 | 491 | ||
| 393 | pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); | 492 | pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); |
| 394 | 493 | ||
| 395 | if (unlikely(clk->flags & RATE_PROPAGATES)) | 494 | return rate; |
| 396 | propagate_rate(clk); | ||
| 397 | } | 495 | } |
| 398 | 496 | ||
| 399 | /** | 497 | /** |
| @@ -405,8 +503,8 @@ void omap2_clksel_recalc(struct clk *clk) | |||
| 405 | * the element associated with the supplied parent clock address. | 503 | * the element associated with the supplied parent clock address. |
| 406 | * Returns a pointer to the struct clksel on success or NULL on error. | 504 | * Returns a pointer to the struct clksel on success or NULL on error. |
| 407 | */ | 505 | */ |
| 408 | const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, | 506 | static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, |
| 409 | struct clk *src_clk) | 507 | struct clk *src_clk) |
| 410 | { | 508 | { |
| 411 | const struct clksel *clks; | 509 | const struct clksel *clks; |
| 412 | 510 | ||
| @@ -455,7 +553,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
| 455 | *new_div = 1; | 553 | *new_div = 1; |
| 456 | 554 | ||
| 457 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | 555 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 458 | if (clks == NULL) | 556 | if (!clks) |
| 459 | return ~0; | 557 | return ~0; |
| 460 | 558 | ||
| 461 | for (clkr = clks->rates; clkr->div; clkr++) { | 559 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -514,7 +612,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) | |||
| 514 | /* Given a clock and a rate apply a clock specific rounding function */ | 612 | /* Given a clock and a rate apply a clock specific rounding function */ |
| 515 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | 613 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) |
| 516 | { | 614 | { |
| 517 | if (clk->round_rate != NULL) | 615 | if (clk->round_rate) |
| 518 | return clk->round_rate(clk, rate); | 616 | return clk->round_rate(clk, rate); |
| 519 | 617 | ||
| 520 | if (clk->flags & RATE_FIXED) | 618 | if (clk->flags & RATE_FIXED) |
| @@ -540,7 +638,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) | |||
| 540 | const struct clksel_rate *clkr; | 638 | const struct clksel_rate *clkr; |
| 541 | 639 | ||
| 542 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | 640 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 543 | if (clks == NULL) | 641 | if (!clks) |
| 544 | return 0; | 642 | return 0; |
| 545 | 643 | ||
| 546 | for (clkr = clks->rates; clkr->div; clkr++) { | 644 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -576,7 +674,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | |||
| 576 | WARN_ON(div == 0); | 674 | WARN_ON(div == 0); |
| 577 | 675 | ||
| 578 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | 676 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 579 | if (clks == NULL) | 677 | if (!clks) |
| 580 | return ~0; | 678 | return ~0; |
| 581 | 679 | ||
| 582 | for (clkr = clks->rates; clkr->div; clkr++) { | 680 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -595,23 +693,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | |||
| 595 | } | 693 | } |
| 596 | 694 | ||
| 597 | /** | 695 | /** |
| 598 | * omap2_get_clksel - find clksel register addr & field mask for a clk | ||
| 599 | * @clk: struct clk to use | ||
| 600 | * @field_mask: ptr to u32 to store the register field mask | ||
| 601 | * | ||
| 602 | * Returns the address of the clksel register upon success or NULL on error. | ||
| 603 | */ | ||
| 604 | void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) | ||
| 605 | { | ||
| 606 | if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL))) | ||
| 607 | return NULL; | ||
| 608 | |||
| 609 | *field_mask = clk->clksel_mask; | ||
| 610 | |||
| 611 | return clk->clksel_reg; | ||
| 612 | } | ||
| 613 | |||
| 614 | /** | ||
| 615 | * omap2_clksel_get_divisor - get current divider applied to parent clock. | 696 | * omap2_clksel_get_divisor - get current divider applied to parent clock. |
| 616 | * @clk: OMAP struct clk to use. | 697 | * @clk: OMAP struct clk to use. |
| 617 | * | 698 | * |
| @@ -619,49 +700,41 @@ void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) | |||
| 619 | */ | 700 | */ |
| 620 | u32 omap2_clksel_get_divisor(struct clk *clk) | 701 | u32 omap2_clksel_get_divisor(struct clk *clk) |
| 621 | { | 702 | { |
| 622 | u32 field_mask, field_val; | 703 | u32 v; |
| 623 | void __iomem *div_addr; | ||
| 624 | 704 | ||
| 625 | div_addr = omap2_get_clksel(clk, &field_mask); | 705 | if (!clk->clksel_mask) |
| 626 | if (div_addr == NULL) | ||
| 627 | return 0; | 706 | return 0; |
| 628 | 707 | ||
| 629 | field_val = __raw_readl(div_addr) & field_mask; | 708 | v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; |
| 630 | field_val >>= __ffs(field_mask); | 709 | v >>= __ffs(clk->clksel_mask); |
| 631 | 710 | ||
| 632 | return omap2_clksel_to_divisor(clk, field_val); | 711 | return omap2_clksel_to_divisor(clk, v); |
| 633 | } | 712 | } |
| 634 | 713 | ||
| 635 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | 714 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) |
| 636 | { | 715 | { |
| 637 | u32 field_mask, field_val, reg_val, validrate, new_div = 0; | 716 | u32 v, field_val, validrate, new_div = 0; |
| 638 | void __iomem *div_addr; | ||
| 639 | 717 | ||
| 640 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | 718 | if (!clk->clksel_mask) |
| 641 | if (validrate != rate) | ||
| 642 | return -EINVAL; | 719 | return -EINVAL; |
| 643 | 720 | ||
| 644 | div_addr = omap2_get_clksel(clk, &field_mask); | 721 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
| 645 | if (div_addr == NULL) | 722 | if (validrate != rate) |
| 646 | return -EINVAL; | 723 | return -EINVAL; |
| 647 | 724 | ||
| 648 | field_val = omap2_divisor_to_clksel(clk, new_div); | 725 | field_val = omap2_divisor_to_clksel(clk, new_div); |
| 649 | if (field_val == ~0) | 726 | if (field_val == ~0) |
| 650 | return -EINVAL; | 727 | return -EINVAL; |
| 651 | 728 | ||
| 652 | reg_val = __raw_readl(div_addr); | 729 | v = __raw_readl(clk->clksel_reg); |
| 653 | reg_val &= ~field_mask; | 730 | v &= ~clk->clksel_mask; |
| 654 | reg_val |= (field_val << __ffs(field_mask)); | 731 | v |= field_val << __ffs(clk->clksel_mask); |
| 655 | __raw_writel(reg_val, div_addr); | 732 | __raw_writel(v, clk->clksel_reg); |
| 656 | wmb(); | 733 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ |
| 657 | 734 | ||
| 658 | clk->rate = clk->parent->rate / new_div; | 735 | clk->rate = clk->parent->rate / new_div; |
| 659 | 736 | ||
| 660 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | 737 | _omap2xxx_clk_commit(clk); |
| 661 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, | ||
| 662 | OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 663 | wmb(); | ||
| 664 | } | ||
| 665 | 738 | ||
| 666 | return 0; | 739 | return 0; |
| 667 | } | 740 | } |
| @@ -680,31 +753,24 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 680 | return -EINVAL; | 753 | return -EINVAL; |
| 681 | 754 | ||
| 682 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | 755 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
| 683 | if (clk->set_rate != NULL) | 756 | if (clk->set_rate) |
| 684 | ret = clk->set_rate(clk, rate); | 757 | ret = clk->set_rate(clk, rate); |
| 685 | 758 | ||
| 686 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | ||
| 687 | propagate_rate(clk); | ||
| 688 | |||
| 689 | return ret; | 759 | return ret; |
| 690 | } | 760 | } |
| 691 | 761 | ||
| 692 | /* | 762 | /* |
| 693 | * Converts encoded control register address into a full address | 763 | * Converts encoded control register address into a full address |
| 694 | * On error, *src_addr will be returned as 0. | 764 | * On error, the return value (parent_div) will be 0. |
| 695 | */ | 765 | */ |
| 696 | static u32 omap2_clksel_get_src_field(void __iomem **src_addr, | 766 | static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, |
| 697 | struct clk *src_clk, u32 *field_mask, | 767 | u32 *field_val) |
| 698 | struct clk *clk, u32 *parent_div) | ||
| 699 | { | 768 | { |
| 700 | const struct clksel *clks; | 769 | const struct clksel *clks; |
| 701 | const struct clksel_rate *clkr; | 770 | const struct clksel_rate *clkr; |
| 702 | 771 | ||
| 703 | *parent_div = 0; | ||
| 704 | *src_addr = NULL; | ||
| 705 | |||
| 706 | clks = omap2_get_clksel_by_parent(clk, src_clk); | 772 | clks = omap2_get_clksel_by_parent(clk, src_clk); |
| 707 | if (clks == NULL) | 773 | if (!clks) |
| 708 | return 0; | 774 | return 0; |
| 709 | 775 | ||
| 710 | for (clkr = clks->rates; clkr->div; clkr++) { | 776 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -722,47 +788,35 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr, | |||
| 722 | /* Should never happen. Add a clksel mask to the struct clk. */ | 788 | /* Should never happen. Add a clksel mask to the struct clk. */ |
| 723 | WARN_ON(clk->clksel_mask == 0); | 789 | WARN_ON(clk->clksel_mask == 0); |
| 724 | 790 | ||
| 725 | *field_mask = clk->clksel_mask; | 791 | *field_val = clkr->val; |
| 726 | *src_addr = clk->clksel_reg; | ||
| 727 | *parent_div = clkr->div; | ||
| 728 | 792 | ||
| 729 | return clkr->val; | 793 | return clkr->div; |
| 730 | } | 794 | } |
| 731 | 795 | ||
| 732 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | 796 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
| 733 | { | 797 | { |
| 734 | void __iomem *src_addr; | 798 | u32 field_val, v, parent_div; |
| 735 | u32 field_val, field_mask, reg_val, parent_div; | ||
| 736 | 799 | ||
| 737 | if (unlikely(clk->flags & CONFIG_PARTICIPANT)) | 800 | if (clk->flags & CONFIG_PARTICIPANT) |
| 738 | return -EINVAL; | 801 | return -EINVAL; |
| 739 | 802 | ||
| 740 | if (!clk->clksel) | 803 | if (!clk->clksel) |
| 741 | return -EINVAL; | 804 | return -EINVAL; |
| 742 | 805 | ||
| 743 | field_val = omap2_clksel_get_src_field(&src_addr, new_parent, | 806 | parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); |
| 744 | &field_mask, clk, &parent_div); | 807 | if (!parent_div) |
| 745 | if (src_addr == NULL) | ||
| 746 | return -EINVAL; | 808 | return -EINVAL; |
| 747 | 809 | ||
| 748 | if (clk->usecount > 0) | ||
| 749 | omap2_clk_disable(clk); | ||
| 750 | |||
| 751 | /* Set new source value (previous dividers if any in effect) */ | 810 | /* Set new source value (previous dividers if any in effect) */ |
| 752 | reg_val = __raw_readl(src_addr) & ~field_mask; | 811 | v = __raw_readl(clk->clksel_reg); |
| 753 | reg_val |= (field_val << __ffs(field_mask)); | 812 | v &= ~clk->clksel_mask; |
| 754 | __raw_writel(reg_val, src_addr); | 813 | v |= field_val << __ffs(clk->clksel_mask); |
| 755 | wmb(); | 814 | __raw_writel(v, clk->clksel_reg); |
| 756 | 815 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ | |
| 757 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | ||
| 758 | __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); | ||
| 759 | wmb(); | ||
| 760 | } | ||
| 761 | 816 | ||
| 762 | clk->parent = new_parent; | 817 | _omap2xxx_clk_commit(clk); |
| 763 | 818 | ||
| 764 | if (clk->usecount > 0) | 819 | clk_reparent(clk, new_parent); |
| 765 | omap2_clk_enable(clk); | ||
| 766 | 820 | ||
| 767 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ | 821 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ |
| 768 | clk->rate = new_parent->rate; | 822 | clk->rate = new_parent->rate; |
| @@ -773,9 +827,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | |||
| 773 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", | 827 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", |
| 774 | clk->name, clk->parent->name, clk->rate); | 828 | clk->name, clk->parent->name, clk->rate); |
| 775 | 829 | ||
| 776 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 777 | propagate_rate(clk); | ||
| 778 | |||
| 779 | return 0; | 830 | return 0; |
| 780 | } | 831 | } |
| 781 | 832 | ||
| @@ -805,7 +856,8 @@ int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) | |||
| 805 | return 0; | 856 | return 0; |
| 806 | } | 857 | } |
| 807 | 858 | ||
| 808 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) | 859 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, |
| 860 | unsigned int m, unsigned int n) | ||
| 809 | { | 861 | { |
| 810 | unsigned long long num; | 862 | unsigned long long num; |
| 811 | 863 | ||
| @@ -838,7 +890,7 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |||
| 838 | unsigned long target_rate, | 890 | unsigned long target_rate, |
| 839 | unsigned long parent_rate) | 891 | unsigned long parent_rate) |
| 840 | { | 892 | { |
| 841 | int flags = 0, carry = 0; | 893 | int r = 0, carry = 0; |
| 842 | 894 | ||
| 843 | /* Unscale m and round if necessary */ | 895 | /* Unscale m and round if necessary */ |
| 844 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) | 896 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) |
| @@ -859,13 +911,13 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |||
| 859 | if (*m < DPLL_MIN_MULTIPLIER) { | 911 | if (*m < DPLL_MIN_MULTIPLIER) { |
| 860 | *m = DPLL_MIN_MULTIPLIER; | 912 | *m = DPLL_MIN_MULTIPLIER; |
| 861 | *new_rate = 0; | 913 | *new_rate = 0; |
| 862 | flags = DPLL_MULT_UNDERFLOW; | 914 | r = DPLL_MULT_UNDERFLOW; |
| 863 | } | 915 | } |
| 864 | 916 | ||
| 865 | if (*new_rate == 0) | 917 | if (*new_rate == 0) |
| 866 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | 918 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); |
| 867 | 919 | ||
| 868 | return flags; | 920 | return r; |
| 869 | } | 921 | } |
| 870 | 922 | ||
| 871 | /** | 923 | /** |
| @@ -889,54 +941,65 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | |||
| 889 | int m, n, r, e, scaled_max_m; | 941 | int m, n, r, e, scaled_max_m; |
| 890 | unsigned long scaled_rt_rp, new_rate; | 942 | unsigned long scaled_rt_rp, new_rate; |
| 891 | int min_e = -1, min_e_m = -1, min_e_n = -1; | 943 | int min_e = -1, min_e_m = -1, min_e_n = -1; |
| 944 | struct dpll_data *dd; | ||
| 892 | 945 | ||
| 893 | if (!clk || !clk->dpll_data) | 946 | if (!clk || !clk->dpll_data) |
| 894 | return ~0; | 947 | return ~0; |
| 895 | 948 | ||
| 949 | dd = clk->dpll_data; | ||
| 950 | |||
| 896 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " | 951 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " |
| 897 | "%ld\n", clk->name, target_rate); | 952 | "%ld\n", clk->name, target_rate); |
| 898 | 953 | ||
| 899 | scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); | 954 | scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); |
| 900 | scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; | 955 | scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; |
| 901 | 956 | ||
| 902 | clk->dpll_data->last_rounded_rate = 0; | 957 | dd->last_rounded_rate = 0; |
| 903 | 958 | ||
| 904 | for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { | 959 | for (n = dd->min_divider; n <= dd->max_divider; n++) { |
| 960 | |||
| 961 | /* Is the (input clk, divider) pair valid for the DPLL? */ | ||
| 962 | r = _dpll_test_fint(clk, n); | ||
| 963 | if (r == DPLL_FINT_UNDERFLOW) | ||
| 964 | break; | ||
| 965 | else if (r == DPLL_FINT_INVALID) | ||
| 966 | continue; | ||
| 905 | 967 | ||
| 906 | /* Compute the scaled DPLL multiplier, based on the divider */ | 968 | /* Compute the scaled DPLL multiplier, based on the divider */ |
| 907 | m = scaled_rt_rp * n; | 969 | m = scaled_rt_rp * n; |
| 908 | 970 | ||
| 909 | /* | 971 | /* |
| 910 | * Since we're counting n down, a m overflow means we can | 972 | * Since we're counting n up, a m overflow means we |
| 911 | * can immediately skip to the next n | 973 | * can bail out completely (since as n increases in |
| 974 | * the next iteration, there's no way that m can | ||
| 975 | * increase beyond the current m) | ||
| 912 | */ | 976 | */ |
| 913 | if (m > scaled_max_m) | 977 | if (m > scaled_max_m) |
| 914 | continue; | 978 | break; |
| 915 | 979 | ||
| 916 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, | 980 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, |
| 917 | clk->parent->rate); | 981 | dd->clk_ref->rate); |
| 982 | |||
| 983 | /* m can't be set low enough for this n - try with a larger n */ | ||
| 984 | if (r == DPLL_MULT_UNDERFLOW) | ||
| 985 | continue; | ||
| 918 | 986 | ||
| 919 | e = target_rate - new_rate; | 987 | e = target_rate - new_rate; |
| 920 | pr_debug("clock: n = %d: m = %d: rate error is %d " | 988 | pr_debug("clock: n = %d: m = %d: rate error is %d " |
| 921 | "(new_rate = %ld)\n", n, m, e, new_rate); | 989 | "(new_rate = %ld)\n", n, m, e, new_rate); |
| 922 | 990 | ||
| 923 | if (min_e == -1 || | 991 | if (min_e == -1 || |
| 924 | min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { | 992 | min_e >= (int)(abs(e) - dd->rate_tolerance)) { |
| 925 | min_e = e; | 993 | min_e = e; |
| 926 | min_e_m = m; | 994 | min_e_m = m; |
| 927 | min_e_n = n; | 995 | min_e_n = n; |
| 928 | 996 | ||
| 929 | pr_debug("clock: found new least error %d\n", min_e); | 997 | pr_debug("clock: found new least error %d\n", min_e); |
| 930 | } | ||
| 931 | 998 | ||
| 932 | /* | 999 | /* We found good settings -- bail out now */ |
| 933 | * Since we're counting n down, a m underflow means we | 1000 | if (min_e <= dd->rate_tolerance) |
| 934 | * can bail out completely (since as n decreases in | 1001 | break; |
| 935 | * the next iteration, there's no way that m can | 1002 | } |
| 936 | * increase beyond the current m) | ||
| 937 | */ | ||
| 938 | if (r & DPLL_MULT_UNDERFLOW) | ||
| 939 | break; | ||
| 940 | } | 1003 | } |
| 941 | 1004 | ||
| 942 | if (min_e < 0) { | 1005 | if (min_e < 0) { |
| @@ -944,17 +1007,17 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | |||
| 944 | return ~0; | 1007 | return ~0; |
| 945 | } | 1008 | } |
| 946 | 1009 | ||
| 947 | clk->dpll_data->last_rounded_m = min_e_m; | 1010 | dd->last_rounded_m = min_e_m; |
| 948 | clk->dpll_data->last_rounded_n = min_e_n; | 1011 | dd->last_rounded_n = min_e_n; |
| 949 | clk->dpll_data->last_rounded_rate = | 1012 | dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, |
| 950 | _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); | 1013 | min_e_m, min_e_n); |
| 951 | 1014 | ||
| 952 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", | 1015 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", |
| 953 | min_e, min_e_m, min_e_n); | 1016 | min_e, min_e_m, min_e_n); |
| 954 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", | 1017 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", |
| 955 | clk->dpll_data->last_rounded_rate, target_rate); | 1018 | dd->last_rounded_rate, target_rate); |
| 956 | 1019 | ||
| 957 | return clk->dpll_data->last_rounded_rate; | 1020 | return dd->last_rounded_rate; |
| 958 | } | 1021 | } |
| 959 | 1022 | ||
| 960 | /*------------------------------------------------------------------------- | 1023 | /*------------------------------------------------------------------------- |
| @@ -973,6 +1036,10 @@ void omap2_clk_disable_unused(struct clk *clk) | |||
| 973 | return; | 1036 | return; |
| 974 | 1037 | ||
| 975 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); | 1038 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); |
| 976 | _omap2_clk_disable(clk); | 1039 | if (cpu_is_omap34xx()) { |
| 1040 | omap2_clk_enable(clk); | ||
| 1041 | omap2_clk_disable(clk); | ||
| 1042 | } else | ||
| 1043 | _omap2_clk_disable(clk); | ||
| 977 | } | 1044 | } |
| 978 | #endif | 1045 | #endif |
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 1fb330e0847d..2679ddfa6424 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
| @@ -21,13 +21,28 @@ | |||
| 21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ | 21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ |
| 22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 | 22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 |
| 23 | 23 | ||
| 24 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ | ||
| 25 | #define CORE_CLK_SRC_32K 0x0 | ||
| 26 | #define CORE_CLK_SRC_DPLL 0x1 | ||
| 27 | #define CORE_CLK_SRC_DPLL_X2 0x2 | ||
| 28 | |||
| 29 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ | ||
| 30 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 | ||
| 31 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 | ||
| 32 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 | ||
| 33 | |||
| 34 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | ||
| 35 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 | ||
| 36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | ||
| 37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | ||
| 38 | |||
| 24 | int omap2_clk_init(void); | 39 | int omap2_clk_init(void); |
| 25 | int omap2_clk_enable(struct clk *clk); | 40 | int omap2_clk_enable(struct clk *clk); |
| 26 | void omap2_clk_disable(struct clk *clk); | 41 | void omap2_clk_disable(struct clk *clk); |
| 27 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | 42 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
| 28 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | 43 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); |
| 29 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | 44 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); |
| 30 | int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance); | 45 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); |
| 31 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); | 46 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
| 32 | 47 | ||
| 33 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 48 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| @@ -36,7 +51,7 @@ void omap2_clk_disable_unused(struct clk *clk); | |||
| 36 | #define omap2_clk_disable_unused NULL | 51 | #define omap2_clk_disable_unused NULL |
| 37 | #endif | 52 | #endif |
| 38 | 53 | ||
| 39 | void omap2_clksel_recalc(struct clk *clk); | 54 | unsigned long omap2_clksel_recalc(struct clk *clk); |
| 40 | void omap2_init_clk_clkdm(struct clk *clk); | 55 | void omap2_init_clk_clkdm(struct clk *clk); |
| 41 | void omap2_init_clksel_parent(struct clk *clk); | 56 | void omap2_init_clksel_parent(struct clk *clk); |
| 42 | u32 omap2_clksel_get_divisor(struct clk *clk); | 57 | u32 omap2_clksel_get_divisor(struct clk *clk); |
| @@ -44,13 +59,16 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
| 44 | u32 *new_div); | 59 | u32 *new_div); |
| 45 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); | 60 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); |
| 46 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); | 61 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); |
| 47 | void omap2_fixed_divisor_recalc(struct clk *clk); | 62 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk); |
| 48 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); | 63 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
| 49 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | 64 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); |
| 50 | u32 omap2_get_dpll_rate(struct clk *clk); | 65 | u32 omap2_get_dpll_rate(struct clk *clk); |
| 51 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); | 66 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
| 52 | void omap2_clk_prepare_for_reboot(void); | 67 | void omap2_clk_prepare_for_reboot(void); |
| 53 | 68 | ||
| 69 | extern const struct clkops clkops_omap2_dflt_wait; | ||
| 70 | extern const struct clkops clkops_omap2_dflt; | ||
| 71 | |||
| 54 | extern u8 cpu_mask; | 72 | extern u8 cpu_mask; |
| 55 | 73 | ||
| 56 | /* clksel_rate data common to 24xx/343x */ | 74 | /* clksel_rate data common to 24xx/343x */ |
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index d382eb0184ac..1e839c5a28c5 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c | |||
| @@ -31,15 +31,192 @@ | |||
| 31 | #include <mach/clock.h> | 31 | #include <mach/clock.h> |
| 32 | #include <mach/sram.h> | 32 | #include <mach/sram.h> |
| 33 | #include <asm/div64.h> | 33 | #include <asm/div64.h> |
| 34 | #include <asm/clkdev.h> | ||
| 34 | 35 | ||
| 35 | #include "memory.h" | 36 | #include <mach/sdrc.h> |
| 36 | #include "clock.h" | 37 | #include "clock.h" |
| 37 | #include "clock24xx.h" | ||
| 38 | #include "prm.h" | 38 | #include "prm.h" |
| 39 | #include "prm-regbits-24xx.h" | 39 | #include "prm-regbits-24xx.h" |
| 40 | #include "cm.h" | 40 | #include "cm.h" |
| 41 | #include "cm-regbits-24xx.h" | 41 | #include "cm-regbits-24xx.h" |
| 42 | 42 | ||
| 43 | static const struct clkops clkops_oscck; | ||
| 44 | static const struct clkops clkops_fixed; | ||
| 45 | |||
| 46 | #include "clock24xx.h" | ||
| 47 | |||
| 48 | struct omap_clk { | ||
| 49 | u32 cpu; | ||
| 50 | struct clk_lookup lk; | ||
| 51 | }; | ||
| 52 | |||
| 53 | #define CLK(dev, con, ck, cp) \ | ||
| 54 | { \ | ||
| 55 | .cpu = cp, \ | ||
| 56 | .lk = { \ | ||
| 57 | .dev_id = dev, \ | ||
| 58 | .con_id = con, \ | ||
| 59 | .clk = ck, \ | ||
| 60 | }, \ | ||
| 61 | } | ||
| 62 | |||
| 63 | #define CK_243X (1 << 0) | ||
| 64 | #define CK_242X (1 << 1) | ||
| 65 | |||
| 66 | static struct omap_clk omap24xx_clks[] = { | ||
| 67 | /* external root sources */ | ||
| 68 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | ||
| 69 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), | ||
| 70 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | ||
| 71 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | ||
| 72 | /* internal analog sources */ | ||
| 73 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | ||
| 74 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | ||
| 75 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | ||
| 76 | /* internal prcm root sources */ | ||
| 77 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | ||
| 78 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | ||
| 79 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | ||
| 80 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | ||
| 81 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | ||
| 82 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | ||
| 83 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | ||
| 84 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | ||
| 85 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | ||
| 86 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
| 87 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
| 88 | /* mpu domain clocks */ | ||
| 89 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | ||
| 90 | /* dsp domain clocks */ | ||
| 91 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | ||
| 92 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | ||
| 93 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
| 94 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | ||
| 95 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
| 96 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
| 97 | /* GFX domain clocks */ | ||
| 98 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | ||
| 99 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | ||
| 100 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | ||
| 101 | /* Modem domain clocks */ | ||
| 102 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | ||
| 103 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | ||
| 104 | /* DSS domain clocks */ | ||
| 105 | CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X), | ||
| 106 | CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X), | ||
| 107 | CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X), | ||
| 108 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X), | ||
| 109 | /* L3 domain clocks */ | ||
| 110 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | ||
| 111 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | ||
| 112 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | ||
| 113 | /* L4 domain clocks */ | ||
| 114 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | ||
| 115 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), | ||
| 116 | /* virtual meta-group clock */ | ||
| 117 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | ||
| 118 | /* general l4 interface ck, multi-parent functional clk */ | ||
| 119 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | ||
| 120 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | ||
| 121 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | ||
| 122 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | ||
| 123 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | ||
| 124 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | ||
| 125 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | ||
| 126 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | ||
| 127 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | ||
| 128 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | ||
| 129 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | ||
| 130 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | ||
| 131 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | ||
| 132 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | ||
| 133 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | ||
| 134 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | ||
| 135 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | ||
| 136 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | ||
| 137 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | ||
| 138 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | ||
| 139 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | ||
| 140 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | ||
| 141 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | ||
| 142 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | ||
| 143 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), | ||
| 144 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | ||
| 145 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | ||
| 146 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | ||
| 147 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | ||
| 148 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | ||
| 149 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | ||
| 150 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | ||
| 151 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | ||
| 152 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | ||
| 153 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), | ||
| 154 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | ||
| 155 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | ||
| 156 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | ||
| 157 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | ||
| 158 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | ||
| 159 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), | ||
| 160 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | ||
| 161 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | ||
| 162 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | ||
| 163 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | ||
| 164 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | ||
| 165 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | ||
| 166 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | ||
| 167 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), | ||
| 168 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | ||
| 169 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), | ||
| 170 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | ||
| 171 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | ||
| 172 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | ||
| 173 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), | ||
| 174 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | ||
| 175 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), | ||
| 176 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | ||
| 177 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | ||
| 178 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | ||
| 179 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | ||
| 180 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | ||
| 181 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | ||
| 182 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | ||
| 183 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | ||
| 184 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), | ||
| 185 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | ||
| 186 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
| 187 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
| 188 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), | ||
| 189 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | ||
| 190 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), | ||
| 191 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
| 192 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | ||
| 193 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | ||
| 194 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
| 195 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | ||
| 196 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), | ||
| 197 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | ||
| 198 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | ||
| 199 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
| 200 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
| 201 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | ||
| 202 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | ||
| 203 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | ||
| 204 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), | ||
| 205 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | ||
| 206 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | ||
| 207 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | ||
| 208 | CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), | ||
| 209 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | ||
| 210 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | ||
| 211 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | ||
| 212 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | ||
| 213 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | ||
| 214 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | ||
| 215 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | ||
| 216 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | ||
| 217 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | ||
| 218 | }; | ||
| 219 | |||
| 43 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | 220 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ |
| 44 | #define EN_APLL_STOPPED 0 | 221 | #define EN_APLL_STOPPED 0 |
| 45 | #define EN_APLL_LOCKED 3 | 222 | #define EN_APLL_LOCKED 3 |
| @@ -59,19 +236,32 @@ static struct clk *sclk; | |||
| 59 | * Omap24xx specific clock functions | 236 | * Omap24xx specific clock functions |
| 60 | *-------------------------------------------------------------------------*/ | 237 | *-------------------------------------------------------------------------*/ |
| 61 | 238 | ||
| 62 | /* This actually returns the rate of core_ck, not dpll_ck. */ | 239 | /** |
| 63 | static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) | 240 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate |
| 241 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | ||
| 242 | * | ||
| 243 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | ||
| 244 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | ||
| 245 | * (the latter is unusual). This currently should be called with | ||
| 246 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | ||
| 247 | * core_ck. | ||
| 248 | */ | ||
| 249 | static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | ||
| 64 | { | 250 | { |
| 65 | long long dpll_clk; | 251 | long long core_clk; |
| 66 | u8 amult; | 252 | u32 v; |
| 253 | |||
| 254 | core_clk = omap2_get_dpll_rate(clk); | ||
| 67 | 255 | ||
| 68 | dpll_clk = omap2_get_dpll_rate(tclk); | 256 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 257 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 69 | 258 | ||
| 70 | amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 259 | if (v == CORE_CLK_SRC_32K) |
| 71 | amult &= OMAP24XX_CORE_CLK_SRC_MASK; | 260 | core_clk = 32768; |
| 72 | dpll_clk *= amult; | 261 | else |
| 262 | core_clk *= v; | ||
| 73 | 263 | ||
| 74 | return dpll_clk; | 264 | return core_clk; |
| 75 | } | 265 | } |
| 76 | 266 | ||
| 77 | static int omap2_enable_osc_ck(struct clk *clk) | 267 | static int omap2_enable_osc_ck(struct clk *clk) |
| @@ -96,6 +286,11 @@ static void omap2_disable_osc_ck(struct clk *clk) | |||
| 96 | OMAP24XX_PRCM_CLKSRC_CTRL); | 286 | OMAP24XX_PRCM_CLKSRC_CTRL); |
| 97 | } | 287 | } |
| 98 | 288 | ||
| 289 | static const struct clkops clkops_oscck = { | ||
| 290 | .enable = &omap2_enable_osc_ck, | ||
| 291 | .disable = &omap2_disable_osc_ck, | ||
| 292 | }; | ||
| 293 | |||
| 99 | #ifdef OLD_CK | 294 | #ifdef OLD_CK |
| 100 | /* Recalculate SYST_CLK */ | 295 | /* Recalculate SYST_CLK */ |
| 101 | static void omap2_sys_clk_recalc(struct clk * clk) | 296 | static void omap2_sys_clk_recalc(struct clk * clk) |
| @@ -149,11 +344,16 @@ static void omap2_clk_fixed_disable(struct clk *clk) | |||
| 149 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | 344 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
| 150 | } | 345 | } |
| 151 | 346 | ||
| 347 | static const struct clkops clkops_fixed = { | ||
| 348 | .enable = &omap2_clk_fixed_enable, | ||
| 349 | .disable = &omap2_clk_fixed_disable, | ||
| 350 | }; | ||
| 351 | |||
| 152 | /* | 352 | /* |
| 153 | * Uses the current prcm set to tell if a rate is valid. | 353 | * Uses the current prcm set to tell if a rate is valid. |
| 154 | * You can go slower, but not faster within a given rate set. | 354 | * You can go slower, but not faster within a given rate set. |
| 155 | */ | 355 | */ |
| 156 | long omap2_dpllcore_round_rate(unsigned long target_rate) | 356 | static long omap2_dpllcore_round_rate(unsigned long target_rate) |
| 157 | { | 357 | { |
| 158 | u32 high, low, core_clk_src; | 358 | u32 high, low, core_clk_src; |
| 159 | 359 | ||
| @@ -182,11 +382,9 @@ long omap2_dpllcore_round_rate(unsigned long target_rate) | |||
| 182 | 382 | ||
| 183 | } | 383 | } |
| 184 | 384 | ||
| 185 | static void omap2_dpllcore_recalc(struct clk *clk) | 385 | static unsigned long omap2_dpllcore_recalc(struct clk *clk) |
| 186 | { | 386 | { |
| 187 | clk->rate = omap2_get_dpll_rate_24xx(clk); | 387 | return omap2xxx_clk_get_core_rate(clk); |
| 188 | |||
| 189 | propagate_rate(clk); | ||
| 190 | } | 388 | } |
| 191 | 389 | ||
| 192 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | 390 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) |
| @@ -195,22 +393,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 195 | u32 bypass = 0; | 393 | u32 bypass = 0; |
| 196 | struct prcm_config tmpset; | 394 | struct prcm_config tmpset; |
| 197 | const struct dpll_data *dd; | 395 | const struct dpll_data *dd; |
| 198 | unsigned long flags; | ||
| 199 | int ret = -EINVAL; | ||
| 200 | 396 | ||
| 201 | local_irq_save(flags); | 397 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 202 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
| 203 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 398 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 204 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | 399 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 205 | 400 | ||
| 206 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | 401 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
| 207 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); | 402 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
| 208 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | 403 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { |
| 209 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | 404 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 210 | } else if (rate != cur_rate) { | 405 | } else if (rate != cur_rate) { |
| 211 | valid_rate = omap2_dpllcore_round_rate(rate); | 406 | valid_rate = omap2_dpllcore_round_rate(rate); |
| 212 | if (valid_rate != rate) | 407 | if (valid_rate != rate) |
| 213 | goto dpll_exit; | 408 | return -EINVAL; |
| 214 | 409 | ||
| 215 | if (mult == 1) | 410 | if (mult == 1) |
| 216 | low = curr_prcm_set->dpll_speed; | 411 | low = curr_prcm_set->dpll_speed; |
| @@ -219,7 +414,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 219 | 414 | ||
| 220 | dd = clk->dpll_data; | 415 | dd = clk->dpll_data; |
| 221 | if (!dd) | 416 | if (!dd) |
| 222 | goto dpll_exit; | 417 | return -EINVAL; |
| 223 | 418 | ||
| 224 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | 419 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); |
| 225 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | 420 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | |
| @@ -245,22 +440,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 245 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | 440 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ |
| 246 | bypass = 1; | 441 | bypass = 1; |
| 247 | 442 | ||
| 248 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ | 443 | /* For omap2xxx_sdrc_init_params() */ |
| 444 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 249 | 445 | ||
| 250 | /* Force dll lock mode */ | 446 | /* Force dll lock mode */ |
| 251 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | 447 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, |
| 252 | bypass); | 448 | bypass); |
| 253 | 449 | ||
| 254 | /* Errata: ret dll entry state */ | 450 | /* Errata: ret dll entry state */ |
| 255 | omap2_init_memory_params(omap2_dll_force_needed()); | 451 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
| 256 | omap2_reprogram_sdrc(done_rate, 0); | 452 | omap2xxx_sdrc_reprogram(done_rate, 0); |
| 257 | } | 453 | } |
| 258 | omap2_dpllcore_recalc(&dpll_ck); | ||
| 259 | ret = 0; | ||
| 260 | 454 | ||
| 261 | dpll_exit: | 455 | return 0; |
| 262 | local_irq_restore(flags); | ||
| 263 | return(ret); | ||
| 264 | } | 456 | } |
| 265 | 457 | ||
| 266 | /** | 458 | /** |
| @@ -269,9 +461,9 @@ dpll_exit: | |||
| 269 | * | 461 | * |
| 270 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | 462 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. |
| 271 | */ | 463 | */ |
| 272 | static void omap2_table_mpu_recalc(struct clk *clk) | 464 | static unsigned long omap2_table_mpu_recalc(struct clk *clk) |
| 273 | { | 465 | { |
| 274 | clk->rate = curr_prcm_set->mpu_speed; | 466 | return curr_prcm_set->mpu_speed; |
| 275 | } | 467 | } |
| 276 | 468 | ||
| 277 | /* | 469 | /* |
| @@ -337,12 +529,12 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) | |||
| 337 | } | 529 | } |
| 338 | 530 | ||
| 339 | curr_prcm_set = prcm; | 531 | curr_prcm_set = prcm; |
| 340 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); | 532 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 341 | 533 | ||
| 342 | if (prcm->dpll_speed == cur_rate / 2) { | 534 | if (prcm->dpll_speed == cur_rate / 2) { |
| 343 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); | 535 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
| 344 | } else if (prcm->dpll_speed == cur_rate * 2) { | 536 | } else if (prcm->dpll_speed == cur_rate * 2) { |
| 345 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | 537 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 346 | } else if (prcm->dpll_speed != cur_rate) { | 538 | } else if (prcm->dpll_speed != cur_rate) { |
| 347 | local_irq_save(flags); | 539 | local_irq_save(flags); |
| 348 | 540 | ||
| @@ -366,27 +558,67 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) | |||
| 366 | 558 | ||
| 367 | /* Major subsystem dividers */ | 559 | /* Major subsystem dividers */ |
| 368 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | 560 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
| 369 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); | 561 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, |
| 562 | CM_CLKSEL1); | ||
| 563 | |||
| 370 | if (cpu_is_omap2430()) | 564 | if (cpu_is_omap2430()) |
| 371 | cm_write_mod_reg(prcm->cm_clksel_mdm, | 565 | cm_write_mod_reg(prcm->cm_clksel_mdm, |
| 372 | OMAP2430_MDM_MOD, CM_CLKSEL); | 566 | OMAP2430_MDM_MOD, CM_CLKSEL); |
| 373 | 567 | ||
| 374 | /* x2 to enter init_mem */ | 568 | /* x2 to enter omap2xxx_sdrc_init_params() */ |
| 375 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | 569 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 376 | 570 | ||
| 377 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | 571 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, |
| 378 | bypass); | 572 | bypass); |
| 379 | 573 | ||
| 380 | omap2_init_memory_params(omap2_dll_force_needed()); | 574 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
| 381 | omap2_reprogram_sdrc(done_rate, 0); | 575 | omap2xxx_sdrc_reprogram(done_rate, 0); |
| 382 | 576 | ||
| 383 | local_irq_restore(flags); | 577 | local_irq_restore(flags); |
| 384 | } | 578 | } |
| 385 | omap2_dpllcore_recalc(&dpll_ck); | ||
| 386 | 579 | ||
| 387 | return 0; | 580 | return 0; |
| 388 | } | 581 | } |
| 389 | 582 | ||
| 583 | #ifdef CONFIG_CPU_FREQ | ||
| 584 | /* | ||
| 585 | * Walk PRCM rate table and fillout cpufreq freq_table | ||
| 586 | */ | ||
| 587 | static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)]; | ||
| 588 | |||
| 589 | void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
| 590 | { | ||
| 591 | struct prcm_config *prcm; | ||
| 592 | int i = 0; | ||
| 593 | |||
| 594 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 595 | if (!(prcm->flags & cpu_mask)) | ||
| 596 | continue; | ||
| 597 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 598 | continue; | ||
| 599 | |||
| 600 | /* don't put bypass rates in table */ | ||
| 601 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 602 | continue; | ||
| 603 | |||
| 604 | freq_table[i].index = i; | ||
| 605 | freq_table[i].frequency = prcm->mpu_speed / 1000; | ||
| 606 | i++; | ||
| 607 | } | ||
| 608 | |||
| 609 | if (i == 0) { | ||
| 610 | printk(KERN_WARNING "%s: failed to initialize frequency " | ||
| 611 | "table\n", __func__); | ||
| 612 | return; | ||
| 613 | } | ||
| 614 | |||
| 615 | freq_table[i].index = i; | ||
| 616 | freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
| 617 | |||
| 618 | *table = &freq_table[0]; | ||
| 619 | } | ||
| 620 | #endif | ||
| 621 | |||
| 390 | static struct clk_functions omap2_clk_functions = { | 622 | static struct clk_functions omap2_clk_functions = { |
| 391 | .clk_enable = omap2_clk_enable, | 623 | .clk_enable = omap2_clk_enable, |
| 392 | .clk_disable = omap2_clk_disable, | 624 | .clk_disable = omap2_clk_disable, |
| @@ -394,24 +626,27 @@ static struct clk_functions omap2_clk_functions = { | |||
| 394 | .clk_set_rate = omap2_clk_set_rate, | 626 | .clk_set_rate = omap2_clk_set_rate, |
| 395 | .clk_set_parent = omap2_clk_set_parent, | 627 | .clk_set_parent = omap2_clk_set_parent, |
| 396 | .clk_disable_unused = omap2_clk_disable_unused, | 628 | .clk_disable_unused = omap2_clk_disable_unused, |
| 629 | #ifdef CONFIG_CPU_FREQ | ||
| 630 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | ||
| 631 | #endif | ||
| 397 | }; | 632 | }; |
| 398 | 633 | ||
| 399 | static u32 omap2_get_apll_clkin(void) | 634 | static u32 omap2_get_apll_clkin(void) |
| 400 | { | 635 | { |
| 401 | u32 aplls, sclk = 0; | 636 | u32 aplls, srate = 0; |
| 402 | 637 | ||
| 403 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | 638 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); |
| 404 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | 639 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; |
| 405 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | 640 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; |
| 406 | 641 | ||
| 407 | if (aplls == APLLS_CLKIN_19_2MHZ) | 642 | if (aplls == APLLS_CLKIN_19_2MHZ) |
| 408 | sclk = 19200000; | 643 | srate = 19200000; |
| 409 | else if (aplls == APLLS_CLKIN_13MHZ) | 644 | else if (aplls == APLLS_CLKIN_13MHZ) |
| 410 | sclk = 13000000; | 645 | srate = 13000000; |
| 411 | else if (aplls == APLLS_CLKIN_12MHZ) | 646 | else if (aplls == APLLS_CLKIN_12MHZ) |
| 412 | sclk = 12000000; | 647 | srate = 12000000; |
| 413 | 648 | ||
| 414 | return sclk; | 649 | return srate; |
| 415 | } | 650 | } |
| 416 | 651 | ||
| 417 | static u32 omap2_get_sysclkdiv(void) | 652 | static u32 omap2_get_sysclkdiv(void) |
| @@ -425,16 +660,14 @@ static u32 omap2_get_sysclkdiv(void) | |||
| 425 | return div; | 660 | return div; |
| 426 | } | 661 | } |
| 427 | 662 | ||
| 428 | static void omap2_osc_clk_recalc(struct clk *clk) | 663 | static unsigned long omap2_osc_clk_recalc(struct clk *clk) |
| 429 | { | 664 | { |
| 430 | clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); | 665 | return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); |
| 431 | propagate_rate(clk); | ||
| 432 | } | 666 | } |
| 433 | 667 | ||
| 434 | static void omap2_sys_clk_recalc(struct clk *clk) | 668 | static unsigned long omap2_sys_clk_recalc(struct clk *clk) |
| 435 | { | 669 | { |
| 436 | clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); | 670 | return clk->parent->rate / omap2_get_sysclkdiv(); |
| 437 | propagate_rate(clk); | ||
| 438 | } | 671 | } |
| 439 | 672 | ||
| 440 | /* | 673 | /* |
| @@ -460,7 +693,7 @@ static int __init omap2_clk_arch_init(void) | |||
| 460 | if (!mpurate) | 693 | if (!mpurate) |
| 461 | return -EINVAL; | 694 | return -EINVAL; |
| 462 | 695 | ||
| 463 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | 696 | if (clk_set_rate(&virt_prcm_set, mpurate)) |
| 464 | printk(KERN_ERR "Could not find matching MPU rate\n"); | 697 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
| 465 | 698 | ||
| 466 | recalculate_root_clocks(); | 699 | recalculate_root_clocks(); |
| @@ -477,8 +710,8 @@ arch_initcall(omap2_clk_arch_init); | |||
| 477 | int __init omap2_clk_init(void) | 710 | int __init omap2_clk_init(void) |
| 478 | { | 711 | { |
| 479 | struct prcm_config *prcm; | 712 | struct prcm_config *prcm; |
| 480 | struct clk **clkp; | 713 | struct omap_clk *c; |
| 481 | u32 clkrate; | 714 | u32 clkrate, cpu_mask; |
| 482 | 715 | ||
| 483 | if (cpu_is_omap242x()) | 716 | if (cpu_is_omap242x()) |
| 484 | cpu_mask = RATE_IN_242X; | 717 | cpu_mask = RATE_IN_242X; |
| @@ -487,26 +720,28 @@ int __init omap2_clk_init(void) | |||
| 487 | 720 | ||
| 488 | clk_init(&omap2_clk_functions); | 721 | clk_init(&omap2_clk_functions); |
| 489 | 722 | ||
| 490 | omap2_osc_clk_recalc(&osc_ck); | 723 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
| 491 | omap2_sys_clk_recalc(&sys_ck); | 724 | propagate_rate(&osc_ck); |
| 725 | sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); | ||
| 726 | propagate_rate(&sys_ck); | ||
| 492 | 727 | ||
| 493 | for (clkp = onchip_24xx_clks; | 728 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
| 494 | clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); | 729 | clk_init_one(c->lk.clk); |
| 495 | clkp++) { | ||
| 496 | 730 | ||
| 497 | if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { | 731 | cpu_mask = 0; |
| 498 | clk_register(*clkp); | 732 | if (cpu_is_omap2420()) |
| 499 | continue; | 733 | cpu_mask |= CK_242X; |
| 500 | } | 734 | if (cpu_is_omap2430()) |
| 735 | cpu_mask |= CK_243X; | ||
| 501 | 736 | ||
| 502 | if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { | 737 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
| 503 | clk_register(*clkp); | 738 | if (c->cpu & cpu_mask) { |
| 504 | continue; | 739 | clkdev_add(&c->lk); |
| 740 | clk_register(c->lk.clk); | ||
| 505 | } | 741 | } |
| 506 | } | ||
| 507 | 742 | ||
| 508 | /* Check the MPU rate set by bootloader */ | 743 | /* Check the MPU rate set by bootloader */ |
| 509 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | 744 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 510 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | 745 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 511 | if (!(prcm->flags & cpu_mask)) | 746 | if (!(prcm->flags & cpu_mask)) |
| 512 | continue; | 747 | continue; |
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index ad6d98d177c5..33c3e5b14323 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h | |||
| @@ -24,17 +24,13 @@ | |||
| 24 | #include "cm-regbits-24xx.h" | 24 | #include "cm-regbits-24xx.h" |
| 25 | #include "sdrc.h" | 25 | #include "sdrc.h" |
| 26 | 26 | ||
| 27 | static void omap2_table_mpu_recalc(struct clk *clk); | 27 | static unsigned long omap2_table_mpu_recalc(struct clk *clk); |
| 28 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate); | 28 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate); |
| 29 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); | 29 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); |
| 30 | static void omap2_sys_clk_recalc(struct clk *clk); | 30 | static unsigned long omap2_sys_clk_recalc(struct clk *clk); |
| 31 | static void omap2_osc_clk_recalc(struct clk *clk); | 31 | static unsigned long omap2_osc_clk_recalc(struct clk *clk); |
| 32 | static void omap2_sys_clk_recalc(struct clk *clk); | 32 | static unsigned long omap2_sys_clk_recalc(struct clk *clk); |
| 33 | static void omap2_dpllcore_recalc(struct clk *clk); | 33 | static unsigned long omap2_dpllcore_recalc(struct clk *clk); |
| 34 | static int omap2_clk_fixed_enable(struct clk *clk); | ||
| 35 | static void omap2_clk_fixed_disable(struct clk *clk); | ||
| 36 | static int omap2_enable_osc_ck(struct clk *clk); | ||
| 37 | static void omap2_disable_osc_ck(struct clk *clk); | ||
| 38 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); | 34 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); |
| 39 | 35 | ||
| 40 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | 36 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
| @@ -623,41 +619,35 @@ static struct prcm_config rate_table[] = { | |||
| 623 | /* Base external input clocks */ | 619 | /* Base external input clocks */ |
| 624 | static struct clk func_32k_ck = { | 620 | static struct clk func_32k_ck = { |
| 625 | .name = "func_32k_ck", | 621 | .name = "func_32k_ck", |
| 622 | .ops = &clkops_null, | ||
| 626 | .rate = 32000, | 623 | .rate = 32000, |
| 627 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 624 | .flags = RATE_FIXED, |
| 628 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 629 | .clkdm_name = "wkup_clkdm", | 625 | .clkdm_name = "wkup_clkdm", |
| 630 | .recalc = &propagate_rate, | ||
| 631 | }; | 626 | }; |
| 632 | 627 | ||
| 633 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ | 628 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
| 634 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | 629 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
| 635 | .name = "osc_ck", | 630 | .name = "osc_ck", |
| 636 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 631 | .ops = &clkops_oscck, |
| 637 | RATE_PROPAGATES, | ||
| 638 | .clkdm_name = "wkup_clkdm", | 632 | .clkdm_name = "wkup_clkdm", |
| 639 | .enable = &omap2_enable_osc_ck, | ||
| 640 | .disable = &omap2_disable_osc_ck, | ||
| 641 | .recalc = &omap2_osc_clk_recalc, | 633 | .recalc = &omap2_osc_clk_recalc, |
| 642 | }; | 634 | }; |
| 643 | 635 | ||
| 644 | /* Without modem likely 12MHz, with modem likely 13MHz */ | 636 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
| 645 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | 637 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
| 646 | .name = "sys_ck", /* ~ ref_clk also */ | 638 | .name = "sys_ck", /* ~ ref_clk also */ |
| 639 | .ops = &clkops_null, | ||
| 647 | .parent = &osc_ck, | 640 | .parent = &osc_ck, |
| 648 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 649 | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 650 | .clkdm_name = "wkup_clkdm", | 641 | .clkdm_name = "wkup_clkdm", |
| 651 | .recalc = &omap2_sys_clk_recalc, | 642 | .recalc = &omap2_sys_clk_recalc, |
| 652 | }; | 643 | }; |
| 653 | 644 | ||
| 654 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | 645 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 655 | .name = "alt_ck", | 646 | .name = "alt_ck", |
| 647 | .ops = &clkops_null, | ||
| 656 | .rate = 54000000, | 648 | .rate = 54000000, |
| 657 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 649 | .flags = RATE_FIXED, |
| 658 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 659 | .clkdm_name = "wkup_clkdm", | 650 | .clkdm_name = "wkup_clkdm", |
| 660 | .recalc = &propagate_rate, | ||
| 661 | }; | 651 | }; |
| 662 | 652 | ||
| 663 | /* | 653 | /* |
| @@ -673,7 +663,12 @@ static struct dpll_data dpll_dd = { | |||
| 673 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 663 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 674 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | 664 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, |
| 675 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | 665 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, |
| 666 | .clk_bypass = &sys_ck, | ||
| 667 | .clk_ref = &sys_ck, | ||
| 668 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 669 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | ||
| 676 | .max_multiplier = 1024, | 670 | .max_multiplier = 1024, |
| 671 | .min_divider = 1, | ||
| 677 | .max_divider = 16, | 672 | .max_divider = 16, |
| 678 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 673 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 679 | }; | 674 | }; |
| @@ -684,10 +679,9 @@ static struct dpll_data dpll_dd = { | |||
| 684 | */ | 679 | */ |
| 685 | static struct clk dpll_ck = { | 680 | static struct clk dpll_ck = { |
| 686 | .name = "dpll_ck", | 681 | .name = "dpll_ck", |
| 682 | .ops = &clkops_null, | ||
| 687 | .parent = &sys_ck, /* Can be func_32k also */ | 683 | .parent = &sys_ck, /* Can be func_32k also */ |
| 688 | .dpll_data = &dpll_dd, | 684 | .dpll_data = &dpll_dd, |
| 689 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 690 | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 691 | .clkdm_name = "wkup_clkdm", | 685 | .clkdm_name = "wkup_clkdm", |
| 692 | .recalc = &omap2_dpllcore_recalc, | 686 | .recalc = &omap2_dpllcore_recalc, |
| 693 | .set_rate = &omap2_reprogram_dpllcore, | 687 | .set_rate = &omap2_reprogram_dpllcore, |
| @@ -695,30 +689,24 @@ static struct clk dpll_ck = { | |||
| 695 | 689 | ||
| 696 | static struct clk apll96_ck = { | 690 | static struct clk apll96_ck = { |
| 697 | .name = "apll96_ck", | 691 | .name = "apll96_ck", |
| 692 | .ops = &clkops_fixed, | ||
| 698 | .parent = &sys_ck, | 693 | .parent = &sys_ck, |
| 699 | .rate = 96000000, | 694 | .rate = 96000000, |
| 700 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 695 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
| 701 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | ||
| 702 | .clkdm_name = "wkup_clkdm", | 696 | .clkdm_name = "wkup_clkdm", |
| 703 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 697 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 704 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | 698 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
| 705 | .enable = &omap2_clk_fixed_enable, | ||
| 706 | .disable = &omap2_clk_fixed_disable, | ||
| 707 | .recalc = &propagate_rate, | ||
| 708 | }; | 699 | }; |
| 709 | 700 | ||
| 710 | static struct clk apll54_ck = { | 701 | static struct clk apll54_ck = { |
| 711 | .name = "apll54_ck", | 702 | .name = "apll54_ck", |
| 703 | .ops = &clkops_fixed, | ||
| 712 | .parent = &sys_ck, | 704 | .parent = &sys_ck, |
| 713 | .rate = 54000000, | 705 | .rate = 54000000, |
| 714 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 706 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
| 715 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | ||
| 716 | .clkdm_name = "wkup_clkdm", | 707 | .clkdm_name = "wkup_clkdm", |
| 717 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 708 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 718 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | 709 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
| 719 | .enable = &omap2_clk_fixed_enable, | ||
| 720 | .disable = &omap2_clk_fixed_disable, | ||
| 721 | .recalc = &propagate_rate, | ||
| 722 | }; | 710 | }; |
| 723 | 711 | ||
| 724 | /* | 712 | /* |
| @@ -745,9 +733,8 @@ static const struct clksel func_54m_clksel[] = { | |||
| 745 | 733 | ||
| 746 | static struct clk func_54m_ck = { | 734 | static struct clk func_54m_ck = { |
| 747 | .name = "func_54m_ck", | 735 | .name = "func_54m_ck", |
| 736 | .ops = &clkops_null, | ||
| 748 | .parent = &apll54_ck, /* can also be alt_clk */ | 737 | .parent = &apll54_ck, /* can also be alt_clk */ |
| 749 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 750 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 751 | .clkdm_name = "wkup_clkdm", | 738 | .clkdm_name = "wkup_clkdm", |
| 752 | .init = &omap2_init_clksel_parent, | 739 | .init = &omap2_init_clksel_parent, |
| 753 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 740 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| @@ -758,9 +745,8 @@ static struct clk func_54m_ck = { | |||
| 758 | 745 | ||
| 759 | static struct clk core_ck = { | 746 | static struct clk core_ck = { |
| 760 | .name = "core_ck", | 747 | .name = "core_ck", |
| 748 | .ops = &clkops_null, | ||
| 761 | .parent = &dpll_ck, /* can also be 32k */ | 749 | .parent = &dpll_ck, /* can also be 32k */ |
| 762 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 763 | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 764 | .clkdm_name = "wkup_clkdm", | 750 | .clkdm_name = "wkup_clkdm", |
| 765 | .recalc = &followparent_recalc, | 751 | .recalc = &followparent_recalc, |
| 766 | }; | 752 | }; |
| @@ -785,9 +771,8 @@ static const struct clksel func_96m_clksel[] = { | |||
| 785 | /* The parent of this clock is not selectable on 2420. */ | 771 | /* The parent of this clock is not selectable on 2420. */ |
| 786 | static struct clk func_96m_ck = { | 772 | static struct clk func_96m_ck = { |
| 787 | .name = "func_96m_ck", | 773 | .name = "func_96m_ck", |
| 774 | .ops = &clkops_null, | ||
| 788 | .parent = &apll96_ck, | 775 | .parent = &apll96_ck, |
| 789 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 790 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 791 | .clkdm_name = "wkup_clkdm", | 776 | .clkdm_name = "wkup_clkdm", |
| 792 | .init = &omap2_init_clksel_parent, | 777 | .init = &omap2_init_clksel_parent, |
| 793 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 778 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| @@ -818,9 +803,8 @@ static const struct clksel func_48m_clksel[] = { | |||
| 818 | 803 | ||
| 819 | static struct clk func_48m_ck = { | 804 | static struct clk func_48m_ck = { |
| 820 | .name = "func_48m_ck", | 805 | .name = "func_48m_ck", |
| 806 | .ops = &clkops_null, | ||
| 821 | .parent = &apll96_ck, /* 96M or Alt */ | 807 | .parent = &apll96_ck, /* 96M or Alt */ |
| 822 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 823 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 824 | .clkdm_name = "wkup_clkdm", | 808 | .clkdm_name = "wkup_clkdm", |
| 825 | .init = &omap2_init_clksel_parent, | 809 | .init = &omap2_init_clksel_parent, |
| 826 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 810 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| @@ -833,10 +817,9 @@ static struct clk func_48m_ck = { | |||
| 833 | 817 | ||
| 834 | static struct clk func_12m_ck = { | 818 | static struct clk func_12m_ck = { |
| 835 | .name = "func_12m_ck", | 819 | .name = "func_12m_ck", |
| 820 | .ops = &clkops_null, | ||
| 836 | .parent = &func_48m_ck, | 821 | .parent = &func_48m_ck, |
| 837 | .fixed_div = 4, | 822 | .fixed_div = 4, |
| 838 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 839 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 840 | .clkdm_name = "wkup_clkdm", | 823 | .clkdm_name = "wkup_clkdm", |
| 841 | .recalc = &omap2_fixed_divisor_recalc, | 824 | .recalc = &omap2_fixed_divisor_recalc, |
| 842 | }; | 825 | }; |
| @@ -844,8 +827,8 @@ static struct clk func_12m_ck = { | |||
| 844 | /* Secure timer, only available in secure mode */ | 827 | /* Secure timer, only available in secure mode */ |
| 845 | static struct clk wdt1_osc_ck = { | 828 | static struct clk wdt1_osc_ck = { |
| 846 | .name = "ck_wdt1_osc", | 829 | .name = "ck_wdt1_osc", |
| 830 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 847 | .parent = &osc_ck, | 831 | .parent = &osc_ck, |
| 848 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 849 | .recalc = &followparent_recalc, | 832 | .recalc = &followparent_recalc, |
| 850 | }; | 833 | }; |
| 851 | 834 | ||
| @@ -887,9 +870,8 @@ static const struct clksel common_clkout_src_clksel[] = { | |||
| 887 | 870 | ||
| 888 | static struct clk sys_clkout_src = { | 871 | static struct clk sys_clkout_src = { |
| 889 | .name = "sys_clkout_src", | 872 | .name = "sys_clkout_src", |
| 873 | .ops = &clkops_omap2_dflt, | ||
| 890 | .parent = &func_54m_ck, | 874 | .parent = &func_54m_ck, |
| 891 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 892 | RATE_PROPAGATES, | ||
| 893 | .clkdm_name = "wkup_clkdm", | 875 | .clkdm_name = "wkup_clkdm", |
| 894 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 876 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 895 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | 877 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
| @@ -918,9 +900,8 @@ static const struct clksel sys_clkout_clksel[] = { | |||
| 918 | 900 | ||
| 919 | static struct clk sys_clkout = { | 901 | static struct clk sys_clkout = { |
| 920 | .name = "sys_clkout", | 902 | .name = "sys_clkout", |
| 903 | .ops = &clkops_null, | ||
| 921 | .parent = &sys_clkout_src, | 904 | .parent = &sys_clkout_src, |
| 922 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 923 | PARENT_CONTROLS_CLOCK, | ||
| 924 | .clkdm_name = "wkup_clkdm", | 905 | .clkdm_name = "wkup_clkdm", |
| 925 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 906 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 926 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | 907 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
| @@ -933,8 +914,8 @@ static struct clk sys_clkout = { | |||
| 933 | /* In 2430, new in 2420 ES2 */ | 914 | /* In 2430, new in 2420 ES2 */ |
| 934 | static struct clk sys_clkout2_src = { | 915 | static struct clk sys_clkout2_src = { |
| 935 | .name = "sys_clkout2_src", | 916 | .name = "sys_clkout2_src", |
| 917 | .ops = &clkops_omap2_dflt, | ||
| 936 | .parent = &func_54m_ck, | 918 | .parent = &func_54m_ck, |
| 937 | .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, | ||
| 938 | .clkdm_name = "wkup_clkdm", | 919 | .clkdm_name = "wkup_clkdm", |
| 939 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 920 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 940 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | 921 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
| @@ -955,8 +936,8 @@ static const struct clksel sys_clkout2_clksel[] = { | |||
| 955 | /* In 2430, new in 2420 ES2 */ | 936 | /* In 2430, new in 2420 ES2 */ |
| 956 | static struct clk sys_clkout2 = { | 937 | static struct clk sys_clkout2 = { |
| 957 | .name = "sys_clkout2", | 938 | .name = "sys_clkout2", |
| 939 | .ops = &clkops_null, | ||
| 958 | .parent = &sys_clkout2_src, | 940 | .parent = &sys_clkout2_src, |
| 959 | .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, | ||
| 960 | .clkdm_name = "wkup_clkdm", | 941 | .clkdm_name = "wkup_clkdm", |
| 961 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 942 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 962 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | 943 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
| @@ -968,8 +949,8 @@ static struct clk sys_clkout2 = { | |||
| 968 | 949 | ||
| 969 | static struct clk emul_ck = { | 950 | static struct clk emul_ck = { |
| 970 | .name = "emul_ck", | 951 | .name = "emul_ck", |
| 952 | .ops = &clkops_omap2_dflt, | ||
| 971 | .parent = &func_54m_ck, | 953 | .parent = &func_54m_ck, |
| 972 | .flags = CLOCK_IN_OMAP242X, | ||
| 973 | .clkdm_name = "wkup_clkdm", | 954 | .clkdm_name = "wkup_clkdm", |
| 974 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, | 955 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, |
| 975 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | 956 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
| @@ -1003,10 +984,9 @@ static const struct clksel mpu_clksel[] = { | |||
| 1003 | 984 | ||
| 1004 | static struct clk mpu_ck = { /* Control cpu */ | 985 | static struct clk mpu_ck = { /* Control cpu */ |
| 1005 | .name = "mpu_ck", | 986 | .name = "mpu_ck", |
| 987 | .ops = &clkops_null, | ||
| 1006 | .parent = &core_ck, | 988 | .parent = &core_ck, |
| 1007 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 989 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1008 | ALWAYS_ENABLED | DELAYED_APP | | ||
| 1009 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1010 | .clkdm_name = "mpu_clkdm", | 990 | .clkdm_name = "mpu_clkdm", |
| 1011 | .init = &omap2_init_clksel_parent, | 991 | .init = &omap2_init_clksel_parent, |
| 1012 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | 992 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
| @@ -1046,9 +1026,9 @@ static const struct clksel dsp_fck_clksel[] = { | |||
| 1046 | 1026 | ||
| 1047 | static struct clk dsp_fck = { | 1027 | static struct clk dsp_fck = { |
| 1048 | .name = "dsp_fck", | 1028 | .name = "dsp_fck", |
| 1029 | .ops = &clkops_omap2_dflt_wait, | ||
| 1049 | .parent = &core_ck, | 1030 | .parent = &core_ck, |
| 1050 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | | 1031 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1051 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1052 | .clkdm_name = "dsp_clkdm", | 1032 | .clkdm_name = "dsp_clkdm", |
| 1053 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1033 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1054 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 1034 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| @@ -1076,9 +1056,9 @@ static const struct clksel dsp_irate_ick_clksel[] = { | |||
| 1076 | /* This clock does not exist as such in the TRM. */ | 1056 | /* This clock does not exist as such in the TRM. */ |
| 1077 | static struct clk dsp_irate_ick = { | 1057 | static struct clk dsp_irate_ick = { |
| 1078 | .name = "dsp_irate_ick", | 1058 | .name = "dsp_irate_ick", |
| 1059 | .ops = &clkops_null, | ||
| 1079 | .parent = &dsp_fck, | 1060 | .parent = &dsp_fck, |
| 1080 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | | 1061 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1081 | CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK, | ||
| 1082 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | 1062 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 1083 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | 1063 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
| 1084 | .clksel = dsp_irate_ick_clksel, | 1064 | .clksel = dsp_irate_ick_clksel, |
| @@ -1090,8 +1070,9 @@ static struct clk dsp_irate_ick = { | |||
| 1090 | /* 2420 only */ | 1070 | /* 2420 only */ |
| 1091 | static struct clk dsp_ick = { | 1071 | static struct clk dsp_ick = { |
| 1092 | .name = "dsp_ick", /* apparently ipi and isp */ | 1072 | .name = "dsp_ick", /* apparently ipi and isp */ |
| 1073 | .ops = &clkops_omap2_dflt_wait, | ||
| 1093 | .parent = &dsp_irate_ick, | 1074 | .parent = &dsp_irate_ick, |
| 1094 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, | 1075 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1095 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), | 1076 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
| 1096 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | 1077 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ |
| 1097 | }; | 1078 | }; |
| @@ -1099,8 +1080,9 @@ static struct clk dsp_ick = { | |||
| 1099 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ | 1080 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
| 1100 | static struct clk iva2_1_ick = { | 1081 | static struct clk iva2_1_ick = { |
| 1101 | .name = "iva2_1_ick", | 1082 | .name = "iva2_1_ick", |
| 1083 | .ops = &clkops_omap2_dflt_wait, | ||
| 1102 | .parent = &dsp_irate_ick, | 1084 | .parent = &dsp_irate_ick, |
| 1103 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, | 1085 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1104 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1086 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1105 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 1087 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| 1106 | }; | 1088 | }; |
| @@ -1112,9 +1094,9 @@ static struct clk iva2_1_ick = { | |||
| 1112 | */ | 1094 | */ |
| 1113 | static struct clk iva1_ifck = { | 1095 | static struct clk iva1_ifck = { |
| 1114 | .name = "iva1_ifck", | 1096 | .name = "iva1_ifck", |
| 1097 | .ops = &clkops_omap2_dflt_wait, | ||
| 1115 | .parent = &core_ck, | 1098 | .parent = &core_ck, |
| 1116 | .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | | 1099 | .flags = CONFIG_PARTICIPANT | DELAYED_APP, |
| 1117 | RATE_PROPAGATES | DELAYED_APP, | ||
| 1118 | .clkdm_name = "iva1_clkdm", | 1100 | .clkdm_name = "iva1_clkdm", |
| 1119 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1101 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1120 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | 1102 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
| @@ -1129,8 +1111,8 @@ static struct clk iva1_ifck = { | |||
| 1129 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | 1111 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ |
| 1130 | static struct clk iva1_mpu_int_ifck = { | 1112 | static struct clk iva1_mpu_int_ifck = { |
| 1131 | .name = "iva1_mpu_int_ifck", | 1113 | .name = "iva1_mpu_int_ifck", |
| 1114 | .ops = &clkops_omap2_dflt_wait, | ||
| 1132 | .parent = &iva1_ifck, | 1115 | .parent = &iva1_ifck, |
| 1133 | .flags = CLOCK_IN_OMAP242X, | ||
| 1134 | .clkdm_name = "iva1_clkdm", | 1116 | .clkdm_name = "iva1_clkdm", |
| 1135 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1117 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1136 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | 1118 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, |
| @@ -1175,10 +1157,9 @@ static const struct clksel core_l3_clksel[] = { | |||
| 1175 | 1157 | ||
| 1176 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | 1158 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
| 1177 | .name = "core_l3_ck", | 1159 | .name = "core_l3_ck", |
| 1160 | .ops = &clkops_null, | ||
| 1178 | .parent = &core_ck, | 1161 | .parent = &core_ck, |
| 1179 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1162 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1180 | ALWAYS_ENABLED | DELAYED_APP | | ||
| 1181 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1182 | .clkdm_name = "core_l3_clkdm", | 1163 | .clkdm_name = "core_l3_clkdm", |
| 1183 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1164 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1184 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | 1165 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
| @@ -1204,9 +1185,9 @@ static const struct clksel usb_l4_ick_clksel[] = { | |||
| 1204 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ | 1185 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
| 1205 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ | 1186 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
| 1206 | .name = "usb_l4_ick", | 1187 | .name = "usb_l4_ick", |
| 1188 | .ops = &clkops_omap2_dflt_wait, | ||
| 1207 | .parent = &core_l3_ck, | 1189 | .parent = &core_l3_ck, |
| 1208 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1190 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1209 | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 1210 | .clkdm_name = "core_l4_clkdm", | 1191 | .clkdm_name = "core_l4_clkdm", |
| 1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1192 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1212 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 1193 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| @@ -1238,9 +1219,9 @@ static const struct clksel l4_clksel[] = { | |||
| 1238 | 1219 | ||
| 1239 | static struct clk l4_ck = { /* used both as an ick and fck */ | 1220 | static struct clk l4_ck = { /* used both as an ick and fck */ |
| 1240 | .name = "l4_ck", | 1221 | .name = "l4_ck", |
| 1222 | .ops = &clkops_null, | ||
| 1241 | .parent = &core_l3_ck, | 1223 | .parent = &core_l3_ck, |
| 1242 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1224 | .flags = DELAYED_APP, |
| 1243 | ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, | ||
| 1244 | .clkdm_name = "core_l4_clkdm", | 1225 | .clkdm_name = "core_l4_clkdm", |
| 1245 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1226 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1246 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | 1227 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
| @@ -1276,9 +1257,9 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |||
| 1276 | 1257 | ||
| 1277 | static struct clk ssi_ssr_sst_fck = { | 1258 | static struct clk ssi_ssr_sst_fck = { |
| 1278 | .name = "ssi_fck", | 1259 | .name = "ssi_fck", |
| 1260 | .ops = &clkops_omap2_dflt_wait, | ||
| 1279 | .parent = &core_ck, | 1261 | .parent = &core_ck, |
| 1280 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1262 | .flags = DELAYED_APP, |
| 1281 | DELAYED_APP, | ||
| 1282 | .clkdm_name = "core_l3_clkdm", | 1263 | .clkdm_name = "core_l3_clkdm", |
| 1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1264 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1284 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | 1265 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| @@ -1290,6 +1271,20 @@ static struct clk ssi_ssr_sst_fck = { | |||
| 1290 | .set_rate = &omap2_clksel_set_rate | 1271 | .set_rate = &omap2_clksel_set_rate |
| 1291 | }; | 1272 | }; |
| 1292 | 1273 | ||
| 1274 | /* | ||
| 1275 | * Presumably this is the same as SSI_ICLK. | ||
| 1276 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | ||
| 1277 | */ | ||
| 1278 | static struct clk ssi_l4_ick = { | ||
| 1279 | .name = "ssi_l4_ick", | ||
| 1280 | .ops = &clkops_omap2_dflt_wait, | ||
| 1281 | .parent = &l4_ck, | ||
| 1282 | .clkdm_name = "core_l4_clkdm", | ||
| 1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1284 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
| 1285 | .recalc = &followparent_recalc, | ||
| 1286 | }; | ||
| 1287 | |||
| 1293 | 1288 | ||
| 1294 | /* | 1289 | /* |
| 1295 | * GFX clock domain | 1290 | * GFX clock domain |
| @@ -1312,8 +1307,8 @@ static const struct clksel gfx_fck_clksel[] = { | |||
| 1312 | 1307 | ||
| 1313 | static struct clk gfx_3d_fck = { | 1308 | static struct clk gfx_3d_fck = { |
| 1314 | .name = "gfx_3d_fck", | 1309 | .name = "gfx_3d_fck", |
| 1310 | .ops = &clkops_omap2_dflt_wait, | ||
| 1315 | .parent = &core_l3_ck, | 1311 | .parent = &core_l3_ck, |
| 1316 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1317 | .clkdm_name = "gfx_clkdm", | 1312 | .clkdm_name = "gfx_clkdm", |
| 1318 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1313 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1319 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | 1314 | .enable_bit = OMAP24XX_EN_3D_SHIFT, |
| @@ -1327,8 +1322,8 @@ static struct clk gfx_3d_fck = { | |||
| 1327 | 1322 | ||
| 1328 | static struct clk gfx_2d_fck = { | 1323 | static struct clk gfx_2d_fck = { |
| 1329 | .name = "gfx_2d_fck", | 1324 | .name = "gfx_2d_fck", |
| 1325 | .ops = &clkops_omap2_dflt_wait, | ||
| 1330 | .parent = &core_l3_ck, | 1326 | .parent = &core_l3_ck, |
| 1331 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1332 | .clkdm_name = "gfx_clkdm", | 1327 | .clkdm_name = "gfx_clkdm", |
| 1333 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1328 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1334 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | 1329 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
| @@ -1342,8 +1337,8 @@ static struct clk gfx_2d_fck = { | |||
| 1342 | 1337 | ||
| 1343 | static struct clk gfx_ick = { | 1338 | static struct clk gfx_ick = { |
| 1344 | .name = "gfx_ick", /* From l3 */ | 1339 | .name = "gfx_ick", /* From l3 */ |
| 1340 | .ops = &clkops_omap2_dflt_wait, | ||
| 1345 | .parent = &core_l3_ck, | 1341 | .parent = &core_l3_ck, |
| 1346 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1347 | .clkdm_name = "gfx_clkdm", | 1342 | .clkdm_name = "gfx_clkdm", |
| 1348 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | 1343 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1349 | .enable_bit = OMAP_EN_GFX_SHIFT, | 1344 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| @@ -1372,8 +1367,9 @@ static const struct clksel mdm_ick_clksel[] = { | |||
| 1372 | 1367 | ||
| 1373 | static struct clk mdm_ick = { /* used both as a ick and fck */ | 1368 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
| 1374 | .name = "mdm_ick", | 1369 | .name = "mdm_ick", |
| 1370 | .ops = &clkops_omap2_dflt_wait, | ||
| 1375 | .parent = &core_ck, | 1371 | .parent = &core_ck, |
| 1376 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, | 1372 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1377 | .clkdm_name = "mdm_clkdm", | 1373 | .clkdm_name = "mdm_clkdm", |
| 1378 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), | 1374 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
| 1379 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | 1375 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, |
| @@ -1387,8 +1383,8 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ | |||
| 1387 | 1383 | ||
| 1388 | static struct clk mdm_osc_ck = { | 1384 | static struct clk mdm_osc_ck = { |
| 1389 | .name = "mdm_osc_ck", | 1385 | .name = "mdm_osc_ck", |
| 1386 | .ops = &clkops_omap2_dflt_wait, | ||
| 1390 | .parent = &osc_ck, | 1387 | .parent = &osc_ck, |
| 1391 | .flags = CLOCK_IN_OMAP243X, | ||
| 1392 | .clkdm_name = "mdm_clkdm", | 1388 | .clkdm_name = "mdm_clkdm", |
| 1393 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), | 1389 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
| 1394 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | 1390 | .enable_bit = OMAP2430_EN_OSC_SHIFT, |
| @@ -1432,8 +1428,8 @@ static const struct clksel dss1_fck_clksel[] = { | |||
| 1432 | 1428 | ||
| 1433 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | 1429 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
| 1434 | .name = "dss_ick", | 1430 | .name = "dss_ick", |
| 1431 | .ops = &clkops_omap2_dflt, | ||
| 1435 | .parent = &l4_ck, /* really both l3 and l4 */ | 1432 | .parent = &l4_ck, /* really both l3 and l4 */ |
| 1436 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1437 | .clkdm_name = "dss_clkdm", | 1433 | .clkdm_name = "dss_clkdm", |
| 1438 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1434 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1439 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 1435 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| @@ -1442,9 +1438,9 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | |||
| 1442 | 1438 | ||
| 1443 | static struct clk dss1_fck = { | 1439 | static struct clk dss1_fck = { |
| 1444 | .name = "dss1_fck", | 1440 | .name = "dss1_fck", |
| 1441 | .ops = &clkops_omap2_dflt, | ||
| 1445 | .parent = &core_ck, /* Core or sys */ | 1442 | .parent = &core_ck, /* Core or sys */ |
| 1446 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1443 | .flags = DELAYED_APP, |
| 1447 | DELAYED_APP, | ||
| 1448 | .clkdm_name = "dss_clkdm", | 1444 | .clkdm_name = "dss_clkdm", |
| 1449 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1445 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1450 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 1446 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| @@ -1475,9 +1471,9 @@ static const struct clksel dss2_fck_clksel[] = { | |||
| 1475 | 1471 | ||
| 1476 | static struct clk dss2_fck = { /* Alt clk used in power management */ | 1472 | static struct clk dss2_fck = { /* Alt clk used in power management */ |
| 1477 | .name = "dss2_fck", | 1473 | .name = "dss2_fck", |
| 1474 | .ops = &clkops_omap2_dflt, | ||
| 1478 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | 1475 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
| 1479 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1476 | .flags = DELAYED_APP, |
| 1480 | DELAYED_APP, | ||
| 1481 | .clkdm_name = "dss_clkdm", | 1477 | .clkdm_name = "dss_clkdm", |
| 1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1478 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1483 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | 1479 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
| @@ -1490,8 +1486,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
| 1490 | 1486 | ||
| 1491 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | 1487 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| 1492 | .name = "dss_54m_fck", /* 54m tv clk */ | 1488 | .name = "dss_54m_fck", /* 54m tv clk */ |
| 1489 | .ops = &clkops_omap2_dflt_wait, | ||
| 1493 | .parent = &func_54m_ck, | 1490 | .parent = &func_54m_ck, |
| 1494 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1495 | .clkdm_name = "dss_clkdm", | 1491 | .clkdm_name = "dss_clkdm", |
| 1496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1492 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1497 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | 1493 | .enable_bit = OMAP24XX_EN_TV_SHIFT, |
| @@ -1518,8 +1514,8 @@ static const struct clksel omap24xx_gpt_clksel[] = { | |||
| 1518 | 1514 | ||
| 1519 | static struct clk gpt1_ick = { | 1515 | static struct clk gpt1_ick = { |
| 1520 | .name = "gpt1_ick", | 1516 | .name = "gpt1_ick", |
| 1517 | .ops = &clkops_omap2_dflt_wait, | ||
| 1521 | .parent = &l4_ck, | 1518 | .parent = &l4_ck, |
| 1522 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1523 | .clkdm_name = "core_l4_clkdm", | 1519 | .clkdm_name = "core_l4_clkdm", |
| 1524 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 1520 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1525 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | 1521 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| @@ -1528,8 +1524,8 @@ static struct clk gpt1_ick = { | |||
| 1528 | 1524 | ||
| 1529 | static struct clk gpt1_fck = { | 1525 | static struct clk gpt1_fck = { |
| 1530 | .name = "gpt1_fck", | 1526 | .name = "gpt1_fck", |
| 1527 | .ops = &clkops_omap2_dflt_wait, | ||
| 1531 | .parent = &func_32k_ck, | 1528 | .parent = &func_32k_ck, |
| 1532 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1533 | .clkdm_name = "core_l4_clkdm", | 1529 | .clkdm_name = "core_l4_clkdm", |
| 1534 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 1530 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1535 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | 1531 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| @@ -1544,8 +1540,8 @@ static struct clk gpt1_fck = { | |||
| 1544 | 1540 | ||
| 1545 | static struct clk gpt2_ick = { | 1541 | static struct clk gpt2_ick = { |
| 1546 | .name = "gpt2_ick", | 1542 | .name = "gpt2_ick", |
| 1543 | .ops = &clkops_omap2_dflt_wait, | ||
| 1547 | .parent = &l4_ck, | 1544 | .parent = &l4_ck, |
| 1548 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1549 | .clkdm_name = "core_l4_clkdm", | 1545 | .clkdm_name = "core_l4_clkdm", |
| 1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1546 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1551 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | 1547 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| @@ -1554,8 +1550,8 @@ static struct clk gpt2_ick = { | |||
| 1554 | 1550 | ||
| 1555 | static struct clk gpt2_fck = { | 1551 | static struct clk gpt2_fck = { |
| 1556 | .name = "gpt2_fck", | 1552 | .name = "gpt2_fck", |
| 1553 | .ops = &clkops_omap2_dflt_wait, | ||
| 1557 | .parent = &func_32k_ck, | 1554 | .parent = &func_32k_ck, |
| 1558 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1559 | .clkdm_name = "core_l4_clkdm", | 1555 | .clkdm_name = "core_l4_clkdm", |
| 1560 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1556 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1561 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | 1557 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| @@ -1568,8 +1564,8 @@ static struct clk gpt2_fck = { | |||
| 1568 | 1564 | ||
| 1569 | static struct clk gpt3_ick = { | 1565 | static struct clk gpt3_ick = { |
| 1570 | .name = "gpt3_ick", | 1566 | .name = "gpt3_ick", |
| 1567 | .ops = &clkops_omap2_dflt_wait, | ||
| 1571 | .parent = &l4_ck, | 1568 | .parent = &l4_ck, |
| 1572 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1573 | .clkdm_name = "core_l4_clkdm", | 1569 | .clkdm_name = "core_l4_clkdm", |
| 1574 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1575 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | 1571 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| @@ -1578,8 +1574,8 @@ static struct clk gpt3_ick = { | |||
| 1578 | 1574 | ||
| 1579 | static struct clk gpt3_fck = { | 1575 | static struct clk gpt3_fck = { |
| 1580 | .name = "gpt3_fck", | 1576 | .name = "gpt3_fck", |
| 1577 | .ops = &clkops_omap2_dflt_wait, | ||
| 1581 | .parent = &func_32k_ck, | 1578 | .parent = &func_32k_ck, |
| 1582 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1583 | .clkdm_name = "core_l4_clkdm", | 1579 | .clkdm_name = "core_l4_clkdm", |
| 1584 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1580 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1585 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | 1581 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| @@ -1592,8 +1588,8 @@ static struct clk gpt3_fck = { | |||
| 1592 | 1588 | ||
| 1593 | static struct clk gpt4_ick = { | 1589 | static struct clk gpt4_ick = { |
| 1594 | .name = "gpt4_ick", | 1590 | .name = "gpt4_ick", |
| 1591 | .ops = &clkops_omap2_dflt_wait, | ||
| 1595 | .parent = &l4_ck, | 1592 | .parent = &l4_ck, |
| 1596 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1597 | .clkdm_name = "core_l4_clkdm", | 1593 | .clkdm_name = "core_l4_clkdm", |
| 1598 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1594 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1599 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | 1595 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| @@ -1602,8 +1598,8 @@ static struct clk gpt4_ick = { | |||
| 1602 | 1598 | ||
| 1603 | static struct clk gpt4_fck = { | 1599 | static struct clk gpt4_fck = { |
| 1604 | .name = "gpt4_fck", | 1600 | .name = "gpt4_fck", |
| 1601 | .ops = &clkops_omap2_dflt_wait, | ||
| 1605 | .parent = &func_32k_ck, | 1602 | .parent = &func_32k_ck, |
| 1606 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1607 | .clkdm_name = "core_l4_clkdm", | 1603 | .clkdm_name = "core_l4_clkdm", |
| 1608 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1604 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1609 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | 1605 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| @@ -1616,8 +1612,8 @@ static struct clk gpt4_fck = { | |||
| 1616 | 1612 | ||
| 1617 | static struct clk gpt5_ick = { | 1613 | static struct clk gpt5_ick = { |
| 1618 | .name = "gpt5_ick", | 1614 | .name = "gpt5_ick", |
| 1615 | .ops = &clkops_omap2_dflt_wait, | ||
| 1619 | .parent = &l4_ck, | 1616 | .parent = &l4_ck, |
| 1620 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1621 | .clkdm_name = "core_l4_clkdm", | 1617 | .clkdm_name = "core_l4_clkdm", |
| 1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1618 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1623 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | 1619 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| @@ -1626,8 +1622,8 @@ static struct clk gpt5_ick = { | |||
| 1626 | 1622 | ||
| 1627 | static struct clk gpt5_fck = { | 1623 | static struct clk gpt5_fck = { |
| 1628 | .name = "gpt5_fck", | 1624 | .name = "gpt5_fck", |
| 1625 | .ops = &clkops_omap2_dflt_wait, | ||
| 1629 | .parent = &func_32k_ck, | 1626 | .parent = &func_32k_ck, |
| 1630 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1631 | .clkdm_name = "core_l4_clkdm", | 1627 | .clkdm_name = "core_l4_clkdm", |
| 1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1628 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1633 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | 1629 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| @@ -1640,8 +1636,8 @@ static struct clk gpt5_fck = { | |||
| 1640 | 1636 | ||
| 1641 | static struct clk gpt6_ick = { | 1637 | static struct clk gpt6_ick = { |
| 1642 | .name = "gpt6_ick", | 1638 | .name = "gpt6_ick", |
| 1639 | .ops = &clkops_omap2_dflt_wait, | ||
| 1643 | .parent = &l4_ck, | 1640 | .parent = &l4_ck, |
| 1644 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1645 | .clkdm_name = "core_l4_clkdm", | 1641 | .clkdm_name = "core_l4_clkdm", |
| 1646 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1642 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1647 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | 1643 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| @@ -1650,8 +1646,8 @@ static struct clk gpt6_ick = { | |||
| 1650 | 1646 | ||
| 1651 | static struct clk gpt6_fck = { | 1647 | static struct clk gpt6_fck = { |
| 1652 | .name = "gpt6_fck", | 1648 | .name = "gpt6_fck", |
| 1649 | .ops = &clkops_omap2_dflt_wait, | ||
| 1653 | .parent = &func_32k_ck, | 1650 | .parent = &func_32k_ck, |
| 1654 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1655 | .clkdm_name = "core_l4_clkdm", | 1651 | .clkdm_name = "core_l4_clkdm", |
| 1656 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1657 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | 1653 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| @@ -1664,8 +1660,8 @@ static struct clk gpt6_fck = { | |||
| 1664 | 1660 | ||
| 1665 | static struct clk gpt7_ick = { | 1661 | static struct clk gpt7_ick = { |
| 1666 | .name = "gpt7_ick", | 1662 | .name = "gpt7_ick", |
| 1663 | .ops = &clkops_omap2_dflt_wait, | ||
| 1667 | .parent = &l4_ck, | 1664 | .parent = &l4_ck, |
| 1668 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1669 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1670 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | 1666 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 1671 | .recalc = &followparent_recalc, | 1667 | .recalc = &followparent_recalc, |
| @@ -1673,8 +1669,8 @@ static struct clk gpt7_ick = { | |||
| 1673 | 1669 | ||
| 1674 | static struct clk gpt7_fck = { | 1670 | static struct clk gpt7_fck = { |
| 1675 | .name = "gpt7_fck", | 1671 | .name = "gpt7_fck", |
| 1672 | .ops = &clkops_omap2_dflt_wait, | ||
| 1676 | .parent = &func_32k_ck, | 1673 | .parent = &func_32k_ck, |
| 1677 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1678 | .clkdm_name = "core_l4_clkdm", | 1674 | .clkdm_name = "core_l4_clkdm", |
| 1679 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1675 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1680 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | 1676 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| @@ -1687,8 +1683,8 @@ static struct clk gpt7_fck = { | |||
| 1687 | 1683 | ||
| 1688 | static struct clk gpt8_ick = { | 1684 | static struct clk gpt8_ick = { |
| 1689 | .name = "gpt8_ick", | 1685 | .name = "gpt8_ick", |
| 1686 | .ops = &clkops_omap2_dflt_wait, | ||
| 1690 | .parent = &l4_ck, | 1687 | .parent = &l4_ck, |
| 1691 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1692 | .clkdm_name = "core_l4_clkdm", | 1688 | .clkdm_name = "core_l4_clkdm", |
| 1693 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1689 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1694 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | 1690 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| @@ -1697,8 +1693,8 @@ static struct clk gpt8_ick = { | |||
| 1697 | 1693 | ||
| 1698 | static struct clk gpt8_fck = { | 1694 | static struct clk gpt8_fck = { |
| 1699 | .name = "gpt8_fck", | 1695 | .name = "gpt8_fck", |
| 1696 | .ops = &clkops_omap2_dflt_wait, | ||
| 1700 | .parent = &func_32k_ck, | 1697 | .parent = &func_32k_ck, |
| 1701 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1702 | .clkdm_name = "core_l4_clkdm", | 1698 | .clkdm_name = "core_l4_clkdm", |
| 1703 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1699 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1704 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | 1700 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| @@ -1711,8 +1707,8 @@ static struct clk gpt8_fck = { | |||
| 1711 | 1707 | ||
| 1712 | static struct clk gpt9_ick = { | 1708 | static struct clk gpt9_ick = { |
| 1713 | .name = "gpt9_ick", | 1709 | .name = "gpt9_ick", |
| 1710 | .ops = &clkops_omap2_dflt_wait, | ||
| 1714 | .parent = &l4_ck, | 1711 | .parent = &l4_ck, |
| 1715 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1716 | .clkdm_name = "core_l4_clkdm", | 1712 | .clkdm_name = "core_l4_clkdm", |
| 1717 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1713 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1718 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | 1714 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| @@ -1721,8 +1717,8 @@ static struct clk gpt9_ick = { | |||
| 1721 | 1717 | ||
| 1722 | static struct clk gpt9_fck = { | 1718 | static struct clk gpt9_fck = { |
| 1723 | .name = "gpt9_fck", | 1719 | .name = "gpt9_fck", |
| 1720 | .ops = &clkops_omap2_dflt_wait, | ||
| 1724 | .parent = &func_32k_ck, | 1721 | .parent = &func_32k_ck, |
| 1725 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1726 | .clkdm_name = "core_l4_clkdm", | 1722 | .clkdm_name = "core_l4_clkdm", |
| 1727 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1723 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1728 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | 1724 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| @@ -1735,8 +1731,8 @@ static struct clk gpt9_fck = { | |||
| 1735 | 1731 | ||
| 1736 | static struct clk gpt10_ick = { | 1732 | static struct clk gpt10_ick = { |
| 1737 | .name = "gpt10_ick", | 1733 | .name = "gpt10_ick", |
| 1734 | .ops = &clkops_omap2_dflt_wait, | ||
| 1738 | .parent = &l4_ck, | 1735 | .parent = &l4_ck, |
| 1739 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1740 | .clkdm_name = "core_l4_clkdm", | 1736 | .clkdm_name = "core_l4_clkdm", |
| 1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1737 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1742 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | 1738 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| @@ -1745,8 +1741,8 @@ static struct clk gpt10_ick = { | |||
| 1745 | 1741 | ||
| 1746 | static struct clk gpt10_fck = { | 1742 | static struct clk gpt10_fck = { |
| 1747 | .name = "gpt10_fck", | 1743 | .name = "gpt10_fck", |
| 1744 | .ops = &clkops_omap2_dflt_wait, | ||
| 1748 | .parent = &func_32k_ck, | 1745 | .parent = &func_32k_ck, |
| 1749 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1750 | .clkdm_name = "core_l4_clkdm", | 1746 | .clkdm_name = "core_l4_clkdm", |
| 1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1747 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1752 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | 1748 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| @@ -1759,8 +1755,8 @@ static struct clk gpt10_fck = { | |||
| 1759 | 1755 | ||
| 1760 | static struct clk gpt11_ick = { | 1756 | static struct clk gpt11_ick = { |
| 1761 | .name = "gpt11_ick", | 1757 | .name = "gpt11_ick", |
| 1758 | .ops = &clkops_omap2_dflt_wait, | ||
| 1762 | .parent = &l4_ck, | 1759 | .parent = &l4_ck, |
| 1763 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1764 | .clkdm_name = "core_l4_clkdm", | 1760 | .clkdm_name = "core_l4_clkdm", |
| 1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1761 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1766 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | 1762 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| @@ -1769,8 +1765,8 @@ static struct clk gpt11_ick = { | |||
| 1769 | 1765 | ||
| 1770 | static struct clk gpt11_fck = { | 1766 | static struct clk gpt11_fck = { |
| 1771 | .name = "gpt11_fck", | 1767 | .name = "gpt11_fck", |
| 1768 | .ops = &clkops_omap2_dflt_wait, | ||
| 1772 | .parent = &func_32k_ck, | 1769 | .parent = &func_32k_ck, |
| 1773 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1774 | .clkdm_name = "core_l4_clkdm", | 1770 | .clkdm_name = "core_l4_clkdm", |
| 1775 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1776 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | 1772 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| @@ -1783,8 +1779,8 @@ static struct clk gpt11_fck = { | |||
| 1783 | 1779 | ||
| 1784 | static struct clk gpt12_ick = { | 1780 | static struct clk gpt12_ick = { |
| 1785 | .name = "gpt12_ick", | 1781 | .name = "gpt12_ick", |
| 1782 | .ops = &clkops_omap2_dflt_wait, | ||
| 1786 | .parent = &l4_ck, | 1783 | .parent = &l4_ck, |
| 1787 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1788 | .clkdm_name = "core_l4_clkdm", | 1784 | .clkdm_name = "core_l4_clkdm", |
| 1789 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1785 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1790 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | 1786 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| @@ -1793,8 +1789,8 @@ static struct clk gpt12_ick = { | |||
| 1793 | 1789 | ||
| 1794 | static struct clk gpt12_fck = { | 1790 | static struct clk gpt12_fck = { |
| 1795 | .name = "gpt12_fck", | 1791 | .name = "gpt12_fck", |
| 1792 | .ops = &clkops_omap2_dflt_wait, | ||
| 1796 | .parent = &func_32k_ck, | 1793 | .parent = &func_32k_ck, |
| 1797 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1798 | .clkdm_name = "core_l4_clkdm", | 1794 | .clkdm_name = "core_l4_clkdm", |
| 1799 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1795 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1800 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | 1796 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| @@ -1807,9 +1803,9 @@ static struct clk gpt12_fck = { | |||
| 1807 | 1803 | ||
| 1808 | static struct clk mcbsp1_ick = { | 1804 | static struct clk mcbsp1_ick = { |
| 1809 | .name = "mcbsp_ick", | 1805 | .name = "mcbsp_ick", |
| 1806 | .ops = &clkops_omap2_dflt_wait, | ||
| 1810 | .id = 1, | 1807 | .id = 1, |
| 1811 | .parent = &l4_ck, | 1808 | .parent = &l4_ck, |
| 1812 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1813 | .clkdm_name = "core_l4_clkdm", | 1809 | .clkdm_name = "core_l4_clkdm", |
| 1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1810 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1815 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | 1811 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| @@ -1818,9 +1814,9 @@ static struct clk mcbsp1_ick = { | |||
| 1818 | 1814 | ||
| 1819 | static struct clk mcbsp1_fck = { | 1815 | static struct clk mcbsp1_fck = { |
| 1820 | .name = "mcbsp_fck", | 1816 | .name = "mcbsp_fck", |
| 1817 | .ops = &clkops_omap2_dflt_wait, | ||
| 1821 | .id = 1, | 1818 | .id = 1, |
| 1822 | .parent = &func_96m_ck, | 1819 | .parent = &func_96m_ck, |
| 1823 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1824 | .clkdm_name = "core_l4_clkdm", | 1820 | .clkdm_name = "core_l4_clkdm", |
| 1825 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1821 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1826 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | 1822 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| @@ -1829,9 +1825,9 @@ static struct clk mcbsp1_fck = { | |||
| 1829 | 1825 | ||
| 1830 | static struct clk mcbsp2_ick = { | 1826 | static struct clk mcbsp2_ick = { |
| 1831 | .name = "mcbsp_ick", | 1827 | .name = "mcbsp_ick", |
| 1828 | .ops = &clkops_omap2_dflt_wait, | ||
| 1832 | .id = 2, | 1829 | .id = 2, |
| 1833 | .parent = &l4_ck, | 1830 | .parent = &l4_ck, |
| 1834 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1835 | .clkdm_name = "core_l4_clkdm", | 1831 | .clkdm_name = "core_l4_clkdm", |
| 1836 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1832 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1837 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | 1833 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| @@ -1840,9 +1836,9 @@ static struct clk mcbsp2_ick = { | |||
| 1840 | 1836 | ||
| 1841 | static struct clk mcbsp2_fck = { | 1837 | static struct clk mcbsp2_fck = { |
| 1842 | .name = "mcbsp_fck", | 1838 | .name = "mcbsp_fck", |
| 1839 | .ops = &clkops_omap2_dflt_wait, | ||
| 1843 | .id = 2, | 1840 | .id = 2, |
| 1844 | .parent = &func_96m_ck, | 1841 | .parent = &func_96m_ck, |
| 1845 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1846 | .clkdm_name = "core_l4_clkdm", | 1842 | .clkdm_name = "core_l4_clkdm", |
| 1847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1843 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1848 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | 1844 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| @@ -1851,9 +1847,9 @@ static struct clk mcbsp2_fck = { | |||
| 1851 | 1847 | ||
| 1852 | static struct clk mcbsp3_ick = { | 1848 | static struct clk mcbsp3_ick = { |
| 1853 | .name = "mcbsp_ick", | 1849 | .name = "mcbsp_ick", |
| 1850 | .ops = &clkops_omap2_dflt_wait, | ||
| 1854 | .id = 3, | 1851 | .id = 3, |
| 1855 | .parent = &l4_ck, | 1852 | .parent = &l4_ck, |
| 1856 | .flags = CLOCK_IN_OMAP243X, | ||
| 1857 | .clkdm_name = "core_l4_clkdm", | 1853 | .clkdm_name = "core_l4_clkdm", |
| 1858 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1854 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1859 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | 1855 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| @@ -1862,9 +1858,9 @@ static struct clk mcbsp3_ick = { | |||
| 1862 | 1858 | ||
| 1863 | static struct clk mcbsp3_fck = { | 1859 | static struct clk mcbsp3_fck = { |
| 1864 | .name = "mcbsp_fck", | 1860 | .name = "mcbsp_fck", |
| 1861 | .ops = &clkops_omap2_dflt_wait, | ||
| 1865 | .id = 3, | 1862 | .id = 3, |
| 1866 | .parent = &func_96m_ck, | 1863 | .parent = &func_96m_ck, |
| 1867 | .flags = CLOCK_IN_OMAP243X, | ||
| 1868 | .clkdm_name = "core_l4_clkdm", | 1864 | .clkdm_name = "core_l4_clkdm", |
| 1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1865 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1870 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | 1866 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| @@ -1873,9 +1869,9 @@ static struct clk mcbsp3_fck = { | |||
| 1873 | 1869 | ||
| 1874 | static struct clk mcbsp4_ick = { | 1870 | static struct clk mcbsp4_ick = { |
| 1875 | .name = "mcbsp_ick", | 1871 | .name = "mcbsp_ick", |
| 1872 | .ops = &clkops_omap2_dflt_wait, | ||
| 1876 | .id = 4, | 1873 | .id = 4, |
| 1877 | .parent = &l4_ck, | 1874 | .parent = &l4_ck, |
| 1878 | .flags = CLOCK_IN_OMAP243X, | ||
| 1879 | .clkdm_name = "core_l4_clkdm", | 1875 | .clkdm_name = "core_l4_clkdm", |
| 1880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1876 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1881 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | 1877 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| @@ -1884,9 +1880,9 @@ static struct clk mcbsp4_ick = { | |||
| 1884 | 1880 | ||
| 1885 | static struct clk mcbsp4_fck = { | 1881 | static struct clk mcbsp4_fck = { |
| 1886 | .name = "mcbsp_fck", | 1882 | .name = "mcbsp_fck", |
| 1883 | .ops = &clkops_omap2_dflt_wait, | ||
| 1887 | .id = 4, | 1884 | .id = 4, |
| 1888 | .parent = &func_96m_ck, | 1885 | .parent = &func_96m_ck, |
| 1889 | .flags = CLOCK_IN_OMAP243X, | ||
| 1890 | .clkdm_name = "core_l4_clkdm", | 1886 | .clkdm_name = "core_l4_clkdm", |
| 1891 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1887 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1892 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | 1888 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| @@ -1895,9 +1891,9 @@ static struct clk mcbsp4_fck = { | |||
| 1895 | 1891 | ||
| 1896 | static struct clk mcbsp5_ick = { | 1892 | static struct clk mcbsp5_ick = { |
| 1897 | .name = "mcbsp_ick", | 1893 | .name = "mcbsp_ick", |
| 1894 | .ops = &clkops_omap2_dflt_wait, | ||
| 1898 | .id = 5, | 1895 | .id = 5, |
| 1899 | .parent = &l4_ck, | 1896 | .parent = &l4_ck, |
| 1900 | .flags = CLOCK_IN_OMAP243X, | ||
| 1901 | .clkdm_name = "core_l4_clkdm", | 1897 | .clkdm_name = "core_l4_clkdm", |
| 1902 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1898 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1903 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | 1899 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| @@ -1906,9 +1902,9 @@ static struct clk mcbsp5_ick = { | |||
| 1906 | 1902 | ||
| 1907 | static struct clk mcbsp5_fck = { | 1903 | static struct clk mcbsp5_fck = { |
| 1908 | .name = "mcbsp_fck", | 1904 | .name = "mcbsp_fck", |
| 1905 | .ops = &clkops_omap2_dflt_wait, | ||
| 1909 | .id = 5, | 1906 | .id = 5, |
| 1910 | .parent = &func_96m_ck, | 1907 | .parent = &func_96m_ck, |
| 1911 | .flags = CLOCK_IN_OMAP243X, | ||
| 1912 | .clkdm_name = "core_l4_clkdm", | 1908 | .clkdm_name = "core_l4_clkdm", |
| 1913 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1909 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1914 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | 1910 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| @@ -1917,10 +1913,10 @@ static struct clk mcbsp5_fck = { | |||
| 1917 | 1913 | ||
| 1918 | static struct clk mcspi1_ick = { | 1914 | static struct clk mcspi1_ick = { |
| 1919 | .name = "mcspi_ick", | 1915 | .name = "mcspi_ick", |
| 1916 | .ops = &clkops_omap2_dflt_wait, | ||
| 1920 | .id = 1, | 1917 | .id = 1, |
| 1921 | .parent = &l4_ck, | 1918 | .parent = &l4_ck, |
| 1922 | .clkdm_name = "core_l4_clkdm", | 1919 | .clkdm_name = "core_l4_clkdm", |
| 1923 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1924 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1920 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1925 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | 1921 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1926 | .recalc = &followparent_recalc, | 1922 | .recalc = &followparent_recalc, |
| @@ -1928,9 +1924,9 @@ static struct clk mcspi1_ick = { | |||
| 1928 | 1924 | ||
| 1929 | static struct clk mcspi1_fck = { | 1925 | static struct clk mcspi1_fck = { |
| 1930 | .name = "mcspi_fck", | 1926 | .name = "mcspi_fck", |
| 1927 | .ops = &clkops_omap2_dflt_wait, | ||
| 1931 | .id = 1, | 1928 | .id = 1, |
| 1932 | .parent = &func_48m_ck, | 1929 | .parent = &func_48m_ck, |
| 1933 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1934 | .clkdm_name = "core_l4_clkdm", | 1930 | .clkdm_name = "core_l4_clkdm", |
| 1935 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1931 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1936 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | 1932 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| @@ -1939,9 +1935,9 @@ static struct clk mcspi1_fck = { | |||
| 1939 | 1935 | ||
| 1940 | static struct clk mcspi2_ick = { | 1936 | static struct clk mcspi2_ick = { |
| 1941 | .name = "mcspi_ick", | 1937 | .name = "mcspi_ick", |
| 1938 | .ops = &clkops_omap2_dflt_wait, | ||
| 1942 | .id = 2, | 1939 | .id = 2, |
| 1943 | .parent = &l4_ck, | 1940 | .parent = &l4_ck, |
| 1944 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1945 | .clkdm_name = "core_l4_clkdm", | 1941 | .clkdm_name = "core_l4_clkdm", |
| 1946 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1947 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | 1943 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| @@ -1950,9 +1946,9 @@ static struct clk mcspi2_ick = { | |||
| 1950 | 1946 | ||
| 1951 | static struct clk mcspi2_fck = { | 1947 | static struct clk mcspi2_fck = { |
| 1952 | .name = "mcspi_fck", | 1948 | .name = "mcspi_fck", |
| 1949 | .ops = &clkops_omap2_dflt_wait, | ||
| 1953 | .id = 2, | 1950 | .id = 2, |
| 1954 | .parent = &func_48m_ck, | 1951 | .parent = &func_48m_ck, |
| 1955 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1956 | .clkdm_name = "core_l4_clkdm", | 1952 | .clkdm_name = "core_l4_clkdm", |
| 1957 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1953 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1958 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | 1954 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| @@ -1961,9 +1957,9 @@ static struct clk mcspi2_fck = { | |||
| 1961 | 1957 | ||
| 1962 | static struct clk mcspi3_ick = { | 1958 | static struct clk mcspi3_ick = { |
| 1963 | .name = "mcspi_ick", | 1959 | .name = "mcspi_ick", |
| 1960 | .ops = &clkops_omap2_dflt_wait, | ||
| 1964 | .id = 3, | 1961 | .id = 3, |
| 1965 | .parent = &l4_ck, | 1962 | .parent = &l4_ck, |
| 1966 | .flags = CLOCK_IN_OMAP243X, | ||
| 1967 | .clkdm_name = "core_l4_clkdm", | 1963 | .clkdm_name = "core_l4_clkdm", |
| 1968 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1964 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1969 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | 1965 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| @@ -1972,9 +1968,9 @@ static struct clk mcspi3_ick = { | |||
| 1972 | 1968 | ||
| 1973 | static struct clk mcspi3_fck = { | 1969 | static struct clk mcspi3_fck = { |
| 1974 | .name = "mcspi_fck", | 1970 | .name = "mcspi_fck", |
| 1971 | .ops = &clkops_omap2_dflt_wait, | ||
| 1975 | .id = 3, | 1972 | .id = 3, |
| 1976 | .parent = &func_48m_ck, | 1973 | .parent = &func_48m_ck, |
| 1977 | .flags = CLOCK_IN_OMAP243X, | ||
| 1978 | .clkdm_name = "core_l4_clkdm", | 1974 | .clkdm_name = "core_l4_clkdm", |
| 1979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1975 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1980 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | 1976 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| @@ -1983,8 +1979,8 @@ static struct clk mcspi3_fck = { | |||
| 1983 | 1979 | ||
| 1984 | static struct clk uart1_ick = { | 1980 | static struct clk uart1_ick = { |
| 1985 | .name = "uart1_ick", | 1981 | .name = "uart1_ick", |
| 1982 | .ops = &clkops_omap2_dflt_wait, | ||
| 1986 | .parent = &l4_ck, | 1983 | .parent = &l4_ck, |
| 1987 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1988 | .clkdm_name = "core_l4_clkdm", | 1984 | .clkdm_name = "core_l4_clkdm", |
| 1989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1985 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1990 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | 1986 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| @@ -1993,8 +1989,8 @@ static struct clk uart1_ick = { | |||
| 1993 | 1989 | ||
| 1994 | static struct clk uart1_fck = { | 1990 | static struct clk uart1_fck = { |
| 1995 | .name = "uart1_fck", | 1991 | .name = "uart1_fck", |
| 1992 | .ops = &clkops_omap2_dflt_wait, | ||
| 1996 | .parent = &func_48m_ck, | 1993 | .parent = &func_48m_ck, |
| 1997 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1998 | .clkdm_name = "core_l4_clkdm", | 1994 | .clkdm_name = "core_l4_clkdm", |
| 1999 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1995 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2000 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | 1996 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| @@ -2003,8 +1999,8 @@ static struct clk uart1_fck = { | |||
| 2003 | 1999 | ||
| 2004 | static struct clk uart2_ick = { | 2000 | static struct clk uart2_ick = { |
| 2005 | .name = "uart2_ick", | 2001 | .name = "uart2_ick", |
| 2002 | .ops = &clkops_omap2_dflt_wait, | ||
| 2006 | .parent = &l4_ck, | 2003 | .parent = &l4_ck, |
| 2007 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2008 | .clkdm_name = "core_l4_clkdm", | 2004 | .clkdm_name = "core_l4_clkdm", |
| 2009 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2005 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2010 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | 2006 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| @@ -2013,8 +2009,8 @@ static struct clk uart2_ick = { | |||
| 2013 | 2009 | ||
| 2014 | static struct clk uart2_fck = { | 2010 | static struct clk uart2_fck = { |
| 2015 | .name = "uart2_fck", | 2011 | .name = "uart2_fck", |
| 2012 | .ops = &clkops_omap2_dflt_wait, | ||
| 2016 | .parent = &func_48m_ck, | 2013 | .parent = &func_48m_ck, |
| 2017 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2018 | .clkdm_name = "core_l4_clkdm", | 2014 | .clkdm_name = "core_l4_clkdm", |
| 2019 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2015 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2020 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | 2016 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| @@ -2023,8 +2019,8 @@ static struct clk uart2_fck = { | |||
| 2023 | 2019 | ||
| 2024 | static struct clk uart3_ick = { | 2020 | static struct clk uart3_ick = { |
| 2025 | .name = "uart3_ick", | 2021 | .name = "uart3_ick", |
| 2022 | .ops = &clkops_omap2_dflt_wait, | ||
| 2026 | .parent = &l4_ck, | 2023 | .parent = &l4_ck, |
| 2027 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2028 | .clkdm_name = "core_l4_clkdm", | 2024 | .clkdm_name = "core_l4_clkdm", |
| 2029 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2025 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2030 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | 2026 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| @@ -2033,8 +2029,8 @@ static struct clk uart3_ick = { | |||
| 2033 | 2029 | ||
| 2034 | static struct clk uart3_fck = { | 2030 | static struct clk uart3_fck = { |
| 2035 | .name = "uart3_fck", | 2031 | .name = "uart3_fck", |
| 2032 | .ops = &clkops_omap2_dflt_wait, | ||
| 2036 | .parent = &func_48m_ck, | 2033 | .parent = &func_48m_ck, |
| 2037 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2038 | .clkdm_name = "core_l4_clkdm", | 2034 | .clkdm_name = "core_l4_clkdm", |
| 2039 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2040 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | 2036 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| @@ -2043,8 +2039,8 @@ static struct clk uart3_fck = { | |||
| 2043 | 2039 | ||
| 2044 | static struct clk gpios_ick = { | 2040 | static struct clk gpios_ick = { |
| 2045 | .name = "gpios_ick", | 2041 | .name = "gpios_ick", |
| 2042 | .ops = &clkops_omap2_dflt_wait, | ||
| 2046 | .parent = &l4_ck, | 2043 | .parent = &l4_ck, |
| 2047 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2048 | .clkdm_name = "core_l4_clkdm", | 2044 | .clkdm_name = "core_l4_clkdm", |
| 2049 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2045 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2050 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | 2046 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| @@ -2053,8 +2049,8 @@ static struct clk gpios_ick = { | |||
| 2053 | 2049 | ||
| 2054 | static struct clk gpios_fck = { | 2050 | static struct clk gpios_fck = { |
| 2055 | .name = "gpios_fck", | 2051 | .name = "gpios_fck", |
| 2052 | .ops = &clkops_omap2_dflt_wait, | ||
| 2056 | .parent = &func_32k_ck, | 2053 | .parent = &func_32k_ck, |
| 2057 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2058 | .clkdm_name = "wkup_clkdm", | 2054 | .clkdm_name = "wkup_clkdm", |
| 2059 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2055 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2060 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | 2056 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| @@ -2063,8 +2059,8 @@ static struct clk gpios_fck = { | |||
| 2063 | 2059 | ||
| 2064 | static struct clk mpu_wdt_ick = { | 2060 | static struct clk mpu_wdt_ick = { |
| 2065 | .name = "mpu_wdt_ick", | 2061 | .name = "mpu_wdt_ick", |
| 2062 | .ops = &clkops_omap2_dflt_wait, | ||
| 2066 | .parent = &l4_ck, | 2063 | .parent = &l4_ck, |
| 2067 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2068 | .clkdm_name = "core_l4_clkdm", | 2064 | .clkdm_name = "core_l4_clkdm", |
| 2069 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2065 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2070 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | 2066 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| @@ -2073,8 +2069,8 @@ static struct clk mpu_wdt_ick = { | |||
| 2073 | 2069 | ||
| 2074 | static struct clk mpu_wdt_fck = { | 2070 | static struct clk mpu_wdt_fck = { |
| 2075 | .name = "mpu_wdt_fck", | 2071 | .name = "mpu_wdt_fck", |
| 2072 | .ops = &clkops_omap2_dflt_wait, | ||
| 2076 | .parent = &func_32k_ck, | 2073 | .parent = &func_32k_ck, |
| 2077 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2078 | .clkdm_name = "wkup_clkdm", | 2074 | .clkdm_name = "wkup_clkdm", |
| 2079 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2075 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2080 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | 2076 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| @@ -2083,9 +2079,9 @@ static struct clk mpu_wdt_fck = { | |||
| 2083 | 2079 | ||
| 2084 | static struct clk sync_32k_ick = { | 2080 | static struct clk sync_32k_ick = { |
| 2085 | .name = "sync_32k_ick", | 2081 | .name = "sync_32k_ick", |
| 2082 | .ops = &clkops_omap2_dflt_wait, | ||
| 2086 | .parent = &l4_ck, | 2083 | .parent = &l4_ck, |
| 2087 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2084 | .flags = ENABLE_ON_INIT, |
| 2088 | ENABLE_ON_INIT, | ||
| 2089 | .clkdm_name = "core_l4_clkdm", | 2085 | .clkdm_name = "core_l4_clkdm", |
| 2090 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2086 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2091 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | 2087 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, |
| @@ -2094,8 +2090,8 @@ static struct clk sync_32k_ick = { | |||
| 2094 | 2090 | ||
| 2095 | static struct clk wdt1_ick = { | 2091 | static struct clk wdt1_ick = { |
| 2096 | .name = "wdt1_ick", | 2092 | .name = "wdt1_ick", |
| 2093 | .ops = &clkops_omap2_dflt_wait, | ||
| 2097 | .parent = &l4_ck, | 2094 | .parent = &l4_ck, |
| 2098 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2099 | .clkdm_name = "core_l4_clkdm", | 2095 | .clkdm_name = "core_l4_clkdm", |
| 2100 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2096 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2101 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | 2097 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, |
| @@ -2104,9 +2100,9 @@ static struct clk wdt1_ick = { | |||
| 2104 | 2100 | ||
| 2105 | static struct clk omapctrl_ick = { | 2101 | static struct clk omapctrl_ick = { |
| 2106 | .name = "omapctrl_ick", | 2102 | .name = "omapctrl_ick", |
| 2103 | .ops = &clkops_omap2_dflt_wait, | ||
| 2107 | .parent = &l4_ck, | 2104 | .parent = &l4_ck, |
| 2108 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2105 | .flags = ENABLE_ON_INIT, |
| 2109 | ENABLE_ON_INIT, | ||
| 2110 | .clkdm_name = "core_l4_clkdm", | 2106 | .clkdm_name = "core_l4_clkdm", |
| 2111 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2107 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2112 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | 2108 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, |
| @@ -2115,8 +2111,8 @@ static struct clk omapctrl_ick = { | |||
| 2115 | 2111 | ||
| 2116 | static struct clk icr_ick = { | 2112 | static struct clk icr_ick = { |
| 2117 | .name = "icr_ick", | 2113 | .name = "icr_ick", |
| 2114 | .ops = &clkops_omap2_dflt_wait, | ||
| 2118 | .parent = &l4_ck, | 2115 | .parent = &l4_ck, |
| 2119 | .flags = CLOCK_IN_OMAP243X, | ||
| 2120 | .clkdm_name = "core_l4_clkdm", | 2116 | .clkdm_name = "core_l4_clkdm", |
| 2121 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2117 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2122 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | 2118 | .enable_bit = OMAP2430_EN_ICR_SHIFT, |
| @@ -2125,8 +2121,8 @@ static struct clk icr_ick = { | |||
| 2125 | 2121 | ||
| 2126 | static struct clk cam_ick = { | 2122 | static struct clk cam_ick = { |
| 2127 | .name = "cam_ick", | 2123 | .name = "cam_ick", |
| 2124 | .ops = &clkops_omap2_dflt, | ||
| 2128 | .parent = &l4_ck, | 2125 | .parent = &l4_ck, |
| 2129 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2130 | .clkdm_name = "core_l4_clkdm", | 2126 | .clkdm_name = "core_l4_clkdm", |
| 2131 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2127 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2132 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | 2128 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| @@ -2140,8 +2136,8 @@ static struct clk cam_ick = { | |||
| 2140 | */ | 2136 | */ |
| 2141 | static struct clk cam_fck = { | 2137 | static struct clk cam_fck = { |
| 2142 | .name = "cam_fck", | 2138 | .name = "cam_fck", |
| 2139 | .ops = &clkops_omap2_dflt, | ||
| 2143 | .parent = &func_96m_ck, | 2140 | .parent = &func_96m_ck, |
| 2144 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2145 | .clkdm_name = "core_l3_clkdm", | 2141 | .clkdm_name = "core_l3_clkdm", |
| 2146 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2142 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2147 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | 2143 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| @@ -2150,8 +2146,8 @@ static struct clk cam_fck = { | |||
| 2150 | 2146 | ||
| 2151 | static struct clk mailboxes_ick = { | 2147 | static struct clk mailboxes_ick = { |
| 2152 | .name = "mailboxes_ick", | 2148 | .name = "mailboxes_ick", |
| 2149 | .ops = &clkops_omap2_dflt_wait, | ||
| 2153 | .parent = &l4_ck, | 2150 | .parent = &l4_ck, |
| 2154 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2155 | .clkdm_name = "core_l4_clkdm", | 2151 | .clkdm_name = "core_l4_clkdm", |
| 2156 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2152 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2157 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | 2153 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| @@ -2160,8 +2156,8 @@ static struct clk mailboxes_ick = { | |||
| 2160 | 2156 | ||
| 2161 | static struct clk wdt4_ick = { | 2157 | static struct clk wdt4_ick = { |
| 2162 | .name = "wdt4_ick", | 2158 | .name = "wdt4_ick", |
| 2159 | .ops = &clkops_omap2_dflt_wait, | ||
| 2163 | .parent = &l4_ck, | 2160 | .parent = &l4_ck, |
| 2164 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2165 | .clkdm_name = "core_l4_clkdm", | 2161 | .clkdm_name = "core_l4_clkdm", |
| 2166 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2162 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2167 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | 2163 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| @@ -2170,8 +2166,8 @@ static struct clk wdt4_ick = { | |||
| 2170 | 2166 | ||
| 2171 | static struct clk wdt4_fck = { | 2167 | static struct clk wdt4_fck = { |
| 2172 | .name = "wdt4_fck", | 2168 | .name = "wdt4_fck", |
| 2169 | .ops = &clkops_omap2_dflt_wait, | ||
| 2173 | .parent = &func_32k_ck, | 2170 | .parent = &func_32k_ck, |
| 2174 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2175 | .clkdm_name = "core_l4_clkdm", | 2171 | .clkdm_name = "core_l4_clkdm", |
| 2176 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2172 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2177 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | 2173 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| @@ -2180,8 +2176,8 @@ static struct clk wdt4_fck = { | |||
| 2180 | 2176 | ||
| 2181 | static struct clk wdt3_ick = { | 2177 | static struct clk wdt3_ick = { |
| 2182 | .name = "wdt3_ick", | 2178 | .name = "wdt3_ick", |
| 2179 | .ops = &clkops_omap2_dflt_wait, | ||
| 2183 | .parent = &l4_ck, | 2180 | .parent = &l4_ck, |
| 2184 | .flags = CLOCK_IN_OMAP242X, | ||
| 2185 | .clkdm_name = "core_l4_clkdm", | 2181 | .clkdm_name = "core_l4_clkdm", |
| 2186 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2182 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2187 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | 2183 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| @@ -2190,8 +2186,8 @@ static struct clk wdt3_ick = { | |||
| 2190 | 2186 | ||
| 2191 | static struct clk wdt3_fck = { | 2187 | static struct clk wdt3_fck = { |
| 2192 | .name = "wdt3_fck", | 2188 | .name = "wdt3_fck", |
| 2189 | .ops = &clkops_omap2_dflt_wait, | ||
| 2193 | .parent = &func_32k_ck, | 2190 | .parent = &func_32k_ck, |
| 2194 | .flags = CLOCK_IN_OMAP242X, | ||
| 2195 | .clkdm_name = "core_l4_clkdm", | 2191 | .clkdm_name = "core_l4_clkdm", |
| 2196 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2192 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2197 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | 2193 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| @@ -2200,8 +2196,8 @@ static struct clk wdt3_fck = { | |||
| 2200 | 2196 | ||
| 2201 | static struct clk mspro_ick = { | 2197 | static struct clk mspro_ick = { |
| 2202 | .name = "mspro_ick", | 2198 | .name = "mspro_ick", |
| 2199 | .ops = &clkops_omap2_dflt_wait, | ||
| 2203 | .parent = &l4_ck, | 2200 | .parent = &l4_ck, |
| 2204 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2205 | .clkdm_name = "core_l4_clkdm", | 2201 | .clkdm_name = "core_l4_clkdm", |
| 2206 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2202 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2207 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | 2203 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| @@ -2210,8 +2206,8 @@ static struct clk mspro_ick = { | |||
| 2210 | 2206 | ||
| 2211 | static struct clk mspro_fck = { | 2207 | static struct clk mspro_fck = { |
| 2212 | .name = "mspro_fck", | 2208 | .name = "mspro_fck", |
| 2209 | .ops = &clkops_omap2_dflt_wait, | ||
| 2213 | .parent = &func_96m_ck, | 2210 | .parent = &func_96m_ck, |
| 2214 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2215 | .clkdm_name = "core_l4_clkdm", | 2211 | .clkdm_name = "core_l4_clkdm", |
| 2216 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2212 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2217 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | 2213 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| @@ -2220,8 +2216,8 @@ static struct clk mspro_fck = { | |||
| 2220 | 2216 | ||
| 2221 | static struct clk mmc_ick = { | 2217 | static struct clk mmc_ick = { |
| 2222 | .name = "mmc_ick", | 2218 | .name = "mmc_ick", |
| 2219 | .ops = &clkops_omap2_dflt_wait, | ||
| 2223 | .parent = &l4_ck, | 2220 | .parent = &l4_ck, |
| 2224 | .flags = CLOCK_IN_OMAP242X, | ||
| 2225 | .clkdm_name = "core_l4_clkdm", | 2221 | .clkdm_name = "core_l4_clkdm", |
| 2226 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2222 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2227 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | 2223 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| @@ -2230,8 +2226,8 @@ static struct clk mmc_ick = { | |||
| 2230 | 2226 | ||
| 2231 | static struct clk mmc_fck = { | 2227 | static struct clk mmc_fck = { |
| 2232 | .name = "mmc_fck", | 2228 | .name = "mmc_fck", |
| 2229 | .ops = &clkops_omap2_dflt_wait, | ||
| 2233 | .parent = &func_96m_ck, | 2230 | .parent = &func_96m_ck, |
| 2234 | .flags = CLOCK_IN_OMAP242X, | ||
| 2235 | .clkdm_name = "core_l4_clkdm", | 2231 | .clkdm_name = "core_l4_clkdm", |
| 2236 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2232 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2237 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | 2233 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| @@ -2240,8 +2236,8 @@ static struct clk mmc_fck = { | |||
| 2240 | 2236 | ||
| 2241 | static struct clk fac_ick = { | 2237 | static struct clk fac_ick = { |
| 2242 | .name = "fac_ick", | 2238 | .name = "fac_ick", |
| 2239 | .ops = &clkops_omap2_dflt_wait, | ||
| 2243 | .parent = &l4_ck, | 2240 | .parent = &l4_ck, |
| 2244 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2245 | .clkdm_name = "core_l4_clkdm", | 2241 | .clkdm_name = "core_l4_clkdm", |
| 2246 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2242 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2247 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | 2243 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| @@ -2250,8 +2246,8 @@ static struct clk fac_ick = { | |||
| 2250 | 2246 | ||
| 2251 | static struct clk fac_fck = { | 2247 | static struct clk fac_fck = { |
| 2252 | .name = "fac_fck", | 2248 | .name = "fac_fck", |
| 2249 | .ops = &clkops_omap2_dflt_wait, | ||
| 2253 | .parent = &func_12m_ck, | 2250 | .parent = &func_12m_ck, |
| 2254 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2255 | .clkdm_name = "core_l4_clkdm", | 2251 | .clkdm_name = "core_l4_clkdm", |
| 2256 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2252 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2257 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | 2253 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| @@ -2260,8 +2256,8 @@ static struct clk fac_fck = { | |||
| 2260 | 2256 | ||
| 2261 | static struct clk eac_ick = { | 2257 | static struct clk eac_ick = { |
| 2262 | .name = "eac_ick", | 2258 | .name = "eac_ick", |
| 2259 | .ops = &clkops_omap2_dflt_wait, | ||
| 2263 | .parent = &l4_ck, | 2260 | .parent = &l4_ck, |
| 2264 | .flags = CLOCK_IN_OMAP242X, | ||
| 2265 | .clkdm_name = "core_l4_clkdm", | 2261 | .clkdm_name = "core_l4_clkdm", |
| 2266 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2262 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2267 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | 2263 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| @@ -2270,8 +2266,8 @@ static struct clk eac_ick = { | |||
| 2270 | 2266 | ||
| 2271 | static struct clk eac_fck = { | 2267 | static struct clk eac_fck = { |
| 2272 | .name = "eac_fck", | 2268 | .name = "eac_fck", |
| 2269 | .ops = &clkops_omap2_dflt_wait, | ||
| 2273 | .parent = &func_96m_ck, | 2270 | .parent = &func_96m_ck, |
| 2274 | .flags = CLOCK_IN_OMAP242X, | ||
| 2275 | .clkdm_name = "core_l4_clkdm", | 2271 | .clkdm_name = "core_l4_clkdm", |
| 2276 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2272 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2277 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | 2273 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| @@ -2280,8 +2276,8 @@ static struct clk eac_fck = { | |||
| 2280 | 2276 | ||
| 2281 | static struct clk hdq_ick = { | 2277 | static struct clk hdq_ick = { |
| 2282 | .name = "hdq_ick", | 2278 | .name = "hdq_ick", |
| 2279 | .ops = &clkops_omap2_dflt_wait, | ||
| 2283 | .parent = &l4_ck, | 2280 | .parent = &l4_ck, |
| 2284 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2285 | .clkdm_name = "core_l4_clkdm", | 2281 | .clkdm_name = "core_l4_clkdm", |
| 2286 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2282 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2287 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | 2283 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| @@ -2290,8 +2286,8 @@ static struct clk hdq_ick = { | |||
| 2290 | 2286 | ||
| 2291 | static struct clk hdq_fck = { | 2287 | static struct clk hdq_fck = { |
| 2292 | .name = "hdq_fck", | 2288 | .name = "hdq_fck", |
| 2289 | .ops = &clkops_omap2_dflt_wait, | ||
| 2293 | .parent = &func_12m_ck, | 2290 | .parent = &func_12m_ck, |
| 2294 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2295 | .clkdm_name = "core_l4_clkdm", | 2291 | .clkdm_name = "core_l4_clkdm", |
| 2296 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2292 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2297 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | 2293 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| @@ -2300,9 +2296,9 @@ static struct clk hdq_fck = { | |||
| 2300 | 2296 | ||
| 2301 | static struct clk i2c2_ick = { | 2297 | static struct clk i2c2_ick = { |
| 2302 | .name = "i2c_ick", | 2298 | .name = "i2c_ick", |
| 2299 | .ops = &clkops_omap2_dflt_wait, | ||
| 2303 | .id = 2, | 2300 | .id = 2, |
| 2304 | .parent = &l4_ck, | 2301 | .parent = &l4_ck, |
| 2305 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2306 | .clkdm_name = "core_l4_clkdm", | 2302 | .clkdm_name = "core_l4_clkdm", |
| 2307 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2303 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2308 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | 2304 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| @@ -2311,9 +2307,9 @@ static struct clk i2c2_ick = { | |||
| 2311 | 2307 | ||
| 2312 | static struct clk i2c2_fck = { | 2308 | static struct clk i2c2_fck = { |
| 2313 | .name = "i2c_fck", | 2309 | .name = "i2c_fck", |
| 2310 | .ops = &clkops_omap2_dflt_wait, | ||
| 2314 | .id = 2, | 2311 | .id = 2, |
| 2315 | .parent = &func_12m_ck, | 2312 | .parent = &func_12m_ck, |
| 2316 | .flags = CLOCK_IN_OMAP242X, | ||
| 2317 | .clkdm_name = "core_l4_clkdm", | 2313 | .clkdm_name = "core_l4_clkdm", |
| 2318 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2314 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2319 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | 2315 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| @@ -2322,9 +2318,9 @@ static struct clk i2c2_fck = { | |||
| 2322 | 2318 | ||
| 2323 | static struct clk i2chs2_fck = { | 2319 | static struct clk i2chs2_fck = { |
| 2324 | .name = "i2c_fck", | 2320 | .name = "i2c_fck", |
| 2321 | .ops = &clkops_omap2_dflt_wait, | ||
| 2325 | .id = 2, | 2322 | .id = 2, |
| 2326 | .parent = &func_96m_ck, | 2323 | .parent = &func_96m_ck, |
| 2327 | .flags = CLOCK_IN_OMAP243X, | ||
| 2328 | .clkdm_name = "core_l4_clkdm", | 2324 | .clkdm_name = "core_l4_clkdm", |
| 2329 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2325 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2330 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | 2326 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, |
| @@ -2333,9 +2329,9 @@ static struct clk i2chs2_fck = { | |||
| 2333 | 2329 | ||
| 2334 | static struct clk i2c1_ick = { | 2330 | static struct clk i2c1_ick = { |
| 2335 | .name = "i2c_ick", | 2331 | .name = "i2c_ick", |
| 2332 | .ops = &clkops_omap2_dflt_wait, | ||
| 2336 | .id = 1, | 2333 | .id = 1, |
| 2337 | .parent = &l4_ck, | 2334 | .parent = &l4_ck, |
| 2338 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2339 | .clkdm_name = "core_l4_clkdm", | 2335 | .clkdm_name = "core_l4_clkdm", |
| 2340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2336 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2341 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | 2337 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| @@ -2344,9 +2340,9 @@ static struct clk i2c1_ick = { | |||
| 2344 | 2340 | ||
| 2345 | static struct clk i2c1_fck = { | 2341 | static struct clk i2c1_fck = { |
| 2346 | .name = "i2c_fck", | 2342 | .name = "i2c_fck", |
| 2343 | .ops = &clkops_omap2_dflt_wait, | ||
| 2347 | .id = 1, | 2344 | .id = 1, |
| 2348 | .parent = &func_12m_ck, | 2345 | .parent = &func_12m_ck, |
| 2349 | .flags = CLOCK_IN_OMAP242X, | ||
| 2350 | .clkdm_name = "core_l4_clkdm", | 2346 | .clkdm_name = "core_l4_clkdm", |
| 2351 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2347 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2352 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | 2348 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| @@ -2355,9 +2351,9 @@ static struct clk i2c1_fck = { | |||
| 2355 | 2351 | ||
| 2356 | static struct clk i2chs1_fck = { | 2352 | static struct clk i2chs1_fck = { |
| 2357 | .name = "i2c_fck", | 2353 | .name = "i2c_fck", |
| 2354 | .ops = &clkops_omap2_dflt_wait, | ||
| 2358 | .id = 1, | 2355 | .id = 1, |
| 2359 | .parent = &func_96m_ck, | 2356 | .parent = &func_96m_ck, |
| 2360 | .flags = CLOCK_IN_OMAP243X, | ||
| 2361 | .clkdm_name = "core_l4_clkdm", | 2357 | .clkdm_name = "core_l4_clkdm", |
| 2362 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2358 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2363 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | 2359 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, |
| @@ -2366,33 +2362,33 @@ static struct clk i2chs1_fck = { | |||
| 2366 | 2362 | ||
| 2367 | static struct clk gpmc_fck = { | 2363 | static struct clk gpmc_fck = { |
| 2368 | .name = "gpmc_fck", | 2364 | .name = "gpmc_fck", |
| 2365 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2369 | .parent = &core_l3_ck, | 2366 | .parent = &core_l3_ck, |
| 2370 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2367 | .flags = ENABLE_ON_INIT, |
| 2371 | ENABLE_ON_INIT, | ||
| 2372 | .clkdm_name = "core_l3_clkdm", | 2368 | .clkdm_name = "core_l3_clkdm", |
| 2373 | .recalc = &followparent_recalc, | 2369 | .recalc = &followparent_recalc, |
| 2374 | }; | 2370 | }; |
| 2375 | 2371 | ||
| 2376 | static struct clk sdma_fck = { | 2372 | static struct clk sdma_fck = { |
| 2377 | .name = "sdma_fck", | 2373 | .name = "sdma_fck", |
| 2374 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2378 | .parent = &core_l3_ck, | 2375 | .parent = &core_l3_ck, |
| 2379 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2380 | .clkdm_name = "core_l3_clkdm", | 2376 | .clkdm_name = "core_l3_clkdm", |
| 2381 | .recalc = &followparent_recalc, | 2377 | .recalc = &followparent_recalc, |
| 2382 | }; | 2378 | }; |
| 2383 | 2379 | ||
| 2384 | static struct clk sdma_ick = { | 2380 | static struct clk sdma_ick = { |
| 2385 | .name = "sdma_ick", | 2381 | .name = "sdma_ick", |
| 2382 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2386 | .parent = &l4_ck, | 2383 | .parent = &l4_ck, |
| 2387 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2388 | .clkdm_name = "core_l3_clkdm", | 2384 | .clkdm_name = "core_l3_clkdm", |
| 2389 | .recalc = &followparent_recalc, | 2385 | .recalc = &followparent_recalc, |
| 2390 | }; | 2386 | }; |
| 2391 | 2387 | ||
| 2392 | static struct clk vlynq_ick = { | 2388 | static struct clk vlynq_ick = { |
| 2393 | .name = "vlynq_ick", | 2389 | .name = "vlynq_ick", |
| 2390 | .ops = &clkops_omap2_dflt_wait, | ||
| 2394 | .parent = &core_l3_ck, | 2391 | .parent = &core_l3_ck, |
| 2395 | .flags = CLOCK_IN_OMAP242X, | ||
| 2396 | .clkdm_name = "core_l3_clkdm", | 2392 | .clkdm_name = "core_l3_clkdm", |
| 2397 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2398 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | 2394 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| @@ -2426,8 +2422,9 @@ static const struct clksel vlynq_fck_clksel[] = { | |||
| 2426 | 2422 | ||
| 2427 | static struct clk vlynq_fck = { | 2423 | static struct clk vlynq_fck = { |
| 2428 | .name = "vlynq_fck", | 2424 | .name = "vlynq_fck", |
| 2425 | .ops = &clkops_omap2_dflt_wait, | ||
| 2429 | .parent = &func_96m_ck, | 2426 | .parent = &func_96m_ck, |
| 2430 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP, | 2427 | .flags = DELAYED_APP, |
| 2431 | .clkdm_name = "core_l3_clkdm", | 2428 | .clkdm_name = "core_l3_clkdm", |
| 2432 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2429 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2433 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | 2430 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| @@ -2442,8 +2439,9 @@ static struct clk vlynq_fck = { | |||
| 2442 | 2439 | ||
| 2443 | static struct clk sdrc_ick = { | 2440 | static struct clk sdrc_ick = { |
| 2444 | .name = "sdrc_ick", | 2441 | .name = "sdrc_ick", |
| 2442 | .ops = &clkops_omap2_dflt_wait, | ||
| 2445 | .parent = &l4_ck, | 2443 | .parent = &l4_ck, |
| 2446 | .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | 2444 | .flags = ENABLE_ON_INIT, |
| 2447 | .clkdm_name = "core_l4_clkdm", | 2445 | .clkdm_name = "core_l4_clkdm", |
| 2448 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 2446 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 2449 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | 2447 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, |
| @@ -2452,8 +2450,8 @@ static struct clk sdrc_ick = { | |||
| 2452 | 2450 | ||
| 2453 | static struct clk des_ick = { | 2451 | static struct clk des_ick = { |
| 2454 | .name = "des_ick", | 2452 | .name = "des_ick", |
| 2453 | .ops = &clkops_omap2_dflt_wait, | ||
| 2455 | .parent = &l4_ck, | 2454 | .parent = &l4_ck, |
| 2456 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2457 | .clkdm_name = "core_l4_clkdm", | 2455 | .clkdm_name = "core_l4_clkdm", |
| 2458 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2456 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2459 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | 2457 | .enable_bit = OMAP24XX_EN_DES_SHIFT, |
| @@ -2462,8 +2460,8 @@ static struct clk des_ick = { | |||
| 2462 | 2460 | ||
| 2463 | static struct clk sha_ick = { | 2461 | static struct clk sha_ick = { |
| 2464 | .name = "sha_ick", | 2462 | .name = "sha_ick", |
| 2463 | .ops = &clkops_omap2_dflt_wait, | ||
| 2465 | .parent = &l4_ck, | 2464 | .parent = &l4_ck, |
| 2466 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2467 | .clkdm_name = "core_l4_clkdm", | 2465 | .clkdm_name = "core_l4_clkdm", |
| 2468 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2466 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2469 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | 2467 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, |
| @@ -2472,8 +2470,8 @@ static struct clk sha_ick = { | |||
| 2472 | 2470 | ||
| 2473 | static struct clk rng_ick = { | 2471 | static struct clk rng_ick = { |
| 2474 | .name = "rng_ick", | 2472 | .name = "rng_ick", |
| 2473 | .ops = &clkops_omap2_dflt_wait, | ||
| 2475 | .parent = &l4_ck, | 2474 | .parent = &l4_ck, |
| 2476 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2477 | .clkdm_name = "core_l4_clkdm", | 2475 | .clkdm_name = "core_l4_clkdm", |
| 2478 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2476 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2479 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | 2477 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, |
| @@ -2482,8 +2480,8 @@ static struct clk rng_ick = { | |||
| 2482 | 2480 | ||
| 2483 | static struct clk aes_ick = { | 2481 | static struct clk aes_ick = { |
| 2484 | .name = "aes_ick", | 2482 | .name = "aes_ick", |
| 2483 | .ops = &clkops_omap2_dflt_wait, | ||
| 2485 | .parent = &l4_ck, | 2484 | .parent = &l4_ck, |
| 2486 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2487 | .clkdm_name = "core_l4_clkdm", | 2485 | .clkdm_name = "core_l4_clkdm", |
| 2488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2486 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2489 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | 2487 | .enable_bit = OMAP24XX_EN_AES_SHIFT, |
| @@ -2492,8 +2490,8 @@ static struct clk aes_ick = { | |||
| 2492 | 2490 | ||
| 2493 | static struct clk pka_ick = { | 2491 | static struct clk pka_ick = { |
| 2494 | .name = "pka_ick", | 2492 | .name = "pka_ick", |
| 2493 | .ops = &clkops_omap2_dflt_wait, | ||
| 2495 | .parent = &l4_ck, | 2494 | .parent = &l4_ck, |
| 2496 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2497 | .clkdm_name = "core_l4_clkdm", | 2495 | .clkdm_name = "core_l4_clkdm", |
| 2498 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2499 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | 2497 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, |
| @@ -2502,8 +2500,8 @@ static struct clk pka_ick = { | |||
| 2502 | 2500 | ||
| 2503 | static struct clk usb_fck = { | 2501 | static struct clk usb_fck = { |
| 2504 | .name = "usb_fck", | 2502 | .name = "usb_fck", |
| 2503 | .ops = &clkops_omap2_dflt_wait, | ||
| 2505 | .parent = &func_48m_ck, | 2504 | .parent = &func_48m_ck, |
| 2506 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2507 | .clkdm_name = "core_l3_clkdm", | 2505 | .clkdm_name = "core_l3_clkdm", |
| 2508 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2506 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2509 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 2507 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| @@ -2512,8 +2510,8 @@ static struct clk usb_fck = { | |||
| 2512 | 2510 | ||
| 2513 | static struct clk usbhs_ick = { | 2511 | static struct clk usbhs_ick = { |
| 2514 | .name = "usbhs_ick", | 2512 | .name = "usbhs_ick", |
| 2513 | .ops = &clkops_omap2_dflt_wait, | ||
| 2515 | .parent = &core_l3_ck, | 2514 | .parent = &core_l3_ck, |
| 2516 | .flags = CLOCK_IN_OMAP243X, | ||
| 2517 | .clkdm_name = "core_l3_clkdm", | 2515 | .clkdm_name = "core_l3_clkdm", |
| 2518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2516 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2519 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | 2517 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, |
| @@ -2522,8 +2520,8 @@ static struct clk usbhs_ick = { | |||
| 2522 | 2520 | ||
| 2523 | static struct clk mmchs1_ick = { | 2521 | static struct clk mmchs1_ick = { |
| 2524 | .name = "mmchs_ick", | 2522 | .name = "mmchs_ick", |
| 2523 | .ops = &clkops_omap2_dflt_wait, | ||
| 2525 | .parent = &l4_ck, | 2524 | .parent = &l4_ck, |
| 2526 | .flags = CLOCK_IN_OMAP243X, | ||
| 2527 | .clkdm_name = "core_l4_clkdm", | 2525 | .clkdm_name = "core_l4_clkdm", |
| 2528 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2526 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2529 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | 2527 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| @@ -2532,8 +2530,8 @@ static struct clk mmchs1_ick = { | |||
| 2532 | 2530 | ||
| 2533 | static struct clk mmchs1_fck = { | 2531 | static struct clk mmchs1_fck = { |
| 2534 | .name = "mmchs_fck", | 2532 | .name = "mmchs_fck", |
| 2533 | .ops = &clkops_omap2_dflt_wait, | ||
| 2535 | .parent = &func_96m_ck, | 2534 | .parent = &func_96m_ck, |
| 2536 | .flags = CLOCK_IN_OMAP243X, | ||
| 2537 | .clkdm_name = "core_l3_clkdm", | 2535 | .clkdm_name = "core_l3_clkdm", |
| 2538 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2536 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2539 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | 2537 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| @@ -2542,9 +2540,9 @@ static struct clk mmchs1_fck = { | |||
| 2542 | 2540 | ||
| 2543 | static struct clk mmchs2_ick = { | 2541 | static struct clk mmchs2_ick = { |
| 2544 | .name = "mmchs_ick", | 2542 | .name = "mmchs_ick", |
| 2543 | .ops = &clkops_omap2_dflt_wait, | ||
| 2545 | .id = 1, | 2544 | .id = 1, |
| 2546 | .parent = &l4_ck, | 2545 | .parent = &l4_ck, |
| 2547 | .flags = CLOCK_IN_OMAP243X, | ||
| 2548 | .clkdm_name = "core_l4_clkdm", | 2546 | .clkdm_name = "core_l4_clkdm", |
| 2549 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2547 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2550 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 2548 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| @@ -2553,9 +2551,9 @@ static struct clk mmchs2_ick = { | |||
| 2553 | 2551 | ||
| 2554 | static struct clk mmchs2_fck = { | 2552 | static struct clk mmchs2_fck = { |
| 2555 | .name = "mmchs_fck", | 2553 | .name = "mmchs_fck", |
| 2554 | .ops = &clkops_omap2_dflt_wait, | ||
| 2556 | .id = 1, | 2555 | .id = 1, |
| 2557 | .parent = &func_96m_ck, | 2556 | .parent = &func_96m_ck, |
| 2558 | .flags = CLOCK_IN_OMAP243X, | ||
| 2559 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2557 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2560 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 2558 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| 2561 | .recalc = &followparent_recalc, | 2559 | .recalc = &followparent_recalc, |
| @@ -2563,8 +2561,8 @@ static struct clk mmchs2_fck = { | |||
| 2563 | 2561 | ||
| 2564 | static struct clk gpio5_ick = { | 2562 | static struct clk gpio5_ick = { |
| 2565 | .name = "gpio5_ick", | 2563 | .name = "gpio5_ick", |
| 2564 | .ops = &clkops_omap2_dflt_wait, | ||
| 2566 | .parent = &l4_ck, | 2565 | .parent = &l4_ck, |
| 2567 | .flags = CLOCK_IN_OMAP243X, | ||
| 2568 | .clkdm_name = "core_l4_clkdm", | 2566 | .clkdm_name = "core_l4_clkdm", |
| 2569 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2567 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2570 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | 2568 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| @@ -2573,8 +2571,8 @@ static struct clk gpio5_ick = { | |||
| 2573 | 2571 | ||
| 2574 | static struct clk gpio5_fck = { | 2572 | static struct clk gpio5_fck = { |
| 2575 | .name = "gpio5_fck", | 2573 | .name = "gpio5_fck", |
| 2574 | .ops = &clkops_omap2_dflt_wait, | ||
| 2576 | .parent = &func_32k_ck, | 2575 | .parent = &func_32k_ck, |
| 2577 | .flags = CLOCK_IN_OMAP243X, | ||
| 2578 | .clkdm_name = "core_l4_clkdm", | 2576 | .clkdm_name = "core_l4_clkdm", |
| 2579 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2577 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2580 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | 2578 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| @@ -2583,8 +2581,8 @@ static struct clk gpio5_fck = { | |||
| 2583 | 2581 | ||
| 2584 | static struct clk mdm_intc_ick = { | 2582 | static struct clk mdm_intc_ick = { |
| 2585 | .name = "mdm_intc_ick", | 2583 | .name = "mdm_intc_ick", |
| 2584 | .ops = &clkops_omap2_dflt_wait, | ||
| 2586 | .parent = &l4_ck, | 2585 | .parent = &l4_ck, |
| 2587 | .flags = CLOCK_IN_OMAP243X, | ||
| 2588 | .clkdm_name = "core_l4_clkdm", | 2586 | .clkdm_name = "core_l4_clkdm", |
| 2589 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2587 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2590 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | 2588 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, |
| @@ -2593,8 +2591,8 @@ static struct clk mdm_intc_ick = { | |||
| 2593 | 2591 | ||
| 2594 | static struct clk mmchsdb1_fck = { | 2592 | static struct clk mmchsdb1_fck = { |
| 2595 | .name = "mmchsdb_fck", | 2593 | .name = "mmchsdb_fck", |
| 2594 | .ops = &clkops_omap2_dflt_wait, | ||
| 2596 | .parent = &func_32k_ck, | 2595 | .parent = &func_32k_ck, |
| 2597 | .flags = CLOCK_IN_OMAP243X, | ||
| 2598 | .clkdm_name = "core_l4_clkdm", | 2596 | .clkdm_name = "core_l4_clkdm", |
| 2599 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2597 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2600 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | 2598 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, |
| @@ -2603,9 +2601,9 @@ static struct clk mmchsdb1_fck = { | |||
| 2603 | 2601 | ||
| 2604 | static struct clk mmchsdb2_fck = { | 2602 | static struct clk mmchsdb2_fck = { |
| 2605 | .name = "mmchsdb_fck", | 2603 | .name = "mmchsdb_fck", |
| 2604 | .ops = &clkops_omap2_dflt_wait, | ||
| 2606 | .id = 1, | 2605 | .id = 1, |
| 2607 | .parent = &func_32k_ck, | 2606 | .parent = &func_32k_ck, |
| 2608 | .flags = CLOCK_IN_OMAP243X, | ||
| 2609 | .clkdm_name = "core_l4_clkdm", | 2607 | .clkdm_name = "core_l4_clkdm", |
| 2610 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2608 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2611 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | 2609 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, |
| @@ -2628,166 +2626,13 @@ static struct clk mmchsdb2_fck = { | |||
| 2628 | */ | 2626 | */ |
| 2629 | static struct clk virt_prcm_set = { | 2627 | static struct clk virt_prcm_set = { |
| 2630 | .name = "virt_prcm_set", | 2628 | .name = "virt_prcm_set", |
| 2631 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2629 | .ops = &clkops_null, |
| 2632 | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, | 2630 | .flags = DELAYED_APP, |
| 2633 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | 2631 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
| 2634 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ | 2632 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
| 2635 | .set_rate = &omap2_select_table_rate, | 2633 | .set_rate = &omap2_select_table_rate, |
| 2636 | .round_rate = &omap2_round_to_table_rate, | 2634 | .round_rate = &omap2_round_to_table_rate, |
| 2637 | }; | 2635 | }; |
| 2638 | 2636 | ||
| 2639 | static struct clk *onchip_24xx_clks[] __initdata = { | ||
| 2640 | /* external root sources */ | ||
| 2641 | &func_32k_ck, | ||
| 2642 | &osc_ck, | ||
| 2643 | &sys_ck, | ||
| 2644 | &alt_ck, | ||
| 2645 | /* internal analog sources */ | ||
| 2646 | &dpll_ck, | ||
| 2647 | &apll96_ck, | ||
| 2648 | &apll54_ck, | ||
| 2649 | /* internal prcm root sources */ | ||
| 2650 | &func_54m_ck, | ||
| 2651 | &core_ck, | ||
| 2652 | &func_96m_ck, | ||
| 2653 | &func_48m_ck, | ||
| 2654 | &func_12m_ck, | ||
| 2655 | &wdt1_osc_ck, | ||
| 2656 | &sys_clkout_src, | ||
| 2657 | &sys_clkout, | ||
| 2658 | &sys_clkout2_src, | ||
| 2659 | &sys_clkout2, | ||
| 2660 | &emul_ck, | ||
| 2661 | /* mpu domain clocks */ | ||
| 2662 | &mpu_ck, | ||
| 2663 | /* dsp domain clocks */ | ||
| 2664 | &dsp_fck, | ||
| 2665 | &dsp_irate_ick, | ||
| 2666 | &dsp_ick, /* 242x */ | ||
| 2667 | &iva2_1_ick, /* 243x */ | ||
| 2668 | &iva1_ifck, /* 242x */ | ||
| 2669 | &iva1_mpu_int_ifck, /* 242x */ | ||
| 2670 | /* GFX domain clocks */ | ||
| 2671 | &gfx_3d_fck, | ||
| 2672 | &gfx_2d_fck, | ||
| 2673 | &gfx_ick, | ||
| 2674 | /* Modem domain clocks */ | ||
| 2675 | &mdm_ick, | ||
| 2676 | &mdm_osc_ck, | ||
| 2677 | /* DSS domain clocks */ | ||
| 2678 | &dss_ick, | ||
| 2679 | &dss1_fck, | ||
| 2680 | &dss2_fck, | ||
| 2681 | &dss_54m_fck, | ||
| 2682 | /* L3 domain clocks */ | ||
| 2683 | &core_l3_ck, | ||
| 2684 | &ssi_ssr_sst_fck, | ||
| 2685 | &usb_l4_ick, | ||
| 2686 | /* L4 domain clocks */ | ||
| 2687 | &l4_ck, /* used as both core_l4 and wu_l4 */ | ||
| 2688 | /* virtual meta-group clock */ | ||
| 2689 | &virt_prcm_set, | ||
| 2690 | /* general l4 interface ck, multi-parent functional clk */ | ||
| 2691 | &gpt1_ick, | ||
| 2692 | &gpt1_fck, | ||
| 2693 | &gpt2_ick, | ||
| 2694 | &gpt2_fck, | ||
| 2695 | &gpt3_ick, | ||
| 2696 | &gpt3_fck, | ||
| 2697 | &gpt4_ick, | ||
| 2698 | &gpt4_fck, | ||
| 2699 | &gpt5_ick, | ||
| 2700 | &gpt5_fck, | ||
| 2701 | &gpt6_ick, | ||
| 2702 | &gpt6_fck, | ||
| 2703 | &gpt7_ick, | ||
| 2704 | &gpt7_fck, | ||
| 2705 | &gpt8_ick, | ||
| 2706 | &gpt8_fck, | ||
| 2707 | &gpt9_ick, | ||
| 2708 | &gpt9_fck, | ||
| 2709 | &gpt10_ick, | ||
| 2710 | &gpt10_fck, | ||
| 2711 | &gpt11_ick, | ||
| 2712 | &gpt11_fck, | ||
| 2713 | &gpt12_ick, | ||
| 2714 | &gpt12_fck, | ||
| 2715 | &mcbsp1_ick, | ||
| 2716 | &mcbsp1_fck, | ||
| 2717 | &mcbsp2_ick, | ||
| 2718 | &mcbsp2_fck, | ||
| 2719 | &mcbsp3_ick, | ||
| 2720 | &mcbsp3_fck, | ||
| 2721 | &mcbsp4_ick, | ||
| 2722 | &mcbsp4_fck, | ||
| 2723 | &mcbsp5_ick, | ||
| 2724 | &mcbsp5_fck, | ||
| 2725 | &mcspi1_ick, | ||
| 2726 | &mcspi1_fck, | ||
| 2727 | &mcspi2_ick, | ||
| 2728 | &mcspi2_fck, | ||
| 2729 | &mcspi3_ick, | ||
| 2730 | &mcspi3_fck, | ||
| 2731 | &uart1_ick, | ||
| 2732 | &uart1_fck, | ||
| 2733 | &uart2_ick, | ||
| 2734 | &uart2_fck, | ||
| 2735 | &uart3_ick, | ||
| 2736 | &uart3_fck, | ||
| 2737 | &gpios_ick, | ||
| 2738 | &gpios_fck, | ||
| 2739 | &mpu_wdt_ick, | ||
| 2740 | &mpu_wdt_fck, | ||
| 2741 | &sync_32k_ick, | ||
| 2742 | &wdt1_ick, | ||
| 2743 | &omapctrl_ick, | ||
| 2744 | &icr_ick, | ||
| 2745 | &cam_fck, | ||
| 2746 | &cam_ick, | ||
| 2747 | &mailboxes_ick, | ||
| 2748 | &wdt4_ick, | ||
| 2749 | &wdt4_fck, | ||
| 2750 | &wdt3_ick, | ||
| 2751 | &wdt3_fck, | ||
| 2752 | &mspro_ick, | ||
| 2753 | &mspro_fck, | ||
| 2754 | &mmc_ick, | ||
| 2755 | &mmc_fck, | ||
| 2756 | &fac_ick, | ||
| 2757 | &fac_fck, | ||
| 2758 | &eac_ick, | ||
| 2759 | &eac_fck, | ||
| 2760 | &hdq_ick, | ||
| 2761 | &hdq_fck, | ||
| 2762 | &i2c1_ick, | ||
| 2763 | &i2c1_fck, | ||
| 2764 | &i2chs1_fck, | ||
| 2765 | &i2c2_ick, | ||
| 2766 | &i2c2_fck, | ||
| 2767 | &i2chs2_fck, | ||
| 2768 | &gpmc_fck, | ||
| 2769 | &sdma_fck, | ||
| 2770 | &sdma_ick, | ||
| 2771 | &vlynq_ick, | ||
| 2772 | &vlynq_fck, | ||
| 2773 | &sdrc_ick, | ||
| 2774 | &des_ick, | ||
| 2775 | &sha_ick, | ||
| 2776 | &rng_ick, | ||
| 2777 | &aes_ick, | ||
| 2778 | &pka_ick, | ||
| 2779 | &usb_fck, | ||
| 2780 | &usbhs_ick, | ||
| 2781 | &mmchs1_ick, | ||
| 2782 | &mmchs1_fck, | ||
| 2783 | &mmchs2_ick, | ||
| 2784 | &mmchs2_fck, | ||
| 2785 | &gpio5_ick, | ||
| 2786 | &gpio5_fck, | ||
| 2787 | &mdm_intc_ick, | ||
| 2788 | &mmchsdb1_fck, | ||
| 2789 | &mmchsdb2_fck, | ||
| 2790 | }; | ||
| 2791 | |||
| 2792 | #endif | 2637 | #endif |
| 2793 | 2638 | ||
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 31bb7010bd48..0a14dca31e30 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
| @@ -30,15 +30,251 @@ | |||
| 30 | #include <mach/clock.h> | 30 | #include <mach/clock.h> |
| 31 | #include <mach/sram.h> | 31 | #include <mach/sram.h> |
| 32 | #include <asm/div64.h> | 32 | #include <asm/div64.h> |
| 33 | #include <asm/clkdev.h> | ||
| 33 | 34 | ||
| 34 | #include "memory.h" | 35 | #include <mach/sdrc.h> |
| 35 | #include "clock.h" | 36 | #include "clock.h" |
| 36 | #include "clock34xx.h" | ||
| 37 | #include "prm.h" | 37 | #include "prm.h" |
| 38 | #include "prm-regbits-34xx.h" | 38 | #include "prm-regbits-34xx.h" |
| 39 | #include "cm.h" | 39 | #include "cm.h" |
| 40 | #include "cm-regbits-34xx.h" | 40 | #include "cm-regbits-34xx.h" |
| 41 | 41 | ||
| 42 | static const struct clkops clkops_noncore_dpll_ops; | ||
| 43 | |||
| 44 | #include "clock34xx.h" | ||
| 45 | |||
| 46 | struct omap_clk { | ||
| 47 | u32 cpu; | ||
| 48 | struct clk_lookup lk; | ||
| 49 | }; | ||
| 50 | |||
| 51 | #define CLK(dev, con, ck, cp) \ | ||
| 52 | { \ | ||
| 53 | .cpu = cp, \ | ||
| 54 | .lk = { \ | ||
| 55 | .dev_id = dev, \ | ||
| 56 | .con_id = con, \ | ||
| 57 | .clk = ck, \ | ||
| 58 | }, \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define CK_343X (1 << 0) | ||
| 62 | #define CK_3430ES1 (1 << 1) | ||
| 63 | #define CK_3430ES2 (1 << 2) | ||
| 64 | |||
| 65 | static struct omap_clk omap34xx_clks[] = { | ||
| 66 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | ||
| 67 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | ||
| 68 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | ||
| 69 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | ||
| 70 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | ||
| 71 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | ||
| 72 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | ||
| 73 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | ||
| 74 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | ||
| 75 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | ||
| 76 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | ||
| 77 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | ||
| 78 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | ||
| 79 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | ||
| 80 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | ||
| 81 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | ||
| 82 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | ||
| 83 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | ||
| 84 | CLK(NULL, "core_ck", &core_ck, CK_343X), | ||
| 85 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | ||
| 86 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | ||
| 87 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | ||
| 88 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | ||
| 89 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | ||
| 90 | CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), | ||
| 91 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), | ||
| 92 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | ||
| 93 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | ||
| 94 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | ||
| 95 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | ||
| 96 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), | ||
| 97 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | ||
| 98 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | ||
| 99 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | ||
| 100 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | ||
| 101 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | ||
| 102 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | ||
| 103 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | ||
| 104 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | ||
| 105 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | ||
| 106 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | ||
| 107 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | ||
| 108 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | ||
| 109 | CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), | ||
| 110 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), | ||
| 111 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | ||
| 112 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), | ||
| 113 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | ||
| 114 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | ||
| 115 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | ||
| 116 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | ||
| 117 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | ||
| 118 | CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), | ||
| 119 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | ||
| 120 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | ||
| 121 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | ||
| 122 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | ||
| 123 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | ||
| 124 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | ||
| 125 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | ||
| 126 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | ||
| 127 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | ||
| 128 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | ||
| 129 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | ||
| 130 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | ||
| 131 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | ||
| 132 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), | ||
| 133 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | ||
| 134 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | ||
| 135 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | ||
| 136 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | ||
| 137 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | ||
| 138 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), | ||
| 139 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | ||
| 140 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | ||
| 141 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), | ||
| 142 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), | ||
| 143 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | ||
| 144 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | ||
| 145 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), | ||
| 146 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | ||
| 147 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), | ||
| 148 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), | ||
| 149 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | ||
| 150 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | ||
| 151 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | ||
| 152 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), | ||
| 153 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | ||
| 154 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | ||
| 155 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | ||
| 156 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), | ||
| 157 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), | ||
| 158 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), | ||
| 159 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | ||
| 160 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X), | ||
| 161 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | ||
| 162 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | ||
| 163 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | ||
| 164 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | ||
| 165 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | ||
| 166 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | ||
| 167 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), | ||
| 168 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | ||
| 169 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | ||
| 170 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | ||
| 171 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | ||
| 172 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), | ||
| 173 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | ||
| 174 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | ||
| 175 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), | ||
| 176 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), | ||
| 177 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | ||
| 178 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | ||
| 179 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | ||
| 180 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), | ||
| 181 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | ||
| 182 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | ||
| 183 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), | ||
| 184 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | ||
| 185 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | ||
| 186 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | ||
| 187 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), | ||
| 188 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | ||
| 189 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | ||
| 190 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | ||
| 191 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | ||
| 192 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | ||
| 193 | CLK(NULL, "ssi_ick", &ssi_ick, CK_343X), | ||
| 194 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | ||
| 195 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | ||
| 196 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | ||
| 197 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | ||
| 198 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | ||
| 199 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | ||
| 200 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X), | ||
| 201 | CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X), | ||
| 202 | CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X), | ||
| 203 | CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X), | ||
| 204 | CLK(NULL, "dss_ick", &dss_ick, CK_343X), | ||
| 205 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | ||
| 206 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | ||
| 207 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | ||
| 208 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), | ||
| 209 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | ||
| 210 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | ||
| 211 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | ||
| 212 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | ||
| 213 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | ||
| 214 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | ||
| 215 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), | ||
| 216 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | ||
| 217 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | ||
| 218 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), | ||
| 219 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), | ||
| 220 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | ||
| 221 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | ||
| 222 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | ||
| 223 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | ||
| 224 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | ||
| 225 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | ||
| 226 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | ||
| 227 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | ||
| 228 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | ||
| 229 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | ||
| 230 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | ||
| 231 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | ||
| 232 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | ||
| 233 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | ||
| 234 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | ||
| 235 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | ||
| 236 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | ||
| 237 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | ||
| 238 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | ||
| 239 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | ||
| 240 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | ||
| 241 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | ||
| 242 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | ||
| 243 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | ||
| 244 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | ||
| 245 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | ||
| 246 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | ||
| 247 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | ||
| 248 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | ||
| 249 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | ||
| 250 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | ||
| 251 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | ||
| 252 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | ||
| 253 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | ||
| 254 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | ||
| 255 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | ||
| 256 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | ||
| 257 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | ||
| 258 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), | ||
| 259 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | ||
| 260 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | ||
| 261 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | ||
| 262 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | ||
| 263 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | ||
| 264 | CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X), | ||
| 265 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), | ||
| 266 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | ||
| 267 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | ||
| 268 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | ||
| 269 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | ||
| 270 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | ||
| 271 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | ||
| 272 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | ||
| 273 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | ||
| 274 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | ||
| 275 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | ||
| 276 | }; | ||
| 277 | |||
| 42 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | 278 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ |
| 43 | #define DPLL_AUTOIDLE_DISABLE 0x0 | 279 | #define DPLL_AUTOIDLE_DISABLE 0x0 |
| 44 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | 280 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 |
| @@ -51,11 +287,9 @@ | |||
| 51 | * | 287 | * |
| 52 | * Recalculate and propagate the DPLL rate. | 288 | * Recalculate and propagate the DPLL rate. |
| 53 | */ | 289 | */ |
| 54 | static void omap3_dpll_recalc(struct clk *clk) | 290 | static unsigned long omap3_dpll_recalc(struct clk *clk) |
| 55 | { | 291 | { |
| 56 | clk->rate = omap2_get_dpll_rate(clk); | 292 | return omap2_get_dpll_rate(clk); |
| 57 | |||
| 58 | propagate_rate(clk); | ||
| 59 | } | 293 | } |
| 60 | 294 | ||
| 61 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | 295 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ |
| @@ -78,14 +312,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |||
| 78 | const struct dpll_data *dd; | 312 | const struct dpll_data *dd; |
| 79 | int i = 0; | 313 | int i = 0; |
| 80 | int ret = -EINVAL; | 314 | int ret = -EINVAL; |
| 81 | u32 idlest_mask; | ||
| 82 | 315 | ||
| 83 | dd = clk->dpll_data; | 316 | dd = clk->dpll_data; |
| 84 | 317 | ||
| 85 | state <<= dd->idlest_bit; | 318 | state <<= __ffs(dd->idlest_mask); |
| 86 | idlest_mask = 1 << dd->idlest_bit; | ||
| 87 | 319 | ||
| 88 | while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) && | 320 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && |
| 89 | i < MAX_DPLL_WAIT_TRIES) { | 321 | i < MAX_DPLL_WAIT_TRIES) { |
| 90 | i++; | 322 | i++; |
| 91 | udelay(1); | 323 | udelay(1); |
| @@ -104,6 +336,42 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |||
| 104 | return ret; | 336 | return ret; |
| 105 | } | 337 | } |
| 106 | 338 | ||
| 339 | /* From 3430 TRM ES2 4.7.6.2 */ | ||
| 340 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | ||
| 341 | { | ||
| 342 | unsigned long fint; | ||
| 343 | u16 f = 0; | ||
| 344 | |||
| 345 | fint = clk->dpll_data->clk_ref->rate / (n + 1); | ||
| 346 | |||
| 347 | pr_debug("clock: fint is %lu\n", fint); | ||
| 348 | |||
| 349 | if (fint >= 750000 && fint <= 1000000) | ||
| 350 | f = 0x3; | ||
| 351 | else if (fint > 1000000 && fint <= 1250000) | ||
| 352 | f = 0x4; | ||
| 353 | else if (fint > 1250000 && fint <= 1500000) | ||
| 354 | f = 0x5; | ||
| 355 | else if (fint > 1500000 && fint <= 1750000) | ||
| 356 | f = 0x6; | ||
| 357 | else if (fint > 1750000 && fint <= 2100000) | ||
| 358 | f = 0x7; | ||
| 359 | else if (fint > 7500000 && fint <= 10000000) | ||
| 360 | f = 0xB; | ||
| 361 | else if (fint > 10000000 && fint <= 12500000) | ||
| 362 | f = 0xC; | ||
| 363 | else if (fint > 12500000 && fint <= 15000000) | ||
| 364 | f = 0xD; | ||
| 365 | else if (fint > 15000000 && fint <= 17500000) | ||
| 366 | f = 0xE; | ||
| 367 | else if (fint > 17500000 && fint <= 21000000) | ||
| 368 | f = 0xF; | ||
| 369 | else | ||
| 370 | pr_debug("clock: unknown freqsel setting for %d\n", n); | ||
| 371 | |||
| 372 | return f; | ||
| 373 | } | ||
| 374 | |||
| 107 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | 375 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ |
| 108 | 376 | ||
| 109 | /* | 377 | /* |
| @@ -128,25 +396,20 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) | |||
| 128 | 396 | ||
| 129 | ai = omap3_dpll_autoidle_read(clk); | 397 | ai = omap3_dpll_autoidle_read(clk); |
| 130 | 398 | ||
| 399 | omap3_dpll_deny_idle(clk); | ||
| 400 | |||
| 131 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | 401 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); |
| 132 | 402 | ||
| 133 | if (ai) { | 403 | r = _omap3_wait_dpll_status(clk, 1); |
| 134 | /* | 404 | |
| 135 | * If no downstream clocks are enabled, CM_IDLEST bit | 405 | if (ai) |
| 136 | * may never become active, so don't wait for DPLL to lock. | ||
| 137 | */ | ||
| 138 | r = 0; | ||
| 139 | omap3_dpll_allow_idle(clk); | 406 | omap3_dpll_allow_idle(clk); |
| 140 | } else { | ||
| 141 | r = _omap3_wait_dpll_status(clk, 1); | ||
| 142 | omap3_dpll_deny_idle(clk); | ||
| 143 | }; | ||
| 144 | 407 | ||
| 145 | return r; | 408 | return r; |
| 146 | } | 409 | } |
| 147 | 410 | ||
| 148 | /* | 411 | /* |
| 149 | * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | 412 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness |
| 150 | * @clk: pointer to a DPLL struct clk | 413 | * @clk: pointer to a DPLL struct clk |
| 151 | * | 414 | * |
| 152 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | 415 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In |
| @@ -236,14 +499,25 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) | |||
| 236 | static int omap3_noncore_dpll_enable(struct clk *clk) | 499 | static int omap3_noncore_dpll_enable(struct clk *clk) |
| 237 | { | 500 | { |
| 238 | int r; | 501 | int r; |
| 502 | struct dpll_data *dd; | ||
| 239 | 503 | ||
| 240 | if (clk == &dpll3_ck) | 504 | if (clk == &dpll3_ck) |
| 241 | return -EINVAL; | 505 | return -EINVAL; |
| 242 | 506 | ||
| 243 | if (clk->parent->rate == clk_get_rate(clk)) | 507 | dd = clk->dpll_data; |
| 508 | if (!dd) | ||
| 509 | return -EINVAL; | ||
| 510 | |||
| 511 | if (clk->rate == dd->clk_bypass->rate) { | ||
| 512 | WARN_ON(clk->parent != dd->clk_bypass); | ||
| 244 | r = _omap3_noncore_dpll_bypass(clk); | 513 | r = _omap3_noncore_dpll_bypass(clk); |
| 245 | else | 514 | } else { |
| 515 | WARN_ON(clk->parent != dd->clk_ref); | ||
| 246 | r = _omap3_noncore_dpll_lock(clk); | 516 | r = _omap3_noncore_dpll_lock(clk); |
| 517 | } | ||
| 518 | /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */ | ||
| 519 | if (!r) | ||
| 520 | clk->rate = omap2_get_dpll_rate(clk); | ||
| 247 | 521 | ||
| 248 | return r; | 522 | return r; |
| 249 | } | 523 | } |
| @@ -270,6 +544,215 @@ static void omap3_noncore_dpll_disable(struct clk *clk) | |||
| 270 | _omap3_noncore_dpll_stop(clk); | 544 | _omap3_noncore_dpll_stop(clk); |
| 271 | } | 545 | } |
| 272 | 546 | ||
| 547 | |||
| 548 | /* Non-CORE DPLL rate set code */ | ||
| 549 | |||
| 550 | /* | ||
| 551 | * omap3_noncore_dpll_program - set non-core DPLL M,N values directly | ||
| 552 | * @clk: struct clk * of DPLL to set | ||
| 553 | * @m: DPLL multiplier to set | ||
| 554 | * @n: DPLL divider to set | ||
| 555 | * @freqsel: FREQSEL value to set | ||
| 556 | * | ||
| 557 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | ||
| 558 | * lock.. Returns -EINVAL upon error, or 0 upon success. | ||
| 559 | */ | ||
| 560 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | ||
| 561 | { | ||
| 562 | struct dpll_data *dd = clk->dpll_data; | ||
| 563 | u32 v; | ||
| 564 | |||
| 565 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | ||
| 566 | _omap3_noncore_dpll_bypass(clk); | ||
| 567 | |||
| 568 | /* Set jitter correction */ | ||
| 569 | v = __raw_readl(dd->control_reg); | ||
| 570 | v &= ~dd->freqsel_mask; | ||
| 571 | v |= freqsel << __ffs(dd->freqsel_mask); | ||
| 572 | __raw_writel(v, dd->control_reg); | ||
| 573 | |||
| 574 | /* Set DPLL multiplier, divider */ | ||
| 575 | v = __raw_readl(dd->mult_div1_reg); | ||
| 576 | v &= ~(dd->mult_mask | dd->div1_mask); | ||
| 577 | v |= m << __ffs(dd->mult_mask); | ||
| 578 | v |= (n - 1) << __ffs(dd->div1_mask); | ||
| 579 | __raw_writel(v, dd->mult_div1_reg); | ||
| 580 | |||
| 581 | /* We let the clock framework set the other output dividers later */ | ||
| 582 | |||
| 583 | /* REVISIT: Set ramp-up delay? */ | ||
| 584 | |||
| 585 | _omap3_noncore_dpll_lock(clk); | ||
| 586 | |||
| 587 | return 0; | ||
| 588 | } | ||
| 589 | |||
| 590 | /** | ||
| 591 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | ||
| 592 | * @clk: struct clk * of DPLL to set | ||
| 593 | * @rate: rounded target rate | ||
| 594 | * | ||
| 595 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | ||
| 596 | * low-power bypass, and the target rate is the bypass source clock | ||
| 597 | * rate, then configure the DPLL for bypass. Otherwise, round the | ||
| 598 | * target rate if it hasn't been done already, then program and lock | ||
| 599 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | ||
| 600 | */ | ||
| 601 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | ||
| 602 | { | ||
| 603 | struct clk *new_parent = NULL; | ||
| 604 | u16 freqsel; | ||
| 605 | struct dpll_data *dd; | ||
| 606 | int ret; | ||
| 607 | |||
| 608 | if (!clk || !rate) | ||
| 609 | return -EINVAL; | ||
| 610 | |||
| 611 | dd = clk->dpll_data; | ||
| 612 | if (!dd) | ||
| 613 | return -EINVAL; | ||
| 614 | |||
| 615 | if (rate == omap2_get_dpll_rate(clk)) | ||
| 616 | return 0; | ||
| 617 | |||
| 618 | /* | ||
| 619 | * Ensure both the bypass and ref clocks are enabled prior to | ||
| 620 | * doing anything; we need the bypass clock running to reprogram | ||
| 621 | * the DPLL. | ||
| 622 | */ | ||
| 623 | omap2_clk_enable(dd->clk_bypass); | ||
| 624 | omap2_clk_enable(dd->clk_ref); | ||
| 625 | |||
| 626 | if (dd->clk_bypass->rate == rate && | ||
| 627 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | ||
| 628 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | ||
| 629 | |||
| 630 | ret = _omap3_noncore_dpll_bypass(clk); | ||
| 631 | if (!ret) | ||
| 632 | new_parent = dd->clk_bypass; | ||
| 633 | } else { | ||
| 634 | if (dd->last_rounded_rate != rate) | ||
| 635 | omap2_dpll_round_rate(clk, rate); | ||
| 636 | |||
| 637 | if (dd->last_rounded_rate == 0) | ||
| 638 | return -EINVAL; | ||
| 639 | |||
| 640 | freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); | ||
| 641 | if (!freqsel) | ||
| 642 | WARN_ON(1); | ||
| 643 | |||
| 644 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | ||
| 645 | clk->name, rate); | ||
| 646 | |||
| 647 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | ||
| 648 | dd->last_rounded_n, freqsel); | ||
| 649 | if (!ret) | ||
| 650 | new_parent = dd->clk_ref; | ||
| 651 | } | ||
| 652 | if (!ret) { | ||
| 653 | /* | ||
| 654 | * Switch the parent clock in the heirarchy, and make sure | ||
| 655 | * that the new parent's usecount is correct. Note: we | ||
| 656 | * enable the new parent before disabling the old to avoid | ||
| 657 | * any unnecessary hardware disable->enable transitions. | ||
| 658 | */ | ||
| 659 | if (clk->usecount) { | ||
| 660 | omap2_clk_enable(new_parent); | ||
| 661 | omap2_clk_disable(clk->parent); | ||
| 662 | } | ||
| 663 | clk_reparent(clk, new_parent); | ||
| 664 | clk->rate = rate; | ||
| 665 | } | ||
| 666 | omap2_clk_disable(dd->clk_ref); | ||
| 667 | omap2_clk_disable(dd->clk_bypass); | ||
| 668 | |||
| 669 | return 0; | ||
| 670 | } | ||
| 671 | |||
| 672 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | ||
| 673 | { | ||
| 674 | /* | ||
| 675 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | ||
| 676 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | ||
| 677 | * on DPLL4. | ||
| 678 | */ | ||
| 679 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
| 680 | printk(KERN_ERR "clock: DPLL4 cannot change rate due to " | ||
| 681 | "silicon 'Limitation 2.5' on 3430ES1.\n"); | ||
| 682 | return -EINVAL; | ||
| 683 | } | ||
| 684 | return omap3_noncore_dpll_set_rate(clk, rate); | ||
| 685 | } | ||
| 686 | |||
| 687 | |||
| 688 | /* | ||
| 689 | * CORE DPLL (DPLL3) rate programming functions | ||
| 690 | * | ||
| 691 | * These call into SRAM code to do the actual CM writes, since the SDRAM | ||
| 692 | * is clocked from DPLL3. | ||
| 693 | */ | ||
| 694 | |||
| 695 | /** | ||
| 696 | * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider | ||
| 697 | * @clk: struct clk * of DPLL to set | ||
| 698 | * @rate: rounded target rate | ||
| 699 | * | ||
| 700 | * Program the DPLL M2 divider with the rounded target rate. Returns | ||
| 701 | * -EINVAL upon error, or 0 upon success. | ||
| 702 | */ | ||
| 703 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | ||
| 704 | { | ||
| 705 | u32 new_div = 0; | ||
| 706 | unsigned long validrate, sdrcrate; | ||
| 707 | struct omap_sdrc_params *sp; | ||
| 708 | |||
| 709 | if (!clk || !rate) | ||
| 710 | return -EINVAL; | ||
| 711 | |||
| 712 | if (clk != &dpll3_m2_ck) | ||
| 713 | return -EINVAL; | ||
| 714 | |||
| 715 | if (rate == clk->rate) | ||
| 716 | return 0; | ||
| 717 | |||
| 718 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | ||
| 719 | if (validrate != rate) | ||
| 720 | return -EINVAL; | ||
| 721 | |||
| 722 | sdrcrate = sdrc_ick.rate; | ||
| 723 | if (rate > clk->rate) | ||
| 724 | sdrcrate <<= ((rate / clk->rate) - 1); | ||
| 725 | else | ||
| 726 | sdrcrate >>= ((clk->rate / rate) - 1); | ||
| 727 | |||
| 728 | sp = omap2_sdrc_get_params(sdrcrate); | ||
| 729 | if (!sp) | ||
| 730 | return -EINVAL; | ||
| 731 | |||
| 732 | pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | ||
| 733 | validrate); | ||
| 734 | pr_info("clock: SDRC timing params used: %08x %08x %08x\n", | ||
| 735 | sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); | ||
| 736 | |||
| 737 | /* REVISIT: SRAM code doesn't support other M2 divisors yet */ | ||
| 738 | WARN_ON(new_div != 1 && new_div != 2); | ||
| 739 | |||
| 740 | /* REVISIT: Add SDRC_MR changing to this code also */ | ||
| 741 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, | ||
| 742 | sp->actim_ctrlb, new_div); | ||
| 743 | |||
| 744 | return 0; | ||
| 745 | } | ||
| 746 | |||
| 747 | |||
| 748 | static const struct clkops clkops_noncore_dpll_ops = { | ||
| 749 | .enable = &omap3_noncore_dpll_enable, | ||
| 750 | .disable = &omap3_noncore_dpll_disable, | ||
| 751 | }; | ||
| 752 | |||
| 753 | /* DPLL autoidle read/set code */ | ||
| 754 | |||
| 755 | |||
| 273 | /** | 756 | /** |
| 274 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | 757 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits |
| 275 | * @clk: struct clk * of the DPLL to read | 758 | * @clk: struct clk * of the DPLL to read |
| @@ -356,9 +839,10 @@ static void omap3_dpll_deny_idle(struct clk *clk) | |||
| 356 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | 839 | * Using parent clock DPLL data, look up DPLL state. If locked, set our |
| 357 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | 840 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. |
| 358 | */ | 841 | */ |
| 359 | static void omap3_clkoutx2_recalc(struct clk *clk) | 842 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk) |
| 360 | { | 843 | { |
| 361 | const struct dpll_data *dd; | 844 | const struct dpll_data *dd; |
| 845 | unsigned long rate; | ||
| 362 | u32 v; | 846 | u32 v; |
| 363 | struct clk *pclk; | 847 | struct clk *pclk; |
| 364 | 848 | ||
| @@ -372,17 +856,15 @@ static void omap3_clkoutx2_recalc(struct clk *clk) | |||
| 372 | 856 | ||
| 373 | dd = pclk->dpll_data; | 857 | dd = pclk->dpll_data; |
| 374 | 858 | ||
| 375 | WARN_ON(!dd->control_reg || !dd->enable_mask); | 859 | WARN_ON(!dd->enable_mask); |
| 376 | 860 | ||
| 377 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | 861 | v = __raw_readl(dd->control_reg) & dd->enable_mask; |
| 378 | v >>= __ffs(dd->enable_mask); | 862 | v >>= __ffs(dd->enable_mask); |
| 379 | if (v != DPLL_LOCKED) | 863 | if (v != OMAP3XXX_EN_DPLL_LOCKED) |
| 380 | clk->rate = clk->parent->rate; | 864 | rate = clk->parent->rate; |
| 381 | else | 865 | else |
| 382 | clk->rate = clk->parent->rate * 2; | 866 | rate = clk->parent->rate * 2; |
| 383 | 867 | return rate; | |
| 384 | if (clk->flags & RATE_PROPAGATES) | ||
| 385 | propagate_rate(clk); | ||
| 386 | } | 868 | } |
| 387 | 869 | ||
| 388 | /* Common clock code */ | 870 | /* Common clock code */ |
| @@ -432,7 +914,7 @@ static int __init omap2_clk_arch_init(void) | |||
| 432 | 914 | ||
| 433 | /* REVISIT: not yet ready for 343x */ | 915 | /* REVISIT: not yet ready for 343x */ |
| 434 | #if 0 | 916 | #if 0 |
| 435 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | 917 | if (clk_set_rate(&virt_prcm_set, mpurate)) |
| 436 | printk(KERN_ERR "Could not find matching MPU rate\n"); | 918 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
| 437 | #endif | 919 | #endif |
| 438 | 920 | ||
| @@ -450,26 +932,13 @@ arch_initcall(omap2_clk_arch_init); | |||
| 450 | int __init omap2_clk_init(void) | 932 | int __init omap2_clk_init(void) |
| 451 | { | 933 | { |
| 452 | /* struct prcm_config *prcm; */ | 934 | /* struct prcm_config *prcm; */ |
| 453 | struct clk **clkp; | 935 | struct omap_clk *c; |
| 454 | /* u32 clkrate; */ | 936 | /* u32 clkrate; */ |
| 455 | u32 cpu_clkflg; | 937 | u32 cpu_clkflg; |
| 456 | 938 | ||
| 457 | /* REVISIT: Ultimately this will be used for multiboot */ | ||
| 458 | #if 0 | ||
| 459 | if (cpu_is_omap242x()) { | ||
| 460 | cpu_mask = RATE_IN_242X; | ||
| 461 | cpu_clkflg = CLOCK_IN_OMAP242X; | ||
| 462 | clkp = onchip_24xx_clks; | ||
| 463 | } else if (cpu_is_omap2430()) { | ||
| 464 | cpu_mask = RATE_IN_243X; | ||
| 465 | cpu_clkflg = CLOCK_IN_OMAP243X; | ||
| 466 | clkp = onchip_24xx_clks; | ||
| 467 | } | ||
| 468 | #endif | ||
| 469 | if (cpu_is_omap34xx()) { | 939 | if (cpu_is_omap34xx()) { |
| 470 | cpu_mask = RATE_IN_343X; | 940 | cpu_mask = RATE_IN_343X; |
| 471 | cpu_clkflg = CLOCK_IN_OMAP343X; | 941 | cpu_clkflg = CK_343X; |
| 472 | clkp = onchip_34xx_clks; | ||
| 473 | 942 | ||
| 474 | /* | 943 | /* |
| 475 | * Update this if there are further clock changes between ES2 | 944 | * Update this if there are further clock changes between ES2 |
| @@ -477,23 +946,24 @@ int __init omap2_clk_init(void) | |||
| 477 | */ | 946 | */ |
| 478 | if (omap_rev() == OMAP3430_REV_ES1_0) { | 947 | if (omap_rev() == OMAP3430_REV_ES1_0) { |
| 479 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | 948 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ |
| 480 | cpu_clkflg |= CLOCK_IN_OMAP3430ES1; | 949 | cpu_clkflg |= CK_3430ES1; |
| 481 | } else { | 950 | } else { |
| 482 | cpu_mask |= RATE_IN_3430ES2; | 951 | cpu_mask |= RATE_IN_3430ES2; |
| 483 | cpu_clkflg |= CLOCK_IN_OMAP3430ES2; | 952 | cpu_clkflg |= CK_3430ES2; |
| 484 | } | 953 | } |
| 485 | } | 954 | } |
| 486 | 955 | ||
| 487 | clk_init(&omap2_clk_functions); | 956 | clk_init(&omap2_clk_functions); |
| 488 | 957 | ||
| 489 | for (clkp = onchip_34xx_clks; | 958 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
| 490 | clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); | 959 | clk_init_one(c->lk.clk); |
| 491 | clkp++) { | 960 | |
| 492 | if ((*clkp)->flags & cpu_clkflg) { | 961 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
| 493 | clk_register(*clkp); | 962 | if (c->cpu & cpu_clkflg) { |
| 494 | omap2_init_clk_clkdm(*clkp); | 963 | clkdev_add(&c->lk); |
| 964 | clk_register(c->lk.clk); | ||
| 965 | omap2_init_clk_clkdm(c->lk.clk); | ||
| 495 | } | 966 | } |
| 496 | } | ||
| 497 | 967 | ||
| 498 | /* REVISIT: Not yet ready for OMAP3 */ | 968 | /* REVISIT: Not yet ready for OMAP3 */ |
| 499 | #if 0 | 969 | #if 0 |
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index a826094d89b5..70ec10deb654 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
| @@ -27,13 +27,14 @@ | |||
| 27 | #include "prm.h" | 27 | #include "prm.h" |
| 28 | #include "prm-regbits-34xx.h" | 28 | #include "prm-regbits-34xx.h" |
| 29 | 29 | ||
| 30 | static void omap3_dpll_recalc(struct clk *clk); | 30 | static unsigned long omap3_dpll_recalc(struct clk *clk); |
| 31 | static void omap3_clkoutx2_recalc(struct clk *clk); | 31 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk); |
| 32 | static void omap3_dpll_allow_idle(struct clk *clk); | 32 | static void omap3_dpll_allow_idle(struct clk *clk); |
| 33 | static void omap3_dpll_deny_idle(struct clk *clk); | 33 | static void omap3_dpll_deny_idle(struct clk *clk); |
| 34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); | 34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); |
| 35 | static int omap3_noncore_dpll_enable(struct clk *clk); | 35 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
| 36 | static void omap3_noncore_dpll_disable(struct clk *clk); | 36 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); |
| 37 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
| 37 | 38 | ||
| 38 | /* Maximum DPLL multiplier, divider values for OMAP3 */ | 39 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
| 39 | #define OMAP3_MAX_DPLL_MULT 2048 | 40 | #define OMAP3_MAX_DPLL_MULT 2048 |
| @@ -47,6 +48,10 @@ static void omap3_noncore_dpll_disable(struct clk *clk); | |||
| 47 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | 48 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). |
| 48 | */ | 49 | */ |
| 49 | 50 | ||
| 51 | /* Forward declarations for DPLL bypass clocks */ | ||
| 52 | static struct clk dpll1_fck; | ||
| 53 | static struct clk dpll2_fck; | ||
| 54 | |||
| 50 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ | 55 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 51 | #define DPLL_LOW_POWER_STOP 0x1 | 56 | #define DPLL_LOW_POWER_STOP 0x1 |
| 52 | #define DPLL_LOW_POWER_BYPASS 0x5 | 57 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| @@ -57,67 +62,59 @@ static void omap3_noncore_dpll_disable(struct clk *clk); | |||
| 57 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | 62 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ |
| 58 | static struct clk omap_32k_fck = { | 63 | static struct clk omap_32k_fck = { |
| 59 | .name = "omap_32k_fck", | 64 | .name = "omap_32k_fck", |
| 65 | .ops = &clkops_null, | ||
| 60 | .rate = 32768, | 66 | .rate = 32768, |
| 61 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 67 | .flags = RATE_FIXED, |
| 62 | ALWAYS_ENABLED, | ||
| 63 | .recalc = &propagate_rate, | ||
| 64 | }; | 68 | }; |
| 65 | 69 | ||
| 66 | static struct clk secure_32k_fck = { | 70 | static struct clk secure_32k_fck = { |
| 67 | .name = "secure_32k_fck", | 71 | .name = "secure_32k_fck", |
| 72 | .ops = &clkops_null, | ||
| 68 | .rate = 32768, | 73 | .rate = 32768, |
| 69 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 74 | .flags = RATE_FIXED, |
| 70 | ALWAYS_ENABLED, | ||
| 71 | .recalc = &propagate_rate, | ||
| 72 | }; | 75 | }; |
| 73 | 76 | ||
| 74 | /* Virtual source clocks for osc_sys_ck */ | 77 | /* Virtual source clocks for osc_sys_ck */ |
| 75 | static struct clk virt_12m_ck = { | 78 | static struct clk virt_12m_ck = { |
| 76 | .name = "virt_12m_ck", | 79 | .name = "virt_12m_ck", |
| 80 | .ops = &clkops_null, | ||
| 77 | .rate = 12000000, | 81 | .rate = 12000000, |
| 78 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 82 | .flags = RATE_FIXED, |
| 79 | ALWAYS_ENABLED, | ||
| 80 | .recalc = &propagate_rate, | ||
| 81 | }; | 83 | }; |
| 82 | 84 | ||
| 83 | static struct clk virt_13m_ck = { | 85 | static struct clk virt_13m_ck = { |
| 84 | .name = "virt_13m_ck", | 86 | .name = "virt_13m_ck", |
| 87 | .ops = &clkops_null, | ||
| 85 | .rate = 13000000, | 88 | .rate = 13000000, |
| 86 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 89 | .flags = RATE_FIXED, |
| 87 | ALWAYS_ENABLED, | ||
| 88 | .recalc = &propagate_rate, | ||
| 89 | }; | 90 | }; |
| 90 | 91 | ||
| 91 | static struct clk virt_16_8m_ck = { | 92 | static struct clk virt_16_8m_ck = { |
| 92 | .name = "virt_16_8m_ck", | 93 | .name = "virt_16_8m_ck", |
| 94 | .ops = &clkops_null, | ||
| 93 | .rate = 16800000, | 95 | .rate = 16800000, |
| 94 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | | 96 | .flags = RATE_FIXED, |
| 95 | ALWAYS_ENABLED, | ||
| 96 | .recalc = &propagate_rate, | ||
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | static struct clk virt_19_2m_ck = { | 99 | static struct clk virt_19_2m_ck = { |
| 100 | .name = "virt_19_2m_ck", | 100 | .name = "virt_19_2m_ck", |
| 101 | .ops = &clkops_null, | ||
| 101 | .rate = 19200000, | 102 | .rate = 19200000, |
| 102 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 103 | .flags = RATE_FIXED, |
| 103 | ALWAYS_ENABLED, | ||
| 104 | .recalc = &propagate_rate, | ||
| 105 | }; | 104 | }; |
| 106 | 105 | ||
| 107 | static struct clk virt_26m_ck = { | 106 | static struct clk virt_26m_ck = { |
| 108 | .name = "virt_26m_ck", | 107 | .name = "virt_26m_ck", |
| 108 | .ops = &clkops_null, | ||
| 109 | .rate = 26000000, | 109 | .rate = 26000000, |
| 110 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 110 | .flags = RATE_FIXED, |
| 111 | ALWAYS_ENABLED, | ||
| 112 | .recalc = &propagate_rate, | ||
| 113 | }; | 111 | }; |
| 114 | 112 | ||
| 115 | static struct clk virt_38_4m_ck = { | 113 | static struct clk virt_38_4m_ck = { |
| 116 | .name = "virt_38_4m_ck", | 114 | .name = "virt_38_4m_ck", |
| 115 | .ops = &clkops_null, | ||
| 117 | .rate = 38400000, | 116 | .rate = 38400000, |
| 118 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 117 | .flags = RATE_FIXED, |
| 119 | ALWAYS_ENABLED, | ||
| 120 | .recalc = &propagate_rate, | ||
| 121 | }; | 118 | }; |
| 122 | 119 | ||
| 123 | static const struct clksel_rate osc_sys_12m_rates[] = { | 120 | static const struct clksel_rate osc_sys_12m_rates[] = { |
| @@ -164,13 +161,13 @@ static const struct clksel osc_sys_clksel[] = { | |||
| 164 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | 161 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ |
| 165 | static struct clk osc_sys_ck = { | 162 | static struct clk osc_sys_ck = { |
| 166 | .name = "osc_sys_ck", | 163 | .name = "osc_sys_ck", |
| 164 | .ops = &clkops_null, | ||
| 167 | .init = &omap2_init_clksel_parent, | 165 | .init = &omap2_init_clksel_parent, |
| 168 | .clksel_reg = OMAP3430_PRM_CLKSEL, | 166 | .clksel_reg = OMAP3430_PRM_CLKSEL, |
| 169 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | 167 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
| 170 | .clksel = osc_sys_clksel, | 168 | .clksel = osc_sys_clksel, |
| 171 | /* REVISIT: deal with autoextclkmode? */ | 169 | /* REVISIT: deal with autoextclkmode? */ |
| 172 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 170 | .flags = RATE_FIXED, |
| 173 | ALWAYS_ENABLED, | ||
| 174 | .recalc = &omap2_clksel_recalc, | 171 | .recalc = &omap2_clksel_recalc, |
| 175 | }; | 172 | }; |
| 176 | 173 | ||
| @@ -189,36 +186,34 @@ static const struct clksel sys_clksel[] = { | |||
| 189 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | 186 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ |
| 190 | static struct clk sys_ck = { | 187 | static struct clk sys_ck = { |
| 191 | .name = "sys_ck", | 188 | .name = "sys_ck", |
| 189 | .ops = &clkops_null, | ||
| 192 | .parent = &osc_sys_ck, | 190 | .parent = &osc_sys_ck, |
| 193 | .init = &omap2_init_clksel_parent, | 191 | .init = &omap2_init_clksel_parent, |
| 194 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | 192 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, |
| 195 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | 193 | .clksel_mask = OMAP_SYSCLKDIV_MASK, |
| 196 | .clksel = sys_clksel, | 194 | .clksel = sys_clksel, |
| 197 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 198 | .recalc = &omap2_clksel_recalc, | 195 | .recalc = &omap2_clksel_recalc, |
| 199 | }; | 196 | }; |
| 200 | 197 | ||
| 201 | static struct clk sys_altclk = { | 198 | static struct clk sys_altclk = { |
| 202 | .name = "sys_altclk", | 199 | .name = "sys_altclk", |
| 203 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 200 | .ops = &clkops_null, |
| 204 | .recalc = &propagate_rate, | ||
| 205 | }; | 201 | }; |
| 206 | 202 | ||
| 207 | /* Optional external clock input for some McBSPs */ | 203 | /* Optional external clock input for some McBSPs */ |
| 208 | static struct clk mcbsp_clks = { | 204 | static struct clk mcbsp_clks = { |
| 209 | .name = "mcbsp_clks", | 205 | .name = "mcbsp_clks", |
| 210 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 206 | .ops = &clkops_null, |
| 211 | .recalc = &propagate_rate, | ||
| 212 | }; | 207 | }; |
| 213 | 208 | ||
| 214 | /* PRM EXTERNAL CLOCK OUTPUT */ | 209 | /* PRM EXTERNAL CLOCK OUTPUT */ |
| 215 | 210 | ||
| 216 | static struct clk sys_clkout1 = { | 211 | static struct clk sys_clkout1 = { |
| 217 | .name = "sys_clkout1", | 212 | .name = "sys_clkout1", |
| 213 | .ops = &clkops_omap2_dflt, | ||
| 218 | .parent = &osc_sys_ck, | 214 | .parent = &osc_sys_ck, |
| 219 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | 215 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, |
| 220 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | 216 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, |
| 221 | .flags = CLOCK_IN_OMAP343X, | ||
| 222 | .recalc = &followparent_recalc, | 217 | .recalc = &followparent_recalc, |
| 223 | }; | 218 | }; |
| 224 | 219 | ||
| @@ -226,16 +221,6 @@ static struct clk sys_clkout1 = { | |||
| 226 | 221 | ||
| 227 | /* CM CLOCKS */ | 222 | /* CM CLOCKS */ |
| 228 | 223 | ||
| 229 | static const struct clksel_rate dpll_bypass_rates[] = { | ||
| 230 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 231 | { .div = 0 } | ||
| 232 | }; | ||
| 233 | |||
| 234 | static const struct clksel_rate dpll_locked_rates[] = { | ||
| 235 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 236 | { .div = 0 } | ||
| 237 | }; | ||
| 238 | |||
| 239 | static const struct clksel_rate div16_dpll_rates[] = { | 224 | static const struct clksel_rate div16_dpll_rates[] = { |
| 240 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | 225 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 241 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | 226 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| @@ -263,6 +248,9 @@ static struct dpll_data dpll1_dd = { | |||
| 263 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | 248 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 264 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | 249 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, |
| 265 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | 250 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, |
| 251 | .clk_bypass = &dpll1_fck, | ||
| 252 | .clk_ref = &sys_ck, | ||
| 253 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, | ||
| 266 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), | 254 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
| 267 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | 255 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, |
| 268 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | 256 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| @@ -272,18 +260,21 @@ static struct dpll_data dpll1_dd = { | |||
| 272 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), | 260 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 273 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | 261 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, |
| 274 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | 262 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 275 | .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, | 263 | .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 276 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 264 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 265 | .min_divider = 1, | ||
| 277 | .max_divider = OMAP3_MAX_DPLL_DIV, | 266 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 278 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 267 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 279 | }; | 268 | }; |
| 280 | 269 | ||
| 281 | static struct clk dpll1_ck = { | 270 | static struct clk dpll1_ck = { |
| 282 | .name = "dpll1_ck", | 271 | .name = "dpll1_ck", |
| 272 | .ops = &clkops_null, | ||
| 283 | .parent = &sys_ck, | 273 | .parent = &sys_ck, |
| 284 | .dpll_data = &dpll1_dd, | 274 | .dpll_data = &dpll1_dd, |
| 285 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 286 | .round_rate = &omap2_dpll_round_rate, | 275 | .round_rate = &omap2_dpll_round_rate, |
| 276 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
| 277 | .clkdm_name = "dpll1_clkdm", | ||
| 287 | .recalc = &omap3_dpll_recalc, | 278 | .recalc = &omap3_dpll_recalc, |
| 288 | }; | 279 | }; |
| 289 | 280 | ||
| @@ -293,9 +284,9 @@ static struct clk dpll1_ck = { | |||
| 293 | */ | 284 | */ |
| 294 | static struct clk dpll1_x2_ck = { | 285 | static struct clk dpll1_x2_ck = { |
| 295 | .name = "dpll1_x2_ck", | 286 | .name = "dpll1_x2_ck", |
| 287 | .ops = &clkops_null, | ||
| 296 | .parent = &dpll1_ck, | 288 | .parent = &dpll1_ck, |
| 297 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 289 | .clkdm_name = "dpll1_clkdm", |
| 298 | PARENT_CONTROLS_CLOCK, | ||
| 299 | .recalc = &omap3_clkoutx2_recalc, | 290 | .recalc = &omap3_clkoutx2_recalc, |
| 300 | }; | 291 | }; |
| 301 | 292 | ||
| @@ -311,13 +302,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = { | |||
| 311 | */ | 302 | */ |
| 312 | static struct clk dpll1_x2m2_ck = { | 303 | static struct clk dpll1_x2m2_ck = { |
| 313 | .name = "dpll1_x2m2_ck", | 304 | .name = "dpll1_x2m2_ck", |
| 305 | .ops = &clkops_null, | ||
| 314 | .parent = &dpll1_x2_ck, | 306 | .parent = &dpll1_x2_ck, |
| 315 | .init = &omap2_init_clksel_parent, | 307 | .init = &omap2_init_clksel_parent, |
| 316 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | 308 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), |
| 317 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | 309 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, |
| 318 | .clksel = div16_dpll1_x2m2_clksel, | 310 | .clksel = div16_dpll1_x2m2_clksel, |
| 319 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 311 | .clkdm_name = "dpll1_clkdm", |
| 320 | PARENT_CONTROLS_CLOCK, | ||
| 321 | .recalc = &omap2_clksel_recalc, | 312 | .recalc = &omap2_clksel_recalc, |
| 322 | }; | 313 | }; |
| 323 | 314 | ||
| @@ -329,6 +320,9 @@ static struct dpll_data dpll2_dd = { | |||
| 329 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | 320 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 330 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | 321 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, |
| 331 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | 322 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, |
| 323 | .clk_bypass = &dpll2_fck, | ||
| 324 | .clk_ref = &sys_ck, | ||
| 325 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, | ||
| 332 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), | 326 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
| 333 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | 327 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, |
| 334 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | | 328 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
| @@ -339,20 +333,21 @@ static struct dpll_data dpll2_dd = { | |||
| 339 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), | 333 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 340 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | 334 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, |
| 341 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | 335 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), |
| 342 | .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, | 336 | .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, |
| 343 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 337 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 338 | .min_divider = 1, | ||
| 344 | .max_divider = OMAP3_MAX_DPLL_DIV, | 339 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 345 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 340 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 346 | }; | 341 | }; |
| 347 | 342 | ||
| 348 | static struct clk dpll2_ck = { | 343 | static struct clk dpll2_ck = { |
| 349 | .name = "dpll2_ck", | 344 | .name = "dpll2_ck", |
| 345 | .ops = &clkops_noncore_dpll_ops, | ||
| 350 | .parent = &sys_ck, | 346 | .parent = &sys_ck, |
| 351 | .dpll_data = &dpll2_dd, | 347 | .dpll_data = &dpll2_dd, |
| 352 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 353 | .enable = &omap3_noncore_dpll_enable, | ||
| 354 | .disable = &omap3_noncore_dpll_disable, | ||
| 355 | .round_rate = &omap2_dpll_round_rate, | 348 | .round_rate = &omap2_dpll_round_rate, |
| 349 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
| 350 | .clkdm_name = "dpll2_clkdm", | ||
| 356 | .recalc = &omap3_dpll_recalc, | 351 | .recalc = &omap3_dpll_recalc, |
| 357 | }; | 352 | }; |
| 358 | 353 | ||
| @@ -367,14 +362,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = { | |||
| 367 | */ | 362 | */ |
| 368 | static struct clk dpll2_m2_ck = { | 363 | static struct clk dpll2_m2_ck = { |
| 369 | .name = "dpll2_m2_ck", | 364 | .name = "dpll2_m2_ck", |
| 365 | .ops = &clkops_null, | ||
| 370 | .parent = &dpll2_ck, | 366 | .parent = &dpll2_ck, |
| 371 | .init = &omap2_init_clksel_parent, | 367 | .init = &omap2_init_clksel_parent, |
| 372 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | 368 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 373 | OMAP3430_CM_CLKSEL2_PLL), | 369 | OMAP3430_CM_CLKSEL2_PLL), |
| 374 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | 370 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, |
| 375 | .clksel = div16_dpll2_m2x2_clksel, | 371 | .clksel = div16_dpll2_m2x2_clksel, |
| 376 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 372 | .clkdm_name = "dpll2_clkdm", |
| 377 | PARENT_CONTROLS_CLOCK, | ||
| 378 | .recalc = &omap2_clksel_recalc, | 373 | .recalc = &omap2_clksel_recalc, |
| 379 | }; | 374 | }; |
| 380 | 375 | ||
| @@ -387,6 +382,9 @@ static struct dpll_data dpll3_dd = { | |||
| 387 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 382 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 388 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | 383 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, |
| 389 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | 384 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, |
| 385 | .clk_bypass = &sys_ck, | ||
| 386 | .clk_ref = &sys_ck, | ||
| 387 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, | ||
| 390 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 388 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 391 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | 389 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, |
| 392 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | 390 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, |
| @@ -394,17 +392,21 @@ static struct dpll_data dpll3_dd = { | |||
| 394 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | 392 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, |
| 395 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | 393 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 396 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | 394 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, |
| 395 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 396 | .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, | ||
| 397 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 397 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 398 | .min_divider = 1, | ||
| 398 | .max_divider = OMAP3_MAX_DPLL_DIV, | 399 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 399 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 400 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 400 | }; | 401 | }; |
| 401 | 402 | ||
| 402 | static struct clk dpll3_ck = { | 403 | static struct clk dpll3_ck = { |
| 403 | .name = "dpll3_ck", | 404 | .name = "dpll3_ck", |
| 405 | .ops = &clkops_null, | ||
| 404 | .parent = &sys_ck, | 406 | .parent = &sys_ck, |
| 405 | .dpll_data = &dpll3_dd, | 407 | .dpll_data = &dpll3_dd, |
| 406 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 407 | .round_rate = &omap2_dpll_round_rate, | 408 | .round_rate = &omap2_dpll_round_rate, |
| 409 | .clkdm_name = "dpll3_clkdm", | ||
| 408 | .recalc = &omap3_dpll_recalc, | 410 | .recalc = &omap3_dpll_recalc, |
| 409 | }; | 411 | }; |
| 410 | 412 | ||
| @@ -414,9 +416,9 @@ static struct clk dpll3_ck = { | |||
| 414 | */ | 416 | */ |
| 415 | static struct clk dpll3_x2_ck = { | 417 | static struct clk dpll3_x2_ck = { |
| 416 | .name = "dpll3_x2_ck", | 418 | .name = "dpll3_x2_ck", |
| 419 | .ops = &clkops_null, | ||
| 417 | .parent = &dpll3_ck, | 420 | .parent = &dpll3_ck, |
| 418 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 421 | .clkdm_name = "dpll3_clkdm", |
| 419 | PARENT_CONTROLS_CLOCK, | ||
| 420 | .recalc = &omap3_clkoutx2_recalc, | 422 | .recalc = &omap3_clkoutx2_recalc, |
| 421 | }; | 423 | }; |
| 422 | 424 | ||
| @@ -460,55 +462,34 @@ static const struct clksel div31_dpll3m2_clksel[] = { | |||
| 460 | { .parent = NULL } | 462 | { .parent = NULL } |
| 461 | }; | 463 | }; |
| 462 | 464 | ||
| 463 | /* | 465 | /* DPLL3 output M2 - primary control point for CORE speed */ |
| 464 | * DPLL3 output M2 | ||
| 465 | * REVISIT: This DPLL output divider must be changed in SRAM, so until | ||
| 466 | * that code is ready, this should remain a 'read-only' clksel clock. | ||
| 467 | */ | ||
| 468 | static struct clk dpll3_m2_ck = { | 466 | static struct clk dpll3_m2_ck = { |
| 469 | .name = "dpll3_m2_ck", | 467 | .name = "dpll3_m2_ck", |
| 468 | .ops = &clkops_null, | ||
| 470 | .parent = &dpll3_ck, | 469 | .parent = &dpll3_ck, |
| 471 | .init = &omap2_init_clksel_parent, | 470 | .init = &omap2_init_clksel_parent, |
| 472 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 471 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 473 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | 472 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, |
| 474 | .clksel = div31_dpll3m2_clksel, | 473 | .clksel = div31_dpll3m2_clksel, |
| 475 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 474 | .clkdm_name = "dpll3_clkdm", |
| 476 | PARENT_CONTROLS_CLOCK, | 475 | .round_rate = &omap2_clksel_round_rate, |
| 476 | .set_rate = &omap3_core_dpll_m2_set_rate, | ||
| 477 | .recalc = &omap2_clksel_recalc, | 477 | .recalc = &omap2_clksel_recalc, |
| 478 | }; | 478 | }; |
| 479 | 479 | ||
| 480 | static const struct clksel core_ck_clksel[] = { | ||
| 481 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 482 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, | ||
| 483 | { .parent = NULL } | ||
| 484 | }; | ||
| 485 | |||
| 486 | static struct clk core_ck = { | 480 | static struct clk core_ck = { |
| 487 | .name = "core_ck", | 481 | .name = "core_ck", |
| 488 | .init = &omap2_init_clksel_parent, | 482 | .ops = &clkops_null, |
| 489 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 483 | .parent = &dpll3_m2_ck, |
| 490 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, | 484 | .recalc = &followparent_recalc, |
| 491 | .clksel = core_ck_clksel, | ||
| 492 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 493 | PARENT_CONTROLS_CLOCK, | ||
| 494 | .recalc = &omap2_clksel_recalc, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static const struct clksel dpll3_m2x2_ck_clksel[] = { | ||
| 498 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 499 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, | ||
| 500 | { .parent = NULL } | ||
| 501 | }; | 485 | }; |
| 502 | 486 | ||
| 503 | static struct clk dpll3_m2x2_ck = { | 487 | static struct clk dpll3_m2x2_ck = { |
| 504 | .name = "dpll3_m2x2_ck", | 488 | .name = "dpll3_m2x2_ck", |
| 505 | .init = &omap2_init_clksel_parent, | 489 | .ops = &clkops_null, |
| 506 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 490 | .parent = &dpll3_x2_ck, |
| 507 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, | 491 | .clkdm_name = "dpll3_clkdm", |
| 508 | .clksel = dpll3_m2x2_ck_clksel, | 492 | .recalc = &followparent_recalc, |
| 509 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 510 | PARENT_CONTROLS_CLOCK, | ||
| 511 | .recalc = &omap2_clksel_recalc, | ||
| 512 | }; | 493 | }; |
| 513 | 494 | ||
| 514 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 495 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| @@ -520,42 +501,34 @@ static const struct clksel div16_dpll3_clksel[] = { | |||
| 520 | /* This virtual clock is the source for dpll3_m3x2_ck */ | 501 | /* This virtual clock is the source for dpll3_m3x2_ck */ |
| 521 | static struct clk dpll3_m3_ck = { | 502 | static struct clk dpll3_m3_ck = { |
| 522 | .name = "dpll3_m3_ck", | 503 | .name = "dpll3_m3_ck", |
| 504 | .ops = &clkops_null, | ||
| 523 | .parent = &dpll3_ck, | 505 | .parent = &dpll3_ck, |
| 524 | .init = &omap2_init_clksel_parent, | 506 | .init = &omap2_init_clksel_parent, |
| 525 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 507 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 526 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | 508 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, |
| 527 | .clksel = div16_dpll3_clksel, | 509 | .clksel = div16_dpll3_clksel, |
| 528 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 510 | .clkdm_name = "dpll3_clkdm", |
| 529 | PARENT_CONTROLS_CLOCK, | ||
| 530 | .recalc = &omap2_clksel_recalc, | 511 | .recalc = &omap2_clksel_recalc, |
| 531 | }; | 512 | }; |
| 532 | 513 | ||
| 533 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 514 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 534 | static struct clk dpll3_m3x2_ck = { | 515 | static struct clk dpll3_m3x2_ck = { |
| 535 | .name = "dpll3_m3x2_ck", | 516 | .name = "dpll3_m3x2_ck", |
| 517 | .ops = &clkops_omap2_dflt_wait, | ||
| 536 | .parent = &dpll3_m3_ck, | 518 | .parent = &dpll3_m3_ck, |
| 537 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 519 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 538 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | 520 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, |
| 539 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 521 | .flags = INVERT_ENABLE, |
| 522 | .clkdm_name = "dpll3_clkdm", | ||
| 540 | .recalc = &omap3_clkoutx2_recalc, | 523 | .recalc = &omap3_clkoutx2_recalc, |
| 541 | }; | 524 | }; |
| 542 | 525 | ||
| 543 | static const struct clksel emu_core_alwon_ck_clksel[] = { | ||
| 544 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 545 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, | ||
| 546 | { .parent = NULL } | ||
| 547 | }; | ||
| 548 | |||
| 549 | static struct clk emu_core_alwon_ck = { | 526 | static struct clk emu_core_alwon_ck = { |
| 550 | .name = "emu_core_alwon_ck", | 527 | .name = "emu_core_alwon_ck", |
| 528 | .ops = &clkops_null, | ||
| 551 | .parent = &dpll3_m3x2_ck, | 529 | .parent = &dpll3_m3x2_ck, |
| 552 | .init = &omap2_init_clksel_parent, | 530 | .clkdm_name = "dpll3_clkdm", |
| 553 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 531 | .recalc = &followparent_recalc, |
| 554 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, | ||
| 555 | .clksel = emu_core_alwon_ck_clksel, | ||
| 556 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 557 | PARENT_CONTROLS_CLOCK, | ||
| 558 | .recalc = &omap2_clksel_recalc, | ||
| 559 | }; | 532 | }; |
| 560 | 533 | ||
| 561 | /* DPLL4 */ | 534 | /* DPLL4 */ |
| @@ -565,6 +538,9 @@ static struct dpll_data dpll4_dd = { | |||
| 565 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | 538 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 566 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | 539 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
| 567 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | 540 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
| 541 | .clk_bypass = &sys_ck, | ||
| 542 | .clk_ref = &sys_ck, | ||
| 543 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, | ||
| 568 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 544 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 569 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | 545 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, |
| 570 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | 546 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
| @@ -574,20 +550,21 @@ static struct dpll_data dpll4_dd = { | |||
| 574 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | 550 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 575 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | 551 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 576 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 552 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 577 | .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, | 553 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
| 578 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 554 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 555 | .min_divider = 1, | ||
| 579 | .max_divider = OMAP3_MAX_DPLL_DIV, | 556 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 580 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 557 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 581 | }; | 558 | }; |
| 582 | 559 | ||
| 583 | static struct clk dpll4_ck = { | 560 | static struct clk dpll4_ck = { |
| 584 | .name = "dpll4_ck", | 561 | .name = "dpll4_ck", |
| 562 | .ops = &clkops_noncore_dpll_ops, | ||
| 585 | .parent = &sys_ck, | 563 | .parent = &sys_ck, |
| 586 | .dpll_data = &dpll4_dd, | 564 | .dpll_data = &dpll4_dd, |
| 587 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 588 | .enable = &omap3_noncore_dpll_enable, | ||
| 589 | .disable = &omap3_noncore_dpll_disable, | ||
| 590 | .round_rate = &omap2_dpll_round_rate, | 565 | .round_rate = &omap2_dpll_round_rate, |
| 566 | .set_rate = &omap3_dpll4_set_rate, | ||
| 567 | .clkdm_name = "dpll4_clkdm", | ||
| 591 | .recalc = &omap3_dpll_recalc, | 568 | .recalc = &omap3_dpll_recalc, |
| 592 | }; | 569 | }; |
| 593 | 570 | ||
| @@ -598,9 +575,9 @@ static struct clk dpll4_ck = { | |||
| 598 | */ | 575 | */ |
| 599 | static struct clk dpll4_x2_ck = { | 576 | static struct clk dpll4_x2_ck = { |
| 600 | .name = "dpll4_x2_ck", | 577 | .name = "dpll4_x2_ck", |
| 578 | .ops = &clkops_null, | ||
| 601 | .parent = &dpll4_ck, | 579 | .parent = &dpll4_ck, |
| 602 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 580 | .clkdm_name = "dpll4_clkdm", |
| 603 | PARENT_CONTROLS_CLOCK, | ||
| 604 | .recalc = &omap3_clkoutx2_recalc, | 581 | .recalc = &omap3_clkoutx2_recalc, |
| 605 | }; | 582 | }; |
| 606 | 583 | ||
| @@ -612,112 +589,101 @@ static const struct clksel div16_dpll4_clksel[] = { | |||
| 612 | /* This virtual clock is the source for dpll4_m2x2_ck */ | 589 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
| 613 | static struct clk dpll4_m2_ck = { | 590 | static struct clk dpll4_m2_ck = { |
| 614 | .name = "dpll4_m2_ck", | 591 | .name = "dpll4_m2_ck", |
| 592 | .ops = &clkops_null, | ||
| 615 | .parent = &dpll4_ck, | 593 | .parent = &dpll4_ck, |
| 616 | .init = &omap2_init_clksel_parent, | 594 | .init = &omap2_init_clksel_parent, |
| 617 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | 595 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), |
| 618 | .clksel_mask = OMAP3430_DIV_96M_MASK, | 596 | .clksel_mask = OMAP3430_DIV_96M_MASK, |
| 619 | .clksel = div16_dpll4_clksel, | 597 | .clksel = div16_dpll4_clksel, |
| 620 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 598 | .clkdm_name = "dpll4_clkdm", |
| 621 | PARENT_CONTROLS_CLOCK, | ||
| 622 | .recalc = &omap2_clksel_recalc, | 599 | .recalc = &omap2_clksel_recalc, |
| 623 | }; | 600 | }; |
| 624 | 601 | ||
| 625 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 602 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 626 | static struct clk dpll4_m2x2_ck = { | 603 | static struct clk dpll4_m2x2_ck = { |
| 627 | .name = "dpll4_m2x2_ck", | 604 | .name = "dpll4_m2x2_ck", |
| 605 | .ops = &clkops_omap2_dflt_wait, | ||
| 628 | .parent = &dpll4_m2_ck, | 606 | .parent = &dpll4_m2_ck, |
| 629 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 607 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 630 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | 608 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, |
| 631 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 609 | .flags = INVERT_ENABLE, |
| 610 | .clkdm_name = "dpll4_clkdm", | ||
| 632 | .recalc = &omap3_clkoutx2_recalc, | 611 | .recalc = &omap3_clkoutx2_recalc, |
| 633 | }; | 612 | }; |
| 634 | 613 | ||
| 635 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | 614 | /* |
| 636 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 615 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as |
| 637 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | 616 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: |
| 638 | { .parent = NULL } | 617 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and |
| 639 | }; | 618 | * CM_96K_(F)CLK. |
| 640 | 619 | */ | |
| 641 | static struct clk omap_96m_alwon_fck = { | 620 | static struct clk omap_96m_alwon_fck = { |
| 642 | .name = "omap_96m_alwon_fck", | 621 | .name = "omap_96m_alwon_fck", |
| 622 | .ops = &clkops_null, | ||
| 643 | .parent = &dpll4_m2x2_ck, | 623 | .parent = &dpll4_m2x2_ck, |
| 644 | .init = &omap2_init_clksel_parent, | 624 | .recalc = &followparent_recalc, |
| 645 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 646 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 647 | .clksel = omap_96m_alwon_fck_clksel, | ||
| 648 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 649 | PARENT_CONTROLS_CLOCK, | ||
| 650 | .recalc = &omap2_clksel_recalc, | ||
| 651 | }; | 625 | }; |
| 652 | 626 | ||
| 653 | static struct clk omap_96m_fck = { | 627 | static struct clk cm_96m_fck = { |
| 654 | .name = "omap_96m_fck", | 628 | .name = "cm_96m_fck", |
| 629 | .ops = &clkops_null, | ||
| 655 | .parent = &omap_96m_alwon_fck, | 630 | .parent = &omap_96m_alwon_fck, |
| 656 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 657 | PARENT_CONTROLS_CLOCK, | ||
| 658 | .recalc = &followparent_recalc, | 631 | .recalc = &followparent_recalc, |
| 659 | }; | 632 | }; |
| 660 | 633 | ||
| 661 | static const struct clksel cm_96m_fck_clksel[] = { | 634 | static const struct clksel_rate omap_96m_dpll_rates[] = { |
| 662 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 635 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 663 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | 636 | { .div = 0 } |
| 637 | }; | ||
| 638 | |||
| 639 | static const struct clksel_rate omap_96m_sys_rates[] = { | ||
| 640 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 641 | { .div = 0 } | ||
| 642 | }; | ||
| 643 | |||
| 644 | static const struct clksel omap_96m_fck_clksel[] = { | ||
| 645 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | ||
| 646 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | ||
| 664 | { .parent = NULL } | 647 | { .parent = NULL } |
| 665 | }; | 648 | }; |
| 666 | 649 | ||
| 667 | static struct clk cm_96m_fck = { | 650 | static struct clk omap_96m_fck = { |
| 668 | .name = "cm_96m_fck", | 651 | .name = "omap_96m_fck", |
| 669 | .parent = &dpll4_m2x2_ck, | 652 | .ops = &clkops_null, |
| 653 | .parent = &sys_ck, | ||
| 670 | .init = &omap2_init_clksel_parent, | 654 | .init = &omap2_init_clksel_parent, |
| 671 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 655 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 672 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | 656 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, |
| 673 | .clksel = cm_96m_fck_clksel, | 657 | .clksel = omap_96m_fck_clksel, |
| 674 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 675 | PARENT_CONTROLS_CLOCK, | ||
| 676 | .recalc = &omap2_clksel_recalc, | 658 | .recalc = &omap2_clksel_recalc, |
| 677 | }; | 659 | }; |
| 678 | 660 | ||
| 679 | /* This virtual clock is the source for dpll4_m3x2_ck */ | 661 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
| 680 | static struct clk dpll4_m3_ck = { | 662 | static struct clk dpll4_m3_ck = { |
| 681 | .name = "dpll4_m3_ck", | 663 | .name = "dpll4_m3_ck", |
| 664 | .ops = &clkops_null, | ||
| 682 | .parent = &dpll4_ck, | 665 | .parent = &dpll4_ck, |
| 683 | .init = &omap2_init_clksel_parent, | 666 | .init = &omap2_init_clksel_parent, |
| 684 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | 667 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 685 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | 668 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, |
| 686 | .clksel = div16_dpll4_clksel, | 669 | .clksel = div16_dpll4_clksel, |
| 687 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 670 | .clkdm_name = "dpll4_clkdm", |
| 688 | PARENT_CONTROLS_CLOCK, | ||
| 689 | .recalc = &omap2_clksel_recalc, | 671 | .recalc = &omap2_clksel_recalc, |
| 690 | }; | 672 | }; |
| 691 | 673 | ||
| 692 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 674 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 693 | static struct clk dpll4_m3x2_ck = { | 675 | static struct clk dpll4_m3x2_ck = { |
| 694 | .name = "dpll4_m3x2_ck", | 676 | .name = "dpll4_m3x2_ck", |
| 677 | .ops = &clkops_omap2_dflt_wait, | ||
| 695 | .parent = &dpll4_m3_ck, | 678 | .parent = &dpll4_m3_ck, |
| 696 | .init = &omap2_init_clksel_parent, | 679 | .init = &omap2_init_clksel_parent, |
| 697 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 680 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 698 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | 681 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, |
| 699 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 682 | .flags = INVERT_ENABLE, |
| 683 | .clkdm_name = "dpll4_clkdm", | ||
| 700 | .recalc = &omap3_clkoutx2_recalc, | 684 | .recalc = &omap3_clkoutx2_recalc, |
| 701 | }; | 685 | }; |
| 702 | 686 | ||
| 703 | static const struct clksel virt_omap_54m_fck_clksel[] = { | ||
| 704 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 705 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, | ||
| 706 | { .parent = NULL } | ||
| 707 | }; | ||
| 708 | |||
| 709 | static struct clk virt_omap_54m_fck = { | ||
| 710 | .name = "virt_omap_54m_fck", | ||
| 711 | .parent = &dpll4_m3x2_ck, | ||
| 712 | .init = &omap2_init_clksel_parent, | ||
| 713 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 714 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 715 | .clksel = virt_omap_54m_fck_clksel, | ||
| 716 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 717 | PARENT_CONTROLS_CLOCK, | ||
| 718 | .recalc = &omap2_clksel_recalc, | ||
| 719 | }; | ||
| 720 | |||
| 721 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | 687 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
| 722 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | 688 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 723 | { .div = 0 } | 689 | { .div = 0 } |
| @@ -729,23 +695,22 @@ static const struct clksel_rate omap_54m_alt_rates[] = { | |||
| 729 | }; | 695 | }; |
| 730 | 696 | ||
| 731 | static const struct clksel omap_54m_clksel[] = { | 697 | static const struct clksel omap_54m_clksel[] = { |
| 732 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, | 698 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, |
| 733 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, | 699 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
| 734 | { .parent = NULL } | 700 | { .parent = NULL } |
| 735 | }; | 701 | }; |
| 736 | 702 | ||
| 737 | static struct clk omap_54m_fck = { | 703 | static struct clk omap_54m_fck = { |
| 738 | .name = "omap_54m_fck", | 704 | .name = "omap_54m_fck", |
| 705 | .ops = &clkops_null, | ||
| 739 | .init = &omap2_init_clksel_parent, | 706 | .init = &omap2_init_clksel_parent, |
| 740 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 707 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 741 | .clksel_mask = OMAP3430_SOURCE_54M, | 708 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, |
| 742 | .clksel = omap_54m_clksel, | 709 | .clksel = omap_54m_clksel, |
| 743 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 744 | PARENT_CONTROLS_CLOCK, | ||
| 745 | .recalc = &omap2_clksel_recalc, | 710 | .recalc = &omap2_clksel_recalc, |
| 746 | }; | 711 | }; |
| 747 | 712 | ||
| 748 | static const struct clksel_rate omap_48m_96md2_rates[] = { | 713 | static const struct clksel_rate omap_48m_cm96m_rates[] = { |
| 749 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | 714 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 750 | { .div = 0 } | 715 | { .div = 0 } |
| 751 | }; | 716 | }; |
| @@ -756,106 +721,112 @@ static const struct clksel_rate omap_48m_alt_rates[] = { | |||
| 756 | }; | 721 | }; |
| 757 | 722 | ||
| 758 | static const struct clksel omap_48m_clksel[] = { | 723 | static const struct clksel omap_48m_clksel[] = { |
| 759 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, | 724 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, |
| 760 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | 725 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, |
| 761 | { .parent = NULL } | 726 | { .parent = NULL } |
| 762 | }; | 727 | }; |
| 763 | 728 | ||
| 764 | static struct clk omap_48m_fck = { | 729 | static struct clk omap_48m_fck = { |
| 765 | .name = "omap_48m_fck", | 730 | .name = "omap_48m_fck", |
| 731 | .ops = &clkops_null, | ||
| 766 | .init = &omap2_init_clksel_parent, | 732 | .init = &omap2_init_clksel_parent, |
| 767 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 733 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 768 | .clksel_mask = OMAP3430_SOURCE_48M, | 734 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, |
| 769 | .clksel = omap_48m_clksel, | 735 | .clksel = omap_48m_clksel, |
| 770 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 771 | PARENT_CONTROLS_CLOCK, | ||
| 772 | .recalc = &omap2_clksel_recalc, | 736 | .recalc = &omap2_clksel_recalc, |
| 773 | }; | 737 | }; |
| 774 | 738 | ||
| 775 | static struct clk omap_12m_fck = { | 739 | static struct clk omap_12m_fck = { |
| 776 | .name = "omap_12m_fck", | 740 | .name = "omap_12m_fck", |
| 741 | .ops = &clkops_null, | ||
| 777 | .parent = &omap_48m_fck, | 742 | .parent = &omap_48m_fck, |
| 778 | .fixed_div = 4, | 743 | .fixed_div = 4, |
| 779 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 780 | PARENT_CONTROLS_CLOCK, | ||
| 781 | .recalc = &omap2_fixed_divisor_recalc, | 744 | .recalc = &omap2_fixed_divisor_recalc, |
| 782 | }; | 745 | }; |
| 783 | 746 | ||
| 784 | /* This virstual clock is the source for dpll4_m4x2_ck */ | 747 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
| 785 | static struct clk dpll4_m4_ck = { | 748 | static struct clk dpll4_m4_ck = { |
| 786 | .name = "dpll4_m4_ck", | 749 | .name = "dpll4_m4_ck", |
| 750 | .ops = &clkops_null, | ||
| 787 | .parent = &dpll4_ck, | 751 | .parent = &dpll4_ck, |
| 788 | .init = &omap2_init_clksel_parent, | 752 | .init = &omap2_init_clksel_parent, |
| 789 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | 753 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 790 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | 754 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, |
| 791 | .clksel = div16_dpll4_clksel, | 755 | .clksel = div16_dpll4_clksel, |
| 792 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 756 | .clkdm_name = "dpll4_clkdm", |
| 793 | PARENT_CONTROLS_CLOCK, | ||
| 794 | .recalc = &omap2_clksel_recalc, | 757 | .recalc = &omap2_clksel_recalc, |
| 758 | .set_rate = &omap2_clksel_set_rate, | ||
| 759 | .round_rate = &omap2_clksel_round_rate, | ||
| 795 | }; | 760 | }; |
| 796 | 761 | ||
| 797 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 762 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 798 | static struct clk dpll4_m4x2_ck = { | 763 | static struct clk dpll4_m4x2_ck = { |
| 799 | .name = "dpll4_m4x2_ck", | 764 | .name = "dpll4_m4x2_ck", |
| 765 | .ops = &clkops_omap2_dflt_wait, | ||
| 800 | .parent = &dpll4_m4_ck, | 766 | .parent = &dpll4_m4_ck, |
| 801 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 767 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 802 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | 768 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
| 803 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 769 | .flags = INVERT_ENABLE, |
| 770 | .clkdm_name = "dpll4_clkdm", | ||
| 804 | .recalc = &omap3_clkoutx2_recalc, | 771 | .recalc = &omap3_clkoutx2_recalc, |
| 805 | }; | 772 | }; |
| 806 | 773 | ||
| 807 | /* This virtual clock is the source for dpll4_m5x2_ck */ | 774 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
| 808 | static struct clk dpll4_m5_ck = { | 775 | static struct clk dpll4_m5_ck = { |
| 809 | .name = "dpll4_m5_ck", | 776 | .name = "dpll4_m5_ck", |
| 777 | .ops = &clkops_null, | ||
| 810 | .parent = &dpll4_ck, | 778 | .parent = &dpll4_ck, |
| 811 | .init = &omap2_init_clksel_parent, | 779 | .init = &omap2_init_clksel_parent, |
| 812 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | 780 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), |
| 813 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | 781 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, |
| 814 | .clksel = div16_dpll4_clksel, | 782 | .clksel = div16_dpll4_clksel, |
| 815 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 783 | .clkdm_name = "dpll4_clkdm", |
| 816 | PARENT_CONTROLS_CLOCK, | ||
| 817 | .recalc = &omap2_clksel_recalc, | 784 | .recalc = &omap2_clksel_recalc, |
| 818 | }; | 785 | }; |
| 819 | 786 | ||
| 820 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 787 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 821 | static struct clk dpll4_m5x2_ck = { | 788 | static struct clk dpll4_m5x2_ck = { |
| 822 | .name = "dpll4_m5x2_ck", | 789 | .name = "dpll4_m5x2_ck", |
| 790 | .ops = &clkops_omap2_dflt_wait, | ||
| 823 | .parent = &dpll4_m5_ck, | 791 | .parent = &dpll4_m5_ck, |
| 824 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 792 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 825 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | 793 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
| 826 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 794 | .flags = INVERT_ENABLE, |
| 795 | .clkdm_name = "dpll4_clkdm", | ||
| 827 | .recalc = &omap3_clkoutx2_recalc, | 796 | .recalc = &omap3_clkoutx2_recalc, |
| 828 | }; | 797 | }; |
| 829 | 798 | ||
| 830 | /* This virtual clock is the source for dpll4_m6x2_ck */ | 799 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
| 831 | static struct clk dpll4_m6_ck = { | 800 | static struct clk dpll4_m6_ck = { |
| 832 | .name = "dpll4_m6_ck", | 801 | .name = "dpll4_m6_ck", |
| 802 | .ops = &clkops_null, | ||
| 833 | .parent = &dpll4_ck, | 803 | .parent = &dpll4_ck, |
| 834 | .init = &omap2_init_clksel_parent, | 804 | .init = &omap2_init_clksel_parent, |
| 835 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 805 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 836 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | 806 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, |
| 837 | .clksel = div16_dpll4_clksel, | 807 | .clksel = div16_dpll4_clksel, |
| 838 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 808 | .clkdm_name = "dpll4_clkdm", |
| 839 | PARENT_CONTROLS_CLOCK, | ||
| 840 | .recalc = &omap2_clksel_recalc, | 809 | .recalc = &omap2_clksel_recalc, |
| 841 | }; | 810 | }; |
| 842 | 811 | ||
| 843 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 812 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 844 | static struct clk dpll4_m6x2_ck = { | 813 | static struct clk dpll4_m6x2_ck = { |
| 845 | .name = "dpll4_m6x2_ck", | 814 | .name = "dpll4_m6x2_ck", |
| 815 | .ops = &clkops_omap2_dflt_wait, | ||
| 846 | .parent = &dpll4_m6_ck, | 816 | .parent = &dpll4_m6_ck, |
| 847 | .init = &omap2_init_clksel_parent, | 817 | .init = &omap2_init_clksel_parent, |
| 848 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 818 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 849 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | 819 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, |
| 850 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 820 | .flags = INVERT_ENABLE, |
| 821 | .clkdm_name = "dpll4_clkdm", | ||
| 851 | .recalc = &omap3_clkoutx2_recalc, | 822 | .recalc = &omap3_clkoutx2_recalc, |
| 852 | }; | 823 | }; |
| 853 | 824 | ||
| 854 | static struct clk emu_per_alwon_ck = { | 825 | static struct clk emu_per_alwon_ck = { |
| 855 | .name = "emu_per_alwon_ck", | 826 | .name = "emu_per_alwon_ck", |
| 827 | .ops = &clkops_null, | ||
| 856 | .parent = &dpll4_m6x2_ck, | 828 | .parent = &dpll4_m6x2_ck, |
| 857 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 829 | .clkdm_name = "dpll4_clkdm", |
| 858 | PARENT_CONTROLS_CLOCK, | ||
| 859 | .recalc = &followparent_recalc, | 830 | .recalc = &followparent_recalc, |
| 860 | }; | 831 | }; |
| 861 | 832 | ||
| @@ -867,6 +838,9 @@ static struct dpll_data dpll5_dd = { | |||
| 867 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | 838 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
| 868 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | 839 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, |
| 869 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | 840 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, |
| 841 | .clk_bypass = &sys_ck, | ||
| 842 | .clk_ref = &sys_ck, | ||
| 843 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, | ||
| 870 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | 844 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), |
| 871 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | 845 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, |
| 872 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | 846 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
| @@ -876,20 +850,21 @@ static struct dpll_data dpll5_dd = { | |||
| 876 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), | 850 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
| 877 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | 851 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, |
| 878 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | 852 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 879 | .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, | 853 | .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
| 880 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 854 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 855 | .min_divider = 1, | ||
| 881 | .max_divider = OMAP3_MAX_DPLL_DIV, | 856 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 882 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 857 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 883 | }; | 858 | }; |
| 884 | 859 | ||
| 885 | static struct clk dpll5_ck = { | 860 | static struct clk dpll5_ck = { |
| 886 | .name = "dpll5_ck", | 861 | .name = "dpll5_ck", |
| 862 | .ops = &clkops_noncore_dpll_ops, | ||
| 887 | .parent = &sys_ck, | 863 | .parent = &sys_ck, |
| 888 | .dpll_data = &dpll5_dd, | 864 | .dpll_data = &dpll5_dd, |
| 889 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, | ||
| 890 | .enable = &omap3_noncore_dpll_enable, | ||
| 891 | .disable = &omap3_noncore_dpll_disable, | ||
| 892 | .round_rate = &omap2_dpll_round_rate, | 865 | .round_rate = &omap2_dpll_round_rate, |
| 866 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
| 867 | .clkdm_name = "dpll5_clkdm", | ||
| 893 | .recalc = &omap3_dpll_recalc, | 868 | .recalc = &omap3_dpll_recalc, |
| 894 | }; | 869 | }; |
| 895 | 870 | ||
| @@ -900,31 +875,13 @@ static const struct clksel div16_dpll5_clksel[] = { | |||
| 900 | 875 | ||
| 901 | static struct clk dpll5_m2_ck = { | 876 | static struct clk dpll5_m2_ck = { |
| 902 | .name = "dpll5_m2_ck", | 877 | .name = "dpll5_m2_ck", |
| 878 | .ops = &clkops_null, | ||
| 903 | .parent = &dpll5_ck, | 879 | .parent = &dpll5_ck, |
| 904 | .init = &omap2_init_clksel_parent, | 880 | .init = &omap2_init_clksel_parent, |
| 905 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | 881 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), |
| 906 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | 882 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, |
| 907 | .clksel = div16_dpll5_clksel, | 883 | .clksel = div16_dpll5_clksel, |
| 908 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | 884 | .clkdm_name = "dpll5_clkdm", |
| 909 | PARENT_CONTROLS_CLOCK, | ||
| 910 | .recalc = &omap2_clksel_recalc, | ||
| 911 | }; | ||
| 912 | |||
| 913 | static const struct clksel omap_120m_fck_clksel[] = { | ||
| 914 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 915 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, | ||
| 916 | { .parent = NULL } | ||
| 917 | }; | ||
| 918 | |||
| 919 | static struct clk omap_120m_fck = { | ||
| 920 | .name = "omap_120m_fck", | ||
| 921 | .parent = &dpll5_m2_ck, | ||
| 922 | .init = &omap2_init_clksel_parent, | ||
| 923 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | ||
| 924 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | ||
| 925 | .clksel = omap_120m_fck_clksel, | ||
| 926 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | ||
| 927 | PARENT_CONTROLS_CLOCK, | ||
| 928 | .recalc = &omap2_clksel_recalc, | 885 | .recalc = &omap2_clksel_recalc, |
| 929 | }; | 886 | }; |
| 930 | 887 | ||
| @@ -951,22 +908,23 @@ static const struct clksel_rate clkout2_src_54m_rates[] = { | |||
| 951 | }; | 908 | }; |
| 952 | 909 | ||
| 953 | static const struct clksel clkout2_src_clksel[] = { | 910 | static const struct clksel clkout2_src_clksel[] = { |
| 954 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | 911 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, |
| 955 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | 912 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, |
| 956 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, | 913 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, |
| 957 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | 914 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, |
| 958 | { .parent = NULL } | 915 | { .parent = NULL } |
| 959 | }; | 916 | }; |
| 960 | 917 | ||
| 961 | static struct clk clkout2_src_ck = { | 918 | static struct clk clkout2_src_ck = { |
| 962 | .name = "clkout2_src_ck", | 919 | .name = "clkout2_src_ck", |
| 920 | .ops = &clkops_omap2_dflt, | ||
| 963 | .init = &omap2_init_clksel_parent, | 921 | .init = &omap2_init_clksel_parent, |
| 964 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | 922 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 965 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | 923 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, |
| 966 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | 924 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 967 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | 925 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, |
| 968 | .clksel = clkout2_src_clksel, | 926 | .clksel = clkout2_src_clksel, |
| 969 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | 927 | .clkdm_name = "core_clkdm", |
| 970 | .recalc = &omap2_clksel_recalc, | 928 | .recalc = &omap2_clksel_recalc, |
| 971 | }; | 929 | }; |
| 972 | 930 | ||
| @@ -986,11 +944,11 @@ static const struct clksel sys_clkout2_clksel[] = { | |||
| 986 | 944 | ||
| 987 | static struct clk sys_clkout2 = { | 945 | static struct clk sys_clkout2 = { |
| 988 | .name = "sys_clkout2", | 946 | .name = "sys_clkout2", |
| 947 | .ops = &clkops_null, | ||
| 989 | .init = &omap2_init_clksel_parent, | 948 | .init = &omap2_init_clksel_parent, |
| 990 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | 949 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 991 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | 950 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, |
| 992 | .clksel = sys_clkout2_clksel, | 951 | .clksel = sys_clkout2_clksel, |
| 993 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 994 | .recalc = &omap2_clksel_recalc, | 952 | .recalc = &omap2_clksel_recalc, |
| 995 | }; | 953 | }; |
| 996 | 954 | ||
| @@ -998,16 +956,22 @@ static struct clk sys_clkout2 = { | |||
| 998 | 956 | ||
| 999 | static struct clk corex2_fck = { | 957 | static struct clk corex2_fck = { |
| 1000 | .name = "corex2_fck", | 958 | .name = "corex2_fck", |
| 959 | .ops = &clkops_null, | ||
| 1001 | .parent = &dpll3_m2x2_ck, | 960 | .parent = &dpll3_m2x2_ck, |
| 1002 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1003 | PARENT_CONTROLS_CLOCK, | ||
| 1004 | .recalc = &followparent_recalc, | 961 | .recalc = &followparent_recalc, |
| 1005 | }; | 962 | }; |
| 1006 | 963 | ||
| 1007 | /* DPLL power domain clock controls */ | 964 | /* DPLL power domain clock controls */ |
| 1008 | 965 | ||
| 1009 | static const struct clksel div2_core_clksel[] = { | 966 | static const struct clksel_rate div4_rates[] = { |
| 1010 | { .parent = &core_ck, .rates = div2_rates }, | 967 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 968 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 969 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
| 970 | { .div = 0 } | ||
| 971 | }; | ||
| 972 | |||
| 973 | static const struct clksel div4_core_clksel[] = { | ||
| 974 | { .parent = &core_ck, .rates = div4_rates }, | ||
| 1011 | { .parent = NULL } | 975 | { .parent = NULL } |
| 1012 | }; | 976 | }; |
| 1013 | 977 | ||
| @@ -1017,39 +981,21 @@ static const struct clksel div2_core_clksel[] = { | |||
| 1017 | */ | 981 | */ |
| 1018 | static struct clk dpll1_fck = { | 982 | static struct clk dpll1_fck = { |
| 1019 | .name = "dpll1_fck", | 983 | .name = "dpll1_fck", |
| 984 | .ops = &clkops_null, | ||
| 1020 | .parent = &core_ck, | 985 | .parent = &core_ck, |
| 1021 | .init = &omap2_init_clksel_parent, | 986 | .init = &omap2_init_clksel_parent, |
| 1022 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | 987 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1023 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | 988 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, |
| 1024 | .clksel = div2_core_clksel, | 989 | .clksel = div4_core_clksel, |
| 1025 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1026 | PARENT_CONTROLS_CLOCK, | ||
| 1027 | .recalc = &omap2_clksel_recalc, | 990 | .recalc = &omap2_clksel_recalc, |
| 1028 | }; | 991 | }; |
| 1029 | 992 | ||
| 1030 | /* | ||
| 1031 | * MPU clksel: | ||
| 1032 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck | ||
| 1033 | * derives from the high-frequency bypass clock originating from DPLL3, | ||
| 1034 | * called 'dpll1_fck' | ||
| 1035 | */ | ||
| 1036 | static const struct clksel mpu_clksel[] = { | ||
| 1037 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, | ||
| 1038 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, | ||
| 1039 | { .parent = NULL } | ||
| 1040 | }; | ||
| 1041 | |||
| 1042 | static struct clk mpu_ck = { | 993 | static struct clk mpu_ck = { |
| 1043 | .name = "mpu_ck", | 994 | .name = "mpu_ck", |
| 995 | .ops = &clkops_null, | ||
| 1044 | .parent = &dpll1_x2m2_ck, | 996 | .parent = &dpll1_x2m2_ck, |
| 1045 | .init = &omap2_init_clksel_parent, | ||
| 1046 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
| 1047 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
| 1048 | .clksel = mpu_clksel, | ||
| 1049 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1050 | PARENT_CONTROLS_CLOCK, | ||
| 1051 | .clkdm_name = "mpu_clkdm", | 997 | .clkdm_name = "mpu_clkdm", |
| 1052 | .recalc = &omap2_clksel_recalc, | 998 | .recalc = &followparent_recalc, |
| 1053 | }; | 999 | }; |
| 1054 | 1000 | ||
| 1055 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | 1001 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ |
| @@ -1066,13 +1012,12 @@ static const struct clksel arm_fck_clksel[] = { | |||
| 1066 | 1012 | ||
| 1067 | static struct clk arm_fck = { | 1013 | static struct clk arm_fck = { |
| 1068 | .name = "arm_fck", | 1014 | .name = "arm_fck", |
| 1015 | .ops = &clkops_null, | ||
| 1069 | .parent = &mpu_ck, | 1016 | .parent = &mpu_ck, |
| 1070 | .init = &omap2_init_clksel_parent, | 1017 | .init = &omap2_init_clksel_parent, |
| 1071 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | 1018 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1072 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | 1019 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1073 | .clksel = arm_fck_clksel, | 1020 | .clksel = arm_fck_clksel, |
| 1074 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1075 | PARENT_CONTROLS_CLOCK, | ||
| 1076 | .recalc = &omap2_clksel_recalc, | 1021 | .recalc = &omap2_clksel_recalc, |
| 1077 | }; | 1022 | }; |
| 1078 | 1023 | ||
| @@ -1084,63 +1029,48 @@ static struct clk arm_fck = { | |||
| 1084 | */ | 1029 | */ |
| 1085 | static struct clk emu_mpu_alwon_ck = { | 1030 | static struct clk emu_mpu_alwon_ck = { |
| 1086 | .name = "emu_mpu_alwon_ck", | 1031 | .name = "emu_mpu_alwon_ck", |
| 1032 | .ops = &clkops_null, | ||
| 1087 | .parent = &mpu_ck, | 1033 | .parent = &mpu_ck, |
| 1088 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1089 | PARENT_CONTROLS_CLOCK, | ||
| 1090 | .recalc = &followparent_recalc, | 1034 | .recalc = &followparent_recalc, |
| 1091 | }; | 1035 | }; |
| 1092 | 1036 | ||
| 1093 | static struct clk dpll2_fck = { | 1037 | static struct clk dpll2_fck = { |
| 1094 | .name = "dpll2_fck", | 1038 | .name = "dpll2_fck", |
| 1039 | .ops = &clkops_null, | ||
| 1095 | .parent = &core_ck, | 1040 | .parent = &core_ck, |
| 1096 | .init = &omap2_init_clksel_parent, | 1041 | .init = &omap2_init_clksel_parent, |
| 1097 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | 1042 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1098 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | 1043 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, |
| 1099 | .clksel = div2_core_clksel, | 1044 | .clksel = div4_core_clksel, |
| 1100 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1101 | PARENT_CONTROLS_CLOCK, | ||
| 1102 | .recalc = &omap2_clksel_recalc, | 1045 | .recalc = &omap2_clksel_recalc, |
| 1103 | }; | 1046 | }; |
| 1104 | 1047 | ||
| 1105 | /* | ||
| 1106 | * IVA2 clksel: | ||
| 1107 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck | ||
| 1108 | * derives from the high-frequency bypass clock originating from DPLL3, | ||
| 1109 | * called 'dpll2_fck' | ||
| 1110 | */ | ||
| 1111 | |||
| 1112 | static const struct clksel iva2_clksel[] = { | ||
| 1113 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, | ||
| 1114 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, | ||
| 1115 | { .parent = NULL } | ||
| 1116 | }; | ||
| 1117 | |||
| 1118 | static struct clk iva2_ck = { | 1048 | static struct clk iva2_ck = { |
| 1119 | .name = "iva2_ck", | 1049 | .name = "iva2_ck", |
| 1050 | .ops = &clkops_omap2_dflt_wait, | ||
| 1120 | .parent = &dpll2_m2_ck, | 1051 | .parent = &dpll2_m2_ck, |
| 1121 | .init = &omap2_init_clksel_parent, | 1052 | .init = &omap2_init_clksel_parent, |
| 1122 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), | 1053 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
| 1123 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | 1054 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
| 1124 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
| 1125 | OMAP3430_CM_IDLEST_PLL), | ||
| 1126 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, | ||
| 1127 | .clksel = iva2_clksel, | ||
| 1128 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 1129 | .clkdm_name = "iva2_clkdm", | 1055 | .clkdm_name = "iva2_clkdm", |
| 1130 | .recalc = &omap2_clksel_recalc, | 1056 | .recalc = &followparent_recalc, |
| 1131 | }; | 1057 | }; |
| 1132 | 1058 | ||
| 1133 | /* Common interface clocks */ | 1059 | /* Common interface clocks */ |
| 1134 | 1060 | ||
| 1061 | static const struct clksel div2_core_clksel[] = { | ||
| 1062 | { .parent = &core_ck, .rates = div2_rates }, | ||
| 1063 | { .parent = NULL } | ||
| 1064 | }; | ||
| 1065 | |||
| 1135 | static struct clk l3_ick = { | 1066 | static struct clk l3_ick = { |
| 1136 | .name = "l3_ick", | 1067 | .name = "l3_ick", |
| 1068 | .ops = &clkops_null, | ||
| 1137 | .parent = &core_ck, | 1069 | .parent = &core_ck, |
| 1138 | .init = &omap2_init_clksel_parent, | 1070 | .init = &omap2_init_clksel_parent, |
| 1139 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1071 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1140 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | 1072 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, |
| 1141 | .clksel = div2_core_clksel, | 1073 | .clksel = div2_core_clksel, |
| 1142 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1143 | PARENT_CONTROLS_CLOCK, | ||
| 1144 | .clkdm_name = "core_l3_clkdm", | 1074 | .clkdm_name = "core_l3_clkdm", |
| 1145 | .recalc = &omap2_clksel_recalc, | 1075 | .recalc = &omap2_clksel_recalc, |
| 1146 | }; | 1076 | }; |
| @@ -1152,13 +1082,12 @@ static const struct clksel div2_l3_clksel[] = { | |||
| 1152 | 1082 | ||
| 1153 | static struct clk l4_ick = { | 1083 | static struct clk l4_ick = { |
| 1154 | .name = "l4_ick", | 1084 | .name = "l4_ick", |
| 1085 | .ops = &clkops_null, | ||
| 1155 | .parent = &l3_ick, | 1086 | .parent = &l3_ick, |
| 1156 | .init = &omap2_init_clksel_parent, | 1087 | .init = &omap2_init_clksel_parent, |
| 1157 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1088 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1158 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | 1089 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, |
| 1159 | .clksel = div2_l3_clksel, | 1090 | .clksel = div2_l3_clksel, |
| 1160 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1161 | PARENT_CONTROLS_CLOCK, | ||
| 1162 | .clkdm_name = "core_l4_clkdm", | 1091 | .clkdm_name = "core_l4_clkdm", |
| 1163 | .recalc = &omap2_clksel_recalc, | 1092 | .recalc = &omap2_clksel_recalc, |
| 1164 | 1093 | ||
| @@ -1171,12 +1100,12 @@ static const struct clksel div2_l4_clksel[] = { | |||
| 1171 | 1100 | ||
| 1172 | static struct clk rm_ick = { | 1101 | static struct clk rm_ick = { |
| 1173 | .name = "rm_ick", | 1102 | .name = "rm_ick", |
| 1103 | .ops = &clkops_null, | ||
| 1174 | .parent = &l4_ick, | 1104 | .parent = &l4_ick, |
| 1175 | .init = &omap2_init_clksel_parent, | 1105 | .init = &omap2_init_clksel_parent, |
| 1176 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | 1106 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 1177 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | 1107 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, |
| 1178 | .clksel = div2_l4_clksel, | 1108 | .clksel = div2_l4_clksel, |
| 1179 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 1180 | .recalc = &omap2_clksel_recalc, | 1109 | .recalc = &omap2_clksel_recalc, |
| 1181 | }; | 1110 | }; |
| 1182 | 1111 | ||
| @@ -1192,53 +1121,52 @@ static const struct clksel gfx_l3_clksel[] = { | |||
| 1192 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ | 1121 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ |
| 1193 | static struct clk gfx_l3_ck = { | 1122 | static struct clk gfx_l3_ck = { |
| 1194 | .name = "gfx_l3_ck", | 1123 | .name = "gfx_l3_ck", |
| 1124 | .ops = &clkops_omap2_dflt_wait, | ||
| 1195 | .parent = &l3_ick, | 1125 | .parent = &l3_ick, |
| 1196 | .init = &omap2_init_clksel_parent, | 1126 | .init = &omap2_init_clksel_parent, |
| 1197 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | 1127 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1198 | .enable_bit = OMAP_EN_GFX_SHIFT, | 1128 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| 1199 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1200 | .recalc = &followparent_recalc, | 1129 | .recalc = &followparent_recalc, |
| 1201 | }; | 1130 | }; |
| 1202 | 1131 | ||
| 1203 | static struct clk gfx_l3_fck = { | 1132 | static struct clk gfx_l3_fck = { |
| 1204 | .name = "gfx_l3_fck", | 1133 | .name = "gfx_l3_fck", |
| 1134 | .ops = &clkops_null, | ||
| 1205 | .parent = &gfx_l3_ck, | 1135 | .parent = &gfx_l3_ck, |
| 1206 | .init = &omap2_init_clksel_parent, | 1136 | .init = &omap2_init_clksel_parent, |
| 1207 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | 1137 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1208 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | 1138 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1209 | .clksel = gfx_l3_clksel, | 1139 | .clksel = gfx_l3_clksel, |
| 1210 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES | | ||
| 1211 | PARENT_CONTROLS_CLOCK, | ||
| 1212 | .clkdm_name = "gfx_3430es1_clkdm", | 1140 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1213 | .recalc = &omap2_clksel_recalc, | 1141 | .recalc = &omap2_clksel_recalc, |
| 1214 | }; | 1142 | }; |
| 1215 | 1143 | ||
| 1216 | static struct clk gfx_l3_ick = { | 1144 | static struct clk gfx_l3_ick = { |
| 1217 | .name = "gfx_l3_ick", | 1145 | .name = "gfx_l3_ick", |
| 1146 | .ops = &clkops_null, | ||
| 1218 | .parent = &gfx_l3_ck, | 1147 | .parent = &gfx_l3_ck, |
| 1219 | .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, | ||
| 1220 | .clkdm_name = "gfx_3430es1_clkdm", | 1148 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1221 | .recalc = &followparent_recalc, | 1149 | .recalc = &followparent_recalc, |
| 1222 | }; | 1150 | }; |
| 1223 | 1151 | ||
| 1224 | static struct clk gfx_cg1_ck = { | 1152 | static struct clk gfx_cg1_ck = { |
| 1225 | .name = "gfx_cg1_ck", | 1153 | .name = "gfx_cg1_ck", |
| 1154 | .ops = &clkops_omap2_dflt_wait, | ||
| 1226 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1155 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
| 1227 | .init = &omap2_init_clk_clkdm, | 1156 | .init = &omap2_init_clk_clkdm, |
| 1228 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1157 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1229 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | 1158 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
| 1230 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1231 | .clkdm_name = "gfx_3430es1_clkdm", | 1159 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1232 | .recalc = &followparent_recalc, | 1160 | .recalc = &followparent_recalc, |
| 1233 | }; | 1161 | }; |
| 1234 | 1162 | ||
| 1235 | static struct clk gfx_cg2_ck = { | 1163 | static struct clk gfx_cg2_ck = { |
| 1236 | .name = "gfx_cg2_ck", | 1164 | .name = "gfx_cg2_ck", |
| 1165 | .ops = &clkops_omap2_dflt_wait, | ||
| 1237 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1166 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
| 1238 | .init = &omap2_init_clk_clkdm, | 1167 | .init = &omap2_init_clk_clkdm, |
| 1239 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1168 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1240 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | 1169 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
| 1241 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1242 | .clkdm_name = "gfx_3430es1_clkdm", | 1170 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1243 | .recalc = &followparent_recalc, | 1171 | .recalc = &followparent_recalc, |
| 1244 | }; | 1172 | }; |
| @@ -1265,24 +1193,24 @@ static const struct clksel sgx_clksel[] = { | |||
| 1265 | 1193 | ||
| 1266 | static struct clk sgx_fck = { | 1194 | static struct clk sgx_fck = { |
| 1267 | .name = "sgx_fck", | 1195 | .name = "sgx_fck", |
| 1196 | .ops = &clkops_omap2_dflt_wait, | ||
| 1268 | .init = &omap2_init_clksel_parent, | 1197 | .init = &omap2_init_clksel_parent, |
| 1269 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | 1198 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), |
| 1270 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | 1199 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, |
| 1271 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | 1200 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), |
| 1272 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | 1201 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, |
| 1273 | .clksel = sgx_clksel, | 1202 | .clksel = sgx_clksel, |
| 1274 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1275 | .clkdm_name = "sgx_clkdm", | 1203 | .clkdm_name = "sgx_clkdm", |
| 1276 | .recalc = &omap2_clksel_recalc, | 1204 | .recalc = &omap2_clksel_recalc, |
| 1277 | }; | 1205 | }; |
| 1278 | 1206 | ||
| 1279 | static struct clk sgx_ick = { | 1207 | static struct clk sgx_ick = { |
| 1280 | .name = "sgx_ick", | 1208 | .name = "sgx_ick", |
| 1209 | .ops = &clkops_omap2_dflt_wait, | ||
| 1281 | .parent = &l3_ick, | 1210 | .parent = &l3_ick, |
| 1282 | .init = &omap2_init_clk_clkdm, | 1211 | .init = &omap2_init_clk_clkdm, |
| 1283 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | 1212 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
| 1284 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | 1213 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, |
| 1285 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1286 | .clkdm_name = "sgx_clkdm", | 1214 | .clkdm_name = "sgx_clkdm", |
| 1287 | .recalc = &followparent_recalc, | 1215 | .recalc = &followparent_recalc, |
| 1288 | }; | 1216 | }; |
| @@ -1291,11 +1219,11 @@ static struct clk sgx_ick = { | |||
| 1291 | 1219 | ||
| 1292 | static struct clk d2d_26m_fck = { | 1220 | static struct clk d2d_26m_fck = { |
| 1293 | .name = "d2d_26m_fck", | 1221 | .name = "d2d_26m_fck", |
| 1222 | .ops = &clkops_omap2_dflt_wait, | ||
| 1294 | .parent = &sys_ck, | 1223 | .parent = &sys_ck, |
| 1295 | .init = &omap2_init_clk_clkdm, | 1224 | .init = &omap2_init_clk_clkdm, |
| 1296 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1225 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1297 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | 1226 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
| 1298 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1299 | .clkdm_name = "d2d_clkdm", | 1227 | .clkdm_name = "d2d_clkdm", |
| 1300 | .recalc = &followparent_recalc, | 1228 | .recalc = &followparent_recalc, |
| 1301 | }; | 1229 | }; |
| @@ -1308,6 +1236,7 @@ static const struct clksel omap343x_gpt_clksel[] = { | |||
| 1308 | 1236 | ||
| 1309 | static struct clk gpt10_fck = { | 1237 | static struct clk gpt10_fck = { |
| 1310 | .name = "gpt10_fck", | 1238 | .name = "gpt10_fck", |
| 1239 | .ops = &clkops_omap2_dflt_wait, | ||
| 1311 | .parent = &sys_ck, | 1240 | .parent = &sys_ck, |
| 1312 | .init = &omap2_init_clksel_parent, | 1241 | .init = &omap2_init_clksel_parent, |
| 1313 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1242 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1315,13 +1244,13 @@ static struct clk gpt10_fck = { | |||
| 1315 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1244 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1316 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | 1245 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, |
| 1317 | .clksel = omap343x_gpt_clksel, | 1246 | .clksel = omap343x_gpt_clksel, |
| 1318 | .flags = CLOCK_IN_OMAP343X, | ||
| 1319 | .clkdm_name = "core_l4_clkdm", | 1247 | .clkdm_name = "core_l4_clkdm", |
| 1320 | .recalc = &omap2_clksel_recalc, | 1248 | .recalc = &omap2_clksel_recalc, |
| 1321 | }; | 1249 | }; |
| 1322 | 1250 | ||
| 1323 | static struct clk gpt11_fck = { | 1251 | static struct clk gpt11_fck = { |
| 1324 | .name = "gpt11_fck", | 1252 | .name = "gpt11_fck", |
| 1253 | .ops = &clkops_omap2_dflt_wait, | ||
| 1325 | .parent = &sys_ck, | 1254 | .parent = &sys_ck, |
| 1326 | .init = &omap2_init_clksel_parent, | 1255 | .init = &omap2_init_clksel_parent, |
| 1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1256 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1329,35 +1258,34 @@ static struct clk gpt11_fck = { | |||
| 1329 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1258 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1330 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | 1259 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, |
| 1331 | .clksel = omap343x_gpt_clksel, | 1260 | .clksel = omap343x_gpt_clksel, |
| 1332 | .flags = CLOCK_IN_OMAP343X, | ||
| 1333 | .clkdm_name = "core_l4_clkdm", | 1261 | .clkdm_name = "core_l4_clkdm", |
| 1334 | .recalc = &omap2_clksel_recalc, | 1262 | .recalc = &omap2_clksel_recalc, |
| 1335 | }; | 1263 | }; |
| 1336 | 1264 | ||
| 1337 | static struct clk cpefuse_fck = { | 1265 | static struct clk cpefuse_fck = { |
| 1338 | .name = "cpefuse_fck", | 1266 | .name = "cpefuse_fck", |
| 1267 | .ops = &clkops_omap2_dflt, | ||
| 1339 | .parent = &sys_ck, | 1268 | .parent = &sys_ck, |
| 1340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1269 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1341 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | 1270 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
| 1342 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1343 | .recalc = &followparent_recalc, | 1271 | .recalc = &followparent_recalc, |
| 1344 | }; | 1272 | }; |
| 1345 | 1273 | ||
| 1346 | static struct clk ts_fck = { | 1274 | static struct clk ts_fck = { |
| 1347 | .name = "ts_fck", | 1275 | .name = "ts_fck", |
| 1276 | .ops = &clkops_omap2_dflt, | ||
| 1348 | .parent = &omap_32k_fck, | 1277 | .parent = &omap_32k_fck, |
| 1349 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1278 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1350 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | 1279 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
| 1351 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1352 | .recalc = &followparent_recalc, | 1280 | .recalc = &followparent_recalc, |
| 1353 | }; | 1281 | }; |
| 1354 | 1282 | ||
| 1355 | static struct clk usbtll_fck = { | 1283 | static struct clk usbtll_fck = { |
| 1356 | .name = "usbtll_fck", | 1284 | .name = "usbtll_fck", |
| 1357 | .parent = &omap_120m_fck, | 1285 | .ops = &clkops_omap2_dflt, |
| 1286 | .parent = &dpll5_m2_ck, | ||
| 1358 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1287 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1359 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1288 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1360 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1361 | .recalc = &followparent_recalc, | 1289 | .recalc = &followparent_recalc, |
| 1362 | }; | 1290 | }; |
| 1363 | 1291 | ||
| @@ -1365,84 +1293,83 @@ static struct clk usbtll_fck = { | |||
| 1365 | 1293 | ||
| 1366 | static struct clk core_96m_fck = { | 1294 | static struct clk core_96m_fck = { |
| 1367 | .name = "core_96m_fck", | 1295 | .name = "core_96m_fck", |
| 1296 | .ops = &clkops_null, | ||
| 1368 | .parent = &omap_96m_fck, | 1297 | .parent = &omap_96m_fck, |
| 1369 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1370 | PARENT_CONTROLS_CLOCK, | ||
| 1371 | .clkdm_name = "core_l4_clkdm", | 1298 | .clkdm_name = "core_l4_clkdm", |
| 1372 | .recalc = &followparent_recalc, | 1299 | .recalc = &followparent_recalc, |
| 1373 | }; | 1300 | }; |
| 1374 | 1301 | ||
| 1375 | static struct clk mmchs3_fck = { | 1302 | static struct clk mmchs3_fck = { |
| 1376 | .name = "mmchs_fck", | 1303 | .name = "mmchs_fck", |
| 1304 | .ops = &clkops_omap2_dflt_wait, | ||
| 1377 | .id = 2, | 1305 | .id = 2, |
| 1378 | .parent = &core_96m_fck, | 1306 | .parent = &core_96m_fck, |
| 1379 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1307 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1380 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1308 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1381 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1382 | .clkdm_name = "core_l4_clkdm", | 1309 | .clkdm_name = "core_l4_clkdm", |
| 1383 | .recalc = &followparent_recalc, | 1310 | .recalc = &followparent_recalc, |
| 1384 | }; | 1311 | }; |
| 1385 | 1312 | ||
| 1386 | static struct clk mmchs2_fck = { | 1313 | static struct clk mmchs2_fck = { |
| 1387 | .name = "mmchs_fck", | 1314 | .name = "mmchs_fck", |
| 1315 | .ops = &clkops_omap2_dflt_wait, | ||
| 1388 | .id = 1, | 1316 | .id = 1, |
| 1389 | .parent = &core_96m_fck, | 1317 | .parent = &core_96m_fck, |
| 1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1318 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1391 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1319 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1392 | .flags = CLOCK_IN_OMAP343X, | ||
| 1393 | .clkdm_name = "core_l4_clkdm", | 1320 | .clkdm_name = "core_l4_clkdm", |
| 1394 | .recalc = &followparent_recalc, | 1321 | .recalc = &followparent_recalc, |
| 1395 | }; | 1322 | }; |
| 1396 | 1323 | ||
| 1397 | static struct clk mspro_fck = { | 1324 | static struct clk mspro_fck = { |
| 1398 | .name = "mspro_fck", | 1325 | .name = "mspro_fck", |
| 1326 | .ops = &clkops_omap2_dflt_wait, | ||
| 1399 | .parent = &core_96m_fck, | 1327 | .parent = &core_96m_fck, |
| 1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1328 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1401 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | 1329 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1402 | .flags = CLOCK_IN_OMAP343X, | ||
| 1403 | .clkdm_name = "core_l4_clkdm", | 1330 | .clkdm_name = "core_l4_clkdm", |
| 1404 | .recalc = &followparent_recalc, | 1331 | .recalc = &followparent_recalc, |
| 1405 | }; | 1332 | }; |
| 1406 | 1333 | ||
| 1407 | static struct clk mmchs1_fck = { | 1334 | static struct clk mmchs1_fck = { |
| 1408 | .name = "mmchs_fck", | 1335 | .name = "mmchs_fck", |
| 1336 | .ops = &clkops_omap2_dflt_wait, | ||
| 1409 | .parent = &core_96m_fck, | 1337 | .parent = &core_96m_fck, |
| 1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1411 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | 1339 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1412 | .flags = CLOCK_IN_OMAP343X, | ||
| 1413 | .clkdm_name = "core_l4_clkdm", | 1340 | .clkdm_name = "core_l4_clkdm", |
| 1414 | .recalc = &followparent_recalc, | 1341 | .recalc = &followparent_recalc, |
| 1415 | }; | 1342 | }; |
| 1416 | 1343 | ||
| 1417 | static struct clk i2c3_fck = { | 1344 | static struct clk i2c3_fck = { |
| 1418 | .name = "i2c_fck", | 1345 | .name = "i2c_fck", |
| 1346 | .ops = &clkops_omap2_dflt_wait, | ||
| 1419 | .id = 3, | 1347 | .id = 3, |
| 1420 | .parent = &core_96m_fck, | 1348 | .parent = &core_96m_fck, |
| 1421 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1349 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1422 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1350 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1423 | .flags = CLOCK_IN_OMAP343X, | ||
| 1424 | .clkdm_name = "core_l4_clkdm", | 1351 | .clkdm_name = "core_l4_clkdm", |
| 1425 | .recalc = &followparent_recalc, | 1352 | .recalc = &followparent_recalc, |
| 1426 | }; | 1353 | }; |
| 1427 | 1354 | ||
| 1428 | static struct clk i2c2_fck = { | 1355 | static struct clk i2c2_fck = { |
| 1429 | .name = "i2c_fck", | 1356 | .name = "i2c_fck", |
| 1357 | .ops = &clkops_omap2_dflt_wait, | ||
| 1430 | .id = 2, | 1358 | .id = 2, |
| 1431 | .parent = &core_96m_fck, | 1359 | .parent = &core_96m_fck, |
| 1432 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1433 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1361 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1434 | .flags = CLOCK_IN_OMAP343X, | ||
| 1435 | .clkdm_name = "core_l4_clkdm", | 1362 | .clkdm_name = "core_l4_clkdm", |
| 1436 | .recalc = &followparent_recalc, | 1363 | .recalc = &followparent_recalc, |
| 1437 | }; | 1364 | }; |
| 1438 | 1365 | ||
| 1439 | static struct clk i2c1_fck = { | 1366 | static struct clk i2c1_fck = { |
| 1440 | .name = "i2c_fck", | 1367 | .name = "i2c_fck", |
| 1368 | .ops = &clkops_omap2_dflt_wait, | ||
| 1441 | .id = 1, | 1369 | .id = 1, |
| 1442 | .parent = &core_96m_fck, | 1370 | .parent = &core_96m_fck, |
| 1443 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1444 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1372 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1445 | .flags = CLOCK_IN_OMAP343X, | ||
| 1446 | .clkdm_name = "core_l4_clkdm", | 1373 | .clkdm_name = "core_l4_clkdm", |
| 1447 | .recalc = &followparent_recalc, | 1374 | .recalc = &followparent_recalc, |
| 1448 | }; | 1375 | }; |
| @@ -1469,6 +1396,7 @@ static const struct clksel mcbsp_15_clksel[] = { | |||
| 1469 | 1396 | ||
| 1470 | static struct clk mcbsp5_fck = { | 1397 | static struct clk mcbsp5_fck = { |
| 1471 | .name = "mcbsp_fck", | 1398 | .name = "mcbsp_fck", |
| 1399 | .ops = &clkops_omap2_dflt_wait, | ||
| 1472 | .id = 5, | 1400 | .id = 5, |
| 1473 | .init = &omap2_init_clksel_parent, | 1401 | .init = &omap2_init_clksel_parent, |
| 1474 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1402 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1476,13 +1404,13 @@ static struct clk mcbsp5_fck = { | |||
| 1476 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | 1404 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 1477 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | 1405 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
| 1478 | .clksel = mcbsp_15_clksel, | 1406 | .clksel = mcbsp_15_clksel, |
| 1479 | .flags = CLOCK_IN_OMAP343X, | ||
| 1480 | .clkdm_name = "core_l4_clkdm", | 1407 | .clkdm_name = "core_l4_clkdm", |
| 1481 | .recalc = &omap2_clksel_recalc, | 1408 | .recalc = &omap2_clksel_recalc, |
| 1482 | }; | 1409 | }; |
| 1483 | 1410 | ||
| 1484 | static struct clk mcbsp1_fck = { | 1411 | static struct clk mcbsp1_fck = { |
| 1485 | .name = "mcbsp_fck", | 1412 | .name = "mcbsp_fck", |
| 1413 | .ops = &clkops_omap2_dflt_wait, | ||
| 1486 | .id = 1, | 1414 | .id = 1, |
| 1487 | .init = &omap2_init_clksel_parent, | 1415 | .init = &omap2_init_clksel_parent, |
| 1488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1416 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1490,7 +1418,6 @@ static struct clk mcbsp1_fck = { | |||
| 1490 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | 1418 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1491 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | 1419 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
| 1492 | .clksel = mcbsp_15_clksel, | 1420 | .clksel = mcbsp_15_clksel, |
| 1493 | .flags = CLOCK_IN_OMAP343X, | ||
| 1494 | .clkdm_name = "core_l4_clkdm", | 1421 | .clkdm_name = "core_l4_clkdm", |
| 1495 | .recalc = &omap2_clksel_recalc, | 1422 | .recalc = &omap2_clksel_recalc, |
| 1496 | }; | 1423 | }; |
| @@ -1499,77 +1426,76 @@ static struct clk mcbsp1_fck = { | |||
| 1499 | 1426 | ||
| 1500 | static struct clk core_48m_fck = { | 1427 | static struct clk core_48m_fck = { |
| 1501 | .name = "core_48m_fck", | 1428 | .name = "core_48m_fck", |
| 1429 | .ops = &clkops_null, | ||
| 1502 | .parent = &omap_48m_fck, | 1430 | .parent = &omap_48m_fck, |
| 1503 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1504 | PARENT_CONTROLS_CLOCK, | ||
| 1505 | .clkdm_name = "core_l4_clkdm", | 1431 | .clkdm_name = "core_l4_clkdm", |
| 1506 | .recalc = &followparent_recalc, | 1432 | .recalc = &followparent_recalc, |
| 1507 | }; | 1433 | }; |
| 1508 | 1434 | ||
| 1509 | static struct clk mcspi4_fck = { | 1435 | static struct clk mcspi4_fck = { |
| 1510 | .name = "mcspi_fck", | 1436 | .name = "mcspi_fck", |
| 1437 | .ops = &clkops_omap2_dflt_wait, | ||
| 1511 | .id = 4, | 1438 | .id = 4, |
| 1512 | .parent = &core_48m_fck, | 1439 | .parent = &core_48m_fck, |
| 1513 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1440 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1514 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1441 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1515 | .flags = CLOCK_IN_OMAP343X, | ||
| 1516 | .recalc = &followparent_recalc, | 1442 | .recalc = &followparent_recalc, |
| 1517 | }; | 1443 | }; |
| 1518 | 1444 | ||
| 1519 | static struct clk mcspi3_fck = { | 1445 | static struct clk mcspi3_fck = { |
| 1520 | .name = "mcspi_fck", | 1446 | .name = "mcspi_fck", |
| 1447 | .ops = &clkops_omap2_dflt_wait, | ||
| 1521 | .id = 3, | 1448 | .id = 3, |
| 1522 | .parent = &core_48m_fck, | 1449 | .parent = &core_48m_fck, |
| 1523 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1450 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1524 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1451 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1525 | .flags = CLOCK_IN_OMAP343X, | ||
| 1526 | .recalc = &followparent_recalc, | 1452 | .recalc = &followparent_recalc, |
| 1527 | }; | 1453 | }; |
| 1528 | 1454 | ||
| 1529 | static struct clk mcspi2_fck = { | 1455 | static struct clk mcspi2_fck = { |
| 1530 | .name = "mcspi_fck", | 1456 | .name = "mcspi_fck", |
| 1457 | .ops = &clkops_omap2_dflt_wait, | ||
| 1531 | .id = 2, | 1458 | .id = 2, |
| 1532 | .parent = &core_48m_fck, | 1459 | .parent = &core_48m_fck, |
| 1533 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1534 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1461 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1535 | .flags = CLOCK_IN_OMAP343X, | ||
| 1536 | .recalc = &followparent_recalc, | 1462 | .recalc = &followparent_recalc, |
| 1537 | }; | 1463 | }; |
| 1538 | 1464 | ||
| 1539 | static struct clk mcspi1_fck = { | 1465 | static struct clk mcspi1_fck = { |
| 1540 | .name = "mcspi_fck", | 1466 | .name = "mcspi_fck", |
| 1467 | .ops = &clkops_omap2_dflt_wait, | ||
| 1541 | .id = 1, | 1468 | .id = 1, |
| 1542 | .parent = &core_48m_fck, | 1469 | .parent = &core_48m_fck, |
| 1543 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1544 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1471 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1545 | .flags = CLOCK_IN_OMAP343X, | ||
| 1546 | .recalc = &followparent_recalc, | 1472 | .recalc = &followparent_recalc, |
| 1547 | }; | 1473 | }; |
| 1548 | 1474 | ||
| 1549 | static struct clk uart2_fck = { | 1475 | static struct clk uart2_fck = { |
| 1550 | .name = "uart2_fck", | 1476 | .name = "uart2_fck", |
| 1477 | .ops = &clkops_omap2_dflt_wait, | ||
| 1551 | .parent = &core_48m_fck, | 1478 | .parent = &core_48m_fck, |
| 1552 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1479 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1553 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | 1480 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
| 1554 | .flags = CLOCK_IN_OMAP343X, | ||
| 1555 | .recalc = &followparent_recalc, | 1481 | .recalc = &followparent_recalc, |
| 1556 | }; | 1482 | }; |
| 1557 | 1483 | ||
| 1558 | static struct clk uart1_fck = { | 1484 | static struct clk uart1_fck = { |
| 1559 | .name = "uart1_fck", | 1485 | .name = "uart1_fck", |
| 1486 | .ops = &clkops_omap2_dflt_wait, | ||
| 1560 | .parent = &core_48m_fck, | 1487 | .parent = &core_48m_fck, |
| 1561 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1562 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | 1489 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
| 1563 | .flags = CLOCK_IN_OMAP343X, | ||
| 1564 | .recalc = &followparent_recalc, | 1490 | .recalc = &followparent_recalc, |
| 1565 | }; | 1491 | }; |
| 1566 | 1492 | ||
| 1567 | static struct clk fshostusb_fck = { | 1493 | static struct clk fshostusb_fck = { |
| 1568 | .name = "fshostusb_fck", | 1494 | .name = "fshostusb_fck", |
| 1495 | .ops = &clkops_omap2_dflt_wait, | ||
| 1569 | .parent = &core_48m_fck, | 1496 | .parent = &core_48m_fck, |
| 1570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1497 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1571 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | 1498 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 1572 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1573 | .recalc = &followparent_recalc, | 1499 | .recalc = &followparent_recalc, |
| 1574 | }; | 1500 | }; |
| 1575 | 1501 | ||
| @@ -1577,19 +1503,18 @@ static struct clk fshostusb_fck = { | |||
| 1577 | 1503 | ||
| 1578 | static struct clk core_12m_fck = { | 1504 | static struct clk core_12m_fck = { |
| 1579 | .name = "core_12m_fck", | 1505 | .name = "core_12m_fck", |
| 1506 | .ops = &clkops_null, | ||
| 1580 | .parent = &omap_12m_fck, | 1507 | .parent = &omap_12m_fck, |
| 1581 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1582 | PARENT_CONTROLS_CLOCK, | ||
| 1583 | .clkdm_name = "core_l4_clkdm", | 1508 | .clkdm_name = "core_l4_clkdm", |
| 1584 | .recalc = &followparent_recalc, | 1509 | .recalc = &followparent_recalc, |
| 1585 | }; | 1510 | }; |
| 1586 | 1511 | ||
| 1587 | static struct clk hdq_fck = { | 1512 | static struct clk hdq_fck = { |
| 1588 | .name = "hdq_fck", | 1513 | .name = "hdq_fck", |
| 1514 | .ops = &clkops_omap2_dflt_wait, | ||
| 1589 | .parent = &core_12m_fck, | 1515 | .parent = &core_12m_fck, |
| 1590 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1516 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1591 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | 1517 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1592 | .flags = CLOCK_IN_OMAP343X, | ||
| 1593 | .recalc = &followparent_recalc, | 1518 | .recalc = &followparent_recalc, |
| 1594 | }; | 1519 | }; |
| 1595 | 1520 | ||
| @@ -1612,22 +1537,22 @@ static const struct clksel ssi_ssr_clksel[] = { | |||
| 1612 | 1537 | ||
| 1613 | static struct clk ssi_ssr_fck = { | 1538 | static struct clk ssi_ssr_fck = { |
| 1614 | .name = "ssi_ssr_fck", | 1539 | .name = "ssi_ssr_fck", |
| 1540 | .ops = &clkops_omap2_dflt, | ||
| 1615 | .init = &omap2_init_clksel_parent, | 1541 | .init = &omap2_init_clksel_parent, |
| 1616 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1542 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1617 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | 1543 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1618 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1544 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1619 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | 1545 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
| 1620 | .clksel = ssi_ssr_clksel, | 1546 | .clksel = ssi_ssr_clksel, |
| 1621 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 1622 | .clkdm_name = "core_l4_clkdm", | 1547 | .clkdm_name = "core_l4_clkdm", |
| 1623 | .recalc = &omap2_clksel_recalc, | 1548 | .recalc = &omap2_clksel_recalc, |
| 1624 | }; | 1549 | }; |
| 1625 | 1550 | ||
| 1626 | static struct clk ssi_sst_fck = { | 1551 | static struct clk ssi_sst_fck = { |
| 1627 | .name = "ssi_sst_fck", | 1552 | .name = "ssi_sst_fck", |
| 1553 | .ops = &clkops_null, | ||
| 1628 | .parent = &ssi_ssr_fck, | 1554 | .parent = &ssi_ssr_fck, |
| 1629 | .fixed_div = 2, | 1555 | .fixed_div = 2, |
| 1630 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 1631 | .recalc = &omap2_fixed_divisor_recalc, | 1556 | .recalc = &omap2_fixed_divisor_recalc, |
| 1632 | }; | 1557 | }; |
| 1633 | 1558 | ||
| @@ -1641,39 +1566,39 @@ static struct clk ssi_sst_fck = { | |||
| 1641 | */ | 1566 | */ |
| 1642 | static struct clk core_l3_ick = { | 1567 | static struct clk core_l3_ick = { |
| 1643 | .name = "core_l3_ick", | 1568 | .name = "core_l3_ick", |
| 1569 | .ops = &clkops_null, | ||
| 1644 | .parent = &l3_ick, | 1570 | .parent = &l3_ick, |
| 1645 | .init = &omap2_init_clk_clkdm, | 1571 | .init = &omap2_init_clk_clkdm, |
| 1646 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1647 | PARENT_CONTROLS_CLOCK, | ||
| 1648 | .clkdm_name = "core_l3_clkdm", | 1572 | .clkdm_name = "core_l3_clkdm", |
| 1649 | .recalc = &followparent_recalc, | 1573 | .recalc = &followparent_recalc, |
| 1650 | }; | 1574 | }; |
| 1651 | 1575 | ||
| 1652 | static struct clk hsotgusb_ick = { | 1576 | static struct clk hsotgusb_ick = { |
| 1653 | .name = "hsotgusb_ick", | 1577 | .name = "hsotgusb_ick", |
| 1578 | .ops = &clkops_omap2_dflt_wait, | ||
| 1654 | .parent = &core_l3_ick, | 1579 | .parent = &core_l3_ick, |
| 1655 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1580 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1656 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | 1581 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
| 1657 | .flags = CLOCK_IN_OMAP343X, | ||
| 1658 | .clkdm_name = "core_l3_clkdm", | 1582 | .clkdm_name = "core_l3_clkdm", |
| 1659 | .recalc = &followparent_recalc, | 1583 | .recalc = &followparent_recalc, |
| 1660 | }; | 1584 | }; |
| 1661 | 1585 | ||
| 1662 | static struct clk sdrc_ick = { | 1586 | static struct clk sdrc_ick = { |
| 1663 | .name = "sdrc_ick", | 1587 | .name = "sdrc_ick", |
| 1588 | .ops = &clkops_omap2_dflt_wait, | ||
| 1664 | .parent = &core_l3_ick, | 1589 | .parent = &core_l3_ick, |
| 1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1590 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1666 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | 1591 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, |
| 1667 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | 1592 | .flags = ENABLE_ON_INIT, |
| 1668 | .clkdm_name = "core_l3_clkdm", | 1593 | .clkdm_name = "core_l3_clkdm", |
| 1669 | .recalc = &followparent_recalc, | 1594 | .recalc = &followparent_recalc, |
| 1670 | }; | 1595 | }; |
| 1671 | 1596 | ||
| 1672 | static struct clk gpmc_fck = { | 1597 | static struct clk gpmc_fck = { |
| 1673 | .name = "gpmc_fck", | 1598 | .name = "gpmc_fck", |
| 1599 | .ops = &clkops_null, | ||
| 1674 | .parent = &core_l3_ick, | 1600 | .parent = &core_l3_ick, |
| 1675 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | | 1601 | .flags = ENABLE_ON_INIT, /* huh? */ |
| 1676 | ENABLE_ON_INIT, | ||
| 1677 | .clkdm_name = "core_l3_clkdm", | 1602 | .clkdm_name = "core_l3_clkdm", |
| 1678 | .recalc = &followparent_recalc, | 1603 | .recalc = &followparent_recalc, |
| 1679 | }; | 1604 | }; |
| @@ -1682,18 +1607,17 @@ static struct clk gpmc_fck = { | |||
| 1682 | 1607 | ||
| 1683 | static struct clk security_l3_ick = { | 1608 | static struct clk security_l3_ick = { |
| 1684 | .name = "security_l3_ick", | 1609 | .name = "security_l3_ick", |
| 1610 | .ops = &clkops_null, | ||
| 1685 | .parent = &l3_ick, | 1611 | .parent = &l3_ick, |
| 1686 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1687 | PARENT_CONTROLS_CLOCK, | ||
| 1688 | .recalc = &followparent_recalc, | 1612 | .recalc = &followparent_recalc, |
| 1689 | }; | 1613 | }; |
| 1690 | 1614 | ||
| 1691 | static struct clk pka_ick = { | 1615 | static struct clk pka_ick = { |
| 1692 | .name = "pka_ick", | 1616 | .name = "pka_ick", |
| 1617 | .ops = &clkops_omap2_dflt_wait, | ||
| 1693 | .parent = &security_l3_ick, | 1618 | .parent = &security_l3_ick, |
| 1694 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1619 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1695 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | 1620 | .enable_bit = OMAP3430_EN_PKA_SHIFT, |
| 1696 | .flags = CLOCK_IN_OMAP343X, | ||
| 1697 | .recalc = &followparent_recalc, | 1621 | .recalc = &followparent_recalc, |
| 1698 | }; | 1622 | }; |
| 1699 | 1623 | ||
| @@ -1701,31 +1625,30 @@ static struct clk pka_ick = { | |||
| 1701 | 1625 | ||
| 1702 | static struct clk core_l4_ick = { | 1626 | static struct clk core_l4_ick = { |
| 1703 | .name = "core_l4_ick", | 1627 | .name = "core_l4_ick", |
| 1628 | .ops = &clkops_null, | ||
| 1704 | .parent = &l4_ick, | 1629 | .parent = &l4_ick, |
| 1705 | .init = &omap2_init_clk_clkdm, | 1630 | .init = &omap2_init_clk_clkdm, |
| 1706 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1707 | PARENT_CONTROLS_CLOCK, | ||
| 1708 | .clkdm_name = "core_l4_clkdm", | 1631 | .clkdm_name = "core_l4_clkdm", |
| 1709 | .recalc = &followparent_recalc, | 1632 | .recalc = &followparent_recalc, |
| 1710 | }; | 1633 | }; |
| 1711 | 1634 | ||
| 1712 | static struct clk usbtll_ick = { | 1635 | static struct clk usbtll_ick = { |
| 1713 | .name = "usbtll_ick", | 1636 | .name = "usbtll_ick", |
| 1637 | .ops = &clkops_omap2_dflt_wait, | ||
| 1714 | .parent = &core_l4_ick, | 1638 | .parent = &core_l4_ick, |
| 1715 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 1639 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1716 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1640 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1717 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1718 | .clkdm_name = "core_l4_clkdm", | 1641 | .clkdm_name = "core_l4_clkdm", |
| 1719 | .recalc = &followparent_recalc, | 1642 | .recalc = &followparent_recalc, |
| 1720 | }; | 1643 | }; |
| 1721 | 1644 | ||
| 1722 | static struct clk mmchs3_ick = { | 1645 | static struct clk mmchs3_ick = { |
| 1723 | .name = "mmchs_ick", | 1646 | .name = "mmchs_ick", |
| 1647 | .ops = &clkops_omap2_dflt_wait, | ||
| 1724 | .id = 2, | 1648 | .id = 2, |
| 1725 | .parent = &core_l4_ick, | 1649 | .parent = &core_l4_ick, |
| 1726 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1650 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1727 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1651 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1728 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1729 | .clkdm_name = "core_l4_clkdm", | 1652 | .clkdm_name = "core_l4_clkdm", |
| 1730 | .recalc = &followparent_recalc, | 1653 | .recalc = &followparent_recalc, |
| 1731 | }; | 1654 | }; |
| @@ -1733,250 +1656,251 @@ static struct clk mmchs3_ick = { | |||
| 1733 | /* Intersystem Communication Registers - chassis mode only */ | 1656 | /* Intersystem Communication Registers - chassis mode only */ |
| 1734 | static struct clk icr_ick = { | 1657 | static struct clk icr_ick = { |
| 1735 | .name = "icr_ick", | 1658 | .name = "icr_ick", |
| 1659 | .ops = &clkops_omap2_dflt_wait, | ||
| 1736 | .parent = &core_l4_ick, | 1660 | .parent = &core_l4_ick, |
| 1737 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1661 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1738 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | 1662 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
| 1739 | .flags = CLOCK_IN_OMAP343X, | ||
| 1740 | .clkdm_name = "core_l4_clkdm", | 1663 | .clkdm_name = "core_l4_clkdm", |
| 1741 | .recalc = &followparent_recalc, | 1664 | .recalc = &followparent_recalc, |
| 1742 | }; | 1665 | }; |
| 1743 | 1666 | ||
| 1744 | static struct clk aes2_ick = { | 1667 | static struct clk aes2_ick = { |
| 1745 | .name = "aes2_ick", | 1668 | .name = "aes2_ick", |
| 1669 | .ops = &clkops_omap2_dflt_wait, | ||
| 1746 | .parent = &core_l4_ick, | 1670 | .parent = &core_l4_ick, |
| 1747 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1671 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1748 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | 1672 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
| 1749 | .flags = CLOCK_IN_OMAP343X, | ||
| 1750 | .clkdm_name = "core_l4_clkdm", | 1673 | .clkdm_name = "core_l4_clkdm", |
| 1751 | .recalc = &followparent_recalc, | 1674 | .recalc = &followparent_recalc, |
| 1752 | }; | 1675 | }; |
| 1753 | 1676 | ||
| 1754 | static struct clk sha12_ick = { | 1677 | static struct clk sha12_ick = { |
| 1755 | .name = "sha12_ick", | 1678 | .name = "sha12_ick", |
| 1679 | .ops = &clkops_omap2_dflt_wait, | ||
| 1756 | .parent = &core_l4_ick, | 1680 | .parent = &core_l4_ick, |
| 1757 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1681 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1758 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | 1682 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
| 1759 | .flags = CLOCK_IN_OMAP343X, | ||
| 1760 | .clkdm_name = "core_l4_clkdm", | 1683 | .clkdm_name = "core_l4_clkdm", |
| 1761 | .recalc = &followparent_recalc, | 1684 | .recalc = &followparent_recalc, |
| 1762 | }; | 1685 | }; |
| 1763 | 1686 | ||
| 1764 | static struct clk des2_ick = { | 1687 | static struct clk des2_ick = { |
| 1765 | .name = "des2_ick", | 1688 | .name = "des2_ick", |
| 1689 | .ops = &clkops_omap2_dflt_wait, | ||
| 1766 | .parent = &core_l4_ick, | 1690 | .parent = &core_l4_ick, |
| 1767 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1691 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1768 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | 1692 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
| 1769 | .flags = CLOCK_IN_OMAP343X, | ||
| 1770 | .clkdm_name = "core_l4_clkdm", | 1693 | .clkdm_name = "core_l4_clkdm", |
| 1771 | .recalc = &followparent_recalc, | 1694 | .recalc = &followparent_recalc, |
| 1772 | }; | 1695 | }; |
| 1773 | 1696 | ||
| 1774 | static struct clk mmchs2_ick = { | 1697 | static struct clk mmchs2_ick = { |
| 1775 | .name = "mmchs_ick", | 1698 | .name = "mmchs_ick", |
| 1699 | .ops = &clkops_omap2_dflt_wait, | ||
| 1776 | .id = 1, | 1700 | .id = 1, |
| 1777 | .parent = &core_l4_ick, | 1701 | .parent = &core_l4_ick, |
| 1778 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1702 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1779 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1703 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1780 | .flags = CLOCK_IN_OMAP343X, | ||
| 1781 | .clkdm_name = "core_l4_clkdm", | 1704 | .clkdm_name = "core_l4_clkdm", |
| 1782 | .recalc = &followparent_recalc, | 1705 | .recalc = &followparent_recalc, |
| 1783 | }; | 1706 | }; |
| 1784 | 1707 | ||
| 1785 | static struct clk mmchs1_ick = { | 1708 | static struct clk mmchs1_ick = { |
| 1786 | .name = "mmchs_ick", | 1709 | .name = "mmchs_ick", |
| 1710 | .ops = &clkops_omap2_dflt_wait, | ||
| 1787 | .parent = &core_l4_ick, | 1711 | .parent = &core_l4_ick, |
| 1788 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1789 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | 1713 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1790 | .flags = CLOCK_IN_OMAP343X, | ||
| 1791 | .clkdm_name = "core_l4_clkdm", | 1714 | .clkdm_name = "core_l4_clkdm", |
| 1792 | .recalc = &followparent_recalc, | 1715 | .recalc = &followparent_recalc, |
| 1793 | }; | 1716 | }; |
| 1794 | 1717 | ||
| 1795 | static struct clk mspro_ick = { | 1718 | static struct clk mspro_ick = { |
| 1796 | .name = "mspro_ick", | 1719 | .name = "mspro_ick", |
| 1720 | .ops = &clkops_omap2_dflt_wait, | ||
| 1797 | .parent = &core_l4_ick, | 1721 | .parent = &core_l4_ick, |
| 1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1722 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1799 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | 1723 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1800 | .flags = CLOCK_IN_OMAP343X, | ||
| 1801 | .clkdm_name = "core_l4_clkdm", | 1724 | .clkdm_name = "core_l4_clkdm", |
| 1802 | .recalc = &followparent_recalc, | 1725 | .recalc = &followparent_recalc, |
| 1803 | }; | 1726 | }; |
| 1804 | 1727 | ||
| 1805 | static struct clk hdq_ick = { | 1728 | static struct clk hdq_ick = { |
| 1806 | .name = "hdq_ick", | 1729 | .name = "hdq_ick", |
| 1730 | .ops = &clkops_omap2_dflt_wait, | ||
| 1807 | .parent = &core_l4_ick, | 1731 | .parent = &core_l4_ick, |
| 1808 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1732 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1809 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | 1733 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1810 | .flags = CLOCK_IN_OMAP343X, | ||
| 1811 | .clkdm_name = "core_l4_clkdm", | 1734 | .clkdm_name = "core_l4_clkdm", |
| 1812 | .recalc = &followparent_recalc, | 1735 | .recalc = &followparent_recalc, |
| 1813 | }; | 1736 | }; |
| 1814 | 1737 | ||
| 1815 | static struct clk mcspi4_ick = { | 1738 | static struct clk mcspi4_ick = { |
| 1816 | .name = "mcspi_ick", | 1739 | .name = "mcspi_ick", |
| 1740 | .ops = &clkops_omap2_dflt_wait, | ||
| 1817 | .id = 4, | 1741 | .id = 4, |
| 1818 | .parent = &core_l4_ick, | 1742 | .parent = &core_l4_ick, |
| 1819 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1743 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1820 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1744 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1821 | .flags = CLOCK_IN_OMAP343X, | ||
| 1822 | .clkdm_name = "core_l4_clkdm", | 1745 | .clkdm_name = "core_l4_clkdm", |
| 1823 | .recalc = &followparent_recalc, | 1746 | .recalc = &followparent_recalc, |
| 1824 | }; | 1747 | }; |
| 1825 | 1748 | ||
| 1826 | static struct clk mcspi3_ick = { | 1749 | static struct clk mcspi3_ick = { |
| 1827 | .name = "mcspi_ick", | 1750 | .name = "mcspi_ick", |
| 1751 | .ops = &clkops_omap2_dflt_wait, | ||
| 1828 | .id = 3, | 1752 | .id = 3, |
| 1829 | .parent = &core_l4_ick, | 1753 | .parent = &core_l4_ick, |
| 1830 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1754 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1831 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1755 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1832 | .flags = CLOCK_IN_OMAP343X, | ||
| 1833 | .clkdm_name = "core_l4_clkdm", | 1756 | .clkdm_name = "core_l4_clkdm", |
| 1834 | .recalc = &followparent_recalc, | 1757 | .recalc = &followparent_recalc, |
| 1835 | }; | 1758 | }; |
| 1836 | 1759 | ||
| 1837 | static struct clk mcspi2_ick = { | 1760 | static struct clk mcspi2_ick = { |
| 1838 | .name = "mcspi_ick", | 1761 | .name = "mcspi_ick", |
| 1762 | .ops = &clkops_omap2_dflt_wait, | ||
| 1839 | .id = 2, | 1763 | .id = 2, |
| 1840 | .parent = &core_l4_ick, | 1764 | .parent = &core_l4_ick, |
| 1841 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1842 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1766 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1843 | .flags = CLOCK_IN_OMAP343X, | ||
| 1844 | .clkdm_name = "core_l4_clkdm", | 1767 | .clkdm_name = "core_l4_clkdm", |
| 1845 | .recalc = &followparent_recalc, | 1768 | .recalc = &followparent_recalc, |
| 1846 | }; | 1769 | }; |
| 1847 | 1770 | ||
| 1848 | static struct clk mcspi1_ick = { | 1771 | static struct clk mcspi1_ick = { |
| 1849 | .name = "mcspi_ick", | 1772 | .name = "mcspi_ick", |
| 1773 | .ops = &clkops_omap2_dflt_wait, | ||
| 1850 | .id = 1, | 1774 | .id = 1, |
| 1851 | .parent = &core_l4_ick, | 1775 | .parent = &core_l4_ick, |
| 1852 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1776 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1853 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1777 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1854 | .flags = CLOCK_IN_OMAP343X, | ||
| 1855 | .clkdm_name = "core_l4_clkdm", | 1778 | .clkdm_name = "core_l4_clkdm", |
| 1856 | .recalc = &followparent_recalc, | 1779 | .recalc = &followparent_recalc, |
| 1857 | }; | 1780 | }; |
| 1858 | 1781 | ||
| 1859 | static struct clk i2c3_ick = { | 1782 | static struct clk i2c3_ick = { |
| 1860 | .name = "i2c_ick", | 1783 | .name = "i2c_ick", |
| 1784 | .ops = &clkops_omap2_dflt_wait, | ||
| 1861 | .id = 3, | 1785 | .id = 3, |
| 1862 | .parent = &core_l4_ick, | 1786 | .parent = &core_l4_ick, |
| 1863 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1787 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1864 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1788 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1865 | .flags = CLOCK_IN_OMAP343X, | ||
| 1866 | .clkdm_name = "core_l4_clkdm", | 1789 | .clkdm_name = "core_l4_clkdm", |
| 1867 | .recalc = &followparent_recalc, | 1790 | .recalc = &followparent_recalc, |
| 1868 | }; | 1791 | }; |
| 1869 | 1792 | ||
| 1870 | static struct clk i2c2_ick = { | 1793 | static struct clk i2c2_ick = { |
| 1871 | .name = "i2c_ick", | 1794 | .name = "i2c_ick", |
| 1795 | .ops = &clkops_omap2_dflt_wait, | ||
| 1872 | .id = 2, | 1796 | .id = 2, |
| 1873 | .parent = &core_l4_ick, | 1797 | .parent = &core_l4_ick, |
| 1874 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1875 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1799 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1876 | .flags = CLOCK_IN_OMAP343X, | ||
| 1877 | .clkdm_name = "core_l4_clkdm", | 1800 | .clkdm_name = "core_l4_clkdm", |
| 1878 | .recalc = &followparent_recalc, | 1801 | .recalc = &followparent_recalc, |
| 1879 | }; | 1802 | }; |
| 1880 | 1803 | ||
| 1881 | static struct clk i2c1_ick = { | 1804 | static struct clk i2c1_ick = { |
| 1882 | .name = "i2c_ick", | 1805 | .name = "i2c_ick", |
| 1806 | .ops = &clkops_omap2_dflt_wait, | ||
| 1883 | .id = 1, | 1807 | .id = 1, |
| 1884 | .parent = &core_l4_ick, | 1808 | .parent = &core_l4_ick, |
| 1885 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1809 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1886 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1810 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1887 | .flags = CLOCK_IN_OMAP343X, | ||
| 1888 | .clkdm_name = "core_l4_clkdm", | 1811 | .clkdm_name = "core_l4_clkdm", |
| 1889 | .recalc = &followparent_recalc, | 1812 | .recalc = &followparent_recalc, |
| 1890 | }; | 1813 | }; |
| 1891 | 1814 | ||
| 1892 | static struct clk uart2_ick = { | 1815 | static struct clk uart2_ick = { |
| 1893 | .name = "uart2_ick", | 1816 | .name = "uart2_ick", |
| 1817 | .ops = &clkops_omap2_dflt_wait, | ||
| 1894 | .parent = &core_l4_ick, | 1818 | .parent = &core_l4_ick, |
| 1895 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1819 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1896 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | 1820 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
| 1897 | .flags = CLOCK_IN_OMAP343X, | ||
| 1898 | .clkdm_name = "core_l4_clkdm", | 1821 | .clkdm_name = "core_l4_clkdm", |
| 1899 | .recalc = &followparent_recalc, | 1822 | .recalc = &followparent_recalc, |
| 1900 | }; | 1823 | }; |
| 1901 | 1824 | ||
| 1902 | static struct clk uart1_ick = { | 1825 | static struct clk uart1_ick = { |
| 1903 | .name = "uart1_ick", | 1826 | .name = "uart1_ick", |
| 1827 | .ops = &clkops_omap2_dflt_wait, | ||
| 1904 | .parent = &core_l4_ick, | 1828 | .parent = &core_l4_ick, |
| 1905 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1829 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1906 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | 1830 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
| 1907 | .flags = CLOCK_IN_OMAP343X, | ||
| 1908 | .clkdm_name = "core_l4_clkdm", | 1831 | .clkdm_name = "core_l4_clkdm", |
| 1909 | .recalc = &followparent_recalc, | 1832 | .recalc = &followparent_recalc, |
| 1910 | }; | 1833 | }; |
| 1911 | 1834 | ||
| 1912 | static struct clk gpt11_ick = { | 1835 | static struct clk gpt11_ick = { |
| 1913 | .name = "gpt11_ick", | 1836 | .name = "gpt11_ick", |
| 1837 | .ops = &clkops_omap2_dflt_wait, | ||
| 1914 | .parent = &core_l4_ick, | 1838 | .parent = &core_l4_ick, |
| 1915 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1839 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1916 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | 1840 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1917 | .flags = CLOCK_IN_OMAP343X, | ||
| 1918 | .clkdm_name = "core_l4_clkdm", | 1841 | .clkdm_name = "core_l4_clkdm", |
| 1919 | .recalc = &followparent_recalc, | 1842 | .recalc = &followparent_recalc, |
| 1920 | }; | 1843 | }; |
| 1921 | 1844 | ||
| 1922 | static struct clk gpt10_ick = { | 1845 | static struct clk gpt10_ick = { |
| 1923 | .name = "gpt10_ick", | 1846 | .name = "gpt10_ick", |
| 1847 | .ops = &clkops_omap2_dflt_wait, | ||
| 1924 | .parent = &core_l4_ick, | 1848 | .parent = &core_l4_ick, |
| 1925 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1849 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1926 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | 1850 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1927 | .flags = CLOCK_IN_OMAP343X, | ||
| 1928 | .clkdm_name = "core_l4_clkdm", | 1851 | .clkdm_name = "core_l4_clkdm", |
| 1929 | .recalc = &followparent_recalc, | 1852 | .recalc = &followparent_recalc, |
| 1930 | }; | 1853 | }; |
| 1931 | 1854 | ||
| 1932 | static struct clk mcbsp5_ick = { | 1855 | static struct clk mcbsp5_ick = { |
| 1933 | .name = "mcbsp_ick", | 1856 | .name = "mcbsp_ick", |
| 1857 | .ops = &clkops_omap2_dflt_wait, | ||
| 1934 | .id = 5, | 1858 | .id = 5, |
| 1935 | .parent = &core_l4_ick, | 1859 | .parent = &core_l4_ick, |
| 1936 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1860 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1937 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 1861 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1938 | .flags = CLOCK_IN_OMAP343X, | ||
| 1939 | .clkdm_name = "core_l4_clkdm", | 1862 | .clkdm_name = "core_l4_clkdm", |
| 1940 | .recalc = &followparent_recalc, | 1863 | .recalc = &followparent_recalc, |
| 1941 | }; | 1864 | }; |
| 1942 | 1865 | ||
| 1943 | static struct clk mcbsp1_ick = { | 1866 | static struct clk mcbsp1_ick = { |
| 1944 | .name = "mcbsp_ick", | 1867 | .name = "mcbsp_ick", |
| 1868 | .ops = &clkops_omap2_dflt_wait, | ||
| 1945 | .id = 1, | 1869 | .id = 1, |
| 1946 | .parent = &core_l4_ick, | 1870 | .parent = &core_l4_ick, |
| 1947 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1871 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1948 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 1872 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 1949 | .flags = CLOCK_IN_OMAP343X, | ||
| 1950 | .clkdm_name = "core_l4_clkdm", | 1873 | .clkdm_name = "core_l4_clkdm", |
| 1951 | .recalc = &followparent_recalc, | 1874 | .recalc = &followparent_recalc, |
| 1952 | }; | 1875 | }; |
| 1953 | 1876 | ||
| 1954 | static struct clk fac_ick = { | 1877 | static struct clk fac_ick = { |
| 1955 | .name = "fac_ick", | 1878 | .name = "fac_ick", |
| 1879 | .ops = &clkops_omap2_dflt_wait, | ||
| 1956 | .parent = &core_l4_ick, | 1880 | .parent = &core_l4_ick, |
| 1957 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1881 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1958 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | 1882 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
| 1959 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1960 | .clkdm_name = "core_l4_clkdm", | 1883 | .clkdm_name = "core_l4_clkdm", |
| 1961 | .recalc = &followparent_recalc, | 1884 | .recalc = &followparent_recalc, |
| 1962 | }; | 1885 | }; |
| 1963 | 1886 | ||
| 1964 | static struct clk mailboxes_ick = { | 1887 | static struct clk mailboxes_ick = { |
| 1965 | .name = "mailboxes_ick", | 1888 | .name = "mailboxes_ick", |
| 1889 | .ops = &clkops_omap2_dflt_wait, | ||
| 1966 | .parent = &core_l4_ick, | 1890 | .parent = &core_l4_ick, |
| 1967 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1891 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1968 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | 1892 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
| 1969 | .flags = CLOCK_IN_OMAP343X, | ||
| 1970 | .clkdm_name = "core_l4_clkdm", | 1893 | .clkdm_name = "core_l4_clkdm", |
| 1971 | .recalc = &followparent_recalc, | 1894 | .recalc = &followparent_recalc, |
| 1972 | }; | 1895 | }; |
| 1973 | 1896 | ||
| 1974 | static struct clk omapctrl_ick = { | 1897 | static struct clk omapctrl_ick = { |
| 1975 | .name = "omapctrl_ick", | 1898 | .name = "omapctrl_ick", |
| 1899 | .ops = &clkops_omap2_dflt_wait, | ||
| 1976 | .parent = &core_l4_ick, | 1900 | .parent = &core_l4_ick, |
| 1977 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1901 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1978 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | 1902 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
| 1979 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | 1903 | .flags = ENABLE_ON_INIT, |
| 1980 | .recalc = &followparent_recalc, | 1904 | .recalc = &followparent_recalc, |
| 1981 | }; | 1905 | }; |
| 1982 | 1906 | ||
| @@ -1984,19 +1908,18 @@ static struct clk omapctrl_ick = { | |||
| 1984 | 1908 | ||
| 1985 | static struct clk ssi_l4_ick = { | 1909 | static struct clk ssi_l4_ick = { |
| 1986 | .name = "ssi_l4_ick", | 1910 | .name = "ssi_l4_ick", |
| 1911 | .ops = &clkops_null, | ||
| 1987 | .parent = &l4_ick, | 1912 | .parent = &l4_ick, |
| 1988 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1989 | PARENT_CONTROLS_CLOCK, | ||
| 1990 | .clkdm_name = "core_l4_clkdm", | 1913 | .clkdm_name = "core_l4_clkdm", |
| 1991 | .recalc = &followparent_recalc, | 1914 | .recalc = &followparent_recalc, |
| 1992 | }; | 1915 | }; |
| 1993 | 1916 | ||
| 1994 | static struct clk ssi_ick = { | 1917 | static struct clk ssi_ick = { |
| 1995 | .name = "ssi_ick", | 1918 | .name = "ssi_ick", |
| 1919 | .ops = &clkops_omap2_dflt, | ||
| 1996 | .parent = &ssi_l4_ick, | 1920 | .parent = &ssi_l4_ick, |
| 1997 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1921 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1998 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | 1922 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1999 | .flags = CLOCK_IN_OMAP343X, | ||
| 2000 | .clkdm_name = "core_l4_clkdm", | 1923 | .clkdm_name = "core_l4_clkdm", |
| 2001 | .recalc = &followparent_recalc, | 1924 | .recalc = &followparent_recalc, |
| 2002 | }; | 1925 | }; |
| @@ -2011,6 +1934,7 @@ static const struct clksel usb_l4_clksel[] = { | |||
| 2011 | 1934 | ||
| 2012 | static struct clk usb_l4_ick = { | 1935 | static struct clk usb_l4_ick = { |
| 2013 | .name = "usb_l4_ick", | 1936 | .name = "usb_l4_ick", |
| 1937 | .ops = &clkops_omap2_dflt_wait, | ||
| 2014 | .parent = &l4_ick, | 1938 | .parent = &l4_ick, |
| 2015 | .init = &omap2_init_clksel_parent, | 1939 | .init = &omap2_init_clksel_parent, |
| 2016 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1940 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -2018,7 +1942,6 @@ static struct clk usb_l4_ick = { | |||
| 2018 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1942 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 2019 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | 1943 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
| 2020 | .clksel = usb_l4_clksel, | 1944 | .clksel = usb_l4_clksel, |
| 2021 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 2022 | .recalc = &omap2_clksel_recalc, | 1945 | .recalc = &omap2_clksel_recalc, |
| 2023 | }; | 1946 | }; |
| 2024 | 1947 | ||
| @@ -2028,98 +1951,87 @@ static struct clk usb_l4_ick = { | |||
| 2028 | 1951 | ||
| 2029 | static struct clk security_l4_ick2 = { | 1952 | static struct clk security_l4_ick2 = { |
| 2030 | .name = "security_l4_ick2", | 1953 | .name = "security_l4_ick2", |
| 1954 | .ops = &clkops_null, | ||
| 2031 | .parent = &l4_ick, | 1955 | .parent = &l4_ick, |
| 2032 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2033 | PARENT_CONTROLS_CLOCK, | ||
| 2034 | .recalc = &followparent_recalc, | 1956 | .recalc = &followparent_recalc, |
| 2035 | }; | 1957 | }; |
| 2036 | 1958 | ||
| 2037 | static struct clk aes1_ick = { | 1959 | static struct clk aes1_ick = { |
| 2038 | .name = "aes1_ick", | 1960 | .name = "aes1_ick", |
| 1961 | .ops = &clkops_omap2_dflt_wait, | ||
| 2039 | .parent = &security_l4_ick2, | 1962 | .parent = &security_l4_ick2, |
| 2040 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1963 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2041 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | 1964 | .enable_bit = OMAP3430_EN_AES1_SHIFT, |
| 2042 | .flags = CLOCK_IN_OMAP343X, | ||
| 2043 | .recalc = &followparent_recalc, | 1965 | .recalc = &followparent_recalc, |
| 2044 | }; | 1966 | }; |
| 2045 | 1967 | ||
| 2046 | static struct clk rng_ick = { | 1968 | static struct clk rng_ick = { |
| 2047 | .name = "rng_ick", | 1969 | .name = "rng_ick", |
| 1970 | .ops = &clkops_omap2_dflt_wait, | ||
| 2048 | .parent = &security_l4_ick2, | 1971 | .parent = &security_l4_ick2, |
| 2049 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2050 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | 1973 | .enable_bit = OMAP3430_EN_RNG_SHIFT, |
| 2051 | .flags = CLOCK_IN_OMAP343X, | ||
| 2052 | .recalc = &followparent_recalc, | 1974 | .recalc = &followparent_recalc, |
| 2053 | }; | 1975 | }; |
| 2054 | 1976 | ||
| 2055 | static struct clk sha11_ick = { | 1977 | static struct clk sha11_ick = { |
| 2056 | .name = "sha11_ick", | 1978 | .name = "sha11_ick", |
| 1979 | .ops = &clkops_omap2_dflt_wait, | ||
| 2057 | .parent = &security_l4_ick2, | 1980 | .parent = &security_l4_ick2, |
| 2058 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1981 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2059 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | 1982 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, |
| 2060 | .flags = CLOCK_IN_OMAP343X, | ||
| 2061 | .recalc = &followparent_recalc, | 1983 | .recalc = &followparent_recalc, |
| 2062 | }; | 1984 | }; |
| 2063 | 1985 | ||
| 2064 | static struct clk des1_ick = { | 1986 | static struct clk des1_ick = { |
| 2065 | .name = "des1_ick", | 1987 | .name = "des1_ick", |
| 1988 | .ops = &clkops_omap2_dflt_wait, | ||
| 2066 | .parent = &security_l4_ick2, | 1989 | .parent = &security_l4_ick2, |
| 2067 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1990 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2068 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | 1991 | .enable_bit = OMAP3430_EN_DES1_SHIFT, |
| 2069 | .flags = CLOCK_IN_OMAP343X, | ||
| 2070 | .recalc = &followparent_recalc, | 1992 | .recalc = &followparent_recalc, |
| 2071 | }; | 1993 | }; |
| 2072 | 1994 | ||
| 2073 | /* DSS */ | 1995 | /* DSS */ |
| 2074 | static const struct clksel dss1_alwon_fck_clksel[] = { | ||
| 2075 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 2076 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, | ||
| 2077 | { .parent = NULL } | ||
| 2078 | }; | ||
| 2079 | |||
| 2080 | static struct clk dss1_alwon_fck = { | 1996 | static struct clk dss1_alwon_fck = { |
| 2081 | .name = "dss1_alwon_fck", | 1997 | .name = "dss1_alwon_fck", |
| 1998 | .ops = &clkops_omap2_dflt, | ||
| 2082 | .parent = &dpll4_m4x2_ck, | 1999 | .parent = &dpll4_m4x2_ck, |
| 2083 | .init = &omap2_init_clksel_parent, | ||
| 2084 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2000 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2085 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | 2001 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, |
| 2086 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 2087 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 2088 | .clksel = dss1_alwon_fck_clksel, | ||
| 2089 | .flags = CLOCK_IN_OMAP343X, | ||
| 2090 | .clkdm_name = "dss_clkdm", | 2002 | .clkdm_name = "dss_clkdm", |
| 2091 | .recalc = &omap2_clksel_recalc, | 2003 | .recalc = &followparent_recalc, |
| 2092 | }; | 2004 | }; |
| 2093 | 2005 | ||
| 2094 | static struct clk dss_tv_fck = { | 2006 | static struct clk dss_tv_fck = { |
| 2095 | .name = "dss_tv_fck", | 2007 | .name = "dss_tv_fck", |
| 2008 | .ops = &clkops_omap2_dflt, | ||
| 2096 | .parent = &omap_54m_fck, | 2009 | .parent = &omap_54m_fck, |
| 2097 | .init = &omap2_init_clk_clkdm, | 2010 | .init = &omap2_init_clk_clkdm, |
| 2098 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2011 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2099 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2012 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2100 | .flags = CLOCK_IN_OMAP343X, | ||
| 2101 | .clkdm_name = "dss_clkdm", | 2013 | .clkdm_name = "dss_clkdm", |
| 2102 | .recalc = &followparent_recalc, | 2014 | .recalc = &followparent_recalc, |
| 2103 | }; | 2015 | }; |
| 2104 | 2016 | ||
| 2105 | static struct clk dss_96m_fck = { | 2017 | static struct clk dss_96m_fck = { |
| 2106 | .name = "dss_96m_fck", | 2018 | .name = "dss_96m_fck", |
| 2019 | .ops = &clkops_omap2_dflt, | ||
| 2107 | .parent = &omap_96m_fck, | 2020 | .parent = &omap_96m_fck, |
| 2108 | .init = &omap2_init_clk_clkdm, | 2021 | .init = &omap2_init_clk_clkdm, |
| 2109 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2022 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2110 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2023 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2111 | .flags = CLOCK_IN_OMAP343X, | ||
| 2112 | .clkdm_name = "dss_clkdm", | 2024 | .clkdm_name = "dss_clkdm", |
| 2113 | .recalc = &followparent_recalc, | 2025 | .recalc = &followparent_recalc, |
| 2114 | }; | 2026 | }; |
| 2115 | 2027 | ||
| 2116 | static struct clk dss2_alwon_fck = { | 2028 | static struct clk dss2_alwon_fck = { |
| 2117 | .name = "dss2_alwon_fck", | 2029 | .name = "dss2_alwon_fck", |
| 2030 | .ops = &clkops_omap2_dflt, | ||
| 2118 | .parent = &sys_ck, | 2031 | .parent = &sys_ck, |
| 2119 | .init = &omap2_init_clk_clkdm, | 2032 | .init = &omap2_init_clk_clkdm, |
| 2120 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2033 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2121 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | 2034 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
| 2122 | .flags = CLOCK_IN_OMAP343X, | ||
| 2123 | .clkdm_name = "dss_clkdm", | 2035 | .clkdm_name = "dss_clkdm", |
| 2124 | .recalc = &followparent_recalc, | 2036 | .recalc = &followparent_recalc, |
| 2125 | }; | 2037 | }; |
| @@ -2127,45 +2039,46 @@ static struct clk dss2_alwon_fck = { | |||
| 2127 | static struct clk dss_ick = { | 2039 | static struct clk dss_ick = { |
| 2128 | /* Handles both L3 and L4 clocks */ | 2040 | /* Handles both L3 and L4 clocks */ |
| 2129 | .name = "dss_ick", | 2041 | .name = "dss_ick", |
| 2042 | .ops = &clkops_omap2_dflt, | ||
| 2130 | .parent = &l4_ick, | 2043 | .parent = &l4_ick, |
| 2131 | .init = &omap2_init_clk_clkdm, | 2044 | .init = &omap2_init_clk_clkdm, |
| 2132 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2045 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
| 2133 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2046 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
| 2134 | .flags = CLOCK_IN_OMAP343X, | ||
| 2135 | .clkdm_name = "dss_clkdm", | 2047 | .clkdm_name = "dss_clkdm", |
| 2136 | .recalc = &followparent_recalc, | 2048 | .recalc = &followparent_recalc, |
| 2137 | }; | 2049 | }; |
| 2138 | 2050 | ||
| 2139 | /* CAM */ | 2051 | /* CAM */ |
| 2140 | 2052 | ||
| 2141 | static const struct clksel cam_mclk_clksel[] = { | ||
| 2142 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 2143 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, | ||
| 2144 | { .parent = NULL } | ||
| 2145 | }; | ||
| 2146 | |||
| 2147 | static struct clk cam_mclk = { | 2053 | static struct clk cam_mclk = { |
| 2148 | .name = "cam_mclk", | 2054 | .name = "cam_mclk", |
| 2055 | .ops = &clkops_omap2_dflt_wait, | ||
| 2149 | .parent = &dpll4_m5x2_ck, | 2056 | .parent = &dpll4_m5x2_ck, |
| 2150 | .init = &omap2_init_clksel_parent, | ||
| 2151 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 2152 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 2153 | .clksel = cam_mclk_clksel, | ||
| 2154 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | 2057 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2155 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2058 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2156 | .flags = CLOCK_IN_OMAP343X, | ||
| 2157 | .clkdm_name = "cam_clkdm", | 2059 | .clkdm_name = "cam_clkdm", |
| 2158 | .recalc = &omap2_clksel_recalc, | 2060 | .recalc = &followparent_recalc, |
| 2159 | }; | 2061 | }; |
| 2160 | 2062 | ||
| 2161 | static struct clk cam_ick = { | 2063 | static struct clk cam_ick = { |
| 2162 | /* Handles both L3 and L4 clocks */ | 2064 | /* Handles both L3 and L4 clocks */ |
| 2163 | .name = "cam_ick", | 2065 | .name = "cam_ick", |
| 2066 | .ops = &clkops_omap2_dflt_wait, | ||
| 2164 | .parent = &l4_ick, | 2067 | .parent = &l4_ick, |
| 2165 | .init = &omap2_init_clk_clkdm, | 2068 | .init = &omap2_init_clk_clkdm, |
| 2166 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | 2069 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
| 2167 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2070 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2168 | .flags = CLOCK_IN_OMAP343X, | 2071 | .clkdm_name = "cam_clkdm", |
| 2072 | .recalc = &followparent_recalc, | ||
| 2073 | }; | ||
| 2074 | |||
| 2075 | static struct clk csi2_96m_fck = { | ||
| 2076 | .name = "csi2_96m_fck", | ||
| 2077 | .ops = &clkops_omap2_dflt_wait, | ||
| 2078 | .parent = &core_96m_fck, | ||
| 2079 | .init = &omap2_init_clk_clkdm, | ||
| 2080 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | ||
| 2081 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | ||
| 2169 | .clkdm_name = "cam_clkdm", | 2082 | .clkdm_name = "cam_clkdm", |
| 2170 | .recalc = &followparent_recalc, | 2083 | .recalc = &followparent_recalc, |
| 2171 | }; | 2084 | }; |
| @@ -2174,22 +2087,22 @@ static struct clk cam_ick = { | |||
| 2174 | 2087 | ||
| 2175 | static struct clk usbhost_120m_fck = { | 2088 | static struct clk usbhost_120m_fck = { |
| 2176 | .name = "usbhost_120m_fck", | 2089 | .name = "usbhost_120m_fck", |
| 2177 | .parent = &omap_120m_fck, | 2090 | .ops = &clkops_omap2_dflt_wait, |
| 2091 | .parent = &dpll5_m2_ck, | ||
| 2178 | .init = &omap2_init_clk_clkdm, | 2092 | .init = &omap2_init_clk_clkdm, |
| 2179 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2093 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2180 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | 2094 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
| 2181 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2182 | .clkdm_name = "usbhost_clkdm", | 2095 | .clkdm_name = "usbhost_clkdm", |
| 2183 | .recalc = &followparent_recalc, | 2096 | .recalc = &followparent_recalc, |
| 2184 | }; | 2097 | }; |
| 2185 | 2098 | ||
| 2186 | static struct clk usbhost_48m_fck = { | 2099 | static struct clk usbhost_48m_fck = { |
| 2187 | .name = "usbhost_48m_fck", | 2100 | .name = "usbhost_48m_fck", |
| 2101 | .ops = &clkops_omap2_dflt_wait, | ||
| 2188 | .parent = &omap_48m_fck, | 2102 | .parent = &omap_48m_fck, |
| 2189 | .init = &omap2_init_clk_clkdm, | 2103 | .init = &omap2_init_clk_clkdm, |
| 2190 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2104 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2191 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | 2105 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
| 2192 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2193 | .clkdm_name = "usbhost_clkdm", | 2106 | .clkdm_name = "usbhost_clkdm", |
| 2194 | .recalc = &followparent_recalc, | 2107 | .recalc = &followparent_recalc, |
| 2195 | }; | 2108 | }; |
| @@ -2197,22 +2110,11 @@ static struct clk usbhost_48m_fck = { | |||
| 2197 | static struct clk usbhost_ick = { | 2110 | static struct clk usbhost_ick = { |
| 2198 | /* Handles both L3 and L4 clocks */ | 2111 | /* Handles both L3 and L4 clocks */ |
| 2199 | .name = "usbhost_ick", | 2112 | .name = "usbhost_ick", |
| 2113 | .ops = &clkops_omap2_dflt_wait, | ||
| 2200 | .parent = &l4_ick, | 2114 | .parent = &l4_ick, |
| 2201 | .init = &omap2_init_clk_clkdm, | 2115 | .init = &omap2_init_clk_clkdm, |
| 2202 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | 2116 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
| 2203 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | 2117 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
| 2204 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2205 | .clkdm_name = "usbhost_clkdm", | ||
| 2206 | .recalc = &followparent_recalc, | ||
| 2207 | }; | ||
| 2208 | |||
| 2209 | static struct clk usbhost_sar_fck = { | ||
| 2210 | .name = "usbhost_sar_fck", | ||
| 2211 | .parent = &osc_sys_ck, | ||
| 2212 | .init = &omap2_init_clk_clkdm, | ||
| 2213 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), | ||
| 2214 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, | ||
| 2215 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2216 | .clkdm_name = "usbhost_clkdm", | 2118 | .clkdm_name = "usbhost_clkdm", |
| 2217 | .recalc = &followparent_recalc, | 2119 | .recalc = &followparent_recalc, |
| 2218 | }; | 2120 | }; |
| @@ -2237,7 +2139,7 @@ static const struct clksel_rate usim_120m_rates[] = { | |||
| 2237 | 2139 | ||
| 2238 | static const struct clksel usim_clksel[] = { | 2140 | static const struct clksel usim_clksel[] = { |
| 2239 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | 2141 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, |
| 2240 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, | 2142 | { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, |
| 2241 | { .parent = &sys_ck, .rates = div2_rates }, | 2143 | { .parent = &sys_ck, .rates = div2_rates }, |
| 2242 | { .parent = NULL }, | 2144 | { .parent = NULL }, |
| 2243 | }; | 2145 | }; |
| @@ -2245,63 +2147,63 @@ static const struct clksel usim_clksel[] = { | |||
| 2245 | /* 3430ES2 only */ | 2147 | /* 3430ES2 only */ |
| 2246 | static struct clk usim_fck = { | 2148 | static struct clk usim_fck = { |
| 2247 | .name = "usim_fck", | 2149 | .name = "usim_fck", |
| 2150 | .ops = &clkops_omap2_dflt_wait, | ||
| 2248 | .init = &omap2_init_clksel_parent, | 2151 | .init = &omap2_init_clksel_parent, |
| 2249 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2152 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2250 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | 2153 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2251 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | 2154 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2252 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | 2155 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, |
| 2253 | .clksel = usim_clksel, | 2156 | .clksel = usim_clksel, |
| 2254 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2255 | .recalc = &omap2_clksel_recalc, | 2157 | .recalc = &omap2_clksel_recalc, |
| 2256 | }; | 2158 | }; |
| 2257 | 2159 | ||
| 2258 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ | 2160 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
| 2259 | static struct clk gpt1_fck = { | 2161 | static struct clk gpt1_fck = { |
| 2260 | .name = "gpt1_fck", | 2162 | .name = "gpt1_fck", |
| 2163 | .ops = &clkops_omap2_dflt_wait, | ||
| 2261 | .init = &omap2_init_clksel_parent, | 2164 | .init = &omap2_init_clksel_parent, |
| 2262 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2165 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2263 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | 2166 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2264 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | 2167 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2265 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | 2168 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, |
| 2266 | .clksel = omap343x_gpt_clksel, | 2169 | .clksel = omap343x_gpt_clksel, |
| 2267 | .flags = CLOCK_IN_OMAP343X, | ||
| 2268 | .clkdm_name = "wkup_clkdm", | 2170 | .clkdm_name = "wkup_clkdm", |
| 2269 | .recalc = &omap2_clksel_recalc, | 2171 | .recalc = &omap2_clksel_recalc, |
| 2270 | }; | 2172 | }; |
| 2271 | 2173 | ||
| 2272 | static struct clk wkup_32k_fck = { | 2174 | static struct clk wkup_32k_fck = { |
| 2273 | .name = "wkup_32k_fck", | 2175 | .name = "wkup_32k_fck", |
| 2176 | .ops = &clkops_null, | ||
| 2274 | .init = &omap2_init_clk_clkdm, | 2177 | .init = &omap2_init_clk_clkdm, |
| 2275 | .parent = &omap_32k_fck, | 2178 | .parent = &omap_32k_fck, |
| 2276 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2277 | .clkdm_name = "wkup_clkdm", | 2179 | .clkdm_name = "wkup_clkdm", |
| 2278 | .recalc = &followparent_recalc, | 2180 | .recalc = &followparent_recalc, |
| 2279 | }; | 2181 | }; |
| 2280 | 2182 | ||
| 2281 | static struct clk gpio1_dbck = { | 2183 | static struct clk gpio1_dbck = { |
| 2282 | .name = "gpio1_dbck", | 2184 | .name = "gpio1_dbck", |
| 2185 | .ops = &clkops_omap2_dflt_wait, | ||
| 2283 | .parent = &wkup_32k_fck, | 2186 | .parent = &wkup_32k_fck, |
| 2284 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2187 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2285 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2188 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2286 | .flags = CLOCK_IN_OMAP343X, | ||
| 2287 | .clkdm_name = "wkup_clkdm", | 2189 | .clkdm_name = "wkup_clkdm", |
| 2288 | .recalc = &followparent_recalc, | 2190 | .recalc = &followparent_recalc, |
| 2289 | }; | 2191 | }; |
| 2290 | 2192 | ||
| 2291 | static struct clk wdt2_fck = { | 2193 | static struct clk wdt2_fck = { |
| 2292 | .name = "wdt2_fck", | 2194 | .name = "wdt2_fck", |
| 2195 | .ops = &clkops_omap2_dflt_wait, | ||
| 2293 | .parent = &wkup_32k_fck, | 2196 | .parent = &wkup_32k_fck, |
| 2294 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2197 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2295 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | 2198 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2296 | .flags = CLOCK_IN_OMAP343X, | ||
| 2297 | .clkdm_name = "wkup_clkdm", | 2199 | .clkdm_name = "wkup_clkdm", |
| 2298 | .recalc = &followparent_recalc, | 2200 | .recalc = &followparent_recalc, |
| 2299 | }; | 2201 | }; |
| 2300 | 2202 | ||
| 2301 | static struct clk wkup_l4_ick = { | 2203 | static struct clk wkup_l4_ick = { |
| 2302 | .name = "wkup_l4_ick", | 2204 | .name = "wkup_l4_ick", |
| 2205 | .ops = &clkops_null, | ||
| 2303 | .parent = &sys_ck, | 2206 | .parent = &sys_ck, |
| 2304 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2305 | .clkdm_name = "wkup_clkdm", | 2207 | .clkdm_name = "wkup_clkdm", |
| 2306 | .recalc = &followparent_recalc, | 2208 | .recalc = &followparent_recalc, |
| 2307 | }; | 2209 | }; |
| @@ -2310,50 +2212,50 @@ static struct clk wkup_l4_ick = { | |||
| 2310 | /* Never specifically named in the TRM, so we have to infer a likely name */ | 2212 | /* Never specifically named in the TRM, so we have to infer a likely name */ |
| 2311 | static struct clk usim_ick = { | 2213 | static struct clk usim_ick = { |
| 2312 | .name = "usim_ick", | 2214 | .name = "usim_ick", |
| 2215 | .ops = &clkops_omap2_dflt_wait, | ||
| 2313 | .parent = &wkup_l4_ick, | 2216 | .parent = &wkup_l4_ick, |
| 2314 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2217 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2315 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | 2218 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2316 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2317 | .clkdm_name = "wkup_clkdm", | 2219 | .clkdm_name = "wkup_clkdm", |
| 2318 | .recalc = &followparent_recalc, | 2220 | .recalc = &followparent_recalc, |
| 2319 | }; | 2221 | }; |
| 2320 | 2222 | ||
| 2321 | static struct clk wdt2_ick = { | 2223 | static struct clk wdt2_ick = { |
| 2322 | .name = "wdt2_ick", | 2224 | .name = "wdt2_ick", |
| 2225 | .ops = &clkops_omap2_dflt_wait, | ||
| 2323 | .parent = &wkup_l4_ick, | 2226 | .parent = &wkup_l4_ick, |
| 2324 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2227 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2325 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | 2228 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2326 | .flags = CLOCK_IN_OMAP343X, | ||
| 2327 | .clkdm_name = "wkup_clkdm", | 2229 | .clkdm_name = "wkup_clkdm", |
| 2328 | .recalc = &followparent_recalc, | 2230 | .recalc = &followparent_recalc, |
| 2329 | }; | 2231 | }; |
| 2330 | 2232 | ||
| 2331 | static struct clk wdt1_ick = { | 2233 | static struct clk wdt1_ick = { |
| 2332 | .name = "wdt1_ick", | 2234 | .name = "wdt1_ick", |
| 2235 | .ops = &clkops_omap2_dflt_wait, | ||
| 2333 | .parent = &wkup_l4_ick, | 2236 | .parent = &wkup_l4_ick, |
| 2334 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2237 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2335 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | 2238 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
| 2336 | .flags = CLOCK_IN_OMAP343X, | ||
| 2337 | .clkdm_name = "wkup_clkdm", | 2239 | .clkdm_name = "wkup_clkdm", |
| 2338 | .recalc = &followparent_recalc, | 2240 | .recalc = &followparent_recalc, |
| 2339 | }; | 2241 | }; |
| 2340 | 2242 | ||
| 2341 | static struct clk gpio1_ick = { | 2243 | static struct clk gpio1_ick = { |
| 2342 | .name = "gpio1_ick", | 2244 | .name = "gpio1_ick", |
| 2245 | .ops = &clkops_omap2_dflt_wait, | ||
| 2343 | .parent = &wkup_l4_ick, | 2246 | .parent = &wkup_l4_ick, |
| 2344 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2247 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2345 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2248 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2346 | .flags = CLOCK_IN_OMAP343X, | ||
| 2347 | .clkdm_name = "wkup_clkdm", | 2249 | .clkdm_name = "wkup_clkdm", |
| 2348 | .recalc = &followparent_recalc, | 2250 | .recalc = &followparent_recalc, |
| 2349 | }; | 2251 | }; |
| 2350 | 2252 | ||
| 2351 | static struct clk omap_32ksync_ick = { | 2253 | static struct clk omap_32ksync_ick = { |
| 2352 | .name = "omap_32ksync_ick", | 2254 | .name = "omap_32ksync_ick", |
| 2255 | .ops = &clkops_omap2_dflt_wait, | ||
| 2353 | .parent = &wkup_l4_ick, | 2256 | .parent = &wkup_l4_ick, |
| 2354 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2257 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2355 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | 2258 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
| 2356 | .flags = CLOCK_IN_OMAP343X, | ||
| 2357 | .clkdm_name = "wkup_clkdm", | 2259 | .clkdm_name = "wkup_clkdm", |
| 2358 | .recalc = &followparent_recalc, | 2260 | .recalc = &followparent_recalc, |
| 2359 | }; | 2261 | }; |
| @@ -2361,20 +2263,20 @@ static struct clk omap_32ksync_ick = { | |||
| 2361 | /* XXX This clock no longer exists in 3430 TRM rev F */ | 2263 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
| 2362 | static struct clk gpt12_ick = { | 2264 | static struct clk gpt12_ick = { |
| 2363 | .name = "gpt12_ick", | 2265 | .name = "gpt12_ick", |
| 2266 | .ops = &clkops_omap2_dflt_wait, | ||
| 2364 | .parent = &wkup_l4_ick, | 2267 | .parent = &wkup_l4_ick, |
| 2365 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2268 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2366 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | 2269 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
| 2367 | .flags = CLOCK_IN_OMAP343X, | ||
| 2368 | .clkdm_name = "wkup_clkdm", | 2270 | .clkdm_name = "wkup_clkdm", |
| 2369 | .recalc = &followparent_recalc, | 2271 | .recalc = &followparent_recalc, |
| 2370 | }; | 2272 | }; |
| 2371 | 2273 | ||
| 2372 | static struct clk gpt1_ick = { | 2274 | static struct clk gpt1_ick = { |
| 2373 | .name = "gpt1_ick", | 2275 | .name = "gpt1_ick", |
| 2276 | .ops = &clkops_omap2_dflt_wait, | ||
| 2374 | .parent = &wkup_l4_ick, | 2277 | .parent = &wkup_l4_ick, |
| 2375 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2278 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2376 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | 2279 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2377 | .flags = CLOCK_IN_OMAP343X, | ||
| 2378 | .clkdm_name = "wkup_clkdm", | 2280 | .clkdm_name = "wkup_clkdm", |
| 2379 | .recalc = &followparent_recalc, | 2281 | .recalc = &followparent_recalc, |
| 2380 | }; | 2282 | }; |
| @@ -2385,406 +2287,404 @@ static struct clk gpt1_ick = { | |||
| 2385 | 2287 | ||
| 2386 | static struct clk per_96m_fck = { | 2288 | static struct clk per_96m_fck = { |
| 2387 | .name = "per_96m_fck", | 2289 | .name = "per_96m_fck", |
| 2290 | .ops = &clkops_null, | ||
| 2388 | .parent = &omap_96m_alwon_fck, | 2291 | .parent = &omap_96m_alwon_fck, |
| 2389 | .init = &omap2_init_clk_clkdm, | 2292 | .init = &omap2_init_clk_clkdm, |
| 2390 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2391 | PARENT_CONTROLS_CLOCK, | ||
| 2392 | .clkdm_name = "per_clkdm", | 2293 | .clkdm_name = "per_clkdm", |
| 2393 | .recalc = &followparent_recalc, | 2294 | .recalc = &followparent_recalc, |
| 2394 | }; | 2295 | }; |
| 2395 | 2296 | ||
| 2396 | static struct clk per_48m_fck = { | 2297 | static struct clk per_48m_fck = { |
| 2397 | .name = "per_48m_fck", | 2298 | .name = "per_48m_fck", |
| 2299 | .ops = &clkops_null, | ||
| 2398 | .parent = &omap_48m_fck, | 2300 | .parent = &omap_48m_fck, |
| 2399 | .init = &omap2_init_clk_clkdm, | 2301 | .init = &omap2_init_clk_clkdm, |
| 2400 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2401 | PARENT_CONTROLS_CLOCK, | ||
| 2402 | .clkdm_name = "per_clkdm", | 2302 | .clkdm_name = "per_clkdm", |
| 2403 | .recalc = &followparent_recalc, | 2303 | .recalc = &followparent_recalc, |
| 2404 | }; | 2304 | }; |
| 2405 | 2305 | ||
| 2406 | static struct clk uart3_fck = { | 2306 | static struct clk uart3_fck = { |
| 2407 | .name = "uart3_fck", | 2307 | .name = "uart3_fck", |
| 2308 | .ops = &clkops_omap2_dflt_wait, | ||
| 2408 | .parent = &per_48m_fck, | 2309 | .parent = &per_48m_fck, |
| 2409 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2310 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2410 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | 2311 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2411 | .flags = CLOCK_IN_OMAP343X, | ||
| 2412 | .clkdm_name = "per_clkdm", | 2312 | .clkdm_name = "per_clkdm", |
| 2413 | .recalc = &followparent_recalc, | 2313 | .recalc = &followparent_recalc, |
| 2414 | }; | 2314 | }; |
| 2415 | 2315 | ||
| 2416 | static struct clk gpt2_fck = { | 2316 | static struct clk gpt2_fck = { |
| 2417 | .name = "gpt2_fck", | 2317 | .name = "gpt2_fck", |
| 2318 | .ops = &clkops_omap2_dflt_wait, | ||
| 2418 | .init = &omap2_init_clksel_parent, | 2319 | .init = &omap2_init_clksel_parent, |
| 2419 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2320 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2420 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | 2321 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2421 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2322 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2422 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | 2323 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, |
| 2423 | .clksel = omap343x_gpt_clksel, | 2324 | .clksel = omap343x_gpt_clksel, |
| 2424 | .flags = CLOCK_IN_OMAP343X, | ||
| 2425 | .clkdm_name = "per_clkdm", | 2325 | .clkdm_name = "per_clkdm", |
| 2426 | .recalc = &omap2_clksel_recalc, | 2326 | .recalc = &omap2_clksel_recalc, |
| 2427 | }; | 2327 | }; |
| 2428 | 2328 | ||
| 2429 | static struct clk gpt3_fck = { | 2329 | static struct clk gpt3_fck = { |
| 2430 | .name = "gpt3_fck", | 2330 | .name = "gpt3_fck", |
| 2331 | .ops = &clkops_omap2_dflt_wait, | ||
| 2431 | .init = &omap2_init_clksel_parent, | 2332 | .init = &omap2_init_clksel_parent, |
| 2432 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2333 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2433 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | 2334 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2434 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2335 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2435 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | 2336 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, |
| 2436 | .clksel = omap343x_gpt_clksel, | 2337 | .clksel = omap343x_gpt_clksel, |
| 2437 | .flags = CLOCK_IN_OMAP343X, | ||
| 2438 | .clkdm_name = "per_clkdm", | 2338 | .clkdm_name = "per_clkdm", |
| 2439 | .recalc = &omap2_clksel_recalc, | 2339 | .recalc = &omap2_clksel_recalc, |
| 2440 | }; | 2340 | }; |
| 2441 | 2341 | ||
| 2442 | static struct clk gpt4_fck = { | 2342 | static struct clk gpt4_fck = { |
| 2443 | .name = "gpt4_fck", | 2343 | .name = "gpt4_fck", |
| 2344 | .ops = &clkops_omap2_dflt_wait, | ||
| 2444 | .init = &omap2_init_clksel_parent, | 2345 | .init = &omap2_init_clksel_parent, |
| 2445 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2346 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2446 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | 2347 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2447 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2348 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2448 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | 2349 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, |
| 2449 | .clksel = omap343x_gpt_clksel, | 2350 | .clksel = omap343x_gpt_clksel, |
| 2450 | .flags = CLOCK_IN_OMAP343X, | ||
| 2451 | .clkdm_name = "per_clkdm", | 2351 | .clkdm_name = "per_clkdm", |
| 2452 | .recalc = &omap2_clksel_recalc, | 2352 | .recalc = &omap2_clksel_recalc, |
| 2453 | }; | 2353 | }; |
| 2454 | 2354 | ||
| 2455 | static struct clk gpt5_fck = { | 2355 | static struct clk gpt5_fck = { |
| 2456 | .name = "gpt5_fck", | 2356 | .name = "gpt5_fck", |
| 2357 | .ops = &clkops_omap2_dflt_wait, | ||
| 2457 | .init = &omap2_init_clksel_parent, | 2358 | .init = &omap2_init_clksel_parent, |
| 2458 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2359 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2459 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | 2360 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2460 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2361 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2461 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | 2362 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, |
| 2462 | .clksel = omap343x_gpt_clksel, | 2363 | .clksel = omap343x_gpt_clksel, |
| 2463 | .flags = CLOCK_IN_OMAP343X, | ||
| 2464 | .clkdm_name = "per_clkdm", | 2364 | .clkdm_name = "per_clkdm", |
| 2465 | .recalc = &omap2_clksel_recalc, | 2365 | .recalc = &omap2_clksel_recalc, |
| 2466 | }; | 2366 | }; |
| 2467 | 2367 | ||
| 2468 | static struct clk gpt6_fck = { | 2368 | static struct clk gpt6_fck = { |
| 2469 | .name = "gpt6_fck", | 2369 | .name = "gpt6_fck", |
| 2370 | .ops = &clkops_omap2_dflt_wait, | ||
| 2470 | .init = &omap2_init_clksel_parent, | 2371 | .init = &omap2_init_clksel_parent, |
| 2471 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2372 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2472 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | 2373 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2473 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2374 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2474 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | 2375 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, |
| 2475 | .clksel = omap343x_gpt_clksel, | 2376 | .clksel = omap343x_gpt_clksel, |
| 2476 | .flags = CLOCK_IN_OMAP343X, | ||
| 2477 | .clkdm_name = "per_clkdm", | 2377 | .clkdm_name = "per_clkdm", |
| 2478 | .recalc = &omap2_clksel_recalc, | 2378 | .recalc = &omap2_clksel_recalc, |
| 2479 | }; | 2379 | }; |
| 2480 | 2380 | ||
| 2481 | static struct clk gpt7_fck = { | 2381 | static struct clk gpt7_fck = { |
| 2482 | .name = "gpt7_fck", | 2382 | .name = "gpt7_fck", |
| 2383 | .ops = &clkops_omap2_dflt_wait, | ||
| 2483 | .init = &omap2_init_clksel_parent, | 2384 | .init = &omap2_init_clksel_parent, |
| 2484 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2385 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2485 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | 2386 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2486 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2387 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2487 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | 2388 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, |
| 2488 | .clksel = omap343x_gpt_clksel, | 2389 | .clksel = omap343x_gpt_clksel, |
| 2489 | .flags = CLOCK_IN_OMAP343X, | ||
| 2490 | .clkdm_name = "per_clkdm", | 2390 | .clkdm_name = "per_clkdm", |
| 2491 | .recalc = &omap2_clksel_recalc, | 2391 | .recalc = &omap2_clksel_recalc, |
| 2492 | }; | 2392 | }; |
| 2493 | 2393 | ||
| 2494 | static struct clk gpt8_fck = { | 2394 | static struct clk gpt8_fck = { |
| 2495 | .name = "gpt8_fck", | 2395 | .name = "gpt8_fck", |
| 2396 | .ops = &clkops_omap2_dflt_wait, | ||
| 2496 | .init = &omap2_init_clksel_parent, | 2397 | .init = &omap2_init_clksel_parent, |
| 2497 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2398 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2498 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | 2399 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2499 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2400 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2500 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | 2401 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, |
| 2501 | .clksel = omap343x_gpt_clksel, | 2402 | .clksel = omap343x_gpt_clksel, |
| 2502 | .flags = CLOCK_IN_OMAP343X, | ||
| 2503 | .clkdm_name = "per_clkdm", | 2403 | .clkdm_name = "per_clkdm", |
| 2504 | .recalc = &omap2_clksel_recalc, | 2404 | .recalc = &omap2_clksel_recalc, |
| 2505 | }; | 2405 | }; |
| 2506 | 2406 | ||
| 2507 | static struct clk gpt9_fck = { | 2407 | static struct clk gpt9_fck = { |
| 2508 | .name = "gpt9_fck", | 2408 | .name = "gpt9_fck", |
| 2409 | .ops = &clkops_omap2_dflt_wait, | ||
| 2509 | .init = &omap2_init_clksel_parent, | 2410 | .init = &omap2_init_clksel_parent, |
| 2510 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2411 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2511 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | 2412 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2512 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2413 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2513 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | 2414 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, |
| 2514 | .clksel = omap343x_gpt_clksel, | 2415 | .clksel = omap343x_gpt_clksel, |
| 2515 | .flags = CLOCK_IN_OMAP343X, | ||
| 2516 | .clkdm_name = "per_clkdm", | 2416 | .clkdm_name = "per_clkdm", |
| 2517 | .recalc = &omap2_clksel_recalc, | 2417 | .recalc = &omap2_clksel_recalc, |
| 2518 | }; | 2418 | }; |
| 2519 | 2419 | ||
| 2520 | static struct clk per_32k_alwon_fck = { | 2420 | static struct clk per_32k_alwon_fck = { |
| 2521 | .name = "per_32k_alwon_fck", | 2421 | .name = "per_32k_alwon_fck", |
| 2422 | .ops = &clkops_null, | ||
| 2522 | .parent = &omap_32k_fck, | 2423 | .parent = &omap_32k_fck, |
| 2523 | .clkdm_name = "per_clkdm", | 2424 | .clkdm_name = "per_clkdm", |
| 2524 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2525 | .recalc = &followparent_recalc, | 2425 | .recalc = &followparent_recalc, |
| 2526 | }; | 2426 | }; |
| 2527 | 2427 | ||
| 2528 | static struct clk gpio6_dbck = { | 2428 | static struct clk gpio6_dbck = { |
| 2529 | .name = "gpio6_dbck", | 2429 | .name = "gpio6_dbck", |
| 2430 | .ops = &clkops_omap2_dflt_wait, | ||
| 2530 | .parent = &per_32k_alwon_fck, | 2431 | .parent = &per_32k_alwon_fck, |
| 2531 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2432 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2532 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2433 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 2533 | .flags = CLOCK_IN_OMAP343X, | ||
| 2534 | .clkdm_name = "per_clkdm", | 2434 | .clkdm_name = "per_clkdm", |
| 2535 | .recalc = &followparent_recalc, | 2435 | .recalc = &followparent_recalc, |
| 2536 | }; | 2436 | }; |
| 2537 | 2437 | ||
| 2538 | static struct clk gpio5_dbck = { | 2438 | static struct clk gpio5_dbck = { |
| 2539 | .name = "gpio5_dbck", | 2439 | .name = "gpio5_dbck", |
| 2440 | .ops = &clkops_omap2_dflt_wait, | ||
| 2540 | .parent = &per_32k_alwon_fck, | 2441 | .parent = &per_32k_alwon_fck, |
| 2541 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2442 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2542 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2443 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 2543 | .flags = CLOCK_IN_OMAP343X, | ||
| 2544 | .clkdm_name = "per_clkdm", | 2444 | .clkdm_name = "per_clkdm", |
| 2545 | .recalc = &followparent_recalc, | 2445 | .recalc = &followparent_recalc, |
| 2546 | }; | 2446 | }; |
| 2547 | 2447 | ||
| 2548 | static struct clk gpio4_dbck = { | 2448 | static struct clk gpio4_dbck = { |
| 2549 | .name = "gpio4_dbck", | 2449 | .name = "gpio4_dbck", |
| 2450 | .ops = &clkops_omap2_dflt_wait, | ||
| 2550 | .parent = &per_32k_alwon_fck, | 2451 | .parent = &per_32k_alwon_fck, |
| 2551 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2452 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2552 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2453 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 2553 | .flags = CLOCK_IN_OMAP343X, | ||
| 2554 | .clkdm_name = "per_clkdm", | 2454 | .clkdm_name = "per_clkdm", |
| 2555 | .recalc = &followparent_recalc, | 2455 | .recalc = &followparent_recalc, |
| 2556 | }; | 2456 | }; |
| 2557 | 2457 | ||
| 2558 | static struct clk gpio3_dbck = { | 2458 | static struct clk gpio3_dbck = { |
| 2559 | .name = "gpio3_dbck", | 2459 | .name = "gpio3_dbck", |
| 2460 | .ops = &clkops_omap2_dflt_wait, | ||
| 2560 | .parent = &per_32k_alwon_fck, | 2461 | .parent = &per_32k_alwon_fck, |
| 2561 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2462 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2562 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2463 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 2563 | .flags = CLOCK_IN_OMAP343X, | ||
| 2564 | .clkdm_name = "per_clkdm", | 2464 | .clkdm_name = "per_clkdm", |
| 2565 | .recalc = &followparent_recalc, | 2465 | .recalc = &followparent_recalc, |
| 2566 | }; | 2466 | }; |
| 2567 | 2467 | ||
| 2568 | static struct clk gpio2_dbck = { | 2468 | static struct clk gpio2_dbck = { |
| 2569 | .name = "gpio2_dbck", | 2469 | .name = "gpio2_dbck", |
| 2470 | .ops = &clkops_omap2_dflt_wait, | ||
| 2570 | .parent = &per_32k_alwon_fck, | 2471 | .parent = &per_32k_alwon_fck, |
| 2571 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2472 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2572 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2473 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 2573 | .flags = CLOCK_IN_OMAP343X, | ||
| 2574 | .clkdm_name = "per_clkdm", | 2474 | .clkdm_name = "per_clkdm", |
| 2575 | .recalc = &followparent_recalc, | 2475 | .recalc = &followparent_recalc, |
| 2576 | }; | 2476 | }; |
| 2577 | 2477 | ||
| 2578 | static struct clk wdt3_fck = { | 2478 | static struct clk wdt3_fck = { |
| 2579 | .name = "wdt3_fck", | 2479 | .name = "wdt3_fck", |
| 2480 | .ops = &clkops_omap2_dflt_wait, | ||
| 2580 | .parent = &per_32k_alwon_fck, | 2481 | .parent = &per_32k_alwon_fck, |
| 2581 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2482 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2582 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | 2483 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2583 | .flags = CLOCK_IN_OMAP343X, | ||
| 2584 | .clkdm_name = "per_clkdm", | 2484 | .clkdm_name = "per_clkdm", |
| 2585 | .recalc = &followparent_recalc, | 2485 | .recalc = &followparent_recalc, |
| 2586 | }; | 2486 | }; |
| 2587 | 2487 | ||
| 2588 | static struct clk per_l4_ick = { | 2488 | static struct clk per_l4_ick = { |
| 2589 | .name = "per_l4_ick", | 2489 | .name = "per_l4_ick", |
| 2490 | .ops = &clkops_null, | ||
| 2590 | .parent = &l4_ick, | 2491 | .parent = &l4_ick, |
| 2591 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2592 | PARENT_CONTROLS_CLOCK, | ||
| 2593 | .clkdm_name = "per_clkdm", | 2492 | .clkdm_name = "per_clkdm", |
| 2594 | .recalc = &followparent_recalc, | 2493 | .recalc = &followparent_recalc, |
| 2595 | }; | 2494 | }; |
| 2596 | 2495 | ||
| 2597 | static struct clk gpio6_ick = { | 2496 | static struct clk gpio6_ick = { |
| 2598 | .name = "gpio6_ick", | 2497 | .name = "gpio6_ick", |
| 2498 | .ops = &clkops_omap2_dflt_wait, | ||
| 2599 | .parent = &per_l4_ick, | 2499 | .parent = &per_l4_ick, |
| 2600 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2500 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2601 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2501 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 2602 | .flags = CLOCK_IN_OMAP343X, | ||
| 2603 | .clkdm_name = "per_clkdm", | 2502 | .clkdm_name = "per_clkdm", |
| 2604 | .recalc = &followparent_recalc, | 2503 | .recalc = &followparent_recalc, |
| 2605 | }; | 2504 | }; |
| 2606 | 2505 | ||
| 2607 | static struct clk gpio5_ick = { | 2506 | static struct clk gpio5_ick = { |
| 2608 | .name = "gpio5_ick", | 2507 | .name = "gpio5_ick", |
| 2508 | .ops = &clkops_omap2_dflt_wait, | ||
| 2609 | .parent = &per_l4_ick, | 2509 | .parent = &per_l4_ick, |
| 2610 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2510 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2611 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2511 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 2612 | .flags = CLOCK_IN_OMAP343X, | ||
| 2613 | .clkdm_name = "per_clkdm", | 2512 | .clkdm_name = "per_clkdm", |
| 2614 | .recalc = &followparent_recalc, | 2513 | .recalc = &followparent_recalc, |
| 2615 | }; | 2514 | }; |
| 2616 | 2515 | ||
| 2617 | static struct clk gpio4_ick = { | 2516 | static struct clk gpio4_ick = { |
| 2618 | .name = "gpio4_ick", | 2517 | .name = "gpio4_ick", |
| 2518 | .ops = &clkops_omap2_dflt_wait, | ||
| 2619 | .parent = &per_l4_ick, | 2519 | .parent = &per_l4_ick, |
| 2620 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2520 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2621 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2521 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 2622 | .flags = CLOCK_IN_OMAP343X, | ||
| 2623 | .clkdm_name = "per_clkdm", | 2522 | .clkdm_name = "per_clkdm", |
| 2624 | .recalc = &followparent_recalc, | 2523 | .recalc = &followparent_recalc, |
| 2625 | }; | 2524 | }; |
| 2626 | 2525 | ||
| 2627 | static struct clk gpio3_ick = { | 2526 | static struct clk gpio3_ick = { |
| 2628 | .name = "gpio3_ick", | 2527 | .name = "gpio3_ick", |
| 2528 | .ops = &clkops_omap2_dflt_wait, | ||
| 2629 | .parent = &per_l4_ick, | 2529 | .parent = &per_l4_ick, |
| 2630 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2530 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2631 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2531 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 2632 | .flags = CLOCK_IN_OMAP343X, | ||
| 2633 | .clkdm_name = "per_clkdm", | 2532 | .clkdm_name = "per_clkdm", |
| 2634 | .recalc = &followparent_recalc, | 2533 | .recalc = &followparent_recalc, |
| 2635 | }; | 2534 | }; |
| 2636 | 2535 | ||
| 2637 | static struct clk gpio2_ick = { | 2536 | static struct clk gpio2_ick = { |
| 2638 | .name = "gpio2_ick", | 2537 | .name = "gpio2_ick", |
| 2538 | .ops = &clkops_omap2_dflt_wait, | ||
| 2639 | .parent = &per_l4_ick, | 2539 | .parent = &per_l4_ick, |
| 2640 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2540 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2641 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2541 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 2642 | .flags = CLOCK_IN_OMAP343X, | ||
| 2643 | .clkdm_name = "per_clkdm", | 2542 | .clkdm_name = "per_clkdm", |
| 2644 | .recalc = &followparent_recalc, | 2543 | .recalc = &followparent_recalc, |
| 2645 | }; | 2544 | }; |
| 2646 | 2545 | ||
| 2647 | static struct clk wdt3_ick = { | 2546 | static struct clk wdt3_ick = { |
| 2648 | .name = "wdt3_ick", | 2547 | .name = "wdt3_ick", |
| 2548 | .ops = &clkops_omap2_dflt_wait, | ||
| 2649 | .parent = &per_l4_ick, | 2549 | .parent = &per_l4_ick, |
| 2650 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2550 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2651 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | 2551 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2652 | .flags = CLOCK_IN_OMAP343X, | ||
| 2653 | .clkdm_name = "per_clkdm", | 2552 | .clkdm_name = "per_clkdm", |
| 2654 | .recalc = &followparent_recalc, | 2553 | .recalc = &followparent_recalc, |
| 2655 | }; | 2554 | }; |
| 2656 | 2555 | ||
| 2657 | static struct clk uart3_ick = { | 2556 | static struct clk uart3_ick = { |
| 2658 | .name = "uart3_ick", | 2557 | .name = "uart3_ick", |
| 2558 | .ops = &clkops_omap2_dflt_wait, | ||
| 2659 | .parent = &per_l4_ick, | 2559 | .parent = &per_l4_ick, |
| 2660 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2560 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2661 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | 2561 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2662 | .flags = CLOCK_IN_OMAP343X, | ||
| 2663 | .clkdm_name = "per_clkdm", | 2562 | .clkdm_name = "per_clkdm", |
| 2664 | .recalc = &followparent_recalc, | 2563 | .recalc = &followparent_recalc, |
| 2665 | }; | 2564 | }; |
| 2666 | 2565 | ||
| 2667 | static struct clk gpt9_ick = { | 2566 | static struct clk gpt9_ick = { |
| 2668 | .name = "gpt9_ick", | 2567 | .name = "gpt9_ick", |
| 2568 | .ops = &clkops_omap2_dflt_wait, | ||
| 2669 | .parent = &per_l4_ick, | 2569 | .parent = &per_l4_ick, |
| 2670 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2570 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2671 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | 2571 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2672 | .flags = CLOCK_IN_OMAP343X, | ||
| 2673 | .clkdm_name = "per_clkdm", | 2572 | .clkdm_name = "per_clkdm", |
| 2674 | .recalc = &followparent_recalc, | 2573 | .recalc = &followparent_recalc, |
| 2675 | }; | 2574 | }; |
| 2676 | 2575 | ||
| 2677 | static struct clk gpt8_ick = { | 2576 | static struct clk gpt8_ick = { |
| 2678 | .name = "gpt8_ick", | 2577 | .name = "gpt8_ick", |
| 2578 | .ops = &clkops_omap2_dflt_wait, | ||
| 2679 | .parent = &per_l4_ick, | 2579 | .parent = &per_l4_ick, |
| 2680 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2580 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2681 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | 2581 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2682 | .flags = CLOCK_IN_OMAP343X, | ||
| 2683 | .clkdm_name = "per_clkdm", | 2582 | .clkdm_name = "per_clkdm", |
| 2684 | .recalc = &followparent_recalc, | 2583 | .recalc = &followparent_recalc, |
| 2685 | }; | 2584 | }; |
| 2686 | 2585 | ||
| 2687 | static struct clk gpt7_ick = { | 2586 | static struct clk gpt7_ick = { |
| 2688 | .name = "gpt7_ick", | 2587 | .name = "gpt7_ick", |
| 2588 | .ops = &clkops_omap2_dflt_wait, | ||
| 2689 | .parent = &per_l4_ick, | 2589 | .parent = &per_l4_ick, |
| 2690 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2590 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2691 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | 2591 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2692 | .flags = CLOCK_IN_OMAP343X, | ||
| 2693 | .clkdm_name = "per_clkdm", | 2592 | .clkdm_name = "per_clkdm", |
| 2694 | .recalc = &followparent_recalc, | 2593 | .recalc = &followparent_recalc, |
| 2695 | }; | 2594 | }; |
| 2696 | 2595 | ||
| 2697 | static struct clk gpt6_ick = { | 2596 | static struct clk gpt6_ick = { |
| 2698 | .name = "gpt6_ick", | 2597 | .name = "gpt6_ick", |
| 2598 | .ops = &clkops_omap2_dflt_wait, | ||
| 2699 | .parent = &per_l4_ick, | 2599 | .parent = &per_l4_ick, |
| 2700 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2600 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2701 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | 2601 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2702 | .flags = CLOCK_IN_OMAP343X, | ||
| 2703 | .clkdm_name = "per_clkdm", | 2602 | .clkdm_name = "per_clkdm", |
| 2704 | .recalc = &followparent_recalc, | 2603 | .recalc = &followparent_recalc, |
| 2705 | }; | 2604 | }; |
| 2706 | 2605 | ||
| 2707 | static struct clk gpt5_ick = { | 2606 | static struct clk gpt5_ick = { |
| 2708 | .name = "gpt5_ick", | 2607 | .name = "gpt5_ick", |
| 2608 | .ops = &clkops_omap2_dflt_wait, | ||
| 2709 | .parent = &per_l4_ick, | 2609 | .parent = &per_l4_ick, |
| 2710 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2610 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2711 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | 2611 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2712 | .flags = CLOCK_IN_OMAP343X, | ||
| 2713 | .clkdm_name = "per_clkdm", | 2612 | .clkdm_name = "per_clkdm", |
| 2714 | .recalc = &followparent_recalc, | 2613 | .recalc = &followparent_recalc, |
| 2715 | }; | 2614 | }; |
| 2716 | 2615 | ||
| 2717 | static struct clk gpt4_ick = { | 2616 | static struct clk gpt4_ick = { |
| 2718 | .name = "gpt4_ick", | 2617 | .name = "gpt4_ick", |
| 2618 | .ops = &clkops_omap2_dflt_wait, | ||
| 2719 | .parent = &per_l4_ick, | 2619 | .parent = &per_l4_ick, |
| 2720 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2620 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2721 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | 2621 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2722 | .flags = CLOCK_IN_OMAP343X, | ||
| 2723 | .clkdm_name = "per_clkdm", | 2622 | .clkdm_name = "per_clkdm", |
| 2724 | .recalc = &followparent_recalc, | 2623 | .recalc = &followparent_recalc, |
| 2725 | }; | 2624 | }; |
| 2726 | 2625 | ||
| 2727 | static struct clk gpt3_ick = { | 2626 | static struct clk gpt3_ick = { |
| 2728 | .name = "gpt3_ick", | 2627 | .name = "gpt3_ick", |
| 2628 | .ops = &clkops_omap2_dflt_wait, | ||
| 2729 | .parent = &per_l4_ick, | 2629 | .parent = &per_l4_ick, |
| 2730 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2630 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2731 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | 2631 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2732 | .flags = CLOCK_IN_OMAP343X, | ||
| 2733 | .clkdm_name = "per_clkdm", | 2632 | .clkdm_name = "per_clkdm", |
| 2734 | .recalc = &followparent_recalc, | 2633 | .recalc = &followparent_recalc, |
| 2735 | }; | 2634 | }; |
| 2736 | 2635 | ||
| 2737 | static struct clk gpt2_ick = { | 2636 | static struct clk gpt2_ick = { |
| 2738 | .name = "gpt2_ick", | 2637 | .name = "gpt2_ick", |
| 2638 | .ops = &clkops_omap2_dflt_wait, | ||
| 2739 | .parent = &per_l4_ick, | 2639 | .parent = &per_l4_ick, |
| 2740 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2640 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2741 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | 2641 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2742 | .flags = CLOCK_IN_OMAP343X, | ||
| 2743 | .clkdm_name = "per_clkdm", | 2642 | .clkdm_name = "per_clkdm", |
| 2744 | .recalc = &followparent_recalc, | 2643 | .recalc = &followparent_recalc, |
| 2745 | }; | 2644 | }; |
| 2746 | 2645 | ||
| 2747 | static struct clk mcbsp2_ick = { | 2646 | static struct clk mcbsp2_ick = { |
| 2748 | .name = "mcbsp_ick", | 2647 | .name = "mcbsp_ick", |
| 2648 | .ops = &clkops_omap2_dflt_wait, | ||
| 2749 | .id = 2, | 2649 | .id = 2, |
| 2750 | .parent = &per_l4_ick, | 2650 | .parent = &per_l4_ick, |
| 2751 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2651 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2752 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2652 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2753 | .flags = CLOCK_IN_OMAP343X, | ||
| 2754 | .clkdm_name = "per_clkdm", | 2653 | .clkdm_name = "per_clkdm", |
| 2755 | .recalc = &followparent_recalc, | 2654 | .recalc = &followparent_recalc, |
| 2756 | }; | 2655 | }; |
| 2757 | 2656 | ||
| 2758 | static struct clk mcbsp3_ick = { | 2657 | static struct clk mcbsp3_ick = { |
| 2759 | .name = "mcbsp_ick", | 2658 | .name = "mcbsp_ick", |
| 2659 | .ops = &clkops_omap2_dflt_wait, | ||
| 2760 | .id = 3, | 2660 | .id = 3, |
| 2761 | .parent = &per_l4_ick, | 2661 | .parent = &per_l4_ick, |
| 2762 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2662 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2763 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2663 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2764 | .flags = CLOCK_IN_OMAP343X, | ||
| 2765 | .clkdm_name = "per_clkdm", | 2664 | .clkdm_name = "per_clkdm", |
| 2766 | .recalc = &followparent_recalc, | 2665 | .recalc = &followparent_recalc, |
| 2767 | }; | 2666 | }; |
| 2768 | 2667 | ||
| 2769 | static struct clk mcbsp4_ick = { | 2668 | static struct clk mcbsp4_ick = { |
| 2770 | .name = "mcbsp_ick", | 2669 | .name = "mcbsp_ick", |
| 2670 | .ops = &clkops_omap2_dflt_wait, | ||
| 2771 | .id = 4, | 2671 | .id = 4, |
| 2772 | .parent = &per_l4_ick, | 2672 | .parent = &per_l4_ick, |
| 2773 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2673 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2774 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2674 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2775 | .flags = CLOCK_IN_OMAP343X, | ||
| 2776 | .clkdm_name = "per_clkdm", | 2675 | .clkdm_name = "per_clkdm", |
| 2777 | .recalc = &followparent_recalc, | 2676 | .recalc = &followparent_recalc, |
| 2778 | }; | 2677 | }; |
| 2779 | 2678 | ||
| 2780 | static const struct clksel mcbsp_234_clksel[] = { | 2679 | static const struct clksel mcbsp_234_clksel[] = { |
| 2781 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, | 2680 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
| 2782 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | 2681 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 2783 | { .parent = NULL } | 2682 | { .parent = NULL } |
| 2784 | }; | 2683 | }; |
| 2785 | 2684 | ||
| 2786 | static struct clk mcbsp2_fck = { | 2685 | static struct clk mcbsp2_fck = { |
| 2787 | .name = "mcbsp_fck", | 2686 | .name = "mcbsp_fck", |
| 2687 | .ops = &clkops_omap2_dflt_wait, | ||
| 2788 | .id = 2, | 2688 | .id = 2, |
| 2789 | .init = &omap2_init_clksel_parent, | 2689 | .init = &omap2_init_clksel_parent, |
| 2790 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2690 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| @@ -2792,13 +2692,13 @@ static struct clk mcbsp2_fck = { | |||
| 2792 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | 2692 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 2793 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | 2693 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
| 2794 | .clksel = mcbsp_234_clksel, | 2694 | .clksel = mcbsp_234_clksel, |
| 2795 | .flags = CLOCK_IN_OMAP343X, | ||
| 2796 | .clkdm_name = "per_clkdm", | 2695 | .clkdm_name = "per_clkdm", |
| 2797 | .recalc = &omap2_clksel_recalc, | 2696 | .recalc = &omap2_clksel_recalc, |
| 2798 | }; | 2697 | }; |
| 2799 | 2698 | ||
| 2800 | static struct clk mcbsp3_fck = { | 2699 | static struct clk mcbsp3_fck = { |
| 2801 | .name = "mcbsp_fck", | 2700 | .name = "mcbsp_fck", |
| 2701 | .ops = &clkops_omap2_dflt_wait, | ||
| 2802 | .id = 3, | 2702 | .id = 3, |
| 2803 | .init = &omap2_init_clksel_parent, | 2703 | .init = &omap2_init_clksel_parent, |
| 2804 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2704 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| @@ -2806,13 +2706,13 @@ static struct clk mcbsp3_fck = { | |||
| 2806 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | 2706 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2807 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | 2707 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
| 2808 | .clksel = mcbsp_234_clksel, | 2708 | .clksel = mcbsp_234_clksel, |
| 2809 | .flags = CLOCK_IN_OMAP343X, | ||
| 2810 | .clkdm_name = "per_clkdm", | 2709 | .clkdm_name = "per_clkdm", |
| 2811 | .recalc = &omap2_clksel_recalc, | 2710 | .recalc = &omap2_clksel_recalc, |
| 2812 | }; | 2711 | }; |
| 2813 | 2712 | ||
| 2814 | static struct clk mcbsp4_fck = { | 2713 | static struct clk mcbsp4_fck = { |
| 2815 | .name = "mcbsp_fck", | 2714 | .name = "mcbsp_fck", |
| 2715 | .ops = &clkops_omap2_dflt_wait, | ||
| 2816 | .id = 4, | 2716 | .id = 4, |
| 2817 | .init = &omap2_init_clksel_parent, | 2717 | .init = &omap2_init_clksel_parent, |
| 2818 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2718 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| @@ -2820,7 +2720,6 @@ static struct clk mcbsp4_fck = { | |||
| 2820 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | 2720 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2821 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | 2721 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
| 2822 | .clksel = mcbsp_234_clksel, | 2722 | .clksel = mcbsp_234_clksel, |
| 2823 | .flags = CLOCK_IN_OMAP343X, | ||
| 2824 | .clkdm_name = "per_clkdm", | 2723 | .clkdm_name = "per_clkdm", |
| 2825 | .recalc = &omap2_clksel_recalc, | 2724 | .recalc = &omap2_clksel_recalc, |
| 2826 | }; | 2725 | }; |
| @@ -2864,11 +2763,11 @@ static const struct clksel emu_src_clksel[] = { | |||
| 2864 | */ | 2763 | */ |
| 2865 | static struct clk emu_src_ck = { | 2764 | static struct clk emu_src_ck = { |
| 2866 | .name = "emu_src_ck", | 2765 | .name = "emu_src_ck", |
| 2766 | .ops = &clkops_null, | ||
| 2867 | .init = &omap2_init_clksel_parent, | 2767 | .init = &omap2_init_clksel_parent, |
| 2868 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2768 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2869 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | 2769 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
| 2870 | .clksel = emu_src_clksel, | 2770 | .clksel = emu_src_clksel, |
| 2871 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2872 | .clkdm_name = "emu_clkdm", | 2771 | .clkdm_name = "emu_clkdm", |
| 2873 | .recalc = &omap2_clksel_recalc, | 2772 | .recalc = &omap2_clksel_recalc, |
| 2874 | }; | 2773 | }; |
| @@ -2888,11 +2787,11 @@ static const struct clksel pclk_emu_clksel[] = { | |||
| 2888 | 2787 | ||
| 2889 | static struct clk pclk_fck = { | 2788 | static struct clk pclk_fck = { |
| 2890 | .name = "pclk_fck", | 2789 | .name = "pclk_fck", |
| 2790 | .ops = &clkops_null, | ||
| 2891 | .init = &omap2_init_clksel_parent, | 2791 | .init = &omap2_init_clksel_parent, |
| 2892 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2792 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2893 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | 2793 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
| 2894 | .clksel = pclk_emu_clksel, | 2794 | .clksel = pclk_emu_clksel, |
| 2895 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2896 | .clkdm_name = "emu_clkdm", | 2795 | .clkdm_name = "emu_clkdm", |
| 2897 | .recalc = &omap2_clksel_recalc, | 2796 | .recalc = &omap2_clksel_recalc, |
| 2898 | }; | 2797 | }; |
| @@ -2911,11 +2810,11 @@ static const struct clksel pclkx2_emu_clksel[] = { | |||
| 2911 | 2810 | ||
| 2912 | static struct clk pclkx2_fck = { | 2811 | static struct clk pclkx2_fck = { |
| 2913 | .name = "pclkx2_fck", | 2812 | .name = "pclkx2_fck", |
| 2813 | .ops = &clkops_null, | ||
| 2914 | .init = &omap2_init_clksel_parent, | 2814 | .init = &omap2_init_clksel_parent, |
| 2915 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2815 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2916 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | 2816 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
| 2917 | .clksel = pclkx2_emu_clksel, | 2817 | .clksel = pclkx2_emu_clksel, |
| 2918 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2919 | .clkdm_name = "emu_clkdm", | 2818 | .clkdm_name = "emu_clkdm", |
| 2920 | .recalc = &omap2_clksel_recalc, | 2819 | .recalc = &omap2_clksel_recalc, |
| 2921 | }; | 2820 | }; |
| @@ -2927,22 +2826,22 @@ static const struct clksel atclk_emu_clksel[] = { | |||
| 2927 | 2826 | ||
| 2928 | static struct clk atclk_fck = { | 2827 | static struct clk atclk_fck = { |
| 2929 | .name = "atclk_fck", | 2828 | .name = "atclk_fck", |
| 2829 | .ops = &clkops_null, | ||
| 2930 | .init = &omap2_init_clksel_parent, | 2830 | .init = &omap2_init_clksel_parent, |
| 2931 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2831 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2932 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | 2832 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
| 2933 | .clksel = atclk_emu_clksel, | 2833 | .clksel = atclk_emu_clksel, |
| 2934 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2935 | .clkdm_name = "emu_clkdm", | 2834 | .clkdm_name = "emu_clkdm", |
| 2936 | .recalc = &omap2_clksel_recalc, | 2835 | .recalc = &omap2_clksel_recalc, |
| 2937 | }; | 2836 | }; |
| 2938 | 2837 | ||
| 2939 | static struct clk traceclk_src_fck = { | 2838 | static struct clk traceclk_src_fck = { |
| 2940 | .name = "traceclk_src_fck", | 2839 | .name = "traceclk_src_fck", |
| 2840 | .ops = &clkops_null, | ||
| 2941 | .init = &omap2_init_clksel_parent, | 2841 | .init = &omap2_init_clksel_parent, |
| 2942 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2842 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2943 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | 2843 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
| 2944 | .clksel = emu_src_clksel, | 2844 | .clksel = emu_src_clksel, |
| 2945 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2946 | .clkdm_name = "emu_clkdm", | 2845 | .clkdm_name = "emu_clkdm", |
| 2947 | .recalc = &omap2_clksel_recalc, | 2846 | .recalc = &omap2_clksel_recalc, |
| 2948 | }; | 2847 | }; |
| @@ -2961,11 +2860,11 @@ static const struct clksel traceclk_clksel[] = { | |||
| 2961 | 2860 | ||
| 2962 | static struct clk traceclk_fck = { | 2861 | static struct clk traceclk_fck = { |
| 2963 | .name = "traceclk_fck", | 2862 | .name = "traceclk_fck", |
| 2863 | .ops = &clkops_null, | ||
| 2964 | .init = &omap2_init_clksel_parent, | 2864 | .init = &omap2_init_clksel_parent, |
| 2965 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2865 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2966 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | 2866 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
| 2967 | .clksel = traceclk_clksel, | 2867 | .clksel = traceclk_clksel, |
| 2968 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | ||
| 2969 | .clkdm_name = "emu_clkdm", | 2868 | .clkdm_name = "emu_clkdm", |
| 2970 | .recalc = &omap2_clksel_recalc, | 2869 | .recalc = &omap2_clksel_recalc, |
| 2971 | }; | 2870 | }; |
| @@ -2975,27 +2874,27 @@ static struct clk traceclk_fck = { | |||
| 2975 | /* SmartReflex fclk (VDD1) */ | 2874 | /* SmartReflex fclk (VDD1) */ |
| 2976 | static struct clk sr1_fck = { | 2875 | static struct clk sr1_fck = { |
| 2977 | .name = "sr1_fck", | 2876 | .name = "sr1_fck", |
| 2877 | .ops = &clkops_omap2_dflt_wait, | ||
| 2978 | .parent = &sys_ck, | 2878 | .parent = &sys_ck, |
| 2979 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2879 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2980 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | 2880 | .enable_bit = OMAP3430_EN_SR1_SHIFT, |
| 2981 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 2982 | .recalc = &followparent_recalc, | 2881 | .recalc = &followparent_recalc, |
| 2983 | }; | 2882 | }; |
| 2984 | 2883 | ||
| 2985 | /* SmartReflex fclk (VDD2) */ | 2884 | /* SmartReflex fclk (VDD2) */ |
| 2986 | static struct clk sr2_fck = { | 2885 | static struct clk sr2_fck = { |
| 2987 | .name = "sr2_fck", | 2886 | .name = "sr2_fck", |
| 2887 | .ops = &clkops_omap2_dflt_wait, | ||
| 2988 | .parent = &sys_ck, | 2888 | .parent = &sys_ck, |
| 2989 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2889 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2990 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | 2890 | .enable_bit = OMAP3430_EN_SR2_SHIFT, |
| 2991 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 2992 | .recalc = &followparent_recalc, | 2891 | .recalc = &followparent_recalc, |
| 2993 | }; | 2892 | }; |
| 2994 | 2893 | ||
| 2995 | static struct clk sr_l4_ick = { | 2894 | static struct clk sr_l4_ick = { |
| 2996 | .name = "sr_l4_ick", | 2895 | .name = "sr_l4_ick", |
| 2896 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2997 | .parent = &l4_ick, | 2897 | .parent = &l4_ick, |
| 2998 | .flags = CLOCK_IN_OMAP343X, | ||
| 2999 | .clkdm_name = "core_l4_clkdm", | 2898 | .clkdm_name = "core_l4_clkdm", |
| 3000 | .recalc = &followparent_recalc, | 2899 | .recalc = &followparent_recalc, |
| 3001 | }; | 2900 | }; |
| @@ -3005,231 +2904,16 @@ static struct clk sr_l4_ick = { | |||
| 3005 | /* XXX This clock no longer exists in 3430 TRM rev F */ | 2904 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
| 3006 | static struct clk gpt12_fck = { | 2905 | static struct clk gpt12_fck = { |
| 3007 | .name = "gpt12_fck", | 2906 | .name = "gpt12_fck", |
| 2907 | .ops = &clkops_null, | ||
| 3008 | .parent = &secure_32k_fck, | 2908 | .parent = &secure_32k_fck, |
| 3009 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | ||
| 3010 | .recalc = &followparent_recalc, | 2909 | .recalc = &followparent_recalc, |
| 3011 | }; | 2910 | }; |
| 3012 | 2911 | ||
| 3013 | static struct clk wdt1_fck = { | 2912 | static struct clk wdt1_fck = { |
| 3014 | .name = "wdt1_fck", | 2913 | .name = "wdt1_fck", |
| 2914 | .ops = &clkops_null, | ||
| 3015 | .parent = &secure_32k_fck, | 2915 | .parent = &secure_32k_fck, |
| 3016 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | 2916 | .recalc = &followparent_recalc, |
| 3017 | .recalc = &followparent_recalc, | ||
| 3018 | }; | ||
| 3019 | |||
| 3020 | static struct clk *onchip_34xx_clks[] __initdata = { | ||
| 3021 | &omap_32k_fck, | ||
| 3022 | &virt_12m_ck, | ||
| 3023 | &virt_13m_ck, | ||
| 3024 | &virt_16_8m_ck, | ||
| 3025 | &virt_19_2m_ck, | ||
| 3026 | &virt_26m_ck, | ||
| 3027 | &virt_38_4m_ck, | ||
| 3028 | &osc_sys_ck, | ||
| 3029 | &sys_ck, | ||
| 3030 | &sys_altclk, | ||
| 3031 | &mcbsp_clks, | ||
| 3032 | &sys_clkout1, | ||
| 3033 | &dpll1_ck, | ||
| 3034 | &dpll1_x2_ck, | ||
| 3035 | &dpll1_x2m2_ck, | ||
| 3036 | &dpll2_ck, | ||
| 3037 | &dpll2_m2_ck, | ||
| 3038 | &dpll3_ck, | ||
| 3039 | &core_ck, | ||
| 3040 | &dpll3_x2_ck, | ||
| 3041 | &dpll3_m2_ck, | ||
| 3042 | &dpll3_m2x2_ck, | ||
| 3043 | &dpll3_m3_ck, | ||
| 3044 | &dpll3_m3x2_ck, | ||
| 3045 | &emu_core_alwon_ck, | ||
| 3046 | &dpll4_ck, | ||
| 3047 | &dpll4_x2_ck, | ||
| 3048 | &omap_96m_alwon_fck, | ||
| 3049 | &omap_96m_fck, | ||
| 3050 | &cm_96m_fck, | ||
| 3051 | &virt_omap_54m_fck, | ||
| 3052 | &omap_54m_fck, | ||
| 3053 | &omap_48m_fck, | ||
| 3054 | &omap_12m_fck, | ||
| 3055 | &dpll4_m2_ck, | ||
| 3056 | &dpll4_m2x2_ck, | ||
| 3057 | &dpll4_m3_ck, | ||
| 3058 | &dpll4_m3x2_ck, | ||
| 3059 | &dpll4_m4_ck, | ||
| 3060 | &dpll4_m4x2_ck, | ||
| 3061 | &dpll4_m5_ck, | ||
| 3062 | &dpll4_m5x2_ck, | ||
| 3063 | &dpll4_m6_ck, | ||
| 3064 | &dpll4_m6x2_ck, | ||
| 3065 | &emu_per_alwon_ck, | ||
| 3066 | &dpll5_ck, | ||
| 3067 | &dpll5_m2_ck, | ||
| 3068 | &omap_120m_fck, | ||
| 3069 | &clkout2_src_ck, | ||
| 3070 | &sys_clkout2, | ||
| 3071 | &corex2_fck, | ||
| 3072 | &dpll1_fck, | ||
| 3073 | &mpu_ck, | ||
| 3074 | &arm_fck, | ||
| 3075 | &emu_mpu_alwon_ck, | ||
| 3076 | &dpll2_fck, | ||
| 3077 | &iva2_ck, | ||
| 3078 | &l3_ick, | ||
| 3079 | &l4_ick, | ||
| 3080 | &rm_ick, | ||
| 3081 | &gfx_l3_ck, | ||
| 3082 | &gfx_l3_fck, | ||
| 3083 | &gfx_l3_ick, | ||
| 3084 | &gfx_cg1_ck, | ||
| 3085 | &gfx_cg2_ck, | ||
| 3086 | &sgx_fck, | ||
| 3087 | &sgx_ick, | ||
| 3088 | &d2d_26m_fck, | ||
| 3089 | &gpt10_fck, | ||
| 3090 | &gpt11_fck, | ||
| 3091 | &cpefuse_fck, | ||
| 3092 | &ts_fck, | ||
| 3093 | &usbtll_fck, | ||
| 3094 | &core_96m_fck, | ||
| 3095 | &mmchs3_fck, | ||
| 3096 | &mmchs2_fck, | ||
| 3097 | &mspro_fck, | ||
| 3098 | &mmchs1_fck, | ||
| 3099 | &i2c3_fck, | ||
| 3100 | &i2c2_fck, | ||
| 3101 | &i2c1_fck, | ||
| 3102 | &mcbsp5_fck, | ||
| 3103 | &mcbsp1_fck, | ||
| 3104 | &core_48m_fck, | ||
| 3105 | &mcspi4_fck, | ||
| 3106 | &mcspi3_fck, | ||
| 3107 | &mcspi2_fck, | ||
| 3108 | &mcspi1_fck, | ||
| 3109 | &uart2_fck, | ||
| 3110 | &uart1_fck, | ||
| 3111 | &fshostusb_fck, | ||
| 3112 | &core_12m_fck, | ||
| 3113 | &hdq_fck, | ||
| 3114 | &ssi_ssr_fck, | ||
| 3115 | &ssi_sst_fck, | ||
| 3116 | &core_l3_ick, | ||
| 3117 | &hsotgusb_ick, | ||
| 3118 | &sdrc_ick, | ||
| 3119 | &gpmc_fck, | ||
| 3120 | &security_l3_ick, | ||
| 3121 | &pka_ick, | ||
| 3122 | &core_l4_ick, | ||
| 3123 | &usbtll_ick, | ||
| 3124 | &mmchs3_ick, | ||
| 3125 | &icr_ick, | ||
| 3126 | &aes2_ick, | ||
| 3127 | &sha12_ick, | ||
| 3128 | &des2_ick, | ||
| 3129 | &mmchs2_ick, | ||
| 3130 | &mmchs1_ick, | ||
| 3131 | &mspro_ick, | ||
| 3132 | &hdq_ick, | ||
| 3133 | &mcspi4_ick, | ||
| 3134 | &mcspi3_ick, | ||
| 3135 | &mcspi2_ick, | ||
| 3136 | &mcspi1_ick, | ||
| 3137 | &i2c3_ick, | ||
| 3138 | &i2c2_ick, | ||
| 3139 | &i2c1_ick, | ||
| 3140 | &uart2_ick, | ||
| 3141 | &uart1_ick, | ||
| 3142 | &gpt11_ick, | ||
| 3143 | &gpt10_ick, | ||
| 3144 | &mcbsp5_ick, | ||
| 3145 | &mcbsp1_ick, | ||
| 3146 | &fac_ick, | ||
| 3147 | &mailboxes_ick, | ||
| 3148 | &omapctrl_ick, | ||
| 3149 | &ssi_l4_ick, | ||
| 3150 | &ssi_ick, | ||
| 3151 | &usb_l4_ick, | ||
| 3152 | &security_l4_ick2, | ||
| 3153 | &aes1_ick, | ||
| 3154 | &rng_ick, | ||
| 3155 | &sha11_ick, | ||
| 3156 | &des1_ick, | ||
| 3157 | &dss1_alwon_fck, | ||
| 3158 | &dss_tv_fck, | ||
| 3159 | &dss_96m_fck, | ||
| 3160 | &dss2_alwon_fck, | ||
| 3161 | &dss_ick, | ||
| 3162 | &cam_mclk, | ||
| 3163 | &cam_ick, | ||
| 3164 | &usbhost_120m_fck, | ||
| 3165 | &usbhost_48m_fck, | ||
| 3166 | &usbhost_ick, | ||
| 3167 | &usbhost_sar_fck, | ||
| 3168 | &usim_fck, | ||
| 3169 | &gpt1_fck, | ||
| 3170 | &wkup_32k_fck, | ||
| 3171 | &gpio1_dbck, | ||
| 3172 | &wdt2_fck, | ||
| 3173 | &wkup_l4_ick, | ||
| 3174 | &usim_ick, | ||
| 3175 | &wdt2_ick, | ||
| 3176 | &wdt1_ick, | ||
| 3177 | &gpio1_ick, | ||
| 3178 | &omap_32ksync_ick, | ||
| 3179 | &gpt12_ick, | ||
| 3180 | &gpt1_ick, | ||
| 3181 | &per_96m_fck, | ||
| 3182 | &per_48m_fck, | ||
| 3183 | &uart3_fck, | ||
| 3184 | &gpt2_fck, | ||
| 3185 | &gpt3_fck, | ||
| 3186 | &gpt4_fck, | ||
| 3187 | &gpt5_fck, | ||
| 3188 | &gpt6_fck, | ||
| 3189 | &gpt7_fck, | ||
| 3190 | &gpt8_fck, | ||
| 3191 | &gpt9_fck, | ||
| 3192 | &per_32k_alwon_fck, | ||
| 3193 | &gpio6_dbck, | ||
| 3194 | &gpio5_dbck, | ||
| 3195 | &gpio4_dbck, | ||
| 3196 | &gpio3_dbck, | ||
| 3197 | &gpio2_dbck, | ||
| 3198 | &wdt3_fck, | ||
| 3199 | &per_l4_ick, | ||
| 3200 | &gpio6_ick, | ||
| 3201 | &gpio5_ick, | ||
| 3202 | &gpio4_ick, | ||
| 3203 | &gpio3_ick, | ||
| 3204 | &gpio2_ick, | ||
| 3205 | &wdt3_ick, | ||
| 3206 | &uart3_ick, | ||
| 3207 | &gpt9_ick, | ||
| 3208 | &gpt8_ick, | ||
| 3209 | &gpt7_ick, | ||
| 3210 | &gpt6_ick, | ||
| 3211 | &gpt5_ick, | ||
| 3212 | &gpt4_ick, | ||
| 3213 | &gpt3_ick, | ||
| 3214 | &gpt2_ick, | ||
| 3215 | &mcbsp2_ick, | ||
| 3216 | &mcbsp3_ick, | ||
| 3217 | &mcbsp4_ick, | ||
| 3218 | &mcbsp2_fck, | ||
| 3219 | &mcbsp3_fck, | ||
| 3220 | &mcbsp4_fck, | ||
| 3221 | &emu_src_ck, | ||
| 3222 | &pclk_fck, | ||
| 3223 | &pclkx2_fck, | ||
| 3224 | &atclk_fck, | ||
| 3225 | &traceclk_src_fck, | ||
| 3226 | &traceclk_fck, | ||
| 3227 | &sr1_fck, | ||
| 3228 | &sr2_fck, | ||
| 3229 | &sr_l4_ick, | ||
| 3230 | &secure_32k_fck, | ||
| 3231 | &gpt12_fck, | ||
| 3232 | &wdt1_fck, | ||
| 3233 | }; | 2917 | }; |
| 3234 | 2918 | ||
| 3235 | #endif | 2919 | #endif |
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 4c3ce9cfd948..0e7d501865b6 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/limits.h> | 24 | #include <linux/limits.h> |
| 25 | #include <linux/err.h> | ||
| 25 | 26 | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | 28 | ||
| @@ -71,16 +72,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) | |||
| 71 | if (!omap_chip_is(autodep->omap_chip)) | 72 | if (!omap_chip_is(autodep->omap_chip)) |
| 72 | return; | 73 | return; |
| 73 | 74 | ||
| 74 | pwrdm = pwrdm_lookup(autodep->pwrdm_name); | 75 | pwrdm = pwrdm_lookup(autodep->pwrdm.name); |
| 75 | if (!pwrdm) { | 76 | if (!pwrdm) { |
| 76 | pr_debug("clockdomain: _autodep_lookup: powerdomain %s " | 77 | pr_err("clockdomain: autodeps: powerdomain %s does not exist\n", |
| 77 | "does not exist\n", autodep->pwrdm_name); | 78 | autodep->pwrdm.name); |
| 78 | WARN_ON(1); | 79 | pwrdm = ERR_PTR(-ENOENT); |
| 79 | return; | ||
| 80 | } | 80 | } |
| 81 | autodep->pwrdm = pwrdm; | 81 | autodep->pwrdm.ptr = pwrdm; |
| 82 | |||
| 83 | return; | ||
| 84 | } | 82 | } |
| 85 | 83 | ||
| 86 | /* | 84 | /* |
| @@ -95,16 +93,19 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) | |||
| 95 | { | 93 | { |
| 96 | struct clkdm_pwrdm_autodep *autodep; | 94 | struct clkdm_pwrdm_autodep *autodep; |
| 97 | 95 | ||
| 98 | for (autodep = autodeps; autodep->pwrdm_name; autodep++) { | 96 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { |
| 99 | if (!autodep->pwrdm) | 97 | if (IS_ERR(autodep->pwrdm.ptr)) |
| 98 | continue; | ||
| 99 | |||
| 100 | if (!omap_chip_is(autodep->omap_chip)) | ||
| 100 | continue; | 101 | continue; |
| 101 | 102 | ||
| 102 | pr_debug("clockdomain: adding %s sleepdep/wkdep for " | 103 | pr_debug("clockdomain: adding %s sleepdep/wkdep for " |
| 103 | "pwrdm %s\n", autodep->pwrdm_name, | 104 | "pwrdm %s\n", autodep->pwrdm.ptr->name, |
| 104 | clkdm->pwrdm->name); | 105 | clkdm->pwrdm.ptr->name); |
| 105 | 106 | ||
| 106 | pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm); | 107 | pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 107 | pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm); | 108 | pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 108 | } | 109 | } |
| 109 | } | 110 | } |
| 110 | 111 | ||
| @@ -120,16 +121,19 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) | |||
| 120 | { | 121 | { |
| 121 | struct clkdm_pwrdm_autodep *autodep; | 122 | struct clkdm_pwrdm_autodep *autodep; |
| 122 | 123 | ||
| 123 | for (autodep = autodeps; autodep->pwrdm_name; autodep++) { | 124 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { |
| 124 | if (!autodep->pwrdm) | 125 | if (IS_ERR(autodep->pwrdm.ptr)) |
| 126 | continue; | ||
| 127 | |||
| 128 | if (!omap_chip_is(autodep->omap_chip)) | ||
| 125 | continue; | 129 | continue; |
| 126 | 130 | ||
| 127 | pr_debug("clockdomain: removing %s sleepdep/wkdep for " | 131 | pr_debug("clockdomain: removing %s sleepdep/wkdep for " |
| 128 | "pwrdm %s\n", autodep->pwrdm_name, | 132 | "pwrdm %s\n", autodep->pwrdm.ptr->name, |
| 129 | clkdm->pwrdm->name); | 133 | clkdm->pwrdm.ptr->name); |
| 130 | 134 | ||
| 131 | pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm); | 135 | pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 132 | pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm); | 136 | pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 133 | } | 137 | } |
| 134 | } | 138 | } |
| 135 | 139 | ||
| @@ -179,7 +183,7 @@ void clkdm_init(struct clockdomain **clkdms, | |||
| 179 | 183 | ||
| 180 | autodeps = init_autodeps; | 184 | autodeps = init_autodeps; |
| 181 | if (autodeps) | 185 | if (autodeps) |
| 182 | for (autodep = autodeps; autodep->pwrdm_name; autodep++) | 186 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) |
| 183 | _autodep_lookup(autodep); | 187 | _autodep_lookup(autodep); |
| 184 | } | 188 | } |
| 185 | 189 | ||
| @@ -202,20 +206,20 @@ int clkdm_register(struct clockdomain *clkdm) | |||
| 202 | if (!omap_chip_is(clkdm->omap_chip)) | 206 | if (!omap_chip_is(clkdm->omap_chip)) |
| 203 | return -EINVAL; | 207 | return -EINVAL; |
| 204 | 208 | ||
| 205 | pwrdm = pwrdm_lookup(clkdm->pwrdm_name); | 209 | pwrdm = pwrdm_lookup(clkdm->pwrdm.name); |
| 206 | if (!pwrdm) { | 210 | if (!pwrdm) { |
| 207 | pr_debug("clockdomain: clkdm_register %s: powerdomain %s " | 211 | pr_err("clockdomain: %s: powerdomain %s does not exist\n", |
| 208 | "does not exist\n", clkdm->name, clkdm->pwrdm_name); | 212 | clkdm->name, clkdm->pwrdm.name); |
| 209 | return -EINVAL; | 213 | return -EINVAL; |
| 210 | } | 214 | } |
| 211 | clkdm->pwrdm = pwrdm; | 215 | clkdm->pwrdm.ptr = pwrdm; |
| 212 | 216 | ||
| 213 | mutex_lock(&clkdm_mutex); | 217 | mutex_lock(&clkdm_mutex); |
| 214 | /* Verify that the clockdomain is not already registered */ | 218 | /* Verify that the clockdomain is not already registered */ |
| 215 | if (_clkdm_lookup(clkdm->name)) { | 219 | if (_clkdm_lookup(clkdm->name)) { |
| 216 | ret = -EEXIST; | 220 | ret = -EEXIST; |
| 217 | goto cr_unlock; | 221 | goto cr_unlock; |
| 218 | }; | 222 | } |
| 219 | 223 | ||
| 220 | list_add(&clkdm->node, &clkdm_list); | 224 | list_add(&clkdm->node, &clkdm_list); |
| 221 | 225 | ||
| @@ -242,7 +246,7 @@ int clkdm_unregister(struct clockdomain *clkdm) | |||
| 242 | if (!clkdm) | 246 | if (!clkdm) |
| 243 | return -EINVAL; | 247 | return -EINVAL; |
| 244 | 248 | ||
| 245 | pwrdm_del_clkdm(clkdm->pwrdm, clkdm); | 249 | pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm); |
| 246 | 250 | ||
| 247 | mutex_lock(&clkdm_mutex); | 251 | mutex_lock(&clkdm_mutex); |
| 248 | list_del(&clkdm->node); | 252 | list_del(&clkdm->node); |
| @@ -327,7 +331,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) | |||
| 327 | if (!clkdm) | 331 | if (!clkdm) |
| 328 | return NULL; | 332 | return NULL; |
| 329 | 333 | ||
| 330 | return clkdm->pwrdm; | 334 | return clkdm->pwrdm.ptr; |
| 331 | } | 335 | } |
| 332 | 336 | ||
| 333 | 337 | ||
| @@ -348,7 +352,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) | |||
| 348 | if (!clkdm) | 352 | if (!clkdm) |
| 349 | return -EINVAL; | 353 | return -EINVAL; |
| 350 | 354 | ||
| 351 | v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 355 | v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 352 | v &= clkdm->clktrctrl_mask; | 356 | v &= clkdm->clktrctrl_mask; |
| 353 | v >>= __ffs(clkdm->clktrctrl_mask); | 357 | v >>= __ffs(clkdm->clktrctrl_mask); |
| 354 | 358 | ||
| @@ -380,7 +384,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) | |||
| 380 | if (cpu_is_omap24xx()) { | 384 | if (cpu_is_omap24xx()) { |
| 381 | 385 | ||
| 382 | cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, | 386 | cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, |
| 383 | clkdm->pwrdm->prcm_offs, PM_PWSTCTRL); | 387 | clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); |
| 384 | 388 | ||
| 385 | } else if (cpu_is_omap34xx()) { | 389 | } else if (cpu_is_omap34xx()) { |
| 386 | 390 | ||
| @@ -388,7 +392,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) | |||
| 388 | __ffs(clkdm->clktrctrl_mask)); | 392 | __ffs(clkdm->clktrctrl_mask)); |
| 389 | 393 | ||
| 390 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, | 394 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, |
| 391 | clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 395 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 392 | 396 | ||
| 393 | } else { | 397 | } else { |
| 394 | BUG(); | 398 | BUG(); |
| @@ -422,7 +426,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) | |||
| 422 | if (cpu_is_omap24xx()) { | 426 | if (cpu_is_omap24xx()) { |
| 423 | 427 | ||
| 424 | cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, | 428 | cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, |
| 425 | clkdm->pwrdm->prcm_offs, PM_PWSTCTRL); | 429 | clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); |
| 426 | 430 | ||
| 427 | } else if (cpu_is_omap34xx()) { | 431 | } else if (cpu_is_omap34xx()) { |
| 428 | 432 | ||
| @@ -430,7 +434,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) | |||
| 430 | __ffs(clkdm->clktrctrl_mask)); | 434 | __ffs(clkdm->clktrctrl_mask)); |
| 431 | 435 | ||
| 432 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, | 436 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, |
| 433 | clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 437 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 434 | 438 | ||
| 435 | } else { | 439 | } else { |
| 436 | BUG(); | 440 | BUG(); |
| @@ -478,7 +482,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) | |||
| 478 | 482 | ||
| 479 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, | 483 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, |
| 480 | v << __ffs(clkdm->clktrctrl_mask), | 484 | v << __ffs(clkdm->clktrctrl_mask), |
| 481 | clkdm->pwrdm->prcm_offs, | 485 | clkdm->pwrdm.ptr->prcm_offs, |
| 482 | CM_CLKSTCTRL); | 486 | CM_CLKSTCTRL); |
| 483 | } | 487 | } |
| 484 | 488 | ||
| @@ -516,7 +520,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | |||
| 516 | 520 | ||
| 517 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, | 521 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, |
| 518 | v << __ffs(clkdm->clktrctrl_mask), | 522 | v << __ffs(clkdm->clktrctrl_mask), |
| 519 | clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 523 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 520 | 524 | ||
| 521 | if (atomic_read(&clkdm->usecount) > 0) | 525 | if (atomic_read(&clkdm->usecount) > 0) |
| 522 | _clkdm_del_autodeps(clkdm); | 526 | _clkdm_del_autodeps(clkdm); |
| @@ -567,6 +571,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
| 567 | else | 571 | else |
| 568 | omap2_clkdm_wakeup(clkdm); | 572 | omap2_clkdm_wakeup(clkdm); |
| 569 | 573 | ||
| 574 | pwrdm_wait_transition(clkdm->pwrdm.ptr); | ||
| 575 | |||
| 570 | return 0; | 576 | return 0; |
| 571 | } | 577 | } |
| 572 | 578 | ||
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index cd86dcc7b424..281d5da19188 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h | |||
| @@ -14,12 +14,29 @@ | |||
| 14 | 14 | ||
| 15 | /* | 15 | /* |
| 16 | * OMAP2/3-common clockdomains | 16 | * OMAP2/3-common clockdomains |
| 17 | * | ||
| 18 | * Even though the 2420 has a single PRCM module from the | ||
| 19 | * interconnect's perspective, internally it does appear to have | ||
| 20 | * separate PRM and CM clockdomains. The usual test case is | ||
| 21 | * sys_clkout/sys_clkout2. | ||
| 17 | */ | 22 | */ |
| 18 | 23 | ||
| 19 | /* This is an implicit clockdomain - it is never defined as such in TRM */ | 24 | /* This is an implicit clockdomain - it is never defined as such in TRM */ |
| 20 | static struct clockdomain wkup_clkdm = { | 25 | static struct clockdomain wkup_clkdm = { |
| 21 | .name = "wkup_clkdm", | 26 | .name = "wkup_clkdm", |
| 22 | .pwrdm_name = "wkup_pwrdm", | 27 | .pwrdm = { .name = "wkup_pwrdm" }, |
| 28 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | ||
| 29 | }; | ||
| 30 | |||
| 31 | static struct clockdomain prm_clkdm = { | ||
| 32 | .name = "prm_clkdm", | ||
| 33 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
| 34 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | ||
| 35 | }; | ||
| 36 | |||
| 37 | static struct clockdomain cm_clkdm = { | ||
| 38 | .name = "cm_clkdm", | ||
| 39 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 23 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 40 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
| 24 | }; | 41 | }; |
| 25 | 42 | ||
| @@ -31,7 +48,7 @@ static struct clockdomain wkup_clkdm = { | |||
| 31 | 48 | ||
| 32 | static struct clockdomain mpu_2420_clkdm = { | 49 | static struct clockdomain mpu_2420_clkdm = { |
| 33 | .name = "mpu_clkdm", | 50 | .name = "mpu_clkdm", |
| 34 | .pwrdm_name = "mpu_pwrdm", | 51 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 35 | .flags = CLKDM_CAN_HWSUP, | 52 | .flags = CLKDM_CAN_HWSUP, |
| 36 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 53 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 37 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 54 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -39,7 +56,7 @@ static struct clockdomain mpu_2420_clkdm = { | |||
| 39 | 56 | ||
| 40 | static struct clockdomain iva1_2420_clkdm = { | 57 | static struct clockdomain iva1_2420_clkdm = { |
| 41 | .name = "iva1_clkdm", | 58 | .name = "iva1_clkdm", |
| 42 | .pwrdm_name = "dsp_pwrdm", | 59 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 43 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 60 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 44 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, | 61 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, |
| 45 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -56,7 +73,7 @@ static struct clockdomain iva1_2420_clkdm = { | |||
| 56 | 73 | ||
| 57 | static struct clockdomain mpu_2430_clkdm = { | 74 | static struct clockdomain mpu_2430_clkdm = { |
| 58 | .name = "mpu_clkdm", | 75 | .name = "mpu_clkdm", |
| 59 | .pwrdm_name = "mpu_pwrdm", | 76 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 60 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 77 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 61 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 78 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| @@ -64,7 +81,7 @@ static struct clockdomain mpu_2430_clkdm = { | |||
| 64 | 81 | ||
| 65 | static struct clockdomain mdm_clkdm = { | 82 | static struct clockdomain mdm_clkdm = { |
| 66 | .name = "mdm_clkdm", | 83 | .name = "mdm_clkdm", |
| 67 | .pwrdm_name = "mdm_pwrdm", | 84 | .pwrdm = { .name = "mdm_pwrdm" }, |
| 68 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 85 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 69 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, | 86 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, |
| 70 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| @@ -81,7 +98,7 @@ static struct clockdomain mdm_clkdm = { | |||
| 81 | 98 | ||
| 82 | static struct clockdomain dsp_clkdm = { | 99 | static struct clockdomain dsp_clkdm = { |
| 83 | .name = "dsp_clkdm", | 100 | .name = "dsp_clkdm", |
| 84 | .pwrdm_name = "dsp_pwrdm", | 101 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 85 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 102 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 86 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, | 103 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
| 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 104 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -89,7 +106,7 @@ static struct clockdomain dsp_clkdm = { | |||
| 89 | 106 | ||
| 90 | static struct clockdomain gfx_24xx_clkdm = { | 107 | static struct clockdomain gfx_24xx_clkdm = { |
| 91 | .name = "gfx_clkdm", | 108 | .name = "gfx_clkdm", |
| 92 | .pwrdm_name = "gfx_pwrdm", | 109 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 93 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 110 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 94 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, | 111 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
| 95 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 112 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -97,7 +114,7 @@ static struct clockdomain gfx_24xx_clkdm = { | |||
| 97 | 114 | ||
| 98 | static struct clockdomain core_l3_24xx_clkdm = { | 115 | static struct clockdomain core_l3_24xx_clkdm = { |
| 99 | .name = "core_l3_clkdm", | 116 | .name = "core_l3_clkdm", |
| 100 | .pwrdm_name = "core_pwrdm", | 117 | .pwrdm = { .name = "core_pwrdm" }, |
| 101 | .flags = CLKDM_CAN_HWSUP, | 118 | .flags = CLKDM_CAN_HWSUP, |
| 102 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, | 119 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
| 103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -105,7 +122,7 @@ static struct clockdomain core_l3_24xx_clkdm = { | |||
| 105 | 122 | ||
| 106 | static struct clockdomain core_l4_24xx_clkdm = { | 123 | static struct clockdomain core_l4_24xx_clkdm = { |
| 107 | .name = "core_l4_clkdm", | 124 | .name = "core_l4_clkdm", |
| 108 | .pwrdm_name = "core_pwrdm", | 125 | .pwrdm = { .name = "core_pwrdm" }, |
| 109 | .flags = CLKDM_CAN_HWSUP, | 126 | .flags = CLKDM_CAN_HWSUP, |
| 110 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, | 127 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
| 111 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -113,7 +130,7 @@ static struct clockdomain core_l4_24xx_clkdm = { | |||
| 113 | 130 | ||
| 114 | static struct clockdomain dss_24xx_clkdm = { | 131 | static struct clockdomain dss_24xx_clkdm = { |
| 115 | .name = "dss_clkdm", | 132 | .name = "dss_clkdm", |
| 116 | .pwrdm_name = "core_pwrdm", | 133 | .pwrdm = { .name = "core_pwrdm" }, |
| 117 | .flags = CLKDM_CAN_HWSUP, | 134 | .flags = CLKDM_CAN_HWSUP, |
| 118 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | 135 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
| 119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -130,7 +147,7 @@ static struct clockdomain dss_24xx_clkdm = { | |||
| 130 | 147 | ||
| 131 | static struct clockdomain mpu_34xx_clkdm = { | 148 | static struct clockdomain mpu_34xx_clkdm = { |
| 132 | .name = "mpu_clkdm", | 149 | .name = "mpu_clkdm", |
| 133 | .pwrdm_name = "mpu_pwrdm", | 150 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 134 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, | 151 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, |
| 135 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | 152 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
| 136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 153 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -138,7 +155,7 @@ static struct clockdomain mpu_34xx_clkdm = { | |||
| 138 | 155 | ||
| 139 | static struct clockdomain neon_clkdm = { | 156 | static struct clockdomain neon_clkdm = { |
| 140 | .name = "neon_clkdm", | 157 | .name = "neon_clkdm", |
| 141 | .pwrdm_name = "neon_pwrdm", | 158 | .pwrdm = { .name = "neon_pwrdm" }, |
| 142 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 159 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 143 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, | 160 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, |
| 144 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 161 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -146,7 +163,7 @@ static struct clockdomain neon_clkdm = { | |||
| 146 | 163 | ||
| 147 | static struct clockdomain iva2_clkdm = { | 164 | static struct clockdomain iva2_clkdm = { |
| 148 | .name = "iva2_clkdm", | 165 | .name = "iva2_clkdm", |
| 149 | .pwrdm_name = "iva2_pwrdm", | 166 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 150 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 167 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 151 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, | 168 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
| 152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -154,7 +171,7 @@ static struct clockdomain iva2_clkdm = { | |||
| 154 | 171 | ||
| 155 | static struct clockdomain gfx_3430es1_clkdm = { | 172 | static struct clockdomain gfx_3430es1_clkdm = { |
| 156 | .name = "gfx_clkdm", | 173 | .name = "gfx_clkdm", |
| 157 | .pwrdm_name = "gfx_pwrdm", | 174 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 158 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 175 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 159 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, | 176 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, |
| 160 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | 177 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), |
| @@ -162,10 +179,10 @@ static struct clockdomain gfx_3430es1_clkdm = { | |||
| 162 | 179 | ||
| 163 | static struct clockdomain sgx_clkdm = { | 180 | static struct clockdomain sgx_clkdm = { |
| 164 | .name = "sgx_clkdm", | 181 | .name = "sgx_clkdm", |
| 165 | .pwrdm_name = "sgx_pwrdm", | 182 | .pwrdm = { .name = "sgx_pwrdm" }, |
| 166 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 183 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 167 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | 184 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
| 168 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 185 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 169 | }; | 186 | }; |
| 170 | 187 | ||
| 171 | /* | 188 | /* |
| @@ -177,7 +194,7 @@ static struct clockdomain sgx_clkdm = { | |||
| 177 | */ | 194 | */ |
| 178 | static struct clockdomain d2d_clkdm = { | 195 | static struct clockdomain d2d_clkdm = { |
| 179 | .name = "d2d_clkdm", | 196 | .name = "d2d_clkdm", |
| 180 | .pwrdm_name = "core_pwrdm", | 197 | .pwrdm = { .name = "core_pwrdm" }, |
| 181 | .flags = CLKDM_CAN_HWSUP, | 198 | .flags = CLKDM_CAN_HWSUP, |
| 182 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, | 199 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
| 183 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -185,7 +202,7 @@ static struct clockdomain d2d_clkdm = { | |||
| 185 | 202 | ||
| 186 | static struct clockdomain core_l3_34xx_clkdm = { | 203 | static struct clockdomain core_l3_34xx_clkdm = { |
| 187 | .name = "core_l3_clkdm", | 204 | .name = "core_l3_clkdm", |
| 188 | .pwrdm_name = "core_pwrdm", | 205 | .pwrdm = { .name = "core_pwrdm" }, |
| 189 | .flags = CLKDM_CAN_HWSUP, | 206 | .flags = CLKDM_CAN_HWSUP, |
| 190 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, | 207 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, |
| 191 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 208 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -193,7 +210,7 @@ static struct clockdomain core_l3_34xx_clkdm = { | |||
| 193 | 210 | ||
| 194 | static struct clockdomain core_l4_34xx_clkdm = { | 211 | static struct clockdomain core_l4_34xx_clkdm = { |
| 195 | .name = "core_l4_clkdm", | 212 | .name = "core_l4_clkdm", |
| 196 | .pwrdm_name = "core_pwrdm", | 213 | .pwrdm = { .name = "core_pwrdm" }, |
| 197 | .flags = CLKDM_CAN_HWSUP, | 214 | .flags = CLKDM_CAN_HWSUP, |
| 198 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, | 215 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, |
| 199 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 216 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -201,7 +218,7 @@ static struct clockdomain core_l4_34xx_clkdm = { | |||
| 201 | 218 | ||
| 202 | static struct clockdomain dss_34xx_clkdm = { | 219 | static struct clockdomain dss_34xx_clkdm = { |
| 203 | .name = "dss_clkdm", | 220 | .name = "dss_clkdm", |
| 204 | .pwrdm_name = "dss_pwrdm", | 221 | .pwrdm = { .name = "dss_pwrdm" }, |
| 205 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 222 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 206 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | 223 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
| 207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 224 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -209,7 +226,7 @@ static struct clockdomain dss_34xx_clkdm = { | |||
| 209 | 226 | ||
| 210 | static struct clockdomain cam_clkdm = { | 227 | static struct clockdomain cam_clkdm = { |
| 211 | .name = "cam_clkdm", | 228 | .name = "cam_clkdm", |
| 212 | .pwrdm_name = "cam_pwrdm", | 229 | .pwrdm = { .name = "cam_pwrdm" }, |
| 213 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 230 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 214 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, | 231 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, |
| 215 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 232 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -217,28 +234,62 @@ static struct clockdomain cam_clkdm = { | |||
| 217 | 234 | ||
| 218 | static struct clockdomain usbhost_clkdm = { | 235 | static struct clockdomain usbhost_clkdm = { |
| 219 | .name = "usbhost_clkdm", | 236 | .name = "usbhost_clkdm", |
| 220 | .pwrdm_name = "usbhost_pwrdm", | 237 | .pwrdm = { .name = "usbhost_pwrdm" }, |
| 221 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 238 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 222 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | 239 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
| 223 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 240 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 224 | }; | 241 | }; |
| 225 | 242 | ||
| 226 | static struct clockdomain per_clkdm = { | 243 | static struct clockdomain per_clkdm = { |
| 227 | .name = "per_clkdm", | 244 | .name = "per_clkdm", |
| 228 | .pwrdm_name = "per_pwrdm", | 245 | .pwrdm = { .name = "per_pwrdm" }, |
| 229 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 246 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 230 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | 247 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
| 231 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 248 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 232 | }; | 249 | }; |
| 233 | 250 | ||
| 251 | /* | ||
| 252 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is | ||
| 253 | * switched of even if sdti is in use | ||
| 254 | */ | ||
| 234 | static struct clockdomain emu_clkdm = { | 255 | static struct clockdomain emu_clkdm = { |
| 235 | .name = "emu_clkdm", | 256 | .name = "emu_clkdm", |
| 236 | .pwrdm_name = "emu_pwrdm", | 257 | .pwrdm = { .name = "emu_pwrdm" }, |
| 237 | .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP, | 258 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, |
| 238 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, | 259 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, |
| 239 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 260 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 240 | }; | 261 | }; |
| 241 | 262 | ||
| 263 | static struct clockdomain dpll1_clkdm = { | ||
| 264 | .name = "dpll1_clkdm", | ||
| 265 | .pwrdm = { .name = "dpll1_pwrdm" }, | ||
| 266 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 267 | }; | ||
| 268 | |||
| 269 | static struct clockdomain dpll2_clkdm = { | ||
| 270 | .name = "dpll2_clkdm", | ||
| 271 | .pwrdm = { .name = "dpll2_pwrdm" }, | ||
| 272 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct clockdomain dpll3_clkdm = { | ||
| 276 | .name = "dpll3_clkdm", | ||
| 277 | .pwrdm = { .name = "dpll3_pwrdm" }, | ||
| 278 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct clockdomain dpll4_clkdm = { | ||
| 282 | .name = "dpll4_clkdm", | ||
| 283 | .pwrdm = { .name = "dpll4_pwrdm" }, | ||
| 284 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 285 | }; | ||
| 286 | |||
| 287 | static struct clockdomain dpll5_clkdm = { | ||
| 288 | .name = "dpll5_clkdm", | ||
| 289 | .pwrdm = { .name = "dpll5_pwrdm" }, | ||
| 290 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | ||
| 291 | }; | ||
| 292 | |||
| 242 | #endif /* CONFIG_ARCH_OMAP34XX */ | 293 | #endif /* CONFIG_ARCH_OMAP34XX */ |
| 243 | 294 | ||
| 244 | /* | 295 | /* |
| @@ -247,14 +298,16 @@ static struct clockdomain emu_clkdm = { | |||
| 247 | 298 | ||
| 248 | static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { | 299 | static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { |
| 249 | { | 300 | { |
| 250 | .pwrdm_name = "mpu_pwrdm", | 301 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 251 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 302 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
| 252 | }, | 303 | }, |
| 253 | { | 304 | { |
| 254 | .pwrdm_name = "iva2_pwrdm", | 305 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 255 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 306 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
| 256 | }, | 307 | }, |
| 257 | { NULL } | 308 | { |
| 309 | .pwrdm = { .name = NULL }, | ||
| 310 | } | ||
| 258 | }; | 311 | }; |
| 259 | 312 | ||
| 260 | /* | 313 | /* |
| @@ -264,6 +317,8 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { | |||
| 264 | static struct clockdomain *clockdomains_omap[] = { | 317 | static struct clockdomain *clockdomains_omap[] = { |
| 265 | 318 | ||
| 266 | &wkup_clkdm, | 319 | &wkup_clkdm, |
| 320 | &cm_clkdm, | ||
| 321 | &prm_clkdm, | ||
| 267 | 322 | ||
| 268 | #ifdef CONFIG_ARCH_OMAP2420 | 323 | #ifdef CONFIG_ARCH_OMAP2420 |
| 269 | &mpu_2420_clkdm, | 324 | &mpu_2420_clkdm, |
| @@ -297,6 +352,11 @@ static struct clockdomain *clockdomains_omap[] = { | |||
| 297 | &usbhost_clkdm, | 352 | &usbhost_clkdm, |
| 298 | &per_clkdm, | 353 | &per_clkdm, |
| 299 | &emu_clkdm, | 354 | &emu_clkdm, |
| 355 | &dpll1_clkdm, | ||
| 356 | &dpll2_clkdm, | ||
| 357 | &dpll3_clkdm, | ||
| 358 | &dpll4_clkdm, | ||
| 359 | &dpll5_clkdm, | ||
| 300 | #endif | 360 | #endif |
| 301 | 361 | ||
| 302 | NULL, | 362 | NULL, |
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 1098ecfab861..297a2fe634ea 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -110,35 +110,56 @@ | |||
| 110 | #define OMAP24XX_EN_DES (1 << 0) | 110 | #define OMAP24XX_EN_DES (1 << 0) |
| 111 | 111 | ||
| 112 | /* CM_IDLEST1_CORE specific bits */ | 112 | /* CM_IDLEST1_CORE specific bits */ |
| 113 | #define OMAP24XX_ST_MAILBOXES (1 << 30) | 113 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 |
| 114 | #define OMAP24XX_ST_WDT4 (1 << 29) | 114 | #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) |
| 115 | #define OMAP2420_ST_WDT3 (1 << 28) | 115 | #define OMAP24XX_ST_WDT4_SHIFT 29 |
| 116 | #define OMAP24XX_ST_MSPRO (1 << 27) | 116 | #define OMAP24XX_ST_WDT4_MASK (1 << 29) |
| 117 | #define OMAP24XX_ST_FAC (1 << 25) | 117 | #define OMAP2420_ST_WDT3_SHIFT 28 |
| 118 | #define OMAP2420_ST_EAC (1 << 24) | 118 | #define OMAP2420_ST_WDT3_MASK (1 << 28) |
| 119 | #define OMAP24XX_ST_HDQ (1 << 23) | 119 | #define OMAP24XX_ST_MSPRO_SHIFT 27 |
| 120 | #define OMAP24XX_ST_I2C2 (1 << 20) | 120 | #define OMAP24XX_ST_MSPRO_MASK (1 << 27) |
| 121 | #define OMAP24XX_ST_I2C1 (1 << 19) | 121 | #define OMAP24XX_ST_FAC_SHIFT 25 |
| 122 | #define OMAP24XX_ST_MCBSP2 (1 << 16) | 122 | #define OMAP24XX_ST_FAC_MASK (1 << 25) |
| 123 | #define OMAP24XX_ST_MCBSP1 (1 << 15) | 123 | #define OMAP2420_ST_EAC_SHIFT 24 |
| 124 | #define OMAP24XX_ST_DSS (1 << 0) | 124 | #define OMAP2420_ST_EAC_MASK (1 << 24) |
| 125 | #define OMAP24XX_ST_HDQ_SHIFT 23 | ||
| 126 | #define OMAP24XX_ST_HDQ_MASK (1 << 23) | ||
| 127 | #define OMAP2420_ST_I2C2_SHIFT 20 | ||
| 128 | #define OMAP2420_ST_I2C2_MASK (1 << 20) | ||
| 129 | #define OMAP2420_ST_I2C1_SHIFT 19 | ||
| 130 | #define OMAP2420_ST_I2C1_MASK (1 << 19) | ||
| 131 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 | ||
| 132 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | ||
| 133 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | ||
| 134 | #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) | ||
| 135 | #define OMAP24XX_ST_DSS_SHIFT 0 | ||
| 136 | #define OMAP24XX_ST_DSS_MASK (1 << 0) | ||
| 125 | 137 | ||
| 126 | /* CM_IDLEST2_CORE */ | 138 | /* CM_IDLEST2_CORE */ |
| 127 | #define OMAP2430_ST_MCBSP5 (1 << 5) | 139 | #define OMAP2430_ST_MCBSP5_SHIFT 5 |
| 128 | #define OMAP2430_ST_MCBSP4 (1 << 4) | 140 | #define OMAP2430_ST_MCBSP5_MASK (1 << 5) |
| 129 | #define OMAP2430_ST_MCBSP3 (1 << 3) | 141 | #define OMAP2430_ST_MCBSP4_SHIFT 4 |
| 130 | #define OMAP24XX_ST_SSI (1 << 1) | 142 | #define OMAP2430_ST_MCBSP4_MASK (1 << 4) |
| 143 | #define OMAP2430_ST_MCBSP3_SHIFT 3 | ||
| 144 | #define OMAP2430_ST_MCBSP3_MASK (1 << 3) | ||
| 145 | #define OMAP24XX_ST_SSI_SHIFT 1 | ||
| 146 | #define OMAP24XX_ST_SSI_MASK (1 << 1) | ||
| 131 | 147 | ||
| 132 | /* CM_IDLEST3_CORE */ | 148 | /* CM_IDLEST3_CORE */ |
| 133 | /* 2430 only */ | 149 | /* 2430 only */ |
| 134 | #define OMAP2430_ST_SDRC (1 << 2) | 150 | #define OMAP2430_ST_SDRC_MASK (1 << 2) |
| 135 | 151 | ||
| 136 | /* CM_IDLEST4_CORE */ | 152 | /* CM_IDLEST4_CORE */ |
| 137 | #define OMAP24XX_ST_PKA (1 << 4) | 153 | #define OMAP24XX_ST_PKA_SHIFT 4 |
| 138 | #define OMAP24XX_ST_AES (1 << 3) | 154 | #define OMAP24XX_ST_PKA_MASK (1 << 4) |
| 139 | #define OMAP24XX_ST_RNG (1 << 2) | 155 | #define OMAP24XX_ST_AES_SHIFT 3 |
| 140 | #define OMAP24XX_ST_SHA (1 << 1) | 156 | #define OMAP24XX_ST_AES_MASK (1 << 3) |
| 141 | #define OMAP24XX_ST_DES (1 << 0) | 157 | #define OMAP24XX_ST_RNG_SHIFT 2 |
| 158 | #define OMAP24XX_ST_RNG_MASK (1 << 2) | ||
| 159 | #define OMAP24XX_ST_SHA_SHIFT 1 | ||
| 160 | #define OMAP24XX_ST_SHA_MASK (1 << 1) | ||
| 161 | #define OMAP24XX_ST_DES_SHIFT 0 | ||
| 162 | #define OMAP24XX_ST_DES_MASK (1 << 0) | ||
| 142 | 163 | ||
| 143 | /* CM_AUTOIDLE1_CORE */ | 164 | /* CM_AUTOIDLE1_CORE */ |
| 144 | #define OMAP24XX_AUTO_CAM (1 << 31) | 165 | #define OMAP24XX_AUTO_CAM (1 << 31) |
| @@ -275,11 +296,16 @@ | |||
| 275 | #define OMAP24XX_EN_32KSYNC (1 << 1) | 296 | #define OMAP24XX_EN_32KSYNC (1 << 1) |
| 276 | 297 | ||
| 277 | /* CM_IDLEST_WKUP specific bits */ | 298 | /* CM_IDLEST_WKUP specific bits */ |
| 278 | #define OMAP2430_ST_ICR (1 << 6) | 299 | #define OMAP2430_ST_ICR_SHIFT 6 |
| 279 | #define OMAP24XX_ST_OMAPCTRL (1 << 5) | 300 | #define OMAP2430_ST_ICR_MASK (1 << 6) |
| 280 | #define OMAP24XX_ST_WDT1 (1 << 4) | 301 | #define OMAP24XX_ST_OMAPCTRL_SHIFT 5 |
| 281 | #define OMAP24XX_ST_MPU_WDT (1 << 3) | 302 | #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) |
| 282 | #define OMAP24XX_ST_32KSYNC (1 << 1) | 303 | #define OMAP24XX_ST_WDT1_SHIFT 4 |
| 304 | #define OMAP24XX_ST_WDT1_MASK (1 << 4) | ||
| 305 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 | ||
| 306 | #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3) | ||
| 307 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 | ||
| 308 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | ||
| 283 | 309 | ||
| 284 | /* CM_AUTOIDLE_WKUP */ | 310 | /* CM_AUTOIDLE_WKUP */ |
| 285 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) | 311 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 219f5c8d9659..6f3f5a36aae6 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -183,31 +183,58 @@ | |||
| 183 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | 183 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) |
| 184 | 184 | ||
| 185 | /* CM_IDLEST1_CORE specific bits */ | 185 | /* CM_IDLEST1_CORE specific bits */ |
| 186 | #define OMAP3430_ST_ICR (1 << 29) | 186 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 |
| 187 | #define OMAP3430_ST_AES2 (1 << 28) | 187 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) |
| 188 | #define OMAP3430_ST_SHA12 (1 << 27) | 188 | #define OMAP3430_ST_ICR_SHIFT 29 |
| 189 | #define OMAP3430_ST_DES2 (1 << 26) | 189 | #define OMAP3430_ST_ICR_MASK (1 << 29) |
| 190 | #define OMAP3430_ST_MSPRO (1 << 23) | 190 | #define OMAP3430_ST_AES2_SHIFT 28 |
| 191 | #define OMAP3430_ST_HDQ (1 << 22) | 191 | #define OMAP3430_ST_AES2_MASK (1 << 28) |
| 192 | #define OMAP3430ES1_ST_FAC (1 << 8) | 192 | #define OMAP3430_ST_SHA12_SHIFT 27 |
| 193 | #define OMAP3430ES1_ST_MAILBOXES (1 << 7) | 193 | #define OMAP3430_ST_SHA12_MASK (1 << 27) |
| 194 | #define OMAP3430_ST_OMAPCTRL (1 << 6) | 194 | #define OMAP3430_ST_DES2_SHIFT 26 |
| 195 | #define OMAP3430_ST_SDMA (1 << 2) | 195 | #define OMAP3430_ST_DES2_MASK (1 << 26) |
| 196 | #define OMAP3430_ST_SDRC (1 << 1) | 196 | #define OMAP3430_ST_MSPRO_SHIFT 23 |
| 197 | #define OMAP3430_ST_SSI (1 << 0) | 197 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) |
| 198 | #define OMAP3430_ST_HDQ_SHIFT 22 | ||
| 199 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | ||
| 200 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | ||
| 201 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | ||
| 202 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | ||
| 203 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | ||
| 204 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | ||
| 205 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | ||
| 206 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | ||
| 207 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | ||
| 208 | #define OMAP3430_ST_SDMA_SHIFT 2 | ||
| 209 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | ||
| 210 | #define OMAP3430_ST_SDRC_SHIFT 1 | ||
| 211 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | ||
| 212 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | ||
| 213 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | ||
| 198 | 214 | ||
| 199 | /* CM_IDLEST2_CORE */ | 215 | /* CM_IDLEST2_CORE */ |
| 200 | #define OMAP3430_ST_PKA (1 << 4) | 216 | #define OMAP3430_ST_PKA_SHIFT 4 |
| 201 | #define OMAP3430_ST_AES1 (1 << 3) | 217 | #define OMAP3430_ST_PKA_MASK (1 << 4) |
| 202 | #define OMAP3430_ST_RNG (1 << 2) | 218 | #define OMAP3430_ST_AES1_SHIFT 3 |
| 203 | #define OMAP3430_ST_SHA11 (1 << 1) | 219 | #define OMAP3430_ST_AES1_MASK (1 << 3) |
| 204 | #define OMAP3430_ST_DES1 (1 << 0) | 220 | #define OMAP3430_ST_RNG_SHIFT 2 |
| 221 | #define OMAP3430_ST_RNG_MASK (1 << 2) | ||
| 222 | #define OMAP3430_ST_SHA11_SHIFT 1 | ||
| 223 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | ||
| 224 | #define OMAP3430_ST_DES1_SHIFT 0 | ||
| 225 | #define OMAP3430_ST_DES1_MASK (1 << 0) | ||
| 205 | 226 | ||
| 206 | /* CM_IDLEST3_CORE */ | 227 | /* CM_IDLEST3_CORE */ |
| 207 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | 228 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 |
| 208 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | 229 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) |
| 230 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 | ||
| 231 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | ||
| 209 | 232 | ||
| 210 | /* CM_AUTOIDLE1_CORE */ | 233 | /* CM_AUTOIDLE1_CORE */ |
| 234 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) | ||
| 235 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | ||
| 236 | #define OMAP3430ES2_AUTO_ICR (1 << 29) | ||
| 237 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 | ||
| 211 | #define OMAP3430_AUTO_AES2 (1 << 28) | 238 | #define OMAP3430_AUTO_AES2 (1 << 28) |
| 212 | #define OMAP3430_AUTO_AES2_SHIFT 28 | 239 | #define OMAP3430_AUTO_AES2_SHIFT 28 |
| 213 | #define OMAP3430_AUTO_SHA12 (1 << 27) | 240 | #define OMAP3430_AUTO_SHA12 (1 << 27) |
| @@ -276,6 +303,9 @@ | |||
| 276 | #define OMAP3430_AUTO_DES1_SHIFT 0 | 303 | #define OMAP3430_AUTO_DES1_SHIFT 0 |
| 277 | 304 | ||
| 278 | /* CM_AUTOIDLE3_CORE */ | 305 | /* CM_AUTOIDLE3_CORE */ |
| 306 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) | ||
| 307 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
| 308 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | ||
| 279 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | 309 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 |
| 280 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | 310 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) |
| 281 | 311 | ||
| @@ -332,8 +362,12 @@ | |||
| 332 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | 362 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) |
| 333 | 363 | ||
| 334 | /* CM_FCLKEN_SGX */ | 364 | /* CM_FCLKEN_SGX */ |
| 335 | #define OMAP3430ES2_EN_SGX_SHIFT 1 | 365 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
| 336 | #define OMAP3430ES2_EN_SGX_MASK (1 << 1) | 366 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) |
| 367 | |||
| 368 | /* CM_ICLKEN_SGX */ | ||
| 369 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | ||
| 370 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | ||
| 337 | 371 | ||
| 338 | /* CM_CLKSEL_SGX */ | 372 | /* CM_CLKSEL_SGX */ |
| 339 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | 373 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 |
| @@ -349,6 +383,7 @@ | |||
| 349 | 383 | ||
| 350 | /* CM_FCLKEN_WKUP specific bits */ | 384 | /* CM_FCLKEN_WKUP specific bits */ |
| 351 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | 385 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 |
| 386 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) | ||
| 352 | 387 | ||
| 353 | /* CM_ICLKEN_WKUP specific bits */ | 388 | /* CM_ICLKEN_WKUP specific bits */ |
| 354 | #define OMAP3430_EN_WDT1 (1 << 4) | 389 | #define OMAP3430_EN_WDT1 (1 << 4) |
| @@ -357,11 +392,18 @@ | |||
| 357 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | 392 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
| 358 | 393 | ||
| 359 | /* CM_IDLEST_WKUP specific bits */ | 394 | /* CM_IDLEST_WKUP specific bits */ |
| 360 | #define OMAP3430_ST_WDT2 (1 << 5) | 395 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 |
| 361 | #define OMAP3430_ST_WDT1 (1 << 4) | 396 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) |
| 362 | #define OMAP3430_ST_32KSYNC (1 << 2) | 397 | #define OMAP3430_ST_WDT2_SHIFT 5 |
| 398 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | ||
| 399 | #define OMAP3430_ST_WDT1_SHIFT 4 | ||
| 400 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | ||
| 401 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | ||
| 402 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | ||
| 363 | 403 | ||
| 364 | /* CM_AUTOIDLE_WKUP */ | 404 | /* CM_AUTOIDLE_WKUP */ |
| 405 | #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) | ||
| 406 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | ||
| 365 | #define OMAP3430_AUTO_WDT2 (1 << 5) | 407 | #define OMAP3430_AUTO_WDT2 (1 << 5) |
| 366 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | 408 | #define OMAP3430_AUTO_WDT2_SHIFT 5 |
| 367 | #define OMAP3430_AUTO_WDT1 (1 << 4) | 409 | #define OMAP3430_AUTO_WDT1 (1 << 4) |
| @@ -426,6 +468,8 @@ | |||
| 426 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | 468 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) |
| 427 | 469 | ||
| 428 | /* CM_IDLEST2_CKGEN */ | 470 | /* CM_IDLEST2_CKGEN */ |
| 471 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 | ||
| 472 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | ||
| 429 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | 473 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 |
| 430 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | 474 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) |
| 431 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | 475 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 |
| @@ -449,8 +493,12 @@ | |||
| 449 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | 493 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) |
| 450 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | 494 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 |
| 451 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | 495 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) |
| 452 | #define OMAP3430_SOURCE_54M (1 << 5) | 496 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
| 453 | #define OMAP3430_SOURCE_48M (1 << 3) | 497 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) |
| 498 | #define OMAP3430_SOURCE_54M_SHIFT 5 | ||
| 499 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | ||
| 500 | #define OMAP3430_SOURCE_48M_SHIFT 3 | ||
| 501 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | ||
| 454 | 502 | ||
| 455 | /* CM_CLKSEL2_PLL */ | 503 | /* CM_CLKSEL2_PLL */ |
| 456 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | 504 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 |
| @@ -493,7 +541,12 @@ | |||
| 493 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | 541 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
| 494 | 542 | ||
| 495 | /* CM_IDLEST_DSS */ | 543 | /* CM_IDLEST_DSS */ |
| 496 | #define OMAP3430_ST_DSS (1 << 0) | 544 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
| 545 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | ||
| 546 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | ||
| 547 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | ||
| 548 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | ||
| 549 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | ||
| 497 | 550 | ||
| 498 | /* CM_AUTOIDLE_DSS */ | 551 | /* CM_AUTOIDLE_DSS */ |
| 499 | #define OMAP3430_AUTO_DSS (1 << 0) | 552 | #define OMAP3430_AUTO_DSS (1 << 0) |
| @@ -516,6 +569,8 @@ | |||
| 516 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | 569 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) |
| 517 | 570 | ||
| 518 | /* CM_FCLKEN_CAM specific bits */ | 571 | /* CM_FCLKEN_CAM specific bits */ |
| 572 | #define OMAP3430_EN_CSI2 (1 << 1) | ||
| 573 | #define OMAP3430_EN_CSI2_SHIFT 1 | ||
| 519 | 574 | ||
| 520 | /* CM_ICLKEN_CAM specific bits */ | 575 | /* CM_ICLKEN_CAM specific bits */ |
| 521 | 576 | ||
| @@ -545,10 +600,14 @@ | |||
| 545 | /* CM_ICLKEN_PER specific bits */ | 600 | /* CM_ICLKEN_PER specific bits */ |
| 546 | 601 | ||
| 547 | /* CM_IDLEST_PER */ | 602 | /* CM_IDLEST_PER */ |
| 548 | #define OMAP3430_ST_WDT3 (1 << 12) | 603 | #define OMAP3430_ST_WDT3_SHIFT 12 |
| 549 | #define OMAP3430_ST_MCBSP4 (1 << 2) | 604 | #define OMAP3430_ST_WDT3_MASK (1 << 12) |
| 550 | #define OMAP3430_ST_MCBSP3 (1 << 1) | 605 | #define OMAP3430_ST_MCBSP4_SHIFT 2 |
| 551 | #define OMAP3430_ST_MCBSP2 (1 << 0) | 606 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) |
| 607 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | ||
| 608 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | ||
| 609 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | ||
| 610 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | ||
| 552 | 611 | ||
| 553 | /* CM_AUTOIDLE_PER */ | 612 | /* CM_AUTOIDLE_PER */ |
| 554 | #define OMAP3430_AUTO_GPIO6 (1 << 17) | 613 | #define OMAP3430_AUTO_GPIO6 (1 << 17) |
| @@ -676,6 +735,10 @@ | |||
| 676 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | 735 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) |
| 677 | 736 | ||
| 678 | /* CM_IDLEST_USBHOST */ | 737 | /* CM_IDLEST_USBHOST */ |
| 738 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 | ||
| 739 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | ||
| 740 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | ||
| 741 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | ||
| 679 | 742 | ||
| 680 | /* CM_AUTOIDLE_USBHOST */ | 743 | /* CM_AUTOIDLE_USBHOST */ |
| 681 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | 744 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index ce03fa750775..d6b4b2f8722f 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -28,13 +28,121 @@ | |||
| 28 | #include <mach/eac.h> | 28 | #include <mach/eac.h> |
| 29 | #include <mach/mmc.h> | 29 | #include <mach/mmc.h> |
| 30 | 30 | ||
| 31 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) | 31 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
| 32 | #define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) | ||
| 33 | 32 | ||
| 34 | static struct resource mbox_resources[] = { | 33 | static struct resource cam_resources[] = { |
| 35 | { | 34 | { |
| 36 | .start = OMAP2_MBOX_BASE, | 35 | .start = OMAP24XX_CAMERA_BASE, |
| 37 | .end = OMAP2_MBOX_BASE + 0x11f, | 36 | .end = OMAP24XX_CAMERA_BASE + 0xfff, |
| 37 | .flags = IORESOURCE_MEM, | ||
| 38 | }, | ||
| 39 | { | ||
| 40 | .start = INT_24XX_CAM_IRQ, | ||
| 41 | .flags = IORESOURCE_IRQ, | ||
| 42 | } | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct platform_device omap_cam_device = { | ||
| 46 | .name = "omap24xxcam", | ||
| 47 | .id = -1, | ||
| 48 | .num_resources = ARRAY_SIZE(cam_resources), | ||
| 49 | .resource = cam_resources, | ||
| 50 | }; | ||
| 51 | |||
| 52 | static inline void omap_init_camera(void) | ||
| 53 | { | ||
| 54 | platform_device_register(&omap_cam_device); | ||
| 55 | } | ||
| 56 | |||
| 57 | #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) | ||
| 58 | |||
| 59 | static struct resource omap3isp_resources[] = { | ||
| 60 | { | ||
| 61 | .start = OMAP3430_ISP_BASE, | ||
| 62 | .end = OMAP3430_ISP_END, | ||
| 63 | .flags = IORESOURCE_MEM, | ||
| 64 | }, | ||
| 65 | { | ||
| 66 | .start = OMAP3430_ISP_CBUFF_BASE, | ||
| 67 | .end = OMAP3430_ISP_CBUFF_END, | ||
| 68 | .flags = IORESOURCE_MEM, | ||
| 69 | }, | ||
| 70 | { | ||
| 71 | .start = OMAP3430_ISP_CCP2_BASE, | ||
| 72 | .end = OMAP3430_ISP_CCP2_END, | ||
| 73 | .flags = IORESOURCE_MEM, | ||
| 74 | }, | ||
| 75 | { | ||
| 76 | .start = OMAP3430_ISP_CCDC_BASE, | ||
| 77 | .end = OMAP3430_ISP_CCDC_END, | ||
| 78 | .flags = IORESOURCE_MEM, | ||
| 79 | }, | ||
| 80 | { | ||
| 81 | .start = OMAP3430_ISP_HIST_BASE, | ||
| 82 | .end = OMAP3430_ISP_HIST_END, | ||
| 83 | .flags = IORESOURCE_MEM, | ||
| 84 | }, | ||
| 85 | { | ||
| 86 | .start = OMAP3430_ISP_H3A_BASE, | ||
| 87 | .end = OMAP3430_ISP_H3A_END, | ||
| 88 | .flags = IORESOURCE_MEM, | ||
| 89 | }, | ||
| 90 | { | ||
| 91 | .start = OMAP3430_ISP_PREV_BASE, | ||
| 92 | .end = OMAP3430_ISP_PREV_END, | ||
| 93 | .flags = IORESOURCE_MEM, | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .start = OMAP3430_ISP_RESZ_BASE, | ||
| 97 | .end = OMAP3430_ISP_RESZ_END, | ||
| 98 | .flags = IORESOURCE_MEM, | ||
| 99 | }, | ||
| 100 | { | ||
| 101 | .start = OMAP3430_ISP_SBL_BASE, | ||
| 102 | .end = OMAP3430_ISP_SBL_END, | ||
| 103 | .flags = IORESOURCE_MEM, | ||
| 104 | }, | ||
| 105 | { | ||
| 106 | .start = OMAP3430_ISP_CSI2A_BASE, | ||
| 107 | .end = OMAP3430_ISP_CSI2A_END, | ||
| 108 | .flags = IORESOURCE_MEM, | ||
| 109 | }, | ||
| 110 | { | ||
| 111 | .start = OMAP3430_ISP_CSI2PHY_BASE, | ||
| 112 | .end = OMAP3430_ISP_CSI2PHY_END, | ||
| 113 | .flags = IORESOURCE_MEM, | ||
| 114 | }, | ||
| 115 | { | ||
| 116 | .start = INT_34XX_CAM_IRQ, | ||
| 117 | .flags = IORESOURCE_IRQ, | ||
| 118 | } | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct platform_device omap3isp_device = { | ||
| 122 | .name = "omap3isp", | ||
| 123 | .id = -1, | ||
| 124 | .num_resources = ARRAY_SIZE(omap3isp_resources), | ||
| 125 | .resource = omap3isp_resources, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static inline void omap_init_camera(void) | ||
| 129 | { | ||
| 130 | platform_device_register(&omap3isp_device); | ||
| 131 | } | ||
| 132 | #else | ||
| 133 | static inline void omap_init_camera(void) | ||
| 134 | { | ||
| 135 | } | ||
| 136 | #endif | ||
| 137 | |||
| 138 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) | ||
| 139 | |||
| 140 | #define MBOX_REG_SIZE 0x120 | ||
| 141 | |||
| 142 | static struct resource omap2_mbox_resources[] = { | ||
| 143 | { | ||
| 144 | .start = OMAP24XX_MAILBOX_BASE, | ||
| 145 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | ||
| 38 | .flags = IORESOURCE_MEM, | 146 | .flags = IORESOURCE_MEM, |
| 39 | }, | 147 | }, |
| 40 | { | 148 | { |
| @@ -47,20 +155,40 @@ static struct resource mbox_resources[] = { | |||
| 47 | }, | 155 | }, |
| 48 | }; | 156 | }; |
| 49 | 157 | ||
| 158 | static struct resource omap3_mbox_resources[] = { | ||
| 159 | { | ||
| 160 | .start = OMAP34XX_MAILBOX_BASE, | ||
| 161 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | ||
| 162 | .flags = IORESOURCE_MEM, | ||
| 163 | }, | ||
| 164 | { | ||
| 165 | .start = INT_24XX_MAIL_U0_MPU, | ||
| 166 | .flags = IORESOURCE_IRQ, | ||
| 167 | }, | ||
| 168 | }; | ||
| 169 | |||
| 50 | static struct platform_device mbox_device = { | 170 | static struct platform_device mbox_device = { |
| 51 | .name = "mailbox", | 171 | .name = "omap2-mailbox", |
| 52 | .id = -1, | 172 | .id = -1, |
| 53 | .num_resources = ARRAY_SIZE(mbox_resources), | ||
| 54 | .resource = mbox_resources, | ||
| 55 | }; | 173 | }; |
| 56 | 174 | ||
| 57 | static inline void omap_init_mbox(void) | 175 | static inline void omap_init_mbox(void) |
| 58 | { | 176 | { |
| 177 | if (cpu_is_omap2420()) { | ||
| 178 | mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources); | ||
| 179 | mbox_device.resource = omap2_mbox_resources; | ||
| 180 | } else if (cpu_is_omap3430()) { | ||
| 181 | mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources); | ||
| 182 | mbox_device.resource = omap3_mbox_resources; | ||
| 183 | } else { | ||
| 184 | pr_err("%s: platform not supported\n", __func__); | ||
| 185 | return; | ||
| 186 | } | ||
| 59 | platform_device_register(&mbox_device); | 187 | platform_device_register(&mbox_device); |
| 60 | } | 188 | } |
| 61 | #else | 189 | #else |
| 62 | static inline void omap_init_mbox(void) { } | 190 | static inline void omap_init_mbox(void) { } |
| 63 | #endif | 191 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
| 64 | 192 | ||
| 65 | #if defined(CONFIG_OMAP_STI) | 193 | #if defined(CONFIG_OMAP_STI) |
| 66 | 194 | ||
| @@ -348,11 +476,12 @@ static void __init omap_hsmmc_reset(void) | |||
| 348 | } | 476 | } |
| 349 | 477 | ||
| 350 | dummy_pdev.id = i; | 478 | dummy_pdev.id = i; |
| 351 | iclk = clk_get(dev, "mmchs_ick"); | 479 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
| 480 | iclk = clk_get(dev, "ick"); | ||
| 352 | if (iclk && clk_enable(iclk)) | 481 | if (iclk && clk_enable(iclk)) |
| 353 | iclk = NULL; | 482 | iclk = NULL; |
| 354 | 483 | ||
| 355 | fclk = clk_get(dev, "mmchs_fck"); | 484 | fclk = clk_get(dev, "fck"); |
| 356 | if (fclk && clk_enable(fclk)) | 485 | if (fclk && clk_enable(fclk)) |
| 357 | fclk = NULL; | 486 | fclk = NULL; |
| 358 | 487 | ||
| @@ -506,6 +635,7 @@ static int __init omap2_init_devices(void) | |||
| 506 | * in alphabetical order so they're easier to sort through. | 635 | * in alphabetical order so they're easier to sort through. |
| 507 | */ | 636 | */ |
| 508 | omap_hsmmc_reset(); | 637 | omap_hsmmc_reset(); |
| 638 | omap_init_camera(); | ||
| 509 | omap_init_mbox(); | 639 | omap_init_mbox(); |
| 510 | omap_init_mcspi(); | 640 | omap_init_mcspi(); |
| 511 | omap_hdq_init(); | 641 | omap_hdq_init(); |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index b52a02fc7cd6..34b5914e0f8b 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -217,8 +217,13 @@ void __init omap2_check_revision(void) | |||
| 217 | omap_chip.oc = CHIP_IS_OMAP3430; | 217 | omap_chip.oc = CHIP_IS_OMAP3430; |
| 218 | if (omap_rev() == OMAP3430_REV_ES1_0) | 218 | if (omap_rev() == OMAP3430_REV_ES1_0) |
| 219 | omap_chip.oc |= CHIP_IS_OMAP3430ES1; | 219 | omap_chip.oc |= CHIP_IS_OMAP3430ES1; |
| 220 | else if (omap_rev() > OMAP3430_REV_ES1_0) | 220 | else if (omap_rev() >= OMAP3430_REV_ES2_0 && |
| 221 | omap_rev() <= OMAP3430_REV_ES2_1) | ||
| 221 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; | 222 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; |
| 223 | else if (omap_rev() == OMAP3430_REV_ES3_0) | ||
| 224 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; | ||
| 225 | else if (omap_rev() == OMAP3430_REV_ES3_1) | ||
| 226 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; | ||
| 222 | } else { | 227 | } else { |
| 223 | pr_err("Uninitialized omap_chip, please fix!\n"); | 228 | pr_err("Uninitialized omap_chip, please fix!\n"); |
| 224 | } | 229 | } |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5ea64f926ed5..916fcd3a2328 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -27,8 +27,8 @@ | |||
| 27 | #include <mach/mux.h> | 27 | #include <mach/mux.h> |
| 28 | #include <mach/omapfb.h> | 28 | #include <mach/omapfb.h> |
| 29 | #include <mach/sram.h> | 29 | #include <mach/sram.h> |
| 30 | 30 | #include <mach/sdrc.h> | |
| 31 | #include "memory.h" | 31 | #include <mach/gpmc.h> |
| 32 | 32 | ||
| 33 | #include "clock.h" | 33 | #include "clock.h" |
| 34 | 34 | ||
| @@ -195,12 +195,12 @@ void __init omap2_map_common_io(void) | |||
| 195 | omapfb_reserve_sdram(); | 195 | omapfb_reserve_sdram(); |
| 196 | } | 196 | } |
| 197 | 197 | ||
| 198 | void __init omap2_init_common_hw(void) | 198 | void __init omap2_init_common_hw(struct omap_sdrc_params *sp) |
| 199 | { | 199 | { |
| 200 | omap2_mux_init(); | 200 | omap2_mux_init(); |
| 201 | pwrdm_init(powerdomains_omap); | 201 | pwrdm_init(powerdomains_omap); |
| 202 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); | 202 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); |
| 203 | omap2_clk_init(); | 203 | omap2_clk_init(); |
| 204 | omap2_init_memory(); | 204 | omap2_sdrc_init(sp); |
| 205 | gpmc_init(); | 205 | gpmc_init(); |
| 206 | } | 206 | } |
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 32b7af3c610b..fd5b8a5925cc 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
| @@ -1,9 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Mailbox reservation modules for OMAP2 | 2 | * Mailbox reservation modules for OMAP2/3 |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 Nokia Corporation | 4 | * Copyright (C) 2006-2009 Nokia Corporation |
| 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| 6 | * and Paul Mundt <paul.mundt@nokia.com> | 6 | * and Paul Mundt |
| 7 | * | 7 | * |
| 8 | * This file is subject to the terms and conditions of the GNU General Public | 8 | * This file is subject to the terms and conditions of the GNU General Public |
| 9 | * License. See the file "COPYING" in the main directory of this archive | 9 | * License. See the file "COPYING" in the main directory of this archive |
| @@ -18,40 +18,22 @@ | |||
| 18 | #include <mach/mailbox.h> | 18 | #include <mach/mailbox.h> |
| 19 | #include <mach/irqs.h> | 19 | #include <mach/irqs.h> |
| 20 | 20 | ||
| 21 | #define MAILBOX_REVISION 0x00 | 21 | #define MAILBOX_REVISION 0x000 |
| 22 | #define MAILBOX_SYSCONFIG 0x10 | 22 | #define MAILBOX_SYSCONFIG 0x010 |
| 23 | #define MAILBOX_SYSSTATUS 0x14 | 23 | #define MAILBOX_SYSSTATUS 0x014 |
| 24 | #define MAILBOX_MESSAGE_0 0x40 | 24 | #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) |
| 25 | #define MAILBOX_MESSAGE_1 0x44 | 25 | #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) |
| 26 | #define MAILBOX_MESSAGE_2 0x48 | 26 | #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) |
| 27 | #define MAILBOX_MESSAGE_3 0x4c | 27 | #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) |
| 28 | #define MAILBOX_MESSAGE_4 0x50 | 28 | #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) |
| 29 | #define MAILBOX_MESSAGE_5 0x54 | 29 | |
| 30 | #define MAILBOX_FIFOSTATUS_0 0x80 | 30 | #define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u))) |
| 31 | #define MAILBOX_FIFOSTATUS_1 0x84 | 31 | #define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1)) |
| 32 | #define MAILBOX_FIFOSTATUS_2 0x88 | 32 | |
| 33 | #define MAILBOX_FIFOSTATUS_3 0x8c | 33 | #define MBOX_REG_SIZE 0x120 |
| 34 | #define MAILBOX_FIFOSTATUS_4 0x90 | 34 | #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32)) |
| 35 | #define MAILBOX_FIFOSTATUS_5 0x94 | 35 | |
| 36 | #define MAILBOX_MSGSTATUS_0 0xc0 | 36 | static void __iomem *mbox_base; |
| 37 | #define MAILBOX_MSGSTATUS_1 0xc4 | ||
| 38 | #define MAILBOX_MSGSTATUS_2 0xc8 | ||
| 39 | #define MAILBOX_MSGSTATUS_3 0xcc | ||
| 40 | #define MAILBOX_MSGSTATUS_4 0xd0 | ||
| 41 | #define MAILBOX_MSGSTATUS_5 0xd4 | ||
| 42 | #define MAILBOX_IRQSTATUS_0 0x100 | ||
| 43 | #define MAILBOX_IRQENABLE_0 0x104 | ||
| 44 | #define MAILBOX_IRQSTATUS_1 0x108 | ||
| 45 | #define MAILBOX_IRQENABLE_1 0x10c | ||
| 46 | #define MAILBOX_IRQSTATUS_2 0x110 | ||
| 47 | #define MAILBOX_IRQENABLE_2 0x114 | ||
| 48 | #define MAILBOX_IRQSTATUS_3 0x118 | ||
| 49 | #define MAILBOX_IRQENABLE_3 0x11c | ||
| 50 | |||
| 51 | static unsigned long mbox_base; | ||
| 52 | |||
| 53 | #define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1)) | ||
| 54 | #define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n))) | ||
| 55 | 37 | ||
| 56 | struct omap_mbox2_fifo { | 38 | struct omap_mbox2_fifo { |
| 57 | unsigned long msg; | 39 | unsigned long msg; |
| @@ -66,6 +48,7 @@ struct omap_mbox2_priv { | |||
| 66 | unsigned long irqstatus; | 48 | unsigned long irqstatus; |
| 67 | u32 newmsg_bit; | 49 | u32 newmsg_bit; |
| 68 | u32 notfull_bit; | 50 | u32 notfull_bit; |
| 51 | u32 ctx[MBOX_NR_REGS]; | ||
| 69 | }; | 52 | }; |
| 70 | 53 | ||
| 71 | static struct clk *mbox_ick_handle; | 54 | static struct clk *mbox_ick_handle; |
| @@ -73,14 +56,14 @@ static struct clk *mbox_ick_handle; | |||
| 73 | static void omap2_mbox_enable_irq(struct omap_mbox *mbox, | 56 | static void omap2_mbox_enable_irq(struct omap_mbox *mbox, |
| 74 | omap_mbox_type_t irq); | 57 | omap_mbox_type_t irq); |
| 75 | 58 | ||
| 76 | static inline unsigned int mbox_read_reg(unsigned int reg) | 59 | static inline unsigned int mbox_read_reg(size_t ofs) |
| 77 | { | 60 | { |
| 78 | return __raw_readl(mbox_base + reg); | 61 | return __raw_readl(mbox_base + ofs); |
| 79 | } | 62 | } |
| 80 | 63 | ||
| 81 | static inline void mbox_write_reg(unsigned int val, unsigned int reg) | 64 | static inline void mbox_write_reg(u32 val, size_t ofs) |
| 82 | { | 65 | { |
| 83 | __raw_writel(val, mbox_base + reg); | 66 | __raw_writel(val, mbox_base + ofs); |
| 84 | } | 67 | } |
| 85 | 68 | ||
| 86 | /* Mailbox H/W preparations */ | 69 | /* Mailbox H/W preparations */ |
| @@ -95,6 +78,9 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) | |||
| 95 | } | 78 | } |
| 96 | clk_enable(mbox_ick_handle); | 79 | clk_enable(mbox_ick_handle); |
| 97 | 80 | ||
| 81 | l = mbox_read_reg(MAILBOX_REVISION); | ||
| 82 | pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); | ||
| 83 | |||
| 98 | /* set smart-idle & autoidle */ | 84 | /* set smart-idle & autoidle */ |
| 99 | l = mbox_read_reg(MAILBOX_SYSCONFIG); | 85 | l = mbox_read_reg(MAILBOX_SYSCONFIG); |
| 100 | l |= 0x00000011; | 86 | l |= 0x00000011; |
| @@ -183,6 +169,32 @@ static int omap2_mbox_is_irq(struct omap_mbox *mbox, | |||
| 183 | return (enable & status & bit); | 169 | return (enable & status & bit); |
| 184 | } | 170 | } |
| 185 | 171 | ||
| 172 | static void omap2_mbox_save_ctx(struct omap_mbox *mbox) | ||
| 173 | { | ||
| 174 | int i; | ||
| 175 | struct omap_mbox2_priv *p = mbox->priv; | ||
| 176 | |||
| 177 | for (i = 0; i < MBOX_NR_REGS; i++) { | ||
| 178 | p->ctx[i] = mbox_read_reg(i * sizeof(u32)); | ||
| 179 | |||
| 180 | dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, | ||
| 181 | i, p->ctx[i]); | ||
| 182 | } | ||
| 183 | } | ||
| 184 | |||
| 185 | static void omap2_mbox_restore_ctx(struct omap_mbox *mbox) | ||
| 186 | { | ||
| 187 | int i; | ||
| 188 | struct omap_mbox2_priv *p = mbox->priv; | ||
| 189 | |||
| 190 | for (i = 0; i < MBOX_NR_REGS; i++) { | ||
| 191 | mbox_write_reg(p->ctx[i], i * sizeof(u32)); | ||
| 192 | |||
| 193 | dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, | ||
| 194 | i, p->ctx[i]); | ||
| 195 | } | ||
| 196 | } | ||
| 197 | |||
| 186 | static struct omap_mbox_ops omap2_mbox_ops = { | 198 | static struct omap_mbox_ops omap2_mbox_ops = { |
| 187 | .type = OMAP_MBOX_TYPE2, | 199 | .type = OMAP_MBOX_TYPE2, |
| 188 | .startup = omap2_mbox_startup, | 200 | .startup = omap2_mbox_startup, |
| @@ -195,6 +207,8 @@ static struct omap_mbox_ops omap2_mbox_ops = { | |||
| 195 | .disable_irq = omap2_mbox_disable_irq, | 207 | .disable_irq = omap2_mbox_disable_irq, |
| 196 | .ack_irq = omap2_mbox_ack_irq, | 208 | .ack_irq = omap2_mbox_ack_irq, |
| 197 | .is_irq = omap2_mbox_is_irq, | 209 | .is_irq = omap2_mbox_is_irq, |
| 210 | .save_ctx = omap2_mbox_save_ctx, | ||
| 211 | .restore_ctx = omap2_mbox_restore_ctx, | ||
| 198 | }; | 212 | }; |
| 199 | 213 | ||
| 200 | /* | 214 | /* |
| @@ -209,15 +223,15 @@ static struct omap_mbox_ops omap2_mbox_ops = { | |||
| 209 | /* DSP */ | 223 | /* DSP */ |
| 210 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { | 224 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { |
| 211 | .tx_fifo = { | 225 | .tx_fifo = { |
| 212 | .msg = MAILBOX_MESSAGE_0, | 226 | .msg = MAILBOX_MESSAGE(0), |
| 213 | .fifo_stat = MAILBOX_FIFOSTATUS_0, | 227 | .fifo_stat = MAILBOX_FIFOSTATUS(0), |
| 214 | }, | 228 | }, |
| 215 | .rx_fifo = { | 229 | .rx_fifo = { |
| 216 | .msg = MAILBOX_MESSAGE_1, | 230 | .msg = MAILBOX_MESSAGE(1), |
| 217 | .msg_stat = MAILBOX_MSGSTATUS_1, | 231 | .msg_stat = MAILBOX_MSGSTATUS(1), |
| 218 | }, | 232 | }, |
| 219 | .irqenable = MAILBOX_IRQENABLE_0, | 233 | .irqenable = MAILBOX_IRQENABLE(0), |
| 220 | .irqstatus = MAILBOX_IRQSTATUS_0, | 234 | .irqstatus = MAILBOX_IRQSTATUS(0), |
| 221 | .notfull_bit = MAILBOX_IRQ_NOTFULL(0), | 235 | .notfull_bit = MAILBOX_IRQ_NOTFULL(0), |
| 222 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), | 236 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), |
| 223 | }; | 237 | }; |
| @@ -229,18 +243,18 @@ struct omap_mbox mbox_dsp_info = { | |||
| 229 | }; | 243 | }; |
| 230 | EXPORT_SYMBOL(mbox_dsp_info); | 244 | EXPORT_SYMBOL(mbox_dsp_info); |
| 231 | 245 | ||
| 232 | /* IVA */ | 246 | #if defined(CONFIG_ARCH_OMAP2420) /* IVA */ |
| 233 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { | 247 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { |
| 234 | .tx_fifo = { | 248 | .tx_fifo = { |
| 235 | .msg = MAILBOX_MESSAGE_2, | 249 | .msg = MAILBOX_MESSAGE(2), |
| 236 | .fifo_stat = MAILBOX_FIFOSTATUS_2, | 250 | .fifo_stat = MAILBOX_FIFOSTATUS(2), |
| 237 | }, | 251 | }, |
| 238 | .rx_fifo = { | 252 | .rx_fifo = { |
| 239 | .msg = MAILBOX_MESSAGE_3, | 253 | .msg = MAILBOX_MESSAGE(3), |
| 240 | .msg_stat = MAILBOX_MSGSTATUS_3, | 254 | .msg_stat = MAILBOX_MSGSTATUS(3), |
| 241 | }, | 255 | }, |
| 242 | .irqenable = MAILBOX_IRQENABLE_3, | 256 | .irqenable = MAILBOX_IRQENABLE(3), |
| 243 | .irqstatus = MAILBOX_IRQSTATUS_3, | 257 | .irqstatus = MAILBOX_IRQSTATUS(3), |
| 244 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), | 258 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), |
| 245 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), | 259 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), |
| 246 | }; | 260 | }; |
| @@ -250,17 +264,12 @@ static struct omap_mbox mbox_iva_info = { | |||
| 250 | .ops = &omap2_mbox_ops, | 264 | .ops = &omap2_mbox_ops, |
| 251 | .priv = &omap2_mbox_iva_priv, | 265 | .priv = &omap2_mbox_iva_priv, |
| 252 | }; | 266 | }; |
| 267 | #endif | ||
| 253 | 268 | ||
| 254 | static int __init omap2_mbox_probe(struct platform_device *pdev) | 269 | static int __devinit omap2_mbox_probe(struct platform_device *pdev) |
| 255 | { | 270 | { |
| 256 | struct resource *res; | 271 | struct resource *res; |
| 257 | int ret = 0; | 272 | int ret; |
| 258 | |||
| 259 | if (pdev->num_resources != 3) { | ||
| 260 | dev_err(&pdev->dev, "invalid number of resources: %d\n", | ||
| 261 | pdev->num_resources); | ||
| 262 | return -ENODEV; | ||
| 263 | } | ||
| 264 | 273 | ||
| 265 | /* MBOX base */ | 274 | /* MBOX base */ |
| 266 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 275 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| @@ -268,42 +277,61 @@ static int __init omap2_mbox_probe(struct platform_device *pdev) | |||
| 268 | dev_err(&pdev->dev, "invalid mem resource\n"); | 277 | dev_err(&pdev->dev, "invalid mem resource\n"); |
| 269 | return -ENODEV; | 278 | return -ENODEV; |
| 270 | } | 279 | } |
| 271 | mbox_base = res->start; | 280 | mbox_base = ioremap(res->start, res->end - res->start); |
| 281 | if (!mbox_base) | ||
| 282 | return -ENOMEM; | ||
| 272 | 283 | ||
| 273 | /* DSP IRQ */ | 284 | /* DSP or IVA2 IRQ */ |
| 274 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 285 | mbox_dsp_info.irq = platform_get_irq(pdev, 0); |
| 275 | if (unlikely(!res)) { | 286 | if (mbox_dsp_info.irq < 0) { |
| 276 | dev_err(&pdev->dev, "invalid irq resource\n"); | 287 | dev_err(&pdev->dev, "invalid irq resource\n"); |
| 277 | return -ENODEV; | 288 | ret = -ENODEV; |
| 289 | goto err_dsp; | ||
| 278 | } | 290 | } |
| 279 | mbox_dsp_info.irq = res->start; | ||
| 280 | 291 | ||
| 281 | ret = omap_mbox_register(&mbox_dsp_info); | 292 | ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); |
| 282 | 293 | if (ret) | |
| 283 | /* IVA IRQ */ | 294 | goto err_dsp; |
| 284 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | 295 | |
| 285 | if (unlikely(!res)) { | 296 | #if defined(CONFIG_ARCH_OMAP2420) /* IVA */ |
| 286 | dev_err(&pdev->dev, "invalid irq resource\n"); | 297 | if (cpu_is_omap2420()) { |
| 287 | return -ENODEV; | 298 | /* IVA IRQ */ |
| 299 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | ||
| 300 | if (unlikely(!res)) { | ||
| 301 | dev_err(&pdev->dev, "invalid irq resource\n"); | ||
| 302 | ret = -ENODEV; | ||
| 303 | goto err_iva1; | ||
| 304 | } | ||
| 305 | mbox_iva_info.irq = res->start; | ||
| 306 | ret = omap_mbox_register(&pdev->dev, &mbox_iva_info); | ||
| 307 | if (ret) | ||
| 308 | goto err_iva1; | ||
| 288 | } | 309 | } |
| 289 | mbox_iva_info.irq = res->start; | 310 | #endif |
| 290 | 311 | return 0; | |
| 291 | ret = omap_mbox_register(&mbox_iva_info); | ||
| 292 | 312 | ||
| 313 | err_iva1: | ||
| 314 | omap_mbox_unregister(&mbox_dsp_info); | ||
| 315 | err_dsp: | ||
| 316 | iounmap(mbox_base); | ||
| 293 | return ret; | 317 | return ret; |
| 294 | } | 318 | } |
| 295 | 319 | ||
| 296 | static int omap2_mbox_remove(struct platform_device *pdev) | 320 | static int __devexit omap2_mbox_remove(struct platform_device *pdev) |
| 297 | { | 321 | { |
| 322 | #if defined(CONFIG_ARCH_OMAP2420) | ||
| 323 | omap_mbox_unregister(&mbox_iva_info); | ||
| 324 | #endif | ||
| 298 | omap_mbox_unregister(&mbox_dsp_info); | 325 | omap_mbox_unregister(&mbox_dsp_info); |
| 326 | iounmap(mbox_base); | ||
| 299 | return 0; | 327 | return 0; |
| 300 | } | 328 | } |
| 301 | 329 | ||
| 302 | static struct platform_driver omap2_mbox_driver = { | 330 | static struct platform_driver omap2_mbox_driver = { |
| 303 | .probe = omap2_mbox_probe, | 331 | .probe = omap2_mbox_probe, |
| 304 | .remove = omap2_mbox_remove, | 332 | .remove = __devexit_p(omap2_mbox_remove), |
| 305 | .driver = { | 333 | .driver = { |
| 306 | .name = "mailbox", | 334 | .name = "omap2-mailbox", |
| 307 | }, | 335 | }, |
| 308 | }; | 336 | }; |
| 309 | 337 | ||
| @@ -320,4 +348,7 @@ static void __exit omap2_mbox_exit(void) | |||
| 320 | module_init(omap2_mbox_init); | 348 | module_init(omap2_mbox_init); |
| 321 | module_exit(omap2_mbox_exit); | 349 | module_exit(omap2_mbox_exit); |
| 322 | 350 | ||
| 323 | MODULE_LICENSE("GPL"); | 351 | MODULE_LICENSE("GPL v2"); |
| 352 | MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions"); | ||
| 353 | MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt"); | ||
| 354 | MODULE_ALIAS("platform:omap2-mailbox"); | ||
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index a9e631fc1134..a5c0f0435cd6 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
| @@ -24,8 +24,6 @@ | |||
| 24 | #include <mach/cpu.h> | 24 | #include <mach/cpu.h> |
| 25 | #include <mach/mcbsp.h> | 25 | #include <mach/mcbsp.h> |
| 26 | 26 | ||
| 27 | const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" }; | ||
| 28 | |||
| 29 | static void omap2_mcbsp2_mux_setup(void) | 27 | static void omap2_mcbsp2_mux_setup(void) |
| 30 | { | 28 | { |
| 31 | omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); | 29 | omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); |
| @@ -57,8 +55,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
| 57 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 55 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 58 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 56 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 59 | .ops = &omap2_mcbsp_ops, | 57 | .ops = &omap2_mcbsp_ops, |
| 60 | .clk_names = clk_names, | ||
| 61 | .num_clks = 2, | ||
| 62 | }, | 58 | }, |
| 63 | { | 59 | { |
| 64 | .phys_base = OMAP24XX_MCBSP2_BASE, | 60 | .phys_base = OMAP24XX_MCBSP2_BASE, |
| @@ -67,8 +63,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
| 67 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 63 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 68 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 64 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 69 | .ops = &omap2_mcbsp_ops, | 65 | .ops = &omap2_mcbsp_ops, |
| 70 | .clk_names = clk_names, | ||
| 71 | .num_clks = 2, | ||
| 72 | }, | 66 | }, |
| 73 | }; | 67 | }; |
| 74 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) | 68 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) |
| @@ -86,8 +80,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 86 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 80 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 87 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 81 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 88 | .ops = &omap2_mcbsp_ops, | 82 | .ops = &omap2_mcbsp_ops, |
| 89 | .clk_names = clk_names, | ||
| 90 | .num_clks = 2, | ||
| 91 | }, | 83 | }, |
| 92 | { | 84 | { |
| 93 | .phys_base = OMAP24XX_MCBSP2_BASE, | 85 | .phys_base = OMAP24XX_MCBSP2_BASE, |
| @@ -96,8 +88,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 96 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 88 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 97 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 89 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 98 | .ops = &omap2_mcbsp_ops, | 90 | .ops = &omap2_mcbsp_ops, |
| 99 | .clk_names = clk_names, | ||
| 100 | .num_clks = 2, | ||
| 101 | }, | 91 | }, |
| 102 | { | 92 | { |
| 103 | .phys_base = OMAP2430_MCBSP3_BASE, | 93 | .phys_base = OMAP2430_MCBSP3_BASE, |
| @@ -106,8 +96,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 106 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 96 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 107 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 97 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 108 | .ops = &omap2_mcbsp_ops, | 98 | .ops = &omap2_mcbsp_ops, |
| 109 | .clk_names = clk_names, | ||
| 110 | .num_clks = 2, | ||
| 111 | }, | 99 | }, |
| 112 | { | 100 | { |
| 113 | .phys_base = OMAP2430_MCBSP4_BASE, | 101 | .phys_base = OMAP2430_MCBSP4_BASE, |
| @@ -116,8 +104,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 116 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 104 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 117 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 105 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 118 | .ops = &omap2_mcbsp_ops, | 106 | .ops = &omap2_mcbsp_ops, |
| 119 | .clk_names = clk_names, | ||
| 120 | .num_clks = 2, | ||
| 121 | }, | 107 | }, |
| 122 | { | 108 | { |
| 123 | .phys_base = OMAP2430_MCBSP5_BASE, | 109 | .phys_base = OMAP2430_MCBSP5_BASE, |
| @@ -126,8 +112,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 126 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 112 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 127 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 113 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 128 | .ops = &omap2_mcbsp_ops, | 114 | .ops = &omap2_mcbsp_ops, |
| 129 | .clk_names = clk_names, | ||
| 130 | .num_clks = 2, | ||
| 131 | }, | 115 | }, |
| 132 | }; | 116 | }; |
| 133 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) | 117 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) |
| @@ -145,8 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 145 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 129 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 146 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 130 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 147 | .ops = &omap2_mcbsp_ops, | 131 | .ops = &omap2_mcbsp_ops, |
| 148 | .clk_names = clk_names, | ||
| 149 | .num_clks = 2, | ||
| 150 | }, | 132 | }, |
| 151 | { | 133 | { |
| 152 | .phys_base = OMAP34XX_MCBSP2_BASE, | 134 | .phys_base = OMAP34XX_MCBSP2_BASE, |
| @@ -155,8 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 155 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 137 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 156 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 138 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 157 | .ops = &omap2_mcbsp_ops, | 139 | .ops = &omap2_mcbsp_ops, |
| 158 | .clk_names = clk_names, | ||
| 159 | .num_clks = 2, | ||
| 160 | }, | 140 | }, |
| 161 | { | 141 | { |
| 162 | .phys_base = OMAP34XX_MCBSP3_BASE, | 142 | .phys_base = OMAP34XX_MCBSP3_BASE, |
| @@ -165,8 +145,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 165 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 145 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 166 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 146 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 167 | .ops = &omap2_mcbsp_ops, | 147 | .ops = &omap2_mcbsp_ops, |
| 168 | .clk_names = clk_names, | ||
| 169 | .num_clks = 2, | ||
| 170 | }, | 148 | }, |
| 171 | { | 149 | { |
| 172 | .phys_base = OMAP34XX_MCBSP4_BASE, | 150 | .phys_base = OMAP34XX_MCBSP4_BASE, |
| @@ -175,8 +153,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 175 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 153 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 176 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 154 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 177 | .ops = &omap2_mcbsp_ops, | 155 | .ops = &omap2_mcbsp_ops, |
| 178 | .clk_names = clk_names, | ||
| 179 | .num_clks = 2, | ||
| 180 | }, | 156 | }, |
| 181 | { | 157 | { |
| 182 | .phys_base = OMAP34XX_MCBSP5_BASE, | 158 | .phys_base = OMAP34XX_MCBSP5_BASE, |
| @@ -185,8 +161,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 185 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 161 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 186 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 162 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 187 | .ops = &omap2_mcbsp_ops, | 163 | .ops = &omap2_mcbsp_ops, |
| 188 | .clk_names = clk_names, | ||
| 189 | .num_clks = 2, | ||
| 190 | }, | 164 | }, |
| 191 | }; | 165 | }; |
| 192 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) | 166 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) |
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h deleted file mode 100644 index bb3db80a7c46..000000000000 --- a/arch/arm/mach-omap2/memory.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/memory.h | ||
| 3 | * | ||
| 4 | * Interface for memory timing related functions for OMAP24XX | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Texas Instruments Inc. | ||
| 7 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 8 | * | ||
| 9 | * Copyright (C) 2005 Nokia Corporation | ||
| 10 | * Tony Lindgren <tony@atomide.com> | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H | ||
| 18 | #define ARCH_ARM_MACH_OMAP2_MEMORY_H | ||
| 19 | |||
| 20 | /* Memory timings */ | ||
| 21 | #define M_DDR 1 | ||
| 22 | #define M_LOCK_CTRL (1 << 2) | ||
| 23 | #define M_UNLOCK 0 | ||
| 24 | #define M_LOCK 1 | ||
| 25 | |||
| 26 | struct memory_timings { | ||
| 27 | u32 m_type; /* ddr = 1, sdr = 0 */ | ||
| 28 | u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ | ||
| 29 | u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ | ||
| 30 | u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ | ||
| 31 | u32 base_cs; /* base chip select to use for calculations */ | ||
| 32 | }; | ||
| 33 | |||
| 34 | extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode); | ||
| 35 | extern u32 omap2_memory_get_slow_dll_ctrl(void); | ||
| 36 | extern u32 omap2_memory_get_fast_dll_ctrl(void); | ||
| 37 | extern u32 omap2_memory_get_type(void); | ||
| 38 | u32 omap2_dll_force_needed(void); | ||
| 39 | u32 omap2_reprogram_sdrc(u32 level, u32 force); | ||
| 40 | void __init omap2_init_memory(void); | ||
| 41 | void __init gpmc_init(void); | ||
| 42 | |||
| 43 | #endif | ||
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c index 437f52073f6e..dc40b3e72206 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.c +++ b/arch/arm/mach-omap2/mmc-twl4030.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
| 18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
| 19 | #include <linux/i2c/twl4030.h> | 19 | #include <linux/i2c/twl4030.h> |
| 20 | #include <linux/regulator/machine.h> | ||
| 20 | 21 | ||
| 21 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 22 | #include <mach/control.h> | 23 | #include <mach/control.h> |
| @@ -44,6 +45,7 @@ | |||
| 44 | #define VMMC2_315V 0x0c | 45 | #define VMMC2_315V 0x0c |
| 45 | #define VMMC2_300V 0x0b | 46 | #define VMMC2_300V 0x0b |
| 46 | #define VMMC2_285V 0x0a | 47 | #define VMMC2_285V 0x0a |
| 48 | #define VMMC2_280V 0x09 | ||
| 47 | #define VMMC2_260V 0x08 | 49 | #define VMMC2_260V 0x08 |
| 48 | #define VMMC2_185V 0x06 | 50 | #define VMMC2_185V 0x06 |
| 49 | #define VMMC2_DEDICATED 0x2E | 51 | #define VMMC2_DEDICATED 0x2E |
| @@ -59,8 +61,8 @@ static struct twl_mmc_controller { | |||
| 59 | struct omap_mmc_platform_data *mmc; | 61 | struct omap_mmc_platform_data *mmc; |
| 60 | u8 twl_vmmc_dev_grp; | 62 | u8 twl_vmmc_dev_grp; |
| 61 | u8 twl_mmc_dedicated; | 63 | u8 twl_mmc_dedicated; |
| 62 | char name[HSMMC_NAME_LEN]; | 64 | char name[HSMMC_NAME_LEN + 1]; |
| 63 | } hsmmc[] = { | 65 | } hsmmc[OMAP34XX_NR_MMC] = { |
| 64 | { | 66 | { |
| 65 | .twl_vmmc_dev_grp = VMMC1_DEV_GRP, | 67 | .twl_vmmc_dev_grp = VMMC1_DEV_GRP, |
| 66 | .twl_mmc_dedicated = VMMC1_DEDICATED, | 68 | .twl_mmc_dedicated = VMMC1_DEDICATED, |
| @@ -98,6 +100,14 @@ static int twl_mmc_get_ro(struct device *dev, int slot) | |||
| 98 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | 100 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); |
| 99 | } | 101 | } |
| 100 | 102 | ||
| 103 | static int twl_mmc_get_cover_state(struct device *dev, int slot) | ||
| 104 | { | ||
| 105 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 106 | |||
| 107 | /* NOTE: assumes card detect signal is active-low */ | ||
| 108 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | ||
| 109 | } | ||
| 110 | |||
| 101 | /* | 111 | /* |
| 102 | * MMC Slot Initialization. | 112 | * MMC Slot Initialization. |
| 103 | */ | 113 | */ |
| @@ -166,66 +176,85 @@ static int twl_mmc_resume(struct device *dev, int slot) | |||
| 166 | /* | 176 | /* |
| 167 | * Sets the MMC voltage in twl4030 | 177 | * Sets the MMC voltage in twl4030 |
| 168 | */ | 178 | */ |
| 179 | |||
| 180 | #define MMC1_OCR (MMC_VDD_165_195 \ | ||
| 181 | |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) | ||
| 182 | #define MMC2_OCR (MMC_VDD_165_195 \ | ||
| 183 | |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \ | ||
| 184 | |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) | ||
| 185 | |||
| 169 | static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd) | 186 | static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd) |
| 170 | { | 187 | { |
| 171 | int ret; | 188 | int ret; |
| 172 | u8 vmmc, dev_grp_val; | 189 | u8 vmmc = 0, dev_grp_val; |
| 173 | 190 | ||
| 174 | switch (1 << vdd) { | 191 | if (!vdd) |
| 175 | case MMC_VDD_35_36: | 192 | goto doit; |
| 176 | case MMC_VDD_34_35: | 193 | |
| 177 | case MMC_VDD_33_34: | 194 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) { |
| 178 | case MMC_VDD_32_33: | 195 | /* VMMC1: max 220 mA. And for 8-bit mode, |
| 179 | case MMC_VDD_31_32: | 196 | * VSIM: max 50 mA |
| 180 | case MMC_VDD_30_31: | 197 | */ |
| 181 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | 198 | switch (1 << vdd) { |
| 182 | vmmc = VMMC1_315V; | 199 | case MMC_VDD_165_195: |
| 183 | else | ||
| 184 | vmmc = VMMC2_315V; | ||
| 185 | break; | ||
| 186 | case MMC_VDD_29_30: | ||
| 187 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 188 | vmmc = VMMC1_315V; | ||
| 189 | else | ||
| 190 | vmmc = VMMC2_300V; | ||
| 191 | break; | ||
| 192 | case MMC_VDD_27_28: | ||
| 193 | case MMC_VDD_26_27: | ||
| 194 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 195 | vmmc = VMMC1_285V; | ||
| 196 | else | ||
| 197 | vmmc = VMMC2_285V; | ||
| 198 | break; | ||
| 199 | case MMC_VDD_25_26: | ||
| 200 | case MMC_VDD_24_25: | ||
| 201 | case MMC_VDD_23_24: | ||
| 202 | case MMC_VDD_22_23: | ||
| 203 | case MMC_VDD_21_22: | ||
| 204 | case MMC_VDD_20_21: | ||
| 205 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 206 | vmmc = VMMC1_285V; | ||
| 207 | else | ||
| 208 | vmmc = VMMC2_260V; | ||
| 209 | break; | ||
| 210 | case MMC_VDD_165_195: | ||
| 211 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 212 | vmmc = VMMC1_185V; | 200 | vmmc = VMMC1_185V; |
| 213 | else | 201 | /* and VSIM_180V */ |
| 202 | break; | ||
| 203 | case MMC_VDD_28_29: | ||
| 204 | vmmc = VMMC1_285V; | ||
| 205 | /* and VSIM_280V */ | ||
| 206 | break; | ||
| 207 | case MMC_VDD_29_30: | ||
| 208 | case MMC_VDD_30_31: | ||
| 209 | vmmc = VMMC1_300V; | ||
| 210 | /* and VSIM_300V */ | ||
| 211 | break; | ||
| 212 | case MMC_VDD_31_32: | ||
| 213 | vmmc = VMMC1_315V; | ||
| 214 | /* error if VSIM needed */ | ||
| 215 | break; | ||
| 216 | default: | ||
| 217 | return -EINVAL; | ||
| 218 | } | ||
| 219 | } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) { | ||
| 220 | /* VMMC2: max 100 mA */ | ||
| 221 | switch (1 << vdd) { | ||
| 222 | case MMC_VDD_165_195: | ||
| 214 | vmmc = VMMC2_185V; | 223 | vmmc = VMMC2_185V; |
| 215 | break; | 224 | break; |
| 216 | default: | 225 | case MMC_VDD_25_26: |
| 217 | vmmc = 0; | 226 | case MMC_VDD_26_27: |
| 218 | break; | 227 | vmmc = VMMC2_260V; |
| 228 | break; | ||
| 229 | case MMC_VDD_27_28: | ||
| 230 | vmmc = VMMC2_280V; | ||
| 231 | break; | ||
| 232 | case MMC_VDD_28_29: | ||
| 233 | vmmc = VMMC2_285V; | ||
| 234 | break; | ||
| 235 | case MMC_VDD_29_30: | ||
| 236 | case MMC_VDD_30_31: | ||
| 237 | vmmc = VMMC2_300V; | ||
| 238 | break; | ||
| 239 | case MMC_VDD_31_32: | ||
| 240 | vmmc = VMMC2_315V; | ||
| 241 | break; | ||
| 242 | default: | ||
| 243 | return -EINVAL; | ||
| 244 | } | ||
| 245 | } else { | ||
| 246 | return -EINVAL; | ||
| 219 | } | 247 | } |
| 220 | 248 | ||
| 221 | if (vmmc) | 249 | doit: |
| 250 | if (vdd) | ||
| 222 | dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */ | 251 | dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */ |
| 223 | else | 252 | else |
| 224 | dev_grp_val = LDO_CLR; /* Power down */ | 253 | dev_grp_val = LDO_CLR; /* Power down */ |
| 225 | 254 | ||
| 226 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, | 255 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, |
| 227 | dev_grp_val, c->twl_vmmc_dev_grp); | 256 | dev_grp_val, c->twl_vmmc_dev_grp); |
| 228 | if (ret) | 257 | if (ret || !vdd) |
| 229 | return ret; | 258 | return ret; |
| 230 | 259 | ||
| 231 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, | 260 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, |
| @@ -242,6 +271,14 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, | |||
| 242 | struct twl_mmc_controller *c = &hsmmc[0]; | 271 | struct twl_mmc_controller *c = &hsmmc[0]; |
| 243 | struct omap_mmc_platform_data *mmc = dev->platform_data; | 272 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
| 244 | 273 | ||
| 274 | /* | ||
| 275 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | ||
| 276 | * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both | ||
| 277 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | ||
| 278 | * | ||
| 279 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | ||
| 280 | * is most naturally TWL VSIM; those pins also use PBIAS. | ||
| 281 | */ | ||
| 245 | if (power_on) { | 282 | if (power_on) { |
| 246 | if (cpu_is_omap2430()) { | 283 | if (cpu_is_omap2430()) { |
| 247 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | 284 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); |
| @@ -298,6 +335,12 @@ static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vd | |||
| 298 | struct twl_mmc_controller *c = &hsmmc[1]; | 335 | struct twl_mmc_controller *c = &hsmmc[1]; |
| 299 | struct omap_mmc_platform_data *mmc = dev->platform_data; | 336 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
| 300 | 337 | ||
| 338 | /* | ||
| 339 | * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP | ||
| 340 | * VDDS is used to power the pins, optionally with a transceiver to | ||
| 341 | * support cards using voltages other than VDDS (1.8V nominal). When a | ||
| 342 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | ||
| 343 | */ | ||
| 301 | if (power_on) { | 344 | if (power_on) { |
| 302 | if (mmc->slots[0].internal_clock) { | 345 | if (mmc->slots[0].internal_clock) { |
| 303 | u32 reg; | 346 | u32 reg; |
| @@ -314,6 +357,16 @@ static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vd | |||
| 314 | return ret; | 357 | return ret; |
| 315 | } | 358 | } |
| 316 | 359 | ||
| 360 | static int twl_mmc3_set_power(struct device *dev, int slot, int power_on, | ||
| 361 | int vdd) | ||
| 362 | { | ||
| 363 | /* | ||
| 364 | * Assume MMC3 has self-powered device connected, for example on-board | ||
| 365 | * chip with external power source. | ||
| 366 | */ | ||
| 367 | return 0; | ||
| 368 | } | ||
| 369 | |||
| 317 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; | 370 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; |
| 318 | 371 | ||
| 319 | void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | 372 | void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) |
| @@ -349,13 +402,13 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | |||
| 349 | return; | 402 | return; |
| 350 | } | 403 | } |
| 351 | 404 | ||
| 352 | sprintf(twl->name, "mmc%islot%i", c->mmc, 1); | 405 | if (c->name) |
| 406 | strncpy(twl->name, c->name, HSMMC_NAME_LEN); | ||
| 407 | else | ||
| 408 | snprintf(twl->name, ARRAY_SIZE(twl->name), | ||
| 409 | "mmc%islot%i", c->mmc, 1); | ||
| 353 | mmc->slots[0].name = twl->name; | 410 | mmc->slots[0].name = twl->name; |
| 354 | mmc->nr_slots = 1; | 411 | mmc->nr_slots = 1; |
| 355 | mmc->slots[0].ocr_mask = MMC_VDD_165_195 | | ||
| 356 | MMC_VDD_26_27 | MMC_VDD_27_28 | | ||
| 357 | MMC_VDD_29_30 | | ||
| 358 | MMC_VDD_30_31 | MMC_VDD_31_32; | ||
| 359 | mmc->slots[0].wires = c->wires; | 412 | mmc->slots[0].wires = c->wires; |
| 360 | mmc->slots[0].internal_clock = !c->ext_clock; | 413 | mmc->slots[0].internal_clock = !c->ext_clock; |
| 361 | mmc->dma_mask = 0xffffffff; | 414 | mmc->dma_mask = 0xffffffff; |
| @@ -369,7 +422,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | |||
| 369 | 422 | ||
| 370 | mmc->slots[0].switch_pin = c->gpio_cd; | 423 | mmc->slots[0].switch_pin = c->gpio_cd; |
| 371 | mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); | 424 | mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); |
| 372 | mmc->slots[0].card_detect = twl_mmc_card_detect; | 425 | if (c->cover_only) |
| 426 | mmc->slots[0].get_cover_state = twl_mmc_get_cover_state; | ||
| 427 | else | ||
| 428 | mmc->slots[0].card_detect = twl_mmc_card_detect; | ||
| 373 | } else | 429 | } else |
| 374 | mmc->slots[0].switch_pin = -EINVAL; | 430 | mmc->slots[0].switch_pin = -EINVAL; |
| 375 | 431 | ||
| @@ -385,24 +441,43 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | |||
| 385 | 441 | ||
| 386 | /* NOTE: we assume OMAP's MMC1 and MMC2 use | 442 | /* NOTE: we assume OMAP's MMC1 and MMC2 use |
| 387 | * the TWL4030's VMMC1 and VMMC2, respectively; | 443 | * the TWL4030's VMMC1 and VMMC2, respectively; |
| 388 | * and that OMAP's MMC3 isn't used. | 444 | * and that MMC3 device has it's own power source. |
| 389 | */ | 445 | */ |
| 390 | 446 | ||
| 391 | switch (c->mmc) { | 447 | switch (c->mmc) { |
| 392 | case 1: | 448 | case 1: |
| 393 | mmc->slots[0].set_power = twl_mmc1_set_power; | 449 | mmc->slots[0].set_power = twl_mmc1_set_power; |
| 450 | mmc->slots[0].ocr_mask = MMC1_OCR; | ||
| 394 | break; | 451 | break; |
| 395 | case 2: | 452 | case 2: |
| 396 | mmc->slots[0].set_power = twl_mmc2_set_power; | 453 | mmc->slots[0].set_power = twl_mmc2_set_power; |
| 454 | if (c->transceiver) | ||
| 455 | mmc->slots[0].ocr_mask = MMC2_OCR; | ||
| 456 | else | ||
| 457 | mmc->slots[0].ocr_mask = MMC_VDD_165_195; | ||
| 458 | break; | ||
| 459 | case 3: | ||
| 460 | mmc->slots[0].set_power = twl_mmc3_set_power; | ||
| 461 | mmc->slots[0].ocr_mask = MMC_VDD_165_195; | ||
| 397 | break; | 462 | break; |
| 398 | default: | 463 | default: |
| 399 | pr_err("MMC%d configuration not supported!\n", c->mmc); | 464 | pr_err("MMC%d configuration not supported!\n", c->mmc); |
| 465 | kfree(mmc); | ||
| 400 | continue; | 466 | continue; |
| 401 | } | 467 | } |
| 402 | hsmmc_data[c->mmc - 1] = mmc; | 468 | hsmmc_data[c->mmc - 1] = mmc; |
| 403 | } | 469 | } |
| 404 | 470 | ||
| 405 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); | 471 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); |
| 472 | |||
| 473 | /* pass the device nodes back to board setup code */ | ||
| 474 | for (c = controllers; c->mmc; c++) { | ||
| 475 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | ||
| 476 | |||
| 477 | if (!c->mmc || c->mmc > nr_hsmmc) | ||
| 478 | continue; | ||
| 479 | c->dev = mmc->dev; | ||
| 480 | } | ||
| 406 | } | 481 | } |
| 407 | 482 | ||
| 408 | #endif | 483 | #endif |
diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/mmc-twl4030.h index e1c8076400ca..ea59e8624290 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.h +++ b/arch/arm/mach-omap2/mmc-twl4030.h | |||
| @@ -9,9 +9,13 @@ | |||
| 9 | struct twl4030_hsmmc_info { | 9 | struct twl4030_hsmmc_info { |
| 10 | u8 mmc; /* controller 1/2/3 */ | 10 | u8 mmc; /* controller 1/2/3 */ |
| 11 | u8 wires; /* 1/4/8 wires */ | 11 | u8 wires; /* 1/4/8 wires */ |
| 12 | bool transceiver; /* MMC-2 option */ | ||
| 13 | bool ext_clock; /* use external pin for input clock */ | ||
| 14 | bool cover_only; /* No card detect - just cover switch */ | ||
| 12 | int gpio_cd; /* or -EINVAL */ | 15 | int gpio_cd; /* or -EINVAL */ |
| 13 | int gpio_wp; /* or -EINVAL */ | 16 | int gpio_wp; /* or -EINVAL */ |
| 14 | int ext_clock:1; /* use external pin for input clock */ | 17 | char *name; /* or NULL for default */ |
| 18 | struct device *dev; /* returned: pointer to mmc adapter */ | ||
| 15 | }; | 19 | }; |
| 16 | 20 | ||
| 17 | #if defined(CONFIG_TWL4030_CORE) && \ | 21 | #if defined(CONFIG_TWL4030_CORE) && \ |
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index dacb41f130c0..026c4fc883a7 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
| @@ -453,10 +453,37 @@ MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, | |||
| 453 | 453 | ||
| 454 | 454 | ||
| 455 | /* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix. | 455 | /* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix. |
| 456 | * (Always specify PIN_INPUT, except for names suffixed by "_OUT".) | ||
| 456 | * No internal pullup/pulldown without "_UP" or "_DOWN" suffix. | 457 | * No internal pullup/pulldown without "_UP" or "_DOWN" suffix. |
| 457 | */ | 458 | */ |
| 459 | MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0, | ||
| 460 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 461 | MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18, | ||
| 462 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 458 | MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa, | 463 | MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa, |
| 459 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | 464 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) |
| 465 | MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4, | ||
| 466 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 467 | MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4, | ||
| 468 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
| 469 | MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce, | ||
| 470 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 471 | MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc, | ||
| 472 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 473 | MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160, | ||
| 474 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 475 | MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164, | ||
| 476 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 477 | MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c, | ||
| 478 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) | ||
| 479 | MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e, | ||
| 480 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 481 | MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170, | ||
| 482 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 483 | MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172, | ||
| 484 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 485 | MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c, | ||
| 486 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 460 | MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, | 487 | MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, |
| 461 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | 488 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) |
| 462 | }; | 489 | }; |
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 55361c16c9d9..ea8ceaed09cb 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c | |||
| @@ -103,7 +103,7 @@ static struct platform_suspend_ops omap_pm_ops = { | |||
| 103 | .valid = suspend_valid_only_mem, | 103 | .valid = suspend_valid_only_mem, |
| 104 | }; | 104 | }; |
| 105 | 105 | ||
| 106 | int __init omap2_pm_init(void) | 106 | static int __init omap2_pm_init(void) |
| 107 | { | 107 | { |
| 108 | return 0; | 108 | return 0; |
| 109 | } | 109 | } |
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 1e151faebbd3..691470ea4c6a 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h | |||
| @@ -171,13 +171,19 @@ static struct powerdomain *powerdomains_omap[] __initdata = { | |||
| 171 | &iva2_pwrdm, | 171 | &iva2_pwrdm, |
| 172 | &mpu_34xx_pwrdm, | 172 | &mpu_34xx_pwrdm, |
| 173 | &neon_pwrdm, | 173 | &neon_pwrdm, |
| 174 | &core_34xx_pwrdm, | 174 | &core_34xx_pre_es3_1_pwrdm, |
| 175 | &core_34xx_es3_1_pwrdm, | ||
| 175 | &cam_pwrdm, | 176 | &cam_pwrdm, |
| 176 | &dss_pwrdm, | 177 | &dss_pwrdm, |
| 177 | &per_pwrdm, | 178 | &per_pwrdm, |
| 178 | &emu_pwrdm, | 179 | &emu_pwrdm, |
| 179 | &sgx_pwrdm, | 180 | &sgx_pwrdm, |
| 180 | &usbhost_pwrdm, | 181 | &usbhost_pwrdm, |
| 182 | &dpll1_pwrdm, | ||
| 183 | &dpll2_pwrdm, | ||
| 184 | &dpll3_pwrdm, | ||
| 185 | &dpll4_pwrdm, | ||
| 186 | &dpll5_pwrdm, | ||
| 181 | #endif | 187 | #endif |
| 182 | 188 | ||
| 183 | NULL | 189 | NULL |
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index f573f7108398..4dcf94b800ab 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
| @@ -200,12 +200,33 @@ static struct powerdomain mpu_34xx_pwrdm = { | |||
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | /* No wkdeps or sleepdeps for 34xx core apparently */ | 202 | /* No wkdeps or sleepdeps for 34xx core apparently */ |
| 203 | static struct powerdomain core_34xx_pwrdm = { | 203 | static struct powerdomain core_34xx_pre_es3_1_pwrdm = { |
| 204 | .name = "core_pwrdm", | 204 | .name = "core_pwrdm", |
| 205 | .prcm_offs = CORE_MOD, | 205 | .prcm_offs = CORE_MOD, |
| 206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | |
| 207 | CHIP_IS_OMAP3430ES2 | | ||
| 208 | CHIP_IS_OMAP3430ES3_0), | ||
| 209 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 210 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | ||
| 211 | .banks = 2, | ||
| 212 | .pwrsts_mem_ret = { | ||
| 213 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | ||
| 214 | [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ | ||
| 215 | }, | ||
| 216 | .pwrsts_mem_on = { | ||
| 217 | [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ | ||
| 218 | [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ | ||
| 219 | }, | ||
| 220 | }; | ||
| 221 | |||
| 222 | /* No wkdeps or sleepdeps for 34xx core apparently */ | ||
| 223 | static struct powerdomain core_34xx_es3_1_pwrdm = { | ||
| 224 | .name = "core_pwrdm", | ||
| 225 | .prcm_offs = CORE_MOD, | ||
| 226 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | ||
| 207 | .pwrsts = PWRSTS_OFF_RET_ON, | 227 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 208 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 228 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
| 229 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | ||
| 209 | .banks = 2, | 230 | .banks = 2, |
| 210 | .pwrsts_mem_ret = { | 231 | .pwrsts_mem_ret = { |
| 211 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 232 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
| @@ -236,14 +257,19 @@ static struct powerdomain dss_pwrdm = { | |||
| 236 | }, | 257 | }, |
| 237 | }; | 258 | }; |
| 238 | 259 | ||
| 260 | /* | ||
| 261 | * Although the 34XX TRM Rev K Table 4-371 notes that retention is a | ||
| 262 | * possible SGX powerstate, the SGX device itself does not support | ||
| 263 | * retention. | ||
| 264 | */ | ||
| 239 | static struct powerdomain sgx_pwrdm = { | 265 | static struct powerdomain sgx_pwrdm = { |
| 240 | .name = "sgx_pwrdm", | 266 | .name = "sgx_pwrdm", |
| 241 | .prcm_offs = OMAP3430ES2_SGX_MOD, | 267 | .prcm_offs = OMAP3430ES2_SGX_MOD, |
| 242 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 268 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 243 | .wkdep_srcs = gfx_sgx_wkdeps, | 269 | .wkdep_srcs = gfx_sgx_wkdeps, |
| 244 | .sleepdep_srcs = cam_gfx_sleepdeps, | 270 | .sleepdep_srcs = cam_gfx_sleepdeps, |
| 245 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ | 271 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ |
| 246 | .pwrsts = PWRSTS_OFF_RET_ON, | 272 | .pwrsts = PWRSTS_OFF_ON, |
| 247 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 273 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 248 | .banks = 1, | 274 | .banks = 1, |
| 249 | .pwrsts_mem_ret = { | 275 | .pwrsts_mem_ret = { |
| @@ -307,11 +333,12 @@ static struct powerdomain neon_pwrdm = { | |||
| 307 | static struct powerdomain usbhost_pwrdm = { | 333 | static struct powerdomain usbhost_pwrdm = { |
| 308 | .name = "usbhost_pwrdm", | 334 | .name = "usbhost_pwrdm", |
| 309 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, | 335 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
| 310 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 336 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 311 | .wkdep_srcs = per_usbhost_wkdeps, | 337 | .wkdep_srcs = per_usbhost_wkdeps, |
| 312 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | 338 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, |
| 313 | .pwrsts = PWRSTS_OFF_RET_ON, | 339 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 314 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 340 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 341 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */ | ||
| 315 | .banks = 1, | 342 | .banks = 1, |
| 316 | .pwrsts_mem_ret = { | 343 | .pwrsts_mem_ret = { |
| 317 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ | 344 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
| @@ -321,6 +348,37 @@ static struct powerdomain usbhost_pwrdm = { | |||
| 321 | }, | 348 | }, |
| 322 | }; | 349 | }; |
| 323 | 350 | ||
| 351 | static struct powerdomain dpll1_pwrdm = { | ||
| 352 | .name = "dpll1_pwrdm", | ||
| 353 | .prcm_offs = MPU_MOD, | ||
| 354 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 355 | }; | ||
| 356 | |||
| 357 | static struct powerdomain dpll2_pwrdm = { | ||
| 358 | .name = "dpll2_pwrdm", | ||
| 359 | .prcm_offs = OMAP3430_IVA2_MOD, | ||
| 360 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 361 | }; | ||
| 362 | |||
| 363 | static struct powerdomain dpll3_pwrdm = { | ||
| 364 | .name = "dpll3_pwrdm", | ||
| 365 | .prcm_offs = PLL_MOD, | ||
| 366 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 367 | }; | ||
| 368 | |||
| 369 | static struct powerdomain dpll4_pwrdm = { | ||
| 370 | .name = "dpll4_pwrdm", | ||
| 371 | .prcm_offs = PLL_MOD, | ||
| 372 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 373 | }; | ||
| 374 | |||
| 375 | static struct powerdomain dpll5_pwrdm = { | ||
| 376 | .name = "dpll5_pwrdm", | ||
| 377 | .prcm_offs = PLL_MOD, | ||
| 378 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | ||
| 379 | }; | ||
| 380 | |||
| 381 | |||
| 324 | #endif /* CONFIG_ARCH_OMAP34XX */ | 382 | #endif /* CONFIG_ARCH_OMAP34XX */ |
| 325 | 383 | ||
| 326 | 384 | ||
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 4a32822ff3fc..812d50ee495d 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -113,33 +113,58 @@ | |||
| 113 | #define OMAP2430_EN_USBHS (1 << 6) | 113 | #define OMAP2430_EN_USBHS (1 << 6) |
| 114 | 114 | ||
| 115 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | 115 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ |
| 116 | #define OMAP2420_ST_MMC (1 << 26) | 116 | #define OMAP2420_ST_MMC_SHIFT 26 |
| 117 | #define OMAP24XX_ST_UART2 (1 << 22) | 117 | #define OMAP2420_ST_MMC_MASK (1 << 26) |
| 118 | #define OMAP24XX_ST_UART1 (1 << 21) | 118 | #define OMAP24XX_ST_UART2_SHIFT 22 |
| 119 | #define OMAP24XX_ST_MCSPI2 (1 << 18) | 119 | #define OMAP24XX_ST_UART2_MASK (1 << 22) |
| 120 | #define OMAP24XX_ST_MCSPI1 (1 << 17) | 120 | #define OMAP24XX_ST_UART1_SHIFT 21 |
| 121 | #define OMAP24XX_ST_GPT12 (1 << 14) | 121 | #define OMAP24XX_ST_UART1_MASK (1 << 21) |
| 122 | #define OMAP24XX_ST_GPT11 (1 << 13) | 122 | #define OMAP24XX_ST_MCSPI2_SHIFT 18 |
| 123 | #define OMAP24XX_ST_GPT10 (1 << 12) | 123 | #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) |
| 124 | #define OMAP24XX_ST_GPT9 (1 << 11) | 124 | #define OMAP24XX_ST_MCSPI1_SHIFT 17 |
| 125 | #define OMAP24XX_ST_GPT8 (1 << 10) | 125 | #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) |
| 126 | #define OMAP24XX_ST_GPT7 (1 << 9) | 126 | #define OMAP24XX_ST_GPT12_SHIFT 14 |
| 127 | #define OMAP24XX_ST_GPT6 (1 << 8) | 127 | #define OMAP24XX_ST_GPT12_MASK (1 << 14) |
| 128 | #define OMAP24XX_ST_GPT5 (1 << 7) | 128 | #define OMAP24XX_ST_GPT11_SHIFT 13 |
| 129 | #define OMAP24XX_ST_GPT4 (1 << 6) | 129 | #define OMAP24XX_ST_GPT11_MASK (1 << 13) |
| 130 | #define OMAP24XX_ST_GPT3 (1 << 5) | 130 | #define OMAP24XX_ST_GPT10_SHIFT 12 |
| 131 | #define OMAP24XX_ST_GPT2 (1 << 4) | 131 | #define OMAP24XX_ST_GPT10_MASK (1 << 12) |
| 132 | #define OMAP2420_ST_VLYNQ (1 << 3) | 132 | #define OMAP24XX_ST_GPT9_SHIFT 11 |
| 133 | #define OMAP24XX_ST_GPT9_MASK (1 << 11) | ||
| 134 | #define OMAP24XX_ST_GPT8_SHIFT 10 | ||
| 135 | #define OMAP24XX_ST_GPT8_MASK (1 << 10) | ||
| 136 | #define OMAP24XX_ST_GPT7_SHIFT 9 | ||
| 137 | #define OMAP24XX_ST_GPT7_MASK (1 << 9) | ||
| 138 | #define OMAP24XX_ST_GPT6_SHIFT 8 | ||
| 139 | #define OMAP24XX_ST_GPT6_MASK (1 << 8) | ||
| 140 | #define OMAP24XX_ST_GPT5_SHIFT 7 | ||
| 141 | #define OMAP24XX_ST_GPT5_MASK (1 << 7) | ||
| 142 | #define OMAP24XX_ST_GPT4_SHIFT 6 | ||
| 143 | #define OMAP24XX_ST_GPT4_MASK (1 << 6) | ||
| 144 | #define OMAP24XX_ST_GPT3_SHIFT 5 | ||
| 145 | #define OMAP24XX_ST_GPT3_MASK (1 << 5) | ||
| 146 | #define OMAP24XX_ST_GPT2_SHIFT 4 | ||
| 147 | #define OMAP24XX_ST_GPT2_MASK (1 << 4) | ||
| 148 | #define OMAP2420_ST_VLYNQ_SHIFT 3 | ||
| 149 | #define OMAP2420_ST_VLYNQ_MASK (1 << 3) | ||
| 133 | 150 | ||
| 134 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ | 151 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ |
| 135 | #define OMAP2430_ST_MDM_INTC (1 << 11) | 152 | #define OMAP2430_ST_MDM_INTC_SHIFT 11 |
| 136 | #define OMAP2430_ST_GPIO5 (1 << 10) | 153 | #define OMAP2430_ST_MDM_INTC_MASK (1 << 11) |
| 137 | #define OMAP2430_ST_MCSPI3 (1 << 9) | 154 | #define OMAP2430_ST_GPIO5_SHIFT 10 |
| 138 | #define OMAP2430_ST_MMCHS2 (1 << 8) | 155 | #define OMAP2430_ST_GPIO5_MASK (1 << 10) |
| 139 | #define OMAP2430_ST_MMCHS1 (1 << 7) | 156 | #define OMAP2430_ST_MCSPI3_SHIFT 9 |
| 140 | #define OMAP2430_ST_USBHS (1 << 6) | 157 | #define OMAP2430_ST_MCSPI3_MASK (1 << 9) |
| 141 | #define OMAP24XX_ST_UART3 (1 << 2) | 158 | #define OMAP2430_ST_MMCHS2_SHIFT 8 |
| 142 | #define OMAP24XX_ST_USB (1 << 0) | 159 | #define OMAP2430_ST_MMCHS2_MASK (1 << 8) |
| 160 | #define OMAP2430_ST_MMCHS1_SHIFT 7 | ||
| 161 | #define OMAP2430_ST_MMCHS1_MASK (1 << 7) | ||
| 162 | #define OMAP2430_ST_USBHS_SHIFT 6 | ||
| 163 | #define OMAP2430_ST_USBHS_MASK (1 << 6) | ||
| 164 | #define OMAP24XX_ST_UART3_SHIFT 2 | ||
| 165 | #define OMAP24XX_ST_UART3_MASK (1 << 2) | ||
| 166 | #define OMAP24XX_ST_USB_SHIFT 0 | ||
| 167 | #define OMAP24XX_ST_USB_MASK (1 << 0) | ||
| 143 | 168 | ||
| 144 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 169 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 145 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | 170 | #define OMAP24XX_EN_GPIOS_SHIFT 2 |
| @@ -148,11 +173,13 @@ | |||
| 148 | #define OMAP24XX_EN_GPT1 (1 << 0) | 173 | #define OMAP24XX_EN_GPT1 (1 << 0) |
| 149 | 174 | ||
| 150 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | 175 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ |
| 151 | #define OMAP24XX_ST_GPIOS (1 << 2) | 176 | #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) |
| 152 | #define OMAP24XX_ST_GPT1 (1 << 0) | 177 | #define OMAP24XX_ST_GPIOS_MASK 2 |
| 178 | #define OMAP24XX_ST_GPT1_SHIFT (1 << 0) | ||
| 179 | #define OMAP24XX_ST_GPT1_MASK 0 | ||
| 153 | 180 | ||
| 154 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ | 181 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ |
| 155 | #define OMAP2430_ST_MDM (1 << 0) | 182 | #define OMAP2430_ST_MDM_SHIFT (1 << 0) |
| 156 | 183 | ||
| 157 | 184 | ||
| 158 | /* 3430 register bits shared between CM & PRM registers */ | 185 | /* 3430 register bits shared between CM & PRM registers */ |
| @@ -205,24 +232,46 @@ | |||
| 205 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | 232 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 |
| 206 | 233 | ||
| 207 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | 234 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ |
| 208 | #define OMAP3430_ST_MMC2 (1 << 25) | 235 | #define OMAP3430_ST_MMC2_SHIFT 25 |
| 209 | #define OMAP3430_ST_MMC1 (1 << 24) | 236 | #define OMAP3430_ST_MMC2_MASK (1 << 25) |
| 210 | #define OMAP3430_ST_MCSPI4 (1 << 21) | 237 | #define OMAP3430_ST_MMC1_SHIFT 24 |
| 211 | #define OMAP3430_ST_MCSPI3 (1 << 20) | 238 | #define OMAP3430_ST_MMC1_MASK (1 << 24) |
| 212 | #define OMAP3430_ST_MCSPI2 (1 << 19) | 239 | #define OMAP3430_ST_MCSPI4_SHIFT 21 |
| 213 | #define OMAP3430_ST_MCSPI1 (1 << 18) | 240 | #define OMAP3430_ST_MCSPI4_MASK (1 << 21) |
| 214 | #define OMAP3430_ST_I2C3 (1 << 17) | 241 | #define OMAP3430_ST_MCSPI3_SHIFT 20 |
| 215 | #define OMAP3430_ST_I2C2 (1 << 16) | 242 | #define OMAP3430_ST_MCSPI3_MASK (1 << 20) |
| 216 | #define OMAP3430_ST_I2C1 (1 << 15) | 243 | #define OMAP3430_ST_MCSPI2_SHIFT 19 |
| 217 | #define OMAP3430_ST_UART2 (1 << 14) | 244 | #define OMAP3430_ST_MCSPI2_MASK (1 << 19) |
| 218 | #define OMAP3430_ST_UART1 (1 << 13) | 245 | #define OMAP3430_ST_MCSPI1_SHIFT 18 |
| 219 | #define OMAP3430_ST_GPT11 (1 << 12) | 246 | #define OMAP3430_ST_MCSPI1_MASK (1 << 18) |
| 220 | #define OMAP3430_ST_GPT10 (1 << 11) | 247 | #define OMAP3430_ST_I2C3_SHIFT 17 |
| 221 | #define OMAP3430_ST_MCBSP5 (1 << 10) | 248 | #define OMAP3430_ST_I2C3_MASK (1 << 17) |
| 222 | #define OMAP3430_ST_MCBSP1 (1 << 9) | 249 | #define OMAP3430_ST_I2C2_SHIFT 16 |
| 223 | #define OMAP3430_ST_FSHOSTUSB (1 << 5) | 250 | #define OMAP3430_ST_I2C2_MASK (1 << 16) |
| 224 | #define OMAP3430_ST_HSOTGUSB (1 << 4) | 251 | #define OMAP3430_ST_I2C1_SHIFT 15 |
| 225 | #define OMAP3430_ST_D2D (1 << 3) | 252 | #define OMAP3430_ST_I2C1_MASK (1 << 15) |
| 253 | #define OMAP3430_ST_UART2_SHIFT 14 | ||
| 254 | #define OMAP3430_ST_UART2_MASK (1 << 14) | ||
| 255 | #define OMAP3430_ST_UART1_SHIFT 13 | ||
| 256 | #define OMAP3430_ST_UART1_MASK (1 << 13) | ||
| 257 | #define OMAP3430_ST_GPT11_SHIFT 12 | ||
| 258 | #define OMAP3430_ST_GPT11_MASK (1 << 12) | ||
| 259 | #define OMAP3430_ST_GPT10_SHIFT 11 | ||
| 260 | #define OMAP3430_ST_GPT10_MASK (1 << 11) | ||
| 261 | #define OMAP3430_ST_MCBSP5_SHIFT 10 | ||
| 262 | #define OMAP3430_ST_MCBSP5_MASK (1 << 10) | ||
| 263 | #define OMAP3430_ST_MCBSP1_SHIFT 9 | ||
| 264 | #define OMAP3430_ST_MCBSP1_MASK (1 << 9) | ||
| 265 | #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 | ||
| 266 | #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) | ||
| 267 | #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 | ||
| 268 | #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) | ||
| 269 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 | ||
| 270 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) | ||
| 271 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 | ||
| 272 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) | ||
| 273 | #define OMAP3430_ST_D2D_SHIFT 3 | ||
| 274 | #define OMAP3430_ST_D2D_MASK (1 << 3) | ||
| 226 | 275 | ||
| 227 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 276 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 228 | #define OMAP3430_EN_GPIO1 (1 << 3) | 277 | #define OMAP3430_EN_GPIO1 (1 << 3) |
| @@ -241,11 +290,16 @@ | |||
| 241 | #define OMAP3430_EN_GPT12_SHIFT 1 | 290 | #define OMAP3430_EN_GPT12_SHIFT 1 |
| 242 | 291 | ||
| 243 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | 292 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ |
| 244 | #define OMAP3430_ST_SR2 (1 << 7) | 293 | #define OMAP3430_ST_SR2_SHIFT 7 |
| 245 | #define OMAP3430_ST_SR1 (1 << 6) | 294 | #define OMAP3430_ST_SR2_MASK (1 << 7) |
| 246 | #define OMAP3430_ST_GPIO1 (1 << 3) | 295 | #define OMAP3430_ST_SR1_SHIFT 6 |
| 247 | #define OMAP3430_ST_GPT12 (1 << 1) | 296 | #define OMAP3430_ST_SR1_MASK (1 << 6) |
| 248 | #define OMAP3430_ST_GPT1 (1 << 0) | 297 | #define OMAP3430_ST_GPIO1_SHIFT 3 |
| 298 | #define OMAP3430_ST_GPIO1_MASK (1 << 3) | ||
| 299 | #define OMAP3430_ST_GPT12_SHIFT 1 | ||
| 300 | #define OMAP3430_ST_GPT12_MASK (1 << 1) | ||
| 301 | #define OMAP3430_ST_GPT1_SHIFT 0 | ||
| 302 | #define OMAP3430_ST_GPT1_MASK (1 << 0) | ||
| 249 | 303 | ||
| 250 | /* | 304 | /* |
| 251 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, | 305 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, |
| @@ -296,20 +350,34 @@ | |||
| 296 | #define OMAP3430_EN_MCBSP2_SHIFT 0 | 350 | #define OMAP3430_EN_MCBSP2_SHIFT 0 |
| 297 | 351 | ||
| 298 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | 352 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ |
| 299 | #define OMAP3430_ST_GPIO6 (1 << 17) | 353 | #define OMAP3430_ST_GPIO6_SHIFT 17 |
| 300 | #define OMAP3430_ST_GPIO5 (1 << 16) | 354 | #define OMAP3430_ST_GPIO6_MASK (1 << 17) |
| 301 | #define OMAP3430_ST_GPIO4 (1 << 15) | 355 | #define OMAP3430_ST_GPIO5_SHIFT 16 |
| 302 | #define OMAP3430_ST_GPIO3 (1 << 14) | 356 | #define OMAP3430_ST_GPIO5_MASK (1 << 16) |
| 303 | #define OMAP3430_ST_GPIO2 (1 << 13) | 357 | #define OMAP3430_ST_GPIO4_SHIFT 15 |
| 304 | #define OMAP3430_ST_UART3 (1 << 11) | 358 | #define OMAP3430_ST_GPIO4_MASK (1 << 15) |
| 305 | #define OMAP3430_ST_GPT9 (1 << 10) | 359 | #define OMAP3430_ST_GPIO3_SHIFT 14 |
| 306 | #define OMAP3430_ST_GPT8 (1 << 9) | 360 | #define OMAP3430_ST_GPIO3_MASK (1 << 14) |
| 307 | #define OMAP3430_ST_GPT7 (1 << 8) | 361 | #define OMAP3430_ST_GPIO2_SHIFT 13 |
| 308 | #define OMAP3430_ST_GPT6 (1 << 7) | 362 | #define OMAP3430_ST_GPIO2_MASK (1 << 13) |
| 309 | #define OMAP3430_ST_GPT5 (1 << 6) | 363 | #define OMAP3430_ST_UART3_SHIFT 11 |
| 310 | #define OMAP3430_ST_GPT4 (1 << 5) | 364 | #define OMAP3430_ST_UART3_MASK (1 << 11) |
| 311 | #define OMAP3430_ST_GPT3 (1 << 4) | 365 | #define OMAP3430_ST_GPT9_SHIFT 10 |
| 312 | #define OMAP3430_ST_GPT2 (1 << 3) | 366 | #define OMAP3430_ST_GPT9_MASK (1 << 10) |
| 367 | #define OMAP3430_ST_GPT8_SHIFT 9 | ||
| 368 | #define OMAP3430_ST_GPT8_MASK (1 << 9) | ||
| 369 | #define OMAP3430_ST_GPT7_SHIFT 8 | ||
| 370 | #define OMAP3430_ST_GPT7_MASK (1 << 8) | ||
| 371 | #define OMAP3430_ST_GPT6_SHIFT 7 | ||
| 372 | #define OMAP3430_ST_GPT6_MASK (1 << 7) | ||
| 373 | #define OMAP3430_ST_GPT5_SHIFT 6 | ||
| 374 | #define OMAP3430_ST_GPT5_MASK (1 << 6) | ||
| 375 | #define OMAP3430_ST_GPT4_SHIFT 5 | ||
| 376 | #define OMAP3430_ST_GPT4_MASK (1 << 5) | ||
| 377 | #define OMAP3430_ST_GPT3_SHIFT 4 | ||
| 378 | #define OMAP3430_ST_GPT3_MASK (1 << 4) | ||
| 379 | #define OMAP3430_ST_GPT2_SHIFT 3 | ||
| 380 | #define OMAP3430_ST_GPT2_MASK (1 << 3) | ||
| 313 | 381 | ||
| 314 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ | 382 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ |
| 315 | #define OMAP3430_EN_CORE_SHIFT 0 | 383 | #define OMAP3430_EN_CORE_SHIFT 0 |
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 5b5ecfe6c999..c6a7940f4287 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
| @@ -366,6 +366,7 @@ | |||
| 366 | 366 | ||
| 367 | /* PM_WKEN_WKUP specific bits */ | 367 | /* PM_WKEN_WKUP specific bits */ |
| 368 | #define OMAP3430_EN_IO (1 << 8) | 368 | #define OMAP3430_EN_IO (1 << 8) |
| 369 | #define OMAP3430_EN_GPIO1 (1 << 3) | ||
| 369 | 370 | ||
| 370 | /* PM_MPUGRPSEL_WKUP specific bits */ | 371 | /* PM_MPUGRPSEL_WKUP specific bits */ |
| 371 | 372 | ||
| @@ -452,6 +453,14 @@ | |||
| 452 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | 453 | #define OMAP3430_CMDRA0_MASK (0xff << 0) |
| 453 | 454 | ||
| 454 | /* PRM_VC_CMD_VAL_0 specific bits */ | 455 | /* PRM_VC_CMD_VAL_0 specific bits */ |
| 456 | #define OMAP3430_VC_CMD_ON_SHIFT 24 | ||
| 457 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) | ||
| 458 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | ||
| 459 | #define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16) | ||
| 460 | #define OMAP3430_VC_CMD_RET_SHIFT 8 | ||
| 461 | #define OMAP3430_VC_CMD_RET_MASK (0xFF << 8) | ||
| 462 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | ||
| 463 | #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) | ||
| 455 | 464 | ||
| 456 | /* PRM_VC_CMD_VAL_1 specific bits */ | 465 | /* PRM_VC_CMD_VAL_1 specific bits */ |
| 457 | 466 | ||
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index e4dc4b17881d..826d326b8062 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h | |||
| @@ -141,6 +141,19 @@ | |||
| 141 | #define PM_PWSTCTRL 0x00e0 | 141 | #define PM_PWSTCTRL 0x00e0 |
| 142 | #define PM_PWSTST 0x00e4 | 142 | #define PM_PWSTST 0x00e4 |
| 143 | 143 | ||
| 144 | /* Omap2 specific registers */ | ||
| 145 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 146 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 147 | |||
| 148 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 149 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 150 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 151 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 152 | |||
| 153 | /* Omap3 specific registers */ | ||
| 154 | #define OMAP3430ES2_PM_WKEN3 0x00f0 | ||
| 155 | #define OMAP3430ES2_PM_WKST3 0x00b8 | ||
| 156 | |||
| 144 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 | 157 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 |
| 145 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL | 158 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL |
| 146 | 159 | ||
| @@ -153,16 +166,6 @@ | |||
| 153 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | 166 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc |
| 154 | 167 | ||
| 155 | 168 | ||
| 156 | /* Architecture-specific registers */ | ||
| 157 | |||
| 158 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 159 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 160 | |||
| 161 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 162 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 163 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 164 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 165 | |||
| 166 | #ifndef __ASSEMBLER__ | 169 | #ifndef __ASSEMBLER__ |
| 167 | 170 | ||
| 168 | /* Power/reset management domain register get/set */ | 171 | /* Power/reset management domain register get/set */ |
| @@ -228,7 +231,6 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | |||
| 228 | #define OMAP_RSTTIME1_SHIFT 0 | 231 | #define OMAP_RSTTIME1_SHIFT 0 |
| 229 | #define OMAP_RSTTIME1_MASK (0xff << 0) | 232 | #define OMAP_RSTTIME1_MASK (0xff << 0) |
| 230 | 233 | ||
| 231 | |||
| 232 | /* PRM_RSTCTRL */ | 234 | /* PRM_RSTCTRL */ |
| 233 | /* Named RM_RSTCTRL_WKUP on the 24xx */ | 235 | /* Named RM_RSTCTRL_WKUP on the 24xx */ |
| 234 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ | 236 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ |
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c new file mode 100644 index 000000000000..2a30060cb4b7 --- /dev/null +++ b/arch/arm/mach-omap2/sdrc.c | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * SMS/SDRC (SDRAM controller) common code for OMAP2/3 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005, 2008 Texas Instruments Inc. | ||
| 5 | * Copyright (C) 2005, 2008 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Tony Lindgren <tony@atomide.com> | ||
| 8 | * Paul Walmsley | ||
| 9 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | #undef DEBUG | ||
| 16 | |||
| 17 | #include <linux/module.h> | ||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/device.h> | ||
| 20 | #include <linux/list.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/delay.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | |||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/clock.h> | ||
| 28 | #include <mach/sram.h> | ||
| 29 | |||
| 30 | #include "prm.h" | ||
| 31 | |||
| 32 | #include <mach/sdrc.h> | ||
| 33 | #include "sdrc.h" | ||
| 34 | |||
| 35 | static struct omap_sdrc_params *sdrc_init_params; | ||
| 36 | |||
| 37 | void __iomem *omap2_sdrc_base; | ||
| 38 | void __iomem *omap2_sms_base; | ||
| 39 | |||
| 40 | |||
| 41 | /** | ||
| 42 | * omap2_sdrc_get_params - return SDRC register values for a given clock rate | ||
| 43 | * @r: SDRC clock rate (in Hz) | ||
| 44 | * | ||
| 45 | * Return pre-calculated values for the SDRC_ACTIM_CTRLA, | ||
| 46 | * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given | ||
| 47 | * SDRC clock rate 'r'. These parameters control various timing | ||
| 48 | * delays in the SDRAM controller that are expressed in terms of the | ||
| 49 | * number of SDRC clock cycles to wait; hence the clock rate | ||
| 50 | * dependency. Note that sdrc_init_params must be sorted rate | ||
| 51 | * descending. Also assumes that both chip-selects use the same | ||
| 52 | * timing parameters. Returns a struct omap_sdrc_params * upon | ||
| 53 | * success, or NULL upon failure. | ||
| 54 | */ | ||
| 55 | struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) | ||
| 56 | { | ||
| 57 | struct omap_sdrc_params *sp; | ||
| 58 | |||
| 59 | sp = sdrc_init_params; | ||
| 60 | |||
| 61 | while (sp->rate != r) | ||
| 62 | sp++; | ||
| 63 | |||
| 64 | if (!sp->rate) | ||
| 65 | return NULL; | ||
| 66 | |||
| 67 | return sp; | ||
| 68 | } | ||
| 69 | |||
| 70 | |||
| 71 | void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) | ||
| 72 | { | ||
| 73 | omap2_sdrc_base = omap2_globals->sdrc; | ||
| 74 | omap2_sms_base = omap2_globals->sms; | ||
| 75 | } | ||
| 76 | |||
| 77 | /* turn on smart idle modes for SDRAM scheduler and controller */ | ||
| 78 | void __init omap2_sdrc_init(struct omap_sdrc_params *sp) | ||
| 79 | { | ||
| 80 | u32 l; | ||
| 81 | |||
| 82 | l = sms_read_reg(SMS_SYSCONFIG); | ||
| 83 | l &= ~(0x3 << 3); | ||
| 84 | l |= (0x2 << 3); | ||
| 85 | sms_write_reg(l, SMS_SYSCONFIG); | ||
| 86 | |||
| 87 | l = sdrc_read_reg(SDRC_SYSCONFIG); | ||
| 88 | l &= ~(0x3 << 3); | ||
| 89 | l |= (0x2 << 3); | ||
| 90 | sdrc_write_reg(l, SDRC_SYSCONFIG); | ||
| 91 | |||
| 92 | sdrc_init_params = sp; | ||
| 93 | } | ||
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/sdrc2xxx.c index 882c70224292..0afdad5ae9fb 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c | |||
| @@ -1,13 +1,14 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/memory.c | 2 | * linux/arch/arm/mach-omap2/sdrc2xxx.c |
| 3 | * | 3 | * |
| 4 | * Memory timing related functions for OMAP24XX | 4 | * SDRAM timing related functions for OMAP2xxx |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2005 Texas Instruments Inc. | 6 | * Copyright (C) 2005, 2008 Texas Instruments Inc. |
| 7 | * Richard Woodruff <r-woodruff2@ti.com> | 7 | * Copyright (C) 2005, 2008 Nokia Corporation |
| 8 | * | 8 | * |
| 9 | * Copyright (C) 2005 Nokia Corporation | ||
| 10 | * Tony Lindgren <tony@atomide.com> | 9 | * Tony Lindgren <tony@atomide.com> |
| 10 | * Paul Walmsley | ||
| 11 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 11 | * | 12 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 13 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as | 14 | * it under the terms of the GNU General Public License version 2 as |
| @@ -28,27 +29,31 @@ | |||
| 28 | #include <mach/sram.h> | 29 | #include <mach/sram.h> |
| 29 | 30 | ||
| 30 | #include "prm.h" | 31 | #include "prm.h" |
| 31 | 32 | #include "clock.h" | |
| 32 | #include "memory.h" | 33 | #include <mach/sdrc.h> |
| 33 | #include "sdrc.h" | 34 | #include "sdrc.h" |
| 34 | 35 | ||
| 35 | void __iomem *omap2_sdrc_base; | 36 | /* Memory timing, DLL mode flags */ |
| 36 | void __iomem *omap2_sms_base; | 37 | #define M_DDR 1 |
| 38 | #define M_LOCK_CTRL (1 << 2) | ||
| 39 | #define M_UNLOCK 0 | ||
| 40 | #define M_LOCK 1 | ||
| 41 | |||
| 37 | 42 | ||
| 38 | static struct memory_timings mem_timings; | 43 | static struct memory_timings mem_timings; |
| 39 | static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; | 44 | static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; |
| 40 | 45 | ||
| 41 | u32 omap2_memory_get_slow_dll_ctrl(void) | 46 | static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void) |
| 42 | { | 47 | { |
| 43 | return mem_timings.slow_dll_ctrl; | 48 | return mem_timings.slow_dll_ctrl; |
| 44 | } | 49 | } |
| 45 | 50 | ||
| 46 | u32 omap2_memory_get_fast_dll_ctrl(void) | 51 | static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void) |
| 47 | { | 52 | { |
| 48 | return mem_timings.fast_dll_ctrl; | 53 | return mem_timings.fast_dll_ctrl; |
| 49 | } | 54 | } |
| 50 | 55 | ||
| 51 | u32 omap2_memory_get_type(void) | 56 | static u32 omap2xxx_sdrc_get_type(void) |
| 52 | { | 57 | { |
| 53 | return mem_timings.m_type; | 58 | return mem_timings.m_type; |
| 54 | } | 59 | } |
| @@ -57,7 +62,7 @@ u32 omap2_memory_get_type(void) | |||
| 57 | * Check the DLL lock state, and return tue if running in unlock mode. | 62 | * Check the DLL lock state, and return tue if running in unlock mode. |
| 58 | * This is needed to compensate for the shifted DLL value in unlock mode. | 63 | * This is needed to compensate for the shifted DLL value in unlock mode. |
| 59 | */ | 64 | */ |
| 60 | u32 omap2_dll_force_needed(void) | 65 | u32 omap2xxx_sdrc_dll_is_unlocked(void) |
| 61 | { | 66 | { |
| 62 | /* dlla and dllb are a set */ | 67 | /* dlla and dllb are a set */ |
| 63 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); | 68 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); |
| @@ -72,8 +77,10 @@ u32 omap2_dll_force_needed(void) | |||
| 72 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. | 77 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. |
| 73 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or | 78 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or |
| 74 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) | 79 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) |
| 80 | * | ||
| 81 | * Used by the clock framework during CORE DPLL changes | ||
| 75 | */ | 82 | */ |
| 76 | u32 omap2_reprogram_sdrc(u32 level, u32 force) | 83 | u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) |
| 77 | { | 84 | { |
| 78 | u32 dll_ctrl, m_type; | 85 | u32 dll_ctrl, m_type; |
| 79 | u32 prev = curr_perf_level; | 86 | u32 prev = curr_perf_level; |
| @@ -82,15 +89,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force) | |||
| 82 | if ((curr_perf_level == level) && !force) | 89 | if ((curr_perf_level == level) && !force) |
| 83 | return prev; | 90 | return prev; |
| 84 | 91 | ||
| 85 | if (level == CORE_CLK_SRC_DPLL) { | 92 | if (level == CORE_CLK_SRC_DPLL) |
| 86 | dll_ctrl = omap2_memory_get_slow_dll_ctrl(); | 93 | dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl(); |
| 87 | } else if (level == CORE_CLK_SRC_DPLL_X2) { | 94 | else if (level == CORE_CLK_SRC_DPLL_X2) |
| 88 | dll_ctrl = omap2_memory_get_fast_dll_ctrl(); | 95 | dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl(); |
| 89 | } else { | 96 | else |
| 90 | return prev; | 97 | return prev; |
| 91 | } | ||
| 92 | 98 | ||
| 93 | m_type = omap2_memory_get_type(); | 99 | m_type = omap2xxx_sdrc_get_type(); |
| 94 | 100 | ||
| 95 | local_irq_save(flags); | 101 | local_irq_save(flags); |
| 96 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); | 102 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); |
| @@ -101,23 +107,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force) | |||
| 101 | return prev; | 107 | return prev; |
| 102 | } | 108 | } |
| 103 | 109 | ||
| 104 | #if !defined(CONFIG_ARCH_OMAP2) | 110 | /* Used by the clock framework during CORE DPLL changes */ |
| 105 | void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | 111 | void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode) |
| 106 | u32 base_cs, u32 force_unlock) | ||
| 107 | { | ||
| 108 | } | ||
| 109 | void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, | ||
| 110 | u32 mem_type) | ||
| 111 | { | ||
| 112 | } | ||
| 113 | #endif | ||
| 114 | |||
| 115 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | ||
| 116 | { | 112 | { |
| 117 | unsigned long dll_cnt; | 113 | unsigned long dll_cnt; |
| 118 | u32 fast_dll = 0; | 114 | u32 fast_dll = 0; |
| 119 | 115 | ||
| 120 | mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ | 116 | /* DDR = 1, SDR = 0 */ |
| 117 | mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); | ||
| 121 | 118 | ||
| 122 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. | 119 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. |
| 123 | * In the case of 2422, its ok to use CS1 instead of CS0. | 120 | * In the case of 2422, its ok to use CS1 instead of CS0. |
| @@ -164,28 +161,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | |||
| 164 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ | 161 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ |
| 165 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); | 162 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); |
| 166 | } | 163 | } |
| 167 | |||
| 168 | void __init omap2_set_globals_memory(struct omap_globals *omap2_globals) | ||
| 169 | { | ||
| 170 | omap2_sdrc_base = omap2_globals->sdrc; | ||
| 171 | omap2_sms_base = omap2_globals->sms; | ||
| 172 | } | ||
| 173 | |||
| 174 | /* turn on smart idle modes for SDRAM scheduler and controller */ | ||
| 175 | void __init omap2_init_memory(void) | ||
| 176 | { | ||
| 177 | u32 l; | ||
| 178 | |||
| 179 | if (!cpu_is_omap2420()) | ||
| 180 | return; | ||
| 181 | |||
| 182 | l = sms_read_reg(SMS_SYSCONFIG); | ||
| 183 | l &= ~(0x3 << 3); | ||
| 184 | l |= (0x2 << 3); | ||
| 185 | sms_write_reg(l, SMS_SYSCONFIG); | ||
| 186 | |||
| 187 | l = sdrc_read_reg(SDRC_SYSCONFIG); | ||
| 188 | l &= ~(0x3 << 3); | ||
| 189 | l |= (0x2 << 3); | ||
| 190 | sdrc_write_reg(l, SDRC_SYSCONFIG); | ||
| 191 | } | ||
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c new file mode 100644 index 000000000000..fc74e913c415 --- /dev/null +++ b/arch/arm/mach-omap2/usb-musb.c | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/usb-musb.c | ||
| 3 | * | ||
| 4 | * This file will contain the board specific details for the | ||
| 5 | * MENTOR USB OTG controller on OMAP3430 | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments | ||
| 8 | * Copyright (C) 2008 Nokia Corporation | ||
| 9 | * Author: Vikram Pandita | ||
| 10 | * | ||
| 11 | * Generalization by: | ||
| 12 | * Felipe Balbi <felipe.balbi@nokia.com> | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | #include <linux/delay.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/dma-mapping.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | |||
| 27 | #include <linux/usb/musb.h> | ||
| 28 | |||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/irqs.h> | ||
| 31 | #include <mach/pm.h> | ||
| 32 | #include <mach/mux.h> | ||
| 33 | #include <mach/usb.h> | ||
| 34 | |||
| 35 | static struct resource musb_resources[] = { | ||
| 36 | [0] = { /* start and end set dynamically */ | ||
| 37 | .flags = IORESOURCE_MEM, | ||
| 38 | }, | ||
| 39 | [1] = { /* general IRQ */ | ||
| 40 | .start = INT_243X_HS_USB_MC, | ||
| 41 | .flags = IORESOURCE_IRQ, | ||
| 42 | }, | ||
| 43 | [2] = { /* DMA IRQ */ | ||
| 44 | .start = INT_243X_HS_USB_DMA, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static int clk_on; | ||
| 50 | |||
| 51 | static int musb_set_clock(struct clk *clk, int state) | ||
| 52 | { | ||
| 53 | if (state) { | ||
| 54 | if (clk_on > 0) | ||
| 55 | return -ENODEV; | ||
| 56 | |||
| 57 | clk_enable(clk); | ||
| 58 | clk_on = 1; | ||
| 59 | } else { | ||
| 60 | if (clk_on == 0) | ||
| 61 | return -ENODEV; | ||
| 62 | |||
| 63 | clk_disable(clk); | ||
| 64 | clk_on = 0; | ||
| 65 | } | ||
| 66 | |||
| 67 | return 0; | ||
| 68 | } | ||
| 69 | |||
| 70 | static struct musb_hdrc_eps_bits musb_eps[] = { | ||
| 71 | { "ep1_tx", 10, }, | ||
| 72 | { "ep1_rx", 10, }, | ||
| 73 | { "ep2_tx", 9, }, | ||
| 74 | { "ep2_rx", 9, }, | ||
| 75 | { "ep3_tx", 3, }, | ||
| 76 | { "ep3_rx", 3, }, | ||
| 77 | { "ep4_tx", 3, }, | ||
| 78 | { "ep4_rx", 3, }, | ||
| 79 | { "ep5_tx", 3, }, | ||
| 80 | { "ep5_rx", 3, }, | ||
| 81 | { "ep6_tx", 3, }, | ||
| 82 | { "ep6_rx", 3, }, | ||
| 83 | { "ep7_tx", 3, }, | ||
| 84 | { "ep7_rx", 3, }, | ||
| 85 | { "ep8_tx", 2, }, | ||
| 86 | { "ep8_rx", 2, }, | ||
| 87 | { "ep9_tx", 2, }, | ||
| 88 | { "ep9_rx", 2, }, | ||
| 89 | { "ep10_tx", 2, }, | ||
| 90 | { "ep10_rx", 2, }, | ||
| 91 | { "ep11_tx", 2, }, | ||
| 92 | { "ep11_rx", 2, }, | ||
| 93 | { "ep12_tx", 2, }, | ||
| 94 | { "ep12_rx", 2, }, | ||
| 95 | { "ep13_tx", 2, }, | ||
| 96 | { "ep13_rx", 2, }, | ||
| 97 | { "ep14_tx", 2, }, | ||
| 98 | { "ep14_rx", 2, }, | ||
| 99 | { "ep15_tx", 2, }, | ||
| 100 | { "ep15_rx", 2, }, | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct musb_hdrc_config musb_config = { | ||
| 104 | .multipoint = 1, | ||
| 105 | .dyn_fifo = 1, | ||
| 106 | .soft_con = 1, | ||
| 107 | .dma = 1, | ||
| 108 | .num_eps = 16, | ||
| 109 | .dma_channels = 7, | ||
| 110 | .dma_req_chan = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), | ||
| 111 | .ram_bits = 12, | ||
| 112 | .eps_bits = musb_eps, | ||
| 113 | }; | ||
| 114 | |||
| 115 | static struct musb_hdrc_platform_data musb_plat = { | ||
| 116 | #ifdef CONFIG_USB_MUSB_OTG | ||
| 117 | .mode = MUSB_OTG, | ||
| 118 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) | ||
| 119 | .mode = MUSB_HOST, | ||
| 120 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) | ||
| 121 | .mode = MUSB_PERIPHERAL, | ||
| 122 | #endif | ||
| 123 | /* .clock is set dynamically */ | ||
| 124 | .set_clock = musb_set_clock, | ||
| 125 | .config = &musb_config, | ||
| 126 | |||
| 127 | /* REVISIT charge pump on TWL4030 can supply up to | ||
| 128 | * 100 mA ... but this value is board-specific, like | ||
| 129 | * "mode", and should be passed to usb_musb_init(). | ||
| 130 | */ | ||
| 131 | .power = 50, /* up to 100 mA */ | ||
| 132 | }; | ||
| 133 | |||
| 134 | static u64 musb_dmamask = DMA_32BIT_MASK; | ||
| 135 | |||
| 136 | static struct platform_device musb_device = { | ||
| 137 | .name = "musb_hdrc", | ||
| 138 | .id = -1, | ||
| 139 | .dev = { | ||
| 140 | .dma_mask = &musb_dmamask, | ||
| 141 | .coherent_dma_mask = DMA_32BIT_MASK, | ||
| 142 | .platform_data = &musb_plat, | ||
| 143 | }, | ||
| 144 | .num_resources = ARRAY_SIZE(musb_resources), | ||
| 145 | .resource = musb_resources, | ||
| 146 | }; | ||
| 147 | |||
| 148 | #ifdef CONFIG_NOP_USB_XCEIV | ||
| 149 | static u64 nop_xceiv_dmamask = DMA_32BIT_MASK; | ||
| 150 | |||
| 151 | static struct platform_device nop_xceiv_device = { | ||
| 152 | .name = "nop_usb_xceiv", | ||
| 153 | .id = -1, | ||
| 154 | .dev = { | ||
| 155 | .dma_mask = &nop_xceiv_dmamask, | ||
| 156 | .coherent_dma_mask = DMA_32BIT_MASK, | ||
| 157 | .platform_data = NULL, | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | #endif | ||
| 161 | |||
| 162 | void __init usb_musb_init(void) | ||
| 163 | { | ||
| 164 | if (cpu_is_omap243x()) | ||
| 165 | musb_resources[0].start = OMAP243X_HS_BASE; | ||
| 166 | else | ||
| 167 | musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; | ||
| 168 | musb_resources[0].end = musb_resources[0].start + SZ_8K - 1; | ||
| 169 | |||
| 170 | /* | ||
| 171 | * REVISIT: This line can be removed once all the platforms using | ||
| 172 | * musb_core.c have been converted to use use clkdev. | ||
| 173 | */ | ||
| 174 | musb_plat.clock = "ick"; | ||
| 175 | |||
| 176 | #ifdef CONFIG_NOP_USB_XCEIV | ||
| 177 | if (platform_device_register(&nop_xceiv_device) < 0) { | ||
| 178 | printk(KERN_ERR "Unable to register NOP-XCEIV device\n"); | ||
| 179 | return; | ||
| 180 | } | ||
| 181 | #endif | ||
| 182 | |||
| 183 | if (platform_device_register(&musb_device) < 0) { | ||
| 184 | printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); | ||
| 185 | return; | ||
| 186 | } | ||
| 187 | } | ||
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index f59a8d0e0824..2c7035d8dcbf 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig | |||
| @@ -71,6 +71,7 @@ config MACH_WRT350N_V2 | |||
| 71 | 71 | ||
| 72 | config MACH_TS78XX | 72 | config MACH_TS78XX |
| 73 | bool "Technologic Systems TS-78xx" | 73 | bool "Technologic Systems TS-78xx" |
| 74 | select PM | ||
| 74 | help | 75 | help |
| 75 | Say 'Y' here if you want your kernel to support the | 76 | Say 'Y' here if you want your kernel to support the |
| 76 | Technologic Systems TS-78xx platform. | 77 | Technologic Systems TS-78xx platform. |
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 0722d6510df1..b31ca4cef365 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c | |||
| @@ -76,7 +76,7 @@ static int __init dns323_dev_id(void) | |||
| 76 | 76 | ||
| 77 | static int __init dns323_pci_init(void) | 77 | static int __init dns323_pci_init(void) |
| 78 | { | 78 | { |
| 79 | /* The 5182 doesn't really use it's PCI bus, and initialising PCI | 79 | /* The 5182 doesn't really use its PCI bus, and initialising PCI |
| 80 | * gets in the way of initialising the SATA controller. | 80 | * gets in the way of initialising the SATA controller. |
| 81 | */ | 81 | */ |
| 82 | if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) | 82 | if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) |
| @@ -418,7 +418,7 @@ static void __init dns323_init(void) | |||
| 418 | orion5x_i2c_init(); | 418 | orion5x_i2c_init(); |
| 419 | orion5x_uart0_init(); | 419 | orion5x_uart0_init(); |
| 420 | 420 | ||
| 421 | /* The 5182 has it's SATA controller on-chip, and needs it's own little | 421 | /* The 5182 has its SATA controller on-chip, and needs its own little |
| 422 | * init routine. | 422 | * init routine. |
| 423 | */ | 423 | */ |
| 424 | if (dns323_dev_id() == MV88F5182_DEV_ID) | 424 | if (dns323_dev_id() == MV88F5182_DEV_ID) |
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h index 08e430757890..9b8db1dcfa83 100644 --- a/arch/arm/mach-orion5x/include/mach/system.h +++ b/arch/arm/mach-orion5x/include/mach/system.h | |||
| @@ -19,7 +19,7 @@ static inline void arch_idle(void) | |||
| 19 | cpu_do_idle(); | 19 | cpu_do_idle(); |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | static inline void arch_reset(char mode) | 22 | static inline void arch_reset(char mode, const char *cmd) |
| 23 | { | 23 | { |
| 24 | /* | 24 | /* |
| 25 | * Enable and issue soft reset | 25 | * Enable and issue soft reset |
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index e0c43b8beb72..c9bf6b81a80d 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c | |||
| @@ -186,7 +186,7 @@ static struct mv_sata_platform_data lsmini_sata_data = { | |||
| 186 | 186 | ||
| 187 | static void lsmini_power_off(void) | 187 | static void lsmini_power_off(void) |
| 188 | { | 188 | { |
| 189 | arch_reset(0); | 189 | arch_reset(0, NULL); |
| 190 | } | 190 | } |
| 191 | 191 | ||
| 192 | 192 | ||
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h new file mode 100644 index 000000000000..0f9cdf458952 --- /dev/null +++ b/arch/arm/mach-orion5x/ts78xx-fpga.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | #define FPGAID(_magic, _rev) ((_magic << 8) + _rev) | ||
| 2 | |||
| 3 | /* | ||
| 4 | * get yer id's from http://ts78xx.digriz.org.uk/ | ||
| 5 | * do *not* make up your own or 'borrow' any! | ||
| 6 | */ | ||
| 7 | enum fpga_ids { | ||
| 8 | /* Technologic Systems */ | ||
| 9 | TS7800_REV_1 = FPGAID(0x00b480, 0x01), | ||
| 10 | TS7800_REV_2 = FPGAID(0x00b480, 0x02), | ||
| 11 | TS7800_REV_3 = FPGAID(0x00b480, 0x03), | ||
| 12 | TS7800_REV_4 = FPGAID(0x00b480, 0x04), | ||
| 13 | TS7800_REV_5 = FPGAID(0x00b480, 0x05), | ||
| 14 | |||
| 15 | /* Unaffordable & Expensive */ | ||
| 16 | UAE_DUMMY = FPGAID(0xffffff, 0x01), | ||
| 17 | }; | ||
| 18 | |||
| 19 | struct fpga_device { | ||
| 20 | unsigned present:1; | ||
| 21 | unsigned init:1; | ||
| 22 | }; | ||
| 23 | |||
| 24 | struct fpga_devices { | ||
| 25 | /* Technologic Systems */ | ||
| 26 | struct fpga_device ts_rtc; | ||
| 27 | struct fpga_device ts_nand; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct ts78xx_fpga_data { | ||
| 31 | unsigned int id; | ||
| 32 | int state; | ||
| 33 | |||
| 34 | struct fpga_devices supports; | ||
| 35 | }; | ||
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 1368e9fd1a06..9a6b397f972d 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c | |||
| @@ -10,17 +10,20 @@ | |||
| 10 | 10 | ||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/sysfs.h> | ||
| 13 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 14 | #include <linux/mtd/physmap.h> | ||
| 15 | #include <linux/mv643xx_eth.h> | 15 | #include <linux/mv643xx_eth.h> |
| 16 | #include <linux/ata_platform.h> | 16 | #include <linux/ata_platform.h> |
| 17 | #include <linux/m48t86.h> | 17 | #include <linux/m48t86.h> |
| 18 | #include <linux/mtd/nand.h> | ||
| 19 | #include <linux/mtd/partitions.h> | ||
| 18 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 19 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 20 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| 21 | #include <mach/orion5x.h> | 23 | #include <mach/orion5x.h> |
| 22 | #include "common.h" | 24 | #include "common.h" |
| 23 | #include "mpp.h" | 25 | #include "mpp.h" |
| 26 | #include "ts78xx-fpga.h" | ||
| 24 | 27 | ||
| 25 | /***************************************************************************** | 28 | /***************************************************************************** |
| 26 | * TS-78xx Info | 29 | * TS-78xx Info |
| @@ -33,18 +36,11 @@ | |||
| 33 | #define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 | 36 | #define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 |
| 34 | #define TS78XX_FPGA_REGS_SIZE SZ_1M | 37 | #define TS78XX_FPGA_REGS_SIZE SZ_1M |
| 35 | 38 | ||
| 36 | #define TS78XX_FPGA_REGS_SYSCON_ID (TS78XX_FPGA_REGS_VIRT_BASE | 0x000) | 39 | static struct ts78xx_fpga_data ts78xx_fpga = { |
| 37 | #define TS78XX_FPGA_REGS_SYSCON_LCDI (TS78XX_FPGA_REGS_VIRT_BASE | 0x004) | 40 | .id = 0, |
| 38 | #define TS78XX_FPGA_REGS_SYSCON_LCDO (TS78XX_FPGA_REGS_VIRT_BASE | 0x008) | 41 | .state = 1, |
| 39 | 42 | /* .supports = ... - populated by ts78xx_fpga_supports() */ | |
| 40 | #define TS78XX_FPGA_REGS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) | 43 | }; |
| 41 | #define TS78XX_FPGA_REGS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * 512kB NOR flash Device | ||
| 45 | */ | ||
| 46 | #define TS78XX_NOR_BOOT_BASE 0xff800000 | ||
| 47 | #define TS78XX_NOR_BOOT_SIZE SZ_512K | ||
| 48 | 44 | ||
| 49 | /***************************************************************************** | 45 | /***************************************************************************** |
| 50 | * I/O Address Mapping | 46 | * I/O Address Mapping |
| @@ -65,73 +61,47 @@ void __init ts78xx_map_io(void) | |||
| 65 | } | 61 | } |
| 66 | 62 | ||
| 67 | /***************************************************************************** | 63 | /***************************************************************************** |
| 68 | * 512kB NOR Boot Flash - the chip is a M25P40 | 64 | * Ethernet |
| 69 | ****************************************************************************/ | 65 | ****************************************************************************/ |
| 70 | static struct mtd_partition ts78xx_nor_boot_flash_resources[] = { | 66 | static struct mv643xx_eth_platform_data ts78xx_eth_data = { |
| 71 | { | 67 | .phy_addr = MV643XX_ETH_PHY_ADDR(0), |
| 72 | .name = "ts-bootrom", | ||
| 73 | .offset = 0, | ||
| 74 | /* only the first 256kB is used */ | ||
| 75 | .size = SZ_256K, | ||
| 76 | .mask_flags = MTD_WRITEABLE, | ||
| 77 | }, | ||
| 78 | }; | ||
| 79 | |||
| 80 | static struct physmap_flash_data ts78xx_nor_boot_flash_data = { | ||
| 81 | .width = 1, | ||
| 82 | .parts = ts78xx_nor_boot_flash_resources, | ||
| 83 | .nr_parts = ARRAY_SIZE(ts78xx_nor_boot_flash_resources), | ||
| 84 | }; | ||
| 85 | |||
| 86 | static struct resource ts78xx_nor_boot_flash_resource = { | ||
| 87 | .flags = IORESOURCE_MEM, | ||
| 88 | .start = TS78XX_NOR_BOOT_BASE, | ||
| 89 | .end = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static struct platform_device ts78xx_nor_boot_flash = { | ||
| 93 | .name = "physmap-flash", | ||
| 94 | .id = -1, | ||
| 95 | .dev = { | ||
| 96 | .platform_data = &ts78xx_nor_boot_flash_data, | ||
| 97 | }, | ||
| 98 | .num_resources = 1, | ||
| 99 | .resource = &ts78xx_nor_boot_flash_resource, | ||
| 100 | }; | 68 | }; |
| 101 | 69 | ||
| 102 | /***************************************************************************** | 70 | /***************************************************************************** |
| 103 | * Ethernet | 71 | * SATA |
| 104 | ****************************************************************************/ | 72 | ****************************************************************************/ |
| 105 | static struct mv643xx_eth_platform_data ts78xx_eth_data = { | 73 | static struct mv_sata_platform_data ts78xx_sata_data = { |
| 106 | .phy_addr = MV643XX_ETH_PHY_ADDR(0), | 74 | .n_ports = 2, |
| 107 | }; | 75 | }; |
| 108 | 76 | ||
| 109 | /***************************************************************************** | 77 | /***************************************************************************** |
| 110 | * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c | 78 | * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c |
| 111 | ****************************************************************************/ | 79 | ****************************************************************************/ |
| 112 | #ifdef CONFIG_RTC_DRV_M48T86 | 80 | #define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) |
| 113 | static unsigned char ts78xx_rtc_readbyte(unsigned long addr) | 81 | #define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) |
| 82 | |||
| 83 | static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr) | ||
| 114 | { | 84 | { |
| 115 | writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); | 85 | writeb(addr, TS_RTC_CTRL); |
| 116 | return readb(TS78XX_FPGA_REGS_RTC_DATA); | 86 | return readb(TS_RTC_DATA); |
| 117 | } | 87 | } |
| 118 | 88 | ||
| 119 | static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr) | 89 | static void ts78xx_ts_rtc_writebyte(unsigned char value, unsigned long addr) |
| 120 | { | 90 | { |
| 121 | writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); | 91 | writeb(addr, TS_RTC_CTRL); |
| 122 | writeb(value, TS78XX_FPGA_REGS_RTC_DATA); | 92 | writeb(value, TS_RTC_DATA); |
| 123 | } | 93 | } |
| 124 | 94 | ||
| 125 | static struct m48t86_ops ts78xx_rtc_ops = { | 95 | static struct m48t86_ops ts78xx_ts_rtc_ops = { |
| 126 | .readbyte = ts78xx_rtc_readbyte, | 96 | .readbyte = ts78xx_ts_rtc_readbyte, |
| 127 | .writebyte = ts78xx_rtc_writebyte, | 97 | .writebyte = ts78xx_ts_rtc_writebyte, |
| 128 | }; | 98 | }; |
| 129 | 99 | ||
| 130 | static struct platform_device ts78xx_rtc_device = { | 100 | static struct platform_device ts78xx_ts_rtc_device = { |
| 131 | .name = "rtc-m48t86", | 101 | .name = "rtc-m48t86", |
| 132 | .id = -1, | 102 | .id = -1, |
| 133 | .dev = { | 103 | .dev = { |
| 134 | .platform_data = &ts78xx_rtc_ops, | 104 | .platform_data = &ts78xx_ts_rtc_ops, |
| 135 | }, | 105 | }, |
| 136 | .num_resources = 0, | 106 | .num_resources = 0, |
| 137 | }; | 107 | }; |
| @@ -146,59 +116,314 @@ static struct platform_device ts78xx_rtc_device = { | |||
| 146 | * TODO: track down a guinea pig without an RTC to see if we can work out a | 116 | * TODO: track down a guinea pig without an RTC to see if we can work out a |
| 147 | * better RTC detection routine | 117 | * better RTC detection routine |
| 148 | */ | 118 | */ |
| 149 | static int __init ts78xx_rtc_init(void) | 119 | static int ts78xx_ts_rtc_load(void) |
| 150 | { | 120 | { |
| 121 | int rc; | ||
| 151 | unsigned char tmp_rtc0, tmp_rtc1; | 122 | unsigned char tmp_rtc0, tmp_rtc1; |
| 152 | 123 | ||
| 153 | tmp_rtc0 = ts78xx_rtc_readbyte(126); | 124 | tmp_rtc0 = ts78xx_ts_rtc_readbyte(126); |
| 154 | tmp_rtc1 = ts78xx_rtc_readbyte(127); | 125 | tmp_rtc1 = ts78xx_ts_rtc_readbyte(127); |
| 155 | 126 | ||
| 156 | ts78xx_rtc_writebyte(0x00, 126); | 127 | ts78xx_ts_rtc_writebyte(0x00, 126); |
| 157 | ts78xx_rtc_writebyte(0x55, 127); | 128 | ts78xx_ts_rtc_writebyte(0x55, 127); |
| 158 | if (ts78xx_rtc_readbyte(127) == 0x55) { | 129 | if (ts78xx_ts_rtc_readbyte(127) == 0x55) { |
| 159 | ts78xx_rtc_writebyte(0xaa, 127); | 130 | ts78xx_ts_rtc_writebyte(0xaa, 127); |
| 160 | if (ts78xx_rtc_readbyte(127) == 0xaa | 131 | if (ts78xx_ts_rtc_readbyte(127) == 0xaa |
| 161 | && ts78xx_rtc_readbyte(126) == 0x00) { | 132 | && ts78xx_ts_rtc_readbyte(126) == 0x00) { |
| 162 | ts78xx_rtc_writebyte(tmp_rtc0, 126); | 133 | ts78xx_ts_rtc_writebyte(tmp_rtc0, 126); |
| 163 | ts78xx_rtc_writebyte(tmp_rtc1, 127); | 134 | ts78xx_ts_rtc_writebyte(tmp_rtc1, 127); |
| 164 | platform_device_register(&ts78xx_rtc_device); | 135 | |
| 165 | return 1; | 136 | if (ts78xx_fpga.supports.ts_rtc.init == 0) { |
| 137 | rc = platform_device_register(&ts78xx_ts_rtc_device); | ||
| 138 | if (!rc) | ||
| 139 | ts78xx_fpga.supports.ts_rtc.init = 1; | ||
| 140 | } else | ||
| 141 | rc = platform_device_add(&ts78xx_ts_rtc_device); | ||
| 142 | |||
| 143 | return rc; | ||
| 166 | } | 144 | } |
| 167 | } | 145 | } |
| 168 | 146 | ||
| 169 | return 0; | 147 | return -ENODEV; |
| 170 | }; | 148 | }; |
| 171 | #else | 149 | |
| 172 | static int __init ts78xx_rtc_init(void) | 150 | static void ts78xx_ts_rtc_unload(void) |
| 173 | { | 151 | { |
| 174 | return 0; | 152 | platform_device_del(&ts78xx_ts_rtc_device); |
| 175 | } | 153 | } |
| 176 | #endif | ||
| 177 | 154 | ||
| 178 | /***************************************************************************** | 155 | /***************************************************************************** |
| 179 | * SATA | 156 | * NAND Flash |
| 180 | ****************************************************************************/ | 157 | ****************************************************************************/ |
| 181 | static struct mv_sata_platform_data ts78xx_sata_data = { | 158 | #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x800) /* VIRT */ |
| 182 | .n_ports = 2, | 159 | #define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x804) /* PHYS */ |
| 160 | |||
| 161 | /* | ||
| 162 | * hardware specific access to control-lines | ||
| 163 | * | ||
| 164 | * ctrl: | ||
| 165 | * NAND_NCE: bit 0 -> bit 2 | ||
| 166 | * NAND_CLE: bit 1 -> bit 1 | ||
| 167 | * NAND_ALE: bit 2 -> bit 0 | ||
| 168 | */ | ||
| 169 | static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, | ||
| 170 | unsigned int ctrl) | ||
| 171 | { | ||
| 172 | struct nand_chip *this = mtd->priv; | ||
| 173 | |||
| 174 | if (ctrl & NAND_CTRL_CHANGE) { | ||
| 175 | unsigned char bits; | ||
| 176 | |||
| 177 | bits = (ctrl & NAND_NCE) << 2; | ||
| 178 | bits |= ctrl & NAND_CLE; | ||
| 179 | bits |= (ctrl & NAND_ALE) >> 2; | ||
| 180 | |||
| 181 | writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL); | ||
| 182 | } | ||
| 183 | |||
| 184 | if (cmd != NAND_CMD_NONE) | ||
| 185 | writeb(cmd, this->IO_ADDR_W); | ||
| 186 | } | ||
| 187 | |||
| 188 | static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd) | ||
| 189 | { | ||
| 190 | return readb(TS_NAND_CTRL) & 0x20; | ||
| 191 | } | ||
| 192 | |||
| 193 | const char *ts_nand_part_probes[] = { "cmdlinepart", NULL }; | ||
| 194 | |||
| 195 | static struct mtd_partition ts78xx_ts_nand_parts[] = { | ||
| 196 | { | ||
| 197 | .name = "mbr", | ||
| 198 | .offset = 0, | ||
| 199 | .size = SZ_128K, | ||
| 200 | .mask_flags = MTD_WRITEABLE, | ||
| 201 | }, { | ||
| 202 | .name = "kernel", | ||
| 203 | .offset = MTDPART_OFS_APPEND, | ||
| 204 | .size = SZ_4M, | ||
| 205 | }, { | ||
| 206 | .name = "initrd", | ||
| 207 | .offset = MTDPART_OFS_APPEND, | ||
| 208 | .size = SZ_4M, | ||
| 209 | }, { | ||
| 210 | .name = "rootfs", | ||
| 211 | .offset = MTDPART_OFS_APPEND, | ||
| 212 | .size = MTDPART_SIZ_FULL, | ||
| 213 | } | ||
| 183 | }; | 214 | }; |
| 184 | 215 | ||
| 216 | static struct platform_nand_data ts78xx_ts_nand_data = { | ||
| 217 | .chip = { | ||
| 218 | .part_probe_types = ts_nand_part_probes, | ||
| 219 | .partitions = ts78xx_ts_nand_parts, | ||
| 220 | .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts), | ||
| 221 | .chip_delay = 15, | ||
| 222 | .options = NAND_USE_FLASH_BBT, | ||
| 223 | }, | ||
| 224 | .ctrl = { | ||
| 225 | /* | ||
| 226 | * The HW ECC offloading functions, used to give about a 9% | ||
| 227 | * performance increase for 'dd if=/dev/mtdblockX' and 5% for | ||
| 228 | * nanddump. This all however was changed by git commit | ||
| 229 | * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is | ||
| 230 | * no performance advantage to be had so we no longer bother | ||
| 231 | */ | ||
| 232 | .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl, | ||
| 233 | .dev_ready = ts78xx_ts_nand_dev_ready, | ||
| 234 | }, | ||
| 235 | }; | ||
| 236 | |||
| 237 | static struct resource ts78xx_ts_nand_resources = { | ||
| 238 | .start = TS_NAND_DATA, | ||
| 239 | .end = TS_NAND_DATA + 4, | ||
| 240 | .flags = IORESOURCE_IO, | ||
| 241 | }; | ||
| 242 | |||
| 243 | static struct platform_device ts78xx_ts_nand_device = { | ||
| 244 | .name = "gen_nand", | ||
| 245 | .id = -1, | ||
| 246 | .dev = { | ||
| 247 | .platform_data = &ts78xx_ts_nand_data, | ||
| 248 | }, | ||
| 249 | .resource = &ts78xx_ts_nand_resources, | ||
| 250 | .num_resources = 1, | ||
| 251 | }; | ||
| 252 | |||
| 253 | static int ts78xx_ts_nand_load(void) | ||
| 254 | { | ||
| 255 | int rc; | ||
| 256 | |||
| 257 | if (ts78xx_fpga.supports.ts_nand.init == 0) { | ||
| 258 | rc = platform_device_register(&ts78xx_ts_nand_device); | ||
| 259 | if (!rc) | ||
| 260 | ts78xx_fpga.supports.ts_nand.init = 1; | ||
| 261 | } else | ||
| 262 | rc = platform_device_add(&ts78xx_ts_nand_device); | ||
| 263 | |||
| 264 | return rc; | ||
| 265 | }; | ||
| 266 | |||
| 267 | static void ts78xx_ts_nand_unload(void) | ||
| 268 | { | ||
| 269 | platform_device_del(&ts78xx_ts_nand_device); | ||
| 270 | } | ||
| 271 | |||
| 185 | /***************************************************************************** | 272 | /***************************************************************************** |
| 186 | * print some information regarding the board | 273 | * FPGA 'hotplug' support code |
| 187 | ****************************************************************************/ | 274 | ****************************************************************************/ |
| 188 | static void __init ts78xx_print_board_id(void) | 275 | static void ts78xx_fpga_devices_zero_init(void) |
| 189 | { | 276 | { |
| 190 | unsigned int board_info; | 277 | ts78xx_fpga.supports.ts_rtc.init = 0; |
| 191 | 278 | ts78xx_fpga.supports.ts_nand.init = 0; | |
| 192 | board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID); | 279 | } |
| 193 | printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ", | 280 | |
| 194 | board_info & 0xff, | 281 | static void ts78xx_fpga_supports(void) |
| 195 | (board_info >> 8) & 0xffffff); | 282 | { |
| 196 | board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI); | 283 | /* TODO: put this 'table' into ts78xx-fpga.h */ |
| 197 | printk("JP1=%d, JP2=%d\n", | 284 | switch (ts78xx_fpga.id) { |
| 198 | (board_info >> 30) & 0x1, | 285 | case TS7800_REV_1: |
| 199 | (board_info >> 31) & 0x1); | 286 | case TS7800_REV_2: |
| 287 | case TS7800_REV_3: | ||
| 288 | case TS7800_REV_4: | ||
| 289 | case TS7800_REV_5: | ||
| 290 | ts78xx_fpga.supports.ts_rtc.present = 1; | ||
| 291 | ts78xx_fpga.supports.ts_nand.present = 1; | ||
| 292 | break; | ||
| 293 | default: | ||
| 294 | ts78xx_fpga.supports.ts_rtc.present = 0; | ||
| 295 | ts78xx_fpga.supports.ts_nand.present = 0; | ||
| 296 | } | ||
| 297 | } | ||
| 298 | |||
| 299 | static int ts78xx_fpga_load_devices(void) | ||
| 300 | { | ||
| 301 | int tmp, ret = 0; | ||
| 302 | |||
| 303 | if (ts78xx_fpga.supports.ts_rtc.present == 1) { | ||
| 304 | tmp = ts78xx_ts_rtc_load(); | ||
| 305 | if (tmp) { | ||
| 306 | printk(KERN_INFO "TS-78xx: RTC not registered\n"); | ||
| 307 | ts78xx_fpga.supports.ts_rtc.present = 0; | ||
| 308 | } | ||
| 309 | ret |= tmp; | ||
| 310 | } | ||
| 311 | if (ts78xx_fpga.supports.ts_nand.present == 1) { | ||
| 312 | tmp = ts78xx_ts_nand_load(); | ||
| 313 | if (tmp) { | ||
| 314 | printk(KERN_INFO "TS-78xx: NAND not registered\n"); | ||
| 315 | ts78xx_fpga.supports.ts_nand.present = 0; | ||
| 316 | } | ||
| 317 | ret |= tmp; | ||
| 318 | } | ||
| 319 | |||
| 320 | return ret; | ||
| 321 | } | ||
| 322 | |||
| 323 | static int ts78xx_fpga_unload_devices(void) | ||
| 324 | { | ||
| 325 | int ret = 0; | ||
| 326 | |||
| 327 | if (ts78xx_fpga.supports.ts_rtc.present == 1) | ||
| 328 | ts78xx_ts_rtc_unload(); | ||
| 329 | if (ts78xx_fpga.supports.ts_nand.present == 1) | ||
| 330 | ts78xx_ts_nand_unload(); | ||
| 331 | |||
| 332 | return ret; | ||
| 333 | } | ||
| 334 | |||
| 335 | static int ts78xx_fpga_load(void) | ||
| 336 | { | ||
| 337 | ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); | ||
| 338 | |||
| 339 | printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", | ||
| 340 | (ts78xx_fpga.id >> 8) & 0xffffff, | ||
| 341 | ts78xx_fpga.id & 0xff); | ||
| 342 | |||
| 343 | ts78xx_fpga_supports(); | ||
| 344 | |||
| 345 | if (ts78xx_fpga_load_devices()) { | ||
| 346 | ts78xx_fpga.state = -1; | ||
| 347 | return -EBUSY; | ||
| 348 | } | ||
| 349 | |||
| 350 | return 0; | ||
| 200 | }; | 351 | }; |
| 201 | 352 | ||
| 353 | static int ts78xx_fpga_unload(void) | ||
| 354 | { | ||
| 355 | unsigned int fpga_id; | ||
| 356 | |||
| 357 | fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE); | ||
| 358 | |||
| 359 | /* | ||
| 360 | * There does not seem to be a feasible way to block access to the GPIO | ||
| 361 | * pins from userspace (/dev/mem). This if clause should hopefully warn | ||
| 362 | * those foolish enough not to follow 'policy' :) | ||
| 363 | * | ||
| 364 | * UrJTAG SVN since r1381 can be used to reprogram the FPGA | ||
| 365 | */ | ||
| 366 | if (ts78xx_fpga.id != fpga_id) { | ||
| 367 | printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n" | ||
| 368 | "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", | ||
| 369 | (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, | ||
| 370 | (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); | ||
| 371 | ts78xx_fpga.state = -1; | ||
| 372 | return -EBUSY; | ||
| 373 | } | ||
| 374 | |||
| 375 | if (ts78xx_fpga_unload_devices()) { | ||
| 376 | ts78xx_fpga.state = -1; | ||
| 377 | return -EBUSY; | ||
| 378 | } | ||
| 379 | |||
| 380 | return 0; | ||
| 381 | }; | ||
| 382 | |||
| 383 | static ssize_t ts78xx_fpga_show(struct kobject *kobj, | ||
| 384 | struct kobj_attribute *attr, char *buf) | ||
| 385 | { | ||
| 386 | if (ts78xx_fpga.state < 0) | ||
| 387 | return sprintf(buf, "borked\n"); | ||
| 388 | |||
| 389 | return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline"); | ||
| 390 | } | ||
| 391 | |||
| 392 | static ssize_t ts78xx_fpga_store(struct kobject *kobj, | ||
| 393 | struct kobj_attribute *attr, const char *buf, size_t n) | ||
| 394 | { | ||
| 395 | int value, ret; | ||
| 396 | |||
| 397 | if (ts78xx_fpga.state < 0) { | ||
| 398 | printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n"); | ||
| 399 | return -EBUSY; | ||
| 400 | } | ||
| 401 | |||
| 402 | if (strncmp(buf, "online", sizeof("online") - 1) == 0) | ||
| 403 | value = 1; | ||
| 404 | else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) | ||
| 405 | value = 0; | ||
| 406 | else { | ||
| 407 | printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n"); | ||
| 408 | return -EINVAL; | ||
| 409 | } | ||
| 410 | |||
| 411 | if (ts78xx_fpga.state == value) | ||
| 412 | return n; | ||
| 413 | |||
| 414 | ret = (ts78xx_fpga.state == 0) | ||
| 415 | ? ts78xx_fpga_load() | ||
| 416 | : ts78xx_fpga_unload(); | ||
| 417 | |||
| 418 | if (!(ret < 0)) | ||
| 419 | ts78xx_fpga.state = value; | ||
| 420 | |||
| 421 | return n; | ||
| 422 | } | ||
| 423 | |||
| 424 | static struct kobj_attribute ts78xx_fpga_attr = | ||
| 425 | __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store); | ||
| 426 | |||
| 202 | /***************************************************************************** | 427 | /***************************************************************************** |
| 203 | * General Setup | 428 | * General Setup |
| 204 | ****************************************************************************/ | 429 | ****************************************************************************/ |
| @@ -223,30 +448,29 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { | |||
| 223 | { 17, MPP_UART }, | 448 | { 17, MPP_UART }, |
| 224 | { 18, MPP_UART }, | 449 | { 18, MPP_UART }, |
| 225 | { 19, MPP_UART }, | 450 | { 19, MPP_UART }, |
| 451 | /* | ||
| 452 | * MPP[20] PCI Clock Out 1 | ||
| 453 | * MPP[21] PCI Clock Out 0 | ||
| 454 | * MPP[22] Unused | ||
| 455 | * MPP[23] Unused | ||
| 456 | * MPP[24] Unused | ||
| 457 | * MPP[25] Unused | ||
| 458 | */ | ||
| 226 | { -1 }, | 459 | { -1 }, |
| 227 | }; | 460 | }; |
| 228 | 461 | ||
| 229 | static void __init ts78xx_init(void) | 462 | static void __init ts78xx_init(void) |
| 230 | { | 463 | { |
| 464 | int ret; | ||
| 465 | |||
| 231 | /* | 466 | /* |
| 232 | * Setup basic Orion functions. Need to be called early. | 467 | * Setup basic Orion functions. Need to be called early. |
| 233 | */ | 468 | */ |
| 234 | orion5x_init(); | 469 | orion5x_init(); |
| 235 | 470 | ||
| 236 | ts78xx_print_board_id(); | ||
| 237 | |||
| 238 | orion5x_mpp_conf(ts78xx_mpp_modes); | 471 | orion5x_mpp_conf(ts78xx_mpp_modes); |
| 239 | 472 | ||
| 240 | /* | 473 | /* |
| 241 | * MPP[20] PCI Clock Out 1 | ||
| 242 | * MPP[21] PCI Clock Out 0 | ||
| 243 | * MPP[22] Unused | ||
| 244 | * MPP[23] Unused | ||
| 245 | * MPP[24] Unused | ||
| 246 | * MPP[25] Unused | ||
| 247 | */ | ||
| 248 | |||
| 249 | /* | ||
| 250 | * Configure peripherals. | 474 | * Configure peripherals. |
| 251 | */ | 475 | */ |
| 252 | orion5x_ehci0_init(); | 476 | orion5x_ehci0_init(); |
| @@ -257,12 +481,12 @@ static void __init ts78xx_init(void) | |||
| 257 | orion5x_uart1_init(); | 481 | orion5x_uart1_init(); |
| 258 | orion5x_xor_init(); | 482 | orion5x_xor_init(); |
| 259 | 483 | ||
| 260 | orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE, | 484 | /* FPGA init */ |
| 261 | TS78XX_NOR_BOOT_SIZE); | 485 | ts78xx_fpga_devices_zero_init(); |
| 262 | platform_device_register(&ts78xx_nor_boot_flash); | 486 | ret = ts78xx_fpga_load(); |
| 263 | 487 | ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); | |
| 264 | if (!ts78xx_rtc_init()) | 488 | if (ret) |
| 265 | printk(KERN_INFO "TS-78xx RTC not detected or enabled\n"); | 489 | printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); |
| 266 | } | 490 | } |
| 267 | 491 | ||
| 268 | MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") | 492 | MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") |
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h index e12e7abfcbcf..5dda2bb55f8d 100644 --- a/arch/arm/mach-pnx4008/include/mach/system.h +++ b/arch/arm/mach-pnx4008/include/mach/system.h | |||
| @@ -30,7 +30,7 @@ static void arch_idle(void) | |||
| 30 | cpu_do_idle(); | 30 | cpu_do_idle(); |
| 31 | } | 31 | } |
| 32 | 32 | ||
| 33 | static inline void arch_reset(char mode) | 33 | static inline void arch_reset(char mode, const char *cmd) |
| 34 | { | 34 | { |
| 35 | cpu_reset(0); | 35 | cpu_reset(0); |
| 36 | } | 36 | } |
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 8eea7306f29b..96a2006cb597 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -40,6 +40,9 @@ choice | |||
| 40 | config GUMSTIX_AM200EPD | 40 | config GUMSTIX_AM200EPD |
| 41 | bool "Enable AM200EPD board support" | 41 | bool "Enable AM200EPD board support" |
| 42 | 42 | ||
| 43 | config GUMSTIX_AM300EPD | ||
| 44 | bool "Enable AM300EPD board support" | ||
| 45 | |||
| 43 | endchoice | 46 | endchoice |
| 44 | 47 | ||
| 45 | config MACH_INTELMOTE2 | 48 | config MACH_INTELMOTE2 |
| @@ -254,10 +257,24 @@ config MACH_EM_X270 | |||
| 254 | bool "CompuLab EM-x270 platform" | 257 | bool "CompuLab EM-x270 platform" |
| 255 | select PXA27x | 258 | select PXA27x |
| 256 | 259 | ||
| 260 | config MACH_EXEDA | ||
| 261 | bool "CompuLab eXeda platform" | ||
| 262 | select PXA27x | ||
| 263 | |||
| 257 | config MACH_COLIBRI | 264 | config MACH_COLIBRI |
| 258 | bool "Toradex Colibri PX27x" | 265 | bool "Toradex Colibri PXA270" |
| 259 | select PXA27x | 266 | select PXA27x |
| 260 | 267 | ||
| 268 | config MACH_COLIBRI300 | ||
| 269 | bool "Toradex Colibri PXA300/310" | ||
| 270 | select PXA3xx | ||
| 271 | select CPU_PXA300 | ||
| 272 | |||
| 273 | config MACH_COLIBRI320 | ||
| 274 | bool "Toradex Colibri PXA320" | ||
| 275 | select PXA3xx | ||
| 276 | select CPU_PXA320 | ||
| 277 | |||
| 261 | config MACH_ZYLONITE | 278 | config MACH_ZYLONITE |
| 262 | bool "PXA3xx Development Platform (aka Zylonite)" | 279 | bool "PXA3xx Development Platform (aka Zylonite)" |
| 263 | select PXA3xx | 280 | select PXA3xx |
| @@ -295,8 +312,15 @@ config MACH_MAGICIAN | |||
| 295 | bool "Enable HTC Magician Support" | 312 | bool "Enable HTC Magician Support" |
| 296 | select PXA27x | 313 | select PXA27x |
| 297 | select IWMMXT | 314 | select IWMMXT |
| 315 | select PXA_SSP | ||
| 316 | select HAVE_PWM | ||
| 298 | select PXA_HAVE_BOARD_IRQS | 317 | select PXA_HAVE_BOARD_IRQS |
| 299 | 318 | ||
| 319 | config MACH_HIMALAYA | ||
| 320 | bool "HTC Himalaya Support" | ||
| 321 | select CPU_PXA26x | ||
| 322 | select FB_W100 | ||
| 323 | |||
| 300 | config MACH_MIOA701 | 324 | config MACH_MIOA701 |
| 301 | bool "Mitac Mio A701 Support" | 325 | bool "Mitac Mio A701 Support" |
| 302 | select PXA27x | 326 | select PXA27x |
| @@ -319,6 +343,16 @@ config ARCH_PXA_PALM | |||
| 319 | bool "PXA based Palm PDAs" | 343 | bool "PXA based Palm PDAs" |
| 320 | select HAVE_PWM | 344 | select HAVE_PWM |
| 321 | 345 | ||
| 346 | config MACH_PALMT5 | ||
| 347 | bool "Palm Tungsten|T5" | ||
| 348 | default y | ||
| 349 | depends on ARCH_PXA_PALM | ||
| 350 | select PXA27x | ||
| 351 | select IWMMXT | ||
| 352 | help | ||
| 353 | Say Y here if you intend to run this kernel on a Palm Tungsten|T5 | ||
| 354 | handheld computer. | ||
| 355 | |||
| 322 | config MACH_PALMTX | 356 | config MACH_PALMTX |
| 323 | bool "Palm T|X" | 357 | bool "Palm T|X" |
| 324 | default y | 358 | default y |
| @@ -339,6 +373,16 @@ config MACH_PALMZ72 | |||
| 339 | Say Y here if you intend to run this kernel on Palm Zire 72 | 373 | Say Y here if you intend to run this kernel on Palm Zire 72 |
| 340 | handheld computer. | 374 | handheld computer. |
| 341 | 375 | ||
| 376 | config MACH_PALMLD | ||
| 377 | bool "Palm LifeDrive" | ||
| 378 | default y | ||
| 379 | depends on ARCH_PXA_PALM | ||
| 380 | select PXA27x | ||
| 381 | select IWMMXT | ||
| 382 | help | ||
| 383 | Say Y here if you intend to run this kernel on a Palm LifeDrive | ||
| 384 | handheld computer. | ||
| 385 | |||
| 342 | config MACH_PCM990_BASEBOARD | 386 | config MACH_PCM990_BASEBOARD |
| 343 | bool "PHYTEC PCM-990 development board" | 387 | bool "PHYTEC PCM-990 development board" |
| 344 | select HAVE_PWM | 388 | select HAVE_PWM |
| @@ -359,6 +403,18 @@ config PCM990_DISPLAY_NONE | |||
| 359 | 403 | ||
| 360 | endchoice | 404 | endchoice |
| 361 | 405 | ||
| 406 | config MACH_CSB726 | ||
| 407 | bool "Enable Cogent CSB726 System On a Module" | ||
| 408 | select PXA27x | ||
| 409 | select IWMMXT | ||
| 410 | help | ||
| 411 | Say Y here if you intend to run this kernel on a Cogent | ||
| 412 | CSB726 System On Module. | ||
| 413 | |||
| 414 | config CSB726_CSB701 | ||
| 415 | bool "Enable supprot for CSB701 baseboard" | ||
| 416 | depends on MACH_CSB726 | ||
| 417 | |||
| 362 | config PXA_EZX | 418 | config PXA_EZX |
| 363 | bool "Motorola EZX Platform" | 419 | bool "Motorola EZX Platform" |
| 364 | select PXA27x | 420 | select PXA27x |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 7b28bb561d63..c80e1bac4945 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -3,8 +3,8 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support (must be linked before board specific support) | 5 | # Common support (must be linked before board specific support) |
| 6 | obj-y += clock.o devices.o generic.o irq.o dma.o \ | 6 | obj-y += clock.o devices.o generic.o irq.o \ |
| 7 | time.o gpio.o reset.o | 7 | time.o reset.o |
| 8 | obj-$(CONFIG_PM) += pm.o sleep.o standby.o | 8 | obj-$(CONFIG_PM) += pm.o sleep.o standby.o |
| 9 | 9 | ||
| 10 | ifeq ($(CONFIG_CPU_FREQ),y) | 10 | ifeq ($(CONFIG_CPU_FREQ),y) |
| @@ -28,13 +28,16 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o | |||
| 28 | # Specific board support | 28 | # Specific board support |
| 29 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o | 29 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o |
| 30 | obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o | 30 | obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o |
| 31 | obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o | ||
| 31 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 32 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
| 32 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | 33 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o |
| 33 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 34 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
| 34 | obj-$(CONFIG_MACH_MP900C) += mp900.o | 35 | obj-$(CONFIG_MACH_MP900C) += mp900.o |
| 35 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o | 36 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o |
| 36 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o | 37 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o |
| 37 | obj-$(CONFIG_MACH_COLIBRI) += colibri.o | 38 | obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o |
| 39 | obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o | ||
| 40 | obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o | ||
| 38 | obj-$(CONFIG_MACH_H5000) += h5000.o | 41 | obj-$(CONFIG_MACH_H5000) += h5000.o |
| 39 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o | 42 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o |
| 40 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o | 43 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o |
| @@ -45,6 +48,7 @@ obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o | |||
| 45 | obj-$(CONFIG_MACH_TOSA) += tosa.o | 48 | obj-$(CONFIG_MACH_TOSA) += tosa.o |
| 46 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o | 49 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o |
| 47 | obj-$(CONFIG_MACH_MAGICIAN) += magician.o | 50 | obj-$(CONFIG_MACH_MAGICIAN) += magician.o |
| 51 | obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o | ||
| 48 | obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o | 52 | obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o |
| 49 | obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o | 53 | obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o |
| 50 | obj-$(CONFIG_MACH_E330) += e330.o | 54 | obj-$(CONFIG_MACH_E330) += e330.o |
| @@ -53,7 +57,9 @@ obj-$(CONFIG_MACH_E740) += e740.o | |||
| 53 | obj-$(CONFIG_MACH_E750) += e750.o | 57 | obj-$(CONFIG_MACH_E750) += e750.o |
| 54 | obj-$(CONFIG_MACH_E400) += e400.o | 58 | obj-$(CONFIG_MACH_E400) += e400.o |
| 55 | obj-$(CONFIG_MACH_E800) += e800.o | 59 | obj-$(CONFIG_MACH_E800) += e800.o |
| 60 | obj-$(CONFIG_MACH_PALMT5) += palmt5.o | ||
| 56 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o | 61 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o |
| 62 | obj-$(CONFIG_MACH_PALMLD) += palmld.o | ||
| 57 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o | 63 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o |
| 58 | obj-$(CONFIG_ARCH_VIPER) += viper.o | 64 | obj-$(CONFIG_ARCH_VIPER) += viper.o |
| 59 | 65 | ||
| @@ -71,6 +77,8 @@ obj-$(CONFIG_MACH_CM_X300) += cm-x300.o | |||
| 71 | obj-$(CONFIG_PXA_EZX) += ezx.o | 77 | obj-$(CONFIG_PXA_EZX) += ezx.o |
| 72 | 78 | ||
| 73 | obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o | 79 | obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o |
| 80 | obj-$(CONFIG_MACH_CSB726) += csb726.o | ||
| 81 | obj-$(CONFIG_CSB726_CSB701) += csb701.o | ||
| 74 | 82 | ||
| 75 | # Support for blinky lights | 83 | # Support for blinky lights |
| 76 | led-y := leds.o | 84 | led-y := leds.o |
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 77ee80e5e47b..3499fada73ae 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c | |||
| @@ -30,8 +30,8 @@ | |||
| 30 | #include <linux/irq.h> | 30 | #include <linux/irq.h> |
| 31 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
| 32 | 32 | ||
| 33 | #include <mach/pxa25x.h> | ||
| 33 | #include <mach/gumstix.h> | 34 | #include <mach/gumstix.h> |
| 34 | #include <mach/mfp-pxa25x.h> | ||
| 35 | #include <mach/pxafb.h> | 35 | #include <mach/pxafb.h> |
| 36 | 36 | ||
| 37 | #include "generic.h" | 37 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c new file mode 100644 index 000000000000..4bd10a17332e --- /dev/null +++ b/arch/arm/mach-pxa/am300epd.c | |||
| @@ -0,0 +1,295 @@ | |||
| 1 | /* | ||
| 2 | * am300epd.c -- Platform device for AM300 EPD kit | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008, Jaya Kumar | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | * | ||
| 10 | * This work was made possible by help and equipment support from E-Ink | ||
| 11 | * Corporation. http://support.eink.com/community | ||
| 12 | * | ||
| 13 | * This driver is written to be used with the Broadsheet display controller. | ||
| 14 | * on the AM300 EPD prototype kit/development kit with an E-Ink 800x600 | ||
| 15 | * Vizplex EPD on a Gumstix board using the Broadsheet interface board. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/string.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/interrupt.h> | ||
| 25 | #include <linux/fb.h> | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/platform_device.h> | ||
| 28 | #include <linux/irq.h> | ||
| 29 | #include <linux/gpio.h> | ||
| 30 | |||
| 31 | #include <mach/gumstix.h> | ||
| 32 | #include <mach/mfp-pxa25x.h> | ||
| 33 | #include <mach/pxafb.h> | ||
| 34 | |||
| 35 | #include "generic.h" | ||
| 36 | |||
| 37 | #include <video/broadsheetfb.h> | ||
| 38 | |||
| 39 | static unsigned int panel_type = 6; | ||
| 40 | static struct platform_device *am300_device; | ||
| 41 | static struct broadsheet_board am300_board; | ||
| 42 | |||
| 43 | static unsigned long am300_pin_config[] __initdata = { | ||
| 44 | GPIO16_GPIO, | ||
| 45 | GPIO17_GPIO, | ||
| 46 | GPIO32_GPIO, | ||
| 47 | GPIO48_GPIO, | ||
| 48 | GPIO49_GPIO, | ||
| 49 | GPIO51_GPIO, | ||
| 50 | GPIO74_GPIO, | ||
| 51 | GPIO75_GPIO, | ||
| 52 | GPIO76_GPIO, | ||
| 53 | GPIO77_GPIO, | ||
| 54 | |||
| 55 | /* this is the 16-bit hdb bus 58-73 */ | ||
| 56 | GPIO58_GPIO, | ||
| 57 | GPIO59_GPIO, | ||
| 58 | GPIO60_GPIO, | ||
| 59 | GPIO61_GPIO, | ||
| 60 | |||
| 61 | GPIO62_GPIO, | ||
| 62 | GPIO63_GPIO, | ||
| 63 | GPIO64_GPIO, | ||
| 64 | GPIO65_GPIO, | ||
| 65 | |||
| 66 | GPIO66_GPIO, | ||
| 67 | GPIO67_GPIO, | ||
| 68 | GPIO68_GPIO, | ||
| 69 | GPIO69_GPIO, | ||
| 70 | |||
| 71 | GPIO70_GPIO, | ||
| 72 | GPIO71_GPIO, | ||
| 73 | GPIO72_GPIO, | ||
| 74 | GPIO73_GPIO, | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* register offsets for gpio control */ | ||
| 78 | #define PWR_GPIO_PIN 16 | ||
| 79 | #define CFG_GPIO_PIN 17 | ||
| 80 | #define RDY_GPIO_PIN 32 | ||
| 81 | #define DC_GPIO_PIN 48 | ||
| 82 | #define RST_GPIO_PIN 49 | ||
| 83 | #define LED_GPIO_PIN 51 | ||
| 84 | #define RD_GPIO_PIN 74 | ||
| 85 | #define WR_GPIO_PIN 75 | ||
| 86 | #define CS_GPIO_PIN 76 | ||
| 87 | #define IRQ_GPIO_PIN 77 | ||
| 88 | |||
| 89 | /* hdb bus */ | ||
| 90 | #define DB0_GPIO_PIN 58 | ||
| 91 | #define DB15_GPIO_PIN 73 | ||
| 92 | |||
| 93 | static int gpios[] = { PWR_GPIO_PIN, CFG_GPIO_PIN, RDY_GPIO_PIN, DC_GPIO_PIN, | ||
| 94 | RST_GPIO_PIN, RD_GPIO_PIN, WR_GPIO_PIN, CS_GPIO_PIN, | ||
| 95 | IRQ_GPIO_PIN, LED_GPIO_PIN }; | ||
| 96 | static char *gpio_names[] = { "PWR", "CFG", "RDY", "DC", "RST", "RD", "WR", | ||
| 97 | "CS", "IRQ", "LED" }; | ||
| 98 | |||
| 99 | static int am300_wait_event(struct broadsheetfb_par *par) | ||
| 100 | { | ||
| 101 | /* todo: improve err recovery */ | ||
| 102 | wait_event(par->waitq, gpio_get_value(RDY_GPIO_PIN)); | ||
| 103 | return 0; | ||
| 104 | } | ||
| 105 | |||
| 106 | static int am300_init_gpio_regs(struct broadsheetfb_par *par) | ||
| 107 | { | ||
| 108 | int i; | ||
| 109 | int err; | ||
| 110 | char dbname[8]; | ||
| 111 | |||
| 112 | for (i = 0; i < ARRAY_SIZE(gpios); i++) { | ||
| 113 | err = gpio_request(gpios[i], gpio_names[i]); | ||
| 114 | if (err) { | ||
| 115 | dev_err(&am300_device->dev, "failed requesting " | ||
| 116 | "gpio %s, err=%d\n", gpio_names[i], err); | ||
| 117 | goto err_req_gpio; | ||
| 118 | } | ||
| 119 | } | ||
| 120 | |||
| 121 | /* we also need to take care of the hdb bus */ | ||
| 122 | for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) { | ||
| 123 | sprintf(dbname, "DB%d", i); | ||
| 124 | err = gpio_request(i, dbname); | ||
| 125 | if (err) { | ||
| 126 | dev_err(&am300_device->dev, "failed requesting " | ||
| 127 | "gpio %d, err=%d\n", i, err); | ||
| 128 | while (i >= DB0_GPIO_PIN) | ||
| 129 | gpio_free(i--); | ||
| 130 | i = ARRAY_SIZE(gpios) - 1; | ||
| 131 | goto err_req_gpio; | ||
| 132 | } | ||
| 133 | } | ||
| 134 | |||
| 135 | /* setup the outputs and init values */ | ||
| 136 | gpio_direction_output(PWR_GPIO_PIN, 0); | ||
| 137 | gpio_direction_output(CFG_GPIO_PIN, 1); | ||
| 138 | gpio_direction_output(DC_GPIO_PIN, 0); | ||
| 139 | gpio_direction_output(RD_GPIO_PIN, 1); | ||
| 140 | gpio_direction_output(WR_GPIO_PIN, 1); | ||
| 141 | gpio_direction_output(CS_GPIO_PIN, 1); | ||
| 142 | gpio_direction_output(RST_GPIO_PIN, 0); | ||
| 143 | |||
| 144 | /* setup the inputs */ | ||
| 145 | gpio_direction_input(RDY_GPIO_PIN); | ||
| 146 | gpio_direction_input(IRQ_GPIO_PIN); | ||
| 147 | |||
| 148 | /* start the hdb bus as an input */ | ||
| 149 | for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) | ||
| 150 | gpio_direction_output(i, 0); | ||
| 151 | |||
| 152 | /* go into command mode */ | ||
| 153 | gpio_set_value(CFG_GPIO_PIN, 1); | ||
| 154 | gpio_set_value(RST_GPIO_PIN, 0); | ||
| 155 | msleep(10); | ||
| 156 | gpio_set_value(RST_GPIO_PIN, 1); | ||
| 157 | msleep(10); | ||
| 158 | am300_wait_event(par); | ||
| 159 | |||
| 160 | return 0; | ||
| 161 | |||
| 162 | err_req_gpio: | ||
| 163 | while (i > 0) | ||
| 164 | gpio_free(gpios[i--]); | ||
| 165 | |||
| 166 | return err; | ||
| 167 | } | ||
| 168 | |||
| 169 | static int am300_init_board(struct broadsheetfb_par *par) | ||
| 170 | { | ||
| 171 | return am300_init_gpio_regs(par); | ||
| 172 | } | ||
| 173 | |||
| 174 | static void am300_cleanup(struct broadsheetfb_par *par) | ||
| 175 | { | ||
| 176 | int i; | ||
| 177 | |||
| 178 | free_irq(IRQ_GPIO(RDY_GPIO_PIN), par); | ||
| 179 | |||
| 180 | for (i = 0; i < ARRAY_SIZE(gpios); i++) | ||
| 181 | gpio_free(gpios[i]); | ||
| 182 | |||
| 183 | for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) | ||
| 184 | gpio_free(i); | ||
| 185 | |||
| 186 | } | ||
| 187 | |||
| 188 | static u16 am300_get_hdb(struct broadsheetfb_par *par) | ||
| 189 | { | ||
| 190 | u16 res = 0; | ||
| 191 | int i; | ||
| 192 | |||
| 193 | for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++) | ||
| 194 | res |= (gpio_get_value(DB0_GPIO_PIN + i)) ? (1 << i) : 0; | ||
| 195 | |||
| 196 | return res; | ||
| 197 | } | ||
| 198 | |||
| 199 | static void am300_set_hdb(struct broadsheetfb_par *par, u16 data) | ||
| 200 | { | ||
| 201 | int i; | ||
| 202 | |||
| 203 | for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++) | ||
| 204 | gpio_set_value(DB0_GPIO_PIN + i, (data >> i) & 0x01); | ||
| 205 | } | ||
| 206 | |||
| 207 | |||
| 208 | static void am300_set_ctl(struct broadsheetfb_par *par, unsigned char bit, | ||
| 209 | u8 state) | ||
| 210 | { | ||
| 211 | switch (bit) { | ||
| 212 | case BS_CS: | ||
| 213 | gpio_set_value(CS_GPIO_PIN, state); | ||
| 214 | break; | ||
| 215 | case BS_DC: | ||
| 216 | gpio_set_value(DC_GPIO_PIN, state); | ||
| 217 | break; | ||
| 218 | case BS_WR: | ||
| 219 | gpio_set_value(WR_GPIO_PIN, state); | ||
| 220 | break; | ||
| 221 | } | ||
| 222 | } | ||
| 223 | |||
| 224 | static int am300_get_panel_type(void) | ||
| 225 | { | ||
| 226 | return panel_type; | ||
| 227 | } | ||
| 228 | |||
| 229 | static irqreturn_t am300_handle_irq(int irq, void *dev_id) | ||
| 230 | { | ||
| 231 | struct broadsheetfb_par *par = dev_id; | ||
| 232 | |||
| 233 | wake_up(&par->waitq); | ||
| 234 | return IRQ_HANDLED; | ||
| 235 | } | ||
| 236 | |||
| 237 | static int am300_setup_irq(struct fb_info *info) | ||
| 238 | { | ||
| 239 | int ret; | ||
| 240 | struct broadsheetfb_par *par = info->par; | ||
| 241 | |||
| 242 | ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am300_handle_irq, | ||
| 243 | IRQF_DISABLED|IRQF_TRIGGER_RISING, | ||
| 244 | "AM300", par); | ||
| 245 | if (ret) | ||
| 246 | dev_err(&am300_device->dev, "request_irq failed: %d\n", ret); | ||
| 247 | |||
| 248 | return ret; | ||
| 249 | } | ||
| 250 | |||
| 251 | static struct broadsheet_board am300_board = { | ||
| 252 | .owner = THIS_MODULE, | ||
| 253 | .init = am300_init_board, | ||
| 254 | .cleanup = am300_cleanup, | ||
| 255 | .set_hdb = am300_set_hdb, | ||
| 256 | .get_hdb = am300_get_hdb, | ||
| 257 | .set_ctl = am300_set_ctl, | ||
| 258 | .wait_for_rdy = am300_wait_event, | ||
| 259 | .get_panel_type = am300_get_panel_type, | ||
| 260 | .setup_irq = am300_setup_irq, | ||
| 261 | }; | ||
| 262 | |||
| 263 | int __init am300_init(void) | ||
| 264 | { | ||
| 265 | int ret; | ||
| 266 | |||
| 267 | pxa2xx_mfp_config(ARRAY_AND_SIZE(am300_pin_config)); | ||
| 268 | |||
| 269 | /* request our platform independent driver */ | ||
| 270 | request_module("broadsheetfb"); | ||
| 271 | |||
| 272 | am300_device = platform_device_alloc("broadsheetfb", -1); | ||
| 273 | if (!am300_device) | ||
| 274 | return -ENOMEM; | ||
| 275 | |||
| 276 | /* the am300_board that will be seen by broadsheetfb is a copy */ | ||
| 277 | platform_device_add_data(am300_device, &am300_board, | ||
| 278 | sizeof(am300_board)); | ||
| 279 | |||
| 280 | ret = platform_device_add(am300_device); | ||
| 281 | |||
| 282 | if (ret) { | ||
| 283 | platform_device_put(am300_device); | ||
| 284 | return ret; | ||
| 285 | } | ||
| 286 | |||
| 287 | return 0; | ||
| 288 | } | ||
| 289 | |||
| 290 | module_param(panel_type, uint, 0); | ||
| 291 | MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97"); | ||
| 292 | |||
| 293 | MODULE_DESCRIPTION("board driver for am300 epd kit"); | ||
| 294 | MODULE_AUTHOR("Jaya Kumar"); | ||
| 295 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 40b774084514..db52d2c4791d 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c | |||
| @@ -87,7 +87,7 @@ void clks_register(struct clk_lookup *clks, size_t num) | |||
| 87 | clkdev_add(&clks[i]); | 87 | clkdev_add(&clks[i]); |
| 88 | } | 88 | } |
| 89 | 89 | ||
| 90 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, | 90 | int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, |
| 91 | struct device *dev) | 91 | struct device *dev) |
| 92 | { | 92 | { |
| 93 | struct clk *r = clk_get(dev, id); | 93 | struct clk *r = clk_get(dev, id); |
| @@ -96,7 +96,7 @@ int clk_add_alias(char *alias, struct device *alias_dev, char *id, | |||
| 96 | if (!r) | 96 | if (!r) |
| 97 | return -ENODEV; | 97 | return -ENODEV; |
| 98 | 98 | ||
| 99 | l = clkdev_alloc(r, alias, alias_dev ? dev_name(alias_dev) : NULL); | 99 | l = clkdev_alloc(r, alias, alias_dev_name); |
| 100 | clk_put(r); | 100 | clk_put(r); |
| 101 | if (!l) | 101 | if (!l) |
| 102 | return -ENODEV; | 102 | return -ENODEV; |
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index 4e9c613c6767..5599bceff738 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h | |||
| @@ -69,6 +69,6 @@ extern void clk_pxa3xx_cken_disable(struct clk *); | |||
| 69 | #endif | 69 | #endif |
| 70 | 70 | ||
| 71 | void clks_register(struct clk_lookup *clks, size_t num); | 71 | void clks_register(struct clk_lookup *clks, size_t num); |
| 72 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, | 72 | int clk_add_alias(const char *alias, const char *alias_name, char *id, |
| 73 | struct device *dev); | 73 | struct device *dev); |
| 74 | 74 | ||
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c index 83a4cdf08176..253fd76142d6 100644 --- a/arch/arm/mach-pxa/cm-x255.c +++ b/arch/arm/mach-pxa/cm-x255.c | |||
| @@ -22,10 +22,8 @@ | |||
| 22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
| 24 | 24 | ||
| 25 | #include <mach/pxa2xx-regs.h> | 25 | #include <mach/pxa25x.h> |
| 26 | #include <mach/mfp-pxa25x.h> | ||
| 27 | #include <mach/pxa2xx_spi.h> | 26 | #include <mach/pxa2xx_spi.h> |
| 28 | #include <mach/bitfield.h> | ||
| 29 | 27 | ||
| 30 | #include "generic.h" | 28 | #include "generic.h" |
| 31 | 29 | ||
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index df83b97f303f..34576ba5f5fd 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #include <linux/rtc-v3020.h> | 17 | #include <linux/rtc-v3020.h> |
| 18 | #include <video/mbxfb.h> | 18 | #include <video/mbxfb.h> |
| 19 | 19 | ||
| 20 | #include <mach/mfp-pxa27x.h> | 20 | #include <mach/pxa27x.h> |
| 21 | #include <mach/ohci.h> | 21 | #include <mach/ohci.h> |
| 22 | #include <mach/mmc.h> | 22 | #include <mach/mmc.h> |
| 23 | 23 | ||
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 3156b25f6e9d..7873fa3d8fa4 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 23 | 23 | ||
| 24 | #include <asm/mach/pci.h> | 24 | #include <asm/mach/pci.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| 27 | 26 | ||
| 28 | #include <asm/hardware/it8152.h> | 27 | #include <asm/hardware/it8152.h> |
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index d99fd9e4d888..117b5435f8d5 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c | |||
| @@ -22,8 +22,6 @@ | |||
| 22 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| 23 | 23 | ||
| 24 | #include <mach/pxa2xx-regs.h> | 24 | #include <mach/pxa2xx-regs.h> |
| 25 | #include <mach/mfp-pxa27x.h> | ||
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | #include <mach/audio.h> | 25 | #include <mach/audio.h> |
| 28 | #include <mach/pxafb.h> | 26 | #include <mach/pxafb.h> |
| 29 | 27 | ||
| @@ -96,7 +94,7 @@ static struct resource cmx270_dm9000_resource[] = { | |||
| 96 | }; | 94 | }; |
| 97 | 95 | ||
| 98 | static struct dm9000_plat_data cmx270_dm9000_platdata = { | 96 | static struct dm9000_plat_data cmx270_dm9000_platdata = { |
| 99 | .flags = DM9000_PLATF_32BITONLY, | 97 | .flags = DM9000_PLATF_32BITONLY | DM9000_PLATF_NO_EEPROM, |
| 100 | }; | 98 | }; |
| 101 | 99 | ||
| 102 | static struct platform_device cmx2xx_dm9000_device = { | 100 | static struct platform_device cmx2xx_dm9000_device = { |
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index ff0c577cd1ac..a9f48b1cb54a 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
| @@ -28,9 +28,7 @@ | |||
| 28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 29 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 30 | 30 | ||
| 31 | #include <mach/mfp-pxa300.h> | 31 | #include <mach/pxa300.h> |
| 32 | |||
| 33 | #include <mach/hardware.h> | ||
| 34 | #include <mach/pxafb.h> | 32 | #include <mach/pxafb.h> |
| 35 | #include <mach/mmc.h> | 33 | #include <mach/mmc.h> |
| 36 | #include <mach/ohci.h> | 34 | #include <mach/ohci.h> |
| @@ -162,7 +160,7 @@ static struct resource dm9000_resources[] = { | |||
| 162 | }; | 160 | }; |
| 163 | 161 | ||
| 164 | static struct dm9000_plat_data cm_x300_dm9000_platdata = { | 162 | static struct dm9000_plat_data cm_x300_dm9000_platdata = { |
| 165 | .flags = DM9000_PLATF_16BITONLY, | 163 | .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM, |
| 166 | }; | 164 | }; |
| 167 | 165 | ||
| 168 | static struct platform_device dm9000_device = { | 166 | static struct platform_device dm9000_device = { |
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri-pxa270.c index e8473624427e..01bcfaae75bc 100644 --- a/arch/arm/mach-pxa/colibri.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/colibri.c | 2 | * linux/arch/arm/mach-pxa/colibri-pxa270.c |
| 3 | * | 3 | * |
| 4 | * Support for Toradex PXA27x based Colibri module | 4 | * Support for Toradex PXA270 based Colibri module |
| 5 | * Daniel Mack <daniel@caiaq.de> | 5 | * Daniel Mack <daniel@caiaq.de> |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/mtd/mtd.h> | 20 | #include <linux/mtd/mtd.h> |
| 21 | #include <linux/mtd/partitions.h> | 21 | #include <linux/mtd/partitions.h> |
| 22 | #include <linux/mtd/physmap.h> | 22 | #include <linux/mtd/physmap.h> |
| 23 | #include <linux/gpio.h> | ||
| 23 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 25 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
| @@ -28,20 +29,23 @@ | |||
| 28 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
| 29 | #include <asm/mach/irq.h> | 30 | #include <asm/mach/irq.h> |
| 30 | #include <asm/mach/flash.h> | 31 | #include <asm/mach/flash.h> |
| 31 | #include <mach/pxa-regs.h> | 32 | |
| 32 | #include <mach/mfp-pxa27x.h> | 33 | #include <mach/pxa27x.h> |
| 33 | #include <mach/colibri.h> | 34 | #include <mach/colibri.h> |
| 34 | 35 | ||
| 35 | #include "generic.h" | 36 | #include "generic.h" |
| 36 | #include "devices.h" | 37 | #include "devices.h" |
| 37 | 38 | ||
| 38 | static unsigned long colibri_pin_config[] __initdata = { | 39 | /* |
| 40 | * GPIO configuration | ||
| 41 | */ | ||
| 42 | static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = { | ||
| 39 | GPIO78_nCS_2, /* Ethernet CS */ | 43 | GPIO78_nCS_2, /* Ethernet CS */ |
| 40 | GPIO114_GPIO, /* Ethernet IRQ */ | 44 | GPIO114_GPIO, /* Ethernet IRQ */ |
| 41 | }; | 45 | }; |
| 42 | 46 | ||
| 43 | /* | 47 | /* |
| 44 | * Flash | 48 | * NOR flash |
| 45 | */ | 49 | */ |
| 46 | static struct mtd_partition colibri_partitions[] = { | 50 | static struct mtd_partition colibri_partitions[] = { |
| 47 | { | 51 | { |
| @@ -70,39 +74,40 @@ static struct physmap_flash_data colibri_flash_data[] = { | |||
| 70 | } | 74 | } |
| 71 | }; | 75 | }; |
| 72 | 76 | ||
| 73 | static struct resource flash_resource = { | 77 | static struct resource colibri_pxa270_flash_resource = { |
| 74 | .start = PXA_CS0_PHYS, | 78 | .start = PXA_CS0_PHYS, |
| 75 | .end = PXA_CS0_PHYS + SZ_32M - 1, | 79 | .end = PXA_CS0_PHYS + SZ_32M - 1, |
| 76 | .flags = IORESOURCE_MEM, | 80 | .flags = IORESOURCE_MEM, |
| 77 | }; | 81 | }; |
| 78 | 82 | ||
| 79 | static struct platform_device flash_device = { | 83 | static struct platform_device colibri_pxa270_flash_device = { |
| 80 | .name = "physmap-flash", | 84 | .name = "physmap-flash", |
| 81 | .id = 0, | 85 | .id = 0, |
| 82 | .dev = { | 86 | .dev = { |
| 83 | .platform_data = colibri_flash_data, | 87 | .platform_data = colibri_flash_data, |
| 84 | }, | 88 | }, |
| 85 | .resource = &flash_resource, | 89 | .resource = &colibri_pxa270_flash_resource, |
| 86 | .num_resources = 1, | 90 | .num_resources = 1, |
| 87 | }; | 91 | }; |
| 88 | 92 | ||
| 89 | /* | 93 | /* |
| 90 | * DM9000 Ethernet | 94 | * DM9000 Ethernet |
| 91 | */ | 95 | */ |
| 96 | #if defined(CONFIG_DM9000) | ||
| 92 | static struct resource dm9000_resources[] = { | 97 | static struct resource dm9000_resources[] = { |
| 93 | [0] = { | 98 | [0] = { |
| 94 | .start = COLIBRI_ETH_PHYS, | 99 | .start = COLIBRI_PXA270_ETH_PHYS, |
| 95 | .end = COLIBRI_ETH_PHYS + 3, | 100 | .end = COLIBRI_PXA270_ETH_PHYS + 3, |
| 96 | .flags = IORESOURCE_MEM, | 101 | .flags = IORESOURCE_MEM, |
| 97 | }, | 102 | }, |
| 98 | [1] = { | 103 | [1] = { |
| 99 | .start = COLIBRI_ETH_PHYS + 4, | 104 | .start = COLIBRI_PXA270_ETH_PHYS + 4, |
| 100 | .end = COLIBRI_ETH_PHYS + 4 + 500, | 105 | .end = COLIBRI_PXA270_ETH_PHYS + 4 + 500, |
| 101 | .flags = IORESOURCE_MEM, | 106 | .flags = IORESOURCE_MEM, |
| 102 | }, | 107 | }, |
| 103 | [2] = { | 108 | [2] = { |
| 104 | .start = COLIBRI_ETH_IRQ, | 109 | .start = COLIBRI_PXA270_ETH_IRQ, |
| 105 | .end = COLIBRI_ETH_IRQ, | 110 | .end = COLIBRI_PXA270_ETH_IRQ, |
| 106 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, | 111 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, |
| 107 | }, | 112 | }, |
| 108 | }; | 113 | }; |
| @@ -113,25 +118,28 @@ static struct platform_device dm9000_device = { | |||
| 113 | .num_resources = ARRAY_SIZE(dm9000_resources), | 118 | .num_resources = ARRAY_SIZE(dm9000_resources), |
| 114 | .resource = dm9000_resources, | 119 | .resource = dm9000_resources, |
| 115 | }; | 120 | }; |
| 121 | #endif /* CONFIG_DM9000 */ | ||
| 116 | 122 | ||
| 117 | static struct platform_device *colibri_devices[] __initdata = { | 123 | static struct platform_device *colibri_pxa270_devices[] __initdata = { |
| 118 | &flash_device, | 124 | &colibri_pxa270_flash_device, |
| 125 | #if defined(CONFIG_DM9000) | ||
| 119 | &dm9000_device, | 126 | &dm9000_device, |
| 127 | #endif | ||
| 120 | }; | 128 | }; |
| 121 | 129 | ||
| 122 | static void __init colibri_init(void) | 130 | static void __init colibri_pxa270_init(void) |
| 123 | { | 131 | { |
| 124 | pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pin_config)); | 132 | pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config)); |
| 125 | 133 | platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices)); | |
| 126 | platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices)); | ||
| 127 | } | 134 | } |
| 128 | 135 | ||
| 129 | MACHINE_START(COLIBRI, "Toradex Colibri PXA27x") | 136 | MACHINE_START(COLIBRI, "Toradex Colibri PXA270") |
| 130 | .phys_io = 0x40000000, | 137 | .phys_io = 0x40000000, |
| 131 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 138 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
| 132 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | 139 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, |
| 133 | .init_machine = colibri_init, | 140 | .init_machine = colibri_pxa270_init, |
| 134 | .map_io = pxa_map_io, | 141 | .map_io = pxa_map_io, |
| 135 | .init_irq = pxa27x_init_irq, | 142 | .init_irq = pxa27x_init_irq, |
| 136 | .timer = &pxa_timer, | 143 | .timer = &pxa_timer, |
| 137 | MACHINE_END | 144 | MACHINE_END |
| 145 | |||
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c new file mode 100644 index 000000000000..10c2eaf93230 --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa300.c | |||
| @@ -0,0 +1,190 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/colibri-pxa300.c | ||
| 3 | * | ||
| 4 | * Support for Toradex PXA300/310 based Colibri module | ||
| 5 | * | ||
| 6 | * Daniel Mack <daniel@caiaq.de> | ||
| 7 | * Matthias Meier <matthias.j.meier@gmx.net> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <net/ax88796.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/sizes.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | #include <asm/mach/irq.h> | ||
| 24 | |||
| 25 | #include <mach/pxa300.h> | ||
| 26 | #include <mach/colibri.h> | ||
| 27 | #include <mach/ohci.h> | ||
| 28 | #include <mach/pxafb.h> | ||
| 29 | |||
| 30 | #include "generic.h" | ||
| 31 | #include "devices.h" | ||
| 32 | |||
| 33 | #if defined(CONFIG_AX88796) | ||
| 34 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO) | ||
| 35 | /* | ||
| 36 | * Asix AX88796 Ethernet | ||
| 37 | */ | ||
| 38 | static struct ax_plat_data colibri_asix_platdata = { | ||
| 39 | .flags = AXFLG_MAC_FROMDEV, | ||
| 40 | .wordlength = 2 | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct resource colibri_asix_resource[] = { | ||
| 44 | [0] = { | ||
| 45 | .start = PXA3xx_CS2_PHYS, | ||
| 46 | .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1, | ||
| 47 | .flags = IORESOURCE_MEM, | ||
| 48 | }, | ||
| 49 | [1] = { | ||
| 50 | .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 51 | .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 52 | .flags = IORESOURCE_IRQ | ||
| 53 | } | ||
| 54 | }; | ||
| 55 | |||
| 56 | static struct platform_device asix_device = { | ||
| 57 | .name = "ax88796", | ||
| 58 | .id = 0, | ||
| 59 | .num_resources = ARRAY_SIZE(colibri_asix_resource), | ||
| 60 | .resource = colibri_asix_resource, | ||
| 61 | .dev = { | ||
| 62 | .platform_data = &colibri_asix_platdata | ||
| 63 | } | ||
| 64 | }; | ||
| 65 | |||
| 66 | static mfp_cfg_t colibri_pxa300_eth_pin_config[] __initdata = { | ||
| 67 | GPIO1_nCS2, /* AX88796 chip select */ | ||
| 68 | GPIO26_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */ | ||
| 69 | }; | ||
| 70 | |||
| 71 | static void __init colibri_pxa300_init_eth(void) | ||
| 72 | { | ||
| 73 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_eth_pin_config)); | ||
| 74 | set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
| 75 | platform_device_register(&asix_device); | ||
| 76 | } | ||
| 77 | #else | ||
| 78 | static inline void __init colibri_pxa300_init_eth(void) {} | ||
| 79 | #endif /* CONFIG_AX88796 */ | ||
| 80 | |||
| 81 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 82 | static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = { | ||
| 83 | GPIO0_2_USBH_PEN, | ||
| 84 | GPIO1_2_USBH_PWR, | ||
| 85 | }; | ||
| 86 | |||
| 87 | static struct pxaohci_platform_data colibri_pxa300_ohci_info = { | ||
| 88 | .port_mode = PMM_GLOBAL_MODE, | ||
| 89 | .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, | ||
| 90 | }; | ||
| 91 | |||
| 92 | void __init colibri_pxa300_init_ohci(void) | ||
| 93 | { | ||
| 94 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config)); | ||
| 95 | pxa_set_ohci_info(&colibri_pxa300_ohci_info); | ||
| 96 | } | ||
| 97 | #else | ||
| 98 | static inline void colibri_pxa300_init_ohci(void) {} | ||
| 99 | #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ | ||
| 100 | |||
| 101 | static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = { | ||
| 102 | GPIO7_MMC1_CLK, | ||
| 103 | GPIO14_MMC1_CMD, | ||
| 104 | GPIO3_MMC1_DAT0, | ||
| 105 | GPIO4_MMC1_DAT1, | ||
| 106 | GPIO5_MMC1_DAT2, | ||
| 107 | GPIO6_MMC1_DAT3, | ||
| 108 | }; | ||
| 109 | |||
| 110 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 111 | static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = { | ||
| 112 | GPIO54_LCD_LDD_0, | ||
| 113 | GPIO55_LCD_LDD_1, | ||
| 114 | GPIO56_LCD_LDD_2, | ||
| 115 | GPIO57_LCD_LDD_3, | ||
| 116 | GPIO58_LCD_LDD_4, | ||
| 117 | GPIO59_LCD_LDD_5, | ||
| 118 | GPIO60_LCD_LDD_6, | ||
| 119 | GPIO61_LCD_LDD_7, | ||
| 120 | GPIO62_LCD_LDD_8, | ||
| 121 | GPIO63_LCD_LDD_9, | ||
| 122 | GPIO64_LCD_LDD_10, | ||
| 123 | GPIO65_LCD_LDD_11, | ||
| 124 | GPIO66_LCD_LDD_12, | ||
| 125 | GPIO67_LCD_LDD_13, | ||
| 126 | GPIO68_LCD_LDD_14, | ||
| 127 | GPIO69_LCD_LDD_15, | ||
| 128 | GPIO70_LCD_LDD_16, | ||
| 129 | GPIO71_LCD_LDD_17, | ||
| 130 | GPIO62_LCD_CS_N, | ||
| 131 | GPIO72_LCD_FCLK, | ||
| 132 | GPIO73_LCD_LCLK, | ||
| 133 | GPIO74_LCD_PCLK, | ||
| 134 | GPIO75_LCD_BIAS, | ||
| 135 | GPIO76_LCD_VSYNC, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static void __init colibri_pxa300_init_lcd(void) | ||
| 139 | { | ||
| 140 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_lcd_pin_config)); | ||
| 141 | } | ||
| 142 | |||
| 143 | #else | ||
| 144 | static inline void colibri_pxa300_init_lcd(void) {} | ||
| 145 | #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */ | ||
| 146 | |||
| 147 | #if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE) | ||
| 148 | static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = { | ||
| 149 | GPIO24_AC97_SYSCLK, | ||
| 150 | GPIO23_AC97_nACRESET, | ||
| 151 | GPIO25_AC97_SDATA_IN_0, | ||
| 152 | GPIO27_AC97_SDATA_OUT, | ||
| 153 | GPIO28_AC97_SYNC, | ||
| 154 | GPIO29_AC97_BITCLK | ||
| 155 | }; | ||
| 156 | |||
| 157 | static inline void __init colibri_pxa310_init_ac97(void) | ||
| 158 | { | ||
| 159 | /* no AC97 codec on Colibri PXA300 */ | ||
| 160 | if (!cpu_is_pxa310()) | ||
| 161 | return; | ||
| 162 | |||
| 163 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa310_ac97_pin_config)); | ||
| 164 | pxa_set_ac97_info(NULL); | ||
| 165 | } | ||
| 166 | #else | ||
| 167 | static inline void colibri_pxa310_init_ac97(void) {} | ||
| 168 | #endif | ||
| 169 | |||
| 170 | void __init colibri_pxa300_init(void) | ||
| 171 | { | ||
| 172 | colibri_pxa300_init_eth(); | ||
| 173 | colibri_pxa300_init_ohci(); | ||
| 174 | colibri_pxa300_init_lcd(); | ||
| 175 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO)); | ||
| 176 | colibri_pxa310_init_ac97(); | ||
| 177 | colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config), | ||
| 178 | mfp_to_gpio(MFP_PIN_GPIO13)); | ||
| 179 | } | ||
| 180 | |||
| 181 | MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") | ||
| 182 | .phys_io = 0x40000000, | ||
| 183 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 184 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | ||
| 185 | .init_machine = colibri_pxa300_init, | ||
| 186 | .map_io = pxa_map_io, | ||
| 187 | .init_irq = pxa3xx_init_irq, | ||
| 188 | .timer = &pxa_timer, | ||
| 189 | MACHINE_END | ||
| 190 | |||
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c new file mode 100644 index 000000000000..55b74a7a6151 --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa320.c | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/colibri-pxa320.c | ||
| 3 | * | ||
| 4 | * Support for Toradex PXA320/310 based Colibri module | ||
| 5 | * | ||
| 6 | * Daniel Mack <daniel@caiaq.de> | ||
| 7 | * Matthias Meier <matthias.j.meier@gmx.net> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <net/ax88796.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/sizes.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | #include <asm/mach/irq.h> | ||
| 24 | |||
| 25 | #include <mach/pxa3xx-regs.h> | ||
| 26 | #include <mach/mfp-pxa320.h> | ||
| 27 | #include <mach/colibri.h> | ||
| 28 | #include <mach/pxafb.h> | ||
| 29 | #include <mach/ohci.h> | ||
| 30 | |||
| 31 | #include "generic.h" | ||
| 32 | #include "devices.h" | ||
| 33 | |||
| 34 | #if defined(CONFIG_AX88796) | ||
| 35 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO) | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Asix AX88796 Ethernet | ||
| 39 | */ | ||
| 40 | static struct ax_plat_data colibri_asix_platdata = { | ||
| 41 | .flags = AXFLG_MAC_FROMDEV, | ||
| 42 | .wordlength = 2 | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct resource colibri_asix_resource[] = { | ||
| 46 | [0] = { | ||
| 47 | .start = PXA3xx_CS2_PHYS, | ||
| 48 | .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1, | ||
| 49 | .flags = IORESOURCE_MEM, | ||
| 50 | }, | ||
| 51 | [1] = { | ||
| 52 | .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 53 | .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 54 | .flags = IORESOURCE_IRQ | ||
| 55 | } | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct platform_device asix_device = { | ||
| 59 | .name = "ax88796", | ||
| 60 | .id = 0, | ||
| 61 | .num_resources = ARRAY_SIZE(colibri_asix_resource), | ||
| 62 | .resource = colibri_asix_resource, | ||
| 63 | .dev = { | ||
| 64 | .platform_data = &colibri_asix_platdata | ||
| 65 | } | ||
| 66 | }; | ||
| 67 | |||
| 68 | static mfp_cfg_t colibri_pxa320_eth_pin_config[] __initdata = { | ||
| 69 | GPIO3_nCS2, /* AX88796 chip select */ | ||
| 70 | GPIO36_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */ | ||
| 71 | }; | ||
| 72 | |||
| 73 | static void __init colibri_pxa320_init_eth(void) | ||
| 74 | { | ||
| 75 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_eth_pin_config)); | ||
| 76 | set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
| 77 | platform_device_register(&asix_device); | ||
| 78 | } | ||
| 79 | #else | ||
| 80 | static inline void __init colibri_pxa320_init_eth(void) {} | ||
| 81 | #endif /* CONFIG_AX88796 */ | ||
| 82 | |||
| 83 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 84 | static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = { | ||
| 85 | GPIO2_2_USBH_PEN, | ||
| 86 | GPIO3_2_USBH_PWR, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct pxaohci_platform_data colibri_pxa320_ohci_info = { | ||
| 90 | .port_mode = PMM_GLOBAL_MODE, | ||
| 91 | .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, | ||
| 92 | }; | ||
| 93 | |||
| 94 | void __init colibri_pxa320_init_ohci(void) | ||
| 95 | { | ||
| 96 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config)); | ||
| 97 | pxa_set_ohci_info(&colibri_pxa320_ohci_info); | ||
| 98 | } | ||
| 99 | #else | ||
| 100 | static inline void colibri_pxa320_init_ohci(void) {} | ||
| 101 | #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ | ||
| 102 | |||
| 103 | static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = { | ||
| 104 | GPIO22_MMC1_CLK, | ||
| 105 | GPIO23_MMC1_CMD, | ||
| 106 | GPIO18_MMC1_DAT0, | ||
| 107 | GPIO19_MMC1_DAT1, | ||
| 108 | GPIO20_MMC1_DAT2, | ||
| 109 | GPIO21_MMC1_DAT3 | ||
| 110 | }; | ||
| 111 | |||
| 112 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 113 | static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = { | ||
| 114 | GPIO6_2_LCD_LDD_0, | ||
| 115 | GPIO7_2_LCD_LDD_1, | ||
| 116 | GPIO8_2_LCD_LDD_2, | ||
| 117 | GPIO9_2_LCD_LDD_3, | ||
| 118 | GPIO10_2_LCD_LDD_4, | ||
| 119 | GPIO11_2_LCD_LDD_5, | ||
| 120 | GPIO12_2_LCD_LDD_6, | ||
| 121 | GPIO13_2_LCD_LDD_7, | ||
| 122 | GPIO63_LCD_LDD_8, | ||
| 123 | GPIO64_LCD_LDD_9, | ||
| 124 | GPIO65_LCD_LDD_10, | ||
| 125 | GPIO66_LCD_LDD_11, | ||
| 126 | GPIO67_LCD_LDD_12, | ||
| 127 | GPIO68_LCD_LDD_13, | ||
| 128 | GPIO69_LCD_LDD_14, | ||
| 129 | GPIO70_LCD_LDD_15, | ||
| 130 | GPIO71_LCD_LDD_16, | ||
| 131 | GPIO72_LCD_LDD_17, | ||
| 132 | GPIO73_LCD_CS_N, | ||
| 133 | GPIO74_LCD_VSYNC, | ||
| 134 | GPIO14_2_LCD_FCLK, | ||
| 135 | GPIO15_2_LCD_LCLK, | ||
| 136 | GPIO16_2_LCD_PCLK, | ||
| 137 | GPIO17_2_LCD_BIAS, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static void __init colibri_pxa320_init_lcd(void) | ||
| 141 | { | ||
| 142 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_lcd_pin_config)); | ||
| 143 | } | ||
| 144 | #else | ||
| 145 | static inline void colibri_pxa320_init_lcd(void) {} | ||
| 146 | #endif | ||
| 147 | |||
| 148 | #if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE) | ||
| 149 | static mfp_cfg_t colibri_pxa320_ac97_pin_config[] __initdata = { | ||
| 150 | GPIO34_AC97_SYSCLK, | ||
| 151 | GPIO35_AC97_SDATA_IN_0, | ||
| 152 | GPIO37_AC97_SDATA_OUT, | ||
| 153 | GPIO38_AC97_SYNC, | ||
| 154 | GPIO39_AC97_BITCLK, | ||
| 155 | GPIO40_AC97_nACRESET | ||
| 156 | }; | ||
| 157 | |||
| 158 | static inline void __init colibri_pxa320_init_ac97(void) | ||
| 159 | { | ||
| 160 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_ac97_pin_config)); | ||
| 161 | pxa_set_ac97_info(NULL); | ||
| 162 | } | ||
| 163 | #else | ||
| 164 | static inline void colibri_pxa320_init_ac97(void) {} | ||
| 165 | #endif | ||
| 166 | |||
| 167 | void __init colibri_pxa320_init(void) | ||
| 168 | { | ||
| 169 | colibri_pxa320_init_eth(); | ||
| 170 | colibri_pxa320_init_ohci(); | ||
| 171 | colibri_pxa320_init_lcd(); | ||
| 172 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO)); | ||
| 173 | colibri_pxa320_init_ac97(); | ||
| 174 | colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config), | ||
| 175 | mfp_to_gpio(MFP_PIN_GPIO28)); | ||
| 176 | } | ||
| 177 | |||
| 178 | MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") | ||
| 179 | .phys_io = 0x40000000, | ||
| 180 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 181 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | ||
| 182 | .init_machine = colibri_pxa320_init, | ||
| 183 | .map_io = pxa_map_io, | ||
| 184 | .init_irq = pxa3xx_init_irq, | ||
| 185 | .timer = &pxa_timer, | ||
| 186 | MACHINE_END | ||
| 187 | |||
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c new file mode 100644 index 000000000000..12d0afc54aa5 --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c | |||
| @@ -0,0 +1,121 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/colibri-pxa3xx.c | ||
| 3 | * | ||
| 4 | * Common functions for all Toradex PXA3xx modules | ||
| 5 | * | ||
| 6 | * Daniel Mack <daniel@caiaq.de> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/gpio.h> | ||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <mach/hardware.h> | ||
| 19 | #include <asm/sizes.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <asm/mach/irq.h> | ||
| 22 | #include <mach/pxa3xx-regs.h> | ||
| 23 | #include <mach/mfp-pxa300.h> | ||
| 24 | #include <mach/colibri.h> | ||
| 25 | #include <mach/mmc.h> | ||
| 26 | #include <mach/pxafb.h> | ||
| 27 | |||
| 28 | #include "generic.h" | ||
| 29 | #include "devices.h" | ||
| 30 | |||
| 31 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | ||
| 32 | static int mmc_detect_pin; | ||
| 33 | |||
| 34 | static int colibri_pxa3xx_mci_init(struct device *dev, | ||
| 35 | irq_handler_t colibri_mmc_detect_int, | ||
| 36 | void *data) | ||
| 37 | { | ||
| 38 | int ret; | ||
| 39 | |||
| 40 | ret = gpio_request(mmc_detect_pin, "mmc card detect"); | ||
| 41 | if (ret) | ||
| 42 | return ret; | ||
| 43 | |||
| 44 | gpio_direction_input(mmc_detect_pin); | ||
| 45 | ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int, | ||
| 46 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | ||
| 47 | "MMC card detect", data); | ||
| 48 | if (ret) { | ||
| 49 | gpio_free(mmc_detect_pin); | ||
| 50 | return ret; | ||
| 51 | } | ||
| 52 | |||
| 53 | return 0; | ||
| 54 | } | ||
| 55 | |||
| 56 | static void colibri_pxa3xx_mci_exit(struct device *dev, void *data) | ||
| 57 | { | ||
| 58 | free_irq(mmc_detect_pin, data); | ||
| 59 | gpio_free(gpio_to_irq(mmc_detect_pin)); | ||
| 60 | } | ||
| 61 | |||
| 62 | static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = { | ||
| 63 | .detect_delay = 20, | ||
| 64 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 65 | .init = colibri_pxa3xx_mci_init, | ||
| 66 | .exit = colibri_pxa3xx_mci_exit, | ||
| 67 | }; | ||
| 68 | |||
| 69 | void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) | ||
| 70 | { | ||
| 71 | pxa3xx_mfp_config(pins, len); | ||
| 72 | mmc_detect_pin = detect_pin; | ||
| 73 | pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data); | ||
| 74 | } | ||
| 75 | #endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */ | ||
| 76 | |||
| 77 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 78 | static int lcd_bl_pin; | ||
| 79 | |||
| 80 | /* | ||
| 81 | * LCD panel (Sharp LQ043T3DX02) | ||
| 82 | */ | ||
| 83 | static void colibri_lcd_backlight(int on) | ||
| 84 | { | ||
| 85 | gpio_set_value(lcd_bl_pin, !!on); | ||
| 86 | } | ||
| 87 | |||
| 88 | static struct pxafb_mode_info sharp_lq43_mode = { | ||
| 89 | .pixclock = 101936, | ||
| 90 | .xres = 480, | ||
| 91 | .yres = 272, | ||
| 92 | .bpp = 32, | ||
| 93 | .depth = 18, | ||
| 94 | .hsync_len = 41, | ||
| 95 | .left_margin = 2, | ||
| 96 | .right_margin = 2, | ||
| 97 | .vsync_len = 10, | ||
| 98 | .upper_margin = 2, | ||
| 99 | .lower_margin = 2, | ||
| 100 | .sync = 0, | ||
| 101 | .cmap_greyscale = 0, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static struct pxafb_mach_info sharp_lq43_info = { | ||
| 105 | .modes = &sharp_lq43_mode, | ||
| 106 | .num_modes = 1, | ||
| 107 | .cmap_inverse = 0, | ||
| 108 | .cmap_static = 0, | ||
| 109 | .lcd_conn = LCD_COLOR_TFT_18BPP, | ||
| 110 | .pxafb_backlight_power = colibri_lcd_backlight, | ||
| 111 | }; | ||
| 112 | |||
| 113 | void __init colibri_pxa3xx_init_lcd(int bl_pin) | ||
| 114 | { | ||
| 115 | lcd_bl_pin = bl_pin; | ||
| 116 | gpio_request(bl_pin, "lcd backlight"); | ||
| 117 | gpio_direction_output(bl_pin, 0); | ||
| 118 | set_pxa_fb_info(&sharp_lq43_info); | ||
| 119 | } | ||
| 120 | #endif | ||
| 121 | |||
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index a8d91b6c136b..cdf21dd135b4 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
| @@ -41,9 +41,7 @@ | |||
| 41 | #include <asm/mach/map.h> | 41 | #include <asm/mach/map.h> |
| 42 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
| 43 | 43 | ||
| 44 | #include <mach/pxa-regs.h> | 44 | #include <mach/pxa25x.h> |
| 45 | #include <mach/pxa2xx-regs.h> | ||
| 46 | #include <mach/mfp-pxa25x.h> | ||
| 47 | #include <mach/i2c.h> | 45 | #include <mach/i2c.h> |
| 48 | #include <mach/irda.h> | 46 | #include <mach/irda.h> |
| 49 | #include <mach/mmc.h> | 47 | #include <mach/mmc.h> |
| @@ -637,16 +635,16 @@ static void corgi_poweroff(void) | |||
| 637 | /* Green LED off tells the bootloader to halt */ | 635 | /* Green LED off tells the bootloader to halt */ |
| 638 | gpio_set_value(CORGI_GPIO_LED_GREEN, 0); | 636 | gpio_set_value(CORGI_GPIO_LED_GREEN, 0); |
| 639 | 637 | ||
| 640 | arm_machine_restart('h'); | 638 | arm_machine_restart('h', NULL); |
| 641 | } | 639 | } |
| 642 | 640 | ||
| 643 | static void corgi_restart(char mode) | 641 | static void corgi_restart(char mode, const char *cmd) |
| 644 | { | 642 | { |
| 645 | if (!machine_is_corgi()) | 643 | if (!machine_is_corgi()) |
| 646 | /* Green LED on tells the bootloader to reboot */ | 644 | /* Green LED on tells the bootloader to reboot */ |
| 647 | gpio_set_value(CORGI_GPIO_LED_GREEN, 1); | 645 | gpio_set_value(CORGI_GPIO_LED_GREEN, 1); |
| 648 | 646 | ||
| 649 | arm_machine_restart('h'); | 647 | arm_machine_restart('h', cmd); |
| 650 | } | 648 | } |
| 651 | 649 | ||
| 652 | static void __init corgi_init(void) | 650 | static void __init corgi_init(void) |
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index 411607bc1fc2..d9b96319d498 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/string.h> | 22 | #include <linux/string.h> |
| 23 | #include <mach/corgi.h> | 23 | #include <mach/corgi.h> |
| 24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/sharpsl.h> | 25 | #include <mach/sharpsl.h> |
| 27 | #include <mach/spitz.h> | 26 | #include <mach/spitz.h> |
| 28 | #include <asm/hardware/scoop.h> | 27 | #include <asm/hardware/scoop.h> |
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index e35259032813..7f04b3a761d1 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/sharpsl.h> | 25 | #include <mach/sharpsl.h> |
| 26 | #include <mach/corgi.h> | 26 | #include <mach/corgi.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/pxa2xx-regs.h> | 27 | #include <mach/pxa2xx-regs.h> |
| 29 | #include <mach/pxa2xx-gpio.h> | 28 | #include <mach/pxa2xx-gpio.h> |
| 30 | #include "sharpsl.h" | 29 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index 8e2f2215c4ba..a5ee70735e04 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 21 | 21 | ||
| 22 | #include <mach/ssp.h> | 22 | #include <mach/ssp.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/pxa2xx-gpio.h> | 23 | #include <mach/pxa2xx-gpio.h> |
| 25 | #include <mach/regs-ssp.h> | 24 | #include <mach/regs-ssp.h> |
| 26 | #include "sharpsl.h" | 25 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 771dd4eac935..083a1d851d49 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c | |||
| @@ -37,8 +37,6 @@ | |||
| 37 | #include <linux/init.h> | 37 | #include <linux/init.h> |
| 38 | #include <linux/cpufreq.h> | 38 | #include <linux/cpufreq.h> |
| 39 | 39 | ||
| 40 | #include <mach/hardware.h> | ||
| 41 | #include <mach/pxa-regs.h> | ||
| 42 | #include <mach/pxa2xx-regs.h> | 40 | #include <mach/pxa2xx-regs.h> |
| 43 | 41 | ||
| 44 | #ifdef DEBUG | 42 | #ifdef DEBUG |
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c index 968c8309ec37..67f34a8d8e60 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c | |||
| @@ -15,8 +15,6 @@ | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/cpufreq.h> | 16 | #include <linux/cpufreq.h> |
| 17 | 17 | ||
| 18 | #include <mach/hardware.h> | ||
| 19 | #include <mach/pxa-regs.h> | ||
| 20 | #include <mach/pxa3xx-regs.h> | 18 | #include <mach/pxa3xx-regs.h> |
| 21 | 19 | ||
| 22 | #include "generic.h" | 20 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/csb701.c b/arch/arm/mach-pxa/csb701.c new file mode 100644 index 000000000000..4a2a2952c374 --- /dev/null +++ b/arch/arm/mach-pxa/csb701.c | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | #include <linux/kernel.h> | ||
| 2 | #include <linux/module.h> | ||
| 3 | #include <linux/platform_device.h> | ||
| 4 | #include <linux/gpio_keys.h> | ||
| 5 | #include <linux/input.h> | ||
| 6 | #include <linux/leds.h> | ||
| 7 | |||
| 8 | static struct gpio_keys_button csb701_buttons[] = { | ||
| 9 | { | ||
| 10 | .code = 0x7, | ||
| 11 | .gpio = 1, | ||
| 12 | .active_low = 1, | ||
| 13 | .desc = "SW2", | ||
| 14 | .type = EV_SW, | ||
| 15 | .wakeup = 1, | ||
| 16 | }, | ||
| 17 | }; | ||
| 18 | |||
| 19 | static struct gpio_keys_platform_data csb701_gpio_keys_data = { | ||
| 20 | .buttons = csb701_buttons, | ||
| 21 | .nbuttons = ARRAY_SIZE(csb701_buttons), | ||
| 22 | }; | ||
| 23 | |||
| 24 | static struct gpio_led csb701_leds[] = { | ||
| 25 | { | ||
| 26 | .name = "csb701:yellow:heartbeat", | ||
| 27 | .default_trigger = "heartbeat", | ||
| 28 | .gpio = 11, | ||
| 29 | .active_low = 1, | ||
| 30 | }, | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct platform_device csb701_gpio_keys = { | ||
| 34 | .name = "gpio-keys", | ||
| 35 | .id = -1, | ||
| 36 | .dev.platform_data = &csb701_gpio_keys_data, | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct gpio_led_platform_data csb701_leds_gpio_data = { | ||
| 40 | .leds = csb701_leds, | ||
| 41 | .num_leds = ARRAY_SIZE(csb701_leds), | ||
| 42 | }; | ||
| 43 | |||
| 44 | static struct platform_device csb701_leds_gpio = { | ||
| 45 | .name = "leds-gpio", | ||
| 46 | .id = -1, | ||
| 47 | .dev.platform_data = &csb701_leds_gpio_data, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct platform_device *devices[] __initdata = { | ||
| 51 | &csb701_gpio_keys, | ||
| 52 | &csb701_leds_gpio, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static int __init csb701_init(void) | ||
| 56 | { | ||
| 57 | return platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 58 | } | ||
| 59 | |||
| 60 | module_init(csb701_init); | ||
| 61 | |||
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c new file mode 100644 index 000000000000..2b289f83a61a --- /dev/null +++ b/arch/arm/mach-pxa/csb726.c | |||
| @@ -0,0 +1,318 @@ | |||
| 1 | /* | ||
| 2 | * Support for Cogent CSB726 | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Dmitry Eremin-Solenikov | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/gpio.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/partitions.h> | ||
| 18 | #include <linux/sm501.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/mach/arch.h> | ||
| 22 | #include <mach/csb726.h> | ||
| 23 | #include <mach/mfp-pxa27x.h> | ||
| 24 | #include <mach/i2c.h> | ||
| 25 | #include <mach/mmc.h> | ||
| 26 | #include <mach/ohci.h> | ||
| 27 | #include <mach/pxa2xx-regs.h> | ||
| 28 | |||
| 29 | #include "generic.h" | ||
| 30 | #include "devices.h" | ||
| 31 | |||
| 32 | /* | ||
| 33 | * n/a: 2, 5, 6, 7, 8, 23, 24, 25, 26, 27, 87, 88, 89, | ||
| 34 | * nu: 58 -- 77, 90, 91, 93, 102, 105-108, 114-116, | ||
| 35 | * XXX: 21, | ||
| 36 | * XXX: 79 CS_3 for LAN9215 or PSKTSEL on R2, R3 | ||
| 37 | * XXX: 33 CS_5 for LAN9215 on R1 | ||
| 38 | */ | ||
| 39 | |||
| 40 | static unsigned long csb726_pin_config[] = { | ||
| 41 | GPIO78_nCS_2, /* EXP_CS */ | ||
| 42 | GPIO79_nCS_3, /* SMSC9215 */ | ||
| 43 | GPIO80_nCS_4, /* SM501 */ | ||
| 44 | |||
| 45 | GPIO52_GPIO, /* #SMSC9251 int */ | ||
| 46 | GPIO53_GPIO, /* SM501 int */ | ||
| 47 | |||
| 48 | GPIO1_GPIO, /* GPIO0 */ | ||
| 49 | GPIO11_GPIO, /* GPIO1 */ | ||
| 50 | GPIO9_GPIO, /* GPIO2 */ | ||
| 51 | GPIO10_GPIO, /* GPIO3 */ | ||
| 52 | GPIO16_PWM0_OUT, /* or GPIO4 */ | ||
| 53 | GPIO17_PWM1_OUT, /* or GPIO5 */ | ||
| 54 | GPIO94_GPIO, /* GPIO6 */ | ||
| 55 | GPIO95_GPIO, /* GPIO7 */ | ||
| 56 | GPIO96_GPIO, /* GPIO8 */ | ||
| 57 | GPIO97_GPIO, /* GPIO9 */ | ||
| 58 | GPIO15_GPIO, /* EXP_IRQ */ | ||
| 59 | GPIO18_RDY, /* EXP_WAIT */ | ||
| 60 | |||
| 61 | GPIO0_GPIO, /* PWR_INT */ | ||
| 62 | GPIO104_GPIO, /* PWR_OFF */ | ||
| 63 | |||
| 64 | GPIO12_GPIO, /* touch irq */ | ||
| 65 | |||
| 66 | GPIO13_SSP2_TXD, | ||
| 67 | GPIO14_SSP2_SFRM, | ||
| 68 | MFP_CFG_OUT(GPIO19, AF1, DRIVE_LOW),/* SSP2_SYSCLK */ | ||
| 69 | GPIO22_SSP2_SCLK, | ||
| 70 | |||
| 71 | GPIO81_SSP3_TXD, | ||
| 72 | GPIO82_SSP3_RXD, | ||
| 73 | GPIO83_SSP3_SFRM, | ||
| 74 | GPIO84_SSP3_SCLK, | ||
| 75 | |||
| 76 | GPIO20_GPIO, /* SDIO int */ | ||
| 77 | GPIO32_MMC_CLK, | ||
| 78 | GPIO92_MMC_DAT_0, | ||
| 79 | GPIO109_MMC_DAT_1, | ||
| 80 | GPIO110_MMC_DAT_2, | ||
| 81 | GPIO111_MMC_DAT_3, | ||
| 82 | GPIO112_MMC_CMD, | ||
| 83 | GPIO100_GPIO, /* SD CD */ | ||
| 84 | GPIO101_GPIO, /* SD WP */ | ||
| 85 | |||
| 86 | GPIO28_AC97_BITCLK, | ||
| 87 | GPIO29_AC97_SDATA_IN_0, | ||
| 88 | GPIO30_AC97_SDATA_OUT, | ||
| 89 | GPIO31_AC97_SYNC, | ||
| 90 | GPIO113_AC97_nRESET, | ||
| 91 | |||
| 92 | GPIO34_FFUART_RXD, | ||
| 93 | GPIO35_FFUART_CTS, | ||
| 94 | GPIO36_FFUART_DCD, | ||
| 95 | GPIO37_FFUART_DSR, | ||
| 96 | GPIO38_FFUART_RI, | ||
| 97 | GPIO39_FFUART_TXD, | ||
| 98 | GPIO40_FFUART_DTR, | ||
| 99 | GPIO41_FFUART_RTS, | ||
| 100 | |||
| 101 | GPIO42_BTUART_RXD, | ||
| 102 | GPIO43_BTUART_TXD, | ||
| 103 | GPIO44_BTUART_CTS, | ||
| 104 | GPIO45_BTUART_RTS, | ||
| 105 | |||
| 106 | GPIO46_STUART_RXD, | ||
| 107 | GPIO47_STUART_TXD, | ||
| 108 | |||
| 109 | GPIO48_nPOE, | ||
| 110 | GPIO49_nPWE, | ||
| 111 | GPIO50_nPIOR, | ||
| 112 | GPIO51_nPIOW, | ||
| 113 | GPIO54_nPCE_2, | ||
| 114 | GPIO55_nPREG, | ||
| 115 | GPIO56_nPWAIT, | ||
| 116 | GPIO57_nIOIS16, /* maybe unused */ | ||
| 117 | GPIO85_nPCE_1, | ||
| 118 | GPIO98_GPIO, /* CF IRQ */ | ||
| 119 | GPIO99_GPIO, /* CF CD */ | ||
| 120 | GPIO103_GPIO, /* Reset */ | ||
| 121 | |||
| 122 | GPIO117_I2C_SCL, | ||
| 123 | GPIO118_I2C_SDA, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct pxamci_platform_data csb726_mci_data; | ||
| 127 | |||
| 128 | static int csb726_mci_init(struct device *dev, | ||
| 129 | irq_handler_t detect, void *data) | ||
| 130 | { | ||
| 131 | int err; | ||
| 132 | |||
| 133 | csb726_mci_data.detect_delay = msecs_to_jiffies(500); | ||
| 134 | |||
| 135 | err = gpio_request(CSB726_GPIO_MMC_DETECT, "MMC detect"); | ||
| 136 | if (err) | ||
| 137 | goto err_det_req; | ||
| 138 | |||
| 139 | err = gpio_direction_input(CSB726_GPIO_MMC_DETECT); | ||
| 140 | if (err) | ||
| 141 | goto err_det_dir; | ||
| 142 | |||
| 143 | err = gpio_request(CSB726_GPIO_MMC_RO, "MMC ro"); | ||
| 144 | if (err) | ||
| 145 | goto err_ro_req; | ||
| 146 | |||
| 147 | err = gpio_direction_input(CSB726_GPIO_MMC_RO); | ||
| 148 | if (err) | ||
| 149 | goto err_ro_dir; | ||
| 150 | |||
| 151 | err = request_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), detect, | ||
| 152 | IRQF_DISABLED, "MMC card detect", data); | ||
| 153 | if (err) | ||
| 154 | goto err_irq; | ||
| 155 | |||
| 156 | return 0; | ||
| 157 | |||
| 158 | err_irq: | ||
| 159 | err_ro_dir: | ||
| 160 | gpio_free(CSB726_GPIO_MMC_RO); | ||
| 161 | err_ro_req: | ||
| 162 | err_det_dir: | ||
| 163 | gpio_free(CSB726_GPIO_MMC_DETECT); | ||
| 164 | err_det_req: | ||
| 165 | return err; | ||
| 166 | } | ||
| 167 | |||
| 168 | static int csb726_mci_get_ro(struct device *dev) | ||
| 169 | { | ||
| 170 | return gpio_get_value(CSB726_GPIO_MMC_RO); | ||
| 171 | } | ||
| 172 | |||
| 173 | static void csb726_mci_exit(struct device *dev, void *data) | ||
| 174 | { | ||
| 175 | free_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), data); | ||
| 176 | gpio_free(CSB726_GPIO_MMC_RO); | ||
| 177 | gpio_free(CSB726_GPIO_MMC_DETECT); | ||
| 178 | } | ||
| 179 | |||
| 180 | static struct pxamci_platform_data csb726_mci = { | ||
| 181 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | ||
| 182 | .init = csb726_mci_init, | ||
| 183 | .get_ro = csb726_mci_get_ro, | ||
| 184 | /* FIXME setpower */ | ||
| 185 | .exit = csb726_mci_exit, | ||
| 186 | }; | ||
| 187 | |||
| 188 | static struct pxaohci_platform_data csb726_ohci_platform_data = { | ||
| 189 | .port_mode = PMM_NPS_MODE, | ||
| 190 | .flags = ENABLE_PORT1 | NO_OC_PROTECTION, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct mtd_partition csb726_flash_partitions[] = { | ||
| 194 | { | ||
| 195 | .name = "Bootloader", | ||
| 196 | .offset = 0, | ||
| 197 | .size = CSB726_FLASH_uMON, | ||
| 198 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 199 | }, | ||
| 200 | { | ||
| 201 | .name = "root", | ||
| 202 | .offset = MTDPART_OFS_APPEND, | ||
| 203 | .size = MTDPART_SIZ_FULL, | ||
| 204 | } | ||
| 205 | }; | ||
| 206 | |||
| 207 | static struct physmap_flash_data csb726_flash_data = { | ||
| 208 | .width = 2, | ||
| 209 | .parts = csb726_flash_partitions, | ||
| 210 | .nr_parts = ARRAY_SIZE(csb726_flash_partitions), | ||
| 211 | }; | ||
| 212 | |||
| 213 | static struct resource csb726_flash_resources[] = { | ||
| 214 | { | ||
| 215 | .start = PXA_CS0_PHYS, | ||
| 216 | .end = PXA_CS0_PHYS + CSB726_FLASH_SIZE - 1 , | ||
| 217 | .flags = IORESOURCE_MEM, | ||
| 218 | } | ||
| 219 | }; | ||
| 220 | |||
| 221 | static struct platform_device csb726_flash = { | ||
| 222 | .name = "physmap-flash", | ||
| 223 | .dev = { | ||
| 224 | .platform_data = &csb726_flash_data, | ||
| 225 | }, | ||
| 226 | .resource = csb726_flash_resources, | ||
| 227 | .num_resources = ARRAY_SIZE(csb726_flash_resources), | ||
| 228 | }; | ||
| 229 | |||
| 230 | static struct resource csb726_sm501_resources[] = { | ||
| 231 | { | ||
| 232 | .start = PXA_CS4_PHYS, | ||
| 233 | .end = PXA_CS4_PHYS + SZ_8M - 1, | ||
| 234 | .flags = IORESOURCE_MEM, | ||
| 235 | .name = "sm501-localmem", | ||
| 236 | }, | ||
| 237 | { | ||
| 238 | .start = PXA_CS4_PHYS + SZ_64M - SZ_2M, | ||
| 239 | .end = PXA_CS4_PHYS + SZ_64M - 1, | ||
| 240 | .flags = IORESOURCE_MEM, | ||
| 241 | .name = "sm501-regs", | ||
| 242 | }, | ||
| 243 | { | ||
| 244 | .start = CSB726_IRQ_SM501, | ||
| 245 | .end = CSB726_IRQ_SM501, | ||
| 246 | .flags = IORESOURCE_IRQ, | ||
| 247 | }, | ||
| 248 | }; | ||
| 249 | |||
| 250 | static struct sm501_initdata csb726_sm501_initdata = { | ||
| 251 | /* .devices = SM501_USE_USB_HOST, */ | ||
| 252 | .devices = SM501_USE_USB_HOST | SM501_USE_UART0 | SM501_USE_UART1, | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct sm501_platdata csb726_sm501_platdata = { | ||
| 256 | .init = &csb726_sm501_initdata, | ||
| 257 | }; | ||
| 258 | |||
| 259 | static struct platform_device csb726_sm501 = { | ||
| 260 | .name = "sm501", | ||
| 261 | .id = 0, | ||
| 262 | .num_resources = ARRAY_SIZE(csb726_sm501_resources), | ||
| 263 | .resource = csb726_sm501_resources, | ||
| 264 | .dev = { | ||
| 265 | .platform_data = &csb726_sm501_platdata, | ||
| 266 | }, | ||
| 267 | }; | ||
| 268 | |||
| 269 | static struct resource csb726_lan_resources[] = { | ||
| 270 | { | ||
| 271 | .start = PXA_CS3_PHYS, | ||
| 272 | .end = PXA_CS3_PHYS + SZ_64K - 1, | ||
| 273 | .flags = IORESOURCE_MEM, | ||
| 274 | }, | ||
| 275 | { | ||
| 276 | .start = CSB726_IRQ_LAN, | ||
| 277 | .end = CSB726_IRQ_LAN, | ||
| 278 | .flags = IORESOURCE_IRQ, | ||
| 279 | }, | ||
| 280 | }; | ||
| 281 | |||
| 282 | static struct platform_device csb726_lan = { | ||
| 283 | .name = "smc911x", | ||
| 284 | .id = -1, | ||
| 285 | .num_resources = ARRAY_SIZE(csb726_lan_resources), | ||
| 286 | .resource = csb726_lan_resources, | ||
| 287 | }; | ||
| 288 | |||
| 289 | static struct platform_device *devices[] __initdata = { | ||
| 290 | &csb726_flash, | ||
| 291 | &csb726_sm501, | ||
| 292 | &csb726_lan, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static void __init csb726_init(void) | ||
| 296 | { | ||
| 297 | pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config)); | ||
| 298 | /* MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */ | ||
| 299 | /* MSC2 = 0x06697ff4; *//* none/SM501 */ | ||
| 300 | MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */ | ||
| 301 | |||
| 302 | pxa_set_i2c_info(NULL); | ||
| 303 | pxa27x_set_i2c_power_info(NULL); | ||
| 304 | pxa_set_mci_info(&csb726_mci); | ||
| 305 | pxa_set_ohci_info(&csb726_ohci_platform_data); | ||
| 306 | |||
| 307 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 308 | } | ||
| 309 | |||
| 310 | MACHINE_START(CSB726, "Cogent CSB726") | ||
| 311 | .phys_io = 0x40000000, | ||
| 312 | .boot_params = 0xa0000100, | ||
| 313 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 314 | .map_io = pxa_map_io, | ||
| 315 | .init_irq = pxa27x_init_irq, | ||
| 316 | .init_machine = csb726_init, | ||
| 317 | .timer = &pxa_timer, | ||
| 318 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index e16f8e3d58d3..d245e59c51b1 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
| @@ -4,7 +4,6 @@ | |||
| 4 | #include <linux/platform_device.h> | 4 | #include <linux/platform_device.h> |
| 5 | #include <linux/dma-mapping.h> | 5 | #include <linux/dma-mapping.h> |
| 6 | 6 | ||
| 7 | #include <mach/pxa-regs.h> | ||
| 8 | #include <mach/udc.h> | 7 | #include <mach/udc.h> |
| 9 | #include <mach/pxafb.h> | 8 | #include <mach/pxafb.h> |
| 10 | #include <mach/mmc.h> | 9 | #include <mach/mmc.h> |
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c index 1bd7f740427c..74d3f8987c5c 100644 --- a/arch/arm/mach-pxa/e330.c +++ b/arch/arm/mach-pxa/e330.c | |||
| @@ -20,9 +20,7 @@ | |||
| 20 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 22 | 22 | ||
| 23 | #include <mach/mfp-pxa25x.h> | 23 | #include <mach/pxa25x.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/eseries-gpio.h> | 24 | #include <mach/eseries-gpio.h> |
| 27 | #include <mach/udc.h> | 25 | #include <mach/udc.h> |
| 28 | 26 | ||
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c index edcd9d5ce545..080036272131 100644 --- a/arch/arm/mach-pxa/e350.c +++ b/arch/arm/mach-pxa/e350.c | |||
| @@ -21,9 +21,7 @@ | |||
| 21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 22 | 22 | ||
| 23 | #include <mach/irqs.h> | 23 | #include <mach/irqs.h> |
| 24 | #include <mach/mfp-pxa25x.h> | 24 | #include <mach/pxa25x.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/hardware.h> | ||
| 27 | #include <mach/eseries-gpio.h> | 25 | #include <mach/eseries-gpio.h> |
| 28 | #include <mach/udc.h> | 26 | #include <mach/udc.h> |
| 29 | 27 | ||
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c index 77bb8e2c48c0..ed9c0c3f64a2 100644 --- a/arch/arm/mach-pxa/e400.c +++ b/arch/arm/mach-pxa/e400.c | |||
| @@ -22,9 +22,7 @@ | |||
| 22 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 24 | 24 | ||
| 25 | #include <mach/mfp-pxa25x.h> | 25 | #include <mach/pxa25x.h> |
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/eseries-gpio.h> | 26 | #include <mach/eseries-gpio.h> |
| 29 | #include <mach/pxafb.h> | 27 | #include <mach/pxafb.h> |
| 30 | #include <mach/udc.h> | 28 | #include <mach/udc.h> |
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c index a6fff782e7a8..07500a04fd8c 100644 --- a/arch/arm/mach-pxa/e740.c +++ b/arch/arm/mach-pxa/e740.c | |||
| @@ -24,9 +24,7 @@ | |||
| 24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| 26 | 26 | ||
| 27 | #include <mach/mfp-pxa25x.h> | 27 | #include <mach/pxa25x.h> |
| 28 | #include <mach/pxa-regs.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/eseries-gpio.h> | 28 | #include <mach/eseries-gpio.h> |
| 31 | #include <mach/udc.h> | 29 | #include <mach/udc.h> |
| 32 | #include <mach/irda.h> | 30 | #include <mach/irda.h> |
| @@ -194,7 +192,7 @@ static void __init e740_init(void) | |||
| 194 | { | 192 | { |
| 195 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); | 193 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); |
| 196 | eseries_register_clks(); | 194 | eseries_register_clks(); |
| 197 | clk_add_alias("CLK_CK48M", &e740_t7l66xb_device.dev, | 195 | clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name, |
| 198 | "UDCCLK", &pxa25x_device_udc.dev), | 196 | "UDCCLK", &pxa25x_device_udc.dev), |
| 199 | eseries_get_tmio_gpios(); | 197 | eseries_get_tmio_gpios(); |
| 200 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 198 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index 665066fd280e..6126c04e02bc 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c | |||
| @@ -23,9 +23,7 @@ | |||
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 25 | 25 | ||
| 26 | #include <mach/mfp-pxa25x.h> | 26 | #include <mach/pxa25x.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/eseries-gpio.h> | 27 | #include <mach/eseries-gpio.h> |
| 30 | #include <mach/udc.h> | 28 | #include <mach/udc.h> |
| 31 | #include <mach/irda.h> | 29 | #include <mach/irda.h> |
| @@ -195,7 +193,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 195 | static void __init e750_init(void) | 193 | static void __init e750_init(void) |
| 196 | { | 194 | { |
| 197 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); | 195 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); |
| 198 | clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev, | 196 | clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name, |
| 199 | "GPIO11_CLK", NULL), | 197 | "GPIO11_CLK", NULL), |
| 200 | eseries_get_tmio_gpios(); | 198 | eseries_get_tmio_gpios(); |
| 201 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 199 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c index cc9b1293e866..74ab09812a72 100644 --- a/arch/arm/mach-pxa/e800.c +++ b/arch/arm/mach-pxa/e800.c | |||
| @@ -23,9 +23,7 @@ | |||
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 25 | 25 | ||
| 26 | #include <mach/mfp-pxa25x.h> | 26 | #include <mach/pxa25x.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/eseries-gpio.h> | 27 | #include <mach/eseries-gpio.h> |
| 30 | #include <mach/udc.h> | 28 | #include <mach/udc.h> |
| 31 | #include <mach/irqs.h> | 29 | #include <mach/irqs.h> |
| @@ -196,7 +194,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 196 | 194 | ||
| 197 | static void __init e800_init(void) | 195 | static void __init e800_init(void) |
| 198 | { | 196 | { |
| 199 | clk_add_alias("CLK_CK3P6MI", &e800_tc6393xb_device.dev, | 197 | clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name, |
| 200 | "GPIO11_CLK", NULL), | 198 | "GPIO11_CLK", NULL), |
| 201 | eseries_get_tmio_gpios(); | 199 | eseries_get_tmio_gpios(); |
| 202 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 200 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index f5ed8038ede5..920dfb8d36da 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
| @@ -11,40 +11,63 @@ | |||
| 11 | 11 | ||
| 12 | #include <linux/irq.h> | 12 | #include <linux/irq.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/delay.h> | ||
| 14 | 15 | ||
| 15 | #include <linux/dm9000.h> | 16 | #include <linux/dm9000.h> |
| 16 | #include <linux/rtc-v3020.h> | 17 | #include <linux/rtc-v3020.h> |
| 17 | #include <linux/mtd/nand.h> | 18 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/mtd/partitions.h> | 19 | #include <linux/mtd/partitions.h> |
| 20 | #include <linux/mtd/physmap.h> | ||
| 19 | #include <linux/input.h> | 21 | #include <linux/input.h> |
| 20 | #include <linux/gpio_keys.h> | 22 | #include <linux/gpio_keys.h> |
| 21 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
| 24 | #include <linux/mfd/da903x.h> | ||
| 25 | #include <linux/regulator/machine.h> | ||
| 26 | #include <linux/spi/spi.h> | ||
| 27 | #include <linux/spi/tdo24m.h> | ||
| 28 | #include <linux/power_supply.h> | ||
| 29 | #include <linux/apm-emulation.h> | ||
| 30 | |||
| 31 | #include <media/soc_camera.h> | ||
| 22 | 32 | ||
| 23 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
| 25 | 35 | ||
| 26 | #include <mach/mfp-pxa27x.h> | 36 | #include <mach/pxa27x.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/pxa27x-udc.h> | 37 | #include <mach/pxa27x-udc.h> |
| 29 | #include <mach/audio.h> | 38 | #include <mach/audio.h> |
| 30 | #include <mach/pxafb.h> | 39 | #include <mach/pxafb.h> |
| 31 | #include <mach/ohci.h> | 40 | #include <mach/ohci.h> |
| 32 | #include <mach/mmc.h> | 41 | #include <mach/mmc.h> |
| 33 | #include <mach/pxa27x_keypad.h> | 42 | #include <mach/pxa27x_keypad.h> |
| 43 | #include <mach/i2c.h> | ||
| 44 | #include <mach/camera.h> | ||
| 45 | #include <mach/pxa2xx_spi.h> | ||
| 34 | 46 | ||
| 35 | #include "generic.h" | 47 | #include "generic.h" |
| 48 | #include "devices.h" | ||
| 36 | 49 | ||
| 37 | /* GPIO IRQ usage */ | 50 | /* EM-X270 specific GPIOs */ |
| 38 | #define GPIO41_ETHIRQ (41) | ||
| 39 | #define GPIO13_MMC_CD (13) | 51 | #define GPIO13_MMC_CD (13) |
| 52 | #define GPIO95_MMC_WP (95) | ||
| 53 | #define GPIO56_NAND_RB (56) | ||
| 54 | |||
| 55 | /* eXeda specific GPIOs */ | ||
| 56 | #define GPIO114_MMC_CD (114) | ||
| 57 | #define GPIO20_NAND_RB (20) | ||
| 58 | #define GPIO38_SD_PWEN (38) | ||
| 59 | |||
| 60 | /* common GPIOs */ | ||
| 61 | #define GPIO11_NAND_CS (11) | ||
| 62 | #define GPIO93_CAM_RESET (93) | ||
| 63 | #define GPIO41_ETHIRQ (41) | ||
| 40 | #define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ) | 64 | #define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ) |
| 41 | #define EM_X270_MMC_CD IRQ_GPIO(GPIO13_MMC_CD) | ||
| 42 | 65 | ||
| 43 | /* NAND control GPIOs */ | 66 | static int mmc_cd; |
| 44 | #define GPIO11_NAND_CS (11) | 67 | static int nand_rb; |
| 45 | #define GPIO56_NAND_RB (56) | 68 | static int dm9000_flags; |
| 46 | 69 | ||
| 47 | static unsigned long em_x270_pin_config[] = { | 70 | static unsigned long common_pin_config[] = { |
| 48 | /* AC'97 */ | 71 | /* AC'97 */ |
| 49 | GPIO28_AC97_BITCLK, | 72 | GPIO28_AC97_BITCLK, |
| 50 | GPIO29_AC97_SDATA_IN_0, | 73 | GPIO29_AC97_SDATA_IN_0, |
| @@ -150,21 +173,32 @@ static unsigned long em_x270_pin_config[] = { | |||
| 150 | GPIO18_RDY, | 173 | GPIO18_RDY, |
| 151 | 174 | ||
| 152 | /* GPIO */ | 175 | /* GPIO */ |
| 153 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, | 176 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* sleep/resume button */ |
| 154 | 177 | ||
| 155 | /* power controls */ | 178 | /* power controls */ |
| 156 | GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* GPRS_PWEN */ | 179 | GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* GPRS_PWEN */ |
| 180 | GPIO93_GPIO | MFP_LPM_DRIVE_LOW, /* Camera reset */ | ||
| 157 | GPIO115_GPIO | MFP_LPM_DRIVE_LOW, /* WLAN_PWEN */ | 181 | GPIO115_GPIO | MFP_LPM_DRIVE_LOW, /* WLAN_PWEN */ |
| 158 | 182 | ||
| 159 | /* NAND controls */ | 183 | /* NAND controls */ |
| 160 | GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */ | 184 | GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */ |
| 161 | GPIO56_GPIO, /* NAND Ready/Busy */ | ||
| 162 | 185 | ||
| 163 | /* interrupts */ | 186 | /* interrupts */ |
| 164 | GPIO13_GPIO, /* MMC card detect */ | ||
| 165 | GPIO41_GPIO, /* DM9000 interrupt */ | 187 | GPIO41_GPIO, /* DM9000 interrupt */ |
| 166 | }; | 188 | }; |
| 167 | 189 | ||
| 190 | static unsigned long em_x270_pin_config[] = { | ||
| 191 | GPIO13_GPIO, /* MMC card detect */ | ||
| 192 | GPIO56_GPIO, /* NAND Ready/Busy */ | ||
| 193 | GPIO95_GPIO, /* MMC Write protect */ | ||
| 194 | }; | ||
| 195 | |||
| 196 | static unsigned long exeda_pin_config[] = { | ||
| 197 | GPIO20_GPIO, /* NAND Ready/Busy */ | ||
| 198 | GPIO38_GPIO | MFP_LPM_DRIVE_LOW, /* SD slot power */ | ||
| 199 | GPIO114_GPIO, /* MMC card detect */ | ||
| 200 | }; | ||
| 201 | |||
| 168 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | 202 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
| 169 | static struct resource em_x270_dm9000_resource[] = { | 203 | static struct resource em_x270_dm9000_resource[] = { |
| 170 | [0] = { | 204 | [0] = { |
| @@ -185,7 +219,7 @@ static struct resource em_x270_dm9000_resource[] = { | |||
| 185 | }; | 219 | }; |
| 186 | 220 | ||
| 187 | static struct dm9000_plat_data em_x270_dm9000_platdata = { | 221 | static struct dm9000_plat_data em_x270_dm9000_platdata = { |
| 188 | .flags = DM9000_PLATF_32BITONLY, | 222 | .flags = DM9000_PLATF_NO_EEPROM, |
| 189 | }; | 223 | }; |
| 190 | 224 | ||
| 191 | static struct platform_device em_x270_dm9000 = { | 225 | static struct platform_device em_x270_dm9000 = { |
| @@ -200,6 +234,7 @@ static struct platform_device em_x270_dm9000 = { | |||
| 200 | 234 | ||
| 201 | static void __init em_x270_init_dm9000(void) | 235 | static void __init em_x270_init_dm9000(void) |
| 202 | { | 236 | { |
| 237 | em_x270_dm9000_platdata.flags |= dm9000_flags; | ||
| 203 | platform_device_register(&em_x270_dm9000); | 238 | platform_device_register(&em_x270_dm9000); |
| 204 | } | 239 | } |
| 205 | #else | 240 | #else |
| @@ -289,7 +324,7 @@ static int em_x270_nand_device_ready(struct mtd_info *mtd) | |||
| 289 | { | 324 | { |
| 290 | dsb(); | 325 | dsb(); |
| 291 | 326 | ||
| 292 | return gpio_get_value(GPIO56_NAND_RB); | 327 | return gpio_get_value(nand_rb); |
| 293 | } | 328 | } |
| 294 | 329 | ||
| 295 | static struct mtd_partition em_x270_partition_info[] = { | 330 | static struct mtd_partition em_x270_partition_info[] = { |
| @@ -354,14 +389,14 @@ static void __init em_x270_init_nand(void) | |||
| 354 | 389 | ||
| 355 | gpio_direction_output(GPIO11_NAND_CS, 1); | 390 | gpio_direction_output(GPIO11_NAND_CS, 1); |
| 356 | 391 | ||
| 357 | err = gpio_request(GPIO56_NAND_RB, "NAND R/B"); | 392 | err = gpio_request(nand_rb, "NAND R/B"); |
| 358 | if (err) { | 393 | if (err) { |
| 359 | pr_warning("EM-X270: failed to request NAND R/B gpio\n"); | 394 | pr_warning("EM-X270: failed to request NAND R/B gpio\n"); |
| 360 | gpio_free(GPIO11_NAND_CS); | 395 | gpio_free(GPIO11_NAND_CS); |
| 361 | return; | 396 | return; |
| 362 | } | 397 | } |
| 363 | 398 | ||
| 364 | gpio_direction_input(GPIO56_NAND_RB); | 399 | gpio_direction_input(nand_rb); |
| 365 | 400 | ||
| 366 | platform_device_register(&em_x270_nand); | 401 | platform_device_register(&em_x270_nand); |
| 367 | } | 402 | } |
| @@ -369,6 +404,61 @@ static void __init em_x270_init_nand(void) | |||
| 369 | static inline void em_x270_init_nand(void) {} | 404 | static inline void em_x270_init_nand(void) {} |
| 370 | #endif | 405 | #endif |
| 371 | 406 | ||
| 407 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 408 | static struct mtd_partition em_x270_nor_parts[] = { | ||
| 409 | { | ||
| 410 | .name = "Bootloader", | ||
| 411 | .offset = 0x00000000, | ||
| 412 | .size = 0x00050000, | ||
| 413 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 414 | }, { | ||
| 415 | .name = "Environment", | ||
| 416 | .offset = 0x00050000, | ||
| 417 | .size = 0x00010000, | ||
| 418 | }, { | ||
| 419 | .name = "Reserved", | ||
| 420 | .offset = 0x00060000, | ||
| 421 | .size = 0x00050000, | ||
| 422 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 423 | }, { | ||
| 424 | .name = "Splashscreen", | ||
| 425 | .offset = 0x000b0000, | ||
| 426 | .size = 0x00050000, | ||
| 427 | } | ||
| 428 | }; | ||
| 429 | |||
| 430 | static struct physmap_flash_data em_x270_nor_data[] = { | ||
| 431 | [0] = { | ||
| 432 | .width = 2, | ||
| 433 | .parts = em_x270_nor_parts, | ||
| 434 | .nr_parts = ARRAY_SIZE(em_x270_nor_parts), | ||
| 435 | }, | ||
| 436 | }; | ||
| 437 | |||
| 438 | static struct resource em_x270_nor_flash_resource = { | ||
| 439 | .start = PXA_CS0_PHYS, | ||
| 440 | .end = PXA_CS0_PHYS + SZ_1M - 1, | ||
| 441 | .flags = IORESOURCE_MEM, | ||
| 442 | }; | ||
| 443 | |||
| 444 | static struct platform_device em_x270_physmap_flash = { | ||
| 445 | .name = "physmap-flash", | ||
| 446 | .id = 0, | ||
| 447 | .num_resources = 1, | ||
| 448 | .resource = &em_x270_nor_flash_resource, | ||
| 449 | .dev = { | ||
| 450 | .platform_data = &em_x270_nor_data, | ||
| 451 | }, | ||
| 452 | }; | ||
| 453 | |||
| 454 | static void __init em_x270_init_nor(void) | ||
| 455 | { | ||
| 456 | platform_device_register(&em_x270_physmap_flash); | ||
| 457 | } | ||
| 458 | #else | ||
| 459 | static inline void em_x270_init_nor(void) {} | ||
| 460 | #endif | ||
| 461 | |||
| 372 | /* PXA27x OHCI controller setup */ | 462 | /* PXA27x OHCI controller setup */ |
| 373 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | 463 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
| 374 | static int em_x270_ohci_init(struct device *dev) | 464 | static int em_x270_ohci_init(struct device *dev) |
| @@ -395,40 +485,93 @@ static inline void em_x270_init_ohci(void) {} | |||
| 395 | 485 | ||
| 396 | /* MCI controller setup */ | 486 | /* MCI controller setup */ |
| 397 | #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE) | 487 | #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE) |
| 488 | static struct regulator *em_x270_sdio_ldo; | ||
| 489 | |||
| 398 | static int em_x270_mci_init(struct device *dev, | 490 | static int em_x270_mci_init(struct device *dev, |
| 399 | irq_handler_t em_x270_detect_int, | 491 | irq_handler_t em_x270_detect_int, |
| 400 | void *data) | 492 | void *data) |
| 401 | { | 493 | { |
| 402 | int err = request_irq(EM_X270_MMC_CD, em_x270_detect_int, | 494 | int err; |
| 403 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | 495 | |
| 496 | em_x270_sdio_ldo = regulator_get(dev, "vcc sdio"); | ||
| 497 | if (IS_ERR(em_x270_sdio_ldo)) { | ||
| 498 | dev_err(dev, "can't request SDIO power supply: %ld\n", | ||
| 499 | PTR_ERR(em_x270_sdio_ldo)); | ||
| 500 | return PTR_ERR(em_x270_sdio_ldo); | ||
| 501 | } | ||
| 502 | |||
| 503 | err = request_irq(gpio_to_irq(mmc_cd), em_x270_detect_int, | ||
| 504 | IRQF_DISABLED | IRQF_TRIGGER_RISING | | ||
| 505 | IRQF_TRIGGER_FALLING, | ||
| 404 | "MMC card detect", data); | 506 | "MMC card detect", data); |
| 405 | if (err) { | 507 | if (err) { |
| 406 | printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n", | 508 | dev_err(dev, "can't request MMC card detect IRQ: %d\n", err); |
| 407 | __func__, err); | 509 | goto err_irq; |
| 408 | return err; | 510 | } |
| 511 | |||
| 512 | if (machine_is_em_x270()) { | ||
| 513 | err = gpio_request(GPIO95_MMC_WP, "MMC WP"); | ||
| 514 | if (err) { | ||
| 515 | dev_err(dev, "can't request MMC write protect: %d\n", | ||
| 516 | err); | ||
| 517 | goto err_gpio_wp; | ||
| 518 | } | ||
| 519 | gpio_direction_input(GPIO95_MMC_WP); | ||
| 520 | } else { | ||
| 521 | err = gpio_request(GPIO38_SD_PWEN, "sdio power"); | ||
| 522 | if (err) { | ||
| 523 | dev_err(dev, "can't request MMC power control : %d\n", | ||
| 524 | err); | ||
| 525 | goto err_gpio_wp; | ||
| 526 | } | ||
| 527 | gpio_direction_output(GPIO38_SD_PWEN, 1); | ||
| 409 | } | 528 | } |
| 410 | 529 | ||
| 411 | return 0; | 530 | return 0; |
| 531 | |||
| 532 | err_gpio_wp: | ||
| 533 | free_irq(gpio_to_irq(mmc_cd), data); | ||
| 534 | err_irq: | ||
| 535 | regulator_put(em_x270_sdio_ldo); | ||
| 536 | |||
| 537 | return err; | ||
| 412 | } | 538 | } |
| 413 | 539 | ||
| 414 | static void em_x270_mci_setpower(struct device *dev, unsigned int vdd) | 540 | static void em_x270_mci_setpower(struct device *dev, unsigned int vdd) |
| 415 | { | 541 | { |
| 416 | /* | 542 | struct pxamci_platform_data* p_d = dev->platform_data; |
| 417 | FIXME: current hardware implementation does not allow to | 543 | |
| 418 | enable/disable MMC power. This will be fixed in next HW releases, | 544 | if ((1 << vdd) & p_d->ocr_mask) { |
| 419 | and we'll need to add implmentation here. | 545 | int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000; |
| 420 | */ | 546 | |
| 421 | return; | 547 | regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV); |
| 548 | regulator_enable(em_x270_sdio_ldo); | ||
| 549 | } else { | ||
| 550 | regulator_disable(em_x270_sdio_ldo); | ||
| 551 | } | ||
| 422 | } | 552 | } |
| 423 | 553 | ||
| 424 | static void em_x270_mci_exit(struct device *dev, void *data) | 554 | static void em_x270_mci_exit(struct device *dev, void *data) |
| 425 | { | 555 | { |
| 426 | int irq = gpio_to_irq(GPIO13_MMC_CD); | 556 | free_irq(gpio_to_irq(mmc_cd), data); |
| 427 | free_irq(irq, data); | 557 | regulator_put(em_x270_sdio_ldo); |
| 558 | |||
| 559 | if (machine_is_em_x270()) | ||
| 560 | gpio_free(GPIO95_MMC_WP); | ||
| 561 | else | ||
| 562 | gpio_free(GPIO38_SD_PWEN); | ||
| 563 | } | ||
| 564 | |||
| 565 | static int em_x270_mci_get_ro(struct device *dev) | ||
| 566 | { | ||
| 567 | return gpio_get_value(GPIO95_MMC_WP); | ||
| 428 | } | 568 | } |
| 429 | 569 | ||
| 430 | static struct pxamci_platform_data em_x270_mci_platform_data = { | 570 | static struct pxamci_platform_data em_x270_mci_platform_data = { |
| 431 | .ocr_mask = MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31, | 571 | .ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23| |
| 572 | MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27| | ||
| 573 | MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| | ||
| 574 | MMC_VDD_30_31|MMC_VDD_31_32, | ||
| 432 | .init = em_x270_mci_init, | 575 | .init = em_x270_mci_init, |
| 433 | .setpower = em_x270_mci_setpower, | 576 | .setpower = em_x270_mci_setpower, |
| 434 | .exit = em_x270_mci_exit, | 577 | .exit = em_x270_mci_exit, |
| @@ -436,33 +579,53 @@ static struct pxamci_platform_data em_x270_mci_platform_data = { | |||
| 436 | 579 | ||
| 437 | static void __init em_x270_init_mmc(void) | 580 | static void __init em_x270_init_mmc(void) |
| 438 | { | 581 | { |
| 582 | if (machine_is_em_x270()) | ||
| 583 | em_x270_mci_platform_data.get_ro = em_x270_mci_get_ro; | ||
| 584 | |||
| 585 | em_x270_mci_platform_data.detect_delay = msecs_to_jiffies(250); | ||
| 439 | pxa_set_mci_info(&em_x270_mci_platform_data); | 586 | pxa_set_mci_info(&em_x270_mci_platform_data); |
| 440 | } | 587 | } |
| 441 | #else | 588 | #else |
| 442 | static inline void em_x270_init_mmc(void) {} | 589 | static inline void em_x270_init_mmc(void) {} |
| 443 | #endif | 590 | #endif |
| 444 | 591 | ||
| 445 | /* LCD 480x640 */ | 592 | /* LCD */ |
| 446 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | 593 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
| 447 | static struct pxafb_mode_info em_x270_lcd_mode = { | 594 | static struct pxafb_mode_info em_x270_lcd_modes[] = { |
| 448 | .pixclock = 50000, | 595 | [0] = { |
| 449 | .bpp = 16, | 596 | .pixclock = 38250, |
| 450 | .xres = 480, | 597 | .bpp = 16, |
| 451 | .yres = 640, | 598 | .xres = 480, |
| 452 | .hsync_len = 8, | 599 | .yres = 640, |
| 453 | .vsync_len = 2, | 600 | .hsync_len = 8, |
| 454 | .left_margin = 8, | 601 | .vsync_len = 2, |
| 455 | .upper_margin = 0, | 602 | .left_margin = 8, |
| 456 | .right_margin = 24, | 603 | .upper_margin = 2, |
| 457 | .lower_margin = 4, | 604 | .right_margin = 24, |
| 458 | .cmap_greyscale = 0, | 605 | .lower_margin = 4, |
| 606 | .sync = 0, | ||
| 607 | }, | ||
| 608 | [1] = { | ||
| 609 | .pixclock = 153800, | ||
| 610 | .bpp = 16, | ||
| 611 | .xres = 240, | ||
| 612 | .yres = 320, | ||
| 613 | .hsync_len = 8, | ||
| 614 | .vsync_len = 2, | ||
| 615 | .left_margin = 8, | ||
| 616 | .upper_margin = 2, | ||
| 617 | .right_margin = 88, | ||
| 618 | .lower_margin = 2, | ||
| 619 | .sync = 0, | ||
| 620 | }, | ||
| 459 | }; | 621 | }; |
| 460 | 622 | ||
| 461 | static struct pxafb_mach_info em_x270_lcd = { | 623 | static struct pxafb_mach_info em_x270_lcd = { |
| 462 | .modes = &em_x270_lcd_mode, | 624 | .modes = em_x270_lcd_modes, |
| 463 | .num_modes = 1, | 625 | .num_modes = 2, |
| 464 | .lcd_conn = LCD_COLOR_TFT_16BPP, | 626 | .lcd_conn = LCD_COLOR_TFT_16BPP, |
| 465 | }; | 627 | }; |
| 628 | |||
| 466 | static void __init em_x270_init_lcd(void) | 629 | static void __init em_x270_init_lcd(void) |
| 467 | { | 630 | { |
| 468 | set_pxa_fb_info(&em_x270_lcd); | 631 | set_pxa_fb_info(&em_x270_lcd); |
| @@ -471,6 +634,40 @@ static void __init em_x270_init_lcd(void) | |||
| 471 | static inline void em_x270_init_lcd(void) {} | 634 | static inline void em_x270_init_lcd(void) {} |
| 472 | #endif | 635 | #endif |
| 473 | 636 | ||
| 637 | #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) | ||
| 638 | static struct pxa2xx_spi_master em_x270_spi_info = { | ||
| 639 | .num_chipselect = 1, | ||
| 640 | }; | ||
| 641 | |||
| 642 | static struct pxa2xx_spi_chip em_x270_tdo24m_chip = { | ||
| 643 | .rx_threshold = 1, | ||
| 644 | .tx_threshold = 1, | ||
| 645 | }; | ||
| 646 | |||
| 647 | static struct tdo24m_platform_data em_x270_tdo24m_pdata = { | ||
| 648 | .model = TDO35S, | ||
| 649 | }; | ||
| 650 | |||
| 651 | static struct spi_board_info em_x270_spi_devices[] __initdata = { | ||
| 652 | { | ||
| 653 | .modalias = "tdo24m", | ||
| 654 | .max_speed_hz = 1000000, | ||
| 655 | .bus_num = 1, | ||
| 656 | .chip_select = 0, | ||
| 657 | .controller_data = &em_x270_tdo24m_chip, | ||
| 658 | .platform_data = &em_x270_tdo24m_pdata, | ||
| 659 | }, | ||
| 660 | }; | ||
| 661 | |||
| 662 | static void __init em_x270_init_spi(void) | ||
| 663 | { | ||
| 664 | pxa2xx_set_spi_info(1, &em_x270_spi_info); | ||
| 665 | spi_register_board_info(ARRAY_AND_SIZE(em_x270_spi_devices)); | ||
| 666 | } | ||
| 667 | #else | ||
| 668 | static inline void em_x270_init_spi(void) {} | ||
| 669 | #endif | ||
| 670 | |||
| 474 | #if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) | 671 | #if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) |
| 475 | static void __init em_x270_init_ac97(void) | 672 | static void __init em_x270_init_ac97(void) |
| 476 | { | 673 | { |
| @@ -481,23 +678,76 @@ static inline void em_x270_init_ac97(void) {} | |||
| 481 | #endif | 678 | #endif |
| 482 | 679 | ||
| 483 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) | 680 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) |
| 484 | static unsigned int em_x270_matrix_keys[] = { | 681 | static unsigned int em_x270_module_matrix_keys[] = { |
| 485 | KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B), | 682 | KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B), |
| 486 | KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT), | 683 | KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT), |
| 487 | KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D), | 684 | KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D), |
| 488 | }; | 685 | }; |
| 489 | 686 | ||
| 490 | struct pxa27x_keypad_platform_data em_x270_keypad_info = { | 687 | struct pxa27x_keypad_platform_data em_x270_module_keypad_info = { |
| 491 | /* code map for the matrix keys */ | 688 | /* code map for the matrix keys */ |
| 492 | .matrix_key_rows = 3, | 689 | .matrix_key_rows = 3, |
| 493 | .matrix_key_cols = 3, | 690 | .matrix_key_cols = 3, |
| 494 | .matrix_key_map = em_x270_matrix_keys, | 691 | .matrix_key_map = em_x270_module_matrix_keys, |
| 495 | .matrix_key_map_size = ARRAY_SIZE(em_x270_matrix_keys), | 692 | .matrix_key_map_size = ARRAY_SIZE(em_x270_module_matrix_keys), |
| 693 | }; | ||
| 694 | |||
| 695 | static unsigned int em_x270_exeda_matrix_keys[] = { | ||
| 696 | KEY(0, 0, KEY_RIGHTSHIFT), KEY(0, 1, KEY_RIGHTCTRL), | ||
| 697 | KEY(0, 2, KEY_RIGHTALT), KEY(0, 3, KEY_SPACE), | ||
| 698 | KEY(0, 4, KEY_LEFTALT), KEY(0, 5, KEY_LEFTCTRL), | ||
| 699 | KEY(0, 6, KEY_ENTER), KEY(0, 7, KEY_SLASH), | ||
| 700 | |||
| 701 | KEY(1, 0, KEY_DOT), KEY(1, 1, KEY_M), | ||
| 702 | KEY(1, 2, KEY_N), KEY(1, 3, KEY_B), | ||
| 703 | KEY(1, 4, KEY_V), KEY(1, 5, KEY_C), | ||
| 704 | KEY(1, 6, KEY_X), KEY(1, 7, KEY_Z), | ||
| 705 | |||
| 706 | KEY(2, 0, KEY_LEFTSHIFT), KEY(2, 1, KEY_SEMICOLON), | ||
| 707 | KEY(2, 2, KEY_L), KEY(2, 3, KEY_K), | ||
| 708 | KEY(2, 4, KEY_J), KEY(2, 5, KEY_H), | ||
| 709 | KEY(2, 6, KEY_G), KEY(2, 7, KEY_F), | ||
| 710 | |||
| 711 | KEY(3, 0, KEY_D), KEY(3, 1, KEY_S), | ||
| 712 | KEY(3, 2, KEY_A), KEY(3, 3, KEY_TAB), | ||
| 713 | KEY(3, 4, KEY_BACKSPACE), KEY(3, 5, KEY_P), | ||
| 714 | KEY(3, 6, KEY_O), KEY(3, 7, KEY_I), | ||
| 715 | |||
| 716 | KEY(4, 0, KEY_U), KEY(4, 1, KEY_Y), | ||
| 717 | KEY(4, 2, KEY_T), KEY(4, 3, KEY_R), | ||
| 718 | KEY(4, 4, KEY_E), KEY(4, 5, KEY_W), | ||
| 719 | KEY(4, 6, KEY_Q), KEY(4, 7, KEY_MINUS), | ||
| 720 | |||
| 721 | KEY(5, 0, KEY_0), KEY(5, 1, KEY_9), | ||
| 722 | KEY(5, 2, KEY_8), KEY(5, 3, KEY_7), | ||
| 723 | KEY(5, 4, KEY_6), KEY(5, 5, KEY_5), | ||
| 724 | KEY(5, 6, KEY_4), KEY(5, 7, KEY_3), | ||
| 725 | |||
| 726 | KEY(6, 0, KEY_2), KEY(6, 1, KEY_1), | ||
| 727 | KEY(6, 2, KEY_ENTER), KEY(6, 3, KEY_END), | ||
| 728 | KEY(6, 4, KEY_DOWN), KEY(6, 5, KEY_UP), | ||
| 729 | KEY(6, 6, KEY_MENU), KEY(6, 7, KEY_F1), | ||
| 730 | |||
| 731 | KEY(7, 0, KEY_LEFT), KEY(7, 1, KEY_RIGHT), | ||
| 732 | KEY(7, 2, KEY_BACK), KEY(7, 3, KEY_HOME), | ||
| 733 | KEY(7, 4, 0), KEY(7, 5, 0), | ||
| 734 | KEY(7, 6, 0), KEY(7, 7, 0), | ||
| 735 | }; | ||
| 736 | |||
| 737 | struct pxa27x_keypad_platform_data em_x270_exeda_keypad_info = { | ||
| 738 | /* code map for the matrix keys */ | ||
| 739 | .matrix_key_rows = 8, | ||
| 740 | .matrix_key_cols = 8, | ||
| 741 | .matrix_key_map = em_x270_exeda_matrix_keys, | ||
| 742 | .matrix_key_map_size = ARRAY_SIZE(em_x270_exeda_matrix_keys), | ||
| 496 | }; | 743 | }; |
| 497 | 744 | ||
| 498 | static void __init em_x270_init_keypad(void) | 745 | static void __init em_x270_init_keypad(void) |
| 499 | { | 746 | { |
| 500 | pxa_set_keypad_info(&em_x270_keypad_info); | 747 | if (machine_is_em_x270()) |
| 748 | pxa_set_keypad_info(&em_x270_module_keypad_info); | ||
| 749 | else | ||
| 750 | pxa_set_keypad_info(&em_x270_exeda_keypad_info); | ||
| 501 | } | 751 | } |
| 502 | #else | 752 | #else |
| 503 | static inline void em_x270_init_keypad(void) {} | 753 | static inline void em_x270_init_keypad(void) {} |
| @@ -535,19 +785,264 @@ static void __init em_x270_init_gpio_keys(void) | |||
| 535 | static inline void em_x270_init_gpio_keys(void) {} | 785 | static inline void em_x270_init_gpio_keys(void) {} |
| 536 | #endif | 786 | #endif |
| 537 | 787 | ||
| 538 | static void __init em_x270_init(void) | 788 | /* Quick Capture Interface and sensor setup */ |
| 789 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) | ||
| 790 | static struct regulator *em_x270_camera_ldo; | ||
| 791 | |||
| 792 | static int em_x270_sensor_init(struct device *dev) | ||
| 539 | { | 793 | { |
| 794 | int ret; | ||
| 795 | |||
| 796 | ret = gpio_request(GPIO93_CAM_RESET, "camera reset"); | ||
| 797 | if (ret) | ||
| 798 | return ret; | ||
| 799 | |||
| 800 | gpio_direction_output(GPIO93_CAM_RESET, 0); | ||
| 801 | |||
| 802 | em_x270_camera_ldo = regulator_get(NULL, "vcc cam"); | ||
| 803 | if (em_x270_camera_ldo == NULL) { | ||
| 804 | gpio_free(GPIO93_CAM_RESET); | ||
| 805 | return -ENODEV; | ||
| 806 | } | ||
| 807 | |||
| 808 | ret = regulator_enable(em_x270_camera_ldo); | ||
| 809 | if (ret) { | ||
| 810 | regulator_put(em_x270_camera_ldo); | ||
| 811 | gpio_free(GPIO93_CAM_RESET); | ||
| 812 | return ret; | ||
| 813 | } | ||
| 814 | |||
| 815 | gpio_set_value(GPIO93_CAM_RESET, 1); | ||
| 816 | |||
| 817 | return 0; | ||
| 818 | } | ||
| 819 | |||
| 820 | struct pxacamera_platform_data em_x270_camera_platform_data = { | ||
| 821 | .init = em_x270_sensor_init, | ||
| 822 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | | ||
| 823 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, | ||
| 824 | .mclk_10khz = 2600, | ||
| 825 | }; | ||
| 826 | |||
| 827 | static int em_x270_sensor_power(struct device *dev, int on) | ||
| 828 | { | ||
| 829 | int ret; | ||
| 830 | int is_on = regulator_is_enabled(em_x270_camera_ldo); | ||
| 831 | |||
| 832 | if (on == is_on) | ||
| 833 | return 0; | ||
| 834 | |||
| 835 | gpio_set_value(GPIO93_CAM_RESET, !on); | ||
| 836 | |||
| 837 | if (on) | ||
| 838 | ret = regulator_enable(em_x270_camera_ldo); | ||
| 839 | else | ||
| 840 | ret = regulator_disable(em_x270_camera_ldo); | ||
| 841 | |||
| 842 | if (ret) | ||
| 843 | return ret; | ||
| 844 | |||
| 845 | gpio_set_value(GPIO93_CAM_RESET, on); | ||
| 846 | |||
| 847 | return 0; | ||
| 848 | } | ||
| 849 | |||
| 850 | static struct soc_camera_link iclink = { | ||
| 851 | .bus_id = 0, | ||
| 852 | .power = em_x270_sensor_power, | ||
| 853 | }; | ||
| 854 | |||
| 855 | static struct i2c_board_info em_x270_i2c_cam_info[] = { | ||
| 856 | { | ||
| 857 | I2C_BOARD_INFO("mt9m111", 0x48), | ||
| 858 | .platform_data = &iclink, | ||
| 859 | }, | ||
| 860 | }; | ||
| 861 | |||
| 862 | static struct i2c_pxa_platform_data em_x270_i2c_info = { | ||
| 863 | .fast_mode = 1, | ||
| 864 | }; | ||
| 865 | |||
| 866 | static void __init em_x270_init_camera(void) | ||
| 867 | { | ||
| 868 | pxa_set_i2c_info(&em_x270_i2c_info); | ||
| 869 | i2c_register_board_info(0, ARRAY_AND_SIZE(em_x270_i2c_cam_info)); | ||
| 870 | pxa_set_camera_info(&em_x270_camera_platform_data); | ||
| 871 | } | ||
| 872 | #else | ||
| 873 | static inline void em_x270_init_camera(void) {} | ||
| 874 | #endif | ||
| 875 | |||
| 876 | /* DA9030 related initializations */ | ||
| 877 | #define REGULATOR_CONSUMER(_name, _dev, _supply) \ | ||
| 878 | static struct regulator_consumer_supply _name##_consumers[] = { \ | ||
| 879 | { \ | ||
| 880 | .dev = _dev, \ | ||
| 881 | .supply = _supply, \ | ||
| 882 | }, \ | ||
| 883 | } | ||
| 884 | |||
| 885 | REGULATOR_CONSUMER(ldo3, NULL, "vcc gps"); | ||
| 886 | REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); | ||
| 887 | REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); | ||
| 888 | REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); | ||
| 889 | REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); | ||
| 890 | |||
| 891 | #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ | ||
| 892 | static struct regulator_init_data _ldo##_data = { \ | ||
| 893 | .constraints = { \ | ||
| 894 | .min_uV = _min_uV, \ | ||
| 895 | .max_uV = _max_uV, \ | ||
| 896 | .state_mem = { \ | ||
| 897 | .enabled = 0, \ | ||
| 898 | }, \ | ||
| 899 | .valid_ops_mask = _ops_mask, \ | ||
| 900 | }, \ | ||
| 901 | .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ | ||
| 902 | .consumer_supplies = _ldo##_consumers, \ | ||
| 903 | }; | ||
| 904 | |||
| 905 | REGULATOR_INIT(ldo3, 3200000, 3200000, REGULATOR_CHANGE_STATUS); | ||
| 906 | REGULATOR_INIT(ldo5, 3000000, 3000000, REGULATOR_CHANGE_STATUS); | ||
| 907 | REGULATOR_INIT(ldo10, 2000000, 3200000, | ||
| 908 | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE); | ||
| 909 | REGULATOR_INIT(ldo12, 3000000, 3000000, REGULATOR_CHANGE_STATUS); | ||
| 910 | REGULATOR_INIT(ldo19, 3200000, 3200000, REGULATOR_CHANGE_STATUS); | ||
| 911 | |||
| 912 | struct led_info em_x270_led_info = { | ||
| 913 | .name = "em-x270:orange", | ||
| 914 | .default_trigger = "battery-charging-or-full", | ||
| 915 | }; | ||
| 916 | |||
| 917 | struct power_supply_info em_x270_psy_info = { | ||
| 918 | .name = "LP555597P6H-FPS", | ||
| 919 | .technology = POWER_SUPPLY_TECHNOLOGY_LIPO, | ||
| 920 | .voltage_max_design = 4200000, | ||
| 921 | .voltage_min_design = 3000000, | ||
| 922 | .use_for_apm = 1, | ||
| 923 | }; | ||
| 924 | |||
| 925 | static void em_x270_battery_low(void) | ||
| 926 | { | ||
| 927 | apm_queue_event(APM_LOW_BATTERY); | ||
| 928 | } | ||
| 929 | |||
| 930 | static void em_x270_battery_critical(void) | ||
| 931 | { | ||
| 932 | apm_queue_event(APM_CRITICAL_SUSPEND); | ||
| 933 | } | ||
| 934 | |||
| 935 | struct da9030_battery_info em_x270_batterty_info = { | ||
| 936 | .battery_info = &em_x270_psy_info, | ||
| 937 | |||
| 938 | .charge_milliamp = 1000, | ||
| 939 | .charge_millivolt = 4200, | ||
| 940 | |||
| 941 | .vbat_low = 3600, | ||
| 942 | .vbat_crit = 3400, | ||
| 943 | .vbat_charge_start = 4100, | ||
| 944 | .vbat_charge_stop = 4200, | ||
| 945 | .vbat_charge_restart = 4000, | ||
| 946 | |||
| 947 | .vcharge_min = 3200, | ||
| 948 | .vcharge_max = 5500, | ||
| 949 | |||
| 950 | .tbat_low = 197, | ||
| 951 | .tbat_high = 78, | ||
| 952 | .tbat_restart = 100, | ||
| 953 | |||
| 954 | .batmon_interval = 0, | ||
| 955 | |||
| 956 | .battery_low = em_x270_battery_low, | ||
| 957 | .battery_critical = em_x270_battery_critical, | ||
| 958 | }; | ||
| 959 | |||
| 960 | #define DA9030_SUBDEV(_name, _id, _pdata) \ | ||
| 961 | { \ | ||
| 962 | .name = "da903x-" #_name, \ | ||
| 963 | .id = DA9030_ID_##_id, \ | ||
| 964 | .platform_data = _pdata, \ | ||
| 965 | } | ||
| 966 | |||
| 967 | #define DA9030_LDO(num) DA9030_SUBDEV(regulator, LDO##num, &ldo##num##_data) | ||
| 968 | |||
| 969 | struct da903x_subdev_info em_x270_da9030_subdevs[] = { | ||
| 970 | DA9030_LDO(3), | ||
| 971 | DA9030_LDO(5), | ||
| 972 | DA9030_LDO(10), | ||
| 973 | DA9030_LDO(12), | ||
| 974 | DA9030_LDO(19), | ||
| 975 | |||
| 976 | DA9030_SUBDEV(led, LED_PC, &em_x270_led_info), | ||
| 977 | DA9030_SUBDEV(backlight, WLED, &em_x270_led_info), | ||
| 978 | DA9030_SUBDEV(battery, BAT, &em_x270_batterty_info), | ||
| 979 | }; | ||
| 980 | |||
| 981 | static struct da903x_platform_data em_x270_da9030_info = { | ||
| 982 | .num_subdevs = ARRAY_SIZE(em_x270_da9030_subdevs), | ||
| 983 | .subdevs = em_x270_da9030_subdevs, | ||
| 984 | }; | ||
| 985 | |||
| 986 | static struct i2c_board_info em_x270_i2c_pmic_info = { | ||
| 987 | I2C_BOARD_INFO("da9030", 0x49), | ||
| 988 | .irq = IRQ_GPIO(0), | ||
| 989 | .platform_data = &em_x270_da9030_info, | ||
| 990 | }; | ||
| 991 | |||
| 992 | static struct i2c_pxa_platform_data em_x270_pwr_i2c_info = { | ||
| 993 | .use_pio = 1, | ||
| 994 | }; | ||
| 995 | |||
| 996 | static void __init em_x270_init_da9030(void) | ||
| 997 | { | ||
| 998 | pxa27x_set_i2c_power_info(&em_x270_pwr_i2c_info); | ||
| 999 | i2c_register_board_info(1, &em_x270_i2c_pmic_info, 1); | ||
| 1000 | } | ||
| 1001 | |||
| 1002 | static void __init em_x270_module_init(void) | ||
| 1003 | { | ||
| 1004 | pr_info("%s\n", __func__); | ||
| 540 | pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config)); | 1005 | pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config)); |
| 541 | 1006 | ||
| 1007 | mmc_cd = GPIO13_MMC_CD; | ||
| 1008 | nand_rb = GPIO56_NAND_RB; | ||
| 1009 | dm9000_flags = DM9000_PLATF_32BITONLY; | ||
| 1010 | } | ||
| 1011 | |||
| 1012 | static void __init em_x270_exeda_init(void) | ||
| 1013 | { | ||
| 1014 | pr_info("%s\n", __func__); | ||
| 1015 | pxa2xx_mfp_config(ARRAY_AND_SIZE(exeda_pin_config)); | ||
| 1016 | |||
| 1017 | mmc_cd = GPIO114_MMC_CD; | ||
| 1018 | nand_rb = GPIO20_NAND_RB; | ||
| 1019 | dm9000_flags = DM9000_PLATF_16BITONLY; | ||
| 1020 | } | ||
| 1021 | |||
| 1022 | static void __init em_x270_init(void) | ||
| 1023 | { | ||
| 1024 | pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config)); | ||
| 1025 | |||
| 1026 | if (machine_is_em_x270()) | ||
| 1027 | em_x270_module_init(); | ||
| 1028 | else if (machine_is_exeda()) | ||
| 1029 | em_x270_exeda_init(); | ||
| 1030 | else | ||
| 1031 | panic("Unsupported machine: %d\n", machine_arch_type); | ||
| 1032 | |||
| 1033 | em_x270_init_da9030(); | ||
| 542 | em_x270_init_dm9000(); | 1034 | em_x270_init_dm9000(); |
| 543 | em_x270_init_rtc(); | 1035 | em_x270_init_rtc(); |
| 544 | em_x270_init_nand(); | 1036 | em_x270_init_nand(); |
| 1037 | em_x270_init_nor(); | ||
| 545 | em_x270_init_lcd(); | 1038 | em_x270_init_lcd(); |
| 546 | em_x270_init_mmc(); | 1039 | em_x270_init_mmc(); |
| 547 | em_x270_init_ohci(); | 1040 | em_x270_init_ohci(); |
| 548 | em_x270_init_keypad(); | 1041 | em_x270_init_keypad(); |
| 549 | em_x270_init_gpio_keys(); | 1042 | em_x270_init_gpio_keys(); |
| 550 | em_x270_init_ac97(); | 1043 | em_x270_init_ac97(); |
| 1044 | em_x270_init_camera(); | ||
| 1045 | em_x270_init_spi(); | ||
| 551 | } | 1046 | } |
| 552 | 1047 | ||
| 553 | MACHINE_START(EM_X270, "Compulab EM-X270") | 1048 | MACHINE_START(EM_X270, "Compulab EM-X270") |
| @@ -559,3 +1054,13 @@ MACHINE_START(EM_X270, "Compulab EM-X270") | |||
| 559 | .timer = &pxa_timer, | 1054 | .timer = &pxa_timer, |
| 560 | .init_machine = em_x270_init, | 1055 | .init_machine = em_x270_init, |
| 561 | MACHINE_END | 1056 | MACHINE_END |
| 1057 | |||
| 1058 | MACHINE_START(EXEDA, "Compulab eXeda") | ||
| 1059 | .boot_params = 0xa0000100, | ||
| 1060 | .phys_io = 0x40000000, | ||
| 1061 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 1062 | .map_io = pxa_map_io, | ||
| 1063 | .init_irq = pxa27x_init_irq, | ||
| 1064 | .timer = &pxa_timer, | ||
| 1065 | .init_machine = em_x270_init, | ||
| 1066 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index dfce7d5b659e..c60dadf847a6 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c | |||
| @@ -20,8 +20,7 @@ | |||
| 20 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 22 | 22 | ||
| 23 | #include <mach/mfp-pxa25x.h> | 23 | #include <mach/pxa25x.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/eseries-gpio.h> | 24 | #include <mach/eseries-gpio.h> |
| 26 | #include <mach/udc.h> | 25 | #include <mach/udc.h> |
| 27 | #include <mach/irda.h> | 26 | #include <mach/irda.h> |
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index df5f822f3b6c..92ba16e1b6fc 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c | |||
| @@ -19,18 +19,16 @@ | |||
| 19 | #include <linux/input.h> | 19 | #include <linux/input.h> |
| 20 | 20 | ||
| 21 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
| 22 | #include <asm/mach-types.h> | ||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | |||
| 25 | #include <mach/pxa27x.h> | ||
| 22 | #include <mach/pxafb.h> | 26 | #include <mach/pxafb.h> |
| 23 | #include <mach/ohci.h> | 27 | #include <mach/ohci.h> |
| 24 | #include <mach/i2c.h> | 28 | #include <mach/i2c.h> |
| 25 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 26 | #include <mach/pxa27x_keypad.h> | 30 | #include <mach/pxa27x_keypad.h> |
| 27 | 31 | ||
| 28 | #include <mach/mfp-pxa27x.h> | ||
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/pxa2xx-regs.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/mach/arch.h> | ||
| 33 | |||
| 34 | #include "devices.h" | 32 | #include "devices.h" |
| 35 | #include "generic.h" | 33 | #include "generic.h" |
| 36 | 34 | ||
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 0ccc91c92c44..3126a35aa002 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
| @@ -26,8 +26,9 @@ | |||
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 28 | 28 | ||
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/reset.h> | 29 | #include <mach/reset.h> |
| 30 | #include <mach/gpio.h> | ||
| 31 | #include <mach/pxa2xx-gpio.h> | ||
| 31 | 32 | ||
| 32 | #include "generic.h" | 33 | #include "generic.h" |
| 33 | 34 | ||
| @@ -127,3 +128,33 @@ void __init pxa_map_io(void) | |||
| 127 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | 128 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); |
| 128 | get_clk_frequency_khz(1); | 129 | get_clk_frequency_khz(1); |
| 129 | } | 130 | } |
| 131 | |||
| 132 | /* | ||
| 133 | * Configure pins for GPIO or other functions | ||
| 134 | */ | ||
| 135 | int pxa_gpio_mode(int gpio_mode) | ||
| 136 | { | ||
| 137 | unsigned long flags; | ||
| 138 | int gpio = gpio_mode & GPIO_MD_MASK_NR; | ||
| 139 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; | ||
| 140 | int gafr; | ||
| 141 | |||
| 142 | if (gpio > pxa_last_gpio) | ||
| 143 | return -EINVAL; | ||
| 144 | |||
| 145 | local_irq_save(flags); | ||
| 146 | if (gpio_mode & GPIO_DFLT_LOW) | ||
| 147 | GPCR(gpio) = GPIO_bit(gpio); | ||
| 148 | else if (gpio_mode & GPIO_DFLT_HIGH) | ||
| 149 | GPSR(gpio) = GPIO_bit(gpio); | ||
| 150 | if (gpio_mode & GPIO_MD_MASK_DIR) | ||
| 151 | GPDR(gpio) |= GPIO_bit(gpio); | ||
| 152 | else | ||
| 153 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
| 154 | gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); | ||
| 155 | GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); | ||
| 156 | local_irq_restore(flags); | ||
| 157 | |||
| 158 | return 0; | ||
| 159 | } | ||
| 160 | EXPORT_SYMBOL(pxa_gpio_mode); | ||
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index dc876a8e6668..3465268ca716 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
| @@ -9,20 +9,17 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | typedef int (*set_wake_t)(unsigned int, unsigned int); | ||
| 13 | |||
| 14 | struct sys_timer; | 12 | struct sys_timer; |
| 15 | 13 | ||
| 16 | extern struct sys_timer pxa_timer; | 14 | extern struct sys_timer pxa_timer; |
| 17 | extern void __init pxa_init_irq(int irq_nr, set_wake_t fn); | 15 | extern void __init pxa_init_irq(int irq_nr, |
| 18 | extern void __init pxa_init_gpio(int gpio_nr, set_wake_t fn); | 16 | int (*set_wake)(unsigned int, unsigned int)); |
| 19 | extern void __init pxa25x_init_irq(void); | 17 | extern void __init pxa25x_init_irq(void); |
| 20 | extern void __init pxa27x_init_irq(void); | 18 | extern void __init pxa27x_init_irq(void); |
| 21 | extern void __init pxa3xx_init_irq(void); | 19 | extern void __init pxa3xx_init_irq(void); |
| 22 | extern void __init pxa_map_io(void); | 20 | extern void __init pxa_map_io(void); |
| 23 | 21 | ||
| 24 | extern unsigned int get_clk_frequency_khz(int info); | 22 | extern unsigned int get_clk_frequency_khz(int info); |
| 25 | extern int pxa_last_gpio; | ||
| 26 | 23 | ||
| 27 | #define SET_BANK(__nr,__start,__size) \ | 24 | #define SET_BANK(__nr,__start,__size) \ |
| 28 | mi->bank[__nr].start = (__start), \ | 25 | mi->bank[__nr].start = (__start), \ |
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c deleted file mode 100644 index 5fec1e479cb3..000000000000 --- a/arch/arm/mach-pxa/gpio.c +++ /dev/null | |||
| @@ -1,453 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/gpio.c | ||
| 3 | * | ||
| 4 | * Generic PXA GPIO handling | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Created: Jun 15, 2001 | ||
| 8 | * Copyright: MontaVista Software Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/irq.h> | ||
| 18 | #include <linux/sysdev.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | |||
| 21 | #include <asm/gpio.h> | ||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/pxa2xx-gpio.h> | ||
| 25 | |||
| 26 | #include "generic.h" | ||
| 27 | |||
| 28 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) | ||
| 29 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | ||
| 30 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | ||
| 31 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | ||
| 32 | |||
| 33 | #define GPLR_OFFSET 0x00 | ||
| 34 | #define GPDR_OFFSET 0x0C | ||
| 35 | #define GPSR_OFFSET 0x18 | ||
| 36 | #define GPCR_OFFSET 0x24 | ||
| 37 | #define GRER_OFFSET 0x30 | ||
| 38 | #define GFER_OFFSET 0x3C | ||
| 39 | #define GEDR_OFFSET 0x48 | ||
| 40 | |||
| 41 | struct pxa_gpio_chip { | ||
| 42 | struct gpio_chip chip; | ||
| 43 | void __iomem *regbase; | ||
| 44 | }; | ||
| 45 | |||
| 46 | int pxa_last_gpio; | ||
| 47 | |||
| 48 | #ifdef CONFIG_CPU_PXA26x | ||
| 49 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, | ||
| 50 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | ||
| 51 | */ | ||
| 52 | static int __gpio_is_inverted(unsigned gpio) | ||
| 53 | { | ||
| 54 | return cpu_is_pxa25x() && gpio > 85; | ||
| 55 | } | ||
| 56 | #else | ||
| 57 | #define __gpio_is_inverted(gpio) (0) | ||
| 58 | #endif | ||
| 59 | |||
| 60 | /* | ||
| 61 | * Configure pins for GPIO or other functions | ||
| 62 | */ | ||
| 63 | int pxa_gpio_mode(int gpio_mode) | ||
| 64 | { | ||
| 65 | unsigned long flags; | ||
| 66 | int gpio = gpio_mode & GPIO_MD_MASK_NR; | ||
| 67 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; | ||
| 68 | int gafr; | ||
| 69 | |||
| 70 | if (gpio > pxa_last_gpio) | ||
| 71 | return -EINVAL; | ||
| 72 | |||
| 73 | local_irq_save(flags); | ||
| 74 | if (gpio_mode & GPIO_DFLT_LOW) | ||
| 75 | GPCR(gpio) = GPIO_bit(gpio); | ||
| 76 | else if (gpio_mode & GPIO_DFLT_HIGH) | ||
| 77 | GPSR(gpio) = GPIO_bit(gpio); | ||
| 78 | if (gpio_mode & GPIO_MD_MASK_DIR) | ||
| 79 | GPDR(gpio) |= GPIO_bit(gpio); | ||
| 80 | else | ||
| 81 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
| 82 | gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); | ||
| 83 | GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); | ||
| 84 | local_irq_restore(flags); | ||
| 85 | |||
| 86 | return 0; | ||
| 87 | } | ||
| 88 | EXPORT_SYMBOL(pxa_gpio_mode); | ||
| 89 | |||
| 90 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 91 | { | ||
| 92 | unsigned long flags; | ||
| 93 | u32 mask = 1 << offset; | ||
| 94 | u32 value; | ||
| 95 | struct pxa_gpio_chip *pxa; | ||
| 96 | void __iomem *gpdr; | ||
| 97 | |||
| 98 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 99 | gpdr = pxa->regbase + GPDR_OFFSET; | ||
| 100 | local_irq_save(flags); | ||
| 101 | value = __raw_readl(gpdr); | ||
| 102 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 103 | value |= mask; | ||
| 104 | else | ||
| 105 | value &= ~mask; | ||
| 106 | __raw_writel(value, gpdr); | ||
| 107 | local_irq_restore(flags); | ||
| 108 | |||
| 109 | return 0; | ||
| 110 | } | ||
| 111 | |||
| 112 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | ||
| 113 | unsigned offset, int value) | ||
| 114 | { | ||
| 115 | unsigned long flags; | ||
| 116 | u32 mask = 1 << offset; | ||
| 117 | u32 tmp; | ||
| 118 | struct pxa_gpio_chip *pxa; | ||
| 119 | void __iomem *gpdr; | ||
| 120 | |||
| 121 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 122 | __raw_writel(mask, | ||
| 123 | pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET)); | ||
| 124 | gpdr = pxa->regbase + GPDR_OFFSET; | ||
| 125 | local_irq_save(flags); | ||
| 126 | tmp = __raw_readl(gpdr); | ||
| 127 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 128 | tmp &= ~mask; | ||
| 129 | else | ||
| 130 | tmp |= mask; | ||
| 131 | __raw_writel(tmp, gpdr); | ||
| 132 | local_irq_restore(flags); | ||
| 133 | |||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | /* | ||
| 138 | * Return GPIO level | ||
| 139 | */ | ||
| 140 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 141 | { | ||
| 142 | u32 mask = 1 << offset; | ||
| 143 | struct pxa_gpio_chip *pxa; | ||
| 144 | |||
| 145 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 146 | return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask; | ||
| 147 | } | ||
| 148 | |||
| 149 | /* | ||
| 150 | * Set output GPIO level | ||
| 151 | */ | ||
| 152 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 153 | { | ||
| 154 | u32 mask = 1 << offset; | ||
| 155 | struct pxa_gpio_chip *pxa; | ||
| 156 | |||
| 157 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 158 | |||
| 159 | if (value) | ||
| 160 | __raw_writel(mask, pxa->regbase + GPSR_OFFSET); | ||
| 161 | else | ||
| 162 | __raw_writel(mask, pxa->regbase + GPCR_OFFSET); | ||
| 163 | } | ||
| 164 | |||
| 165 | #define GPIO_CHIP(_n) \ | ||
| 166 | [_n] = { \ | ||
| 167 | .regbase = GPIO##_n##_BASE, \ | ||
| 168 | .chip = { \ | ||
| 169 | .label = "gpio-" #_n, \ | ||
| 170 | .direction_input = pxa_gpio_direction_input, \ | ||
| 171 | .direction_output = pxa_gpio_direction_output, \ | ||
| 172 | .get = pxa_gpio_get, \ | ||
| 173 | .set = pxa_gpio_set, \ | ||
| 174 | .base = (_n) * 32, \ | ||
| 175 | .ngpio = 32, \ | ||
| 176 | }, \ | ||
| 177 | } | ||
| 178 | |||
| 179 | static struct pxa_gpio_chip pxa_gpio_chip[] = { | ||
| 180 | GPIO_CHIP(0), | ||
| 181 | GPIO_CHIP(1), | ||
| 182 | GPIO_CHIP(2), | ||
| 183 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 184 | GPIO_CHIP(3), | ||
| 185 | #endif | ||
| 186 | }; | ||
| 187 | |||
| 188 | /* | ||
| 189 | * PXA GPIO edge detection for IRQs: | ||
| 190 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | ||
| 191 | * Use this instead of directly setting GRER/GFER. | ||
| 192 | */ | ||
| 193 | |||
| 194 | static unsigned long GPIO_IRQ_rising_edge[4]; | ||
| 195 | static unsigned long GPIO_IRQ_falling_edge[4]; | ||
| 196 | static unsigned long GPIO_IRQ_mask[4]; | ||
| 197 | |||
| 198 | /* | ||
| 199 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | ||
| 200 | * function of a GPIO, and GPDRx cannot be altered once configured. It | ||
| 201 | * is attributed as "occupied" here (I know this terminology isn't | ||
| 202 | * accurate, you are welcome to propose a better one :-) | ||
| 203 | */ | ||
| 204 | static int __gpio_is_occupied(unsigned gpio) | ||
| 205 | { | ||
| 206 | if (cpu_is_pxa27x() || cpu_is_pxa25x()) { | ||
| 207 | int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; | ||
| 208 | int dir = GPDR(gpio) & GPIO_bit(gpio); | ||
| 209 | |||
| 210 | if (__gpio_is_inverted(gpio)) | ||
| 211 | return af != 1 || dir == 0; | ||
| 212 | else | ||
| 213 | return af != 0 || dir != 0; | ||
| 214 | } | ||
| 215 | |||
| 216 | return 0; | ||
| 217 | } | ||
| 218 | |||
| 219 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | ||
| 220 | { | ||
| 221 | int gpio, idx; | ||
| 222 | |||
| 223 | gpio = IRQ_TO_GPIO(irq); | ||
| 224 | idx = gpio >> 5; | ||
| 225 | |||
| 226 | if (type == IRQ_TYPE_PROBE) { | ||
| 227 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
| 228 | * GPIOs set to alternate function or to output during probe | ||
| 229 | */ | ||
| 230 | if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) || | ||
| 231 | (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio))) | ||
| 232 | return 0; | ||
| 233 | |||
| 234 | if (__gpio_is_occupied(gpio)) | ||
| 235 | return 0; | ||
| 236 | |||
| 237 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | ||
| 238 | } | ||
| 239 | |||
| 240 | if (__gpio_is_inverted(gpio)) | ||
| 241 | GPDR(gpio) |= GPIO_bit(gpio); | ||
| 242 | else | ||
| 243 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
| 244 | |||
| 245 | if (type & IRQ_TYPE_EDGE_RISING) | ||
| 246 | __set_bit(gpio, GPIO_IRQ_rising_edge); | ||
| 247 | else | ||
| 248 | __clear_bit(gpio, GPIO_IRQ_rising_edge); | ||
| 249 | |||
| 250 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
| 251 | __set_bit(gpio, GPIO_IRQ_falling_edge); | ||
| 252 | else | ||
| 253 | __clear_bit(gpio, GPIO_IRQ_falling_edge); | ||
| 254 | |||
| 255 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 256 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 257 | |||
| 258 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | ||
| 259 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | ||
| 260 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | ||
| 261 | return 0; | ||
| 262 | } | ||
| 263 | |||
| 264 | /* | ||
| 265 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. | ||
| 266 | */ | ||
| 267 | |||
| 268 | static void pxa_ack_low_gpio(unsigned int irq) | ||
| 269 | { | ||
| 270 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | ||
| 271 | } | ||
| 272 | |||
| 273 | static void pxa_mask_low_gpio(unsigned int irq) | ||
| 274 | { | ||
| 275 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | ||
| 276 | } | ||
| 277 | |||
| 278 | static void pxa_unmask_low_gpio(unsigned int irq) | ||
| 279 | { | ||
| 280 | ICMR |= 1 << (irq - PXA_IRQ(0)); | ||
| 281 | } | ||
| 282 | |||
| 283 | static struct irq_chip pxa_low_gpio_chip = { | ||
| 284 | .name = "GPIO-l", | ||
| 285 | .ack = pxa_ack_low_gpio, | ||
| 286 | .mask = pxa_mask_low_gpio, | ||
| 287 | .unmask = pxa_unmask_low_gpio, | ||
| 288 | .set_type = pxa_gpio_irq_type, | ||
| 289 | }; | ||
| 290 | |||
| 291 | /* | ||
| 292 | * Demux handler for GPIO>=2 edge detect interrupts | ||
| 293 | */ | ||
| 294 | |||
| 295 | #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) | ||
| 296 | |||
| 297 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | ||
| 298 | { | ||
| 299 | int loop, bit, n; | ||
| 300 | unsigned long gedr[4]; | ||
| 301 | |||
| 302 | do { | ||
| 303 | gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; | ||
| 304 | gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; | ||
| 305 | gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; | ||
| 306 | gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; | ||
| 307 | |||
| 308 | GEDR0 = gedr[0]; GEDR1 = gedr[1]; | ||
| 309 | GEDR2 = gedr[2]; GEDR3 = gedr[3]; | ||
| 310 | |||
| 311 | loop = 0; | ||
| 312 | bit = find_first_bit(gedr, GEDR_BITS); | ||
| 313 | while (bit < GEDR_BITS) { | ||
| 314 | loop = 1; | ||
| 315 | |||
| 316 | n = PXA_GPIO_IRQ_BASE + bit; | ||
| 317 | generic_handle_irq(n); | ||
| 318 | |||
| 319 | bit = find_next_bit(gedr, GEDR_BITS, bit + 1); | ||
| 320 | } | ||
| 321 | } while (loop); | ||
| 322 | } | ||
| 323 | |||
| 324 | static void pxa_ack_muxed_gpio(unsigned int irq) | ||
| 325 | { | ||
| 326 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 327 | GEDR(gpio) = GPIO_bit(gpio); | ||
| 328 | } | ||
| 329 | |||
| 330 | static void pxa_mask_muxed_gpio(unsigned int irq) | ||
| 331 | { | ||
| 332 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 333 | __clear_bit(gpio, GPIO_IRQ_mask); | ||
| 334 | GRER(gpio) &= ~GPIO_bit(gpio); | ||
| 335 | GFER(gpio) &= ~GPIO_bit(gpio); | ||
| 336 | } | ||
| 337 | |||
| 338 | static void pxa_unmask_muxed_gpio(unsigned int irq) | ||
| 339 | { | ||
| 340 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 341 | int idx = gpio >> 5; | ||
| 342 | __set_bit(gpio, GPIO_IRQ_mask); | ||
| 343 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 344 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 345 | } | ||
| 346 | |||
| 347 | static struct irq_chip pxa_muxed_gpio_chip = { | ||
| 348 | .name = "GPIO", | ||
| 349 | .ack = pxa_ack_muxed_gpio, | ||
| 350 | .mask = pxa_mask_muxed_gpio, | ||
| 351 | .unmask = pxa_unmask_muxed_gpio, | ||
| 352 | .set_type = pxa_gpio_irq_type, | ||
| 353 | }; | ||
| 354 | |||
| 355 | void __init pxa_init_gpio(int gpio_nr, set_wake_t fn) | ||
| 356 | { | ||
| 357 | int irq, i, gpio; | ||
| 358 | |||
| 359 | pxa_last_gpio = gpio_nr - 1; | ||
| 360 | |||
| 361 | /* clear all GPIO edge detects */ | ||
| 362 | for (i = 0; i < gpio_nr; i += 32) { | ||
| 363 | GFER(i) = 0; | ||
| 364 | GRER(i) = 0; | ||
| 365 | GEDR(i) = GEDR(i); | ||
| 366 | } | ||
| 367 | |||
| 368 | /* GPIO 0 and 1 must have their mask bit always set */ | ||
| 369 | GPIO_IRQ_mask[0] = 3; | ||
| 370 | |||
| 371 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | ||
| 372 | set_irq_chip(irq, &pxa_low_gpio_chip); | ||
| 373 | set_irq_handler(irq, handle_edge_irq); | ||
| 374 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 375 | } | ||
| 376 | |||
| 377 | for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { | ||
| 378 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | ||
| 379 | set_irq_handler(irq, handle_edge_irq); | ||
| 380 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 381 | } | ||
| 382 | |||
| 383 | /* Install handler for GPIO>=2 edge detect interrupts */ | ||
| 384 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | ||
| 385 | |||
| 386 | pxa_low_gpio_chip.set_wake = fn; | ||
| 387 | pxa_muxed_gpio_chip.set_wake = fn; | ||
| 388 | |||
| 389 | /* add a GPIO chip for each register bank. | ||
| 390 | * the last PXA25x register only contains 21 GPIOs | ||
| 391 | */ | ||
| 392 | for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { | ||
| 393 | if (gpio + 32 > gpio_nr) | ||
| 394 | pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; | ||
| 395 | gpiochip_add(&pxa_gpio_chip[i].chip); | ||
| 396 | } | ||
| 397 | } | ||
| 398 | |||
| 399 | #ifdef CONFIG_PM | ||
| 400 | |||
| 401 | static unsigned long saved_gplr[4]; | ||
| 402 | static unsigned long saved_gpdr[4]; | ||
| 403 | static unsigned long saved_grer[4]; | ||
| 404 | static unsigned long saved_gfer[4]; | ||
| 405 | |||
| 406 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) | ||
| 407 | { | ||
| 408 | int i, gpio; | ||
| 409 | |||
| 410 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 411 | saved_gplr[i] = GPLR(gpio); | ||
| 412 | saved_gpdr[i] = GPDR(gpio); | ||
| 413 | saved_grer[i] = GRER(gpio); | ||
| 414 | saved_gfer[i] = GFER(gpio); | ||
| 415 | |||
| 416 | /* Clear GPIO transition detect bits */ | ||
| 417 | GEDR(gpio) = GEDR(gpio); | ||
| 418 | } | ||
| 419 | return 0; | ||
| 420 | } | ||
| 421 | |||
| 422 | static int pxa_gpio_resume(struct sys_device *dev) | ||
| 423 | { | ||
| 424 | int i, gpio; | ||
| 425 | |||
| 426 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 427 | /* restore level with set/clear */ | ||
| 428 | GPSR(gpio) = saved_gplr[i]; | ||
| 429 | GPCR(gpio) = ~saved_gplr[i]; | ||
| 430 | |||
| 431 | GRER(gpio) = saved_grer[i]; | ||
| 432 | GFER(gpio) = saved_gfer[i]; | ||
| 433 | GPDR(gpio) = saved_gpdr[i]; | ||
| 434 | } | ||
| 435 | return 0; | ||
| 436 | } | ||
| 437 | #else | ||
| 438 | #define pxa_gpio_suspend NULL | ||
| 439 | #define pxa_gpio_resume NULL | ||
| 440 | #endif | ||
| 441 | |||
| 442 | struct sysdev_class pxa_gpio_sysclass = { | ||
| 443 | .name = "gpio", | ||
| 444 | .suspend = pxa_gpio_suspend, | ||
| 445 | .resume = pxa_gpio_resume, | ||
| 446 | }; | ||
| 447 | |||
| 448 | static int __init pxa_gpio_init(void) | ||
| 449 | { | ||
| 450 | return sysdev_class_register(&pxa_gpio_sysclass); | ||
| 451 | } | ||
| 452 | |||
| 453 | core_initcall(pxa_gpio_init); | ||
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index e296ce11658c..ca9912ea78d9 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c | |||
| @@ -38,14 +38,12 @@ | |||
| 38 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 39 | #include <asm/mach/irq.h> | 39 | #include <asm/mach/irq.h> |
| 40 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 41 | |||
| 42 | #include <mach/pxa25x.h> | ||
| 41 | #include <mach/mmc.h> | 43 | #include <mach/mmc.h> |
| 42 | #include <mach/udc.h> | 44 | #include <mach/udc.h> |
| 43 | #include <mach/gumstix.h> | 45 | #include <mach/gumstix.h> |
| 44 | 46 | ||
| 45 | #include <mach/pxa-regs.h> | ||
| 46 | #include <mach/pxa2xx-regs.h> | ||
| 47 | #include <mach/mfp-pxa25x.h> | ||
| 48 | |||
| 49 | #include "generic.h" | 47 | #include "generic.h" |
| 50 | 48 | ||
| 51 | static struct resource flash_resource = { | 49 | static struct resource flash_resource = { |
| @@ -191,6 +189,11 @@ int __attribute__((weak)) am200_init(void) | |||
| 191 | return 0; | 189 | return 0; |
| 192 | } | 190 | } |
| 193 | 191 | ||
| 192 | int __attribute__((weak)) am300_init(void) | ||
| 193 | { | ||
| 194 | return 0; | ||
| 195 | } | ||
| 196 | |||
| 194 | static void __init carrier_board_init(void) | 197 | static void __init carrier_board_init(void) |
| 195 | { | 198 | { |
| 196 | /* | 199 | /* |
| @@ -198,6 +201,7 @@ static void __init carrier_board_init(void) | |||
| 198 | * they cannot be detected programatically | 201 | * they cannot be detected programatically |
| 199 | */ | 202 | */ |
| 200 | am200_init(); | 203 | am200_init(); |
| 204 | am300_init(); | ||
| 201 | } | 205 | } |
| 202 | 206 | ||
| 203 | static void __init gumstix_init(void) | 207 | static void __init gumstix_init(void) |
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index 295ec413d804..f3d220c32e07 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c | |||
| @@ -24,14 +24,15 @@ | |||
| 24 | #include <linux/mtd/mtd.h> | 24 | #include <linux/mtd/mtd.h> |
| 25 | #include <linux/mtd/partitions.h> | 25 | #include <linux/mtd/partitions.h> |
| 26 | #include <linux/mtd/physmap.h> | 26 | #include <linux/mtd/physmap.h> |
| 27 | |||
| 27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| 31 | |||
| 32 | #include <mach/pxa25x.h> | ||
| 30 | #include <mach/h5000.h> | 33 | #include <mach/h5000.h> |
| 31 | #include <mach/pxa-regs.h> | ||
| 32 | #include <mach/pxa2xx-regs.h> | ||
| 33 | #include <mach/mfp-pxa25x.h> | ||
| 34 | #include <mach/udc.h> | 34 | #include <mach/udc.h> |
| 35 | |||
| 35 | #include "generic.h" | 36 | #include "generic.h" |
| 36 | 37 | ||
| 37 | /* | 38 | /* |
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c new file mode 100644 index 000000000000..cea99fe65b97 --- /dev/null +++ b/arch/arm/mach-pxa/himalaya.c | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/himalaya.c | ||
| 3 | * | ||
| 4 | * Hardware definitions for the HTC Himalaya | ||
| 5 | * | ||
| 6 | * Based on 2.6.21-hh20's himalaya.c and himalaya_lcd.c | ||
| 7 | * | ||
| 8 | * Copyright (c) 2008 Zbynek Michl <Zbynek.Michl@seznam.cz> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/device.h> | ||
| 18 | #include <linux/fb.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | |||
| 21 | #include <video/w100fb.h> | ||
| 22 | |||
| 23 | #include <asm/setup.h> | ||
| 24 | #include <asm/mach-types.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | |||
| 27 | #include <mach/mfp-pxa25x.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | |||
| 30 | #include "generic.h" | ||
| 31 | |||
| 32 | /* ---------------------- Himalaya LCD definitions -------------------- */ | ||
| 33 | |||
| 34 | static struct w100_gen_regs himalaya_lcd_regs = { | ||
| 35 | .lcd_format = 0x00000003, | ||
| 36 | .lcdd_cntl1 = 0x00000000, | ||
| 37 | .lcdd_cntl2 = 0x0003ffff, | ||
| 38 | .genlcd_cntl1 = 0x00fff003, | ||
| 39 | .genlcd_cntl2 = 0x00000003, | ||
| 40 | .genlcd_cntl3 = 0x000102aa, | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct w100_mode himalaya4_lcd_mode = { | ||
| 44 | .xres = 240, | ||
| 45 | .yres = 320, | ||
| 46 | .left_margin = 0, | ||
| 47 | .right_margin = 31, | ||
| 48 | .upper_margin = 15, | ||
| 49 | .lower_margin = 0, | ||
| 50 | .crtc_ss = 0x80150014, | ||
| 51 | .crtc_ls = 0xa0fb00f7, | ||
| 52 | .crtc_gs = 0xc0080007, | ||
| 53 | .crtc_vpos_gs = 0x00080007, | ||
| 54 | .crtc_rev = 0x0000000a, | ||
| 55 | .crtc_dclk = 0x81700030, | ||
| 56 | .crtc_gclk = 0x8015010f, | ||
| 57 | .crtc_goe = 0x00000000, | ||
| 58 | .pll_freq = 80, | ||
| 59 | .pixclk_divider = 15, | ||
| 60 | .pixclk_divider_rotated = 15, | ||
| 61 | .pixclk_src = CLK_SRC_PLL, | ||
| 62 | .sysclk_divider = 0, | ||
| 63 | .sysclk_src = CLK_SRC_PLL, | ||
| 64 | }; | ||
| 65 | |||
| 66 | static struct w100_mode himalaya6_lcd_mode = { | ||
| 67 | .xres = 240, | ||
| 68 | .yres = 320, | ||
| 69 | .left_margin = 9, | ||
| 70 | .right_margin = 8, | ||
| 71 | .upper_margin = 5, | ||
| 72 | .lower_margin = 4, | ||
| 73 | .crtc_ss = 0x80150014, | ||
| 74 | .crtc_ls = 0xa0fb00f7, | ||
| 75 | .crtc_gs = 0xc0080007, | ||
| 76 | .crtc_vpos_gs = 0x00080007, | ||
| 77 | .crtc_rev = 0x0000000a, | ||
| 78 | .crtc_dclk = 0xa1700030, | ||
| 79 | .crtc_gclk = 0x8015010f, | ||
| 80 | .crtc_goe = 0x00000000, | ||
| 81 | .pll_freq = 95, | ||
| 82 | .pixclk_divider = 0xb, | ||
| 83 | .pixclk_divider_rotated = 4, | ||
| 84 | .pixclk_src = CLK_SRC_PLL, | ||
| 85 | .sysclk_divider = 1, | ||
| 86 | .sysclk_src = CLK_SRC_PLL, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct w100_gpio_regs himalaya_w100_gpio_info = { | ||
| 90 | .init_data1 = 0xffff0000, /* GPIO_DATA */ | ||
| 91 | .gpio_dir1 = 0x00000000, /* GPIO_CNTL1 */ | ||
| 92 | .gpio_oe1 = 0x003c0000, /* GPIO_CNTL2 */ | ||
| 93 | .init_data2 = 0x00000000, /* GPIO_DATA2 */ | ||
| 94 | .gpio_dir2 = 0x00000000, /* GPIO_CNTL3 */ | ||
| 95 | .gpio_oe2 = 0x00000000, /* GPIO_CNTL4 */ | ||
| 96 | }; | ||
| 97 | |||
| 98 | static struct w100fb_mach_info himalaya_fb_info = { | ||
| 99 | .num_modes = 1, | ||
| 100 | .regs = &himalaya_lcd_regs, | ||
| 101 | .gpio = &himalaya_w100_gpio_info, | ||
| 102 | .xtal_freq = 16000000, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct resource himalaya_fb_resources[] = { | ||
| 106 | [0] = { | ||
| 107 | .start = 0x08000000, | ||
| 108 | .end = 0x08ffffff, | ||
| 109 | .flags = IORESOURCE_MEM, | ||
| 110 | }, | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct platform_device himalaya_fb_device = { | ||
| 114 | .name = "w100fb", | ||
| 115 | .id = -1, | ||
| 116 | .dev = { | ||
| 117 | .platform_data = &himalaya_fb_info, | ||
| 118 | }, | ||
| 119 | .num_resources = ARRAY_SIZE(himalaya_fb_resources), | ||
| 120 | .resource = himalaya_fb_resources, | ||
| 121 | }; | ||
| 122 | |||
| 123 | /* ----------------------------------------------------------------------- */ | ||
| 124 | |||
| 125 | static struct platform_device *devices[] __initdata = { | ||
| 126 | &himalaya_fb_device, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static void __init himalaya_lcd_init(void) | ||
| 130 | { | ||
| 131 | int himalaya_boardid; | ||
| 132 | |||
| 133 | himalaya_boardid = 0x4; /* hardcoded (detection needs ASIC3 functions) */ | ||
| 134 | printk(KERN_INFO "himalaya LCD Driver init. boardid=%d\n", | ||
| 135 | himalaya_boardid); | ||
| 136 | |||
| 137 | switch (himalaya_boardid) { | ||
| 138 | case 0x4: | ||
| 139 | himalaya_fb_info.modelist = &himalaya4_lcd_mode; | ||
| 140 | break; | ||
| 141 | case 0x6: | ||
| 142 | himalaya_fb_info.modelist = &himalaya6_lcd_mode; | ||
| 143 | break; | ||
| 144 | default: | ||
| 145 | printk(KERN_INFO "himalaya lcd_init: unknown boardid=%d. Using 0x4\n", | ||
| 146 | himalaya_boardid); | ||
| 147 | himalaya_fb_info.modelist = &himalaya4_lcd_mode; | ||
| 148 | } | ||
| 149 | } | ||
| 150 | |||
| 151 | static void __init himalaya_init(void) | ||
| 152 | { | ||
| 153 | himalaya_lcd_init(); | ||
| 154 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 155 | } | ||
| 156 | |||
| 157 | |||
| 158 | MACHINE_START(HIMALAYA, "HTC Himalaya") | ||
| 159 | .phys_io = 0x40000000, | ||
| 160 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 161 | .boot_params = 0xa0000100, | ||
| 162 | .map_io = pxa_map_io, | ||
| 163 | .init_irq = pxa25x_init_irq, | ||
| 164 | .init_machine = himalaya_init, | ||
| 165 | .timer = &pxa_timer, | ||
| 166 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 013b15baa034..b6243b59d9be 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c | |||
| @@ -31,8 +31,7 @@ | |||
| 31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 32 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
| 33 | 33 | ||
| 34 | #include <mach/pxa-regs.h> | 34 | #include <mach/pxa25x.h> |
| 35 | #include <mach/mfp-pxa25x.h> | ||
| 36 | #include <mach/idp.h> | 35 | #include <mach/idp.h> |
| 37 | #include <mach/pxafb.h> | 36 | #include <mach/pxafb.h> |
| 38 | #include <mach/bitfield.h> | 37 | #include <mach/bitfield.h> |
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c index 364c5e271330..2121309b2474 100644 --- a/arch/arm/mach-pxa/imote2.c +++ b/arch/arm/mach-pxa/imote2.c | |||
| @@ -28,11 +28,8 @@ | |||
| 28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
| 30 | 30 | ||
| 31 | #include <mach/pxa27x.h> | ||
| 31 | #include <mach/i2c.h> | 32 | #include <mach/i2c.h> |
| 32 | #include <mach/pxa-regs.h> | ||
| 33 | #include <mach/pxa2xx-regs.h> | ||
| 34 | #include <mach/mfp-pxa27x.h> | ||
| 35 | #include <mach/regs-ssp.h> | ||
| 36 | #include <mach/udc.h> | 33 | #include <mach/udc.h> |
| 37 | #include <mach/mmc.h> | 34 | #include <mach/mmc.h> |
| 38 | #include <mach/pxa2xx_spi.h> | 35 | #include <mach/pxa2xx_spi.h> |
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h index 2ae373fb5675..3f2a01d6a03c 100644 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ b/arch/arm/mach-pxa/include/mach/colibri.h | |||
| @@ -1,19 +1,31 @@ | |||
| 1 | #ifndef _COLIBRI_H_ | 1 | #ifndef _COLIBRI_H_ |
| 2 | #define _COLIBRI_H_ | 2 | #define _COLIBRI_H_ |
| 3 | /* | ||
| 4 | * common settings for all modules | ||
| 5 | */ | ||
| 6 | |||
| 7 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | ||
| 8 | extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin); | ||
| 9 | #else | ||
| 10 | static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *, int, int) {} | ||
| 11 | #endif | ||
| 12 | |||
| 13 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 14 | extern void colibri_pxa3xx_init_lcd(int bl_pin); | ||
| 15 | #else | ||
| 16 | static inline void colibri_pxa3xx_init_lcd(int) {} | ||
| 17 | #endif | ||
| 3 | 18 | ||
| 4 | /* physical memory regions */ | 19 | /* physical memory regions */ |
| 5 | #define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ | ||
| 6 | #define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ | ||
| 7 | #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ | 20 | #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ |
| 8 | 21 | ||
| 9 | /* virtual memory regions */ | 22 | /* definitions for Colibri PXA270 */ |
| 10 | #define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */ | ||
| 11 | 23 | ||
| 12 | /* size of flash */ | 24 | #define COLIBRI_PXA270_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ |
| 13 | #define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ | 25 | #define COLIBRI_PXA270_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet */ |
| 14 | 26 | #define COLIBRI_PXA270_ETH_IRQ_GPIO 114 | |
| 15 | /* Ethernet Controller Davicom DM9000 */ | 27 | #define COLIBRI_PXA270_ETH_IRQ \ |
| 16 | #define GPIO_DM9000 114 | 28 | gpio_to_irq(mfp_to_gpio(COLIBRI_PXA270_ETH_IRQ_GPIO)) |
| 17 | #define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000) | ||
| 18 | 29 | ||
| 19 | #endif /* _COLIBRI_H_ */ | 30 | #endif /* _COLIBRI_H_ */ |
| 31 | |||
diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h new file mode 100644 index 000000000000..747ab1a71f2f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/csb726.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Support for Cogent CSB726 | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Dmitry Baryshkov | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #ifndef CSB726_H | ||
| 12 | #define CSB726_H | ||
| 13 | |||
| 14 | #define CSB726_GPIO_IRQ_LAN 52 | ||
| 15 | #define CSB726_GPIO_IRQ_SM501 53 | ||
| 16 | #define CSB726_GPIO_MMC_DETECT 100 | ||
| 17 | #define CSB726_GPIO_MMC_RO 101 | ||
| 18 | |||
| 19 | #define CSB726_FLASH_SIZE (64 * 1024 * 1024) | ||
| 20 | #define CSB726_FLASH_uMON (8 * 1024 * 1024) | ||
| 21 | |||
| 22 | #define CSB726_IRQ_LAN gpio_to_irq(CSB726_GPIO_IRQ_LAN) | ||
| 23 | #define CSB726_IRQ_SM501 gpio_to_irq(CSB726_GPIO_IRQ_SM501) | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h index 7804637a6df3..5bd55894a48d 100644 --- a/arch/arm/mach-pxa/include/mach/dma.h +++ b/arch/arm/mach-pxa/include/mach/dma.h | |||
| @@ -12,35 +12,10 @@ | |||
| 12 | #ifndef __ASM_ARCH_DMA_H | 12 | #ifndef __ASM_ARCH_DMA_H |
| 13 | #define __ASM_ARCH_DMA_H | 13 | #define __ASM_ARCH_DMA_H |
| 14 | 14 | ||
| 15 | /* | 15 | #include <mach/hardware.h> |
| 16 | * Descriptor structure for PXA's DMA engine | ||
| 17 | * Note: this structure must always be aligned to a 16-byte boundary. | ||
| 18 | */ | ||
| 19 | |||
| 20 | typedef struct pxa_dma_desc { | ||
| 21 | volatile u32 ddadr; /* Points to the next descriptor + flags */ | ||
| 22 | volatile u32 dsadr; /* DSADR value for the current transfer */ | ||
| 23 | volatile u32 dtadr; /* DTADR value for the current transfer */ | ||
| 24 | volatile u32 dcmd; /* DCMD value for the current transfer */ | ||
| 25 | } pxa_dma_desc; | ||
| 26 | |||
| 27 | typedef enum { | ||
| 28 | DMA_PRIO_HIGH = 0, | ||
| 29 | DMA_PRIO_MEDIUM = 1, | ||
| 30 | DMA_PRIO_LOW = 2 | ||
| 31 | } pxa_dma_prio; | ||
| 32 | |||
| 33 | /* | ||
| 34 | * DMA registration | ||
| 35 | */ | ||
| 36 | |||
| 37 | int __init pxa_init_dma(int num_ch); | ||
| 38 | |||
| 39 | int pxa_request_dma (char *name, | ||
| 40 | pxa_dma_prio prio, | ||
| 41 | void (*irq_handler)(int, void *), | ||
| 42 | void *data); | ||
| 43 | 16 | ||
| 44 | void pxa_free_dma (int dma_ch); | 17 | /* DMA Controller Registers Definitions */ |
| 18 | #define DMAC_REGS_VIRT io_p2v(0x40000000) | ||
| 45 | 19 | ||
| 20 | #include <plat/dma.h> | ||
| 46 | #endif /* _ASM_ARCH_DMA_H */ | 21 | #endif /* _ASM_ARCH_DMA_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h index 2c538d8c362d..b024a8b37439 100644 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ b/arch/arm/mach-pxa/include/mach/gpio.h | |||
| @@ -24,42 +24,118 @@ | |||
| 24 | #ifndef __ASM_ARCH_PXA_GPIO_H | 24 | #ifndef __ASM_ARCH_PXA_GPIO_H |
| 25 | #define __ASM_ARCH_PXA_GPIO_H | 25 | #define __ASM_ARCH_PXA_GPIO_H |
| 26 | 26 | ||
| 27 | #include <mach/pxa-regs.h> | 27 | #include <mach/irqs.h> |
| 28 | #include <asm/irq.h> | ||
| 29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 30 | |||
| 31 | #include <asm-generic/gpio.h> | 29 | #include <asm-generic/gpio.h> |
| 32 | 30 | ||
| 31 | #define GPIO_REGS_VIRT io_p2v(0x40E00000) | ||
| 32 | |||
| 33 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | ||
| 34 | #define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) | ||
| 35 | |||
| 36 | /* GPIO Pin Level Registers */ | ||
| 37 | #define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) | ||
| 38 | #define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) | ||
| 39 | #define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) | ||
| 40 | #define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) | ||
| 41 | |||
| 42 | /* GPIO Pin Direction Registers */ | ||
| 43 | #define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) | ||
| 44 | #define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) | ||
| 45 | #define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) | ||
| 46 | #define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) | ||
| 47 | |||
| 48 | /* GPIO Pin Output Set Registers */ | ||
| 49 | #define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) | ||
| 50 | #define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) | ||
| 51 | #define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) | ||
| 52 | #define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) | ||
| 53 | |||
| 54 | /* GPIO Pin Output Clear Registers */ | ||
| 55 | #define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) | ||
| 56 | #define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) | ||
| 57 | #define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) | ||
| 58 | #define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) | ||
| 59 | |||
| 60 | /* GPIO Rising Edge Detect Registers */ | ||
| 61 | #define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) | ||
| 62 | #define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) | ||
| 63 | #define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) | ||
| 64 | #define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) | ||
| 65 | |||
| 66 | /* GPIO Falling Edge Detect Registers */ | ||
| 67 | #define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) | ||
| 68 | #define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) | ||
| 69 | #define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) | ||
| 70 | #define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) | ||
| 71 | |||
| 72 | /* GPIO Edge Detect Status Registers */ | ||
| 73 | #define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) | ||
| 74 | #define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) | ||
| 75 | #define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) | ||
| 76 | #define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) | ||
| 77 | |||
| 78 | /* GPIO Alternate Function Select Registers */ | ||
| 79 | #define GAFR0_L GPIO_REG(0x0054) | ||
| 80 | #define GAFR0_U GPIO_REG(0x0058) | ||
| 81 | #define GAFR1_L GPIO_REG(0x005C) | ||
| 82 | #define GAFR1_U GPIO_REG(0x0060) | ||
| 83 | #define GAFR2_L GPIO_REG(0x0064) | ||
| 84 | #define GAFR2_U GPIO_REG(0x0068) | ||
| 85 | #define GAFR3_L GPIO_REG(0x006C) | ||
| 86 | #define GAFR3_U GPIO_REG(0x0070) | ||
| 87 | |||
| 88 | /* More handy macros. The argument is a literal GPIO number. */ | ||
| 89 | |||
| 90 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | ||
| 91 | |||
| 92 | #define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) | ||
| 93 | #define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) | ||
| 94 | #define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) | ||
| 95 | #define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) | ||
| 96 | #define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) | ||
| 97 | #define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) | ||
| 98 | #define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) | ||
| 99 | #define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) | ||
| 100 | |||
| 33 | 101 | ||
| 34 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). | ||
| 35 | * Those cases currently cause holes in the GPIO number space. | ||
| 36 | */ | ||
| 37 | #define NR_BUILTIN_GPIO 128 | 102 | #define NR_BUILTIN_GPIO 128 |
| 38 | 103 | ||
| 39 | static inline int gpio_get_value(unsigned gpio) | 104 | #define gpio_to_bank(gpio) ((gpio) >> 5) |
| 105 | #define gpio_to_irq(gpio) IRQ_GPIO(gpio) | ||
| 106 | #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) | ||
| 107 | |||
| 108 | #ifdef CONFIG_CPU_PXA26x | ||
| 109 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, | ||
| 110 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | ||
| 111 | */ | ||
| 112 | static inline int __gpio_is_inverted(unsigned gpio) | ||
| 40 | { | 113 | { |
| 41 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) | 114 | return cpu_is_pxa25x() && gpio > 85; |
| 42 | return GPLR(gpio) & GPIO_bit(gpio); | ||
| 43 | else | ||
| 44 | return __gpio_get_value(gpio); | ||
| 45 | } | 115 | } |
| 116 | #else | ||
| 117 | static inline int __gpio_is_inverted(unsigned gpio) { return 0; } | ||
| 118 | #endif | ||
| 46 | 119 | ||
| 47 | static inline void gpio_set_value(unsigned gpio, int value) | 120 | /* |
| 121 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | ||
| 122 | * function of a GPIO, and GPDRx cannot be altered once configured. It | ||
| 123 | * is attributed as "occupied" here (I know this terminology isn't | ||
| 124 | * accurate, you are welcome to propose a better one :-) | ||
| 125 | */ | ||
| 126 | static inline int __gpio_is_occupied(unsigned gpio) | ||
| 48 | { | 127 | { |
| 49 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { | 128 | if (cpu_is_pxa27x() || cpu_is_pxa25x()) { |
| 50 | if (value) | 129 | int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; |
| 51 | GPSR(gpio) = GPIO_bit(gpio); | 130 | int dir = GPDR(gpio) & GPIO_bit(gpio); |
| 131 | |||
| 132 | if (__gpio_is_inverted(gpio)) | ||
| 133 | return af != 1 || dir == 0; | ||
| 52 | else | 134 | else |
| 53 | GPCR(gpio) = GPIO_bit(gpio); | 135 | return af != 0 || dir != 0; |
| 54 | } else { | 136 | } else |
| 55 | __gpio_set_value(gpio, value); | 137 | return GPDR(gpio) & GPIO_bit(gpio); |
| 56 | } | ||
| 57 | } | 138 | } |
| 58 | 139 | ||
| 59 | #define gpio_cansleep __gpio_cansleep | 140 | #include <plat/gpio.h> |
| 60 | |||
| 61 | #define gpio_to_irq(gpio) IRQ_GPIO(gpio) | ||
| 62 | #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) | ||
| 63 | |||
| 64 | |||
| 65 | #endif | 141 | #endif |
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 099f54a41de4..06abd4160607 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h | |||
| @@ -97,4 +97,5 @@ has detected a cable insertion; driven low otherwise. */ | |||
| 97 | 97 | ||
| 98 | /* for expansion boards that can't be programatically detected */ | 98 | /* for expansion boards that can't be programatically detected */ |
| 99 | extern int am200_init(void); | 99 | extern int am200_init(void); |
| 100 | extern int am300_init(void); | ||
| 100 | 101 | ||
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h index 4cb24154a5a8..751b74811d0f 100644 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ b/arch/arm/mach-pxa/include/mach/lubbock.h | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | 25 | ||
| 26 | /* FPGA register virtual addresses */ | 26 | /* FPGA register virtual addresses */ |
| 27 | #define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) | 27 | #define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) |
| 28 | #define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010) | ||
| 29 | #define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) | 28 | #define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) |
| 30 | #define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) | 29 | #define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) |
| 31 | #define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) | 30 | #define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) |
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h index 38d68d99f585..82a399f3f9f2 100644 --- a/arch/arm/mach-pxa/include/mach/magician.h +++ b/arch/arm/mach-pxa/include/mach/magician.h | |||
| @@ -69,7 +69,7 @@ | |||
| 69 | #define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) | 69 | #define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) |
| 70 | #define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) | 70 | #define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) |
| 71 | #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) | 71 | #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) |
| 72 | #define IRQ_MAGICIAN_AC (IRQ_BOARD_START + 3) | 72 | #define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3) |
| 73 | 73 | ||
| 74 | /* | 74 | /* |
| 75 | * CPLD EGPIOs | 75 | * CPLD EGPIOs |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index a72869b73ee3..b13dc0269a6d 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h | |||
| @@ -1,7 +1,6 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA25X_H | 1 | #ifndef __ASM_ARCH_MFP_PXA25X_H |
| 2 | #define __ASM_ARCH_MFP_PXA25X_H | 2 | #define __ASM_ARCH_MFP_PXA25X_H |
| 3 | 3 | ||
| 4 | #include <mach/mfp.h> | ||
| 5 | #include <mach/mfp-pxa2xx.h> | 4 | #include <mach/mfp-pxa2xx.h> |
| 6 | 5 | ||
| 7 | /* GPIO */ | 6 | /* GPIO */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index da4f85a4f990..6543c05f47ed 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h | |||
| @@ -8,7 +8,6 @@ | |||
| 8 | * specific controller, and this should work in most cases. | 8 | * specific controller, and this should work in most cases. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <mach/mfp.h> | ||
| 12 | #include <mach/mfp-pxa2xx.h> | 11 | #include <mach/mfp-pxa2xx.h> |
| 13 | 12 | ||
| 14 | /* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN | 13 | /* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h index 3e9211591e20..658b28ed129b 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA2XX_H | 1 | #ifndef __ASM_ARCH_MFP_PXA2XX_H |
| 2 | #define __ASM_ARCH_MFP_PXA2XX_H | 2 | #define __ASM_ARCH_MFP_PXA2XX_H |
| 3 | 3 | ||
| 4 | #include <mach/mfp.h> | 4 | #include <plat/mfp.h> |
| 5 | 5 | ||
| 6 | /* | 6 | /* |
| 7 | * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: | 7 | * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h index bc1fb33a6e70..ae8441192ef0 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #ifndef __ASM_ARCH_MFP_PXA300_H | 15 | #ifndef __ASM_ARCH_MFP_PXA300_H |
| 16 | #define __ASM_ARCH_MFP_PXA300_H | 16 | #define __ASM_ARCH_MFP_PXA300_H |
| 17 | 17 | ||
| 18 | #include <mach/mfp.h> | ||
| 19 | #include <mach/mfp-pxa3xx.h> | 18 | #include <mach/mfp-pxa3xx.h> |
| 20 | 19 | ||
| 21 | /* GPIO */ | 20 | /* GPIO */ |
| @@ -41,6 +40,7 @@ | |||
| 41 | #endif | 40 | #endif |
| 42 | 41 | ||
| 43 | /* Chip Select */ | 42 | /* Chip Select */ |
| 43 | #define GPIO1_nCS2 MFP_CFG(GPIO1, AF1) | ||
| 44 | #define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) | 44 | #define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) |
| 45 | 45 | ||
| 46 | /* AC97 */ | 46 | /* AC97 */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h index 67f8385ea548..07897e61d05a 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #ifndef __ASM_ARCH_MFP_PXA320_H | 15 | #ifndef __ASM_ARCH_MFP_PXA320_H |
| 16 | #define __ASM_ARCH_MFP_PXA320_H | 16 | #define __ASM_ARCH_MFP_PXA320_H |
| 17 | 17 | ||
| 18 | #include <mach/mfp.h> | ||
| 19 | #include <mach/mfp-pxa3xx.h> | 18 | #include <mach/mfp-pxa3xx.h> |
| 20 | 19 | ||
| 21 | /* GPIO */ | 20 | /* GPIO */ |
| @@ -38,6 +37,7 @@ | |||
| 38 | #define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) | 37 | #define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) |
| 39 | 38 | ||
| 40 | /* Chip Select */ | 39 | /* Chip Select */ |
| 40 | #define GPIO3_nCS2 MFP_CFG(GPIO3, AF1) | ||
| 41 | #define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) | 41 | #define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) |
| 42 | 42 | ||
| 43 | /* AC97 */ | 43 | /* AC97 */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h index 1f6b35c015d0..d375195d982b 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h | |||
| @@ -1,68 +1,9 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA3XX_H | 1 | #ifndef __ASM_ARCH_MFP_PXA3XX_H |
| 2 | #define __ASM_ARCH_MFP_PXA3XX_H | 2 | #define __ASM_ARCH_MFP_PXA3XX_H |
| 3 | 3 | ||
| 4 | #define MFPR_BASE (0x40e10000) | 4 | #include <plat/mfp.h> |
| 5 | #define MFPR_SIZE (PAGE_SIZE) | ||
| 6 | |||
| 7 | /* MFPR register bit definitions */ | ||
| 8 | #define MFPR_PULL_SEL (0x1 << 15) | ||
| 9 | #define MFPR_PULLUP_EN (0x1 << 14) | ||
| 10 | #define MFPR_PULLDOWN_EN (0x1 << 13) | ||
| 11 | #define MFPR_SLEEP_SEL (0x1 << 9) | ||
| 12 | #define MFPR_SLEEP_OE_N (0x1 << 7) | ||
| 13 | #define MFPR_EDGE_CLEAR (0x1 << 6) | ||
| 14 | #define MFPR_EDGE_FALL_EN (0x1 << 5) | ||
| 15 | #define MFPR_EDGE_RISE_EN (0x1 << 4) | ||
| 16 | |||
| 17 | #define MFPR_SLEEP_DATA(x) ((x) << 8) | ||
| 18 | #define MFPR_DRIVE(x) (((x) & 0x7) << 10) | ||
| 19 | #define MFPR_AF_SEL(x) (((x) & 0x7) << 0) | ||
| 20 | 5 | ||
| 21 | #define MFPR_EDGE_NONE (0) | 6 | #define MFPR_BASE (0x40e10000) |
| 22 | #define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) | ||
| 23 | #define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) | ||
| 24 | #define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Table that determines the low power modes outputs, with actual settings | ||
| 28 | * used in parentheses for don't-care values. Except for the float output, | ||
| 29 | * the configured driven and pulled levels match, so if there is a need for | ||
| 30 | * non-LPM pulled output, the same configuration could probably be used. | ||
| 31 | * | ||
| 32 | * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel | ||
| 33 | * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) | ||
| 34 | * | ||
| 35 | * Input 0 X(0) X(0) X(0) 0 | ||
| 36 | * Drive 0 0 0 0 X(1) 0 | ||
| 37 | * Drive 1 0 1 X(1) 0 0 | ||
| 38 | * Pull hi (1) 1 X(1) 1 0 0 | ||
| 39 | * Pull lo (0) 1 X(0) 0 1 0 | ||
| 40 | * Z (float) 1 X(0) 0 0 0 | ||
| 41 | */ | ||
| 42 | #define MFPR_LPM_INPUT (0) | ||
| 43 | #define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) | ||
| 44 | #define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) | ||
| 45 | #define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) | ||
| 46 | #define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) | ||
| 47 | #define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) | ||
| 48 | #define MFPR_LPM_MASK (0xe080) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * The pullup and pulldown state of the MFP pin at run mode is by default | ||
| 52 | * determined by the selected alternate function. In case that some buggy | ||
| 53 | * devices need to override this default behavior, the definitions below | ||
| 54 | * indicates the setting of corresponding MFPR bits | ||
| 55 | * | ||
| 56 | * Definition pull_sel pullup_en pulldown_en | ||
| 57 | * MFPR_PULL_NONE 0 0 0 | ||
| 58 | * MFPR_PULL_LOW 1 0 1 | ||
| 59 | * MFPR_PULL_HIGH 1 1 0 | ||
| 60 | * MFPR_PULL_BOTH 1 1 1 | ||
| 61 | */ | ||
| 62 | #define MFPR_PULL_NONE (0) | ||
| 63 | #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) | ||
| 64 | #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) | ||
| 65 | #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) | ||
| 66 | 7 | ||
| 67 | /* PXA3xx common MFP configurations - processor specific ones defined | 8 | /* PXA3xx common MFP configurations - processor specific ones defined |
| 68 | * in mfp-pxa300.h and mfp-pxa320.h | 9 | * in mfp-pxa300.h and mfp-pxa320.h |
| @@ -197,56 +138,21 @@ | |||
| 197 | #define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) | 138 | #define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) |
| 198 | #define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) | 139 | #define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) |
| 199 | 140 | ||
| 200 | /* | 141 | /* NOTE: usage of these two functions is not recommended, |
| 201 | * each MFP pin will have a MFPR register, since the offset of the | 142 | * use pxa3xx_mfp_config() instead. |
| 202 | * register varies between processors, the processor specific code | ||
| 203 | * should initialize the pin offsets by pxa3xx_mfp_init_addr() | ||
| 204 | * | ||
| 205 | * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" | ||
| 206 | * structure, which represents a range of MFP pins from "start" to | ||
| 207 | * "end", with the offset begining at "offset", to define a single | ||
| 208 | * pin, let "end" = -1 | ||
| 209 | * | ||
| 210 | * use | ||
| 211 | * | ||
| 212 | * MFP_ADDR_X() to define a range of pins | ||
| 213 | * MFP_ADDR() to define a single pin | ||
| 214 | * MFP_ADDR_END to signal the end of pin offset definitions | ||
| 215 | */ | ||
| 216 | struct pxa3xx_mfp_addr_map { | ||
| 217 | unsigned int start; | ||
| 218 | unsigned int end; | ||
| 219 | unsigned long offset; | ||
| 220 | }; | ||
| 221 | |||
| 222 | #define MFP_ADDR_X(start, end, offset) \ | ||
| 223 | { MFP_PIN_##start, MFP_PIN_##end, offset } | ||
| 224 | |||
| 225 | #define MFP_ADDR(pin, offset) \ | ||
| 226 | { MFP_PIN_##pin, -1, offset } | ||
| 227 | |||
| 228 | #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } | ||
| 229 | |||
| 230 | /* | ||
| 231 | * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access | ||
| 232 | * to the MFPR register | ||
| 233 | */ | ||
| 234 | unsigned long pxa3xx_mfp_read(int mfp); | ||
| 235 | void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); | ||
| 236 | |||
| 237 | /* | ||
| 238 | * pxa3xx_mfp_config - configure the MFPR registers | ||
| 239 | * | ||
| 240 | * used by board specific initialization code | ||
| 241 | */ | ||
| 242 | void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num); | ||
| 243 | |||
| 244 | /* | ||
| 245 | * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin | ||
| 246 | * index and MFPR register offset | ||
| 247 | * | ||
| 248 | * used by processor specific code | ||
| 249 | */ | 143 | */ |
| 250 | void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); | 144 | static inline unsigned long pxa3xx_mfp_read(int mfp) |
| 251 | void __init pxa3xx_init_mfp(void); | 145 | { |
| 146 | return mfp_read(mfp); | ||
| 147 | } | ||
| 148 | |||
| 149 | static inline void pxa3xx_mfp_write(int mfp, unsigned long val) | ||
| 150 | { | ||
| 151 | mfp_write(mfp, val); | ||
| 152 | } | ||
| 153 | |||
| 154 | static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) | ||
| 155 | { | ||
| 156 | mfp_config(mfp_cfg, num); | ||
| 157 | } | ||
| 252 | #endif /* __ASM_ARCH_MFP_PXA3XX_H */ | 158 | #endif /* __ASM_ARCH_MFP_PXA3XX_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h index fa73f56a1372..0d119d3b9221 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #ifndef __ASM_ARCH_MFP_PXA9xx_H | 13 | #ifndef __ASM_ARCH_MFP_PXA9xx_H |
| 14 | #define __ASM_ARCH_MFP_PXA9xx_H | 14 | #define __ASM_ARCH_MFP_PXA9xx_H |
| 15 | 15 | ||
| 16 | #include <mach/mfp.h> | ||
| 17 | #include <mach/mfp-pxa3xx.h> | 16 | #include <mach/mfp-pxa3xx.h> |
| 18 | 17 | ||
| 19 | /* GPIO */ | 18 | /* GPIO */ |
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index cfca8155be72..297387ec3618 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h | |||
| @@ -15,8 +15,8 @@ | |||
| 15 | #ifndef __ARCH_PXA_MTD_XIP_H__ | 15 | #ifndef __ARCH_PXA_MTD_XIP_H__ |
| 16 | #define __ARCH_PXA_MTD_XIP_H__ | 16 | #define __ARCH_PXA_MTD_XIP_H__ |
| 17 | 17 | ||
| 18 | #include <mach/hardware.h> | 18 | #include <mach/regs-ost.h> |
| 19 | #include <mach/pxa-regs.h> | 19 | #include <mach/regs-intc.h> |
| 20 | 20 | ||
| 21 | #define xip_irqpending() (ICIP & ICMR) | 21 | #define xip_irqpending() (ICIP & ICMR) |
| 22 | 22 | ||
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h new file mode 100644 index 000000000000..7c295a48d784 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmld.h | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm LifeDrive Handheld Computer | ||
| 3 | * | ||
| 4 | * Authors: Alex Osborne <ato@meshy.org> | ||
| 5 | * Marek Vasut <marek.vasut@gmail.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _INCLUDE_PALMLD_H_ | ||
| 14 | #define _INCLUDE_PALMLD_H_ | ||
| 15 | |||
| 16 | /** HERE ARE GPIOs **/ | ||
| 17 | |||
| 18 | /* GPIOs */ | ||
| 19 | #define GPIO_NR_PALMLD_GPIO_RESET 1 | ||
| 20 | #define GPIO_NR_PALMLD_POWER_DETECT 4 | ||
| 21 | #define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10 | ||
| 22 | #define GPIO_NR_PALMLD_POWER_SWITCH 12 | ||
| 23 | #define GPIO_NR_PALMLD_EARPHONE_DETECT 13 | ||
| 24 | #define GPIO_NR_PALMLD_LOCK_SWITCH 15 | ||
| 25 | |||
| 26 | /* SD/MMC */ | ||
| 27 | #define GPIO_NR_PALMLD_SD_DETECT_N 14 | ||
| 28 | #define GPIO_NR_PALMLD_SD_POWER 114 | ||
| 29 | #define GPIO_NR_PALMLD_SD_READONLY 116 | ||
| 30 | |||
| 31 | /* TOUCHSCREEN */ | ||
| 32 | #define GPIO_NR_PALMLD_WM9712_IRQ 27 | ||
| 33 | |||
| 34 | /* IRDA */ | ||
| 35 | #define GPIO_NR_PALMLD_IR_DISABLE 108 | ||
| 36 | |||
| 37 | /* LCD/BACKLIGHT */ | ||
| 38 | #define GPIO_NR_PALMLD_BL_POWER 19 | ||
| 39 | #define GPIO_NR_PALMLD_LCD_POWER 96 | ||
| 40 | |||
| 41 | /* LCD BORDER */ | ||
| 42 | #define GPIO_NR_PALMLD_BORDER_SWITCH 21 | ||
| 43 | #define GPIO_NR_PALMLD_BORDER_SELECT 22 | ||
| 44 | |||
| 45 | /* BLUETOOTH */ | ||
| 46 | #define GPIO_NR_PALMLD_BT_POWER 17 | ||
| 47 | #define GPIO_NR_PALMLD_BT_RESET 83 | ||
| 48 | |||
| 49 | /* PCMCIA (WiFi) */ | ||
| 50 | #define GPIO_NR_PALMLD_PCMCIA_READY 38 | ||
| 51 | #define GPIO_NR_PALMLD_PCMCIA_POWER 36 | ||
| 52 | #define GPIO_NR_PALMLD_PCMCIA_RESET 81 | ||
| 53 | |||
| 54 | /* LEDs */ | ||
| 55 | #define GPIO_NR_PALMLD_LED_GREEN 52 | ||
| 56 | #define GPIO_NR_PALMLD_LED_AMBER 94 | ||
| 57 | |||
| 58 | /* IDE */ | ||
| 59 | #define GPIO_NR_PALMLD_IDE_IRQ 95 | ||
| 60 | #define GPIO_NR_PALMLD_IDE_RESET 98 | ||
| 61 | #define GPIO_NR_PALMLD_IDE_PWEN 115 | ||
| 62 | |||
| 63 | /* USB */ | ||
| 64 | #define GPIO_NR_PALMLD_USB_DETECT_N 3 | ||
| 65 | #define GPIO_NR_PALMLD_USB_READY 86 | ||
| 66 | #define GPIO_NR_PALMLD_USB_RESET 88 | ||
| 67 | #define GPIO_NR_PALMLD_USB_INT 106 | ||
| 68 | #define GPIO_NR_PALMLD_USB_POWER 118 | ||
| 69 | /* 20, 53 and 86 are usb related too */ | ||
| 70 | |||
| 71 | /* INTERRUPTS */ | ||
| 72 | #define IRQ_GPIO_PALMLD_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET) | ||
| 73 | #define IRQ_GPIO_PALMLD_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N) | ||
| 74 | #define IRQ_GPIO_PALMLD_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ) | ||
| 75 | #define IRQ_GPIO_PALMLD_IDE_IRQ IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ) | ||
| 76 | |||
| 77 | |||
| 78 | /** HERE ARE INIT VALUES **/ | ||
| 79 | |||
| 80 | /* IO mappings */ | ||
| 81 | #define PALMLD_USB_PHYS PXA_CS2_PHYS | ||
| 82 | #define PALMLD_USB_VIRT 0xf0000000 | ||
| 83 | #define PALMLD_USB_SIZE 0x00100000 | ||
| 84 | |||
| 85 | #define PALMLD_IDE_PHYS 0x20000000 | ||
| 86 | #define PALMLD_IDE_VIRT 0xf1000000 | ||
| 87 | #define PALMLD_IDE_SIZE 0x00100000 | ||
| 88 | |||
| 89 | #define PALMLD_PHYS_IO_START 0x40000000 | ||
| 90 | |||
| 91 | /* BATTERY */ | ||
| 92 | #define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ | ||
| 93 | #define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ | ||
| 94 | #define PALMLD_BAT_MAX_CURRENT 0 /* unknokn */ | ||
| 95 | #define PALMLD_BAT_MIN_CURRENT 0 /* unknown */ | ||
| 96 | #define PALMLD_BAT_MAX_CHARGE 1 /* unknown */ | ||
| 97 | #define PALMLD_BAT_MIN_CHARGE 1 /* unknown */ | ||
| 98 | #define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */ | ||
| 99 | |||
| 100 | #define PALMLD_BAT_MEASURE_DELAY (HZ * 1) | ||
| 101 | |||
| 102 | /* BACKLIGHT */ | ||
| 103 | #define PALMLD_MAX_INTENSITY 0xFE | ||
| 104 | #define PALMLD_DEFAULT_INTENSITY 0x7E | ||
| 105 | #define PALMLD_LIMIT_MASK 0x7F | ||
| 106 | #define PALMLD_PRESCALER 0x3F | ||
| 107 | #define PALMLD_PERIOD_NS 3500 | ||
| 108 | |||
| 109 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h new file mode 100644 index 000000000000..94db2881f048 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmt5.h | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer | ||
| 3 | * | ||
| 4 | * Authors: Ales Snuparek <snuparek@atlas.cz> | ||
| 5 | * Marek Vasut <marek.vasut@gmail.com> | ||
| 6 | * Justin Kendrick <twilightsentry@gmail.com> | ||
| 7 | * RichardT5 <richard_t5@users.sourceforge.net> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef _INCLUDE_PALMT5_H_ | ||
| 16 | #define _INCLUDE_PALMT5_H_ | ||
| 17 | |||
| 18 | /** HERE ARE GPIOs **/ | ||
| 19 | |||
| 20 | /* GPIOs */ | ||
| 21 | #define GPIO_NR_PALMT5_GPIO_RESET 1 | ||
| 22 | |||
| 23 | #define GPIO_NR_PALMT5_POWER_DETECT 90 | ||
| 24 | #define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N 10 | ||
| 25 | #define GPIO_NR_PALMT5_EARPHONE_DETECT 107 | ||
| 26 | |||
| 27 | /* SD/MMC */ | ||
| 28 | #define GPIO_NR_PALMT5_SD_DETECT_N 14 | ||
| 29 | #define GPIO_NR_PALMT5_SD_POWER 114 | ||
| 30 | #define GPIO_NR_PALMT5_SD_READONLY 115 | ||
| 31 | |||
| 32 | /* TOUCHSCREEN */ | ||
| 33 | #define GPIO_NR_PALMT5_WM9712_IRQ 27 | ||
| 34 | |||
| 35 | /* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ | ||
| 36 | #define GPIO_NR_PALMT5_IR_DISABLE 40 | ||
| 37 | |||
| 38 | /* USB */ | ||
| 39 | #define GPIO_NR_PALMT5_USB_DETECT_N 15 | ||
| 40 | #define GPIO_NR_PALMT5_USB_POWER 95 | ||
| 41 | #define GPIO_NR_PALMT5_USB_PULLUP 93 | ||
| 42 | |||
| 43 | /* LCD/BACKLIGHT */ | ||
| 44 | #define GPIO_NR_PALMT5_BL_POWER 84 | ||
| 45 | #define GPIO_NR_PALMT5_LCD_POWER 96 | ||
| 46 | |||
| 47 | /* BLUETOOTH */ | ||
| 48 | #define GPIO_NR_PALMT5_BT_POWER 17 | ||
| 49 | #define GPIO_NR_PALMT5_BT_RESET 83 | ||
| 50 | |||
| 51 | /* INTERRUPTS */ | ||
| 52 | #define IRQ_GPIO_PALMT5_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N) | ||
| 53 | #define IRQ_GPIO_PALMT5_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ) | ||
| 54 | #define IRQ_GPIO_PALMT5_USB_DETECT IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT) | ||
| 55 | #define IRQ_GPIO_PALMT5_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET) | ||
| 56 | |||
| 57 | /** HERE ARE INIT VALUES **/ | ||
| 58 | |||
| 59 | /* Various addresses */ | ||
| 60 | #define PALMT5_PHYS_RAM_START 0xa0000000 | ||
| 61 | #define PALMT5_PHYS_IO_START 0x40000000 | ||
| 62 | |||
| 63 | /* TOUCHSCREEN */ | ||
| 64 | #define AC97_LINK_FRAME 21 | ||
| 65 | |||
| 66 | /* BATTERY */ | ||
| 67 | #define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ | ||
| 68 | #define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ | ||
| 69 | #define PALMT5_BAT_MAX_CURRENT 0 /* unknokn */ | ||
| 70 | #define PALMT5_BAT_MIN_CURRENT 0 /* unknown */ | ||
| 71 | #define PALMT5_BAT_MAX_CHARGE 1 /* unknown */ | ||
| 72 | #define PALMT5_BAT_MIN_CHARGE 1 /* unknown */ | ||
| 73 | #define PALMT5_MAX_LIFE_MINS 360 /* on-life in minutes */ | ||
| 74 | |||
| 75 | #define PALMT5_BAT_MEASURE_DELAY (HZ * 1) | ||
| 76 | |||
| 77 | /* BACKLIGHT */ | ||
| 78 | #define PALMT5_MAX_INTENSITY 0xFE | ||
| 79 | #define PALMT5_DEFAULT_INTENSITY 0x7E | ||
| 80 | #define PALMT5_LIMIT_MASK 0x7F | ||
| 81 | #define PALMT5_PRESCALER 0x3F | ||
| 82 | #define PALMT5_PERIOD_NS 3500 | ||
| 83 | |||
| 84 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h index 83342469acac..a6eeef8a075f 100644 --- a/arch/arm/mach-pxa/include/mach/pm.h +++ b/arch/arm/mach-pxa/include/mach/pm.h | |||
| @@ -27,3 +27,13 @@ extern void pxa27x_cpu_suspend(unsigned int); | |||
| 27 | extern void pxa_cpu_resume(void); | 27 | extern void pxa_cpu_resume(void); |
| 28 | 28 | ||
| 29 | extern int pxa_pm_enter(suspend_state_t state); | 29 | extern int pxa_pm_enter(suspend_state_t state); |
| 30 | |||
| 31 | /* NOTE: this is for PM debugging on Lubbock, it's really a big | ||
| 32 | * ugly, but let's keep the crap minimum here, instead of direct | ||
| 33 | * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c | ||
| 34 | */ | ||
| 35 | #ifdef CONFIG_ARCH_LUBBOCK | ||
| 36 | extern void lubbock_set_hexled(uint32_t value); | ||
| 37 | #else | ||
| 38 | #define lubbock_set_hexled(x) | ||
| 39 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h deleted file mode 100644 index 31d615aa7723..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ /dev/null | |||
| @@ -1,263 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/include/mach/pxa-regs.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __PXA_REGS_H | ||
| 14 | #define __PXA_REGS_H | ||
| 15 | |||
| 16 | #include <mach/hardware.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * PXA Chip selects | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define PXA_CS0_PHYS 0x00000000 | ||
| 23 | #define PXA_CS1_PHYS 0x04000000 | ||
| 24 | #define PXA_CS2_PHYS 0x08000000 | ||
| 25 | #define PXA_CS3_PHYS 0x0C000000 | ||
| 26 | #define PXA_CS4_PHYS 0x10000000 | ||
| 27 | #define PXA_CS5_PHYS 0x14000000 | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * Personal Computer Memory Card International Association (PCMCIA) sockets | ||
| 32 | */ | ||
| 33 | |||
| 34 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | ||
| 35 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | ||
| 36 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | ||
| 37 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | ||
| 38 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | ||
| 39 | |||
| 40 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | ||
| 41 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | ||
| 42 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | ||
| 43 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | ||
| 44 | |||
| 45 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | ||
| 46 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | ||
| 47 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | ||
| 48 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | ||
| 49 | |||
| 50 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 51 | (0x20000000 + (Nb)*PCMCIASp) | ||
| 52 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ | ||
| 53 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | ||
| 54 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) | ||
| 55 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | ||
| 56 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) | ||
| 57 | |||
| 58 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ | ||
| 59 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ | ||
| 60 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ | ||
| 61 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ | ||
| 62 | |||
| 63 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ | ||
| 64 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ | ||
| 65 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ | ||
| 66 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ | ||
| 67 | |||
| 68 | |||
| 69 | |||
| 70 | /* | ||
| 71 | * DMA Controller | ||
| 72 | */ | ||
| 73 | #define DCSR(x) __REG2(0x40000000, (x) << 2) | ||
| 74 | |||
| 75 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | ||
| 76 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | ||
| 77 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | ||
| 78 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
| 79 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
| 80 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
| 81 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
| 82 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
| 83 | |||
| 84 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 85 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | ||
| 86 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
| 87 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
| 88 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | ||
| 89 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | ||
| 90 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | ||
| 91 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | ||
| 92 | #endif | ||
| 93 | |||
| 94 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ | ||
| 95 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ | ||
| 96 | |||
| 97 | #define DRCMR(n) (*(((n) < 64) ? \ | ||
| 98 | &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ | ||
| 99 | &__REG2(0x40001100, ((n) & 0x3f) << 2))) | ||
| 100 | |||
| 101 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ | ||
| 102 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | ||
| 103 | |||
| 104 | #define DDADR(x) __REG2(0x40000200, (x) << 4) | ||
| 105 | #define DSADR(x) __REG2(0x40000204, (x) << 4) | ||
| 106 | #define DTADR(x) __REG2(0x40000208, (x) << 4) | ||
| 107 | #define DCMD(x) __REG2(0x4000020c, (x) << 4) | ||
| 108 | |||
| 109 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | ||
| 110 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | ||
| 111 | |||
| 112 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | ||
| 113 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | ||
| 114 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | ||
| 115 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | ||
| 116 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
| 117 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
| 118 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | ||
| 119 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | ||
| 120 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | ||
| 121 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | ||
| 122 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | ||
| 123 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | ||
| 124 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | ||
| 125 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
| 126 | |||
| 127 | /* | ||
| 128 | * Real Time Clock | ||
| 129 | */ | ||
| 130 | |||
| 131 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | ||
| 132 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | ||
| 133 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | ||
| 134 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | ||
| 135 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | ||
| 136 | |||
| 137 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | ||
| 138 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | ||
| 139 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | ||
| 140 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | ||
| 141 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | ||
| 142 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | ||
| 143 | |||
| 144 | |||
| 145 | /* | ||
| 146 | * OS Timer & Match Registers | ||
| 147 | */ | ||
| 148 | |||
| 149 | #define OSMR0 __REG(0x40A00000) /* */ | ||
| 150 | #define OSMR1 __REG(0x40A00004) /* */ | ||
| 151 | #define OSMR2 __REG(0x40A00008) /* */ | ||
| 152 | #define OSMR3 __REG(0x40A0000C) /* */ | ||
| 153 | #define OSMR4 __REG(0x40A00080) /* */ | ||
| 154 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | ||
| 155 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | ||
| 156 | #define OMCR4 __REG(0x40A000C0) /* */ | ||
| 157 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | ||
| 158 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | ||
| 159 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | ||
| 160 | |||
| 161 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | ||
| 162 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | ||
| 163 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | ||
| 164 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | ||
| 165 | |||
| 166 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | ||
| 167 | |||
| 168 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | ||
| 169 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | ||
| 170 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | ||
| 171 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | ||
| 172 | |||
| 173 | |||
| 174 | /* | ||
| 175 | * Interrupt Controller | ||
| 176 | */ | ||
| 177 | |||
| 178 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | ||
| 179 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | ||
| 180 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | ||
| 181 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | ||
| 182 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | ||
| 183 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | ||
| 184 | |||
| 185 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 186 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 187 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 188 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 189 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 190 | |||
| 191 | /* | ||
| 192 | * General Purpose I/O | ||
| 193 | */ | ||
| 194 | |||
| 195 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ | ||
| 196 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ | ||
| 197 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ | ||
| 198 | |||
| 199 | #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ | ||
| 200 | #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ | ||
| 201 | #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ | ||
| 202 | |||
| 203 | #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ | ||
| 204 | #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ | ||
| 205 | #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ | ||
| 206 | |||
| 207 | #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ | ||
| 208 | #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ | ||
| 209 | #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ | ||
| 210 | |||
| 211 | #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ | ||
| 212 | #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ | ||
| 213 | #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ | ||
| 214 | |||
| 215 | #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ | ||
| 216 | #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ | ||
| 217 | #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ | ||
| 218 | |||
| 219 | #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ | ||
| 220 | #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ | ||
| 221 | #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ | ||
| 222 | |||
| 223 | #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ | ||
| 224 | #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ | ||
| 225 | #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ | ||
| 226 | #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ | ||
| 227 | #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ | ||
| 228 | #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */ | ||
| 229 | #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ | ||
| 230 | #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ | ||
| 231 | |||
| 232 | #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ | ||
| 233 | #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ | ||
| 234 | #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ | ||
| 235 | #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ | ||
| 236 | #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ | ||
| 237 | #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ | ||
| 238 | #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ | ||
| 239 | |||
| 240 | /* More handy macros. The argument is a literal GPIO number. */ | ||
| 241 | |||
| 242 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | ||
| 243 | |||
| 244 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | ||
| 245 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | ||
| 246 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | ||
| 247 | #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | ||
| 248 | #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | ||
| 249 | #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | ||
| 250 | #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | ||
| 251 | #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | ||
| 252 | |||
| 253 | #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) | ||
| 254 | #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) | ||
| 255 | #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) | ||
| 256 | #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) | ||
| 257 | #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) | ||
| 258 | #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) | ||
| 259 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) | ||
| 260 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ | ||
| 261 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) | ||
| 262 | |||
| 263 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h new file mode 100644 index 000000000000..508c3ba1f4d0 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa25x.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef __MACH_PXA25x_H | ||
| 2 | #define __MACH_PXA25x_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa2xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa25x.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA25x_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h new file mode 100644 index 000000000000..6876e16c2970 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa27x.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | #ifndef __MACH_PXA27x_H | ||
| 2 | #define __MACH_PXA27x_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa2xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa27x.h> | ||
| 7 | |||
| 8 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ | ||
| 9 | |||
| 10 | #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ | ||
| 11 | #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ | ||
| 12 | #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ | ||
| 13 | #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ | ||
| 14 | #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ | ||
| 15 | #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ | ||
| 16 | #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ | ||
| 17 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ | ||
| 18 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ | ||
| 19 | #endif /* __MACH_PXA27x_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h index d83393e25273..1209c44aa6f1 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | 3 | ||
| 4 | #warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h | 4 | #warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h |
| 5 | 5 | ||
| 6 | #include <mach/gpio.h> | ||
| 7 | |||
| 6 | /* GPIO alternate function assignments */ | 8 | /* GPIO alternate function assignments */ |
| 7 | 9 | ||
| 8 | #define GPIO1_RST 1 /* reset */ | 10 | #define GPIO1_RST 1 /* reset */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 77102d695cc7..4fcddd9cab76 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | |||
| @@ -14,6 +14,19 @@ | |||
| 14 | #ifndef __PXA2XX_REGS_H | 14 | #ifndef __PXA2XX_REGS_H |
| 15 | #define __PXA2XX_REGS_H | 15 | #define __PXA2XX_REGS_H |
| 16 | 16 | ||
| 17 | #include <mach/hardware.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * PXA Chip selects | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define PXA_CS0_PHYS 0x00000000 | ||
| 24 | #define PXA_CS1_PHYS 0x04000000 | ||
| 25 | #define PXA_CS2_PHYS 0x08000000 | ||
| 26 | #define PXA_CS3_PHYS 0x0C000000 | ||
| 27 | #define PXA_CS4_PHYS 0x10000000 | ||
| 28 | #define PXA_CS5_PHYS 0x14000000 | ||
| 29 | |||
| 17 | /* | 30 | /* |
| 18 | * Memory controller | 31 | * Memory controller |
| 19 | */ | 32 | */ |
| @@ -69,24 +82,6 @@ | |||
| 69 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ | 82 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ |
| 70 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ | 83 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ |
| 71 | 84 | ||
| 72 | |||
| 73 | #ifdef CONFIG_PXA27x | ||
| 74 | |||
| 75 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ | ||
| 76 | |||
| 77 | #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ | ||
| 78 | #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ | ||
| 79 | #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ | ||
| 80 | #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ | ||
| 81 | #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ | ||
| 82 | #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ | ||
| 83 | #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ | ||
| 84 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ | ||
| 85 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ | ||
| 86 | |||
| 87 | #endif | ||
| 88 | |||
| 89 | |||
| 90 | /* | 85 | /* |
| 91 | * Power Manager | 86 | * Power Manager |
| 92 | */ | 87 | */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h new file mode 100644 index 000000000000..2f33076c9e48 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa300.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef __MACH_PXA300_H | ||
| 2 | #define __MACH_PXA300_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa3xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa300.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA300_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h new file mode 100644 index 000000000000..cab78e903273 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa320.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | #ifndef __MACH_PXA320_H | ||
| 2 | #define __MACH_PXA320_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa3xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa320.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA320_H */ | ||
| 9 | |||
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index bcf3fb2c4b3a..7d1a059b3d43 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | |||
| @@ -13,6 +13,17 @@ | |||
| 13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H | 13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H |
| 14 | #define __ASM_ARCH_PXA3XX_REGS_H | 14 | #define __ASM_ARCH_PXA3XX_REGS_H |
| 15 | 15 | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Static Chip Selects | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */ | ||
| 23 | #define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */ | ||
| 24 | #define PXA3xx_CS2_PHYS (0x10000000) | ||
| 25 | #define PXA3xx_CS3_PHYS (0x14000000) | ||
| 26 | |||
| 16 | /* | 27 | /* |
| 17 | * Oscillator Configuration Register (OSCC) | 28 | * Oscillator Configuration Register (OSCC) |
| 18 | */ | 29 | */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h new file mode 100644 index 000000000000..d45f76a9b54d --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa930.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef __MACH_PXA930_H | ||
| 2 | #define __MACH_PXA930_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa3xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa930.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA930_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h new file mode 100644 index 000000000000..ad23e74b762f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-intc.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_REGS_INTC_H | ||
| 2 | #define __ASM_MACH_REGS_INTC_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Interrupt Controller | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | ||
| 11 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | ||
| 12 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | ||
| 13 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | ||
| 14 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | ||
| 15 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | ||
| 16 | |||
| 17 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 18 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 19 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 20 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 21 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 22 | |||
| 23 | #endif /* __ASM_MACH_REGS_INTC_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h new file mode 100644 index 000000000000..a3e5f86ef67e --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | #ifndef __ASM_MACH_REGS_OST_H | ||
| 2 | #define __ASM_MACH_REGS_OST_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * OS Timer & Match Registers | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define OSMR0 __REG(0x40A00000) /* */ | ||
| 11 | #define OSMR1 __REG(0x40A00004) /* */ | ||
| 12 | #define OSMR2 __REG(0x40A00008) /* */ | ||
| 13 | #define OSMR3 __REG(0x40A0000C) /* */ | ||
| 14 | #define OSMR4 __REG(0x40A00080) /* */ | ||
| 15 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | ||
| 16 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | ||
| 17 | #define OMCR4 __REG(0x40A000C0) /* */ | ||
| 18 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | ||
| 19 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | ||
| 20 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | ||
| 21 | |||
| 22 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | ||
| 23 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | ||
| 24 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | ||
| 25 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | ||
| 26 | |||
| 27 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | ||
| 28 | |||
| 29 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | ||
| 30 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | ||
| 31 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | ||
| 32 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | ||
| 33 | |||
| 34 | #endif /* __ASM_MACH_REGS_OST_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-rtc.h b/arch/arm/mach-pxa/include/mach/regs-rtc.h new file mode 100644 index 000000000000..f0e4a589bbe1 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-rtc.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_REGS_RTC_H | ||
| 2 | #define __ASM_MACH_REGS_RTC_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Real Time Clock | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | ||
| 11 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | ||
| 12 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | ||
| 13 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | ||
| 14 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | ||
| 15 | |||
| 16 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | ||
| 17 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | ||
| 18 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | ||
| 19 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | ||
| 20 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | ||
| 21 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | ||
| 22 | |||
| 23 | #endif /* __ASM_MACH_REGS_RTC_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h index 018f6d65b57b..6a2ed35acd59 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ssp.h +++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h | |||
| @@ -37,7 +37,6 @@ | |||
| 37 | #if defined(CONFIG_PXA25x) | 37 | #if defined(CONFIG_PXA25x) |
| 38 | #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ | 38 | #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ |
| 39 | #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ | 39 | #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ |
| 40 | |||
| 41 | #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | 40 | #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
| 42 | #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ | 41 | #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ |
| 43 | #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ | 42 | #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ |
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h index 0f381e692999..d1fce8b6d105 100644 --- a/arch/arm/mach-pxa/include/mach/system.h +++ b/arch/arm/mach-pxa/include/mach/system.h | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <asm/proc-fns.h> | 13 | #include <asm/proc-fns.h> |
| 14 | #include "hardware.h" | 14 | #include "hardware.h" |
| 15 | #include "pxa2xx-regs.h" | 15 | #include "pxa2xx-regs.h" |
| 16 | #include "pxa-regs.h" | ||
| 17 | 16 | ||
| 18 | static inline void arch_idle(void) | 17 | static inline void arch_idle(void) |
| 19 | { | 18 | { |
| @@ -21,4 +20,4 @@ static inline void arch_idle(void) | |||
| 21 | } | 20 | } |
| 22 | 21 | ||
| 23 | 22 | ||
| 24 | void arch_reset(char mode); | 23 | void arch_reset(char mode, const char *cmd); |
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index f4b029c03957..5706cea95d11 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h | |||
| @@ -35,7 +35,8 @@ static inline void flush(void) | |||
| 35 | 35 | ||
| 36 | static inline void arch_decomp_setup(void) | 36 | static inline void arch_decomp_setup(void) |
| 37 | { | 37 | { |
| 38 | if (machine_is_littleton() || machine_is_intelmote2()) | 38 | if (machine_is_littleton() || machine_is_intelmote2() |
| 39 | || machine_is_csb726()) | ||
| 39 | UART = STUART; | 40 | UART = STUART; |
| 40 | } | 41 | } |
| 41 | 42 | ||
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index fa69c3a6a38e..f6e0300e4f64 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
| @@ -20,7 +20,8 @@ | |||
| 20 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
| 21 | #include <asm/irq.h> | 21 | #include <asm/irq.h> |
| 22 | #include <asm/mach/irq.h> | 22 | #include <asm/mach/irq.h> |
| 23 | #include <mach/pxa-regs.h> | 23 | #include <mach/gpio.h> |
| 24 | #include <mach/regs-intc.h> | ||
| 24 | 25 | ||
| 25 | #include "generic.h" | 26 | #include "generic.h" |
| 26 | 27 | ||
| @@ -51,6 +52,72 @@ static struct irq_chip pxa_internal_irq_chip = { | |||
| 51 | .unmask = pxa_unmask_irq, | 52 | .unmask = pxa_unmask_irq, |
| 52 | }; | 53 | }; |
| 53 | 54 | ||
| 55 | /* | ||
| 56 | * GPIO IRQs for GPIO 0 and 1 | ||
| 57 | */ | ||
| 58 | static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type) | ||
| 59 | { | ||
| 60 | int gpio = irq - IRQ_GPIO0; | ||
| 61 | |||
| 62 | if (__gpio_is_occupied(gpio)) { | ||
| 63 | pr_err("%s failed: GPIO is configured\n", __func__); | ||
| 64 | return -EINVAL; | ||
| 65 | } | ||
| 66 | |||
| 67 | if (type & IRQ_TYPE_EDGE_RISING) | ||
| 68 | GRER0 |= GPIO_bit(gpio); | ||
| 69 | else | ||
| 70 | GRER0 &= ~GPIO_bit(gpio); | ||
| 71 | |||
| 72 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
| 73 | GFER0 |= GPIO_bit(gpio); | ||
| 74 | else | ||
| 75 | GFER0 &= ~GPIO_bit(gpio); | ||
| 76 | |||
| 77 | return 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | static void pxa_ack_low_gpio(unsigned int irq) | ||
| 81 | { | ||
| 82 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | ||
| 83 | } | ||
| 84 | |||
| 85 | static void pxa_mask_low_gpio(unsigned int irq) | ||
| 86 | { | ||
| 87 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | ||
| 88 | } | ||
| 89 | |||
| 90 | static void pxa_unmask_low_gpio(unsigned int irq) | ||
| 91 | { | ||
| 92 | ICMR |= 1 << (irq - PXA_IRQ(0)); | ||
| 93 | } | ||
| 94 | |||
| 95 | static struct irq_chip pxa_low_gpio_chip = { | ||
| 96 | .name = "GPIO-l", | ||
| 97 | .ack = pxa_ack_low_gpio, | ||
| 98 | .mask = pxa_mask_low_gpio, | ||
| 99 | .unmask = pxa_unmask_low_gpio, | ||
| 100 | .set_type = pxa_set_low_gpio_type, | ||
| 101 | }; | ||
| 102 | |||
| 103 | static void __init pxa_init_low_gpio_irq(set_wake_t fn) | ||
| 104 | { | ||
| 105 | int irq; | ||
| 106 | |||
| 107 | /* clear edge detection on GPIO 0 and 1 */ | ||
| 108 | GFER0 &= ~0x3; | ||
| 109 | GRER0 &= ~0x3; | ||
| 110 | GEDR0 = 0x3; | ||
| 111 | |||
| 112 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | ||
| 113 | set_irq_chip(irq, &pxa_low_gpio_chip); | ||
| 114 | set_irq_handler(irq, handle_edge_irq); | ||
| 115 | set_irq_flags(irq, IRQF_VALID); | ||
| 116 | } | ||
| 117 | |||
| 118 | pxa_low_gpio_chip.set_wake = fn; | ||
| 119 | } | ||
| 120 | |||
| 54 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) | 121 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
| 55 | { | 122 | { |
| 56 | int irq; | 123 | int irq; |
| @@ -72,6 +139,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) | |||
| 72 | } | 139 | } |
| 73 | 140 | ||
| 74 | pxa_internal_irq_chip.set_wake = fn; | 141 | pxa_internal_irq_chip.set_wake = fn; |
| 142 | pxa_init_low_gpio_irq(fn); | ||
| 75 | } | 143 | } |
| 76 | 144 | ||
| 77 | #ifdef CONFIG_PM | 145 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c index 18b20d469410..8b9c17142d5a 100644 --- a/arch/arm/mach-pxa/leds-idp.c +++ b/arch/arm/mach-pxa/leds-idp.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #include <asm/leds.h> | 18 | #include <asm/leds.h> |
| 19 | #include <asm/system.h> | 19 | #include <asm/system.h> |
| 20 | 20 | ||
| 21 | #include <mach/pxa-regs.h> | 21 | #include <mach/pxa25x.h> |
| 22 | #include <mach/idp.h> | 22 | #include <mach/idp.h> |
| 23 | 23 | ||
| 24 | #include "leds.h" | 24 | #include "leds.h" |
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c index 1a258029c33c..e26d5efe1969 100644 --- a/arch/arm/mach-pxa/leds-lubbock.c +++ b/arch/arm/mach-pxa/leds-lubbock.c | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 17 | #include <asm/leds.h> | 17 | #include <asm/leds.h> |
| 18 | #include <asm/system.h> | 18 | #include <asm/system.h> |
| 19 | #include <mach/pxa-regs.h> | 19 | #include <mach/pxa25x.h> |
| 20 | #include <mach/lubbock.h> | 20 | #include <mach/lubbock.h> |
| 21 | 21 | ||
| 22 | #include "leds.h" | 22 | #include "leds.h" |
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c index 95e06b849634..db4af5eee8b2 100644 --- a/arch/arm/mach-pxa/leds-mainstone.c +++ b/arch/arm/mach-pxa/leds-mainstone.c | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #include <asm/leds.h> | 16 | #include <asm/leds.h> |
| 17 | #include <asm/system.h> | 17 | #include <asm/system.h> |
| 18 | 18 | ||
| 19 | #include <mach/pxa-regs.h> | 19 | #include <mach/pxa27x.h> |
| 20 | #include <mach/mainstone.h> | 20 | #include <mach/mainstone.h> |
| 21 | 21 | ||
| 22 | #include "leds.h" | 22 | #include "leds.h" |
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 31da7f3c06f6..e13f6a81c223 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
| @@ -39,8 +39,7 @@ | |||
| 39 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
| 40 | #include <asm/mach/irq.h> | 40 | #include <asm/mach/irq.h> |
| 41 | 41 | ||
| 42 | #include <mach/pxa-regs.h> | 42 | #include <mach/pxa300.h> |
| 43 | #include <mach/mfp-pxa300.h> | ||
| 44 | #include <mach/pxafb.h> | 43 | #include <mach/pxafb.h> |
| 45 | #include <mach/ssp.h> | 44 | #include <mach/ssp.h> |
| 46 | #include <mach/pxa2xx_spi.h> | 45 | #include <mach/pxa2xx_spi.h> |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index de3f67daaacf..d64395f26a3e 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
| @@ -38,9 +38,8 @@ | |||
| 38 | #include <asm/mach/irq.h> | 38 | #include <asm/mach/irq.h> |
| 39 | #include <asm/mach/flash.h> | 39 | #include <asm/mach/flash.h> |
| 40 | 40 | ||
| 41 | #include <mach/pxa-regs.h> | 41 | #include <mach/pxa27x.h> |
| 42 | #include <mach/pxa2xx-regs.h> | 42 | #include <mach/gpio.h> |
| 43 | #include <mach/mfp-pxa27x.h> | ||
| 44 | #include <mach/lpd270.h> | 43 | #include <mach/lpd270.h> |
| 45 | #include <mach/audio.h> | 44 | #include <mach/audio.h> |
| 46 | #include <mach/pxafb.h> | 45 | #include <mach/pxafb.h> |
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index bff704354c1a..f04c8333dff7 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
| @@ -41,15 +41,15 @@ | |||
| 41 | 41 | ||
| 42 | #include <asm/hardware/sa1111.h> | 42 | #include <asm/hardware/sa1111.h> |
| 43 | 43 | ||
| 44 | #include <mach/pxa-regs.h> | 44 | #include <mach/pxa25x.h> |
| 45 | #include <mach/pxa2xx-regs.h> | 45 | #include <mach/gpio.h> |
| 46 | #include <mach/mfp-pxa25x.h> | ||
| 47 | #include <mach/audio.h> | 46 | #include <mach/audio.h> |
| 48 | #include <mach/lubbock.h> | 47 | #include <mach/lubbock.h> |
| 49 | #include <mach/udc.h> | 48 | #include <mach/udc.h> |
| 50 | #include <mach/irda.h> | 49 | #include <mach/irda.h> |
| 51 | #include <mach/pxafb.h> | 50 | #include <mach/pxafb.h> |
| 52 | #include <mach/mmc.h> | 51 | #include <mach/mmc.h> |
| 52 | #include <mach/pm.h> | ||
| 53 | 53 | ||
| 54 | #include "generic.h" | 54 | #include "generic.h" |
| 55 | #include "clock.h" | 55 | #include "clock.h" |
| @@ -113,8 +113,14 @@ static unsigned long lubbock_pin_config[] __initdata = { | |||
| 113 | GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, | 113 | GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, |
| 114 | }; | 114 | }; |
| 115 | 115 | ||
| 116 | #define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010) | ||
| 116 | #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) | 117 | #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) |
| 117 | 118 | ||
| 119 | void lubbock_set_hexled(uint32_t value) | ||
| 120 | { | ||
| 121 | LUB_HEXLED = value; | ||
| 122 | } | ||
| 123 | |||
| 118 | void lubbock_set_misc_wr(unsigned int mask, unsigned int set) | 124 | void lubbock_set_misc_wr(unsigned int mask, unsigned int set) |
| 119 | { | 125 | { |
| 120 | unsigned long flags; | 126 | unsigned long flags; |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 21b821e1a60d..d46b36746be2 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
| @@ -25,14 +25,14 @@ | |||
| 25 | #include <linux/mtd/physmap.h> | 25 | #include <linux/mtd/physmap.h> |
| 26 | #include <linux/pda_power.h> | 26 | #include <linux/pda_power.h> |
| 27 | #include <linux/pwm_backlight.h> | 27 | #include <linux/pwm_backlight.h> |
| 28 | #include <linux/usb/gpio_vbus.h> | ||
| 28 | 29 | ||
| 29 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 30 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 33 | |||
| 34 | #include <mach/pxa27x.h> | ||
| 32 | #include <mach/magician.h> | 35 | #include <mach/magician.h> |
| 33 | #include <mach/mfp-pxa27x.h> | ||
| 34 | #include <mach/pxa-regs.h> | ||
| 35 | #include <mach/pxa2xx-regs.h> | ||
| 36 | #include <mach/pxafb.h> | 36 | #include <mach/pxafb.h> |
| 37 | #include <mach/i2c.h> | 37 | #include <mach/i2c.h> |
| 38 | #include <mach/mmc.h> | 38 | #include <mach/mmc.h> |
| @@ -66,6 +66,11 @@ static unsigned long magician_pin_config[] __initdata = { | |||
| 66 | GPIO31_I2S_SYNC, | 66 | GPIO31_I2S_SYNC, |
| 67 | GPIO113_I2S_SYSCLK, | 67 | GPIO113_I2S_SYSCLK, |
| 68 | 68 | ||
| 69 | /* SSP 1 */ | ||
| 70 | GPIO23_SSP1_SCLK, | ||
| 71 | GPIO24_SSP1_SFRM, | ||
| 72 | GPIO25_SSP1_TXD, | ||
| 73 | |||
| 69 | /* SSP 2 */ | 74 | /* SSP 2 */ |
| 70 | GPIO19_SSP2_SCLK, | 75 | GPIO19_SSP2_SCLK, |
| 71 | GPIO14_SSP2_SFRM, | 76 | GPIO14_SSP2_SFRM, |
| @@ -148,22 +153,31 @@ static struct pxaficp_platform_data magician_ficp_info = { | |||
| 148 | * GPIO Keys | 153 | * GPIO Keys |
| 149 | */ | 154 | */ |
| 150 | 155 | ||
| 156 | #define INIT_KEY(_code, _gpio, _desc) \ | ||
| 157 | { \ | ||
| 158 | .code = KEY_##_code, \ | ||
| 159 | .gpio = _gpio, \ | ||
| 160 | .desc = _desc, \ | ||
| 161 | .type = EV_KEY, \ | ||
| 162 | .wakeup = 1, \ | ||
| 163 | } | ||
| 164 | |||
| 151 | static struct gpio_keys_button magician_button_table[] = { | 165 | static struct gpio_keys_button magician_button_table[] = { |
| 152 | {KEY_POWER, GPIO0_MAGICIAN_KEY_POWER, 0, "Power button"}, | 166 | INIT_KEY(POWER, GPIO0_MAGICIAN_KEY_POWER, "Power button"), |
| 153 | {KEY_ESC, GPIO37_MAGICIAN_KEY_HANGUP, 0, "Hangup button"}, | 167 | INIT_KEY(ESC, GPIO37_MAGICIAN_KEY_HANGUP, "Hangup button"), |
| 154 | {KEY_F10, GPIO38_MAGICIAN_KEY_CONTACTS, 0, "Contacts button"}, | 168 | INIT_KEY(F10, GPIO38_MAGICIAN_KEY_CONTACTS, "Contacts button"), |
| 155 | {KEY_CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, 0, "Calendar button"}, | 169 | INIT_KEY(CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, "Calendar button"), |
| 156 | {KEY_CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, 0, "Camera button"}, | 170 | INIT_KEY(CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, "Camera button"), |
| 157 | {KEY_UP, GPIO93_MAGICIAN_KEY_UP, 0, "Up button"}, | 171 | INIT_KEY(UP, GPIO93_MAGICIAN_KEY_UP, "Up button"), |
| 158 | {KEY_DOWN, GPIO94_MAGICIAN_KEY_DOWN, 0, "Down button"}, | 172 | INIT_KEY(DOWN, GPIO94_MAGICIAN_KEY_DOWN, "Down button"), |
| 159 | {KEY_LEFT, GPIO95_MAGICIAN_KEY_LEFT, 0, "Left button"}, | 173 | INIT_KEY(LEFT, GPIO95_MAGICIAN_KEY_LEFT, "Left button"), |
| 160 | {KEY_RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, 0, "Right button"}, | 174 | INIT_KEY(RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, "Right button"), |
| 161 | {KEY_KPENTER, GPIO97_MAGICIAN_KEY_ENTER, 0, "Action button"}, | 175 | INIT_KEY(KPENTER, GPIO97_MAGICIAN_KEY_ENTER, "Action button"), |
| 162 | {KEY_RECORD, GPIO98_MAGICIAN_KEY_RECORD, 0, "Record button"}, | 176 | INIT_KEY(RECORD, GPIO98_MAGICIAN_KEY_RECORD, "Record button"), |
| 163 | {KEY_VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, 0, "Volume up"}, | 177 | INIT_KEY(VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, "Volume up"), |
| 164 | {KEY_VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, 0, "Volume down"}, | 178 | INIT_KEY(VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, "Volume down"), |
| 165 | {KEY_PHONE, GPIO102_MAGICIAN_KEY_PHONE, 0, "Phone button"}, | 179 | INIT_KEY(PHONE, GPIO102_MAGICIAN_KEY_PHONE, "Phone button"), |
| 166 | {KEY_PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, 0, "Headset button"}, | 180 | INIT_KEY(PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, "Headset button"), |
| 167 | }; | 181 | }; |
| 168 | 182 | ||
| 169 | static struct gpio_keys_platform_data gpio_keys_data = { | 183 | static struct gpio_keys_platform_data gpio_keys_data = { |
| @@ -189,7 +203,7 @@ static struct platform_device gpio_keys = { | |||
| 189 | static struct resource egpio_resources[] = { | 203 | static struct resource egpio_resources[] = { |
| 190 | [0] = { | 204 | [0] = { |
| 191 | .start = PXA_CS3_PHYS, | 205 | .start = PXA_CS3_PHYS, |
| 192 | .end = PXA_CS3_PHYS + 0x20, | 206 | .end = PXA_CS3_PHYS + 0x20 - 1, |
| 193 | .flags = IORESOURCE_MEM, | 207 | .flags = IORESOURCE_MEM, |
| 194 | }, | 208 | }, |
| 195 | [1] = { | 209 | [1] = { |
| @@ -420,7 +434,7 @@ static struct gpio_led gpio_leds[] = { | |||
| 420 | }, | 434 | }, |
| 421 | { | 435 | { |
| 422 | .name = "magician::phone_bl", | 436 | .name = "magician::phone_bl", |
| 423 | .default_trigger = "none", | 437 | .default_trigger = "backlight", |
| 424 | .gpio = GPIO103_MAGICIAN_LED_KP, | 438 | .gpio = GPIO103_MAGICIAN_LED_KP, |
| 425 | }, | 439 | }, |
| 426 | }; | 440 | }; |
| @@ -468,8 +482,6 @@ static struct pasic3_led pasic3_leds[] = { | |||
| 468 | }, | 482 | }, |
| 469 | }; | 483 | }; |
| 470 | 484 | ||
| 471 | static struct platform_device pasic3; | ||
| 472 | |||
| 473 | static struct pasic3_leds_machinfo pasic3_leds_info = { | 485 | static struct pasic3_leds_machinfo pasic3_leds_info = { |
| 474 | .num_leds = ARRAY_SIZE(pasic3_leds), | 486 | .num_leds = ARRAY_SIZE(pasic3_leds), |
| 475 | .power_gpio = EGPIO_MAGICIAN_LED_POWER, | 487 | .power_gpio = EGPIO_MAGICIAN_LED_POWER, |
| @@ -511,6 +523,31 @@ static struct platform_device pasic3 = { | |||
| 511 | }; | 523 | }; |
| 512 | 524 | ||
| 513 | /* | 525 | /* |
| 526 | * USB "Transceiver" | ||
| 527 | */ | ||
| 528 | |||
| 529 | static struct resource gpio_vbus_resource = { | ||
| 530 | .flags = IORESOURCE_IRQ, | ||
| 531 | .start = IRQ_MAGICIAN_VBUS, | ||
| 532 | .end = IRQ_MAGICIAN_VBUS, | ||
| 533 | }; | ||
| 534 | |||
| 535 | static struct gpio_vbus_mach_info gpio_vbus_info = { | ||
| 536 | .gpio_pullup = GPIO27_MAGICIAN_USBC_PUEN, | ||
| 537 | .gpio_vbus = EGPIO_MAGICIAN_CABLE_STATE_USB, | ||
| 538 | }; | ||
| 539 | |||
| 540 | static struct platform_device gpio_vbus = { | ||
| 541 | .name = "gpio-vbus", | ||
| 542 | .id = -1, | ||
| 543 | .num_resources = 1, | ||
| 544 | .resource = &gpio_vbus_resource, | ||
| 545 | .dev = { | ||
| 546 | .platform_data = &gpio_vbus_info, | ||
| 547 | }, | ||
| 548 | }; | ||
| 549 | |||
| 550 | /* | ||
| 514 | * External power | 551 | * External power |
| 515 | */ | 552 | */ |
| 516 | 553 | ||
| @@ -586,15 +623,17 @@ static struct pda_power_pdata power_supply_info = { | |||
| 586 | static struct resource power_supply_resources[] = { | 623 | static struct resource power_supply_resources[] = { |
| 587 | [0] = { | 624 | [0] = { |
| 588 | .name = "ac", | 625 | .name = "ac", |
| 589 | .flags = IORESOURCE_IRQ, | 626 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | |
| 590 | .start = IRQ_MAGICIAN_AC, | 627 | IORESOURCE_IRQ_LOWEDGE, |
| 591 | .end = IRQ_MAGICIAN_AC, | 628 | .start = IRQ_MAGICIAN_VBUS, |
| 629 | .end = IRQ_MAGICIAN_VBUS, | ||
| 592 | }, | 630 | }, |
| 593 | [1] = { | 631 | [1] = { |
| 594 | .name = "usb", | 632 | .name = "usb", |
| 595 | .flags = IORESOURCE_IRQ, | 633 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | |
| 596 | .start = IRQ_MAGICIAN_AC, | 634 | IORESOURCE_IRQ_LOWEDGE, |
| 597 | .end = IRQ_MAGICIAN_AC, | 635 | .start = IRQ_MAGICIAN_VBUS, |
| 636 | .end = IRQ_MAGICIAN_VBUS, | ||
| 598 | }, | 637 | }, |
| 599 | }; | 638 | }; |
| 600 | 639 | ||
| @@ -688,11 +727,9 @@ static void magician_set_vpp(struct map_info *map, int vpp) | |||
| 688 | gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); | 727 | gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); |
| 689 | } | 728 | } |
| 690 | 729 | ||
| 691 | #define PXA_CS_SIZE 0x04000000 | ||
| 692 | |||
| 693 | static struct resource strataflash_resource = { | 730 | static struct resource strataflash_resource = { |
| 694 | .start = PXA_CS0_PHYS, | 731 | .start = PXA_CS0_PHYS, |
| 695 | .end = PXA_CS0_PHYS + PXA_CS_SIZE - 1, | 732 | .end = PXA_CS0_PHYS + SZ_64M - 1, |
| 696 | .flags = IORESOURCE_MEM, | 733 | .flags = IORESOURCE_MEM, |
| 697 | }; | 734 | }; |
| 698 | 735 | ||
| @@ -720,6 +757,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 720 | &egpio, | 757 | &egpio, |
| 721 | &backlight, | 758 | &backlight, |
| 722 | &pasic3, | 759 | &pasic3, |
| 760 | &gpio_vbus, | ||
| 723 | &power_supply, | 761 | &power_supply, |
| 724 | &strataflash, | 762 | &strataflash, |
| 725 | &leds_gpio, | 763 | &leds_gpio, |
| @@ -743,6 +781,7 @@ static void __init magician_init(void) | |||
| 743 | gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1); | 781 | gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1); |
| 744 | pxa_set_ficp_info(&magician_ficp_info); | 782 | pxa_set_ficp_info(&magician_ficp_info); |
| 745 | } | 783 | } |
| 784 | pxa27x_set_i2c_power_info(NULL); | ||
| 746 | pxa_set_i2c_info(NULL); | 785 | pxa_set_i2c_info(NULL); |
| 747 | pxa_set_mci_info(&magician_mci_info); | 786 | pxa_set_mci_info(&magician_mci_info); |
| 748 | pxa_set_ohci_info(&magician_ohci_info); | 787 | pxa_set_ohci_info(&magician_ohci_info); |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 5f224968043c..a6c8429e975f 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
| @@ -41,9 +41,8 @@ | |||
| 41 | #include <asm/mach/irq.h> | 41 | #include <asm/mach/irq.h> |
| 42 | #include <asm/mach/flash.h> | 42 | #include <asm/mach/flash.h> |
| 43 | 43 | ||
| 44 | #include <mach/pxa-regs.h> | 44 | #include <mach/pxa27x.h> |
| 45 | #include <mach/pxa2xx-regs.h> | 45 | #include <mach/gpio.h> |
| 46 | #include <mach/mfp-pxa27x.h> | ||
| 47 | #include <mach/mainstone.h> | 46 | #include <mach/mainstone.h> |
| 48 | #include <mach/audio.h> | 47 | #include <mach/audio.h> |
| 49 | #include <mach/pxafb.h> | 48 | #include <mach/pxafb.h> |
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 33626de8cbf6..7ffb91d64c39 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c | |||
| @@ -18,15 +18,12 @@ | |||
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/sysdev.h> | 19 | #include <linux/sysdev.h> |
| 20 | 20 | ||
| 21 | #include <mach/hardware.h> | 21 | #include <mach/gpio.h> |
| 22 | #include <mach/pxa-regs.h> | ||
| 23 | #include <mach/pxa2xx-regs.h> | 22 | #include <mach/pxa2xx-regs.h> |
| 24 | #include <mach/mfp-pxa2xx.h> | 23 | #include <mach/mfp-pxa2xx.h> |
| 25 | 24 | ||
| 26 | #include "generic.h" | 25 | #include "generic.h" |
| 27 | 26 | ||
| 28 | #define gpio_to_bank(gpio) ((gpio) >> 5) | ||
| 29 | |||
| 30 | #define PGSR(x) __REG2(0x40F00020, (x) << 2) | 27 | #define PGSR(x) __REG2(0x40F00020, (x) << 2) |
| 31 | #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) | 28 | #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) |
| 32 | #define GAFR_L(x) __GAFR(0, x) | 29 | #define GAFR_L(x) __GAFR(0, x) |
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index eb197a6e8e94..7a270eecd480 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c | |||
| @@ -20,183 +20,9 @@ | |||
| 20 | #include <linux/sysdev.h> | 20 | #include <linux/sysdev.h> |
| 21 | 21 | ||
| 22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 23 | #include <mach/mfp.h> | ||
| 24 | #include <mach/mfp-pxa3xx.h> | 23 | #include <mach/mfp-pxa3xx.h> |
| 25 | #include <mach/pxa3xx-regs.h> | 24 | #include <mach/pxa3xx-regs.h> |
| 26 | 25 | ||
| 27 | /* mfp_spin_lock is used to ensure that MFP register configuration | ||
| 28 | * (most likely a read-modify-write operation) is atomic, and that | ||
| 29 | * mfp_table[] is consistent | ||
| 30 | */ | ||
| 31 | static DEFINE_SPINLOCK(mfp_spin_lock); | ||
| 32 | |||
| 33 | static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE); | ||
| 34 | |||
| 35 | struct pxa3xx_mfp_pin { | ||
| 36 | unsigned long config; /* -1 for not configured */ | ||
| 37 | unsigned long mfpr_off; /* MFPRxx Register offset */ | ||
| 38 | unsigned long mfpr_run; /* Run-Mode Register Value */ | ||
| 39 | unsigned long mfpr_lpm; /* Low Power Mode Register Value */ | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; | ||
| 43 | |||
| 44 | /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ | ||
| 45 | static const unsigned long mfpr_lpm[] = { | ||
| 46 | MFPR_LPM_INPUT, | ||
| 47 | MFPR_LPM_DRIVE_LOW, | ||
| 48 | MFPR_LPM_DRIVE_HIGH, | ||
| 49 | MFPR_LPM_PULL_LOW, | ||
| 50 | MFPR_LPM_PULL_HIGH, | ||
| 51 | MFPR_LPM_FLOAT, | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ | ||
| 55 | static const unsigned long mfpr_pull[] = { | ||
| 56 | MFPR_PULL_NONE, | ||
| 57 | MFPR_PULL_LOW, | ||
| 58 | MFPR_PULL_HIGH, | ||
| 59 | MFPR_PULL_BOTH, | ||
| 60 | }; | ||
| 61 | |||
| 62 | /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ | ||
| 63 | static const unsigned long mfpr_edge[] = { | ||
| 64 | MFPR_EDGE_NONE, | ||
| 65 | MFPR_EDGE_RISE, | ||
| 66 | MFPR_EDGE_FALL, | ||
| 67 | MFPR_EDGE_BOTH, | ||
| 68 | }; | ||
| 69 | |||
| 70 | #define mfpr_readl(off) \ | ||
| 71 | __raw_readl(mfpr_mmio_base + (off)) | ||
| 72 | |||
| 73 | #define mfpr_writel(off, val) \ | ||
| 74 | __raw_writel(val, mfpr_mmio_base + (off)) | ||
| 75 | |||
| 76 | #define mfp_configured(p) ((p)->config != -1) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * perform a read-back of any MFPR register to make sure the | ||
| 80 | * previous writings are finished | ||
| 81 | */ | ||
| 82 | #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) | ||
| 83 | |||
| 84 | static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p) | ||
| 85 | { | ||
| 86 | if (mfp_configured(p)) | ||
| 87 | mfpr_writel(p->mfpr_off, p->mfpr_run); | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p) | ||
| 91 | { | ||
| 92 | if (mfp_configured(p)) { | ||
| 93 | unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR; | ||
| 94 | if (mfpr_clr != p->mfpr_run) | ||
| 95 | mfpr_writel(p->mfpr_off, mfpr_clr); | ||
| 96 | if (p->mfpr_lpm != mfpr_clr) | ||
| 97 | mfpr_writel(p->mfpr_off, p->mfpr_lpm); | ||
| 98 | } | ||
| 99 | } | ||
| 100 | |||
| 101 | void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num) | ||
| 102 | { | ||
| 103 | unsigned long flags; | ||
| 104 | int i; | ||
| 105 | |||
| 106 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 107 | |||
| 108 | for (i = 0; i < num; i++, mfp_cfgs++) { | ||
| 109 | unsigned long tmp, c = *mfp_cfgs; | ||
| 110 | struct pxa3xx_mfp_pin *p; | ||
| 111 | int pin, af, drv, lpm, edge, pull; | ||
| 112 | |||
| 113 | pin = MFP_PIN(c); | ||
| 114 | BUG_ON(pin >= MFP_PIN_MAX); | ||
| 115 | p = &mfp_table[pin]; | ||
| 116 | |||
| 117 | af = MFP_AF(c); | ||
| 118 | drv = MFP_DS(c); | ||
| 119 | lpm = MFP_LPM_STATE(c); | ||
| 120 | edge = MFP_LPM_EDGE(c); | ||
| 121 | pull = MFP_PULL(c); | ||
| 122 | |||
| 123 | /* run-mode pull settings will conflict with MFPR bits of | ||
| 124 | * low power mode state, calculate mfpr_run and mfpr_lpm | ||
| 125 | * individually if pull != MFP_PULL_NONE | ||
| 126 | */ | ||
| 127 | tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); | ||
| 128 | |||
| 129 | if (likely(pull == MFP_PULL_NONE)) { | ||
| 130 | p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 131 | p->mfpr_lpm = p->mfpr_run; | ||
| 132 | } else { | ||
| 133 | p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 134 | p->mfpr_run = tmp | mfpr_pull[pull]; | ||
| 135 | } | ||
| 136 | |||
| 137 | p->config = c; __mfp_config_run(p); | ||
| 138 | } | ||
| 139 | |||
| 140 | mfpr_sync(); | ||
| 141 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 142 | } | ||
| 143 | |||
| 144 | unsigned long pxa3xx_mfp_read(int mfp) | ||
| 145 | { | ||
| 146 | unsigned long val, flags; | ||
| 147 | |||
| 148 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 149 | |||
| 150 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 151 | val = mfpr_readl(mfp_table[mfp].mfpr_off); | ||
| 152 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 153 | |||
| 154 | return val; | ||
| 155 | } | ||
| 156 | |||
| 157 | void pxa3xx_mfp_write(int mfp, unsigned long val) | ||
| 158 | { | ||
| 159 | unsigned long flags; | ||
| 160 | |||
| 161 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 162 | |||
| 163 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 164 | mfpr_writel(mfp_table[mfp].mfpr_off, val); | ||
| 165 | mfpr_sync(); | ||
| 166 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 167 | } | ||
| 168 | |||
| 169 | void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) | ||
| 170 | { | ||
| 171 | struct pxa3xx_mfp_addr_map *p; | ||
| 172 | unsigned long offset, flags; | ||
| 173 | int i; | ||
| 174 | |||
| 175 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 176 | |||
| 177 | for (p = map; p->start != MFP_PIN_INVALID; p++) { | ||
| 178 | offset = p->offset; | ||
| 179 | i = p->start; | ||
| 180 | |||
| 181 | do { | ||
| 182 | mfp_table[i].mfpr_off = offset; | ||
| 183 | mfp_table[i].mfpr_run = 0; | ||
| 184 | mfp_table[i].mfpr_lpm = 0; | ||
| 185 | offset += 4; i++; | ||
| 186 | } while ((i <= p->end) && (p->end != -1)); | ||
| 187 | } | ||
| 188 | |||
| 189 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 190 | } | ||
| 191 | |||
| 192 | void __init pxa3xx_init_mfp(void) | ||
| 193 | { | ||
| 194 | int i; | ||
| 195 | |||
| 196 | for (i = 0; i < ARRAY_SIZE(mfp_table); i++) | ||
| 197 | mfp_table[i].config = -1; | ||
| 198 | } | ||
| 199 | |||
| 200 | #ifdef CONFIG_PM | 26 | #ifdef CONFIG_PM |
| 201 | /* | 27 | /* |
| 202 | * Configure the MFPs appropriately for suspend/resume. | 28 | * Configure the MFPs appropriately for suspend/resume. |
| @@ -207,23 +33,13 @@ void __init pxa3xx_init_mfp(void) | |||
| 207 | */ | 33 | */ |
| 208 | static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) | 34 | static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) |
| 209 | { | 35 | { |
| 210 | int pin; | 36 | mfp_config_lpm(); |
| 211 | |||
| 212 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) { | ||
| 213 | struct pxa3xx_mfp_pin *p = &mfp_table[pin]; | ||
| 214 | __mfp_config_lpm(p); | ||
| 215 | } | ||
| 216 | return 0; | 37 | return 0; |
| 217 | } | 38 | } |
| 218 | 39 | ||
| 219 | static int pxa3xx_mfp_resume(struct sys_device *d) | 40 | static int pxa3xx_mfp_resume(struct sys_device *d) |
| 220 | { | 41 | { |
| 221 | int pin; | 42 | mfp_config_run(); |
| 222 | |||
| 223 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) { | ||
| 224 | struct pxa3xx_mfp_pin *p = &mfp_table[pin]; | ||
| 225 | __mfp_config_run(p); | ||
| 226 | } | ||
| 227 | 43 | ||
| 228 | /* clear RDH bit when MFP settings are restored | 44 | /* clear RDH bit when MFP settings are restored |
| 229 | * | 45 | * |
| @@ -231,7 +47,6 @@ static int pxa3xx_mfp_resume(struct sys_device *d) | |||
| 231 | * preserve them here in case they will be referenced later | 47 | * preserve them here in case they will be referenced later |
| 232 | */ | 48 | */ |
| 233 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); | 49 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); |
| 234 | |||
| 235 | return 0; | 50 | return 0; |
| 236 | } | 51 | } |
| 237 | #else | 52 | #else |
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 2b427e015b6f..97c93a7a285c 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c | |||
| @@ -36,13 +36,15 @@ | |||
| 36 | #include <linux/power_supply.h> | 36 | #include <linux/power_supply.h> |
| 37 | #include <linux/wm97xx_batt.h> | 37 | #include <linux/wm97xx_batt.h> |
| 38 | #include <linux/mtd/physmap.h> | 38 | #include <linux/mtd/physmap.h> |
| 39 | #include <linux/usb/gpio_vbus.h> | ||
| 39 | 40 | ||
| 40 | #include <asm/mach-types.h> | 41 | #include <asm/mach-types.h> |
| 41 | #include <asm/mach/arch.h> | 42 | #include <asm/mach/arch.h> |
| 42 | #include <mach/mfp-pxa27x.h> | 43 | |
| 44 | #include <mach/pxa27x.h> | ||
| 45 | #include <mach/regs-rtc.h> | ||
| 43 | #include <mach/pxa27x_keypad.h> | 46 | #include <mach/pxa27x_keypad.h> |
| 44 | #include <mach/pxafb.h> | 47 | #include <mach/pxafb.h> |
| 45 | #include <mach/pxa2xx-regs.h> | ||
| 46 | #include <mach/mmc.h> | 48 | #include <mach/mmc.h> |
| 47 | #include <mach/udc.h> | 49 | #include <mach/udc.h> |
| 48 | #include <mach/pxa27x-udc.h> | 50 | #include <mach/pxa27x-udc.h> |
| @@ -411,21 +413,6 @@ static void gsm_exit(void) | |||
| 411 | /* | 413 | /* |
| 412 | * USB UDC | 414 | * USB UDC |
| 413 | */ | 415 | */ |
| 414 | static void udc_power_command(int cmd) | ||
| 415 | { | ||
| 416 | switch (cmd) { | ||
| 417 | case PXA2XX_UDC_CMD_DISCONNECT: | ||
| 418 | gpio_set_value(GPIO22_USB_ENABLE, 0); | ||
| 419 | break; | ||
| 420 | case PXA2XX_UDC_CMD_CONNECT: | ||
| 421 | gpio_set_value(GPIO22_USB_ENABLE, 1); | ||
| 422 | break; | ||
| 423 | default: | ||
| 424 | printk(KERN_INFO "udc_control: unknown command (0x%x)!\n", cmd); | ||
| 425 | break; | ||
| 426 | } | ||
| 427 | } | ||
| 428 | |||
| 429 | static int is_usb_connected(void) | 416 | static int is_usb_connected(void) |
| 430 | { | 417 | { |
| 431 | return !gpio_get_value(GPIO13_nUSB_DETECT); | 418 | return !gpio_get_value(GPIO13_nUSB_DETECT); |
| @@ -433,24 +420,15 @@ static int is_usb_connected(void) | |||
| 433 | 420 | ||
| 434 | static struct pxa2xx_udc_mach_info mioa701_udc_info = { | 421 | static struct pxa2xx_udc_mach_info mioa701_udc_info = { |
| 435 | .udc_is_connected = is_usb_connected, | 422 | .udc_is_connected = is_usb_connected, |
| 436 | .udc_command = udc_power_command, | 423 | .gpio_pullup = GPIO22_USB_ENABLE, |
| 437 | }; | 424 | }; |
| 438 | 425 | ||
| 439 | struct gpio_ress udc_gpios[] = { | 426 | struct gpio_vbus_mach_info gpio_vbus_data = { |
| 440 | MIO_GPIO_OUT(GPIO22_USB_ENABLE, 0, "USB Vbus enable") | 427 | .gpio_vbus = GPIO13_nUSB_DETECT, |
| 428 | .gpio_vbus_inverted = 1, | ||
| 429 | .gpio_pullup = -1, | ||
| 441 | }; | 430 | }; |
| 442 | 431 | ||
| 443 | static int __init udc_init(void) | ||
| 444 | { | ||
| 445 | pxa_set_udc_info(&mioa701_udc_info); | ||
| 446 | return mio_gpio_request(ARRAY_AND_SIZE(udc_gpios)); | ||
| 447 | } | ||
| 448 | |||
| 449 | static void udc_exit(void) | ||
| 450 | { | ||
| 451 | mio_gpio_free(ARRAY_AND_SIZE(udc_gpios)); | ||
| 452 | } | ||
| 453 | |||
| 454 | /* | 432 | /* |
| 455 | * SDIO/MMC Card controller | 433 | * SDIO/MMC Card controller |
| 456 | */ | 434 | */ |
| @@ -789,6 +767,7 @@ MIO_SIMPLE_DEV(pxa2xx_ac97, "pxa2xx-ac97", NULL) | |||
| 789 | MIO_PARENT_DEV(mio_wm9713_codec, "wm9713-codec", &pxa2xx_ac97.dev, NULL) | 767 | MIO_PARENT_DEV(mio_wm9713_codec, "wm9713-codec", &pxa2xx_ac97.dev, NULL) |
| 790 | MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL) | 768 | MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL) |
| 791 | MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL) | 769 | MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL) |
| 770 | MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data); | ||
| 792 | 771 | ||
| 793 | static struct platform_device *devices[] __initdata = { | 772 | static struct platform_device *devices[] __initdata = { |
| 794 | &mioa701_gpio_keys, | 773 | &mioa701_gpio_keys, |
| @@ -800,7 +779,8 @@ static struct platform_device *devices[] __initdata = { | |||
| 800 | &mioa701_sound, | 779 | &mioa701_sound, |
| 801 | &power_dev, | 780 | &power_dev, |
| 802 | &strataflash, | 781 | &strataflash, |
| 803 | &mioa701_board | 782 | &gpio_vbus, |
| 783 | &mioa701_board, | ||
| 804 | }; | 784 | }; |
| 805 | 785 | ||
| 806 | static void mioa701_machine_exit(void); | 786 | static void mioa701_machine_exit(void); |
| @@ -808,13 +788,13 @@ static void mioa701_machine_exit(void); | |||
| 808 | static void mioa701_poweroff(void) | 788 | static void mioa701_poweroff(void) |
| 809 | { | 789 | { |
| 810 | mioa701_machine_exit(); | 790 | mioa701_machine_exit(); |
| 811 | arm_machine_restart('s'); | 791 | arm_machine_restart('s', NULL); |
| 812 | } | 792 | } |
| 813 | 793 | ||
| 814 | static void mioa701_restart(char c) | 794 | static void mioa701_restart(char c, const char *cmd) |
| 815 | { | 795 | { |
| 816 | mioa701_machine_exit(); | 796 | mioa701_machine_exit(); |
| 817 | arm_machine_restart('s'); | 797 | arm_machine_restart('s', cmd); |
| 818 | } | 798 | } |
| 819 | 799 | ||
| 820 | struct gpio_ress global_gpios[] = { | 800 | struct gpio_ress global_gpios[] = { |
| @@ -837,7 +817,7 @@ static void __init mioa701_machine_init(void) | |||
| 837 | pxa_set_mci_info(&mioa701_mci_info); | 817 | pxa_set_mci_info(&mioa701_mci_info); |
| 838 | pxa_set_keypad_info(&mioa701_keypad_info); | 818 | pxa_set_keypad_info(&mioa701_keypad_info); |
| 839 | wm97xx_bat_set_pdata(&mioa701_battery_data); | 819 | wm97xx_bat_set_pdata(&mioa701_battery_data); |
| 840 | udc_init(); | 820 | pxa_set_udc_info(&mioa701_udc_info); |
| 841 | pm_power_off = mioa701_poweroff; | 821 | pm_power_off = mioa701_poweroff; |
| 842 | arm_pm_restart = mioa701_restart; | 822 | arm_pm_restart = mioa701_restart; |
| 843 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 823 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| @@ -850,7 +830,6 @@ static void __init mioa701_machine_init(void) | |||
| 850 | 830 | ||
| 851 | static void mioa701_machine_exit(void) | 831 | static void mioa701_machine_exit(void) |
| 852 | { | 832 | { |
| 853 | udc_exit(); | ||
| 854 | bootstrap_exit(); | 833 | bootstrap_exit(); |
| 855 | gsm_exit(); | 834 | gsm_exit(); |
| 856 | } | 835 | } |
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index 8a73814126b1..a65713ce019e 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c | |||
| @@ -19,10 +19,10 @@ | |||
| 19 | #include <linux/types.h> | 19 | #include <linux/types.h> |
| 20 | #include <linux/usb/isp116x.h> | 20 | #include <linux/usb/isp116x.h> |
| 21 | 21 | ||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | |||
| 25 | #include <mach/pxa25x.h> | ||
| 26 | #include "generic.h" | 26 | #include "generic.h" |
| 27 | 27 | ||
| 28 | static void isp116x_pfm_delay(struct device *dev, int delay) | 28 | static void isp116x_pfm_delay(struct device *dev, int delay) |
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c new file mode 100644 index 000000000000..8587477a9bb7 --- /dev/null +++ b/arch/arm/mach-pxa/palmld.c | |||
| @@ -0,0 +1,565 @@ | |||
| 1 | /* | ||
| 2 | * Hardware definitions for Palm LifeDrive | ||
| 3 | * | ||
| 4 | * Author: Marek Vasut <marek.vasut@gmail.com> | ||
| 5 | * | ||
| 6 | * Based on work of: | ||
| 7 | * Alex Osborne <ato@meshy.org> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * (find more info at www.hackndev.com) | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/gpio_keys.h> | ||
| 21 | #include <linux/input.h> | ||
| 22 | #include <linux/pda_power.h> | ||
| 23 | #include <linux/pwm_backlight.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/wm97xx_batt.h> | ||
| 26 | #include <linux/power_supply.h> | ||
| 27 | |||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/map.h> | ||
| 31 | |||
| 32 | #include <mach/pxa27x.h> | ||
| 33 | #include <mach/audio.h> | ||
| 34 | #include <mach/palmld.h> | ||
| 35 | #include <mach/mmc.h> | ||
| 36 | #include <mach/pxafb.h> | ||
| 37 | #include <mach/irda.h> | ||
| 38 | #include <mach/pxa27x_keypad.h> | ||
| 39 | #include <mach/palmasoc.h> | ||
| 40 | |||
| 41 | #include "generic.h" | ||
| 42 | #include "devices.h" | ||
| 43 | |||
| 44 | /****************************************************************************** | ||
| 45 | * Pin configuration | ||
| 46 | ******************************************************************************/ | ||
| 47 | static unsigned long palmld_pin_config[] __initdata = { | ||
| 48 | /* MMC */ | ||
| 49 | GPIO32_MMC_CLK, | ||
| 50 | GPIO92_MMC_DAT_0, | ||
| 51 | GPIO109_MMC_DAT_1, | ||
| 52 | GPIO110_MMC_DAT_2, | ||
| 53 | GPIO111_MMC_DAT_3, | ||
| 54 | GPIO112_MMC_CMD, | ||
| 55 | GPIO14_GPIO, /* SD detect */ | ||
| 56 | GPIO114_GPIO, /* SD power */ | ||
| 57 | GPIO116_GPIO, /* SD r/o switch */ | ||
| 58 | |||
| 59 | /* AC97 */ | ||
| 60 | GPIO28_AC97_BITCLK, | ||
| 61 | GPIO29_AC97_SDATA_IN_0, | ||
| 62 | GPIO30_AC97_SDATA_OUT, | ||
| 63 | GPIO31_AC97_SYNC, | ||
| 64 | |||
| 65 | /* IrDA */ | ||
| 66 | GPIO108_GPIO, /* ir disable */ | ||
| 67 | GPIO46_FICP_RXD, | ||
| 68 | GPIO47_FICP_TXD, | ||
| 69 | |||
| 70 | /* MATRIX KEYPAD */ | ||
| 71 | GPIO100_KP_MKIN_0, | ||
| 72 | GPIO101_KP_MKIN_1, | ||
| 73 | GPIO102_KP_MKIN_2, | ||
| 74 | GPIO97_KP_MKIN_3, | ||
| 75 | GPIO103_KP_MKOUT_0, | ||
| 76 | GPIO104_KP_MKOUT_1, | ||
| 77 | GPIO105_KP_MKOUT_2, | ||
| 78 | |||
| 79 | /* LCD */ | ||
| 80 | GPIO58_LCD_LDD_0, | ||
| 81 | GPIO59_LCD_LDD_1, | ||
| 82 | GPIO60_LCD_LDD_2, | ||
| 83 | GPIO61_LCD_LDD_3, | ||
| 84 | GPIO62_LCD_LDD_4, | ||
| 85 | GPIO63_LCD_LDD_5, | ||
| 86 | GPIO64_LCD_LDD_6, | ||
| 87 | GPIO65_LCD_LDD_7, | ||
| 88 | GPIO66_LCD_LDD_8, | ||
| 89 | GPIO67_LCD_LDD_9, | ||
| 90 | GPIO68_LCD_LDD_10, | ||
| 91 | GPIO69_LCD_LDD_11, | ||
| 92 | GPIO70_LCD_LDD_12, | ||
| 93 | GPIO71_LCD_LDD_13, | ||
| 94 | GPIO72_LCD_LDD_14, | ||
| 95 | GPIO73_LCD_LDD_15, | ||
| 96 | GPIO74_LCD_FCLK, | ||
| 97 | GPIO75_LCD_LCLK, | ||
| 98 | GPIO76_LCD_PCLK, | ||
| 99 | GPIO77_LCD_BIAS, | ||
| 100 | |||
| 101 | /* PWM */ | ||
| 102 | GPIO16_PWM0_OUT, | ||
| 103 | |||
| 104 | /* GPIO KEYS */ | ||
| 105 | GPIO10_GPIO, /* hotsync button */ | ||
| 106 | GPIO12_GPIO, /* power switch */ | ||
| 107 | GPIO15_GPIO, /* lock switch */ | ||
| 108 | |||
| 109 | /* LEDs */ | ||
| 110 | GPIO52_GPIO, /* green led */ | ||
| 111 | GPIO94_GPIO, /* orange led */ | ||
| 112 | |||
| 113 | /* PCMCIA */ | ||
| 114 | GPIO48_nPOE, | ||
| 115 | GPIO49_nPWE, | ||
| 116 | GPIO50_nPIOR, | ||
| 117 | GPIO51_nPIOW, | ||
| 118 | GPIO85_nPCE_1, | ||
| 119 | GPIO54_nPCE_2, | ||
| 120 | GPIO79_PSKTSEL, | ||
| 121 | GPIO55_nPREG, | ||
| 122 | GPIO56_nPWAIT, | ||
| 123 | GPIO57_nIOIS16, | ||
| 124 | GPIO36_GPIO, /* wifi power */ | ||
| 125 | GPIO38_GPIO, /* wifi ready */ | ||
| 126 | GPIO81_GPIO, /* wifi reset */ | ||
| 127 | |||
| 128 | /* HDD */ | ||
| 129 | GPIO95_GPIO, /* HDD irq */ | ||
| 130 | GPIO115_GPIO, /* HDD power */ | ||
| 131 | |||
| 132 | /* MISC */ | ||
| 133 | GPIO13_GPIO, /* earphone detect */ | ||
| 134 | }; | ||
| 135 | |||
| 136 | /****************************************************************************** | ||
| 137 | * SD/MMC card controller | ||
| 138 | ******************************************************************************/ | ||
| 139 | static int palmld_mci_init(struct device *dev, irq_handler_t palmld_detect_int, | ||
| 140 | void *data) | ||
| 141 | { | ||
| 142 | int err = 0; | ||
| 143 | |||
| 144 | /* Setup an interrupt for detecting card insert/remove events */ | ||
| 145 | err = gpio_request(GPIO_NR_PALMLD_SD_DETECT_N, "SD IRQ"); | ||
| 146 | if (err) | ||
| 147 | goto err; | ||
| 148 | err = gpio_direction_input(GPIO_NR_PALMLD_SD_DETECT_N); | ||
| 149 | if (err) | ||
| 150 | goto err2; | ||
| 151 | err = request_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), | ||
| 152 | palmld_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | | ||
| 153 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
| 154 | "SD/MMC card detect", data); | ||
| 155 | if (err) { | ||
| 156 | printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", | ||
| 157 | __func__); | ||
| 158 | goto err2; | ||
| 159 | } | ||
| 160 | |||
| 161 | err = gpio_request(GPIO_NR_PALMLD_SD_POWER, "SD_POWER"); | ||
| 162 | if (err) | ||
| 163 | goto err3; | ||
| 164 | err = gpio_direction_output(GPIO_NR_PALMLD_SD_POWER, 0); | ||
| 165 | if (err) | ||
| 166 | goto err4; | ||
| 167 | |||
| 168 | err = gpio_request(GPIO_NR_PALMLD_SD_READONLY, "SD_READONLY"); | ||
| 169 | if (err) | ||
| 170 | goto err4; | ||
| 171 | err = gpio_direction_input(GPIO_NR_PALMLD_SD_READONLY); | ||
| 172 | if (err) | ||
| 173 | goto err5; | ||
| 174 | |||
| 175 | printk(KERN_DEBUG "%s: irq registered\n", __func__); | ||
| 176 | |||
| 177 | return 0; | ||
| 178 | |||
| 179 | err5: | ||
| 180 | gpio_free(GPIO_NR_PALMLD_SD_READONLY); | ||
| 181 | err4: | ||
| 182 | gpio_free(GPIO_NR_PALMLD_SD_POWER); | ||
| 183 | err3: | ||
| 184 | free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data); | ||
| 185 | err2: | ||
| 186 | gpio_free(GPIO_NR_PALMLD_SD_DETECT_N); | ||
| 187 | err: | ||
| 188 | return err; | ||
| 189 | } | ||
| 190 | |||
| 191 | static void palmld_mci_exit(struct device *dev, void *data) | ||
| 192 | { | ||
| 193 | gpio_free(GPIO_NR_PALMLD_SD_READONLY); | ||
| 194 | gpio_free(GPIO_NR_PALMLD_SD_POWER); | ||
| 195 | free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data); | ||
| 196 | gpio_free(GPIO_NR_PALMLD_SD_DETECT_N); | ||
| 197 | } | ||
| 198 | |||
| 199 | static void palmld_mci_power(struct device *dev, unsigned int vdd) | ||
| 200 | { | ||
| 201 | struct pxamci_platform_data *p_d = dev->platform_data; | ||
| 202 | gpio_set_value(GPIO_NR_PALMLD_SD_POWER, p_d->ocr_mask & (1 << vdd)); | ||
| 203 | } | ||
| 204 | |||
| 205 | static int palmld_mci_get_ro(struct device *dev) | ||
| 206 | { | ||
| 207 | return gpio_get_value(GPIO_NR_PALMLD_SD_READONLY); | ||
| 208 | } | ||
| 209 | |||
| 210 | static struct pxamci_platform_data palmld_mci_platform_data = { | ||
| 211 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 212 | .setpower = palmld_mci_power, | ||
| 213 | .get_ro = palmld_mci_get_ro, | ||
| 214 | .init = palmld_mci_init, | ||
| 215 | .exit = palmld_mci_exit, | ||
| 216 | }; | ||
| 217 | |||
| 218 | /****************************************************************************** | ||
| 219 | * GPIO keyboard | ||
| 220 | ******************************************************************************/ | ||
| 221 | static unsigned int palmld_matrix_keys[] = { | ||
| 222 | KEY(0, 1, KEY_F2), | ||
| 223 | KEY(0, 2, KEY_UP), | ||
| 224 | |||
| 225 | KEY(1, 0, KEY_F3), | ||
| 226 | KEY(1, 1, KEY_F4), | ||
| 227 | KEY(1, 2, KEY_RIGHT), | ||
| 228 | |||
| 229 | KEY(2, 0, KEY_F1), | ||
| 230 | KEY(2, 1, KEY_F5), | ||
| 231 | KEY(2, 2, KEY_DOWN), | ||
| 232 | |||
| 233 | KEY(3, 0, KEY_F6), | ||
| 234 | KEY(3, 1, KEY_ENTER), | ||
| 235 | KEY(3, 2, KEY_LEFT), | ||
| 236 | }; | ||
| 237 | |||
| 238 | static struct pxa27x_keypad_platform_data palmld_keypad_platform_data = { | ||
| 239 | .matrix_key_rows = 4, | ||
| 240 | .matrix_key_cols = 3, | ||
| 241 | .matrix_key_map = palmld_matrix_keys, | ||
| 242 | .matrix_key_map_size = ARRAY_SIZE(palmld_matrix_keys), | ||
| 243 | |||
| 244 | .debounce_interval = 30, | ||
| 245 | }; | ||
| 246 | |||
| 247 | /****************************************************************************** | ||
| 248 | * GPIO keys | ||
| 249 | ******************************************************************************/ | ||
| 250 | static struct gpio_keys_button palmld_pxa_buttons[] = { | ||
| 251 | {KEY_F8, GPIO_NR_PALMLD_HOTSYNC_BUTTON_N, 1, "HotSync Button" }, | ||
| 252 | {KEY_F9, GPIO_NR_PALMLD_LOCK_SWITCH, 0, "Lock Switch" }, | ||
| 253 | {KEY_POWER, GPIO_NR_PALMLD_POWER_SWITCH, 0, "Power Switch" }, | ||
| 254 | }; | ||
| 255 | |||
| 256 | static struct gpio_keys_platform_data palmld_pxa_keys_data = { | ||
| 257 | .buttons = palmld_pxa_buttons, | ||
| 258 | .nbuttons = ARRAY_SIZE(palmld_pxa_buttons), | ||
| 259 | }; | ||
| 260 | |||
| 261 | static struct platform_device palmld_pxa_keys = { | ||
| 262 | .name = "gpio-keys", | ||
| 263 | .id = -1, | ||
| 264 | .dev = { | ||
| 265 | .platform_data = &palmld_pxa_keys_data, | ||
| 266 | }, | ||
| 267 | }; | ||
| 268 | |||
| 269 | /****************************************************************************** | ||
| 270 | * Backlight | ||
| 271 | ******************************************************************************/ | ||
| 272 | static int palmld_backlight_init(struct device *dev) | ||
| 273 | { | ||
| 274 | int ret; | ||
| 275 | |||
| 276 | ret = gpio_request(GPIO_NR_PALMLD_BL_POWER, "BL POWER"); | ||
| 277 | if (ret) | ||
| 278 | goto err; | ||
| 279 | ret = gpio_direction_output(GPIO_NR_PALMLD_BL_POWER, 0); | ||
| 280 | if (ret) | ||
| 281 | goto err2; | ||
| 282 | ret = gpio_request(GPIO_NR_PALMLD_LCD_POWER, "LCD POWER"); | ||
| 283 | if (ret) | ||
| 284 | goto err2; | ||
| 285 | ret = gpio_direction_output(GPIO_NR_PALMLD_LCD_POWER, 0); | ||
| 286 | if (ret) | ||
| 287 | goto err3; | ||
| 288 | |||
| 289 | return 0; | ||
| 290 | err3: | ||
| 291 | gpio_free(GPIO_NR_PALMLD_LCD_POWER); | ||
| 292 | err2: | ||
| 293 | gpio_free(GPIO_NR_PALMLD_BL_POWER); | ||
| 294 | err: | ||
| 295 | return ret; | ||
| 296 | } | ||
| 297 | |||
| 298 | static int palmld_backlight_notify(int brightness) | ||
| 299 | { | ||
| 300 | gpio_set_value(GPIO_NR_PALMLD_BL_POWER, brightness); | ||
| 301 | gpio_set_value(GPIO_NR_PALMLD_LCD_POWER, brightness); | ||
| 302 | return brightness; | ||
| 303 | } | ||
| 304 | |||
| 305 | static void palmld_backlight_exit(struct device *dev) | ||
| 306 | { | ||
| 307 | gpio_free(GPIO_NR_PALMLD_BL_POWER); | ||
| 308 | gpio_free(GPIO_NR_PALMLD_LCD_POWER); | ||
| 309 | } | ||
| 310 | |||
| 311 | static struct platform_pwm_backlight_data palmld_backlight_data = { | ||
| 312 | .pwm_id = 0, | ||
| 313 | .max_brightness = PALMLD_MAX_INTENSITY, | ||
| 314 | .dft_brightness = PALMLD_MAX_INTENSITY, | ||
| 315 | .pwm_period_ns = PALMLD_PERIOD_NS, | ||
| 316 | .init = palmld_backlight_init, | ||
| 317 | .notify = palmld_backlight_notify, | ||
| 318 | .exit = palmld_backlight_exit, | ||
| 319 | }; | ||
| 320 | |||
| 321 | static struct platform_device palmld_backlight = { | ||
| 322 | .name = "pwm-backlight", | ||
| 323 | .dev = { | ||
| 324 | .parent = &pxa27x_device_pwm0.dev, | ||
| 325 | .platform_data = &palmld_backlight_data, | ||
| 326 | }, | ||
| 327 | }; | ||
| 328 | |||
| 329 | /****************************************************************************** | ||
| 330 | * IrDA | ||
| 331 | ******************************************************************************/ | ||
| 332 | static int palmld_irda_startup(struct device *dev) | ||
| 333 | { | ||
| 334 | int err; | ||
| 335 | err = gpio_request(GPIO_NR_PALMLD_IR_DISABLE, "IR DISABLE"); | ||
| 336 | if (err) | ||
| 337 | goto err; | ||
| 338 | err = gpio_direction_output(GPIO_NR_PALMLD_IR_DISABLE, 1); | ||
| 339 | if (err) | ||
| 340 | gpio_free(GPIO_NR_PALMLD_IR_DISABLE); | ||
| 341 | err: | ||
| 342 | return err; | ||
| 343 | } | ||
| 344 | |||
| 345 | static void palmld_irda_shutdown(struct device *dev) | ||
| 346 | { | ||
| 347 | gpio_free(GPIO_NR_PALMLD_IR_DISABLE); | ||
| 348 | } | ||
| 349 | |||
| 350 | static void palmld_irda_transceiver_mode(struct device *dev, int mode) | ||
| 351 | { | ||
| 352 | gpio_set_value(GPIO_NR_PALMLD_IR_DISABLE, mode & IR_OFF); | ||
| 353 | pxa2xx_transceiver_mode(dev, mode); | ||
| 354 | } | ||
| 355 | |||
| 356 | static struct pxaficp_platform_data palmld_ficp_platform_data = { | ||
| 357 | .startup = palmld_irda_startup, | ||
| 358 | .shutdown = palmld_irda_shutdown, | ||
| 359 | .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, | ||
| 360 | .transceiver_mode = palmld_irda_transceiver_mode, | ||
| 361 | }; | ||
| 362 | |||
| 363 | /****************************************************************************** | ||
| 364 | * LEDs | ||
| 365 | ******************************************************************************/ | ||
| 366 | struct gpio_led gpio_leds[] = { | ||
| 367 | { | ||
| 368 | .name = "palmld:green:led", | ||
| 369 | .default_trigger = "none", | ||
| 370 | .gpio = GPIO_NR_PALMLD_LED_GREEN, | ||
| 371 | }, { | ||
| 372 | .name = "palmld:amber:led", | ||
| 373 | .default_trigger = "none", | ||
| 374 | .gpio = GPIO_NR_PALMLD_LED_AMBER, | ||
| 375 | }, | ||
| 376 | }; | ||
| 377 | |||
| 378 | static struct gpio_led_platform_data gpio_led_info = { | ||
| 379 | .leds = gpio_leds, | ||
| 380 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 381 | }; | ||
| 382 | |||
| 383 | static struct platform_device palmld_leds = { | ||
| 384 | .name = "leds-gpio", | ||
| 385 | .id = -1, | ||
| 386 | .dev = { | ||
| 387 | .platform_data = &gpio_led_info, | ||
| 388 | } | ||
| 389 | }; | ||
| 390 | |||
| 391 | /****************************************************************************** | ||
| 392 | * Power supply | ||
| 393 | ******************************************************************************/ | ||
| 394 | static int power_supply_init(struct device *dev) | ||
| 395 | { | ||
| 396 | int ret; | ||
| 397 | |||
| 398 | ret = gpio_request(GPIO_NR_PALMLD_POWER_DETECT, "CABLE_STATE_AC"); | ||
| 399 | if (ret) | ||
| 400 | goto err1; | ||
| 401 | ret = gpio_direction_input(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 402 | if (ret) | ||
| 403 | goto err2; | ||
| 404 | |||
| 405 | ret = gpio_request(GPIO_NR_PALMLD_USB_DETECT_N, "CABLE_STATE_USB"); | ||
| 406 | if (ret) | ||
| 407 | goto err2; | ||
| 408 | ret = gpio_direction_input(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 409 | if (ret) | ||
| 410 | goto err3; | ||
| 411 | |||
| 412 | return 0; | ||
| 413 | |||
| 414 | err3: | ||
| 415 | gpio_free(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 416 | err2: | ||
| 417 | gpio_free(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 418 | err1: | ||
| 419 | return ret; | ||
| 420 | } | ||
| 421 | |||
| 422 | static int palmld_is_ac_online(void) | ||
| 423 | { | ||
| 424 | return gpio_get_value(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 425 | } | ||
| 426 | |||
| 427 | static int palmld_is_usb_online(void) | ||
| 428 | { | ||
| 429 | return !gpio_get_value(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 430 | } | ||
| 431 | |||
| 432 | static void power_supply_exit(struct device *dev) | ||
| 433 | { | ||
| 434 | gpio_free(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 435 | gpio_free(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 436 | } | ||
| 437 | |||
| 438 | static char *palmld_supplicants[] = { | ||
| 439 | "main-battery", | ||
| 440 | }; | ||
| 441 | |||
| 442 | static struct pda_power_pdata power_supply_info = { | ||
| 443 | .init = power_supply_init, | ||
| 444 | .is_ac_online = palmld_is_ac_online, | ||
| 445 | .is_usb_online = palmld_is_usb_online, | ||
| 446 | .exit = power_supply_exit, | ||
| 447 | .supplied_to = palmld_supplicants, | ||
| 448 | .num_supplicants = ARRAY_SIZE(palmld_supplicants), | ||
| 449 | }; | ||
| 450 | |||
| 451 | static struct platform_device power_supply = { | ||
| 452 | .name = "pda-power", | ||
| 453 | .id = -1, | ||
| 454 | .dev = { | ||
| 455 | .platform_data = &power_supply_info, | ||
| 456 | }, | ||
| 457 | }; | ||
| 458 | |||
| 459 | /****************************************************************************** | ||
| 460 | * WM97xx battery | ||
| 461 | ******************************************************************************/ | ||
| 462 | static struct wm97xx_batt_info wm97xx_batt_pdata = { | ||
| 463 | .batt_aux = WM97XX_AUX_ID3, | ||
| 464 | .temp_aux = WM97XX_AUX_ID2, | ||
| 465 | .charge_gpio = -1, | ||
| 466 | .max_voltage = PALMLD_BAT_MAX_VOLTAGE, | ||
| 467 | .min_voltage = PALMLD_BAT_MIN_VOLTAGE, | ||
| 468 | .batt_mult = 1000, | ||
| 469 | .batt_div = 414, | ||
| 470 | .temp_mult = 1, | ||
| 471 | .temp_div = 1, | ||
| 472 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, | ||
| 473 | .batt_name = "main-batt", | ||
| 474 | }; | ||
| 475 | |||
| 476 | /****************************************************************************** | ||
| 477 | * aSoC audio | ||
| 478 | ******************************************************************************/ | ||
| 479 | static struct palm27x_asoc_info palm27x_asoc_pdata = { | ||
| 480 | .jack_gpio = GPIO_NR_PALMLD_EARPHONE_DETECT, | ||
| 481 | }; | ||
| 482 | |||
| 483 | /****************************************************************************** | ||
| 484 | * Framebuffer | ||
| 485 | ******************************************************************************/ | ||
| 486 | static struct pxafb_mode_info palmld_lcd_modes[] = { | ||
| 487 | { | ||
| 488 | .pixclock = 57692, | ||
| 489 | .xres = 320, | ||
| 490 | .yres = 480, | ||
| 491 | .bpp = 16, | ||
| 492 | |||
| 493 | .left_margin = 32, | ||
| 494 | .right_margin = 1, | ||
| 495 | .upper_margin = 7, | ||
| 496 | .lower_margin = 1, | ||
| 497 | |||
| 498 | .hsync_len = 4, | ||
| 499 | .vsync_len = 1, | ||
| 500 | }, | ||
| 501 | }; | ||
| 502 | |||
| 503 | static struct pxafb_mach_info palmld_lcd_screen = { | ||
| 504 | .modes = palmld_lcd_modes, | ||
| 505 | .num_modes = ARRAY_SIZE(palmld_lcd_modes), | ||
| 506 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | ||
| 507 | }; | ||
| 508 | |||
| 509 | /****************************************************************************** | ||
| 510 | * Machine init | ||
| 511 | ******************************************************************************/ | ||
| 512 | static struct platform_device *devices[] __initdata = { | ||
| 513 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 514 | &palmld_pxa_keys, | ||
| 515 | #endif | ||
| 516 | &palmld_backlight, | ||
| 517 | &palmld_leds, | ||
| 518 | &power_supply, | ||
| 519 | }; | ||
| 520 | |||
| 521 | static struct map_desc palmld_io_desc[] __initdata = { | ||
| 522 | { | ||
| 523 | .virtual = PALMLD_IDE_VIRT, | ||
| 524 | .pfn = __phys_to_pfn(PALMLD_IDE_PHYS), | ||
| 525 | .length = PALMLD_IDE_SIZE, | ||
| 526 | .type = MT_DEVICE | ||
| 527 | }, | ||
| 528 | { | ||
| 529 | .virtual = PALMLD_USB_VIRT, | ||
| 530 | .pfn = __phys_to_pfn(PALMLD_USB_PHYS), | ||
| 531 | .length = PALMLD_USB_SIZE, | ||
| 532 | .type = MT_DEVICE | ||
| 533 | }, | ||
| 534 | }; | ||
| 535 | |||
| 536 | static void __init palmld_map_io(void) | ||
| 537 | { | ||
| 538 | pxa_map_io(); | ||
| 539 | iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc)); | ||
| 540 | } | ||
| 541 | |||
| 542 | static void __init palmld_init(void) | ||
| 543 | { | ||
| 544 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config)); | ||
| 545 | |||
| 546 | set_pxa_fb_info(&palmld_lcd_screen); | ||
| 547 | pxa_set_mci_info(&palmld_mci_platform_data); | ||
| 548 | pxa_set_ac97_info(NULL); | ||
| 549 | pxa_set_ficp_info(&palmld_ficp_platform_data); | ||
| 550 | pxa_set_keypad_info(&palmld_keypad_platform_data); | ||
| 551 | wm97xx_bat_set_pdata(&wm97xx_batt_pdata); | ||
| 552 | palm27x_asoc_set_pdata(&palm27x_asoc_pdata); | ||
| 553 | |||
| 554 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 555 | } | ||
| 556 | |||
| 557 | MACHINE_START(PALMLD, "Palm LifeDrive") | ||
| 558 | .phys_io = PALMLD_PHYS_IO_START, | ||
| 559 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 560 | .boot_params = 0xa0000100, | ||
| 561 | .map_io = palmld_map_io, | ||
| 562 | .init_irq = pxa27x_init_irq, | ||
| 563 | .timer = &pxa_timer, | ||
| 564 | .init_machine = palmld_init | ||
| 565 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c new file mode 100644 index 000000000000..9521c7b33492 --- /dev/null +++ b/arch/arm/mach-pxa/palmt5.c | |||
| @@ -0,0 +1,496 @@ | |||
| 1 | /* | ||
| 2 | * Hardware definitions for Palm Tungsten|T5 | ||
| 3 | * | ||
| 4 | * Author: Marek Vasut <marek.vasut@gmail.com> | ||
| 5 | * | ||
| 6 | * Based on work of: | ||
| 7 | * Ales Snuparek <snuparek@atlas.cz> | ||
| 8 | * Justin Kendrick <twilightsentry@gmail.com> | ||
| 9 | * RichardT5 <richard_t5@users.sourceforge.net> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * (find more info at www.hackndev.com) | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | #include <linux/gpio_keys.h> | ||
| 23 | #include <linux/input.h> | ||
| 24 | #include <linux/pda_power.h> | ||
| 25 | #include <linux/pwm_backlight.h> | ||
| 26 | #include <linux/gpio.h> | ||
| 27 | #include <linux/wm97xx_batt.h> | ||
| 28 | #include <linux/power_supply.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/map.h> | ||
| 33 | |||
| 34 | #include <mach/pxa27x.h> | ||
| 35 | #include <mach/audio.h> | ||
| 36 | #include <mach/palmt5.h> | ||
| 37 | #include <mach/mmc.h> | ||
| 38 | #include <mach/pxafb.h> | ||
| 39 | #include <mach/irda.h> | ||
| 40 | #include <mach/pxa27x_keypad.h> | ||
| 41 | #include <mach/udc.h> | ||
| 42 | #include <mach/palmasoc.h> | ||
| 43 | |||
| 44 | #include "generic.h" | ||
| 45 | #include "devices.h" | ||
| 46 | |||
| 47 | /****************************************************************************** | ||
| 48 | * Pin configuration | ||
| 49 | ******************************************************************************/ | ||
| 50 | static unsigned long palmt5_pin_config[] __initdata = { | ||
| 51 | /* MMC */ | ||
| 52 | GPIO32_MMC_CLK, | ||
| 53 | GPIO92_MMC_DAT_0, | ||
| 54 | GPIO109_MMC_DAT_1, | ||
| 55 | GPIO110_MMC_DAT_2, | ||
| 56 | GPIO111_MMC_DAT_3, | ||
| 57 | GPIO112_MMC_CMD, | ||
| 58 | GPIO14_GPIO, /* SD detect */ | ||
| 59 | GPIO114_GPIO, /* SD power */ | ||
| 60 | GPIO115_GPIO, /* SD r/o switch */ | ||
| 61 | |||
| 62 | /* AC97 */ | ||
| 63 | GPIO28_AC97_BITCLK, | ||
| 64 | GPIO29_AC97_SDATA_IN_0, | ||
| 65 | GPIO30_AC97_SDATA_OUT, | ||
| 66 | GPIO31_AC97_SYNC, | ||
| 67 | |||
| 68 | /* IrDA */ | ||
| 69 | GPIO40_GPIO, /* ir disable */ | ||
| 70 | GPIO46_FICP_RXD, | ||
| 71 | GPIO47_FICP_TXD, | ||
| 72 | |||
| 73 | /* USB */ | ||
| 74 | GPIO15_GPIO, /* usb detect */ | ||
| 75 | GPIO95_GPIO, /* usb power */ | ||
| 76 | |||
| 77 | /* MATRIX KEYPAD */ | ||
| 78 | GPIO100_KP_MKIN_0, | ||
| 79 | GPIO101_KP_MKIN_1, | ||
| 80 | GPIO102_KP_MKIN_2, | ||
| 81 | GPIO97_KP_MKIN_3, | ||
| 82 | GPIO103_KP_MKOUT_0, | ||
| 83 | GPIO104_KP_MKOUT_1, | ||
| 84 | GPIO105_KP_MKOUT_2, | ||
| 85 | |||
| 86 | /* LCD */ | ||
| 87 | GPIO58_LCD_LDD_0, | ||
| 88 | GPIO59_LCD_LDD_1, | ||
| 89 | GPIO60_LCD_LDD_2, | ||
| 90 | GPIO61_LCD_LDD_3, | ||
| 91 | GPIO62_LCD_LDD_4, | ||
| 92 | GPIO63_LCD_LDD_5, | ||
| 93 | GPIO64_LCD_LDD_6, | ||
| 94 | GPIO65_LCD_LDD_7, | ||
| 95 | GPIO66_LCD_LDD_8, | ||
| 96 | GPIO67_LCD_LDD_9, | ||
| 97 | GPIO68_LCD_LDD_10, | ||
| 98 | GPIO69_LCD_LDD_11, | ||
| 99 | GPIO70_LCD_LDD_12, | ||
| 100 | GPIO71_LCD_LDD_13, | ||
| 101 | GPIO72_LCD_LDD_14, | ||
| 102 | GPIO73_LCD_LDD_15, | ||
| 103 | GPIO74_LCD_FCLK, | ||
| 104 | GPIO75_LCD_LCLK, | ||
| 105 | GPIO76_LCD_PCLK, | ||
| 106 | GPIO77_LCD_BIAS, | ||
| 107 | |||
| 108 | /* PWM */ | ||
| 109 | GPIO16_PWM0_OUT, | ||
| 110 | |||
| 111 | /* MISC */ | ||
| 112 | GPIO10_GPIO, /* hotsync button */ | ||
| 113 | GPIO90_GPIO, /* power detect */ | ||
| 114 | GPIO107_GPIO, /* earphone detect */ | ||
| 115 | }; | ||
| 116 | |||
| 117 | /****************************************************************************** | ||
| 118 | * SD/MMC card controller | ||
| 119 | ******************************************************************************/ | ||
| 120 | static int palmt5_mci_init(struct device *dev, irq_handler_t palmt5_detect_int, | ||
| 121 | void *data) | ||
| 122 | { | ||
| 123 | int err = 0; | ||
| 124 | |||
| 125 | /* Setup an interrupt for detecting card insert/remove events */ | ||
| 126 | err = gpio_request(GPIO_NR_PALMT5_SD_DETECT_N, "SD IRQ"); | ||
| 127 | if (err) | ||
| 128 | goto err; | ||
| 129 | err = gpio_direction_input(GPIO_NR_PALMT5_SD_DETECT_N); | ||
| 130 | if (err) | ||
| 131 | goto err2; | ||
| 132 | err = request_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N), | ||
| 133 | palmt5_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | | ||
| 134 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
| 135 | "SD/MMC card detect", data); | ||
| 136 | if (err) { | ||
| 137 | printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", | ||
| 138 | __func__); | ||
| 139 | goto err2; | ||
| 140 | } | ||
| 141 | |||
| 142 | err = gpio_request(GPIO_NR_PALMT5_SD_POWER, "SD_POWER"); | ||
| 143 | if (err) | ||
| 144 | goto err3; | ||
| 145 | err = gpio_direction_output(GPIO_NR_PALMT5_SD_POWER, 0); | ||
| 146 | if (err) | ||
| 147 | goto err4; | ||
| 148 | |||
| 149 | err = gpio_request(GPIO_NR_PALMT5_SD_READONLY, "SD_READONLY"); | ||
| 150 | if (err) | ||
| 151 | goto err4; | ||
| 152 | err = gpio_direction_input(GPIO_NR_PALMT5_SD_READONLY); | ||
| 153 | if (err) | ||
| 154 | goto err5; | ||
| 155 | |||
| 156 | printk(KERN_DEBUG "%s: irq registered\n", __func__); | ||
| 157 | |||
| 158 | return 0; | ||
| 159 | |||
| 160 | err5: | ||
| 161 | gpio_free(GPIO_NR_PALMT5_SD_READONLY); | ||
| 162 | err4: | ||
| 163 | gpio_free(GPIO_NR_PALMT5_SD_POWER); | ||
| 164 | err3: | ||
| 165 | free_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N), data); | ||
| 166 | err2: | ||
| 167 | gpio_free(GPIO_NR_PALMT5_SD_DETECT_N); | ||
| 168 | err: | ||
| 169 | return err; | ||
| 170 | } | ||
| 171 | |||
| 172 | static void palmt5_mci_exit(struct device *dev, void *data) | ||
| 173 | { | ||
| 174 | gpio_free(GPIO_NR_PALMT5_SD_READONLY); | ||
| 175 | gpio_free(GPIO_NR_PALMT5_SD_POWER); | ||
| 176 | free_irq(IRQ_GPIO_PALMT5_SD_DETECT_N, data); | ||
| 177 | gpio_free(GPIO_NR_PALMT5_SD_DETECT_N); | ||
| 178 | } | ||
| 179 | |||
| 180 | static void palmt5_mci_power(struct device *dev, unsigned int vdd) | ||
| 181 | { | ||
| 182 | struct pxamci_platform_data *p_d = dev->platform_data; | ||
| 183 | gpio_set_value(GPIO_NR_PALMT5_SD_POWER, p_d->ocr_mask & (1 << vdd)); | ||
| 184 | } | ||
| 185 | |||
| 186 | static int palmt5_mci_get_ro(struct device *dev) | ||
| 187 | { | ||
| 188 | return gpio_get_value(GPIO_NR_PALMT5_SD_READONLY); | ||
| 189 | } | ||
| 190 | |||
| 191 | static struct pxamci_platform_data palmt5_mci_platform_data = { | ||
| 192 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 193 | .setpower = palmt5_mci_power, | ||
| 194 | .get_ro = palmt5_mci_get_ro, | ||
| 195 | .init = palmt5_mci_init, | ||
| 196 | .exit = palmt5_mci_exit, | ||
| 197 | }; | ||
| 198 | |||
| 199 | /****************************************************************************** | ||
| 200 | * GPIO keyboard | ||
| 201 | ******************************************************************************/ | ||
| 202 | static unsigned int palmt5_matrix_keys[] = { | ||
| 203 | KEY(0, 0, KEY_POWER), | ||
| 204 | KEY(0, 1, KEY_F1), | ||
| 205 | KEY(0, 2, KEY_ENTER), | ||
| 206 | |||
| 207 | KEY(1, 0, KEY_F2), | ||
| 208 | KEY(1, 1, KEY_F3), | ||
| 209 | KEY(1, 2, KEY_F4), | ||
| 210 | |||
| 211 | KEY(2, 0, KEY_UP), | ||
| 212 | KEY(2, 2, KEY_DOWN), | ||
| 213 | |||
| 214 | KEY(3, 0, KEY_RIGHT), | ||
| 215 | KEY(3, 2, KEY_LEFT), | ||
| 216 | }; | ||
| 217 | |||
| 218 | static struct pxa27x_keypad_platform_data palmt5_keypad_platform_data = { | ||
| 219 | .matrix_key_rows = 4, | ||
| 220 | .matrix_key_cols = 3, | ||
| 221 | .matrix_key_map = palmt5_matrix_keys, | ||
| 222 | .matrix_key_map_size = ARRAY_SIZE(palmt5_matrix_keys), | ||
| 223 | |||
| 224 | .debounce_interval = 30, | ||
| 225 | }; | ||
| 226 | |||
| 227 | /****************************************************************************** | ||
| 228 | * GPIO keys | ||
| 229 | ******************************************************************************/ | ||
| 230 | static struct gpio_keys_button palmt5_pxa_buttons[] = { | ||
| 231 | {KEY_F8, GPIO_NR_PALMT5_HOTSYNC_BUTTON_N, 1, "HotSync Button" }, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct gpio_keys_platform_data palmt5_pxa_keys_data = { | ||
| 235 | .buttons = palmt5_pxa_buttons, | ||
| 236 | .nbuttons = ARRAY_SIZE(palmt5_pxa_buttons), | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct platform_device palmt5_pxa_keys = { | ||
| 240 | .name = "gpio-keys", | ||
| 241 | .id = -1, | ||
| 242 | .dev = { | ||
| 243 | .platform_data = &palmt5_pxa_keys_data, | ||
| 244 | }, | ||
| 245 | }; | ||
| 246 | |||
| 247 | /****************************************************************************** | ||
| 248 | * Backlight | ||
| 249 | ******************************************************************************/ | ||
| 250 | static int palmt5_backlight_init(struct device *dev) | ||
| 251 | { | ||
| 252 | int ret; | ||
| 253 | |||
| 254 | ret = gpio_request(GPIO_NR_PALMT5_BL_POWER, "BL POWER"); | ||
| 255 | if (ret) | ||
| 256 | goto err; | ||
| 257 | ret = gpio_direction_output(GPIO_NR_PALMT5_BL_POWER, 0); | ||
| 258 | if (ret) | ||
| 259 | goto err2; | ||
| 260 | ret = gpio_request(GPIO_NR_PALMT5_LCD_POWER, "LCD POWER"); | ||
| 261 | if (ret) | ||
| 262 | goto err2; | ||
| 263 | ret = gpio_direction_output(GPIO_NR_PALMT5_LCD_POWER, 0); | ||
| 264 | if (ret) | ||
| 265 | goto err3; | ||
| 266 | |||
| 267 | return 0; | ||
| 268 | err3: | ||
| 269 | gpio_free(GPIO_NR_PALMT5_LCD_POWER); | ||
| 270 | err2: | ||
| 271 | gpio_free(GPIO_NR_PALMT5_BL_POWER); | ||
| 272 | err: | ||
| 273 | return ret; | ||
| 274 | } | ||
| 275 | |||
| 276 | static int palmt5_backlight_notify(int brightness) | ||
| 277 | { | ||
| 278 | gpio_set_value(GPIO_NR_PALMT5_BL_POWER, brightness); | ||
| 279 | gpio_set_value(GPIO_NR_PALMT5_LCD_POWER, brightness); | ||
| 280 | return brightness; | ||
| 281 | } | ||
| 282 | |||
| 283 | static void palmt5_backlight_exit(struct device *dev) | ||
| 284 | { | ||
| 285 | gpio_free(GPIO_NR_PALMT5_BL_POWER); | ||
| 286 | gpio_free(GPIO_NR_PALMT5_LCD_POWER); | ||
| 287 | } | ||
| 288 | |||
| 289 | static struct platform_pwm_backlight_data palmt5_backlight_data = { | ||
| 290 | .pwm_id = 0, | ||
| 291 | .max_brightness = PALMT5_MAX_INTENSITY, | ||
| 292 | .dft_brightness = PALMT5_MAX_INTENSITY, | ||
| 293 | .pwm_period_ns = PALMT5_PERIOD_NS, | ||
| 294 | .init = palmt5_backlight_init, | ||
| 295 | .notify = palmt5_backlight_notify, | ||
| 296 | .exit = palmt5_backlight_exit, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct platform_device palmt5_backlight = { | ||
| 300 | .name = "pwm-backlight", | ||
| 301 | .dev = { | ||
| 302 | .parent = &pxa27x_device_pwm0.dev, | ||
| 303 | .platform_data = &palmt5_backlight_data, | ||
| 304 | }, | ||
| 305 | }; | ||
| 306 | |||
| 307 | /****************************************************************************** | ||
| 308 | * IrDA | ||
| 309 | ******************************************************************************/ | ||
| 310 | static int palmt5_irda_startup(struct device *dev) | ||
| 311 | { | ||
| 312 | int err; | ||
| 313 | err = gpio_request(GPIO_NR_PALMT5_IR_DISABLE, "IR DISABLE"); | ||
| 314 | if (err) | ||
| 315 | goto err; | ||
| 316 | err = gpio_direction_output(GPIO_NR_PALMT5_IR_DISABLE, 1); | ||
| 317 | if (err) | ||
| 318 | gpio_free(GPIO_NR_PALMT5_IR_DISABLE); | ||
| 319 | err: | ||
| 320 | return err; | ||
| 321 | } | ||
| 322 | |||
| 323 | static void palmt5_irda_shutdown(struct device *dev) | ||
| 324 | { | ||
| 325 | gpio_free(GPIO_NR_PALMT5_IR_DISABLE); | ||
| 326 | } | ||
| 327 | |||
| 328 | static void palmt5_irda_transceiver_mode(struct device *dev, int mode) | ||
| 329 | { | ||
| 330 | gpio_set_value(GPIO_NR_PALMT5_IR_DISABLE, mode & IR_OFF); | ||
| 331 | pxa2xx_transceiver_mode(dev, mode); | ||
| 332 | } | ||
| 333 | |||
| 334 | static struct pxaficp_platform_data palmt5_ficp_platform_data = { | ||
| 335 | .startup = palmt5_irda_startup, | ||
| 336 | .shutdown = palmt5_irda_shutdown, | ||
| 337 | .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, | ||
| 338 | .transceiver_mode = palmt5_irda_transceiver_mode, | ||
| 339 | }; | ||
| 340 | |||
| 341 | /****************************************************************************** | ||
| 342 | * UDC | ||
| 343 | ******************************************************************************/ | ||
| 344 | static struct pxa2xx_udc_mach_info palmt5_udc_info __initdata = { | ||
| 345 | .gpio_vbus = GPIO_NR_PALMT5_USB_DETECT_N, | ||
| 346 | .gpio_vbus_inverted = 1, | ||
| 347 | .gpio_pullup = GPIO_NR_PALMT5_USB_POWER, | ||
| 348 | .gpio_pullup_inverted = 0, | ||
| 349 | }; | ||
| 350 | |||
| 351 | /****************************************************************************** | ||
| 352 | * Power supply | ||
| 353 | ******************************************************************************/ | ||
| 354 | static int power_supply_init(struct device *dev) | ||
| 355 | { | ||
| 356 | int ret; | ||
| 357 | |||
| 358 | ret = gpio_request(GPIO_NR_PALMT5_POWER_DETECT, "CABLE_STATE_AC"); | ||
| 359 | if (ret) | ||
| 360 | goto err1; | ||
| 361 | ret = gpio_direction_input(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 362 | if (ret) | ||
| 363 | goto err2; | ||
| 364 | |||
| 365 | return 0; | ||
| 366 | err2: | ||
| 367 | gpio_free(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 368 | err1: | ||
| 369 | return ret; | ||
| 370 | } | ||
| 371 | |||
| 372 | static int palmt5_is_ac_online(void) | ||
| 373 | { | ||
| 374 | return gpio_get_value(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 375 | } | ||
| 376 | |||
| 377 | static void power_supply_exit(struct device *dev) | ||
| 378 | { | ||
| 379 | gpio_free(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 380 | } | ||
| 381 | |||
| 382 | static char *palmt5_supplicants[] = { | ||
| 383 | "main-battery", | ||
| 384 | }; | ||
| 385 | |||
| 386 | static struct pda_power_pdata power_supply_info = { | ||
| 387 | .init = power_supply_init, | ||
| 388 | .is_ac_online = palmt5_is_ac_online, | ||
| 389 | .exit = power_supply_exit, | ||
| 390 | .supplied_to = palmt5_supplicants, | ||
| 391 | .num_supplicants = ARRAY_SIZE(palmt5_supplicants), | ||
| 392 | }; | ||
| 393 | |||
| 394 | static struct platform_device power_supply = { | ||
| 395 | .name = "pda-power", | ||
| 396 | .id = -1, | ||
| 397 | .dev = { | ||
| 398 | .platform_data = &power_supply_info, | ||
| 399 | }, | ||
| 400 | }; | ||
| 401 | |||
| 402 | /****************************************************************************** | ||
| 403 | * WM97xx battery | ||
| 404 | ******************************************************************************/ | ||
| 405 | static struct wm97xx_batt_info wm97xx_batt_pdata = { | ||
| 406 | .batt_aux = WM97XX_AUX_ID3, | ||
| 407 | .temp_aux = WM97XX_AUX_ID2, | ||
| 408 | .charge_gpio = -1, | ||
| 409 | .max_voltage = PALMT5_BAT_MAX_VOLTAGE, | ||
| 410 | .min_voltage = PALMT5_BAT_MIN_VOLTAGE, | ||
| 411 | .batt_mult = 1000, | ||
| 412 | .batt_div = 414, | ||
| 413 | .temp_mult = 1, | ||
| 414 | .temp_div = 1, | ||
| 415 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, | ||
| 416 | .batt_name = "main-batt", | ||
| 417 | }; | ||
| 418 | |||
| 419 | /****************************************************************************** | ||
| 420 | * aSoC audio | ||
| 421 | ******************************************************************************/ | ||
| 422 | static struct palm27x_asoc_info palm27x_asoc_pdata = { | ||
| 423 | .jack_gpio = GPIO_NR_PALMT5_EARPHONE_DETECT, | ||
| 424 | }; | ||
| 425 | |||
| 426 | /****************************************************************************** | ||
| 427 | * Framebuffer | ||
| 428 | ******************************************************************************/ | ||
| 429 | static struct pxafb_mode_info palmt5_lcd_modes[] = { | ||
| 430 | { | ||
| 431 | .pixclock = 57692, | ||
| 432 | .xres = 320, | ||
| 433 | .yres = 480, | ||
| 434 | .bpp = 16, | ||
| 435 | |||
| 436 | .left_margin = 32, | ||
| 437 | .right_margin = 1, | ||
| 438 | .upper_margin = 7, | ||
| 439 | .lower_margin = 1, | ||
| 440 | |||
| 441 | .hsync_len = 4, | ||
| 442 | .vsync_len = 1, | ||
| 443 | }, | ||
| 444 | }; | ||
| 445 | |||
| 446 | static struct pxafb_mach_info palmt5_lcd_screen = { | ||
| 447 | .modes = palmt5_lcd_modes, | ||
| 448 | .num_modes = ARRAY_SIZE(palmt5_lcd_modes), | ||
| 449 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | ||
| 450 | }; | ||
| 451 | |||
| 452 | /****************************************************************************** | ||
| 453 | * Machine init | ||
| 454 | ******************************************************************************/ | ||
| 455 | static struct platform_device *devices[] __initdata = { | ||
| 456 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 457 | &palmt5_pxa_keys, | ||
| 458 | #endif | ||
| 459 | &palmt5_backlight, | ||
| 460 | &power_supply, | ||
| 461 | }; | ||
| 462 | |||
| 463 | /* setup udc GPIOs initial state */ | ||
| 464 | static void __init palmt5_udc_init(void) | ||
| 465 | { | ||
| 466 | if (!gpio_request(GPIO_NR_PALMT5_USB_POWER, "UDC Vbus")) { | ||
| 467 | gpio_direction_output(GPIO_NR_PALMT5_USB_POWER, 1); | ||
| 468 | gpio_free(GPIO_NR_PALMT5_USB_POWER); | ||
| 469 | } | ||
| 470 | } | ||
| 471 | |||
| 472 | static void __init palmt5_init(void) | ||
| 473 | { | ||
| 474 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); | ||
| 475 | |||
| 476 | set_pxa_fb_info(&palmt5_lcd_screen); | ||
| 477 | pxa_set_mci_info(&palmt5_mci_platform_data); | ||
| 478 | palmt5_udc_init(); | ||
| 479 | pxa_set_udc_info(&palmt5_udc_info); | ||
| 480 | pxa_set_ac97_info(NULL); | ||
| 481 | pxa_set_ficp_info(&palmt5_ficp_platform_data); | ||
| 482 | pxa_set_keypad_info(&palmt5_keypad_platform_data); | ||
| 483 | wm97xx_bat_set_pdata(&wm97xx_batt_pdata); | ||
| 484 | palm27x_asoc_set_pdata(&palm27x_asoc_pdata); | ||
| 485 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 486 | } | ||
| 487 | |||
| 488 | MACHINE_START(PALMT5, "Palm Tungsten|T5") | ||
| 489 | .phys_io = PALMT5_PHYS_IO_START, | ||
| 490 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 491 | .boot_params = 0xa0000100, | ||
| 492 | .map_io = pxa_map_io, | ||
| 493 | .init_irq = pxa27x_init_irq, | ||
| 494 | .timer = &pxa_timer, | ||
| 495 | .init_machine = palmt5_init | ||
| 496 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index a9d94f5dbec4..b490c0924619 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c | |||
| @@ -32,12 +32,11 @@ | |||
| 32 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 34 | 34 | ||
| 35 | #include <mach/pxa27x.h> | ||
| 35 | #include <mach/audio.h> | 36 | #include <mach/audio.h> |
| 36 | #include <mach/palmtx.h> | 37 | #include <mach/palmtx.h> |
| 37 | #include <mach/mmc.h> | 38 | #include <mach/mmc.h> |
| 38 | #include <mach/pxafb.h> | 39 | #include <mach/pxafb.h> |
| 39 | #include <mach/pxa-regs.h> | ||
| 40 | #include <mach/mfp-pxa27x.h> | ||
| 41 | #include <mach/irda.h> | 40 | #include <mach/irda.h> |
| 42 | #include <mach/pxa27x_keypad.h> | 41 | #include <mach/pxa27x_keypad.h> |
| 43 | #include <mach/udc.h> | 42 | #include <mach/udc.h> |
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 2f730da3bba8..b88eb4dd2c84 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c | |||
| @@ -33,13 +33,11 @@ | |||
| 33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 35 | 35 | ||
| 36 | #include <mach/pxa27x.h> | ||
| 36 | #include <mach/audio.h> | 37 | #include <mach/audio.h> |
| 37 | #include <mach/palmz72.h> | 38 | #include <mach/palmz72.h> |
| 38 | #include <mach/mmc.h> | 39 | #include <mach/mmc.h> |
| 39 | #include <mach/pxafb.h> | 40 | #include <mach/pxafb.h> |
| 40 | #include <mach/pxa-regs.h> | ||
| 41 | #include <mach/pxa2xx-regs.h> | ||
| 42 | #include <mach/mfp-pxa27x.h> | ||
| 43 | #include <mach/irda.h> | 41 | #include <mach/irda.h> |
| 44 | #include <mach/pxa27x_keypad.h> | 42 | #include <mach/pxa27x_keypad.h> |
| 45 | #include <mach/udc.h> | 43 | #include <mach/udc.h> |
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 36135a02fdc7..6abfa2979c61 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c | |||
| @@ -29,10 +29,7 @@ | |||
| 29 | 29 | ||
| 30 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 32 | #include <mach/hardware.h> | 32 | #include <mach/pxa27x.h> |
| 33 | #include <mach/pxa-regs.h> | ||
| 34 | #include <mach/mfp-pxa27x.h> | ||
| 35 | #include <mach/pxa2xx-regs.h> | ||
| 36 | #include <mach/pxa2xx_spi.h> | 33 | #include <mach/pxa2xx_spi.h> |
| 37 | #include <mach/pcm027.h> | 34 | #include <mach/pcm027.h> |
| 38 | #include "generic.h" | 35 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 34841c72815f..f46698e20c1f 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c | |||
| @@ -31,13 +31,12 @@ | |||
| 31 | #include <mach/i2c.h> | 31 | #include <mach/i2c.h> |
| 32 | #include <mach/camera.h> | 32 | #include <mach/camera.h> |
| 33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 34 | #include <mach/pxa-regs.h> | 34 | #include <mach/pxa27x.h> |
| 35 | #include <mach/audio.h> | 35 | #include <mach/audio.h> |
| 36 | #include <mach/mmc.h> | 36 | #include <mach/mmc.h> |
| 37 | #include <mach/ohci.h> | 37 | #include <mach/ohci.h> |
| 38 | #include <mach/pcm990_baseboard.h> | 38 | #include <mach/pcm990_baseboard.h> |
| 39 | #include <mach/pxafb.h> | 39 | #include <mach/pxafb.h> |
| 40 | #include <mach/mfp-pxa27x.h> | ||
| 41 | 40 | ||
| 42 | #include "devices.h" | 41 | #include "devices.h" |
| 43 | #include "generic.h" | 42 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index 164eb0bb6321..884b174c8ead 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c | |||
| @@ -14,15 +14,8 @@ | |||
| 14 | #include <linux/module.h> | 14 | #include <linux/module.h> |
| 15 | #include <linux/suspend.h> | 15 | #include <linux/suspend.h> |
| 16 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
| 17 | #include <linux/time.h> | ||
| 18 | 17 | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | #include <asm/memory.h> | ||
| 21 | #include <asm/system.h> | ||
| 22 | #include <mach/pm.h> | 18 | #include <mach/pm.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/lubbock.h> | ||
| 25 | #include <asm/mach/time.h> | ||
| 26 | 19 | ||
| 27 | struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; | 20 | struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; |
| 28 | static unsigned long *sleep_save; | 21 | static unsigned long *sleep_save; |
| @@ -57,9 +50,9 @@ int pxa_pm_enter(suspend_state_t state) | |||
| 57 | 50 | ||
| 58 | /* if invalid, display message and wait for a hardware reset */ | 51 | /* if invalid, display message and wait for a hardware reset */ |
| 59 | if (checksum != sleep_save_checksum) { | 52 | if (checksum != sleep_save_checksum) { |
| 60 | #ifdef CONFIG_ARCH_LUBBOCK | 53 | |
| 61 | LUB_HEXLED = 0xbadbadc5; | 54 | lubbock_set_hexled(0xbadbadc5); |
| 62 | #endif | 55 | |
| 63 | while (1) | 56 | while (1) |
| 64 | pxa_cpu_pm_fns->enter(state); | 57 | pxa_cpu_pm_fns->enter(state); |
| 65 | } | 58 | } |
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index f9093beba752..036bbde4d221 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
| @@ -36,9 +36,7 @@ | |||
| 36 | #include <asm/mach/map.h> | 36 | #include <asm/mach/map.h> |
| 37 | #include <asm/mach/irq.h> | 37 | #include <asm/mach/irq.h> |
| 38 | 38 | ||
| 39 | #include <mach/pxa-regs.h> | 39 | #include <mach/pxa25x.h> |
| 40 | #include <mach/pxa2xx-regs.h> | ||
| 41 | #include <mach/mfp-pxa25x.h> | ||
| 42 | #include <mach/mmc.h> | 40 | #include <mach/mmc.h> |
| 43 | #include <mach/udc.h> | 41 | #include <mach/udc.h> |
| 44 | #include <mach/i2c.h> | 42 | #include <mach/i2c.h> |
| @@ -503,12 +501,12 @@ static struct platform_device *devices[] __initdata = { | |||
| 503 | 501 | ||
| 504 | static void poodle_poweroff(void) | 502 | static void poodle_poweroff(void) |
| 505 | { | 503 | { |
| 506 | arm_machine_restart('h'); | 504 | arm_machine_restart('h', NULL); |
| 507 | } | 505 | } |
| 508 | 506 | ||
| 509 | static void poodle_restart(char mode) | 507 | static void poodle_restart(char mode, const char *cmd) |
| 510 | { | 508 | { |
| 511 | arm_machine_restart('h'); | 509 | arm_machine_restart('h', cmd); |
| 512 | } | 510 | } |
| 513 | 511 | ||
| 514 | static void __init poodle_init(void) | 512 | static void __init poodle_init(void) |
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c index 3ca7ffc6904b..fcdd374437a8 100644 --- a/arch/arm/mach-pxa/pwm.c +++ b/arch/arm/mach-pxa/pwm.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <linux/pwm.h> | 20 | #include <linux/pwm.h> |
| 21 | 21 | ||
| 22 | #include <asm/div64.h> | 22 | #include <asm/div64.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | 23 | ||
| 25 | /* PWM registers and bits definitions */ | 24 | /* PWM registers and bits definitions */ |
| 26 | #define PWMCR (0x00) | 25 | #define PWMCR (0x00) |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 6c57522e2469..77c2693cfeef 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
| @@ -25,9 +25,8 @@ | |||
| 25 | 25 | ||
| 26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 27 | #include <mach/irqs.h> | 27 | #include <mach/irqs.h> |
| 28 | #include <mach/pxa-regs.h> | 28 | #include <mach/gpio.h> |
| 29 | #include <mach/pxa2xx-regs.h> | 29 | #include <mach/pxa25x.h> |
| 30 | #include <mach/mfp-pxa25x.h> | ||
| 31 | #include <mach/reset.h> | 30 | #include <mach/reset.h> |
| 32 | #include <mach/pm.h> | 31 | #include <mach/pm.h> |
| 33 | #include <mach/dma.h> | 32 | #include <mach/dma.h> |
| @@ -310,14 +309,14 @@ set_pwer: | |||
| 310 | void __init pxa25x_init_irq(void) | 309 | void __init pxa25x_init_irq(void) |
| 311 | { | 310 | { |
| 312 | pxa_init_irq(32, pxa25x_set_wake); | 311 | pxa_init_irq(32, pxa25x_set_wake); |
| 313 | pxa_init_gpio(85, pxa25x_set_wake); | 312 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake); |
| 314 | } | 313 | } |
| 315 | 314 | ||
| 316 | #ifdef CONFIG_CPU_PXA26x | 315 | #ifdef CONFIG_CPU_PXA26x |
| 317 | void __init pxa26x_init_irq(void) | 316 | void __init pxa26x_init_irq(void) |
| 318 | { | 317 | { |
| 319 | pxa_init_irq(32, pxa25x_set_wake); | 318 | pxa_init_irq(32, pxa25x_set_wake); |
| 320 | pxa_init_gpio(90, pxa25x_set_wake); | 319 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake); |
| 321 | } | 320 | } |
| 322 | #endif | 321 | #endif |
| 323 | 322 | ||
| @@ -355,7 +354,7 @@ static int __init pxa25x_init(void) | |||
| 355 | 354 | ||
| 356 | clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs)); | 355 | clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs)); |
| 357 | 356 | ||
| 358 | if ((ret = pxa_init_dma(16))) | 357 | if ((ret = pxa_init_dma(IRQ_DMA, 16))) |
| 359 | return ret; | 358 | return ret; |
| 360 | 359 | ||
| 361 | pxa25x_init_pm(); | 360 | pxa25x_init_pm(); |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 411bec54fdc4..a425ec71e657 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
| @@ -21,9 +21,8 @@ | |||
| 21 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 22 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
| 23 | #include <mach/irqs.h> | 23 | #include <mach/irqs.h> |
| 24 | #include <mach/pxa-regs.h> | 24 | #include <mach/gpio.h> |
| 25 | #include <mach/pxa2xx-regs.h> | 25 | #include <mach/pxa27x.h> |
| 26 | #include <mach/mfp-pxa27x.h> | ||
| 27 | #include <mach/reset.h> | 26 | #include <mach/reset.h> |
| 28 | #include <mach/ohci.h> | 27 | #include <mach/ohci.h> |
| 29 | #include <mach/pm.h> | 28 | #include <mach/pm.h> |
| @@ -332,7 +331,7 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on) | |||
| 332 | void __init pxa27x_init_irq(void) | 331 | void __init pxa27x_init_irq(void) |
| 333 | { | 332 | { |
| 334 | pxa_init_irq(34, pxa27x_set_wake); | 333 | pxa_init_irq(34, pxa27x_set_wake); |
| 335 | pxa_init_gpio(121, pxa27x_set_wake); | 334 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); |
| 336 | } | 335 | } |
| 337 | 336 | ||
| 338 | /* | 337 | /* |
| @@ -381,7 +380,7 @@ static int __init pxa27x_init(void) | |||
| 381 | 380 | ||
| 382 | clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); | 381 | clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); |
| 383 | 382 | ||
| 384 | if ((ret = pxa_init_dma(32))) | 383 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
| 385 | return ret; | 384 | return ret; |
| 386 | 385 | ||
| 387 | pxa27x_init_pm(); | 386 | pxa27x_init_pm(); |
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c index 73d04d81c75a..2f3394f85917 100644 --- a/arch/arm/mach-pxa/pxa2xx.c +++ b/arch/arm/mach-pxa/pxa2xx.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | 16 | ||
| 17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 18 | #include <mach/pxa2xx-regs.h> | 18 | #include <mach/pxa2xx-regs.h> |
| 19 | #include <mach/mfp-pxa2xx.h> | ||
| 20 | #include <mach/mfp-pxa25x.h> | 19 | #include <mach/mfp-pxa25x.h> |
| 21 | #include <mach/reset.h> | 20 | #include <mach/reset.h> |
| 22 | #include <mach/irda.h> | 21 | #include <mach/irda.h> |
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 83fb609b6eb7..4ba6d21f851c 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c | |||
| @@ -17,15 +17,13 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | 19 | ||
| 20 | #include <mach/hardware.h> | 20 | #include <mach/pxa300.h> |
| 21 | #include <mach/pxa3xx-regs.h> | ||
| 22 | #include <mach/mfp-pxa300.h> | ||
| 23 | 21 | ||
| 24 | #include "generic.h" | 22 | #include "generic.h" |
| 25 | #include "devices.h" | 23 | #include "devices.h" |
| 26 | #include "clock.h" | 24 | #include "clock.h" |
| 27 | 25 | ||
| 28 | static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { | 26 | static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = { |
| 29 | 27 | ||
| 30 | MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), | 28 | MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), |
| 31 | MFP_ADDR_X(GPIO3, GPIO26, 0x027c), | 29 | MFP_ADDR_X(GPIO3, GPIO26, 0x027c), |
| @@ -74,7 +72,7 @@ static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { | |||
| 74 | }; | 72 | }; |
| 75 | 73 | ||
| 76 | /* override pxa300 MFP register addresses */ | 74 | /* override pxa300 MFP register addresses */ |
| 77 | static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { | 75 | static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = { |
| 78 | MFP_ADDR_X(GPIO30, GPIO98, 0x0418), | 76 | MFP_ADDR_X(GPIO30, GPIO98, 0x0418), |
| 79 | MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), | 77 | MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), |
| 80 | 78 | ||
| @@ -100,13 +98,13 @@ static struct clk_lookup pxa310_clkregs[] = { | |||
| 100 | static int __init pxa300_init(void) | 98 | static int __init pxa300_init(void) |
| 101 | { | 99 | { |
| 102 | if (cpu_is_pxa300() || cpu_is_pxa310()) { | 100 | if (cpu_is_pxa300() || cpu_is_pxa310()) { |
| 103 | pxa3xx_init_mfp(); | 101 | mfp_init_base(io_p2v(MFPR_BASE)); |
| 104 | pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); | 102 | mfp_init_addr(pxa300_mfp_addr_map); |
| 105 | clks_register(ARRAY_AND_SIZE(common_clkregs)); | 103 | clks_register(ARRAY_AND_SIZE(common_clkregs)); |
| 106 | } | 104 | } |
| 107 | 105 | ||
| 108 | if (cpu_is_pxa310()) { | 106 | if (cpu_is_pxa310()) { |
| 109 | pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); | 107 | mfp_init_addr(pxa310_mfp_addr_map); |
| 110 | clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); | 108 | clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); |
| 111 | } | 109 | } |
| 112 | 110 | ||
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 36f066196fa2..8b3d97efadab 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c | |||
| @@ -17,16 +17,13 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | 19 | ||
| 20 | #include <mach/hardware.h> | 20 | #include <mach/pxa320.h> |
| 21 | #include <mach/mfp.h> | ||
| 22 | #include <mach/pxa3xx-regs.h> | ||
| 23 | #include <mach/mfp-pxa320.h> | ||
| 24 | 21 | ||
| 25 | #include "generic.h" | 22 | #include "generic.h" |
| 26 | #include "devices.h" | 23 | #include "devices.h" |
| 27 | #include "clock.h" | 24 | #include "clock.h" |
| 28 | 25 | ||
| 29 | static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { | 26 | static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = { |
| 30 | 27 | ||
| 31 | MFP_ADDR_X(GPIO0, GPIO4, 0x0124), | 28 | MFP_ADDR_X(GPIO0, GPIO4, 0x0124), |
| 32 | MFP_ADDR_X(GPIO5, GPIO9, 0x028C), | 29 | MFP_ADDR_X(GPIO5, GPIO9, 0x028C), |
| @@ -89,8 +86,8 @@ static struct clk_lookup pxa320_clkregs[] = { | |||
| 89 | static int __init pxa320_init(void) | 86 | static int __init pxa320_init(void) |
| 90 | { | 87 | { |
| 91 | if (cpu_is_pxa320()) { | 88 | if (cpu_is_pxa320()) { |
| 92 | pxa3xx_init_mfp(); | 89 | mfp_init_base(io_p2v(MFPR_BASE)); |
| 93 | pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); | 90 | mfp_init_addr(pxa320_mfp_addr_map); |
| 94 | clks_register(ARRAY_AND_SIZE(pxa320_clkregs)); | 91 | clks_register(ARRAY_AND_SIZE(pxa320_clkregs)); |
| 95 | } | 92 | } |
| 96 | 93 | ||
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 490893824e78..b02d4544dc95 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/sysdev.h> | 23 | #include <linux/sysdev.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <mach/gpio.h> | ||
| 26 | #include <mach/pxa3xx-regs.h> | 27 | #include <mach/pxa3xx-regs.h> |
| 27 | #include <mach/reset.h> | 28 | #include <mach/reset.h> |
| 28 | #include <mach/ohci.h> | 29 | #include <mach/ohci.h> |
| @@ -538,7 +539,7 @@ void __init pxa3xx_init_irq(void) | |||
| 538 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | 539 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); |
| 539 | 540 | ||
| 540 | pxa_init_irq(56, pxa3xx_set_wake); | 541 | pxa_init_irq(56, pxa3xx_set_wake); |
| 541 | pxa_init_gpio(128, NULL); | 542 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); |
| 542 | } | 543 | } |
| 543 | 544 | ||
| 544 | /* | 545 | /* |
| @@ -594,7 +595,7 @@ static int __init pxa3xx_init(void) | |||
| 594 | 595 | ||
| 595 | clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); | 596 | clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); |
| 596 | 597 | ||
| 597 | if ((ret = pxa_init_dma(32))) | 598 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
| 598 | return ret; | 599 | return ret; |
| 599 | 600 | ||
| 600 | pxa3xx_init_pm(); | 601 | pxa3xx_init_pm(); |
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c index 13e6bfdfff60..71131742fffd 100644 --- a/arch/arm/mach-pxa/pxa930.c +++ b/arch/arm/mach-pxa/pxa930.c | |||
| @@ -16,10 +16,9 @@ | |||
| 16 | #include <linux/irq.h> | 16 | #include <linux/irq.h> |
| 17 | #include <linux/dma-mapping.h> | 17 | #include <linux/dma-mapping.h> |
| 18 | 18 | ||
| 19 | #include <mach/hardware.h> | 19 | #include <mach/pxa930.h> |
| 20 | #include <mach/mfp-pxa930.h> | ||
| 21 | 20 | ||
| 22 | static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = { | 21 | static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = { |
| 23 | 22 | ||
| 24 | MFP_ADDR(GPIO0, 0x02e0), | 23 | MFP_ADDR(GPIO0, 0x02e0), |
| 25 | MFP_ADDR(GPIO1, 0x02dc), | 24 | MFP_ADDR(GPIO1, 0x02dc), |
| @@ -180,8 +179,8 @@ static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = { | |||
| 180 | static int __init pxa930_init(void) | 179 | static int __init pxa930_init(void) |
| 181 | { | 180 | { |
| 182 | if (cpu_is_pxa930()) { | 181 | if (cpu_is_pxa930()) { |
| 183 | pxa3xx_init_mfp(); | 182 | mfp_init_base(io_p2v(MFPR_BASE)); |
| 184 | pxa3xx_mfp_init_addr(pxa930_mfp_addr_map); | 183 | mfp_init_addr(pxa930_mfp_addr_map); |
| 185 | } | 184 | } |
| 186 | 185 | ||
| 187 | return 0; | 186 | return 0; |
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index 00b2dc2a1074..df29d45fb4e7 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | #include <linux/io.h> | 10 | #include <linux/io.h> |
| 11 | #include <asm/proc-fns.h> | 11 | #include <asm/proc-fns.h> |
| 12 | 12 | ||
| 13 | #include <mach/pxa-regs.h> | 13 | #include <mach/regs-ost.h> |
| 14 | #include <mach/reset.h> | 14 | #include <mach/reset.h> |
| 15 | 15 | ||
| 16 | unsigned int reset_status; | 16 | unsigned int reset_status; |
| @@ -81,7 +81,7 @@ static void do_hw_reset(void) | |||
| 81 | OSMR3 = OSCR + 368640; /* ... in 100 ms */ | 81 | OSMR3 = OSCR + 368640; /* ... in 100 ms */ |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | void arch_reset(char mode) | 84 | void arch_reset(char mode, const char *cmd) |
| 85 | { | 85 | { |
| 86 | clear_reset_status(RESET_STATUS_ALL); | 86 | clear_reset_status(RESET_STATUS_ALL); |
| 87 | 87 | ||
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 5d02a7325586..ff8239991430 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c | |||
| @@ -25,11 +25,9 @@ | |||
| 25 | 25 | ||
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 28 | #include <mach/hardware.h> | 28 | |
| 29 | #include <mach/pxa3xx-regs.h> | 29 | #include <mach/pxa930.h> |
| 30 | #include <mach/mfp-pxa930.h> | ||
| 31 | #include <mach/i2c.h> | 30 | #include <mach/i2c.h> |
| 32 | #include <mach/regs-lcd.h> | ||
| 33 | #include <mach/pxafb.h> | 31 | #include <mach/pxafb.h> |
| 34 | 32 | ||
| 35 | #include "devices.h" | 33 | #include "devices.h" |
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index f0845c1b001c..16b4ec67e3b6 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | #include <mach/pm.h> | 27 | #include <mach/pm.h> |
| 28 | #include <mach/pxa-regs.h> | ||
| 29 | #include <mach/pxa2xx-gpio.h> | 28 | #include <mach/pxa2xx-gpio.h> |
| 30 | #include <mach/sharpsl.h> | 29 | #include <mach/sharpsl.h> |
| 31 | #include "sharpsl.h" | 30 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index a62c8375eb53..2ed95f369cfc 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #include <asm/assembler.h> | 15 | #include <asm/assembler.h> |
| 16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 17 | 17 | ||
| 18 | #include <mach/pxa-regs.h> | ||
| 19 | #include <mach/pxa2xx-regs.h> | 18 | #include <mach/pxa2xx-regs.h> |
| 20 | 19 | ||
| 21 | #define MDREFR_KDIV 0x200a4000 // all banks | 20 | #define MDREFR_KDIV 0x200a4000 // all banks |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 0d62d311d41a..8c61ddac119e 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
| @@ -44,9 +44,7 @@ | |||
| 44 | #include <asm/mach/map.h> | 44 | #include <asm/mach/map.h> |
| 45 | #include <asm/mach/irq.h> | 45 | #include <asm/mach/irq.h> |
| 46 | 46 | ||
| 47 | #include <mach/pxa-regs.h> | 47 | #include <mach/pxa27x.h> |
| 48 | #include <mach/pxa2xx-regs.h> | ||
| 49 | #include <mach/mfp-pxa27x.h> | ||
| 50 | #include <mach/pxa27x-udc.h> | 48 | #include <mach/pxa27x-udc.h> |
| 51 | #include <mach/reset.h> | 49 | #include <mach/reset.h> |
| 52 | #include <mach/i2c.h> | 50 | #include <mach/i2c.h> |
| @@ -709,10 +707,10 @@ static struct platform_device *devices[] __initdata = { | |||
| 709 | 707 | ||
| 710 | static void spitz_poweroff(void) | 708 | static void spitz_poweroff(void) |
| 711 | { | 709 | { |
| 712 | arm_machine_restart('g'); | 710 | arm_machine_restart('g', NULL); |
| 713 | } | 711 | } |
| 714 | 712 | ||
| 715 | static void spitz_restart(char mode) | 713 | static void spitz_restart(char mode, const char *cmd) |
| 716 | { | 714 | { |
| 717 | /* Bootloader magic for a reboot */ | 715 | /* Bootloader magic for a reboot */ |
| 718 | if((MSC0 & 0xffff0000) == 0x7ff00000) | 716 | if((MSC0 & 0xffff0000) == 0x7ff00000) |
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 072e77cfe5a3..2e4490562c9e 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/sharpsl.h> | 25 | #include <mach/sharpsl.h> |
| 26 | #include <mach/spitz.h> | 26 | #include <mach/spitz.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/pxa2xx-regs.h> | 27 | #include <mach/pxa2xx-regs.h> |
| 29 | #include <mach/pxa2xx-gpio.h> | 28 | #include <mach/pxa2xx-gpio.h> |
| 30 | #include "sharpsl.h" | 29 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 6f42004db3ed..965e38c6bafe 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c | |||
| @@ -33,7 +33,6 @@ | |||
| 33 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| 34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 35 | #include <mach/ssp.h> | 35 | #include <mach/ssp.h> |
| 36 | #include <mach/pxa-regs.h> | ||
| 37 | #include <mach/regs-ssp.h> | 36 | #include <mach/regs-ssp.h> |
| 38 | 37 | ||
| 39 | #define TIMEOUT 100000 | 38 | #define TIMEOUT 100000 |
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S index f3821cfda72f..29f5f5c180b7 100644 --- a/arch/arm/mach-pxa/standby.S +++ b/arch/arm/mach-pxa/standby.S | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <asm/assembler.h> | 13 | #include <asm/assembler.h> |
| 14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
| 15 | 15 | ||
| 16 | #include <mach/pxa-regs.h> | ||
| 17 | #include <mach/pxa2xx-regs.h> | 16 | #include <mach/pxa2xx-regs.h> |
| 18 | 17 | ||
| 19 | .text | 18 | .text |
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 58ef08a5224b..b75353a2ec75 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c | |||
| @@ -22,9 +22,8 @@ | |||
| 22 | 22 | ||
| 23 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 25 | #include <mach/hardware.h> | 25 | |
| 26 | #include <mach/pxa3xx-regs.h> | 26 | #include <mach/pxa930.h> |
| 27 | #include <mach/mfp-pxa930.h> | ||
| 28 | #include <mach/pxafb.h> | 27 | #include <mach/pxafb.h> |
| 29 | #include <mach/pxa27x_keypad.h> | 28 | #include <mach/pxa27x_keypad.h> |
| 30 | 29 | ||
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 95656a72268d..8eb3830fbb0b 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c | |||
| @@ -22,8 +22,7 @@ | |||
| 22 | #include <asm/div64.h> | 22 | #include <asm/div64.h> |
| 23 | #include <asm/mach/irq.h> | 23 | #include <asm/mach/irq.h> |
| 24 | #include <asm/mach/time.h> | 24 | #include <asm/mach/time.h> |
| 25 | #include <mach/hardware.h> | 25 | #include <mach/regs-ost.h> |
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | 26 | ||
| 28 | /* | 27 | /* |
| 29 | * This is PXA's sched_clock implementation. This has a resolution | 28 | * This is PXA's sched_clock implementation. This has a resolution |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 3332e5d0356c..6e8ade6ae339 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
| @@ -36,8 +36,8 @@ | |||
| 36 | 36 | ||
| 37 | #include <asm/setup.h> | 37 | #include <asm/setup.h> |
| 38 | #include <asm/mach-types.h> | 38 | #include <asm/mach-types.h> |
| 39 | #include <mach/pxa2xx-regs.h> | 39 | |
| 40 | #include <mach/mfp-pxa25x.h> | 40 | #include <mach/pxa25x.h> |
| 41 | #include <mach/reset.h> | 41 | #include <mach/reset.h> |
| 42 | #include <mach/irda.h> | 42 | #include <mach/irda.h> |
| 43 | #include <mach/i2c.h> | 43 | #include <mach/i2c.h> |
| @@ -876,10 +876,10 @@ static struct platform_device *devices[] __initdata = { | |||
| 876 | 876 | ||
| 877 | static void tosa_poweroff(void) | 877 | static void tosa_poweroff(void) |
| 878 | { | 878 | { |
| 879 | arm_machine_restart('g'); | 879 | arm_machine_restart('g', NULL); |
| 880 | } | 880 | } |
| 881 | 881 | ||
| 882 | static void tosa_restart(char mode) | 882 | static void tosa_restart(char mode, const char *cmd) |
| 883 | { | 883 | { |
| 884 | /* Bootloader magic for a reboot */ | 884 | /* Bootloader magic for a reboot */ |
| 885 | if((MSC0 & 0xffff0000) == 0x7ff00000) | 885 | if((MSC0 & 0xffff0000) == 0x7ff00000) |
| @@ -919,7 +919,7 @@ static void __init tosa_init(void) | |||
| 919 | pxa2xx_set_spi_info(2, &pxa_ssp_master_info); | 919 | pxa2xx_set_spi_info(2, &pxa_ssp_master_info); |
| 920 | spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); | 920 | spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); |
| 921 | 921 | ||
| 922 | clk_add_alias("CLK_CK3P6MI", &tc6393xb_device.dev, "GPIO11_CLK", NULL); | 922 | clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL); |
| 923 | 923 | ||
| 924 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 924 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 925 | } | 925 | } |
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index a72e3add743c..f79c9cb70ae4 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
| @@ -39,10 +39,7 @@ | |||
| 39 | #include <asm/mach/irq.h> | 39 | #include <asm/mach/irq.h> |
| 40 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 41 | 41 | ||
| 42 | #include <mach/hardware.h> | 42 | #include <mach/pxa27x.h> |
| 43 | #include <mach/pxa-regs.h> | ||
| 44 | #include <mach/pxa2xx-regs.h> | ||
| 45 | #include <mach/mfp-pxa27x.h> | ||
| 46 | #include <mach/pxa2xx_spi.h> | 43 | #include <mach/pxa2xx_spi.h> |
| 47 | #include <mach/trizeps4.h> | 44 | #include <mach/trizeps4.h> |
| 48 | #include <mach/audio.h> | 45 | #include <mach/audio.h> |
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 4b3120dbc049..0e65344e9f53 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
| @@ -42,12 +42,9 @@ | |||
| 42 | #include <linux/mtd/partitions.h> | 42 | #include <linux/mtd/partitions.h> |
| 43 | #include <linux/mtd/physmap.h> | 43 | #include <linux/mtd/physmap.h> |
| 44 | 44 | ||
| 45 | #include <mach/pxa-regs.h> | 45 | #include <mach/pxa25x.h> |
| 46 | #include <mach/pxa2xx-regs.h> | ||
| 47 | #include <mach/bitfield.h> | ||
| 48 | #include <mach/audio.h> | 46 | #include <mach/audio.h> |
| 49 | #include <mach/pxafb.h> | 47 | #include <mach/pxafb.h> |
| 50 | #include <mach/mfp-pxa25x.h> | ||
| 51 | #include <mach/i2c.h> | 48 | #include <mach/i2c.h> |
| 52 | #include <mach/viper.h> | 49 | #include <mach/viper.h> |
| 53 | 50 | ||
| @@ -956,7 +953,7 @@ static struct map_desc viper_io_desc[] __initdata = { | |||
| 956 | }, | 953 | }, |
| 957 | { | 954 | { |
| 958 | .virtual = VIPER_PC104IO_BASE, | 955 | .virtual = VIPER_PC104IO_BASE, |
| 959 | .pfn = __phys_to_pfn(_PCMCIA1IO), | 956 | .pfn = __phys_to_pfn(0x30000000), |
| 960 | .length = 0x00800000, | 957 | .length = 0x00800000, |
| 961 | .type = MT_DEVICE, | 958 | .type = MT_DEVICE, |
| 962 | }, | 959 | }, |
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 46538885a58a..c1f73205d078 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c | |||
| @@ -18,9 +18,9 @@ | |||
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/i2c.h> | 19 | #include <linux/i2c.h> |
| 20 | #include <linux/i2c/pca953x.h> | 20 | #include <linux/i2c/pca953x.h> |
| 21 | #include <linux/gpio.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/gpio.h> | 23 | #include <mach/pxa300.h> |
| 23 | #include <mach/mfp-pxa300.h> | ||
| 24 | #include <mach/i2c.h> | 24 | #include <mach/i2c.h> |
| 25 | #include <mach/zylonite.h> | 25 | #include <mach/zylonite.h> |
| 26 | 26 | ||
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 28e4e623780b..4e1c488c6906 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
| 20 | 20 | ||
| 21 | #include <mach/mfp-pxa320.h> | 21 | #include <mach/pxa320.h> |
| 22 | #include <mach/zylonite.h> | 22 | #include <mach/zylonite.h> |
| 23 | 23 | ||
| 24 | #include "generic.h" | 24 | #include "generic.h" |
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index ad911854eb4c..b6ec10627776 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig | |||
| @@ -35,6 +35,7 @@ config MACH_REALVIEW_PB11MP | |||
| 35 | bool "Support RealView/PB11MPCore platform" | 35 | bool "Support RealView/PB11MPCore platform" |
| 36 | select CPU_V6 | 36 | select CPU_V6 |
| 37 | select ARM_GIC | 37 | select ARM_GIC |
| 38 | select HAVE_PATA_PLATFORM | ||
| 38 | help | 39 | help |
| 39 | Include support for the ARM(R) RealView MPCore Platform Baseboard. | 40 | Include support for the ARM(R) RealView MPCore Platform Baseboard. |
| 40 | PB11MPCore is a platform with an on-board ARM11MPCore and has | 41 | PB11MPCore is a platform with an on-board ARM11MPCore and has |
| @@ -51,6 +52,7 @@ config MACH_REALVIEW_PBA8 | |||
| 51 | bool "Support RealView/PB-A8 platform" | 52 | bool "Support RealView/PB-A8 platform" |
| 52 | select CPU_V7 | 53 | select CPU_V7 |
| 53 | select ARM_GIC | 54 | select ARM_GIC |
| 55 | select HAVE_PATA_PLATFORM | ||
| 54 | help | 56 | help |
| 55 | Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard. | 57 | Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard. |
| 56 | PB-A8 is a platform with an on-board Cortex-A8 and has support for | 58 | PB-A8 is a platform with an on-board Cortex-A8 and has support for |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index bd2aa4f16141..d6766685cfc7 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <linux/clockchips.h> | 29 | #include <linux/clockchips.h> |
| 30 | #include <linux/io.h> | 30 | #include <linux/io.h> |
| 31 | #include <linux/smc911x.h> | 31 | #include <linux/smc911x.h> |
| 32 | #include <linux/ata_platform.h> | ||
| 32 | 33 | ||
| 33 | #include <asm/clkdev.h> | 34 | #include <asm/clkdev.h> |
| 34 | #include <asm/system.h> | 35 | #include <asm/system.h> |
| @@ -150,6 +151,44 @@ int realview_eth_register(const char *name, struct resource *res) | |||
| 150 | return platform_device_register(&realview_eth_device); | 151 | return platform_device_register(&realview_eth_device); |
| 151 | } | 152 | } |
| 152 | 153 | ||
| 154 | struct platform_device realview_usb_device = { | ||
| 155 | .name = "isp1760", | ||
| 156 | .num_resources = 2, | ||
| 157 | }; | ||
| 158 | |||
| 159 | int realview_usb_register(struct resource *res) | ||
| 160 | { | ||
| 161 | realview_usb_device.resource = res; | ||
| 162 | return platform_device_register(&realview_usb_device); | ||
| 163 | } | ||
| 164 | |||
| 165 | static struct pata_platform_info pata_platform_data = { | ||
| 166 | .ioport_shift = 1, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct resource pata_resources[] = { | ||
| 170 | [0] = { | ||
| 171 | .start = REALVIEW_CF_BASE, | ||
| 172 | .end = REALVIEW_CF_BASE + 0xff, | ||
| 173 | .flags = IORESOURCE_MEM, | ||
| 174 | }, | ||
| 175 | [1] = { | ||
| 176 | .start = REALVIEW_CF_BASE + 0x100, | ||
| 177 | .end = REALVIEW_CF_BASE + SZ_4K - 1, | ||
| 178 | .flags = IORESOURCE_MEM, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | struct platform_device realview_cf_device = { | ||
| 183 | .name = "pata_platform", | ||
| 184 | .id = -1, | ||
| 185 | .num_resources = ARRAY_SIZE(pata_resources), | ||
| 186 | .resource = pata_resources, | ||
| 187 | .dev = { | ||
| 188 | .platform_data = &pata_platform_data, | ||
| 189 | }, | ||
| 190 | }; | ||
| 191 | |||
| 153 | static struct resource realview_i2c_resource = { | 192 | static struct resource realview_i2c_resource = { |
| 154 | .start = REALVIEW_I2C_BASE, | 193 | .start = REALVIEW_I2C_BASE, |
| 155 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, | 194 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, |
| @@ -158,11 +197,25 @@ static struct resource realview_i2c_resource = { | |||
| 158 | 197 | ||
| 159 | struct platform_device realview_i2c_device = { | 198 | struct platform_device realview_i2c_device = { |
| 160 | .name = "versatile-i2c", | 199 | .name = "versatile-i2c", |
| 161 | .id = -1, | 200 | .id = 0, |
| 162 | .num_resources = 1, | 201 | .num_resources = 1, |
| 163 | .resource = &realview_i2c_resource, | 202 | .resource = &realview_i2c_resource, |
| 164 | }; | 203 | }; |
| 165 | 204 | ||
| 205 | static struct i2c_board_info realview_i2c_board_info[] = { | ||
| 206 | { | ||
| 207 | I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1), | ||
| 208 | .type = "ds1338", | ||
| 209 | }, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static int __init realview_i2c_init(void) | ||
| 213 | { | ||
| 214 | return i2c_register_board_info(0, realview_i2c_board_info, | ||
| 215 | ARRAY_SIZE(realview_i2c_board_info)); | ||
| 216 | } | ||
| 217 | arch_initcall(realview_i2c_init); | ||
| 218 | |||
| 166 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) | 219 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
| 167 | 220 | ||
| 168 | static unsigned int realview_mmc_status(struct device *dev) | 221 | static unsigned int realview_mmc_status(struct device *dev) |
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 44269b162d49..21c08637683b 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h | |||
| @@ -45,6 +45,7 @@ static struct amba_device name##_device = { \ | |||
| 45 | } | 45 | } |
| 46 | 46 | ||
| 47 | extern struct platform_device realview_flash_device; | 47 | extern struct platform_device realview_flash_device; |
| 48 | extern struct platform_device realview_cf_device; | ||
| 48 | extern struct platform_device realview_i2c_device; | 49 | extern struct platform_device realview_i2c_device; |
| 49 | extern struct mmc_platform_data realview_mmc0_plat_data; | 50 | extern struct mmc_platform_data realview_mmc0_plat_data; |
| 50 | extern struct mmc_platform_data realview_mmc1_plat_data; | 51 | extern struct mmc_platform_data realview_mmc1_plat_data; |
| @@ -62,5 +63,6 @@ extern void realview_leds_event(led_event_t ledevt); | |||
| 62 | extern void realview_timer_init(unsigned int timer_irq); | 63 | extern void realview_timer_init(unsigned int timer_irq); |
| 63 | extern int realview_flash_register(struct resource *res, u32 num); | 64 | extern int realview_flash_register(struct resource *res, u32 num); |
| 64 | extern int realview_eth_register(const char *name, struct resource *res); | 65 | extern int realview_eth_register(const char *name, struct resource *res); |
| 66 | extern int realview_usb_register(struct resource *res); | ||
| 65 | 67 | ||
| 66 | #endif | 68 | #endif |
diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h index c8bed8f58bab..307f97b16e5b 100644 --- a/arch/arm/mach-realview/include/mach/board-pba8.h +++ b/arch/arm/mach-realview/include/mach/board-pba8.h | |||
| @@ -45,8 +45,6 @@ | |||
| 45 | #define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */ | 45 | #define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */ |
| 46 | #define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */ | 46 | #define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */ |
| 47 | #define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */ | 47 | #define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */ |
| 48 | #define REALVIEW_PBA8_CF_BASE 0x18000000 /* Compact flash */ | ||
| 49 | #define REALVIEW_PBA8_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */ | ||
| 50 | #define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ | 48 | #define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ |
| 51 | #define REALVIEW_PBA8_FLASH0_BASE 0x40000000 | 49 | #define REALVIEW_PBA8_FLASH0_BASE 0x40000000 |
| 52 | #define REALVIEW_PBA8_FLASH0_SIZE SZ_64M | 50 | #define REALVIEW_PBA8_FLASH0_SIZE SZ_64M |
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h index 793a3a332712..c8f50835fed2 100644 --- a/arch/arm/mach-realview/include/mach/platform.h +++ b/arch/arm/mach-realview/include/mach/platform.h | |||
| @@ -204,6 +204,12 @@ | |||
| 204 | #define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */ | 204 | #define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */ |
| 205 | 205 | ||
| 206 | /* | 206 | /* |
| 207 | * CompactFlash | ||
| 208 | */ | ||
| 209 | #define REALVIEW_CF_BASE 0x18000000 /* CompactFlash */ | ||
| 210 | #define REALVIEW_CF_MEM_BASE 0x18003000 /* SMC for CompactFlash */ | ||
| 211 | |||
| 212 | /* | ||
| 207 | * Disk on Chip | 213 | * Disk on Chip |
| 208 | */ | 214 | */ |
| 209 | #define REALVIEW_DOC_BASE 0x2C000000 | 215 | #define REALVIEW_DOC_BASE 0x2C000000 |
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h index a2f61c78adbf..1a15a441e027 100644 --- a/arch/arm/mach-realview/include/mach/system.h +++ b/arch/arm/mach-realview/include/mach/system.h | |||
| @@ -34,7 +34,7 @@ static inline void arch_idle(void) | |||
| 34 | cpu_do_idle(); | 34 | cpu_do_idle(); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | static inline void arch_reset(char mode) | 37 | static inline void arch_reset(char mode, const char *cmd) |
| 38 | { | 38 | { |
| 39 | void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET; | 39 | void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET; |
| 40 | unsigned int val; | 40 | unsigned int val; |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index bed39ed97613..c20fbef122b3 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -264,6 +264,19 @@ static int eth_device_register(void) | |||
| 264 | return realview_eth_register(name, realview_eb_eth_resources); | 264 | return realview_eth_register(name, realview_eb_eth_resources); |
| 265 | } | 265 | } |
| 266 | 266 | ||
| 267 | static struct resource realview_eb_isp1761_resources[] = { | ||
| 268 | [0] = { | ||
| 269 | .start = REALVIEW_EB_USB_BASE, | ||
| 270 | .end = REALVIEW_EB_USB_BASE + SZ_128K - 1, | ||
| 271 | .flags = IORESOURCE_MEM, | ||
| 272 | }, | ||
| 273 | [1] = { | ||
| 274 | .start = IRQ_EB_USB, | ||
| 275 | .end = IRQ_EB_USB, | ||
| 276 | .flags = IORESOURCE_IRQ, | ||
| 277 | }, | ||
| 278 | }; | ||
| 279 | |||
| 267 | static void __init gic_init_irq(void) | 280 | static void __init gic_init_irq(void) |
| 268 | { | 281 | { |
| 269 | if (core_tile_eb11mp() || core_tile_a9mp()) { | 282 | if (core_tile_eb11mp() || core_tile_a9mp()) { |
| @@ -323,6 +336,8 @@ static void realview_eb11mp_fixup(void) | |||
| 323 | /* platform devices */ | 336 | /* platform devices */ |
| 324 | realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; | 337 | realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; |
| 325 | realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; | 338 | realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; |
| 339 | realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB; | ||
| 340 | realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB; | ||
| 326 | } | 341 | } |
| 327 | 342 | ||
| 328 | static void __init realview_eb_timer_init(void) | 343 | static void __init realview_eb_timer_init(void) |
| @@ -366,6 +381,7 @@ static void __init realview_eb_init(void) | |||
| 366 | realview_flash_register(&realview_eb_flash_resource, 1); | 381 | realview_flash_register(&realview_eb_flash_resource, 1); |
| 367 | platform_device_register(&realview_i2c_device); | 382 | platform_device_register(&realview_i2c_device); |
| 368 | eth_device_register(); | 383 | eth_device_register(); |
| 384 | realview_usb_register(realview_eb_isp1761_resources); | ||
| 369 | 385 | ||
| 370 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 386 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 371 | struct amba_device *d = amba_devs[i]; | 387 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 8f0683c22140..a64b84a7a3df 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -222,6 +222,19 @@ static struct resource realview_pb1176_smsc911x_resources[] = { | |||
| 222 | }, | 222 | }, |
| 223 | }; | 223 | }; |
| 224 | 224 | ||
| 225 | static struct resource realview_pb1176_isp1761_resources[] = { | ||
| 226 | [0] = { | ||
| 227 | .start = REALVIEW_PB1176_USB_BASE, | ||
| 228 | .end = REALVIEW_PB1176_USB_BASE + SZ_128K - 1, | ||
| 229 | .flags = IORESOURCE_MEM, | ||
| 230 | }, | ||
| 231 | [1] = { | ||
| 232 | .start = IRQ_PB1176_USB, | ||
| 233 | .end = IRQ_PB1176_USB, | ||
| 234 | .flags = IORESOURCE_IRQ, | ||
| 235 | }, | ||
| 236 | }; | ||
| 237 | |||
| 225 | static void __init gic_init_irq(void) | 238 | static void __init gic_init_irq(void) |
| 226 | { | 239 | { |
| 227 | /* ARM1176 DevChip GIC, primary */ | 240 | /* ARM1176 DevChip GIC, primary */ |
| @@ -260,6 +273,8 @@ static void __init realview_pb1176_init(void) | |||
| 260 | 273 | ||
| 261 | realview_flash_register(&realview_pb1176_flash_resource, 1); | 274 | realview_flash_register(&realview_pb1176_flash_resource, 1); |
| 262 | realview_eth_register(NULL, realview_pb1176_smsc911x_resources); | 275 | realview_eth_register(NULL, realview_pb1176_smsc911x_resources); |
| 276 | platform_device_register(&realview_i2c_device); | ||
| 277 | realview_usb_register(realview_pb1176_isp1761_resources); | ||
| 263 | 278 | ||
| 264 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 279 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 265 | struct amba_device *d = amba_devs[i]; | 280 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 3ebdb2dadd6f..ea1e60eca359 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -230,31 +230,19 @@ static struct resource realview_pb11mp_smsc911x_resources[] = { | |||
| 230 | }, | 230 | }, |
| 231 | }; | 231 | }; |
| 232 | 232 | ||
| 233 | struct resource realview_pb11mp_cf_resources[] = { | 233 | static struct resource realview_pb11mp_isp1761_resources[] = { |
| 234 | [0] = { | 234 | [0] = { |
| 235 | .start = REALVIEW_PB11MP_CF_BASE, | 235 | .start = REALVIEW_PB11MP_USB_BASE, |
| 236 | .end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1, | 236 | .end = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1, |
| 237 | .flags = IORESOURCE_MEM, | 237 | .flags = IORESOURCE_MEM, |
| 238 | }, | 238 | }, |
| 239 | [1] = { | 239 | [1] = { |
| 240 | .start = REALVIEW_PB11MP_CF_MEM_BASE, | 240 | .start = IRQ_TC11MP_USB, |
| 241 | .end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1, | 241 | .end = IRQ_TC11MP_USB, |
| 242 | .flags = IORESOURCE_MEM, | ||
| 243 | }, | ||
| 244 | [2] = { | ||
| 245 | .start = -1, /* FIXME: Find correct irq */ | ||
| 246 | .end = -1, | ||
| 247 | .flags = IORESOURCE_IRQ, | 242 | .flags = IORESOURCE_IRQ, |
| 248 | }, | 243 | }, |
| 249 | }; | 244 | }; |
| 250 | 245 | ||
| 251 | struct platform_device realview_pb11mp_cf_device = { | ||
| 252 | .name = "compactflash", | ||
| 253 | .id = 0, | ||
| 254 | .num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources), | ||
| 255 | .resource = realview_pb11mp_cf_resources, | ||
| 256 | }; | ||
| 257 | |||
| 258 | static void __init gic_init_irq(void) | 246 | static void __init gic_init_irq(void) |
| 259 | { | 247 | { |
| 260 | unsigned int pldctrl; | 248 | unsigned int pldctrl; |
| @@ -308,7 +296,8 @@ static void __init realview_pb11mp_init(void) | |||
| 308 | ARRAY_SIZE(realview_pb11mp_flash_resource)); | 296 | ARRAY_SIZE(realview_pb11mp_flash_resource)); |
| 309 | realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); | 297 | realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); |
| 310 | platform_device_register(&realview_i2c_device); | 298 | platform_device_register(&realview_i2c_device); |
| 311 | platform_device_register(&realview_pb11mp_cf_device); | 299 | platform_device_register(&realview_cf_device); |
| 300 | realview_usb_register(realview_pb11mp_isp1761_resources); | ||
| 312 | 301 | ||
| 313 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 302 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 314 | struct amba_device *d = amba_devs[i]; | 303 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 34c94435d2d8..d6ac1eb86576 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c | |||
| @@ -221,31 +221,19 @@ static struct resource realview_pba8_smsc911x_resources[] = { | |||
| 221 | }, | 221 | }, |
| 222 | }; | 222 | }; |
| 223 | 223 | ||
| 224 | struct resource realview_pba8_cf_resources[] = { | 224 | static struct resource realview_pba8_isp1761_resources[] = { |
| 225 | [0] = { | 225 | [0] = { |
| 226 | .start = REALVIEW_PBA8_CF_BASE, | 226 | .start = REALVIEW_PBA8_USB_BASE, |
| 227 | .end = REALVIEW_PBA8_CF_BASE + SZ_4K - 1, | 227 | .end = REALVIEW_PBA8_USB_BASE + SZ_128K - 1, |
| 228 | .flags = IORESOURCE_MEM, | 228 | .flags = IORESOURCE_MEM, |
| 229 | }, | 229 | }, |
| 230 | [1] = { | 230 | [1] = { |
| 231 | .start = REALVIEW_PBA8_CF_MEM_BASE, | 231 | .start = IRQ_PBA8_USB, |
| 232 | .end = REALVIEW_PBA8_CF_MEM_BASE + SZ_4K - 1, | 232 | .end = IRQ_PBA8_USB, |
| 233 | .flags = IORESOURCE_MEM, | ||
| 234 | }, | ||
| 235 | [2] = { | ||
| 236 | .start = -1, /* FIXME: Find correct irq */ | ||
| 237 | .end = -1, | ||
| 238 | .flags = IORESOURCE_IRQ, | 233 | .flags = IORESOURCE_IRQ, |
| 239 | }, | 234 | }, |
| 240 | }; | 235 | }; |
| 241 | 236 | ||
| 242 | struct platform_device realview_pba8_cf_device = { | ||
| 243 | .name = "compactflash", | ||
| 244 | .id = 0, | ||
| 245 | .num_resources = ARRAY_SIZE(realview_pba8_cf_resources), | ||
| 246 | .resource = realview_pba8_cf_resources, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static void __init gic_init_irq(void) | 237 | static void __init gic_init_irq(void) |
| 250 | { | 238 | { |
| 251 | /* ARM PB-A8 on-board GIC */ | 239 | /* ARM PB-A8 on-board GIC */ |
| @@ -276,7 +264,8 @@ static void __init realview_pba8_init(void) | |||
| 276 | ARRAY_SIZE(realview_pba8_flash_resource)); | 264 | ARRAY_SIZE(realview_pba8_flash_resource)); |
| 277 | realview_eth_register(NULL, realview_pba8_smsc911x_resources); | 265 | realview_eth_register(NULL, realview_pba8_smsc911x_resources); |
| 278 | platform_device_register(&realview_i2c_device); | 266 | platform_device_register(&realview_i2c_device); |
| 279 | platform_device_register(&realview_pba8_cf_device); | 267 | platform_device_register(&realview_cf_device); |
| 268 | realview_usb_register(realview_pba8_isp1761_resources); | ||
| 280 | 269 | ||
| 281 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 270 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 282 | struct amba_device *d = amba_devs[i]; | 271 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c index 7958a30f8932..c47d974d52bd 100644 --- a/arch/arm/mach-rpc/dma.c +++ b/arch/arm/mach-rpc/dma.c | |||
| @@ -26,6 +26,16 @@ | |||
| 26 | #include <asm/mach/dma.h> | 26 | #include <asm/mach/dma.h> |
| 27 | #include <asm/hardware/iomd.h> | 27 | #include <asm/hardware/iomd.h> |
| 28 | 28 | ||
| 29 | struct iomd_dma { | ||
| 30 | struct dma_struct dma; | ||
| 31 | unsigned int state; | ||
| 32 | unsigned long base; /* Controller base address */ | ||
| 33 | int irq; /* Controller IRQ */ | ||
| 34 | struct scatterlist cur_sg; /* Current controller buffer */ | ||
| 35 | dma_addr_t dma_addr; | ||
| 36 | unsigned int dma_len; | ||
| 37 | }; | ||
| 38 | |||
| 29 | #if 0 | 39 | #if 0 |
| 30 | typedef enum { | 40 | typedef enum { |
| 31 | dma_size_8 = 1, | 41 | dma_size_8 = 1, |
| @@ -44,15 +54,15 @@ typedef enum { | |||
| 44 | #define CR (IOMD_IO0CR - IOMD_IO0CURA) | 54 | #define CR (IOMD_IO0CR - IOMD_IO0CURA) |
| 45 | #define ST (IOMD_IO0ST - IOMD_IO0CURA) | 55 | #define ST (IOMD_IO0ST - IOMD_IO0CURA) |
| 46 | 56 | ||
| 47 | static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma) | 57 | static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma) |
| 48 | { | 58 | { |
| 49 | unsigned long end, offset, flags = 0; | 59 | unsigned long end, offset, flags = 0; |
| 50 | 60 | ||
| 51 | if (dma->sg) { | 61 | if (idma->dma.sg) { |
| 52 | sg->dma_address = dma->sg->dma_address; | 62 | sg->dma_address = idma->dma_addr; |
| 53 | offset = sg->dma_address & ~PAGE_MASK; | 63 | offset = sg->dma_address & ~PAGE_MASK; |
| 54 | 64 | ||
| 55 | end = offset + dma->sg->length; | 65 | end = offset + idma->dma_len; |
| 56 | 66 | ||
| 57 | if (end > PAGE_SIZE) | 67 | if (end > PAGE_SIZE) |
| 58 | end = PAGE_SIZE; | 68 | end = PAGE_SIZE; |
| @@ -62,15 +72,17 @@ static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma) | |||
| 62 | 72 | ||
| 63 | sg->length = end - TRANSFER_SIZE; | 73 | sg->length = end - TRANSFER_SIZE; |
| 64 | 74 | ||
| 65 | dma->sg->length -= end - offset; | 75 | idma->dma_len -= end - offset; |
| 66 | dma->sg->dma_address += end - offset; | 76 | idma->dma_addr += end - offset; |
| 67 | 77 | ||
| 68 | if (dma->sg->length == 0) { | 78 | if (idma->dma_len == 0) { |
| 69 | if (dma->sgcount > 1) { | 79 | if (idma->dma.sgcount > 1) { |
| 70 | dma->sg++; | 80 | idma->dma.sg = sg_next(idma->dma.sg); |
| 71 | dma->sgcount--; | 81 | idma->dma_addr = idma->dma.sg->dma_address; |
| 82 | idma->dma_len = idma->dma.sg->length; | ||
| 83 | idma->dma.sgcount--; | ||
| 72 | } else { | 84 | } else { |
| 73 | dma->sg = NULL; | 85 | idma->dma.sg = NULL; |
| 74 | flags |= DMA_END_S; | 86 | flags |= DMA_END_S; |
| 75 | } | 87 | } |
| 76 | } | 88 | } |
| @@ -85,8 +97,8 @@ static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma) | |||
| 85 | 97 | ||
| 86 | static irqreturn_t iomd_dma_handle(int irq, void *dev_id) | 98 | static irqreturn_t iomd_dma_handle(int irq, void *dev_id) |
| 87 | { | 99 | { |
| 88 | dma_t *dma = (dma_t *)dev_id; | 100 | struct iomd_dma *idma = dev_id; |
| 89 | unsigned long base = dma->dma_base; | 101 | unsigned long base = idma->base; |
| 90 | 102 | ||
| 91 | do { | 103 | do { |
| 92 | unsigned int status; | 104 | unsigned int status; |
| @@ -95,93 +107,99 @@ static irqreturn_t iomd_dma_handle(int irq, void *dev_id) | |||
| 95 | if (!(status & DMA_ST_INT)) | 107 | if (!(status & DMA_ST_INT)) |
| 96 | return IRQ_HANDLED; | 108 | return IRQ_HANDLED; |
| 97 | 109 | ||
| 98 | if ((dma->state ^ status) & DMA_ST_AB) | 110 | if ((idma->state ^ status) & DMA_ST_AB) |
| 99 | iomd_get_next_sg(&dma->cur_sg, dma); | 111 | iomd_get_next_sg(&idma->cur_sg, idma); |
| 100 | 112 | ||
| 101 | switch (status & (DMA_ST_OFL | DMA_ST_AB)) { | 113 | switch (status & (DMA_ST_OFL | DMA_ST_AB)) { |
| 102 | case DMA_ST_OFL: /* OIA */ | 114 | case DMA_ST_OFL: /* OIA */ |
| 103 | case DMA_ST_AB: /* .IB */ | 115 | case DMA_ST_AB: /* .IB */ |
| 104 | iomd_writel(dma->cur_sg.dma_address, base + CURA); | 116 | iomd_writel(idma->cur_sg.dma_address, base + CURA); |
| 105 | iomd_writel(dma->cur_sg.length, base + ENDA); | 117 | iomd_writel(idma->cur_sg.length, base + ENDA); |
| 106 | dma->state = DMA_ST_AB; | 118 | idma->state = DMA_ST_AB; |
| 107 | break; | 119 | break; |
| 108 | 120 | ||
| 109 | case DMA_ST_OFL | DMA_ST_AB: /* OIB */ | 121 | case DMA_ST_OFL | DMA_ST_AB: /* OIB */ |
| 110 | case 0: /* .IA */ | 122 | case 0: /* .IA */ |
| 111 | iomd_writel(dma->cur_sg.dma_address, base + CURB); | 123 | iomd_writel(idma->cur_sg.dma_address, base + CURB); |
| 112 | iomd_writel(dma->cur_sg.length, base + ENDB); | 124 | iomd_writel(idma->cur_sg.length, base + ENDB); |
| 113 | dma->state = 0; | 125 | idma->state = 0; |
| 114 | break; | 126 | break; |
| 115 | } | 127 | } |
| 116 | 128 | ||
| 117 | if (status & DMA_ST_OFL && | 129 | if (status & DMA_ST_OFL && |
| 118 | dma->cur_sg.length == (DMA_END_S|DMA_END_L)) | 130 | idma->cur_sg.length == (DMA_END_S|DMA_END_L)) |
| 119 | break; | 131 | break; |
| 120 | } while (1); | 132 | } while (1); |
| 121 | 133 | ||
| 122 | dma->state = ~DMA_ST_AB; | 134 | idma->state = ~DMA_ST_AB; |
| 123 | disable_irq(irq); | 135 | disable_irq(irq); |
| 124 | 136 | ||
| 125 | return IRQ_HANDLED; | 137 | return IRQ_HANDLED; |
| 126 | } | 138 | } |
| 127 | 139 | ||
| 128 | static int iomd_request_dma(dmach_t channel, dma_t *dma) | 140 | static int iomd_request_dma(unsigned int chan, dma_t *dma) |
| 129 | { | 141 | { |
| 130 | return request_irq(dma->dma_irq, iomd_dma_handle, | 142 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 131 | IRQF_DISABLED, dma->device_id, dma); | 143 | |
| 144 | return request_irq(idma->irq, iomd_dma_handle, | ||
| 145 | IRQF_DISABLED, idma->dma.device_id, idma); | ||
| 132 | } | 146 | } |
| 133 | 147 | ||
| 134 | static void iomd_free_dma(dmach_t channel, dma_t *dma) | 148 | static void iomd_free_dma(unsigned int chan, dma_t *dma) |
| 135 | { | 149 | { |
| 136 | free_irq(dma->dma_irq, dma); | 150 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 151 | |||
| 152 | free_irq(idma->irq, idma); | ||
| 137 | } | 153 | } |
| 138 | 154 | ||
| 139 | static void iomd_enable_dma(dmach_t channel, dma_t *dma) | 155 | static void iomd_enable_dma(unsigned int chan, dma_t *dma) |
| 140 | { | 156 | { |
| 141 | unsigned long dma_base = dma->dma_base; | 157 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 158 | unsigned long dma_base = idma->base; | ||
| 142 | unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; | 159 | unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; |
| 143 | 160 | ||
| 144 | if (dma->invalid) { | 161 | if (idma->dma.invalid) { |
| 145 | dma->invalid = 0; | 162 | idma->dma.invalid = 0; |
| 146 | 163 | ||
| 147 | /* | 164 | /* |
| 148 | * Cope with ISA-style drivers which expect cache | 165 | * Cope with ISA-style drivers which expect cache |
| 149 | * coherence. | 166 | * coherence. |
| 150 | */ | 167 | */ |
| 151 | if (!dma->sg) { | 168 | if (!idma->dma.sg) { |
| 152 | dma->sg = &dma->buf; | 169 | idma->dma.sg = &idma->dma.buf; |
| 153 | dma->sgcount = 1; | 170 | idma->dma.sgcount = 1; |
| 154 | dma->buf.length = dma->count; | 171 | idma->dma.buf.length = idma->dma.count; |
| 155 | dma->buf.dma_address = dma_map_single(NULL, | 172 | idma->dma.buf.dma_address = dma_map_single(NULL, |
| 156 | dma->addr, dma->count, | 173 | idma->dma.addr, idma->dma.count, |
| 157 | dma->dma_mode == DMA_MODE_READ ? | 174 | idma->dma.dma_mode == DMA_MODE_READ ? |
| 158 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | 175 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 159 | } | 176 | } |
| 160 | 177 | ||
| 161 | iomd_writeb(DMA_CR_C, dma_base + CR); | 178 | iomd_writeb(DMA_CR_C, dma_base + CR); |
| 162 | dma->state = DMA_ST_AB; | 179 | idma->state = DMA_ST_AB; |
| 163 | } | 180 | } |
| 164 | 181 | ||
| 165 | if (dma->dma_mode == DMA_MODE_READ) | 182 | if (idma->dma.dma_mode == DMA_MODE_READ) |
| 166 | ctrl |= DMA_CR_D; | 183 | ctrl |= DMA_CR_D; |
| 167 | 184 | ||
| 168 | iomd_writeb(ctrl, dma_base + CR); | 185 | iomd_writeb(ctrl, dma_base + CR); |
| 169 | enable_irq(dma->dma_irq); | 186 | enable_irq(idma->irq); |
| 170 | } | 187 | } |
| 171 | 188 | ||
| 172 | static void iomd_disable_dma(dmach_t channel, dma_t *dma) | 189 | static void iomd_disable_dma(unsigned int chan, dma_t *dma) |
| 173 | { | 190 | { |
| 174 | unsigned long dma_base = dma->dma_base; | 191 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 192 | unsigned long dma_base = idma->base; | ||
| 175 | unsigned long flags; | 193 | unsigned long flags; |
| 176 | 194 | ||
| 177 | local_irq_save(flags); | 195 | local_irq_save(flags); |
| 178 | if (dma->state != ~DMA_ST_AB) | 196 | if (idma->state != ~DMA_ST_AB) |
| 179 | disable_irq(dma->dma_irq); | 197 | disable_irq(idma->irq); |
| 180 | iomd_writeb(0, dma_base + CR); | 198 | iomd_writeb(0, dma_base + CR); |
| 181 | local_irq_restore(flags); | 199 | local_irq_restore(flags); |
| 182 | } | 200 | } |
| 183 | 201 | ||
| 184 | static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle) | 202 | static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle) |
| 185 | { | 203 | { |
| 186 | int tcr, speed; | 204 | int tcr, speed; |
| 187 | 205 | ||
| @@ -197,7 +215,7 @@ static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle) | |||
| 197 | tcr = iomd_readb(IOMD_DMATCR); | 215 | tcr = iomd_readb(IOMD_DMATCR); |
| 198 | speed &= 3; | 216 | speed &= 3; |
| 199 | 217 | ||
| 200 | switch (channel) { | 218 | switch (chan) { |
| 201 | case DMA_0: | 219 | case DMA_0: |
| 202 | tcr = (tcr & ~0x03) | speed; | 220 | tcr = (tcr & ~0x03) | speed; |
| 203 | break; | 221 | break; |
| @@ -236,16 +254,22 @@ static struct fiq_handler fh = { | |||
| 236 | .name = "floppydma" | 254 | .name = "floppydma" |
| 237 | }; | 255 | }; |
| 238 | 256 | ||
| 239 | static void floppy_enable_dma(dmach_t channel, dma_t *dma) | 257 | struct floppy_dma { |
| 258 | struct dma_struct dma; | ||
| 259 | unsigned int fiq; | ||
| 260 | }; | ||
| 261 | |||
| 262 | static void floppy_enable_dma(unsigned int chan, dma_t *dma) | ||
| 240 | { | 263 | { |
| 264 | struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); | ||
| 241 | void *fiqhandler_start; | 265 | void *fiqhandler_start; |
| 242 | unsigned int fiqhandler_length; | 266 | unsigned int fiqhandler_length; |
| 243 | struct pt_regs regs; | 267 | struct pt_regs regs; |
| 244 | 268 | ||
| 245 | if (dma->sg) | 269 | if (fdma->dma.sg) |
| 246 | BUG(); | 270 | BUG(); |
| 247 | 271 | ||
| 248 | if (dma->dma_mode == DMA_MODE_READ) { | 272 | if (fdma->dma.dma_mode == DMA_MODE_READ) { |
| 249 | extern unsigned char floppy_fiqin_start, floppy_fiqin_end; | 273 | extern unsigned char floppy_fiqin_start, floppy_fiqin_end; |
| 250 | fiqhandler_start = &floppy_fiqin_start; | 274 | fiqhandler_start = &floppy_fiqin_start; |
| 251 | fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start; | 275 | fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start; |
| @@ -255,8 +279,8 @@ static void floppy_enable_dma(dmach_t channel, dma_t *dma) | |||
| 255 | fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start; | 279 | fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start; |
| 256 | } | 280 | } |
| 257 | 281 | ||
| 258 | regs.ARM_r9 = dma->count; | 282 | regs.ARM_r9 = fdma->dma.count; |
| 259 | regs.ARM_r10 = (unsigned long)dma->addr; | 283 | regs.ARM_r10 = (unsigned long)fdma->dma.addr; |
| 260 | regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE; | 284 | regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE; |
| 261 | 285 | ||
| 262 | if (claim_fiq(&fh)) { | 286 | if (claim_fiq(&fh)) { |
| @@ -266,16 +290,17 @@ static void floppy_enable_dma(dmach_t channel, dma_t *dma) | |||
| 266 | 290 | ||
| 267 | set_fiq_handler(fiqhandler_start, fiqhandler_length); | 291 | set_fiq_handler(fiqhandler_start, fiqhandler_length); |
| 268 | set_fiq_regs(®s); | 292 | set_fiq_regs(®s); |
| 269 | enable_fiq(dma->dma_irq); | 293 | enable_fiq(fdma->fiq); |
| 270 | } | 294 | } |
| 271 | 295 | ||
| 272 | static void floppy_disable_dma(dmach_t channel, dma_t *dma) | 296 | static void floppy_disable_dma(unsigned int chan, dma_t *dma) |
| 273 | { | 297 | { |
| 274 | disable_fiq(dma->dma_irq); | 298 | struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); |
| 299 | disable_fiq(fdma->fiq); | ||
| 275 | release_fiq(&fh); | 300 | release_fiq(&fh); |
| 276 | } | 301 | } |
| 277 | 302 | ||
| 278 | static int floppy_get_residue(dmach_t channel, dma_t *dma) | 303 | static int floppy_get_residue(unsigned int chan, dma_t *dma) |
| 279 | { | 304 | { |
| 280 | struct pt_regs regs; | 305 | struct pt_regs regs; |
| 281 | get_fiq_regs(®s); | 306 | get_fiq_regs(®s); |
| @@ -292,7 +317,7 @@ static struct dma_ops floppy_dma_ops = { | |||
| 292 | /* | 317 | /* |
| 293 | * This is virtual DMA - we don't need anything here. | 318 | * This is virtual DMA - we don't need anything here. |
| 294 | */ | 319 | */ |
| 295 | static void sound_enable_disable_dma(dmach_t channel, dma_t *dma) | 320 | static void sound_enable_disable_dma(unsigned int chan, dma_t *dma) |
| 296 | { | 321 | { |
| 297 | } | 322 | } |
| 298 | 323 | ||
| @@ -302,8 +327,24 @@ static struct dma_ops sound_dma_ops = { | |||
| 302 | .disable = sound_enable_disable_dma, | 327 | .disable = sound_enable_disable_dma, |
| 303 | }; | 328 | }; |
| 304 | 329 | ||
| 305 | void __init arch_dma_init(dma_t *dma) | 330 | static struct iomd_dma iomd_dma[6]; |
| 331 | |||
| 332 | static struct floppy_dma floppy_dma = { | ||
| 333 | .dma = { | ||
| 334 | .d_ops = &floppy_dma_ops, | ||
| 335 | }, | ||
| 336 | .fiq = FIQ_FLOPPYDATA, | ||
| 337 | }; | ||
| 338 | |||
| 339 | static dma_t sound_dma = { | ||
| 340 | .d_ops = &sound_dma_ops, | ||
| 341 | }; | ||
| 342 | |||
| 343 | static int __init rpc_dma_init(void) | ||
| 306 | { | 344 | { |
| 345 | unsigned int i; | ||
| 346 | int ret; | ||
| 347 | |||
| 307 | iomd_writeb(0, IOMD_IO0CR); | 348 | iomd_writeb(0, IOMD_IO0CR); |
| 308 | iomd_writeb(0, IOMD_IO1CR); | 349 | iomd_writeb(0, IOMD_IO1CR); |
| 309 | iomd_writeb(0, IOMD_IO2CR); | 350 | iomd_writeb(0, IOMD_IO2CR); |
| @@ -311,31 +352,39 @@ void __init arch_dma_init(dma_t *dma) | |||
| 311 | 352 | ||
| 312 | iomd_writeb(0xa0, IOMD_DMATCR); | 353 | iomd_writeb(0xa0, IOMD_DMATCR); |
| 313 | 354 | ||
| 314 | dma[DMA_0].dma_base = IOMD_IO0CURA; | ||
| 315 | dma[DMA_0].dma_irq = IRQ_DMA0; | ||
| 316 | dma[DMA_0].d_ops = &iomd_dma_ops; | ||
| 317 | dma[DMA_1].dma_base = IOMD_IO1CURA; | ||
| 318 | dma[DMA_1].dma_irq = IRQ_DMA1; | ||
| 319 | dma[DMA_1].d_ops = &iomd_dma_ops; | ||
| 320 | dma[DMA_2].dma_base = IOMD_IO2CURA; | ||
| 321 | dma[DMA_2].dma_irq = IRQ_DMA2; | ||
| 322 | dma[DMA_2].d_ops = &iomd_dma_ops; | ||
| 323 | dma[DMA_3].dma_base = IOMD_IO3CURA; | ||
| 324 | dma[DMA_3].dma_irq = IRQ_DMA3; | ||
| 325 | dma[DMA_3].d_ops = &iomd_dma_ops; | ||
| 326 | dma[DMA_S0].dma_base = IOMD_SD0CURA; | ||
| 327 | dma[DMA_S0].dma_irq = IRQ_DMAS0; | ||
| 328 | dma[DMA_S0].d_ops = &iomd_dma_ops; | ||
| 329 | dma[DMA_S1].dma_base = IOMD_SD1CURA; | ||
| 330 | dma[DMA_S1].dma_irq = IRQ_DMAS1; | ||
| 331 | dma[DMA_S1].d_ops = &iomd_dma_ops; | ||
| 332 | dma[DMA_VIRTUAL_FLOPPY].dma_irq = FIQ_FLOPPYDATA; | ||
| 333 | dma[DMA_VIRTUAL_FLOPPY].d_ops = &floppy_dma_ops; | ||
| 334 | dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops; | ||
| 335 | |||
| 336 | /* | 355 | /* |
| 337 | * Setup DMA channels 2,3 to be for podules | 356 | * Setup DMA channels 2,3 to be for podules |
| 338 | * and channels 0,1 for internal devices | 357 | * and channels 0,1 for internal devices |
| 339 | */ | 358 | */ |
| 340 | iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); | 359 | iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); |
| 360 | |||
| 361 | iomd_dma[DMA_0].base = IOMD_IO0CURA; | ||
| 362 | iomd_dma[DMA_0].irq = IRQ_DMA0; | ||
| 363 | iomd_dma[DMA_1].base = IOMD_IO1CURA; | ||
| 364 | iomd_dma[DMA_1].irq = IRQ_DMA1; | ||
| 365 | iomd_dma[DMA_2].base = IOMD_IO2CURA; | ||
| 366 | iomd_dma[DMA_2].irq = IRQ_DMA2; | ||
| 367 | iomd_dma[DMA_3].base = IOMD_IO3CURA; | ||
| 368 | iomd_dma[DMA_3].irq = IRQ_DMA3; | ||
| 369 | iomd_dma[DMA_S0].base = IOMD_SD0CURA; | ||
| 370 | iomd_dma[DMA_S0].irq = IRQ_DMAS0; | ||
| 371 | iomd_dma[DMA_S1].base = IOMD_SD1CURA; | ||
| 372 | iomd_dma[DMA_S1].irq = IRQ_DMAS1; | ||
| 373 | |||
| 374 | for (i = DMA_0; i <= DMA_S1; i++) { | ||
| 375 | iomd_dma[i].dma.d_ops = &iomd_dma_ops; | ||
| 376 | |||
| 377 | ret = isa_dma_add(i, &iomd_dma[i].dma); | ||
| 378 | if (ret) | ||
| 379 | printk("IOMDDMA%u: unable to register: %d\n", i, ret); | ||
| 380 | } | ||
| 381 | |||
| 382 | ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma); | ||
| 383 | if (ret) | ||
| 384 | printk("IOMDFLOPPY: unable to register: %d\n", ret); | ||
| 385 | ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma); | ||
| 386 | if (ret) | ||
| 387 | printk("IOMDSOUND: unable to register: %d\n", ret); | ||
| 388 | return 0; | ||
| 341 | } | 389 | } |
| 390 | core_initcall(rpc_dma_init); | ||
diff --git a/arch/arm/mach-rpc/include/mach/isa-dma.h b/arch/arm/mach-rpc/include/mach/isa-dma.h index bad720548587..67bfc6719c34 100644 --- a/arch/arm/mach-rpc/include/mach/isa-dma.h +++ b/arch/arm/mach-rpc/include/mach/isa-dma.h | |||
| @@ -23,5 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | #define DMA_FLOPPY DMA_VIRTUAL_FLOPPY | 24 | #define DMA_FLOPPY DMA_VIRTUAL_FLOPPY |
| 25 | 25 | ||
| 26 | #define IOMD_DMA_BOUNDARY (PAGE_SIZE - 1) | ||
| 27 | |||
| 26 | #endif /* _ASM_ARCH_DMA_H */ | 28 | #endif /* _ASM_ARCH_DMA_H */ |
| 27 | 29 | ||
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h index bd7268ba17e2..45c7b935dc45 100644 --- a/arch/arm/mach-rpc/include/mach/system.h +++ b/arch/arm/mach-rpc/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static inline void arch_idle(void) | |||
| 16 | cpu_do_idle(); | 16 | cpu_do_idle(); |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static inline void arch_reset(char mode) | 19 | static inline void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | iomd_writeb(0, IOMD_ROMCR0); | 21 | iomd_writeb(0, IOMD_ROMCR0); |
| 22 | 22 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h new file mode 100644 index 000000000000..ce1ec69806a1 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * S3C2410 - GPIO bank numbering | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) | ||
| 15 | |||
| 16 | #define S3C2410_GPIO_BANKA (32*0) | ||
| 17 | #define S3C2410_GPIO_BANKB (32*1) | ||
| 18 | #define S3C2410_GPIO_BANKC (32*2) | ||
| 19 | #define S3C2410_GPIO_BANKD (32*3) | ||
| 20 | #define S3C2410_GPIO_BANKE (32*4) | ||
| 21 | #define S3C2410_GPIO_BANKF (32*5) | ||
| 22 | #define S3C2410_GPIO_BANKG (32*6) | ||
| 23 | #define S3C2410_GPIO_BANKH (32*7) | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 00476a573bbe..51a88cf9526b 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h | |||
| @@ -23,3 +23,6 @@ | |||
| 23 | #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) | 23 | #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) |
| 24 | 24 | ||
| 25 | #include <asm-generic/gpio.h> | 25 | #include <asm-generic/gpio.h> |
| 26 | #include <mach/gpio-nrs.h> | ||
| 27 | |||
| 28 | #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 49efce8cd4a7..2a2384ffa7b1 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h | |||
| @@ -80,7 +80,7 @@ | |||
| 80 | #define IRQ_EINT22 S3C2410_IRQ(50) | 80 | #define IRQ_EINT22 S3C2410_IRQ(50) |
| 81 | #define IRQ_EINT23 S3C2410_IRQ(51) | 81 | #define IRQ_EINT23 S3C2410_IRQ(51) |
| 82 | 82 | ||
| 83 | 83 | #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) | |
| 84 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) | 84 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) |
| 85 | 85 | ||
| 86 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) | 86 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 321077613067..35a03df473fc 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
| @@ -14,16 +14,7 @@ | |||
| 14 | #ifndef __ASM_ARCH_REGS_GPIO_H | 14 | #ifndef __ASM_ARCH_REGS_GPIO_H |
| 15 | #define __ASM_ARCH_REGS_GPIO_H | 15 | #define __ASM_ARCH_REGS_GPIO_H |
| 16 | 16 | ||
| 17 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) | 17 | #include <mach/gpio-nrs.h> |
| 18 | |||
| 19 | #define S3C2410_GPIO_BANKA (32*0) | ||
| 20 | #define S3C2410_GPIO_BANKB (32*1) | ||
| 21 | #define S3C2410_GPIO_BANKC (32*2) | ||
| 22 | #define S3C2410_GPIO_BANKD (32*3) | ||
| 23 | #define S3C2410_GPIO_BANKE (32*4) | ||
| 24 | #define S3C2410_GPIO_BANKF (32*5) | ||
| 25 | #define S3C2410_GPIO_BANKG (32*6) | ||
| 26 | #define S3C2410_GPIO_BANKH (32*7) | ||
| 27 | 18 | ||
| 28 | #ifdef CONFIG_CPU_S3C2400 | 19 | #ifdef CONFIG_CPU_S3C2400 |
| 29 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) | 20 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) |
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h index 7613d0a384ba..b8687f71c304 100644 --- a/arch/arm/mach-s3c2410/include/mach/system-reset.h +++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | extern void (*s3c24xx_reset_hook)(void); | 22 | extern void (*s3c24xx_reset_hook)(void); |
| 23 | 23 | ||
| 24 | static void | 24 | static void |
| 25 | arch_reset(char mode) | 25 | arch_reset(char mode, const char *cmd) |
| 26 | { | 26 | { |
| 27 | struct clk *wdtclk; | 27 | struct clk *wdtclk; |
| 28 | 28 | ||
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 821a1668c3ac..7a7c4da4c256 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c | |||
| @@ -203,7 +203,7 @@ static void __init h1940_map_io(void) | |||
| 203 | #ifdef CONFIG_PM_H1940 | 203 | #ifdef CONFIG_PM_H1940 |
| 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); | 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); |
| 205 | #endif | 205 | #endif |
| 206 | s3c2410_pm_init(); | 206 | s3c_pm_init(); |
| 207 | } | 207 | } |
| 208 | 208 | ||
| 209 | static void __init h1940_init_irq(void) | 209 | static void __init h1940_init_irq(void) |
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 9678a53ceeb1..9f1ba9b63f70 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c | |||
| @@ -355,7 +355,7 @@ static void __init qt2410_machine_init(void) | |||
| 355 | s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); | 355 | s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); |
| 356 | 356 | ||
| 357 | platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); | 357 | platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); |
| 358 | s3c2410_pm_init(); | 358 | s3c_pm_init(); |
| 359 | } | 359 | } |
| 360 | 360 | ||
| 361 | MACHINE_START(QT2410, "QT2410") | 361 | MACHINE_START(QT2410, "QT2410") |
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index a6970f613192..87fc481d92d4 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c | |||
| @@ -37,21 +37,14 @@ | |||
| 37 | #include <plat/cpu.h> | 37 | #include <plat/cpu.h> |
| 38 | #include <plat/pm.h> | 38 | #include <plat/pm.h> |
| 39 | 39 | ||
| 40 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 41 | extern void pm_dbg(const char *fmt, ...); | ||
| 42 | #define DBG(fmt...) pm_dbg(fmt) | ||
| 43 | #else | ||
| 44 | #define DBG(fmt...) printk(KERN_DEBUG fmt) | ||
| 45 | #endif | ||
| 46 | |||
| 47 | static void s3c2410_pm_prepare(void) | 40 | static void s3c2410_pm_prepare(void) |
| 48 | { | 41 | { |
| 49 | /* ensure at least GSTATUS3 has the resume address */ | 42 | /* ensure at least GSTATUS3 has the resume address */ |
| 50 | 43 | ||
| 51 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); | 44 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); |
| 52 | 45 | ||
| 53 | DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); | 46 | S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); |
| 54 | DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); | 47 | S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); |
| 55 | 48 | ||
| 56 | if (machine_is_h1940()) { | 49 | if (machine_is_h1940()) { |
| 57 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); | 50 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); |
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index ecddbbb34832..72c266aee141 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c | |||
| @@ -494,7 +494,7 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) | |||
| 494 | * correct address to resume from. */ | 494 | * correct address to resume from. */ |
| 495 | 495 | ||
| 496 | __raw_writel(0x2BED, S3C2412_INFORM0); | 496 | __raw_writel(0x2BED, S3C2412_INFORM0); |
| 497 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1); | 497 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); |
| 498 | 498 | ||
| 499 | return 0; | 499 | return 0; |
| 500 | } | 500 | } |
| @@ -630,7 +630,7 @@ static void __init jive_machine_init(void) | |||
| 630 | 630 | ||
| 631 | /* initialise the power management now we've setup everything. */ | 631 | /* initialise the power management now we've setup everything. */ |
| 632 | 632 | ||
| 633 | s3c2410_pm_init(); | 633 | s3c_pm_init(); |
| 634 | 634 | ||
| 635 | s3c_device_nand.dev.platform_data = &jive_nand_info; | 635 | s3c_device_nand.dev.platform_data = &jive_nand_info; |
| 636 | 636 | ||
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c index 217e9e4ed45f..c9cfe40e21f6 100644 --- a/arch/arm/mach-s3c2412/pm.c +++ b/arch/arm/mach-s3c2412/pm.c | |||
| @@ -85,7 +85,7 @@ static struct sleep_save s3c2412_sleep[] = { | |||
| 85 | 85 | ||
| 86 | static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) | 86 | static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) |
| 87 | { | 87 | { |
| 88 | s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); | 88 | s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); |
| 89 | return 0; | 89 | return 0; |
| 90 | } | 90 | } |
| 91 | 91 | ||
| @@ -98,7 +98,7 @@ static int s3c2412_pm_resume(struct sys_device *dev) | |||
| 98 | tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; | 98 | tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; |
| 99 | __raw_writel(tmp, S3C2412_PWRCFG); | 99 | __raw_writel(tmp, S3C2412_PWRCFG); |
| 100 | 100 | ||
| 101 | s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); | 101 | s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); |
| 102 | return 0; | 102 | return 0; |
| 103 | } | 103 | } |
| 104 | 104 | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 12d378f84ad2..bc8d8d1ebd1a 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c | |||
| @@ -203,7 +203,7 @@ static void __init rx3715_init_machine(void) | |||
| 203 | #ifdef CONFIG_PM_H1940 | 203 | #ifdef CONFIG_PM_H1940 |
| 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); | 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); |
| 205 | #endif | 205 | #endif |
| 206 | s3c2410_pm_init(); | 206 | s3c_pm_init(); |
| 207 | 207 | ||
| 208 | s3c24xx_fb_set_platdata(&rx3715_fb_info); | 208 | s3c24xx_fb_set_platdata(&rx3715_fb_info); |
| 209 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); | 209 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); |
diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h index ae8c0e359783..83ce2a7a9dae 100644 --- a/arch/arm/mach-s3c24a0/include/mach/irqs.h +++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h | |||
| @@ -70,6 +70,8 @@ | |||
| 70 | #define IRQ_EINT17 S3C2410_IRQ(49) | 70 | #define IRQ_EINT17 S3C2410_IRQ(49) |
| 71 | #define IRQ_EINT18 S3C2410_IRQ(50) | 71 | #define IRQ_EINT18 S3C2410_IRQ(50) |
| 72 | 72 | ||
| 73 | #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00) | ||
| 74 | |||
| 73 | /* SUB IRQS */ | 75 | /* SUB IRQS */ |
| 74 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ | 76 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ |
| 75 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(52) | 77 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(52) |
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index cff27d813fc6..baf1c0f1ea5a 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h | |||
| @@ -52,6 +52,9 @@ | |||
| 52 | #define S3C64XX_PA_VIC0 (0x71200000) | 52 | #define S3C64XX_PA_VIC0 (0x71200000) |
| 53 | #define S3C64XX_PA_VIC1 (0x71300000) | 53 | #define S3C64XX_PA_VIC1 (0x71300000) |
| 54 | 54 | ||
| 55 | #define S3C64XX_PA_MODEM (0x74108000) | ||
| 56 | #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) | ||
| 57 | |||
| 55 | /* place VICs close together */ | 58 | /* place VICs close together */ |
| 56 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) | 59 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) |
| 57 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) | 60 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) |
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h index 652bbc403f0b..090cfd969bc7 100644 --- a/arch/arm/mach-s3c6400/include/mach/system.h +++ b/arch/arm/mach-s3c6400/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static void arch_idle(void) | |||
| 16 | /* nothing here yet */ | 16 | /* nothing here yet */ |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static void arch_reset(char mode) | 19 | static void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | /* nothing here yet */ | 21 | /* nothing here yet */ |
| 22 | } | 22 | } |
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index f99d9013905f..81ffff7ed498 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig | |||
| @@ -71,19 +71,9 @@ config SA1100_H3600 | |||
| 71 | <http://www.handhelds.org/Compaq/index.html#iPAQ_H3600> | 71 | <http://www.handhelds.org/Compaq/index.html#iPAQ_H3600> |
| 72 | <http://www.compaq.com/products/handhelds/pocketpc/> | 72 | <http://www.compaq.com/products/handhelds/pocketpc/> |
| 73 | 73 | ||
| 74 | config SA1100_H3800 | ||
| 75 | bool "Compaq iPAQ H3800" | ||
| 76 | help | ||
| 77 | Say Y here if you intend to run this kernel on the Compaq iPAQ H3800 | ||
| 78 | series handheld computer. Information about this machine and the | ||
| 79 | Linux port to this machine can be found at: | ||
| 80 | |||
| 81 | <http://www.handhelds.org/Compaq/index.html#iPAQ_H3800> | ||
| 82 | <http://www.compaq.com/products/handhelds/pocketpc/> | ||
| 83 | |||
| 84 | config SA1100_H3XXX | 74 | config SA1100_H3XXX |
| 85 | bool | 75 | bool |
| 86 | depends on SA1100_H3100 || SA1100_H3600 || SA1100_H3800 | 76 | depends on SA1100_H3100 || SA1100_H3600 |
| 87 | default y | 77 | default y |
| 88 | 78 | ||
| 89 | config SA1100_BADGE4 | 79 | config SA1100_BADGE4 |
| @@ -157,15 +147,6 @@ config SA1100_SSP | |||
| 157 | This isn't for audio support, but for attached sensors and | 147 | This isn't for audio support, but for attached sensors and |
| 158 | other devices, eg for BadgePAD 4 sensor support. | 148 | other devices, eg for BadgePAD 4 sensor support. |
| 159 | 149 | ||
| 160 | config H3600_SLEEVE | ||
| 161 | tristate "Compaq iPAQ Handheld sleeve support" | ||
| 162 | depends on SA1100_H3100 || SA1100_H3600 | ||
| 163 | help | ||
| 164 | Choose this option to enable support for extension packs (sleeves) | ||
| 165 | for the Compaq iPAQ H3XXX series of handheld computers. This option | ||
| 166 | is required for the CF, PCMCIA, Bluetooth and GSM/GPRS extension | ||
| 167 | packs. | ||
| 168 | |||
| 169 | endmenu | 150 | endmenu |
| 170 | 151 | ||
| 171 | endif | 152 | endif |
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 2052eb88c961..bbf2ebcc3066 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/mtd/mtd.h> | 25 | #include <linux/mtd/mtd.h> |
| 26 | #include <linux/mtd/partitions.h> | 26 | #include <linux/mtd/partitions.h> |
| 27 | #include <linux/timer.h> | 27 | #include <linux/timer.h> |
| 28 | #include <linux/gpio.h> | ||
| 28 | 29 | ||
| 29 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 30 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| @@ -145,7 +146,8 @@ static struct locomo_driver collie_uart_driver = { | |||
| 145 | .remove = collie_uart_remove, | 146 | .remove = collie_uart_remove, |
| 146 | }; | 147 | }; |
| 147 | 148 | ||
| 148 | static int __init collie_uart_init(void) { | 149 | static int __init collie_uart_init(void) |
| 150 | { | ||
| 149 | return locomo_driver_register(&collie_uart_driver); | 151 | return locomo_driver_register(&collie_uart_driver); |
| 150 | } | 152 | } |
| 151 | device_initcall(collie_uart_init); | 153 | device_initcall(collie_uart_init); |
| @@ -195,18 +197,34 @@ static struct mtd_partition collie_partitions[] = { | |||
| 195 | } | 197 | } |
| 196 | }; | 198 | }; |
| 197 | 199 | ||
| 200 | static int collie_flash_init(void) | ||
| 201 | { | ||
| 202 | int rc = gpio_request(COLLIE_GPIO_VPEN, "flash Vpp enable"); | ||
| 203 | if (rc) | ||
| 204 | return rc; | ||
| 205 | |||
| 206 | rc = gpio_direction_output(COLLIE_GPIO_VPEN, 1); | ||
| 207 | if (rc) | ||
| 208 | gpio_free(COLLIE_GPIO_VPEN); | ||
| 209 | |||
| 210 | return rc; | ||
| 211 | } | ||
| 212 | |||
| 198 | static void collie_set_vpp(int vpp) | 213 | static void collie_set_vpp(int vpp) |
| 199 | { | 214 | { |
| 200 | write_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR) | COLLIE_SCP_VPEN); | 215 | gpio_set_value(COLLIE_GPIO_VPEN, vpp); |
| 201 | if (vpp) | 216 | } |
| 202 | write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) | COLLIE_SCP_VPEN); | 217 | |
| 203 | else | 218 | static void collie_flash_exit(void) |
| 204 | write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) & ~COLLIE_SCP_VPEN); | 219 | { |
| 220 | gpio_free(COLLIE_GPIO_VPEN); | ||
| 205 | } | 221 | } |
| 206 | 222 | ||
| 207 | static struct flash_platform_data collie_flash_data = { | 223 | static struct flash_platform_data collie_flash_data = { |
| 208 | .map_name = "cfi_probe", | 224 | .map_name = "cfi_probe", |
| 225 | .init = collie_flash_init, | ||
| 209 | .set_vpp = collie_set_vpp, | 226 | .set_vpp = collie_set_vpp, |
| 227 | .exit = collie_flash_exit, | ||
| 210 | .parts = collie_partitions, | 228 | .parts = collie_partitions, |
| 211 | .nr_parts = ARRAY_SIZE(collie_partitions), | 229 | .nr_parts = ARRAY_SIZE(collie_partitions), |
| 212 | }; | 230 | }; |
diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c index b39307f26b52..444f266ecc06 100644 --- a/arch/arm/mach-sa1100/collie_pm.c +++ b/arch/arm/mach-sa1100/collie_pm.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/device.h> | 23 | #include <linux/device.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/gpio.h> | ||
| 25 | 26 | ||
| 26 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| @@ -58,6 +59,9 @@ static void collie_charger_init(void) | |||
| 58 | return; | 59 | return; |
| 59 | } | 60 | } |
| 60 | 61 | ||
| 62 | gpio_request(COLLIE_GPIO_CHARGE_ON, "charge on"); | ||
| 63 | gpio_direction_output(COLLIE_GPIO_CHARGE_ON, 1); | ||
| 64 | |||
| 61 | ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON | | 65 | ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON | |
| 62 | COLLIE_TC35143_GPIO_BBAT_ON); | 66 | COLLIE_TC35143_GPIO_BBAT_ON); |
| 63 | return; | 67 | return; |
| @@ -73,17 +77,11 @@ static void collie_measure_temp(int on) | |||
| 73 | 77 | ||
| 74 | static void collie_charge(int on) | 78 | static void collie_charge(int on) |
| 75 | { | 79 | { |
| 76 | extern struct platform_device colliescoop_device; | ||
| 77 | |||
| 78 | /* Zaurus seems to contain LTC1731; it should know when to | 80 | /* Zaurus seems to contain LTC1731; it should know when to |
| 79 | * stop charging itself, so setting charge on should be | 81 | * stop charging itself, so setting charge on should be |
| 80 | * relatively harmless (as long as it is not done too often). | 82 | * relatively harmless (as long as it is not done too often). |
| 81 | */ | 83 | */ |
| 82 | if (on) { | 84 | gpio_set_value(COLLIE_GPIO_CHARGE_ON, on); |
| 83 | set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); | ||
| 84 | } else { | ||
| 85 | reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); | ||
| 86 | } | ||
| 87 | } | 85 | } |
| 88 | 86 | ||
| 89 | static void collie_discharge(int on) | 87 | static void collie_discharge(int on) |
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index af25a78d705d..0eb2f159578b 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c | |||
| @@ -42,19 +42,12 @@ | |||
| 42 | #include <asm/mach/serial_sa1100.h> | 42 | #include <asm/mach/serial_sa1100.h> |
| 43 | 43 | ||
| 44 | #include <mach/h3600.h> | 44 | #include <mach/h3600.h> |
| 45 | |||
| 46 | #if defined (CONFIG_SA1100_H3600) || defined (CONFIG_SA1100_H3100) | ||
| 47 | #include <mach/h3600_gpio.h> | 45 | #include <mach/h3600_gpio.h> |
| 48 | #endif | ||
| 49 | |||
| 50 | #ifdef CONFIG_SA1100_H3800 | ||
| 51 | #include <mach/h3600_asic.h> | ||
| 52 | #endif | ||
| 53 | 46 | ||
| 54 | #include "generic.h" | 47 | #include "generic.h" |
| 55 | 48 | ||
| 56 | struct ipaq_model_ops ipaq_model_ops; | 49 | void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level); |
| 57 | EXPORT_SYMBOL(ipaq_model_ops); | 50 | EXPORT_SYMBOL(assign_h3600_egpio); |
| 58 | 51 | ||
| 59 | static struct mtd_partition h3xxx_partitions[] = { | 52 | static struct mtd_partition h3xxx_partitions[] = { |
| 60 | { | 53 | { |
| @@ -63,41 +56,9 @@ static struct mtd_partition h3xxx_partitions[] = { | |||
| 63 | .offset = 0, | 56 | .offset = 0, |
| 64 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | 57 | .mask_flags = MTD_WRITEABLE, /* force read-only */ |
| 65 | }, { | 58 | }, { |
| 66 | #ifdef CONFIG_MTD_2PARTS_IPAQ | 59 | .name = "H3XXX rootfs", |
| 67 | .name = "H3XXX root jffs2", | ||
| 68 | .size = MTDPART_SIZ_FULL, | 60 | .size = MTDPART_SIZ_FULL, |
| 69 | .offset = 0x00040000, | 61 | .offset = 0x00040000, |
| 70 | #else | ||
| 71 | .name = "H3XXX kernel", | ||
| 72 | .size = 0x00080000, | ||
| 73 | .offset = 0x00040000, | ||
| 74 | }, { | ||
| 75 | .name = "H3XXX params", | ||
| 76 | .size = 0x00040000, | ||
| 77 | .offset = 0x000C0000, | ||
| 78 | }, { | ||
| 79 | #ifdef CONFIG_JFFS2_FS | ||
| 80 | .name = "H3XXX root jffs2", | ||
| 81 | .size = MTDPART_SIZ_FULL, | ||
| 82 | .offset = 0x00100000, | ||
| 83 | #else | ||
| 84 | .name = "H3XXX initrd", | ||
| 85 | .size = 0x00100000, | ||
| 86 | .offset = 0x00100000, | ||
| 87 | }, { | ||
| 88 | .name = "H3XXX root cramfs", | ||
| 89 | .size = 0x00300000, | ||
| 90 | .offset = 0x00200000, | ||
| 91 | }, { | ||
| 92 | .name = "H3XXX usr cramfs", | ||
| 93 | .size = 0x00800000, | ||
| 94 | .offset = 0x00500000, | ||
| 95 | }, { | ||
| 96 | .name = "H3XXX usr local", | ||
| 97 | .size = MTDPART_SIZ_FULL, | ||
| 98 | .offset = 0x00d00000, | ||
| 99 | #endif | ||
| 100 | #endif | ||
| 101 | } | 62 | } |
| 102 | }; | 63 | }; |
| 103 | 64 | ||
| @@ -131,11 +92,7 @@ static int h3600_irda_set_power(struct device *dev, unsigned int state) | |||
| 131 | 92 | ||
| 132 | static void h3600_irda_set_speed(struct device *dev, unsigned int speed) | 93 | static void h3600_irda_set_speed(struct device *dev, unsigned int speed) |
| 133 | { | 94 | { |
| 134 | if (speed < 4000000) { | 95 | assign_h3600_egpio(IPAQ_EGPIO_IR_FSEL, !(speed < 4000000)); |
| 135 | clr_h3600_egpio(IPAQ_EGPIO_IR_FSEL); | ||
| 136 | } else { | ||
| 137 | set_h3600_egpio(IPAQ_EGPIO_IR_FSEL); | ||
| 138 | } | ||
| 139 | } | 96 | } |
| 140 | 97 | ||
| 141 | static struct irda_platform_data h3600_irda_data = { | 98 | static struct irda_platform_data h3600_irda_data = { |
| @@ -266,12 +223,6 @@ static void __init h3xxx_map_io(void) | |||
| 266 | sa1100fb_lcd_power = h3xxx_lcd_power; | 223 | sa1100fb_lcd_power = h3xxx_lcd_power; |
| 267 | } | 224 | } |
| 268 | 225 | ||
| 269 | static __inline__ void do_blank(int setp) | ||
| 270 | { | ||
| 271 | if (ipaq_model_ops.blank_callback) | ||
| 272 | ipaq_model_ops.blank_callback(1-setp); | ||
| 273 | } | ||
| 274 | |||
| 275 | /************************* H3100 *************************/ | 226 | /************************* H3100 *************************/ |
| 276 | 227 | ||
| 277 | #ifdef CONFIG_SA1100_H3100 | 228 | #ifdef CONFIG_SA1100_H3100 |
| @@ -289,7 +240,6 @@ static void h3100_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 289 | case IPAQ_EGPIO_LCD_POWER: | 240 | case IPAQ_EGPIO_LCD_POWER: |
| 290 | egpio |= EGPIO_H3600_LCD_ON; | 241 | egpio |= EGPIO_H3600_LCD_ON; |
| 291 | gpio |= GPIO_H3100_LCD_3V_ON; | 242 | gpio |= GPIO_H3100_LCD_3V_ON; |
| 292 | do_blank(setp); | ||
| 293 | break; | 243 | break; |
| 294 | case IPAQ_EGPIO_LCD_ENABLE: | 244 | case IPAQ_EGPIO_LCD_ENABLE: |
| 295 | break; | 245 | break; |
| @@ -343,25 +293,6 @@ static void h3100_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 343 | } | 293 | } |
| 344 | } | 294 | } |
| 345 | 295 | ||
| 346 | static unsigned long h3100_read_egpio(void) | ||
| 347 | { | ||
| 348 | return h3100_egpio; | ||
| 349 | } | ||
| 350 | |||
| 351 | static int h3100_pm_callback(int req) | ||
| 352 | { | ||
| 353 | if (ipaq_model_ops.pm_callback_aux) | ||
| 354 | return ipaq_model_ops.pm_callback_aux(req); | ||
| 355 | return 0; | ||
| 356 | } | ||
| 357 | |||
| 358 | static struct ipaq_model_ops h3100_model_ops __initdata = { | ||
| 359 | .generic_name = "3100", | ||
| 360 | .control = h3100_control_egpio, | ||
| 361 | .read = h3100_read_egpio, | ||
| 362 | .pm_callback = h3100_pm_callback | ||
| 363 | }; | ||
| 364 | |||
| 365 | #define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON \ | 296 | #define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON \ |
| 366 | | GPIO_H3100_GPIO3 \ | 297 | | GPIO_H3100_GPIO3 \ |
| 367 | | GPIO_H3100_QMUTE \ | 298 | | GPIO_H3100_QMUTE \ |
| @@ -387,7 +318,7 @@ static void __init h3100_map_io(void) | |||
| 387 | GAFR &= ~H3100_DIRECT_EGPIO; | 318 | GAFR &= ~H3100_DIRECT_EGPIO; |
| 388 | 319 | ||
| 389 | H3100_EGPIO = h3100_egpio; | 320 | H3100_EGPIO = h3100_egpio; |
| 390 | ipaq_model_ops = h3100_model_ops; | 321 | assign_h3600_egpio = h3100_control_egpio; |
| 391 | } | 322 | } |
| 392 | 323 | ||
| 393 | MACHINE_START(H3100, "Compaq iPAQ H3100") | 324 | MACHINE_START(H3100, "Compaq iPAQ H3100") |
| @@ -420,7 +351,6 @@ static void h3600_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 420 | EGPIO_H3600_LCD_PCI | | 351 | EGPIO_H3600_LCD_PCI | |
| 421 | EGPIO_H3600_LCD_5V_ON | | 352 | EGPIO_H3600_LCD_5V_ON | |
| 422 | EGPIO_H3600_LVDD_ON; | 353 | EGPIO_H3600_LVDD_ON; |
| 423 | do_blank(setp); | ||
| 424 | break; | 354 | break; |
| 425 | case IPAQ_EGPIO_LCD_ENABLE: | 355 | case IPAQ_EGPIO_LCD_ENABLE: |
| 426 | break; | 356 | break; |
| @@ -471,25 +401,6 @@ static void h3600_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 471 | } | 401 | } |
| 472 | } | 402 | } |
| 473 | 403 | ||
| 474 | static unsigned long h3600_read_egpio(void) | ||
| 475 | { | ||
| 476 | return h3600_egpio; | ||
| 477 | } | ||
| 478 | |||
| 479 | static int h3600_pm_callback(int req) | ||
| 480 | { | ||
| 481 | if (ipaq_model_ops.pm_callback_aux) | ||
| 482 | return ipaq_model_ops.pm_callback_aux(req); | ||
| 483 | return 0; | ||
| 484 | } | ||
| 485 | |||
| 486 | static struct ipaq_model_ops h3600_model_ops __initdata = { | ||
| 487 | .generic_name = "3600", | ||
| 488 | .control = h3600_control_egpio, | ||
| 489 | .read = h3600_read_egpio, | ||
| 490 | .pm_callback = h3600_pm_callback | ||
| 491 | }; | ||
| 492 | |||
| 493 | static void __init h3600_map_io(void) | 404 | static void __init h3600_map_io(void) |
| 494 | { | 405 | { |
| 495 | h3xxx_map_io(); | 406 | h3xxx_map_io(); |
| @@ -504,7 +415,7 @@ static void __init h3600_map_io(void) | |||
| 504 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; | 415 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; |
| 505 | 416 | ||
| 506 | H3600_EGPIO = h3600_egpio; /* Maintains across sleep? */ | 417 | H3600_EGPIO = h3600_egpio; /* Maintains across sleep? */ |
| 507 | ipaq_model_ops = h3600_model_ops; | 418 | assign_h3600_egpio = h3600_control_egpio; |
| 508 | } | 419 | } |
| 509 | 420 | ||
| 510 | MACHINE_START(H3600, "Compaq iPAQ H3600") | 421 | MACHINE_START(H3600, "Compaq iPAQ H3600") |
| @@ -519,388 +430,3 @@ MACHINE_END | |||
| 519 | 430 | ||
| 520 | #endif /* CONFIG_SA1100_H3600 */ | 431 | #endif /* CONFIG_SA1100_H3600 */ |
| 521 | 432 | ||
| 522 | #ifdef CONFIG_SA1100_H3800 | ||
| 523 | |||
| 524 | #define SET_ASIC1(x) \ | ||
| 525 | do {if (setp) { H3800_ASIC1_GPIO_OUT |= (x); } else { H3800_ASIC1_GPIO_OUT &= ~(x); }} while(0) | ||
| 526 | |||
| 527 | #define SET_ASIC2(x) \ | ||
| 528 | do {if (setp) { H3800_ASIC2_GPIOPIOD |= (x); } else { H3800_ASIC2_GPIOPIOD &= ~(x); }} while(0) | ||
| 529 | |||
| 530 | #define CLEAR_ASIC1(x) \ | ||
| 531 | do {if (setp) { H3800_ASIC1_GPIO_OUT &= ~(x); } else { H3800_ASIC1_GPIO_OUT |= (x); }} while(0) | ||
| 532 | |||
| 533 | #define CLEAR_ASIC2(x) \ | ||
| 534 | do {if (setp) { H3800_ASIC2_GPIOPIOD &= ~(x); } else { H3800_ASIC2_GPIOPIOD |= (x); }} while(0) | ||
| 535 | |||
| 536 | |||
| 537 | /* | ||
| 538 | On screen enable, we get | ||
| 539 | |||
| 540 | h3800_video_power_on(1) | ||
| 541 | LCD controller starts | ||
| 542 | h3800_video_lcd_enable(1) | ||
| 543 | |||
| 544 | On screen disable, we get | ||
| 545 | |||
| 546 | h3800_video_lcd_enable(0) | ||
| 547 | LCD controller stops | ||
| 548 | h3800_video_power_on(0) | ||
| 549 | */ | ||
| 550 | |||
| 551 | |||
| 552 | static void h3800_video_power_on(int setp) | ||
| 553 | { | ||
| 554 | if (setp) { | ||
| 555 | H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_ON; | ||
| 556 | msleep(30); | ||
| 557 | H3800_ASIC1_GPIO_OUT |= GPIO1_VGL_ON; | ||
| 558 | msleep(5); | ||
| 559 | H3800_ASIC1_GPIO_OUT |= GPIO1_VGH_ON; | ||
| 560 | msleep(50); | ||
| 561 | H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_5V_ON; | ||
| 562 | msleep(5); | ||
| 563 | } else { | ||
| 564 | msleep(5); | ||
| 565 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_5V_ON; | ||
| 566 | msleep(50); | ||
| 567 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGL_ON; | ||
| 568 | msleep(5); | ||
| 569 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGH_ON; | ||
| 570 | msleep(100); | ||
| 571 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_ON; | ||
| 572 | } | ||
| 573 | } | ||
| 574 | |||
| 575 | static void h3800_video_lcd_enable(int setp) | ||
| 576 | { | ||
| 577 | if (setp) { | ||
| 578 | msleep(17); // Wait one from before turning on | ||
| 579 | H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_PCI; | ||
| 580 | } else { | ||
| 581 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_PCI; | ||
| 582 | msleep(30); // Wait before turning off | ||
| 583 | } | ||
| 584 | } | ||
| 585 | |||
| 586 | |||
| 587 | static void h3800_control_egpio(enum ipaq_egpio_type x, int setp) | ||
| 588 | { | ||
| 589 | switch (x) { | ||
| 590 | case IPAQ_EGPIO_LCD_POWER: | ||
| 591 | h3800_video_power_on(setp); | ||
| 592 | break; | ||
| 593 | case IPAQ_EGPIO_LCD_ENABLE: | ||
| 594 | h3800_video_lcd_enable(setp); | ||
| 595 | break; | ||
| 596 | case IPAQ_EGPIO_CODEC_NRESET: | ||
| 597 | case IPAQ_EGPIO_AUDIO_ON: | ||
| 598 | case IPAQ_EGPIO_QMUTE: | ||
| 599 | printk("%s: error - should not be called\n", __func__); | ||
| 600 | break; | ||
| 601 | case IPAQ_EGPIO_OPT_NVRAM_ON: | ||
| 602 | SET_ASIC2(GPIO2_OPT_ON_NVRAM); | ||
| 603 | break; | ||
| 604 | case IPAQ_EGPIO_OPT_ON: | ||
| 605 | SET_ASIC2(GPIO2_OPT_ON); | ||
| 606 | break; | ||
| 607 | case IPAQ_EGPIO_CARD_RESET: | ||
| 608 | SET_ASIC2(GPIO2_OPT_PCM_RESET); | ||
| 609 | break; | ||
| 610 | case IPAQ_EGPIO_OPT_RESET: | ||
| 611 | SET_ASIC2(GPIO2_OPT_RESET); | ||
| 612 | break; | ||
| 613 | case IPAQ_EGPIO_IR_ON: | ||
| 614 | CLEAR_ASIC1(GPIO1_IR_ON_N); | ||
| 615 | break; | ||
| 616 | case IPAQ_EGPIO_IR_FSEL: | ||
| 617 | break; | ||
| 618 | case IPAQ_EGPIO_RS232_ON: | ||
| 619 | SET_ASIC1(GPIO1_RS232_ON); | ||
| 620 | break; | ||
| 621 | case IPAQ_EGPIO_VPP_ON: | ||
| 622 | H3800_ASIC2_FlashWP_VPP_ON = setp; | ||
| 623 | break; | ||
| 624 | } | ||
| 625 | } | ||
| 626 | |||
| 627 | static unsigned long h3800_read_egpio(void) | ||
| 628 | { | ||
| 629 | return H3800_ASIC1_GPIO_OUT | (H3800_ASIC2_GPIOPIOD << 16); | ||
| 630 | } | ||
| 631 | |||
| 632 | /* We need to fix ASIC2 GPIO over suspend/resume. At the moment, | ||
| 633 | it doesn't appear that ASIC1 GPIO has the same problem */ | ||
| 634 | |||
| 635 | static int h3800_pm_callback(int req) | ||
| 636 | { | ||
| 637 | static u16 asic1_data; | ||
| 638 | static u16 asic2_data; | ||
| 639 | int result = 0; | ||
| 640 | |||
| 641 | printk("%s %d\n", __func__, req); | ||
| 642 | |||
| 643 | switch (req) { | ||
| 644 | case PM_RESUME: | ||
| 645 | MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000; /* Set MSC2 correctly */ | ||
| 646 | |||
| 647 | H3800_ASIC2_GPIOPIOD = asic2_data; | ||
| 648 | H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ | ||
| 649 | | GPIO2_SD_DETECT | ||
| 650 | | GPIO2_EAR_IN_N | ||
| 651 | | GPIO2_USB_DETECT_N | ||
| 652 | | GPIO2_SD_CON_SLT; | ||
| 653 | |||
| 654 | H3800_ASIC1_GPIO_OUT = asic1_data; | ||
| 655 | |||
| 656 | if (ipaq_model_ops.pm_callback_aux) | ||
| 657 | result = ipaq_model_ops.pm_callback_aux(req); | ||
| 658 | break; | ||
| 659 | |||
| 660 | case PM_SUSPEND: | ||
| 661 | if (ipaq_model_ops.pm_callback_aux && | ||
| 662 | ((result = ipaq_model_ops.pm_callback_aux(req)) != 0)) | ||
| 663 | return result; | ||
| 664 | |||
| 665 | asic1_data = H3800_ASIC1_GPIO_OUT; | ||
| 666 | asic2_data = H3800_ASIC2_GPIOPIOD; | ||
| 667 | break; | ||
| 668 | default: | ||
| 669 | printk("%s: unrecognized PM callback\n", __func__); | ||
| 670 | break; | ||
| 671 | } | ||
| 672 | return result; | ||
| 673 | } | ||
| 674 | |||
| 675 | static struct ipaq_model_ops h3800_model_ops __initdata = { | ||
| 676 | .generic_name = "3800", | ||
| 677 | .control = h3800_control_egpio, | ||
| 678 | .read = h3800_read_egpio, | ||
| 679 | .pm_callback = h3800_pm_callback | ||
| 680 | }; | ||
| 681 | |||
| 682 | #define MAX_ASIC_ISR_LOOPS 20 | ||
| 683 | |||
| 684 | /* The order of these is important - see #include <mach/irqs.h> */ | ||
| 685 | static u32 kpio_irq_mask[] = { | ||
| 686 | KPIO_KEY_ALL, | ||
| 687 | KPIO_SPI_INT, | ||
| 688 | KPIO_OWM_INT, | ||
| 689 | KPIO_ADC_INT, | ||
| 690 | KPIO_UART_0_INT, | ||
| 691 | KPIO_UART_1_INT, | ||
| 692 | KPIO_TIMER_0_INT, | ||
| 693 | KPIO_TIMER_1_INT, | ||
| 694 | KPIO_TIMER_2_INT | ||
| 695 | }; | ||
| 696 | |||
| 697 | static u32 gpio_irq_mask[] = { | ||
| 698 | GPIO2_PEN_IRQ, | ||
| 699 | GPIO2_SD_DETECT, | ||
| 700 | GPIO2_EAR_IN_N, | ||
| 701 | GPIO2_USB_DETECT_N, | ||
| 702 | GPIO2_SD_CON_SLT, | ||
| 703 | }; | ||
| 704 | |||
| 705 | static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc) | ||
| 706 | { | ||
| 707 | int i; | ||
| 708 | |||
| 709 | if (0) printk("%s: interrupt received\n", __func__); | ||
| 710 | |||
| 711 | desc->chip->ack(irq); | ||
| 712 | |||
| 713 | for (i = 0; i < MAX_ASIC_ISR_LOOPS && (GPLR & GPIO_H3800_ASIC); i++) { | ||
| 714 | u32 irq; | ||
| 715 | int j; | ||
| 716 | |||
| 717 | /* KPIO */ | ||
| 718 | irq = H3800_ASIC2_KPIINTFLAG; | ||
| 719 | if (0) printk("%s KPIO 0x%08X\n", __func__, irq); | ||
| 720 | for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) | ||
| 721 | if (irq & kpio_irq_mask[j]) | ||
| 722 | handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); | ||
| 723 | |||
| 724 | /* GPIO2 */ | ||
| 725 | irq = H3800_ASIC2_GPIINTFLAG; | ||
| 726 | if (0) printk("%s GPIO 0x%08X\n", __func__, irq); | ||
| 727 | for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) | ||
| 728 | if (irq & gpio_irq_mask[j]) | ||
| 729 | handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); | ||
| 730 | } | ||
| 731 | |||
| 732 | if (i >= MAX_ASIC_ISR_LOOPS) | ||
| 733 | printk("%s: interrupt processing overrun\n", __func__); | ||
| 734 | |||
| 735 | /* For level-based interrupts */ | ||
| 736 | desc->chip->unmask(irq); | ||
| 737 | |||
| 738 | } | ||
| 739 | |||
| 740 | static struct irqaction h3800_irq = { | ||
| 741 | .name = "h3800_asic", | ||
| 742 | .handler = h3800_IRQ_demux, | ||
| 743 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 744 | }; | ||
| 745 | |||
| 746 | u32 kpio_int_shadow = 0; | ||
| 747 | |||
| 748 | |||
| 749 | /* mask_ack <- IRQ is first serviced. | ||
| 750 | mask <- IRQ is disabled. | ||
| 751 | unmask <- IRQ is enabled | ||
| 752 | |||
| 753 | The INTCLR registers are poorly documented. I believe that writing | ||
| 754 | a "1" to the register clears the specific interrupt, but the documentation | ||
| 755 | indicates writing a "0" clears the interrupt. In any case, they shouldn't | ||
| 756 | be read (that's the INTFLAG register) | ||
| 757 | */ | ||
| 758 | |||
| 759 | static void h3800_mask_ack_kpio_irq(unsigned int irq) | ||
| 760 | { | ||
| 761 | u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; | ||
| 762 | kpio_int_shadow &= ~mask; | ||
| 763 | H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; | ||
| 764 | H3800_ASIC2_KPIINTCLR = mask; | ||
| 765 | } | ||
| 766 | |||
| 767 | static void h3800_mask_kpio_irq(unsigned int irq) | ||
| 768 | { | ||
| 769 | u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; | ||
| 770 | kpio_int_shadow &= ~mask; | ||
| 771 | H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; | ||
| 772 | } | ||
| 773 | |||
| 774 | static void h3800_unmask_kpio_irq(unsigned int irq) | ||
| 775 | { | ||
| 776 | u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; | ||
| 777 | kpio_int_shadow |= mask; | ||
| 778 | H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; | ||
| 779 | } | ||
| 780 | |||
| 781 | static void h3800_mask_ack_gpio_irq(unsigned int irq) | ||
| 782 | { | ||
| 783 | u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; | ||
| 784 | H3800_ASIC2_GPIINTSTAT &= ~mask; | ||
| 785 | H3800_ASIC2_GPIINTCLR = mask; | ||
| 786 | } | ||
| 787 | |||
| 788 | static void h3800_mask_gpio_irq(unsigned int irq) | ||
| 789 | { | ||
| 790 | u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; | ||
| 791 | H3800_ASIC2_GPIINTSTAT &= ~mask; | ||
| 792 | } | ||
| 793 | |||
| 794 | static void h3800_unmask_gpio_irq(unsigned int irq) | ||
| 795 | { | ||
| 796 | u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; | ||
| 797 | H3800_ASIC2_GPIINTSTAT |= mask; | ||
| 798 | } | ||
| 799 | |||
| 800 | static void __init h3800_init_irq(void) | ||
| 801 | { | ||
| 802 | int i; | ||
| 803 | |||
| 804 | /* Initialize standard IRQs */ | ||
| 805 | sa1100_init_irq(); | ||
| 806 | |||
| 807 | /* Disable all IRQs and set up clock */ | ||
| 808 | H3800_ASIC2_KPIINTSTAT = 0; /* Disable all interrupts */ | ||
| 809 | H3800_ASIC2_GPIINTSTAT = 0; | ||
| 810 | |||
| 811 | H3800_ASIC2_KPIINTCLR = 0; /* Clear all KPIO interrupts */ | ||
| 812 | H3800_ASIC2_GPIINTCLR = 0; /* Clear all GPIO interrupts */ | ||
| 813 | |||
| 814 | // H3800_ASIC2_KPIINTCLR = 0xffff; /* Clear all KPIO interrupts */ | ||
| 815 | // H3800_ASIC2_GPIINTCLR = 0xffff; /* Clear all GPIO interrupts */ | ||
| 816 | |||
| 817 | H3800_ASIC2_CLOCK_Enable |= ASIC2_CLOCK_EX0; /* 32 kHZ crystal on */ | ||
| 818 | H3800_ASIC2_INTR_ClockPrescale |= ASIC2_INTCPS_SET; | ||
| 819 | H3800_ASIC2_INTR_ClockPrescale = ASIC2_INTCPS_CPS(0x0e) | ASIC2_INTCPS_SET; | ||
| 820 | H3800_ASIC2_INTR_TimerSet = 1; | ||
| 821 | |||
| 822 | #if 0 | ||
| 823 | for (i = 0; i < H3800_KPIO_IRQ_COUNT; i++) { | ||
| 824 | int irq = i + H3800_KPIO_IRQ_START; | ||
| 825 | irq_desc[irq].valid = 1; | ||
| 826 | irq_desc[irq].probe_ok = 1; | ||
| 827 | set_irq_chip(irq, &h3800_kpio_irqchip); | ||
| 828 | } | ||
| 829 | |||
| 830 | for (i = 0; i < H3800_GPIO_IRQ_COUNT; i++) { | ||
| 831 | int irq = i + H3800_GPIO_IRQ_START; | ||
| 832 | irq_desc[irq].valid = 1; | ||
| 833 | irq_desc[irq].probe_ok = 1; | ||
| 834 | set_irq_chip(irq, &h3800_gpio_irqchip); | ||
| 835 | } | ||
| 836 | #endif | ||
| 837 | set_irq_type(IRQ_GPIO_H3800_ASIC, IRQ_TYPE_EDGE_RISING); | ||
| 838 | set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux); | ||
| 839 | } | ||
| 840 | |||
| 841 | |||
| 842 | #define ASIC1_OUTPUTS 0x7fff /* First 15 bits are used */ | ||
| 843 | |||
| 844 | static void __init h3800_map_io(void) | ||
| 845 | { | ||
| 846 | h3xxx_map_io(); | ||
| 847 | |||
| 848 | /* Add wakeup on AC plug/unplug */ | ||
| 849 | PWER |= PWER_GPIO12; | ||
| 850 | |||
| 851 | /* Initialize h3800-specific values here */ | ||
| 852 | GPCR = 0x0fffffff; /* All outputs are set low by default */ | ||
| 853 | GAFR = GPIO_H3800_CLK_OUT | | ||
| 854 | GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | | ||
| 855 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; | ||
| 856 | GPDR = GPIO_H3800_CLK_OUT | | ||
| 857 | GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK | | ||
| 858 | GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA | | ||
| 859 | GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | | ||
| 860 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; | ||
| 861 | TUCR = TUCR_3_6864MHz; /* Seems to be used only for the Bluetooth UART */ | ||
| 862 | |||
| 863 | /* Fix the memory bus */ | ||
| 864 | MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000; | ||
| 865 | |||
| 866 | /* Set up ASIC #1 */ | ||
| 867 | H3800_ASIC1_GPIO_DIR = ASIC1_OUTPUTS; /* All outputs */ | ||
| 868 | H3800_ASIC1_GPIO_MASK = ASIC1_OUTPUTS; /* No interrupts */ | ||
| 869 | H3800_ASIC1_GPIO_SLEEP_MASK = ASIC1_OUTPUTS; | ||
| 870 | H3800_ASIC1_GPIO_SLEEP_DIR = ASIC1_OUTPUTS; | ||
| 871 | H3800_ASIC1_GPIO_SLEEP_OUT = GPIO1_EAR_ON_N; | ||
| 872 | H3800_ASIC1_GPIO_BATT_FAULT_DIR = ASIC1_OUTPUTS; | ||
| 873 | H3800_ASIC1_GPIO_BATT_FAULT_OUT = GPIO1_EAR_ON_N; | ||
| 874 | |||
| 875 | H3800_ASIC1_GPIO_OUT = GPIO1_IR_ON_N | ||
| 876 | | GPIO1_RS232_ON | ||
| 877 | | GPIO1_EAR_ON_N; | ||
| 878 | |||
| 879 | /* Set up ASIC #2 */ | ||
| 880 | H3800_ASIC2_GPIOPIOD = GPIO2_IN_Y1_N | GPIO2_IN_X1_N; | ||
| 881 | H3800_ASIC2_GPOBFSTAT = GPIO2_IN_Y1_N | GPIO2_IN_X1_N; | ||
| 882 | |||
| 883 | H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ | ||
| 884 | | GPIO2_SD_DETECT | ||
| 885 | | GPIO2_EAR_IN_N | ||
| 886 | | GPIO2_USB_DETECT_N | ||
| 887 | | GPIO2_SD_CON_SLT; | ||
| 888 | |||
| 889 | /* TODO : Set sleep states & battery fault states */ | ||
| 890 | |||
| 891 | /* Clear VPP Enable */ | ||
| 892 | H3800_ASIC2_FlashWP_VPP_ON = 0; | ||
| 893 | ipaq_model_ops = h3800_model_ops; | ||
| 894 | } | ||
| 895 | |||
| 896 | MACHINE_START(H3800, "Compaq iPAQ H3800") | ||
| 897 | .phys_io = 0x80000000, | ||
| 898 | .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, | ||
| 899 | .boot_params = 0xc0000100, | ||
| 900 | .map_io = h3800_map_io, | ||
| 901 | .init_irq = h3800_init_irq, | ||
| 902 | .timer = &sa1100_timer, | ||
| 903 | .init_machine = h3xxx_mach_init, | ||
| 904 | MACHINE_END | ||
| 905 | |||
| 906 | #endif /* CONFIG_SA1100_H3800 */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h index 69e962416e3f..9efb569cdb60 100644 --- a/arch/arm/mach-sa1100/include/mach/collie.h +++ b/arch/arm/mach-sa1100/include/mach/collie.h | |||
| @@ -14,21 +14,21 @@ | |||
| 14 | #define __ASM_ARCH_COLLIE_H | 14 | #define __ASM_ARCH_COLLIE_H |
| 15 | 15 | ||
| 16 | 16 | ||
| 17 | #define COLLIE_SCP_CHARGE_ON SCOOP_GPCR_PA11 | 17 | #define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) |
| 18 | #define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0) | ||
| 18 | #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 | 19 | #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 |
| 19 | #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 | 20 | #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 |
| 20 | #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 | 21 | #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 |
| 21 | #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 | 22 | #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 |
| 22 | #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 | 23 | #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 |
| 23 | #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 | 24 | #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 |
| 24 | #define COLLIE_SCP_VPEN SCOOP_GPCR_PA18 | 25 | #define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7) |
| 25 | #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 | 26 | #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 |
| 26 | 27 | ||
| 27 | #define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ | 28 | #define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ |
| 28 | COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \ | 29 | COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \ |
| 29 | COLLIE_SCP_LB_VOL_CHG ) | 30 | COLLIE_SCP_LB_VOL_CHG ) |
| 30 | #define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \ | 31 | #define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R ) |
| 31 | COLLIE_SCP_CHARGE_ON ) | ||
| 32 | 32 | ||
| 33 | /* GPIOs for which the generic definition doesn't say much */ | 33 | /* GPIOs for which the generic definition doesn't say much */ |
| 34 | 34 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h index 9cc47fddb335..2827faa47421 100644 --- a/arch/arm/mach-sa1100/include/mach/h3600.h +++ b/arch/arm/mach-sa1100/include/mach/h3600.h | |||
| @@ -29,7 +29,7 @@ typedef int __bitwise pm_request_t; | |||
| 29 | #define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ | 29 | #define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ |
| 30 | 30 | ||
| 31 | /* generalized support for H3xxx series Compaq Pocket PC's */ | 31 | /* generalized support for H3xxx series Compaq Pocket PC's */ |
| 32 | #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) | 32 | #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600()) |
| 33 | 33 | ||
| 34 | /* Physical memory regions corresponding to chip selects */ | 34 | /* Physical memory regions corresponding to chip selects */ |
| 35 | #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) | 35 | #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) |
| @@ -93,76 +93,7 @@ enum ipaq_egpio_type { | |||
| 93 | IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ | 93 | IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ |
| 94 | }; | 94 | }; |
| 95 | 95 | ||
| 96 | struct ipaq_model_ops { | 96 | extern void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level); |
| 97 | const char *generic_name; | ||
| 98 | void (*control)(enum ipaq_egpio_type, int); | ||
| 99 | unsigned long (*read)(void); | ||
| 100 | void (*blank_callback)(int blank); | ||
| 101 | int (*pm_callback)(int req); /* Primary model callback */ | ||
| 102 | int (*pm_callback_aux)(int req); /* Secondary callback (used by HAL modules) */ | ||
| 103 | }; | ||
| 104 | |||
| 105 | extern struct ipaq_model_ops ipaq_model_ops; | ||
| 106 | |||
| 107 | static __inline__ const char * h3600_generic_name(void) | ||
| 108 | { | ||
| 109 | return ipaq_model_ops.generic_name; | ||
| 110 | } | ||
| 111 | |||
| 112 | static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level) | ||
| 113 | { | ||
| 114 | if (ipaq_model_ops.control) | ||
| 115 | ipaq_model_ops.control(x,level); | ||
| 116 | } | ||
| 117 | |||
| 118 | static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x) | ||
| 119 | { | ||
| 120 | if (ipaq_model_ops.control) | ||
| 121 | ipaq_model_ops.control(x,0); | ||
| 122 | } | ||
| 123 | |||
| 124 | static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x) | ||
| 125 | { | ||
| 126 | if (ipaq_model_ops.control) | ||
| 127 | ipaq_model_ops.control(x,1); | ||
| 128 | } | ||
| 129 | |||
| 130 | static __inline__ unsigned long read_h3600_egpio(void) | ||
| 131 | { | ||
| 132 | if (ipaq_model_ops.read) | ||
| 133 | return ipaq_model_ops.read(); | ||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | static __inline__ int h3600_register_blank_callback(void (*f)(int)) | ||
| 138 | { | ||
| 139 | ipaq_model_ops.blank_callback = f; | ||
| 140 | return 0; | ||
| 141 | } | ||
| 142 | |||
| 143 | static __inline__ void h3600_unregister_blank_callback(void (*f)(int)) | ||
| 144 | { | ||
| 145 | ipaq_model_ops.blank_callback = NULL; | ||
| 146 | } | ||
| 147 | |||
| 148 | |||
| 149 | static __inline__ int h3600_register_pm_callback(int (*f)(int)) | ||
| 150 | { | ||
| 151 | ipaq_model_ops.pm_callback_aux = f; | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | static __inline__ void h3600_unregister_pm_callback(int (*f)(int)) | ||
| 156 | { | ||
| 157 | ipaq_model_ops.pm_callback_aux = NULL; | ||
| 158 | } | ||
| 159 | |||
| 160 | static __inline__ int h3600_power_management(int req) | ||
| 161 | { | ||
| 162 | if (ipaq_model_ops.pm_callback) | ||
| 163 | return ipaq_model_ops.pm_callback(req); | ||
| 164 | return 0; | ||
| 165 | } | ||
| 166 | 97 | ||
| 167 | #endif /* ASSEMBLY */ | 98 | #endif /* ASSEMBLY */ |
| 168 | 99 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h index 62b0b7879685..a36ca76d018b 100644 --- a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h +++ b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h | |||
| @@ -48,22 +48,11 @@ | |||
| 48 | #define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) | 48 | #define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) |
| 49 | #define GPIO_H3600_OPT_DET GPIO_GPIO (27) | 49 | #define GPIO_H3600_OPT_DET GPIO_GPIO (27) |
| 50 | 50 | ||
| 51 | /* H3800 specific pins */ | ||
| 52 | #define GPIO_H3800_AC_IN GPIO_GPIO (12) | ||
| 53 | #define GPIO_H3800_COM_DSR GPIO_GPIO (13) | ||
| 54 | #define GPIO_H3800_MMC_INT GPIO_GPIO (18) | ||
| 55 | #define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */ | ||
| 56 | #define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22) | ||
| 57 | #define GPIO_H3800_CLK_OUT GPIO_GPIO (27) | ||
| 58 | |||
| 59 | /****************************************************/ | 51 | /****************************************************/ |
| 60 | 52 | ||
| 61 | #define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 | 53 | #define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 |
| 62 | #define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 | 54 | #define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 |
| 63 | 55 | ||
| 64 | #define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18 | ||
| 65 | #define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */ | ||
| 66 | |||
| 67 | /* H3100 / 3600 EGPIO pins */ | 56 | /* H3100 / 3600 EGPIO pins */ |
| 68 | #define EGPIO_H3600_VPP_ON (1 << 0) | 57 | #define EGPIO_H3600_VPP_ON (1 << 0) |
| 69 | #define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ | 58 | #define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ |
| @@ -84,457 +73,5 @@ | |||
| 84 | #define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ | 73 | #define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ |
| 85 | #define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ | 74 | #define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ |
| 86 | 75 | ||
| 87 | /********************* H3800, ASIC #2 ********************/ | ||
| 88 | |||
| 89 | #define _H3800_ASIC2_Base (H3600_EGPIO_VIRT) | ||
| 90 | #define H3800_ASIC2_OFFSET(s,x,y) \ | ||
| 91 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 92 | #define H3800_ASIC2_NOFFSET(s,x,n,y) \ | ||
| 93 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 94 | |||
| 95 | #define _H3800_ASIC2_GPIO_Base 0x0000 | ||
| 96 | #define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */ | ||
| 97 | #define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 98 | #define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 99 | #define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 100 | #define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */ | ||
| 101 | #define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */ | ||
| 102 | #define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 103 | #define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 104 | #define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */ | ||
| 105 | #define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */ | ||
| 106 | |||
| 107 | #define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction ) | ||
| 108 | #define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType ) | ||
| 109 | #define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType ) | ||
| 110 | #define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType ) | ||
| 111 | #define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear ) | ||
| 112 | #define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag ) | ||
| 113 | #define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data ) | ||
| 114 | #define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 115 | #define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable ) | ||
| 116 | #define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate ) | ||
| 117 | |||
| 118 | #define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */ | ||
| 119 | #define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */ | ||
| 120 | #define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */ | ||
| 121 | #define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */ | ||
| 122 | #define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */ | ||
| 123 | #define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */ | ||
| 124 | #define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */ | ||
| 125 | #define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */ | ||
| 126 | #define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */ | ||
| 127 | #define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */ | ||
| 128 | #define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */ | ||
| 129 | #define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */ | ||
| 130 | |||
| 131 | #define _H3800_ASIC2_KPIO_Base 0x0200 | ||
| 132 | #define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */ | ||
| 133 | #define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 134 | #define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 135 | #define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 136 | #define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */ | ||
| 137 | #define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */ | ||
| 138 | #define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 139 | #define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 140 | #define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */ | ||
| 141 | #define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */ | ||
| 142 | |||
| 143 | #define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction ) | ||
| 144 | #define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType ) | ||
| 145 | #define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType ) | ||
| 146 | #define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType ) | ||
| 147 | #define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear ) | ||
| 148 | #define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag ) | ||
| 149 | #define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data ) | ||
| 150 | #define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut ) | ||
| 151 | #define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable ) | ||
| 152 | #define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate ) | ||
| 153 | |||
| 154 | #define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 ) | ||
| 155 | #define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 ) | ||
| 156 | #define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 ) | ||
| 157 | #define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 ) | ||
| 158 | #define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 ) | ||
| 159 | #define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 ) | ||
| 160 | #define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 ) | ||
| 161 | #define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 ) | ||
| 162 | |||
| 163 | #define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */ | ||
| 164 | #define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */ | ||
| 165 | #define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */ | ||
| 166 | #define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */ | ||
| 167 | #define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */ | ||
| 168 | #define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */ | ||
| 169 | #define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */ | ||
| 170 | #define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */ | ||
| 171 | #define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */ | ||
| 172 | #define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */ | ||
| 173 | #define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */ | ||
| 174 | #define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */ | ||
| 175 | |||
| 176 | /* Alternate KPIO functions (set by default) */ | ||
| 177 | #define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */ | ||
| 178 | #define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */ | ||
| 179 | #define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */ | ||
| 180 | #define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */ | ||
| 181 | #define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */ | ||
| 182 | |||
| 183 | #define _H3800_ASIC2_SPI_Base 0x0400 | ||
| 184 | #define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */ | ||
| 185 | #define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */ | ||
| 186 | #define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */ | ||
| 187 | |||
| 188 | #define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control ) | ||
| 189 | #define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data ) | ||
| 190 | #define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled ) | ||
| 191 | |||
| 192 | #define _H3800_ASIC2_PWM_0_Base 0x0600 | ||
| 193 | #define _H3800_ASIC2_PWM_1_Base 0x0700 | ||
| 194 | #define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */ | ||
| 195 | #define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 196 | #define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 197 | |||
| 198 | #define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase ) | ||
| 199 | #define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime ) | ||
| 200 | #define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime ) | ||
| 201 | |||
| 202 | #define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase ) | ||
| 203 | #define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime ) | ||
| 204 | #define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime ) | ||
| 205 | |||
| 206 | #define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */ | ||
| 207 | #define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */ | ||
| 208 | #define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */ | ||
| 209 | |||
| 210 | #define _H3800_ASIC2_LED_0_Base 0x0800 | ||
| 211 | #define _H3800_ASIC2_LED_1_Base 0x0880 | ||
| 212 | #define _H3800_ASIC2_LED_2_Base 0x0900 | ||
| 213 | #define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */ | ||
| 214 | #define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 215 | #define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 216 | #define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */ | ||
| 217 | |||
| 218 | #define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase ) | ||
| 219 | #define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime ) | ||
| 220 | #define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime ) | ||
| 221 | #define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock ) | ||
| 222 | |||
| 223 | #define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase ) | ||
| 224 | #define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime ) | ||
| 225 | #define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime ) | ||
| 226 | #define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock ) | ||
| 227 | |||
| 228 | #define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase ) | ||
| 229 | #define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime ) | ||
| 230 | #define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime ) | ||
| 231 | #define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock ) | ||
| 232 | |||
| 233 | #define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */ | ||
| 234 | #define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */ | ||
| 235 | #define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 ) | ||
| 236 | #define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */ | ||
| 237 | |||
| 238 | #define _H3800_ASIC2_UART_0_Base 0x0A00 | ||
| 239 | #define _H3800_ASIC2_UART_1_Base 0x0C00 | ||
| 240 | #define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */ | ||
| 241 | #define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */ | ||
| 242 | #define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */ | ||
| 243 | #define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */ | ||
| 244 | #define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */ | ||
| 245 | #define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */ | ||
| 246 | #define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */ | ||
| 247 | #define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */ | ||
| 248 | #define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */ | ||
| 249 | #define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */ | ||
| 250 | #define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */ | ||
| 251 | |||
| 252 | #define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive ) | ||
| 253 | #define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit ) | ||
| 254 | #define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable ) | ||
| 255 | #define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify ) | ||
| 256 | #define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl ) | ||
| 257 | #define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl ) | ||
| 258 | #define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus ) | ||
| 259 | #define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus ) | ||
| 260 | #define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad ) | ||
| 261 | #define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL ) | ||
| 262 | #define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH ) | ||
| 263 | |||
| 264 | #define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive ) | ||
| 265 | #define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit ) | ||
| 266 | #define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable ) | ||
| 267 | #define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify ) | ||
| 268 | #define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl ) | ||
| 269 | #define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl ) | ||
| 270 | #define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus ) | ||
| 271 | #define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus ) | ||
| 272 | #define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad ) | ||
| 273 | #define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL ) | ||
| 274 | #define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH ) | ||
| 275 | |||
| 276 | #define _H3800_ASIC2_TIMER_Base 0x0E00 | ||
| 277 | #define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */ | ||
| 278 | |||
| 279 | #define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command ) | ||
| 280 | |||
| 281 | #define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */ | ||
| 282 | #define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */ | ||
| 283 | #define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */ | ||
| 284 | #define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */ | ||
| 285 | #define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */ | ||
| 286 | #define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */ | ||
| 287 | #define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */ | ||
| 288 | #define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */ | ||
| 289 | |||
| 290 | #define _H3800_ASIC2_CLOCK_Base 0x1000 | ||
| 291 | #define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */ | ||
| 292 | |||
| 293 | #define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable ) | ||
| 294 | |||
| 295 | #define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */ | ||
| 296 | #define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */ | ||
| 297 | #define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */ | ||
| 298 | #define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */ | ||
| 299 | #define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */ | ||
| 300 | #define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */ | ||
| 301 | #define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */ | ||
| 302 | #define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */ | ||
| 303 | #define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */ | ||
| 304 | #define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */ | ||
| 305 | #define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */ | ||
| 306 | #define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */ | ||
| 307 | #define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */ | ||
| 308 | #define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */ | ||
| 309 | #define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */ | ||
| 310 | #define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */ | ||
| 311 | #define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */ | ||
| 312 | #define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */ | ||
| 313 | #define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */ | ||
| 314 | |||
| 315 | #define _H3800_ASIC2_ADC_Base 0x1200 | ||
| 316 | #define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */ | ||
| 317 | #define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */ | ||
| 318 | #define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */ | ||
| 319 | |||
| 320 | #define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer ) | ||
| 321 | #define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus ) | ||
| 322 | #define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data ) | ||
| 323 | |||
| 324 | #define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */ | ||
| 325 | #define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */ | ||
| 326 | |||
| 327 | #define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */ | ||
| 328 | #define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 ) | ||
| 329 | #define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 ) | ||
| 330 | #define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */ | ||
| 331 | #define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */ | ||
| 332 | |||
| 333 | |||
| 334 | #define _H3800_ASIC2_INTR_Base 0x1600 | ||
| 335 | #define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */ | ||
| 336 | #define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */ | ||
| 337 | #define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */ | ||
| 338 | |||
| 339 | #define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag ) | ||
| 340 | #define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale ) | ||
| 341 | #define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet ) | ||
| 342 | |||
| 343 | #define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */ | ||
| 344 | #define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */ | ||
| 345 | #define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */ | ||
| 346 | #define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 ) | ||
| 347 | #define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 ) | ||
| 348 | #define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 ) | ||
| 349 | #define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 ) | ||
| 350 | |||
| 351 | #define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */ | ||
| 352 | #define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */ | ||
| 353 | |||
| 354 | |||
| 355 | #define _H3800_ASIC2_OWM_Base 0x1800 | ||
| 356 | #define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */ | ||
| 357 | #define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */ | ||
| 358 | #define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */ | ||
| 359 | #define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */ | ||
| 360 | #define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */ | ||
| 361 | |||
| 362 | #define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command ) | ||
| 363 | #define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data ) | ||
| 364 | #define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt ) | ||
| 365 | #define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable ) | ||
| 366 | #define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor ) | ||
| 367 | |||
| 368 | #define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */ | ||
| 369 | #define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */ | ||
| 370 | #define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */ | ||
| 371 | #define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */ | ||
| 372 | |||
| 373 | #define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */ | ||
| 374 | #define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */ | ||
| 375 | #define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */ | ||
| 376 | #define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */ | ||
| 377 | #define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */ | ||
| 378 | |||
| 379 | #define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */ | ||
| 380 | #define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */ | ||
| 381 | #define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */ | ||
| 382 | #define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */ | ||
| 383 | #define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */ | ||
| 384 | |||
| 385 | #define _H3800_ASIC2_FlashCtl_Base 0x1A00 | ||
| 386 | |||
| 387 | /****************************************************/ | ||
| 388 | /* H3800, ASIC #1 | ||
| 389 | * This ASIC is accesed through ASIC #2, and | ||
| 390 | * mapped into the 1c00 - 1f00 region | ||
| 391 | */ | ||
| 392 | |||
| 393 | #define H3800_ASIC1_OFFSET(s,x,y) \ | ||
| 394 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1)))) | ||
| 395 | |||
| 396 | #define _H3800_ASIC1_MMC_Base 0x1c00 | ||
| 397 | |||
| 398 | #define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */ | ||
| 399 | #define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */ | ||
| 400 | #define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */ | ||
| 401 | #define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */ | ||
| 402 | #define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */ | ||
| 403 | #define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */ | ||
| 404 | #define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */ | ||
| 405 | #define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */ | ||
| 406 | #define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */ | ||
| 407 | #define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */ | ||
| 408 | #define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */ | ||
| 409 | #define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */ | ||
| 410 | #define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */ | ||
| 411 | #define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */ | ||
| 412 | #define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */ | ||
| 413 | |||
| 414 | #define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock ) | ||
| 415 | #define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status ) | ||
| 416 | #define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate ) | ||
| 417 | #define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister ) | ||
| 418 | #define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont ) | ||
| 419 | #define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout ) | ||
| 420 | #define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout ) | ||
| 421 | #define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength ) | ||
| 422 | #define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks ) | ||
| 423 | #define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask ) | ||
| 424 | #define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber ) | ||
| 425 | #define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH ) | ||
| 426 | #define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL ) | ||
| 427 | #define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo ) | ||
| 428 | #define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull ) | ||
| 429 | |||
| 430 | #define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */ | ||
| 431 | #define H3800_ASIC1_MMC_START_CLOCK (1 << 1) | ||
| 432 | |||
| 433 | #define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0) | ||
| 434 | #define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1) | ||
| 435 | #define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2) | ||
| 436 | #define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3) | ||
| 437 | #define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */ | ||
| 438 | #define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5) | ||
| 439 | #define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6) | ||
| 440 | #define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7) | ||
| 441 | #define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */ | ||
| 442 | #define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */ | ||
| 443 | #define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */ | ||
| 444 | #define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */ | ||
| 445 | |||
| 446 | #define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */ | ||
| 447 | #define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */ | ||
| 448 | #define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */ | ||
| 449 | #define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */ | ||
| 450 | |||
| 451 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00 | ||
| 452 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01 | ||
| 453 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02 | ||
| 454 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03 | ||
| 455 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */ | ||
| 456 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */ | ||
| 457 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */ | ||
| 458 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */ | ||
| 459 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */ | ||
| 460 | |||
| 461 | #define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0) | ||
| 462 | #define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1) | ||
| 463 | #define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2) | ||
| 464 | #define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3) | ||
| 465 | |||
| 466 | #define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0) | ||
| 467 | |||
| 468 | /********* GPIO **********/ | ||
| 469 | |||
| 470 | #define _H3800_ASIC1_GPIO_Base 0x1e00 | ||
| 471 | |||
| 472 | #define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */ | ||
| 473 | #define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */ | ||
| 474 | #define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */ | ||
| 475 | #define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */ | ||
| 476 | #define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */ | ||
| 477 | #define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */ | ||
| 478 | #define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */ | ||
| 479 | #define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */ | ||
| 480 | #define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ | ||
| 481 | #define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ | ||
| 482 | #define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ | ||
| 483 | #define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */ | ||
| 484 | #define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ | ||
| 485 | #define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ | ||
| 486 | #define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ | ||
| 487 | #define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */ | ||
| 488 | |||
| 489 | #define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask ) | ||
| 490 | #define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction ) | ||
| 491 | #define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out ) | ||
| 492 | #define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType ) | ||
| 493 | #define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger ) | ||
| 494 | #define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger ) | ||
| 495 | #define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus ) | ||
| 496 | #define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus ) | ||
| 497 | #define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State ) | ||
| 498 | #define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset ) | ||
| 499 | #define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask ) | ||
| 500 | #define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir ) | ||
| 501 | #define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut ) | ||
| 502 | #define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status ) | ||
| 503 | #define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir ) | ||
| 504 | #define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 505 | |||
| 506 | #define H3800_ASIC1_GPIO_STATE_MASK (1 << 0) | ||
| 507 | #define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1) | ||
| 508 | #define H3800_ASIC1_GPIO_STATE_OUT (1 << 2) | ||
| 509 | #define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3) | ||
| 510 | #define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4) | ||
| 511 | #define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5) | ||
| 512 | |||
| 513 | #define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0) | ||
| 514 | #define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1) | ||
| 515 | #define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2) | ||
| 516 | |||
| 517 | /* These are all outputs */ | ||
| 518 | #define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */ | ||
| 519 | #define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */ | ||
| 520 | #define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */ | ||
| 521 | #define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */ | ||
| 522 | #define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */ | ||
| 523 | #define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */ | ||
| 524 | #define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */ | ||
| 525 | #define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */ | ||
| 526 | #define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */ | ||
| 527 | #define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */ | ||
| 528 | #define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */ | ||
| 529 | #define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */ | ||
| 530 | #define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */ | ||
| 531 | #define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */ | ||
| 532 | #define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */ | ||
| 533 | |||
| 534 | /* Write enable for the flash */ | ||
| 535 | |||
| 536 | #define _H3800_ASIC1_FlashWP_Base 0x1F00 | ||
| 537 | #define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */ | ||
| 538 | #define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON ) | ||
| 539 | 76 | ||
| 540 | #endif /* _INCLUDE_H3600_GPIO_H_ */ | 77 | #endif /* _INCLUDE_H3600_GPIO_H_ */ |
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h index 0cb36609b3ac..ae81f80b0cf9 100644 --- a/arch/arm/mach-sa1100/include/mach/irqs.h +++ b/arch/arm/mach-sa1100/include/mach/irqs.h | |||
| @@ -153,8 +153,6 @@ | |||
| 153 | */ | 153 | */ |
| 154 | #ifdef CONFIG_SA1111 | 154 | #ifdef CONFIG_SA1111 |
| 155 | #define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) | 155 | #define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) |
| 156 | #elif defined(CONFIG_SA1100_H3800) | ||
| 157 | #define NR_IRQS (IRQ_BOARD_END) | ||
| 158 | #elif defined(CONFIG_SHARP_LOCOMO) | 156 | #elif defined(CONFIG_SHARP_LOCOMO) |
| 159 | #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) | 157 | #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) |
| 160 | #else | 158 | #else |
| @@ -175,23 +173,3 @@ | |||
| 175 | #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) | 173 | #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) |
| 176 | #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) | 174 | #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) |
| 177 | 175 | ||
| 178 | /* H3800-specific IRQs (CONFIG_SA1100_H3800) */ | ||
| 179 | #define H3800_KPIO_IRQ_START (IRQ_BOARD_START) | ||
| 180 | #define IRQ_H3800_KEY (IRQ_BOARD_START + 0) | ||
| 181 | #define IRQ_H3800_SPI (IRQ_BOARD_START + 1) | ||
| 182 | #define IRQ_H3800_OWM (IRQ_BOARD_START + 2) | ||
| 183 | #define IRQ_H3800_ADC (IRQ_BOARD_START + 3) | ||
| 184 | #define IRQ_H3800_UART_0 (IRQ_BOARD_START + 4) | ||
| 185 | #define IRQ_H3800_UART_1 (IRQ_BOARD_START + 5) | ||
| 186 | #define IRQ_H3800_TIMER_0 (IRQ_BOARD_START + 6) | ||
| 187 | #define IRQ_H3800_TIMER_1 (IRQ_BOARD_START + 7) | ||
| 188 | #define IRQ_H3800_TIMER_2 (IRQ_BOARD_START + 8) | ||
| 189 | #define H3800_KPIO_IRQ_COUNT 9 | ||
| 190 | |||
| 191 | #define H3800_GPIO_IRQ_START (IRQ_BOARD_START + 9) | ||
| 192 | #define IRQ_H3800_PEN (IRQ_BOARD_START + 9) | ||
| 193 | #define IRQ_H3800_SD_DETECT (IRQ_BOARD_START + 10) | ||
| 194 | #define IRQ_H3800_EAR_IN (IRQ_BOARD_START + 11) | ||
| 195 | #define IRQ_H3800_USB_DETECT (IRQ_BOARD_START + 12) | ||
| 196 | #define IRQ_H3800_SD_CON_SLT (IRQ_BOARD_START + 13) | ||
| 197 | #define H3800_GPIO_IRQ_COUNT 5 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h index 63755ca5b1b4..942b153e251d 100644 --- a/arch/arm/mach-sa1100/include/mach/system.h +++ b/arch/arm/mach-sa1100/include/mach/system.h | |||
| @@ -10,7 +10,7 @@ static inline void arch_idle(void) | |||
| 10 | cpu_do_idle(); | 10 | cpu_do_idle(); |
| 11 | } | 11 | } |
| 12 | 12 | ||
| 13 | static inline void arch_reset(char mode) | 13 | static inline void arch_reset(char mode, const char *cmd) |
| 14 | { | 14 | { |
| 15 | if (mode == 's') { | 15 | if (mode == 's') { |
| 16 | /* Jump into ROM at address 0 */ | 16 | /* Jump into ROM at address 0 */ |
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index 81848aa96424..fd776bb666cd 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c | |||
| @@ -226,12 +226,22 @@ static struct platform_device jornada_ssp_device = { | |||
| 226 | .id = -1, | 226 | .id = -1, |
| 227 | }; | 227 | }; |
| 228 | 228 | ||
| 229 | static struct platform_device jornada_kbd_device = { | ||
| 230 | .name = "jornada720_kbd", | ||
| 231 | .id = -1, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct platform_device jornada_ts_device = { | ||
| 235 | .name = "jornada_ts", | ||
| 236 | .id = -1, | ||
| 237 | }; | ||
| 238 | |||
| 229 | static struct platform_device *devices[] __initdata = { | 239 | static struct platform_device *devices[] __initdata = { |
| 230 | &sa1111_device, | 240 | &sa1111_device, |
| 231 | #ifdef CONFIG_SA1100_JORNADA720_SSP | ||
| 232 | &jornada_ssp_device, | 241 | &jornada_ssp_device, |
| 233 | #endif | ||
| 234 | &s1d13xxxfb_device, | 242 | &s1d13xxxfb_device, |
| 243 | &jornada_kbd_device, | ||
| 244 | &jornada_ts_device, | ||
| 235 | }; | 245 | }; |
| 236 | 246 | ||
| 237 | static int __init jornada720_init(void) | 247 | static int __init jornada720_init(void) |
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index a23fd3d0163a..358d875ace14 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c | |||
| @@ -16,12 +16,28 @@ | |||
| 16 | #include <asm/leds.h> | 16 | #include <asm/leds.h> |
| 17 | #include <asm/param.h> | 17 | #include <asm/param.h> |
| 18 | 18 | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | |||
| 21 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 22 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 24 | 22 | ||
| 23 | #define IO_BASE 0xe0000000 | ||
| 24 | #define IO_SIZE 0x08000000 | ||
| 25 | #define IO_START 0x40000000 | ||
| 26 | #define ROMCARD_SIZE 0x08000000 | ||
| 27 | #define ROMCARD_START 0x10000000 | ||
| 28 | |||
| 29 | void arch_reset(char mode, const char *cmd) | ||
| 30 | { | ||
| 31 | short temp; | ||
| 32 | local_irq_disable(); | ||
| 33 | /* Reset the Machine via pc[3] of the sequoia chipset */ | ||
| 34 | outw(0x09,0x24); | ||
| 35 | temp=inw(0x26); | ||
| 36 | temp = temp | (1<<3) | (1<<10); | ||
| 37 | outw(0x09,0x24); | ||
| 38 | outw(temp,0x26); | ||
| 39 | } | ||
| 40 | |||
| 25 | static struct plat_serial8250_port serial_platform_data[] = { | 41 | static struct plat_serial8250_port serial_platform_data[] = { |
| 26 | { | 42 | { |
| 27 | .iobase = 0x3f8, | 43 | .iobase = 0x3f8, |
| @@ -50,14 +66,38 @@ static struct platform_device serial_device = { | |||
| 50 | }, | 66 | }, |
| 51 | }; | 67 | }; |
| 52 | 68 | ||
| 69 | static struct resource rtc_resources[] = { | ||
| 70 | [0] = { | ||
| 71 | .start = 0x70, | ||
| 72 | .end = 0x73, | ||
| 73 | .flags = IORESOURCE_IO, | ||
| 74 | }, | ||
| 75 | [1] = { | ||
| 76 | .start = IRQ_ISA_RTC_ALARM, | ||
| 77 | .end = IRQ_ISA_RTC_ALARM, | ||
| 78 | .flags = IORESOURCE_IRQ, | ||
| 79 | } | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct platform_device rtc_device = { | ||
| 83 | .name = "rtc_cmos", | ||
| 84 | .id = -1, | ||
| 85 | .resource = rtc_resources, | ||
| 86 | .num_resources = ARRAY_SIZE(rtc_resources), | ||
| 87 | }; | ||
| 88 | |||
| 53 | static int __init shark_init(void) | 89 | static int __init shark_init(void) |
| 54 | { | 90 | { |
| 55 | int ret; | 91 | int ret; |
| 56 | 92 | ||
| 57 | if (machine_is_shark()) | 93 | if (machine_is_shark()) |
| 94 | { | ||
| 95 | ret = platform_device_register(&rtc_device); | ||
| 96 | if (ret) printk(KERN_ERR "Unable to register RTC device: %d\n", ret); | ||
| 58 | ret = platform_device_register(&serial_device); | 97 | ret = platform_device_register(&serial_device); |
| 59 | 98 | if (ret) printk(KERN_ERR "Unable to register Serial device: %d\n", ret); | |
| 60 | return ret; | 99 | } |
| 100 | return 0; | ||
| 61 | } | 101 | } |
| 62 | 102 | ||
| 63 | arch_initcall(shark_init); | 103 | arch_initcall(shark_init); |
diff --git a/arch/arm/mach-shark/dma.c b/arch/arm/mach-shark/dma.c index 6774b8d5d13d..10b5b8b3272a 100644 --- a/arch/arm/mach-shark/dma.c +++ b/arch/arm/mach-shark/dma.c | |||
| @@ -13,9 +13,11 @@ | |||
| 13 | #include <asm/dma.h> | 13 | #include <asm/dma.h> |
| 14 | #include <asm/mach/dma.h> | 14 | #include <asm/mach/dma.h> |
| 15 | 15 | ||
| 16 | void __init arch_dma_init(dma_t *dma) | 16 | static int __init shark_dma_init(void) |
| 17 | { | 17 | { |
| 18 | #ifdef CONFIG_ISA_DMA | 18 | #ifdef CONFIG_ISA_DMA |
| 19 | isa_init_dma(dma); | 19 | isa_init_dma(); |
| 20 | #endif | 20 | #endif |
| 21 | return 0; | ||
| 21 | } | 22 | } |
| 23 | core_initcall(shark_dma_init); | ||
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S index 0836cb78b29a..f97a7626bd58 100644 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/arch/arm/mach-shark/include/mach/debug-macro.S | |||
| @@ -27,5 +27,3 @@ | |||
| 27 | bne 1001b | 27 | bne 1001b |
| 28 | .endm | 28 | .endm |
| 29 | 29 | ||
| 30 | .macro waituart,rd,rx | ||
| 31 | .endm | ||
diff --git a/arch/arm/mach-shark/include/mach/framebuffer.h b/arch/arm/mach-shark/include/mach/framebuffer.h new file mode 100644 index 000000000000..84a5bf6e5ba3 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/framebuffer.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-shark/include/mach/framebuffer.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | * | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ASM_ARCH_FRAMEBUFFER_H | ||
| 9 | #define __ASM_ARCH_FRAMEBUFFER_H | ||
| 10 | |||
| 11 | /* defines for the Framebuffer */ | ||
| 12 | #define FB_START 0x06000000 | ||
| 13 | #define FB_SIZE 0x01000000 | ||
| 14 | |||
| 15 | #endif | ||
| 16 | |||
diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h index 01bf76099ce5..94d84b27a0cb 100644 --- a/arch/arm/mach-shark/include/mach/hardware.h +++ b/arch/arm/mach-shark/include/mach/hardware.h | |||
| @@ -10,35 +10,8 @@ | |||
| 10 | #ifndef __ASM_ARCH_HARDWARE_H | 10 | #ifndef __ASM_ARCH_HARDWARE_H |
| 11 | #define __ASM_ARCH_HARDWARE_H | 11 | #define __ASM_ARCH_HARDWARE_H |
| 12 | 12 | ||
| 13 | #ifndef __ASSEMBLY__ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Mapping areas | ||
| 17 | */ | ||
| 18 | #define IO_BASE 0xe0000000 | ||
| 19 | |||
| 20 | #else | ||
| 21 | |||
| 22 | #define IO_BASE 0 | ||
| 23 | |||
| 24 | #endif | ||
| 25 | |||
| 26 | #define IO_SIZE 0x08000000 | ||
| 27 | #define IO_START 0x40000000 | ||
| 28 | #define ROMCARD_SIZE 0x08000000 | ||
| 29 | #define ROMCARD_START 0x10000000 | ||
| 30 | |||
| 31 | |||
| 32 | /* defines for the Framebuffer */ | ||
| 33 | #define FB_START 0x06000000 | ||
| 34 | #define FB_SIZE 0x01000000 | ||
| 35 | |||
| 36 | #define UNCACHEABLE_ADDR 0xdf010000 | 13 | #define UNCACHEABLE_ADDR 0xdf010000 |
| 37 | 14 | ||
| 38 | #define SEQUOIA_LED_GREEN (1<<6) | ||
| 39 | #define SEQUOIA_LED_AMBER (1<<5) | ||
| 40 | #define SEQUOIA_LED_BACK (1<<7) | ||
| 41 | |||
| 42 | #define pcibios_assign_all_busses() 1 | 15 | #define pcibios_assign_all_busses() 1 |
| 43 | 16 | ||
| 44 | #define PCIBIOS_MIN_IO 0x6000 | 17 | #define PCIBIOS_MIN_IO 0x6000 |
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h index c5cee829fc87..9ccbcecc430b 100644 --- a/arch/arm/mach-shark/include/mach/io.h +++ b/arch/arm/mach-shark/include/mach/io.h | |||
| @@ -11,10 +11,10 @@ | |||
| 11 | #ifndef __ASM_ARM_ARCH_IO_H | 11 | #ifndef __ASM_ARM_ARCH_IO_H |
| 12 | #define __ASM_ARM_ARCH_IO_H | 12 | #define __ASM_ARM_ARCH_IO_H |
| 13 | 13 | ||
| 14 | #define PCIO_BASE 0xe0000000 | 14 | #define IO_SPACE_LIMIT 0xffffffff |
| 15 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 16 | 15 | ||
| 17 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | 16 | #define __io(a) ((void __iomem *)(0xe0000000 + (a))) |
| 18 | #define __mem_pci(addr) (addr) | 17 | |
| 18 | #define __mem_pci(addr) (addr) | ||
| 19 | 19 | ||
| 20 | #endif | 20 | #endif |
diff --git a/arch/arm/mach-shark/include/mach/irqs.h b/arch/arm/mach-shark/include/mach/irqs.h index 0586acd7cdd5..c8e8a4e1f61a 100644 --- a/arch/arm/mach-shark/include/mach/irqs.h +++ b/arch/arm/mach-shark/include/mach/irqs.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | #define NR_IRQS 16 | 7 | #define NR_IRQS 16 |
| 8 | 8 | ||
| 9 | #define IRQ_ISA_KEYBOARD 1 | 9 | #define IRQ_ISA_KEYBOARD 1 |
| 10 | #define RTC_IRQ 8 | 10 | #define IRQ_ISA_RTC_ALARM 8 |
| 11 | #define I8042_KBD_IRQ 1 | 11 | #define I8042_KBD_IRQ 1 |
| 12 | #define I8042_AUX_IRQ 12 | 12 | #define I8042_AUX_IRQ 12 |
| 13 | #define IRQ_HARDDISK 14 | 13 | #define IRQ_HARDDISK 14 |
diff --git a/arch/arm/mach-shark/include/mach/isa-dma.h b/arch/arm/mach-shark/include/mach/isa-dma.h index 864298ff3927..96c43b8f8dda 100644 --- a/arch/arm/mach-shark/include/mach/isa-dma.h +++ b/arch/arm/mach-shark/include/mach/isa-dma.h | |||
| @@ -6,10 +6,6 @@ | |||
| 6 | #ifndef __ASM_ARCH_DMA_H | 6 | #ifndef __ASM_ARCH_DMA_H |
| 7 | #define __ASM_ARCH_DMA_H | 7 | #define __ASM_ARCH_DMA_H |
| 8 | 8 | ||
| 9 | /* Use only the lowest 4MB, nothing else works. | ||
| 10 | * The rest is not DMAable. See dev / .properties | ||
| 11 | * in OpenFirmware. | ||
| 12 | */ | ||
| 13 | #define MAX_DMA_CHANNELS 8 | 9 | #define MAX_DMA_CHANNELS 8 |
| 14 | #define DMA_ISA_CASCADE 4 | 10 | #define DMA_ISA_CASCADE 4 |
| 15 | 11 | ||
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index c5ab038925d6..3053e5b7f168 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h | |||
| @@ -23,6 +23,7 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig | |||
| 23 | { | 23 | { |
| 24 | if (node != 0) return; | 24 | if (node != 0) return; |
| 25 | /* Only the first 4 MB (=1024 Pages) are usable for DMA */ | 25 | /* Only the first 4 MB (=1024 Pages) are usable for DMA */ |
| 26 | /* See dev / -> .properties in OpenFirmware. */ | ||
| 26 | zone_size[1] = zone_size[0] - 1024; | 27 | zone_size[1] = zone_size[0] - 1024; |
| 27 | zone_size[0] = 1024; | 28 | zone_size[0] = 1024; |
| 28 | zhole_size[1] = zhole_size[0]; | 29 | zhole_size[1] = zhole_size[0]; |
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h index e45bd734a03e..21c373b30bbc 100644 --- a/arch/arm/mach-shark/include/mach/system.h +++ b/arch/arm/mach-shark/include/mach/system.h | |||
| @@ -6,20 +6,8 @@ | |||
| 6 | #ifndef __ASM_ARCH_SYSTEM_H | 6 | #ifndef __ASM_ARCH_SYSTEM_H |
| 7 | #define __ASM_ARCH_SYSTEM_H | 7 | #define __ASM_ARCH_SYSTEM_H |
| 8 | 8 | ||
| 9 | #include <linux/io.h> | 9 | /* Found in arch/mach-shark/core.c */ |
| 10 | 10 | extern void arch_reset(char mode, const char *cmd); | |
| 11 | static void arch_reset(char mode) | ||
| 12 | { | ||
| 13 | short temp; | ||
| 14 | local_irq_disable(); | ||
| 15 | /* Reset the Machine via pc[3] of the sequoia chipset */ | ||
| 16 | outw(0x09,0x24); | ||
| 17 | temp=inw(0x26); | ||
| 18 | temp = temp | (1<<3) | (1<<10); | ||
| 19 | outw(0x09,0x24); | ||
| 20 | outw(temp,0x26); | ||
| 21 | |||
| 22 | } | ||
| 23 | 11 | ||
| 24 | static inline void arch_idle(void) | 12 | static inline void arch_idle(void) |
| 25 | { | 13 | { |
diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h index 3725e1633418..22ccab4c3c5e 100644 --- a/arch/arm/mach-shark/include/mach/uncompress.h +++ b/arch/arm/mach-shark/include/mach/uncompress.h | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | 11 | ||
| 12 | static inline void putc(int c) | 12 | static inline void putc(int c) |
| 13 | { | 13 | { |
| 14 | int t; | 14 | volatile int t; |
| 15 | 15 | ||
| 16 | SERIAL_BASE[0] = c; | 16 | SERIAL_BASE[0] = c; |
| 17 | t=0x10000; | 17 | t=0x10000; |
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c index 8bd8d6bb4d92..c9e32de4adf9 100644 --- a/arch/arm/mach-shark/leds.c +++ b/arch/arm/mach-shark/leds.c | |||
| @@ -22,12 +22,16 @@ | |||
| 22 | #include <linux/ioport.h> | 22 | #include <linux/ioport.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <asm/leds.h> | 25 | #include <asm/leds.h> |
| 27 | #include <asm/system.h> | 26 | #include <asm/system.h> |
| 28 | 27 | ||
| 29 | #define LED_STATE_ENABLED 1 | 28 | #define LED_STATE_ENABLED 1 |
| 30 | #define LED_STATE_CLAIMED 2 | 29 | #define LED_STATE_CLAIMED 2 |
| 30 | |||
| 31 | #define SEQUOIA_LED_GREEN (1<<6) | ||
| 32 | #define SEQUOIA_LED_AMBER (1<<5) | ||
| 33 | #define SEQUOIA_LED_BACK (1<<7) | ||
| 34 | |||
| 31 | static char led_state; | 35 | static char led_state; |
| 32 | static short hw_led_state; | 36 | static short hw_led_state; |
| 33 | static short saved_state; | 37 | static short saved_state; |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 1c43494f5c42..565776680d8c 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
| @@ -335,11 +335,25 @@ static struct resource versatile_i2c_resource = { | |||
| 335 | 335 | ||
| 336 | static struct platform_device versatile_i2c_device = { | 336 | static struct platform_device versatile_i2c_device = { |
| 337 | .name = "versatile-i2c", | 337 | .name = "versatile-i2c", |
| 338 | .id = -1, | 338 | .id = 0, |
| 339 | .num_resources = 1, | 339 | .num_resources = 1, |
| 340 | .resource = &versatile_i2c_resource, | 340 | .resource = &versatile_i2c_resource, |
| 341 | }; | 341 | }; |
| 342 | 342 | ||
| 343 | static struct i2c_board_info versatile_i2c_board_info[] = { | ||
| 344 | { | ||
| 345 | I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1), | ||
| 346 | .type = "ds1338", | ||
| 347 | }, | ||
| 348 | }; | ||
| 349 | |||
| 350 | static int __init versatile_i2c_init(void) | ||
| 351 | { | ||
| 352 | return i2c_register_board_info(0, versatile_i2c_board_info, | ||
| 353 | ARRAY_SIZE(versatile_i2c_board_info)); | ||
| 354 | } | ||
| 355 | arch_initcall(versatile_i2c_init); | ||
| 356 | |||
| 343 | #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) | 357 | #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) |
| 344 | 358 | ||
| 345 | unsigned int mmc_status(struct device *dev) | 359 | unsigned int mmc_status(struct device *dev) |
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h index c59e6100c7e3..8ffc12a7cb25 100644 --- a/arch/arm/mach-versatile/include/mach/system.h +++ b/arch/arm/mach-versatile/include/mach/system.h | |||
| @@ -34,7 +34,7 @@ static inline void arch_idle(void) | |||
| 34 | cpu_do_idle(); | 34 | cpu_do_idle(); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | static inline void arch_reset(char mode) | 37 | static inline void arch_reset(char mode, const char *cmd) |
| 38 | { | 38 | { |
| 39 | u32 val; | 39 | u32 val; |
| 40 | 40 | ||
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h index 40ff40845df0..de29ddcb9459 100644 --- a/arch/arm/mach-w90x900/cpu.h +++ b/arch/arm/mach-w90x900/cpu.h | |||
| @@ -43,35 +43,16 @@ extern void w90p910_init_io(struct map_desc *mach_desc, int size); | |||
| 43 | extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no); | 43 | extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no); |
| 44 | extern void w90p910_init_clocks(int xtal); | 44 | extern void w90p910_init_clocks(int xtal); |
| 45 | extern void w90p910_map_io(struct map_desc *mach_desc, int size); | 45 | extern void w90p910_map_io(struct map_desc *mach_desc, int size); |
| 46 | extern struct platform_device w90p910_serial_device; | ||
| 46 | extern struct sys_timer w90x900_timer; | 47 | extern struct sys_timer w90x900_timer; |
| 47 | 48 | ||
| 48 | #define W90X900_RES(name) \ | 49 | #define W90X900_8250PORT(name) \ |
| 49 | struct resource w90x900_##name##_resource[] = { \ | 50 | { \ |
| 50 | [0] = { \ | 51 | .membase = name##_BA, \ |
| 51 | .start = name##_PA, \ | 52 | .mapbase = name##_PA, \ |
| 52 | .end = name##_PA + 0x0ff, \ | 53 | .irq = IRQ_##name, \ |
| 53 | .flags = IORESOURCE_MEM, \ | 54 | .uartclk = 11313600, \ |
| 54 | }, \ | 55 | .regshift = 2, \ |
| 55 | [1] = { \ | 56 | .iotype = UPIO_MEM, \ |
| 56 | .start = IRQ_##name, \ | 57 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ |
| 57 | .end = IRQ_##name, \ | ||
| 58 | .flags = IORESOURCE_IRQ, \ | ||
| 59 | } \ | ||
| 60 | } | ||
| 61 | |||
| 62 | #define W90X900_DEVICE(devname, regname, devid, platdevname) \ | ||
| 63 | struct platform_device w90x900_##devname = { \ | ||
| 64 | .name = platdevname, \ | ||
| 65 | .id = devid, \ | ||
| 66 | .num_resources = ARRAY_SIZE(w90x900_##regname##_resource), \ | ||
| 67 | .resource = w90x900_##regname##_resource, \ | ||
| 68 | } | ||
| 69 | |||
| 70 | #define W90X900_UARTCFG(port, flag, uc, ulc, ufc) \ | ||
| 71 | { \ | ||
| 72 | .hwport = port, \ | ||
| 73 | .flags = flag, \ | ||
| 74 | .ucon = uc, \ | ||
| 75 | .ulcon = ulc, \ | ||
| 76 | .ufcon = ufc, \ | ||
| 77 | } | 58 | } |
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h index 93753f922618..940640066857 100644 --- a/arch/arm/mach-w90x900/include/mach/system.h +++ b/arch/arm/mach-w90x900/include/mach/system.h | |||
| @@ -21,7 +21,7 @@ static void arch_idle(void) | |||
| 21 | { | 21 | { |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static void arch_reset(char mode) | 24 | static void arch_reset(char mode, const char *cmd) |
| 25 | { | 25 | { |
| 26 | cpu_reset(0); | 26 | cpu_reset(0); |
| 27 | } | 27 | } |
diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c index 9ebc93f48530..726ff6798a56 100644 --- a/arch/arm/mach-w90x900/mach-w90p910evb.c +++ b/arch/arm/mach-w90x900/mach-w90p910evb.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/timer.h> | 22 | #include <linux/timer.h> |
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/mtd/physmap.h> | ||
| 25 | 26 | ||
| 26 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| @@ -32,28 +33,67 @@ | |||
| 32 | #include <mach/map.h> | 33 | #include <mach/map.h> |
| 33 | 34 | ||
| 34 | #include "cpu.h" | 35 | #include "cpu.h" |
| 36 | /*w90p910 evb norflash driver data */ | ||
| 35 | 37 | ||
| 36 | static struct map_desc w90p910_iodesc[] __initdata = { | 38 | #define W90P910_FLASH_BASE 0xA0000000 |
| 39 | #define W90P910_FLASH_SIZE 0x400000 | ||
| 40 | |||
| 41 | static struct mtd_partition w90p910_flash_partitions[] = { | ||
| 42 | { | ||
| 43 | .name = "NOR Partition 1 for kernel (960K)", | ||
| 44 | .size = 0xF0000, | ||
| 45 | .offset = 0x10000, | ||
| 46 | }, | ||
| 47 | { | ||
| 48 | .name = "NOR Partition 2 for image (1M)", | ||
| 49 | .size = 0x100000, | ||
| 50 | .offset = 0x100000, | ||
| 51 | }, | ||
| 52 | { | ||
| 53 | .name = "NOR Partition 3 for user (2M)", | ||
| 54 | .size = 0x200000, | ||
| 55 | .offset = 0x00200000, | ||
| 56 | } | ||
| 37 | }; | 57 | }; |
| 38 | 58 | ||
| 39 | static struct w90x900_uartcfg w90p910_uartcfgs[] = { | 59 | static struct physmap_flash_data w90p910_flash_data = { |
| 40 | W90X900_UARTCFG(0, 0, 0, 0, 0), | 60 | .width = 2, |
| 41 | W90X900_UARTCFG(1, 0, 0, 0, 0), | 61 | .parts = w90p910_flash_partitions, |
| 42 | W90X900_UARTCFG(2, 0, 0, 0, 0), | 62 | .nr_parts = ARRAY_SIZE(w90p910_flash_partitions), |
| 43 | W90X900_UARTCFG(3, 0, 0, 0, 0), | 63 | }; |
| 44 | W90X900_UARTCFG(4, 0, 0, 0, 0), | 64 | |
| 65 | static struct resource w90p910_flash_resources[] = { | ||
| 66 | { | ||
| 67 | .start = W90P910_FLASH_BASE, | ||
| 68 | .end = W90P910_FLASH_BASE + W90P910_FLASH_SIZE - 1, | ||
| 69 | .flags = IORESOURCE_MEM, | ||
| 70 | } | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct platform_device w90p910_flash_device = { | ||
| 74 | .name = "physmap-flash", | ||
| 75 | .id = 0, | ||
| 76 | .dev = { | ||
| 77 | .platform_data = &w90p910_flash_data, | ||
| 78 | }, | ||
| 79 | .resource = w90p910_flash_resources, | ||
| 80 | .num_resources = ARRAY_SIZE(w90p910_flash_resources), | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct map_desc w90p910_iodesc[] __initdata = { | ||
| 45 | }; | 84 | }; |
| 46 | 85 | ||
| 47 | /*Here should be your evb resourse,such as LCD*/ | 86 | /*Here should be your evb resourse,such as LCD*/ |
| 48 | 87 | ||
| 49 | static struct platform_device *w90p910evb_dev[] __initdata = { | 88 | static struct platform_device *w90p910evb_dev[] __initdata = { |
| 89 | &w90p910_serial_device, | ||
| 90 | &w90p910_flash_device, | ||
| 50 | }; | 91 | }; |
| 51 | 92 | ||
| 52 | static void __init w90p910evb_map_io(void) | 93 | static void __init w90p910evb_map_io(void) |
| 53 | { | 94 | { |
| 54 | w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); | 95 | w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); |
| 55 | w90p910_init_clocks(0); | 96 | w90p910_init_clocks(0); |
| 56 | w90p910_init_uarts(w90p910_uartcfgs, ARRAY_SIZE(w90p910_uartcfgs)); | ||
| 57 | } | 97 | } |
| 58 | 98 | ||
| 59 | static void __init w90p910evb_init(void) | 99 | static void __init w90p910evb_init(void) |
diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c index aa783bc94310..2bcbaa681b99 100644 --- a/arch/arm/mach-w90x900/w90p910.c +++ b/arch/arm/mach-w90x900/w90p910.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/init.h> | 25 | #include <linux/init.h> |
| 26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 28 | #include <linux/serial_8250.h> | ||
| 28 | 29 | ||
| 29 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 30 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| @@ -36,12 +37,6 @@ | |||
| 36 | 37 | ||
| 37 | #include "cpu.h" | 38 | #include "cpu.h" |
| 38 | 39 | ||
| 39 | /*W90P910 has five uarts*/ | ||
| 40 | |||
| 41 | #define MAX_UART_COUNT 5 | ||
| 42 | static int uart_count; | ||
| 43 | static struct platform_device *uart_devs[MAX_UART_COUNT-1]; | ||
| 44 | |||
| 45 | /* Initial IO mappings */ | 40 | /* Initial IO mappings */ |
| 46 | 41 | ||
| 47 | static struct map_desc w90p910_iodesc[] __initdata = { | 42 | static struct map_desc w90p910_iodesc[] __initdata = { |
| @@ -53,48 +48,19 @@ static struct map_desc w90p910_iodesc[] __initdata = { | |||
| 53 | /*IODESC_ENT(LCD),*/ | 48 | /*IODESC_ENT(LCD),*/ |
| 54 | }; | 49 | }; |
| 55 | 50 | ||
| 56 | /*Init the dev resource*/ | 51 | /* Initial serial platform data */ |
| 57 | |||
| 58 | static W90X900_RES(UART0); | ||
| 59 | static W90X900_RES(UART1); | ||
| 60 | static W90X900_RES(UART2); | ||
| 61 | static W90X900_RES(UART3); | ||
| 62 | static W90X900_RES(UART4); | ||
| 63 | static W90X900_DEVICE(uart0, UART0, 0, "w90x900-uart"); | ||
| 64 | static W90X900_DEVICE(uart1, UART1, 1, "w90x900-uart"); | ||
| 65 | static W90X900_DEVICE(uart2, UART2, 2, "w90x900-uart"); | ||
| 66 | static W90X900_DEVICE(uart3, UART3, 3, "w90x900-uart"); | ||
| 67 | static W90X900_DEVICE(uart4, UART4, 4, "w90x900-uart"); | ||
| 68 | |||
| 69 | static struct platform_device *uart_devices[] __initdata = { | ||
| 70 | &w90x900_uart0, | ||
| 71 | &w90x900_uart1, | ||
| 72 | &w90x900_uart2, | ||
| 73 | &w90x900_uart3, | ||
| 74 | &w90x900_uart4 | ||
| 75 | }; | ||
| 76 | 52 | ||
| 77 | /*Init W90P910 uart device*/ | 53 | struct plat_serial8250_port w90p910_uart_data[] = { |
| 54 | W90X900_8250PORT(UART0), | ||
| 55 | }; | ||
| 78 | 56 | ||
| 79 | void __init w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no) | 57 | struct platform_device w90p910_serial_device = { |
| 80 | { | 58 | .name = "serial8250", |
| 81 | struct platform_device *platdev; | 59 | .id = PLAT8250_DEV_PLATFORM, |
| 82 | int uart, uartdev; | 60 | .dev = { |
| 83 | 61 | .platform_data = w90p910_uart_data, | |
| 84 | /*By min() to judge count of uart be used indeed*/ | 62 | }, |
| 85 | 63 | }; | |
| 86 | uartdev = ARRAY_SIZE(uart_devices); | ||
| 87 | no = min(uartdev, no); | ||
| 88 | |||
| 89 | for (uart = 0; uart < no; uart++, cfg++) { | ||
| 90 | if (cfg->hwport != uart) | ||
| 91 | printk(KERN_ERR "w90x900_uartcfg[%d] error\n", uart); | ||
| 92 | platdev = uart_devices[cfg->hwport]; | ||
| 93 | uart_devs[uart] = platdev; | ||
| 94 | platdev->dev.platform_data = cfg; | ||
| 95 | } | ||
| 96 | uart_count = uart; | ||
| 97 | } | ||
| 98 | 64 | ||
| 99 | /*Init W90P910 evb io*/ | 65 | /*Init W90P910 evb io*/ |
| 100 | 66 | ||
| @@ -122,13 +88,6 @@ static int __init w90p910_init_cpu(void) | |||
| 122 | 88 | ||
| 123 | static int __init w90x900_arch_init(void) | 89 | static int __init w90x900_arch_init(void) |
| 124 | { | 90 | { |
| 125 | int ret; | 91 | return w90p910_init_cpu(); |
| 126 | |||
| 127 | ret = w90p910_init_cpu(); | ||
| 128 | if (ret != 0) | ||
| 129 | return ret; | ||
| 130 | |||
| 131 | return platform_add_devices(uart_devs, uart_count); | ||
| 132 | |||
| 133 | } | 92 | } |
| 134 | arch_initcall(w90x900_arch_init); | 93 | arch_initcall(w90x900_arch_init); |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index d490f3773c01..20979564e7ee 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
| @@ -186,6 +186,24 @@ config CPU_ARM926T | |||
| 186 | Say Y if you want support for the ARM926T processor. | 186 | Say Y if you want support for the ARM926T processor. |
| 187 | Otherwise, say N. | 187 | Otherwise, say N. |
| 188 | 188 | ||
| 189 | # FA526 | ||
| 190 | config CPU_FA526 | ||
| 191 | bool | ||
| 192 | select CPU_32v4 | ||
| 193 | select CPU_ABRT_EV4 | ||
| 194 | select CPU_PABRT_NOIFAR | ||
| 195 | select CPU_CACHE_VIVT | ||
| 196 | select CPU_CP15_MMU | ||
| 197 | select CPU_CACHE_FA | ||
| 198 | select CPU_COPY_FA if MMU | ||
| 199 | select CPU_TLB_FA if MMU | ||
| 200 | help | ||
| 201 | The FA526 is a version of the ARMv4 compatible processor with | ||
| 202 | Branch Target Buffer, Unified TLB and cache line size 16. | ||
| 203 | |||
| 204 | Say Y if you want support for the FA526 processor. | ||
| 205 | Otherwise, say N. | ||
| 206 | |||
| 189 | # ARM940T | 207 | # ARM940T |
| 190 | config CPU_ARM940T | 208 | config CPU_ARM940T |
| 191 | bool "Support ARM940T processor" if ARCH_INTEGRATOR | 209 | bool "Support ARM940T processor" if ARCH_INTEGRATOR |
| @@ -340,6 +358,17 @@ config CPU_XSC3 | |||
| 340 | select CPU_TLB_V4WBI if MMU | 358 | select CPU_TLB_V4WBI if MMU |
| 341 | select IO_36 | 359 | select IO_36 |
| 342 | 360 | ||
| 361 | # Marvell PJ1 (Mohawk) | ||
| 362 | config CPU_MOHAWK | ||
| 363 | bool | ||
| 364 | select CPU_32v5 | ||
| 365 | select CPU_ABRT_EV5T | ||
| 366 | select CPU_PABRT_NOIFAR | ||
| 367 | select CPU_CACHE_VIVT | ||
| 368 | select CPU_CP15_MMU | ||
| 369 | select CPU_TLB_V4WBI if MMU | ||
| 370 | select CPU_COPY_V4WB if MMU | ||
| 371 | |||
| 343 | # Feroceon | 372 | # Feroceon |
| 344 | config CPU_FEROCEON | 373 | config CPU_FEROCEON |
| 345 | bool | 374 | bool |
| @@ -484,6 +513,9 @@ config CPU_CACHE_VIVT | |||
| 484 | config CPU_CACHE_VIPT | 513 | config CPU_CACHE_VIPT |
| 485 | bool | 514 | bool |
| 486 | 515 | ||
| 516 | config CPU_CACHE_FA | ||
| 517 | bool | ||
| 518 | |||
| 487 | if MMU | 519 | if MMU |
| 488 | # The copy-page model | 520 | # The copy-page model |
| 489 | config CPU_COPY_V3 | 521 | config CPU_COPY_V3 |
| @@ -498,6 +530,9 @@ config CPU_COPY_V4WB | |||
| 498 | config CPU_COPY_FEROCEON | 530 | config CPU_COPY_FEROCEON |
| 499 | bool | 531 | bool |
| 500 | 532 | ||
| 533 | config CPU_COPY_FA | ||
| 534 | bool | ||
| 535 | |||
| 501 | config CPU_COPY_V6 | 536 | config CPU_COPY_V6 |
| 502 | bool | 537 | bool |
| 503 | 538 | ||
| @@ -528,6 +563,13 @@ config CPU_TLB_FEROCEON | |||
| 528 | help | 563 | help |
| 529 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | 564 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). |
| 530 | 565 | ||
| 566 | config CPU_TLB_FA | ||
| 567 | bool | ||
| 568 | help | ||
| 569 | Faraday ARM FA526 architecture, unified TLB with writeback cache | ||
| 570 | and invalidate instruction cache entry. Branch target buffer is | ||
| 571 | also supported. | ||
| 572 | |||
| 531 | config CPU_TLB_V6 | 573 | config CPU_TLB_V6 |
| 532 | bool | 574 | bool |
| 533 | 575 | ||
| @@ -569,7 +611,7 @@ comment "Processor Features" | |||
| 569 | 611 | ||
| 570 | config ARM_THUMB | 612 | config ARM_THUMB |
| 571 | bool "Support Thumb user binaries" | 613 | bool "Support Thumb user binaries" |
| 572 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON | 614 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON |
| 573 | default y | 615 | default y |
| 574 | help | 616 | help |
| 575 | Say Y if you want to include kernel support for running user space | 617 | Say Y if you want to include kernel support for running user space |
| @@ -638,7 +680,7 @@ config CPU_DCACHE_SIZE | |||
| 638 | 680 | ||
| 639 | config CPU_DCACHE_WRITETHROUGH | 681 | config CPU_DCACHE_WRITETHROUGH |
| 640 | bool "Force write through D-cache" | 682 | bool "Force write through D-cache" |
| 641 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE | 683 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
| 642 | default y if CPU_ARM925T | 684 | default y if CPU_ARM925T |
| 643 | help | 685 | help |
| 644 | Say Y here to use the data cache in writethrough mode. Unless you | 686 | Say Y here to use the data cache in writethrough mode. Unless you |
| @@ -653,7 +695,7 @@ config CPU_CACHE_ROUND_ROBIN | |||
| 653 | 695 | ||
| 654 | config CPU_BPREDICT_DISABLE | 696 | config CPU_BPREDICT_DISABLE |
| 655 | bool "Disable branch prediction" | 697 | bool "Disable branch prediction" |
| 656 | depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 | 698 | depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
| 657 | help | 699 | help |
| 658 | Say Y here to disable branch prediction. If unsure, say N. | 700 | Say Y here to disable branch prediction. If unsure, say N. |
| 659 | 701 | ||
| @@ -704,7 +746,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH | |||
| 704 | 746 | ||
| 705 | config CACHE_L2X0 | 747 | config CACHE_L2X0 |
| 706 | bool "Enable the L2x0 outer cache controller" | 748 | bool "Enable the L2x0 outer cache controller" |
| 707 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP | 749 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ |
| 750 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 | ||
| 708 | default y | 751 | default y |
| 709 | select OUTER_CACHE | 752 | select OUTER_CACHE |
| 710 | help | 753 | help |
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 480f78a3611a..63e3f6dd0e21 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile | |||
| @@ -16,6 +16,7 @@ obj-$(CONFIG_MODULES) += proc-syms.o | |||
| 16 | 16 | ||
| 17 | obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o | 17 | obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o |
| 18 | obj-$(CONFIG_DISCONTIGMEM) += discontig.o | 18 | obj-$(CONFIG_DISCONTIGMEM) += discontig.o |
| 19 | obj-$(CONFIG_HIGHMEM) += highmem.o | ||
| 19 | 20 | ||
| 20 | obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o | 21 | obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o |
| 21 | obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o | 22 | obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o |
| @@ -32,6 +33,7 @@ obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o | |||
| 32 | obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o | 33 | obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o |
| 33 | obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o | 34 | obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o |
| 34 | obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o | 35 | obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o |
| 36 | obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o | ||
| 35 | 37 | ||
| 36 | obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o | 38 | obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o |
| 37 | obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o | 39 | obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o |
| @@ -41,6 +43,7 @@ obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o context.o | |||
| 41 | obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o | 43 | obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o |
| 42 | obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o | 44 | obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o |
| 43 | obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o | 45 | obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o |
| 46 | obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o | ||
| 44 | 47 | ||
| 45 | obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o | 48 | obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o |
| 46 | obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o | 49 | obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o |
| @@ -49,6 +52,7 @@ obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o | |||
| 49 | obj-$(CONFIG_CPU_TLB_FEROCEON) += tlb-v4wbi.o # reuse v4wbi TLB functions | 52 | obj-$(CONFIG_CPU_TLB_FEROCEON) += tlb-v4wbi.o # reuse v4wbi TLB functions |
| 50 | obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o | 53 | obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o |
| 51 | obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o | 54 | obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o |
| 55 | obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o | ||
| 52 | 56 | ||
| 53 | obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o | 57 | obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o |
| 54 | obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o | 58 | obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o |
| @@ -62,6 +66,7 @@ obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o | |||
| 62 | obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o | 66 | obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o |
| 63 | obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o | 67 | obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o |
| 64 | obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o | 68 | obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o |
| 69 | obj-$(CONFIG_CPU_FA526) += proc-fa526.o | ||
| 65 | obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o | 70 | obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o |
| 66 | obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o | 71 | obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o |
| 67 | obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o | 72 | obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o |
| @@ -70,6 +75,7 @@ obj-$(CONFIG_CPU_SA110) += proc-sa110.o | |||
| 70 | obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o | 75 | obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o |
| 71 | obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o | 76 | obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o |
| 72 | obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o | 77 | obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o |
| 78 | obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o | ||
| 73 | obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o | 79 | obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o |
| 74 | obj-$(CONFIG_CPU_V6) += proc-v6.o | 80 | obj-$(CONFIG_CPU_V6) += proc-v6.o |
| 75 | obj-$(CONFIG_CPU_V7) += proc-v7.o | 81 | obj-$(CONFIG_CPU_V7) += proc-v7.o |
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S new file mode 100644 index 000000000000..b63a8f7b95cf --- /dev/null +++ b/arch/arm/mm/cache-fa.S | |||
| @@ -0,0 +1,220 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mm/cache-fa.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Faraday Corp. | ||
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 6 | * | ||
| 7 | * Based on cache-v4wb.S: | ||
| 8 | * Copyright (C) 1997-2002 Russell king | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * Processors: FA520 FA526 FA626 | ||
| 15 | */ | ||
| 16 | #include <linux/linkage.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <asm/memory.h> | ||
| 19 | #include <asm/page.h> | ||
| 20 | |||
| 21 | #include "proc-macros.S" | ||
| 22 | |||
| 23 | /* | ||
| 24 | * The size of one data cache line. | ||
| 25 | */ | ||
| 26 | #define CACHE_DLINESIZE 16 | ||
| 27 | |||
| 28 | /* | ||
| 29 | * The total size of the data cache. | ||
| 30 | */ | ||
| 31 | #ifdef CONFIG_ARCH_GEMINI | ||
| 32 | #define CACHE_DSIZE 8192 | ||
| 33 | #else | ||
| 34 | #define CACHE_DSIZE 16384 | ||
| 35 | #endif | ||
| 36 | |||
| 37 | /* FIXME: put optimal value here. Current one is just estimation */ | ||
| 38 | #define CACHE_DLIMIT (CACHE_DSIZE * 2) | ||
| 39 | |||
| 40 | /* | ||
| 41 | * flush_user_cache_all() | ||
| 42 | * | ||
| 43 | * Clean and invalidate all cache entries in a particular address | ||
| 44 | * space. | ||
| 45 | */ | ||
| 46 | ENTRY(fa_flush_user_cache_all) | ||
| 47 | /* FALLTHROUGH */ | ||
| 48 | /* | ||
| 49 | * flush_kern_cache_all() | ||
| 50 | * | ||
| 51 | * Clean and invalidate the entire cache. | ||
| 52 | */ | ||
| 53 | ENTRY(fa_flush_kern_cache_all) | ||
| 54 | mov ip, #0 | ||
| 55 | mov r2, #VM_EXEC | ||
| 56 | __flush_whole_cache: | ||
| 57 | mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache | ||
| 58 | tst r2, #VM_EXEC | ||
| 59 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | ||
| 60 | mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB | ||
| 61 | mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer | ||
| 62 | mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush | ||
| 63 | mov pc, lr | ||
| 64 | |||
| 65 | /* | ||
| 66 | * flush_user_cache_range(start, end, flags) | ||
| 67 | * | ||
| 68 | * Invalidate a range of cache entries in the specified | ||
| 69 | * address space. | ||
| 70 | * | ||
| 71 | * - start - start address (inclusive, page aligned) | ||
| 72 | * - end - end address (exclusive, page aligned) | ||
| 73 | * - flags - vma_area_struct flags describing address space | ||
| 74 | */ | ||
| 75 | ENTRY(fa_flush_user_cache_range) | ||
| 76 | mov ip, #0 | ||
| 77 | sub r3, r1, r0 @ calculate total size | ||
| 78 | cmp r3, #CACHE_DLIMIT @ total size >= limit? | ||
| 79 | bhs __flush_whole_cache @ flush whole D cache | ||
| 80 | |||
| 81 | 1: tst r2, #VM_EXEC | ||
| 82 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line | ||
| 83 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | ||
| 84 | add r0, r0, #CACHE_DLINESIZE | ||
| 85 | cmp r0, r1 | ||
| 86 | blo 1b | ||
| 87 | tst r2, #VM_EXEC | ||
| 88 | mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB | ||
| 89 | mcrne p15, 0, ip, c7, c10, 4 @ data write barrier | ||
| 90 | mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush | ||
| 91 | mov pc, lr | ||
| 92 | |||
| 93 | /* | ||
| 94 | * coherent_kern_range(start, end) | ||
| 95 | * | ||
| 96 | * Ensure coherency between the Icache and the Dcache in the | ||
| 97 | * region described by start. If you have non-snooping | ||
| 98 | * Harvard caches, you need to implement this function. | ||
| 99 | * | ||
| 100 | * - start - virtual start address | ||
| 101 | * - end - virtual end address | ||
| 102 | */ | ||
| 103 | ENTRY(fa_coherent_kern_range) | ||
| 104 | /* fall through */ | ||
| 105 | |||
| 106 | /* | ||
| 107 | * coherent_user_range(start, end) | ||
| 108 | * | ||
| 109 | * Ensure coherency between the Icache and the Dcache in the | ||
| 110 | * region described by start. If you have non-snooping | ||
| 111 | * Harvard caches, you need to implement this function. | ||
| 112 | * | ||
| 113 | * - start - virtual start address | ||
| 114 | * - end - virtual end address | ||
| 115 | */ | ||
| 116 | ENTRY(fa_coherent_user_range) | ||
| 117 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 118 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | ||
| 119 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 120 | add r0, r0, #CACHE_DLINESIZE | ||
| 121 | cmp r0, r1 | ||
| 122 | blo 1b | ||
| 123 | mov r0, #0 | ||
| 124 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB | ||
| 125 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 126 | mcr p15, 0, r0, c7, c5, 4 @ prefetch flush | ||
| 127 | mov pc, lr | ||
| 128 | |||
| 129 | /* | ||
| 130 | * flush_kern_dcache_page(kaddr) | ||
| 131 | * | ||
| 132 | * Ensure that the data held in the page kaddr is written back | ||
| 133 | * to the page in question. | ||
| 134 | * | ||
| 135 | * - kaddr - kernel address (guaranteed to be page aligned) | ||
| 136 | */ | ||
| 137 | ENTRY(fa_flush_kern_dcache_page) | ||
| 138 | add r1, r0, #PAGE_SZ | ||
| 139 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line | ||
| 140 | add r0, r0, #CACHE_DLINESIZE | ||
| 141 | cmp r0, r1 | ||
| 142 | blo 1b | ||
| 143 | mov r0, #0 | ||
| 144 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | ||
| 145 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 146 | mov pc, lr | ||
| 147 | |||
| 148 | /* | ||
| 149 | * dma_inv_range(start, end) | ||
| 150 | * | ||
| 151 | * Invalidate (discard) the specified virtual address range. | ||
| 152 | * May not write back any entries. If 'start' or 'end' | ||
| 153 | * are not cache line aligned, those lines must be written | ||
| 154 | * back. | ||
| 155 | * | ||
| 156 | * - start - virtual start address | ||
| 157 | * - end - virtual end address | ||
| 158 | */ | ||
| 159 | ENTRY(fa_dma_inv_range) | ||
| 160 | tst r0, #CACHE_DLINESIZE - 1 | ||
| 161 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 162 | mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry | ||
| 163 | tst r1, #CACHE_DLINESIZE - 1 | ||
| 164 | bic r1, r1, #CACHE_DLINESIZE - 1 | ||
| 165 | mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry | ||
| 166 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | ||
| 167 | add r0, r0, #CACHE_DLINESIZE | ||
| 168 | cmp r0, r1 | ||
| 169 | blo 1b | ||
| 170 | mov r0, #0 | ||
| 171 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 172 | mov pc, lr | ||
| 173 | |||
| 174 | /* | ||
| 175 | * dma_clean_range(start, end) | ||
| 176 | * | ||
| 177 | * Clean (write back) the specified virtual address range. | ||
| 178 | * | ||
| 179 | * - start - virtual start address | ||
| 180 | * - end - virtual end address | ||
| 181 | */ | ||
| 182 | ENTRY(fa_dma_clean_range) | ||
| 183 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 184 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 185 | add r0, r0, #CACHE_DLINESIZE | ||
| 186 | cmp r0, r1 | ||
| 187 | blo 1b | ||
| 188 | mov r0, #0 | ||
| 189 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 190 | mov pc, lr | ||
| 191 | |||
| 192 | /* | ||
| 193 | * dma_flush_range(start,end) | ||
| 194 | * - start - virtual start address of region | ||
| 195 | * - end - virtual end address of region | ||
| 196 | */ | ||
| 197 | ENTRY(fa_dma_flush_range) | ||
| 198 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 199 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry | ||
| 200 | add r0, r0, #CACHE_DLINESIZE | ||
| 201 | cmp r0, r1 | ||
| 202 | blo 1b | ||
| 203 | mov r0, #0 | ||
| 204 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 205 | mov pc, lr | ||
| 206 | |||
| 207 | __INITDATA | ||
| 208 | |||
| 209 | .type fa_cache_fns, #object | ||
| 210 | ENTRY(fa_cache_fns) | ||
| 211 | .long fa_flush_kern_cache_all | ||
| 212 | .long fa_flush_user_cache_all | ||
| 213 | .long fa_flush_user_cache_range | ||
| 214 | .long fa_coherent_kern_range | ||
| 215 | .long fa_coherent_user_range | ||
| 216 | .long fa_flush_kern_dcache_page | ||
| 217 | .long fa_dma_inv_range | ||
| 218 | .long fa_dma_clean_range | ||
| 219 | .long fa_dma_flush_range | ||
| 220 | .size fa_cache_fns, . - fa_cache_fns | ||
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 80cd207cbaea..d6dd83826f8a 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c | |||
| @@ -14,8 +14,12 @@ | |||
| 14 | 14 | ||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <asm/cacheflush.h> | 16 | #include <asm/cacheflush.h> |
| 17 | #include <asm/kmap_types.h> | ||
| 18 | #include <asm/fixmap.h> | ||
| 19 | #include <asm/pgtable.h> | ||
| 20 | #include <asm/tlbflush.h> | ||
| 17 | #include <plat/cache-feroceon-l2.h> | 21 | #include <plat/cache-feroceon-l2.h> |
| 18 | 22 | #include "mm.h" | |
| 19 | 23 | ||
| 20 | /* | 24 | /* |
| 21 | * Low-level cache maintenance operations. | 25 | * Low-level cache maintenance operations. |
| @@ -34,14 +38,36 @@ | |||
| 34 | * The range operations require two successive cp15 writes, in | 38 | * The range operations require two successive cp15 writes, in |
| 35 | * between which we don't want to be preempted. | 39 | * between which we don't want to be preempted. |
| 36 | */ | 40 | */ |
| 41 | |||
| 42 | static inline unsigned long l2_start_va(unsigned long paddr) | ||
| 43 | { | ||
| 44 | #ifdef CONFIG_HIGHMEM | ||
| 45 | /* | ||
| 46 | * Let's do our own fixmap stuff in a minimal way here. | ||
| 47 | * Because range ops can't be done on physical addresses, | ||
| 48 | * we simply install a virtual mapping for it only for the | ||
| 49 | * TLB lookup to occur, hence no need to flush the untouched | ||
| 50 | * memory mapping. This is protected with the disabling of | ||
| 51 | * interrupts by the caller. | ||
| 52 | */ | ||
| 53 | unsigned long idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id(); | ||
| 54 | unsigned long vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 55 | set_pte_ext(TOP_PTE(vaddr), pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL), 0); | ||
| 56 | local_flush_tlb_kernel_page(vaddr); | ||
| 57 | return vaddr + (paddr & ~PAGE_MASK); | ||
| 58 | #else | ||
| 59 | return __phys_to_virt(paddr); | ||
| 60 | #endif | ||
| 61 | } | ||
| 62 | |||
| 37 | static inline void l2_clean_pa(unsigned long addr) | 63 | static inline void l2_clean_pa(unsigned long addr) |
| 38 | { | 64 | { |
| 39 | __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); | 65 | __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); |
| 40 | } | 66 | } |
| 41 | 67 | ||
| 42 | static inline void l2_clean_mva_range(unsigned long start, unsigned long end) | 68 | static inline void l2_clean_pa_range(unsigned long start, unsigned long end) |
| 43 | { | 69 | { |
| 44 | unsigned long flags; | 70 | unsigned long va_start, va_end, flags; |
| 45 | 71 | ||
| 46 | /* | 72 | /* |
| 47 | * Make sure 'start' and 'end' reference the same page, as | 73 | * Make sure 'start' and 'end' reference the same page, as |
| @@ -51,17 +77,14 @@ static inline void l2_clean_mva_range(unsigned long start, unsigned long end) | |||
| 51 | BUG_ON((start ^ end) >> PAGE_SHIFT); | 77 | BUG_ON((start ^ end) >> PAGE_SHIFT); |
| 52 | 78 | ||
| 53 | raw_local_irq_save(flags); | 79 | raw_local_irq_save(flags); |
| 80 | va_start = l2_start_va(start); | ||
| 81 | va_end = va_start + (end - start); | ||
| 54 | __asm__("mcr p15, 1, %0, c15, c9, 4\n\t" | 82 | __asm__("mcr p15, 1, %0, c15, c9, 4\n\t" |
| 55 | "mcr p15, 1, %1, c15, c9, 5" | 83 | "mcr p15, 1, %1, c15, c9, 5" |
| 56 | : : "r" (start), "r" (end)); | 84 | : : "r" (va_start), "r" (va_end)); |
| 57 | raw_local_irq_restore(flags); | 85 | raw_local_irq_restore(flags); |
| 58 | } | 86 | } |
| 59 | 87 | ||
| 60 | static inline void l2_clean_pa_range(unsigned long start, unsigned long end) | ||
| 61 | { | ||
| 62 | l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end)); | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline void l2_clean_inv_pa(unsigned long addr) | 88 | static inline void l2_clean_inv_pa(unsigned long addr) |
| 66 | { | 89 | { |
| 67 | __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); | 90 | __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); |
| @@ -72,9 +95,9 @@ static inline void l2_inv_pa(unsigned long addr) | |||
| 72 | __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); | 95 | __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); |
| 73 | } | 96 | } |
| 74 | 97 | ||
| 75 | static inline void l2_inv_mva_range(unsigned long start, unsigned long end) | 98 | static inline void l2_inv_pa_range(unsigned long start, unsigned long end) |
| 76 | { | 99 | { |
| 77 | unsigned long flags; | 100 | unsigned long va_start, va_end, flags; |
| 78 | 101 | ||
| 79 | /* | 102 | /* |
| 80 | * Make sure 'start' and 'end' reference the same page, as | 103 | * Make sure 'start' and 'end' reference the same page, as |
| @@ -84,17 +107,14 @@ static inline void l2_inv_mva_range(unsigned long start, unsigned long end) | |||
| 84 | BUG_ON((start ^ end) >> PAGE_SHIFT); | 107 | BUG_ON((start ^ end) >> PAGE_SHIFT); |
| 85 | 108 | ||
| 86 | raw_local_irq_save(flags); | 109 | raw_local_irq_save(flags); |
| 110 | va_start = l2_start_va(start); | ||
| 111 | va_end = va_start + (end - start); | ||
| 87 | __asm__("mcr p15, 1, %0, c15, c11, 4\n\t" | 112 | __asm__("mcr p15, 1, %0, c15, c11, 4\n\t" |
| 88 | "mcr p15, 1, %1, c15, c11, 5" | 113 | "mcr p15, 1, %1, c15, c11, 5" |
| 89 | : : "r" (start), "r" (end)); | 114 | : : "r" (va_start), "r" (va_end)); |
| 90 | raw_local_irq_restore(flags); | 115 | raw_local_irq_restore(flags); |
| 91 | } | 116 | } |
| 92 | 117 | ||
| 93 | static inline void l2_inv_pa_range(unsigned long start, unsigned long end) | ||
| 94 | { | ||
| 95 | l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end)); | ||
| 96 | } | ||
| 97 | |||
| 98 | 118 | ||
| 99 | /* | 119 | /* |
| 100 | * Linux primitives. | 120 | * Linux primitives. |
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 464de893a988..5d180cb0bd94 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c | |||
| @@ -17,12 +17,14 @@ | |||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ | 18 | */ |
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/spinlock.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | |||
| 23 | #include <asm/system.h> | 20 | #include <asm/system.h> |
| 24 | #include <asm/cputype.h> | 21 | #include <asm/cputype.h> |
| 25 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
| 23 | #include <asm/kmap_types.h> | ||
| 24 | #include <asm/fixmap.h> | ||
| 25 | #include <asm/pgtable.h> | ||
| 26 | #include <asm/tlbflush.h> | ||
| 27 | #include "mm.h" | ||
| 26 | 28 | ||
| 27 | #define CR_L2 (1 << 26) | 29 | #define CR_L2 (1 << 26) |
| 28 | 30 | ||
| @@ -47,21 +49,11 @@ static inline void xsc3_l2_clean_mva(unsigned long addr) | |||
| 47 | __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr)); | 49 | __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr)); |
| 48 | } | 50 | } |
| 49 | 51 | ||
| 50 | static inline void xsc3_l2_clean_pa(unsigned long addr) | ||
| 51 | { | ||
| 52 | xsc3_l2_clean_mva(__phys_to_virt(addr)); | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline void xsc3_l2_inv_mva(unsigned long addr) | 52 | static inline void xsc3_l2_inv_mva(unsigned long addr) |
| 56 | { | 53 | { |
| 57 | __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr)); | 54 | __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr)); |
| 58 | } | 55 | } |
| 59 | 56 | ||
| 60 | static inline void xsc3_l2_inv_pa(unsigned long addr) | ||
| 61 | { | ||
| 62 | xsc3_l2_inv_mva(__phys_to_virt(addr)); | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline void xsc3_l2_inv_all(void) | 57 | static inline void xsc3_l2_inv_all(void) |
| 66 | { | 58 | { |
| 67 | unsigned long l2ctype, set_way; | 59 | unsigned long l2ctype, set_way; |
| @@ -79,50 +71,103 @@ static inline void xsc3_l2_inv_all(void) | |||
| 79 | dsb(); | 71 | dsb(); |
| 80 | } | 72 | } |
| 81 | 73 | ||
| 74 | #ifdef CONFIG_HIGHMEM | ||
| 75 | #define l2_map_save_flags(x) raw_local_save_flags(x) | ||
| 76 | #define l2_map_restore_flags(x) raw_local_irq_restore(x) | ||
| 77 | #else | ||
| 78 | #define l2_map_save_flags(x) ((x) = 0) | ||
| 79 | #define l2_map_restore_flags(x) ((void)(x)) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va, | ||
| 83 | unsigned long flags) | ||
| 84 | { | ||
| 85 | #ifdef CONFIG_HIGHMEM | ||
| 86 | unsigned long va = prev_va & PAGE_MASK; | ||
| 87 | unsigned long pa_offset = pa << (32 - PAGE_SHIFT); | ||
| 88 | if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { | ||
| 89 | /* | ||
| 90 | * Switching to a new page. Because cache ops are | ||
| 91 | * using virtual addresses only, we must put a mapping | ||
| 92 | * in place for it. We also enable interrupts for a | ||
| 93 | * short while and disable them again to protect this | ||
| 94 | * mapping. | ||
| 95 | */ | ||
| 96 | unsigned long idx; | ||
| 97 | raw_local_irq_restore(flags); | ||
| 98 | idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id(); | ||
| 99 | va = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 100 | raw_local_irq_restore(flags | PSR_I_BIT); | ||
| 101 | set_pte_ext(TOP_PTE(va), pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL), 0); | ||
| 102 | local_flush_tlb_kernel_page(va); | ||
| 103 | } | ||
| 104 | return va + (pa_offset >> (32 - PAGE_SHIFT)); | ||
| 105 | #else | ||
| 106 | return __phys_to_virt(pa); | ||
| 107 | #endif | ||
| 108 | } | ||
| 109 | |||
| 82 | static void xsc3_l2_inv_range(unsigned long start, unsigned long end) | 110 | static void xsc3_l2_inv_range(unsigned long start, unsigned long end) |
| 83 | { | 111 | { |
| 112 | unsigned long vaddr, flags; | ||
| 113 | |||
| 84 | if (start == 0 && end == -1ul) { | 114 | if (start == 0 && end == -1ul) { |
| 85 | xsc3_l2_inv_all(); | 115 | xsc3_l2_inv_all(); |
| 86 | return; | 116 | return; |
| 87 | } | 117 | } |
| 88 | 118 | ||
| 119 | vaddr = -1; /* to force the first mapping */ | ||
| 120 | l2_map_save_flags(flags); | ||
| 121 | |||
| 89 | /* | 122 | /* |
| 90 | * Clean and invalidate partial first cache line. | 123 | * Clean and invalidate partial first cache line. |
| 91 | */ | 124 | */ |
| 92 | if (start & (CACHE_LINE_SIZE - 1)) { | 125 | if (start & (CACHE_LINE_SIZE - 1)) { |
| 93 | xsc3_l2_clean_pa(start & ~(CACHE_LINE_SIZE - 1)); | 126 | vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr, flags); |
| 94 | xsc3_l2_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); | 127 | xsc3_l2_clean_mva(vaddr); |
| 128 | xsc3_l2_inv_mva(vaddr); | ||
| 95 | start = (start | (CACHE_LINE_SIZE - 1)) + 1; | 129 | start = (start | (CACHE_LINE_SIZE - 1)) + 1; |
| 96 | } | 130 | } |
| 97 | 131 | ||
| 98 | /* | 132 | /* |
| 99 | * Clean and invalidate partial last cache line. | 133 | * Invalidate all full cache lines between 'start' and 'end'. |
| 100 | */ | 134 | */ |
| 101 | if (start < end && (end & (CACHE_LINE_SIZE - 1))) { | 135 | while (start < (end & ~(CACHE_LINE_SIZE - 1))) { |
| 102 | xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1)); | 136 | vaddr = l2_map_va(start, vaddr, flags); |
| 103 | xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); | 137 | xsc3_l2_inv_mva(vaddr); |
| 104 | end &= ~(CACHE_LINE_SIZE - 1); | 138 | start += CACHE_LINE_SIZE; |
| 105 | } | 139 | } |
| 106 | 140 | ||
| 107 | /* | 141 | /* |
| 108 | * Invalidate all full cache lines between 'start' and 'end'. | 142 | * Clean and invalidate partial last cache line. |
| 109 | */ | 143 | */ |
| 110 | while (start < end) { | 144 | if (start < end) { |
| 111 | xsc3_l2_inv_pa(start); | 145 | vaddr = l2_map_va(start, vaddr, flags); |
| 112 | start += CACHE_LINE_SIZE; | 146 | xsc3_l2_clean_mva(vaddr); |
| 147 | xsc3_l2_inv_mva(vaddr); | ||
| 113 | } | 148 | } |
| 114 | 149 | ||
| 150 | l2_map_restore_flags(flags); | ||
| 151 | |||
| 115 | dsb(); | 152 | dsb(); |
| 116 | } | 153 | } |
| 117 | 154 | ||
| 118 | static void xsc3_l2_clean_range(unsigned long start, unsigned long end) | 155 | static void xsc3_l2_clean_range(unsigned long start, unsigned long end) |
| 119 | { | 156 | { |
| 157 | unsigned long vaddr, flags; | ||
| 158 | |||
| 159 | vaddr = -1; /* to force the first mapping */ | ||
| 160 | l2_map_save_flags(flags); | ||
| 161 | |||
| 120 | start &= ~(CACHE_LINE_SIZE - 1); | 162 | start &= ~(CACHE_LINE_SIZE - 1); |
| 121 | while (start < end) { | 163 | while (start < end) { |
| 122 | xsc3_l2_clean_pa(start); | 164 | vaddr = l2_map_va(start, vaddr, flags); |
| 165 | xsc3_l2_clean_mva(vaddr); | ||
| 123 | start += CACHE_LINE_SIZE; | 166 | start += CACHE_LINE_SIZE; |
| 124 | } | 167 | } |
| 125 | 168 | ||
| 169 | l2_map_restore_flags(flags); | ||
| 170 | |||
| 126 | dsb(); | 171 | dsb(); |
| 127 | } | 172 | } |
| 128 | 173 | ||
| @@ -148,18 +193,26 @@ static inline void xsc3_l2_flush_all(void) | |||
| 148 | 193 | ||
| 149 | static void xsc3_l2_flush_range(unsigned long start, unsigned long end) | 194 | static void xsc3_l2_flush_range(unsigned long start, unsigned long end) |
| 150 | { | 195 | { |
| 196 | unsigned long vaddr, flags; | ||
| 197 | |||
| 151 | if (start == 0 && end == -1ul) { | 198 | if (start == 0 && end == -1ul) { |
| 152 | xsc3_l2_flush_all(); | 199 | xsc3_l2_flush_all(); |
| 153 | return; | 200 | return; |
| 154 | } | 201 | } |
| 155 | 202 | ||
| 203 | vaddr = -1; /* to force the first mapping */ | ||
| 204 | l2_map_save_flags(flags); | ||
| 205 | |||
| 156 | start &= ~(CACHE_LINE_SIZE - 1); | 206 | start &= ~(CACHE_LINE_SIZE - 1); |
| 157 | while (start < end) { | 207 | while (start < end) { |
| 158 | xsc3_l2_clean_pa(start); | 208 | vaddr = l2_map_va(start, vaddr, flags); |
| 159 | xsc3_l2_inv_pa(start); | 209 | xsc3_l2_clean_mva(vaddr); |
| 210 | xsc3_l2_inv_mva(vaddr); | ||
| 160 | start += CACHE_LINE_SIZE; | 211 | start += CACHE_LINE_SIZE; |
| 161 | } | 212 | } |
| 162 | 213 | ||
| 214 | l2_map_restore_flags(flags); | ||
| 215 | |||
| 163 | dsb(); | 216 | dsb(); |
| 164 | } | 217 | } |
| 165 | 218 | ||
diff --git a/arch/arm/mm/copypage-fa.c b/arch/arm/mm/copypage-fa.c new file mode 100644 index 000000000000..b2a6008b0111 --- /dev/null +++ b/arch/arm/mm/copypage-fa.c | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/lib/copypage-fa.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Faraday Corp. | ||
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 6 | * | ||
| 7 | * Based on copypage-v4wb.S: | ||
| 8 | * Copyright (C) 1995-1999 Russell King | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/highmem.h> | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Faraday optimised copy_user_page | ||
| 19 | */ | ||
| 20 | static void __naked | ||
| 21 | fa_copy_user_page(void *kto, const void *kfrom) | ||
| 22 | { | ||
| 23 | asm("\ | ||
| 24 | stmfd sp!, {r4, lr} @ 2\n\ | ||
| 25 | mov r2, %0 @ 1\n\ | ||
| 26 | 1: ldmia r1!, {r3, r4, ip, lr} @ 4\n\ | ||
| 27 | stmia r0, {r3, r4, ip, lr} @ 4\n\ | ||
| 28 | mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ | ||
| 29 | add r0, r0, #16 @ 1\n\ | ||
| 30 | ldmia r1!, {r3, r4, ip, lr} @ 4\n\ | ||
| 31 | stmia r0, {r3, r4, ip, lr} @ 4\n\ | ||
| 32 | mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ | ||
| 33 | add r0, r0, #16 @ 1\n\ | ||
| 34 | subs r2, r2, #1 @ 1\n\ | ||
| 35 | bne 1b @ 1\n\ | ||
| 36 | mcr p15, 0, r2, c7, c10, 4 @ 1 drain WB\n\ | ||
| 37 | ldmfd sp!, {r4, pc} @ 3" | ||
| 38 | : | ||
| 39 | : "I" (PAGE_SIZE / 32)); | ||
| 40 | } | ||
| 41 | |||
| 42 | void fa_copy_user_highpage(struct page *to, struct page *from, | ||
| 43 | unsigned long vaddr) | ||
| 44 | { | ||
| 45 | void *kto, *kfrom; | ||
| 46 | |||
| 47 | kto = kmap_atomic(to, KM_USER0); | ||
| 48 | kfrom = kmap_atomic(from, KM_USER1); | ||
| 49 | fa_copy_user_page(kto, kfrom); | ||
| 50 | kunmap_atomic(kfrom, KM_USER1); | ||
| 51 | kunmap_atomic(kto, KM_USER0); | ||
| 52 | } | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Faraday optimised clear_user_page | ||
| 56 | * | ||
| 57 | * Same story as above. | ||
| 58 | */ | ||
| 59 | void fa_clear_user_highpage(struct page *page, unsigned long vaddr) | ||
| 60 | { | ||
| 61 | void *ptr, *kaddr = kmap_atomic(page, KM_USER0); | ||
| 62 | asm volatile("\ | ||
| 63 | mov r1, %2 @ 1\n\ | ||
| 64 | mov r2, #0 @ 1\n\ | ||
| 65 | mov r3, #0 @ 1\n\ | ||
| 66 | mov ip, #0 @ 1\n\ | ||
| 67 | mov lr, #0 @ 1\n\ | ||
| 68 | 1: stmia %0, {r2, r3, ip, lr} @ 4\n\ | ||
| 69 | mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ | ||
| 70 | add %0, %0, #16 @ 1\n\ | ||
| 71 | stmia %0, {r2, r3, ip, lr} @ 4\n\ | ||
| 72 | mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ | ||
| 73 | add %0, %0, #16 @ 1\n\ | ||
| 74 | subs r1, r1, #1 @ 1\n\ | ||
| 75 | bne 1b @ 1\n\ | ||
| 76 | mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" | ||
| 77 | : "=r" (ptr) | ||
| 78 | : "0" (kaddr), "I" (PAGE_SIZE / 32) | ||
| 79 | : "r1", "r2", "r3", "ip", "lr"); | ||
| 80 | kunmap_atomic(kaddr, KM_USER0); | ||
| 81 | } | ||
| 82 | |||
| 83 | struct cpu_user_fns fa_user_fns __initdata = { | ||
| 84 | .cpu_clear_user_highpage = fa_clear_user_highpage, | ||
| 85 | .cpu_copy_user_highpage = fa_copy_user_highpage, | ||
| 86 | }; | ||
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index f1ef5613ccd4..510c179b0ac8 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/dma-mapping.h> | 19 | #include <linux/dma-mapping.h> |
| 20 | 20 | ||
| 21 | #include <asm/memory.h> | 21 | #include <asm/memory.h> |
| 22 | #include <asm/highmem.h> | ||
| 22 | #include <asm/cacheflush.h> | 23 | #include <asm/cacheflush.h> |
| 23 | #include <asm/tlbflush.h> | 24 | #include <asm/tlbflush.h> |
| 24 | #include <asm/sizes.h> | 25 | #include <asm/sizes.h> |
| @@ -517,6 +518,74 @@ void dma_cache_maint(const void *start, size_t size, int direction) | |||
| 517 | } | 518 | } |
| 518 | EXPORT_SYMBOL(dma_cache_maint); | 519 | EXPORT_SYMBOL(dma_cache_maint); |
| 519 | 520 | ||
| 521 | static void dma_cache_maint_contiguous(struct page *page, unsigned long offset, | ||
| 522 | size_t size, int direction) | ||
| 523 | { | ||
| 524 | void *vaddr; | ||
| 525 | unsigned long paddr; | ||
| 526 | void (*inner_op)(const void *, const void *); | ||
| 527 | void (*outer_op)(unsigned long, unsigned long); | ||
| 528 | |||
| 529 | switch (direction) { | ||
| 530 | case DMA_FROM_DEVICE: /* invalidate only */ | ||
| 531 | inner_op = dmac_inv_range; | ||
| 532 | outer_op = outer_inv_range; | ||
| 533 | break; | ||
| 534 | case DMA_TO_DEVICE: /* writeback only */ | ||
| 535 | inner_op = dmac_clean_range; | ||
| 536 | outer_op = outer_clean_range; | ||
| 537 | break; | ||
| 538 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | ||
| 539 | inner_op = dmac_flush_range; | ||
| 540 | outer_op = outer_flush_range; | ||
| 541 | break; | ||
| 542 | default: | ||
| 543 | BUG(); | ||
| 544 | } | ||
| 545 | |||
| 546 | if (!PageHighMem(page)) { | ||
| 547 | vaddr = page_address(page) + offset; | ||
| 548 | inner_op(vaddr, vaddr + size); | ||
| 549 | } else { | ||
| 550 | vaddr = kmap_high_get(page); | ||
| 551 | if (vaddr) { | ||
| 552 | vaddr += offset; | ||
| 553 | inner_op(vaddr, vaddr + size); | ||
| 554 | kunmap_high(page); | ||
| 555 | } | ||
| 556 | } | ||
| 557 | |||
| 558 | paddr = page_to_phys(page) + offset; | ||
| 559 | outer_op(paddr, paddr + size); | ||
| 560 | } | ||
| 561 | |||
| 562 | void dma_cache_maint_page(struct page *page, unsigned long offset, | ||
| 563 | size_t size, int dir) | ||
| 564 | { | ||
| 565 | /* | ||
| 566 | * A single sg entry may refer to multiple physically contiguous | ||
| 567 | * pages. But we still need to process highmem pages individually. | ||
| 568 | * If highmem is not configured then the bulk of this loop gets | ||
| 569 | * optimized out. | ||
| 570 | */ | ||
| 571 | size_t left = size; | ||
| 572 | do { | ||
| 573 | size_t len = left; | ||
| 574 | if (PageHighMem(page) && len + offset > PAGE_SIZE) { | ||
| 575 | if (offset >= PAGE_SIZE) { | ||
| 576 | page += offset / PAGE_SIZE; | ||
| 577 | offset %= PAGE_SIZE; | ||
| 578 | } | ||
| 579 | len = PAGE_SIZE - offset; | ||
| 580 | } | ||
| 581 | dma_cache_maint_contiguous(page, offset, len, dir); | ||
| 582 | offset = 0; | ||
| 583 | page++; | ||
| 584 | left -= len; | ||
| 585 | } while (left); | ||
| 586 | } | ||
| 587 | EXPORT_SYMBOL(dma_cache_maint_page); | ||
| 588 | |||
| 520 | /** | 589 | /** |
| 521 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | 590 | * dma_map_sg - map a set of SG buffers for streaming mode DMA |
| 522 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | 591 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
| @@ -614,7 +683,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |||
| 614 | continue; | 683 | continue; |
| 615 | 684 | ||
| 616 | if (!arch_is_coherent()) | 685 | if (!arch_is_coherent()) |
| 617 | dma_cache_maint(sg_virt(s), s->length, dir); | 686 | dma_cache_maint_page(sg_page(s), s->offset, |
| 687 | s->length, dir); | ||
| 618 | } | 688 | } |
| 619 | } | 689 | } |
| 620 | EXPORT_SYMBOL(dma_sync_sg_for_device); | 690 | EXPORT_SYMBOL(dma_sync_sg_for_device); |
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 0fa9bf388f0b..4e283481cee1 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c | |||
| @@ -192,7 +192,7 @@ void flush_dcache_page(struct page *page) | |||
| 192 | struct address_space *mapping = page_mapping(page); | 192 | struct address_space *mapping = page_mapping(page); |
| 193 | 193 | ||
| 194 | #ifndef CONFIG_SMP | 194 | #ifndef CONFIG_SMP |
| 195 | if (mapping && !mapping_mapped(mapping)) | 195 | if (!PageHighMem(page) && mapping && !mapping_mapped(mapping)) |
| 196 | set_bit(PG_dcache_dirty, &page->flags); | 196 | set_bit(PG_dcache_dirty, &page->flags); |
| 197 | else | 197 | else |
| 198 | #endif | 198 | #endif |
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c new file mode 100644 index 000000000000..a34954d9df7d --- /dev/null +++ b/arch/arm/mm/highmem.c | |||
| @@ -0,0 +1,116 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mm/highmem.c -- ARM highmem support | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: september 8, 2008 | ||
| 6 | * Copyright: Marvell Semiconductors Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/highmem.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <asm/fixmap.h> | ||
| 17 | #include <asm/cacheflush.h> | ||
| 18 | #include <asm/tlbflush.h> | ||
| 19 | #include "mm.h" | ||
| 20 | |||
| 21 | void *kmap(struct page *page) | ||
| 22 | { | ||
| 23 | might_sleep(); | ||
| 24 | if (!PageHighMem(page)) | ||
| 25 | return page_address(page); | ||
| 26 | return kmap_high(page); | ||
| 27 | } | ||
| 28 | EXPORT_SYMBOL(kmap); | ||
| 29 | |||
| 30 | void kunmap(struct page *page) | ||
| 31 | { | ||
| 32 | BUG_ON(in_interrupt()); | ||
| 33 | if (!PageHighMem(page)) | ||
| 34 | return; | ||
| 35 | kunmap_high(page); | ||
| 36 | } | ||
| 37 | EXPORT_SYMBOL(kunmap); | ||
| 38 | |||
| 39 | void *kmap_atomic(struct page *page, enum km_type type) | ||
| 40 | { | ||
| 41 | unsigned int idx; | ||
| 42 | unsigned long vaddr; | ||
| 43 | |||
| 44 | pagefault_disable(); | ||
| 45 | if (!PageHighMem(page)) | ||
| 46 | return page_address(page); | ||
| 47 | |||
| 48 | idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 49 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 50 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 51 | /* | ||
| 52 | * With debugging enabled, kunmap_atomic forces that entry to 0. | ||
| 53 | * Make sure it was indeed properly unmapped. | ||
| 54 | */ | ||
| 55 | BUG_ON(!pte_none(*(TOP_PTE(vaddr)))); | ||
| 56 | #endif | ||
| 57 | set_pte_ext(TOP_PTE(vaddr), mk_pte(page, kmap_prot), 0); | ||
| 58 | /* | ||
| 59 | * When debugging is off, kunmap_atomic leaves the previous mapping | ||
| 60 | * in place, so this TLB flush ensures the TLB is updated with the | ||
| 61 | * new mapping. | ||
| 62 | */ | ||
| 63 | local_flush_tlb_kernel_page(vaddr); | ||
| 64 | |||
| 65 | return (void *)vaddr; | ||
| 66 | } | ||
| 67 | EXPORT_SYMBOL(kmap_atomic); | ||
| 68 | |||
| 69 | void kunmap_atomic(void *kvaddr, enum km_type type) | ||
| 70 | { | ||
| 71 | unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; | ||
| 72 | unsigned int idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 73 | |||
| 74 | if (kvaddr >= (void *)FIXADDR_START) { | ||
| 75 | __cpuc_flush_dcache_page((void *)vaddr); | ||
| 76 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 77 | BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); | ||
| 78 | set_pte_ext(TOP_PTE(vaddr), __pte(0), 0); | ||
| 79 | local_flush_tlb_kernel_page(vaddr); | ||
| 80 | #else | ||
| 81 | (void) idx; /* to kill a warning */ | ||
| 82 | #endif | ||
| 83 | } | ||
| 84 | pagefault_enable(); | ||
| 85 | } | ||
| 86 | EXPORT_SYMBOL(kunmap_atomic); | ||
| 87 | |||
| 88 | void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) | ||
| 89 | { | ||
| 90 | unsigned int idx; | ||
| 91 | unsigned long vaddr; | ||
| 92 | |||
| 93 | pagefault_disable(); | ||
| 94 | |||
| 95 | idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 96 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 97 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 98 | BUG_ON(!pte_none(*(TOP_PTE(vaddr)))); | ||
| 99 | #endif | ||
| 100 | set_pte_ext(TOP_PTE(vaddr), pfn_pte(pfn, kmap_prot), 0); | ||
| 101 | local_flush_tlb_kernel_page(vaddr); | ||
| 102 | |||
| 103 | return (void *)vaddr; | ||
| 104 | } | ||
| 105 | |||
| 106 | struct page *kmap_atomic_to_page(const void *ptr) | ||
| 107 | { | ||
| 108 | unsigned long vaddr = (unsigned long)ptr; | ||
| 109 | pte_t *pte; | ||
| 110 | |||
| 111 | if (vaddr < FIXADDR_START) | ||
| 112 | return virt_to_page(ptr); | ||
| 113 | |||
| 114 | pte = TOP_PTE(vaddr); | ||
| 115 | return pte_page(*pte); | ||
| 116 | } | ||
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 80fd3b69ae1f..8277802ec859 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #include <linux/mman.h> | 15 | #include <linux/mman.h> |
| 16 | #include <linux/nodemask.h> | 16 | #include <linux/nodemask.h> |
| 17 | #include <linux/initrd.h> | 17 | #include <linux/initrd.h> |
| 18 | #include <linux/highmem.h> | ||
| 18 | 19 | ||
| 19 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 20 | #include <asm/sections.h> | 21 | #include <asm/sections.h> |
| @@ -485,7 +486,7 @@ void __init mem_init(void) | |||
| 485 | int i, node; | 486 | int i, node; |
| 486 | 487 | ||
| 487 | #ifndef CONFIG_DISCONTIGMEM | 488 | #ifndef CONFIG_DISCONTIGMEM |
| 488 | max_mapnr = virt_to_page(high_memory) - mem_map; | 489 | max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map; |
| 489 | #endif | 490 | #endif |
| 490 | 491 | ||
| 491 | /* this will put all unused low memory onto the freelists */ | 492 | /* this will put all unused low memory onto the freelists */ |
| @@ -504,6 +505,19 @@ void __init mem_init(void) | |||
| 504 | __phys_to_pfn(__pa(swapper_pg_dir)), NULL); | 505 | __phys_to_pfn(__pa(swapper_pg_dir)), NULL); |
| 505 | #endif | 506 | #endif |
| 506 | 507 | ||
| 508 | #ifdef CONFIG_HIGHMEM | ||
| 509 | /* set highmem page free */ | ||
| 510 | for_each_online_node(node) { | ||
| 511 | for_each_nodebank (i, &meminfo, node) { | ||
| 512 | unsigned long start = bank_pfn_start(&meminfo.bank[i]); | ||
| 513 | unsigned long end = bank_pfn_end(&meminfo.bank[i]); | ||
| 514 | if (start >= max_low_pfn + PHYS_PFN_OFFSET) | ||
| 515 | totalhigh_pages += free_area(start, end, NULL); | ||
| 516 | } | ||
| 517 | } | ||
| 518 | totalram_pages += totalhigh_pages; | ||
| 519 | #endif | ||
| 520 | |||
| 507 | /* | 521 | /* |
| 508 | * Since our memory may not be contiguous, calculate the | 522 | * Since our memory may not be contiguous, calculate the |
| 509 | * real number of pages we have in this system | 523 | * real number of pages we have in this system |
| @@ -521,9 +535,10 @@ void __init mem_init(void) | |||
| 521 | initsize = __init_end - __init_begin; | 535 | initsize = __init_end - __init_begin; |
| 522 | 536 | ||
| 523 | printk(KERN_NOTICE "Memory: %luKB available (%dK code, " | 537 | printk(KERN_NOTICE "Memory: %luKB available (%dK code, " |
| 524 | "%dK data, %dK init)\n", | 538 | "%dK data, %dK init, %luK highmem)\n", |
| 525 | (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), | 539 | (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), |
| 526 | codesize >> 10, datasize >> 10, initsize >> 10); | 540 | codesize >> 10, datasize >> 10, initsize >> 10, |
| 541 | (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); | ||
| 527 | 542 | ||
| 528 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { | 543 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { |
| 529 | extern int sysctl_overcommit_memory; | 544 | extern int sysctl_overcommit_memory; |
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 95bbe112965e..c4f6f05198e0 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h | |||
| @@ -1,7 +1,6 @@ | |||
| 1 | /* the upper-most page table pointer */ | ||
| 2 | |||
| 3 | #ifdef CONFIG_MMU | 1 | #ifdef CONFIG_MMU |
| 4 | 2 | ||
| 3 | /* the upper-most page table pointer */ | ||
| 5 | extern pmd_t *top_pmd; | 4 | extern pmd_t *top_pmd; |
| 6 | 5 | ||
| 7 | #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) | 6 | #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) |
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index d4d082c5c2d4..b438fc4fb77b 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
| @@ -18,9 +18,11 @@ | |||
| 18 | #include <asm/cputype.h> | 18 | #include <asm/cputype.h> |
| 19 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
| 20 | #include <asm/sections.h> | 20 | #include <asm/sections.h> |
| 21 | #include <asm/cachetype.h> | ||
| 21 | #include <asm/setup.h> | 22 | #include <asm/setup.h> |
| 22 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
| 23 | #include <asm/tlb.h> | 24 | #include <asm/tlb.h> |
| 25 | #include <asm/highmem.h> | ||
| 24 | 26 | ||
| 25 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| @@ -243,6 +245,10 @@ static struct mem_type mem_types[] = { | |||
| 243 | .prot_sect = PMD_TYPE_SECT, | 245 | .prot_sect = PMD_TYPE_SECT, |
| 244 | .domain = DOMAIN_KERNEL, | 246 | .domain = DOMAIN_KERNEL, |
| 245 | }, | 247 | }, |
| 248 | [MT_MEMORY_NONCACHED] = { | ||
| 249 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | ||
| 250 | .domain = DOMAIN_KERNEL, | ||
| 251 | }, | ||
| 246 | }; | 252 | }; |
| 247 | 253 | ||
| 248 | const struct mem_type *get_mem_type(unsigned int type) | 254 | const struct mem_type *get_mem_type(unsigned int type) |
| @@ -406,9 +412,28 @@ static void __init build_mem_type_table(void) | |||
| 406 | kern_pgprot |= L_PTE_SHARED; | 412 | kern_pgprot |= L_PTE_SHARED; |
| 407 | vecs_pgprot |= L_PTE_SHARED; | 413 | vecs_pgprot |= L_PTE_SHARED; |
| 408 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | 414 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
| 415 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | ||
| 409 | #endif | 416 | #endif |
| 410 | } | 417 | } |
| 411 | 418 | ||
| 419 | /* | ||
| 420 | * Non-cacheable Normal - intended for memory areas that must | ||
| 421 | * not cause dirty cache line writebacks when used | ||
| 422 | */ | ||
| 423 | if (cpu_arch >= CPU_ARCH_ARMv6) { | ||
| 424 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | ||
| 425 | /* Non-cacheable Normal is XCB = 001 */ | ||
| 426 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | ||
| 427 | PMD_SECT_BUFFERED; | ||
| 428 | } else { | ||
| 429 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | ||
| 430 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | ||
| 431 | PMD_SECT_TEX(1); | ||
| 432 | } | ||
| 433 | } else { | ||
| 434 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | ||
| 435 | } | ||
| 436 | |||
| 412 | for (i = 0; i < 16; i++) { | 437 | for (i = 0; i < 16; i++) { |
| 413 | unsigned long v = pgprot_val(protection_map[i]); | 438 | unsigned long v = pgprot_val(protection_map[i]); |
| 414 | protection_map[i] = __pgprot(v | user_pgprot); | 439 | protection_map[i] = __pgprot(v | user_pgprot); |
| @@ -677,6 +702,10 @@ static void __init sanity_check_meminfo(void) | |||
| 677 | if (meminfo.nr_banks >= NR_BANKS) { | 702 | if (meminfo.nr_banks >= NR_BANKS) { |
| 678 | printk(KERN_CRIT "NR_BANKS too low, " | 703 | printk(KERN_CRIT "NR_BANKS too low, " |
| 679 | "ignoring high memory\n"); | 704 | "ignoring high memory\n"); |
| 705 | } else if (cache_is_vipt_aliasing()) { | ||
| 706 | printk(KERN_CRIT "HIGHMEM is not yet supported " | ||
| 707 | "with VIPT aliasing cache, " | ||
| 708 | "ignoring high memory\n"); | ||
| 680 | } else { | 709 | } else { |
| 681 | memmove(bank + 1, bank, | 710 | memmove(bank + 1, bank, |
| 682 | (meminfo.nr_banks - i) * sizeof(*bank)); | 711 | (meminfo.nr_banks - i) * sizeof(*bank)); |
| @@ -694,7 +723,7 @@ static void __init sanity_check_meminfo(void) | |||
| 694 | * the vmalloc area. | 723 | * the vmalloc area. |
| 695 | */ | 724 | */ |
| 696 | if (__va(bank->start) >= VMALLOC_MIN || | 725 | if (__va(bank->start) >= VMALLOC_MIN || |
| 697 | __va(bank->start) < PAGE_OFFSET) { | 726 | __va(bank->start) < (void *)PAGE_OFFSET) { |
| 698 | printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " | 727 | printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " |
| 699 | "(vmalloc region overlap).\n", | 728 | "(vmalloc region overlap).\n", |
| 700 | bank->start, bank->start + bank->size - 1); | 729 | bank->start, bank->start + bank->size - 1); |
| @@ -895,6 +924,17 @@ static void __init devicemaps_init(struct machine_desc *mdesc) | |||
| 895 | flush_cache_all(); | 924 | flush_cache_all(); |
| 896 | } | 925 | } |
| 897 | 926 | ||
| 927 | static void __init kmap_init(void) | ||
| 928 | { | ||
| 929 | #ifdef CONFIG_HIGHMEM | ||
| 930 | pmd_t *pmd = pmd_off_k(PKMAP_BASE); | ||
| 931 | pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); | ||
| 932 | BUG_ON(!pmd_none(*pmd) || !pte); | ||
| 933 | __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE); | ||
| 934 | pkmap_page_table = pte + PTRS_PER_PTE; | ||
| 935 | #endif | ||
| 936 | } | ||
| 937 | |||
| 898 | /* | 938 | /* |
| 899 | * paging_init() sets up the page tables, initialises the zone memory | 939 | * paging_init() sets up the page tables, initialises the zone memory |
| 900 | * maps, and sets up the zero page, bad page and bad page tables. | 940 | * maps, and sets up the zero page, bad page and bad page tables. |
| @@ -908,6 +948,7 @@ void __init paging_init(struct machine_desc *mdesc) | |||
| 908 | prepare_page_table(); | 948 | prepare_page_table(); |
| 909 | bootmem_init(); | 949 | bootmem_init(); |
| 910 | devicemaps_init(mdesc); | 950 | devicemaps_init(mdesc); |
| 951 | kmap_init(); | ||
| 911 | 952 | ||
| 912 | top_pmd = pmd_off_k(0xffff0000); | 953 | top_pmd = pmd_off_k(0xffff0000); |
| 913 | 954 | ||
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S new file mode 100644 index 000000000000..08b8a955d5d7 --- /dev/null +++ b/arch/arm/mm/proc-fa526.S | |||
| @@ -0,0 +1,248 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526 | ||
| 3 | * | ||
| 4 | * Written by : Luke Lee | ||
| 5 | * Copyright (C) 2005 Faraday Corp. | ||
| 6 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * | ||
| 14 | * These are the low level assembler for performing cache and TLB | ||
| 15 | * functions on the fa526. | ||
| 16 | */ | ||
| 17 | #include <linux/linkage.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <asm/assembler.h> | ||
| 20 | #include <asm/hwcap.h> | ||
| 21 | #include <asm/pgtable-hwdef.h> | ||
| 22 | #include <asm/pgtable.h> | ||
| 23 | #include <asm/page.h> | ||
| 24 | #include <asm/ptrace.h> | ||
| 25 | #include <asm/system.h> | ||
| 26 | |||
| 27 | #include "proc-macros.S" | ||
| 28 | |||
| 29 | #define CACHE_DLINESIZE 16 | ||
| 30 | |||
| 31 | .text | ||
| 32 | /* | ||
| 33 | * cpu_fa526_proc_init() | ||
| 34 | */ | ||
| 35 | ENTRY(cpu_fa526_proc_init) | ||
| 36 | mov pc, lr | ||
| 37 | |||
| 38 | /* | ||
| 39 | * cpu_fa526_proc_fin() | ||
| 40 | */ | ||
| 41 | ENTRY(cpu_fa526_proc_fin) | ||
| 42 | stmfd sp!, {lr} | ||
| 43 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | ||
| 44 | msr cpsr_c, ip | ||
| 45 | bl fa_flush_kern_cache_all | ||
| 46 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | ||
| 47 | bic r0, r0, #0x1000 @ ...i............ | ||
| 48 | bic r0, r0, #0x000e @ ............wca. | ||
| 49 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | ||
| 50 | nop | ||
| 51 | nop | ||
| 52 | ldmfd sp!, {pc} | ||
| 53 | |||
| 54 | /* | ||
| 55 | * cpu_fa526_reset(loc) | ||
| 56 | * | ||
| 57 | * Perform a soft reset of the system. Put the CPU into the | ||
| 58 | * same state as it would be if it had been reset, and branch | ||
| 59 | * to what would be the reset vector. | ||
| 60 | * | ||
| 61 | * loc: location to jump to for soft reset | ||
| 62 | */ | ||
| 63 | .align 4 | ||
| 64 | ENTRY(cpu_fa526_reset) | ||
| 65 | /* TODO: Use CP8 if possible... */ | ||
| 66 | mov ip, #0 | ||
| 67 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | ||
| 68 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | ||
| 69 | #ifdef CONFIG_MMU | ||
| 70 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | ||
| 71 | #endif | ||
| 72 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | ||
| 73 | bic ip, ip, #0x000f @ ............wcam | ||
| 74 | bic ip, ip, #0x1100 @ ...i...s........ | ||
| 75 | bic ip, ip, #0x0800 @ BTB off | ||
| 76 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | ||
| 77 | nop | ||
| 78 | nop | ||
| 79 | mov pc, r0 | ||
| 80 | |||
| 81 | /* | ||
| 82 | * cpu_fa526_do_idle() | ||
| 83 | */ | ||
| 84 | .align 4 | ||
| 85 | ENTRY(cpu_fa526_do_idle) | ||
| 86 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | ||
| 87 | mov pc, lr | ||
| 88 | |||
| 89 | |||
| 90 | ENTRY(cpu_fa526_dcache_clean_area) | ||
| 91 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 92 | add r0, r0, #CACHE_DLINESIZE | ||
| 93 | subs r1, r1, #CACHE_DLINESIZE | ||
| 94 | bhi 1b | ||
| 95 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 96 | mov pc, lr | ||
| 97 | |||
| 98 | /* =============================== PageTable ============================== */ | ||
| 99 | |||
| 100 | /* | ||
| 101 | * cpu_fa526_switch_mm(pgd) | ||
| 102 | * | ||
| 103 | * Set the translation base pointer to be as described by pgd. | ||
| 104 | * | ||
| 105 | * pgd: new page tables | ||
| 106 | */ | ||
| 107 | .align 4 | ||
| 108 | ENTRY(cpu_fa526_switch_mm) | ||
| 109 | #ifdef CONFIG_MMU | ||
| 110 | mov ip, #0 | ||
| 111 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | ||
| 112 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | ||
| 113 | #else | ||
| 114 | mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache | ||
| 115 | #endif | ||
| 116 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | ||
| 117 | mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed | ||
| 118 | mcr p15, 0, ip, c7, c10, 4 @ data write barrier | ||
| 119 | mcr p15, 0, ip, c7, c5, 4 @ prefetch flush | ||
| 120 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | ||
| 121 | mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB | ||
| 122 | #endif | ||
| 123 | mov pc, lr | ||
| 124 | |||
| 125 | /* | ||
| 126 | * cpu_fa526_set_pte_ext(ptep, pte, ext) | ||
| 127 | * | ||
| 128 | * Set a PTE and flush it out | ||
| 129 | */ | ||
| 130 | .align 4 | ||
| 131 | ENTRY(cpu_fa526_set_pte_ext) | ||
| 132 | #ifdef CONFIG_MMU | ||
| 133 | armv3_set_pte_ext | ||
| 134 | mov r0, r0 | ||
| 135 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 136 | mov r0, #0 | ||
| 137 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 138 | #endif | ||
| 139 | mov pc, lr | ||
| 140 | |||
| 141 | __INIT | ||
| 142 | |||
| 143 | .type __fa526_setup, #function | ||
| 144 | __fa526_setup: | ||
| 145 | /* On return of this routine, r0 must carry correct flags for CFG register */ | ||
| 146 | mov r0, #0 | ||
| 147 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | ||
| 148 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | ||
| 149 | #ifdef CONFIG_MMU | ||
| 150 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 | ||
| 151 | #endif | ||
| 152 | mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM | ||
| 153 | |||
| 154 | mov r0, #1 | ||
| 155 | mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR | ||
| 156 | |||
| 157 | mov r0, #0 | ||
| 158 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All | ||
| 159 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | ||
| 160 | mcr p15, 0, r0, c7, c5, 4 @ prefetch flush | ||
| 161 | |||
| 162 | mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client | ||
| 163 | mcr p15, 0, r0, c3, c0 @ load domain access register | ||
| 164 | |||
| 165 | mrc p15, 0, r0, c1, c0 @ get control register v4 | ||
| 166 | ldr r5, fa526_cr1_clear | ||
| 167 | bic r0, r0, r5 | ||
| 168 | ldr r5, fa526_cr1_set | ||
| 169 | orr r0, r0, r5 | ||
| 170 | mov pc, lr | ||
| 171 | .size __fa526_setup, . - __fa526_setup | ||
| 172 | |||
| 173 | /* | ||
| 174 | * .RVI ZFRS BLDP WCAM | ||
| 175 | * ..11 1001 .111 1101 | ||
| 176 | * | ||
| 177 | */ | ||
| 178 | .type fa526_cr1_clear, #object | ||
| 179 | .type fa526_cr1_set, #object | ||
| 180 | fa526_cr1_clear: | ||
| 181 | .word 0x3f3f | ||
| 182 | fa526_cr1_set: | ||
| 183 | .word 0x397D | ||
| 184 | |||
| 185 | __INITDATA | ||
| 186 | |||
| 187 | /* | ||
| 188 | * Purpose : Function pointers used to access above functions - all calls | ||
| 189 | * come through these | ||
| 190 | */ | ||
| 191 | .type fa526_processor_functions, #object | ||
| 192 | fa526_processor_functions: | ||
| 193 | .word v4_early_abort | ||
| 194 | .word pabort_noifar | ||
| 195 | .word cpu_fa526_proc_init | ||
| 196 | .word cpu_fa526_proc_fin | ||
| 197 | .word cpu_fa526_reset | ||
| 198 | .word cpu_fa526_do_idle | ||
| 199 | .word cpu_fa526_dcache_clean_area | ||
| 200 | .word cpu_fa526_switch_mm | ||
| 201 | .word cpu_fa526_set_pte_ext | ||
| 202 | .size fa526_processor_functions, . - fa526_processor_functions | ||
| 203 | |||
| 204 | .section ".rodata" | ||
| 205 | |||
| 206 | .type cpu_arch_name, #object | ||
| 207 | cpu_arch_name: | ||
| 208 | .asciz "armv4" | ||
| 209 | .size cpu_arch_name, . - cpu_arch_name | ||
| 210 | |||
| 211 | .type cpu_elf_name, #object | ||
| 212 | cpu_elf_name: | ||
| 213 | .asciz "v4" | ||
| 214 | .size cpu_elf_name, . - cpu_elf_name | ||
| 215 | |||
| 216 | .type cpu_fa526_name, #object | ||
| 217 | cpu_fa526_name: | ||
| 218 | .asciz "FA526" | ||
| 219 | .size cpu_fa526_name, . - cpu_fa526_name | ||
| 220 | |||
| 221 | .align | ||
| 222 | |||
| 223 | .section ".proc.info.init", #alloc, #execinstr | ||
| 224 | |||
| 225 | .type __fa526_proc_info,#object | ||
| 226 | __fa526_proc_info: | ||
| 227 | .long 0x66015261 | ||
| 228 | .long 0xff01fff1 | ||
| 229 | .long PMD_TYPE_SECT | \ | ||
| 230 | PMD_SECT_BUFFERABLE | \ | ||
| 231 | PMD_SECT_CACHEABLE | \ | ||
| 232 | PMD_BIT4 | \ | ||
| 233 | PMD_SECT_AP_WRITE | \ | ||
| 234 | PMD_SECT_AP_READ | ||
| 235 | .long PMD_TYPE_SECT | \ | ||
| 236 | PMD_BIT4 | \ | ||
| 237 | PMD_SECT_AP_WRITE | \ | ||
| 238 | PMD_SECT_AP_READ | ||
| 239 | b __fa526_setup | ||
| 240 | .long cpu_arch_name | ||
| 241 | .long cpu_elf_name | ||
| 242 | .long HWCAP_SWP | HWCAP_HALF | ||
| 243 | .long cpu_fa526_name | ||
| 244 | .long fa526_processor_functions | ||
| 245 | .long fa_tlb_fns | ||
| 246 | .long fa_user_fns | ||
| 247 | .long fa_cache_fns | ||
| 248 | .size __fa526_proc_info, . - __fa526_proc_info | ||
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S new file mode 100644 index 000000000000..540f5078496b --- /dev/null +++ b/arch/arm/mm/proc-mohawk.S | |||
| @@ -0,0 +1,416 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core | ||
| 3 | * | ||
| 4 | * PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core. | ||
| 5 | * | ||
| 6 | * Heavily based on proc-arm926.S and proc-xsc3.S | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/linkage.h> | ||
| 24 | #include <linux/init.h> | ||
| 25 | #include <asm/assembler.h> | ||
| 26 | #include <asm/hwcap.h> | ||
| 27 | #include <asm/pgtable-hwdef.h> | ||
| 28 | #include <asm/pgtable.h> | ||
| 29 | #include <asm/page.h> | ||
| 30 | #include <asm/ptrace.h> | ||
| 31 | #include "proc-macros.S" | ||
| 32 | |||
| 33 | /* | ||
| 34 | * This is the maximum size of an area which will be flushed. If the | ||
| 35 | * area is larger than this, then we flush the whole cache. | ||
| 36 | */ | ||
| 37 | #define CACHE_DLIMIT 32768 | ||
| 38 | |||
| 39 | /* | ||
| 40 | * The cache line size of the L1 D cache. | ||
| 41 | */ | ||
| 42 | #define CACHE_DLINESIZE 32 | ||
| 43 | |||
| 44 | /* | ||
| 45 | * cpu_mohawk_proc_init() | ||
| 46 | */ | ||
| 47 | ENTRY(cpu_mohawk_proc_init) | ||
| 48 | mov pc, lr | ||
| 49 | |||
| 50 | /* | ||
| 51 | * cpu_mohawk_proc_fin() | ||
| 52 | */ | ||
| 53 | ENTRY(cpu_mohawk_proc_fin) | ||
| 54 | stmfd sp!, {lr} | ||
| 55 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | ||
| 56 | msr cpsr_c, ip | ||
| 57 | bl mohawk_flush_kern_cache_all | ||
| 58 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | ||
| 59 | bic r0, r0, #0x1800 @ ...iz........... | ||
| 60 | bic r0, r0, #0x0006 @ .............ca. | ||
| 61 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | ||
| 62 | ldmfd sp!, {pc} | ||
| 63 | |||
| 64 | /* | ||
| 65 | * cpu_mohawk_reset(loc) | ||
| 66 | * | ||
| 67 | * Perform a soft reset of the system. Put the CPU into the | ||
| 68 | * same state as it would be if it had been reset, and branch | ||
| 69 | * to what would be the reset vector. | ||
| 70 | * | ||
| 71 | * loc: location to jump to for soft reset | ||
| 72 | * | ||
| 73 | * (same as arm926) | ||
| 74 | */ | ||
| 75 | .align 5 | ||
| 76 | ENTRY(cpu_mohawk_reset) | ||
| 77 | mov ip, #0 | ||
| 78 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | ||
| 79 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | ||
| 80 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | ||
| 81 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | ||
| 82 | bic ip, ip, #0x0007 @ .............cam | ||
| 83 | bic ip, ip, #0x1100 @ ...i...s........ | ||
| 84 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | ||
| 85 | mov pc, r0 | ||
| 86 | |||
| 87 | /* | ||
| 88 | * cpu_mohawk_do_idle() | ||
| 89 | * | ||
| 90 | * Called with IRQs disabled | ||
| 91 | */ | ||
| 92 | .align 5 | ||
| 93 | ENTRY(cpu_mohawk_do_idle) | ||
| 94 | mov r0, #0 | ||
| 95 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 96 | mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt | ||
| 97 | mov pc, lr | ||
| 98 | |||
| 99 | /* | ||
| 100 | * flush_user_cache_all() | ||
| 101 | * | ||
| 102 | * Clean and invalidate all cache entries in a particular | ||
| 103 | * address space. | ||
| 104 | */ | ||
| 105 | ENTRY(mohawk_flush_user_cache_all) | ||
| 106 | /* FALLTHROUGH */ | ||
| 107 | |||
| 108 | /* | ||
| 109 | * flush_kern_cache_all() | ||
| 110 | * | ||
| 111 | * Clean and invalidate the entire cache. | ||
| 112 | */ | ||
| 113 | ENTRY(mohawk_flush_kern_cache_all) | ||
| 114 | mov r2, #VM_EXEC | ||
| 115 | mov ip, #0 | ||
| 116 | __flush_whole_cache: | ||
| 117 | mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache | ||
| 118 | tst r2, #VM_EXEC | ||
| 119 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | ||
| 120 | mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer | ||
| 121 | mov pc, lr | ||
| 122 | |||
| 123 | /* | ||
| 124 | * flush_user_cache_range(start, end, flags) | ||
| 125 | * | ||
| 126 | * Clean and invalidate a range of cache entries in the | ||
| 127 | * specified address range. | ||
| 128 | * | ||
| 129 | * - start - start address (inclusive) | ||
| 130 | * - end - end address (exclusive) | ||
| 131 | * - flags - vm_flags describing address space | ||
| 132 | * | ||
| 133 | * (same as arm926) | ||
| 134 | */ | ||
| 135 | ENTRY(mohawk_flush_user_cache_range) | ||
| 136 | mov ip, #0 | ||
| 137 | sub r3, r1, r0 @ calculate total size | ||
| 138 | cmp r3, #CACHE_DLIMIT | ||
| 139 | bgt __flush_whole_cache | ||
| 140 | 1: tst r2, #VM_EXEC | ||
| 141 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | ||
| 142 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 143 | add r0, r0, #CACHE_DLINESIZE | ||
| 144 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | ||
| 145 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 146 | add r0, r0, #CACHE_DLINESIZE | ||
| 147 | cmp r0, r1 | ||
| 148 | blo 1b | ||
| 149 | tst r2, #VM_EXEC | ||
| 150 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | ||
| 151 | mov pc, lr | ||
| 152 | |||
| 153 | /* | ||
| 154 | * coherent_kern_range(start, end) | ||
| 155 | * | ||
| 156 | * Ensure coherency between the Icache and the Dcache in the | ||
| 157 | * region described by start, end. If you have non-snooping | ||
| 158 | * Harvard caches, you need to implement this function. | ||
| 159 | * | ||
| 160 | * - start - virtual start address | ||
| 161 | * - end - virtual end address | ||
| 162 | */ | ||
| 163 | ENTRY(mohawk_coherent_kern_range) | ||
| 164 | /* FALLTHROUGH */ | ||
| 165 | |||
| 166 | /* | ||
| 167 | * coherent_user_range(start, end) | ||
| 168 | * | ||
| 169 | * Ensure coherency between the Icache and the Dcache in the | ||
| 170 | * region described by start, end. If you have non-snooping | ||
| 171 | * Harvard caches, you need to implement this function. | ||
| 172 | * | ||
| 173 | * - start - virtual start address | ||
| 174 | * - end - virtual end address | ||
| 175 | * | ||
| 176 | * (same as arm926) | ||
| 177 | */ | ||
| 178 | ENTRY(mohawk_coherent_user_range) | ||
| 179 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 180 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 181 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 182 | add r0, r0, #CACHE_DLINESIZE | ||
| 183 | cmp r0, r1 | ||
| 184 | blo 1b | ||
| 185 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 186 | mov pc, lr | ||
| 187 | |||
| 188 | /* | ||
| 189 | * flush_kern_dcache_page(void *page) | ||
| 190 | * | ||
| 191 | * Ensure no D cache aliasing occurs, either with itself or | ||
| 192 | * the I cache | ||
| 193 | * | ||
| 194 | * - addr - page aligned address | ||
| 195 | */ | ||
| 196 | ENTRY(mohawk_flush_kern_dcache_page) | ||
| 197 | add r1, r0, #PAGE_SZ | ||
| 198 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | ||
| 199 | add r0, r0, #CACHE_DLINESIZE | ||
| 200 | cmp r0, r1 | ||
| 201 | blo 1b | ||
| 202 | mov r0, #0 | ||
| 203 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | ||
| 204 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 205 | mov pc, lr | ||
| 206 | |||
| 207 | /* | ||
| 208 | * dma_inv_range(start, end) | ||
| 209 | * | ||
| 210 | * Invalidate (discard) the specified virtual address range. | ||
| 211 | * May not write back any entries. If 'start' or 'end' | ||
| 212 | * are not cache line aligned, those lines must be written | ||
| 213 | * back. | ||
| 214 | * | ||
| 215 | * - start - virtual start address | ||
| 216 | * - end - virtual end address | ||
| 217 | * | ||
| 218 | * (same as v4wb) | ||
| 219 | */ | ||
| 220 | ENTRY(mohawk_dma_inv_range) | ||
| 221 | tst r0, #CACHE_DLINESIZE - 1 | ||
| 222 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 223 | tst r1, #CACHE_DLINESIZE - 1 | ||
| 224 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | ||
| 225 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 226 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | ||
| 227 | add r0, r0, #CACHE_DLINESIZE | ||
| 228 | cmp r0, r1 | ||
| 229 | blo 1b | ||
| 230 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 231 | mov pc, lr | ||
| 232 | |||
| 233 | /* | ||
| 234 | * dma_clean_range(start, end) | ||
| 235 | * | ||
| 236 | * Clean the specified virtual address range. | ||
| 237 | * | ||
| 238 | * - start - virtual start address | ||
| 239 | * - end - virtual end address | ||
| 240 | * | ||
| 241 | * (same as v4wb) | ||
| 242 | */ | ||
| 243 | ENTRY(mohawk_dma_clean_range) | ||
| 244 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 245 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 246 | add r0, r0, #CACHE_DLINESIZE | ||
| 247 | cmp r0, r1 | ||
| 248 | blo 1b | ||
| 249 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 250 | mov pc, lr | ||
| 251 | |||
| 252 | /* | ||
| 253 | * dma_flush_range(start, end) | ||
| 254 | * | ||
| 255 | * Clean and invalidate the specified virtual address range. | ||
| 256 | * | ||
| 257 | * - start - virtual start address | ||
| 258 | * - end - virtual end address | ||
| 259 | */ | ||
| 260 | ENTRY(mohawk_dma_flush_range) | ||
| 261 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 262 | 1: | ||
| 263 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | ||
| 264 | add r0, r0, #CACHE_DLINESIZE | ||
| 265 | cmp r0, r1 | ||
| 266 | blo 1b | ||
| 267 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 268 | mov pc, lr | ||
| 269 | |||
| 270 | ENTRY(mohawk_cache_fns) | ||
| 271 | .long mohawk_flush_kern_cache_all | ||
| 272 | .long mohawk_flush_user_cache_all | ||
| 273 | .long mohawk_flush_user_cache_range | ||
| 274 | .long mohawk_coherent_kern_range | ||
| 275 | .long mohawk_coherent_user_range | ||
| 276 | .long mohawk_flush_kern_dcache_page | ||
| 277 | .long mohawk_dma_inv_range | ||
| 278 | .long mohawk_dma_clean_range | ||
| 279 | .long mohawk_dma_flush_range | ||
| 280 | |||
| 281 | ENTRY(cpu_mohawk_dcache_clean_area) | ||
| 282 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 283 | add r0, r0, #CACHE_DLINESIZE | ||
| 284 | subs r1, r1, #CACHE_DLINESIZE | ||
| 285 | bhi 1b | ||
| 286 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 287 | mov pc, lr | ||
| 288 | |||
| 289 | /* | ||
| 290 | * cpu_mohawk_switch_mm(pgd) | ||
| 291 | * | ||
| 292 | * Set the translation base pointer to be as described by pgd. | ||
| 293 | * | ||
| 294 | * pgd: new page tables | ||
| 295 | */ | ||
| 296 | .align 5 | ||
| 297 | ENTRY(cpu_mohawk_switch_mm) | ||
| 298 | mov ip, #0 | ||
| 299 | mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache | ||
| 300 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | ||
| 301 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | ||
| 302 | orr r0, r0, #0x18 @ cache the page table in L2 | ||
| 303 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | ||
| 304 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | ||
| 305 | mov pc, lr | ||
| 306 | |||
| 307 | /* | ||
| 308 | * cpu_mohawk_set_pte_ext(ptep, pte, ext) | ||
| 309 | * | ||
| 310 | * Set a PTE and flush it out | ||
| 311 | */ | ||
| 312 | .align 5 | ||
| 313 | ENTRY(cpu_mohawk_set_pte_ext) | ||
| 314 | armv3_set_pte_ext | ||
| 315 | mov r0, r0 | ||
| 316 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 317 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 318 | mov pc, lr | ||
| 319 | |||
| 320 | __INIT | ||
| 321 | |||
| 322 | .type __mohawk_setup, #function | ||
| 323 | __mohawk_setup: | ||
| 324 | mov r0, #0 | ||
| 325 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches | ||
| 326 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 327 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs | ||
| 328 | orr r4, r4, #0x18 @ cache the page table in L2 | ||
| 329 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer | ||
| 330 | |||
| 331 | mov r0, #0 @ don't allow CP access | ||
| 332 | mcr p15, 0, r0, c15, c1, 0 @ write CP access register | ||
| 333 | |||
| 334 | adr r5, mohawk_crval | ||
| 335 | ldmia r5, {r5, r6} | ||
| 336 | mrc p15, 0, r0, c1, c0 @ get control register | ||
| 337 | bic r0, r0, r5 | ||
| 338 | orr r0, r0, r6 | ||
| 339 | mov pc, lr | ||
| 340 | |||
| 341 | .size __mohawk_setup, . - __mohawk_setup | ||
| 342 | |||
| 343 | /* | ||
| 344 | * R | ||
| 345 | * .RVI ZFRS BLDP WCAM | ||
| 346 | * .011 1001 ..00 0101 | ||
| 347 | * | ||
| 348 | */ | ||
| 349 | .type mohawk_crval, #object | ||
| 350 | mohawk_crval: | ||
| 351 | crval clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134 | ||
| 352 | |||
| 353 | __INITDATA | ||
| 354 | |||
| 355 | /* | ||
| 356 | * Purpose : Function pointers used to access above functions - all calls | ||
| 357 | * come through these | ||
| 358 | */ | ||
| 359 | .type mohawk_processor_functions, #object | ||
| 360 | mohawk_processor_functions: | ||
| 361 | .word v5t_early_abort | ||
| 362 | .word pabort_noifar | ||
| 363 | .word cpu_mohawk_proc_init | ||
| 364 | .word cpu_mohawk_proc_fin | ||
| 365 | .word cpu_mohawk_reset | ||
| 366 | .word cpu_mohawk_do_idle | ||
| 367 | .word cpu_mohawk_dcache_clean_area | ||
| 368 | .word cpu_mohawk_switch_mm | ||
| 369 | .word cpu_mohawk_set_pte_ext | ||
| 370 | .size mohawk_processor_functions, . - mohawk_processor_functions | ||
| 371 | |||
| 372 | .section ".rodata" | ||
| 373 | |||
| 374 | .type cpu_arch_name, #object | ||
| 375 | cpu_arch_name: | ||
| 376 | .asciz "armv5te" | ||
| 377 | .size cpu_arch_name, . - cpu_arch_name | ||
| 378 | |||
| 379 | .type cpu_elf_name, #object | ||
| 380 | cpu_elf_name: | ||
| 381 | .asciz "v5" | ||
| 382 | .size cpu_elf_name, . - cpu_elf_name | ||
| 383 | |||
| 384 | .type cpu_mohawk_name, #object | ||
| 385 | cpu_mohawk_name: | ||
| 386 | .asciz "Marvell 88SV331x" | ||
| 387 | .size cpu_mohawk_name, . - cpu_mohawk_name | ||
| 388 | |||
| 389 | .align | ||
| 390 | |||
| 391 | .section ".proc.info.init", #alloc, #execinstr | ||
| 392 | |||
| 393 | .type __88sv331x_proc_info,#object | ||
| 394 | __88sv331x_proc_info: | ||
| 395 | .long 0x56158000 @ Marvell 88SV331x (MOHAWK) | ||
| 396 | .long 0xfffff000 | ||
| 397 | .long PMD_TYPE_SECT | \ | ||
| 398 | PMD_SECT_BUFFERABLE | \ | ||
| 399 | PMD_SECT_CACHEABLE | \ | ||
| 400 | PMD_BIT4 | \ | ||
| 401 | PMD_SECT_AP_WRITE | \ | ||
| 402 | PMD_SECT_AP_READ | ||
| 403 | .long PMD_TYPE_SECT | \ | ||
| 404 | PMD_BIT4 | \ | ||
| 405 | PMD_SECT_AP_WRITE | \ | ||
| 406 | PMD_SECT_AP_READ | ||
| 407 | b __mohawk_setup | ||
| 408 | .long cpu_arch_name | ||
| 409 | .long cpu_elf_name | ||
| 410 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | ||
| 411 | .long cpu_mohawk_name | ||
| 412 | .long mohawk_processor_functions | ||
| 413 | .long v4wbi_tlb_fns | ||
| 414 | .long v4wb_user_fns | ||
| 415 | .long mohawk_cache_fns | ||
| 416 | .size __88sv331x_proc_info, . - __88sv331x_proc_info | ||
diff --git a/arch/arm/mm/tlb-fa.S b/arch/arm/mm/tlb-fa.S new file mode 100644 index 000000000000..9694f1f6f485 --- /dev/null +++ b/arch/arm/mm/tlb-fa.S | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mm/tlb-fa.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Faraday Corp. | ||
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 6 | * | ||
| 7 | * Based on tlb-v4wbi.S: | ||
| 8 | * Copyright (C) 1997-2002 Russell King | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * ARM architecture version 4, Faraday variation. | ||
| 15 | * This assume an unified TLBs, with a write buffer, and branch target buffer (BTB) | ||
| 16 | * | ||
| 17 | * Processors: FA520 FA526 FA626 | ||
| 18 | */ | ||
| 19 | #include <linux/linkage.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <asm/asm-offsets.h> | ||
| 22 | #include <asm/tlbflush.h> | ||
| 23 | #include "proc-macros.S" | ||
| 24 | |||
| 25 | |||
| 26 | /* | ||
| 27 | * flush_user_tlb_range(start, end, mm) | ||
| 28 | * | ||
| 29 | * Invalidate a range of TLB entries in the specified address space. | ||
| 30 | * | ||
| 31 | * - start - range start address | ||
| 32 | * - end - range end address | ||
| 33 | * - mm - mm_struct describing address space | ||
| 34 | */ | ||
| 35 | .align 4 | ||
| 36 | ENTRY(fa_flush_user_tlb_range) | ||
| 37 | vma_vm_mm ip, r2 | ||
| 38 | act_mm r3 @ get current->active_mm | ||
| 39 | eors r3, ip, r3 @ == mm ? | ||
| 40 | movne pc, lr @ no, we dont do anything | ||
| 41 | mov r3, #0 | ||
| 42 | mcr p15, 0, r3, c7, c10, 4 @ drain WB | ||
| 43 | bic r0, r0, #0x0ff | ||
| 44 | bic r0, r0, #0xf00 | ||
| 45 | 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry | ||
| 46 | add r0, r0, #PAGE_SZ | ||
| 47 | cmp r0, r1 | ||
| 48 | blo 1b | ||
| 49 | mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB | ||
| 50 | mcr p15, 0, r3, c7, c10, 4 @ data write barrier | ||
| 51 | mov pc, lr | ||
| 52 | |||
| 53 | |||
| 54 | ENTRY(fa_flush_kern_tlb_range) | ||
| 55 | mov r3, #0 | ||
| 56 | mcr p15, 0, r3, c7, c10, 4 @ drain WB | ||
| 57 | bic r0, r0, #0x0ff | ||
| 58 | bic r0, r0, #0xf00 | ||
| 59 | 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry | ||
| 60 | add r0, r0, #PAGE_SZ | ||
| 61 | cmp r0, r1 | ||
| 62 | blo 1b | ||
| 63 | mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB | ||
| 64 | mcr p15, 0, r3, c7, c10, 4 @ data write barrier | ||
| 65 | mcr p15, 0, r3, c7, c5, 4 @ prefetch flush | ||
| 66 | mov pc, lr | ||
| 67 | |||
| 68 | __INITDATA | ||
| 69 | |||
| 70 | .type fa_tlb_fns, #object | ||
| 71 | ENTRY(fa_tlb_fns) | ||
| 72 | .long fa_flush_user_tlb_range | ||
| 73 | .long fa_flush_kern_tlb_range | ||
| 74 | .long fa_tlb_flags | ||
| 75 | .size fa_tlb_fns, . - fa_tlb_fns | ||
diff --git a/arch/arm/oprofile/backtrace.c b/arch/arm/oprofile/backtrace.c index cefc21c2eee4..d805a52b5032 100644 --- a/arch/arm/oprofile/backtrace.c +++ b/arch/arm/oprofile/backtrace.c | |||
| @@ -18,15 +18,14 @@ | |||
| 18 | #include <linux/mm.h> | 18 | #include <linux/mm.h> |
| 19 | #include <linux/uaccess.h> | 19 | #include <linux/uaccess.h> |
| 20 | #include <asm/ptrace.h> | 20 | #include <asm/ptrace.h> |
| 21 | 21 | #include <asm/stacktrace.h> | |
| 22 | #include "../kernel/stacktrace.h" | ||
| 23 | 22 | ||
| 24 | static int report_trace(struct stackframe *frame, void *d) | 23 | static int report_trace(struct stackframe *frame, void *d) |
| 25 | { | 24 | { |
| 26 | unsigned int *depth = d; | 25 | unsigned int *depth = d; |
| 27 | 26 | ||
| 28 | if (*depth) { | 27 | if (*depth) { |
| 29 | oprofile_add_trace(frame->lr); | 28 | oprofile_add_trace(frame->pc); |
| 30 | (*depth)--; | 29 | (*depth)--; |
| 31 | } | 30 | } |
| 32 | 31 | ||
| @@ -70,9 +69,12 @@ void arm_backtrace(struct pt_regs * const regs, unsigned int depth) | |||
| 70 | struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1; | 69 | struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1; |
| 71 | 70 | ||
| 72 | if (!user_mode(regs)) { | 71 | if (!user_mode(regs)) { |
| 73 | unsigned long base = ((unsigned long)regs) & ~(THREAD_SIZE - 1); | 72 | struct stackframe frame; |
| 74 | walk_stackframe(regs->ARM_fp, base, base + THREAD_SIZE, | 73 | frame.fp = regs->ARM_fp; |
| 75 | report_trace, &depth); | 74 | frame.sp = regs->ARM_sp; |
| 75 | frame.lr = regs->ARM_lr; | ||
| 76 | frame.pc = regs->ARM_pc; | ||
| 77 | walk_stackframe(&frame, report_trace, &depth); | ||
| 76 | return; | 78 | return; |
| 77 | } | 79 | } |
| 78 | 80 | ||
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 9cc2b16fdf79..17d0e9906d5f 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
| @@ -3,7 +3,7 @@ if ARCH_MXC | |||
| 3 | menu "Freescale MXC Implementations" | 3 | menu "Freescale MXC Implementations" |
| 4 | 4 | ||
| 5 | choice | 5 | choice |
| 6 | prompt "MXC/iMX Base Type" | 6 | prompt "Freescale CPU family:" |
| 7 | default ARCH_MX3 | 7 | default ARCH_MX3 |
| 8 | 8 | ||
| 9 | config ARCH_MX1 | 9 | config ARCH_MX1 |
| @@ -15,12 +15,14 @@ config ARCH_MX1 | |||
| 15 | config ARCH_MX2 | 15 | config ARCH_MX2 |
| 16 | bool "MX2-based" | 16 | bool "MX2-based" |
| 17 | select CPU_ARM926T | 17 | select CPU_ARM926T |
| 18 | select COMMON_CLKDEV | ||
| 18 | help | 19 | help |
| 19 | This enables support for systems based on the Freescale i.MX2 family | 20 | This enables support for systems based on the Freescale i.MX2 family |
| 20 | 21 | ||
| 21 | config ARCH_MX3 | 22 | config ARCH_MX3 |
| 22 | bool "MX3-based" | 23 | bool "MX3-based" |
| 23 | select CPU_V6 | 24 | select CPU_V6 |
| 25 | select COMMON_CLKDEV | ||
| 24 | help | 26 | help |
| 25 | This enables support for systems based on the Freescale i.MX3 family | 27 | This enables support for systems based on the Freescale i.MX3 family |
| 26 | 28 | ||
| @@ -43,4 +45,10 @@ config MXC_IRQ_PRIOR | |||
| 43 | requirements for timing. | 45 | requirements for timing. |
| 44 | Say N here, unless you have a specialized requirement. | 46 | Say N here, unless you have a specialized requirement. |
| 45 | 47 | ||
| 48 | config MXC_PWM | ||
| 49 | tristate "Enable PWM driver" | ||
| 50 | depends on ARCH_MXC | ||
| 51 | help | ||
| 52 | Enable support for the i.MX PWM controller(s). | ||
| 53 | |||
| 46 | endif | 54 | endif |
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index db74a929179d..055406312b69 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile | |||
| @@ -3,7 +3,8 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o clock.o gpio.o time.o devices.o | 6 | obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o |
| 7 | 7 | ||
| 8 | obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o | 8 | obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o |
| 9 | obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o | 9 | obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o |
| 10 | obj-$(CONFIG_MXC_PWM) += pwm.o | ||
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 0a38f0b396eb..92e13566cd4f 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c | |||
| @@ -48,6 +48,11 @@ static DEFINE_MUTEX(clocks_mutex); | |||
| 48 | *-------------------------------------------------------------------------*/ | 48 | *-------------------------------------------------------------------------*/ |
| 49 | 49 | ||
| 50 | /* | 50 | /* |
| 51 | * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all | ||
| 52 | * MXC architectures have switched to using clkdev. | ||
| 53 | */ | ||
| 54 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 55 | /* | ||
| 51 | * Retrieve a clock by name. | 56 | * Retrieve a clock by name. |
| 52 | * | 57 | * |
| 53 | * Note that we first try to use device id on the bus | 58 | * Note that we first try to use device id on the bus |
| @@ -110,6 +115,7 @@ found: | |||
| 110 | return clk; | 115 | return clk; |
| 111 | } | 116 | } |
| 112 | EXPORT_SYMBOL(clk_get); | 117 | EXPORT_SYMBOL(clk_get); |
| 118 | #endif | ||
| 113 | 119 | ||
| 114 | static void __clk_disable(struct clk *clk) | 120 | static void __clk_disable(struct clk *clk) |
| 115 | { | 121 | { |
| @@ -187,6 +193,7 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 187 | } | 193 | } |
| 188 | EXPORT_SYMBOL(clk_get_rate); | 194 | EXPORT_SYMBOL(clk_get_rate); |
| 189 | 195 | ||
| 196 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 190 | /* Decrement the clock's module reference count */ | 197 | /* Decrement the clock's module reference count */ |
| 191 | void clk_put(struct clk *clk) | 198 | void clk_put(struct clk *clk) |
| 192 | { | 199 | { |
| @@ -194,6 +201,7 @@ void clk_put(struct clk *clk) | |||
| 194 | module_put(clk->owner); | 201 | module_put(clk->owner); |
| 195 | } | 202 | } |
| 196 | EXPORT_SYMBOL(clk_put); | 203 | EXPORT_SYMBOL(clk_put); |
| 204 | #endif | ||
| 197 | 205 | ||
| 198 | /* Round the requested clock rate to the nearest supported | 206 | /* Round the requested clock rate to the nearest supported |
| 199 | * rate that is less than or equal to the requested rate. | 207 | * rate that is less than or equal to the requested rate. |
| @@ -257,6 +265,7 @@ struct clk *clk_get_parent(struct clk *clk) | |||
| 257 | } | 265 | } |
| 258 | EXPORT_SYMBOL(clk_get_parent); | 266 | EXPORT_SYMBOL(clk_get_parent); |
| 259 | 267 | ||
| 268 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 260 | /* | 269 | /* |
| 261 | * Add a new clock to the clock tree. | 270 | * Add a new clock to the clock tree. |
| 262 | */ | 271 | */ |
| @@ -327,4 +336,49 @@ static int __init mxc_setup_proc_entry(void) | |||
| 327 | } | 336 | } |
| 328 | 337 | ||
| 329 | late_initcall(mxc_setup_proc_entry); | 338 | late_initcall(mxc_setup_proc_entry); |
| 339 | #endif /* CONFIG_PROC_FS */ | ||
| 340 | #endif | ||
| 341 | |||
| 342 | /* | ||
| 343 | * Get the resulting clock rate from a PLL register value and the input | ||
| 344 | * frequency. PLLs with this register layout can at least be found on | ||
| 345 | * MX1, MX21, MX27 and MX31 | ||
| 346 | * | ||
| 347 | * mfi + mfn / (mfd + 1) | ||
| 348 | * f = 2 * f_ref * -------------------- | ||
| 349 | * pd + 1 | ||
| 350 | */ | ||
| 351 | unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) | ||
| 352 | { | ||
| 353 | long long ll; | ||
| 354 | int mfn_abs; | ||
| 355 | unsigned int mfi, mfn, mfd, pd; | ||
| 356 | |||
| 357 | mfi = (reg_val >> 10) & 0xf; | ||
| 358 | mfn = reg_val & 0x3ff; | ||
| 359 | mfd = (reg_val >> 16) & 0x3ff; | ||
| 360 | pd = (reg_val >> 26) & 0xf; | ||
| 361 | |||
| 362 | mfi = mfi <= 5 ? 5 : mfi; | ||
| 363 | |||
| 364 | mfn_abs = mfn; | ||
| 365 | |||
| 366 | #if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21 | ||
| 367 | if (mfn >= 0x200) { | ||
| 368 | mfn |= 0xFFFFFE00; | ||
| 369 | mfn_abs = -mfn; | ||
| 370 | } | ||
| 330 | #endif | 371 | #endif |
| 372 | |||
| 373 | freq *= 2; | ||
| 374 | freq /= pd + 1; | ||
| 375 | |||
| 376 | ll = (unsigned long long)freq * mfn_abs; | ||
| 377 | |||
| 378 | do_div(ll, mfd + 1); | ||
| 379 | if (mfn < 0) | ||
| 380 | ll = -ll; | ||
| 381 | ll = (freq * mfi) + ll; | ||
| 382 | |||
| 383 | return ll; | ||
| 384 | } | ||
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c new file mode 100644 index 000000000000..386e0d52cf58 --- /dev/null +++ b/arch/arm/plat-mxc/cpu.c | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | |||
| 2 | #include <linux/module.h> | ||
| 3 | |||
| 4 | unsigned int __mxc_cpu_type; | ||
| 5 | EXPORT_SYMBOL(__mxc_cpu_type); | ||
| 6 | |||
| 7 | void mxc_set_cpu_type(unsigned int type) | ||
| 8 | { | ||
| 9 | __mxc_cpu_type = type; | ||
| 10 | } | ||
| 11 | |||
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index c66748267c45..56f2fb5cc456 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
| 20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <mach/common.h> | ||
| 22 | 23 | ||
| 23 | int __init mxc_register_device(struct platform_device *pdev, void *data) | 24 | int __init mxc_register_device(struct platform_device *pdev, void *data) |
| 24 | { | 25 | { |
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c index 2905ec758758..e364a5ed10f1 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c | |||
| @@ -113,7 +113,7 @@ struct imx_dma_channel { | |||
| 113 | void (*err_handler) (int, void *, int errcode); | 113 | void (*err_handler) (int, void *, int errcode); |
| 114 | void (*prog_handler) (int, void *, struct scatterlist *); | 114 | void (*prog_handler) (int, void *, struct scatterlist *); |
| 115 | void *data; | 115 | void *data; |
| 116 | unsigned int dma_mode; | 116 | unsigned int dma_mode; |
| 117 | struct scatterlist *sg; | 117 | struct scatterlist *sg; |
| 118 | unsigned int resbytes; | 118 | unsigned int resbytes; |
| 119 | int dma_num; | 119 | int dma_num; |
| @@ -802,7 +802,7 @@ static int __init imx_dma_init(void) | |||
| 802 | int ret = 0; | 802 | int ret = 0; |
| 803 | int i; | 803 | int i; |
| 804 | 804 | ||
| 805 | dma_clk = clk_get(NULL, "dma_clk"); | 805 | dma_clk = clk_get(NULL, "dma"); |
| 806 | clk_enable(dma_clk); | 806 | clk_enable(dma_clk); |
| 807 | 807 | ||
| 808 | /* reset DMA module */ | 808 | /* reset DMA module */ |
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index ccbd94adc668..c6483bad8a26 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
| @@ -200,8 +200,8 @@ static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |||
| 200 | static int mxc_gpio_direction_output(struct gpio_chip *chip, | 200 | static int mxc_gpio_direction_output(struct gpio_chip *chip, |
| 201 | unsigned offset, int value) | 201 | unsigned offset, int value) |
| 202 | { | 202 | { |
| 203 | _set_gpio_direction(chip, offset, 1); | ||
| 204 | mxc_gpio_set(chip, offset, value); | 203 | mxc_gpio_set(chip, offset, value); |
| 204 | _set_gpio_direction(chip, offset, 1); | ||
| 205 | return 0; | 205 | return 0; |
| 206 | } | 206 | } |
| 207 | 207 | ||
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h index 8f34a05afc87..1cac9d1135cd 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h | |||
| @@ -48,7 +48,8 @@ | |||
| 48 | * Base address of PBC controller, CS4 | 48 | * Base address of PBC controller, CS4 |
| 49 | */ | 49 | */ |
| 50 | #define PBC_BASE_ADDRESS 0xEB000000 | 50 | #define PBC_BASE_ADDRESS 0xEB000000 |
| 51 | #define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset)) | 51 | #define PBC_REG_ADDR(offset) (void __force __iomem *) \ |
| 52 | (PBC_BASE_ADDRESS + (offset)) | ||
| 52 | 53 | ||
| 53 | /* | 54 | /* |
| 54 | * PBC Interupt name definitions | 55 | * PBC Interupt name definitions |
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 451d510d08c3..318c72ada13d 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h | |||
| @@ -11,6 +11,8 @@ | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 13 | 13 | ||
| 14 | #include <mach/hardware.h> | ||
| 15 | |||
| 14 | /* Base address of PBC controller */ | 16 | /* Base address of PBC controller */ |
| 15 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) | 17 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) |
| 16 | /* Offsets for the PBC Controller register */ | 18 | /* Offsets for the PBC Controller register */ |
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h new file mode 100644 index 000000000000..f8aef1babb75 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ | ||
| 20 | #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ | ||
| 21 | |||
| 22 | /* mandatory for CONFIG_LL_DEBUG */ | ||
| 23 | |||
| 24 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 25 | #define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) | ||
| 26 | |||
| 27 | #ifndef __ASSEMBLY__ | ||
| 28 | |||
| 29 | enum mx31moboard_boards { | ||
| 30 | MX31NOBOARD = 0, | ||
| 31 | MX31DEVBOARD = 1, | ||
| 32 | MX31MARXBOT = 2, | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | * This CPU module needs a baseboard to work. After basic initializing | ||
| 37 | * its own devices, it calls baseboard's init function. | ||
| 38 | */ | ||
| 39 | |||
| 40 | extern void mx31moboard_devboard_init(void); | ||
| 41 | extern void mx31moboard_marxbot_init(void); | ||
| 42 | |||
| 43 | #endif | ||
| 44 | |||
| 45 | #endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h new file mode 100644 index 000000000000..4ff762dd45cf --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-qong.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ | ||
| 12 | #define __ASM_ARCH_MXC_BOARD_QONG_H__ | ||
| 13 | |||
| 14 | /* mandatory for CONFIG_LL_DEBUG */ | ||
| 15 | |||
| 16 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 17 | #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 18 | |||
| 19 | /* NOR FLASH */ | ||
| 20 | #define QONG_NOR_SIZE (128*1024*1024) | ||
| 21 | |||
| 22 | #endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/clkdev.h b/arch/arm/plat-mxc/include/mach/clkdev.h new file mode 100644 index 000000000000..04b37a89801c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/clkdev.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #define __clk_get(clk) ({ 1; }) | ||
| 5 | #define __clk_put(clk) do { } while (0) | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index d21f78e78819..43a82d0c534d 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h | |||
| @@ -26,9 +26,13 @@ | |||
| 26 | struct module; | 26 | struct module; |
| 27 | 27 | ||
| 28 | struct clk { | 28 | struct clk { |
| 29 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 30 | /* As soon as i.MX1 and i.MX31 switched to clkdev, this | ||
| 31 | * block can go away */ | ||
| 29 | struct list_head node; | 32 | struct list_head node; |
| 30 | struct module *owner; | 33 | struct module *owner; |
| 31 | const char *name; | 34 | const char *name; |
| 35 | #endif | ||
| 32 | int id; | 36 | int id; |
| 33 | /* Source clock this clk depends on */ | 37 | /* Source clock this clk depends on */ |
| 34 | struct clk *parent; | 38 | struct clk *parent; |
| @@ -63,5 +67,7 @@ struct clk { | |||
| 63 | int clk_register(struct clk *clk); | 67 | int clk_register(struct clk *clk); |
| 64 | void clk_unregister(struct clk *clk); | 68 | void clk_unregister(struct clk *clk); |
| 65 | 69 | ||
| 70 | unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref); | ||
| 71 | |||
| 66 | #endif /* __ASSEMBLY__ */ | 72 | #endif /* __ASSEMBLY__ */ |
| 67 | #endif /* __ASM_ARCH_MXC_CLOCK_H__ */ | 73 | #endif /* __ASM_ARCH_MXC_CLOCK_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 6350287a59b9..b2f9b72644db 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h | |||
| @@ -12,12 +12,18 @@ | |||
| 12 | #define __ASM_ARCH_MXC_COMMON_H__ | 12 | #define __ASM_ARCH_MXC_COMMON_H__ |
| 13 | 13 | ||
| 14 | struct platform_device; | 14 | struct platform_device; |
| 15 | struct clk; | ||
| 15 | 16 | ||
| 16 | extern void mxc_map_io(void); | 17 | extern void mxc_map_io(void); |
| 17 | extern void mxc_init_irq(void); | 18 | extern void mxc_init_irq(void); |
| 18 | extern void mxc_timer_init(const char *clk_timer); | 19 | extern void mxc_timer_init(struct clk *timer_clk); |
| 19 | extern int mxc_clocks_init(unsigned long fref); | 20 | extern int mx1_clocks_init(unsigned long fref); |
| 21 | extern int mx21_clocks_init(unsigned long lref, unsigned long fref); | ||
| 22 | extern int mx27_clocks_init(unsigned long fref); | ||
| 23 | extern int mx31_clocks_init(unsigned long fref); | ||
| 24 | extern int mx35_clocks_init(void); | ||
| 20 | extern int mxc_register_gpios(void); | 25 | extern int mxc_register_gpios(void); |
| 21 | extern int mxc_register_device(struct platform_device *pdev, void *data); | 26 | extern int mxc_register_device(struct platform_device *pdev, void *data); |
| 27 | extern void mxc_set_cpu_type(unsigned int type); | ||
| 22 | 28 | ||
| 23 | #endif | 29 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 602768b427e2..4f773148bc20 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S | |||
| @@ -31,6 +31,9 @@ | |||
| 31 | #ifdef CONFIG_MACH_MX31_3DS | 31 | #ifdef CONFIG_MACH_MX31_3DS |
| 32 | #include <mach/board-mx31pdk.h> | 32 | #include <mach/board-mx31pdk.h> |
| 33 | #endif | 33 | #endif |
| 34 | #ifdef CONFIG_MACH_QONG | ||
| 35 | #include <mach/board-qong.h> | ||
| 36 | #endif | ||
| 34 | .macro addruart,rx | 37 | .macro addruart,rx |
| 35 | mrc p15, 0, \rx, c1, c0 | 38 | mrc p15, 0, \rx, c1, c0 |
| 36 | tst \rx, #1 @ MMU enabled? | 39 | tst \rx, #1 @ MMU enabled? |
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index a612d8bb73c8..42e4ee37ca1f 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h | |||
| @@ -23,10 +23,16 @@ | |||
| 23 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
| 24 | 24 | ||
| 25 | #ifdef CONFIG_ARCH_MX3 | 25 | #ifdef CONFIG_ARCH_MX3 |
| 26 | # include <mach/mx31.h> | 26 | #include <mach/mx3x.h> |
| 27 | #include <mach/mx31.h> | ||
| 28 | #include <mach/mx35.h> | ||
| 27 | #endif | 29 | #endif |
| 28 | 30 | ||
| 29 | #ifdef CONFIG_ARCH_MX2 | 31 | #ifdef CONFIG_ARCH_MX2 |
| 32 | # include <mach/mx2x.h> | ||
| 33 | # ifdef CONFIG_MACH_MX21 | ||
| 34 | # include <mach/mx21.h> | ||
| 35 | # endif | ||
| 30 | # ifdef CONFIG_MACH_MX27 | 36 | # ifdef CONFIG_MACH_MX27 |
| 31 | # include <mach/mx27.h> | 37 | # include <mach/mx27.h> |
| 32 | # endif | 38 | # endif |
diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 870d0d939616..762a7b0430e2 100644 --- a/arch/arm/mach-imx/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h | |||
| @@ -76,6 +76,9 @@ struct imx_fb_platform_data { | |||
| 76 | u_char * fixed_screen_cpu; | 76 | u_char * fixed_screen_cpu; |
| 77 | dma_addr_t fixed_screen_dma; | 77 | dma_addr_t fixed_screen_dma; |
| 78 | 78 | ||
| 79 | int (*init)(struct platform_device*); | ||
| 80 | int (*exit)(struct platform_device*); | ||
| 81 | |||
| 79 | void (*lcd_power)(int); | 82 | void (*lcd_power)(int); |
| 80 | void (*backlight_power)(int); | 83 | void (*backlight_power)(int); |
| 81 | }; | 84 | }; |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h deleted file mode 100644 index 95a383be628e..000000000000 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ /dev/null | |||
| @@ -1,416 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _MXC_GPIO_MX1_MX2_H | ||
| 20 | #define _MXC_GPIO_MX1_MX2_H | ||
| 21 | |||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * GPIO Module and I/O Multiplexer | ||
| 26 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
| 27 | */ | ||
| 28 | #define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR) | ||
| 29 | #define MXC_DDIR(x) (0x00 + ((x) << 8)) | ||
| 30 | #define MXC_OCR1(x) (0x04 + ((x) << 8)) | ||
| 31 | #define MXC_OCR2(x) (0x08 + ((x) << 8)) | ||
| 32 | #define MXC_ICONFA1(x) (0x0c + ((x) << 8)) | ||
| 33 | #define MXC_ICONFA2(x) (0x10 + ((x) << 8)) | ||
| 34 | #define MXC_ICONFB1(x) (0x14 + ((x) << 8)) | ||
| 35 | #define MXC_ICONFB2(x) (0x18 + ((x) << 8)) | ||
| 36 | #define MXC_DR(x) (0x1c + ((x) << 8)) | ||
| 37 | #define MXC_GIUS(x) (0x20 + ((x) << 8)) | ||
| 38 | #define MXC_SSR(x) (0x24 + ((x) << 8)) | ||
| 39 | #define MXC_ICR1(x) (0x28 + ((x) << 8)) | ||
| 40 | #define MXC_ICR2(x) (0x2c + ((x) << 8)) | ||
| 41 | #define MXC_IMR(x) (0x30 + ((x) << 8)) | ||
| 42 | #define MXC_ISR(x) (0x34 + ((x) << 8)) | ||
| 43 | #define MXC_GPR(x) (0x38 + ((x) << 8)) | ||
| 44 | #define MXC_SWR(x) (0x3c + ((x) << 8)) | ||
| 45 | #define MXC_PUEN(x) (0x40 + ((x) << 8)) | ||
| 46 | |||
| 47 | #ifdef CONFIG_ARCH_MX1 | ||
| 48 | # define GPIO_PORT_MAX 3 | ||
| 49 | #endif | ||
| 50 | #ifdef CONFIG_ARCH_MX2 | ||
| 51 | # define GPIO_PORT_MAX 5 | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #ifndef GPIO_PORT_MAX | ||
| 55 | # error "GPIO config port count unknown!" | ||
| 56 | #endif | ||
| 57 | |||
| 58 | #define GPIO_PIN_MASK 0x1f | ||
| 59 | |||
| 60 | #define GPIO_PORT_SHIFT 5 | ||
| 61 | #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) | ||
| 62 | |||
| 63 | #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) | ||
| 64 | #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) | ||
| 65 | #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) | ||
| 66 | #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) | ||
| 67 | #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) | ||
| 68 | #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) | ||
| 69 | |||
| 70 | #define GPIO_OUT (1 << 8) | ||
| 71 | #define GPIO_IN (0 << 8) | ||
| 72 | #define GPIO_PUEN (1 << 9) | ||
| 73 | |||
| 74 | #define GPIO_PF (1 << 10) | ||
| 75 | #define GPIO_AF (1 << 11) | ||
| 76 | |||
| 77 | #define GPIO_OCR_SHIFT 12 | ||
| 78 | #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) | ||
| 79 | #define GPIO_AIN (0 << GPIO_OCR_SHIFT) | ||
| 80 | #define GPIO_BIN (1 << GPIO_OCR_SHIFT) | ||
| 81 | #define GPIO_CIN (2 << GPIO_OCR_SHIFT) | ||
| 82 | #define GPIO_GPIO (3 << GPIO_OCR_SHIFT) | ||
| 83 | |||
| 84 | #define GPIO_AOUT_SHIFT 14 | ||
| 85 | #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) | ||
| 86 | #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) | ||
| 87 | #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) | ||
| 88 | #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) | ||
| 89 | #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) | ||
| 90 | |||
| 91 | #define GPIO_BOUT_SHIFT 16 | ||
| 92 | #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) | ||
| 93 | #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) | ||
| 94 | #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) | ||
| 95 | #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) | ||
| 96 | #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) | ||
| 97 | |||
| 98 | extern void mxc_gpio_mode(int gpio_mode); | ||
| 99 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
| 100 | const char *label); | ||
| 101 | extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); | ||
| 102 | |||
| 103 | /*-------------------------------------------------------------------------*/ | ||
| 104 | |||
| 105 | /* assignements for GPIO alternate/primary functions */ | ||
| 106 | |||
| 107 | /* FIXME: This list is not completed. The correct directions are | ||
| 108 | * missing on some (many) pins | ||
| 109 | */ | ||
| 110 | #ifdef CONFIG_ARCH_MX1 | ||
| 111 | #define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0) | ||
| 112 | #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) | ||
| 113 | #define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1) | ||
| 114 | #define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) | ||
| 115 | #define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2) | ||
| 116 | #define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) | ||
| 117 | #define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) | ||
| 118 | #define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) | ||
| 119 | #define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) | ||
| 120 | #define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) | ||
| 121 | #define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) | ||
| 122 | #define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) | ||
| 123 | #define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) | ||
| 124 | #define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) | ||
| 125 | #define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) | ||
| 126 | #define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) | ||
| 127 | #define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) | ||
| 128 | #define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) | ||
| 129 | #define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) | ||
| 130 | #define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) | ||
| 131 | #define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17) | ||
| 132 | #define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) | ||
| 133 | #define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) | ||
| 134 | #define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) | ||
| 135 | #define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) | ||
| 136 | #define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) | ||
| 137 | #define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) | ||
| 138 | #define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) | ||
| 139 | #define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) | ||
| 140 | #define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) | ||
| 141 | #define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) | ||
| 142 | #define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) | ||
| 143 | #define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) | ||
| 144 | #define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) | ||
| 145 | #define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) | ||
| 146 | #define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) | ||
| 147 | #define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) | ||
| 148 | #define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) | ||
| 149 | #define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) | ||
| 150 | #define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) | ||
| 151 | #define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) | ||
| 152 | #define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) | ||
| 153 | #define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) | ||
| 154 | #define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) | ||
| 155 | #define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) | ||
| 156 | #define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) | ||
| 157 | #define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) | ||
| 158 | #define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) | ||
| 159 | #define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) | ||
| 160 | #define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) | ||
| 161 | #define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) | ||
| 162 | #define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) | ||
| 163 | #define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) | ||
| 164 | #define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) | ||
| 165 | #define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) | ||
| 166 | #define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) | ||
| 167 | #define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) | ||
| 168 | #define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16) | ||
| 169 | #define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17) | ||
| 170 | #define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) | ||
| 171 | #define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) | ||
| 172 | #define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) | ||
| 173 | #define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) | ||
| 174 | #define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22) | ||
| 175 | #define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) | ||
| 176 | #define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) | ||
| 177 | #define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) | ||
| 178 | #define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) | ||
| 179 | #define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) | ||
| 180 | #define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28) | ||
| 181 | #define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29) | ||
| 182 | #define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30) | ||
| 183 | #define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31) | ||
| 184 | #define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) | ||
| 185 | #define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) | ||
| 186 | #define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) | ||
| 187 | #define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) | ||
| 188 | #define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) | ||
| 189 | #define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) | ||
| 190 | #define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) | ||
| 191 | #define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10) | ||
| 192 | #define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) | ||
| 193 | #define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12) | ||
| 194 | #define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) | ||
| 195 | #define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) | ||
| 196 | #define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) | ||
| 197 | #define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) | ||
| 198 | #define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) | ||
| 199 | #define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) | ||
| 200 | #define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) | ||
| 201 | #define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26) | ||
| 202 | #define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) | ||
| 203 | #define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) | ||
| 204 | #define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29) | ||
| 205 | #define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) | ||
| 206 | #define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31) | ||
| 207 | #define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6) | ||
| 208 | #define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) | ||
| 209 | #define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7) | ||
| 210 | #define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) | ||
| 211 | #define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) | ||
| 212 | #define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8) | ||
| 213 | #define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) | ||
| 214 | #define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) | ||
| 215 | #define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9) | ||
| 216 | #define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9) | ||
| 217 | #define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10) | ||
| 218 | #define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10) | ||
| 219 | #define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10) | ||
| 220 | #define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11) | ||
| 221 | #define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12) | ||
| 222 | #define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13) | ||
| 223 | #define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14) | ||
| 224 | #define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15) | ||
| 225 | #define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16) | ||
| 226 | #define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) | ||
| 227 | #define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) | ||
| 228 | #define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19) | ||
| 229 | #define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20) | ||
| 230 | #define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21) | ||
| 231 | #define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22) | ||
| 232 | #define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23) | ||
| 233 | #define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24) | ||
| 234 | #define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) | ||
| 235 | #define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) | ||
| 236 | #define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) | ||
| 237 | #define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) | ||
| 238 | #define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) | ||
| 239 | #define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30) | ||
| 240 | #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) | ||
| 241 | #define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) | ||
| 242 | #endif | ||
| 243 | |||
| 244 | #ifdef CONFIG_ARCH_MX2 | ||
| 245 | #define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) | ||
| 246 | #define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) | ||
| 247 | #define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) | ||
| 248 | #define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) | ||
| 249 | #define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) | ||
| 250 | #define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5) | ||
| 251 | #define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6) | ||
| 252 | #define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7) | ||
| 253 | #define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8) | ||
| 254 | #define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9) | ||
| 255 | #define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10) | ||
| 256 | #define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11) | ||
| 257 | #define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12) | ||
| 258 | #define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13) | ||
| 259 | #define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14) | ||
| 260 | #define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) | ||
| 261 | #define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) | ||
| 262 | #define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17) | ||
| 263 | #define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18) | ||
| 264 | #define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19) | ||
| 265 | #define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20) | ||
| 266 | #define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21) | ||
| 267 | #define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22) | ||
| 268 | #define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23) | ||
| 269 | #define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24) | ||
| 270 | #define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25) | ||
| 271 | #define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26) | ||
| 272 | #define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27) | ||
| 273 | #define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28) | ||
| 274 | #define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29) | ||
| 275 | #define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30) | ||
| 276 | #define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31) | ||
| 277 | #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) | ||
| 278 | #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) | ||
| 279 | #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) | ||
| 280 | #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) | ||
| 281 | #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) | ||
| 282 | #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) | ||
| 283 | #define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10) | ||
| 284 | #define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10) | ||
| 285 | #define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11) | ||
| 286 | #define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11) | ||
| 287 | #define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12) | ||
| 288 | #define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12) | ||
| 289 | #define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13) | ||
| 290 | #define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13) | ||
| 291 | #define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14) | ||
| 292 | #define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15) | ||
| 293 | #define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16) | ||
| 294 | #define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17) | ||
| 295 | #define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18) | ||
| 296 | #define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18) | ||
| 297 | #define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19) | ||
| 298 | #define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19) | ||
| 299 | #define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20) | ||
| 300 | #define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20) | ||
| 301 | #define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21) | ||
| 302 | #define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21) | ||
| 303 | #define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) | ||
| 304 | #define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) | ||
| 305 | #define PB24_PF_USB_OC_B (GPIO_PORTB | GPIO_PF | 24) | ||
| 306 | #define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) | ||
| 307 | #define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) | ||
| 308 | #define PB27_PF_USBH1_OE_B (GPIO_PORTB | GPIO_PF | 27) | ||
| 309 | #define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) | ||
| 310 | #define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) | ||
| 311 | #define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) | ||
| 312 | #define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) | ||
| 313 | #define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26) | ||
| 314 | #define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28) | ||
| 315 | #define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29) | ||
| 316 | #define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31) | ||
| 317 | #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) | ||
| 318 | #define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6) | ||
| 319 | #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) | ||
| 320 | #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) | ||
| 321 | #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) | ||
| 322 | #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) | ||
| 323 | #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) | ||
| 324 | #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) | ||
| 325 | #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) | ||
| 326 | #define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16) | ||
| 327 | #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17) | ||
| 328 | #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18) | ||
| 329 | #define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19) | ||
| 330 | #define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20) | ||
| 331 | #define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21) | ||
| 332 | #define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22) | ||
| 333 | #define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23) | ||
| 334 | #define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24) | ||
| 335 | #define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25) | ||
| 336 | #define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26) | ||
| 337 | #define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27) | ||
| 338 | #define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28) | ||
| 339 | #define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29) | ||
| 340 | #define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30) | ||
| 341 | #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31) | ||
| 342 | #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) | ||
| 343 | #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) | ||
| 344 | #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) | ||
| 345 | #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) | ||
| 346 | #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) | ||
| 347 | #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) | ||
| 348 | #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) | ||
| 349 | #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) | ||
| 350 | #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) | ||
| 351 | #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) | ||
| 352 | #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) | ||
| 353 | #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) | ||
| 354 | #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) | ||
| 355 | #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) | ||
| 356 | #define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) | ||
| 357 | #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) | ||
| 358 | #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) | ||
| 359 | #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) | ||
| 360 | #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) | ||
| 361 | #define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) | ||
| 362 | #define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) | ||
| 363 | #define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) | ||
| 364 | #define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) | ||
| 365 | #define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) | ||
| 366 | #define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) | ||
| 367 | #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) | ||
| 368 | #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) | ||
| 369 | #define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) | ||
| 370 | #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) | ||
| 371 | #define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) | ||
| 372 | #define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) | ||
| 373 | #define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) | ||
| 374 | #define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) | ||
| 375 | #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) | ||
| 376 | #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) | ||
| 377 | #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) | ||
| 378 | #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) | ||
| 379 | #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) | ||
| 380 | #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) | ||
| 381 | #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) | ||
| 382 | #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) | ||
| 383 | #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) | ||
| 384 | #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) | ||
| 385 | #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) | ||
| 386 | #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) | ||
| 387 | #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) | ||
| 388 | #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) | ||
| 389 | #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) | ||
| 390 | #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) | ||
| 391 | #define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16) | ||
| 392 | #define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16) | ||
| 393 | #define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18) | ||
| 394 | #define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18) | ||
| 395 | #define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19) | ||
| 396 | #define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20) | ||
| 397 | #define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21) | ||
| 398 | #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) | ||
| 399 | #define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22) | ||
| 400 | #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) | ||
| 401 | #define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23) | ||
| 402 | #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23) | ||
| 403 | #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) | ||
| 404 | #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) | ||
| 405 | #endif | ||
| 406 | |||
| 407 | /* decode irq number to use with IMR(x), ISR(x) and friends */ | ||
| 408 | #define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) | ||
| 409 | |||
| 410 | #define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) | ||
| 411 | #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) | ||
| 412 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | ||
| 413 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | ||
| 414 | #define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) | ||
| 415 | |||
| 416 | #endif /* _MXC_GPIO_MX1_MX2_H */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h new file mode 100644 index 000000000000..bf23305c19cc --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _MXC_IOMUX_MX1_H | ||
| 20 | #define _MXC_IOMUX_MX1_H | ||
| 21 | |||
| 22 | #ifndef GPIO_PORTA | ||
| 23 | #error Please include mach/iomux.h | ||
| 24 | #endif | ||
| 25 | |||
| 26 | /* FIXME: This list is not completed. The correct directions are | ||
| 27 | * missing on some (many) pins | ||
| 28 | */ | ||
| 29 | |||
| 30 | |||
| 31 | /* Primary GPIO pin functions */ | ||
| 32 | |||
| 33 | #define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) | ||
| 34 | #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) | ||
| 35 | #define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) | ||
| 36 | #define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) | ||
| 37 | #define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) | ||
| 38 | #define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) | ||
| 39 | #define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) | ||
| 40 | #define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) | ||
| 41 | #define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) | ||
| 42 | #define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) | ||
| 43 | #define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) | ||
| 44 | #define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) | ||
| 45 | #define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) | ||
| 46 | #define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) | ||
| 47 | #define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) | ||
| 48 | #define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) | ||
| 49 | #define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) | ||
| 50 | #define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) | ||
| 51 | #define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) | ||
| 52 | #define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) | ||
| 53 | #define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) | ||
| 54 | #define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) | ||
| 55 | #define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) | ||
| 56 | #define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) | ||
| 57 | #define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) | ||
| 58 | #define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) | ||
| 59 | #define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) | ||
| 60 | #define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) | ||
| 61 | #define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) | ||
| 62 | #define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) | ||
| 63 | #define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) | ||
| 64 | #define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) | ||
| 65 | #define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) | ||
| 66 | #define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) | ||
| 67 | #define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) | ||
| 68 | #define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) | ||
| 69 | #define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) | ||
| 70 | #define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) | ||
| 71 | #define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) | ||
| 72 | #define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) | ||
| 73 | #define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) | ||
| 74 | #define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) | ||
| 75 | #define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) | ||
| 76 | #define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) | ||
| 77 | #define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) | ||
| 78 | #define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) | ||
| 79 | #define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) | ||
| 80 | #define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) | ||
| 81 | #define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) | ||
| 82 | #define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) | ||
| 83 | #define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) | ||
| 84 | #define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) | ||
| 85 | #define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) | ||
| 86 | #define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) | ||
| 87 | #define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) | ||
| 88 | #define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) | ||
| 89 | #define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) | ||
| 90 | #define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) | ||
| 91 | #define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) | ||
| 92 | #define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) | ||
| 93 | #define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) | ||
| 94 | #define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) | ||
| 95 | #define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) | ||
| 96 | #define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) | ||
| 97 | #define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) | ||
| 98 | #define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) | ||
| 99 | #define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) | ||
| 100 | #define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) | ||
| 101 | #define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) | ||
| 102 | #define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) | ||
| 103 | #define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) | ||
| 104 | #define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) | ||
| 105 | #define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) | ||
| 106 | #define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) | ||
| 107 | #define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) | ||
| 108 | #define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) | ||
| 109 | #define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) | ||
| 110 | #define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) | ||
| 111 | #define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) | ||
| 112 | #define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) | ||
| 113 | #define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) | ||
| 114 | #define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) | ||
| 115 | #define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) | ||
| 116 | #define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) | ||
| 117 | #define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) | ||
| 118 | #define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) | ||
| 119 | #define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) | ||
| 120 | #define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) | ||
| 121 | #define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) | ||
| 122 | #define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) | ||
| 123 | #define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) | ||
| 124 | #define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) | ||
| 125 | #define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) | ||
| 126 | #define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) | ||
| 127 | #define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) | ||
| 128 | #define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) | ||
| 129 | #define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) | ||
| 130 | #define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) | ||
| 131 | #define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) | ||
| 132 | #define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) | ||
| 133 | #define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) | ||
| 134 | #define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) | ||
| 135 | #define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) | ||
| 136 | #define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) | ||
| 137 | #define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) | ||
| 138 | #define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) | ||
| 139 | #define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) | ||
| 140 | #define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) | ||
| 141 | #define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) | ||
| 142 | #define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) | ||
| 143 | #define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) | ||
| 144 | #define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) | ||
| 145 | #define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) | ||
| 146 | #define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) | ||
| 147 | #define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) | ||
| 148 | #define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) | ||
| 149 | #define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) | ||
| 150 | #define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) | ||
| 151 | #define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) | ||
| 152 | #define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) | ||
| 153 | #define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) | ||
| 154 | #define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) | ||
| 155 | #define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) | ||
| 156 | #define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) | ||
| 157 | #define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) | ||
| 158 | #define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) | ||
| 159 | #define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) | ||
| 160 | #define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) | ||
| 161 | #define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) | ||
| 162 | #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) | ||
| 163 | #define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) | ||
| 164 | |||
| 165 | |||
| 166 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h new file mode 100644 index 000000000000..63aaa972e275 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h | |||
| @@ -0,0 +1,126 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _MXC_IOMUX_MX21_H | ||
| 20 | #define _MXC_IOMUX_MX21_H | ||
| 21 | |||
| 22 | #ifndef GPIO_PORTA | ||
| 23 | #error Please include mach/iomux.h | ||
| 24 | #endif | ||
| 25 | |||
| 26 | |||
| 27 | /* Primary GPIO pin functions */ | ||
| 28 | |||
| 29 | #define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) | ||
| 30 | #define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) | ||
| 31 | #define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) | ||
| 32 | #define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) | ||
| 33 | #define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) | ||
| 34 | #define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) | ||
| 35 | #define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) | ||
| 36 | #define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) | ||
| 37 | #define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) | ||
| 38 | #define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) | ||
| 39 | #define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) | ||
| 40 | #define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) | ||
| 41 | #define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) | ||
| 42 | #define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) | ||
| 43 | #define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) | ||
| 44 | #define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) | ||
| 45 | #define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) | ||
| 46 | #define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) | ||
| 47 | #define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) | ||
| 48 | #define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) | ||
| 49 | #define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) | ||
| 50 | #define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) | ||
| 51 | #define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) | ||
| 52 | #define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) | ||
| 53 | #define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) | ||
| 54 | #define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) | ||
| 55 | #define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) | ||
| 56 | #define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) | ||
| 57 | #define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) | ||
| 58 | |||
| 59 | /* Alternate GPIO pin functions */ | ||
| 60 | |||
| 61 | #define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) | ||
| 62 | #define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) | ||
| 63 | #define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) | ||
| 64 | #define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) | ||
| 65 | #define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) | ||
| 66 | #define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) | ||
| 67 | #define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) | ||
| 68 | #define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) | ||
| 69 | #define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) | ||
| 70 | #define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) | ||
| 71 | #define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) | ||
| 72 | #define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) | ||
| 73 | #define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) | ||
| 74 | #define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) | ||
| 75 | #define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) | ||
| 76 | #define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) | ||
| 77 | #define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) | ||
| 78 | #define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) | ||
| 79 | #define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) | ||
| 80 | #define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) | ||
| 81 | #define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) | ||
| 82 | |||
| 83 | /* AIN GPIO pin functions */ | ||
| 84 | |||
| 85 | #define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) | ||
| 86 | #define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) | ||
| 87 | #define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) | ||
| 88 | #define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) | ||
| 89 | #define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) | ||
| 90 | #define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) | ||
| 91 | #define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) | ||
| 92 | #define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) | ||
| 93 | #define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) | ||
| 94 | #define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) | ||
| 95 | #define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) | ||
| 96 | #define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) | ||
| 97 | |||
| 98 | /* BIN GPIO pin functions */ | ||
| 99 | |||
| 100 | #define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) | ||
| 101 | #define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) | ||
| 102 | |||
| 103 | /* CIN GPIO pin functions */ | ||
| 104 | |||
| 105 | #define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) | ||
| 106 | |||
| 107 | /* AOUT GPIO pin functions */ | ||
| 108 | |||
| 109 | #define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) | ||
| 110 | #define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) | ||
| 111 | #define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) | ||
| 112 | #define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) | ||
| 113 | #define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) | ||
| 114 | #define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) | ||
| 115 | #define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) | ||
| 116 | #define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) | ||
| 117 | #define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) | ||
| 118 | #define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) | ||
| 119 | #define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) | ||
| 120 | #define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) | ||
| 121 | #define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) | ||
| 122 | #define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) | ||
| 123 | #define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) | ||
| 124 | |||
| 125 | |||
| 126 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h new file mode 100644 index 000000000000..5ac158b70f61 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h | |||
| @@ -0,0 +1,207 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _MXC_IOMUX_MX27_H | ||
| 21 | #define _MXC_IOMUX_MX27_H | ||
| 22 | |||
| 23 | #ifndef GPIO_PORTA | ||
| 24 | #error Please include mach/iomux.h | ||
| 25 | #endif | ||
| 26 | |||
| 27 | |||
| 28 | /* Primary GPIO pin functions */ | ||
| 29 | |||
| 30 | #define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) | ||
| 31 | #define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) | ||
| 32 | #define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) | ||
| 33 | #define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) | ||
| 34 | #define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) | ||
| 35 | #define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) | ||
| 36 | #define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) | ||
| 37 | #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) | ||
| 38 | #define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) | ||
| 39 | #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) | ||
| 40 | #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) | ||
| 41 | #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) | ||
| 42 | #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) | ||
| 43 | #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) | ||
| 44 | #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) | ||
| 45 | #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) | ||
| 46 | #define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) | ||
| 47 | #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) | ||
| 48 | #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) | ||
| 49 | #define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) | ||
| 50 | #define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) | ||
| 51 | #define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) | ||
| 52 | #define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) | ||
| 53 | #define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) | ||
| 54 | #define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) | ||
| 55 | #define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) | ||
| 56 | #define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) | ||
| 57 | #define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) | ||
| 58 | #define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) | ||
| 59 | #define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) | ||
| 60 | #define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) | ||
| 61 | #define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) | ||
| 62 | #define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) | ||
| 63 | #define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) | ||
| 64 | #define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) | ||
| 65 | #define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) | ||
| 66 | #define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) | ||
| 67 | #define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) | ||
| 68 | #define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) | ||
| 69 | #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) | ||
| 70 | #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) | ||
| 71 | #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) | ||
| 72 | #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) | ||
| 73 | #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) | ||
| 74 | #define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) | ||
| 75 | #define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) | ||
| 76 | #define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) | ||
| 77 | #define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) | ||
| 78 | #define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) | ||
| 79 | #define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) | ||
| 80 | #define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) | ||
| 81 | #define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) | ||
| 82 | #define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) | ||
| 83 | #define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) | ||
| 84 | #define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) | ||
| 85 | #define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) | ||
| 86 | #define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) | ||
| 87 | #define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) | ||
| 88 | #define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) | ||
| 89 | #define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) | ||
| 90 | |||
| 91 | /* Alternate GPIO pin functions */ | ||
| 92 | |||
| 93 | #define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) | ||
| 94 | #define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) | ||
| 95 | #define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) | ||
| 96 | #define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) | ||
| 97 | #define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) | ||
| 98 | #define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) | ||
| 99 | #define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) | ||
| 100 | #define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) | ||
| 101 | #define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) | ||
| 102 | #define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) | ||
| 103 | #define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) | ||
| 104 | #define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) | ||
| 105 | #define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) | ||
| 106 | #define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) | ||
| 107 | #define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) | ||
| 108 | #define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) | ||
| 109 | #define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) | ||
| 110 | #define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) | ||
| 111 | #define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) | ||
| 112 | #define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) | ||
| 113 | #define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) | ||
| 114 | #define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) | ||
| 115 | #define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) | ||
| 116 | #define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) | ||
| 117 | #define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) | ||
| 118 | #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) | ||
| 119 | #define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) | ||
| 120 | #define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) | ||
| 121 | #define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) | ||
| 122 | #define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) | ||
| 123 | #define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) | ||
| 124 | #define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) | ||
| 125 | #define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) | ||
| 126 | #define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) | ||
| 127 | #define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) | ||
| 128 | #define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) | ||
| 129 | #define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) | ||
| 130 | #define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) | ||
| 131 | #define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) | ||
| 132 | #define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) | ||
| 133 | #define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) | ||
| 134 | #define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) | ||
| 135 | #define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) | ||
| 136 | #define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) | ||
| 137 | #define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) | ||
| 138 | #define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) | ||
| 139 | #define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) | ||
| 140 | #define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) | ||
| 141 | #define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) | ||
| 142 | #define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) | ||
| 143 | #define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) | ||
| 144 | #define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) | ||
| 145 | |||
| 146 | /* AIN GPIO pin functions */ | ||
| 147 | |||
| 148 | #define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) | ||
| 149 | #define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) | ||
| 150 | #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) | ||
| 151 | #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) | ||
| 152 | #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) | ||
| 153 | #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) | ||
| 154 | #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) | ||
| 155 | #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) | ||
| 156 | #define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) | ||
| 157 | #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) | ||
| 158 | |||
| 159 | /* BIN GPIO pin functions */ | ||
| 160 | |||
| 161 | #define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) | ||
| 162 | |||
| 163 | /* CIN GPIO pin functions */ | ||
| 164 | |||
| 165 | #define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) | ||
| 166 | #define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) | ||
| 167 | #define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) | ||
| 168 | #define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) | ||
| 169 | #define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) | ||
| 170 | #define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) | ||
| 171 | #define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) | ||
| 172 | #define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) | ||
| 173 | #define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) | ||
| 174 | #define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) | ||
| 175 | #define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) | ||
| 176 | #define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) | ||
| 177 | #define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) | ||
| 178 | #define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) | ||
| 179 | #define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) | ||
| 180 | #define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) | ||
| 181 | #define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) | ||
| 182 | /* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ | ||
| 183 | |||
| 184 | /* AOUT GPIO pin functions */ | ||
| 185 | |||
| 186 | #define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) | ||
| 187 | #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) | ||
| 188 | #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) | ||
| 189 | #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) | ||
| 190 | #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) | ||
| 191 | #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) | ||
| 192 | #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) | ||
| 193 | #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) | ||
| 194 | #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) | ||
| 195 | #define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) | ||
| 196 | #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) | ||
| 197 | |||
| 198 | #define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) | ||
| 199 | #define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) | ||
| 200 | #define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) | ||
| 201 | #define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) | ||
| 202 | #define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) | ||
| 203 | #define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) | ||
| 204 | #define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) | ||
| 205 | |||
| 206 | |||
| 207 | #endif /* _MXC_GPIO_MX1_MX2_H */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h new file mode 100644 index 000000000000..fb5ae638e79f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h | |||
| @@ -0,0 +1,237 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _MXC_IOMUX_MX2x_H | ||
| 21 | #define _MXC_IOMUX_MX2x_H | ||
| 22 | |||
| 23 | #ifndef GPIO_PORTA | ||
| 24 | #error Please include mach/iomux.h | ||
| 25 | #endif | ||
| 26 | |||
| 27 | |||
| 28 | /* Primary GPIO pin functions */ | ||
| 29 | |||
| 30 | #define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) | ||
| 31 | #define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) | ||
| 32 | #define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) | ||
| 33 | #define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) | ||
| 34 | #define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) | ||
| 35 | #define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) | ||
| 36 | #define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) | ||
| 37 | #define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) | ||
| 38 | #define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) | ||
| 39 | #define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) | ||
| 40 | #define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) | ||
| 41 | #define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) | ||
| 42 | #define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) | ||
| 43 | #define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) | ||
| 44 | #define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) | ||
| 45 | #define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) | ||
| 46 | #define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) | ||
| 47 | #define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) | ||
| 48 | #define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) | ||
| 49 | #define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) | ||
| 50 | #define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) | ||
| 51 | #define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) | ||
| 52 | #define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) | ||
| 53 | #define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) | ||
| 54 | #define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) | ||
| 55 | #define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) | ||
| 56 | #define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) | ||
| 57 | #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) | ||
| 58 | #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) | ||
| 59 | #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) | ||
| 60 | #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) | ||
| 61 | #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) | ||
| 62 | #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) | ||
| 63 | #define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) | ||
| 64 | #define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) | ||
| 65 | #define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) | ||
| 66 | #define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) | ||
| 67 | #define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) | ||
| 68 | #define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) | ||
| 69 | #define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) | ||
| 70 | #define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) | ||
| 71 | #define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) | ||
| 72 | #define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) | ||
| 73 | #define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) | ||
| 74 | #define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) | ||
| 75 | #define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) | ||
| 76 | #define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) | ||
| 77 | #define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) | ||
| 78 | #define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) | ||
| 79 | #define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) | ||
| 80 | #define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) | ||
| 81 | #define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) | ||
| 82 | #define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) | ||
| 83 | #define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) | ||
| 84 | #define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) | ||
| 85 | #define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) | ||
| 86 | #define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) | ||
| 87 | #define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) | ||
| 88 | #define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) | ||
| 89 | #define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) | ||
| 90 | #define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) | ||
| 91 | #define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) | ||
| 92 | #define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) | ||
| 93 | #define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) | ||
| 94 | #define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) | ||
| 95 | #define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) | ||
| 96 | #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) | ||
| 97 | #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) | ||
| 98 | #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) | ||
| 99 | #define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) | ||
| 100 | #define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) | ||
| 101 | #define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) | ||
| 102 | #define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) | ||
| 103 | #define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) | ||
| 104 | #define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) | ||
| 105 | #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) | ||
| 106 | #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) | ||
| 107 | #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) | ||
| 108 | #define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) | ||
| 109 | #define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) | ||
| 110 | #define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) | ||
| 111 | #define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) | ||
| 112 | #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) | ||
| 113 | #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) | ||
| 114 | #define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) | ||
| 115 | #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) | ||
| 116 | #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) | ||
| 117 | #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) | ||
| 118 | #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) | ||
| 119 | #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) | ||
| 120 | #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) | ||
| 121 | #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) | ||
| 122 | #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) | ||
| 123 | #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) | ||
| 124 | #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) | ||
| 125 | #define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) | ||
| 126 | #define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) | ||
| 127 | #define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) | ||
| 128 | #define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) | ||
| 129 | #define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) | ||
| 130 | #define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) | ||
| 131 | #define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) | ||
| 132 | #define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) | ||
| 133 | #define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) | ||
| 134 | #define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) | ||
| 135 | #define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) | ||
| 136 | #define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) | ||
| 137 | #define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) | ||
| 138 | #define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) | ||
| 139 | #define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) | ||
| 140 | #define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) | ||
| 141 | |||
| 142 | /* Alternate GPIO pin functions */ | ||
| 143 | |||
| 144 | #define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) | ||
| 145 | #define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) | ||
| 146 | #define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) | ||
| 147 | #define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) | ||
| 148 | #define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) | ||
| 149 | #define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) | ||
| 150 | #define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) | ||
| 151 | #define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) | ||
| 152 | #define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) | ||
| 153 | #define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) | ||
| 154 | #define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) | ||
| 155 | #define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) | ||
| 156 | #define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) | ||
| 157 | #define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) | ||
| 158 | #define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) | ||
| 159 | #define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) | ||
| 160 | #define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) | ||
| 161 | #define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) | ||
| 162 | #define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) | ||
| 163 | #define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) | ||
| 164 | #define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) | ||
| 165 | #define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) | ||
| 166 | #define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) | ||
| 167 | #define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) | ||
| 168 | #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) | ||
| 169 | #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) | ||
| 170 | #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) | ||
| 171 | |||
| 172 | /* AIN GPIO pin functions */ | ||
| 173 | |||
| 174 | #define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) | ||
| 175 | #define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) | ||
| 176 | #define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) | ||
| 177 | #define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) | ||
| 178 | #define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) | ||
| 179 | #define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) | ||
| 180 | #define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) | ||
| 181 | #define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) | ||
| 182 | #define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) | ||
| 183 | #define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) | ||
| 184 | #define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) | ||
| 185 | #define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) | ||
| 186 | #define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) | ||
| 187 | #define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) | ||
| 188 | #define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) | ||
| 189 | #define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) | ||
| 190 | #define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) | ||
| 191 | #define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) | ||
| 192 | #define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) | ||
| 193 | #define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) | ||
| 194 | #define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) | ||
| 195 | #define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) | ||
| 196 | #define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) | ||
| 197 | #define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) | ||
| 198 | #define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) | ||
| 199 | #define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) | ||
| 200 | #define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) | ||
| 201 | #define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) | ||
| 202 | #define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) | ||
| 203 | #define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) | ||
| 204 | #define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) | ||
| 205 | #define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) | ||
| 206 | #define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) | ||
| 207 | #define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) | ||
| 208 | #define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) | ||
| 209 | #define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) | ||
| 210 | |||
| 211 | /* BIN GPIO pin functions */ | ||
| 212 | |||
| 213 | #define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) | ||
| 214 | |||
| 215 | /* CIN GPIO pin functions */ | ||
| 216 | |||
| 217 | #define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) | ||
| 218 | #define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) | ||
| 219 | #define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) | ||
| 220 | #define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) | ||
| 221 | #define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) | ||
| 222 | #define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) | ||
| 223 | #define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) | ||
| 224 | #define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) | ||
| 225 | #define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) | ||
| 226 | #define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) | ||
| 227 | |||
| 228 | /* AOUT GPIO pin functions */ | ||
| 229 | |||
| 230 | #define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) | ||
| 231 | #define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) | ||
| 232 | #define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) | ||
| 233 | #define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) | ||
| 234 | #define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) | ||
| 235 | |||
| 236 | |||
| 237 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index c9198c0aea18..ab838cfe94f9 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h | |||
| @@ -92,7 +92,7 @@ enum iomux_gp_func { | |||
| 92 | MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, | 92 | MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, |
| 93 | MUX_TAMPER_DETECT_EN = 1 << 16, | 93 | MUX_TAMPER_DETECT_EN = 1 << 16, |
| 94 | MUX_PGP_USB_4WIRE = 1 << 17, | 94 | MUX_PGP_USB_4WIRE = 1 << 17, |
| 95 | MUX_PGB_USB_COMMON = 1 << 18, | 95 | MUX_PGP_USB_COMMON = 1 << 18, |
| 96 | MUX_SDHC_MEMSTICK1 = 1 << 19, | 96 | MUX_SDHC_MEMSTICK1 = 1 << 19, |
| 97 | MUX_SDHC_MEMSTICK2 = 1 << 20, | 97 | MUX_SDHC_MEMSTICK2 = 1 << 20, |
| 98 | MUX_PGP_SPLL_BYP = 1 << 21, | 98 | MUX_PGP_SPLL_BYP = 1 << 21, |
| @@ -109,21 +109,44 @@ enum iomux_gp_func { | |||
| 109 | }; | 109 | }; |
| 110 | 110 | ||
| 111 | /* | 111 | /* |
| 112 | * This function enables/disables the general purpose function for a particular | 112 | * setups a single pin: |
| 113 | * signal. | 113 | * - reserves the pin so that it is not claimed by another driver |
| 114 | * - setups the iomux according to the configuration | ||
| 115 | * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib | ||
| 116 | */ | ||
| 117 | int mxc_iomux_setup_pin(const unsigned int pin, const char *label); | ||
| 118 | /* | ||
| 119 | * setups mutliple pins | ||
| 120 | * convenient way to call the above function with tables | ||
| 114 | */ | 121 | */ |
| 115 | void iomux_config_gpr(enum iomux_gp_func , bool); | 122 | int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, |
| 123 | const char *label); | ||
| 116 | 124 | ||
| 117 | /* | 125 | /* |
| 118 | * set the mode for a IOMUX pin. | 126 | * releases a single pin: |
| 127 | * - make it available for a future use by another driver | ||
| 128 | * - frees the GPIO if the pin was configured as GPIO | ||
| 129 | * - DOES NOT reconfigure the IOMUX in its reset state | ||
| 119 | */ | 130 | */ |
| 120 | int mxc_iomux_mode(unsigned int); | 131 | void mxc_iomux_release_pin(const unsigned int pin); |
| 132 | /* | ||
| 133 | * releases multiple pins | ||
| 134 | * convenvient way to call the above function with tables | ||
| 135 | */ | ||
| 136 | void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); | ||
| 121 | 137 | ||
| 122 | /* | 138 | /* |
| 123 | * This function enables/disables the general purpose function for a particular | 139 | * This function enables/disables the general purpose function for a particular |
| 124 | * signal. | 140 | * signal. |
| 125 | */ | 141 | */ |
| 126 | void mxc_iomux_set_gpr(enum iomux_gp_func, bool); | 142 | void mxc_iomux_set_gpr(enum iomux_gp_func, bool en); |
| 143 | |||
| 144 | /* | ||
| 145 | * This function only configures the iomux hardware. | ||
| 146 | * It is called by the setup functions and should not be called directly anymore. | ||
| 147 | * It is here visible for backward compatibility | ||
| 148 | */ | ||
| 149 | int mxc_iomux_mode(unsigned int pin_mode); | ||
| 127 | 150 | ||
| 128 | #define IOMUX_PADNUM_MASK 0x1ff | 151 | #define IOMUX_PADNUM_MASK 0x1ff |
| 129 | #define IOMUX_GPIONUM_SHIFT 9 | 152 | #define IOMUX_GPIONUM_SHIFT 9 |
| @@ -144,6 +167,11 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool); | |||
| 144 | MXC_GPIO_IRQ_START) | 167 | MXC_GPIO_IRQ_START) |
| 145 | 168 | ||
| 146 | /* | 169 | /* |
| 170 | * The number of gpio devices among the pads | ||
| 171 | */ | ||
| 172 | #define GPIO_PORT_MAX 3 | ||
| 173 | |||
| 174 | /* | ||
| 147 | * This enumeration is constructed based on the Section | 175 | * This enumeration is constructed based on the Section |
| 148 | * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated | 176 | * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated |
| 149 | * value is constructed based on the rules described above. | 177 | * value is constructed based on the rules described above. |
| @@ -480,6 +508,9 @@ enum iomux_pins { | |||
| 480 | MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), | 508 | MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), |
| 481 | }; | 509 | }; |
| 482 | 510 | ||
| 511 | #define PIN_MAX 327 | ||
| 512 | #define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ | ||
| 513 | |||
| 483 | /* | 514 | /* |
| 484 | * Convenience values for use with mxc_iomux_mode() | 515 | * Convenience values for use with mxc_iomux_mode() |
| 485 | * | 516 | * |
| @@ -507,7 +538,9 @@ enum iomux_pins { | |||
| 507 | #define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) | 538 | #define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) |
| 508 | #define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) | 539 | #define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) |
| 509 | #define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) | 540 | #define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) |
| 541 | #define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) | ||
| 510 | #define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) | 542 | #define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) |
| 543 | #define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) | ||
| 511 | #define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) | 544 | #define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) |
| 512 | #define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) | 545 | #define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) |
| 513 | #define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) | 546 | #define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) |
| @@ -525,6 +558,33 @@ enum iomux_pins { | |||
| 525 | #define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) | 558 | #define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) |
| 526 | #define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) | 559 | #define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) |
| 527 | #define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) | 560 | #define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) |
| 561 | #define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) | ||
| 562 | #define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) | ||
| 563 | #define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) | ||
| 564 | #define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) | ||
| 565 | #define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) | ||
| 566 | #define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) | ||
| 567 | #define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) | ||
| 568 | #define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) | ||
| 569 | #define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) | ||
| 570 | #define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) | ||
| 571 | #define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) | ||
| 572 | #define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) | ||
| 573 | #define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) | ||
| 574 | #define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) | ||
| 575 | #define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) | ||
| 576 | #define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) | ||
| 577 | #define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) | ||
| 578 | #define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) | ||
| 579 | #define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) | ||
| 580 | #define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) | ||
| 581 | #define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) | ||
| 582 | #define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) | ||
| 583 | #define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) | ||
| 584 | #define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) | ||
| 585 | #define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) | ||
| 586 | #define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) | ||
| 587 | #define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) | ||
| 528 | 588 | ||
| 529 | /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 | 589 | /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 |
| 530 | * cspi1_ss1*/ | 590 | * cspi1_ss1*/ |
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h new file mode 100644 index 000000000000..171f8adc1109 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux.h | |||
| @@ -0,0 +1,127 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _MXC_IOMUX_H | ||
| 21 | #define _MXC_IOMUX_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * GPIO Module and I/O Multiplexer | ||
| 25 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
| 26 | */ | ||
| 27 | #define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR) | ||
| 28 | #define MXC_DDIR(x) (0x00 + ((x) << 8)) | ||
| 29 | #define MXC_OCR1(x) (0x04 + ((x) << 8)) | ||
| 30 | #define MXC_OCR2(x) (0x08 + ((x) << 8)) | ||
| 31 | #define MXC_ICONFA1(x) (0x0c + ((x) << 8)) | ||
| 32 | #define MXC_ICONFA2(x) (0x10 + ((x) << 8)) | ||
| 33 | #define MXC_ICONFB1(x) (0x14 + ((x) << 8)) | ||
| 34 | #define MXC_ICONFB2(x) (0x18 + ((x) << 8)) | ||
| 35 | #define MXC_DR(x) (0x1c + ((x) << 8)) | ||
| 36 | #define MXC_GIUS(x) (0x20 + ((x) << 8)) | ||
| 37 | #define MXC_SSR(x) (0x24 + ((x) << 8)) | ||
| 38 | #define MXC_ICR1(x) (0x28 + ((x) << 8)) | ||
| 39 | #define MXC_ICR2(x) (0x2c + ((x) << 8)) | ||
| 40 | #define MXC_IMR(x) (0x30 + ((x) << 8)) | ||
| 41 | #define MXC_ISR(x) (0x34 + ((x) << 8)) | ||
| 42 | #define MXC_GPR(x) (0x38 + ((x) << 8)) | ||
| 43 | #define MXC_SWR(x) (0x3c + ((x) << 8)) | ||
| 44 | #define MXC_PUEN(x) (0x40 + ((x) << 8)) | ||
| 45 | |||
| 46 | #ifdef CONFIG_ARCH_MX1 | ||
| 47 | # define GPIO_PORT_MAX 3 | ||
| 48 | #endif | ||
| 49 | #ifdef CONFIG_ARCH_MX2 | ||
| 50 | # define GPIO_PORT_MAX 5 | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef GPIO_PORT_MAX | ||
| 54 | # error "GPIO config port count unknown!" | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #define GPIO_PIN_MASK 0x1f | ||
| 58 | |||
| 59 | #define GPIO_PORT_SHIFT 5 | ||
| 60 | #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) | ||
| 61 | |||
| 62 | #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) | ||
| 63 | #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) | ||
| 64 | #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) | ||
| 65 | #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) | ||
| 66 | #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) | ||
| 67 | #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) | ||
| 68 | |||
| 69 | #define GPIO_OUT (1 << 8) | ||
| 70 | #define GPIO_IN (0 << 8) | ||
| 71 | #define GPIO_PUEN (1 << 9) | ||
| 72 | |||
| 73 | #define GPIO_PF (1 << 10) | ||
| 74 | #define GPIO_AF (1 << 11) | ||
| 75 | |||
| 76 | #define GPIO_OCR_SHIFT 12 | ||
| 77 | #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) | ||
| 78 | #define GPIO_AIN (0 << GPIO_OCR_SHIFT) | ||
| 79 | #define GPIO_BIN (1 << GPIO_OCR_SHIFT) | ||
| 80 | #define GPIO_CIN (2 << GPIO_OCR_SHIFT) | ||
| 81 | #define GPIO_GPIO (3 << GPIO_OCR_SHIFT) | ||
| 82 | |||
| 83 | #define GPIO_AOUT_SHIFT 14 | ||
| 84 | #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) | ||
| 85 | #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) | ||
| 86 | #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) | ||
| 87 | #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) | ||
| 88 | #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) | ||
| 89 | |||
| 90 | #define GPIO_BOUT_SHIFT 16 | ||
| 91 | #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) | ||
| 92 | #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) | ||
| 93 | #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) | ||
| 94 | #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) | ||
| 95 | #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) | ||
| 96 | |||
| 97 | |||
| 98 | #ifdef CONFIG_ARCH_MX1 | ||
| 99 | #include <mach/iomux-mx1.h> | ||
| 100 | #endif | ||
| 101 | #ifdef CONFIG_ARCH_MX2 | ||
| 102 | #include <mach/iomux-mx2x.h> | ||
| 103 | #ifdef CONFIG_MACH_MX21 | ||
| 104 | #include <mach/iomux-mx21.h> | ||
| 105 | #endif | ||
| 106 | #ifdef CONFIG_MACH_MX27 | ||
| 107 | #include <mach/iomux-mx27.h> | ||
| 108 | #endif | ||
| 109 | #endif | ||
| 110 | |||
| 111 | |||
| 112 | /* decode irq number to use with IMR(x), ISR(x) and friends */ | ||
| 113 | #define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) | ||
| 114 | |||
| 115 | #define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) | ||
| 116 | #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) | ||
| 117 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | ||
| 118 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | ||
| 119 | #define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) | ||
| 120 | |||
| 121 | |||
| 122 | extern void mxc_gpio_mode(int gpio_mode); | ||
| 123 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
| 124 | const char *label); | ||
| 125 | extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); | ||
| 126 | |||
| 127 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 0b808399097f..e0783e619580 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h | |||
| @@ -14,7 +14,12 @@ | |||
| 14 | #if defined CONFIG_ARCH_MX1 | 14 | #if defined CONFIG_ARCH_MX1 |
| 15 | #define PHYS_OFFSET UL(0x08000000) | 15 | #define PHYS_OFFSET UL(0x08000000) |
| 16 | #elif defined CONFIG_ARCH_MX2 | 16 | #elif defined CONFIG_ARCH_MX2 |
| 17 | #ifdef CONFIG_MACH_MX21 | ||
| 18 | #define PHYS_OFFSET UL(0xC0000000) | ||
| 19 | #endif | ||
| 20 | #ifdef CONFIG_MACH_MX27 | ||
| 17 | #define PHYS_OFFSET UL(0xA0000000) | 21 | #define PHYS_OFFSET UL(0xA0000000) |
| 22 | #endif | ||
| 18 | #elif defined CONFIG_ARCH_MX3 | 23 | #elif defined CONFIG_ARCH_MX3 |
| 19 | #define PHYS_OFFSET UL(0x80000000) | 24 | #define PHYS_OFFSET UL(0x80000000) |
| 20 | #endif | 25 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h new file mode 100644 index 000000000000..e8c4cf56c24e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx21.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de | ||
| 5 | * | ||
| 6 | * This contains i.MX21-specific hardware definitions. For those | ||
| 7 | * hardware pieces that are common between i.MX21 and i.MX27, have a | ||
| 8 | * look at mx2x.h. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License | ||
| 12 | * as published by the Free Software Foundation; either version 2 | ||
| 13 | * of the License, or (at your option) any later version. | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 22 | * MA 02110-1301, USA. | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef __ASM_ARCH_MXC_MX21_H__ | ||
| 26 | #define __ASM_ARCH_MXC_MX21_H__ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 29 | #error "Do not include directly." | ||
| 30 | #endif | ||
| 31 | |||
| 32 | |||
| 33 | /* Memory regions and CS */ | ||
| 34 | #define SDRAM_BASE_ADDR 0xC0000000 | ||
| 35 | #define CSD1_BASE_ADDR 0xC4000000 | ||
| 36 | |||
| 37 | #define CS0_BASE_ADDR 0xC8000000 | ||
| 38 | #define CS1_BASE_ADDR 0xCC000000 | ||
| 39 | #define CS2_BASE_ADDR 0xD0000000 | ||
| 40 | #define CS3_BASE_ADDR 0xD1000000 | ||
| 41 | #define CS4_BASE_ADDR 0xD2000000 | ||
| 42 | #define CS5_BASE_ADDR 0xDD000000 | ||
| 43 | #define PCMCIA_MEM_BASE_ADDR 0xD4000000 | ||
| 44 | |||
| 45 | /* NAND, SDRAM, WEIM etc controllers */ | ||
| 46 | #define X_MEMC_BASE_ADDR 0xDF000000 | ||
| 47 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 | ||
| 48 | #define X_MEMC_SIZE SZ_256K | ||
| 49 | |||
| 50 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | ||
| 51 | #define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 52 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 53 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 54 | |||
| 55 | #define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ | ||
| 56 | |||
| 57 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ | ||
| 58 | #define ARCH_NR_GPIOS (6*32 + 16) | ||
| 59 | |||
| 60 | /* fixed interrupt numbers */ | ||
| 61 | #define MXC_INT_USBCTRL 58 | ||
| 62 | #define MXC_INT_USBCTRL 58 | ||
| 63 | #define MXC_INT_USBMNP 57 | ||
| 64 | #define MXC_INT_USBFUNC 56 | ||
| 65 | #define MXC_INT_USBHOST 55 | ||
| 66 | #define MXC_INT_USBDMA 54 | ||
| 67 | #define MXC_INT_USBWKUP 53 | ||
| 68 | #define MXC_INT_EMMADEC 50 | ||
| 69 | #define MXC_INT_EMMAENC 49 | ||
| 70 | #define MXC_INT_BMI 30 | ||
| 71 | #define MXC_INT_FIRI 9 | ||
| 72 | |||
| 73 | /* fixed DMA request numbers */ | ||
| 74 | #define DMA_REQ_BMI_RX 29 | ||
| 75 | #define DMA_REQ_BMI_TX 28 | ||
| 76 | #define DMA_REQ_FIRI_RX 4 | ||
| 77 | |||
| 78 | #endif /* __ASM_ARCH_MXC_MX21_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 0313be720552..6e93f2c0b7bb 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
| @@ -2,6 +2,10 @@ | |||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * | 4 | * |
| 5 | * This contains i.MX27-specific hardware definitions. For those | ||
| 6 | * hardware pieces that are common between i.MX21 and i.MX27, have a | ||
| 7 | * look at mx2x.h. | ||
| 8 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | 9 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License | 10 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 | 11 | * as published by the Free Software Foundation; either version 2 |
| @@ -27,35 +31,6 @@ | |||
| 27 | /* IRAM */ | 31 | /* IRAM */ |
| 28 | #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ | 32 | #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ |
| 29 | 33 | ||
| 30 | /* Register offests */ | ||
| 31 | #define AIPI_BASE_ADDR 0x10000000 | ||
| 32 | #define AIPI_BASE_ADDR_VIRT 0xF4000000 | ||
| 33 | #define AIPI_SIZE SZ_1M | ||
| 34 | |||
| 35 | #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) | ||
| 36 | #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) | ||
| 37 | #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) | ||
| 38 | #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) | ||
| 39 | #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) | ||
| 40 | #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) | ||
| 41 | #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) | ||
| 42 | #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) | ||
| 43 | #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) | ||
| 44 | #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) | ||
| 45 | #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) | ||
| 46 | #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) | ||
| 47 | #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) | ||
| 48 | #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) | ||
| 49 | #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) | ||
| 50 | #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) | ||
| 51 | #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) | ||
| 52 | #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) | ||
| 53 | #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) | ||
| 54 | #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) | ||
| 55 | #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) | ||
| 56 | #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) | ||
| 57 | |||
| 58 | #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) | ||
| 59 | #define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) | 34 | #define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) |
| 60 | #define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) | 35 | #define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) |
| 61 | #define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) | 36 | #define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) |
| @@ -64,55 +39,24 @@ | |||
| 64 | #define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) | 39 | #define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) |
| 65 | #define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) | 40 | #define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) |
| 66 | #define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) | 41 | #define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) |
| 67 | |||
| 68 | #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) | ||
| 69 | #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) | ||
| 70 | #define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) | 42 | #define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) |
| 71 | #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) | ||
| 72 | /* for mx27*/ | ||
| 73 | #define OTG_BASE_ADDR USBOTG_BASE_ADDR | 43 | #define OTG_BASE_ADDR USBOTG_BASE_ADDR |
| 74 | #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) | 44 | #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) |
| 75 | #define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) | ||
| 76 | #define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) | ||
| 77 | #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) | ||
| 78 | #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) | ||
| 79 | #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) | 45 | #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) |
| 80 | |||
| 81 | #define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) | 46 | #define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) |
| 82 | #define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) | 47 | #define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) |
| 83 | #define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) | 48 | #define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) |
| 84 | #define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) | 49 | #define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) |
| 85 | #define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) | 50 | #define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) |
| 86 | 51 | ||
| 87 | #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) | 52 | /* ROM patch */ |
| 88 | #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) | ||
| 89 | |||
| 90 | /* ROMP and AVIC */ | ||
| 91 | #define ROMP_BASE_ADDR 0x10041000 | 53 | #define ROMP_BASE_ADDR 0x10041000 |
| 92 | 54 | ||
| 93 | #define AVIC_BASE_ADDR 0x10040000 | ||
| 94 | |||
| 95 | #define SAHB1_BASE_ADDR 0x80000000 | ||
| 96 | #define SAHB1_BASE_ADDR_VIRT 0xF4100000 | ||
| 97 | #define SAHB1_SIZE SZ_1M | ||
| 98 | |||
| 99 | #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) | ||
| 100 | #define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) | 55 | #define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) |
| 101 | 56 | ||
| 102 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ | ||
| 103 | #define X_MEMC_BASE_ADDR 0xD8000000 | ||
| 104 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 | ||
| 105 | #define X_MEMC_SIZE SZ_1M | ||
| 106 | |||
| 107 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) | ||
| 108 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 109 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 110 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 111 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 112 | |||
| 113 | /* Memory regions and CS */ | 57 | /* Memory regions and CS */ |
| 114 | #define SDRAM_BASE_ADDR 0xA0000000 | 58 | #define SDRAM_BASE_ADDR 0xA0000000 |
| 115 | #define CSD1_BASE_ADDR 0xB0000000 | 59 | #define CSD1_BASE_ADDR 0xB0000000 |
| 116 | 60 | ||
| 117 | #define CS0_BASE_ADDR 0xC0000000 | 61 | #define CS0_BASE_ADDR 0xC0000000 |
| 118 | #define CS1_BASE_ADDR 0xC8000000 | 62 | #define CS1_BASE_ADDR 0xC8000000 |
| @@ -122,44 +66,20 @@ | |||
| 122 | #define CS5_BASE_ADDR 0xD6000000 | 66 | #define CS5_BASE_ADDR 0xD6000000 |
| 123 | #define PCMCIA_MEM_BASE_ADDR 0xDC000000 | 67 | #define PCMCIA_MEM_BASE_ADDR 0xDC000000 |
| 124 | 68 | ||
| 125 | /* | 69 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ |
| 126 | * This macro defines the physical to virtual address mapping for all the | 70 | #define X_MEMC_BASE_ADDR 0xD8000000 |
| 127 | * peripheral modules. It is used by passing in the physical address as x | 71 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 |
| 128 | * and returning the virtual address. If the physical address is not mapped, | 72 | #define X_MEMC_SIZE SZ_1M |
| 129 | * it returns 0xDEADBEEF | ||
| 130 | */ | ||
| 131 | #define IO_ADDRESS(x) \ | ||
| 132 | (void __iomem *) \ | ||
| 133 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | ||
| 134 | AIPI_IO_ADDRESS(x) : \ | ||
| 135 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | ||
| 136 | SAHB1_IO_ADDRESS(x) : \ | ||
| 137 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ | ||
| 138 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) | ||
| 139 | |||
| 140 | /* define the address mapping macros: in physical address order */ | ||
| 141 | #define AIPI_IO_ADDRESS(x) \ | ||
| 142 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) | ||
| 143 | |||
| 144 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) | ||
| 145 | |||
| 146 | #define SAHB1_IO_ADDRESS(x) \ | ||
| 147 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) | ||
| 148 | |||
| 149 | #define CS4_IO_ADDRESS(x) \ | ||
| 150 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 151 | |||
| 152 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 153 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 154 | 73 | ||
| 155 | #define PCMCIA_IO_ADDRESS(x) \ | 74 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) |
| 156 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | 75 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) |
| 76 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 77 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 78 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 157 | 79 | ||
| 158 | /* fixed interrput numbers */ | 80 | /* fixed interrupt numbers */ |
| 159 | #define MXC_INT_CCM 63 | 81 | #define MXC_INT_CCM 63 |
| 160 | #define MXC_INT_IIM 62 | 82 | #define MXC_INT_IIM 62 |
| 161 | #define MXC_INT_LCDC 61 | ||
| 162 | #define MXC_INT_SLCDC 60 | ||
| 163 | #define MXC_INT_SAHARA 59 | 83 | #define MXC_INT_SAHARA 59 |
| 164 | #define MXC_INT_SCC_SCM 58 | 84 | #define MXC_INT_SCC_SCM 58 |
| 165 | #define MXC_INT_SCC_SMN 57 | 85 | #define MXC_INT_SCC_SMN 57 |
| @@ -167,54 +87,12 @@ | |||
| 167 | #define MXC_INT_USB2 55 | 87 | #define MXC_INT_USB2 55 |
| 168 | #define MXC_INT_USB1 54 | 88 | #define MXC_INT_USB1 54 |
| 169 | #define MXC_INT_VPU 53 | 89 | #define MXC_INT_VPU 53 |
| 170 | #define MXC_INT_EMMAPP 52 | ||
| 171 | #define MXC_INT_EMMAPRP 51 | ||
| 172 | #define MXC_INT_FEC 50 | 90 | #define MXC_INT_FEC 50 |
| 173 | #define MXC_INT_UART5 49 | 91 | #define MXC_INT_UART5 49 |
| 174 | #define MXC_INT_UART6 48 | 92 | #define MXC_INT_UART6 48 |
| 175 | #define MXC_INT_DMACH15 47 | ||
| 176 | #define MXC_INT_DMACH14 46 | ||
| 177 | #define MXC_INT_DMACH13 45 | ||
| 178 | #define MXC_INT_DMACH12 44 | ||
| 179 | #define MXC_INT_DMACH11 43 | ||
| 180 | #define MXC_INT_DMACH10 42 | ||
| 181 | #define MXC_INT_DMACH9 41 | ||
| 182 | #define MXC_INT_DMACH8 40 | ||
| 183 | #define MXC_INT_DMACH7 39 | ||
| 184 | #define MXC_INT_DMACH6 38 | ||
| 185 | #define MXC_INT_DMACH5 37 | ||
| 186 | #define MXC_INT_DMACH4 36 | ||
| 187 | #define MXC_INT_DMACH3 35 | ||
| 188 | #define MXC_INT_DMACH2 34 | ||
| 189 | #define MXC_INT_DMACH1 33 | ||
| 190 | #define MXC_INT_DMACH0 32 | ||
| 191 | #define MXC_INT_CSI 31 | ||
| 192 | #define MXC_INT_ATA 30 | 93 | #define MXC_INT_ATA 30 |
| 193 | #define MXC_INT_NANDFC 29 | ||
| 194 | #define MXC_INT_PCMCIA 28 | ||
| 195 | #define MXC_INT_WDOG 27 | ||
| 196 | #define MXC_INT_GPT1 26 | ||
| 197 | #define MXC_INT_GPT2 25 | ||
| 198 | #define MXC_INT_GPT3 24 | ||
| 199 | #define MXC_INT_GPT INT_GPT1 | ||
| 200 | #define MXC_INT_PWM 23 | ||
| 201 | #define MXC_INT_RTC 22 | ||
| 202 | #define MXC_INT_KPP 21 | ||
| 203 | #define MXC_INT_UART1 20 | ||
| 204 | #define MXC_INT_UART2 19 | ||
| 205 | #define MXC_INT_UART3 18 | ||
| 206 | #define MXC_INT_UART4 17 | ||
| 207 | #define MXC_INT_CSPI1 16 | ||
| 208 | #define MXC_INT_CSPI2 15 | ||
| 209 | #define MXC_INT_SSI1 14 | ||
| 210 | #define MXC_INT_SSI2 13 | ||
| 211 | #define MXC_INT_I2C 12 | ||
| 212 | #define MXC_INT_SDHC1 11 | ||
| 213 | #define MXC_INT_SDHC2 10 | ||
| 214 | #define MXC_INT_SDHC3 9 | 94 | #define MXC_INT_SDHC3 9 |
| 215 | #define MXC_INT_GPIO 8 | ||
| 216 | #define MXC_INT_SDHC 7 | 95 | #define MXC_INT_SDHC 7 |
| 217 | #define MXC_INT_CSPI3 6 | ||
| 218 | #define MXC_INT_RTIC 5 | 96 | #define MXC_INT_RTIC 5 |
| 219 | #define MXC_INT_GPT4 4 | 97 | #define MXC_INT_GPT4 4 |
| 220 | #define MXC_INT_GPT5 3 | 98 | #define MXC_INT_GPT5 3 |
| @@ -228,36 +106,9 @@ | |||
| 228 | #define DMA_REQ_UART6_TX 34 | 106 | #define DMA_REQ_UART6_TX 34 |
| 229 | #define DMA_REQ_UART5_RX 33 | 107 | #define DMA_REQ_UART5_RX 33 |
| 230 | #define DMA_REQ_UART5_TX 32 | 108 | #define DMA_REQ_UART5_TX 32 |
| 231 | #define DMA_REQ_CSI_RX 31 | ||
| 232 | #define DMA_REQ_CSI_STAT 30 | ||
| 233 | #define DMA_REQ_ATA_RCV 29 | 109 | #define DMA_REQ_ATA_RCV 29 |
| 234 | #define DMA_REQ_ATA_TX 28 | 110 | #define DMA_REQ_ATA_TX 28 |
| 235 | #define DMA_REQ_UART1_TX 27 | ||
| 236 | #define DMA_REQ_UART1_RX 26 | ||
| 237 | #define DMA_REQ_UART2_TX 25 | ||
| 238 | #define DMA_REQ_UART2_RX 24 | ||
| 239 | #define DMA_REQ_UART3_TX 23 | ||
| 240 | #define DMA_REQ_UART3_RX 22 | ||
| 241 | #define DMA_REQ_UART4_TX 21 | ||
| 242 | #define DMA_REQ_UART4_RX 20 | ||
| 243 | #define DMA_REQ_CSPI1_TX 19 | ||
| 244 | #define DMA_REQ_CSPI1_RX 18 | ||
| 245 | #define DMA_REQ_CSPI2_TX 17 | ||
| 246 | #define DMA_REQ_CSPI2_RX 16 | ||
| 247 | #define DMA_REQ_SSI1_TX1 15 | ||
| 248 | #define DMA_REQ_SSI1_RX1 14 | ||
| 249 | #define DMA_REQ_SSI1_TX0 13 | ||
| 250 | #define DMA_REQ_SSI1_RX0 12 | ||
| 251 | #define DMA_REQ_SSI2_TX1 11 | ||
| 252 | #define DMA_REQ_SSI2_RX1 10 | ||
| 253 | #define DMA_REQ_SSI2_TX0 9 | ||
| 254 | #define DMA_REQ_SSI2_RX0 8 | ||
| 255 | #define DMA_REQ_SDHC1 7 | ||
| 256 | #define DMA_REQ_SDHC2 6 | ||
| 257 | #define DMA_REQ_MSHC 4 | 111 | #define DMA_REQ_MSHC 4 |
| 258 | #define DMA_REQ_EXT 3 | ||
| 259 | #define DMA_REQ_CSPI3_TX 2 | ||
| 260 | #define DMA_REQ_CSPI3_RX 1 | ||
| 261 | 112 | ||
| 262 | /* silicon revisions specific to i.MX27 */ | 113 | /* silicon revisions specific to i.MX27 */ |
| 263 | #define CHIP_REV_1_0 0x00 | 114 | #define CHIP_REV_1_0 0x00 |
| @@ -267,25 +118,8 @@ | |||
| 267 | extern int mx27_revision(void); | 118 | extern int mx27_revision(void); |
| 268 | #endif | 119 | #endif |
| 269 | 120 | ||
| 270 | /* gpio and gpio based interrupt handling */ | ||
| 271 | #define GPIO_DR 0x1C | ||
| 272 | #define GPIO_GDIR 0x00 | ||
| 273 | #define GPIO_PSR 0x24 | ||
| 274 | #define GPIO_ICR1 0x28 | ||
| 275 | #define GPIO_ICR2 0x2C | ||
| 276 | #define GPIO_IMR 0x30 | ||
| 277 | #define GPIO_ISR 0x34 | ||
| 278 | #define GPIO_INT_LOW_LEV 0x3 | ||
| 279 | #define GPIO_INT_HIGH_LEV 0x2 | ||
| 280 | #define GPIO_INT_RISE_EDGE 0x0 | ||
| 281 | #define GPIO_INT_FALL_EDGE 0x1 | ||
| 282 | #define GPIO_INT_NONE 0x4 | ||
| 283 | |||
| 284 | /* Mandatory defines used globally */ | 121 | /* Mandatory defines used globally */ |
| 285 | 122 | ||
| 286 | /* this is an i.MX27 CPU */ | ||
| 287 | #define cpu_is_mx27() (1) | ||
| 288 | |||
| 289 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ | 123 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ |
| 290 | #define ARCH_NR_GPIOS (192 + 16) | 124 | #define ARCH_NR_GPIOS (192 + 16) |
| 291 | 125 | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h new file mode 100644 index 000000000000..fc40d3ab8c5b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx2x.h | |||
| @@ -0,0 +1,200 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This contains hardware definitions that are common between i.MX21 and | ||
| 6 | * i.MX27. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version 2 | ||
| 11 | * of the License, or (at your option) any later version. | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 20 | * MA 02110-1301, USA. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ASM_ARCH_MXC_MX2x_H__ | ||
| 24 | #define __ASM_ARCH_MXC_MX2x_H__ | ||
| 25 | |||
| 26 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 27 | #error "Do not include directly." | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* The following addresses are common between i.MX21 and i.MX27 */ | ||
| 31 | |||
| 32 | /* Register offests */ | ||
| 33 | #define AIPI_BASE_ADDR 0x10000000 | ||
| 34 | #define AIPI_BASE_ADDR_VIRT 0xF4000000 | ||
| 35 | #define AIPI_SIZE SZ_1M | ||
| 36 | |||
| 37 | #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) | ||
| 38 | #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) | ||
| 39 | #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) | ||
| 40 | #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) | ||
| 41 | #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) | ||
| 42 | #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) | ||
| 43 | #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) | ||
| 44 | #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) | ||
| 45 | #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) | ||
| 46 | #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) | ||
| 47 | #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) | ||
| 48 | #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) | ||
| 49 | #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) | ||
| 50 | #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) | ||
| 51 | #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) | ||
| 52 | #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) | ||
| 53 | #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) | ||
| 54 | #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) | ||
| 55 | #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) | ||
| 56 | #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) | ||
| 57 | #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) | ||
| 58 | #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) | ||
| 59 | #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) | ||
| 60 | #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) | ||
| 61 | #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) | ||
| 62 | #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) | ||
| 63 | #define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) | ||
| 64 | #define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) | ||
| 65 | #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) | ||
| 66 | #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) | ||
| 67 | #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) | ||
| 68 | #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) | ||
| 69 | |||
| 70 | #define AVIC_BASE_ADDR 0x10040000 | ||
| 71 | |||
| 72 | #define SAHB1_BASE_ADDR 0x80000000 | ||
| 73 | #define SAHB1_BASE_ADDR_VIRT 0xF4100000 | ||
| 74 | #define SAHB1_SIZE SZ_1M | ||
| 75 | |||
| 76 | #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * This macro defines the physical to virtual address mapping for all the | ||
| 80 | * peripheral modules. It is used by passing in the physical address as x | ||
| 81 | * and returning the virtual address. If the physical address is not mapped, | ||
| 82 | * it returns 0xDEADBEEF | ||
| 83 | */ | ||
| 84 | #define IO_ADDRESS(x) \ | ||
| 85 | (void __force __iomem *) \ | ||
| 86 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | ||
| 87 | AIPI_IO_ADDRESS(x) : \ | ||
| 88 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | ||
| 89 | SAHB1_IO_ADDRESS(x) : \ | ||
| 90 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ | ||
| 91 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) | ||
| 92 | |||
| 93 | /* define the address mapping macros: in physical address order */ | ||
| 94 | #define AIPI_IO_ADDRESS(x) \ | ||
| 95 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) | ||
| 96 | |||
| 97 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) | ||
| 98 | |||
| 99 | #define SAHB1_IO_ADDRESS(x) \ | ||
| 100 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) | ||
| 101 | |||
| 102 | #define CS4_IO_ADDRESS(x) \ | ||
| 103 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 104 | |||
| 105 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 106 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 107 | |||
| 108 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 109 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 110 | |||
| 111 | /* fixed interrupt numbers */ | ||
| 112 | #define MXC_INT_LCDC 61 | ||
| 113 | #define MXC_INT_SLCDC 60 | ||
| 114 | #define MXC_INT_EMMAPP 52 | ||
| 115 | #define MXC_INT_EMMAPRP 51 | ||
| 116 | #define MXC_INT_DMACH15 47 | ||
| 117 | #define MXC_INT_DMACH14 46 | ||
| 118 | #define MXC_INT_DMACH13 45 | ||
| 119 | #define MXC_INT_DMACH12 44 | ||
| 120 | #define MXC_INT_DMACH11 43 | ||
| 121 | #define MXC_INT_DMACH10 42 | ||
| 122 | #define MXC_INT_DMACH9 41 | ||
| 123 | #define MXC_INT_DMACH8 40 | ||
| 124 | #define MXC_INT_DMACH7 39 | ||
| 125 | #define MXC_INT_DMACH6 38 | ||
| 126 | #define MXC_INT_DMACH5 37 | ||
| 127 | #define MXC_INT_DMACH4 36 | ||
| 128 | #define MXC_INT_DMACH3 35 | ||
| 129 | #define MXC_INT_DMACH2 34 | ||
| 130 | #define MXC_INT_DMACH1 33 | ||
| 131 | #define MXC_INT_DMACH0 32 | ||
| 132 | #define MXC_INT_CSI 31 | ||
| 133 | #define MXC_INT_NANDFC 29 | ||
| 134 | #define MXC_INT_PCMCIA 28 | ||
| 135 | #define MXC_INT_WDOG 27 | ||
| 136 | #define MXC_INT_GPT1 26 | ||
| 137 | #define MXC_INT_GPT2 25 | ||
| 138 | #define MXC_INT_GPT3 24 | ||
| 139 | #define MXC_INT_GPT INT_GPT1 | ||
| 140 | #define MXC_INT_PWM 23 | ||
| 141 | #define MXC_INT_RTC 22 | ||
| 142 | #define MXC_INT_KPP 21 | ||
| 143 | #define MXC_INT_UART1 20 | ||
| 144 | #define MXC_INT_UART2 19 | ||
| 145 | #define MXC_INT_UART3 18 | ||
| 146 | #define MXC_INT_UART4 17 | ||
| 147 | #define MXC_INT_CSPI1 16 | ||
| 148 | #define MXC_INT_CSPI2 15 | ||
| 149 | #define MXC_INT_SSI1 14 | ||
| 150 | #define MXC_INT_SSI2 13 | ||
| 151 | #define MXC_INT_I2C 12 | ||
| 152 | #define MXC_INT_SDHC1 11 | ||
| 153 | #define MXC_INT_SDHC2 10 | ||
| 154 | #define MXC_INT_GPIO 8 | ||
| 155 | #define MXC_INT_CSPI3 6 | ||
| 156 | |||
| 157 | /* gpio and gpio based interrupt handling */ | ||
| 158 | #define GPIO_DR 0x1C | ||
| 159 | #define GPIO_GDIR 0x00 | ||
| 160 | #define GPIO_PSR 0x24 | ||
| 161 | #define GPIO_ICR1 0x28 | ||
| 162 | #define GPIO_ICR2 0x2C | ||
| 163 | #define GPIO_IMR 0x30 | ||
| 164 | #define GPIO_ISR 0x34 | ||
| 165 | #define GPIO_INT_LOW_LEV 0x3 | ||
| 166 | #define GPIO_INT_HIGH_LEV 0x2 | ||
| 167 | #define GPIO_INT_RISE_EDGE 0x0 | ||
| 168 | #define GPIO_INT_FALL_EDGE 0x1 | ||
| 169 | #define GPIO_INT_NONE 0x4 | ||
| 170 | |||
| 171 | /* fixed DMA request numbers */ | ||
| 172 | #define DMA_REQ_CSI_RX 31 | ||
| 173 | #define DMA_REQ_CSI_STAT 30 | ||
| 174 | #define DMA_REQ_UART1_TX 27 | ||
| 175 | #define DMA_REQ_UART1_RX 26 | ||
| 176 | #define DMA_REQ_UART2_TX 25 | ||
| 177 | #define DMA_REQ_UART2_RX 24 | ||
| 178 | #define DMA_REQ_UART3_TX 23 | ||
| 179 | #define DMA_REQ_UART3_RX 22 | ||
| 180 | #define DMA_REQ_UART4_TX 21 | ||
| 181 | #define DMA_REQ_UART4_RX 20 | ||
| 182 | #define DMA_REQ_CSPI1_TX 19 | ||
| 183 | #define DMA_REQ_CSPI1_RX 18 | ||
| 184 | #define DMA_REQ_CSPI2_TX 17 | ||
| 185 | #define DMA_REQ_CSPI2_RX 16 | ||
| 186 | #define DMA_REQ_SSI1_TX1 15 | ||
| 187 | #define DMA_REQ_SSI1_RX1 14 | ||
| 188 | #define DMA_REQ_SSI1_TX0 13 | ||
| 189 | #define DMA_REQ_SSI1_RX0 12 | ||
| 190 | #define DMA_REQ_SSI2_TX1 11 | ||
| 191 | #define DMA_REQ_SSI2_RX1 10 | ||
| 192 | #define DMA_REQ_SSI2_TX0 9 | ||
| 193 | #define DMA_REQ_SSI2_RX0 8 | ||
| 194 | #define DMA_REQ_SDHC1 7 | ||
| 195 | #define DMA_REQ_SDHC2 6 | ||
| 196 | #define DMA_REQ_EXT 3 | ||
| 197 | #define DMA_REQ_CSPI3_TX 2 | ||
| 198 | #define DMA_REQ_CSPI3_RX 1 | ||
| 199 | |||
| 200 | #endif /* __ASM_ARCH_MXC_MX2x_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index de026654b00e..0b06941b6139 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
| @@ -1,360 +1,45 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_MX31_H__ | ||
| 12 | #define __ASM_ARCH_MXC_MX31_H__ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 15 | #error "Do not include directly." | ||
| 16 | #endif | ||
| 17 | |||
| 18 | /* | ||
| 19 | * MX31 memory map: | ||
| 20 | * | ||
| 21 | * Virt Phys Size What | ||
| 22 | * --------------------------------------------------------------------------- | ||
| 23 | * F8000000 1FFC0000 16K IRAM | ||
| 24 | * F9000000 30000000 256M L2CC | ||
| 25 | * FC000000 43F00000 1M AIPS 1 | ||
| 26 | * FC100000 50000000 1M SPBA | ||
| 27 | * FC200000 53F00000 1M AIPS 2 | ||
| 28 | * FC500000 60000000 128M ROMPATCH | ||
| 29 | * FC400000 68000000 128M AVIC | ||
| 30 | * 70000000 256M IPU (MAX M2) | ||
| 31 | * 80000000 256M CSD0 SDRAM/DDR | ||
| 32 | * 90000000 256M CSD1 SDRAM/DDR | ||
| 33 | * A0000000 128M CS0 Flash | ||
| 34 | * A8000000 128M CS1 Flash | ||
| 35 | * B0000000 32M CS2 | ||
| 36 | * B2000000 32M CS3 | ||
| 37 | * F4000000 B4000000 32M CS4 | ||
| 38 | * B6000000 32M CS5 | ||
| 39 | * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 40 | * C0000000 64M PCMCIA/CF | ||
| 41 | */ | ||
| 42 | |||
| 43 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 44 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 45 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 46 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 47 | |||
| 48 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 49 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 50 | #define CS4_SIZE SZ_32M | ||
| 51 | |||
| 52 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 53 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 54 | |||
| 55 | /* | ||
| 56 | * IRAM | 2 | * IRAM |
| 57 | */ | 3 | */ |
| 58 | #define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ | 4 | #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ |
| 59 | #define IRAM_BASE_ADDR_VIRT 0xF8000000 | 5 | #define MX31_IRAM_SIZE SZ_16K |
| 60 | #define IRAM_SIZE SZ_16K | ||
| 61 | |||
| 62 | /* | ||
| 63 | * L2CC | ||
| 64 | */ | ||
| 65 | #define L2CC_BASE_ADDR 0x30000000 | ||
| 66 | #define L2CC_BASE_ADDR_VIRT 0xF9000000 | ||
| 67 | #define L2CC_SIZE SZ_1M | ||
| 68 | |||
| 69 | /* | ||
| 70 | * AIPS 1 | ||
| 71 | */ | ||
| 72 | #define AIPS1_BASE_ADDR 0x43F00000 | ||
| 73 | #define AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
| 74 | #define AIPS1_SIZE SZ_1M | ||
| 75 | 6 | ||
| 76 | #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) | ||
| 77 | #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) | ||
| 78 | #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) | ||
| 79 | #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) | ||
| 80 | #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) | ||
| 81 | #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) | ||
| 82 | #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) | ||
| 83 | #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) | ||
| 84 | #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) | 7 | #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) |
| 85 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) | 8 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) |
| 86 | #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) | ||
| 87 | #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) | ||
| 88 | #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) | ||
| 89 | #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) | ||
| 90 | #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) | ||
| 91 | #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) | ||
| 92 | #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) | ||
| 93 | #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) | ||
| 94 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) | 9 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) |
| 95 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) | 10 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) |
| 96 | #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) | ||
| 97 | #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) | ||
| 98 | |||
| 99 | /* | ||
| 100 | * SPBA global module enabled #0 | ||
| 101 | */ | ||
| 102 | #define SPBA0_BASE_ADDR 0x50000000 | ||
| 103 | #define SPBA0_BASE_ADDR_VIRT 0xFC100000 | ||
| 104 | #define SPBA0_SIZE SZ_1M | ||
| 105 | 11 | ||
| 106 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) | 12 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) |
| 107 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) | 13 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) |
| 108 | #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) | ||
| 109 | #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) | ||
| 110 | #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) | ||
| 111 | #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) | 14 | #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) |
| 112 | #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) | 15 | #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) |
| 113 | #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) | ||
| 114 | #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 115 | #define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 116 | #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) | ||
| 117 | 16 | ||
| 118 | /* | ||
| 119 | * AIPS 2 | ||
| 120 | */ | ||
| 121 | #define AIPS2_BASE_ADDR 0x53F00000 | ||
| 122 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 | ||
| 123 | #define AIPS2_SIZE SZ_1M | ||
| 124 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) | ||
| 125 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) | 17 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) |
| 126 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) | 18 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) |
| 127 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) | ||
| 128 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) | ||
| 129 | #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) | ||
| 130 | #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) | ||
| 131 | #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) | ||
| 132 | #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) | 19 | #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) |
| 133 | #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) | 20 | #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) |
| 134 | #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) | ||
| 135 | #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) | ||
| 136 | #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) | ||
| 137 | #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) | 21 | #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) |
| 138 | #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) | ||
| 139 | #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) | ||
| 140 | #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) | ||
| 141 | #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) | ||
| 142 | #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) | ||
| 143 | #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) | ||
| 144 | #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) | ||
| 145 | |||
| 146 | /* | ||
| 147 | * ROMP and AVIC | ||
| 148 | */ | ||
| 149 | #define ROMP_BASE_ADDR 0x60000000 | ||
| 150 | #define ROMP_BASE_ADDR_VIRT 0xFC500000 | ||
| 151 | #define ROMP_SIZE SZ_1M | ||
| 152 | |||
| 153 | #define AVIC_BASE_ADDR 0x68000000 | ||
| 154 | #define AVIC_BASE_ADDR_VIRT 0xFC400000 | ||
| 155 | #define AVIC_SIZE SZ_1M | ||
| 156 | |||
| 157 | /* | ||
| 158 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 159 | */ | ||
| 160 | #define X_MEMC_BASE_ADDR 0xB8000000 | ||
| 161 | #define X_MEMC_BASE_ADDR_VIRT 0xFC320000 | ||
| 162 | #define X_MEMC_SIZE SZ_64K | ||
| 163 | 22 | ||
| 164 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | 23 | #define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) |
| 165 | #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 166 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 167 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 168 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 169 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR | ||
| 170 | 24 | ||
| 171 | /* | ||
| 172 | * Memory regions and CS | ||
| 173 | */ | ||
| 174 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
| 175 | #define CSD0_BASE_ADDR 0x80000000 | ||
| 176 | #define CSD1_BASE_ADDR 0x90000000 | ||
| 177 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 178 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 179 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 180 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 181 | |||
| 182 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 183 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 184 | #define CS4_SIZE SZ_32M | ||
| 185 | |||
| 186 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 187 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 188 | |||
| 189 | /*! | ||
| 190 | * This macro defines the physical to virtual address mapping for all the | ||
| 191 | * peripheral modules. It is used by passing in the physical address as x | ||
| 192 | * and returning the virtual address. If the physical address is not mapped, | ||
| 193 | * it returns 0xDEADBEEF | ||
| 194 | */ | ||
| 195 | #define IO_ADDRESS(x) \ | ||
| 196 | (void __iomem *) \ | ||
| 197 | (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\ | ||
| 198 | ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ | ||
| 199 | ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | ||
| 200 | ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ | ||
| 201 | ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ | ||
| 202 | ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ | ||
| 203 | ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ | ||
| 204 | ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ | ||
| 205 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ | ||
| 206 | 0xDEADBEEF) | ||
| 207 | |||
| 208 | /* | ||
| 209 | * define the address mapping macros: in physical address order | ||
| 210 | */ | ||
| 211 | |||
| 212 | #define IRAM_IO_ADDRESS(x) \ | ||
| 213 | (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT) | ||
| 214 | |||
| 215 | #define L2CC_IO_ADDRESS(x) \ | ||
| 216 | (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) | ||
| 217 | |||
| 218 | #define AIPS1_IO_ADDRESS(x) \ | ||
| 219 | (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) | ||
| 220 | |||
| 221 | #define SPBA0_IO_ADDRESS(x) \ | ||
| 222 | (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) | ||
| 223 | |||
| 224 | #define AIPS2_IO_ADDRESS(x) \ | ||
| 225 | (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) | ||
| 226 | |||
| 227 | #define ROMP_IO_ADDRESS(x) \ | ||
| 228 | (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) | ||
| 229 | |||
| 230 | #define AVIC_IO_ADDRESS(x) \ | ||
| 231 | (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) | ||
| 232 | |||
| 233 | #define CS4_IO_ADDRESS(x) \ | ||
| 234 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 235 | |||
| 236 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 237 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 238 | |||
| 239 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 240 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 241 | |||
| 242 | /* | ||
| 243 | * Interrupt numbers | ||
| 244 | */ | ||
| 245 | #define MXC_INT_PEN_ADS7843 0 | ||
| 246 | #define MXC_INT_RESV1 1 | ||
| 247 | #define MXC_INT_CS8900A 2 | ||
| 248 | #define MXC_INT_I2C3 3 | ||
| 249 | #define MXC_INT_I2C2 4 | ||
| 250 | #define MXC_INT_MPEG4_ENCODER 5 | 25 | #define MXC_INT_MPEG4_ENCODER 5 |
| 251 | #define MXC_INT_RTIC 6 | ||
| 252 | #define MXC_INT_FIRI 7 | 26 | #define MXC_INT_FIRI 7 |
| 253 | #define MXC_INT_MMC_SDHC2 8 | 27 | #define MX31_INT_MMC_SDHC2 8 |
| 254 | #define MXC_INT_MMC_SDHC1 9 | 28 | #define MXC_INT_MMC_SDHC1 9 |
| 255 | #define MXC_INT_I2C 10 | 29 | #define MX31_INT_SSI2 11 |
| 256 | #define MXC_INT_SSI2 11 | 30 | #define MX31_INT_SSI1 12 |
| 257 | #define MXC_INT_SSI1 12 | ||
| 258 | #define MXC_INT_CSPI2 13 | ||
| 259 | #define MXC_INT_CSPI1 14 | ||
| 260 | #define MXC_INT_ATA 15 | ||
| 261 | #define MXC_INT_MBX 16 | 31 | #define MXC_INT_MBX 16 |
| 262 | #define MXC_INT_CSPI3 17 | 32 | #define MXC_INT_CSPI3 17 |
| 263 | #define MXC_INT_UART3 18 | ||
| 264 | #define MXC_INT_IIM 19 | ||
| 265 | #define MXC_INT_SIM2 20 | 33 | #define MXC_INT_SIM2 20 |
| 266 | #define MXC_INT_SIM1 21 | 34 | #define MXC_INT_SIM1 21 |
| 267 | #define MXC_INT_RNGA 22 | 35 | #define MXC_INT_CCM_DVFS 31 |
| 268 | #define MXC_INT_EVTMON 23 | ||
| 269 | #define MXC_INT_KPP 24 | ||
| 270 | #define MXC_INT_RTC 25 | ||
| 271 | #define MXC_INT_PWM 26 | ||
| 272 | #define MXC_INT_EPIT2 27 | ||
| 273 | #define MXC_INT_EPIT1 28 | ||
| 274 | #define MXC_INT_GPT 29 | ||
| 275 | #define MXC_INT_RESV30 30 | ||
| 276 | #define MXC_INT_RESV31 31 | ||
| 277 | #define MXC_INT_UART2 32 | ||
| 278 | #define MXC_INT_NANDFC 33 | ||
| 279 | #define MXC_INT_SDMA 34 | ||
| 280 | #define MXC_INT_USB1 35 | 36 | #define MXC_INT_USB1 35 |
| 281 | #define MXC_INT_USB2 36 | 37 | #define MXC_INT_USB2 36 |
| 282 | #define MXC_INT_USB3 37 | 38 | #define MXC_INT_USB3 37 |
| 283 | #define MXC_INT_USB4 38 | 39 | #define MXC_INT_USB4 38 |
| 284 | #define MXC_INT_MSHC1 39 | ||
| 285 | #define MXC_INT_MSHC2 40 | 40 | #define MXC_INT_MSHC2 40 |
| 286 | #define MXC_INT_IPU_ERR 41 | ||
| 287 | #define MXC_INT_IPU_SYN 42 | ||
| 288 | #define MXC_INT_RESV43 43 | ||
| 289 | #define MXC_INT_RESV44 44 | ||
| 290 | #define MXC_INT_UART1 45 | ||
| 291 | #define MXC_INT_UART4 46 | 41 | #define MXC_INT_UART4 46 |
| 292 | #define MXC_INT_UART5 47 | 42 | #define MXC_INT_UART5 47 |
| 293 | #define MXC_INT_ECT 48 | ||
| 294 | #define MXC_INT_SCC_SCM 49 | ||
| 295 | #define MXC_INT_SCC_SMN 50 | ||
| 296 | #define MXC_INT_GPIO2 51 | ||
| 297 | #define MXC_INT_GPIO1 52 | ||
| 298 | #define MXC_INT_CCM 53 | 43 | #define MXC_INT_CCM 53 |
| 299 | #define MXC_INT_PCMCIA 54 | 44 | #define MXC_INT_PCMCIA 54 |
| 300 | #define MXC_INT_WDOG 55 | ||
| 301 | #define MXC_INT_GPIO3 56 | ||
| 302 | #define MXC_INT_RESV57 57 | ||
| 303 | #define MXC_INT_EXT_POWER 58 | ||
| 304 | #define MXC_INT_EXT_TEMPER 59 | ||
| 305 | #define MXC_INT_EXT_SENSOR60 60 | ||
| 306 | #define MXC_INT_EXT_SENSOR61 61 | ||
| 307 | #define MXC_INT_EXT_WDOG 62 | ||
| 308 | #define MXC_INT_EXT_TV 63 | ||
| 309 | |||
| 310 | #define PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 311 | |||
| 312 | /* silicon revisions specific to i.MX31 */ | ||
| 313 | #define CHIP_REV_1_0 0x10 | ||
| 314 | #define CHIP_REV_1_1 0x11 | ||
| 315 | #define CHIP_REV_1_2 0x12 | ||
| 316 | #define CHIP_REV_1_3 0x13 | ||
| 317 | #define CHIP_REV_2_0 0x20 | ||
| 318 | #define CHIP_REV_2_1 0x21 | ||
| 319 | #define CHIP_REV_2_2 0x22 | ||
| 320 | #define CHIP_REV_2_3 0x23 | ||
| 321 | #define CHIP_REV_3_0 0x30 | ||
| 322 | #define CHIP_REV_3_1 0x31 | ||
| 323 | #define CHIP_REV_3_2 0x32 | ||
| 324 | |||
| 325 | #define SYSTEM_REV_MIN CHIP_REV_1_0 | ||
| 326 | #define SYSTEM_REV_NUM 3 | ||
| 327 | |||
| 328 | /* gpio and gpio based interrupt handling */ | ||
| 329 | #define GPIO_DR 0x00 | ||
| 330 | #define GPIO_GDIR 0x04 | ||
| 331 | #define GPIO_PSR 0x08 | ||
| 332 | #define GPIO_ICR1 0x0C | ||
| 333 | #define GPIO_ICR2 0x10 | ||
| 334 | #define GPIO_IMR 0x14 | ||
| 335 | #define GPIO_ISR 0x18 | ||
| 336 | #define GPIO_INT_LOW_LEV 0x0 | ||
| 337 | #define GPIO_INT_HIGH_LEV 0x1 | ||
| 338 | #define GPIO_INT_RISE_EDGE 0x2 | ||
| 339 | #define GPIO_INT_FALL_EDGE 0x3 | ||
| 340 | #define GPIO_INT_NONE 0x4 | ||
| 341 | |||
| 342 | /* Mandatory defines used globally */ | ||
| 343 | |||
| 344 | /* this CPU supports up to 96 GPIOs */ | ||
| 345 | #define ARCH_NR_GPIOS 96 | ||
| 346 | |||
| 347 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | ||
| 348 | |||
| 349 | /* this is a i.MX31 CPU */ | ||
| 350 | #define cpu_is_mx31() (1) | ||
| 351 | |||
| 352 | extern unsigned int system_rev; | ||
| 353 | |||
| 354 | static inline int mx31_revision(void) | ||
| 355 | { | ||
| 356 | return system_rev; | ||
| 357 | } | ||
| 358 | #endif | ||
| 359 | 45 | ||
| 360 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h new file mode 100644 index 000000000000..6465fefb42e3 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx35.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * IRAM | ||
| 3 | */ | ||
| 4 | #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ | ||
| 5 | #define MX35_IRAM_SIZE SZ_128K | ||
| 6 | |||
| 7 | #define MXC_FEC_BASE_ADDR 0x50038000 | ||
| 8 | #define MX35_NFC_BASE_ADDR 0xBB000000 | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Interrupt numbers | ||
| 12 | */ | ||
| 13 | #define MXC_INT_OWIRE 2 | ||
| 14 | #define MX35_INT_MMC_SDHC1 7 | ||
| 15 | #define MXC_INT_MMC_SDHC2 8 | ||
| 16 | #define MXC_INT_MMC_SDHC3 9 | ||
| 17 | #define MX35_INT_SSI1 11 | ||
| 18 | #define MX35_INT_SSI2 12 | ||
| 19 | #define MXC_INT_GPU2D 16 | ||
| 20 | #define MXC_INT_ASRC 17 | ||
| 21 | #define MXC_INT_USBHS 35 | ||
| 22 | #define MXC_INT_USBOTG 37 | ||
| 23 | #define MXC_INT_ESAI 40 | ||
| 24 | #define MXC_INT_CAN1 43 | ||
| 25 | #define MXC_INT_CAN2 44 | ||
| 26 | #define MXC_INT_MLB 46 | ||
| 27 | #define MXC_INT_SPDIF 47 | ||
| 28 | #define MXC_INT_FEC 57 | ||
| 29 | |||
diff --git a/arch/arm/plat-mxc/include/mach/mx3fb.h b/arch/arm/plat-mxc/include/mach/mx3fb.h index e391a76ca87d..ac24c5c4bc83 100644 --- a/arch/arm/plat-mxc/include/mach/mx3fb.h +++ b/arch/arm/plat-mxc/include/mach/mx3fb.h | |||
| @@ -14,25 +14,25 @@ | |||
| 14 | #include <linux/fb.h> | 14 | #include <linux/fb.h> |
| 15 | 15 | ||
| 16 | /* Proprietary FB_SYNC_ flags */ | 16 | /* Proprietary FB_SYNC_ flags */ |
| 17 | #define FB_SYNC_OE_ACT_HIGH 0x80000000 | 17 | #define FB_SYNC_OE_ACT_HIGH 0x80000000 |
| 18 | #define FB_SYNC_CLK_INVERT 0x40000000 | 18 | #define FB_SYNC_CLK_INVERT 0x40000000 |
| 19 | #define FB_SYNC_DATA_INVERT 0x20000000 | 19 | #define FB_SYNC_DATA_INVERT 0x20000000 |
| 20 | #define FB_SYNC_CLK_IDLE_EN 0x10000000 | 20 | #define FB_SYNC_CLK_IDLE_EN 0x10000000 |
| 21 | #define FB_SYNC_SHARP_MODE 0x08000000 | 21 | #define FB_SYNC_SHARP_MODE 0x08000000 |
| 22 | #define FB_SYNC_SWAP_RGB 0x04000000 | 22 | #define FB_SYNC_SWAP_RGB 0x04000000 |
| 23 | #define FB_SYNC_CLK_SEL_EN 0x02000000 | 23 | #define FB_SYNC_CLK_SEL_EN 0x02000000 |
| 24 | 24 | ||
| 25 | /** | 25 | /** |
| 26 | * struct mx3fb_platform_data - mx3fb platform data | 26 | * struct mx3fb_platform_data - mx3fb platform data |
| 27 | * | 27 | * |
| 28 | * @dma_dev: pointer to the dma-device, used for dma-slave connection | 28 | * @dma_dev: pointer to the dma-device, used for dma-slave connection |
| 29 | * @mode: pointer to a platform-provided per mxc_register_fb() videomode | 29 | * @mode: pointer to a platform-provided per mxc_register_fb() videomode |
| 30 | */ | 30 | */ |
| 31 | struct mx3fb_platform_data { | 31 | struct mx3fb_platform_data { |
| 32 | struct device *dma_dev; | 32 | struct device *dma_dev; |
| 33 | const char *name; | 33 | const char *name; |
| 34 | const struct fb_videomode *mode; | 34 | const struct fb_videomode *mode; |
| 35 | int num_modes; | 35 | int num_modes; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | #endif | 38 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h new file mode 100644 index 000000000000..3878c6085d5c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx3x.h | |||
| @@ -0,0 +1,290 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_MX31_H__ | ||
| 12 | #define __ASM_ARCH_MXC_MX31_H__ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 15 | #error "Do not include directly." | ||
| 16 | #endif | ||
| 17 | |||
| 18 | /* | ||
| 19 | * MX31 memory map: | ||
| 20 | * | ||
| 21 | * Virt Phys Size What | ||
| 22 | * --------------------------------------------------------------------------- | ||
| 23 | * FC000000 43F00000 1M AIPS 1 | ||
| 24 | * FC100000 50000000 1M SPBA | ||
| 25 | * FC200000 53F00000 1M AIPS 2 | ||
| 26 | * FC500000 60000000 128M ROMPATCH | ||
| 27 | * FC400000 68000000 128M AVIC | ||
| 28 | * 70000000 256M IPU (MAX M2) | ||
| 29 | * 80000000 256M CSD0 SDRAM/DDR | ||
| 30 | * 90000000 256M CSD1 SDRAM/DDR | ||
| 31 | * A0000000 128M CS0 Flash | ||
| 32 | * A8000000 128M CS1 Flash | ||
| 33 | * B0000000 32M CS2 | ||
| 34 | * B2000000 32M CS3 | ||
| 35 | * F4000000 B4000000 32M CS4 | ||
| 36 | * B6000000 32M CS5 | ||
| 37 | * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 38 | * C0000000 64M PCMCIA/CF | ||
| 39 | */ | ||
| 40 | |||
| 41 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 42 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 43 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 44 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 45 | |||
| 46 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 47 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 48 | #define CS4_SIZE SZ_32M | ||
| 49 | |||
| 50 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 51 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 52 | |||
| 53 | /* | ||
| 54 | * L2CC | ||
| 55 | */ | ||
| 56 | #define L2CC_BASE_ADDR 0x30000000 | ||
| 57 | #define L2CC_SIZE SZ_1M | ||
| 58 | |||
| 59 | /* | ||
| 60 | * AIPS 1 | ||
| 61 | */ | ||
| 62 | #define AIPS1_BASE_ADDR 0x43F00000 | ||
| 63 | #define AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
| 64 | #define AIPS1_SIZE SZ_1M | ||
| 65 | |||
| 66 | #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) | ||
| 67 | #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) | ||
| 68 | #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) | ||
| 69 | #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) | ||
| 70 | #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) | ||
| 71 | #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) | ||
| 72 | #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) | ||
| 73 | #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) | ||
| 74 | #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) | ||
| 75 | #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) | ||
| 76 | #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) | ||
| 77 | #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) | ||
| 78 | #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) | ||
| 79 | #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) | ||
| 80 | #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) | ||
| 81 | #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) | ||
| 82 | #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) | ||
| 83 | #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) | ||
| 84 | |||
| 85 | /* | ||
| 86 | * SPBA global module enabled #0 | ||
| 87 | */ | ||
| 88 | #define SPBA0_BASE_ADDR 0x50000000 | ||
| 89 | #define SPBA0_BASE_ADDR_VIRT 0xFC100000 | ||
| 90 | #define SPBA0_SIZE SZ_1M | ||
| 91 | |||
| 92 | #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) | ||
| 93 | #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) | ||
| 94 | #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) | ||
| 95 | #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) | ||
| 96 | #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 97 | #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) | ||
| 98 | |||
| 99 | /* | ||
| 100 | * AIPS 2 | ||
| 101 | */ | ||
| 102 | #define AIPS2_BASE_ADDR 0x53F00000 | ||
| 103 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 | ||
| 104 | #define AIPS2_SIZE SZ_1M | ||
| 105 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) | ||
| 106 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) | ||
| 107 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) | ||
| 108 | #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) | ||
| 109 | #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) | ||
| 110 | #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) | ||
| 111 | #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) | ||
| 112 | #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) | ||
| 113 | #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) | ||
| 114 | #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) | ||
| 115 | #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) | ||
| 116 | #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) | ||
| 117 | #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) | ||
| 118 | #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) | ||
| 119 | #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) | ||
| 120 | #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) | ||
| 121 | |||
| 122 | /* | ||
| 123 | * ROMP and AVIC | ||
| 124 | */ | ||
| 125 | #define ROMP_BASE_ADDR 0x60000000 | ||
| 126 | #define ROMP_BASE_ADDR_VIRT 0xFC500000 | ||
| 127 | #define ROMP_SIZE SZ_1M | ||
| 128 | |||
| 129 | #define AVIC_BASE_ADDR 0x68000000 | ||
| 130 | #define AVIC_BASE_ADDR_VIRT 0xFC400000 | ||
| 131 | #define AVIC_SIZE SZ_1M | ||
| 132 | |||
| 133 | /* | ||
| 134 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 135 | */ | ||
| 136 | #define X_MEMC_BASE_ADDR 0xB8000000 | ||
| 137 | #define X_MEMC_BASE_ADDR_VIRT 0xFC320000 | ||
| 138 | #define X_MEMC_SIZE SZ_64K | ||
| 139 | |||
| 140 | #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 141 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 142 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 143 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 144 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR | ||
| 145 | |||
| 146 | /* | ||
| 147 | * Memory regions and CS | ||
| 148 | */ | ||
| 149 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
| 150 | #define CSD0_BASE_ADDR 0x80000000 | ||
| 151 | #define CSD1_BASE_ADDR 0x90000000 | ||
| 152 | |||
| 153 | /*! | ||
| 154 | * This macro defines the physical to virtual address mapping for all the | ||
| 155 | * peripheral modules. It is used by passing in the physical address as x | ||
| 156 | * and returning the virtual address. If the physical address is not mapped, | ||
| 157 | * it returns 0xDEADBEEF | ||
| 158 | */ | ||
| 159 | #define IO_ADDRESS(x) \ | ||
| 160 | (void __force __iomem *) \ | ||
| 161 | (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | ||
| 162 | ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ | ||
| 163 | ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ | ||
| 164 | ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ | ||
| 165 | ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ | ||
| 166 | ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ | ||
| 167 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ | ||
| 168 | 0xDEADBEEF) | ||
| 169 | |||
| 170 | /* | ||
| 171 | * define the address mapping macros: in physical address order | ||
| 172 | */ | ||
| 173 | #define L2CC_IO_ADDRESS(x) \ | ||
| 174 | (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) | ||
| 175 | |||
| 176 | #define AIPS1_IO_ADDRESS(x) \ | ||
| 177 | (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) | ||
| 178 | |||
| 179 | #define SPBA0_IO_ADDRESS(x) \ | ||
| 180 | (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) | ||
| 181 | |||
| 182 | #define AIPS2_IO_ADDRESS(x) \ | ||
| 183 | (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) | ||
| 184 | |||
| 185 | #define ROMP_IO_ADDRESS(x) \ | ||
| 186 | (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) | ||
| 187 | |||
| 188 | #define AVIC_IO_ADDRESS(x) \ | ||
| 189 | (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) | ||
| 190 | |||
| 191 | #define CS4_IO_ADDRESS(x) \ | ||
| 192 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 193 | |||
| 194 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 195 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 196 | |||
| 197 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 198 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 199 | |||
| 200 | /* | ||
| 201 | * Interrupt numbers | ||
| 202 | */ | ||
| 203 | #define MXC_INT_I2C3 3 | ||
| 204 | #define MXC_INT_I2C2 4 | ||
| 205 | #define MXC_INT_RTIC 6 | ||
| 206 | #define MXC_INT_I2C 10 | ||
| 207 | #define MXC_INT_CSPI2 13 | ||
| 208 | #define MXC_INT_CSPI1 14 | ||
| 209 | #define MXC_INT_ATA 15 | ||
| 210 | #define MXC_INT_UART3 18 | ||
| 211 | #define MXC_INT_IIM 19 | ||
| 212 | #define MXC_INT_RNGA 22 | ||
| 213 | #define MXC_INT_EVTMON 23 | ||
| 214 | #define MXC_INT_KPP 24 | ||
| 215 | #define MXC_INT_RTC 25 | ||
| 216 | #define MXC_INT_PWM 26 | ||
| 217 | #define MXC_INT_EPIT2 27 | ||
| 218 | #define MXC_INT_EPIT1 28 | ||
| 219 | #define MXC_INT_GPT 29 | ||
| 220 | #define MXC_INT_POWER_FAIL 30 | ||
| 221 | #define MXC_INT_UART2 32 | ||
| 222 | #define MXC_INT_NANDFC 33 | ||
| 223 | #define MXC_INT_SDMA 34 | ||
| 224 | #define MXC_INT_MSHC1 39 | ||
| 225 | #define MXC_INT_IPU_ERR 41 | ||
| 226 | #define MXC_INT_IPU_SYN 42 | ||
| 227 | #define MXC_INT_UART1 45 | ||
| 228 | #define MXC_INT_ECT 48 | ||
| 229 | #define MXC_INT_SCC_SCM 49 | ||
| 230 | #define MXC_INT_SCC_SMN 50 | ||
| 231 | #define MXC_INT_GPIO2 51 | ||
| 232 | #define MXC_INT_GPIO1 52 | ||
| 233 | #define MXC_INT_WDOG 55 | ||
| 234 | #define MXC_INT_GPIO3 56 | ||
| 235 | #define MXC_INT_EXT_POWER 58 | ||
| 236 | #define MXC_INT_EXT_TEMPER 59 | ||
| 237 | #define MXC_INT_EXT_SENSOR60 60 | ||
| 238 | #define MXC_INT_EXT_SENSOR61 61 | ||
| 239 | #define MXC_INT_EXT_WDOG 62 | ||
| 240 | #define MXC_INT_EXT_TV 63 | ||
| 241 | |||
| 242 | #define PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 243 | |||
| 244 | /* silicon revisions specific to i.MX31 */ | ||
| 245 | #define CHIP_REV_1_0 0x10 | ||
| 246 | #define CHIP_REV_1_1 0x11 | ||
| 247 | #define CHIP_REV_1_2 0x12 | ||
| 248 | #define CHIP_REV_1_3 0x13 | ||
| 249 | #define CHIP_REV_2_0 0x20 | ||
| 250 | #define CHIP_REV_2_1 0x21 | ||
| 251 | #define CHIP_REV_2_2 0x22 | ||
| 252 | #define CHIP_REV_2_3 0x23 | ||
| 253 | #define CHIP_REV_3_0 0x30 | ||
| 254 | #define CHIP_REV_3_1 0x31 | ||
| 255 | #define CHIP_REV_3_2 0x32 | ||
| 256 | |||
| 257 | #define SYSTEM_REV_MIN CHIP_REV_1_0 | ||
| 258 | #define SYSTEM_REV_NUM 3 | ||
| 259 | |||
| 260 | /* gpio and gpio based interrupt handling */ | ||
| 261 | #define GPIO_DR 0x00 | ||
| 262 | #define GPIO_GDIR 0x04 | ||
| 263 | #define GPIO_PSR 0x08 | ||
| 264 | #define GPIO_ICR1 0x0C | ||
| 265 | #define GPIO_ICR2 0x10 | ||
| 266 | #define GPIO_IMR 0x14 | ||
| 267 | #define GPIO_ISR 0x18 | ||
| 268 | #define GPIO_INT_LOW_LEV 0x0 | ||
| 269 | #define GPIO_INT_HIGH_LEV 0x1 | ||
| 270 | #define GPIO_INT_RISE_EDGE 0x2 | ||
| 271 | #define GPIO_INT_FALL_EDGE 0x3 | ||
| 272 | #define GPIO_INT_NONE 0x4 | ||
| 273 | |||
| 274 | /* Mandatory defines used globally */ | ||
| 275 | |||
| 276 | /* this CPU supports up to 96 GPIOs */ | ||
| 277 | #define ARCH_NR_GPIOS 96 | ||
| 278 | |||
| 279 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | ||
| 280 | |||
| 281 | extern unsigned int system_rev; | ||
| 282 | |||
| 283 | static inline int mx31_revision(void) | ||
| 284 | { | ||
| 285 | return system_rev; | ||
| 286 | } | ||
| 287 | #endif | ||
| 288 | |||
| 289 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | ||
| 290 | |||
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index f6caab062131..5fa2a07f4eaf 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h | |||
| @@ -24,13 +24,74 @@ | |||
| 24 | #error "Do not include directly." | 24 | #error "Do not include directly." |
| 25 | #endif | 25 | #endif |
| 26 | 26 | ||
| 27 | /* clean up all things that are not used */ | 27 | #define MXC_CPU_MX1 1 |
| 28 | #ifndef CONFIG_ARCH_MX3 | 28 | #define MXC_CPU_MX21 21 |
| 29 | # define cpu_is_mx31() (0) | 29 | #define MXC_CPU_MX27 27 |
| 30 | #define MXC_CPU_MX31 31 | ||
| 31 | #define MXC_CPU_MX35 35 | ||
| 32 | |||
| 33 | #ifndef __ASSEMBLY__ | ||
| 34 | extern unsigned int __mxc_cpu_type; | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #ifdef CONFIG_ARCH_MX1 | ||
| 38 | # ifdef mxc_cpu_type | ||
| 39 | # undef mxc_cpu_type | ||
| 40 | # define mxc_cpu_type __mxc_cpu_type | ||
| 41 | # else | ||
| 42 | # define mxc_cpu_type MXC_CPU_MX1 | ||
| 43 | # endif | ||
| 44 | # define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) | ||
| 45 | #else | ||
| 46 | # define cpu_is_mx1() (0) | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #ifdef CONFIG_MACH_MX21 | ||
| 50 | # ifdef mxc_cpu_type | ||
| 51 | # undef mxc_cpu_type | ||
| 52 | # define mxc_cpu_type __mxc_cpu_type | ||
| 53 | # else | ||
| 54 | # define mxc_cpu_type MXC_CPU_MX21 | ||
| 55 | # endif | ||
| 56 | # define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) | ||
| 57 | #else | ||
| 58 | # define cpu_is_mx21() (0) | ||
| 30 | #endif | 59 | #endif |
| 31 | 60 | ||
| 32 | #ifndef CONFIG_MACH_MX27 | 61 | #ifdef CONFIG_MACH_MX27 |
| 33 | # define cpu_is_mx27() (0) | 62 | # ifdef mxc_cpu_type |
| 63 | # undef mxc_cpu_type | ||
| 64 | # define mxc_cpu_type __mxc_cpu_type | ||
| 65 | # else | ||
| 66 | # define mxc_cpu_type MXC_CPU_MX27 | ||
| 67 | # endif | ||
| 68 | # define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) | ||
| 69 | #else | ||
| 70 | # define cpu_is_mx27() (0) | ||
| 71 | #endif | ||
| 72 | |||
| 73 | #ifdef CONFIG_ARCH_MX31 | ||
| 74 | # ifdef mxc_cpu_type | ||
| 75 | # undef mxc_cpu_type | ||
| 76 | # define mxc_cpu_type __mxc_cpu_type | ||
| 77 | # else | ||
| 78 | # define mxc_cpu_type MXC_CPU_MX31 | ||
| 79 | # endif | ||
| 80 | # define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) | ||
| 81 | #else | ||
| 82 | # define cpu_is_mx31() (0) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | #ifdef CONFIG_ARCH_MX35 | ||
| 86 | # ifdef mxc_cpu_type | ||
| 87 | # undef mxc_cpu_type | ||
| 88 | # define mxc_cpu_type __mxc_cpu_type | ||
| 89 | # else | ||
| 90 | # define mxc_cpu_type MXC_CPU_MX35 | ||
| 91 | # endif | ||
| 92 | # define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) | ||
| 93 | #else | ||
| 94 | # define cpu_is_mx35() (0) | ||
| 34 | #endif | 95 | #endif |
| 35 | 96 | ||
| 36 | #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) | 97 | #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) |
| @@ -39,4 +100,7 @@ | |||
| 39 | #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) | 100 | #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) |
| 40 | #endif | 101 | #endif |
| 41 | 102 | ||
| 103 | #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) | ||
| 104 | #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) | ||
| 105 | |||
| 42 | #endif /* __ASM_ARCH_MXC_H__ */ | 106 | #endif /* __ASM_ARCH_MXC_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index bbfc37465fc5..e56241af870e 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h | |||
| @@ -26,9 +26,6 @@ static inline void arch_idle(void) | |||
| 26 | cpu_do_idle(); | 26 | cpu_do_idle(); |
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | static inline void arch_reset(char mode) | 29 | void arch_reset(char mode, const char *cmd); |
| 30 | { | ||
| 31 | cpu_reset(0); | ||
| 32 | } | ||
| 33 | 30 | ||
| 34 | #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ | 31 | #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ |
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c index df6f18395686..a37163ce280b 100644 --- a/arch/arm/plat-mxc/iomux-mx1-mx2.c +++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c | |||
| @@ -32,7 +32,7 @@ | |||
| 32 | 32 | ||
| 33 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 35 | #include <mach/iomux-mx1-mx2.h> | 35 | #include <mach/iomux.h> |
| 36 | 36 | ||
| 37 | void mxc_gpio_mode(int gpio_mode) | 37 | void mxc_gpio_mode(int gpio_mode) |
| 38 | { | 38 | { |
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c new file mode 100644 index 000000000000..9bffbc507cc2 --- /dev/null +++ b/arch/arm/plat-mxc/pwm.c | |||
| @@ -0,0 +1,300 @@ | |||
| 1 | /* | ||
| 2 | * simple driver for PWM (Pulse Width Modulator) controller | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/err.h> | ||
| 15 | #include <linux/clk.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/pwm.h> | ||
| 18 | |||
| 19 | #if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21 | ||
| 20 | #define PWM_VER_1 | ||
| 21 | |||
| 22 | #define PWMCR 0x00 /* PWM Control Register */ | ||
| 23 | #define PWMSR 0x04 /* PWM Sample Register */ | ||
| 24 | #define PWMPR 0x08 /* PWM Period Register */ | ||
| 25 | #define PWMCNR 0x0C /* PWM Counter Register */ | ||
| 26 | |||
| 27 | #define PWMCR_HCTR (1 << 18) /* Halfword FIFO Data Swapping */ | ||
| 28 | #define PWMCR_BCTR (1 << 17) /* Byte FIFO Data Swapping */ | ||
| 29 | #define PWMCR_SWR (1 << 16) /* Software Reset */ | ||
| 30 | #define PWMCR_CLKSRC_PERCLK (0 << 15) /* PERCLK Clock Source */ | ||
| 31 | #define PWMCR_CLKSRC_CLK32 (1 << 15) /* 32KHz Clock Source */ | ||
| 32 | #define PWMCR_PRESCALER(x) (((x - 1) & 0x7F) << 8) /* PRESCALER */ | ||
| 33 | #define PWMCR_IRQ (1 << 7) /* Interrupt Request */ | ||
| 34 | #define PWMCR_IRQEN (1 << 6) /* Interrupt Request Enable */ | ||
| 35 | #define PWMCR_FIFOAV (1 << 5) /* FIFO Available */ | ||
| 36 | #define PWMCR_EN (1 << 4) /* Enables/Disables the PWM */ | ||
| 37 | #define PWMCR_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ | ||
| 38 | #define PWMCR_DIV(x) (((x) & 0x03) << 0) /* Clock divider 2/4/8/16 */ | ||
| 39 | |||
| 40 | #define MAX_DIV (128 * 16) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31 | ||
| 44 | #define PWM_VER_2 | ||
| 45 | |||
| 46 | #define PWMCR 0x00 /* PWM Control Register */ | ||
| 47 | #define PWMSR 0x04 /* PWM Status Register */ | ||
| 48 | #define PWMIR 0x08 /* PWM Interrupt Register */ | ||
| 49 | #define PWMSAR 0x0C /* PWM Sample Register */ | ||
| 50 | #define PWMPR 0x10 /* PWM Period Register */ | ||
| 51 | #define PWMCNR 0x14 /* PWM Counter Register */ | ||
| 52 | |||
| 53 | #define PWMCR_EN (1 << 0) /* Enables/Disables the PWM */ | ||
| 54 | #define PWMCR_REPEAT(x) (((x) & 0x03) << 1) /* Sample Repeats */ | ||
| 55 | #define PWMCR_SWR (1 << 3) /* Software Reset */ | ||
| 56 | #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)/* PRESCALER */ | ||
| 57 | #define PWMCR_CLKSRC(x) (((x) & 0x3) << 16) | ||
| 58 | #define PWMCR_CLKSRC_OFF (0 << 16) | ||
| 59 | #define PWMCR_CLKSRC_IPG (1 << 16) | ||
| 60 | #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) | ||
| 61 | #define PWMCR_CLKSRC_CLK32 (3 << 16) | ||
| 62 | #define PWMCR_POUTC | ||
| 63 | #define PWMCR_HCTR (1 << 20) /* Halfword FIFO Data Swapping */ | ||
| 64 | #define PWMCR_BCTR (1 << 21) /* Byte FIFO Data Swapping */ | ||
| 65 | #define PWMCR_DBGEN (1 << 22) /* Debug Mode */ | ||
| 66 | #define PWMCR_WAITEN (1 << 23) /* Wait Mode */ | ||
| 67 | #define PWMCR_DOZEN (1 << 24) /* Doze Mode */ | ||
| 68 | #define PWMCR_STOPEN (1 << 25) /* Stop Mode */ | ||
| 69 | #define PWMCR_FWM(x) (((x) & 0x3) << 26) /* FIFO Water Mark */ | ||
| 70 | |||
| 71 | #define MAX_DIV 4096 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ | ||
| 75 | #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ | ||
| 76 | #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ | ||
| 77 | |||
| 78 | struct pwm_device { | ||
| 79 | struct list_head node; | ||
| 80 | struct platform_device *pdev; | ||
| 81 | |||
| 82 | const char *label; | ||
| 83 | struct clk *clk; | ||
| 84 | |||
| 85 | int clk_enabled; | ||
| 86 | void __iomem *mmio_base; | ||
| 87 | |||
| 88 | unsigned int use_count; | ||
| 89 | unsigned int pwm_id; | ||
| 90 | }; | ||
| 91 | |||
| 92 | int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) | ||
| 93 | { | ||
| 94 | unsigned long long c; | ||
| 95 | unsigned long period_cycles, duty_cycles, prescale; | ||
| 96 | |||
| 97 | if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) | ||
| 98 | return -EINVAL; | ||
| 99 | |||
| 100 | c = clk_get_rate(pwm->clk); | ||
| 101 | c = c * period_ns; | ||
| 102 | do_div(c, 1000000000); | ||
| 103 | period_cycles = c; | ||
| 104 | |||
| 105 | prescale = period_cycles / 0x10000 + 1; | ||
| 106 | |||
| 107 | period_cycles /= prescale; | ||
| 108 | c = (unsigned long long)period_cycles * duty_ns; | ||
| 109 | do_div(c, period_ns); | ||
| 110 | duty_cycles = c; | ||
| 111 | |||
| 112 | #ifdef PWM_VER_2 | ||
| 113 | writel(duty_cycles, pwm->mmio_base + PWMSAR); | ||
| 114 | writel(period_cycles, pwm->mmio_base + PWMPR); | ||
| 115 | writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN, | ||
| 116 | pwm->mmio_base + PWMCR); | ||
| 117 | #elif defined PWM_VER_1 | ||
| 118 | #error PWM not yet working on MX1 / MX21 | ||
| 119 | #endif | ||
| 120 | |||
| 121 | return 0; | ||
| 122 | } | ||
| 123 | EXPORT_SYMBOL(pwm_config); | ||
| 124 | |||
| 125 | int pwm_enable(struct pwm_device *pwm) | ||
| 126 | { | ||
| 127 | int rc = 0; | ||
| 128 | |||
| 129 | if (!pwm->clk_enabled) { | ||
| 130 | rc = clk_enable(pwm->clk); | ||
| 131 | if (!rc) | ||
| 132 | pwm->clk_enabled = 1; | ||
| 133 | } | ||
| 134 | return rc; | ||
| 135 | } | ||
| 136 | EXPORT_SYMBOL(pwm_enable); | ||
| 137 | |||
| 138 | void pwm_disable(struct pwm_device *pwm) | ||
| 139 | { | ||
| 140 | if (pwm->clk_enabled) { | ||
| 141 | clk_disable(pwm->clk); | ||
| 142 | pwm->clk_enabled = 0; | ||
| 143 | } | ||
| 144 | } | ||
| 145 | EXPORT_SYMBOL(pwm_disable); | ||
| 146 | |||
| 147 | static DEFINE_MUTEX(pwm_lock); | ||
| 148 | static LIST_HEAD(pwm_list); | ||
| 149 | |||
| 150 | struct pwm_device *pwm_request(int pwm_id, const char *label) | ||
| 151 | { | ||
| 152 | struct pwm_device *pwm; | ||
| 153 | int found = 0; | ||
| 154 | |||
| 155 | mutex_lock(&pwm_lock); | ||
| 156 | |||
| 157 | list_for_each_entry(pwm, &pwm_list, node) { | ||
| 158 | if (pwm->pwm_id == pwm_id) { | ||
| 159 | found = 1; | ||
| 160 | break; | ||
| 161 | } | ||
| 162 | } | ||
| 163 | |||
| 164 | if (found) { | ||
| 165 | if (pwm->use_count == 0) { | ||
| 166 | pwm->use_count++; | ||
| 167 | pwm->label = label; | ||
| 168 | } else | ||
| 169 | pwm = ERR_PTR(-EBUSY); | ||
| 170 | } else | ||
| 171 | pwm = ERR_PTR(-ENOENT); | ||
| 172 | |||
| 173 | mutex_unlock(&pwm_lock); | ||
| 174 | return pwm; | ||
| 175 | } | ||
| 176 | EXPORT_SYMBOL(pwm_request); | ||
| 177 | |||
| 178 | void pwm_free(struct pwm_device *pwm) | ||
| 179 | { | ||
| 180 | mutex_lock(&pwm_lock); | ||
| 181 | |||
| 182 | if (pwm->use_count) { | ||
| 183 | pwm->use_count--; | ||
| 184 | pwm->label = NULL; | ||
| 185 | } else | ||
| 186 | pr_warning("PWM device already freed\n"); | ||
| 187 | |||
| 188 | mutex_unlock(&pwm_lock); | ||
| 189 | } | ||
| 190 | EXPORT_SYMBOL(pwm_free); | ||
| 191 | |||
| 192 | static int __devinit mxc_pwm_probe(struct platform_device *pdev) | ||
| 193 | { | ||
| 194 | struct pwm_device *pwm; | ||
| 195 | struct resource *r; | ||
| 196 | int ret = 0; | ||
| 197 | |||
| 198 | pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); | ||
| 199 | if (pwm == NULL) { | ||
| 200 | dev_err(&pdev->dev, "failed to allocate memory\n"); | ||
| 201 | return -ENOMEM; | ||
| 202 | } | ||
| 203 | |||
| 204 | pwm->clk = clk_get(&pdev->dev, "pwm"); | ||
| 205 | |||
| 206 | if (IS_ERR(pwm->clk)) { | ||
| 207 | ret = PTR_ERR(pwm->clk); | ||
| 208 | goto err_free; | ||
| 209 | } | ||
| 210 | |||
| 211 | pwm->clk_enabled = 0; | ||
| 212 | |||
| 213 | pwm->use_count = 0; | ||
| 214 | pwm->pwm_id = pdev->id; | ||
| 215 | pwm->pdev = pdev; | ||
| 216 | |||
| 217 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 218 | if (r == NULL) { | ||
| 219 | dev_err(&pdev->dev, "no memory resource defined\n"); | ||
| 220 | ret = -ENODEV; | ||
| 221 | goto err_free_clk; | ||
| 222 | } | ||
| 223 | |||
| 224 | r = request_mem_region(r->start, r->end - r->start + 1, pdev->name); | ||
| 225 | if (r == NULL) { | ||
| 226 | dev_err(&pdev->dev, "failed to request memory resource\n"); | ||
| 227 | ret = -EBUSY; | ||
| 228 | goto err_free_clk; | ||
| 229 | } | ||
| 230 | |||
| 231 | pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); | ||
| 232 | if (pwm->mmio_base == NULL) { | ||
| 233 | dev_err(&pdev->dev, "failed to ioremap() registers\n"); | ||
| 234 | ret = -ENODEV; | ||
| 235 | goto err_free_mem; | ||
| 236 | } | ||
| 237 | |||
| 238 | mutex_lock(&pwm_lock); | ||
| 239 | list_add_tail(&pwm->node, &pwm_list); | ||
| 240 | mutex_unlock(&pwm_lock); | ||
| 241 | |||
| 242 | platform_set_drvdata(pdev, pwm); | ||
| 243 | return 0; | ||
| 244 | |||
| 245 | err_free_mem: | ||
| 246 | release_mem_region(r->start, r->end - r->start + 1); | ||
| 247 | err_free_clk: | ||
| 248 | clk_put(pwm->clk); | ||
| 249 | err_free: | ||
| 250 | kfree(pwm); | ||
| 251 | return ret; | ||
| 252 | } | ||
| 253 | |||
| 254 | static int __devexit mxc_pwm_remove(struct platform_device *pdev) | ||
| 255 | { | ||
| 256 | struct pwm_device *pwm; | ||
| 257 | struct resource *r; | ||
| 258 | |||
| 259 | pwm = platform_get_drvdata(pdev); | ||
| 260 | if (pwm == NULL) | ||
| 261 | return -ENODEV; | ||
| 262 | |||
| 263 | mutex_lock(&pwm_lock); | ||
| 264 | list_del(&pwm->node); | ||
| 265 | mutex_unlock(&pwm_lock); | ||
| 266 | |||
| 267 | iounmap(pwm->mmio_base); | ||
| 268 | |||
| 269 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 270 | release_mem_region(r->start, r->end - r->start + 1); | ||
| 271 | |||
| 272 | clk_put(pwm->clk); | ||
| 273 | |||
| 274 | kfree(pwm); | ||
| 275 | return 0; | ||
| 276 | } | ||
| 277 | |||
| 278 | static struct platform_driver mxc_pwm_driver = { | ||
| 279 | .driver = { | ||
| 280 | .name = "mxc_pwm", | ||
| 281 | }, | ||
| 282 | .probe = mxc_pwm_probe, | ||
| 283 | .remove = __devexit_p(mxc_pwm_remove), | ||
| 284 | }; | ||
| 285 | |||
| 286 | static int __init mxc_pwm_init(void) | ||
| 287 | { | ||
| 288 | return platform_driver_register(&mxc_pwm_driver); | ||
| 289 | } | ||
| 290 | arch_initcall(mxc_pwm_init); | ||
| 291 | |||
| 292 | static void __exit mxc_pwm_exit(void) | ||
| 293 | { | ||
| 294 | platform_driver_unregister(&mxc_pwm_driver); | ||
| 295 | } | ||
| 296 | module_exit(mxc_pwm_exit); | ||
| 297 | |||
| 298 | MODULE_LICENSE("GPL v2"); | ||
| 299 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); | ||
| 300 | |||
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/plat-mxc/system.c index 7b8269719d11..79c37577c916 100644 --- a/arch/arm/mach-mx2/system.c +++ b/arch/arm/plat-mxc/system.c | |||
| @@ -3,6 +3,7 @@ | |||
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
| 4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | 4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | 5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com | ||
| 6 | * | 7 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by | 9 | * it under the terms of the GNU General Public License as published by |
| @@ -22,42 +23,45 @@ | |||
| 22 | #include <linux/kernel.h> | 23 | #include <linux/kernel.h> |
| 23 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
| 24 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | #include <linux/err.h> | ||
| 27 | #include <linux/delay.h> | ||
| 25 | 28 | ||
| 26 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 27 | #include <asm/proc-fns.h> | 30 | #include <asm/proc-fns.h> |
| 28 | #include <asm/system.h> | 31 | #include <asm/system.h> |
| 29 | 32 | ||
| 30 | /* | 33 | #ifdef CONFIG_ARCH_MX1 |
| 31 | * Put the CPU into idle mode. It is called by default_idle() | 34 | #define WDOG_WCR_REG IO_ADDRESS(WDT_BASE_ADDR) |
| 32 | * in process.c file. | 35 | #define WDOG_WCR_ENABLE (1 << 0) |
| 33 | */ | 36 | #else |
| 34 | void arch_idle(void) | 37 | #define WDOG_WCR_REG IO_ADDRESS(WDOG_BASE_ADDR) |
| 35 | { | 38 | #define WDOG_WCR_ENABLE (1 << 2) |
| 36 | /* | 39 | #endif |
| 37 | * This should do all the clock switching | ||
| 38 | * and wait for interrupt tricks. | ||
| 39 | */ | ||
| 40 | cpu_do_idle(); | ||
| 41 | } | ||
| 42 | |||
| 43 | #define WDOG_WCR_REG IO_ADDRESS(WDOG_BASE_ADDR) | ||
| 44 | #define WDOG_WCR_SRS (1 << 4) | ||
| 45 | 40 | ||
| 46 | /* | 41 | /* |
| 47 | * Reset the system. It is called by machine_restart(). | 42 | * Reset the system. It is called by machine_restart(). |
| 48 | */ | 43 | */ |
| 49 | void arch_reset(char mode) | 44 | void arch_reset(char mode, const char *cmd) |
| 50 | { | 45 | { |
| 51 | struct clk *clk; | 46 | if (!cpu_is_mx1()) { |
| 47 | struct clk *clk; | ||
| 52 | 48 | ||
| 53 | clk = clk_get(NULL, "wdog_clk"); | 49 | clk = clk_get_sys("imx-wdt.0", NULL); |
| 54 | if (!clk) { | 50 | if (!IS_ERR(clk)) |
| 55 | printk(KERN_ERR"Cannot activate the watchdog. Giving up\n"); | 51 | clk_enable(clk); |
| 56 | return; | ||
| 57 | } | 52 | } |
| 58 | 53 | ||
| 59 | clk_enable(clk); | ||
| 60 | |||
| 61 | /* Assert SRS signal */ | 54 | /* Assert SRS signal */ |
| 62 | __raw_writew(__raw_readw(WDOG_WCR_REG) & ~WDOG_WCR_SRS, WDOG_WCR_REG); | 55 | __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG); |
| 56 | |||
| 57 | /* wait for reset to assert... */ | ||
| 58 | mdelay(500); | ||
| 59 | |||
| 60 | printk(KERN_ERR "Watchdog reset failed to assert reset\n"); | ||
| 61 | |||
| 62 | /* delay to allow the serial port to show the message */ | ||
| 63 | mdelay(50); | ||
| 64 | |||
| 65 | /* we'll take a jump through zero as a poor second */ | ||
| 66 | cpu_reset(0); | ||
| 63 | } | 67 | } |
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 758a1293bcfa..ef1b3cd85bd3 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c | |||
| @@ -34,9 +34,6 @@ | |||
| 34 | static struct clock_event_device clockevent_mxc; | 34 | static struct clock_event_device clockevent_mxc; |
| 35 | static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; | 35 | static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; |
| 36 | 36 | ||
| 37 | /* clock source for the timer */ | ||
| 38 | static struct clk *timer_clk; | ||
| 39 | |||
| 40 | /* clock source */ | 37 | /* clock source */ |
| 41 | 38 | ||
| 42 | static cycle_t mxc_get_cycles(void) | 39 | static cycle_t mxc_get_cycles(void) |
| @@ -53,13 +50,11 @@ static struct clocksource clocksource_mxc = { | |||
| 53 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 50 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 54 | }; | 51 | }; |
| 55 | 52 | ||
| 56 | static int __init mxc_clocksource_init(void) | 53 | static int __init mxc_clocksource_init(struct clk *timer_clk) |
| 57 | { | 54 | { |
| 58 | unsigned int clock; | 55 | unsigned int c = clk_get_rate(timer_clk); |
| 59 | |||
| 60 | clock = clk_get_rate(timer_clk); | ||
| 61 | 56 | ||
| 62 | clocksource_mxc.mult = clocksource_hz2mult(clock, | 57 | clocksource_mxc.mult = clocksource_hz2mult(c, |
| 63 | clocksource_mxc.shift); | 58 | clocksource_mxc.shift); |
| 64 | clocksource_register(&clocksource_mxc); | 59 | clocksource_register(&clocksource_mxc); |
| 65 | 60 | ||
| @@ -177,13 +172,11 @@ static struct clock_event_device clockevent_mxc = { | |||
| 177 | .rating = 200, | 172 | .rating = 200, |
| 178 | }; | 173 | }; |
| 179 | 174 | ||
| 180 | static int __init mxc_clockevent_init(void) | 175 | static int __init mxc_clockevent_init(struct clk *timer_clk) |
| 181 | { | 176 | { |
| 182 | unsigned int clock; | 177 | unsigned int c = clk_get_rate(timer_clk); |
| 183 | |||
| 184 | clock = clk_get_rate(timer_clk); | ||
| 185 | 178 | ||
| 186 | clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC, | 179 | clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, |
| 187 | clockevent_mxc.shift); | 180 | clockevent_mxc.shift); |
| 188 | clockevent_mxc.max_delta_ns = | 181 | clockevent_mxc.max_delta_ns = |
| 189 | clockevent_delta2ns(0xfffffffe, &clockevent_mxc); | 182 | clockevent_delta2ns(0xfffffffe, &clockevent_mxc); |
| @@ -197,14 +190,8 @@ static int __init mxc_clockevent_init(void) | |||
| 197 | return 0; | 190 | return 0; |
| 198 | } | 191 | } |
| 199 | 192 | ||
| 200 | void __init mxc_timer_init(const char *clk_timer) | 193 | void __init mxc_timer_init(struct clk *timer_clk) |
| 201 | { | 194 | { |
| 202 | timer_clk = clk_get(NULL, clk_timer); | ||
| 203 | if (!timer_clk) { | ||
| 204 | printk(KERN_ERR"Cannot determine timer clock. Giving up.\n"); | ||
| 205 | return; | ||
| 206 | } | ||
| 207 | |||
| 208 | clk_enable(timer_clk); | 195 | clk_enable(timer_clk); |
| 209 | 196 | ||
| 210 | /* | 197 | /* |
| @@ -219,10 +206,9 @@ void __init mxc_timer_init(const char *clk_timer) | |||
| 219 | TIMER_BASE + MXC_TCTL); | 206 | TIMER_BASE + MXC_TCTL); |
| 220 | 207 | ||
| 221 | /* init and register the timer to the framework */ | 208 | /* init and register the timer to the framework */ |
| 222 | mxc_clocksource_init(); | 209 | mxc_clocksource_init(timer_clk); |
| 223 | mxc_clockevent_init(); | 210 | mxc_clockevent_init(timer_clk); |
| 224 | 211 | ||
| 225 | /* Make irqs happen */ | 212 | /* Make irqs happen */ |
| 226 | setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); | 213 | setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); |
| 227 | } | 214 | } |
| 228 | |||
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 46d3b0b9ce69..9dd68fafb374 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -11,14 +11,17 @@ choice | |||
| 11 | 11 | ||
| 12 | config ARCH_OMAP1 | 12 | config ARCH_OMAP1 |
| 13 | bool "TI OMAP1" | 13 | bool "TI OMAP1" |
| 14 | select COMMON_CLKDEV | ||
| 14 | 15 | ||
| 15 | config ARCH_OMAP2 | 16 | config ARCH_OMAP2 |
| 16 | bool "TI OMAP2" | 17 | bool "TI OMAP2" |
| 17 | select CPU_V6 | 18 | select CPU_V6 |
| 19 | select COMMON_CLKDEV | ||
| 18 | 20 | ||
| 19 | config ARCH_OMAP3 | 21 | config ARCH_OMAP3 |
| 20 | bool "TI OMAP3" | 22 | bool "TI OMAP3" |
| 21 | select CPU_V7 | 23 | select CPU_V7 |
| 24 | select COMMON_CLKDEV | ||
| 22 | 25 | ||
| 23 | endchoice | 26 | endchoice |
| 24 | 27 | ||
| @@ -104,6 +107,14 @@ config OMAP_MCBSP | |||
| 104 | Say Y here if you want support for the OMAP Multichannel | 107 | Say Y here if you want support for the OMAP Multichannel |
| 105 | Buffered Serial Port. | 108 | Buffered Serial Port. |
| 106 | 109 | ||
| 110 | config OMAP_MBOX_FWK | ||
| 111 | tristate "Mailbox framework support" | ||
| 112 | depends on ARCH_OMAP | ||
| 113 | default n | ||
| 114 | help | ||
| 115 | Say Y here if you want to use OMAP Mailbox framework support for | ||
| 116 | DSP, IVA1.0 and IVA2 in OMAP1/2/3. | ||
| 117 | |||
| 107 | choice | 118 | choice |
| 108 | prompt "System timer" | 119 | prompt "System timer" |
| 109 | default OMAP_MPU_TIMER | 120 | default OMAP_MPU_TIMER |
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index be6aab9c6834..2e0614552ac8 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
| @@ -36,44 +36,6 @@ static struct clk_functions *arch_clock; | |||
| 36 | * Standard clock functions defined in include/linux/clk.h | 36 | * Standard clock functions defined in include/linux/clk.h |
| 37 | *-------------------------------------------------------------------------*/ | 37 | *-------------------------------------------------------------------------*/ |
| 38 | 38 | ||
| 39 | /* | ||
| 40 | * Returns a clock. Note that we first try to use device id on the bus | ||
| 41 | * and clock name. If this fails, we try to use clock name only. | ||
| 42 | */ | ||
| 43 | struct clk * clk_get(struct device *dev, const char *id) | ||
| 44 | { | ||
| 45 | struct clk *p, *clk = ERR_PTR(-ENOENT); | ||
| 46 | int idno; | ||
| 47 | |||
| 48 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
| 49 | idno = -1; | ||
| 50 | else | ||
| 51 | idno = to_platform_device(dev)->id; | ||
| 52 | |||
| 53 | mutex_lock(&clocks_mutex); | ||
| 54 | |||
| 55 | list_for_each_entry(p, &clocks, node) { | ||
| 56 | if (p->id == idno && | ||
| 57 | strcmp(id, p->name) == 0 && try_module_get(p->owner)) { | ||
| 58 | clk = p; | ||
| 59 | goto found; | ||
| 60 | } | ||
| 61 | } | ||
| 62 | |||
| 63 | list_for_each_entry(p, &clocks, node) { | ||
| 64 | if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { | ||
| 65 | clk = p; | ||
| 66 | break; | ||
| 67 | } | ||
| 68 | } | ||
| 69 | |||
| 70 | found: | ||
| 71 | mutex_unlock(&clocks_mutex); | ||
| 72 | |||
| 73 | return clk; | ||
| 74 | } | ||
| 75 | EXPORT_SYMBOL(clk_get); | ||
| 76 | |||
| 77 | int clk_enable(struct clk *clk) | 39 | int clk_enable(struct clk *clk) |
| 78 | { | 40 | { |
| 79 | unsigned long flags; | 41 | unsigned long flags; |
| @@ -114,22 +76,6 @@ out: | |||
| 114 | } | 76 | } |
| 115 | EXPORT_SYMBOL(clk_disable); | 77 | EXPORT_SYMBOL(clk_disable); |
| 116 | 78 | ||
| 117 | int clk_get_usecount(struct clk *clk) | ||
| 118 | { | ||
| 119 | unsigned long flags; | ||
| 120 | int ret = 0; | ||
| 121 | |||
| 122 | if (clk == NULL || IS_ERR(clk)) | ||
| 123 | return 0; | ||
| 124 | |||
| 125 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 126 | ret = clk->usecount; | ||
| 127 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 128 | |||
| 129 | return ret; | ||
| 130 | } | ||
| 131 | EXPORT_SYMBOL(clk_get_usecount); | ||
| 132 | |||
| 133 | unsigned long clk_get_rate(struct clk *clk) | 79 | unsigned long clk_get_rate(struct clk *clk) |
| 134 | { | 80 | { |
| 135 | unsigned long flags; | 81 | unsigned long flags; |
| @@ -146,13 +92,6 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 146 | } | 92 | } |
| 147 | EXPORT_SYMBOL(clk_get_rate); | 93 | EXPORT_SYMBOL(clk_get_rate); |
| 148 | 94 | ||
| 149 | void clk_put(struct clk *clk) | ||
| 150 | { | ||
| 151 | if (clk && !IS_ERR(clk)) | ||
| 152 | module_put(clk->owner); | ||
| 153 | } | ||
| 154 | EXPORT_SYMBOL(clk_put); | ||
| 155 | |||
| 156 | /*------------------------------------------------------------------------- | 95 | /*------------------------------------------------------------------------- |
| 157 | * Optional clock functions defined in include/linux/clk.h | 96 | * Optional clock functions defined in include/linux/clk.h |
| 158 | *-------------------------------------------------------------------------*/ | 97 | *-------------------------------------------------------------------------*/ |
| @@ -185,6 +124,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 185 | spin_lock_irqsave(&clockfw_lock, flags); | 124 | spin_lock_irqsave(&clockfw_lock, flags); |
| 186 | if (arch_clock->clk_set_rate) | 125 | if (arch_clock->clk_set_rate) |
| 187 | ret = arch_clock->clk_set_rate(clk, rate); | 126 | ret = arch_clock->clk_set_rate(clk, rate); |
| 127 | if (ret == 0) { | ||
| 128 | if (clk->recalc) | ||
| 129 | clk->rate = clk->recalc(clk); | ||
| 130 | propagate_rate(clk); | ||
| 131 | } | ||
| 188 | spin_unlock_irqrestore(&clockfw_lock, flags); | 132 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 189 | 133 | ||
| 190 | return ret; | 134 | return ret; |
| @@ -200,8 +144,16 @@ int clk_set_parent(struct clk *clk, struct clk *parent) | |||
| 200 | return ret; | 144 | return ret; |
| 201 | 145 | ||
| 202 | spin_lock_irqsave(&clockfw_lock, flags); | 146 | spin_lock_irqsave(&clockfw_lock, flags); |
| 203 | if (arch_clock->clk_set_parent) | 147 | if (clk->usecount == 0) { |
| 204 | ret = arch_clock->clk_set_parent(clk, parent); | 148 | if (arch_clock->clk_set_parent) |
| 149 | ret = arch_clock->clk_set_parent(clk, parent); | ||
| 150 | if (ret == 0) { | ||
| 151 | if (clk->recalc) | ||
| 152 | clk->rate = clk->recalc(clk); | ||
| 153 | propagate_rate(clk); | ||
| 154 | } | ||
| 155 | } else | ||
| 156 | ret = -EBUSY; | ||
| 205 | spin_unlock_irqrestore(&clockfw_lock, flags); | 157 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 206 | 158 | ||
| 207 | return ret; | 159 | return ret; |
| @@ -210,18 +162,7 @@ EXPORT_SYMBOL(clk_set_parent); | |||
| 210 | 162 | ||
| 211 | struct clk *clk_get_parent(struct clk *clk) | 163 | struct clk *clk_get_parent(struct clk *clk) |
| 212 | { | 164 | { |
| 213 | unsigned long flags; | 165 | return clk->parent; |
| 214 | struct clk * ret = NULL; | ||
| 215 | |||
| 216 | if (clk == NULL || IS_ERR(clk)) | ||
| 217 | return ret; | ||
| 218 | |||
| 219 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 220 | if (arch_clock->clk_get_parent) | ||
| 221 | ret = arch_clock->clk_get_parent(clk); | ||
| 222 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 223 | |||
| 224 | return ret; | ||
| 225 | } | 166 | } |
| 226 | EXPORT_SYMBOL(clk_get_parent); | 167 | EXPORT_SYMBOL(clk_get_parent); |
| 227 | 168 | ||
| @@ -250,14 +191,20 @@ static int __init omap_clk_setup(char *str) | |||
| 250 | __setup("mpurate=", omap_clk_setup); | 191 | __setup("mpurate=", omap_clk_setup); |
| 251 | 192 | ||
| 252 | /* Used for clocks that always have same value as the parent clock */ | 193 | /* Used for clocks that always have same value as the parent clock */ |
| 253 | void followparent_recalc(struct clk *clk) | 194 | unsigned long followparent_recalc(struct clk *clk) |
| 254 | { | 195 | { |
| 255 | if (clk == NULL || IS_ERR(clk)) | 196 | return clk->parent->rate; |
| 256 | return; | 197 | } |
| 257 | 198 | ||
| 258 | clk->rate = clk->parent->rate; | 199 | void clk_reparent(struct clk *child, struct clk *parent) |
| 259 | if (unlikely(clk->flags & RATE_PROPAGATES)) | 200 | { |
| 260 | propagate_rate(clk); | 201 | list_del_init(&child->sibling); |
| 202 | if (parent) | ||
| 203 | list_add(&child->sibling, &parent->children); | ||
| 204 | child->parent = parent; | ||
| 205 | |||
| 206 | /* now do the debugfs renaming to reattach the child | ||
| 207 | to the proper parent */ | ||
| 261 | } | 208 | } |
| 262 | 209 | ||
| 263 | /* Propagate rate to children */ | 210 | /* Propagate rate to children */ |
| @@ -265,17 +212,15 @@ void propagate_rate(struct clk * tclk) | |||
| 265 | { | 212 | { |
| 266 | struct clk *clkp; | 213 | struct clk *clkp; |
| 267 | 214 | ||
| 268 | if (tclk == NULL || IS_ERR(tclk)) | 215 | list_for_each_entry(clkp, &tclk->children, sibling) { |
| 269 | return; | 216 | if (clkp->recalc) |
| 270 | 217 | clkp->rate = clkp->recalc(clkp); | |
| 271 | list_for_each_entry(clkp, &clocks, node) { | 218 | propagate_rate(clkp); |
| 272 | if (likely(clkp->parent != tclk)) | ||
| 273 | continue; | ||
| 274 | if (likely((u32)clkp->recalc)) | ||
| 275 | clkp->recalc(clkp); | ||
| 276 | } | 219 | } |
| 277 | } | 220 | } |
| 278 | 221 | ||
| 222 | static LIST_HEAD(root_clks); | ||
| 223 | |||
| 279 | /** | 224 | /** |
| 280 | * recalculate_root_clocks - recalculate and propagate all root clocks | 225 | * recalculate_root_clocks - recalculate and propagate all root clocks |
| 281 | * | 226 | * |
| @@ -287,18 +232,35 @@ void recalculate_root_clocks(void) | |||
| 287 | { | 232 | { |
| 288 | struct clk *clkp; | 233 | struct clk *clkp; |
| 289 | 234 | ||
| 290 | list_for_each_entry(clkp, &clocks, node) { | 235 | list_for_each_entry(clkp, &root_clks, sibling) { |
| 291 | if (unlikely(!clkp->parent) && likely((u32)clkp->recalc)) | 236 | if (clkp->recalc) |
| 292 | clkp->recalc(clkp); | 237 | clkp->rate = clkp->recalc(clkp); |
| 238 | propagate_rate(clkp); | ||
| 293 | } | 239 | } |
| 294 | } | 240 | } |
| 295 | 241 | ||
| 242 | void clk_init_one(struct clk *clk) | ||
| 243 | { | ||
| 244 | INIT_LIST_HEAD(&clk->children); | ||
| 245 | } | ||
| 246 | |||
| 296 | int clk_register(struct clk *clk) | 247 | int clk_register(struct clk *clk) |
| 297 | { | 248 | { |
| 298 | if (clk == NULL || IS_ERR(clk)) | 249 | if (clk == NULL || IS_ERR(clk)) |
| 299 | return -EINVAL; | 250 | return -EINVAL; |
| 300 | 251 | ||
| 252 | /* | ||
| 253 | * trap out already registered clocks | ||
| 254 | */ | ||
| 255 | if (clk->node.next || clk->node.prev) | ||
| 256 | return 0; | ||
| 257 | |||
| 301 | mutex_lock(&clocks_mutex); | 258 | mutex_lock(&clocks_mutex); |
| 259 | if (clk->parent) | ||
| 260 | list_add(&clk->sibling, &clk->parent->children); | ||
| 261 | else | ||
| 262 | list_add(&clk->sibling, &root_clks); | ||
| 263 | |||
| 302 | list_add(&clk->node, &clocks); | 264 | list_add(&clk->node, &clocks); |
| 303 | if (clk->init) | 265 | if (clk->init) |
| 304 | clk->init(clk); | 266 | clk->init(clk); |
| @@ -314,39 +276,12 @@ void clk_unregister(struct clk *clk) | |||
| 314 | return; | 276 | return; |
| 315 | 277 | ||
| 316 | mutex_lock(&clocks_mutex); | 278 | mutex_lock(&clocks_mutex); |
| 279 | list_del(&clk->sibling); | ||
| 317 | list_del(&clk->node); | 280 | list_del(&clk->node); |
| 318 | mutex_unlock(&clocks_mutex); | 281 | mutex_unlock(&clocks_mutex); |
| 319 | } | 282 | } |
| 320 | EXPORT_SYMBOL(clk_unregister); | 283 | EXPORT_SYMBOL(clk_unregister); |
| 321 | 284 | ||
| 322 | void clk_deny_idle(struct clk *clk) | ||
| 323 | { | ||
| 324 | unsigned long flags; | ||
| 325 | |||
| 326 | if (clk == NULL || IS_ERR(clk)) | ||
| 327 | return; | ||
| 328 | |||
| 329 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 330 | if (arch_clock->clk_deny_idle) | ||
| 331 | arch_clock->clk_deny_idle(clk); | ||
| 332 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 333 | } | ||
| 334 | EXPORT_SYMBOL(clk_deny_idle); | ||
| 335 | |||
| 336 | void clk_allow_idle(struct clk *clk) | ||
| 337 | { | ||
| 338 | unsigned long flags; | ||
| 339 | |||
| 340 | if (clk == NULL || IS_ERR(clk)) | ||
| 341 | return; | ||
| 342 | |||
| 343 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 344 | if (arch_clock->clk_allow_idle) | ||
| 345 | arch_clock->clk_allow_idle(clk); | ||
| 346 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 347 | } | ||
| 348 | EXPORT_SYMBOL(clk_allow_idle); | ||
| 349 | |||
| 350 | void clk_enable_init_clocks(void) | 285 | void clk_enable_init_clocks(void) |
| 351 | { | 286 | { |
| 352 | struct clk *clkp; | 287 | struct clk *clkp; |
| @@ -358,6 +293,23 @@ void clk_enable_init_clocks(void) | |||
| 358 | } | 293 | } |
| 359 | EXPORT_SYMBOL(clk_enable_init_clocks); | 294 | EXPORT_SYMBOL(clk_enable_init_clocks); |
| 360 | 295 | ||
| 296 | /* | ||
| 297 | * Low level helpers | ||
| 298 | */ | ||
| 299 | static int clkll_enable_null(struct clk *clk) | ||
| 300 | { | ||
| 301 | return 0; | ||
| 302 | } | ||
| 303 | |||
| 304 | static void clkll_disable_null(struct clk *clk) | ||
| 305 | { | ||
| 306 | } | ||
| 307 | |||
| 308 | const struct clkops clkops_null = { | ||
| 309 | .enable = clkll_enable_null, | ||
| 310 | .disable = clkll_disable_null, | ||
| 311 | }; | ||
| 312 | |||
| 361 | #ifdef CONFIG_CPU_FREQ | 313 | #ifdef CONFIG_CPU_FREQ |
| 362 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | 314 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) |
| 363 | { | 315 | { |
| @@ -383,8 +335,10 @@ static int __init clk_disable_unused(void) | |||
| 383 | unsigned long flags; | 335 | unsigned long flags; |
| 384 | 336 | ||
| 385 | list_for_each_entry(ck, &clocks, node) { | 337 | list_for_each_entry(ck, &clocks, node) { |
| 386 | if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) || | 338 | if (ck->ops == &clkops_null) |
| 387 | ck->enable_reg == 0) | 339 | continue; |
| 340 | |||
| 341 | if (ck->usecount > 0 || ck->enable_reg == 0) | ||
| 388 | continue; | 342 | continue; |
| 389 | 343 | ||
| 390 | spin_lock_irqsave(&clockfw_lock, flags); | 344 | spin_lock_irqsave(&clockfw_lock, flags); |
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 6825fbb5a056..d1797147732f 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
| @@ -245,7 +245,7 @@ static struct omap_globals *omap2_globals; | |||
| 245 | static void __init __omap2_set_globals(void) | 245 | static void __init __omap2_set_globals(void) |
| 246 | { | 246 | { |
| 247 | omap2_set_globals_tap(omap2_globals); | 247 | omap2_set_globals_tap(omap2_globals); |
| 248 | omap2_set_globals_memory(omap2_globals); | 248 | omap2_set_globals_sdrc(omap2_globals); |
| 249 | omap2_set_globals_control(omap2_globals); | 249 | omap2_set_globals_control(omap2_globals); |
| 250 | omap2_set_globals_prcm(omap2_globals); | 250 | omap2_set_globals_prcm(omap2_globals); |
| 251 | } | 251 | } |
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index b2690242a390..843e8af64066 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c | |||
| @@ -23,10 +23,13 @@ | |||
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <mach/clock.h> | ||
| 26 | #include <asm/system.h> | 27 | #include <asm/system.h> |
| 27 | 28 | ||
| 28 | #define VERY_HI_RATE 900000000 | 29 | #define VERY_HI_RATE 900000000 |
| 29 | 30 | ||
| 31 | static struct cpufreq_frequency_table *freq_table; | ||
| 32 | |||
| 30 | #ifdef CONFIG_ARCH_OMAP1 | 33 | #ifdef CONFIG_ARCH_OMAP1 |
| 31 | #define MPU_CLK "mpu" | 34 | #define MPU_CLK "mpu" |
| 32 | #else | 35 | #else |
| @@ -39,6 +42,9 @@ static struct clk *mpu_clk; | |||
| 39 | 42 | ||
| 40 | int omap_verify_speed(struct cpufreq_policy *policy) | 43 | int omap_verify_speed(struct cpufreq_policy *policy) |
| 41 | { | 44 | { |
| 45 | if (freq_table) | ||
| 46 | return cpufreq_frequency_table_verify(policy, freq_table); | ||
| 47 | |||
| 42 | if (policy->cpu) | 48 | if (policy->cpu) |
| 43 | return -EINVAL; | 49 | return -EINVAL; |
| 44 | 50 | ||
| @@ -70,12 +76,26 @@ static int omap_target(struct cpufreq_policy *policy, | |||
| 70 | struct cpufreq_freqs freqs; | 76 | struct cpufreq_freqs freqs; |
| 71 | int ret = 0; | 77 | int ret = 0; |
| 72 | 78 | ||
| 79 | /* Ensure desired rate is within allowed range. Some govenors | ||
| 80 | * (ondemand) will just pass target_freq=0 to get the minimum. */ | ||
| 81 | if (target_freq < policy->cpuinfo.min_freq) | ||
| 82 | target_freq = policy->cpuinfo.min_freq; | ||
| 83 | if (target_freq > policy->cpuinfo.max_freq) | ||
| 84 | target_freq = policy->cpuinfo.max_freq; | ||
| 85 | |||
| 73 | freqs.old = omap_getspeed(0); | 86 | freqs.old = omap_getspeed(0); |
| 74 | freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; | 87 | freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; |
| 75 | freqs.cpu = 0; | 88 | freqs.cpu = 0; |
| 76 | 89 | ||
| 90 | if (freqs.old == freqs.new) | ||
| 91 | return ret; | ||
| 92 | |||
| 77 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | 93 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
| 78 | ret = clk_set_rate(mpu_clk, target_freq * 1000); | 94 | #ifdef CONFIG_CPU_FREQ_DEBUG |
| 95 | printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n", | ||
| 96 | freqs.old, freqs.new); | ||
| 97 | #endif | ||
| 98 | ret = clk_set_rate(mpu_clk, freqs.new * 1000); | ||
| 79 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | 99 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
| 80 | 100 | ||
| 81 | return ret; | 101 | return ret; |
| @@ -83,16 +103,31 @@ static int omap_target(struct cpufreq_policy *policy, | |||
| 83 | 103 | ||
| 84 | static int __init omap_cpu_init(struct cpufreq_policy *policy) | 104 | static int __init omap_cpu_init(struct cpufreq_policy *policy) |
| 85 | { | 105 | { |
| 106 | int result = 0; | ||
| 107 | |||
| 86 | mpu_clk = clk_get(NULL, MPU_CLK); | 108 | mpu_clk = clk_get(NULL, MPU_CLK); |
| 87 | if (IS_ERR(mpu_clk)) | 109 | if (IS_ERR(mpu_clk)) |
| 88 | return PTR_ERR(mpu_clk); | 110 | return PTR_ERR(mpu_clk); |
| 89 | 111 | ||
| 90 | if (policy->cpu != 0) | 112 | if (policy->cpu != 0) |
| 91 | return -EINVAL; | 113 | return -EINVAL; |
| 114 | |||
| 92 | policy->cur = policy->min = policy->max = omap_getspeed(0); | 115 | policy->cur = policy->min = policy->max = omap_getspeed(0); |
| 93 | policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; | 116 | |
| 94 | policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000; | 117 | clk_init_cpufreq_table(&freq_table); |
| 95 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | 118 | if (freq_table) { |
| 119 | result = cpufreq_frequency_table_cpuinfo(policy, freq_table); | ||
| 120 | if (!result) | ||
| 121 | cpufreq_frequency_table_get_attr(freq_table, | ||
| 122 | policy->cpu); | ||
| 123 | } else { | ||
| 124 | policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; | ||
| 125 | policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, | ||
| 126 | VERY_HI_RATE) / 1000; | ||
| 127 | } | ||
| 128 | |||
| 129 | /* FIXME: what's the actual transition time? */ | ||
| 130 | policy->cpuinfo.transition_latency = 10 * 1000 * 1000; | ||
| 96 | 131 | ||
| 97 | return 0; | 132 | return 0; |
| 98 | } | 133 | } |
| @@ -103,6 +138,11 @@ static int omap_cpu_exit(struct cpufreq_policy *policy) | |||
| 103 | return 0; | 138 | return 0; |
| 104 | } | 139 | } |
| 105 | 140 | ||
| 141 | static struct freq_attr *omap_cpufreq_attr[] = { | ||
| 142 | &cpufreq_freq_attr_scaling_available_freqs, | ||
| 143 | NULL, | ||
| 144 | }; | ||
| 145 | |||
| 106 | static struct cpufreq_driver omap_driver = { | 146 | static struct cpufreq_driver omap_driver = { |
| 107 | .flags = CPUFREQ_STICKY, | 147 | .flags = CPUFREQ_STICKY, |
| 108 | .verify = omap_verify_speed, | 148 | .verify = omap_verify_speed, |
| @@ -111,6 +151,7 @@ static struct cpufreq_driver omap_driver = { | |||
| 111 | .init = omap_cpu_init, | 151 | .init = omap_cpu_init, |
| 112 | .exit = omap_cpu_exit, | 152 | .exit = omap_cpu_exit, |
| 113 | .name = "omap", | 153 | .name = "omap", |
| 154 | .attr = omap_cpufreq_attr, | ||
| 114 | }; | 155 | }; |
| 115 | 156 | ||
| 116 | static int __init omap_cpufreq_init(void) | 157 | static int __init omap_cpufreq_init(void) |
| @@ -119,3 +160,11 @@ static int __init omap_cpufreq_init(void) | |||
| 119 | } | 160 | } |
| 120 | 161 | ||
| 121 | arch_initcall(omap_cpufreq_init); | 162 | arch_initcall(omap_cpufreq_init); |
| 163 | |||
| 164 | /* | ||
| 165 | * if ever we want to remove this, upon cleanup call: | ||
| 166 | * | ||
| 167 | * cpufreq_unregister_driver() | ||
| 168 | * cpufreq_frequency_table_put_attr() | ||
| 169 | */ | ||
| 170 | |||
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 208dbb121f47..87fb7ff41794 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
| @@ -228,6 +228,9 @@ int __init omap_mmc_add(const char *name, int id, unsigned long base, | |||
| 228 | ret = platform_device_add(pdev); | 228 | ret = platform_device_add(pdev); |
| 229 | if (ret) | 229 | if (ret) |
| 230 | goto fail; | 230 | goto fail; |
| 231 | |||
| 232 | /* return device handle to board setup code */ | ||
| 233 | data->dev = &pdev->dev; | ||
| 231 | return 0; | 234 | return 0; |
| 232 | 235 | ||
| 233 | fail: | 236 | fail: |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 47ec77af4ccb..21cc0142b97a 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
| @@ -123,6 +123,7 @@ static struct dma_link_info *dma_linked_lch; | |||
| 123 | 123 | ||
| 124 | static int dma_lch_count; | 124 | static int dma_lch_count; |
| 125 | static int dma_chan_count; | 125 | static int dma_chan_count; |
| 126 | static int omap_dma_reserve_channels; | ||
| 126 | 127 | ||
| 127 | static spinlock_t dma_chan_lock; | 128 | static spinlock_t dma_chan_lock; |
| 128 | static struct omap_dma_lch *dma_chan; | 129 | static struct omap_dma_lch *dma_chan; |
| @@ -737,7 +738,7 @@ int omap_request_dma(int dev_id, const char *dev_name, | |||
| 737 | * id. | 738 | * id. |
| 738 | */ | 739 | */ |
| 739 | dma_write(dev_id | (1 << 10), CCR(free_ch)); | 740 | dma_write(dev_id | (1 << 10), CCR(free_ch)); |
| 740 | } else if (cpu_is_omap730() || cpu_is_omap15xx()) { | 741 | } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { |
| 741 | dma_write(dev_id, CCR(free_ch)); | 742 | dma_write(dev_id, CCR(free_ch)); |
| 742 | } | 743 | } |
| 743 | 744 | ||
| @@ -1900,7 +1901,7 @@ static int omap2_dma_handle_ch(int ch) | |||
| 1900 | /* STATUS register count is from 1-32 while our is 0-31 */ | 1901 | /* STATUS register count is from 1-32 while our is 0-31 */ |
| 1901 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) | 1902 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) |
| 1902 | { | 1903 | { |
| 1903 | u32 val; | 1904 | u32 val, enable_reg; |
| 1904 | int i; | 1905 | int i; |
| 1905 | 1906 | ||
| 1906 | val = dma_read(IRQSTATUS_L0); | 1907 | val = dma_read(IRQSTATUS_L0); |
| @@ -1909,6 +1910,8 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) | |||
| 1909 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | 1910 | printk(KERN_WARNING "Spurious DMA IRQ\n"); |
| 1910 | return IRQ_HANDLED; | 1911 | return IRQ_HANDLED; |
| 1911 | } | 1912 | } |
| 1913 | enable_reg = dma_read(IRQENABLE_L0); | ||
| 1914 | val &= enable_reg; /* Dispatch only relevant interrupts */ | ||
| 1912 | for (i = 0; i < dma_lch_count && val != 0; i++) { | 1915 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
| 1913 | if (val & 1) | 1916 | if (val & 1) |
| 1914 | omap2_dma_handle_ch(i); | 1917 | omap2_dma_handle_ch(i); |
| @@ -2321,6 +2324,10 @@ static int __init omap_init_dma(void) | |||
| 2321 | return -ENODEV; | 2324 | return -ENODEV; |
| 2322 | } | 2325 | } |
| 2323 | 2326 | ||
| 2327 | if (cpu_class_is_omap2() && omap_dma_reserve_channels | ||
| 2328 | && (omap_dma_reserve_channels <= dma_lch_count)) | ||
| 2329 | dma_lch_count = omap_dma_reserve_channels; | ||
| 2330 | |||
| 2324 | dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, | 2331 | dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, |
| 2325 | GFP_KERNEL); | 2332 | GFP_KERNEL); |
| 2326 | if (!dma_chan) | 2333 | if (!dma_chan) |
| @@ -2339,7 +2346,7 @@ static int __init omap_init_dma(void) | |||
| 2339 | printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); | 2346 | printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); |
| 2340 | dma_chan_count = 9; | 2347 | dma_chan_count = 9; |
| 2341 | enable_1510_mode = 1; | 2348 | enable_1510_mode = 1; |
| 2342 | } else if (cpu_is_omap16xx() || cpu_is_omap730()) { | 2349 | } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { |
| 2343 | printk(KERN_INFO "OMAP DMA hardware version %d\n", | 2350 | printk(KERN_INFO "OMAP DMA hardware version %d\n", |
| 2344 | dma_read(HW_ID)); | 2351 | dma_read(HW_ID)); |
| 2345 | printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", | 2352 | printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", |
| @@ -2371,7 +2378,7 @@ static int __init omap_init_dma(void) | |||
| 2371 | u8 revision = dma_read(REVISION) & 0xff; | 2378 | u8 revision = dma_read(REVISION) & 0xff; |
| 2372 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", | 2379 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", |
| 2373 | revision >> 4, revision & 0xf); | 2380 | revision >> 4, revision & 0xf); |
| 2374 | dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | 2381 | dma_chan_count = dma_lch_count; |
| 2375 | } else { | 2382 | } else { |
| 2376 | dma_chan_count = 0; | 2383 | dma_chan_count = 0; |
| 2377 | return 0; | 2384 | return 0; |
| @@ -2437,4 +2444,17 @@ static int __init omap_init_dma(void) | |||
| 2437 | 2444 | ||
| 2438 | arch_initcall(omap_init_dma); | 2445 | arch_initcall(omap_init_dma); |
| 2439 | 2446 | ||
| 2447 | /* | ||
| 2448 | * Reserve the omap SDMA channels using cmdline bootarg | ||
| 2449 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | ||
| 2450 | */ | ||
| 2451 | static int __init omap_dma_cmdline_reserve_ch(char *str) | ||
| 2452 | { | ||
| 2453 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | ||
| 2454 | omap_dma_reserve_channels = 0; | ||
| 2455 | return 1; | ||
| 2456 | } | ||
| 2457 | |||
| 2458 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | ||
| 2459 | |||
| 2440 | 2460 | ||
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index e4f0ce04ba92..bfd47570cc91 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <linux/clk.h> | 33 | #include <linux/clk.h> |
| 34 | #include <linux/delay.h> | 34 | #include <linux/delay.h> |
| 35 | #include <linux/io.h> | 35 | #include <linux/io.h> |
| 36 | #include <linux/module.h> | ||
| 36 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
| 37 | #include <mach/dmtimer.h> | 38 | #include <mach/dmtimer.h> |
| 38 | #include <mach/irqs.h> | 39 | #include <mach/irqs.h> |
| @@ -362,6 +363,7 @@ struct omap_dm_timer *omap_dm_timer_request(void) | |||
| 362 | 363 | ||
| 363 | return timer; | 364 | return timer; |
| 364 | } | 365 | } |
| 366 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); | ||
| 365 | 367 | ||
| 366 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | 368 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) |
| 367 | { | 369 | { |
| @@ -385,6 +387,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |||
| 385 | 387 | ||
| 386 | return timer; | 388 | return timer; |
| 387 | } | 389 | } |
| 390 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); | ||
| 388 | 391 | ||
| 389 | void omap_dm_timer_free(struct omap_dm_timer *timer) | 392 | void omap_dm_timer_free(struct omap_dm_timer *timer) |
| 390 | { | 393 | { |
| @@ -395,6 +398,7 @@ void omap_dm_timer_free(struct omap_dm_timer *timer) | |||
| 395 | WARN_ON(!timer->reserved); | 398 | WARN_ON(!timer->reserved); |
| 396 | timer->reserved = 0; | 399 | timer->reserved = 0; |
| 397 | } | 400 | } |
| 401 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); | ||
| 398 | 402 | ||
| 399 | void omap_dm_timer_enable(struct omap_dm_timer *timer) | 403 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
| 400 | { | 404 | { |
| @@ -406,6 +410,7 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer) | |||
| 406 | 410 | ||
| 407 | timer->enabled = 1; | 411 | timer->enabled = 1; |
| 408 | } | 412 | } |
| 413 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); | ||
| 409 | 414 | ||
| 410 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | 415 | void omap_dm_timer_disable(struct omap_dm_timer *timer) |
| 411 | { | 416 | { |
| @@ -417,11 +422,13 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer) | |||
| 417 | 422 | ||
| 418 | timer->enabled = 0; | 423 | timer->enabled = 0; |
| 419 | } | 424 | } |
| 425 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); | ||
| 420 | 426 | ||
| 421 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) | 427 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
| 422 | { | 428 | { |
| 423 | return timer->irq; | 429 | return timer->irq; |
| 424 | } | 430 | } |
| 431 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); | ||
| 425 | 432 | ||
| 426 | #if defined(CONFIG_ARCH_OMAP1) | 433 | #if defined(CONFIG_ARCH_OMAP1) |
| 427 | 434 | ||
| @@ -452,6 +459,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |||
| 452 | 459 | ||
| 453 | return inputmask; | 460 | return inputmask; |
| 454 | } | 461 | } |
| 462 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); | ||
| 455 | 463 | ||
| 456 | #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) | 464 | #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) |
| 457 | 465 | ||
| @@ -459,6 +467,7 @@ struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) | |||
| 459 | { | 467 | { |
| 460 | return timer->fclk; | 468 | return timer->fclk; |
| 461 | } | 469 | } |
| 470 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); | ||
| 462 | 471 | ||
| 463 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | 472 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
| 464 | { | 473 | { |
| @@ -466,6 +475,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |||
| 466 | 475 | ||
| 467 | return 0; | 476 | return 0; |
| 468 | } | 477 | } |
| 478 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); | ||
| 469 | 479 | ||
| 470 | #endif | 480 | #endif |
| 471 | 481 | ||
| @@ -473,6 +483,7 @@ void omap_dm_timer_trigger(struct omap_dm_timer *timer) | |||
| 473 | { | 483 | { |
| 474 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); | 484 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
| 475 | } | 485 | } |
| 486 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); | ||
| 476 | 487 | ||
| 477 | void omap_dm_timer_start(struct omap_dm_timer *timer) | 488 | void omap_dm_timer_start(struct omap_dm_timer *timer) |
| 478 | { | 489 | { |
| @@ -484,6 +495,7 @@ void omap_dm_timer_start(struct omap_dm_timer *timer) | |||
| 484 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 495 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 485 | } | 496 | } |
| 486 | } | 497 | } |
| 498 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); | ||
| 487 | 499 | ||
| 488 | void omap_dm_timer_stop(struct omap_dm_timer *timer) | 500 | void omap_dm_timer_stop(struct omap_dm_timer *timer) |
| 489 | { | 501 | { |
| @@ -495,6 +507,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer) | |||
| 495 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 507 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 496 | } | 508 | } |
| 497 | } | 509 | } |
| 510 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); | ||
| 498 | 511 | ||
| 499 | #ifdef CONFIG_ARCH_OMAP1 | 512 | #ifdef CONFIG_ARCH_OMAP1 |
| 500 | 513 | ||
| @@ -507,6 +520,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) | |||
| 507 | l |= source << n; | 520 | l |= source << n; |
| 508 | omap_writel(l, MOD_CONF_CTRL_1); | 521 | omap_writel(l, MOD_CONF_CTRL_1); |
| 509 | } | 522 | } |
| 523 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); | ||
| 510 | 524 | ||
| 511 | #else | 525 | #else |
| 512 | 526 | ||
| @@ -523,6 +537,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) | |||
| 523 | * cause an abort. */ | 537 | * cause an abort. */ |
| 524 | __delay(150000); | 538 | __delay(150000); |
| 525 | } | 539 | } |
| 540 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); | ||
| 526 | 541 | ||
| 527 | #endif | 542 | #endif |
| 528 | 543 | ||
| @@ -541,6 +556,7 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, | |||
| 541 | 556 | ||
| 542 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); | 557 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
| 543 | } | 558 | } |
| 559 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); | ||
| 544 | 560 | ||
| 545 | /* Optimized set_load which removes costly spin wait in timer_start */ | 561 | /* Optimized set_load which removes costly spin wait in timer_start */ |
| 546 | void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, | 562 | void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
| @@ -560,6 +576,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, | |||
| 560 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); | 576 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); |
| 561 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 577 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 562 | } | 578 | } |
| 579 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); | ||
| 563 | 580 | ||
| 564 | void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, | 581 | void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
| 565 | unsigned int match) | 582 | unsigned int match) |
| @@ -574,6 +591,7 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, | |||
| 574 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 591 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 575 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); | 592 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
| 576 | } | 593 | } |
| 594 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); | ||
| 577 | 595 | ||
| 578 | void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, | 596 | void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
| 579 | int toggle, int trigger) | 597 | int toggle, int trigger) |
| @@ -590,6 +608,7 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, | |||
| 590 | l |= trigger << 10; | 608 | l |= trigger << 10; |
| 591 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 609 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 592 | } | 610 | } |
| 611 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); | ||
| 593 | 612 | ||
| 594 | void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) | 613 | void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
| 595 | { | 614 | { |
| @@ -603,6 +622,7 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) | |||
| 603 | } | 622 | } |
| 604 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 623 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 605 | } | 624 | } |
| 625 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); | ||
| 606 | 626 | ||
| 607 | void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, | 627 | void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
| 608 | unsigned int value) | 628 | unsigned int value) |
| @@ -610,6 +630,7 @@ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, | |||
| 610 | omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); | 630 | omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); |
| 611 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value); | 631 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value); |
| 612 | } | 632 | } |
| 633 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); | ||
| 613 | 634 | ||
| 614 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) | 635 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
| 615 | { | 636 | { |
| @@ -619,11 +640,13 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) | |||
| 619 | 640 | ||
| 620 | return l; | 641 | return l; |
| 621 | } | 642 | } |
| 643 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); | ||
| 622 | 644 | ||
| 623 | void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) | 645 | void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
| 624 | { | 646 | { |
| 625 | omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); | 647 | omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); |
| 626 | } | 648 | } |
| 649 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); | ||
| 627 | 650 | ||
| 628 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) | 651 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
| 629 | { | 652 | { |
| @@ -633,11 +656,13 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) | |||
| 633 | 656 | ||
| 634 | return l; | 657 | return l; |
| 635 | } | 658 | } |
| 659 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); | ||
| 636 | 660 | ||
| 637 | void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) | 661 | void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
| 638 | { | 662 | { |
| 639 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); | 663 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
| 640 | } | 664 | } |
| 665 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); | ||
| 641 | 666 | ||
| 642 | int omap_dm_timers_active(void) | 667 | int omap_dm_timers_active(void) |
| 643 | { | 668 | { |
| @@ -658,6 +683,7 @@ int omap_dm_timers_active(void) | |||
| 658 | } | 683 | } |
| 659 | return 0; | 684 | return 0; |
| 660 | } | 685 | } |
| 686 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); | ||
| 661 | 687 | ||
| 662 | int __init omap_dm_timer_init(void) | 688 | int __init omap_dm_timer_init(void) |
| 663 | { | 689 | { |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index f856a90b264e..d3fa41e3d8c5 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
| @@ -81,6 +81,22 @@ | |||
| 81 | #define OMAP730_GPIO_INT_STATUS 0x14 | 81 | #define OMAP730_GPIO_INT_STATUS 0x14 |
| 82 | 82 | ||
| 83 | /* | 83 | /* |
| 84 | * OMAP850 specific GPIO registers | ||
| 85 | */ | ||
| 86 | #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000) | ||
| 87 | #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800) | ||
| 88 | #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000) | ||
| 89 | #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800) | ||
| 90 | #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000) | ||
| 91 | #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800) | ||
| 92 | #define OMAP850_GPIO_DATA_INPUT 0x00 | ||
| 93 | #define OMAP850_GPIO_DATA_OUTPUT 0x04 | ||
| 94 | #define OMAP850_GPIO_DIR_CONTROL 0x08 | ||
| 95 | #define OMAP850_GPIO_INT_CONTROL 0x0c | ||
| 96 | #define OMAP850_GPIO_INT_MASK 0x10 | ||
| 97 | #define OMAP850_GPIO_INT_STATUS 0x14 | ||
| 98 | |||
| 99 | /* | ||
| 84 | * omap24xx specific GPIO registers | 100 | * omap24xx specific GPIO registers |
| 85 | */ | 101 | */ |
| 86 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) | 102 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) |
| @@ -159,7 +175,8 @@ struct gpio_bank { | |||
| 159 | #define METHOD_GPIO_1510 1 | 175 | #define METHOD_GPIO_1510 1 |
| 160 | #define METHOD_GPIO_1610 2 | 176 | #define METHOD_GPIO_1610 2 |
| 161 | #define METHOD_GPIO_730 3 | 177 | #define METHOD_GPIO_730 3 |
| 162 | #define METHOD_GPIO_24XX 4 | 178 | #define METHOD_GPIO_850 4 |
| 179 | #define METHOD_GPIO_24XX 5 | ||
| 163 | 180 | ||
| 164 | #ifdef CONFIG_ARCH_OMAP16XX | 181 | #ifdef CONFIG_ARCH_OMAP16XX |
| 165 | static struct gpio_bank gpio_bank_1610[5] = { | 182 | static struct gpio_bank gpio_bank_1610[5] = { |
| @@ -190,6 +207,19 @@ static struct gpio_bank gpio_bank_730[7] = { | |||
| 190 | }; | 207 | }; |
| 191 | #endif | 208 | #endif |
| 192 | 209 | ||
| 210 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 211 | static struct gpio_bank gpio_bank_850[7] = { | ||
| 212 | { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | ||
| 213 | { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, | ||
| 214 | { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, | ||
| 215 | { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, | ||
| 216 | { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, | ||
| 217 | { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, | ||
| 218 | { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, | ||
| 219 | }; | ||
| 220 | #endif | ||
| 221 | |||
| 222 | |||
| 193 | #ifdef CONFIG_ARCH_OMAP24XX | 223 | #ifdef CONFIG_ARCH_OMAP24XX |
| 194 | 224 | ||
| 195 | static struct gpio_bank gpio_bank_242x[4] = { | 225 | static struct gpio_bank gpio_bank_242x[4] = { |
| @@ -236,7 +266,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) | |||
| 236 | return &gpio_bank[0]; | 266 | return &gpio_bank[0]; |
| 237 | return &gpio_bank[1 + (gpio >> 4)]; | 267 | return &gpio_bank[1 + (gpio >> 4)]; |
| 238 | } | 268 | } |
| 239 | if (cpu_is_omap730()) { | 269 | if (cpu_is_omap7xx()) { |
| 240 | if (OMAP_GPIO_IS_MPUIO(gpio)) | 270 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
| 241 | return &gpio_bank[0]; | 271 | return &gpio_bank[0]; |
| 242 | return &gpio_bank[1 + (gpio >> 5)]; | 272 | return &gpio_bank[1 + (gpio >> 5)]; |
| @@ -251,7 +281,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) | |||
| 251 | 281 | ||
| 252 | static inline int get_gpio_index(int gpio) | 282 | static inline int get_gpio_index(int gpio) |
| 253 | { | 283 | { |
| 254 | if (cpu_is_omap730()) | 284 | if (cpu_is_omap7xx()) |
| 255 | return gpio & 0x1f; | 285 | return gpio & 0x1f; |
| 256 | if (cpu_is_omap24xx()) | 286 | if (cpu_is_omap24xx()) |
| 257 | return gpio & 0x1f; | 287 | return gpio & 0x1f; |
| @@ -273,7 +303,7 @@ static inline int gpio_valid(int gpio) | |||
| 273 | return 0; | 303 | return 0; |
| 274 | if ((cpu_is_omap16xx()) && gpio < 64) | 304 | if ((cpu_is_omap16xx()) && gpio < 64) |
| 275 | return 0; | 305 | return 0; |
| 276 | if (cpu_is_omap730() && gpio < 192) | 306 | if (cpu_is_omap7xx() && gpio < 192) |
| 277 | return 0; | 307 | return 0; |
| 278 | if (cpu_is_omap24xx() && gpio < 128) | 308 | if (cpu_is_omap24xx() && gpio < 128) |
| 279 | return 0; | 309 | return 0; |
| @@ -318,6 +348,11 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |||
| 318 | reg += OMAP730_GPIO_DIR_CONTROL; | 348 | reg += OMAP730_GPIO_DIR_CONTROL; |
| 319 | break; | 349 | break; |
| 320 | #endif | 350 | #endif |
| 351 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 352 | case METHOD_GPIO_850: | ||
| 353 | reg += OMAP850_GPIO_DIR_CONTROL; | ||
| 354 | break; | ||
| 355 | #endif | ||
| 321 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 356 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 322 | case METHOD_GPIO_24XX: | 357 | case METHOD_GPIO_24XX: |
| 323 | reg += OMAP24XX_GPIO_OE; | 358 | reg += OMAP24XX_GPIO_OE; |
| @@ -380,6 +415,16 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |||
| 380 | l &= ~(1 << gpio); | 415 | l &= ~(1 << gpio); |
| 381 | break; | 416 | break; |
| 382 | #endif | 417 | #endif |
| 418 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 419 | case METHOD_GPIO_850: | ||
| 420 | reg += OMAP850_GPIO_DATA_OUTPUT; | ||
| 421 | l = __raw_readl(reg); | ||
| 422 | if (enable) | ||
| 423 | l |= 1 << gpio; | ||
| 424 | else | ||
| 425 | l &= ~(1 << gpio); | ||
| 426 | break; | ||
| 427 | #endif | ||
| 383 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 428 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 384 | case METHOD_GPIO_24XX: | 429 | case METHOD_GPIO_24XX: |
| 385 | if (enable) | 430 | if (enable) |
| @@ -426,6 +471,11 @@ static int __omap_get_gpio_datain(int gpio) | |||
| 426 | reg += OMAP730_GPIO_DATA_INPUT; | 471 | reg += OMAP730_GPIO_DATA_INPUT; |
| 427 | break; | 472 | break; |
| 428 | #endif | 473 | #endif |
| 474 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 475 | case METHOD_GPIO_850: | ||
| 476 | reg += OMAP850_GPIO_DATA_INPUT; | ||
| 477 | break; | ||
| 478 | #endif | ||
| 429 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 479 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 430 | case METHOD_GPIO_24XX: | 480 | case METHOD_GPIO_24XX: |
| 431 | reg += OMAP24XX_GPIO_DATAIN; | 481 | reg += OMAP24XX_GPIO_DATAIN; |
| @@ -598,6 +648,18 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
| 598 | goto bad; | 648 | goto bad; |
| 599 | break; | 649 | break; |
| 600 | #endif | 650 | #endif |
| 651 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 652 | case METHOD_GPIO_850: | ||
| 653 | reg += OMAP850_GPIO_INT_CONTROL; | ||
| 654 | l = __raw_readl(reg); | ||
| 655 | if (trigger & IRQ_TYPE_EDGE_RISING) | ||
| 656 | l |= 1 << gpio; | ||
| 657 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | ||
| 658 | l &= ~(1 << gpio); | ||
| 659 | else | ||
| 660 | goto bad; | ||
| 661 | break; | ||
| 662 | #endif | ||
| 601 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 663 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 602 | case METHOD_GPIO_24XX: | 664 | case METHOD_GPIO_24XX: |
| 603 | set_24xx_gpio_triggering(bank, gpio, trigger); | 665 | set_24xx_gpio_triggering(bank, gpio, trigger); |
| @@ -678,6 +740,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
| 678 | reg += OMAP730_GPIO_INT_STATUS; | 740 | reg += OMAP730_GPIO_INT_STATUS; |
| 679 | break; | 741 | break; |
| 680 | #endif | 742 | #endif |
| 743 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 744 | case METHOD_GPIO_850: | ||
| 745 | reg += OMAP850_GPIO_INT_STATUS; | ||
| 746 | break; | ||
| 747 | #endif | ||
| 681 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 748 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 682 | case METHOD_GPIO_24XX: | 749 | case METHOD_GPIO_24XX: |
| 683 | reg += OMAP24XX_GPIO_IRQSTATUS1; | 750 | reg += OMAP24XX_GPIO_IRQSTATUS1; |
| @@ -736,6 +803,13 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | |||
| 736 | inv = 1; | 803 | inv = 1; |
| 737 | break; | 804 | break; |
| 738 | #endif | 805 | #endif |
| 806 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 807 | case METHOD_GPIO_850: | ||
| 808 | reg += OMAP850_GPIO_INT_MASK; | ||
| 809 | mask = 0xffffffff; | ||
| 810 | inv = 1; | ||
| 811 | break; | ||
| 812 | #endif | ||
| 739 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 813 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 740 | case METHOD_GPIO_24XX: | 814 | case METHOD_GPIO_24XX: |
| 741 | reg += OMAP24XX_GPIO_IRQENABLE1; | 815 | reg += OMAP24XX_GPIO_IRQENABLE1; |
| @@ -799,6 +873,16 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab | |||
| 799 | l |= gpio_mask; | 873 | l |= gpio_mask; |
| 800 | break; | 874 | break; |
| 801 | #endif | 875 | #endif |
| 876 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 877 | case METHOD_GPIO_850: | ||
| 878 | reg += OMAP850_GPIO_INT_MASK; | ||
| 879 | l = __raw_readl(reg); | ||
| 880 | if (enable) | ||
| 881 | l &= ~(gpio_mask); | ||
| 882 | else | ||
| 883 | l |= gpio_mask; | ||
| 884 | break; | ||
| 885 | #endif | ||
| 802 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 886 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 803 | case METHOD_GPIO_24XX: | 887 | case METHOD_GPIO_24XX: |
| 804 | if (enable) | 888 | if (enable) |
| @@ -983,6 +1067,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 983 | if (bank->method == METHOD_GPIO_730) | 1067 | if (bank->method == METHOD_GPIO_730) |
| 984 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | 1068 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; |
| 985 | #endif | 1069 | #endif |
| 1070 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 1071 | if (bank->method == METHOD_GPIO_850) | ||
| 1072 | isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; | ||
| 1073 | #endif | ||
| 986 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1074 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 987 | if (bank->method == METHOD_GPIO_24XX) | 1075 | if (bank->method == METHOD_GPIO_24XX) |
| 988 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | 1076 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; |
| @@ -1372,6 +1460,13 @@ static int __init _omap_gpio_init(void) | |||
| 1372 | gpio_bank = gpio_bank_730; | 1460 | gpio_bank = gpio_bank_730; |
| 1373 | } | 1461 | } |
| 1374 | #endif | 1462 | #endif |
| 1463 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 1464 | if (cpu_is_omap850()) { | ||
| 1465 | printk(KERN_INFO "OMAP850 GPIO hardware\n"); | ||
| 1466 | gpio_bank_count = 7; | ||
| 1467 | gpio_bank = gpio_bank_850; | ||
| 1468 | } | ||
| 1469 | #endif | ||
| 1375 | 1470 | ||
| 1376 | #ifdef CONFIG_ARCH_OMAP24XX | 1471 | #ifdef CONFIG_ARCH_OMAP24XX |
| 1377 | if (cpu_is_omap242x()) { | 1472 | if (cpu_is_omap242x()) { |
| @@ -1420,7 +1515,7 @@ static int __init _omap_gpio_init(void) | |||
| 1420 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | 1515 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); |
| 1421 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); | 1516 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
| 1422 | } | 1517 | } |
| 1423 | if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { | 1518 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { |
| 1424 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); | 1519 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
| 1425 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | 1520 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); |
| 1426 | 1521 | ||
| @@ -1743,6 +1838,9 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) | |||
| 1743 | case METHOD_GPIO_730: | 1838 | case METHOD_GPIO_730: |
| 1744 | reg += OMAP730_GPIO_DIR_CONTROL; | 1839 | reg += OMAP730_GPIO_DIR_CONTROL; |
| 1745 | break; | 1840 | break; |
| 1841 | case METHOD_GPIO_850: | ||
| 1842 | reg += OMAP850_GPIO_DIR_CONTROL; | ||
| 1843 | break; | ||
| 1746 | case METHOD_GPIO_24XX: | 1844 | case METHOD_GPIO_24XX: |
| 1747 | reg += OMAP24XX_GPIO_OE; | 1845 | reg += OMAP24XX_GPIO_OE; |
| 1748 | break; | 1846 | break; |
| @@ -1762,7 +1860,8 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) | |||
| 1762 | 1860 | ||
| 1763 | if (bank_is_mpuio(bank)) | 1861 | if (bank_is_mpuio(bank)) |
| 1764 | gpio = OMAP_MPUIO(0); | 1862 | gpio = OMAP_MPUIO(0); |
| 1765 | else if (cpu_class_is_omap2() || cpu_is_omap730()) | 1863 | else if (cpu_class_is_omap2() || cpu_is_omap730() || |
| 1864 | cpu_is_omap850()) | ||
| 1766 | bankwidth = 32; | 1865 | bankwidth = 32; |
| 1767 | 1866 | ||
| 1768 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | 1867 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 467531edefd3..a303071d5e36 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
| @@ -98,6 +98,8 @@ static const int omap34xx_pins[][2] = { | |||
| 98 | static const int omap34xx_pins[][2] = {}; | 98 | static const int omap34xx_pins[][2] = {}; |
| 99 | #endif | 99 | #endif |
| 100 | 100 | ||
| 101 | #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) | ||
| 102 | |||
| 101 | static void __init omap_i2c_mux_pins(int bus) | 103 | static void __init omap_i2c_mux_pins(int bus) |
| 102 | { | 104 | { |
| 103 | int scl, sda; | 105 | int scl, sda; |
| @@ -119,14 +121,9 @@ static void __init omap_i2c_mux_pins(int bus) | |||
| 119 | omap_cfg_reg(scl); | 121 | omap_cfg_reg(scl); |
| 120 | } | 122 | } |
| 121 | 123 | ||
| 122 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | 124 | static int __init omap_i2c_nr_ports(void) |
| 123 | struct i2c_board_info const *info, | ||
| 124 | unsigned len) | ||
| 125 | { | 125 | { |
| 126 | int ports, err; | 126 | int ports = 0; |
| 127 | struct platform_device *pdev; | ||
| 128 | struct resource *res; | ||
| 129 | resource_size_t base, irq; | ||
| 130 | 127 | ||
| 131 | if (cpu_class_is_omap1()) | 128 | if (cpu_class_is_omap1()) |
| 132 | ports = 1; | 129 | ports = 1; |
| @@ -135,17 +132,16 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 135 | else if (cpu_is_omap34xx()) | 132 | else if (cpu_is_omap34xx()) |
| 136 | ports = 3; | 133 | ports = 3; |
| 137 | 134 | ||
| 138 | BUG_ON(bus_id < 1 || bus_id > ports); | 135 | return ports; |
| 136 | } | ||
| 139 | 137 | ||
| 140 | if (info) { | 138 | static int __init omap_i2c_add_bus(int bus_id) |
| 141 | err = i2c_register_board_info(bus_id, info, len); | 139 | { |
| 142 | if (err) | 140 | struct platform_device *pdev; |
| 143 | return err; | 141 | struct resource *res; |
| 144 | } | 142 | resource_size_t base, irq; |
| 145 | 143 | ||
| 146 | pdev = &omap_i2c_devices[bus_id - 1]; | 144 | pdev = &omap_i2c_devices[bus_id - 1]; |
| 147 | *(u32 *)pdev->dev.platform_data = clkrate; | ||
| 148 | |||
| 149 | if (bus_id == 1) { | 145 | if (bus_id == 1) { |
| 150 | res = pdev->resource; | 146 | res = pdev->resource; |
| 151 | if (cpu_class_is_omap1()) { | 147 | if (cpu_class_is_omap1()) { |
| @@ -163,3 +159,81 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 163 | omap_i2c_mux_pins(bus_id - 1); | 159 | omap_i2c_mux_pins(bus_id - 1); |
| 164 | return platform_device_register(pdev); | 160 | return platform_device_register(pdev); |
| 165 | } | 161 | } |
| 162 | |||
| 163 | /** | ||
| 164 | * omap_i2c_bus_setup - Process command line options for the I2C bus speed | ||
| 165 | * @str: String of options | ||
| 166 | * | ||
| 167 | * This function allow to override the default I2C bus speed for given I2C | ||
| 168 | * bus with a command line option. | ||
| 169 | * | ||
| 170 | * Format: i2c_bus=bus_id,clkrate (in kHz) | ||
| 171 | * | ||
| 172 | * Returns 1 on success, 0 otherwise. | ||
| 173 | */ | ||
| 174 | static int __init omap_i2c_bus_setup(char *str) | ||
| 175 | { | ||
| 176 | int ports; | ||
| 177 | int ints[3]; | ||
| 178 | |||
| 179 | ports = omap_i2c_nr_ports(); | ||
| 180 | get_options(str, 3, ints); | ||
| 181 | if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports) | ||
| 182 | return 0; | ||
| 183 | i2c_rate[ints[1] - 1] = ints[2]; | ||
| 184 | i2c_rate[ints[1] - 1] |= OMAP_I2C_CMDLINE_SETUP; | ||
| 185 | |||
| 186 | return 1; | ||
| 187 | } | ||
| 188 | __setup("i2c_bus=", omap_i2c_bus_setup); | ||
| 189 | |||
| 190 | /* | ||
| 191 | * Register busses defined in command line but that are not registered with | ||
| 192 | * omap_register_i2c_bus from board initialization code. | ||
| 193 | */ | ||
| 194 | static int __init omap_register_i2c_bus_cmdline(void) | ||
| 195 | { | ||
| 196 | int i, err = 0; | ||
| 197 | |||
| 198 | for (i = 0; i < ARRAY_SIZE(i2c_rate); i++) | ||
| 199 | if (i2c_rate[i] & OMAP_I2C_CMDLINE_SETUP) { | ||
| 200 | i2c_rate[i] &= ~OMAP_I2C_CMDLINE_SETUP; | ||
| 201 | err = omap_i2c_add_bus(i + 1); | ||
| 202 | if (err) | ||
| 203 | goto out; | ||
| 204 | } | ||
| 205 | |||
| 206 | out: | ||
| 207 | return err; | ||
| 208 | } | ||
| 209 | subsys_initcall(omap_register_i2c_bus_cmdline); | ||
| 210 | |||
| 211 | /** | ||
| 212 | * omap_register_i2c_bus - register I2C bus with device descriptors | ||
| 213 | * @bus_id: bus id counting from number 1 | ||
| 214 | * @clkrate: clock rate of the bus in kHz | ||
| 215 | * @info: pointer into I2C device descriptor table or NULL | ||
| 216 | * @len: number of descriptors in the table | ||
| 217 | * | ||
| 218 | * Returns 0 on success or an error code. | ||
| 219 | */ | ||
| 220 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
| 221 | struct i2c_board_info const *info, | ||
| 222 | unsigned len) | ||
| 223 | { | ||
| 224 | int err; | ||
| 225 | |||
| 226 | BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports()); | ||
| 227 | |||
| 228 | if (info) { | ||
| 229 | err = i2c_register_board_info(bus_id, info, len); | ||
| 230 | if (err) | ||
| 231 | return err; | ||
| 232 | } | ||
| 233 | |||
| 234 | if (!i2c_rate[bus_id - 1]) | ||
| 235 | i2c_rate[bus_id - 1] = clkrate; | ||
| 236 | i2c_rate[bus_id - 1] &= ~OMAP_I2C_CMDLINE_SETUP; | ||
| 237 | |||
| 238 | return omap_i2c_add_bus(bus_id); | ||
| 239 | } | ||
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h deleted file mode 100644 index 10d449ea7ed0..000000000000 --- a/arch/arm/plat-omap/include/mach/board-2430sdp.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-2430sdp.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP2430 SDP board. | ||
| 5 | * | ||
| 6 | * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_2430SDP_H | ||
| 30 | #define __ASM_ARCH_OMAP_2430SDP_H | ||
| 31 | |||
| 32 | /* Placeholder for 2430SDP specific defines */ | ||
| 33 | #define OMAP24XX_ETHR_START 0x08000300 | ||
| 34 | #define OMAP24XX_ETHR_GPIO_IRQ 149 | ||
| 35 | #define SDP2430_CS0_BASE 0x04000000 | ||
| 36 | |||
| 37 | /* Function prototypes */ | ||
| 38 | extern void sdp2430_flash_init(void); | ||
| 39 | extern void sdp2430_usb_init(void); | ||
| 40 | |||
| 41 | #endif /* __ASM_ARCH_OMAP_2430SDP_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h deleted file mode 100644 index 61bd5e8f09b1..000000000000 --- a/arch/arm/plat-omap/include/mach/board-apollon.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-apollon.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for Samsung OMAP24XX Apollon board. | ||
| 5 | * | ||
| 6 | * Initial creation by Kyungmin Park <kyungmin.park@samsung.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_APOLLON_H | ||
| 30 | #define __ASM_ARCH_OMAP_APOLLON_H | ||
| 31 | |||
| 32 | #include <mach/cpu.h> | ||
| 33 | |||
| 34 | extern void apollon_mmc_init(void); | ||
| 35 | |||
| 36 | static inline int apollon_plus(void) | ||
| 37 | { | ||
| 38 | /* The apollon plus has IDCODE revision 5 */ | ||
| 39 | return omap_rev() & 0xc0; | ||
| 40 | } | ||
| 41 | |||
| 42 | /* Placeholder for APOLLON specific defines */ | ||
| 43 | #define APOLLON_ETHR_GPIO_IRQ 74 | ||
| 44 | |||
| 45 | #endif /* __ASM_ARCH_OMAP_APOLLON_H */ | ||
| 46 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-fsample.h b/arch/arm/plat-omap/include/mach/board-fsample.h deleted file mode 100644 index cb3c5ae12776..000000000000 --- a/arch/arm/plat-omap/include/mach/board-fsample.h +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-fsample.h | ||
| 3 | * | ||
| 4 | * Board-specific goodies for TI F-Sample. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006 Google, Inc. | ||
| 7 | * Author: Brian Swetland <swetland@google.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_OMAP_FSAMPLE_H | ||
| 15 | #define __ASM_ARCH_OMAP_FSAMPLE_H | ||
| 16 | |||
| 17 | /* fsample is pretty close to p2-sample */ | ||
| 18 | #include <mach/board-perseus2.h> | ||
| 19 | |||
| 20 | #define fsample_cpld_read(reg) __raw_readb(reg) | ||
| 21 | #define fsample_cpld_write(val, reg) __raw_writeb(val, reg) | ||
| 22 | |||
| 23 | #define FSAMPLE_CPLD_BASE 0xE8100000 | ||
| 24 | #define FSAMPLE_CPLD_SIZE SZ_4K | ||
| 25 | #define FSAMPLE_CPLD_START 0x05080000 | ||
| 26 | |||
| 27 | #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00) | ||
| 28 | #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02) | ||
| 29 | #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02) | ||
| 30 | #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04) | ||
| 31 | #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06) | ||
| 32 | #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06) | ||
| 33 | |||
| 34 | #define FSAMPLE_CPLD_BIT_BT_RESET 0 | ||
| 35 | #define FSAMPLE_CPLD_BIT_LCD_RESET 1 | ||
| 36 | #define FSAMPLE_CPLD_BIT_CAM_PWDN 2 | ||
| 37 | #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3 | ||
| 38 | #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4 | ||
| 39 | #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5 | ||
| 40 | #define FSAMPLE_CPLD_BIT_BACKLIGHT 6 | ||
| 41 | #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7 | ||
| 42 | #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8 | ||
| 43 | #define FSAMPLE_CPLD_BIT_OTG_RESET 9 | ||
| 44 | |||
| 45 | #define fsample_cpld_set(bit) \ | ||
| 46 | fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR) | ||
| 47 | |||
| 48 | #define fsample_cpld_clear(bit) \ | ||
| 49 | fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) | ||
| 50 | |||
| 51 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h deleted file mode 100644 index 7c3fa0f0a65e..000000000000 --- a/arch/arm/plat-omap/include/mach/board-h4.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-h4.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP2420 H4 board. | ||
| 5 | * | ||
| 6 | * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_H4_H | ||
| 30 | #define __ASM_ARCH_OMAP_H4_H | ||
| 31 | |||
| 32 | /* MMC Prototypes */ | ||
| 33 | extern void h4_mmc_init(void); | ||
| 34 | |||
| 35 | /* Placeholder for H4 specific defines */ | ||
| 36 | #define OMAP24XX_ETHR_GPIO_IRQ 92 | ||
| 37 | #endif /* __ASM_ARCH_OMAP_H4_H */ | ||
| 38 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-innovator.h b/arch/arm/plat-omap/include/mach/board-innovator.h deleted file mode 100644 index 5ae3e79b9f9c..000000000000 --- a/arch/arm/plat-omap/include/mach/board-innovator.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-innovator.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License along | ||
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 25 | */ | ||
| 26 | #ifndef __ASM_ARCH_OMAP_INNOVATOR_H | ||
| 27 | #define __ASM_ARCH_OMAP_INNOVATOR_H | ||
| 28 | |||
| 29 | #if defined (CONFIG_ARCH_OMAP15XX) | ||
| 30 | |||
| 31 | #ifndef OMAP_SDRAM_DEVICE | ||
| 32 | #define OMAP_SDRAM_DEVICE D256M_1X16_4B | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #define OMAP1510P1_IMIF_PRI_VALUE 0x00 | ||
| 36 | #define OMAP1510P1_EMIFS_PRI_VALUE 0x00 | ||
| 37 | #define OMAP1510P1_EMIFF_PRI_VALUE 0x00 | ||
| 38 | |||
| 39 | #ifndef __ASSEMBLY__ | ||
| 40 | void fpga_write(unsigned char val, int reg); | ||
| 41 | unsigned char fpga_read(int reg); | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #endif /* CONFIG_ARCH_OMAP15XX */ | ||
| 45 | |||
| 46 | #if defined (CONFIG_ARCH_OMAP16XX) | ||
| 47 | |||
| 48 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 49 | #define INNOVATOR1610_ETHR_START 0x04000300 | ||
| 50 | |||
| 51 | #endif /* CONFIG_ARCH_OMAP1610 */ | ||
| 52 | #endif /* __ASM_ARCH_OMAP_INNOVATOR_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h deleted file mode 100644 index f23399665212..000000000000 --- a/arch/arm/plat-omap/include/mach/board-ldp.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-ldp.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP3 LDP. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Texas Instruments Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_LDP_H | ||
| 30 | #define __ASM_ARCH_OMAP_LDP_H | ||
| 31 | |||
| 32 | extern void twl4030_bci_battery_init(void); | ||
| 33 | |||
| 34 | #define TWL4030_IRQNUM INT_34XX_SYS_NIRQ | ||
| 35 | #define LDP_SMC911X_CS 1 | ||
| 36 | #define LDP_SMC911X_GPIO 152 | ||
| 37 | #define DEBUG_BASE 0x08000000 | ||
| 38 | #define OMAP34XX_ETHR_START DEBUG_BASE | ||
| 39 | #endif /* __ASM_ARCH_OMAP_LDP_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-nokia.h b/arch/arm/plat-omap/include/mach/board-nokia.h deleted file mode 100644 index 2abbe001af8c..000000000000 --- a/arch/arm/plat-omap/include/mach/board-nokia.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-nokia.h | ||
| 3 | * | ||
| 4 | * Information structures for Nokia-specific board config data | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Nokia Corporation | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _OMAP_BOARD_NOKIA_H | ||
| 10 | #define _OMAP_BOARD_NOKIA_H | ||
| 11 | |||
| 12 | #include <linux/types.h> | ||
| 13 | |||
| 14 | #define OMAP_TAG_NOKIA_BT 0x4e01 | ||
| 15 | #define OMAP_TAG_WLAN_CX3110X 0x4e02 | ||
| 16 | #define OMAP_TAG_CBUS 0x4e03 | ||
| 17 | #define OMAP_TAG_EM_ASIC_BB5 0x4e04 | ||
| 18 | |||
| 19 | |||
| 20 | #define BT_CHIP_CSR 1 | ||
| 21 | #define BT_CHIP_TI 2 | ||
| 22 | |||
| 23 | #define BT_SYSCLK_12 1 | ||
| 24 | #define BT_SYSCLK_38_4 2 | ||
| 25 | |||
| 26 | struct omap_bluetooth_config { | ||
| 27 | u8 chip_type; | ||
| 28 | u8 bt_wakeup_gpio; | ||
| 29 | u8 host_wakeup_gpio; | ||
| 30 | u8 reset_gpio; | ||
| 31 | u8 bt_uart; | ||
| 32 | u8 bd_addr[6]; | ||
| 33 | u8 bt_sysclk; | ||
| 34 | }; | ||
| 35 | |||
| 36 | struct omap_wlan_cx3110x_config { | ||
| 37 | u8 chip_type; | ||
| 38 | s16 power_gpio; | ||
| 39 | s16 irq_gpio; | ||
| 40 | s16 spi_cs_gpio; | ||
| 41 | }; | ||
| 42 | |||
| 43 | struct omap_cbus_config { | ||
| 44 | s16 clk_gpio; | ||
| 45 | s16 dat_gpio; | ||
| 46 | s16 sel_gpio; | ||
| 47 | }; | ||
| 48 | |||
| 49 | struct omap_em_asic_bb5_config { | ||
| 50 | s16 retu_irq_gpio; | ||
| 51 | s16 tahvo_irq_gpio; | ||
| 52 | }; | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/board-omap3beagle.h b/arch/arm/plat-omap/include/mach/board-omap3beagle.h deleted file mode 100644 index 3080d52d877a..000000000000 --- a/arch/arm/plat-omap/include/mach/board-omap3beagle.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-omap3beagle.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP3 BEAGLE. | ||
| 5 | * | ||
| 6 | * Initial creation by Syed Mohammed Khasim <khasim@ti.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP3_BEAGLE_H | ||
| 30 | #define __ASM_ARCH_OMAP3_BEAGLE_H | ||
| 31 | |||
| 32 | #endif /* __ASM_ARCH_OMAP3_BEAGLE_H */ | ||
| 33 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-osk.h b/arch/arm/plat-omap/include/mach/board-osk.h deleted file mode 100644 index 3850cb1f220a..000000000000 --- a/arch/arm/plat-omap/include/mach/board-osk.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-osk.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP5912 OSK board. | ||
| 5 | * | ||
| 6 | * Written by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_OSK_H | ||
| 30 | #define __ASM_ARCH_OMAP_OSK_H | ||
| 31 | |||
| 32 | /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ | ||
| 33 | #define OMAP_OSK_ETHR_START 0x04800300 | ||
| 34 | |||
| 35 | /* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with | ||
| 36 | * alternate pin configurations for hardware-controlled blinking. | ||
| 37 | */ | ||
| 38 | #define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | ||
| 39 | # define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0) | ||
| 40 | # define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1) | ||
| 41 | # define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2) | ||
| 42 | # define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3) | ||
| 43 | # define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4) | ||
| 44 | # define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5) | ||
| 45 | |||
| 46 | #endif /* __ASM_ARCH_OMAP_OSK_H */ | ||
| 47 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-overo.h b/arch/arm/plat-omap/include/mach/board-overo.h deleted file mode 100644 index 7ecae66966d1..000000000000 --- a/arch/arm/plat-omap/include/mach/board-overo.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * board-overo.h (Gumstix Overo) | ||
| 3 | * | ||
| 4 | * Initial code: Steve Sakoman <steve@sakoman.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * You should have received a copy of the GNU General Public License along | ||
| 12 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 13 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_OVERO_H | ||
| 17 | #define __ASM_ARCH_OVERO_H | ||
| 18 | |||
| 19 | #define OVERO_GPIO_BT_XGATE 15 | ||
| 20 | #define OVERO_GPIO_W2W_NRESET 16 | ||
| 21 | #define OVERO_GPIO_BT_NRESET 164 | ||
| 22 | #define OVERO_GPIO_USBH_CPEN 168 | ||
| 23 | #define OVERO_GPIO_USBH_NRESET 183 | ||
| 24 | |||
| 25 | #endif /* ____ASM_ARCH_OVERO_H */ | ||
| 26 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-palmte.h b/arch/arm/plat-omap/include/mach/board-palmte.h deleted file mode 100644 index 6906cdebbcfb..000000000000 --- a/arch/arm/plat-omap/include/mach/board-palmte.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-palmte.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Tungsten E device. | ||
| 5 | * | ||
| 6 | * Maintainters : http://palmtelinux.sf.net | ||
| 7 | * palmtelinux-developpers@lists.sf.net | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __OMAP_BOARD_PALMTE_H | ||
| 15 | #define __OMAP_BOARD_PALMTE_H | ||
| 16 | |||
| 17 | #define PALMTE_USBDETECT_GPIO 0 | ||
| 18 | #define PALMTE_USB_OR_DC_GPIO 1 | ||
| 19 | #define PALMTE_TSC_GPIO 4 | ||
| 20 | #define PALMTE_PINTDAV_GPIO 6 | ||
| 21 | #define PALMTE_MMC_WP_GPIO 8 | ||
| 22 | #define PALMTE_MMC_POWER_GPIO 9 | ||
| 23 | #define PALMTE_HDQ_GPIO 11 | ||
| 24 | #define PALMTE_HEADPHONES_GPIO 14 | ||
| 25 | #define PALMTE_SPEAKER_GPIO 15 | ||
| 26 | #define PALMTE_DC_GPIO OMAP_MPUIO(2) | ||
| 27 | #define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4) | ||
| 28 | #define PALMTE_MMC1_GPIO OMAP_MPUIO(6) | ||
| 29 | #define PALMTE_MMC2_GPIO OMAP_MPUIO(7) | ||
| 30 | #define PALMTE_MMC3_GPIO OMAP_MPUIO(11) | ||
| 31 | |||
| 32 | #endif /* __OMAP_BOARD_PALMTE_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-palmtt.h b/arch/arm/plat-omap/include/mach/board-palmtt.h deleted file mode 100644 index e79f382b5931..000000000000 --- a/arch/arm/plat-omap/include/mach/board-palmtt.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-palmte.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Tungsten|T device. | ||
| 5 | * | ||
| 6 | * Maintainters : Marek Vasut <marek.vasut@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __OMAP_BOARD_PALMTT_H | ||
| 14 | #define __OMAP_BOARD_PALMTT_H | ||
| 15 | |||
| 16 | #define PALMTT_USBDETECT_GPIO 0 | ||
| 17 | #define PALMTT_CABLE_GPIO 1 | ||
| 18 | #define PALMTT_LED_GPIO 3 | ||
| 19 | #define PALMTT_PENIRQ_GPIO 6 | ||
| 20 | #define PALMTT_MMC_WP_GPIO 8 | ||
| 21 | #define PALMTT_HDQ_GPIO 11 | ||
| 22 | |||
| 23 | #endif /* __OMAP_BOARD_PALMTT_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-palmz71.h b/arch/arm/plat-omap/include/mach/board-palmz71.h deleted file mode 100644 index b1d7d579b313..000000000000 --- a/arch/arm/plat-omap/include/mach/board-palmz71.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-palmz71.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Zire71 device. | ||
| 5 | * | ||
| 6 | * Maintainters : Marek Vasut <marek.vasut@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __OMAP_BOARD_PALMZ71_H | ||
| 14 | #define __OMAP_BOARD_PALMZ71_H | ||
| 15 | |||
| 16 | #define PALMZ71_USBDETECT_GPIO 0 | ||
| 17 | #define PALMZ71_PENIRQ_GPIO 6 | ||
| 18 | #define PALMZ71_MMC_WP_GPIO 8 | ||
| 19 | #define PALMZ71_HDQ_GPIO 11 | ||
| 20 | |||
| 21 | #define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) | ||
| 22 | #define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) | ||
| 23 | #define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) | ||
| 24 | #define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) | ||
| 25 | |||
| 26 | #endif /* __OMAP_BOARD_PALMZ71_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-perseus2.h b/arch/arm/plat-omap/include/mach/board-perseus2.h deleted file mode 100644 index c06c3d717d57..000000000000 --- a/arch/arm/plat-omap/include/mach/board-perseus2.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-perseus2.h | ||
| 3 | * | ||
| 4 | * Copyright 2003 by Texas Instruments Incorporated | ||
| 5 | * OMAP730 / Perseus2 support by Jean Pihet | ||
| 6 | * | ||
| 7 | * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) | ||
| 8 | * Author: RidgeRun, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License along | ||
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 29 | */ | ||
| 30 | #ifndef __ASM_ARCH_OMAP_PERSEUS2_H | ||
| 31 | #define __ASM_ARCH_OMAP_PERSEUS2_H | ||
| 32 | |||
| 33 | #include <mach/fpga.h> | ||
| 34 | |||
| 35 | #ifndef OMAP_SDRAM_DEVICE | ||
| 36 | #define OMAP_SDRAM_DEVICE D256M_1X16_4B | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/mach/board-voiceblue.h index ed6d346ee123..27916b210f57 100644 --- a/arch/arm/plat-omap/include/mach/board-voiceblue.h +++ b/arch/arm/plat-omap/include/mach/board-voiceblue.h | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | extern void voiceblue_wdt_enable(void); | 14 | extern void voiceblue_wdt_enable(void); |
| 15 | extern void voiceblue_wdt_disable(void); | 15 | extern void voiceblue_wdt_disable(void); |
| 16 | extern void voiceblue_wdt_ping(void); | 16 | extern void voiceblue_wdt_ping(void); |
| 17 | extern void voiceblue_reset(void); | ||
| 18 | 17 | ||
| 19 | #endif /* __ASM_ARCH_VOICEBLUE_H */ | 18 | #endif /* __ASM_ARCH_VOICEBLUE_H */ |
| 20 | 19 | ||
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h index 9466772fc7c8..50ea79a0efa2 100644 --- a/arch/arm/plat-omap/include/mach/board.h +++ b/arch/arm/plat-omap/include/mach/board.h | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | /* Different peripheral ids */ | 17 | /* Different peripheral ids */ |
| 18 | #define OMAP_TAG_CLOCK 0x4f01 | 18 | #define OMAP_TAG_CLOCK 0x4f01 |
| 19 | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 | 19 | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
| 20 | #define OMAP_TAG_USB 0x4f04 | ||
| 21 | #define OMAP_TAG_LCD 0x4f05 | 20 | #define OMAP_TAG_LCD 0x4f05 |
| 22 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 | 21 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
| 23 | #define OMAP_TAG_UART 0x4f07 | 22 | #define OMAP_TAG_UART 0x4f07 |
| @@ -133,9 +132,6 @@ struct omap_version_config { | |||
| 133 | char version[12]; | 132 | char version[12]; |
| 134 | }; | 133 | }; |
| 135 | 134 | ||
| 136 | |||
| 137 | #include <mach/board-nokia.h> | ||
| 138 | |||
| 139 | struct omap_board_config_entry { | 135 | struct omap_board_config_entry { |
| 140 | u16 tag; | 136 | u16 tag; |
| 141 | u16 len; | 137 | u16 len; |
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/mach/clkdev.h new file mode 100644 index 000000000000..730c49d1ebd8 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/clkdev.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef __MACH_CLKDEV_H | ||
| 2 | #define __MACH_CLKDEV_H | ||
| 3 | |||
| 4 | static inline int __clk_get(struct clk *clk) | ||
| 5 | { | ||
| 6 | return 1; | ||
| 7 | } | ||
| 8 | |||
| 9 | static inline void __clk_put(struct clk *clk) | ||
| 10 | { | ||
| 11 | } | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 719298554ed7..073a2c5569f0 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h | |||
| @@ -17,11 +17,16 @@ struct module; | |||
| 17 | struct clk; | 17 | struct clk; |
| 18 | struct clockdomain; | 18 | struct clockdomain; |
| 19 | 19 | ||
| 20 | struct clkops { | ||
| 21 | int (*enable)(struct clk *); | ||
| 22 | void (*disable)(struct clk *); | ||
| 23 | }; | ||
| 24 | |||
| 20 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 25 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 21 | 26 | ||
| 22 | struct clksel_rate { | 27 | struct clksel_rate { |
| 23 | u8 div; | ||
| 24 | u32 val; | 28 | u32 val; |
| 29 | u8 div; | ||
| 25 | u8 flags; | 30 | u8 flags; |
| 26 | }; | 31 | }; |
| 27 | 32 | ||
| @@ -34,24 +39,28 @@ struct dpll_data { | |||
| 34 | void __iomem *mult_div1_reg; | 39 | void __iomem *mult_div1_reg; |
| 35 | u32 mult_mask; | 40 | u32 mult_mask; |
| 36 | u32 div1_mask; | 41 | u32 div1_mask; |
| 42 | struct clk *clk_bypass; | ||
| 43 | struct clk *clk_ref; | ||
| 44 | void __iomem *control_reg; | ||
| 45 | u32 enable_mask; | ||
| 46 | unsigned int rate_tolerance; | ||
| 47 | unsigned long last_rounded_rate; | ||
| 37 | u16 last_rounded_m; | 48 | u16 last_rounded_m; |
| 38 | u8 last_rounded_n; | 49 | u8 last_rounded_n; |
| 39 | unsigned long last_rounded_rate; | 50 | u8 min_divider; |
| 40 | unsigned int rate_tolerance; | ||
| 41 | u16 max_multiplier; | ||
| 42 | u8 max_divider; | 51 | u8 max_divider; |
| 43 | u32 max_tolerance; | 52 | u32 max_tolerance; |
| 53 | u16 max_multiplier; | ||
| 44 | # if defined(CONFIG_ARCH_OMAP3) | 54 | # if defined(CONFIG_ARCH_OMAP3) |
| 45 | u8 modes; | 55 | u8 modes; |
| 46 | void __iomem *control_reg; | 56 | void __iomem *autoidle_reg; |
| 47 | u32 enable_mask; | 57 | void __iomem *idlest_reg; |
| 58 | u32 autoidle_mask; | ||
| 59 | u32 freqsel_mask; | ||
| 60 | u32 idlest_mask; | ||
| 48 | u8 auto_recal_bit; | 61 | u8 auto_recal_bit; |
| 49 | u8 recal_en_bit; | 62 | u8 recal_en_bit; |
| 50 | u8 recal_st_bit; | 63 | u8 recal_st_bit; |
| 51 | void __iomem *autoidle_reg; | ||
| 52 | u32 autoidle_mask; | ||
| 53 | void __iomem *idlest_reg; | ||
| 54 | u8 idlest_bit; | ||
| 55 | # endif | 64 | # endif |
| 56 | }; | 65 | }; |
| 57 | 66 | ||
| @@ -59,21 +68,21 @@ struct dpll_data { | |||
| 59 | 68 | ||
| 60 | struct clk { | 69 | struct clk { |
| 61 | struct list_head node; | 70 | struct list_head node; |
| 62 | struct module *owner; | 71 | const struct clkops *ops; |
| 63 | const char *name; | 72 | const char *name; |
| 64 | int id; | 73 | int id; |
| 65 | struct clk *parent; | 74 | struct clk *parent; |
| 75 | struct list_head children; | ||
| 76 | struct list_head sibling; /* node for children */ | ||
| 66 | unsigned long rate; | 77 | unsigned long rate; |
| 67 | __u32 flags; | 78 | __u32 flags; |
| 68 | void __iomem *enable_reg; | 79 | void __iomem *enable_reg; |
| 69 | __u8 enable_bit; | 80 | unsigned long (*recalc)(struct clk *); |
| 70 | __s8 usecount; | ||
| 71 | void (*recalc)(struct clk *); | ||
| 72 | int (*set_rate)(struct clk *, unsigned long); | 81 | int (*set_rate)(struct clk *, unsigned long); |
| 73 | long (*round_rate)(struct clk *, unsigned long); | 82 | long (*round_rate)(struct clk *, unsigned long); |
| 74 | void (*init)(struct clk *); | 83 | void (*init)(struct clk *); |
| 75 | int (*enable)(struct clk *); | 84 | __u8 enable_bit; |
| 76 | void (*disable)(struct clk *); | 85 | __s8 usecount; |
| 77 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 86 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 78 | u8 fixed_div; | 87 | u8 fixed_div; |
| 79 | void __iomem *clksel_reg; | 88 | void __iomem *clksel_reg; |
| @@ -99,7 +108,6 @@ struct clk_functions { | |||
| 99 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); | 108 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); |
| 100 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); | 109 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); |
| 101 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); | 110 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); |
| 102 | struct clk * (*clk_get_parent)(struct clk *clk); | ||
| 103 | void (*clk_allow_idle)(struct clk *clk); | 111 | void (*clk_allow_idle)(struct clk *clk); |
| 104 | void (*clk_deny_idle)(struct clk *clk); | 112 | void (*clk_deny_idle)(struct clk *clk); |
| 105 | void (*clk_disable_unused)(struct clk *clk); | 113 | void (*clk_disable_unused)(struct clk *clk); |
| @@ -110,42 +118,33 @@ struct clk_functions { | |||
| 110 | 118 | ||
| 111 | extern unsigned int mpurate; | 119 | extern unsigned int mpurate; |
| 112 | 120 | ||
| 113 | extern int clk_init(struct clk_functions * custom_clocks); | 121 | extern int clk_init(struct clk_functions *custom_clocks); |
| 122 | extern void clk_init_one(struct clk *clk); | ||
| 114 | extern int clk_register(struct clk *clk); | 123 | extern int clk_register(struct clk *clk); |
| 124 | extern void clk_reparent(struct clk *child, struct clk *parent); | ||
| 115 | extern void clk_unregister(struct clk *clk); | 125 | extern void clk_unregister(struct clk *clk); |
| 116 | extern void propagate_rate(struct clk *clk); | 126 | extern void propagate_rate(struct clk *clk); |
| 117 | extern void recalculate_root_clocks(void); | 127 | extern void recalculate_root_clocks(void); |
| 118 | extern void followparent_recalc(struct clk * clk); | 128 | extern unsigned long followparent_recalc(struct clk *clk); |
| 119 | extern void clk_allow_idle(struct clk *clk); | ||
| 120 | extern void clk_deny_idle(struct clk *clk); | ||
| 121 | extern int clk_get_usecount(struct clk *clk); | ||
| 122 | extern void clk_enable_init_clocks(void); | 129 | extern void clk_enable_init_clocks(void); |
| 130 | #ifdef CONFIG_CPU_FREQ | ||
| 131 | extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); | ||
| 132 | #endif | ||
| 133 | |||
| 134 | extern const struct clkops clkops_null; | ||
| 123 | 135 | ||
| 124 | /* Clock flags */ | 136 | /* Clock flags */ |
| 125 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ | 137 | /* bit 0 is free */ |
| 126 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ | 138 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ |
| 127 | #define RATE_PROPAGATES (1 << 2) /* Program children too */ | 139 | /* bits 2-4 are free */ |
| 128 | #define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */ | ||
| 129 | #define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ | ||
| 130 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ | 140 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ |
| 131 | #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ | ||
| 132 | #define CLOCK_IDLE_CONTROL (1 << 7) | 141 | #define CLOCK_IDLE_CONTROL (1 << 7) |
| 133 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | 142 | #define CLOCK_NO_IDLE_PARENT (1 << 8) |
| 134 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | 143 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ |
| 135 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | 144 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ |
| 136 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ | 145 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ |
| 137 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | 146 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ |
| 138 | /* bits 13-20 are currently free */ | 147 | /* bits 13-31 are currently free */ |
| 139 | #define CLOCK_IN_OMAP310 (1 << 21) | ||
| 140 | #define CLOCK_IN_OMAP730 (1 << 22) | ||
| 141 | #define CLOCK_IN_OMAP1510 (1 << 23) | ||
| 142 | #define CLOCK_IN_OMAP16XX (1 << 24) | ||
| 143 | #define CLOCK_IN_OMAP242X (1 << 25) | ||
| 144 | #define CLOCK_IN_OMAP243X (1 << 26) | ||
| 145 | #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ | ||
| 146 | #define PARENT_CONTROLS_CLOCK (1 << 28) | ||
| 147 | #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ | ||
| 148 | #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ | ||
| 149 | 148 | ||
| 150 | /* Clksel_rate flags */ | 149 | /* Clksel_rate flags */ |
| 151 | #define DEFAULT_RATE (1 << 0) | 150 | #define DEFAULT_RATE (1 << 0) |
| @@ -157,9 +156,4 @@ extern void clk_enable_init_clocks(void); | |||
| 157 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | 156 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
| 158 | 157 | ||
| 159 | 158 | ||
| 160 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ | ||
| 161 | #define CORE_CLK_SRC_32K 0 | ||
| 162 | #define CORE_CLK_SRC_DPLL 1 | ||
| 163 | #define CORE_CLK_SRC_DPLL_X2 2 | ||
| 164 | |||
| 165 | #endif | 159 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h index 1f51f0173784..b9d0dd2da89b 100644 --- a/arch/arm/plat-omap/include/mach/clockdomain.h +++ b/arch/arm/plat-omap/include/mach/clockdomain.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/include/asm-arm/arch-omap/clockdomain.h | 2 | * arch/arm/plat-omap/include/mach/clockdomain.h |
| 3 | * | 3 | * |
| 4 | * OMAP2/3 clockdomain framework functions | 4 | * OMAP2/3 clockdomain framework functions |
| 5 | * | 5 | * |
| @@ -48,11 +48,13 @@ | |||
| 48 | */ | 48 | */ |
| 49 | struct clkdm_pwrdm_autodep { | 49 | struct clkdm_pwrdm_autodep { |
| 50 | 50 | ||
| 51 | /* Name of the powerdomain to add a wkdep/sleepdep on */ | 51 | union { |
| 52 | const char *pwrdm_name; | 52 | /* Name of the powerdomain to add a wkdep/sleepdep on */ |
| 53 | const char *name; | ||
| 53 | 54 | ||
| 54 | /* Powerdomain pointer (looked up at clkdm_init() time) */ | 55 | /* Powerdomain pointer (looked up at clkdm_init() time) */ |
| 55 | struct powerdomain *pwrdm; | 56 | struct powerdomain *ptr; |
| 57 | } pwrdm; | ||
| 56 | 58 | ||
| 57 | /* OMAP chip types that this clockdomain dep is valid on */ | 59 | /* OMAP chip types that this clockdomain dep is valid on */ |
| 58 | const struct omap_chip_id omap_chip; | 60 | const struct omap_chip_id omap_chip; |
| @@ -64,8 +66,13 @@ struct clockdomain { | |||
| 64 | /* Clockdomain name */ | 66 | /* Clockdomain name */ |
| 65 | const char *name; | 67 | const char *name; |
| 66 | 68 | ||
| 67 | /* Powerdomain enclosing this clockdomain */ | 69 | union { |
| 68 | const char *pwrdm_name; | 70 | /* Powerdomain enclosing this clockdomain */ |
| 71 | const char *name; | ||
| 72 | |||
| 73 | /* Powerdomain pointer assigned at clkdm_register() */ | ||
| 74 | struct powerdomain *ptr; | ||
| 75 | } pwrdm; | ||
| 69 | 76 | ||
| 70 | /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ | 77 | /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ |
| 71 | const u16 clktrctrl_mask; | 78 | const u16 clktrctrl_mask; |
| @@ -79,9 +86,6 @@ struct clockdomain { | |||
| 79 | /* Usecount tracking */ | 86 | /* Usecount tracking */ |
| 80 | atomic_t usecount; | 87 | atomic_t usecount; |
| 81 | 88 | ||
| 82 | /* Powerdomain pointer assigned at clkdm_register() */ | ||
| 83 | struct powerdomain *pwrdm; | ||
| 84 | |||
| 85 | struct list_head node; | 89 | struct list_head node; |
| 86 | 90 | ||
| 87 | }; | 91 | }; |
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h index e746ec7e785e..0ecf36deb17b 100644 --- a/arch/arm/plat-omap/include/mach/common.h +++ b/arch/arm/plat-omap/include/mach/common.h | |||
| @@ -65,7 +65,7 @@ void omap2_set_globals_343x(void); | |||
| 65 | 65 | ||
| 66 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | 66 | /* These get called from omap2_set_globals_xxxx(), do not call these */ |
| 67 | void omap2_set_globals_tap(struct omap_globals *); | 67 | void omap2_set_globals_tap(struct omap_globals *); |
| 68 | void omap2_set_globals_memory(struct omap_globals *); | 68 | void omap2_set_globals_sdrc(struct omap_globals *); |
| 69 | void omap2_set_globals_control(struct omap_globals *); | 69 | void omap2_set_globals_control(struct omap_globals *); |
| 70 | void omap2_set_globals_prcm(struct omap_globals *); | 70 | void omap2_set_globals_prcm(struct omap_globals *); |
| 71 | 71 | ||
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h index a8e1178a9468..98b144252364 100644 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ b/arch/arm/plat-omap/include/mach/cpu.h | |||
| @@ -56,6 +56,14 @@ unsigned int omap_rev(void); | |||
| 56 | # define OMAP_NAME omap730 | 56 | # define OMAP_NAME omap730 |
| 57 | # endif | 57 | # endif |
| 58 | #endif | 58 | #endif |
| 59 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 60 | # ifdef OMAP_NAME | ||
| 61 | # undef MULTI_OMAP1 | ||
| 62 | # define MULTI_OMAP1 | ||
| 63 | # else | ||
| 64 | # define OMAP_NAME omap850 | ||
| 65 | # endif | ||
| 66 | #endif | ||
| 59 | #ifdef CONFIG_ARCH_OMAP15XX | 67 | #ifdef CONFIG_ARCH_OMAP15XX |
| 60 | # ifdef OMAP_NAME | 68 | # ifdef OMAP_NAME |
| 61 | # undef MULTI_OMAP1 | 69 | # undef MULTI_OMAP1 |
| @@ -105,7 +113,7 @@ unsigned int omap_rev(void); | |||
| 105 | /* | 113 | /* |
| 106 | * Macros to group OMAP into cpu classes. | 114 | * Macros to group OMAP into cpu classes. |
| 107 | * These can be used in most places. | 115 | * These can be used in most places. |
| 108 | * cpu_is_omap7xx(): True for OMAP730 | 116 | * cpu_is_omap7xx(): True for OMAP730, OMAP850 |
| 109 | * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 | 117 | * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 |
| 110 | * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 | 118 | * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 |
| 111 | * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 | 119 | * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 |
| @@ -153,6 +161,10 @@ IS_OMAP_SUBCLASS(343x, 0x343) | |||
| 153 | # undef cpu_is_omap7xx | 161 | # undef cpu_is_omap7xx |
| 154 | # define cpu_is_omap7xx() is_omap7xx() | 162 | # define cpu_is_omap7xx() is_omap7xx() |
| 155 | # endif | 163 | # endif |
| 164 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 165 | # undef cpu_is_omap7xx | ||
| 166 | # define cpu_is_omap7xx() is_omap7xx() | ||
| 167 | # endif | ||
| 156 | # if defined(CONFIG_ARCH_OMAP15XX) | 168 | # if defined(CONFIG_ARCH_OMAP15XX) |
| 157 | # undef cpu_is_omap15xx | 169 | # undef cpu_is_omap15xx |
| 158 | # define cpu_is_omap15xx() is_omap15xx() | 170 | # define cpu_is_omap15xx() is_omap15xx() |
| @@ -166,6 +178,10 @@ IS_OMAP_SUBCLASS(343x, 0x343) | |||
| 166 | # undef cpu_is_omap7xx | 178 | # undef cpu_is_omap7xx |
| 167 | # define cpu_is_omap7xx() 1 | 179 | # define cpu_is_omap7xx() 1 |
| 168 | # endif | 180 | # endif |
| 181 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 182 | # undef cpu_is_omap7xx | ||
| 183 | # define cpu_is_omap7xx() 1 | ||
| 184 | # endif | ||
| 169 | # if defined(CONFIG_ARCH_OMAP15XX) | 185 | # if defined(CONFIG_ARCH_OMAP15XX) |
| 170 | # undef cpu_is_omap15xx | 186 | # undef cpu_is_omap15xx |
| 171 | # define cpu_is_omap15xx() 1 | 187 | # define cpu_is_omap15xx() 1 |
| @@ -219,6 +235,7 @@ IS_OMAP_SUBCLASS(343x, 0x343) | |||
| 219 | * These are only rarely needed. | 235 | * These are only rarely needed. |
| 220 | * cpu_is_omap330(): True for OMAP330 | 236 | * cpu_is_omap330(): True for OMAP330 |
| 221 | * cpu_is_omap730(): True for OMAP730 | 237 | * cpu_is_omap730(): True for OMAP730 |
| 238 | * cpu_is_omap850(): True for OMAP850 | ||
| 222 | * cpu_is_omap1510(): True for OMAP1510 | 239 | * cpu_is_omap1510(): True for OMAP1510 |
| 223 | * cpu_is_omap1610(): True for OMAP1610 | 240 | * cpu_is_omap1610(): True for OMAP1610 |
| 224 | * cpu_is_omap1611(): True for OMAP1611 | 241 | * cpu_is_omap1611(): True for OMAP1611 |
| @@ -241,6 +258,7 @@ static inline int is_omap ##type (void) \ | |||
| 241 | 258 | ||
| 242 | IS_OMAP_TYPE(310, 0x0310) | 259 | IS_OMAP_TYPE(310, 0x0310) |
| 243 | IS_OMAP_TYPE(730, 0x0730) | 260 | IS_OMAP_TYPE(730, 0x0730) |
| 261 | IS_OMAP_TYPE(850, 0x0850) | ||
| 244 | IS_OMAP_TYPE(1510, 0x1510) | 262 | IS_OMAP_TYPE(1510, 0x1510) |
| 245 | IS_OMAP_TYPE(1610, 0x1610) | 263 | IS_OMAP_TYPE(1610, 0x1610) |
| 246 | IS_OMAP_TYPE(1611, 0x1611) | 264 | IS_OMAP_TYPE(1611, 0x1611) |
| @@ -255,6 +273,7 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 255 | 273 | ||
| 256 | #define cpu_is_omap310() 0 | 274 | #define cpu_is_omap310() 0 |
| 257 | #define cpu_is_omap730() 0 | 275 | #define cpu_is_omap730() 0 |
| 276 | #define cpu_is_omap850() 0 | ||
| 258 | #define cpu_is_omap1510() 0 | 277 | #define cpu_is_omap1510() 0 |
| 259 | #define cpu_is_omap1610() 0 | 278 | #define cpu_is_omap1610() 0 |
| 260 | #define cpu_is_omap5912() 0 | 279 | #define cpu_is_omap5912() 0 |
| @@ -272,12 +291,22 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 272 | # undef cpu_is_omap730 | 291 | # undef cpu_is_omap730 |
| 273 | # define cpu_is_omap730() is_omap730() | 292 | # define cpu_is_omap730() is_omap730() |
| 274 | # endif | 293 | # endif |
| 294 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 295 | # undef cpu_is_omap850 | ||
| 296 | # define cpu_is_omap850() is_omap850() | ||
| 297 | # endif | ||
| 275 | #else | 298 | #else |
| 276 | # if defined(CONFIG_ARCH_OMAP730) | 299 | # if defined(CONFIG_ARCH_OMAP730) |
| 277 | # undef cpu_is_omap730 | 300 | # undef cpu_is_omap730 |
| 278 | # define cpu_is_omap730() 1 | 301 | # define cpu_is_omap730() 1 |
| 279 | # endif | 302 | # endif |
| 280 | #endif | 303 | #endif |
| 304 | #else | ||
| 305 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 306 | # undef cpu_is_omap850 | ||
| 307 | # define cpu_is_omap850() 1 | ||
| 308 | # endif | ||
| 309 | #endif | ||
| 281 | 310 | ||
| 282 | /* | 311 | /* |
| 283 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish | 312 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish |
| @@ -320,7 +349,7 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 320 | #endif | 349 | #endif |
| 321 | 350 | ||
| 322 | /* Macros to detect if we have OMAP1 or OMAP2 */ | 351 | /* Macros to detect if we have OMAP1 or OMAP2 */ |
| 323 | #define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ | 352 | #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ |
| 324 | cpu_is_omap16xx()) | 353 | cpu_is_omap16xx()) |
| 325 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) | 354 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) |
| 326 | 355 | ||
| @@ -355,13 +384,27 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 355 | * use omap_chip_is(). | 384 | * use omap_chip_is(). |
| 356 | * | 385 | * |
| 357 | */ | 386 | */ |
| 358 | #define CHIP_IS_OMAP2420 (1 << 0) | 387 | #define CHIP_IS_OMAP2420 (1 << 0) |
| 359 | #define CHIP_IS_OMAP2430 (1 << 1) | 388 | #define CHIP_IS_OMAP2430 (1 << 1) |
| 360 | #define CHIP_IS_OMAP3430 (1 << 2) | 389 | #define CHIP_IS_OMAP3430 (1 << 2) |
| 361 | #define CHIP_IS_OMAP3430ES1 (1 << 3) | 390 | #define CHIP_IS_OMAP3430ES1 (1 << 3) |
| 362 | #define CHIP_IS_OMAP3430ES2 (1 << 4) | 391 | #define CHIP_IS_OMAP3430ES2 (1 << 4) |
| 392 | #define CHIP_IS_OMAP3430ES3_0 (1 << 5) | ||
| 393 | #define CHIP_IS_OMAP3430ES3_1 (1 << 6) | ||
| 394 | |||
| 395 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) | ||
| 396 | |||
| 397 | /* | ||
| 398 | * "GE" here represents "greater than or equal to" in terms of ES | ||
| 399 | * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 | ||
| 400 | * chips at ES2 and beyond, but not, for example, any OMAP lines after | ||
| 401 | * OMAP3. | ||
| 402 | */ | ||
| 403 | #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ | ||
| 404 | CHIP_IS_OMAP3430ES3_0 | \ | ||
| 405 | CHIP_IS_OMAP3430ES3_1) | ||
| 406 | #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1) | ||
| 363 | 407 | ||
| 364 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) | ||
| 365 | 408 | ||
| 366 | int omap_chip_is(struct omap_chip_id oci); | 409 | int omap_chip_is(struct omap_chip_id oci); |
| 367 | int omap_type(void); | 410 | int omap_type(void); |
| @@ -378,5 +421,3 @@ int omap_type(void); | |||
| 378 | void omap2_check_revision(void); | 421 | void omap2_check_revision(void); |
| 379 | 422 | ||
| 380 | #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ | 423 | #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ |
| 381 | |||
| 382 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h index 8d9dfe314387..2b22a8799bc6 100644 --- a/arch/arm/plat-omap/include/mach/gpio.h +++ b/arch/arm/plat-omap/include/mach/gpio.h | |||
| @@ -31,7 +31,8 @@ | |||
| 31 | 31 | ||
| 32 | #define OMAP_MPUIO_BASE 0xfffb5000 | 32 | #define OMAP_MPUIO_BASE 0xfffb5000 |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_ARCH_OMAP730 | 34 | #if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) |
| 35 | |||
| 35 | #define OMAP_MPUIO_INPUT_LATCH 0x00 | 36 | #define OMAP_MPUIO_INPUT_LATCH 0x00 |
| 36 | #define OMAP_MPUIO_OUTPUT 0x02 | 37 | #define OMAP_MPUIO_OUTPUT 0x02 |
| 37 | #define OMAP_MPUIO_IO_CNTL 0x04 | 38 | #define OMAP_MPUIO_IO_CNTL 0x04 |
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h index 45b678439bb7..921b16532ff5 100644 --- a/arch/arm/plat-omap/include/mach/gpmc.h +++ b/arch/arm/plat-omap/include/mach/gpmc.h | |||
| @@ -103,6 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); | |||
| 103 | extern void gpmc_cs_free(int cs); | 103 | extern void gpmc_cs_free(int cs); |
| 104 | extern int gpmc_cs_set_reserved(int cs, int reserved); | 104 | extern int gpmc_cs_set_reserved(int cs, int reserved); |
| 105 | extern int gpmc_cs_reserved(int cs); | 105 | extern int gpmc_cs_reserved(int cs); |
| 106 | extern void gpmc_init(void); | 106 | extern void __init gpmc_init(void); |
| 107 | 107 | ||
| 108 | #endif | 108 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h index 6589ddbb63b2..3dc423ed3e80 100644 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ b/arch/arm/plat-omap/include/mach/hardware.h | |||
| @@ -286,78 +286,4 @@ | |||
| 286 | #include "omap24xx.h" | 286 | #include "omap24xx.h" |
| 287 | #include "omap34xx.h" | 287 | #include "omap34xx.h" |
| 288 | 288 | ||
| 289 | #ifndef __ASSEMBLER__ | ||
| 290 | |||
| 291 | /* | ||
| 292 | * --------------------------------------------------------------------------- | ||
| 293 | * Board specific defines | ||
| 294 | * --------------------------------------------------------------------------- | ||
| 295 | */ | ||
| 296 | |||
| 297 | #ifdef CONFIG_MACH_OMAP_INNOVATOR | ||
| 298 | #include "board-innovator.h" | ||
| 299 | #endif | ||
| 300 | |||
| 301 | #ifdef CONFIG_MACH_OMAP_H2 | ||
| 302 | #include "board-h2.h" | ||
| 303 | #endif | ||
| 304 | |||
| 305 | #ifdef CONFIG_MACH_OMAP_PERSEUS2 | ||
| 306 | #include "board-perseus2.h" | ||
| 307 | #endif | ||
| 308 | |||
| 309 | #ifdef CONFIG_MACH_OMAP_FSAMPLE | ||
| 310 | #include "board-fsample.h" | ||
| 311 | #endif | ||
| 312 | |||
| 313 | #ifdef CONFIG_MACH_OMAP_H3 | ||
| 314 | #include "board-h3.h" | ||
| 315 | #endif | ||
| 316 | |||
| 317 | #ifdef CONFIG_MACH_OMAP_H4 | ||
| 318 | #include "board-h4.h" | ||
| 319 | #endif | ||
| 320 | |||
| 321 | #ifdef CONFIG_MACH_OMAP_2430SDP | ||
| 322 | #include "board-2430sdp.h" | ||
| 323 | #endif | ||
| 324 | |||
| 325 | #ifdef CONFIG_MACH_OMAP3_BEAGLE | ||
| 326 | #include "board-omap3beagle.h" | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifdef CONFIG_MACH_OMAP_LDP | ||
| 330 | #include "board-ldp.h" | ||
| 331 | #endif | ||
| 332 | |||
| 333 | #ifdef CONFIG_MACH_OMAP_APOLLON | ||
| 334 | #include "board-apollon.h" | ||
| 335 | #endif | ||
| 336 | |||
| 337 | #ifdef CONFIG_MACH_OMAP_OSK | ||
| 338 | #include "board-osk.h" | ||
| 339 | #endif | ||
| 340 | |||
| 341 | #ifdef CONFIG_MACH_VOICEBLUE | ||
| 342 | #include "board-voiceblue.h" | ||
| 343 | #endif | ||
| 344 | |||
| 345 | #ifdef CONFIG_MACH_OMAP_PALMTE | ||
| 346 | #include "board-palmte.h" | ||
| 347 | #endif | ||
| 348 | |||
| 349 | #ifdef CONFIG_MACH_OMAP_PALMZ71 | ||
| 350 | #include "board-palmz71.h" | ||
| 351 | #endif | ||
| 352 | |||
| 353 | #ifdef CONFIG_MACH_OMAP_PALMTT | ||
| 354 | #include "board-palmtt.h" | ||
| 355 | #endif | ||
| 356 | |||
| 357 | #ifdef CONFIG_MACH_SX1 | ||
| 358 | #include "board-sx1.h" | ||
| 359 | #endif | ||
| 360 | |||
| 361 | #endif /* !__ASSEMBLER__ */ | ||
| 362 | |||
| 363 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ | 289 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ |
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h index d92bf7964481..0610d7e2b3d7 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/mach/io.h | |||
| @@ -185,11 +185,13 @@ | |||
| 185 | #define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a)) | 185 | #define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a)) |
| 186 | #define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a)) | 186 | #define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a)) |
| 187 | 187 | ||
| 188 | struct omap_sdrc_params; | ||
| 189 | |||
| 188 | extern void omap1_map_common_io(void); | 190 | extern void omap1_map_common_io(void); |
| 189 | extern void omap1_init_common_hw(void); | 191 | extern void omap1_init_common_hw(void); |
| 190 | 192 | ||
| 191 | extern void omap2_map_common_io(void); | 193 | extern void omap2_map_common_io(void); |
| 192 | extern void omap2_init_common_hw(void); | 194 | extern void omap2_init_common_hw(struct omap_sdrc_params *sp); |
| 193 | 195 | ||
| 194 | #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) | 196 | #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) |
| 195 | #define __arch_iounmap(v) omap_iounmap(v) | 197 | #define __arch_iounmap(v) omap_iounmap(v) |
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h index bed5274c910a..7f57ee66f364 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/mach/irqs.h | |||
| @@ -105,6 +105,29 @@ | |||
| 105 | #define INT_730_SPGIO_WR 29 | 105 | #define INT_730_SPGIO_WR 29 |
| 106 | 106 | ||
| 107 | /* | 107 | /* |
| 108 | * OMAP-850 specific IRQ numbers for interrupt handler 1 | ||
| 109 | */ | ||
| 110 | #define INT_850_IH2_FIQ 0 | ||
| 111 | #define INT_850_IH2_IRQ 1 | ||
| 112 | #define INT_850_USB_NON_ISO 2 | ||
| 113 | #define INT_850_USB_ISO 3 | ||
| 114 | #define INT_850_ICR 4 | ||
| 115 | #define INT_850_EAC 5 | ||
| 116 | #define INT_850_GPIO_BANK1 6 | ||
| 117 | #define INT_850_GPIO_BANK2 7 | ||
| 118 | #define INT_850_GPIO_BANK3 8 | ||
| 119 | #define INT_850_McBSP2TX 10 | ||
| 120 | #define INT_850_McBSP2RX 11 | ||
| 121 | #define INT_850_McBSP2RX_OVF 12 | ||
| 122 | #define INT_850_LCD_LINE 14 | ||
| 123 | #define INT_850_GSM_PROTECT 15 | ||
| 124 | #define INT_850_TIMER3 16 | ||
| 125 | #define INT_850_GPIO_BANK5 17 | ||
| 126 | #define INT_850_GPIO_BANK6 18 | ||
| 127 | #define INT_850_SPGIO_WR 29 | ||
| 128 | |||
| 129 | |||
| 130 | /* | ||
| 108 | * IRQ numbers for interrupt handler 2 | 131 | * IRQ numbers for interrupt handler 2 |
| 109 | * | 132 | * |
| 110 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | 133 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below |
| @@ -237,6 +260,64 @@ | |||
| 237 | #define INT_730_DMA_CH15 (62 + IH2_BASE) | 260 | #define INT_730_DMA_CH15 (62 + IH2_BASE) |
| 238 | #define INT_730_NAND (63 + IH2_BASE) | 261 | #define INT_730_NAND (63 + IH2_BASE) |
| 239 | 262 | ||
| 263 | /* | ||
| 264 | * OMAP-850 specific IRQ numbers for interrupt handler 2 | ||
| 265 | */ | ||
| 266 | #define INT_850_HW_ERRORS (0 + IH2_BASE) | ||
| 267 | #define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE) | ||
| 268 | #define INT_850_CFCD (2 + IH2_BASE) | ||
| 269 | #define INT_850_CFIREQ (3 + IH2_BASE) | ||
| 270 | #define INT_850_I2C (4 + IH2_BASE) | ||
| 271 | #define INT_850_PCC (5 + IH2_BASE) | ||
| 272 | #define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE) | ||
| 273 | #define INT_850_SPI_100K_1 (7 + IH2_BASE) | ||
| 274 | #define INT_850_SYREN_SPI (8 + IH2_BASE) | ||
| 275 | #define INT_850_VLYNQ (9 + IH2_BASE) | ||
| 276 | #define INT_850_GPIO_BANK4 (10 + IH2_BASE) | ||
| 277 | #define INT_850_McBSP1TX (11 + IH2_BASE) | ||
| 278 | #define INT_850_McBSP1RX (12 + IH2_BASE) | ||
| 279 | #define INT_850_McBSP1RX_OF (13 + IH2_BASE) | ||
| 280 | #define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE) | ||
| 281 | #define INT_850_UART_MODEM_1 (15 + IH2_BASE) | ||
| 282 | #define INT_850_MCSI (16 + IH2_BASE) | ||
| 283 | #define INT_850_uWireTX (17 + IH2_BASE) | ||
| 284 | #define INT_850_uWireRX (18 + IH2_BASE) | ||
| 285 | #define INT_850_SMC_CD (19 + IH2_BASE) | ||
| 286 | #define INT_850_SMC_IREQ (20 + IH2_BASE) | ||
| 287 | #define INT_850_HDQ_1WIRE (21 + IH2_BASE) | ||
| 288 | #define INT_850_TIMER32K (22 + IH2_BASE) | ||
| 289 | #define INT_850_MMC_SDIO (23 + IH2_BASE) | ||
| 290 | #define INT_850_UPLD (24 + IH2_BASE) | ||
| 291 | #define INT_850_USB_HHC_1 (27 + IH2_BASE) | ||
| 292 | #define INT_850_USB_HHC_2 (28 + IH2_BASE) | ||
| 293 | #define INT_850_USB_GENI (29 + IH2_BASE) | ||
| 294 | #define INT_850_USB_OTG (30 + IH2_BASE) | ||
| 295 | #define INT_850_CAMERA_IF (31 + IH2_BASE) | ||
| 296 | #define INT_850_RNG (32 + IH2_BASE) | ||
| 297 | #define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE) | ||
| 298 | #define INT_850_DBB_RF_EN (34 + IH2_BASE) | ||
| 299 | #define INT_850_MPUIO_KEYPAD (35 + IH2_BASE) | ||
| 300 | #define INT_850_SHA1_MD5 (36 + IH2_BASE) | ||
| 301 | #define INT_850_SPI_100K_2 (37 + IH2_BASE) | ||
| 302 | #define INT_850_RNG_IDLE (38 + IH2_BASE) | ||
| 303 | #define INT_850_MPUIO (39 + IH2_BASE) | ||
| 304 | #define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | ||
| 305 | #define INT_850_LLPC_OE_FALLING (41 + IH2_BASE) | ||
| 306 | #define INT_850_LLPC_OE_RISING (42 + IH2_BASE) | ||
| 307 | #define INT_850_LLPC_VSYNC (43 + IH2_BASE) | ||
| 308 | #define INT_850_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 309 | #define INT_850_DMA_CH6 (53 + IH2_BASE) | ||
| 310 | #define INT_850_DMA_CH7 (54 + IH2_BASE) | ||
| 311 | #define INT_850_DMA_CH8 (55 + IH2_BASE) | ||
| 312 | #define INT_850_DMA_CH9 (56 + IH2_BASE) | ||
| 313 | #define INT_850_DMA_CH10 (57 + IH2_BASE) | ||
| 314 | #define INT_850_DMA_CH11 (58 + IH2_BASE) | ||
| 315 | #define INT_850_DMA_CH12 (59 + IH2_BASE) | ||
| 316 | #define INT_850_DMA_CH13 (60 + IH2_BASE) | ||
| 317 | #define INT_850_DMA_CH14 (61 + IH2_BASE) | ||
| 318 | #define INT_850_DMA_CH15 (62 + IH2_BASE) | ||
| 319 | #define INT_850_NAND (63 + IH2_BASE) | ||
| 320 | |||
| 240 | #define INT_24XX_SYS_NIRQ 7 | 321 | #define INT_24XX_SYS_NIRQ 7 |
| 241 | #define INT_24XX_SDMA_IRQ0 12 | 322 | #define INT_24XX_SDMA_IRQ0 12 |
| 242 | #define INT_24XX_SDMA_IRQ1 13 | 323 | #define INT_24XX_SDMA_IRQ1 13 |
| @@ -341,7 +422,7 @@ | |||
| 341 | 422 | ||
| 342 | #define INT_34XX_BENCH_MPU_EMUL 3 | 423 | #define INT_34XX_BENCH_MPU_EMUL 3 |
| 343 | 424 | ||
| 344 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and | 425 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and |
| 345 | * 16 MPUIO lines */ | 426 | * 16 MPUIO lines */ |
| 346 | #define OMAP_MAX_GPIO_LINES 192 | 427 | #define OMAP_MAX_GPIO_LINES 192 |
| 347 | #define IH_GPIO_BASE (128 + IH2_BASE) | 428 | #define IH_GPIO_BASE (128 + IH2_BASE) |
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/mach/mailbox.h index 7cbed9332e16..b7a6991814ec 100644 --- a/arch/arm/plat-omap/include/mach/mailbox.h +++ b/arch/arm/plat-omap/include/mach/mailbox.h | |||
| @@ -33,6 +33,9 @@ struct omap_mbox_ops { | |||
| 33 | void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | 33 | void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); |
| 34 | void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | 34 | void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); |
| 35 | int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | 35 | int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); |
| 36 | /* ctx */ | ||
| 37 | void (*save_ctx)(struct omap_mbox *mbox); | ||
| 38 | void (*restore_ctx)(struct omap_mbox *mbox); | ||
| 36 | }; | 39 | }; |
| 37 | 40 | ||
| 38 | struct omap_mbox_queue { | 41 | struct omap_mbox_queue { |
| @@ -53,7 +56,7 @@ struct omap_mbox { | |||
| 53 | 56 | ||
| 54 | mbox_msg_t seq_snd, seq_rcv; | 57 | mbox_msg_t seq_snd, seq_rcv; |
| 55 | 58 | ||
| 56 | struct device dev; | 59 | struct device *dev; |
| 57 | 60 | ||
| 58 | struct omap_mbox *next; | 61 | struct omap_mbox *next; |
| 59 | void *priv; | 62 | void *priv; |
| @@ -67,7 +70,27 @@ void omap_mbox_init_seq(struct omap_mbox *); | |||
| 67 | struct omap_mbox *omap_mbox_get(const char *); | 70 | struct omap_mbox *omap_mbox_get(const char *); |
| 68 | void omap_mbox_put(struct omap_mbox *); | 71 | void omap_mbox_put(struct omap_mbox *); |
| 69 | 72 | ||
| 70 | int omap_mbox_register(struct omap_mbox *); | 73 | int omap_mbox_register(struct device *parent, struct omap_mbox *); |
| 71 | int omap_mbox_unregister(struct omap_mbox *); | 74 | int omap_mbox_unregister(struct omap_mbox *); |
| 72 | 75 | ||
| 76 | static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) | ||
| 77 | { | ||
| 78 | if (!mbox->ops->save_ctx) { | ||
| 79 | dev_err(mbox->dev, "%s:\tno save\n", __func__); | ||
| 80 | return; | ||
| 81 | } | ||
| 82 | |||
| 83 | mbox->ops->save_ctx(mbox); | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox) | ||
| 87 | { | ||
| 88 | if (!mbox->ops->restore_ctx) { | ||
| 89 | dev_err(mbox->dev, "%s:\tno restore\n", __func__); | ||
| 90 | return; | ||
| 91 | } | ||
| 92 | |||
| 93 | mbox->ops->restore_ctx(mbox); | ||
| 94 | } | ||
| 95 | |||
| 73 | #endif /* MAILBOX_H */ | 96 | #endif /* MAILBOX_H */ |
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h index 113c2466c86a..bb154ea76769 100644 --- a/arch/arm/plat-omap/include/mach/mcbsp.h +++ b/arch/arm/plat-omap/include/mach/mcbsp.h | |||
| @@ -344,8 +344,6 @@ struct omap_mcbsp_platform_data { | |||
| 344 | u8 dma_rx_sync, dma_tx_sync; | 344 | u8 dma_rx_sync, dma_tx_sync; |
| 345 | u16 rx_irq, tx_irq; | 345 | u16 rx_irq, tx_irq; |
| 346 | struct omap_mcbsp_ops *ops; | 346 | struct omap_mcbsp_ops *ops; |
| 347 | char const **clk_names; | ||
| 348 | int num_clks; | ||
| 349 | }; | 347 | }; |
| 350 | 348 | ||
| 351 | struct omap_mcbsp { | 349 | struct omap_mcbsp { |
| @@ -377,8 +375,8 @@ struct omap_mcbsp { | |||
| 377 | /* Protect the field .free, while checking if the mcbsp is in use */ | 375 | /* Protect the field .free, while checking if the mcbsp is in use */ |
| 378 | spinlock_t lock; | 376 | spinlock_t lock; |
| 379 | struct omap_mcbsp_platform_data *pdata; | 377 | struct omap_mcbsp_platform_data *pdata; |
| 380 | struct clk **clks; | 378 | struct clk *iclk; |
| 381 | int num_clks; | 379 | struct clk *fclk; |
| 382 | }; | 380 | }; |
| 383 | extern struct omap_mcbsp **mcbsp_ptr; | 381 | extern struct omap_mcbsp **mcbsp_ptr; |
| 384 | extern int omap_mcbsp_count; | 382 | extern int omap_mcbsp_count; |
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h index d6b5ca6c7da2..99ed564d9277 100644 --- a/arch/arm/plat-omap/include/mach/memory.h +++ b/arch/arm/plat-omap/include/mach/memory.h | |||
| @@ -61,9 +61,11 @@ | |||
| 61 | #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) | 61 | #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) |
| 62 | #define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) | 62 | #define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) |
| 63 | 63 | ||
| 64 | #define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \ | 64 | #define __arch_page_to_dma(dev, page) \ |
| 65 | (dma_addr_t)virt_to_lbus(page_address(page)) : \ | 65 | ({ dma_addr_t __dma = page_to_phys(page); \ |
| 66 | (dma_addr_t)__virt_to_phys(page_address(page));}) | 66 | if (is_lbus_device(dev)) \ |
| 67 | __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \ | ||
| 68 | __dma; }) | ||
| 67 | 69 | ||
| 68 | #define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ | 70 | #define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ |
| 69 | lbus_to_virt(addr) : \ | 71 | lbus_to_virt(addr) : \ |
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h index 73a9e15031b1..4435bd434e17 100644 --- a/arch/arm/plat-omap/include/mach/mmc.h +++ b/arch/arm/plat-omap/include/mach/mmc.h | |||
| @@ -37,6 +37,8 @@ | |||
| 37 | #define OMAP_MMC_MAX_SLOTS 2 | 37 | #define OMAP_MMC_MAX_SLOTS 2 |
| 38 | 38 | ||
| 39 | struct omap_mmc_platform_data { | 39 | struct omap_mmc_platform_data { |
| 40 | /* back-link to device */ | ||
| 41 | struct device *dev; | ||
| 40 | 42 | ||
| 41 | /* number of slots per controller */ | 43 | /* number of slots per controller */ |
| 42 | unsigned nr_slots:2; | 44 | unsigned nr_slots:2; |
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h index f4362b8682c7..85a621705766 100644 --- a/arch/arm/plat-omap/include/mach/mux.h +++ b/arch/arm/plat-omap/include/mach/mux.h | |||
| @@ -61,6 +61,16 @@ | |||
| 61 | .pull_bit = bit, \ | 61 | .pull_bit = bit, \ |
| 62 | .pull_val = status, | 62 | .pull_val = status, |
| 63 | 63 | ||
| 64 | #define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \ | ||
| 65 | .mux_reg = OMAP850_IO_CONF_##reg, \ | ||
| 66 | .mask_offset = mode_offset, \ | ||
| 67 | .mask = mode, | ||
| 68 | |||
| 69 | #define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \ | ||
| 70 | .pull_reg = OMAP850_IO_CONF_##reg, \ | ||
| 71 | .pull_bit = bit, \ | ||
| 72 | .pull_val = status, | ||
| 73 | |||
| 64 | #else | 74 | #else |
| 65 | 75 | ||
| 66 | #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ | 76 | #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ |
| @@ -83,6 +93,15 @@ | |||
| 83 | .pull_bit = bit, \ | 93 | .pull_bit = bit, \ |
| 84 | .pull_val = status, | 94 | .pull_val = status, |
| 85 | 95 | ||
| 96 | #define MUX_REG_850(reg, mode_offset, mode) \ | ||
| 97 | .mux_reg = OMAP850_IO_CONF_##reg, \ | ||
| 98 | .mask_offset = mode_offset, \ | ||
| 99 | .mask = mode, | ||
| 100 | |||
| 101 | #define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \ | ||
| 102 | .pull_bit = bit, \ | ||
| 103 | .pull_val = status, | ||
| 104 | |||
| 86 | #endif /* CONFIG_OMAP_MUX_DEBUG */ | 105 | #endif /* CONFIG_OMAP_MUX_DEBUG */ |
| 87 | 106 | ||
| 88 | #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ | 107 | #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ |
| @@ -98,7 +117,7 @@ | |||
| 98 | 117 | ||
| 99 | 118 | ||
| 100 | /* | 119 | /* |
| 101 | * OMAP730 has a slightly different config for the pin mux. | 120 | * OMAP730/850 has a slightly different config for the pin mux. |
| 102 | * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and | 121 | * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and |
| 103 | * not the FUNC_MUX_CTRL_x regs from hardware.h | 122 | * not the FUNC_MUX_CTRL_x regs from hardware.h |
| 104 | * - for pull-up/down, only has one enable bit which is is in the same register | 123 | * - for pull-up/down, only has one enable bit which is is in the same register |
| @@ -114,6 +133,17 @@ | |||
| 114 | PU_PD_REG(NA, 0) \ | 133 | PU_PD_REG(NA, 0) \ |
| 115 | }, | 134 | }, |
| 116 | 135 | ||
| 136 | #define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \ | ||
| 137 | pull_bit, pull_status, debug_status)\ | ||
| 138 | { \ | ||
| 139 | .name = desc, \ | ||
| 140 | .debug = debug_status, \ | ||
| 141 | MUX_REG_850(mux_reg, mode_offset, mode) \ | ||
| 142 | PULL_REG_850(mux_reg, pull_bit, pull_status) \ | ||
| 143 | PU_PD_REG(NA, 0) \ | ||
| 144 | }, | ||
| 145 | |||
| 146 | |||
| 117 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ | 147 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ |
| 118 | pull_en, pull_mode, dbg) \ | 148 | pull_en, pull_mode, dbg) \ |
| 119 | { \ | 149 | { \ |
| @@ -221,6 +251,26 @@ enum omap730_index { | |||
| 221 | W17_730_USB_VBUSI, | 251 | W17_730_USB_VBUSI, |
| 222 | }; | 252 | }; |
| 223 | 253 | ||
| 254 | enum omap850_index { | ||
| 255 | /* OMAP 850 keyboard */ | ||
| 256 | E2_850_KBR0, | ||
| 257 | J7_850_KBR1, | ||
| 258 | E1_850_KBR2, | ||
| 259 | F3_850_KBR3, | ||
| 260 | D2_850_KBR4, | ||
| 261 | C2_850_KBC0, | ||
| 262 | D3_850_KBC1, | ||
| 263 | E4_850_KBC2, | ||
| 264 | F4_850_KBC3, | ||
| 265 | E3_850_KBC4, | ||
| 266 | |||
| 267 | /* USB */ | ||
| 268 | AA17_850_USB_DM, | ||
| 269 | W16_850_USB_PU_EN, | ||
| 270 | W17_850_USB_VBUSI, | ||
| 271 | }; | ||
| 272 | |||
| 273 | |||
| 224 | enum omap1xxx_index { | 274 | enum omap1xxx_index { |
| 225 | /* UART1 (BT_UART_GATING)*/ | 275 | /* UART1 (BT_UART_GATING)*/ |
| 226 | UART1_TX = 0, | 276 | UART1_TX = 0, |
| @@ -788,7 +838,20 @@ enum omap34xx_index { | |||
| 788 | * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown | 838 | * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown |
| 789 | * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) | 839 | * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) |
| 790 | */ | 840 | */ |
| 841 | AF26_34XX_GPIO0, | ||
| 842 | AF22_34XX_GPIO9, | ||
| 791 | AH8_34XX_GPIO29, | 843 | AH8_34XX_GPIO29, |
| 844 | U8_34XX_GPIO54_OUT, | ||
| 845 | U8_34XX_GPIO54_DOWN, | ||
| 846 | L8_34XX_GPIO63, | ||
| 847 | G25_34XX_GPIO86_OUT, | ||
| 848 | AG4_34XX_GPIO134_OUT, | ||
| 849 | AE4_34XX_GPIO136_OUT, | ||
| 850 | AF6_34XX_GPIO140_UP, | ||
| 851 | AE6_34XX_GPIO141, | ||
| 852 | AF5_34XX_GPIO142, | ||
| 853 | AE5_34XX_GPIO143, | ||
| 854 | H19_34XX_GPIO164_OUT, | ||
| 792 | J25_34XX_GPIO170, | 855 | J25_34XX_GPIO170, |
| 793 | }; | 856 | }; |
| 794 | 857 | ||
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h index 8e0479fff05a..ab640151d3ec 100644 --- a/arch/arm/plat-omap/include/mach/omap34xx.h +++ b/arch/arm/plat-omap/include/mach/omap34xx.h | |||
| @@ -49,11 +49,39 @@ | |||
| 49 | #define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE | 49 | #define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE |
| 50 | 50 | ||
| 51 | #define OMAP34XX_IC_BASE 0x48200000 | 51 | #define OMAP34XX_IC_BASE 0x48200000 |
| 52 | |||
| 53 | #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) | ||
| 54 | #define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100) | ||
| 55 | #define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400) | ||
| 56 | #define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600) | ||
| 57 | #define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00) | ||
| 58 | #define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00) | ||
| 59 | #define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00) | ||
| 60 | #define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) | ||
| 61 | #define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) | ||
| 62 | #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) | ||
| 63 | #define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800) | ||
| 64 | #define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970) | ||
| 65 | |||
| 66 | #define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) | ||
| 67 | #define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) | ||
| 68 | #define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF) | ||
| 69 | #define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7) | ||
| 70 | #define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047) | ||
| 71 | #define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F) | ||
| 72 | #define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F) | ||
| 73 | #define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) | ||
| 74 | #define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) | ||
| 75 | #define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) | ||
| 76 | #define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F) | ||
| 77 | #define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007) | ||
| 78 | |||
| 52 | #define OMAP34XX_IVA_INTC_BASE 0x40000000 | 79 | #define OMAP34XX_IVA_INTC_BASE 0x40000000 |
| 53 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) | 80 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) |
| 54 | #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) | 81 | #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) |
| 55 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) | 82 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) |
| 56 | 83 | ||
| 84 | #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) | ||
| 57 | 85 | ||
| 58 | #if defined(CONFIG_ARCH_OMAP3430) | 86 | #if defined(CONFIG_ARCH_OMAP3430) |
| 59 | 87 | ||
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/mach/omap850.h new file mode 100644 index 000000000000..c33f67981712 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap850.h | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | /* arch/arm/plat-omap/include/mach/omap850.h | ||
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP850 processor. | ||
| 4 | * | ||
| 5 | * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP850_H | ||
| 29 | #define __ASM_ARCH_OMAP850_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * ---------------------------------------------------------------------------- | ||
| 33 | * Base addresses | ||
| 34 | * ---------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
| 38 | |||
| 39 | #define OMAP850_DSP_BASE 0xE0000000 | ||
| 40 | #define OMAP850_DSP_SIZE 0x50000 | ||
| 41 | #define OMAP850_DSP_START 0xE0000000 | ||
| 42 | |||
| 43 | #define OMAP850_DSPREG_BASE 0xE1000000 | ||
| 44 | #define OMAP850_DSPREG_SIZE SZ_128K | ||
| 45 | #define OMAP850_DSPREG_START 0xE1000000 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * ---------------------------------------------------------------------------- | ||
| 49 | * OMAP850 specific configuration registers | ||
| 50 | * ---------------------------------------------------------------------------- | ||
| 51 | */ | ||
| 52 | #define OMAP850_CONFIG_BASE 0xfffe1000 | ||
| 53 | #define OMAP850_IO_CONF_0 0xfffe1070 | ||
| 54 | #define OMAP850_IO_CONF_1 0xfffe1074 | ||
| 55 | #define OMAP850_IO_CONF_2 0xfffe1078 | ||
| 56 | #define OMAP850_IO_CONF_3 0xfffe107c | ||
| 57 | #define OMAP850_IO_CONF_4 0xfffe1080 | ||
| 58 | #define OMAP850_IO_CONF_5 0xfffe1084 | ||
| 59 | #define OMAP850_IO_CONF_6 0xfffe1088 | ||
| 60 | #define OMAP850_IO_CONF_7 0xfffe108c | ||
| 61 | #define OMAP850_IO_CONF_8 0xfffe1090 | ||
| 62 | #define OMAP850_IO_CONF_9 0xfffe1094 | ||
| 63 | #define OMAP850_IO_CONF_10 0xfffe1098 | ||
| 64 | #define OMAP850_IO_CONF_11 0xfffe109c | ||
| 65 | #define OMAP850_IO_CONF_12 0xfffe10a0 | ||
| 66 | #define OMAP850_IO_CONF_13 0xfffe10a4 | ||
| 67 | |||
| 68 | #define OMAP850_MODE_1 0xfffe1010 | ||
| 69 | #define OMAP850_MODE_2 0xfffe1014 | ||
| 70 | |||
| 71 | /* CSMI specials: in terms of base + offset */ | ||
| 72 | #define OMAP850_MODE2_OFFSET 0x14 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * ---------------------------------------------------------------------------- | ||
| 76 | * OMAP850 traffic controller configuration registers | ||
| 77 | * ---------------------------------------------------------------------------- | ||
| 78 | */ | ||
| 79 | #define OMAP850_FLASH_CFG_0 0xfffecc10 | ||
| 80 | #define OMAP850_FLASH_ACFG_0 0xfffecc50 | ||
| 81 | #define OMAP850_FLASH_CFG_1 0xfffecc14 | ||
| 82 | #define OMAP850_FLASH_ACFG_1 0xfffecc54 | ||
| 83 | |||
| 84 | /* | ||
| 85 | * ---------------------------------------------------------------------------- | ||
| 86 | * OMAP850 DSP control registers | ||
| 87 | * ---------------------------------------------------------------------------- | ||
| 88 | */ | ||
| 89 | #define OMAP850_ICR_BASE 0xfffbb800 | ||
| 90 | #define OMAP850_DSP_M_CTL 0xfffbb804 | ||
| 91 | #define OMAP850_DSP_MMU_BASE 0xfffed200 | ||
| 92 | |||
| 93 | /* | ||
| 94 | * ---------------------------------------------------------------------------- | ||
| 95 | * OMAP850 PCC_UPLD configuration registers | ||
| 96 | * ---------------------------------------------------------------------------- | ||
| 97 | */ | ||
| 98 | #define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
| 99 | #define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00) | ||
| 100 | |||
| 101 | #endif /* __ASM_ARCH_OMAP850_H */ | ||
| 102 | |||
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h index 37e2f0f38b46..ce6ee7927537 100644 --- a/arch/arm/plat-omap/include/mach/pm.h +++ b/arch/arm/plat-omap/include/mach/pm.h | |||
| @@ -118,18 +118,6 @@ | |||
| 118 | extern void prevent_idle_sleep(void); | 118 | extern void prevent_idle_sleep(void); |
| 119 | extern void allow_idle_sleep(void); | 119 | extern void allow_idle_sleep(void); |
| 120 | 120 | ||
| 121 | /** | ||
| 122 | * clk_deny_idle - Prevents the clock from being idled during MPU idle | ||
| 123 | * @clk: clock signal handle | ||
| 124 | */ | ||
| 125 | void clk_deny_idle(struct clk *clk); | ||
| 126 | |||
| 127 | /** | ||
| 128 | * clk_allow_idle - Counters previous clk_deny_idle | ||
| 129 | * @clk: clock signal handle | ||
| 130 | */ | ||
| 131 | void clk_allow_idle(struct clk *clk); | ||
| 132 | |||
| 133 | extern void omap_pm_idle(void); | 121 | extern void omap_pm_idle(void); |
| 134 | extern void omap_pm_suspend(void); | 122 | extern void omap_pm_suspend(void); |
| 135 | extern void omap730_cpu_suspend(unsigned short, unsigned short); | 123 | extern void omap730_cpu_suspend(unsigned short, unsigned short); |
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h index 2806a9c8e4d7..69c9e675d8ee 100644 --- a/arch/arm/plat-omap/include/mach/powerdomain.h +++ b/arch/arm/plat-omap/include/mach/powerdomain.h | |||
| @@ -50,9 +50,9 @@ | |||
| 50 | 50 | ||
| 51 | /* | 51 | /* |
| 52 | * Maximum number of clockdomains that can be associated with a powerdomain. | 52 | * Maximum number of clockdomains that can be associated with a powerdomain. |
| 53 | * CORE powerdomain is probably the worst case. | 53 | * CORE powerdomain on OMAP3 is the worst case |
| 54 | */ | 54 | */ |
| 55 | #define PWRDM_MAX_CLKDMS 3 | 55 | #define PWRDM_MAX_CLKDMS 4 |
| 56 | 56 | ||
| 57 | /* XXX A completely arbitrary number. What is reasonable here? */ | 57 | /* XXX A completely arbitrary number. What is reasonable here? */ |
| 58 | #define PWRDM_TRANSITION_BAILOUT 100000 | 58 | #define PWRDM_TRANSITION_BAILOUT 100000 |
| @@ -145,6 +145,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); | |||
| 145 | 145 | ||
| 146 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); | 146 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); |
| 147 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); | 147 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); |
| 148 | int pwrdm_read_pwrst(struct powerdomain *pwrdm); | ||
| 148 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); | 149 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); |
| 149 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); | 150 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); |
| 150 | 151 | ||
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h index 56eba0fd6f6a..24ac3c715912 100644 --- a/arch/arm/plat-omap/include/mach/prcm.h +++ b/arch/arm/plat-omap/include/mach/prcm.h | |||
| @@ -20,10 +20,11 @@ | |||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ | 21 | */ |
| 22 | 22 | ||
| 23 | #ifndef __ASM_ARM_ARCH_DPM_PRCM_H | 23 | #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H |
| 24 | #define __ASM_ARM_ARCH_DPM_PRCM_H | 24 | #define __ASM_ARM_ARCH_OMAP_PRCM_H |
| 25 | 25 | ||
| 26 | u32 omap_prcm_get_reset_sources(void); | 26 | u32 omap_prcm_get_reset_sources(void); |
| 27 | void omap_prcm_arch_reset(char mode); | ||
| 27 | 28 | ||
| 28 | #endif | 29 | #endif |
| 29 | 30 | ||
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h index a98c6c3beb2c..adc73522491f 100644 --- a/arch/arm/plat-omap/include/mach/sdrc.h +++ b/arch/arm/plat-omap/include/mach/sdrc.h | |||
| @@ -4,10 +4,12 @@ | |||
| 4 | /* | 4 | /* |
| 5 | * OMAP2/3 SDRC/SMS register definitions | 5 | * OMAP2/3 SDRC/SMS register definitions |
| 6 | * | 6 | * |
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 8 | * Copyright (C) 2007 Nokia Corporation | 8 | * Copyright (C) 2007-2008 Nokia Corporation |
| 9 | * | 9 | * |
| 10 | * Written by Paul Walmsley | 10 | * Tony Lindgren |
| 11 | * Paul Walmsley | ||
| 12 | * Richard Woodruff | ||
| 11 | * | 13 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 14 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as | 15 | * it under the terms of the GNU General Public License version 2 as |
| @@ -64,14 +66,62 @@ | |||
| 64 | * SMS register access | 66 | * SMS register access |
| 65 | */ | 67 | */ |
| 66 | 68 | ||
| 67 | 69 | #define OMAP242X_SMS_REGADDR(reg) \ | |
| 68 | #define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg) | 70 | (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
| 69 | #define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg) | 71 | #define OMAP243X_SMS_REGADDR(reg) \ |
| 70 | #define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg) | 72 | (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) |
| 73 | #define OMAP343X_SMS_REGADDR(reg) \ | ||
| 74 | (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) | ||
| 71 | 75 | ||
| 72 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ | 76 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ |
| 73 | 77 | ||
| 74 | #define SMS_SYSCONFIG 0x010 | 78 | #define SMS_SYSCONFIG 0x010 |
| 75 | /* REVISIT: fill in other SMS registers here */ | 79 | /* REVISIT: fill in other SMS registers here */ |
| 76 | 80 | ||
| 81 | |||
| 82 | #ifndef __ASSEMBLER__ | ||
| 83 | |||
| 84 | /** | ||
| 85 | * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate | ||
| 86 | * @rate: SDRC clock rate (in Hz) | ||
| 87 | * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate | ||
| 88 | * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate | ||
| 89 | * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate | ||
| 90 | * @mr: Value to program to SDRC_MR for this rate | ||
| 91 | * | ||
| 92 | * This structure holds a pre-computed set of register values for the | ||
| 93 | * SDRC for a given SDRC clock rate and SDRAM chip. These are | ||
| 94 | * intended to be pre-computed and specified in an array in the board-*.c | ||
| 95 | * files. The structure is keyed off the 'rate' field. | ||
| 96 | */ | ||
| 97 | struct omap_sdrc_params { | ||
| 98 | unsigned long rate; | ||
| 99 | u32 actim_ctrla; | ||
| 100 | u32 actim_ctrlb; | ||
| 101 | u32 rfr_ctrl; | ||
| 102 | u32 mr; | ||
| 103 | }; | ||
| 104 | |||
| 105 | void __init omap2_sdrc_init(struct omap_sdrc_params *sp); | ||
| 106 | struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r); | ||
| 107 | |||
| 108 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 109 | |||
| 110 | struct memory_timings { | ||
| 111 | u32 m_type; /* ddr = 1, sdr = 0 */ | ||
| 112 | u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ | ||
| 113 | u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ | ||
| 114 | u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ | ||
| 115 | u32 base_cs; /* base chip select to use for calculations */ | ||
| 116 | }; | ||
| 117 | |||
| 118 | extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); | ||
| 119 | |||
| 120 | u32 omap2xxx_sdrc_dll_is_unlocked(void); | ||
| 121 | u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); | ||
| 122 | |||
| 123 | #endif /* CONFIG_ARCH_OMAP2 */ | ||
| 124 | |||
| 125 | #endif /* __ASSEMBLER__ */ | ||
| 126 | |||
| 77 | #endif | 127 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h index 06923f261545..1060e345423b 100644 --- a/arch/arm/plat-omap/include/mach/system.h +++ b/arch/arm/plat-omap/include/mach/system.h | |||
| @@ -9,12 +9,14 @@ | |||
| 9 | #include <asm/mach-types.h> | 9 | #include <asm/mach-types.h> |
| 10 | #include <mach/hardware.h> | 10 | #include <mach/hardware.h> |
| 11 | 11 | ||
| 12 | #include <mach/prcm.h> | ||
| 13 | |||
| 12 | #ifndef CONFIG_MACH_VOICEBLUE | 14 | #ifndef CONFIG_MACH_VOICEBLUE |
| 13 | #define voiceblue_reset() do {} while (0) | 15 | #define voiceblue_reset() do {} while (0) |
| 16 | #else | ||
| 17 | extern void voiceblue_reset(void); | ||
| 14 | #endif | 18 | #endif |
| 15 | 19 | ||
| 16 | extern void omap_prcm_arch_reset(char mode); | ||
| 17 | |||
| 18 | static inline void arch_idle(void) | 20 | static inline void arch_idle(void) |
| 19 | { | 21 | { |
| 20 | cpu_do_idle(); | 22 | cpu_do_idle(); |
| @@ -38,7 +40,7 @@ static inline void omap1_arch_reset(char mode) | |||
| 38 | omap_writew(1, ARM_RSTCT1); | 40 | omap_writew(1, ARM_RSTCT1); |
| 39 | } | 41 | } |
| 40 | 42 | ||
| 41 | static inline void arch_reset(char mode) | 43 | static inline void arch_reset(char mode, const char *cmd) |
| 42 | { | 44 | { |
| 43 | if (!cpu_class_is_omap2()) | 45 | if (!cpu_class_is_omap2()) |
| 44 | omap1_arch_reset(mode); | 46 | omap1_arch_reset(mode); |
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h index a56a610950c2..69f0ceed500b 100644 --- a/arch/arm/plat-omap/include/mach/usb.h +++ b/arch/arm/plat-omap/include/mach/usb.h | |||
| @@ -27,8 +27,18 @@ | |||
| 27 | #define UDC_BASE OMAP2_UDC_BASE | 27 | #define UDC_BASE OMAP2_UDC_BASE |
| 28 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE | 28 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE |
| 29 | 29 | ||
| 30 | #ifdef CONFIG_USB_MUSB_SOC | ||
| 31 | extern void usb_musb_init(void); | ||
| 32 | #else | ||
| 33 | static inline void usb_musb_init(void) | ||
| 34 | { | ||
| 35 | } | ||
| 36 | #endif | ||
| 37 | |||
| 30 | #endif | 38 | #endif |
| 31 | 39 | ||
| 40 | void omap_usb_init(struct omap_usb_config *pdata); | ||
| 41 | |||
| 32 | /*-------------------------------------------------------------------------*/ | 42 | /*-------------------------------------------------------------------------*/ |
| 33 | 43 | ||
| 34 | /* | 44 | /* |
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index b52ce053e6f2..0abfbaa59871 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
| @@ -1,10 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP mailbox driver | 2 | * OMAP mailbox driver |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 Nokia Corporation. All rights reserved. | 4 | * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. |
| 5 | * | 5 | * |
| 6 | * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com> | 6 | * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| 7 | * Restructured by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
| 8 | * | 7 | * |
| 9 | * This program is free software; you can redistribute it and/or | 8 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License | 9 | * modify it under the terms of the GNU General Public License |
| @@ -22,21 +21,98 @@ | |||
| 22 | * | 21 | * |
| 23 | */ | 22 | */ |
| 24 | 23 | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/module.h> | 24 | #include <linux/module.h> |
| 27 | #include <linux/sched.h> | ||
| 28 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 29 | #include <linux/device.h> | 26 | #include <linux/device.h> |
| 30 | #include <linux/blkdev.h> | ||
| 31 | #include <linux/err.h> | ||
| 32 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 33 | #include <linux/io.h> | 28 | |
| 34 | #include <mach/mailbox.h> | 29 | #include <mach/mailbox.h> |
| 35 | #include "mailbox.h" | 30 | |
| 31 | static int enable_seq_bit; | ||
| 32 | module_param(enable_seq_bit, bool, 0); | ||
| 33 | MODULE_PARM_DESC(enable_seq_bit, "Enable sequence bit checking."); | ||
| 36 | 34 | ||
| 37 | static struct omap_mbox *mboxes; | 35 | static struct omap_mbox *mboxes; |
| 38 | static DEFINE_RWLOCK(mboxes_lock); | 36 | static DEFINE_RWLOCK(mboxes_lock); |
| 39 | 37 | ||
| 38 | /* | ||
| 39 | * Mailbox sequence bit API | ||
| 40 | */ | ||
| 41 | |||
| 42 | /* seq_rcv should be initialized with any value other than | ||
| 43 | * 0 and 1 << 31, to allow either value for the first | ||
| 44 | * message. */ | ||
| 45 | static inline void mbox_seq_init(struct omap_mbox *mbox) | ||
| 46 | { | ||
| 47 | if (!enable_seq_bit) | ||
| 48 | return; | ||
| 49 | |||
| 50 | /* any value other than 0 and 1 << 31 */ | ||
| 51 | mbox->seq_rcv = 0xffffffff; | ||
| 52 | } | ||
| 53 | |||
| 54 | static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg) | ||
| 55 | { | ||
| 56 | if (!enable_seq_bit) | ||
| 57 | return; | ||
| 58 | |||
| 59 | /* add seq_snd to msg */ | ||
| 60 | *msg = (*msg & 0x7fffffff) | mbox->seq_snd; | ||
| 61 | /* flip seq_snd */ | ||
| 62 | mbox->seq_snd ^= 1 << 31; | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 66 | { | ||
| 67 | mbox_msg_t seq; | ||
| 68 | |||
| 69 | if (!enable_seq_bit) | ||
| 70 | return 0; | ||
| 71 | |||
| 72 | seq = msg & (1 << 31); | ||
| 73 | if (seq == mbox->seq_rcv) | ||
| 74 | return -1; | ||
| 75 | mbox->seq_rcv = seq; | ||
| 76 | return 0; | ||
| 77 | } | ||
| 78 | |||
| 79 | /* Mailbox FIFO handle functions */ | ||
| 80 | static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) | ||
| 81 | { | ||
| 82 | return mbox->ops->fifo_read(mbox); | ||
| 83 | } | ||
| 84 | static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 85 | { | ||
| 86 | mbox->ops->fifo_write(mbox, msg); | ||
| 87 | } | ||
| 88 | static inline int mbox_fifo_empty(struct omap_mbox *mbox) | ||
| 89 | { | ||
| 90 | return mbox->ops->fifo_empty(mbox); | ||
| 91 | } | ||
| 92 | static inline int mbox_fifo_full(struct omap_mbox *mbox) | ||
| 93 | { | ||
| 94 | return mbox->ops->fifo_full(mbox); | ||
| 95 | } | ||
| 96 | |||
| 97 | /* Mailbox IRQ handle functions */ | ||
| 98 | static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 99 | { | ||
| 100 | mbox->ops->enable_irq(mbox, irq); | ||
| 101 | } | ||
| 102 | static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 103 | { | ||
| 104 | mbox->ops->disable_irq(mbox, irq); | ||
| 105 | } | ||
| 106 | static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 107 | { | ||
| 108 | if (mbox->ops->ack_irq) | ||
| 109 | mbox->ops->ack_irq(mbox, irq); | ||
| 110 | } | ||
| 111 | static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 112 | { | ||
| 113 | return mbox->ops->is_irq(mbox, irq); | ||
| 114 | } | ||
| 115 | |||
| 40 | /* Mailbox Sequence Bit function */ | 116 | /* Mailbox Sequence Bit function */ |
| 41 | void omap_mbox_init_seq(struct omap_mbox *mbox) | 117 | void omap_mbox_init_seq(struct omap_mbox *mbox) |
| 42 | { | 118 | { |
| @@ -136,7 +212,7 @@ static void mbox_rx_work(struct work_struct *work) | |||
| 136 | unsigned long flags; | 212 | unsigned long flags; |
| 137 | 213 | ||
| 138 | if (mbox->rxq->callback == NULL) { | 214 | if (mbox->rxq->callback == NULL) { |
| 139 | sysfs_notify(&mbox->dev.kobj, NULL, "mbox"); | 215 | sysfs_notify(&mbox->dev->kobj, NULL, "mbox"); |
| 140 | return; | 216 | return; |
| 141 | } | 217 | } |
| 142 | 218 | ||
| @@ -204,7 +280,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox) | |||
| 204 | /* no more messages in the fifo. clear IRQ source. */ | 280 | /* no more messages in the fifo. clear IRQ source. */ |
| 205 | ack_mbox_irq(mbox, IRQ_RX); | 281 | ack_mbox_irq(mbox, IRQ_RX); |
| 206 | enable_mbox_irq(mbox, IRQ_RX); | 282 | enable_mbox_irq(mbox, IRQ_RX); |
| 207 | nomem: | 283 | nomem: |
| 208 | schedule_work(&mbox->rxq->work); | 284 | schedule_work(&mbox->rxq->work); |
| 209 | } | 285 | } |
| 210 | 286 | ||
| @@ -286,7 +362,7 @@ static ssize_t mbox_show(struct class *class, char *buf) | |||
| 286 | static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL); | 362 | static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL); |
| 287 | 363 | ||
| 288 | static struct class omap_mbox_class = { | 364 | static struct class omap_mbox_class = { |
| 289 | .name = "omap_mbox", | 365 | .name = "omap-mailbox", |
| 290 | }; | 366 | }; |
| 291 | 367 | ||
| 292 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, | 368 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, |
| @@ -333,21 +409,6 @@ static int omap_mbox_init(struct omap_mbox *mbox) | |||
| 333 | return ret; | 409 | return ret; |
| 334 | } | 410 | } |
| 335 | 411 | ||
| 336 | mbox->dev.class = &omap_mbox_class; | ||
| 337 | dev_set_name(&mbox->dev, "%s", mbox->name); | ||
| 338 | dev_set_drvdata(&mbox->dev, mbox); | ||
| 339 | |||
| 340 | ret = device_register(&mbox->dev); | ||
| 341 | if (unlikely(ret)) | ||
| 342 | goto fail_device_reg; | ||
| 343 | |||
| 344 | ret = device_create_file(&mbox->dev, &dev_attr_mbox); | ||
| 345 | if (unlikely(ret)) { | ||
| 346 | printk(KERN_ERR | ||
| 347 | "device_create_file failed: %d\n", ret); | ||
| 348 | goto fail_create_mbox; | ||
| 349 | } | ||
| 350 | |||
| 351 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED, | 412 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED, |
| 352 | mbox->name, mbox); | 413 | mbox->name, mbox); |
| 353 | if (unlikely(ret)) { | 414 | if (unlikely(ret)) { |
| @@ -377,10 +438,6 @@ static int omap_mbox_init(struct omap_mbox *mbox) | |||
| 377 | fail_alloc_txq: | 438 | fail_alloc_txq: |
| 378 | free_irq(mbox->irq, mbox); | 439 | free_irq(mbox->irq, mbox); |
| 379 | fail_request_irq: | 440 | fail_request_irq: |
| 380 | device_remove_file(&mbox->dev, &dev_attr_mbox); | ||
| 381 | fail_create_mbox: | ||
| 382 | device_unregister(&mbox->dev); | ||
| 383 | fail_device_reg: | ||
| 384 | if (unlikely(mbox->ops->shutdown)) | 441 | if (unlikely(mbox->ops->shutdown)) |
| 385 | mbox->ops->shutdown(mbox); | 442 | mbox->ops->shutdown(mbox); |
| 386 | 443 | ||
| @@ -393,8 +450,6 @@ static void omap_mbox_fini(struct omap_mbox *mbox) | |||
| 393 | mbox_queue_free(mbox->rxq); | 450 | mbox_queue_free(mbox->rxq); |
| 394 | 451 | ||
| 395 | free_irq(mbox->irq, mbox); | 452 | free_irq(mbox->irq, mbox); |
| 396 | device_remove_file(&mbox->dev, &dev_attr_mbox); | ||
| 397 | class_unregister(&omap_mbox_class); | ||
| 398 | 453 | ||
| 399 | if (unlikely(mbox->ops->shutdown)) | 454 | if (unlikely(mbox->ops->shutdown)) |
| 400 | mbox->ops->shutdown(mbox); | 455 | mbox->ops->shutdown(mbox); |
| @@ -440,7 +495,7 @@ void omap_mbox_put(struct omap_mbox *mbox) | |||
| 440 | } | 495 | } |
| 441 | EXPORT_SYMBOL(omap_mbox_put); | 496 | EXPORT_SYMBOL(omap_mbox_put); |
| 442 | 497 | ||
| 443 | int omap_mbox_register(struct omap_mbox *mbox) | 498 | int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) |
| 444 | { | 499 | { |
| 445 | int ret = 0; | 500 | int ret = 0; |
| 446 | struct omap_mbox **tmp; | 501 | struct omap_mbox **tmp; |
| @@ -450,14 +505,31 @@ int omap_mbox_register(struct omap_mbox *mbox) | |||
| 450 | if (mbox->next) | 505 | if (mbox->next) |
| 451 | return -EBUSY; | 506 | return -EBUSY; |
| 452 | 507 | ||
| 508 | mbox->dev = device_create(&omap_mbox_class, | ||
| 509 | parent, 0, mbox, "%s", mbox->name); | ||
| 510 | if (IS_ERR(mbox->dev)) | ||
| 511 | return PTR_ERR(mbox->dev); | ||
| 512 | |||
| 513 | ret = device_create_file(mbox->dev, &dev_attr_mbox); | ||
| 514 | if (ret) | ||
| 515 | goto err_sysfs; | ||
| 516 | |||
| 453 | write_lock(&mboxes_lock); | 517 | write_lock(&mboxes_lock); |
| 454 | tmp = find_mboxes(mbox->name); | 518 | tmp = find_mboxes(mbox->name); |
| 455 | if (*tmp) | 519 | if (*tmp) { |
| 456 | ret = -EBUSY; | 520 | ret = -EBUSY; |
| 457 | else | 521 | write_unlock(&mboxes_lock); |
| 458 | *tmp = mbox; | 522 | goto err_find; |
| 523 | } | ||
| 524 | *tmp = mbox; | ||
| 459 | write_unlock(&mboxes_lock); | 525 | write_unlock(&mboxes_lock); |
| 460 | 526 | ||
| 527 | return 0; | ||
| 528 | |||
| 529 | err_find: | ||
| 530 | device_remove_file(mbox->dev, &dev_attr_mbox); | ||
| 531 | err_sysfs: | ||
| 532 | device_unregister(mbox->dev); | ||
| 461 | return ret; | 533 | return ret; |
| 462 | } | 534 | } |
| 463 | EXPORT_SYMBOL(omap_mbox_register); | 535 | EXPORT_SYMBOL(omap_mbox_register); |
| @@ -473,6 +545,8 @@ int omap_mbox_unregister(struct omap_mbox *mbox) | |||
| 473 | *tmp = mbox->next; | 545 | *tmp = mbox->next; |
| 474 | mbox->next = NULL; | 546 | mbox->next = NULL; |
| 475 | write_unlock(&mboxes_lock); | 547 | write_unlock(&mboxes_lock); |
| 548 | device_remove_file(mbox->dev, &dev_attr_mbox); | ||
| 549 | device_unregister(mbox->dev); | ||
| 476 | return 0; | 550 | return 0; |
| 477 | } | 551 | } |
| 478 | tmp = &(*tmp)->next; | 552 | tmp = &(*tmp)->next; |
| @@ -501,4 +575,6 @@ static void __exit omap_mbox_class_exit(void) | |||
| 501 | subsys_initcall(omap_mbox_class_init); | 575 | subsys_initcall(omap_mbox_class_init); |
| 502 | module_exit(omap_mbox_class_exit); | 576 | module_exit(omap_mbox_class_exit); |
| 503 | 577 | ||
| 504 | MODULE_LICENSE("GPL"); | 578 | MODULE_LICENSE("GPL v2"); |
| 579 | MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); | ||
| 580 | MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU"); | ||
diff --git a/arch/arm/plat-omap/mailbox.h b/arch/arm/plat-omap/mailbox.h deleted file mode 100644 index 67c6740b8ad5..000000000000 --- a/arch/arm/plat-omap/mailbox.h +++ /dev/null | |||
| @@ -1,100 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Mailbox internal functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Nokia Corporation | ||
| 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
| 6 | * | ||
| 7 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 8 | * License. See the file "COPYING" in the main directory of this archive | ||
| 9 | * for more details. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ARCH_ARM_PLAT_MAILBOX_H | ||
| 13 | #define __ARCH_ARM_PLAT_MAILBOX_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Mailbox sequence bit API | ||
| 17 | */ | ||
| 18 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 19 | # define MBOX_USE_SEQ_BIT | ||
| 20 | #elif defined(CONFIG_ARCH_OMAP2) | ||
| 21 | # define MBOX_USE_SEQ_BIT | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #ifdef MBOX_USE_SEQ_BIT | ||
| 25 | /* seq_rcv should be initialized with any value other than | ||
| 26 | * 0 and 1 << 31, to allow either value for the first | ||
| 27 | * message. */ | ||
| 28 | static inline void mbox_seq_init(struct omap_mbox *mbox) | ||
| 29 | { | ||
| 30 | /* any value other than 0 and 1 << 31 */ | ||
| 31 | mbox->seq_rcv = 0xffffffff; | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg) | ||
| 35 | { | ||
| 36 | /* add seq_snd to msg */ | ||
| 37 | *msg = (*msg & 0x7fffffff) | mbox->seq_snd; | ||
| 38 | /* flip seq_snd */ | ||
| 39 | mbox->seq_snd ^= 1 << 31; | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 43 | { | ||
| 44 | mbox_msg_t seq = msg & (1 << 31); | ||
| 45 | if (seq == mbox->seq_rcv) | ||
| 46 | return -1; | ||
| 47 | mbox->seq_rcv = seq; | ||
| 48 | return 0; | ||
| 49 | } | ||
| 50 | #else | ||
| 51 | static inline void mbox_seq_init(struct omap_mbox *mbox) | ||
| 52 | { | ||
| 53 | } | ||
| 54 | static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg) | ||
| 55 | { | ||
| 56 | } | ||
| 57 | static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 58 | { | ||
| 59 | return 0; | ||
| 60 | } | ||
| 61 | #endif | ||
| 62 | |||
| 63 | /* Mailbox FIFO handle functions */ | ||
| 64 | static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) | ||
| 65 | { | ||
| 66 | return mbox->ops->fifo_read(mbox); | ||
| 67 | } | ||
| 68 | static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 69 | { | ||
| 70 | mbox->ops->fifo_write(mbox, msg); | ||
| 71 | } | ||
| 72 | static inline int mbox_fifo_empty(struct omap_mbox *mbox) | ||
| 73 | { | ||
| 74 | return mbox->ops->fifo_empty(mbox); | ||
| 75 | } | ||
| 76 | static inline int mbox_fifo_full(struct omap_mbox *mbox) | ||
| 77 | { | ||
| 78 | return mbox->ops->fifo_full(mbox); | ||
| 79 | } | ||
| 80 | |||
| 81 | /* Mailbox IRQ handle functions */ | ||
| 82 | static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 83 | { | ||
| 84 | mbox->ops->enable_irq(mbox, irq); | ||
| 85 | } | ||
| 86 | static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 87 | { | ||
| 88 | mbox->ops->disable_irq(mbox, irq); | ||
| 89 | } | ||
| 90 | static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 91 | { | ||
| 92 | if (mbox->ops->ack_irq) | ||
| 93 | mbox->ops->ack_irq(mbox, irq); | ||
| 94 | } | ||
| 95 | static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 96 | { | ||
| 97 | return mbox->ops->is_irq(mbox, irq); | ||
| 98 | } | ||
| 99 | |||
| 100 | #endif /* __ARCH_ARM_PLAT_MAILBOX_H */ | ||
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e5842e30e534..28b0a824b8cf 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
| @@ -214,7 +214,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type); | |||
| 214 | int omap_mcbsp_request(unsigned int id) | 214 | int omap_mcbsp_request(unsigned int id) |
| 215 | { | 215 | { |
| 216 | struct omap_mcbsp *mcbsp; | 216 | struct omap_mcbsp *mcbsp; |
| 217 | int i; | ||
| 218 | int err; | 217 | int err; |
| 219 | 218 | ||
| 220 | if (!omap_mcbsp_check_valid_id(id)) { | 219 | if (!omap_mcbsp_check_valid_id(id)) { |
| @@ -223,23 +222,23 @@ int omap_mcbsp_request(unsigned int id) | |||
| 223 | } | 222 | } |
| 224 | mcbsp = id_to_mcbsp_ptr(id); | 223 | mcbsp = id_to_mcbsp_ptr(id); |
| 225 | 224 | ||
| 226 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) | ||
| 227 | mcbsp->pdata->ops->request(id); | ||
| 228 | |||
| 229 | for (i = 0; i < mcbsp->num_clks; i++) | ||
| 230 | clk_enable(mcbsp->clks[i]); | ||
| 231 | |||
| 232 | spin_lock(&mcbsp->lock); | 225 | spin_lock(&mcbsp->lock); |
| 233 | if (!mcbsp->free) { | 226 | if (!mcbsp->free) { |
| 234 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", | 227 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", |
| 235 | mcbsp->id); | 228 | mcbsp->id); |
| 236 | spin_unlock(&mcbsp->lock); | 229 | spin_unlock(&mcbsp->lock); |
| 237 | return -1; | 230 | return -EBUSY; |
| 238 | } | 231 | } |
| 239 | 232 | ||
| 240 | mcbsp->free = 0; | 233 | mcbsp->free = 0; |
| 241 | spin_unlock(&mcbsp->lock); | 234 | spin_unlock(&mcbsp->lock); |
| 242 | 235 | ||
| 236 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) | ||
| 237 | mcbsp->pdata->ops->request(id); | ||
| 238 | |||
| 239 | clk_enable(mcbsp->iclk); | ||
| 240 | clk_enable(mcbsp->fclk); | ||
| 241 | |||
| 243 | /* | 242 | /* |
| 244 | * Make sure that transmitter, receiver and sample-rate generator are | 243 | * Make sure that transmitter, receiver and sample-rate generator are |
| 245 | * not running before activating IRQs. | 244 | * not running before activating IRQs. |
| @@ -278,7 +277,6 @@ EXPORT_SYMBOL(omap_mcbsp_request); | |||
| 278 | void omap_mcbsp_free(unsigned int id) | 277 | void omap_mcbsp_free(unsigned int id) |
| 279 | { | 278 | { |
| 280 | struct omap_mcbsp *mcbsp; | 279 | struct omap_mcbsp *mcbsp; |
| 281 | int i; | ||
| 282 | 280 | ||
| 283 | if (!omap_mcbsp_check_valid_id(id)) { | 281 | if (!omap_mcbsp_check_valid_id(id)) { |
| 284 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | 282 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); |
| @@ -289,8 +287,14 @@ void omap_mcbsp_free(unsigned int id) | |||
| 289 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) | 287 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) |
| 290 | mcbsp->pdata->ops->free(id); | 288 | mcbsp->pdata->ops->free(id); |
| 291 | 289 | ||
| 292 | for (i = mcbsp->num_clks - 1; i >= 0; i--) | 290 | clk_disable(mcbsp->fclk); |
| 293 | clk_disable(mcbsp->clks[i]); | 291 | clk_disable(mcbsp->iclk); |
| 292 | |||
| 293 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { | ||
| 294 | /* Free IRQs */ | ||
| 295 | free_irq(mcbsp->rx_irq, (void *)mcbsp); | ||
| 296 | free_irq(mcbsp->tx_irq, (void *)mcbsp); | ||
| 297 | } | ||
| 294 | 298 | ||
| 295 | spin_lock(&mcbsp->lock); | 299 | spin_lock(&mcbsp->lock); |
| 296 | if (mcbsp->free) { | 300 | if (mcbsp->free) { |
| @@ -302,12 +306,6 @@ void omap_mcbsp_free(unsigned int id) | |||
| 302 | 306 | ||
| 303 | mcbsp->free = 1; | 307 | mcbsp->free = 1; |
| 304 | spin_unlock(&mcbsp->lock); | 308 | spin_unlock(&mcbsp->lock); |
| 305 | |||
| 306 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { | ||
| 307 | /* Free IRQs */ | ||
| 308 | free_irq(mcbsp->rx_irq, (void *)mcbsp); | ||
| 309 | free_irq(mcbsp->tx_irq, (void *)mcbsp); | ||
| 310 | } | ||
| 311 | } | 309 | } |
| 312 | EXPORT_SYMBOL(omap_mcbsp_free); | 310 | EXPORT_SYMBOL(omap_mcbsp_free); |
| 313 | 311 | ||
| @@ -876,7 +874,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) | |||
| 876 | struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; | 874 | struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; |
| 877 | struct omap_mcbsp *mcbsp; | 875 | struct omap_mcbsp *mcbsp; |
| 878 | int id = pdev->id - 1; | 876 | int id = pdev->id - 1; |
| 879 | int i; | ||
| 880 | int ret = 0; | 877 | int ret = 0; |
| 881 | 878 | ||
| 882 | if (!pdata) { | 879 | if (!pdata) { |
| @@ -899,7 +896,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) | |||
| 899 | ret = -ENOMEM; | 896 | ret = -ENOMEM; |
| 900 | goto exit; | 897 | goto exit; |
| 901 | } | 898 | } |
| 902 | mcbsp_ptr[id] = mcbsp; | ||
| 903 | 899 | ||
| 904 | spin_lock_init(&mcbsp->lock); | 900 | spin_lock_init(&mcbsp->lock); |
| 905 | mcbsp->id = id + 1; | 901 | mcbsp->id = id + 1; |
| @@ -921,39 +917,32 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) | |||
| 921 | mcbsp->dma_rx_sync = pdata->dma_rx_sync; | 917 | mcbsp->dma_rx_sync = pdata->dma_rx_sync; |
| 922 | mcbsp->dma_tx_sync = pdata->dma_tx_sync; | 918 | mcbsp->dma_tx_sync = pdata->dma_tx_sync; |
| 923 | 919 | ||
| 924 | if (pdata->num_clks) { | 920 | mcbsp->iclk = clk_get(&pdev->dev, "ick"); |
| 925 | mcbsp->num_clks = pdata->num_clks; | 921 | if (IS_ERR(mcbsp->iclk)) { |
| 926 | mcbsp->clks = kzalloc(mcbsp->num_clks * sizeof(struct clk *), | 922 | ret = PTR_ERR(mcbsp->iclk); |
| 927 | GFP_KERNEL); | 923 | dev_err(&pdev->dev, "unable to get ick: %d\n", ret); |
| 928 | if (!mcbsp->clks) { | 924 | goto err_iclk; |
| 929 | ret = -ENOMEM; | 925 | } |
| 930 | goto exit; | ||
| 931 | } | ||
| 932 | for (i = 0; i < mcbsp->num_clks; i++) { | ||
| 933 | mcbsp->clks[i] = clk_get(&pdev->dev, pdata->clk_names[i]); | ||
| 934 | if (IS_ERR(mcbsp->clks[i])) { | ||
| 935 | dev_err(&pdev->dev, | ||
| 936 | "Invalid %s configuration for McBSP%d.\n", | ||
| 937 | pdata->clk_names[i], mcbsp->id); | ||
| 938 | ret = PTR_ERR(mcbsp->clks[i]); | ||
| 939 | goto err_clk; | ||
| 940 | } | ||
| 941 | } | ||
| 942 | 926 | ||
| 927 | mcbsp->fclk = clk_get(&pdev->dev, "fck"); | ||
| 928 | if (IS_ERR(mcbsp->fclk)) { | ||
| 929 | ret = PTR_ERR(mcbsp->fclk); | ||
| 930 | dev_err(&pdev->dev, "unable to get fck: %d\n", ret); | ||
| 931 | goto err_fclk; | ||
| 943 | } | 932 | } |
| 944 | 933 | ||
| 945 | mcbsp->pdata = pdata; | 934 | mcbsp->pdata = pdata; |
| 946 | mcbsp->dev = &pdev->dev; | 935 | mcbsp->dev = &pdev->dev; |
| 936 | mcbsp_ptr[id] = mcbsp; | ||
| 947 | platform_set_drvdata(pdev, mcbsp); | 937 | platform_set_drvdata(pdev, mcbsp); |
| 948 | return 0; | 938 | return 0; |
| 949 | 939 | ||
| 950 | err_clk: | 940 | err_fclk: |
| 951 | while (i--) | 941 | clk_put(mcbsp->iclk); |
| 952 | clk_put(mcbsp->clks[i]); | 942 | err_iclk: |
| 953 | kfree(mcbsp->clks); | ||
| 954 | iounmap(mcbsp->io_base); | 943 | iounmap(mcbsp->io_base); |
| 955 | err_ioremap: | 944 | err_ioremap: |
| 956 | mcbsp->free = 0; | 945 | kfree(mcbsp); |
| 957 | exit: | 946 | exit: |
| 958 | return ret; | 947 | return ret; |
| 959 | } | 948 | } |
| @@ -961,7 +950,6 @@ exit: | |||
| 961 | static int __devexit omap_mcbsp_remove(struct platform_device *pdev) | 950 | static int __devexit omap_mcbsp_remove(struct platform_device *pdev) |
| 962 | { | 951 | { |
| 963 | struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); | 952 | struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); |
| 964 | int i; | ||
| 965 | 953 | ||
| 966 | platform_set_drvdata(pdev, NULL); | 954 | platform_set_drvdata(pdev, NULL); |
| 967 | if (mcbsp) { | 955 | if (mcbsp) { |
| @@ -970,18 +958,15 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) | |||
| 970 | mcbsp->pdata->ops->free) | 958 | mcbsp->pdata->ops->free) |
| 971 | mcbsp->pdata->ops->free(mcbsp->id); | 959 | mcbsp->pdata->ops->free(mcbsp->id); |
| 972 | 960 | ||
| 973 | for (i = mcbsp->num_clks - 1; i >= 0; i--) { | 961 | clk_disable(mcbsp->fclk); |
| 974 | clk_disable(mcbsp->clks[i]); | 962 | clk_disable(mcbsp->iclk); |
| 975 | clk_put(mcbsp->clks[i]); | 963 | clk_put(mcbsp->fclk); |
| 976 | } | 964 | clk_put(mcbsp->iclk); |
| 977 | 965 | ||
| 978 | iounmap(mcbsp->io_base); | 966 | iounmap(mcbsp->io_base); |
| 979 | 967 | ||
| 980 | if (mcbsp->num_clks) { | 968 | mcbsp->fclk = NULL; |
| 981 | kfree(mcbsp->clks); | 969 | mcbsp->iclk = NULL; |
| 982 | mcbsp->clks = NULL; | ||
| 983 | mcbsp->num_clks = 0; | ||
| 984 | } | ||
| 985 | mcbsp->free = 0; | 970 | mcbsp->free = 0; |
| 986 | mcbsp->dev = NULL; | 971 | mcbsp->dev = NULL; |
| 987 | } | 972 | } |
| @@ -1002,4 +987,3 @@ int __init omap_mcbsp_init(void) | |||
| 1002 | /* Register the McBSP driver */ | 987 | /* Register the McBSP driver */ |
| 1003 | return platform_driver_register(&omap_mcbsp_driver); | 988 | return platform_driver_register(&omap_mcbsp_driver); |
| 1004 | } | 989 | } |
| 1005 | |||
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index be7bcaf2b832..fa5297d643d3 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
| @@ -148,7 +148,7 @@ void __init omap_detect_sram(void) | |||
| 148 | omap_sram_base = OMAP1_SRAM_VA; | 148 | omap_sram_base = OMAP1_SRAM_VA; |
| 149 | omap_sram_start = OMAP1_SRAM_PA; | 149 | omap_sram_start = OMAP1_SRAM_PA; |
| 150 | 150 | ||
| 151 | if (cpu_is_omap730()) | 151 | if (cpu_is_omap7xx()) |
| 152 | omap_sram_size = 0x32000; /* 200K */ | 152 | omap_sram_size = 0x32000; /* 200K */ |
| 153 | else if (cpu_is_omap15xx()) | 153 | else if (cpu_is_omap15xx()) |
| 154 | omap_sram_size = 0x30000; /* 192K */ | 154 | omap_sram_size = 0x30000; /* 192K */ |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index e278de6862ae..509f2ed99e21 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c | |||
| @@ -729,30 +729,13 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {} | |||
| 729 | 729 | ||
| 730 | /*-------------------------------------------------------------------------*/ | 730 | /*-------------------------------------------------------------------------*/ |
| 731 | 731 | ||
| 732 | static struct omap_usb_config platform_data; | 732 | void __init omap_usb_init(struct omap_usb_config *pdata) |
| 733 | |||
| 734 | static int __init | ||
| 735 | omap_usb_init(void) | ||
| 736 | { | 733 | { |
| 737 | const struct omap_usb_config *config; | ||
| 738 | |||
| 739 | config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config); | ||
| 740 | if (config == NULL) { | ||
| 741 | printk(KERN_ERR "USB: No board-specific " | ||
| 742 | "platform config found\n"); | ||
| 743 | return -ENODEV; | ||
| 744 | } | ||
| 745 | platform_data = *config; | ||
| 746 | |||
| 747 | if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) | 734 | if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) |
| 748 | omap_otg_init(&platform_data); | 735 | omap_otg_init(pdata); |
| 749 | else if (cpu_is_omap15xx()) | 736 | else if (cpu_is_omap15xx()) |
| 750 | omap_1510_usb_init(&platform_data); | 737 | omap_1510_usb_init(pdata); |
| 751 | else { | 738 | else |
| 752 | printk(KERN_ERR "USB: No init for your chip yet\n"); | 739 | printk(KERN_ERR "USB: No init for your chip yet\n"); |
| 753 | return -ENODEV; | ||
| 754 | } | ||
| 755 | return 0; | ||
| 756 | } | 740 | } |
| 757 | 741 | ||
| 758 | subsys_initcall(omap_usb_init); | ||
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 0d12c2164766..32eb9e33bebb 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c | |||
| @@ -19,7 +19,8 @@ | |||
| 19 | 19 | ||
| 20 | static DEFINE_SPINLOCK(gpio_lock); | 20 | static DEFINE_SPINLOCK(gpio_lock); |
| 21 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ | 21 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ |
| 22 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; | 22 | static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)]; |
| 23 | static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)]; | ||
| 23 | 24 | ||
| 24 | static inline void __set_direction(unsigned pin, int input) | 25 | static inline void __set_direction(unsigned pin, int input) |
| 25 | { | 26 | { |
| @@ -53,7 +54,7 @@ int gpio_direction_input(unsigned pin) | |||
| 53 | { | 54 | { |
| 54 | unsigned long flags; | 55 | unsigned long flags; |
| 55 | 56 | ||
| 56 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 57 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_input)) { |
| 57 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 58 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 58 | return -EINVAL; | 59 | return -EINVAL; |
| 59 | } | 60 | } |
| @@ -83,7 +84,7 @@ int gpio_direction_output(unsigned pin, int value) | |||
| 83 | unsigned long flags; | 84 | unsigned long flags; |
| 84 | u32 u; | 85 | u32 u; |
| 85 | 86 | ||
| 86 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 87 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_output)) { |
| 87 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 88 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 88 | return -EINVAL; | 89 | return -EINVAL; |
| 89 | } | 90 | } |
| @@ -161,7 +162,9 @@ int gpio_request(unsigned pin, const char *label) | |||
| 161 | unsigned long flags; | 162 | unsigned long flags; |
| 162 | int ret; | 163 | int ret; |
| 163 | 164 | ||
| 164 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 165 | if (pin >= GPIO_MAX || |
| 166 | !(test_bit(pin, gpio_valid_input) || | ||
| 167 | test_bit(pin, gpio_valid_output))) { | ||
| 165 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 168 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 166 | return -EINVAL; | 169 | return -EINVAL; |
| 167 | } | 170 | } |
| @@ -183,7 +186,9 @@ EXPORT_SYMBOL(gpio_request); | |||
| 183 | 186 | ||
| 184 | void gpio_free(unsigned pin) | 187 | void gpio_free(unsigned pin) |
| 185 | { | 188 | { |
| 186 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 189 | if (pin >= GPIO_MAX || |
| 190 | !(test_bit(pin, gpio_valid_input) || | ||
| 191 | test_bit(pin, gpio_valid_output))) { | ||
| 187 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 192 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 188 | return; | 193 | return; |
| 189 | } | 194 | } |
| @@ -208,12 +213,18 @@ void __init orion_gpio_set_unused(unsigned pin) | |||
| 208 | __set_direction(pin, 0); | 213 | __set_direction(pin, 0); |
| 209 | } | 214 | } |
| 210 | 215 | ||
| 211 | void __init orion_gpio_set_valid(unsigned pin, int valid) | 216 | void __init orion_gpio_set_valid(unsigned pin, int mode) |
| 212 | { | 217 | { |
| 213 | if (valid) | 218 | if (mode == 1) |
| 214 | __set_bit(pin, gpio_valid); | 219 | mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; |
| 220 | if (mode & GPIO_INPUT_OK) | ||
| 221 | __set_bit(pin, gpio_valid_input); | ||
| 215 | else | 222 | else |
| 216 | __clear_bit(pin, gpio_valid); | 223 | __clear_bit(pin, gpio_valid_input); |
| 224 | if (mode & GPIO_OUTPUT_OK) | ||
| 225 | __set_bit(pin, gpio_valid_output); | ||
| 226 | else | ||
| 227 | __clear_bit(pin, gpio_valid_output); | ||
| 217 | } | 228 | } |
| 218 | 229 | ||
| 219 | void orion_gpio_set_blink(unsigned pin, int blink) | 230 | void orion_gpio_set_blink(unsigned pin, int blink) |
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h index ec743e82c876..33f6c6aec185 100644 --- a/arch/arm/plat-orion/include/plat/gpio.h +++ b/arch/arm/plat-orion/include/plat/gpio.h | |||
| @@ -25,9 +25,13 @@ void gpio_set_value(unsigned pin, int value); | |||
| 25 | * Orion-specific GPIO API extensions. | 25 | * Orion-specific GPIO API extensions. |
| 26 | */ | 26 | */ |
| 27 | void orion_gpio_set_unused(unsigned pin); | 27 | void orion_gpio_set_unused(unsigned pin); |
| 28 | void orion_gpio_set_valid(unsigned pin, int valid); | ||
| 29 | void orion_gpio_set_blink(unsigned pin, int blink); | 28 | void orion_gpio_set_blink(unsigned pin, int blink); |
| 30 | 29 | ||
| 30 | #define GPIO_BIDI_OK (1 << 0) | ||
| 31 | #define GPIO_INPUT_OK (1 << 1) | ||
| 32 | #define GPIO_OUTPUT_OK (1 << 2) | ||
| 33 | void orion_gpio_set_valid(unsigned pin, int mode); | ||
| 34 | |||
| 31 | /* | 35 | /* |
| 32 | * GPIO interrupt handling. | 36 | * GPIO interrupt handling. |
| 33 | */ | 37 | */ |
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h new file mode 100644 index 000000000000..14ca88676002 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/mvsdio.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/include/plat/mvsdio.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __MACH_MVSDIO_H | ||
| 10 | #define __MACH_MVSDIO_H | ||
| 11 | |||
| 12 | #include <linux/mbus.h> | ||
| 13 | |||
| 14 | struct mvsdio_platform_data { | ||
| 15 | struct mbus_dram_target_info *dram; | ||
| 16 | unsigned int clock; | ||
| 17 | int gpio_card_detect; | ||
| 18 | int gpio_write_protect; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig new file mode 100644 index 000000000000..b158e98038ed --- /dev/null +++ b/arch/arm/plat-pxa/Kconfig | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | if PLAT_PXA | ||
| 2 | |||
| 3 | endif | ||
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile new file mode 100644 index 000000000000..8f2c4c7fbd48 --- /dev/null +++ b/arch/arm/plat-pxa/Makefile | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | # | ||
| 2 | # Makefile for code common across different PXA processor families | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y := dma.o | ||
| 6 | |||
| 7 | obj-$(CONFIG_GENERIC_GPIO) += gpio.o | ||
| 8 | obj-$(CONFIG_PXA3xx) += mfp.o | ||
| 9 | obj-$(CONFIG_ARCH_MMP) += mfp.o | ||
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 7de17fc5d54b..70aeee407f7d 100644 --- a/arch/arm/mach-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/dma.c | 2 | * linux/arch/arm/plat-pxa/dma.c |
| 3 | * | 3 | * |
| 4 | * PXA DMA registration and IRQ dispatching | 4 | * PXA DMA registration and IRQ dispatching |
| 5 | * | 5 | * |
| @@ -23,8 +23,6 @@ | |||
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/dma.h> | 24 | #include <mach/dma.h> |
| 25 | 25 | ||
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | |||
| 28 | struct dma_channel { | 26 | struct dma_channel { |
| 29 | char *name; | 27 | char *name; |
| 30 | pxa_dma_prio prio; | 28 | pxa_dma_prio prio; |
| @@ -36,8 +34,8 @@ static struct dma_channel *dma_channels; | |||
| 36 | static int num_dma_channels; | 34 | static int num_dma_channels; |
| 37 | 35 | ||
| 38 | int pxa_request_dma (char *name, pxa_dma_prio prio, | 36 | int pxa_request_dma (char *name, pxa_dma_prio prio, |
| 39 | void (*irq_handler)(int, void *), | 37 | void (*irq_handler)(int, void *), |
| 40 | void *data) | 38 | void *data) |
| 41 | { | 39 | { |
| 42 | unsigned long flags; | 40 | unsigned long flags; |
| 43 | int i, found = 0; | 41 | int i, found = 0; |
| @@ -113,7 +111,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) | |||
| 113 | return IRQ_HANDLED; | 111 | return IRQ_HANDLED; |
| 114 | } | 112 | } |
| 115 | 113 | ||
| 116 | int __init pxa_init_dma(int num_ch) | 114 | int __init pxa_init_dma(int irq, int num_ch) |
| 117 | { | 115 | { |
| 118 | int i, ret; | 116 | int i, ret; |
| 119 | 117 | ||
| @@ -131,7 +129,7 @@ int __init pxa_init_dma(int num_ch) | |||
| 131 | dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); | 129 | dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); |
| 132 | } | 130 | } |
| 133 | 131 | ||
| 134 | ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); | 132 | ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); |
| 135 | if (ret) { | 133 | if (ret) { |
| 136 | printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); | 134 | printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); |
| 137 | kfree(dma_channels); | 135 | kfree(dma_channels); |
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c new file mode 100644 index 000000000000..af819bf21b63 --- /dev/null +++ b/arch/arm/plat-pxa/gpio.c | |||
| @@ -0,0 +1,337 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-pxa/gpio.c | ||
| 3 | * | ||
| 4 | * Generic PXA GPIO handling | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Created: Jun 15, 2001 | ||
| 8 | * Copyright: MontaVista Software Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/sysdev.h> | ||
| 19 | #include <linux/bootmem.h> | ||
| 20 | |||
| 21 | #include <mach/gpio.h> | ||
| 22 | |||
| 23 | int pxa_last_gpio; | ||
| 24 | |||
| 25 | struct pxa_gpio_chip { | ||
| 26 | struct gpio_chip chip; | ||
| 27 | void __iomem *regbase; | ||
| 28 | char label[10]; | ||
| 29 | |||
| 30 | unsigned long irq_mask; | ||
| 31 | unsigned long irq_edge_rise; | ||
| 32 | unsigned long irq_edge_fall; | ||
| 33 | |||
| 34 | #ifdef CONFIG_PM | ||
| 35 | unsigned long saved_gplr; | ||
| 36 | unsigned long saved_gpdr; | ||
| 37 | unsigned long saved_grer; | ||
| 38 | unsigned long saved_gfer; | ||
| 39 | #endif | ||
| 40 | }; | ||
| 41 | |||
| 42 | static DEFINE_SPINLOCK(gpio_lock); | ||
| 43 | static struct pxa_gpio_chip *pxa_gpio_chips; | ||
| 44 | |||
| 45 | #define for_each_gpio_chip(i, c) \ | ||
| 46 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) | ||
| 47 | |||
| 48 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) | ||
| 49 | { | ||
| 50 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio) | ||
| 54 | { | ||
| 55 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; | ||
| 56 | } | ||
| 57 | |||
| 58 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 59 | { | ||
| 60 | void __iomem *base = gpio_chip_base(chip); | ||
| 61 | uint32_t value, mask = 1 << offset; | ||
| 62 | unsigned long flags; | ||
| 63 | |||
| 64 | spin_lock_irqsave(&gpio_lock, flags); | ||
| 65 | |||
| 66 | value = __raw_readl(base + GPDR_OFFSET); | ||
| 67 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 68 | value |= mask; | ||
| 69 | else | ||
| 70 | value &= ~mask; | ||
| 71 | __raw_writel(value, base + GPDR_OFFSET); | ||
| 72 | |||
| 73 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
| 74 | return 0; | ||
| 75 | } | ||
| 76 | |||
| 77 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | ||
| 78 | unsigned offset, int value) | ||
| 79 | { | ||
| 80 | void __iomem *base = gpio_chip_base(chip); | ||
| 81 | uint32_t tmp, mask = 1 << offset; | ||
| 82 | unsigned long flags; | ||
| 83 | |||
| 84 | __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); | ||
| 85 | |||
| 86 | spin_lock_irqsave(&gpio_lock, flags); | ||
| 87 | |||
| 88 | tmp = __raw_readl(base + GPDR_OFFSET); | ||
| 89 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 90 | tmp &= ~mask; | ||
| 91 | else | ||
| 92 | tmp |= mask; | ||
| 93 | __raw_writel(tmp, base + GPDR_OFFSET); | ||
| 94 | |||
| 95 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
| 96 | return 0; | ||
| 97 | } | ||
| 98 | |||
| 99 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 100 | { | ||
| 101 | return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); | ||
| 102 | } | ||
| 103 | |||
| 104 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 105 | { | ||
| 106 | __raw_writel(1 << offset, gpio_chip_base(chip) + | ||
| 107 | (value ? GPSR_OFFSET : GPCR_OFFSET)); | ||
| 108 | } | ||
| 109 | |||
| 110 | static int __init pxa_init_gpio_chip(int gpio_end) | ||
| 111 | { | ||
| 112 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; | ||
| 113 | struct pxa_gpio_chip *chips; | ||
| 114 | |||
| 115 | /* this is early, we have to use bootmem allocator, and we really | ||
| 116 | * want this to be allocated dynamically for different 'gpio_end' | ||
| 117 | */ | ||
| 118 | chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip)); | ||
| 119 | if (chips == NULL) { | ||
| 120 | pr_err("%s: failed to allocate GPIO chips\n", __func__); | ||
| 121 | return -ENOMEM; | ||
| 122 | } | ||
| 123 | |||
| 124 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { | ||
| 125 | struct gpio_chip *c = &chips[i].chip; | ||
| 126 | |||
| 127 | sprintf(chips[i].label, "gpio-%d", i); | ||
| 128 | chips[i].regbase = (void __iomem *)GPIO_BANK(i); | ||
| 129 | |||
| 130 | c->base = gpio; | ||
| 131 | c->label = chips[i].label; | ||
| 132 | |||
| 133 | c->direction_input = pxa_gpio_direction_input; | ||
| 134 | c->direction_output = pxa_gpio_direction_output; | ||
| 135 | c->get = pxa_gpio_get; | ||
| 136 | c->set = pxa_gpio_set; | ||
| 137 | |||
| 138 | /* number of GPIOs on last bank may be less than 32 */ | ||
| 139 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; | ||
| 140 | gpiochip_add(c); | ||
| 141 | } | ||
| 142 | pxa_gpio_chips = chips; | ||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | ||
| 147 | { | ||
| 148 | struct pxa_gpio_chip *c; | ||
| 149 | int gpio = irq_to_gpio(irq); | ||
| 150 | unsigned long gpdr, mask = GPIO_bit(gpio); | ||
| 151 | |||
| 152 | c = gpio_to_chip(gpio); | ||
| 153 | |||
| 154 | if (type == IRQ_TYPE_PROBE) { | ||
| 155 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
| 156 | * GPIOs set to alternate function or to output during probe | ||
| 157 | */ | ||
| 158 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) | ||
| 159 | return 0; | ||
| 160 | |||
| 161 | if (__gpio_is_occupied(gpio)) | ||
| 162 | return 0; | ||
| 163 | |||
| 164 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | ||
| 165 | } | ||
| 166 | |||
| 167 | gpdr = __raw_readl(c->regbase + GPDR_OFFSET); | ||
| 168 | |||
| 169 | if (__gpio_is_inverted(gpio)) | ||
| 170 | __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET); | ||
| 171 | else | ||
| 172 | __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET); | ||
| 173 | |||
| 174 | if (type & IRQ_TYPE_EDGE_RISING) | ||
| 175 | c->irq_edge_rise |= mask; | ||
| 176 | else | ||
| 177 | c->irq_edge_rise &= ~mask; | ||
| 178 | |||
| 179 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
| 180 | c->irq_edge_fall |= mask; | ||
| 181 | else | ||
| 182 | c->irq_edge_fall &= ~mask; | ||
| 183 | |||
| 184 | __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); | ||
| 185 | __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); | ||
| 186 | |||
| 187 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | ||
| 188 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | ||
| 189 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | ||
| 190 | return 0; | ||
| 191 | } | ||
| 192 | |||
| 193 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | ||
| 194 | { | ||
| 195 | struct pxa_gpio_chip *c; | ||
| 196 | int loop, gpio, gpio_base, n; | ||
| 197 | unsigned long gedr; | ||
| 198 | |||
| 199 | do { | ||
| 200 | loop = 0; | ||
| 201 | for_each_gpio_chip(gpio, c) { | ||
| 202 | gpio_base = c->chip.base; | ||
| 203 | |||
| 204 | gedr = __raw_readl(c->regbase + GEDR_OFFSET); | ||
| 205 | gedr = gedr & c->irq_mask; | ||
| 206 | __raw_writel(gedr, c->regbase + GEDR_OFFSET); | ||
| 207 | |||
| 208 | n = find_first_bit(&gedr, BITS_PER_LONG); | ||
| 209 | while (n < BITS_PER_LONG) { | ||
| 210 | loop = 1; | ||
| 211 | |||
| 212 | generic_handle_irq(gpio_to_irq(gpio_base + n)); | ||
| 213 | n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); | ||
| 214 | } | ||
| 215 | } | ||
| 216 | } while (loop); | ||
| 217 | } | ||
| 218 | |||
| 219 | static void pxa_ack_muxed_gpio(unsigned int irq) | ||
| 220 | { | ||
| 221 | int gpio = irq_to_gpio(irq); | ||
| 222 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | ||
| 223 | |||
| 224 | __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); | ||
| 225 | } | ||
| 226 | |||
| 227 | static void pxa_mask_muxed_gpio(unsigned int irq) | ||
| 228 | { | ||
| 229 | int gpio = irq_to_gpio(irq); | ||
| 230 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | ||
| 231 | uint32_t grer, gfer; | ||
| 232 | |||
| 233 | c->irq_mask &= ~GPIO_bit(gpio); | ||
| 234 | |||
| 235 | grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); | ||
| 236 | gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); | ||
| 237 | __raw_writel(grer, c->regbase + GRER_OFFSET); | ||
| 238 | __raw_writel(gfer, c->regbase + GFER_OFFSET); | ||
| 239 | } | ||
| 240 | |||
| 241 | static void pxa_unmask_muxed_gpio(unsigned int irq) | ||
| 242 | { | ||
| 243 | int gpio = irq_to_gpio(irq); | ||
| 244 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | ||
| 245 | |||
| 246 | c->irq_mask |= GPIO_bit(gpio); | ||
| 247 | __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); | ||
| 248 | __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); | ||
| 249 | } | ||
| 250 | |||
| 251 | static struct irq_chip pxa_muxed_gpio_chip = { | ||
| 252 | .name = "GPIO", | ||
| 253 | .ack = pxa_ack_muxed_gpio, | ||
| 254 | .mask = pxa_mask_muxed_gpio, | ||
| 255 | .unmask = pxa_unmask_muxed_gpio, | ||
| 256 | .set_type = pxa_gpio_irq_type, | ||
| 257 | }; | ||
| 258 | |||
| 259 | void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) | ||
| 260 | { | ||
| 261 | struct pxa_gpio_chip *c; | ||
| 262 | int gpio, irq; | ||
| 263 | |||
| 264 | pxa_last_gpio = end; | ||
| 265 | |||
| 266 | /* Initialize GPIO chips */ | ||
| 267 | pxa_init_gpio_chip(end); | ||
| 268 | |||
| 269 | /* clear all GPIO edge detects */ | ||
| 270 | for_each_gpio_chip(gpio, c) { | ||
| 271 | __raw_writel(0, c->regbase + GFER_OFFSET); | ||
| 272 | __raw_writel(0, c->regbase + GRER_OFFSET); | ||
| 273 | __raw_writel(~0,c->regbase + GEDR_OFFSET); | ||
| 274 | } | ||
| 275 | |||
| 276 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { | ||
| 277 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | ||
| 278 | set_irq_handler(irq, handle_edge_irq); | ||
| 279 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 280 | } | ||
| 281 | |||
| 282 | /* Install handler for GPIO>=2 edge detect interrupts */ | ||
| 283 | set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); | ||
| 284 | pxa_muxed_gpio_chip.set_wake = fn; | ||
| 285 | } | ||
| 286 | |||
| 287 | #ifdef CONFIG_PM | ||
| 288 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) | ||
| 289 | { | ||
| 290 | struct pxa_gpio_chip *c; | ||
| 291 | int gpio; | ||
| 292 | |||
| 293 | for_each_gpio_chip(gpio, c) { | ||
| 294 | c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET); | ||
| 295 | c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET); | ||
| 296 | c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET); | ||
| 297 | c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET); | ||
| 298 | |||
| 299 | /* Clear GPIO transition detect bits */ | ||
| 300 | __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET); | ||
| 301 | } | ||
| 302 | return 0; | ||
| 303 | } | ||
| 304 | |||
| 305 | static int pxa_gpio_resume(struct sys_device *dev) | ||
| 306 | { | ||
| 307 | struct pxa_gpio_chip *c; | ||
| 308 | int gpio; | ||
| 309 | |||
| 310 | for_each_gpio_chip(gpio, c) { | ||
| 311 | /* restore level with set/clear */ | ||
| 312 | __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET); | ||
| 313 | __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET); | ||
| 314 | |||
| 315 | __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET); | ||
| 316 | __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET); | ||
| 317 | __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET); | ||
| 318 | } | ||
| 319 | return 0; | ||
| 320 | } | ||
| 321 | #else | ||
| 322 | #define pxa_gpio_suspend NULL | ||
| 323 | #define pxa_gpio_resume NULL | ||
| 324 | #endif | ||
| 325 | |||
| 326 | struct sysdev_class pxa_gpio_sysclass = { | ||
| 327 | .name = "gpio", | ||
| 328 | .suspend = pxa_gpio_suspend, | ||
| 329 | .resume = pxa_gpio_resume, | ||
| 330 | }; | ||
| 331 | |||
| 332 | static int __init pxa_gpio_init(void) | ||
| 333 | { | ||
| 334 | return sysdev_class_register(&pxa_gpio_sysclass); | ||
| 335 | } | ||
| 336 | |||
| 337 | core_initcall(pxa_gpio_init); | ||
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h new file mode 100644 index 000000000000..a7b91dc06852 --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/dma.h | |||
| @@ -0,0 +1,85 @@ | |||
| 1 | #ifndef __PLAT_DMA_H | ||
| 2 | #define __PLAT_DMA_H | ||
| 3 | |||
| 4 | #define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x)))) | ||
| 5 | |||
| 6 | #define DCSR(n) DMAC_REG((n) << 2) | ||
| 7 | #define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */ | ||
| 8 | #define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */ | ||
| 9 | #define DDADR(n) DMAC_REG(0x0200 + ((n) << 4)) | ||
| 10 | #define DSADR(n) DMAC_REG(0x0204 + ((n) << 4)) | ||
| 11 | #define DTADR(n) DMAC_REG(0x0208 + ((n) << 4)) | ||
| 12 | #define DCMD(n) DMAC_REG(0x020c + ((n) << 4)) | ||
| 13 | #define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \ | ||
| 14 | (((n) & 0x3f) << 2)) | ||
| 15 | |||
| 16 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | ||
| 17 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | ||
| 18 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | ||
| 19 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
| 20 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
| 21 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
| 22 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
| 23 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
| 24 | |||
| 25 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | ||
| 26 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
| 27 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
| 28 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | ||
| 29 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | ||
| 30 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | ||
| 31 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | ||
| 32 | |||
| 33 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ | ||
| 34 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | ||
| 35 | |||
| 36 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | ||
| 37 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | ||
| 38 | |||
| 39 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | ||
| 40 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | ||
| 41 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | ||
| 42 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | ||
| 43 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
| 44 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
| 45 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | ||
| 46 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | ||
| 47 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | ||
| 48 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | ||
| 49 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | ||
| 50 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | ||
| 51 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | ||
| 52 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Descriptor structure for PXA's DMA engine | ||
| 56 | * Note: this structure must always be aligned to a 16-byte boundary. | ||
| 57 | */ | ||
| 58 | |||
| 59 | typedef struct pxa_dma_desc { | ||
| 60 | volatile u32 ddadr; /* Points to the next descriptor + flags */ | ||
| 61 | volatile u32 dsadr; /* DSADR value for the current transfer */ | ||
| 62 | volatile u32 dtadr; /* DTADR value for the current transfer */ | ||
| 63 | volatile u32 dcmd; /* DCMD value for the current transfer */ | ||
| 64 | } pxa_dma_desc; | ||
| 65 | |||
| 66 | typedef enum { | ||
| 67 | DMA_PRIO_HIGH = 0, | ||
| 68 | DMA_PRIO_MEDIUM = 1, | ||
| 69 | DMA_PRIO_LOW = 2 | ||
| 70 | } pxa_dma_prio; | ||
| 71 | |||
| 72 | /* | ||
| 73 | * DMA registration | ||
| 74 | */ | ||
| 75 | |||
| 76 | int __init pxa_init_dma(int irq, int num_ch); | ||
| 77 | |||
| 78 | int pxa_request_dma (char *name, | ||
| 79 | pxa_dma_prio prio, | ||
| 80 | void (*irq_handler)(int, void *), | ||
| 81 | void *data); | ||
| 82 | |||
| 83 | void pxa_free_dma (int dma_ch); | ||
| 84 | |||
| 85 | #endif /* __PLAT_DMA_H */ | ||
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h new file mode 100644 index 000000000000..44248cb926a5 --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/gpio.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | #ifndef __PLAT_GPIO_H | ||
| 2 | #define __PLAT_GPIO_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | ||
| 6 | * one set of registers. The register offsets are organized below: | ||
| 7 | * | ||
| 8 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | ||
| 9 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | ||
| 10 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | ||
| 11 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | ||
| 12 | * | ||
| 13 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | ||
| 14 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | ||
| 15 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | ||
| 16 | * | ||
| 17 | * NOTE: | ||
| 18 | * BANK 3 is only available on PXA27x and later processors. | ||
| 19 | * BANK 4 and 5 are only available on PXA935 | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) | ||
| 23 | |||
| 24 | #define GPLR_OFFSET 0x00 | ||
| 25 | #define GPDR_OFFSET 0x0C | ||
| 26 | #define GPSR_OFFSET 0x18 | ||
| 27 | #define GPCR_OFFSET 0x24 | ||
| 28 | #define GRER_OFFSET 0x30 | ||
| 29 | #define GFER_OFFSET 0x3C | ||
| 30 | #define GEDR_OFFSET 0x48 | ||
| 31 | |||
| 32 | static inline int gpio_get_value(unsigned gpio) | ||
| 33 | { | ||
| 34 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) | ||
| 35 | return GPLR(gpio) & GPIO_bit(gpio); | ||
| 36 | else | ||
| 37 | return __gpio_get_value(gpio); | ||
| 38 | } | ||
| 39 | |||
| 40 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 41 | { | ||
| 42 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { | ||
| 43 | if (value) | ||
| 44 | GPSR(gpio) = GPIO_bit(gpio); | ||
| 45 | else | ||
| 46 | GPCR(gpio) = GPIO_bit(gpio); | ||
| 47 | } else | ||
| 48 | __gpio_set_value(gpio, value); | ||
| 49 | } | ||
| 50 | |||
| 51 | #define gpio_cansleep __gpio_cansleep | ||
| 52 | |||
| 53 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). | ||
| 54 | * Those cases currently cause holes in the GPIO number space, the | ||
| 55 | * actual number of the last GPIO is recorded by 'pxa_last_gpio'. | ||
| 56 | */ | ||
| 57 | extern int pxa_last_gpio; | ||
| 58 | |||
| 59 | typedef int (*set_wake_t)(unsigned int irq, unsigned int on); | ||
| 60 | |||
| 61 | extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); | ||
| 62 | #endif /* __PLAT_GPIO_H */ | ||
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h new file mode 100644 index 000000000000..64019464c8db --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/mfp.h | |||
| @@ -0,0 +1,399 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-pxa/include/plat/mfp.h | ||
| 3 | * | ||
| 4 | * Common Multi-Function Pin Definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * 2007-8-21: eric miao <eric.miao@marvell.com> | ||
| 9 | * initial version | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_PLAT_MFP_H | ||
| 17 | #define __ASM_PLAT_MFP_H | ||
| 18 | |||
| 19 | #define mfp_to_gpio(m) ((m) % 128) | ||
| 20 | |||
| 21 | /* list of all the configurable MFP pins */ | ||
| 22 | enum { | ||
| 23 | MFP_PIN_INVALID = -1, | ||
| 24 | |||
| 25 | MFP_PIN_GPIO0 = 0, | ||
| 26 | MFP_PIN_GPIO1, | ||
| 27 | MFP_PIN_GPIO2, | ||
| 28 | MFP_PIN_GPIO3, | ||
| 29 | MFP_PIN_GPIO4, | ||
| 30 | MFP_PIN_GPIO5, | ||
| 31 | MFP_PIN_GPIO6, | ||
| 32 | MFP_PIN_GPIO7, | ||
| 33 | MFP_PIN_GPIO8, | ||
| 34 | MFP_PIN_GPIO9, | ||
| 35 | MFP_PIN_GPIO10, | ||
| 36 | MFP_PIN_GPIO11, | ||
| 37 | MFP_PIN_GPIO12, | ||
| 38 | MFP_PIN_GPIO13, | ||
| 39 | MFP_PIN_GPIO14, | ||
| 40 | MFP_PIN_GPIO15, | ||
| 41 | MFP_PIN_GPIO16, | ||
| 42 | MFP_PIN_GPIO17, | ||
| 43 | MFP_PIN_GPIO18, | ||
| 44 | MFP_PIN_GPIO19, | ||
| 45 | MFP_PIN_GPIO20, | ||
| 46 | MFP_PIN_GPIO21, | ||
| 47 | MFP_PIN_GPIO22, | ||
| 48 | MFP_PIN_GPIO23, | ||
| 49 | MFP_PIN_GPIO24, | ||
| 50 | MFP_PIN_GPIO25, | ||
| 51 | MFP_PIN_GPIO26, | ||
| 52 | MFP_PIN_GPIO27, | ||
| 53 | MFP_PIN_GPIO28, | ||
| 54 | MFP_PIN_GPIO29, | ||
| 55 | MFP_PIN_GPIO30, | ||
| 56 | MFP_PIN_GPIO31, | ||
| 57 | MFP_PIN_GPIO32, | ||
| 58 | MFP_PIN_GPIO33, | ||
| 59 | MFP_PIN_GPIO34, | ||
| 60 | MFP_PIN_GPIO35, | ||
| 61 | MFP_PIN_GPIO36, | ||
| 62 | MFP_PIN_GPIO37, | ||
| 63 | MFP_PIN_GPIO38, | ||
| 64 | MFP_PIN_GPIO39, | ||
| 65 | MFP_PIN_GPIO40, | ||
| 66 | MFP_PIN_GPIO41, | ||
| 67 | MFP_PIN_GPIO42, | ||
| 68 | MFP_PIN_GPIO43, | ||
| 69 | MFP_PIN_GPIO44, | ||
| 70 | MFP_PIN_GPIO45, | ||
| 71 | MFP_PIN_GPIO46, | ||
| 72 | MFP_PIN_GPIO47, | ||
| 73 | MFP_PIN_GPIO48, | ||
| 74 | MFP_PIN_GPIO49, | ||
| 75 | MFP_PIN_GPIO50, | ||
| 76 | MFP_PIN_GPIO51, | ||
| 77 | MFP_PIN_GPIO52, | ||
| 78 | MFP_PIN_GPIO53, | ||
| 79 | MFP_PIN_GPIO54, | ||
| 80 | MFP_PIN_GPIO55, | ||
| 81 | MFP_PIN_GPIO56, | ||
| 82 | MFP_PIN_GPIO57, | ||
| 83 | MFP_PIN_GPIO58, | ||
| 84 | MFP_PIN_GPIO59, | ||
| 85 | MFP_PIN_GPIO60, | ||
| 86 | MFP_PIN_GPIO61, | ||
| 87 | MFP_PIN_GPIO62, | ||
| 88 | MFP_PIN_GPIO63, | ||
| 89 | MFP_PIN_GPIO64, | ||
| 90 | MFP_PIN_GPIO65, | ||
| 91 | MFP_PIN_GPIO66, | ||
| 92 | MFP_PIN_GPIO67, | ||
| 93 | MFP_PIN_GPIO68, | ||
| 94 | MFP_PIN_GPIO69, | ||
| 95 | MFP_PIN_GPIO70, | ||
| 96 | MFP_PIN_GPIO71, | ||
| 97 | MFP_PIN_GPIO72, | ||
| 98 | MFP_PIN_GPIO73, | ||
| 99 | MFP_PIN_GPIO74, | ||
| 100 | MFP_PIN_GPIO75, | ||
| 101 | MFP_PIN_GPIO76, | ||
| 102 | MFP_PIN_GPIO77, | ||
| 103 | MFP_PIN_GPIO78, | ||
| 104 | MFP_PIN_GPIO79, | ||
| 105 | MFP_PIN_GPIO80, | ||
| 106 | MFP_PIN_GPIO81, | ||
| 107 | MFP_PIN_GPIO82, | ||
| 108 | MFP_PIN_GPIO83, | ||
| 109 | MFP_PIN_GPIO84, | ||
| 110 | MFP_PIN_GPIO85, | ||
| 111 | MFP_PIN_GPIO86, | ||
| 112 | MFP_PIN_GPIO87, | ||
| 113 | MFP_PIN_GPIO88, | ||
| 114 | MFP_PIN_GPIO89, | ||
| 115 | MFP_PIN_GPIO90, | ||
| 116 | MFP_PIN_GPIO91, | ||
| 117 | MFP_PIN_GPIO92, | ||
| 118 | MFP_PIN_GPIO93, | ||
| 119 | MFP_PIN_GPIO94, | ||
| 120 | MFP_PIN_GPIO95, | ||
| 121 | MFP_PIN_GPIO96, | ||
| 122 | MFP_PIN_GPIO97, | ||
| 123 | MFP_PIN_GPIO98, | ||
| 124 | MFP_PIN_GPIO99, | ||
| 125 | MFP_PIN_GPIO100, | ||
| 126 | MFP_PIN_GPIO101, | ||
| 127 | MFP_PIN_GPIO102, | ||
| 128 | MFP_PIN_GPIO103, | ||
| 129 | MFP_PIN_GPIO104, | ||
| 130 | MFP_PIN_GPIO105, | ||
| 131 | MFP_PIN_GPIO106, | ||
| 132 | MFP_PIN_GPIO107, | ||
| 133 | MFP_PIN_GPIO108, | ||
| 134 | MFP_PIN_GPIO109, | ||
| 135 | MFP_PIN_GPIO110, | ||
| 136 | MFP_PIN_GPIO111, | ||
| 137 | MFP_PIN_GPIO112, | ||
| 138 | MFP_PIN_GPIO113, | ||
| 139 | MFP_PIN_GPIO114, | ||
| 140 | MFP_PIN_GPIO115, | ||
| 141 | MFP_PIN_GPIO116, | ||
| 142 | MFP_PIN_GPIO117, | ||
| 143 | MFP_PIN_GPIO118, | ||
| 144 | MFP_PIN_GPIO119, | ||
| 145 | MFP_PIN_GPIO120, | ||
| 146 | MFP_PIN_GPIO121, | ||
| 147 | MFP_PIN_GPIO122, | ||
| 148 | MFP_PIN_GPIO123, | ||
| 149 | MFP_PIN_GPIO124, | ||
| 150 | MFP_PIN_GPIO125, | ||
| 151 | MFP_PIN_GPIO126, | ||
| 152 | MFP_PIN_GPIO127, | ||
| 153 | MFP_PIN_GPIO0_2, | ||
| 154 | MFP_PIN_GPIO1_2, | ||
| 155 | MFP_PIN_GPIO2_2, | ||
| 156 | MFP_PIN_GPIO3_2, | ||
| 157 | MFP_PIN_GPIO4_2, | ||
| 158 | MFP_PIN_GPIO5_2, | ||
| 159 | MFP_PIN_GPIO6_2, | ||
| 160 | MFP_PIN_GPIO7_2, | ||
| 161 | MFP_PIN_GPIO8_2, | ||
| 162 | MFP_PIN_GPIO9_2, | ||
| 163 | MFP_PIN_GPIO10_2, | ||
| 164 | MFP_PIN_GPIO11_2, | ||
| 165 | MFP_PIN_GPIO12_2, | ||
| 166 | MFP_PIN_GPIO13_2, | ||
| 167 | MFP_PIN_GPIO14_2, | ||
| 168 | MFP_PIN_GPIO15_2, | ||
| 169 | MFP_PIN_GPIO16_2, | ||
| 170 | MFP_PIN_GPIO17_2, | ||
| 171 | |||
| 172 | MFP_PIN_ULPI_STP, | ||
| 173 | MFP_PIN_ULPI_NXT, | ||
| 174 | MFP_PIN_ULPI_DIR, | ||
| 175 | |||
| 176 | MFP_PIN_nXCVREN, | ||
| 177 | MFP_PIN_DF_CLE_nOE, | ||
| 178 | MFP_PIN_DF_nADV1_ALE, | ||
| 179 | MFP_PIN_DF_SCLK_E, | ||
| 180 | MFP_PIN_DF_SCLK_S, | ||
| 181 | MFP_PIN_nBE0, | ||
| 182 | MFP_PIN_nBE1, | ||
| 183 | MFP_PIN_DF_nADV2_ALE, | ||
| 184 | MFP_PIN_DF_INT_RnB, | ||
| 185 | MFP_PIN_DF_nCS0, | ||
| 186 | MFP_PIN_DF_nCS1, | ||
| 187 | MFP_PIN_nLUA, | ||
| 188 | MFP_PIN_nLLA, | ||
| 189 | MFP_PIN_DF_nWE, | ||
| 190 | MFP_PIN_DF_ALE_nWE, | ||
| 191 | MFP_PIN_DF_nRE_nOE, | ||
| 192 | MFP_PIN_DF_ADDR0, | ||
| 193 | MFP_PIN_DF_ADDR1, | ||
| 194 | MFP_PIN_DF_ADDR2, | ||
| 195 | MFP_PIN_DF_ADDR3, | ||
| 196 | MFP_PIN_DF_IO0, | ||
| 197 | MFP_PIN_DF_IO1, | ||
| 198 | MFP_PIN_DF_IO2, | ||
| 199 | MFP_PIN_DF_IO3, | ||
| 200 | MFP_PIN_DF_IO4, | ||
| 201 | MFP_PIN_DF_IO5, | ||
| 202 | MFP_PIN_DF_IO6, | ||
| 203 | MFP_PIN_DF_IO7, | ||
| 204 | MFP_PIN_DF_IO8, | ||
| 205 | MFP_PIN_DF_IO9, | ||
| 206 | MFP_PIN_DF_IO10, | ||
| 207 | MFP_PIN_DF_IO11, | ||
| 208 | MFP_PIN_DF_IO12, | ||
| 209 | MFP_PIN_DF_IO13, | ||
| 210 | MFP_PIN_DF_IO14, | ||
| 211 | MFP_PIN_DF_IO15, | ||
| 212 | MFP_PIN_DF_nCS0_SM_nCS2, | ||
| 213 | MFP_PIN_DF_nCS1_SM_nCS3, | ||
| 214 | MFP_PIN_SM_nCS0, | ||
| 215 | MFP_PIN_SM_nCS1, | ||
| 216 | MFP_PIN_DF_WEn, | ||
| 217 | MFP_PIN_DF_REn, | ||
| 218 | MFP_PIN_DF_CLE_SM_OEn, | ||
| 219 | MFP_PIN_DF_ALE_SM_WEn, | ||
| 220 | MFP_PIN_DF_RDY0, | ||
| 221 | MFP_PIN_DF_RDY1, | ||
| 222 | |||
| 223 | MFP_PIN_SM_SCLK, | ||
| 224 | MFP_PIN_SM_BE0, | ||
| 225 | MFP_PIN_SM_BE1, | ||
| 226 | MFP_PIN_SM_ADV, | ||
| 227 | MFP_PIN_SM_ADVMUX, | ||
| 228 | MFP_PIN_SM_RDY, | ||
| 229 | |||
| 230 | MFP_PIN_MMC1_DAT7, | ||
| 231 | MFP_PIN_MMC1_DAT6, | ||
| 232 | MFP_PIN_MMC1_DAT5, | ||
| 233 | MFP_PIN_MMC1_DAT4, | ||
| 234 | MFP_PIN_MMC1_DAT3, | ||
| 235 | MFP_PIN_MMC1_DAT2, | ||
| 236 | MFP_PIN_MMC1_DAT1, | ||
| 237 | MFP_PIN_MMC1_DAT0, | ||
| 238 | MFP_PIN_MMC1_CMD, | ||
| 239 | MFP_PIN_MMC1_CLK, | ||
| 240 | MFP_PIN_MMC1_CD, | ||
| 241 | MFP_PIN_MMC1_WP, | ||
| 242 | |||
| 243 | /* additional pins on PXA930 */ | ||
| 244 | MFP_PIN_GSIM_UIO, | ||
| 245 | MFP_PIN_GSIM_UCLK, | ||
| 246 | MFP_PIN_GSIM_UDET, | ||
| 247 | MFP_PIN_GSIM_nURST, | ||
| 248 | MFP_PIN_PMIC_INT, | ||
| 249 | MFP_PIN_RDY, | ||
| 250 | |||
| 251 | MFP_PIN_MAX, | ||
| 252 | }; | ||
| 253 | |||
| 254 | /* | ||
| 255 | * a possible MFP configuration is represented by a 32-bit integer | ||
| 256 | * | ||
| 257 | * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) | ||
| 258 | * bit 10..12 - Alternate Function Selection | ||
| 259 | * bit 13..15 - Drive Strength | ||
| 260 | * bit 16..18 - Low Power Mode State | ||
| 261 | * bit 19..20 - Low Power Mode Edge Detection | ||
| 262 | * bit 21..22 - Run Mode Pull State | ||
| 263 | * | ||
| 264 | * to facilitate the definition, the following macros are provided | ||
| 265 | * | ||
| 266 | * MFP_CFG_DEFAULT - default MFP configuration value, with | ||
| 267 | * alternate function = 0, | ||
| 268 | * drive strength = fast 3mA (MFP_DS03X) | ||
| 269 | * low power mode = default | ||
| 270 | * edge detection = none | ||
| 271 | * | ||
| 272 | * MFP_CFG - default MFPR value with alternate function | ||
| 273 | * MFP_CFG_DRV - default MFPR value with alternate function and | ||
| 274 | * pin drive strength | ||
| 275 | * MFP_CFG_LPM - default MFPR value with alternate function and | ||
| 276 | * low power mode | ||
| 277 | * MFP_CFG_X - default MFPR value with alternate function, | ||
| 278 | * pin drive strength and low power mode | ||
| 279 | */ | ||
| 280 | |||
| 281 | typedef unsigned long mfp_cfg_t; | ||
| 282 | |||
| 283 | #define MFP_PIN(x) ((x) & 0x3ff) | ||
| 284 | |||
| 285 | #define MFP_AF0 (0x0 << 10) | ||
| 286 | #define MFP_AF1 (0x1 << 10) | ||
| 287 | #define MFP_AF2 (0x2 << 10) | ||
| 288 | #define MFP_AF3 (0x3 << 10) | ||
| 289 | #define MFP_AF4 (0x4 << 10) | ||
| 290 | #define MFP_AF5 (0x5 << 10) | ||
| 291 | #define MFP_AF6 (0x6 << 10) | ||
| 292 | #define MFP_AF7 (0x7 << 10) | ||
| 293 | #define MFP_AF_MASK (0x7 << 10) | ||
| 294 | #define MFP_AF(x) (((x) >> 10) & 0x7) | ||
| 295 | |||
| 296 | #define MFP_DS01X (0x0 << 13) | ||
| 297 | #define MFP_DS02X (0x1 << 13) | ||
| 298 | #define MFP_DS03X (0x2 << 13) | ||
| 299 | #define MFP_DS04X (0x3 << 13) | ||
| 300 | #define MFP_DS06X (0x4 << 13) | ||
| 301 | #define MFP_DS08X (0x5 << 13) | ||
| 302 | #define MFP_DS10X (0x6 << 13) | ||
| 303 | #define MFP_DS13X (0x7 << 13) | ||
| 304 | #define MFP_DS_MASK (0x7 << 13) | ||
| 305 | #define MFP_DS(x) (((x) >> 13) & 0x7) | ||
| 306 | |||
| 307 | #define MFP_LPM_DEFAULT (0x0 << 16) | ||
| 308 | #define MFP_LPM_DRIVE_LOW (0x1 << 16) | ||
| 309 | #define MFP_LPM_DRIVE_HIGH (0x2 << 16) | ||
| 310 | #define MFP_LPM_PULL_LOW (0x3 << 16) | ||
| 311 | #define MFP_LPM_PULL_HIGH (0x4 << 16) | ||
| 312 | #define MFP_LPM_FLOAT (0x5 << 16) | ||
| 313 | #define MFP_LPM_INPUT (0x6 << 16) | ||
| 314 | #define MFP_LPM_STATE_MASK (0x7 << 16) | ||
| 315 | #define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) | ||
| 316 | |||
| 317 | #define MFP_LPM_EDGE_NONE (0x0 << 19) | ||
| 318 | #define MFP_LPM_EDGE_RISE (0x1 << 19) | ||
| 319 | #define MFP_LPM_EDGE_FALL (0x2 << 19) | ||
| 320 | #define MFP_LPM_EDGE_BOTH (0x3 << 19) | ||
| 321 | #define MFP_LPM_EDGE_MASK (0x3 << 19) | ||
| 322 | #define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) | ||
| 323 | |||
| 324 | #define MFP_PULL_NONE (0x0 << 21) | ||
| 325 | #define MFP_PULL_LOW (0x1 << 21) | ||
| 326 | #define MFP_PULL_HIGH (0x2 << 21) | ||
| 327 | #define MFP_PULL_BOTH (0x3 << 21) | ||
| 328 | #define MFP_PULL_MASK (0x3 << 21) | ||
| 329 | #define MFP_PULL(x) (((x) >> 21) & 0x3) | ||
| 330 | |||
| 331 | #define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\ | ||
| 332 | MFP_LPM_EDGE_NONE | MFP_PULL_NONE) | ||
| 333 | |||
| 334 | #define MFP_CFG(pin, af) \ | ||
| 335 | ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ | ||
| 336 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) | ||
| 337 | |||
| 338 | #define MFP_CFG_DRV(pin, af, drv) \ | ||
| 339 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ | ||
| 340 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) | ||
| 341 | |||
| 342 | #define MFP_CFG_LPM(pin, af, lpm) \ | ||
| 343 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 344 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) | ||
| 345 | |||
| 346 | #define MFP_CFG_X(pin, af, drv, lpm) \ | ||
| 347 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 348 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) | ||
| 349 | |||
| 350 | #if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP) | ||
| 351 | /* | ||
| 352 | * each MFP pin will have a MFPR register, since the offset of the | ||
| 353 | * register varies between processors, the processor specific code | ||
| 354 | * should initialize the pin offsets by mfp_init() | ||
| 355 | * | ||
| 356 | * mfp_init_base() - accepts a virtual base for all MFPR registers and | ||
| 357 | * initialize the MFP table to a default state | ||
| 358 | * | ||
| 359 | * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which | ||
| 360 | * represents a range of MFP pins from "start" to "end", with the offset | ||
| 361 | * begining at "offset", to define a single pin, let "end" = -1. | ||
| 362 | * | ||
| 363 | * use | ||
| 364 | * | ||
| 365 | * MFP_ADDR_X() to define a range of pins | ||
| 366 | * MFP_ADDR() to define a single pin | ||
| 367 | * MFP_ADDR_END to signal the end of pin offset definitions | ||
| 368 | */ | ||
| 369 | struct mfp_addr_map { | ||
| 370 | unsigned int start; | ||
| 371 | unsigned int end; | ||
| 372 | unsigned long offset; | ||
| 373 | }; | ||
| 374 | |||
| 375 | #define MFP_ADDR_X(start, end, offset) \ | ||
| 376 | { MFP_PIN_##start, MFP_PIN_##end, offset } | ||
| 377 | |||
| 378 | #define MFP_ADDR(pin, offset) \ | ||
| 379 | { MFP_PIN_##pin, -1, offset } | ||
| 380 | |||
| 381 | #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } | ||
| 382 | |||
| 383 | void __init mfp_init_base(unsigned long mfpr_base); | ||
| 384 | void __init mfp_init_addr(struct mfp_addr_map *map); | ||
| 385 | |||
| 386 | /* | ||
| 387 | * mfp_{read, write}() - for direct read/write access to the MFPR register | ||
| 388 | * mfp_config() - for configuring a group of MFPR registers | ||
| 389 | * mfp_config_lpm() - configuring all low power MFPR registers for suspend | ||
| 390 | * mfp_config_run() - configuring all run time MFPR registers after resume | ||
| 391 | */ | ||
| 392 | unsigned long mfp_read(int mfp); | ||
| 393 | void mfp_write(int mfp, unsigned long mfpr_val); | ||
| 394 | void mfp_config(unsigned long *mfp_cfgs, int num); | ||
| 395 | void mfp_config_run(void); | ||
| 396 | void mfp_config_lpm(void); | ||
| 397 | #endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */ | ||
| 398 | |||
| 399 | #endif /* __ASM_PLAT_MFP_H */ | ||
diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c new file mode 100644 index 000000000000..e716c622a17c --- /dev/null +++ b/arch/arm/plat-pxa/mfp.c | |||
| @@ -0,0 +1,278 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-pxa/mfp.c | ||
| 3 | * | ||
| 4 | * Multi-Function Pin Support | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell Internation Ltd. | ||
| 7 | * | ||
| 8 | * 2007-08-21: eric miao <eric.miao@marvell.com> | ||
| 9 | * initial version | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/sysdev.h> | ||
| 21 | |||
| 22 | #include <plat/mfp.h> | ||
| 23 | |||
| 24 | #define MFPR_SIZE (PAGE_SIZE) | ||
| 25 | |||
| 26 | /* MFPR register bit definitions */ | ||
| 27 | #define MFPR_PULL_SEL (0x1 << 15) | ||
| 28 | #define MFPR_PULLUP_EN (0x1 << 14) | ||
| 29 | #define MFPR_PULLDOWN_EN (0x1 << 13) | ||
| 30 | #define MFPR_SLEEP_SEL (0x1 << 9) | ||
| 31 | #define MFPR_SLEEP_OE_N (0x1 << 7) | ||
| 32 | #define MFPR_EDGE_CLEAR (0x1 << 6) | ||
| 33 | #define MFPR_EDGE_FALL_EN (0x1 << 5) | ||
| 34 | #define MFPR_EDGE_RISE_EN (0x1 << 4) | ||
| 35 | |||
| 36 | #define MFPR_SLEEP_DATA(x) ((x) << 8) | ||
| 37 | #define MFPR_DRIVE(x) (((x) & 0x7) << 10) | ||
| 38 | #define MFPR_AF_SEL(x) (((x) & 0x7) << 0) | ||
| 39 | |||
| 40 | #define MFPR_EDGE_NONE (0) | ||
| 41 | #define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) | ||
| 42 | #define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) | ||
| 43 | #define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Table that determines the low power modes outputs, with actual settings | ||
| 47 | * used in parentheses for don't-care values. Except for the float output, | ||
| 48 | * the configured driven and pulled levels match, so if there is a need for | ||
| 49 | * non-LPM pulled output, the same configuration could probably be used. | ||
| 50 | * | ||
| 51 | * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel | ||
| 52 | * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) | ||
| 53 | * | ||
| 54 | * Input 0 X(0) X(0) X(0) 0 | ||
| 55 | * Drive 0 0 0 0 X(1) 0 | ||
| 56 | * Drive 1 0 1 X(1) 0 0 | ||
| 57 | * Pull hi (1) 1 X(1) 1 0 0 | ||
| 58 | * Pull lo (0) 1 X(0) 0 1 0 | ||
| 59 | * Z (float) 1 X(0) 0 0 0 | ||
| 60 | */ | ||
| 61 | #define MFPR_LPM_INPUT (0) | ||
| 62 | #define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) | ||
| 63 | #define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) | ||
| 64 | #define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) | ||
| 65 | #define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) | ||
| 66 | #define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) | ||
| 67 | #define MFPR_LPM_MASK (0xe080) | ||
| 68 | |||
| 69 | /* | ||
| 70 | * The pullup and pulldown state of the MFP pin at run mode is by default | ||
| 71 | * determined by the selected alternate function. In case that some buggy | ||
| 72 | * devices need to override this default behavior, the definitions below | ||
| 73 | * indicates the setting of corresponding MFPR bits | ||
| 74 | * | ||
| 75 | * Definition pull_sel pullup_en pulldown_en | ||
| 76 | * MFPR_PULL_NONE 0 0 0 | ||
| 77 | * MFPR_PULL_LOW 1 0 1 | ||
| 78 | * MFPR_PULL_HIGH 1 1 0 | ||
| 79 | * MFPR_PULL_BOTH 1 1 1 | ||
| 80 | */ | ||
| 81 | #define MFPR_PULL_NONE (0) | ||
| 82 | #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) | ||
| 83 | #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) | ||
| 84 | #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) | ||
| 85 | |||
| 86 | /* mfp_spin_lock is used to ensure that MFP register configuration | ||
| 87 | * (most likely a read-modify-write operation) is atomic, and that | ||
| 88 | * mfp_table[] is consistent | ||
| 89 | */ | ||
| 90 | static DEFINE_SPINLOCK(mfp_spin_lock); | ||
| 91 | |||
| 92 | static void __iomem *mfpr_mmio_base; | ||
| 93 | |||
| 94 | struct mfp_pin { | ||
| 95 | unsigned long config; /* -1 for not configured */ | ||
| 96 | unsigned long mfpr_off; /* MFPRxx Register offset */ | ||
| 97 | unsigned long mfpr_run; /* Run-Mode Register Value */ | ||
| 98 | unsigned long mfpr_lpm; /* Low Power Mode Register Value */ | ||
| 99 | }; | ||
| 100 | |||
| 101 | static struct mfp_pin mfp_table[MFP_PIN_MAX]; | ||
| 102 | |||
| 103 | /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ | ||
| 104 | static const unsigned long mfpr_lpm[] = { | ||
| 105 | MFPR_LPM_INPUT, | ||
| 106 | MFPR_LPM_DRIVE_LOW, | ||
| 107 | MFPR_LPM_DRIVE_HIGH, | ||
| 108 | MFPR_LPM_PULL_LOW, | ||
| 109 | MFPR_LPM_PULL_HIGH, | ||
| 110 | MFPR_LPM_FLOAT, | ||
| 111 | }; | ||
| 112 | |||
| 113 | /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ | ||
| 114 | static const unsigned long mfpr_pull[] = { | ||
| 115 | MFPR_PULL_NONE, | ||
| 116 | MFPR_PULL_LOW, | ||
| 117 | MFPR_PULL_HIGH, | ||
| 118 | MFPR_PULL_BOTH, | ||
| 119 | }; | ||
| 120 | |||
| 121 | /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ | ||
| 122 | static const unsigned long mfpr_edge[] = { | ||
| 123 | MFPR_EDGE_NONE, | ||
| 124 | MFPR_EDGE_RISE, | ||
| 125 | MFPR_EDGE_FALL, | ||
| 126 | MFPR_EDGE_BOTH, | ||
| 127 | }; | ||
| 128 | |||
| 129 | #define mfpr_readl(off) \ | ||
| 130 | __raw_readl(mfpr_mmio_base + (off)) | ||
| 131 | |||
| 132 | #define mfpr_writel(off, val) \ | ||
| 133 | __raw_writel(val, mfpr_mmio_base + (off)) | ||
| 134 | |||
| 135 | #define mfp_configured(p) ((p)->config != -1) | ||
| 136 | |||
| 137 | /* | ||
| 138 | * perform a read-back of any MFPR register to make sure the | ||
| 139 | * previous writings are finished | ||
| 140 | */ | ||
| 141 | #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) | ||
| 142 | |||
| 143 | static inline void __mfp_config_run(struct mfp_pin *p) | ||
| 144 | { | ||
| 145 | if (mfp_configured(p)) | ||
| 146 | mfpr_writel(p->mfpr_off, p->mfpr_run); | ||
| 147 | } | ||
| 148 | |||
| 149 | static inline void __mfp_config_lpm(struct mfp_pin *p) | ||
| 150 | { | ||
| 151 | if (mfp_configured(p)) { | ||
| 152 | unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR; | ||
| 153 | if (mfpr_clr != p->mfpr_run) | ||
| 154 | mfpr_writel(p->mfpr_off, mfpr_clr); | ||
| 155 | if (p->mfpr_lpm != mfpr_clr) | ||
| 156 | mfpr_writel(p->mfpr_off, p->mfpr_lpm); | ||
| 157 | } | ||
| 158 | } | ||
| 159 | |||
| 160 | void mfp_config(unsigned long *mfp_cfgs, int num) | ||
| 161 | { | ||
| 162 | unsigned long flags; | ||
| 163 | int i; | ||
| 164 | |||
| 165 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 166 | |||
| 167 | for (i = 0; i < num; i++, mfp_cfgs++) { | ||
| 168 | unsigned long tmp, c = *mfp_cfgs; | ||
| 169 | struct mfp_pin *p; | ||
| 170 | int pin, af, drv, lpm, edge, pull; | ||
| 171 | |||
| 172 | pin = MFP_PIN(c); | ||
| 173 | BUG_ON(pin >= MFP_PIN_MAX); | ||
| 174 | p = &mfp_table[pin]; | ||
| 175 | |||
| 176 | af = MFP_AF(c); | ||
| 177 | drv = MFP_DS(c); | ||
| 178 | lpm = MFP_LPM_STATE(c); | ||
| 179 | edge = MFP_LPM_EDGE(c); | ||
| 180 | pull = MFP_PULL(c); | ||
| 181 | |||
| 182 | /* run-mode pull settings will conflict with MFPR bits of | ||
| 183 | * low power mode state, calculate mfpr_run and mfpr_lpm | ||
| 184 | * individually if pull != MFP_PULL_NONE | ||
| 185 | */ | ||
| 186 | tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); | ||
| 187 | |||
| 188 | if (likely(pull == MFP_PULL_NONE)) { | ||
| 189 | p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 190 | p->mfpr_lpm = p->mfpr_run; | ||
| 191 | } else { | ||
| 192 | p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 193 | p->mfpr_run = tmp | mfpr_pull[pull]; | ||
| 194 | } | ||
| 195 | |||
| 196 | p->config = c; __mfp_config_run(p); | ||
| 197 | } | ||
| 198 | |||
| 199 | mfpr_sync(); | ||
| 200 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 201 | } | ||
| 202 | |||
| 203 | unsigned long mfp_read(int mfp) | ||
| 204 | { | ||
| 205 | unsigned long val, flags; | ||
| 206 | |||
| 207 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 208 | |||
| 209 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 210 | val = mfpr_readl(mfp_table[mfp].mfpr_off); | ||
| 211 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 212 | |||
| 213 | return val; | ||
| 214 | } | ||
| 215 | |||
| 216 | void mfp_write(int mfp, unsigned long val) | ||
| 217 | { | ||
| 218 | unsigned long flags; | ||
| 219 | |||
| 220 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 221 | |||
| 222 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 223 | mfpr_writel(mfp_table[mfp].mfpr_off, val); | ||
| 224 | mfpr_sync(); | ||
| 225 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 226 | } | ||
| 227 | |||
| 228 | void __init mfp_init_base(unsigned long mfpr_base) | ||
| 229 | { | ||
| 230 | int i; | ||
| 231 | |||
| 232 | /* initialize the table with default - unconfigured */ | ||
| 233 | for (i = 0; i < ARRAY_SIZE(mfp_table); i++) | ||
| 234 | mfp_table[i].config = -1; | ||
| 235 | |||
| 236 | mfpr_mmio_base = (void __iomem *)mfpr_base; | ||
| 237 | } | ||
| 238 | |||
| 239 | void __init mfp_init_addr(struct mfp_addr_map *map) | ||
| 240 | { | ||
| 241 | struct mfp_addr_map *p; | ||
| 242 | unsigned long offset, flags; | ||
| 243 | int i; | ||
| 244 | |||
| 245 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 246 | |||
| 247 | for (p = map; p->start != MFP_PIN_INVALID; p++) { | ||
| 248 | offset = p->offset; | ||
| 249 | i = p->start; | ||
| 250 | |||
| 251 | do { | ||
| 252 | mfp_table[i].mfpr_off = offset; | ||
| 253 | mfp_table[i].mfpr_run = 0; | ||
| 254 | mfp_table[i].mfpr_lpm = 0; | ||
| 255 | offset += 4; i++; | ||
| 256 | } while ((i <= p->end) && (p->end != -1)); | ||
| 257 | } | ||
| 258 | |||
| 259 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 260 | } | ||
| 261 | |||
| 262 | void mfp_config_lpm(void) | ||
| 263 | { | ||
| 264 | struct mfp_pin *p = &mfp_table[0]; | ||
| 265 | int pin; | ||
| 266 | |||
| 267 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) | ||
| 268 | __mfp_config_lpm(p); | ||
| 269 | } | ||
| 270 | |||
| 271 | void mfp_config_run(void) | ||
| 272 | { | ||
| 273 | struct mfp_pin *p = &mfp_table[0]; | ||
| 274 | int pin; | ||
| 275 | |||
| 276 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) | ||
| 277 | __mfp_config_run(p); | ||
| 278 | } | ||
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 39195f972d5e..8d7815d25a51 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile | |||
| @@ -18,6 +18,11 @@ obj-y += pwm-clock.o | |||
| 18 | obj-y += gpio.o | 18 | obj-y += gpio.o |
| 19 | obj-y += gpio-config.o | 19 | obj-y += gpio-config.o |
| 20 | 20 | ||
| 21 | # PM support | ||
| 22 | |||
| 23 | obj-$(CONFIG_PM) += pm.o | ||
| 24 | obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o | ||
| 25 | |||
| 21 | # devices | 26 | # devices |
| 22 | 27 | ||
| 23 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | 28 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o |
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h new file mode 100644 index 000000000000..3779775133a9 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/pm.h | |||
| @@ -0,0 +1,174 @@ | |||
| 1 | /* linux/include/asm-arm/plat-s3c24xx/pm.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Written by Ben Dooks, <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* s3c_pm_init | ||
| 13 | * | ||
| 14 | * called from board at initialisation time to setup the power | ||
| 15 | * management | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifdef CONFIG_PM | ||
| 19 | |||
| 20 | extern __init int s3c_pm_init(void); | ||
| 21 | |||
| 22 | #else | ||
| 23 | |||
| 24 | static inline int s3c_pm_init(void) | ||
| 25 | { | ||
| 26 | return 0; | ||
| 27 | } | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* configuration for the IRQ mask over sleep */ | ||
| 31 | extern unsigned long s3c_irqwake_intmask; | ||
| 32 | extern unsigned long s3c_irqwake_eintmask; | ||
| 33 | |||
| 34 | /* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ | ||
| 35 | extern unsigned long s3c_irqwake_intallow; | ||
| 36 | extern unsigned long s3c_irqwake_eintallow; | ||
| 37 | |||
| 38 | /* per-cpu sleep functions */ | ||
| 39 | |||
| 40 | extern void (*pm_cpu_prep)(void); | ||
| 41 | extern void (*pm_cpu_sleep)(void); | ||
| 42 | |||
| 43 | /* Flags for PM Control */ | ||
| 44 | |||
| 45 | extern unsigned long s3c_pm_flags; | ||
| 46 | |||
| 47 | /* from sleep.S */ | ||
| 48 | |||
| 49 | extern int s3c_cpu_save(unsigned long *saveblk); | ||
| 50 | extern void s3c_cpu_resume(void); | ||
| 51 | |||
| 52 | extern void s3c2410_cpu_suspend(void); | ||
| 53 | |||
| 54 | extern unsigned long s3c_sleep_save_phys; | ||
| 55 | |||
| 56 | /* sleep save info */ | ||
| 57 | |||
| 58 | /** | ||
| 59 | * struct sleep_save - save information for shared peripherals. | ||
| 60 | * @reg: Pointer to the register to save. | ||
| 61 | * @val: Holder for the value saved from reg. | ||
| 62 | * | ||
| 63 | * This describes a list of registers which is used by the pm core and | ||
| 64 | * other subsystem to save and restore register values over suspend. | ||
| 65 | */ | ||
| 66 | struct sleep_save { | ||
| 67 | void __iomem *reg; | ||
| 68 | unsigned long val; | ||
| 69 | }; | ||
| 70 | |||
| 71 | #define SAVE_ITEM(x) \ | ||
| 72 | { .reg = (x) } | ||
| 73 | |||
| 74 | /** | ||
| 75 | * struct pm_uart_save - save block for core UART | ||
| 76 | * @ulcon: Save value for S3C2410_ULCON | ||
| 77 | * @ucon: Save value for S3C2410_UCON | ||
| 78 | * @ufcon: Save value for S3C2410_UFCON | ||
| 79 | * @umcon: Save value for S3C2410_UMCON | ||
| 80 | * @ubrdiv: Save value for S3C2410_UBRDIV | ||
| 81 | * | ||
| 82 | * Save block for UART registers to be held over sleep and restored if they | ||
| 83 | * are needed (say by debug). | ||
| 84 | */ | ||
| 85 | struct pm_uart_save { | ||
| 86 | u32 ulcon; | ||
| 87 | u32 ucon; | ||
| 88 | u32 ufcon; | ||
| 89 | u32 umcon; | ||
| 90 | u32 ubrdiv; | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* helper functions to save/restore lists of registers. */ | ||
| 94 | |||
| 95 | extern void s3c_pm_do_save(struct sleep_save *ptr, int count); | ||
| 96 | extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); | ||
| 97 | extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); | ||
| 98 | |||
| 99 | #ifdef CONFIG_PM | ||
| 100 | extern int s3c_irqext_wake(unsigned int irqno, unsigned int state); | ||
| 101 | extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); | ||
| 102 | extern int s3c24xx_irq_resume(struct sys_device *dev); | ||
| 103 | #else | ||
| 104 | #define s3c_irqext_wake NULL | ||
| 105 | #define s3c24xx_irq_suspend NULL | ||
| 106 | #define s3c24xx_irq_resume NULL | ||
| 107 | #endif | ||
| 108 | |||
| 109 | /* PM debug functions */ | ||
| 110 | |||
| 111 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 112 | /** | ||
| 113 | * s3c_pm_dbg() - low level debug function for use in suspend/resume. | ||
| 114 | * @msg: The message to print. | ||
| 115 | * | ||
| 116 | * This function is used mainly to debug the resume process before the system | ||
| 117 | * can rely on printk/console output. It uses the low-level debugging output | ||
| 118 | * routine printascii() to do its work. | ||
| 119 | */ | ||
| 120 | extern void s3c_pm_dbg(const char *msg, ...); | ||
| 121 | |||
| 122 | #define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) | ||
| 123 | #else | ||
| 124 | #define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) | ||
| 125 | #endif | ||
| 126 | |||
| 127 | /* suspend memory checking */ | ||
| 128 | |||
| 129 | #ifdef CONFIG_S3C2410_PM_CHECK | ||
| 130 | extern void s3c_pm_check_prepare(void); | ||
| 131 | extern void s3c_pm_check_restore(void); | ||
| 132 | extern void s3c_pm_check_cleanup(void); | ||
| 133 | extern void s3c_pm_check_store(void); | ||
| 134 | #else | ||
| 135 | #define s3c_pm_check_prepare() do { } while(0) | ||
| 136 | #define s3c_pm_check_restore() do { } while(0) | ||
| 137 | #define s3c_pm_check_cleanup() do { } while(0) | ||
| 138 | #define s3c_pm_check_store() do { } while(0) | ||
| 139 | #endif | ||
| 140 | |||
| 141 | /** | ||
| 142 | * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ | ||
| 143 | * | ||
| 144 | * Setup all the necessary GPIO pins for waking the system on external | ||
| 145 | * interrupt. | ||
| 146 | */ | ||
| 147 | extern void s3c_pm_configure_extint(void); | ||
| 148 | |||
| 149 | /** | ||
| 150 | * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. | ||
| 151 | * | ||
| 152 | * Restore the state of the GPIO pins after sleep, which may involve ensuring | ||
| 153 | * that we do not glitch the state of the pins from that the bootloader's | ||
| 154 | * resume code has done. | ||
| 155 | */ | ||
| 156 | extern void s3c_pm_restore_gpios(void); | ||
| 157 | |||
| 158 | /** | ||
| 159 | * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. | ||
| 160 | * | ||
| 161 | * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios(). | ||
| 162 | */ | ||
| 163 | extern void s3c_pm_save_gpios(void); | ||
| 164 | |||
| 165 | /** | ||
| 166 | * s3c_pm_cb_flushcache - callback for assembly code | ||
| 167 | * | ||
| 168 | * Callback to issue flush_cache_all() as this call is | ||
| 169 | * not a directly callable object. | ||
| 170 | */ | ||
| 171 | extern void s3c_pm_cb_flushcache(void); | ||
| 172 | |||
| 173 | extern void s3c_pm_save_core(void); | ||
| 174 | extern void s3c_pm_restore_core(void); | ||
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h index 6061de87f225..dc66a477f62e 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-s3c/include/plat/uncompress.h | |||
| @@ -90,7 +90,10 @@ static inline void flush(void) | |||
| 90 | { | 90 | { |
| 91 | } | 91 | } |
| 92 | 92 | ||
| 93 | #define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) | 93 | #define __raw_writel(d, ad) \ |
| 94 | do { \ | ||
| 95 | *((volatile unsigned int __force *)(ad)) = (d); \ | ||
| 96 | } while (0) | ||
| 94 | 97 | ||
| 95 | /* CONFIG_S3C_BOOT_WATCHDOG | 98 | /* CONFIG_S3C_BOOT_WATCHDOG |
| 96 | * | 99 | * |
diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-s3c/pm-check.c new file mode 100644 index 000000000000..39f2555564da --- /dev/null +++ b/arch/arm/plat-s3c/pm-check.c | |||
| @@ -0,0 +1,242 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/pm-check.c | ||
| 2 | * originally in linux/arch/arm/plat-s3c24xx/pm.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2004,2006,2008 Simtec Electronics | ||
| 5 | * http://armlinux.simtec.co.uk | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * S3C Power Mangament - suspend/resume memory corruptiuon check. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/suspend.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/crc32.h> | ||
| 19 | #include <linux/ioport.h> | ||
| 20 | |||
| 21 | #include <plat/pm.h> | ||
| 22 | |||
| 23 | #if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1 | ||
| 24 | #error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value | ||
| 25 | #endif | ||
| 26 | |||
| 27 | /* suspend checking code... | ||
| 28 | * | ||
| 29 | * this next area does a set of crc checks over all the installed | ||
| 30 | * memory, so the system can verify if the resume was ok. | ||
| 31 | * | ||
| 32 | * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, | ||
| 33 | * increasing it will mean that the area corrupted will be less easy to spot, | ||
| 34 | * and reducing the size will cause the CRC save area to grow | ||
| 35 | */ | ||
| 36 | |||
| 37 | #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) | ||
| 38 | |||
| 39 | static u32 crc_size; /* size needed for the crc block */ | ||
| 40 | static u32 *crcs; /* allocated over suspend/resume */ | ||
| 41 | |||
| 42 | typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); | ||
| 43 | |||
| 44 | /* s3c_pm_run_res | ||
| 45 | * | ||
| 46 | * go through the given resource list, and look for system ram | ||
| 47 | */ | ||
| 48 | |||
| 49 | static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) | ||
| 50 | { | ||
| 51 | while (ptr != NULL) { | ||
| 52 | if (ptr->child != NULL) | ||
| 53 | s3c_pm_run_res(ptr->child, fn, arg); | ||
| 54 | |||
| 55 | if ((ptr->flags & IORESOURCE_MEM) && | ||
| 56 | strcmp(ptr->name, "System RAM") == 0) { | ||
| 57 | S3C_PMDBG("Found system RAM at %08lx..%08lx\n", | ||
| 58 | (unsigned long)ptr->start, | ||
| 59 | (unsigned long)ptr->end); | ||
| 60 | arg = (fn)(ptr, arg); | ||
| 61 | } | ||
| 62 | |||
| 63 | ptr = ptr->sibling; | ||
| 64 | } | ||
| 65 | } | ||
| 66 | |||
| 67 | static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg) | ||
| 68 | { | ||
| 69 | s3c_pm_run_res(&iomem_resource, fn, arg); | ||
| 70 | } | ||
| 71 | |||
| 72 | static u32 *s3c_pm_countram(struct resource *res, u32 *val) | ||
| 73 | { | ||
| 74 | u32 size = (u32)(res->end - res->start)+1; | ||
| 75 | |||
| 76 | size += CHECK_CHUNKSIZE-1; | ||
| 77 | size /= CHECK_CHUNKSIZE; | ||
| 78 | |||
| 79 | S3C_PMDBG("Area %08lx..%08lx, %d blocks\n", | ||
| 80 | (unsigned long)res->start, (unsigned long)res->end, size); | ||
| 81 | |||
| 82 | *val += size * sizeof(u32); | ||
| 83 | return val; | ||
| 84 | } | ||
| 85 | |||
| 86 | /* s3c_pm_prepare_check | ||
| 87 | * | ||
| 88 | * prepare the necessary information for creating the CRCs. This | ||
| 89 | * must be done before the final save, as it will require memory | ||
| 90 | * allocating, and thus touching bits of the kernel we do not | ||
| 91 | * know about. | ||
| 92 | */ | ||
| 93 | |||
| 94 | void s3c_pm_check_prepare(void) | ||
| 95 | { | ||
| 96 | crc_size = 0; | ||
| 97 | |||
| 98 | s3c_pm_run_sysram(s3c_pm_countram, &crc_size); | ||
| 99 | |||
| 100 | S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size); | ||
| 101 | |||
| 102 | crcs = kmalloc(crc_size+4, GFP_KERNEL); | ||
| 103 | if (crcs == NULL) | ||
| 104 | printk(KERN_ERR "Cannot allocated CRC save area\n"); | ||
| 105 | } | ||
| 106 | |||
| 107 | static u32 *s3c_pm_makecheck(struct resource *res, u32 *val) | ||
| 108 | { | ||
| 109 | unsigned long addr, left; | ||
| 110 | |||
| 111 | for (addr = res->start; addr < res->end; | ||
| 112 | addr += CHECK_CHUNKSIZE) { | ||
| 113 | left = res->end - addr; | ||
| 114 | |||
| 115 | if (left > CHECK_CHUNKSIZE) | ||
| 116 | left = CHECK_CHUNKSIZE; | ||
| 117 | |||
| 118 | *val = crc32_le(~0, phys_to_virt(addr), left); | ||
| 119 | val++; | ||
| 120 | } | ||
| 121 | |||
| 122 | return val; | ||
| 123 | } | ||
| 124 | |||
| 125 | /* s3c_pm_check_store | ||
| 126 | * | ||
| 127 | * compute the CRC values for the memory blocks before the final | ||
| 128 | * sleep. | ||
| 129 | */ | ||
| 130 | |||
| 131 | void s3c_pm_check_store(void) | ||
| 132 | { | ||
| 133 | if (crcs != NULL) | ||
| 134 | s3c_pm_run_sysram(s3c_pm_makecheck, crcs); | ||
| 135 | } | ||
| 136 | |||
| 137 | /* in_region | ||
| 138 | * | ||
| 139 | * return TRUE if the area defined by ptr..ptr+size contains the | ||
| 140 | * what..what+whatsz | ||
| 141 | */ | ||
| 142 | |||
| 143 | static inline int in_region(void *ptr, int size, void *what, size_t whatsz) | ||
| 144 | { | ||
| 145 | if ((what+whatsz) < ptr) | ||
| 146 | return 0; | ||
| 147 | |||
| 148 | if (what > (ptr+size)) | ||
| 149 | return 0; | ||
| 150 | |||
| 151 | return 1; | ||
| 152 | } | ||
| 153 | |||
| 154 | /** | ||
| 155 | * s3c_pm_runcheck() - helper to check a resource on restore. | ||
| 156 | * @res: The resource to check | ||
| 157 | * @vak: Pointer to list of CRC32 values to check. | ||
| 158 | * | ||
| 159 | * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this | ||
| 160 | * function runs the given memory resource checking it against the stored | ||
| 161 | * CRC to ensure that memory is restored. The function tries to skip as | ||
| 162 | * many of the areas used during the suspend process. | ||
| 163 | */ | ||
| 164 | static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) | ||
| 165 | { | ||
| 166 | void *save_at = phys_to_virt(s3c_sleep_save_phys); | ||
| 167 | unsigned long addr; | ||
| 168 | unsigned long left; | ||
| 169 | void *stkpage; | ||
| 170 | void *ptr; | ||
| 171 | u32 calc; | ||
| 172 | |||
| 173 | stkpage = (void *)((u32)&calc & ~PAGE_MASK); | ||
| 174 | |||
| 175 | for (addr = res->start; addr < res->end; | ||
| 176 | addr += CHECK_CHUNKSIZE) { | ||
| 177 | left = res->end - addr; | ||
| 178 | |||
| 179 | if (left > CHECK_CHUNKSIZE) | ||
| 180 | left = CHECK_CHUNKSIZE; | ||
| 181 | |||
| 182 | ptr = phys_to_virt(addr); | ||
| 183 | |||
| 184 | if (in_region(ptr, left, stkpage, 4096)) { | ||
| 185 | S3C_PMDBG("skipping %08lx, has stack in\n", addr); | ||
| 186 | goto skip_check; | ||
| 187 | } | ||
| 188 | |||
| 189 | if (in_region(ptr, left, crcs, crc_size)) { | ||
| 190 | S3C_PMDBG("skipping %08lx, has crc block in\n", addr); | ||
| 191 | goto skip_check; | ||
| 192 | } | ||
| 193 | |||
| 194 | if (in_region(ptr, left, save_at, 32*4 )) { | ||
| 195 | S3C_PMDBG("skipping %08lx, has save block in\n", addr); | ||
| 196 | goto skip_check; | ||
| 197 | } | ||
| 198 | |||
| 199 | /* calculate and check the checksum */ | ||
| 200 | |||
| 201 | calc = crc32_le(~0, ptr, left); | ||
| 202 | if (calc != *val) { | ||
| 203 | printk(KERN_ERR "Restore CRC error at " | ||
| 204 | "%08lx (%08x vs %08x)\n", addr, calc, *val); | ||
| 205 | |||
| 206 | S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n", | ||
| 207 | addr, calc, *val); | ||
| 208 | } | ||
| 209 | |||
| 210 | skip_check: | ||
| 211 | val++; | ||
| 212 | } | ||
| 213 | |||
| 214 | return val; | ||
| 215 | } | ||
| 216 | |||
| 217 | /** | ||
| 218 | * s3c_pm_check_restore() - memory check called on resume | ||
| 219 | * | ||
| 220 | * check the CRCs after the restore event and free the memory used | ||
| 221 | * to hold them | ||
| 222 | */ | ||
| 223 | void s3c_pm_check_restore(void) | ||
| 224 | { | ||
| 225 | if (crcs != NULL) | ||
| 226 | s3c_pm_run_sysram(s3c_pm_runcheck, crcs); | ||
| 227 | } | ||
| 228 | |||
| 229 | /** | ||
| 230 | * s3c_pm_check_cleanup() - free memory resources | ||
| 231 | * | ||
| 232 | * Free the resources that where allocated by the suspend | ||
| 233 | * memory check code. We do this separately from the | ||
| 234 | * s3c_pm_check_restore() function as we cannot call any | ||
| 235 | * functions that might sleep during that resume. | ||
| 236 | */ | ||
| 237 | void s3c_pm_check_cleanup(void) | ||
| 238 | { | ||
| 239 | kfree(crcs); | ||
| 240 | crcs = NULL; | ||
| 241 | } | ||
| 242 | |||
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c new file mode 100644 index 000000000000..061182ca66e3 --- /dev/null +++ b/arch/arm/plat-s3c/pm.c | |||
| @@ -0,0 +1,363 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/pm.c | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2004,2006,2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * S3C common power management (suspend to ram) support. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/suspend.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/serial_core.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <asm/cacheflush.h> | ||
| 23 | #include <mach/hardware.h> | ||
| 24 | |||
| 25 | #include <plat/regs-serial.h> | ||
| 26 | #include <mach/regs-clock.h> | ||
| 27 | #include <mach/regs-gpio.h> | ||
| 28 | #include <mach/regs-mem.h> | ||
| 29 | #include <mach/regs-irq.h> | ||
| 30 | #include <asm/irq.h> | ||
| 31 | |||
| 32 | #include <plat/pm.h> | ||
| 33 | #include <plat/pm-core.h> | ||
| 34 | |||
| 35 | /* for external use */ | ||
| 36 | |||
| 37 | unsigned long s3c_pm_flags; | ||
| 38 | |||
| 39 | /* Debug code: | ||
| 40 | * | ||
| 41 | * This code supports debug output to the low level UARTs for use on | ||
| 42 | * resume before the console layer is available. | ||
| 43 | */ | ||
| 44 | |||
| 45 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 46 | extern void printascii(const char *); | ||
| 47 | |||
| 48 | void s3c_pm_dbg(const char *fmt, ...) | ||
| 49 | { | ||
| 50 | va_list va; | ||
| 51 | char buff[256]; | ||
| 52 | |||
| 53 | va_start(va, fmt); | ||
| 54 | vsprintf(buff, fmt, va); | ||
| 55 | va_end(va); | ||
| 56 | |||
| 57 | printascii(buff); | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline void s3c_pm_debug_init(void) | ||
| 61 | { | ||
| 62 | /* restart uart clocks so we can use them to output */ | ||
| 63 | s3c_pm_debug_init_uart(); | ||
| 64 | } | ||
| 65 | |||
| 66 | #else | ||
| 67 | #define s3c_pm_debug_init() do { } while(0) | ||
| 68 | |||
| 69 | #endif /* CONFIG_S3C2410_PM_DEBUG */ | ||
| 70 | |||
| 71 | /* Save the UART configurations if we are configured for debug. */ | ||
| 72 | |||
| 73 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 74 | |||
| 75 | struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; | ||
| 76 | |||
| 77 | static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) | ||
| 78 | { | ||
| 79 | void __iomem *regs = S3C_VA_UARTx(uart); | ||
| 80 | |||
| 81 | save->ulcon = __raw_readl(regs + S3C2410_ULCON); | ||
| 82 | save->ucon = __raw_readl(regs + S3C2410_UCON); | ||
| 83 | save->ufcon = __raw_readl(regs + S3C2410_UFCON); | ||
| 84 | save->umcon = __raw_readl(regs + S3C2410_UMCON); | ||
| 85 | save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); | ||
| 86 | } | ||
| 87 | |||
| 88 | static void s3c_pm_save_uarts(void) | ||
| 89 | { | ||
| 90 | struct pm_uart_save *save = uart_save; | ||
| 91 | unsigned int uart; | ||
| 92 | |||
| 93 | for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) | ||
| 94 | s3c_pm_save_uart(uart, save); | ||
| 95 | } | ||
| 96 | |||
| 97 | static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) | ||
| 98 | { | ||
| 99 | void __iomem *regs = S3C_VA_UARTx(uart); | ||
| 100 | |||
| 101 | __raw_writel(save->ulcon, regs + S3C2410_ULCON); | ||
| 102 | __raw_writel(save->ucon, regs + S3C2410_UCON); | ||
| 103 | __raw_writel(save->ufcon, regs + S3C2410_UFCON); | ||
| 104 | __raw_writel(save->umcon, regs + S3C2410_UMCON); | ||
| 105 | __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); | ||
| 106 | } | ||
| 107 | |||
| 108 | static void s3c_pm_restore_uarts(void) | ||
| 109 | { | ||
| 110 | struct pm_uart_save *save = uart_save; | ||
| 111 | unsigned int uart; | ||
| 112 | |||
| 113 | for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) | ||
| 114 | s3c_pm_restore_uart(uart, save); | ||
| 115 | } | ||
| 116 | #else | ||
| 117 | static void s3c_pm_save_uarts(void) { } | ||
| 118 | static void s3c_pm_restore_uarts(void) { } | ||
| 119 | #endif | ||
| 120 | |||
| 121 | /* The IRQ ext-int code goes here, it is too small to currently bother | ||
| 122 | * with its own file. */ | ||
| 123 | |||
| 124 | unsigned long s3c_irqwake_intmask = 0xffffffffL; | ||
| 125 | unsigned long s3c_irqwake_eintmask = 0xffffffffL; | ||
| 126 | |||
| 127 | int s3c_irqext_wake(unsigned int irqno, unsigned int state) | ||
| 128 | { | ||
| 129 | unsigned long bit = 1L << IRQ_EINT_BIT(irqno); | ||
| 130 | |||
| 131 | if (!(s3c_irqwake_eintallow & bit)) | ||
| 132 | return -ENOENT; | ||
| 133 | |||
| 134 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 135 | state ? "enabled" : "disabled", irqno); | ||
| 136 | |||
| 137 | if (!state) | ||
| 138 | s3c_irqwake_eintmask |= bit; | ||
| 139 | else | ||
| 140 | s3c_irqwake_eintmask &= ~bit; | ||
| 141 | |||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | /* helper functions to save and restore register state */ | ||
| 146 | |||
| 147 | /** | ||
| 148 | * s3c_pm_do_save() - save a set of registers for restoration on resume. | ||
| 149 | * @ptr: Pointer to an array of registers. | ||
| 150 | * @count: Size of the ptr array. | ||
| 151 | * | ||
| 152 | * Run through the list of registers given, saving their contents in the | ||
| 153 | * array for later restoration when we wakeup. | ||
| 154 | */ | ||
| 155 | void s3c_pm_do_save(struct sleep_save *ptr, int count) | ||
| 156 | { | ||
| 157 | for (; count > 0; count--, ptr++) { | ||
| 158 | ptr->val = __raw_readl(ptr->reg); | ||
| 159 | S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); | ||
| 160 | } | ||
| 161 | } | ||
| 162 | |||
| 163 | /** | ||
| 164 | * s3c_pm_do_restore() - restore register values from the save list. | ||
| 165 | * @ptr: Pointer to an array of registers. | ||
| 166 | * @count: Size of the ptr array. | ||
| 167 | * | ||
| 168 | * Restore the register values saved from s3c_pm_do_save(). | ||
| 169 | * | ||
| 170 | * Note, we do not use S3C_PMDBG() in here, as the system may not have | ||
| 171 | * restore the UARTs state yet | ||
| 172 | */ | ||
| 173 | |||
| 174 | void s3c_pm_do_restore(struct sleep_save *ptr, int count) | ||
| 175 | { | ||
| 176 | for (; count > 0; count--, ptr++) { | ||
| 177 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | ||
| 178 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | ||
| 179 | |||
| 180 | __raw_writel(ptr->val, ptr->reg); | ||
| 181 | } | ||
| 182 | } | ||
| 183 | |||
| 184 | /** | ||
| 185 | * s3c_pm_do_restore_core() - early restore register values from save list. | ||
| 186 | * | ||
| 187 | * This is similar to s3c_pm_do_restore() except we try and minimise the | ||
| 188 | * side effects of the function in case registers that hardware might need | ||
| 189 | * to work has been restored. | ||
| 190 | * | ||
| 191 | * WARNING: Do not put any debug in here that may effect memory or use | ||
| 192 | * peripherals, as things may be changing! | ||
| 193 | */ | ||
| 194 | |||
| 195 | void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) | ||
| 196 | { | ||
| 197 | for (; count > 0; count--, ptr++) | ||
| 198 | __raw_writel(ptr->val, ptr->reg); | ||
| 199 | } | ||
| 200 | |||
| 201 | /* s3c2410_pm_show_resume_irqs | ||
| 202 | * | ||
| 203 | * print any IRQs asserted at resume time (ie, we woke from) | ||
| 204 | */ | ||
| 205 | static void s3c_pm_show_resume_irqs(int start, unsigned long which, | ||
| 206 | unsigned long mask) | ||
| 207 | { | ||
| 208 | int i; | ||
| 209 | |||
| 210 | which &= ~mask; | ||
| 211 | |||
| 212 | for (i = 0; i <= 31; i++) { | ||
| 213 | if (which & (1L<<i)) { | ||
| 214 | S3C_PMDBG("IRQ %d asserted at resume\n", start+i); | ||
| 215 | } | ||
| 216 | } | ||
| 217 | } | ||
| 218 | |||
| 219 | |||
| 220 | void (*pm_cpu_prep)(void); | ||
| 221 | void (*pm_cpu_sleep)(void); | ||
| 222 | |||
| 223 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | ||
| 224 | |||
| 225 | /* s3c_pm_enter | ||
| 226 | * | ||
| 227 | * central control for sleep/resume process | ||
| 228 | */ | ||
| 229 | |||
| 230 | static int s3c_pm_enter(suspend_state_t state) | ||
| 231 | { | ||
| 232 | static unsigned long regs_save[16]; | ||
| 233 | |||
| 234 | /* ensure the debug is initialised (if enabled) */ | ||
| 235 | |||
| 236 | s3c_pm_debug_init(); | ||
| 237 | |||
| 238 | S3C_PMDBG("%s(%d)\n", __func__, state); | ||
| 239 | |||
| 240 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | ||
| 241 | printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__); | ||
| 242 | return -EINVAL; | ||
| 243 | } | ||
| 244 | |||
| 245 | /* check if we have anything to wake-up with... bad things seem | ||
| 246 | * to happen if you suspend with no wakeup (system will often | ||
| 247 | * require a full power-cycle) | ||
| 248 | */ | ||
| 249 | |||
| 250 | if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | ||
| 251 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { | ||
| 252 | printk(KERN_ERR "%s: No wake-up sources!\n", __func__); | ||
| 253 | printk(KERN_ERR "%s: Aborting sleep\n", __func__); | ||
| 254 | return -EINVAL; | ||
| 255 | } | ||
| 256 | |||
| 257 | /* store the physical address of the register recovery block */ | ||
| 258 | |||
| 259 | s3c_sleep_save_phys = virt_to_phys(regs_save); | ||
| 260 | |||
| 261 | S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); | ||
| 262 | |||
| 263 | /* save all necessary core registers not covered by the drivers */ | ||
| 264 | |||
| 265 | s3c_pm_save_gpios(); | ||
| 266 | s3c_pm_save_uarts(); | ||
| 267 | s3c_pm_save_core(); | ||
| 268 | |||
| 269 | /* set the irq configuration for wake */ | ||
| 270 | |||
| 271 | s3c_pm_configure_extint(); | ||
| 272 | |||
| 273 | S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n", | ||
| 274 | s3c_irqwake_intmask, s3c_irqwake_eintmask); | ||
| 275 | |||
| 276 | s3c_pm_arch_prepare_irqs(); | ||
| 277 | |||
| 278 | /* call cpu specific preparation */ | ||
| 279 | |||
| 280 | pm_cpu_prep(); | ||
| 281 | |||
| 282 | /* flush cache back to ram */ | ||
| 283 | |||
| 284 | flush_cache_all(); | ||
| 285 | |||
| 286 | s3c_pm_check_store(); | ||
| 287 | |||
| 288 | /* send the cpu to sleep... */ | ||
| 289 | |||
| 290 | s3c_pm_arch_stop_clocks(); | ||
| 291 | |||
| 292 | /* s3c_cpu_save will also act as our return point from when | ||
| 293 | * we resume as it saves its own register state and restores it | ||
| 294 | * during the resume. */ | ||
| 295 | |||
| 296 | s3c_cpu_save(regs_save); | ||
| 297 | |||
| 298 | /* restore the cpu state using the kernel's cpu init code. */ | ||
| 299 | |||
| 300 | cpu_init(); | ||
| 301 | |||
| 302 | /* restore the system state */ | ||
| 303 | |||
| 304 | s3c_pm_restore_core(); | ||
| 305 | s3c_pm_restore_uarts(); | ||
| 306 | s3c_pm_restore_gpios(); | ||
| 307 | |||
| 308 | s3c_pm_debug_init(); | ||
| 309 | |||
| 310 | /* check what irq (if any) restored the system */ | ||
| 311 | |||
| 312 | s3c_pm_arch_show_resume_irqs(); | ||
| 313 | |||
| 314 | S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); | ||
| 315 | |||
| 316 | s3c_pm_check_restore(); | ||
| 317 | |||
| 318 | /* ok, let's return from sleep */ | ||
| 319 | |||
| 320 | S3C_PMDBG("S3C PM Resume (post-restore)\n"); | ||
| 321 | return 0; | ||
| 322 | } | ||
| 323 | |||
| 324 | /* callback from assembly code */ | ||
| 325 | void s3c_pm_cb_flushcache(void) | ||
| 326 | { | ||
| 327 | flush_cache_all(); | ||
| 328 | } | ||
| 329 | |||
| 330 | static int s3c_pm_prepare(void) | ||
| 331 | { | ||
| 332 | /* prepare check area if configured */ | ||
| 333 | |||
| 334 | s3c_pm_check_prepare(); | ||
| 335 | return 0; | ||
| 336 | } | ||
| 337 | |||
| 338 | static void s3c_pm_finish(void) | ||
| 339 | { | ||
| 340 | s3c_pm_check_cleanup(); | ||
| 341 | } | ||
| 342 | |||
| 343 | static struct platform_suspend_ops s3c_pm_ops = { | ||
| 344 | .enter = s3c_pm_enter, | ||
| 345 | .prepare = s3c_pm_prepare, | ||
| 346 | .finish = s3c_pm_finish, | ||
| 347 | .valid = suspend_valid_only_mem, | ||
| 348 | }; | ||
| 349 | |||
| 350 | /* s3c_pm_init | ||
| 351 | * | ||
| 352 | * Attach the power management functions. This should be called | ||
| 353 | * from the board specific initialisation if the board supports | ||
| 354 | * it. | ||
| 355 | */ | ||
| 356 | |||
| 357 | int __init s3c_pm_init(void) | ||
| 358 | { | ||
| 359 | printk("S3C Power Management, Copyright 2004 Simtec Electronics\n"); | ||
| 360 | |||
| 361 | suspend_set_ops(&s3c_pm_ops); | ||
| 362 | return 0; | ||
| 363 | } | ||
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 1e0767b266b8..636cb12711df 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
| @@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o | |||
| 27 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o | 27 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o |
| 28 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o | 28 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o |
| 29 | obj-$(CONFIG_PM) += pm.o | 29 | obj-$(CONFIG_PM) += pm.o |
| 30 | obj-$(CONFIG_PM) += irq-pm.o | ||
| 30 | obj-$(CONFIG_PM) += sleep.o | 31 | obj-$(CONFIG_PM) += sleep.o |
| 31 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 32 | obj-$(CONFIG_HAVE_PWM) += pwm.o |
| 32 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | 33 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o |
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 3d4837021ac7..1a8347cec20a 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c | |||
| @@ -201,5 +201,5 @@ void __init smdk_machine_init(void) | |||
| 201 | 201 | ||
| 202 | platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); | 202 | platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); |
| 203 | 203 | ||
| 204 | s3c2410_pm_init(); | 204 | s3c_pm_init(); |
| 205 | } | 205 | } |
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 542062f8cbc1..1932b7e0da15 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
| @@ -182,7 +182,7 @@ static unsigned long s3c24xx_read_idcode_v4(void) | |||
| 182 | * with the caches enabled. It seems at least the S3C2440 has a problem | 182 | * with the caches enabled. It seems at least the S3C2440 has a problem |
| 183 | * resetting if there is bus activity interrupted by the reset. | 183 | * resetting if there is bus activity interrupted by the reset. |
| 184 | */ | 184 | */ |
| 185 | static void s3c24xx_pm_restart(char mode) | 185 | static void s3c24xx_pm_restart(char mode, const char *cmd) |
| 186 | { | 186 | { |
| 187 | if (mode != 's') { | 187 | if (mode != 's') { |
| 188 | unsigned long flags; | 188 | unsigned long flags; |
| @@ -191,12 +191,12 @@ static void s3c24xx_pm_restart(char mode) | |||
| 191 | __cpuc_flush_kern_all(); | 191 | __cpuc_flush_kern_all(); |
| 192 | __cpuc_flush_user_all(); | 192 | __cpuc_flush_user_all(); |
| 193 | 193 | ||
| 194 | arch_reset(mode); | 194 | arch_reset(mode, cmd); |
| 195 | local_irq_restore(flags); | 195 | local_irq_restore(flags); |
| 196 | } | 196 | } |
| 197 | 197 | ||
| 198 | /* fallback, or unhandled */ | 198 | /* fallback, or unhandled */ |
| 199 | arm_machine_restart(mode); | 199 | arm_machine_restart(mode, cmd); |
| 200 | } | 200 | } |
| 201 | 201 | ||
| 202 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | 202 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) |
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h index 45746a995343..69e1be8bec35 100644 --- a/arch/arm/plat-s3c24xx/include/plat/irq.h +++ b/arch/arm/plat-s3c24xx/include/plat/irq.h | |||
| @@ -10,6 +10,12 @@ | |||
| 10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/io.h> | ||
| 14 | |||
| 15 | #include <mach/hardware.h> | ||
| 16 | #include <mach/regs-irq.h> | ||
| 17 | #include <mach/regs-gpio.h> | ||
| 18 | |||
| 13 | #define irqdbf(x...) | 19 | #define irqdbf(x...) |
| 14 | #define irqdbf2(x...) | 20 | #define irqdbf2(x...) |
| 15 | 21 | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h index fef8ea8b8e1e..eed8f78e7593 100644 --- a/arch/arm/plat-s3c24xx/include/plat/map.h +++ b/arch/arm/plat-s3c24xx/include/plat/map.h | |||
| @@ -31,6 +31,8 @@ | |||
| 31 | #define S3C24XX_SZ_UART SZ_1M | 31 | #define S3C24XX_SZ_UART SZ_1M |
| 32 | #define S3C_UART_OFFSET (0x4000) | 32 | #define S3C_UART_OFFSET (0x4000) |
| 33 | 33 | ||
| 34 | #define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) | ||
| 35 | |||
| 34 | /* Timers */ | 36 | /* Timers */ |
| 35 | #define S3C24XX_VA_TIMER S3C_VA_TIMER | 37 | #define S3C24XX_VA_TIMER S3C_VA_TIMER |
| 36 | #define S3C2410_PA_TIMER (0x51000000) | 38 | #define S3C2410_PA_TIMER (0x51000000) |
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h new file mode 100644 index 000000000000..c75882113e04 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/include/plat/pll.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | static inline void s3c_pm_debug_init_uart(void) | ||
| 15 | { | ||
| 16 | unsigned long tmp = __raw_readl(S3C2410_CLKCON); | ||
| 17 | |||
| 18 | /* re-start uart clocks */ | ||
| 19 | tmp |= S3C2410_CLKCON_UART0; | ||
| 20 | tmp |= S3C2410_CLKCON_UART1; | ||
| 21 | tmp |= S3C2410_CLKCON_UART2; | ||
| 22 | |||
| 23 | __raw_writel(tmp, S3C2410_CLKCON); | ||
| 24 | udelay(10); | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline void s3c_pm_arch_prepare_irqs(void) | ||
| 28 | { | ||
| 29 | __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); | ||
| 30 | __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); | ||
| 31 | |||
| 32 | /* ack any outstanding external interrupts before we go to sleep */ | ||
| 33 | |||
| 34 | __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); | ||
| 35 | __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); | ||
| 36 | __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); | ||
| 37 | |||
| 38 | } | ||
| 39 | |||
| 40 | static inline void s3c_pm_arch_stop_clocks(void) | ||
| 41 | { | ||
| 42 | __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ | ||
| 43 | } | ||
| 44 | |||
| 45 | static void s3c_pm_show_resume_irqs(int start, unsigned long which, | ||
| 46 | unsigned long mask); | ||
| 47 | |||
| 48 | static inline void s3c_pm_arch_show_resume_irqs(void) | ||
| 49 | { | ||
| 50 | S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n", | ||
| 51 | __raw_readl(S3C2410_SRCPND), | ||
| 52 | __raw_readl(S3C2410_EINTPEND)); | ||
| 53 | |||
| 54 | s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), | ||
| 55 | s3c_irqwake_intmask); | ||
| 56 | |||
| 57 | s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), | ||
| 58 | s3c_irqwake_eintmask); | ||
| 59 | } | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm.h b/arch/arm/plat-s3c24xx/include/plat/pm.h deleted file mode 100644 index cc623667e48a..000000000000 --- a/arch/arm/plat-s3c24xx/include/plat/pm.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/plat-s3c24xx/pm.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics | ||
| 4 | * Written by Ben Dooks, <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /* s3c2410_pm_init | ||
| 12 | * | ||
| 13 | * called from board at initialisation time to setup the power | ||
| 14 | * management | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifdef CONFIG_PM | ||
| 18 | |||
| 19 | extern __init int s3c2410_pm_init(void); | ||
| 20 | |||
| 21 | #else | ||
| 22 | |||
| 23 | static inline int s3c2410_pm_init(void) | ||
| 24 | { | ||
| 25 | return 0; | ||
| 26 | } | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /* configuration for the IRQ mask over sleep */ | ||
| 30 | extern unsigned long s3c_irqwake_intmask; | ||
| 31 | extern unsigned long s3c_irqwake_eintmask; | ||
| 32 | |||
| 33 | /* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ | ||
| 34 | extern unsigned long s3c_irqwake_intallow; | ||
| 35 | extern unsigned long s3c_irqwake_eintallow; | ||
| 36 | |||
| 37 | /* per-cpu sleep functions */ | ||
| 38 | |||
| 39 | extern void (*pm_cpu_prep)(void); | ||
| 40 | extern void (*pm_cpu_sleep)(void); | ||
| 41 | |||
| 42 | /* Flags for PM Control */ | ||
| 43 | |||
| 44 | extern unsigned long s3c_pm_flags; | ||
| 45 | |||
| 46 | /* from sleep.S */ | ||
| 47 | |||
| 48 | extern int s3c2410_cpu_save(unsigned long *saveblk); | ||
| 49 | extern void s3c2410_cpu_suspend(void); | ||
| 50 | extern void s3c2410_cpu_resume(void); | ||
| 51 | |||
| 52 | extern unsigned long s3c2410_sleep_save_phys; | ||
| 53 | |||
| 54 | /* sleep save info */ | ||
| 55 | |||
| 56 | struct sleep_save { | ||
| 57 | void __iomem *reg; | ||
| 58 | unsigned long val; | ||
| 59 | }; | ||
| 60 | |||
| 61 | #define SAVE_ITEM(x) \ | ||
| 62 | { .reg = (x) } | ||
| 63 | |||
| 64 | extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count); | ||
| 65 | extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count); | ||
| 66 | |||
| 67 | #ifdef CONFIG_PM | ||
| 68 | extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); | ||
| 69 | extern int s3c24xx_irq_resume(struct sys_device *dev); | ||
| 70 | #else | ||
| 71 | #define s3c24xx_irq_suspend NULL | ||
| 72 | #define s3c24xx_irq_resume NULL | ||
| 73 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c new file mode 100644 index 000000000000..b7acf1a8ecd2 --- /dev/null +++ b/arch/arm/plat-s3c24xx/irq-pm.c | |||
| @@ -0,0 +1,95 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/irq-om.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * S3C24XX - IRQ PM code | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/sysdev.h> | ||
| 18 | |||
| 19 | #include <plat/cpu.h> | ||
| 20 | #include <plat/pm.h> | ||
| 21 | #include <plat/irq.h> | ||
| 22 | |||
| 23 | /* state for IRQs over sleep */ | ||
| 24 | |||
| 25 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | ||
| 26 | * | ||
| 27 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | ||
| 28 | */ | ||
| 29 | |||
| 30 | unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; | ||
| 31 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; | ||
| 32 | |||
| 33 | int s3c_irq_wake(unsigned int irqno, unsigned int state) | ||
| 34 | { | ||
| 35 | unsigned long irqbit = 1 << (irqno - IRQ_EINT0); | ||
| 36 | |||
| 37 | if (!(s3c_irqwake_intallow & irqbit)) | ||
| 38 | return -ENOENT; | ||
| 39 | |||
| 40 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 41 | state ? "enabled" : "disabled", irqno); | ||
| 42 | |||
| 43 | if (!state) | ||
| 44 | s3c_irqwake_intmask |= irqbit; | ||
| 45 | else | ||
| 46 | s3c_irqwake_intmask &= ~irqbit; | ||
| 47 | |||
| 48 | return 0; | ||
| 49 | } | ||
| 50 | |||
| 51 | static struct sleep_save irq_save[] = { | ||
| 52 | SAVE_ITEM(S3C2410_INTMSK), | ||
| 53 | SAVE_ITEM(S3C2410_INTSUBMSK), | ||
| 54 | }; | ||
| 55 | |||
| 56 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | ||
| 57 | * so we use an array to hold them, and to calculate the address of | ||
| 58 | * the register at run-time | ||
| 59 | */ | ||
| 60 | |||
| 61 | static unsigned long save_extint[3]; | ||
| 62 | static unsigned long save_eintflt[4]; | ||
| 63 | static unsigned long save_eintmask; | ||
| 64 | |||
| 65 | int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) | ||
| 66 | { | ||
| 67 | unsigned int i; | ||
| 68 | |||
| 69 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 70 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | ||
| 71 | |||
| 72 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 73 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | ||
| 74 | |||
| 75 | s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | ||
| 76 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | int s3c24xx_irq_resume(struct sys_device *dev) | ||
| 82 | { | ||
| 83 | unsigned int i; | ||
| 84 | |||
| 85 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 86 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | ||
| 87 | |||
| 88 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 89 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | ||
| 90 | |||
| 91 | s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | ||
| 92 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 0192ecdc1442..958737775ad2 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/irq.c | 1 | /* linux/arch/arm/plat-s3c24xx/irq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003,2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| @@ -16,38 +16,6 @@ | |||
| 16 | * You should have received a copy of the GNU General Public License | 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software | 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | * | ||
| 20 | * Changelog: | ||
| 21 | * | ||
| 22 | * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk> | ||
| 23 | * Fixed compile warnings | ||
| 24 | * | ||
| 25 | * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn> | ||
| 26 | * Fixed s3c_extirq_type | ||
| 27 | * | ||
| 28 | * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> | ||
| 29 | * Addition of ADC/TC demux | ||
| 30 | * | ||
| 31 | * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de> | ||
| 32 | * Fix for set_irq_type() on low EINT numbers | ||
| 33 | * | ||
| 34 | * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> | ||
| 35 | * Tidy up KF's patch and sort out new release | ||
| 36 | * | ||
| 37 | * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> | ||
| 38 | * Add support for power management controls | ||
| 39 | * | ||
| 40 | * 04-Nov-2004 Ben Dooks | ||
| 41 | * Fix standard IRQ wake for EINT0..4 and RTC | ||
| 42 | * | ||
| 43 | * 22-Feb-2005 Ben Dooks | ||
| 44 | * Fixed edge-triggering on ADC IRQ | ||
| 45 | * | ||
| 46 | * 28-Jun-2005 Ben Dooks | ||
| 47 | * Mark IRQ_LCD valid | ||
| 48 | * | ||
| 49 | * 25-Jul-2005 Ben Dooks | ||
| 50 | * Split the S3C2440 IRQ code to separate file | ||
| 51 | */ | 19 | */ |
| 52 | 20 | ||
| 53 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| @@ -55,81 +23,16 @@ | |||
| 55 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
| 56 | #include <linux/ioport.h> | 24 | #include <linux/ioport.h> |
| 57 | #include <linux/sysdev.h> | 25 | #include <linux/sysdev.h> |
| 58 | #include <linux/io.h> | ||
| 59 | 26 | ||
| 60 | #include <mach/hardware.h> | ||
| 61 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 62 | |||
| 63 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
| 64 | 29 | ||
| 65 | #include <plat/regs-irqtype.h> | 30 | #include <plat/regs-irqtype.h> |
| 66 | #include <mach/regs-irq.h> | ||
| 67 | #include <mach/regs-gpio.h> | ||
| 68 | 31 | ||
| 69 | #include <plat/cpu.h> | 32 | #include <plat/cpu.h> |
| 70 | #include <plat/pm.h> | 33 | #include <plat/pm.h> |
| 71 | #include <plat/irq.h> | 34 | #include <plat/irq.h> |
| 72 | 35 | ||
| 73 | /* wakeup irq control */ | ||
| 74 | |||
| 75 | #ifdef CONFIG_PM | ||
| 76 | |||
| 77 | /* state for IRQs over sleep */ | ||
| 78 | |||
| 79 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | ||
| 80 | * | ||
| 81 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | ||
| 82 | */ | ||
| 83 | |||
| 84 | unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; | ||
| 85 | unsigned long s3c_irqwake_intmask = 0xffffffffL; | ||
| 86 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; | ||
| 87 | unsigned long s3c_irqwake_eintmask = 0xffffffffL; | ||
| 88 | |||
| 89 | int | ||
| 90 | s3c_irq_wake(unsigned int irqno, unsigned int state) | ||
| 91 | { | ||
| 92 | unsigned long irqbit = 1 << (irqno - IRQ_EINT0); | ||
| 93 | |||
| 94 | if (!(s3c_irqwake_intallow & irqbit)) | ||
| 95 | return -ENOENT; | ||
| 96 | |||
| 97 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 98 | state ? "enabled" : "disabled", irqno); | ||
| 99 | |||
| 100 | if (!state) | ||
| 101 | s3c_irqwake_intmask |= irqbit; | ||
| 102 | else | ||
| 103 | s3c_irqwake_intmask &= ~irqbit; | ||
| 104 | |||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | static int | ||
| 109 | s3c_irqext_wake(unsigned int irqno, unsigned int state) | ||
| 110 | { | ||
| 111 | unsigned long bit = 1L << (irqno - EXTINT_OFF); | ||
| 112 | |||
| 113 | if (!(s3c_irqwake_eintallow & bit)) | ||
| 114 | return -ENOENT; | ||
| 115 | |||
| 116 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 117 | state ? "enabled" : "disabled", irqno); | ||
| 118 | |||
| 119 | if (!state) | ||
| 120 | s3c_irqwake_eintmask |= bit; | ||
| 121 | else | ||
| 122 | s3c_irqwake_eintmask &= ~bit; | ||
| 123 | |||
| 124 | return 0; | ||
| 125 | } | ||
| 126 | |||
| 127 | #else | ||
| 128 | #define s3c_irqext_wake NULL | ||
| 129 | #define s3c_irq_wake NULL | ||
| 130 | #endif | ||
| 131 | |||
| 132 | |||
| 133 | static void | 36 | static void |
| 134 | s3c_irq_mask(unsigned int irqno) | 37 | s3c_irq_mask(unsigned int irqno) |
| 135 | { | 38 | { |
| @@ -590,59 +493,6 @@ s3c_irq_demux_extint4t7(unsigned int irq, | |||
| 590 | } | 493 | } |
| 591 | } | 494 | } |
| 592 | 495 | ||
| 593 | #ifdef CONFIG_PM | ||
| 594 | |||
| 595 | static struct sleep_save irq_save[] = { | ||
| 596 | SAVE_ITEM(S3C2410_INTMSK), | ||
| 597 | SAVE_ITEM(S3C2410_INTSUBMSK), | ||
| 598 | }; | ||
| 599 | |||
| 600 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | ||
| 601 | * so we use an array to hold them, and to calculate the address of | ||
| 602 | * the register at run-time | ||
| 603 | */ | ||
| 604 | |||
| 605 | static unsigned long save_extint[3]; | ||
| 606 | static unsigned long save_eintflt[4]; | ||
| 607 | static unsigned long save_eintmask; | ||
| 608 | |||
| 609 | int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) | ||
| 610 | { | ||
| 611 | unsigned int i; | ||
| 612 | |||
| 613 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 614 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | ||
| 615 | |||
| 616 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 617 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | ||
| 618 | |||
| 619 | s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | ||
| 620 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | ||
| 621 | |||
| 622 | return 0; | ||
| 623 | } | ||
| 624 | |||
| 625 | int s3c24xx_irq_resume(struct sys_device *dev) | ||
| 626 | { | ||
| 627 | unsigned int i; | ||
| 628 | |||
| 629 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 630 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | ||
| 631 | |||
| 632 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 633 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | ||
| 634 | |||
| 635 | s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | ||
| 636 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | ||
| 637 | |||
| 638 | return 0; | ||
| 639 | } | ||
| 640 | |||
| 641 | #else | ||
| 642 | #define s3c24xx_irq_suspend NULL | ||
| 643 | #define s3c24xx_irq_resume NULL | ||
| 644 | #endif | ||
| 645 | |||
| 646 | /* s3c24xx_init_irq | 496 | /* s3c24xx_init_irq |
| 647 | * | 497 | * |
| 648 | * Initialise S3C2410 IRQ system | 498 | * Initialise S3C2410 IRQ system |
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c index 21dfa74773d1..da0d3217d3e3 100644 --- a/arch/arm/plat-s3c24xx/pm-simtec.c +++ b/arch/arm/plat-s3c24xx/pm-simtec.c | |||
| @@ -61,7 +61,7 @@ static __init int pm_simtec_init(void) | |||
| 61 | 61 | ||
| 62 | __raw_writel(gstatus4, S3C2410_GSTATUS4); | 62 | __raw_writel(gstatus4, S3C2410_GSTATUS4); |
| 63 | 63 | ||
| 64 | return s3c2410_pm_init(); | 64 | return s3c_pm_init(); |
| 65 | } | 65 | } |
| 66 | 66 | ||
| 67 | arch_initcall(pm_simtec_init); | 67 | arch_initcall(pm_simtec_init); |
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 34ef18e5b2a1..062a29339a91 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c | |||
| @@ -31,14 +31,9 @@ | |||
| 31 | #include <linux/errno.h> | 31 | #include <linux/errno.h> |
| 32 | #include <linux/time.h> | 32 | #include <linux/time.h> |
| 33 | #include <linux/interrupt.h> | 33 | #include <linux/interrupt.h> |
| 34 | #include <linux/crc32.h> | ||
| 35 | #include <linux/ioport.h> | ||
| 36 | #include <linux/serial_core.h> | 34 | #include <linux/serial_core.h> |
| 37 | #include <linux/io.h> | 35 | #include <linux/io.h> |
| 38 | 36 | ||
| 39 | #include <asm/cacheflush.h> | ||
| 40 | #include <mach/hardware.h> | ||
| 41 | |||
| 42 | #include <plat/regs-serial.h> | 37 | #include <plat/regs-serial.h> |
| 43 | #include <mach/regs-clock.h> | 38 | #include <mach/regs-clock.h> |
| 44 | #include <mach/regs-gpio.h> | 39 | #include <mach/regs-gpio.h> |
| @@ -49,10 +44,6 @@ | |||
| 49 | 44 | ||
| 50 | #include <plat/pm.h> | 45 | #include <plat/pm.h> |
| 51 | 46 | ||
| 52 | /* for external use */ | ||
| 53 | |||
| 54 | unsigned long s3c_pm_flags; | ||
| 55 | |||
| 56 | #define PFX "s3c24xx-pm: " | 47 | #define PFX "s3c24xx-pm: " |
| 57 | 48 | ||
| 58 | static struct sleep_save core_save[] = { | 49 | static struct sleep_save core_save[] = { |
| @@ -120,328 +111,14 @@ static struct sleep_save misc_save[] = { | |||
| 120 | SAVE_ITEM(S3C2410_DCLKCON), | 111 | SAVE_ITEM(S3C2410_DCLKCON), |
| 121 | }; | 112 | }; |
| 122 | 113 | ||
| 123 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 124 | |||
| 125 | #define SAVE_UART(va) \ | ||
| 126 | SAVE_ITEM((va) + S3C2410_ULCON), \ | ||
| 127 | SAVE_ITEM((va) + S3C2410_UCON), \ | ||
| 128 | SAVE_ITEM((va) + S3C2410_UFCON), \ | ||
| 129 | SAVE_ITEM((va) + S3C2410_UMCON), \ | ||
| 130 | SAVE_ITEM((va) + S3C2410_UBRDIV) | ||
| 131 | |||
| 132 | static struct sleep_save uart_save[] = { | ||
| 133 | SAVE_UART(S3C24XX_VA_UART0), | ||
| 134 | SAVE_UART(S3C24XX_VA_UART1), | ||
| 135 | #ifndef CONFIG_CPU_S3C2400 | ||
| 136 | SAVE_UART(S3C24XX_VA_UART2), | ||
| 137 | #endif | ||
| 138 | }; | ||
| 139 | |||
| 140 | /* debug | ||
| 141 | * | ||
| 142 | * we send the debug to printascii() to allow it to be seen if the | ||
| 143 | * system never wakes up from the sleep | ||
| 144 | */ | ||
| 145 | |||
| 146 | extern void printascii(const char *); | ||
| 147 | |||
| 148 | void pm_dbg(const char *fmt, ...) | ||
| 149 | { | ||
| 150 | va_list va; | ||
| 151 | char buff[256]; | ||
| 152 | |||
| 153 | va_start(va, fmt); | ||
| 154 | vsprintf(buff, fmt, va); | ||
| 155 | va_end(va); | ||
| 156 | |||
| 157 | printascii(buff); | ||
| 158 | } | ||
| 159 | |||
| 160 | static void s3c2410_pm_debug_init(void) | ||
| 161 | { | ||
| 162 | unsigned long tmp = __raw_readl(S3C2410_CLKCON); | ||
| 163 | |||
| 164 | /* re-start uart clocks */ | ||
| 165 | tmp |= S3C2410_CLKCON_UART0; | ||
| 166 | tmp |= S3C2410_CLKCON_UART1; | ||
| 167 | tmp |= S3C2410_CLKCON_UART2; | ||
| 168 | |||
| 169 | __raw_writel(tmp, S3C2410_CLKCON); | ||
| 170 | udelay(10); | ||
| 171 | } | ||
| 172 | |||
| 173 | #define DBG(fmt...) pm_dbg(fmt) | ||
| 174 | #else | ||
| 175 | #define DBG(fmt...) printk(KERN_DEBUG fmt) | ||
| 176 | |||
| 177 | #define s3c2410_pm_debug_init() do { } while(0) | ||
| 178 | |||
| 179 | static struct sleep_save uart_save[] = {}; | ||
| 180 | #endif | ||
| 181 | |||
| 182 | #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 | ||
| 183 | |||
| 184 | /* suspend checking code... | ||
| 185 | * | ||
| 186 | * this next area does a set of crc checks over all the installed | ||
| 187 | * memory, so the system can verify if the resume was ok. | ||
| 188 | * | ||
| 189 | * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, | ||
| 190 | * increasing it will mean that the area corrupted will be less easy to spot, | ||
| 191 | * and reducing the size will cause the CRC save area to grow | ||
| 192 | */ | ||
| 193 | |||
| 194 | #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) | ||
| 195 | |||
| 196 | static u32 crc_size; /* size needed for the crc block */ | ||
| 197 | static u32 *crcs; /* allocated over suspend/resume */ | ||
| 198 | |||
| 199 | typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); | ||
| 200 | |||
| 201 | /* s3c2410_pm_run_res | ||
| 202 | * | ||
| 203 | * go thorugh the given resource list, and look for system ram | ||
| 204 | */ | ||
| 205 | |||
| 206 | static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) | ||
| 207 | { | ||
| 208 | while (ptr != NULL) { | ||
| 209 | if (ptr->child != NULL) | ||
| 210 | s3c2410_pm_run_res(ptr->child, fn, arg); | ||
| 211 | |||
| 212 | if ((ptr->flags & IORESOURCE_MEM) && | ||
| 213 | strcmp(ptr->name, "System RAM") == 0) { | ||
| 214 | DBG("Found system RAM at %08lx..%08lx\n", | ||
| 215 | ptr->start, ptr->end); | ||
| 216 | arg = (fn)(ptr, arg); | ||
| 217 | } | ||
| 218 | |||
| 219 | ptr = ptr->sibling; | ||
| 220 | } | ||
| 221 | } | ||
| 222 | |||
| 223 | static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg) | ||
| 224 | { | ||
| 225 | s3c2410_pm_run_res(&iomem_resource, fn, arg); | ||
| 226 | } | ||
| 227 | |||
| 228 | static u32 *s3c2410_pm_countram(struct resource *res, u32 *val) | ||
| 229 | { | ||
| 230 | u32 size = (u32)(res->end - res->start)+1; | ||
| 231 | |||
| 232 | size += CHECK_CHUNKSIZE-1; | ||
| 233 | size /= CHECK_CHUNKSIZE; | ||
| 234 | |||
| 235 | DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); | ||
| 236 | |||
| 237 | *val += size * sizeof(u32); | ||
| 238 | return val; | ||
| 239 | } | ||
| 240 | |||
| 241 | /* s3c2410_pm_prepare_check | ||
| 242 | * | ||
| 243 | * prepare the necessary information for creating the CRCs. This | ||
| 244 | * must be done before the final save, as it will require memory | ||
| 245 | * allocating, and thus touching bits of the kernel we do not | ||
| 246 | * know about. | ||
| 247 | */ | ||
| 248 | |||
| 249 | static void s3c2410_pm_check_prepare(void) | ||
| 250 | { | ||
| 251 | crc_size = 0; | ||
| 252 | |||
| 253 | s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); | ||
| 254 | |||
| 255 | DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); | ||
| 256 | |||
| 257 | crcs = kmalloc(crc_size+4, GFP_KERNEL); | ||
| 258 | if (crcs == NULL) | ||
| 259 | printk(KERN_ERR "Cannot allocated CRC save area\n"); | ||
| 260 | } | ||
| 261 | |||
| 262 | static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) | ||
| 263 | { | ||
| 264 | unsigned long addr, left; | ||
| 265 | |||
| 266 | for (addr = res->start; addr < res->end; | ||
| 267 | addr += CHECK_CHUNKSIZE) { | ||
| 268 | left = res->end - addr; | ||
| 269 | |||
| 270 | if (left > CHECK_CHUNKSIZE) | ||
| 271 | left = CHECK_CHUNKSIZE; | ||
| 272 | |||
| 273 | *val = crc32_le(~0, phys_to_virt(addr), left); | ||
| 274 | val++; | ||
| 275 | } | ||
| 276 | |||
| 277 | return val; | ||
| 278 | } | ||
| 279 | |||
| 280 | /* s3c2410_pm_check_store | ||
| 281 | * | ||
| 282 | * compute the CRC values for the memory blocks before the final | ||
| 283 | * sleep. | ||
| 284 | */ | ||
| 285 | |||
| 286 | static void s3c2410_pm_check_store(void) | ||
| 287 | { | ||
| 288 | if (crcs != NULL) | ||
| 289 | s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs); | ||
| 290 | } | ||
| 291 | |||
| 292 | /* in_region | ||
| 293 | * | ||
| 294 | * return TRUE if the area defined by ptr..ptr+size contatins the | ||
| 295 | * what..what+whatsz | ||
| 296 | */ | ||
| 297 | |||
| 298 | static inline int in_region(void *ptr, int size, void *what, size_t whatsz) | ||
| 299 | { | ||
| 300 | if ((what+whatsz) < ptr) | ||
| 301 | return 0; | ||
| 302 | |||
| 303 | if (what > (ptr+size)) | ||
| 304 | return 0; | ||
| 305 | |||
| 306 | return 1; | ||
| 307 | } | ||
| 308 | |||
| 309 | static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val) | ||
| 310 | { | ||
| 311 | void *save_at = phys_to_virt(s3c2410_sleep_save_phys); | ||
| 312 | unsigned long addr; | ||
| 313 | unsigned long left; | ||
| 314 | void *ptr; | ||
| 315 | u32 calc; | ||
| 316 | |||
| 317 | for (addr = res->start; addr < res->end; | ||
| 318 | addr += CHECK_CHUNKSIZE) { | ||
| 319 | left = res->end - addr; | ||
| 320 | |||
| 321 | if (left > CHECK_CHUNKSIZE) | ||
| 322 | left = CHECK_CHUNKSIZE; | ||
| 323 | |||
| 324 | ptr = phys_to_virt(addr); | ||
| 325 | |||
| 326 | if (in_region(ptr, left, crcs, crc_size)) { | ||
| 327 | DBG("skipping %08lx, has crc block in\n", addr); | ||
| 328 | goto skip_check; | ||
| 329 | } | ||
| 330 | |||
| 331 | if (in_region(ptr, left, save_at, 32*4 )) { | ||
| 332 | DBG("skipping %08lx, has save block in\n", addr); | ||
| 333 | goto skip_check; | ||
| 334 | } | ||
| 335 | |||
| 336 | /* calculate and check the checksum */ | ||
| 337 | |||
| 338 | calc = crc32_le(~0, ptr, left); | ||
| 339 | if (calc != *val) { | ||
| 340 | printk(KERN_ERR PFX "Restore CRC error at " | ||
| 341 | "%08lx (%08x vs %08x)\n", addr, calc, *val); | ||
| 342 | |||
| 343 | DBG("Restore CRC error at %08lx (%08x vs %08x)\n", | ||
| 344 | addr, calc, *val); | ||
| 345 | } | ||
| 346 | |||
| 347 | skip_check: | ||
| 348 | val++; | ||
| 349 | } | ||
| 350 | |||
| 351 | return val; | ||
| 352 | } | ||
| 353 | |||
| 354 | /* s3c2410_pm_check_restore | ||
| 355 | * | ||
| 356 | * check the CRCs after the restore event and free the memory used | ||
| 357 | * to hold them | ||
| 358 | */ | ||
| 359 | |||
| 360 | static void s3c2410_pm_check_restore(void) | ||
| 361 | { | ||
| 362 | if (crcs != NULL) { | ||
| 363 | s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs); | ||
| 364 | kfree(crcs); | ||
| 365 | crcs = NULL; | ||
| 366 | } | ||
| 367 | } | ||
| 368 | |||
| 369 | #else | ||
| 370 | |||
| 371 | #define s3c2410_pm_check_prepare() do { } while(0) | ||
| 372 | #define s3c2410_pm_check_restore() do { } while(0) | ||
| 373 | #define s3c2410_pm_check_store() do { } while(0) | ||
| 374 | #endif | ||
| 375 | |||
| 376 | /* helper functions to save and restore register state */ | ||
| 377 | |||
| 378 | void s3c2410_pm_do_save(struct sleep_save *ptr, int count) | ||
| 379 | { | ||
| 380 | for (; count > 0; count--, ptr++) { | ||
| 381 | ptr->val = __raw_readl(ptr->reg); | ||
| 382 | DBG("saved %p value %08lx\n", ptr->reg, ptr->val); | ||
| 383 | } | ||
| 384 | } | ||
| 385 | |||
| 386 | /* s3c2410_pm_do_restore | ||
| 387 | * | ||
| 388 | * restore the system from the given list of saved registers | ||
| 389 | * | ||
| 390 | * Note, we do not use DBG() in here, as the system may not have | ||
| 391 | * restore the UARTs state yet | ||
| 392 | */ | ||
| 393 | |||
| 394 | void s3c2410_pm_do_restore(struct sleep_save *ptr, int count) | ||
| 395 | { | ||
| 396 | for (; count > 0; count--, ptr++) { | ||
| 397 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | ||
| 398 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | ||
| 399 | |||
| 400 | __raw_writel(ptr->val, ptr->reg); | ||
| 401 | } | ||
| 402 | } | ||
| 403 | |||
| 404 | /* s3c2410_pm_do_restore_core | ||
| 405 | * | ||
| 406 | * similar to s3c2410_pm_do_restore_core | ||
| 407 | * | ||
| 408 | * WARNING: Do not put any debug in here that may effect memory or use | ||
| 409 | * peripherals, as things may be changing! | ||
| 410 | */ | ||
| 411 | |||
| 412 | static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count) | ||
| 413 | { | ||
| 414 | for (; count > 0; count--, ptr++) { | ||
| 415 | __raw_writel(ptr->val, ptr->reg); | ||
| 416 | } | ||
| 417 | } | ||
| 418 | 114 | ||
| 419 | /* s3c2410_pm_show_resume_irqs | 115 | /* s3c_pm_check_resume_pin |
| 420 | * | ||
| 421 | * print any IRQs asserted at resume time (ie, we woke from) | ||
| 422 | */ | ||
| 423 | |||
| 424 | static void s3c2410_pm_show_resume_irqs(int start, unsigned long which, | ||
| 425 | unsigned long mask) | ||
| 426 | { | ||
| 427 | int i; | ||
| 428 | |||
| 429 | which &= ~mask; | ||
| 430 | |||
| 431 | for (i = 0; i <= 31; i++) { | ||
| 432 | if ((which) & (1L<<i)) { | ||
| 433 | DBG("IRQ %d asserted at resume\n", start+i); | ||
| 434 | } | ||
| 435 | } | ||
| 436 | } | ||
| 437 | |||
| 438 | /* s3c2410_pm_check_resume_pin | ||
| 439 | * | 116 | * |
| 440 | * check to see if the pin is configured correctly for sleep mode, and | 117 | * check to see if the pin is configured correctly for sleep mode, and |
| 441 | * make any necessary adjustments if it is not | 118 | * make any necessary adjustments if it is not |
| 442 | */ | 119 | */ |
| 443 | 120 | ||
| 444 | static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) | 121 | static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) |
| 445 | { | 122 | { |
| 446 | unsigned long irqstate; | 123 | unsigned long irqstate; |
| 447 | unsigned long pinstate; | 124 | unsigned long pinstate; |
| @@ -456,21 +133,21 @@ static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) | |||
| 456 | 133 | ||
| 457 | if (!irqstate) { | 134 | if (!irqstate) { |
| 458 | if (pinstate == S3C2410_GPIO_IRQ) | 135 | if (pinstate == S3C2410_GPIO_IRQ) |
| 459 | DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); | 136 | S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); |
| 460 | } else { | 137 | } else { |
| 461 | if (pinstate == S3C2410_GPIO_IRQ) { | 138 | if (pinstate == S3C2410_GPIO_IRQ) { |
| 462 | DBG("Disabling IRQ %d (pin %d)\n", irq, pin); | 139 | S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); |
| 463 | s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); | 140 | s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); |
| 464 | } | 141 | } |
| 465 | } | 142 | } |
| 466 | } | 143 | } |
| 467 | 144 | ||
| 468 | /* s3c2410_pm_configure_extint | 145 | /* s3c_pm_configure_extint |
| 469 | * | 146 | * |
| 470 | * configure all external interrupt pins | 147 | * configure all external interrupt pins |
| 471 | */ | 148 | */ |
| 472 | 149 | ||
| 473 | static void s3c2410_pm_configure_extint(void) | 150 | void s3c_pm_configure_extint(void) |
| 474 | { | 151 | { |
| 475 | int pin; | 152 | int pin; |
| 476 | 153 | ||
| @@ -480,11 +157,11 @@ static void s3c2410_pm_configure_extint(void) | |||
| 480 | */ | 157 | */ |
| 481 | 158 | ||
| 482 | for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { | 159 | for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { |
| 483 | s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0); | 160 | s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0); |
| 484 | } | 161 | } |
| 485 | 162 | ||
| 486 | for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { | 163 | for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { |
| 487 | s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); | 164 | s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); |
| 488 | } | 165 | } |
| 489 | } | 166 | } |
| 490 | 167 | ||
| @@ -494,12 +171,12 @@ static void s3c2410_pm_configure_extint(void) | |||
| 494 | #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) | 171 | #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) |
| 495 | #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) | 172 | #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) |
| 496 | 173 | ||
| 497 | /* s3c2410_pm_save_gpios() | 174 | /* s3c_pm_save_gpios() |
| 498 | * | 175 | * |
| 499 | * Save the state of the GPIOs | 176 | * Save the state of the GPIOs |
| 500 | */ | 177 | */ |
| 501 | 178 | ||
| 502 | static void s3c2410_pm_save_gpios(void) | 179 | void s3c_pm_save_gpios(void) |
| 503 | { | 180 | { |
| 504 | struct gpio_sleep *gps = gpio_save; | 181 | struct gpio_sleep *gps = gpio_save; |
| 505 | unsigned int gpio; | 182 | unsigned int gpio; |
| @@ -538,7 +215,10 @@ static inline int is_out(unsigned long con) | |||
| 538 | return con == 1; | 215 | return con == 1; |
| 539 | } | 216 | } |
| 540 | 217 | ||
| 541 | /* s3c2410_pm_restore_gpio() | 218 | /** |
| 219 | * s3c2410_pm_restore_gpio() - restore the given GPIO bank | ||
| 220 | * @index: The number of the GPIO bank being resumed. | ||
| 221 | * @gps: The sleep confgiuration for the bank. | ||
| 542 | * | 222 | * |
| 543 | * Restore one of the GPIO banks that was saved during suspend. This is | 223 | * Restore one of the GPIO banks that was saved during suspend. This is |
| 544 | * not as simple as once thought, due to the possibility of glitches | 224 | * not as simple as once thought, due to the possibility of glitches |
| @@ -646,8 +326,8 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) | |||
| 646 | __raw_writel(gps->gpup, base + OFFS_UP); | 326 | __raw_writel(gps->gpup, base + OFFS_UP); |
| 647 | } | 327 | } |
| 648 | 328 | ||
| 649 | DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", | 329 | S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", |
| 650 | index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); | 330 | index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); |
| 651 | } | 331 | } |
| 652 | 332 | ||
| 653 | 333 | ||
| @@ -656,7 +336,7 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) | |||
| 656 | * Restore the state of the GPIOs | 336 | * Restore the state of the GPIOs |
| 657 | */ | 337 | */ |
| 658 | 338 | ||
| 659 | static void s3c2410_pm_restore_gpios(void) | 339 | void s3c_pm_restore_gpios(void) |
| 660 | { | 340 | { |
| 661 | struct gpio_sleep *gps = gpio_save; | 341 | struct gpio_sleep *gps = gpio_save; |
| 662 | int gpio; | 342 | int gpio; |
| @@ -666,150 +346,15 @@ static void s3c2410_pm_restore_gpios(void) | |||
| 666 | } | 346 | } |
| 667 | } | 347 | } |
| 668 | 348 | ||
| 669 | void (*pm_cpu_prep)(void); | 349 | void s3c_pm_restore_core(void) |
| 670 | void (*pm_cpu_sleep)(void); | ||
| 671 | |||
| 672 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | ||
| 673 | |||
| 674 | /* s3c2410_pm_enter | ||
| 675 | * | ||
| 676 | * central control for sleep/resume process | ||
| 677 | */ | ||
| 678 | |||
| 679 | static int s3c2410_pm_enter(suspend_state_t state) | ||
| 680 | { | 350 | { |
| 681 | unsigned long regs_save[16]; | 351 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); |
| 682 | 352 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | |
| 683 | /* ensure the debug is initialised (if enabled) */ | ||
| 684 | |||
| 685 | s3c2410_pm_debug_init(); | ||
| 686 | |||
| 687 | DBG("s3c2410_pm_enter(%d)\n", state); | ||
| 688 | |||
| 689 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | ||
| 690 | printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); | ||
| 691 | return -EINVAL; | ||
| 692 | } | ||
| 693 | |||
| 694 | /* check if we have anything to wake-up with... bad things seem | ||
| 695 | * to happen if you suspend with no wakeup (system will often | ||
| 696 | * require a full power-cycle) | ||
| 697 | */ | ||
| 698 | |||
| 699 | if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | ||
| 700 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { | ||
| 701 | printk(KERN_ERR PFX "No sources enabled for wake-up!\n"); | ||
| 702 | printk(KERN_ERR PFX "Aborting sleep\n"); | ||
| 703 | return -EINVAL; | ||
| 704 | } | ||
| 705 | |||
| 706 | /* prepare check area if configured */ | ||
| 707 | |||
| 708 | s3c2410_pm_check_prepare(); | ||
| 709 | |||
| 710 | /* store the physical address of the register recovery block */ | ||
| 711 | |||
| 712 | s3c2410_sleep_save_phys = virt_to_phys(regs_save); | ||
| 713 | |||
| 714 | DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys); | ||
| 715 | |||
| 716 | /* save all necessary core registers not covered by the drivers */ | ||
| 717 | |||
| 718 | s3c2410_pm_save_gpios(); | ||
| 719 | s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); | ||
| 720 | s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save)); | ||
| 721 | s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save)); | ||
| 722 | |||
| 723 | /* set the irq configuration for wake */ | ||
| 724 | |||
| 725 | s3c2410_pm_configure_extint(); | ||
| 726 | |||
| 727 | DBG("sleep: irq wakeup masks: %08lx,%08lx\n", | ||
| 728 | s3c_irqwake_intmask, s3c_irqwake_eintmask); | ||
| 729 | |||
| 730 | __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); | ||
| 731 | __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); | ||
| 732 | |||
| 733 | /* ack any outstanding external interrupts before we go to sleep */ | ||
| 734 | |||
| 735 | __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); | ||
| 736 | __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); | ||
| 737 | __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); | ||
| 738 | |||
| 739 | /* call cpu specific preparation */ | ||
| 740 | |||
| 741 | pm_cpu_prep(); | ||
| 742 | |||
| 743 | /* flush cache back to ram */ | ||
| 744 | |||
| 745 | flush_cache_all(); | ||
| 746 | |||
| 747 | s3c2410_pm_check_store(); | ||
| 748 | |||
| 749 | /* send the cpu to sleep... */ | ||
| 750 | |||
| 751 | __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ | ||
| 752 | |||
| 753 | /* s3c2410_cpu_save will also act as our return point from when | ||
| 754 | * we resume as it saves its own register state, so use the return | ||
| 755 | * code to differentiate return from save and return from sleep */ | ||
| 756 | |||
| 757 | if (s3c2410_cpu_save(regs_save) == 0) { | ||
| 758 | flush_cache_all(); | ||
| 759 | pm_cpu_sleep(); | ||
| 760 | } | ||
| 761 | |||
| 762 | /* restore the cpu state */ | ||
| 763 | |||
| 764 | cpu_init(); | ||
| 765 | |||
| 766 | /* restore the system state */ | ||
| 767 | |||
| 768 | s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); | ||
| 769 | s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | ||
| 770 | s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save)); | ||
| 771 | s3c2410_pm_restore_gpios(); | ||
| 772 | |||
| 773 | s3c2410_pm_debug_init(); | ||
| 774 | |||
| 775 | /* check what irq (if any) restored the system */ | ||
| 776 | |||
| 777 | DBG("post sleep: IRQs 0x%08x, 0x%08x\n", | ||
| 778 | __raw_readl(S3C2410_SRCPND), | ||
| 779 | __raw_readl(S3C2410_EINTPEND)); | ||
| 780 | |||
| 781 | s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), | ||
| 782 | s3c_irqwake_intmask); | ||
| 783 | |||
| 784 | s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), | ||
| 785 | s3c_irqwake_eintmask); | ||
| 786 | |||
| 787 | DBG("post sleep, preparing to return\n"); | ||
| 788 | |||
| 789 | s3c2410_pm_check_restore(); | ||
| 790 | |||
| 791 | /* ok, let's return from sleep */ | ||
| 792 | |||
| 793 | DBG("S3C2410 PM Resume (post-restore)\n"); | ||
| 794 | return 0; | ||
| 795 | } | 353 | } |
| 796 | 354 | ||
| 797 | static struct platform_suspend_ops s3c2410_pm_ops = { | 355 | void s3c_pm_save_core(void) |
| 798 | .enter = s3c2410_pm_enter, | ||
| 799 | .valid = suspend_valid_only_mem, | ||
| 800 | }; | ||
| 801 | |||
| 802 | /* s3c2410_pm_init | ||
| 803 | * | ||
| 804 | * Attach the power management functions. This should be called | ||
| 805 | * from the board specific initialisation if the board supports | ||
| 806 | * it. | ||
| 807 | */ | ||
| 808 | |||
| 809 | int __init s3c2410_pm_init(void) | ||
| 810 | { | 356 | { |
| 811 | printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n"); | 357 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); |
| 812 | 358 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | |
| 813 | suspend_set_ops(&s3c2410_pm_ops); | ||
| 814 | return 0; | ||
| 815 | } | 359 | } |
| 360 | |||
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index c1de6bb0101b..1364317d421e 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c | |||
| @@ -145,13 +145,13 @@ static struct sleep_save s3c244x_sleep[] = { | |||
| 145 | 145 | ||
| 146 | static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) | 146 | static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) |
| 147 | { | 147 | { |
| 148 | s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); | 148 | s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); |
| 149 | return 0; | 149 | return 0; |
| 150 | } | 150 | } |
| 151 | 151 | ||
| 152 | static int s3c244x_resume(struct sys_device *dev) | 152 | static int s3c244x_resume(struct sys_device *dev) |
| 153 | { | 153 | { |
| 154 | s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); | 154 | s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); |
| 155 | return 0; | 155 | return 0; |
| 156 | } | 156 | } |
| 157 | 157 | ||
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 76594b212802..e73e3b6e88d2 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S | |||
| @@ -41,25 +41,13 @@ | |||
| 41 | 41 | ||
| 42 | .text | 42 | .text |
| 43 | 43 | ||
| 44 | /* s3c2410_cpu_save | 44 | /* s3c_cpu_save |
| 45 | * | ||
| 46 | * save enough of the CPU state to allow us to re-start | ||
| 47 | * pm.c code. as we store items like the sp/lr, we will | ||
| 48 | * end up returning from this function when the cpu resumes | ||
| 49 | * so the return value is set to mark this. | ||
| 50 | * | ||
| 51 | * This arangement means we avoid having to flush the cache | ||
| 52 | * from this code. | ||
| 53 | * | 45 | * |
| 54 | * entry: | 46 | * entry: |
| 55 | * r0 = pointer to save block | 47 | * r0 = save address (virtual addr of s3c_sleep_save_phys) |
| 56 | * | ||
| 57 | * exit: | ||
| 58 | * r0 = 0 => we stored everything | ||
| 59 | * 1 => resumed from sleep | ||
| 60 | */ | 48 | */ |
| 61 | 49 | ||
| 62 | ENTRY(s3c2410_cpu_save) | 50 | ENTRY(s3c_cpu_save) |
| 63 | stmfd sp!, { r4 - r12, lr } | 51 | stmfd sp!, { r4 - r12, lr } |
| 64 | 52 | ||
| 65 | @@ store co-processor registers | 53 | @@ store co-processor registers |
| @@ -71,20 +59,25 @@ ENTRY(s3c2410_cpu_save) | |||
| 71 | 59 | ||
| 72 | stmia r0, { r4 - r13 } | 60 | stmia r0, { r4 - r13 } |
| 73 | 61 | ||
| 74 | mov r0, #0 | 62 | @@ write our state back to RAM |
| 75 | ldmfd sp, { r4 - r12, pc } | 63 | bl s3c_pm_cb_flushcache |
| 76 | 64 | ||
| 65 | @@ jump to final code to send system to sleep | ||
| 66 | ldr r0, =pm_cpu_sleep | ||
| 67 | @@ldr pc, [ r0 ] | ||
| 68 | ldr r0, [ r0 ] | ||
| 69 | mov pc, r0 | ||
| 70 | |||
| 77 | @@ return to the caller, after having the MMU | 71 | @@ return to the caller, after having the MMU |
| 78 | @@ turned on, this restores the last bits from the | 72 | @@ turned on, this restores the last bits from the |
| 79 | @@ stack | 73 | @@ stack |
| 80 | resume_with_mmu: | 74 | resume_with_mmu: |
| 81 | mov r0, #1 | ||
| 82 | ldmfd sp!, { r4 - r12, pc } | 75 | ldmfd sp!, { r4 - r12, pc } |
| 83 | 76 | ||
| 84 | .ltorg | 77 | .ltorg |
| 85 | 78 | ||
| 86 | @@ the next bits sit in the .data segment, even though they | 79 | @@ the next bits sit in the .data segment, even though they |
| 87 | @@ happen to be code... the s3c2410_sleep_save_phys needs to be | 80 | @@ happen to be code... the s3c_sleep_save_phys needs to be |
| 88 | @@ accessed by the resume code before it can restore the MMU. | 81 | @@ accessed by the resume code before it can restore the MMU. |
| 89 | @@ This means that the variable has to be close enough for the | 82 | @@ This means that the variable has to be close enough for the |
| 90 | @@ code to read it... since the .text segment needs to be RO, | 83 | @@ code to read it... since the .text segment needs to be RO, |
| @@ -92,19 +85,19 @@ resume_with_mmu: | |||
| 92 | 85 | ||
| 93 | .data | 86 | .data |
| 94 | 87 | ||
| 95 | .global s3c2410_sleep_save_phys | 88 | .global s3c_sleep_save_phys |
| 96 | s3c2410_sleep_save_phys: | 89 | s3c_sleep_save_phys: |
| 97 | .word 0 | 90 | .word 0 |
| 98 | 91 | ||
| 99 | 92 | ||
| 100 | /* sleep magic, to allow the bootloader to check for an valid | 93 | /* sleep magic, to allow the bootloader to check for an valid |
| 101 | * image to resume to. Must be the first word before the | 94 | * image to resume to. Must be the first word before the |
| 102 | * s3c2410_cpu_resume entry. | 95 | * s3c_cpu_resume entry. |
| 103 | */ | 96 | */ |
| 104 | 97 | ||
| 105 | .word 0x2bedf00d | 98 | .word 0x2bedf00d |
| 106 | 99 | ||
| 107 | /* s3c2410_cpu_resume | 100 | /* s3c_cpu_resume |
| 108 | * | 101 | * |
| 109 | * resume code entry for bootloader to call | 102 | * resume code entry for bootloader to call |
| 110 | * | 103 | * |
| @@ -113,7 +106,7 @@ s3c2410_sleep_save_phys: | |||
| 113 | * must not write to the code segment (code is read-only) | 106 | * must not write to the code segment (code is read-only) |
| 114 | */ | 107 | */ |
| 115 | 108 | ||
| 116 | ENTRY(s3c2410_cpu_resume) | 109 | ENTRY(s3c_cpu_resume) |
| 117 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE | 110 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE |
| 118 | msr cpsr_c, r0 | 111 | msr cpsr_c, r0 |
| 119 | 112 | ||
| @@ -145,7 +138,7 @@ ENTRY(s3c2410_cpu_resume) | |||
| 145 | mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs | 138 | mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs |
| 146 | mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches | 139 | mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches |
| 147 | 140 | ||
| 148 | ldr r0, s3c2410_sleep_save_phys @ address of restore block | 141 | ldr r0, s3c_sleep_save_phys @ address of restore block |
| 149 | ldmia r0, { r4 - r13 } | 142 | ldmia r0, { r4 - r13 } |
| 150 | 143 | ||
| 151 | mcr p15, 0, r4, c13, c0, 0 @ PID | 144 | mcr p15, 0, r4, c13, c0, 0 @ PID |
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index fbde183a4560..91f49a3a665d 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c | |||
| @@ -96,6 +96,11 @@ static struct map_desc s3c_iodesc[] __initdata = { | |||
| 96 | .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), | 96 | .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), |
| 97 | .length = SZ_4K, | 97 | .length = SZ_4K, |
| 98 | .type = MT_DEVICE, | 98 | .type = MT_DEVICE, |
| 99 | }, { | ||
| 100 | .virtual = (unsigned long)S3C64XX_VA_MODEM, | ||
| 101 | .pfn = __phys_to_pfn(S3C64XX_PA_MODEM), | ||
| 102 | .length = SZ_4K, | ||
| 103 | .type = MT_DEVICE, | ||
| 99 | }, | 104 | }, |
| 100 | }; | 105 | }; |
| 101 | 106 | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h new file mode 100644 index 000000000000..82342f6fd27d --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * S3C64XX - GPIO memory port register definitions | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H | ||
| 12 | #define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__ | ||
| 13 | |||
| 14 | #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0) | ||
| 15 | #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4) | ||
| 16 | |||
| 17 | #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0) | ||
| 18 | #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4) | ||
| 19 | #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8) | ||
| 20 | |||
| 21 | #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0) | ||
| 22 | #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4) | ||
| 23 | |||
| 24 | #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */ | ||
| 25 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h index 75b873d82808..81f7f6e6832e 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h | |||
| @@ -13,23 +13,175 @@ | |||
| 13 | 13 | ||
| 14 | /* Base addresses for each of the banks */ | 14 | /* Base addresses for each of the banks */ |
| 15 | 15 | ||
| 16 | #define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) | 16 | #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) |
| 17 | #define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) | 17 | |
| 18 | #define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) | 18 | #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) |
| 19 | #define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) | 19 | #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) |
| 20 | #define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) | 20 | #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) |
| 21 | #define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) | 21 | #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) |
| 22 | #define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) | 22 | #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) |
| 23 | #define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) | 23 | #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) |
| 24 | #define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) | 24 | #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) |
| 25 | #define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) | 25 | #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) |
| 26 | #define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) | 26 | #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) |
| 27 | #define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) | 27 | #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) |
| 28 | #define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) | 28 | #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) |
| 29 | #define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) | 29 | #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) |
| 30 | #define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) | 30 | #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) |
| 31 | #define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) | 31 | #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) |
| 32 | #define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) | 32 | #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) |
| 33 | #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) | ||
| 34 | #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) | ||
| 35 | |||
| 36 | /* SPCON */ | ||
| 37 | |||
| 38 | #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) | ||
| 39 | |||
| 40 | #define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) | ||
| 41 | #define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) | ||
| 42 | #define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) | ||
| 43 | #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) | ||
| 44 | #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) | ||
| 45 | #define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) | ||
| 46 | |||
| 47 | #define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) | ||
| 48 | #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) | ||
| 49 | #define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) | ||
| 50 | #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) | ||
| 51 | #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) | ||
| 52 | #define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) | ||
| 53 | |||
| 54 | #define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) | ||
| 55 | #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) | ||
| 56 | #define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) | ||
| 57 | #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) | ||
| 58 | #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) | ||
| 59 | #define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) | ||
| 60 | |||
| 61 | #define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) | ||
| 62 | #define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) | ||
| 63 | #define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) | ||
| 64 | #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) | ||
| 65 | #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) | ||
| 66 | #define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) | ||
| 67 | |||
| 68 | #define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) | ||
| 69 | #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) | ||
| 70 | #define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) | ||
| 71 | #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) | ||
| 72 | #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) | ||
| 73 | #define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) | ||
| 74 | |||
| 75 | #define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) | ||
| 76 | |||
| 77 | #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) | ||
| 78 | #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) | ||
| 79 | #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) | ||
| 80 | #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) | ||
| 81 | #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) | ||
| 82 | #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) | ||
| 83 | |||
| 84 | #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) | ||
| 85 | #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) | ||
| 86 | #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) | ||
| 87 | #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) | ||
| 88 | #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) | ||
| 89 | |||
| 90 | #define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) | ||
| 91 | #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) | ||
| 92 | #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) | ||
| 93 | #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) | ||
| 94 | #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) | ||
| 95 | |||
| 96 | #define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) | ||
| 97 | #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) | ||
| 98 | #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) | ||
| 99 | #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) | ||
| 100 | #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) | ||
| 101 | |||
| 102 | #define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) | ||
| 103 | #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) | ||
| 104 | #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) | ||
| 105 | #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) | ||
| 106 | #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) | ||
| 107 | |||
| 108 | #define S3C64XX_SPCON_USBH_DMPD (1 << 7) | ||
| 109 | #define S3C64XX_SPCON_USBH_DPPD (1 << 6) | ||
| 110 | #define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) | ||
| 111 | #define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) | ||
| 112 | #define S3C64XX_SPCON_USBH_SUSPND (1 << 3) | ||
| 113 | |||
| 114 | #define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) | ||
| 115 | #define S3C64XX_SPCON_LCD_SEL_SHIFT (0) | ||
| 116 | #define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) | ||
| 117 | #define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) | ||
| 118 | #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) | ||
| 119 | |||
| 120 | |||
| 121 | /* External interrupt registers */ | ||
| 122 | |||
| 123 | #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) | ||
| 124 | #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) | ||
| 125 | #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) | ||
| 126 | #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) | ||
| 127 | #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) | ||
| 128 | |||
| 129 | #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) | ||
| 130 | #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) | ||
| 131 | #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) | ||
| 132 | #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) | ||
| 133 | #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) | ||
| 134 | |||
| 135 | #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) | ||
| 136 | #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) | ||
| 137 | #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) | ||
| 138 | #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) | ||
| 139 | #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) | ||
| 140 | |||
| 141 | #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) | ||
| 142 | #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) | ||
| 143 | #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) | ||
| 144 | #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) | ||
| 145 | #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) | ||
| 146 | |||
| 147 | #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) | ||
| 148 | #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) | ||
| 149 | |||
| 150 | #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) | ||
| 151 | #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) | ||
| 152 | |||
| 153 | #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) | ||
| 154 | #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) | ||
| 155 | #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) | ||
| 156 | #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) | ||
| 157 | #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) | ||
| 158 | #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) | ||
| 159 | |||
| 160 | #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) | ||
| 161 | #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) | ||
| 162 | |||
| 163 | /* GPIO sleep configuration */ | ||
| 164 | |||
| 165 | #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) | ||
| 166 | |||
| 167 | #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) | ||
| 168 | #define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) | ||
| 169 | |||
| 170 | #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) | ||
| 171 | #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) | ||
| 172 | #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) | ||
| 173 | #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) | ||
| 174 | |||
| 175 | #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) | ||
| 176 | #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) | ||
| 177 | #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) | ||
| 178 | #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) | ||
| 179 | |||
| 180 | |||
| 181 | #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) | ||
| 182 | |||
| 183 | #define S3C64XX_SLPEN_USE_xSLP (1 << 0) | ||
| 184 | #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) | ||
| 33 | 185 | ||
| 34 | #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ | 186 | #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ |
| 35 | 187 | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-modem.h b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h new file mode 100644 index 000000000000..49f7759dedfa --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* arch/arm/plat-s3c64xx/include/plat/regs-modem.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * S3C64XX - modem block registers | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __PLAT_S3C64XX_REGS_MODEM_H | ||
| 16 | #define __PLAT_S3C64XX_REGS_MODEM_H __FILE__ | ||
| 17 | |||
| 18 | #define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x)) | ||
| 19 | |||
| 20 | #define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0) | ||
| 21 | #define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4) | ||
| 22 | #define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8) | ||
| 23 | #define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC) | ||
| 24 | #define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10) | ||
| 25 | #define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14) | ||
| 26 | #define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18) | ||
| 27 | |||
| 28 | #define MIFPCON_INT2M_LEVEL (1 << 4) | ||
| 29 | #define MIFPCON_LCD_BYPASS (1 << 3) | ||
| 30 | |||
| 31 | #endif /* __PLAT_S3C64XX_REGS_MODEM_H */ | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h index d8ed82917096..69b78d9f83b8 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h | |||
| @@ -17,6 +17,10 @@ | |||
| 17 | 17 | ||
| 18 | #define S3C_SYSREG(x) (S3C_VA_SYS + (x)) | 18 | #define S3C_SYSREG(x) (S3C_VA_SYS + (x)) |
| 19 | 19 | ||
| 20 | #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100) | ||
| 21 | #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) | ||
| 22 | #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) | ||
| 23 | |||
| 20 | #define S3C64XX_OTHERS S3C_SYSREG(0x900) | 24 | #define S3C64XX_OTHERS S3C_SYSREG(0x900) |
| 21 | 25 | ||
| 22 | #define S3C64XX_OTHERS_USBMASK (1 << 16) | 26 | #define S3C64XX_OTHERS_USBMASK (1 << 16) |
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h new file mode 100644 index 000000000000..270d96ac9705 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h | |||
| @@ -0,0 +1,116 @@ | |||
| 1 | /* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * S3C64XX - syscon power and sleep control registers | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H | ||
| 16 | #define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__ | ||
| 17 | |||
| 18 | #define S3C64XX_PWR_CFG S3C_SYSREG(0x804) | ||
| 19 | |||
| 20 | #define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17) | ||
| 21 | #define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16) | ||
| 22 | #define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15) | ||
| 23 | #define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14) | ||
| 24 | #define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13) | ||
| 25 | #define S3C64XX_PWRCFG_TS_DISABLE (1 << 12) | ||
| 26 | #define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11) | ||
| 27 | #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10) | ||
| 28 | #define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9) | ||
| 29 | #define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8) | ||
| 30 | #define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7) | ||
| 31 | |||
| 32 | #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5) | ||
| 33 | #define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5) | ||
| 34 | #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5) | ||
| 35 | #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5) | ||
| 36 | #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5) | ||
| 37 | #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5) | ||
| 38 | |||
| 39 | #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3) | ||
| 40 | #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3) | ||
| 41 | #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3) | ||
| 42 | #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3) | ||
| 43 | #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3) | ||
| 44 | |||
| 45 | #define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2) | ||
| 46 | #define S3C64XX_PWRCFG_OSC27_EN (1 << 0) | ||
| 47 | |||
| 48 | #define S3C64XX_EINT_MASK S3C_SYSREG(0x808) | ||
| 49 | |||
| 50 | #define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810) | ||
| 51 | |||
| 52 | #define S3C64XX_NORMALCFG_IROM_ON (1 << 30) | ||
| 53 | #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16) | ||
| 54 | #define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15) | ||
| 55 | #define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14) | ||
| 56 | #define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13) | ||
| 57 | #define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12) | ||
| 58 | #define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10) | ||
| 59 | #define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9) | ||
| 60 | |||
| 61 | #define S3C64XX_STOP_CFG S3C_SYSREG(0x814) | ||
| 62 | |||
| 63 | #define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29) | ||
| 64 | #define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20) | ||
| 65 | #define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17) | ||
| 66 | #define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8) | ||
| 67 | #define S3C64XX_STOPCFG_OSC_EN (1 << 0) | ||
| 68 | |||
| 69 | #define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818) | ||
| 70 | |||
| 71 | #define S3C64XX_SLEEPCFG_OSC_EN (1 << 0) | ||
| 72 | |||
| 73 | #define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c) | ||
| 74 | |||
| 75 | #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6) | ||
| 76 | #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5) | ||
| 77 | #define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4) | ||
| 78 | #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3) | ||
| 79 | #define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2) | ||
| 80 | #define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1) | ||
| 81 | #define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0) | ||
| 82 | |||
| 83 | #define S3C64XX_OSC_STABLE S3C_SYSREG(0x824) | ||
| 84 | #define S3C64XX_PWR_STABLE S3C_SYSREG(0x828) | ||
| 85 | |||
| 86 | #define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908) | ||
| 87 | |||
| 88 | #define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11) | ||
| 89 | #define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10) | ||
| 90 | #define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9) | ||
| 91 | #define S3C64XX_WAKEUPSTAT_HSI (1 << 8) | ||
| 92 | #define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6) | ||
| 93 | #define S3C64XX_WAKEUPSTAT_MSM (1 << 5) | ||
| 94 | #define S3C64XX_WAKEUPSTAT_KEY (1 << 4) | ||
| 95 | #define S3C64XX_WAKEUPSTAT_TS (1 << 3) | ||
| 96 | #define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2) | ||
| 97 | #define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1) | ||
| 98 | #define S3C64XX_WAKEUPSTAT_EINT (1 << 0) | ||
| 99 | |||
| 100 | #define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c) | ||
| 101 | |||
| 102 | #define S3C64XX_BLKPWRSTAT_G (1 << 7) | ||
| 103 | #define S3C64XX_BLKPWRSTAT_ETM (1 << 6) | ||
| 104 | #define S3C64XX_BLKPWRSTAT_S (1 << 5) | ||
| 105 | #define S3C64XX_BLKPWRSTAT_F (1 << 4) | ||
| 106 | #define S3C64XX_BLKPWRSTAT_P (1 << 3) | ||
| 107 | #define S3C64XX_BLKPWRSTAT_I (1 << 2) | ||
| 108 | #define S3C64XX_BLKPWRSTAT_V (1 << 1) | ||
| 109 | #define S3C64XX_BLKPWRSTAT_TOP (1 << 0) | ||
| 110 | |||
| 111 | #define S3C64XX_INFORM0 S3C_SYSREG(0xA00) | ||
| 112 | #define S3C64XX_INFORM1 S3C_SYSREG(0xA04) | ||
| 113 | #define S3C64XX_INFORM2 S3C_SYSREG(0xA08) | ||
| 114 | #define S3C64XX_INFORM3 S3C_SYSREG(0xA0C) | ||
| 115 | |||
| 116 | #endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */ | ||
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index cf524826c93a..47e5155bb13e 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c | |||
| @@ -27,20 +27,6 @@ | |||
| 27 | #include <mach/map.h> | 27 | #include <mach/map.h> |
| 28 | #include <plat/cpu.h> | 28 | #include <plat/cpu.h> |
| 29 | 29 | ||
| 30 | /* GPIO is 0x7F008xxx, */ | ||
| 31 | #define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x)) | ||
| 32 | |||
| 33 | #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) | ||
| 34 | #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) | ||
| 35 | #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) | ||
| 36 | #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) | ||
| 37 | #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) | ||
| 38 | #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) | ||
| 39 | |||
| 40 | #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) | ||
| 41 | #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) | ||
| 42 | |||
| 43 | |||
| 44 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) | 30 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) |
| 45 | #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) | 31 | #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) |
| 46 | 32 | ||
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index b4211d8b2ac7..945e0d237a1d 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | # | 12 | # |
| 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new | 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new |
| 14 | # | 14 | # |
| 15 | # Last update: Thu Mar 12 18:01:45 2009 | 15 | # Last update: Mon Mar 23 20:09:01 2009 |
| 16 | # | 16 | # |
| 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number | 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number |
| 18 | # | 18 | # |
| @@ -2124,3 +2124,11 @@ mx27wallace MACH_MX27WALLACE MX27WALLACE 2133 | |||
| 2124 | fmzwebmodul MACH_FMZWEBMODUL FMZWEBMODUL 2134 | 2124 | fmzwebmodul MACH_FMZWEBMODUL FMZWEBMODUL 2134 |
| 2125 | rd78x00_masa MACH_RD78X00_MASA RD78X00_MASA 2135 | 2125 | rd78x00_masa MACH_RD78X00_MASA RD78X00_MASA 2135 |
| 2126 | smallogger MACH_SMALLOGGER SMALLOGGER 2136 | 2126 | smallogger MACH_SMALLOGGER SMALLOGGER 2136 |
| 2127 | ccw9p9215 MACH_CCW9P9215 CCW9P9215 2137 | ||
| 2128 | dm355_leopard MACH_DM355_LEOPARD DM355_LEOPARD 2138 | ||
| 2129 | ts219 MACH_TS219 TS219 2139 | ||
| 2130 | tny_a9263 MACH_TNY_A9263 TNY_A9263 2140 | ||
| 2131 | apollo MACH_APOLLO APOLLO 2141 | ||
| 2132 | at91cap9stk MACH_AT91CAP9STK AT91CAP9STK 2142 | ||
| 2133 | spc300 MACH_SPC300 SPC300 2143 | ||
| 2134 | eko MACH_EKO EKO 2144 | ||
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h index 8de86e4feada..c8c98dd44ad4 100644 --- a/arch/arm/vfp/vfp.h +++ b/arch/arm/vfp/vfp.h | |||
| @@ -377,6 +377,4 @@ struct op { | |||
| 377 | u32 flags; | 377 | u32 flags; |
| 378 | }; | 378 | }; |
| 379 | 379 | ||
| 380 | #if defined(CONFIG_SMP) || defined(CONFIG_PM) | ||
| 381 | extern void vfp_save_state(void *location, u32 fpexc); | 380 | extern void vfp_save_state(void *location, u32 fpexc); |
| 382 | #endif | ||
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index c92a08bd6a86..a5a4e57763c3 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S | |||
| @@ -172,7 +172,6 @@ process_exception: | |||
| 172 | @ retry the faulted instruction | 172 | @ retry the faulted instruction |
| 173 | ENDPROC(vfp_support_entry) | 173 | ENDPROC(vfp_support_entry) |
| 174 | 174 | ||
| 175 | #if defined(CONFIG_SMP) || defined(CONFIG_PM) | ||
| 176 | ENTRY(vfp_save_state) | 175 | ENTRY(vfp_save_state) |
| 177 | @ Save the current VFP state | 176 | @ Save the current VFP state |
| 178 | @ r0 - save location | 177 | @ r0 - save location |
| @@ -190,7 +189,6 @@ ENTRY(vfp_save_state) | |||
| 190 | stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 | 189 | stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 |
| 191 | mov pc, lr | 190 | mov pc, lr |
| 192 | ENDPROC(vfp_save_state) | 191 | ENDPROC(vfp_save_state) |
| 193 | #endif | ||
| 194 | 192 | ||
| 195 | last_VFP_context_address: | 193 | last_VFP_context_address: |
| 196 | .word last_VFP_context | 194 | .word last_VFP_context |
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 9f476a1be2ca..75457b30d813 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c | |||
| @@ -377,6 +377,55 @@ static void vfp_pm_init(void) | |||
| 377 | static inline void vfp_pm_init(void) { } | 377 | static inline void vfp_pm_init(void) { } |
| 378 | #endif /* CONFIG_PM */ | 378 | #endif /* CONFIG_PM */ |
| 379 | 379 | ||
| 380 | /* | ||
| 381 | * Synchronise the hardware VFP state of a thread other than current with the | ||
| 382 | * saved one. This function is used by the ptrace mechanism. | ||
| 383 | */ | ||
| 384 | #ifdef CONFIG_SMP | ||
| 385 | void vfp_sync_state(struct thread_info *thread) | ||
| 386 | { | ||
| 387 | /* | ||
| 388 | * On SMP systems, the VFP state is automatically saved at every | ||
| 389 | * context switch. We mark the thread VFP state as belonging to a | ||
| 390 | * non-existent CPU so that the saved one will be reloaded when | ||
| 391 | * needed. | ||
| 392 | */ | ||
| 393 | thread->vfpstate.hard.cpu = NR_CPUS; | ||
| 394 | } | ||
| 395 | #else | ||
| 396 | void vfp_sync_state(struct thread_info *thread) | ||
| 397 | { | ||
| 398 | unsigned int cpu = get_cpu(); | ||
| 399 | u32 fpexc = fmrx(FPEXC); | ||
| 400 | |||
| 401 | /* | ||
| 402 | * If VFP is enabled, the previous state was already saved and | ||
| 403 | * last_VFP_context updated. | ||
| 404 | */ | ||
| 405 | if (fpexc & FPEXC_EN) | ||
| 406 | goto out; | ||
| 407 | |||
| 408 | if (!last_VFP_context[cpu]) | ||
| 409 | goto out; | ||
| 410 | |||
| 411 | /* | ||
| 412 | * Save the last VFP state on this CPU. | ||
| 413 | */ | ||
| 414 | fmxr(FPEXC, fpexc | FPEXC_EN); | ||
| 415 | vfp_save_state(last_VFP_context[cpu], fpexc); | ||
| 416 | fmxr(FPEXC, fpexc); | ||
| 417 | |||
| 418 | /* | ||
| 419 | * Set the context to NULL to force a reload the next time the thread | ||
| 420 | * uses the VFP. | ||
| 421 | */ | ||
| 422 | last_VFP_context[cpu] = NULL; | ||
| 423 | |||
| 424 | out: | ||
| 425 | put_cpu(); | ||
| 426 | } | ||
| 427 | #endif | ||
| 428 | |||
| 380 | #include <linux/smp.h> | 429 | #include <linux/smp.h> |
| 381 | 430 | ||
| 382 | /* | 431 | /* |
| @@ -427,6 +476,18 @@ static int __init vfp_init(void) | |||
| 427 | * in place; report VFP support to userspace. | 476 | * in place; report VFP support to userspace. |
| 428 | */ | 477 | */ |
| 429 | elf_hwcap |= HWCAP_VFP; | 478 | elf_hwcap |= HWCAP_VFP; |
| 479 | #ifdef CONFIG_VFPv3 | ||
| 480 | if (VFP_arch >= 3) { | ||
| 481 | elf_hwcap |= HWCAP_VFPv3; | ||
| 482 | |||
| 483 | /* | ||
| 484 | * Check for VFPv3 D16. CPUs in this configuration | ||
| 485 | * only have 16 x 64bit registers. | ||
| 486 | */ | ||
| 487 | if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1) | ||
| 488 | elf_hwcap |= HWCAP_VFPv3D16; | ||
| 489 | } | ||
| 490 | #endif | ||
| 430 | #ifdef CONFIG_NEON | 491 | #ifdef CONFIG_NEON |
| 431 | /* | 492 | /* |
| 432 | * Check for the presence of the Advanced SIMD | 493 | * Check for the presence of the Advanced SIMD |
diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c index e7347db5b6c4..b663b7ffae4b 100644 --- a/drivers/ata/pata_icside.c +++ b/drivers/ata/pata_icside.c | |||
| @@ -45,8 +45,6 @@ static const struct portinfo pata_icside_portinfo_v6_2 = { | |||
| 45 | .stepping = 6, | 45 | .stepping = 6, |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | #define PATA_ICSIDE_MAX_SG 128 | ||
| 49 | |||
| 50 | struct pata_icside_state { | 48 | struct pata_icside_state { |
| 51 | void __iomem *irq_port; | 49 | void __iomem *irq_port; |
| 52 | void __iomem *ioc_base; | 50 | void __iomem *ioc_base; |
| @@ -57,7 +55,6 @@ struct pata_icside_state { | |||
| 57 | u8 disabled; | 55 | u8 disabled; |
| 58 | unsigned int speed[ATA_MAX_DEVICES]; | 56 | unsigned int speed[ATA_MAX_DEVICES]; |
| 59 | } port[2]; | 57 | } port[2]; |
| 60 | struct scatterlist sg[PATA_ICSIDE_MAX_SG]; | ||
| 61 | }; | 58 | }; |
| 62 | 59 | ||
| 63 | struct pata_icside_info { | 60 | struct pata_icside_info { |
| @@ -222,9 +219,7 @@ static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc) | |||
| 222 | { | 219 | { |
| 223 | struct ata_port *ap = qc->ap; | 220 | struct ata_port *ap = qc->ap; |
| 224 | struct pata_icside_state *state = ap->host->private_data; | 221 | struct pata_icside_state *state = ap->host->private_data; |
| 225 | struct scatterlist *sg, *rsg = state->sg; | ||
| 226 | unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; | 222 | unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; |
| 227 | unsigned int si; | ||
| 228 | 223 | ||
| 229 | /* | 224 | /* |
| 230 | * We are simplex; BUG if we try to fiddle with DMA | 225 | * We are simplex; BUG if we try to fiddle with DMA |
| @@ -233,20 +228,12 @@ static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc) | |||
| 233 | BUG_ON(dma_channel_active(state->dma)); | 228 | BUG_ON(dma_channel_active(state->dma)); |
| 234 | 229 | ||
| 235 | /* | 230 | /* |
| 236 | * Copy ATAs scattered sg list into a contiguous array of sg | ||
| 237 | */ | ||
| 238 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | ||
| 239 | memcpy(rsg, sg, sizeof(*sg)); | ||
| 240 | rsg++; | ||
| 241 | } | ||
| 242 | |||
| 243 | /* | ||
| 244 | * Route the DMA signals to the correct interface | 231 | * Route the DMA signals to the correct interface |
| 245 | */ | 232 | */ |
| 246 | writeb(state->port[ap->port_no].port_sel, state->ioc_base); | 233 | writeb(state->port[ap->port_no].port_sel, state->ioc_base); |
| 247 | 234 | ||
| 248 | set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); | 235 | set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); |
| 249 | set_dma_sg(state->dma, state->sg, rsg - state->sg); | 236 | set_dma_sg(state->dma, qc->sg, qc->n_elem); |
| 250 | set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); | 237 | set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); |
| 251 | 238 | ||
| 252 | /* issue r/w command */ | 239 | /* issue r/w command */ |
| @@ -306,8 +293,8 @@ static int icside_dma_init(struct pata_icside_info *info) | |||
| 306 | 293 | ||
| 307 | static struct scsi_host_template pata_icside_sht = { | 294 | static struct scsi_host_template pata_icside_sht = { |
| 308 | ATA_BASE_SHT(DRV_NAME), | 295 | ATA_BASE_SHT(DRV_NAME), |
| 309 | .sg_tablesize = PATA_ICSIDE_MAX_SG, | 296 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 310 | .dma_boundary = ~0, /* no dma boundaries */ | 297 | .dma_boundary = IOMD_DMA_BOUNDARY, |
| 311 | }; | 298 | }; |
| 312 | 299 | ||
| 313 | static void pata_icside_postreset(struct ata_link *link, unsigned int *classes) | 300 | static void pata_icside_postreset(struct ata_link *link, unsigned int *classes) |
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c index ba68a4671cb5..538313f9e7ac 100644 --- a/drivers/char/hw_random/omap-rng.c +++ b/drivers/char/hw_random/omap-rng.c | |||
| @@ -102,7 +102,7 @@ static int __init omap_rng_probe(struct platform_device *pdev) | |||
| 102 | return -EBUSY; | 102 | return -EBUSY; |
| 103 | 103 | ||
| 104 | if (cpu_is_omap24xx()) { | 104 | if (cpu_is_omap24xx()) { |
| 105 | rng_ick = clk_get(&pdev->dev, "rng_ick"); | 105 | rng_ick = clk_get(&pdev->dev, "ick"); |
| 106 | if (IS_ERR(rng_ick)) { | 106 | if (IS_ERR(rng_ick)) { |
| 107 | dev_err(&pdev->dev, "Could not get rng_ick\n"); | 107 | dev_err(&pdev->dev, "Could not get rng_ick\n"); |
| 108 | ret = PTR_ERR(rng_ick); | 108 | ret = PTR_ERR(rng_ick); |
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c index ae50a9d1a4e6..da781d107895 100644 --- a/drivers/dma/ipu/ipu_idmac.c +++ b/drivers/dma/ipu/ipu_idmac.c | |||
| @@ -1649,7 +1649,7 @@ static int ipu_probe(struct platform_device *pdev) | |||
| 1649 | } | 1649 | } |
| 1650 | 1650 | ||
| 1651 | /* Get IPU clock */ | 1651 | /* Get IPU clock */ |
| 1652 | ipu_data.ipu_clk = clk_get(&pdev->dev, "ipu_clk"); | 1652 | ipu_data.ipu_clk = clk_get(&pdev->dev, NULL); |
| 1653 | if (IS_ERR(ipu_data.ipu_clk)) { | 1653 | if (IS_ERR(ipu_data.ipu_clk)) { |
| 1654 | ret = PTR_ERR(ipu_data.ipu_clk); | 1654 | ret = PTR_ERR(ipu_data.ipu_clk); |
| 1655 | goto err_clk_get; | 1655 | goto err_clk_get; |
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c index 9aefb5e5864d..86796488ef4f 100644 --- a/drivers/i2c/busses/i2c-acorn.c +++ b/drivers/i2c/busses/i2c-acorn.c | |||
| @@ -15,9 +15,9 @@ | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/i2c.h> | 16 | #include <linux/i2c.h> |
| 17 | #include <linux/i2c-algo-bit.h> | 17 | #include <linux/i2c-algo-bit.h> |
| 18 | #include <linux/io.h> | ||
| 18 | 19 | ||
| 19 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
| 20 | #include <asm/io.h> | ||
| 21 | #include <asm/hardware/ioc.h> | 21 | #include <asm/hardware/ioc.h> |
| 22 | #include <asm/system.h> | 22 | #include <asm/system.h> |
| 23 | 23 | ||
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index be8ee2cac8bb..ece0125a1ee5 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c | |||
| @@ -193,22 +193,24 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |||
| 193 | 193 | ||
| 194 | static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) | 194 | static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) |
| 195 | { | 195 | { |
| 196 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | 196 | int ret; |
| 197 | dev->iclk = clk_get(dev->dev, "i2c_ick"); | 197 | |
| 198 | if (IS_ERR(dev->iclk)) { | 198 | dev->iclk = clk_get(dev->dev, "ick"); |
| 199 | dev->iclk = NULL; | 199 | if (IS_ERR(dev->iclk)) { |
| 200 | return -ENODEV; | 200 | ret = PTR_ERR(dev->iclk); |
| 201 | } | 201 | dev->iclk = NULL; |
| 202 | return ret; | ||
| 202 | } | 203 | } |
| 203 | 204 | ||
| 204 | dev->fclk = clk_get(dev->dev, "i2c_fck"); | 205 | dev->fclk = clk_get(dev->dev, "fck"); |
| 205 | if (IS_ERR(dev->fclk)) { | 206 | if (IS_ERR(dev->fclk)) { |
| 207 | ret = PTR_ERR(dev->fclk); | ||
| 206 | if (dev->iclk != NULL) { | 208 | if (dev->iclk != NULL) { |
| 207 | clk_put(dev->iclk); | 209 | clk_put(dev->iclk); |
| 208 | dev->iclk = NULL; | 210 | dev->iclk = NULL; |
| 209 | } | 211 | } |
| 210 | dev->fclk = NULL; | 212 | dev->fclk = NULL; |
| 211 | return -ENODEV; | 213 | return ret; |
| 212 | } | 214 | } |
| 213 | 215 | ||
| 214 | return 0; | 216 | return 0; |
| @@ -218,18 +220,15 @@ static void omap_i2c_put_clocks(struct omap_i2c_dev *dev) | |||
| 218 | { | 220 | { |
| 219 | clk_put(dev->fclk); | 221 | clk_put(dev->fclk); |
| 220 | dev->fclk = NULL; | 222 | dev->fclk = NULL; |
| 221 | if (dev->iclk != NULL) { | 223 | clk_put(dev->iclk); |
| 222 | clk_put(dev->iclk); | 224 | dev->iclk = NULL; |
| 223 | dev->iclk = NULL; | ||
| 224 | } | ||
| 225 | } | 225 | } |
| 226 | 226 | ||
| 227 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) | 227 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) |
| 228 | { | 228 | { |
| 229 | WARN_ON(!dev->idle); | 229 | WARN_ON(!dev->idle); |
| 230 | 230 | ||
| 231 | if (dev->iclk != NULL) | 231 | clk_enable(dev->iclk); |
| 232 | clk_enable(dev->iclk); | ||
| 233 | clk_enable(dev->fclk); | 232 | clk_enable(dev->fclk); |
| 234 | dev->idle = 0; | 233 | dev->idle = 0; |
| 235 | if (dev->iestate) | 234 | if (dev->iestate) |
| @@ -254,8 +253,7 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev) | |||
| 254 | } | 253 | } |
| 255 | dev->idle = 1; | 254 | dev->idle = 1; |
| 256 | clk_disable(dev->fclk); | 255 | clk_disable(dev->fclk); |
| 257 | if (dev->iclk != NULL) | 256 | clk_disable(dev->iclk); |
| 258 | clk_disable(dev->iclk); | ||
| 259 | } | 257 | } |
| 260 | 258 | ||
| 261 | static int omap_i2c_init(struct omap_i2c_dev *dev) | 259 | static int omap_i2c_init(struct omap_i2c_dev *dev) |
| @@ -312,15 +310,14 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) | |||
| 312 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | 310 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
| 313 | 311 | ||
| 314 | if (cpu_class_is_omap1()) { | 312 | if (cpu_class_is_omap1()) { |
| 315 | struct clk *armxor_ck; | 313 | /* |
| 316 | 314 | * The I2C functional clock is the armxor_ck, so there's | |
| 317 | armxor_ck = clk_get(NULL, "armxor_ck"); | 315 | * no need to get "armxor_ck" separately. Now, if OMAP2420 |
| 318 | if (IS_ERR(armxor_ck)) | 316 | * always returns 12MHz for the functional clock, we can |
| 319 | dev_warn(dev->dev, "Could not get armxor_ck\n"); | 317 | * do this bit unconditionally. |
| 320 | else { | 318 | */ |
| 321 | fclk_rate = clk_get_rate(armxor_ck); | 319 | fclk_rate = clk_get_rate(dev->fclk); |
| 322 | clk_put(armxor_ck); | 320 | |
| 323 | } | ||
| 324 | /* TRM for 5912 says the I2C clock must be prescaled to be | 321 | /* TRM for 5912 says the I2C clock must be prescaled to be |
| 325 | * between 7 - 12 MHz. The XOR input clock is typically | 322 | * between 7 - 12 MHz. The XOR input clock is typically |
| 326 | * 12, 13 or 19.2 MHz. So we should have code that produces: | 323 | * 12, 13 or 19.2 MHz. So we should have code that produces: |
diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index 4678babd3ce6..fede619ba227 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c | |||
| @@ -102,7 +102,13 @@ static int i2c_versatile_probe(struct platform_device *dev) | |||
| 102 | i2c->algo = i2c_versatile_algo; | 102 | i2c->algo = i2c_versatile_algo; |
| 103 | i2c->algo.data = i2c; | 103 | i2c->algo.data = i2c; |
| 104 | 104 | ||
| 105 | ret = i2c_bit_add_bus(&i2c->adap); | 105 | if (dev->id >= 0) { |
| 106 | /* static bus numbering */ | ||
| 107 | i2c->adap.nr = dev->id; | ||
| 108 | ret = i2c_bit_add_numbered_bus(&i2c->adap); | ||
| 109 | } else | ||
| 110 | /* dynamic bus numbering */ | ||
| 111 | ret = i2c_bit_add_bus(&i2c->adap); | ||
| 106 | if (ret >= 0) { | 112 | if (ret >= 0) { |
| 107 | platform_set_drvdata(dev, i2c); | 113 | platform_set_drvdata(dev, i2c); |
| 108 | return 0; | 114 | return 0; |
| @@ -146,7 +152,7 @@ static void __exit i2c_versatile_exit(void) | |||
| 146 | platform_driver_unregister(&i2c_versatile_driver); | 152 | platform_driver_unregister(&i2c_versatile_driver); |
| 147 | } | 153 | } |
| 148 | 154 | ||
| 149 | module_init(i2c_versatile_init); | 155 | subsys_initcall(i2c_versatile_init); |
| 150 | module_exit(i2c_versatile_exit); | 156 | module_exit(i2c_versatile_exit); |
| 151 | 157 | ||
| 152 | MODULE_DESCRIPTION("ARM Versatile I2C bus driver"); | 158 | MODULE_DESCRIPTION("ARM Versatile I2C bus driver"); |
diff --git a/drivers/input/keyboard/corgikbd.c b/drivers/input/keyboard/corgikbd.c index abb04c82c622..634af6a8e6b3 100644 --- a/drivers/input/keyboard/corgikbd.c +++ b/drivers/input/keyboard/corgikbd.c | |||
| @@ -21,8 +21,6 @@ | |||
| 21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
| 22 | 22 | ||
| 23 | #include <mach/corgi.h> | 23 | #include <mach/corgi.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/pxa2xx-gpio.h> | 24 | #include <mach/pxa2xx-gpio.h> |
| 27 | #include <asm/hardware/scoop.h> | 25 | #include <asm/hardware/scoop.h> |
| 28 | 26 | ||
diff --git a/drivers/input/keyboard/spitzkbd.c b/drivers/input/keyboard/spitzkbd.c index 9d1781a618e9..13967422658c 100644 --- a/drivers/input/keyboard/spitzkbd.c +++ b/drivers/input/keyboard/spitzkbd.c | |||
| @@ -21,8 +21,6 @@ | |||
| 21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
| 22 | 22 | ||
| 23 | #include <mach/spitz.h> | 23 | #include <mach/spitz.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/pxa2xx-gpio.h> | 24 | #include <mach/pxa2xx-gpio.h> |
| 27 | 25 | ||
| 28 | #define KB_ROWS 7 | 26 | #define KB_ROWS 7 |
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c index 56c079ef5018..272deddc8db6 100644 --- a/drivers/input/mouse/rpcmouse.c +++ b/drivers/input/mouse/rpcmouse.c | |||
| @@ -22,10 +22,10 @@ | |||
| 22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/input.h> | 24 | #include <linux/input.h> |
| 25 | #include <linux/io.h> | ||
| 25 | 26 | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
| 28 | #include <asm/io.h> | ||
| 29 | #include <asm/hardware/iomd.h> | 29 | #include <asm/hardware/iomd.h> |
| 30 | 30 | ||
| 31 | MODULE_AUTHOR("Vojtech Pavlik, Russell King"); | 31 | MODULE_AUTHOR("Vojtech Pavlik, Russell King"); |
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c index 7f36edd34f8b..ed045c99f84b 100644 --- a/drivers/input/serio/rpckbd.c +++ b/drivers/input/serio/rpckbd.c | |||
| @@ -33,10 +33,10 @@ | |||
| 33 | #include <linux/serio.h> | 33 | #include <linux/serio.h> |
| 34 | #include <linux/err.h> | 34 | #include <linux/err.h> |
| 35 | #include <linux/platform_device.h> | 35 | #include <linux/platform_device.h> |
| 36 | #include <linux/io.h> | ||
| 36 | 37 | ||
| 37 | #include <asm/irq.h> | 38 | #include <asm/irq.h> |
| 38 | #include <mach/hardware.h> | 39 | #include <mach/hardware.h> |
| 39 | #include <asm/io.h> | ||
| 40 | #include <asm/hardware/iomd.h> | 40 | #include <asm/hardware/iomd.h> |
| 41 | #include <asm/system.h> | 41 | #include <asm/system.h> |
| 42 | 42 | ||
diff --git a/drivers/input/touchscreen/corgi_ts.c b/drivers/input/touchscreen/corgi_ts.c index 3fb51b54fe61..94a1919d439d 100644 --- a/drivers/input/touchscreen/corgi_ts.c +++ b/drivers/input/touchscreen/corgi_ts.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | 21 | ||
| 22 | #include <mach/sharpsl.h> | 22 | #include <mach/sharpsl.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/pxa-regs.h> | ||
| 25 | #include <mach/pxa2xx-gpio.h> | 24 | #include <mach/pxa2xx-gpio.h> |
| 26 | 25 | ||
| 27 | 26 | ||
diff --git a/drivers/media/video/omap24xxcam.c b/drivers/media/video/omap24xxcam.c index 73eb656acfe3..805faaea6449 100644 --- a/drivers/media/video/omap24xxcam.c +++ b/drivers/media/video/omap24xxcam.c | |||
| @@ -80,17 +80,17 @@ static int omap24xxcam_clock_get(struct omap24xxcam_device *cam) | |||
| 80 | { | 80 | { |
| 81 | int rval = 0; | 81 | int rval = 0; |
| 82 | 82 | ||
| 83 | cam->fck = clk_get(cam->dev, "cam_fck"); | 83 | cam->fck = clk_get(cam->dev, "fck"); |
| 84 | if (IS_ERR(cam->fck)) { | 84 | if (IS_ERR(cam->fck)) { |
| 85 | dev_err(cam->dev, "can't get cam_fck"); | 85 | dev_err(cam->dev, "can't get camera fck"); |
| 86 | rval = PTR_ERR(cam->fck); | 86 | rval = PTR_ERR(cam->fck); |
| 87 | omap24xxcam_clock_put(cam); | 87 | omap24xxcam_clock_put(cam); |
| 88 | return rval; | 88 | return rval; |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | cam->ick = clk_get(cam->dev, "cam_ick"); | 91 | cam->ick = clk_get(cam->dev, "ick"); |
| 92 | if (IS_ERR(cam->ick)) { | 92 | if (IS_ERR(cam->ick)) { |
| 93 | dev_err(cam->dev, "can't get cam_ick"); | 93 | dev_err(cam->dev, "can't get camera ick"); |
| 94 | rval = PTR_ERR(cam->ick); | 94 | rval = PTR_ERR(cam->ick); |
| 95 | omap24xxcam_clock_put(cam); | 95 | omap24xxcam_clock_put(cam); |
| 96 | } | 96 | } |
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index 07c334f25aae..0c4ce58c53d5 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | #include <linux/videodev2.h> | 35 | #include <linux/videodev2.h> |
| 36 | 36 | ||
| 37 | #include <mach/dma.h> | 37 | #include <mach/dma.h> |
| 38 | #include <mach/pxa-regs.h> | ||
| 39 | #include <mach/camera.h> | 38 | #include <mach/camera.h> |
| 40 | 39 | ||
| 41 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | 40 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) |
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 2909bbc8ad00..a663429b3d55 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c | |||
| @@ -490,7 +490,7 @@ static void mmci_check_status(unsigned long data) | |||
| 490 | mod_timer(&host->timer, jiffies + HZ); | 490 | mod_timer(&host->timer, jiffies + HZ); |
| 491 | } | 491 | } |
| 492 | 492 | ||
| 493 | static int mmci_probe(struct amba_device *dev, void *id) | 493 | static int __devinit mmci_probe(struct amba_device *dev, void *id) |
| 494 | { | 494 | { |
| 495 | struct mmc_platform_data *plat = dev->dev.platform_data; | 495 | struct mmc_platform_data *plat = dev->dev.platform_data; |
| 496 | struct mmci_host *host; | 496 | struct mmci_host *host; |
| @@ -633,7 +633,7 @@ static int mmci_probe(struct amba_device *dev, void *id) | |||
| 633 | return ret; | 633 | return ret; |
| 634 | } | 634 | } |
| 635 | 635 | ||
| 636 | static int mmci_remove(struct amba_device *dev) | 636 | static int __devexit mmci_remove(struct amba_device *dev) |
| 637 | { | 637 | { |
| 638 | struct mmc_host *mmc = amba_get_drvdata(dev); | 638 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 639 | 639 | ||
| @@ -730,7 +730,7 @@ static struct amba_driver mmci_driver = { | |||
| 730 | .name = DRIVER_NAME, | 730 | .name = DRIVER_NAME, |
| 731 | }, | 731 | }, |
| 732 | .probe = mmci_probe, | 732 | .probe = mmci_probe, |
| 733 | .remove = mmci_remove, | 733 | .remove = __devexit_p(mmci_remove), |
| 734 | .suspend = mmci_suspend, | 734 | .suspend = mmci_suspend, |
| 735 | .resume = mmci_resume, | 735 | .resume = mmci_resume, |
| 736 | .id_table = mmci_ids, | 736 | .id_table = mmci_ids, |
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index dda0be4e25dc..b4a615c55f28 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c | |||
| @@ -42,7 +42,7 @@ | |||
| 42 | #define HAS_DMA | 42 | #define HAS_DMA |
| 43 | #endif | 43 | #endif |
| 44 | 44 | ||
| 45 | #define DRIVER_NAME "imx-mmc" | 45 | #define DRIVER_NAME "mxc-mmc" |
| 46 | 46 | ||
| 47 | #define MMC_REG_STR_STP_CLK 0x00 | 47 | #define MMC_REG_STR_STP_CLK 0x00 |
| 48 | #define MMC_REG_STATUS 0x04 | 48 | #define MMC_REG_STATUS 0x04 |
| @@ -707,7 +707,7 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
| 707 | host->res = r; | 707 | host->res = r; |
| 708 | host->irq = irq; | 708 | host->irq = irq; |
| 709 | 709 | ||
| 710 | host->clk = clk_get(&pdev->dev, "sdhc_clk"); | 710 | host->clk = clk_get(&pdev->dev, NULL); |
| 711 | if (IS_ERR(host->clk)) { | 711 | if (IS_ERR(host->clk)) { |
| 712 | ret = PTR_ERR(host->clk); | 712 | ret = PTR_ERR(host->clk); |
| 713 | goto out_iounmap; | 713 | goto out_iounmap; |
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index 67d7b7fef084..5570849188cc 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c | |||
| @@ -1460,18 +1460,12 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
| 1460 | if (!host->virt_base) | 1460 | if (!host->virt_base) |
| 1461 | goto err_ioremap; | 1461 | goto err_ioremap; |
| 1462 | 1462 | ||
| 1463 | if (cpu_is_omap24xx()) { | 1463 | host->iclk = clk_get(&pdev->dev, "ick"); |
| 1464 | host->iclk = clk_get(&pdev->dev, "mmc_ick"); | 1464 | if (IS_ERR(host->iclk)) |
| 1465 | if (IS_ERR(host->iclk)) | 1465 | goto err_free_mmc_host; |
| 1466 | goto err_free_mmc_host; | 1466 | clk_enable(host->iclk); |
| 1467 | clk_enable(host->iclk); | ||
| 1468 | } | ||
| 1469 | |||
| 1470 | if (!cpu_is_omap24xx()) | ||
| 1471 | host->fclk = clk_get(&pdev->dev, "mmc_ck"); | ||
| 1472 | else | ||
| 1473 | host->fclk = clk_get(&pdev->dev, "mmc_fck"); | ||
| 1474 | 1467 | ||
| 1468 | host->fclk = clk_get(&pdev->dev, "fck"); | ||
| 1475 | if (IS_ERR(host->fclk)) { | 1469 | if (IS_ERR(host->fclk)) { |
| 1476 | ret = PTR_ERR(host->fclk); | 1470 | ret = PTR_ERR(host->fclk); |
| 1477 | goto err_free_iclk; | 1471 | goto err_free_iclk; |
| @@ -1536,10 +1530,10 @@ static int mmc_omap_remove(struct platform_device *pdev) | |||
| 1536 | if (host->pdata->cleanup) | 1530 | if (host->pdata->cleanup) |
| 1537 | host->pdata->cleanup(&pdev->dev); | 1531 | host->pdata->cleanup(&pdev->dev); |
| 1538 | 1532 | ||
| 1539 | if (host->iclk && !IS_ERR(host->iclk)) | 1533 | mmc_omap_fclk_enable(host, 0); |
| 1540 | clk_put(host->iclk); | 1534 | clk_put(host->fclk); |
| 1541 | if (host->fclk && !IS_ERR(host->fclk)) | 1535 | clk_disable(host->iclk); |
| 1542 | clk_put(host->fclk); | 1536 | clk_put(host->iclk); |
| 1543 | 1537 | ||
| 1544 | iounmap(host->virt_base); | 1538 | iounmap(host->virt_base); |
| 1545 | release_mem_region(pdev->resource[0].start, | 1539 | release_mem_region(pdev->resource[0].start, |
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index a631c81dce12..3916a5618e28 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c | |||
| @@ -956,13 +956,13 @@ static int __init omap_mmc_probe(struct platform_device *pdev) | |||
| 956 | 956 | ||
| 957 | sema_init(&host->sem, 1); | 957 | sema_init(&host->sem, 1); |
| 958 | 958 | ||
| 959 | host->iclk = clk_get(&pdev->dev, "mmchs_ick"); | 959 | host->iclk = clk_get(&pdev->dev, "ick"); |
| 960 | if (IS_ERR(host->iclk)) { | 960 | if (IS_ERR(host->iclk)) { |
| 961 | ret = PTR_ERR(host->iclk); | 961 | ret = PTR_ERR(host->iclk); |
| 962 | host->iclk = NULL; | 962 | host->iclk = NULL; |
| 963 | goto err1; | 963 | goto err1; |
| 964 | } | 964 | } |
| 965 | host->fclk = clk_get(&pdev->dev, "mmchs_fck"); | 965 | host->fclk = clk_get(&pdev->dev, "fck"); |
| 966 | if (IS_ERR(host->fclk)) { | 966 | if (IS_ERR(host->fclk)) { |
| 967 | ret = PTR_ERR(host->fclk); | 967 | ret = PTR_ERR(host->fclk); |
| 968 | host->fclk = NULL; | 968 | host->fclk = NULL; |
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index 9702ad3774cf..430095725f9f 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c | |||
| @@ -30,9 +30,8 @@ | |||
| 30 | 30 | ||
| 31 | #include <asm/sizes.h> | 31 | #include <asm/sizes.h> |
| 32 | 32 | ||
| 33 | #include <mach/dma.h> | ||
| 34 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 35 | #include <mach/pxa-regs.h> | 34 | #include <mach/dma.h> |
| 36 | #include <mach/mmc.h> | 35 | #include <mach/mmc.h> |
| 37 | 36 | ||
| 38 | #include "pxamci.h" | 37 | #include "pxamci.h" |
diff --git a/drivers/mtd/maps/integrator-flash.c b/drivers/mtd/maps/integrator-flash.c index d2ec262666c7..c9681a339a59 100644 --- a/drivers/mtd/maps/integrator-flash.c +++ b/drivers/mtd/maps/integrator-flash.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #include <linux/ioport.h> | 31 | #include <linux/ioport.h> |
| 32 | #include <linux/platform_device.h> | 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/init.h> | 33 | #include <linux/init.h> |
| 34 | #include <linux/io.h> | ||
| 34 | 35 | ||
| 35 | #include <linux/mtd/mtd.h> | 36 | #include <linux/mtd/mtd.h> |
| 36 | #include <linux/mtd/map.h> | 37 | #include <linux/mtd/map.h> |
| @@ -38,7 +39,6 @@ | |||
| 38 | 39 | ||
| 39 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 40 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
| 41 | #include <asm/io.h> | ||
| 42 | #include <asm/system.h> | 42 | #include <asm/system.h> |
| 43 | 43 | ||
| 44 | #ifdef CONFIG_ARCH_P720T | 44 | #ifdef CONFIG_ARCH_P720T |
diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c index 6f6a0f6dafd6..8f57b6f40aa2 100644 --- a/drivers/mtd/maps/sa1100-flash.c +++ b/drivers/mtd/maps/sa1100-flash.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <linux/slab.h> | 12 | #include <linux/slab.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> | ||
| 15 | 16 | ||
| 16 | #include <linux/mtd/mtd.h> | 17 | #include <linux/mtd/mtd.h> |
| 17 | #include <linux/mtd/map.h> | 18 | #include <linux/mtd/map.h> |
| @@ -19,7 +20,6 @@ | |||
| 19 | #include <linux/mtd/concat.h> | 20 | #include <linux/mtd/concat.h> |
| 20 | 21 | ||
| 21 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 22 | #include <asm/io.h> | ||
| 23 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
| 24 | #include <asm/mach/flash.h> | 24 | #include <asm/mach/flash.h> |
| 25 | 25 | ||
diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c index fa129c09bca8..10081e656a6f 100644 --- a/drivers/mtd/nand/cmx270_nand.c +++ b/drivers/mtd/nand/cmx270_nand.c | |||
| @@ -26,8 +26,7 @@ | |||
| 26 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
| 27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 28 | 28 | ||
| 29 | #include <mach/hardware.h> | 29 | #include <mach/pxa2xx-regs.h> |
| 30 | #include <mach/pxa-regs.h> | ||
| 31 | 30 | ||
| 32 | #define GPIO_NAND_CS (11) | 31 | #define GPIO_NAND_CS (11) |
| 33 | #define GPIO_NAND_RB (89) | 32 | #define GPIO_NAND_RB (89) |
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 21fd4f1c4806..bad048aca89a 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c | |||
| @@ -880,7 +880,7 @@ static int __init mxcnd_probe(struct platform_device *pdev) | |||
| 880 | this->read_buf = mxc_nand_read_buf; | 880 | this->read_buf = mxc_nand_read_buf; |
| 881 | this->verify_buf = mxc_nand_verify_buf; | 881 | this->verify_buf = mxc_nand_verify_buf; |
| 882 | 882 | ||
| 883 | host->clk = clk_get(&pdev->dev, "nfc_clk"); | 883 | host->clk = clk_get(&pdev->dev, "nfc"); |
| 884 | if (IS_ERR(host->clk)) | 884 | if (IS_ERR(host->clk)) |
| 885 | goto eclk; | 885 | goto eclk; |
| 886 | 886 | ||
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index cc55cbc2b308..61b69cc40009 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
| 23 | 23 | ||
| 24 | #include <mach/dma.h> | 24 | #include <mach/dma.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/pxa3xx_nand.h> | 25 | #include <mach/pxa3xx_nand.h> |
| 27 | 26 | ||
| 28 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | 27 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) |
diff --git a/drivers/net/arm/am79c961a.c b/drivers/net/arm/am79c961a.c index c2d012fcc29b..4bc6901b3819 100644 --- a/drivers/net/arm/am79c961a.c +++ b/drivers/net/arm/am79c961a.c | |||
| @@ -27,9 +27,9 @@ | |||
| 27 | #include <linux/crc32.h> | 27 | #include <linux/crc32.h> |
| 28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 29 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/io.h> | ||
| 30 | 31 | ||
| 31 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 32 | #include <asm/io.h> | ||
| 33 | #include <asm/system.h> | 33 | #include <asm/system.h> |
| 34 | 34 | ||
| 35 | #define TX_BUFFERS 15 | 35 | #define TX_BUFFERS 15 |
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c index 5fe17d5eaa54..448487e22fa3 100644 --- a/drivers/net/arm/ixp4xx_eth.c +++ b/drivers/net/arm/ixp4xx_eth.c | |||
| @@ -335,11 +335,20 @@ static int ixp4xx_mdio_register(void) | |||
| 335 | if (!(mdio_bus = mdiobus_alloc())) | 335 | if (!(mdio_bus = mdiobus_alloc())) |
| 336 | return -ENOMEM; | 336 | return -ENOMEM; |
| 337 | 337 | ||
| 338 | /* All MII PHY accesses use NPE-B Ethernet registers */ | 338 | if (cpu_is_ixp43x()) { |
| 339 | spin_lock_init(&mdio_lock); | 339 | /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */ |
| 340 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; | 340 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH)) |
| 341 | __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); | 341 | return -ENOSYS; |
| 342 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; | ||
| 343 | } else { | ||
| 344 | /* All MII PHY accesses use NPE-B Ethernet registers */ | ||
| 345 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) | ||
| 346 | return -ENOSYS; | ||
| 347 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; | ||
| 348 | } | ||
| 342 | 349 | ||
| 350 | __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); | ||
| 351 | spin_lock_init(&mdio_lock); | ||
| 343 | mdio_bus->name = "IXP4xx MII Bus"; | 352 | mdio_bus->name = "IXP4xx MII Bus"; |
| 344 | mdio_bus->read = &ixp4xx_mdio_read; | 353 | mdio_bus->read = &ixp4xx_mdio_read; |
| 345 | mdio_bus->write = &ixp4xx_mdio_write; | 354 | mdio_bus->write = &ixp4xx_mdio_write; |
| @@ -1250,9 +1259,6 @@ static struct platform_driver ixp4xx_eth_driver = { | |||
| 1250 | static int __init eth_init_module(void) | 1259 | static int __init eth_init_module(void) |
| 1251 | { | 1260 | { |
| 1252 | int err; | 1261 | int err; |
| 1253 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) | ||
| 1254 | return -ENOSYS; | ||
| 1255 | |||
| 1256 | if ((err = ixp4xx_mdio_register())) | 1262 | if ((err = ixp4xx_mdio_register())) |
| 1257 | return err; | 1263 | return err; |
| 1258 | return platform_driver_register(&ixp4xx_eth_driver); | 1264 | return platform_driver_register(&ixp4xx_eth_driver); |
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index 31794c2363ec..e775338b525f 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c | |||
| @@ -24,9 +24,8 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/dma.h> | 25 | #include <mach/dma.h> |
| 26 | #include <mach/irda.h> | 26 | #include <mach/irda.h> |
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/pxa-regs.h> | ||
| 29 | #include <mach/regs-uart.h> | 27 | #include <mach/regs-uart.h> |
| 28 | #include <mach/regs-ost.h> | ||
| 30 | 29 | ||
| 31 | #define FICP __REG(0x40800000) /* Start of FICP area */ | 30 | #define FICP __REG(0x40800000) /* Start of FICP area */ |
| 32 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ | 31 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ |
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index a45952e72018..8140f7cb4d85 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h | |||
| @@ -236,8 +236,7 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg, | |||
| 236 | * Use a DMA for RX and TX packets. | 236 | * Use a DMA for RX and TX packets. |
| 237 | */ | 237 | */ |
| 238 | #include <linux/dma-mapping.h> | 238 | #include <linux/dma-mapping.h> |
| 239 | #include <asm/dma.h> | 239 | #include <mach/dma.h> |
| 240 | #include <mach/pxa-regs.h> | ||
| 241 | 240 | ||
| 242 | static dma_addr_t rx_dmabuf, tx_dmabuf; | 241 | static dma_addr_t rx_dmabuf, tx_dmabuf; |
| 243 | static int rx_dmalen, tx_dmalen; | 242 | static int rx_dmalen, tx_dmalen; |
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index ed9ae43523a1..6c44f86ae3fd 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | defined(CONFIG_MACH_MAINSTONE) ||\ | 44 | defined(CONFIG_MACH_MAINSTONE) ||\ |
| 45 | defined(CONFIG_MACH_ZYLONITE) ||\ | 45 | defined(CONFIG_MACH_ZYLONITE) ||\ |
| 46 | defined(CONFIG_MACH_LITTLETON) ||\ | 46 | defined(CONFIG_MACH_LITTLETON) ||\ |
| 47 | defined(CONFIG_MACH_ZYLONITE2) ||\ | ||
| 47 | defined(CONFIG_ARCH_VIPER) | 48 | defined(CONFIG_ARCH_VIPER) |
| 48 | 49 | ||
| 49 | #include <asm/mach-types.h> | 50 | #include <asm/mach-types.h> |
| @@ -494,8 +495,6 @@ struct smc_local { | |||
| 494 | */ | 495 | */ |
| 495 | #include <linux/dma-mapping.h> | 496 | #include <linux/dma-mapping.h> |
| 496 | #include <mach/dma.h> | 497 | #include <mach/dma.h> |
| 497 | #include <mach/hardware.h> | ||
| 498 | #include <mach/pxa-regs.h> | ||
| 499 | 498 | ||
| 500 | #ifdef SMC_insl | 499 | #ifdef SMC_insl |
| 501 | #undef SMC_insl | 500 | #undef SMC_insl |
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c index bb9ddb9532e3..c49a7269f6d1 100644 --- a/drivers/pcmcia/pxa2xx_base.c +++ b/drivers/pcmcia/pxa2xx_base.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/io.h> | 28 | #include <asm/io.h> |
| 29 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
| 30 | #include <asm/system.h> | 30 | #include <asm/system.h> |
| 31 | #include <mach/pxa-regs.h> | ||
| 32 | #include <mach/pxa2xx-regs.h> | 31 | #include <mach/pxa2xx-regs.h> |
| 33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 34 | 33 | ||
| @@ -39,6 +38,44 @@ | |||
| 39 | #include "soc_common.h" | 38 | #include "soc_common.h" |
| 40 | #include "pxa2xx_base.h" | 39 | #include "pxa2xx_base.h" |
| 41 | 40 | ||
| 41 | /* | ||
| 42 | * Personal Computer Memory Card International Association (PCMCIA) sockets | ||
| 43 | */ | ||
| 44 | |||
| 45 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | ||
| 46 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | ||
| 47 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | ||
| 48 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | ||
| 49 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | ||
| 50 | |||
| 51 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | ||
| 52 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | ||
| 53 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | ||
| 54 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | ||
| 55 | |||
| 56 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | ||
| 57 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | ||
| 58 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | ||
| 59 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | ||
| 60 | |||
| 61 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 62 | (0x20000000 + (Nb) * PCMCIASp) | ||
| 63 | #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */ | ||
| 64 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | ||
| 65 | (_PCMCIA(Nb) + 2 * PCMCIAPrtSp) | ||
| 66 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | ||
| 67 | (_PCMCIA(Nb) + 3 * PCMCIAPrtSp) | ||
| 68 | |||
| 69 | #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */ | ||
| 70 | #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */ | ||
| 71 | #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */ | ||
| 72 | #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */ | ||
| 73 | |||
| 74 | #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */ | ||
| 75 | #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */ | ||
| 76 | #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */ | ||
| 77 | #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */ | ||
| 78 | |||
| 42 | 79 | ||
| 43 | #define MCXX_SETUP_MASK (0x7f) | 80 | #define MCXX_SETUP_MASK (0x7f) |
| 44 | #define MCXX_ASST_MASK (0x1f) | 81 | #define MCXX_ASST_MASK (0x1f) |
| @@ -177,29 +214,73 @@ static void pxa2xx_configure_sockets(struct device *dev) | |||
| 177 | MECR |= MECR_CIT; | 214 | MECR |= MECR_CIT; |
| 178 | 215 | ||
| 179 | /* Set MECR:NOS (Number Of Sockets) */ | 216 | /* Set MECR:NOS (Number Of Sockets) */ |
| 180 | if (ops->nr > 1 || machine_is_viper()) | 217 | if ((ops->first + ops->nr) > 1 || machine_is_viper()) |
| 181 | MECR |= MECR_NOS; | 218 | MECR |= MECR_NOS; |
| 182 | else | 219 | else |
| 183 | MECR &= ~MECR_NOS; | 220 | MECR &= ~MECR_NOS; |
| 184 | } | 221 | } |
| 185 | 222 | ||
| 223 | static const char *skt_names[] = { | ||
| 224 | "PCMCIA socket 0", | ||
| 225 | "PCMCIA socket 1", | ||
| 226 | }; | ||
| 227 | |||
| 228 | #define SKT_DEV_INFO_SIZE(n) \ | ||
| 229 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | ||
| 230 | |||
| 186 | int __pxa2xx_drv_pcmcia_probe(struct device *dev) | 231 | int __pxa2xx_drv_pcmcia_probe(struct device *dev) |
| 187 | { | 232 | { |
| 188 | int ret; | 233 | int i, ret; |
| 189 | struct pcmcia_low_level *ops; | 234 | struct pcmcia_low_level *ops; |
| 235 | struct skt_dev_info *sinfo; | ||
| 236 | struct soc_pcmcia_socket *skt; | ||
| 190 | 237 | ||
| 191 | if (!dev || !dev->platform_data) | 238 | if (!dev || !dev->platform_data) |
| 192 | return -ENODEV; | 239 | return -ENODEV; |
| 193 | 240 | ||
| 194 | ops = (struct pcmcia_low_level *)dev->platform_data; | 241 | ops = (struct pcmcia_low_level *)dev->platform_data; |
| 195 | 242 | ||
| 243 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); | ||
| 244 | if (!sinfo) | ||
| 245 | return -ENOMEM; | ||
| 246 | |||
| 247 | sinfo->nskt = ops->nr; | ||
| 248 | |||
| 249 | /* Initialize processor specific parameters */ | ||
| 250 | for (i = 0; i < ops->nr; i++) { | ||
| 251 | skt = &sinfo->skt[i]; | ||
| 252 | |||
| 253 | skt->nr = ops->first + i; | ||
| 254 | skt->irq = NO_IRQ; | ||
| 255 | |||
| 256 | skt->res_skt.start = _PCMCIA(skt->nr); | ||
| 257 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | ||
| 258 | skt->res_skt.name = skt_names[skt->nr]; | ||
| 259 | skt->res_skt.flags = IORESOURCE_MEM; | ||
| 260 | |||
| 261 | skt->res_io.start = _PCMCIAIO(skt->nr); | ||
| 262 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | ||
| 263 | skt->res_io.name = "io"; | ||
| 264 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
| 265 | |||
| 266 | skt->res_mem.start = _PCMCIAMem(skt->nr); | ||
| 267 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | ||
| 268 | skt->res_mem.name = "memory"; | ||
| 269 | skt->res_mem.flags = IORESOURCE_MEM; | ||
| 270 | |||
| 271 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | ||
| 272 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | ||
| 273 | skt->res_attr.name = "attribute"; | ||
| 274 | skt->res_attr.flags = IORESOURCE_MEM; | ||
| 275 | } | ||
| 276 | |||
| 196 | /* Provide our PXA2xx specific timing routines. */ | 277 | /* Provide our PXA2xx specific timing routines. */ |
| 197 | ops->set_timing = pxa2xx_pcmcia_set_timing; | 278 | ops->set_timing = pxa2xx_pcmcia_set_timing; |
| 198 | #ifdef CONFIG_CPU_FREQ | 279 | #ifdef CONFIG_CPU_FREQ |
| 199 | ops->frequency_change = pxa2xx_pcmcia_frequency_change; | 280 | ops->frequency_change = pxa2xx_pcmcia_frequency_change; |
| 200 | #endif | 281 | #endif |
| 201 | 282 | ||
| 202 | ret = soc_common_drv_pcmcia_probe(dev, ops, ops->first, ops->nr); | 283 | ret = soc_common_drv_pcmcia_probe(dev, ops, sinfo); |
| 203 | 284 | ||
| 204 | if (!ret) | 285 | if (!ret) |
| 205 | pxa2xx_configure_sockets(dev); | 286 | pxa2xx_configure_sockets(dev); |
diff --git a/drivers/pcmcia/pxa2xx_cm_x255.c b/drivers/pcmcia/pxa2xx_cm_x255.c index 7c8bcb476622..4ed64d8e95e7 100644 --- a/drivers/pcmcia/pxa2xx_cm_x255.c +++ b/drivers/pcmcia/pxa2xx_cm_x255.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
| 17 | 17 | ||
| 18 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 19 | #include <mach/pxa-regs.h> | ||
| 20 | 19 | ||
| 21 | #include "soc_common.h" | 20 | #include "soc_common.h" |
| 22 | 21 | ||
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c index 6c3aac377126..a7b943d01e34 100644 --- a/drivers/pcmcia/pxa2xx_cm_x270.c +++ b/drivers/pcmcia/pxa2xx_cm_x270.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
| 17 | 17 | ||
| 18 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 19 | #include <mach/pxa-regs.h> | ||
| 20 | 19 | ||
| 21 | #include "soc_common.h" | 20 | #include "soc_common.h" |
| 22 | 21 | ||
diff --git a/drivers/pcmcia/pxa2xx_e740.c b/drivers/pcmcia/pxa2xx_e740.c index f663a011bf4a..d09c0dc4a31a 100644 --- a/drivers/pcmcia/pxa2xx_e740.c +++ b/drivers/pcmcia/pxa2xx_e740.c | |||
| @@ -16,8 +16,6 @@ | |||
| 16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | 18 | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | #include <mach/pxa-regs.h> | ||
| 21 | #include <mach/eseries-gpio.h> | 19 | #include <mach/eseries-gpio.h> |
| 22 | 20 | ||
| 23 | #include <asm/irq.h> | 21 | #include <asm/irq.h> |
diff --git a/drivers/pcmcia/pxa2xx_lubbock.c b/drivers/pcmcia/pxa2xx_lubbock.c index 37ec55df086e..6cbb1b1f7cfd 100644 --- a/drivers/pcmcia/pxa2xx_lubbock.c +++ b/drivers/pcmcia/pxa2xx_lubbock.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 25 | #include <asm/hardware/sa1111.h> | 25 | #include <asm/hardware/sa1111.h> |
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/lubbock.h> | 27 | #include <mach/lubbock.h> |
| 29 | 28 | ||
| 30 | #include "sa1111_generic.h" | 29 | #include "sa1111_generic.h" |
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c index 877001db4916..1138551ba8f6 100644 --- a/drivers/pcmcia/pxa2xx_mainstone.c +++ b/drivers/pcmcia/pxa2xx_mainstone.c | |||
| @@ -21,11 +21,10 @@ | |||
| 21 | 21 | ||
| 22 | #include <pcmcia/ss.h> | 22 | #include <pcmcia/ss.h> |
| 23 | 23 | ||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 26 | #include <asm/irq.h> | 25 | #include <asm/irq.h> |
| 27 | 26 | ||
| 28 | #include <mach/pxa-regs.h> | 27 | #include <mach/pxa2xx-regs.h> |
| 29 | #include <mach/mainstone.h> | 28 | #include <mach/mainstone.h> |
| 30 | 29 | ||
| 31 | #include "soc_common.h" | 30 | #include "soc_common.h" |
diff --git a/drivers/pcmcia/pxa2xx_palmld.c b/drivers/pcmcia/pxa2xx_palmld.c index 1736c67e547e..5ba9b3664a00 100644 --- a/drivers/pcmcia/pxa2xx_palmld.c +++ b/drivers/pcmcia/pxa2xx_palmld.c | |||
| @@ -98,8 +98,8 @@ static void palmld_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) | |||
| 98 | static struct pcmcia_low_level palmld_pcmcia_ops = { | 98 | static struct pcmcia_low_level palmld_pcmcia_ops = { |
| 99 | .owner = THIS_MODULE, | 99 | .owner = THIS_MODULE, |
| 100 | 100 | ||
| 101 | .first = 0, | 101 | .first = 1, |
| 102 | .nr = 2, | 102 | .nr = 1, |
| 103 | 103 | ||
| 104 | .hw_init = palmld_pcmcia_hw_init, | 104 | .hw_init = palmld_pcmcia_hw_init, |
| 105 | .hw_shutdown = palmld_pcmcia_hw_shutdown, | 105 | .hw_shutdown = palmld_pcmcia_hw_shutdown, |
diff --git a/drivers/pcmcia/pxa2xx_trizeps4.c b/drivers/pcmcia/pxa2xx_trizeps4.c index 36c7a0b324d2..e0e5cb339b4a 100644 --- a/drivers/pcmcia/pxa2xx_trizeps4.c +++ b/drivers/pcmcia/pxa2xx_trizeps4.c | |||
| @@ -22,8 +22,7 @@ | |||
| 22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/irq.h> | 23 | #include <asm/irq.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/pxa2xx-regs.h> |
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | #include <mach/trizeps4.h> | 26 | #include <mach/trizeps4.h> |
| 28 | 27 | ||
| 29 | #include "soc_common.h" | 28 | #include "soc_common.h" |
diff --git a/drivers/pcmcia/pxa2xx_viper.c b/drivers/pcmcia/pxa2xx_viper.c index dd10481be7bf..17871360fe99 100644 --- a/drivers/pcmcia/pxa2xx_viper.c +++ b/drivers/pcmcia/pxa2xx_viper.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | 26 | ||
| 27 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 28 | 28 | ||
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/viper.h> | 29 | #include <mach/viper.h> |
| 31 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 32 | 31 | ||
diff --git a/drivers/pcmcia/sa1100_h3600.c b/drivers/pcmcia/sa1100_h3600.c index 6de4e1b41d60..0cc3748f3758 100644 --- a/drivers/pcmcia/sa1100_h3600.c +++ b/drivers/pcmcia/sa1100_h3600.c | |||
| @@ -37,9 +37,9 @@ static void h3600_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) | |||
| 37 | soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); | 37 | soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); |
| 38 | 38 | ||
| 39 | /* Disable CF bus: */ | 39 | /* Disable CF bus: */ |
| 40 | clr_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON); | 40 | assign_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON, 0); |
| 41 | clr_h3600_egpio(IPAQ_EGPIO_OPT_ON); | 41 | assign_h3600_egpio(IPAQ_EGPIO_OPT_ON, 0); |
| 42 | set_h3600_egpio(IPAQ_EGPIO_OPT_RESET); | 42 | assign_h3600_egpio(IPAQ_EGPIO_OPT_RESET, 1); |
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | static void | 45 | static void |
| @@ -79,10 +79,7 @@ h3600_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_ | |||
| 79 | return -1; | 79 | return -1; |
| 80 | } | 80 | } |
| 81 | 81 | ||
| 82 | if (state->flags & SS_RESET) | 82 | assign_h3600_egpio(IPAQ_EGPIO_CARD_RESET, !!(state->flags & SS_RESET)); |
| 83 | set_h3600_egpio(IPAQ_EGPIO_CARD_RESET); | ||
| 84 | else | ||
| 85 | clr_h3600_egpio(IPAQ_EGPIO_CARD_RESET); | ||
| 86 | 83 | ||
| 87 | /* Silently ignore Vpp, output enable, speaker enable. */ | 84 | /* Silently ignore Vpp, output enable, speaker enable. */ |
| 88 | 85 | ||
| @@ -92,9 +89,9 @@ h3600_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_ | |||
| 92 | static void h3600_pcmcia_socket_init(struct soc_pcmcia_socket *skt) | 89 | static void h3600_pcmcia_socket_init(struct soc_pcmcia_socket *skt) |
| 93 | { | 90 | { |
| 94 | /* Enable CF bus: */ | 91 | /* Enable CF bus: */ |
| 95 | set_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON); | 92 | assign_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON, 1); |
| 96 | set_h3600_egpio(IPAQ_EGPIO_OPT_ON); | 93 | assign_h3600_egpio(IPAQ_EGPIO_OPT_ON, 1); |
| 97 | clr_h3600_egpio(IPAQ_EGPIO_OPT_RESET); | 94 | assign_h3600_egpio(IPAQ_EGPIO_OPT_RESET, 0); |
| 98 | 95 | ||
| 99 | msleep(10); | 96 | msleep(10); |
| 100 | 97 | ||
| @@ -112,10 +109,10 @@ static void h3600_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) | |||
| 112 | * socket 0 then socket 1. | 109 | * socket 0 then socket 1. |
| 113 | */ | 110 | */ |
| 114 | if (skt->nr == 1) { | 111 | if (skt->nr == 1) { |
| 115 | clr_h3600_egpio(IPAQ_EGPIO_OPT_ON); | 112 | assign_h3600_egpio(IPAQ_EGPIO_OPT_ON, 0); |
| 116 | clr_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON); | 113 | assign_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON, 0); |
| 117 | /* hmm, does this suck power? */ | 114 | /* hmm, does this suck power? */ |
| 118 | set_h3600_egpio(IPAQ_EGPIO_OPT_RESET); | 115 | assign_h3600_egpio(IPAQ_EGPIO_OPT_RESET, 1); |
| 119 | } | 116 | } |
| 120 | } | 117 | } |
| 121 | 118 | ||
diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c index 6924d0ea8d32..401052a21ce8 100644 --- a/drivers/pcmcia/sa1111_generic.c +++ b/drivers/pcmcia/sa1111_generic.c | |||
| @@ -11,12 +11,12 @@ | |||
| 11 | #include <linux/device.h> | 11 | #include <linux/device.h> |
| 12 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/io.h> | ||
| 14 | 15 | ||
| 15 | #include <pcmcia/ss.h> | 16 | #include <pcmcia/ss.h> |
| 16 | 17 | ||
| 17 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 18 | #include <asm/hardware/sa1111.h> | 19 | #include <asm/hardware/sa1111.h> |
| 19 | #include <asm/io.h> | ||
| 20 | #include <asm/irq.h> | 20 | #include <asm/irq.h> |
| 21 | 21 | ||
| 22 | #include "sa1111_generic.h" | 22 | #include "sa1111_generic.h" |
diff --git a/drivers/pcmcia/sa11xx_base.c b/drivers/pcmcia/sa11xx_base.c index 7cb1273202cc..e15d59f2d8a9 100644 --- a/drivers/pcmcia/sa11xx_base.c +++ b/drivers/pcmcia/sa11xx_base.c | |||
| @@ -36,9 +36,9 @@ | |||
| 36 | #include <linux/ioport.h> | 36 | #include <linux/ioport.h> |
| 37 | #include <linux/kernel.h> | 37 | #include <linux/kernel.h> |
| 38 | #include <linux/spinlock.h> | 38 | #include <linux/spinlock.h> |
| 39 | #include <linux/io.h> | ||
| 39 | 40 | ||
| 40 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
| 41 | #include <asm/io.h> | ||
| 42 | #include <asm/irq.h> | 42 | #include <asm/irq.h> |
| 43 | #include <asm/system.h> | 43 | #include <asm/system.h> |
| 44 | 44 | ||
| @@ -163,9 +163,55 @@ sa1100_pcmcia_show_timing(struct soc_pcmcia_socket *skt, char *buf) | |||
| 163 | return p - buf; | 163 | return p - buf; |
| 164 | } | 164 | } |
| 165 | 165 | ||
| 166 | static const char *skt_names[] = { | ||
| 167 | "PCMCIA socket 0", | ||
| 168 | "PCMCIA socket 1", | ||
| 169 | }; | ||
| 170 | |||
| 171 | #define SKT_DEV_INFO_SIZE(n) \ | ||
| 172 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | ||
| 173 | |||
| 166 | int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, | 174 | int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, |
| 167 | int first, int nr) | 175 | int first, int nr) |
| 168 | { | 176 | { |
| 177 | struct skt_dev_info *sinfo; | ||
| 178 | struct soc_pcmcia_socket *skt; | ||
| 179 | int i; | ||
| 180 | |||
| 181 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL); | ||
| 182 | if (!sinfo) | ||
| 183 | return -ENOMEM; | ||
| 184 | |||
| 185 | sinfo->nskt = nr; | ||
| 186 | |||
| 187 | /* Initiliaze processor specific parameters */ | ||
| 188 | for (i = 0; i < nr; i++) { | ||
| 189 | skt = &sinfo->skt[i]; | ||
| 190 | |||
| 191 | skt->nr = first + i; | ||
| 192 | skt->irq = NO_IRQ; | ||
| 193 | |||
| 194 | skt->res_skt.start = _PCMCIA(skt->nr); | ||
| 195 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | ||
| 196 | skt->res_skt.name = skt_names[skt->nr]; | ||
| 197 | skt->res_skt.flags = IORESOURCE_MEM; | ||
| 198 | |||
| 199 | skt->res_io.start = _PCMCIAIO(skt->nr); | ||
| 200 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | ||
| 201 | skt->res_io.name = "io"; | ||
| 202 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
| 203 | |||
| 204 | skt->res_mem.start = _PCMCIAMem(skt->nr); | ||
| 205 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | ||
| 206 | skt->res_mem.name = "memory"; | ||
| 207 | skt->res_mem.flags = IORESOURCE_MEM; | ||
| 208 | |||
| 209 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | ||
| 210 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | ||
| 211 | skt->res_attr.name = "attribute"; | ||
| 212 | skt->res_attr.flags = IORESOURCE_MEM; | ||
| 213 | } | ||
| 214 | |||
| 169 | /* | 215 | /* |
| 170 | * set default MECR calculation if the board specific | 216 | * set default MECR calculation if the board specific |
| 171 | * code did not specify one... | 217 | * code did not specify one... |
| @@ -180,7 +226,7 @@ int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, | |||
| 180 | ops->frequency_change = sa1100_pcmcia_frequency_change; | 226 | ops->frequency_change = sa1100_pcmcia_frequency_change; |
| 181 | #endif | 227 | #endif |
| 182 | 228 | ||
| 183 | return soc_common_drv_pcmcia_probe(dev, ops, first, nr); | 229 | return soc_common_drv_pcmcia_probe(dev, ops, sinfo); |
| 184 | } | 230 | } |
| 185 | EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe); | 231 | EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe); |
| 186 | 232 | ||
diff --git a/drivers/pcmcia/soc_common.c b/drivers/pcmcia/soc_common.c index f49ac6666153..163cf98e2386 100644 --- a/drivers/pcmcia/soc_common.c +++ b/drivers/pcmcia/soc_common.c | |||
| @@ -49,11 +49,6 @@ | |||
| 49 | 49 | ||
| 50 | #include "soc_common.h" | 50 | #include "soc_common.h" |
| 51 | 51 | ||
| 52 | /* FIXME: platform dependent resource declaration has to move out of this file */ | ||
| 53 | #ifdef CONFIG_ARCH_PXA | ||
| 54 | #include <mach/pxa-regs.h> | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #ifdef CONFIG_PCMCIA_DEBUG | 52 | #ifdef CONFIG_PCMCIA_DEBUG |
| 58 | 53 | ||
| 59 | static int pc_debug; | 54 | static int pc_debug; |
| @@ -581,19 +576,6 @@ EXPORT_SYMBOL(soc_pcmcia_enable_irqs); | |||
| 581 | LIST_HEAD(soc_pcmcia_sockets); | 576 | LIST_HEAD(soc_pcmcia_sockets); |
| 582 | static DEFINE_MUTEX(soc_pcmcia_sockets_lock); | 577 | static DEFINE_MUTEX(soc_pcmcia_sockets_lock); |
| 583 | 578 | ||
| 584 | static const char *skt_names[] = { | ||
| 585 | "PCMCIA socket 0", | ||
| 586 | "PCMCIA socket 1", | ||
| 587 | }; | ||
| 588 | |||
| 589 | struct skt_dev_info { | ||
| 590 | int nskt; | ||
| 591 | struct soc_pcmcia_socket skt[0]; | ||
| 592 | }; | ||
| 593 | |||
| 594 | #define SKT_DEV_INFO_SIZE(n) \ | ||
| 595 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | ||
| 596 | |||
| 597 | #ifdef CONFIG_CPU_FREQ | 579 | #ifdef CONFIG_CPU_FREQ |
| 598 | static int | 580 | static int |
| 599 | soc_pcmcia_notifier(struct notifier_block *nb, unsigned long val, void *data) | 581 | soc_pcmcia_notifier(struct notifier_block *nb, unsigned long val, void *data) |
| @@ -637,26 +619,18 @@ static int soc_pcmcia_cpufreq_register(void) { return 0; } | |||
| 637 | static void soc_pcmcia_cpufreq_unregister(void) {} | 619 | static void soc_pcmcia_cpufreq_unregister(void) {} |
| 638 | #endif | 620 | #endif |
| 639 | 621 | ||
| 640 | int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr) | 622 | int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, |
| 623 | struct skt_dev_info *sinfo) | ||
| 641 | { | 624 | { |
| 642 | struct skt_dev_info *sinfo; | ||
| 643 | struct soc_pcmcia_socket *skt; | 625 | struct soc_pcmcia_socket *skt; |
| 644 | int ret, i; | 626 | int ret, i; |
| 645 | 627 | ||
| 646 | mutex_lock(&soc_pcmcia_sockets_lock); | 628 | mutex_lock(&soc_pcmcia_sockets_lock); |
| 647 | 629 | ||
| 648 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL); | ||
| 649 | if (!sinfo) { | ||
| 650 | ret = -ENOMEM; | ||
| 651 | goto out; | ||
| 652 | } | ||
| 653 | |||
| 654 | sinfo->nskt = nr; | ||
| 655 | |||
| 656 | /* | 630 | /* |
| 657 | * Initialise the per-socket structure. | 631 | * Initialise the per-socket structure. |
| 658 | */ | 632 | */ |
| 659 | for (i = 0; i < nr; i++) { | 633 | for (i = 0; i < sinfo->nskt; i++) { |
| 660 | skt = &sinfo->skt[i]; | 634 | skt = &sinfo->skt[i]; |
| 661 | 635 | ||
| 662 | skt->socket.ops = &soc_common_pcmcia_operations; | 636 | skt->socket.ops = &soc_common_pcmcia_operations; |
| @@ -668,43 +642,21 @@ int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops | |||
| 668 | skt->poll_timer.data = (unsigned long)skt; | 642 | skt->poll_timer.data = (unsigned long)skt; |
| 669 | skt->poll_timer.expires = jiffies + SOC_PCMCIA_POLL_PERIOD; | 643 | skt->poll_timer.expires = jiffies + SOC_PCMCIA_POLL_PERIOD; |
| 670 | 644 | ||
| 671 | skt->nr = first + i; | ||
| 672 | skt->irq = NO_IRQ; | ||
| 673 | skt->dev = dev; | 645 | skt->dev = dev; |
| 674 | skt->ops = ops; | 646 | skt->ops = ops; |
| 675 | 647 | ||
| 676 | skt->res_skt.start = _PCMCIA(skt->nr); | ||
| 677 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | ||
| 678 | skt->res_skt.name = skt_names[skt->nr]; | ||
| 679 | skt->res_skt.flags = IORESOURCE_MEM; | ||
| 680 | |||
| 681 | ret = request_resource(&iomem_resource, &skt->res_skt); | 648 | ret = request_resource(&iomem_resource, &skt->res_skt); |
| 682 | if (ret) | 649 | if (ret) |
| 683 | goto out_err_1; | 650 | goto out_err_1; |
| 684 | 651 | ||
| 685 | skt->res_io.start = _PCMCIAIO(skt->nr); | ||
| 686 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | ||
| 687 | skt->res_io.name = "io"; | ||
| 688 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
| 689 | |||
| 690 | ret = request_resource(&skt->res_skt, &skt->res_io); | 652 | ret = request_resource(&skt->res_skt, &skt->res_io); |
| 691 | if (ret) | 653 | if (ret) |
| 692 | goto out_err_2; | 654 | goto out_err_2; |
| 693 | 655 | ||
| 694 | skt->res_mem.start = _PCMCIAMem(skt->nr); | ||
| 695 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | ||
| 696 | skt->res_mem.name = "memory"; | ||
| 697 | skt->res_mem.flags = IORESOURCE_MEM; | ||
| 698 | |||
| 699 | ret = request_resource(&skt->res_skt, &skt->res_mem); | 656 | ret = request_resource(&skt->res_skt, &skt->res_mem); |
| 700 | if (ret) | 657 | if (ret) |
| 701 | goto out_err_3; | 658 | goto out_err_3; |
| 702 | 659 | ||
| 703 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | ||
| 704 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | ||
| 705 | skt->res_attr.name = "attribute"; | ||
| 706 | skt->res_attr.flags = IORESOURCE_MEM; | ||
| 707 | |||
| 708 | ret = request_resource(&skt->res_skt, &skt->res_attr); | 660 | ret = request_resource(&skt->res_skt, &skt->res_attr); |
| 709 | if (ret) | 661 | if (ret) |
| 710 | goto out_err_4; | 662 | goto out_err_4; |
diff --git a/drivers/pcmcia/soc_common.h b/drivers/pcmcia/soc_common.h index 38c67375f363..290e143839ee 100644 --- a/drivers/pcmcia/soc_common.h +++ b/drivers/pcmcia/soc_common.h | |||
| @@ -58,6 +58,11 @@ struct soc_pcmcia_socket { | |||
| 58 | struct list_head node; | 58 | struct list_head node; |
| 59 | }; | 59 | }; |
| 60 | 60 | ||
| 61 | struct skt_dev_info { | ||
| 62 | int nskt; | ||
| 63 | struct soc_pcmcia_socket skt[0]; | ||
| 64 | }; | ||
| 65 | |||
| 61 | struct pcmcia_state { | 66 | struct pcmcia_state { |
| 62 | unsigned detect: 1, | 67 | unsigned detect: 1, |
| 63 | ready: 1, | 68 | ready: 1, |
| @@ -132,7 +137,7 @@ extern void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *, struct soc_ | |||
| 132 | 137 | ||
| 133 | extern struct list_head soc_pcmcia_sockets; | 138 | extern struct list_head soc_pcmcia_sockets; |
| 134 | 139 | ||
| 135 | extern int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr); | 140 | extern int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, struct skt_dev_info *sinfo); |
| 136 | extern int soc_common_drv_pcmcia_remove(struct device *dev); | 141 | extern int soc_common_drv_pcmcia_remove(struct device *dev); |
| 137 | 142 | ||
| 138 | 143 | ||
diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c index 45f12dcd3716..e0263d2005ee 100644 --- a/drivers/rtc/rtc-mv.c +++ b/drivers/rtc/rtc-mv.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <linux/bcd.h> | 12 | #include <linux/bcd.h> |
| 13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/delay.h> | ||
| 15 | 16 | ||
| 16 | 17 | ||
| 17 | #define RTC_TIME_REG_OFFS 0 | 18 | #define RTC_TIME_REG_OFFS 0 |
| @@ -119,6 +120,16 @@ static int __init mv_rtc_probe(struct platform_device *pdev) | |||
| 119 | return -EINVAL; | 120 | return -EINVAL; |
| 120 | } | 121 | } |
| 121 | 122 | ||
| 123 | /* make sure it is actually functional */ | ||
| 124 | if (rtc_time == 0x01000000) { | ||
| 125 | ssleep(1); | ||
| 126 | rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS); | ||
| 127 | if (rtc_time == 0x01000000) { | ||
| 128 | dev_err(&pdev->dev, "internal RTC not ticking\n"); | ||
| 129 | return -ENODEV; | ||
| 130 | } | ||
| 131 | } | ||
| 132 | |||
| 122 | platform_set_drvdata(pdev, pdata); | 133 | platform_set_drvdata(pdev, pdata); |
| 123 | pdata->rtc = rtc_device_register(pdev->name, &pdev->dev, | 134 | pdata->rtc = rtc_device_register(pdev->name, &pdev->dev, |
| 124 | &mv_rtc_ops, THIS_MODULE); | 135 | &mv_rtc_ops, THIS_MODULE); |
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c index d26a5f82aaba..4f247e4dd3f9 100644 --- a/drivers/rtc/rtc-sa1100.c +++ b/drivers/rtc/rtc-sa1100.c | |||
| @@ -35,7 +35,8 @@ | |||
| 35 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
| 36 | 36 | ||
| 37 | #ifdef CONFIG_ARCH_PXA | 37 | #ifdef CONFIG_ARCH_PXA |
| 38 | #include <mach/pxa-regs.h> | 38 | #include <mach/regs-rtc.h> |
| 39 | #include <mach/regs-ost.h> | ||
| 39 | #endif | 40 | #endif |
| 40 | 41 | ||
| 41 | #define RTC_DEF_DIVIDER 32768 - 1 | 42 | #define RTC_DEF_DIVIDER 32768 - 1 |
diff --git a/drivers/scsi/arm/cumana_2.c b/drivers/scsi/arm/cumana_2.c index 68a64123af8f..c9902b5c1f2b 100644 --- a/drivers/scsi/arm/cumana_2.c +++ b/drivers/scsi/arm/cumana_2.c | |||
| @@ -318,7 +318,7 @@ cumanascsi_2_set_proc_info(struct Scsi_Host *host, char *buffer, int length) | |||
| 318 | { | 318 | { |
| 319 | int ret = length; | 319 | int ret = length; |
| 320 | 320 | ||
| 321 | if (length >= 11 && strcmp(buffer, "CUMANASCSI2") == 0) { | 321 | if (length >= 11 && strncmp(buffer, "CUMANASCSI2", 11) == 0) { |
| 322 | buffer += 11; | 322 | buffer += 11; |
| 323 | length -= 11; | 323 | length -= 11; |
| 324 | 324 | ||
| @@ -390,7 +390,8 @@ static struct scsi_host_template cumanascsi2_template = { | |||
| 390 | .eh_abort_handler = fas216_eh_abort, | 390 | .eh_abort_handler = fas216_eh_abort, |
| 391 | .can_queue = 1, | 391 | .can_queue = 1, |
| 392 | .this_id = 7, | 392 | .this_id = 7, |
| 393 | .sg_tablesize = SG_ALL, | 393 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 394 | .dma_boundary = IOMD_DMA_BOUNDARY, | ||
| 394 | .cmd_per_lun = 1, | 395 | .cmd_per_lun = 1, |
| 395 | .use_clustering = DISABLE_CLUSTERING, | 396 | .use_clustering = DISABLE_CLUSTERING, |
| 396 | .proc_name = "cumanascsi2", | 397 | .proc_name = "cumanascsi2", |
diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c index bb2477b3fb0b..d8435132f461 100644 --- a/drivers/scsi/arm/eesox.c +++ b/drivers/scsi/arm/eesox.c | |||
| @@ -508,7 +508,8 @@ static struct scsi_host_template eesox_template = { | |||
| 508 | .eh_abort_handler = fas216_eh_abort, | 508 | .eh_abort_handler = fas216_eh_abort, |
| 509 | .can_queue = 1, | 509 | .can_queue = 1, |
| 510 | .this_id = 7, | 510 | .this_id = 7, |
| 511 | .sg_tablesize = SG_ALL, | 511 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 512 | .dma_boundary = IOMD_DMA_BOUNDARY, | ||
| 512 | .cmd_per_lun = 1, | 513 | .cmd_per_lun = 1, |
| 513 | .use_clustering = DISABLE_CLUSTERING, | 514 | .use_clustering = DISABLE_CLUSTERING, |
| 514 | .proc_name = "eesox", | 515 | .proc_name = "eesox", |
diff --git a/drivers/scsi/arm/powertec.c b/drivers/scsi/arm/powertec.c index d9a546d1917c..e2297b4c1b9e 100644 --- a/drivers/scsi/arm/powertec.c +++ b/drivers/scsi/arm/powertec.c | |||
| @@ -302,7 +302,8 @@ static struct scsi_host_template powertecscsi_template = { | |||
| 302 | 302 | ||
| 303 | .can_queue = 8, | 303 | .can_queue = 8, |
| 304 | .this_id = 7, | 304 | .this_id = 7, |
| 305 | .sg_tablesize = SG_ALL, | 305 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 306 | .dma_boundary = IOMD_DMA_BOUNDARY, | ||
| 306 | .cmd_per_lun = 2, | 307 | .cmd_per_lun = 2, |
| 307 | .use_clustering = ENABLE_CLUSTERING, | 308 | .use_clustering = ENABLE_CLUSTERING, |
| 308 | .proc_name = "powertec", | 309 | .proc_name = "powertec", |
diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c index f31c6698419c..cb6d85d7ff43 100644 --- a/drivers/serial/21285.c +++ b/drivers/serial/21285.c | |||
| @@ -14,8 +14,8 @@ | |||
| 14 | #include <linux/tty_flip.h> | 14 | #include <linux/tty_flip.h> |
| 15 | #include <linux/serial_core.h> | 15 | #include <linux/serial_core.h> |
| 16 | #include <linux/serial.h> | 16 | #include <linux/serial.h> |
| 17 | #include <linux/io.h> | ||
| 17 | 18 | ||
| 18 | #include <asm/io.h> | ||
| 19 | #include <asm/irq.h> | 19 | #include <asm/irq.h> |
| 20 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 21 | #include <asm/hardware/dec21285.h> | 21 | #include <asm/hardware/dec21285.h> |
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 7d7f576da202..9be11b0963f2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
| @@ -628,7 +628,7 @@ config SERIAL_MPSC_CONSOLE | |||
| 628 | 628 | ||
| 629 | config SERIAL_PXA | 629 | config SERIAL_PXA |
| 630 | bool "PXA serial port support" | 630 | bool "PXA serial port support" |
| 631 | depends on ARM && ARCH_PXA | 631 | depends on ARCH_PXA || ARCH_MMP |
| 632 | select SERIAL_CORE | 632 | select SERIAL_CORE |
| 633 | help | 633 | help |
| 634 | If you have a machine based on an Intel XScale PXA2xx CPU you | 634 | If you have a machine based on an Intel XScale PXA2xx CPU you |
diff --git a/drivers/serial/clps711x.c b/drivers/serial/clps711x.c index 459f3420a429..80e76426131d 100644 --- a/drivers/serial/clps711x.c +++ b/drivers/serial/clps711x.c | |||
| @@ -38,9 +38,9 @@ | |||
| 38 | #include <linux/tty_flip.h> | 38 | #include <linux/tty_flip.h> |
| 39 | #include <linux/serial_core.h> | 39 | #include <linux/serial_core.h> |
| 40 | #include <linux/serial.h> | 40 | #include <linux/serial.h> |
| 41 | #include <linux/io.h> | ||
| 41 | 42 | ||
| 42 | #include <mach/hardware.h> | 43 | #include <mach/hardware.h> |
| 43 | #include <asm/io.h> | ||
| 44 | #include <asm/irq.h> | 44 | #include <asm/irq.h> |
| 45 | #include <asm/hardware/clps7111.h> | 45 | #include <asm/hardware/clps7111.h> |
| 46 | 46 | ||
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index a50954612b60..9f460b175c50 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
| @@ -1129,7 +1129,7 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
| 1129 | sport->timer.function = imx_timeout; | 1129 | sport->timer.function = imx_timeout; |
| 1130 | sport->timer.data = (unsigned long)sport; | 1130 | sport->timer.data = (unsigned long)sport; |
| 1131 | 1131 | ||
| 1132 | sport->clk = clk_get(&pdev->dev, "uart_clk"); | 1132 | sport->clk = clk_get(&pdev->dev, "uart"); |
| 1133 | if (IS_ERR(sport->clk)) { | 1133 | if (IS_ERR(sport->clk)) { |
| 1134 | ret = PTR_ERR(sport->clk); | 1134 | ret = PTR_ERR(sport->clk); |
| 1135 | goto unmap; | 1135 | goto unmap; |
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c index f6e3b86bb0be..a48a8a13d87b 100644 --- a/drivers/serial/pxa.c +++ b/drivers/serial/pxa.c | |||
| @@ -43,13 +43,7 @@ | |||
| 43 | #include <linux/tty_flip.h> | 43 | #include <linux/tty_flip.h> |
| 44 | #include <linux/serial_core.h> | 44 | #include <linux/serial_core.h> |
| 45 | #include <linux/clk.h> | 45 | #include <linux/clk.h> |
| 46 | 46 | #include <linux/io.h> | |
| 47 | #include <asm/io.h> | ||
| 48 | #include <mach/hardware.h> | ||
| 49 | #include <asm/irq.h> | ||
| 50 | #include <mach/pxa-regs.h> | ||
| 51 | #include <mach/regs-uart.h> | ||
| 52 | |||
| 53 | 47 | ||
| 54 | struct uart_pxa_port { | 48 | struct uart_pxa_port { |
| 55 | struct uart_port port; | 49 | struct uart_port port; |
| @@ -491,7 +485,7 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, | |||
| 491 | * Ensure the port will be enabled. | 485 | * Ensure the port will be enabled. |
| 492 | * This is required especially for serial console. | 486 | * This is required especially for serial console. |
| 493 | */ | 487 | */ |
| 494 | up->ier |= IER_UUE; | 488 | up->ier |= UART_IER_UUE; |
| 495 | 489 | ||
| 496 | /* | 490 | /* |
| 497 | * Update the per-port timeout. | 491 | * Update the per-port timeout. |
| @@ -784,19 +778,15 @@ static int serial_pxa_probe(struct platform_device *dev) | |||
| 784 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | 778 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; |
| 785 | sport->port.uartclk = clk_get_rate(sport->clk); | 779 | sport->port.uartclk = clk_get_rate(sport->clk); |
| 786 | 780 | ||
| 787 | /* | 781 | switch (dev->id) { |
| 788 | * Is it worth keeping this? | 782 | case 0: sport->name = "FFUART"; break; |
| 789 | */ | 783 | case 1: sport->name = "BTUART"; break; |
| 790 | if (mmres->start == __PREG(FFUART)) | 784 | case 2: sport->name = "STUART"; break; |
| 791 | sport->name = "FFUART"; | 785 | case 3: sport->name = "HWUART"; break; |
| 792 | else if (mmres->start == __PREG(BTUART)) | 786 | default: |
| 793 | sport->name = "BTUART"; | ||
| 794 | else if (mmres->start == __PREG(STUART)) | ||
| 795 | sport->name = "STUART"; | ||
| 796 | else if (mmres->start == __PREG(HWUART)) | ||
| 797 | sport->name = "HWUART"; | ||
| 798 | else | ||
| 799 | sport->name = "???"; | 787 | sport->name = "???"; |
| 788 | break; | ||
| 789 | } | ||
| 800 | 790 | ||
| 801 | sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); | 791 | sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); |
| 802 | if (!sport->port.membase) { | 792 | if (!sport->port.membase) { |
diff --git a/drivers/serial/sa1100.c b/drivers/serial/sa1100.c index b24a25ea6bc5..94530f01521e 100644 --- a/drivers/serial/sa1100.c +++ b/drivers/serial/sa1100.c | |||
| @@ -36,8 +36,8 @@ | |||
| 36 | #include <linux/tty_flip.h> | 36 | #include <linux/tty_flip.h> |
| 37 | #include <linux/serial_core.h> | 37 | #include <linux/serial_core.h> |
| 38 | #include <linux/serial.h> | 38 | #include <linux/serial.h> |
| 39 | #include <linux/io.h> | ||
| 39 | 40 | ||
| 40 | #include <asm/io.h> | ||
| 41 | #include <asm/irq.h> | 41 | #include <asm/irq.h> |
| 42 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
| 43 | #include <asm/mach/serial_sa1100.h> | 43 | #include <asm/mach/serial_sa1100.h> |
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index 1c65e380c845..d6d0c5d241ce 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c | |||
| @@ -1021,13 +1021,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) | |||
| 1021 | spin_lock_init(&mcspi->lock); | 1021 | spin_lock_init(&mcspi->lock); |
| 1022 | INIT_LIST_HEAD(&mcspi->msg_queue); | 1022 | INIT_LIST_HEAD(&mcspi->msg_queue); |
| 1023 | 1023 | ||
| 1024 | mcspi->ick = clk_get(&pdev->dev, "mcspi_ick"); | 1024 | mcspi->ick = clk_get(&pdev->dev, "ick"); |
| 1025 | if (IS_ERR(mcspi->ick)) { | 1025 | if (IS_ERR(mcspi->ick)) { |
| 1026 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); | 1026 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); |
| 1027 | status = PTR_ERR(mcspi->ick); | 1027 | status = PTR_ERR(mcspi->ick); |
| 1028 | goto err1a; | 1028 | goto err1a; |
| 1029 | } | 1029 | } |
| 1030 | mcspi->fck = clk_get(&pdev->dev, "mcspi_fck"); | 1030 | mcspi->fck = clk_get(&pdev->dev, "fck"); |
| 1031 | if (IS_ERR(mcspi->fck)) { | 1031 | if (IS_ERR(mcspi->fck)) { |
| 1032 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); | 1032 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); |
| 1033 | status = PTR_ERR(mcspi->fck); | 1033 | status = PTR_ERR(mcspi->fck); |
diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c index 60b5381c65c4..fe8b9ac0ccef 100644 --- a/drivers/spi/omap_uwire.c +++ b/drivers/spi/omap_uwire.c | |||
| @@ -506,11 +506,12 @@ static int __init uwire_probe(struct platform_device *pdev) | |||
| 506 | 506 | ||
| 507 | dev_set_drvdata(&pdev->dev, uwire); | 507 | dev_set_drvdata(&pdev->dev, uwire); |
| 508 | 508 | ||
| 509 | uwire->ck = clk_get(&pdev->dev, "armxor_ck"); | 509 | uwire->ck = clk_get(&pdev->dev, "fck"); |
| 510 | if (!uwire->ck || IS_ERR(uwire->ck)) { | 510 | if (IS_ERR(uwire->ck)) { |
| 511 | dev_dbg(&pdev->dev, "no mpu_xor_clk ?\n"); | 511 | status = PTR_ERR(uwire->ck); |
| 512 | dev_dbg(&pdev->dev, "no functional clock?\n"); | ||
| 512 | spi_master_put(master); | 513 | spi_master_put(master); |
| 513 | return -ENODEV; | 514 | return status; |
| 514 | } | 515 | } |
| 515 | clk_enable(uwire->ck); | 516 | clk_enable(uwire->ck); |
| 516 | 517 | ||
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c index ec24f2d16f3c..33fcef3150d4 100644 --- a/drivers/spi/pxa2xx_spi.c +++ b/drivers/spi/pxa2xx_spi.c | |||
| @@ -34,8 +34,6 @@ | |||
| 34 | #include <asm/delay.h> | 34 | #include <asm/delay.h> |
| 35 | 35 | ||
| 36 | #include <mach/dma.h> | 36 | #include <mach/dma.h> |
| 37 | #include <mach/hardware.h> | ||
| 38 | #include <mach/pxa-regs.h> | ||
| 39 | #include <mach/regs-ssp.h> | 37 | #include <mach/regs-ssp.h> |
| 40 | #include <mach/ssp.h> | 38 | #include <mach/ssp.h> |
| 41 | #include <mach/pxa2xx_spi.h> | 39 | #include <mach/pxa2xx_spi.h> |
diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c index fb3055f084b5..7cf74f8c2db1 100644 --- a/drivers/usb/host/ohci-ep93xx.c +++ b/drivers/usb/host/ohci-ep93xx.c | |||
| @@ -28,8 +28,6 @@ | |||
| 28 | #include <linux/signal.h> | 28 | #include <linux/signal.h> |
| 29 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 30 | 30 | ||
| 31 | #include <mach/hardware.h> | ||
| 32 | |||
| 33 | static struct clk *usb_host_clock; | 31 | static struct clk *usb_host_clock; |
| 34 | 32 | ||
| 35 | static void ep93xx_start_hc(struct device *dev) | 33 | static void ep93xx_start_hc(struct device *dev) |
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fb19803060cf..41c27a44bd82 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig | |||
| @@ -397,7 +397,7 @@ config FB_SA1100 | |||
| 397 | 397 | ||
| 398 | config FB_IMX | 398 | config FB_IMX |
| 399 | tristate "Motorola i.MX LCD support" | 399 | tristate "Motorola i.MX LCD support" |
| 400 | depends on FB && ARM && ARCH_IMX | 400 | depends on FB && (ARCH_IMX || ARCH_MX2) |
| 401 | select FB_CFB_FILLRECT | 401 | select FB_CFB_FILLRECT |
| 402 | select FB_CFB_COPYAREA | 402 | select FB_CFB_COPYAREA |
| 403 | select FB_CFB_IMAGEBLIT | 403 | select FB_CFB_IMAGEBLIT |
| @@ -2120,16 +2120,30 @@ config FB_PRE_INIT_FB | |||
| 2120 | the bootloader. | 2120 | the bootloader. |
| 2121 | 2121 | ||
| 2122 | config FB_MX3 | 2122 | config FB_MX3 |
| 2123 | tristate "MX3 Framebuffer support" | 2123 | tristate "MX3 Framebuffer support" |
| 2124 | depends on FB && MX3_IPU | 2124 | depends on FB && MX3_IPU |
| 2125 | select FB_CFB_FILLRECT | 2125 | select FB_CFB_FILLRECT |
| 2126 | select FB_CFB_COPYAREA | 2126 | select FB_CFB_COPYAREA |
| 2127 | select FB_CFB_IMAGEBLIT | 2127 | select FB_CFB_IMAGEBLIT |
| 2128 | default y | 2128 | default y |
| 2129 | help | 2129 | help |
| 2130 | This is a framebuffer device for the i.MX31 LCD Controller. So | 2130 | This is a framebuffer device for the i.MX31 LCD Controller. So |
| 2131 | far only synchronous displays are supported. If you plan to use | 2131 | far only synchronous displays are supported. If you plan to use |
| 2132 | an LCD display with your i.MX31 system, say Y here. | 2132 | an LCD display with your i.MX31 system, say Y here. |
| 2133 | |||
| 2134 | config FB_BROADSHEET | ||
| 2135 | tristate "E-Ink Broadsheet/Epson S1D13521 controller support" | ||
| 2136 | depends on FB | ||
| 2137 | select FB_SYS_FILLRECT | ||
| 2138 | select FB_SYS_COPYAREA | ||
| 2139 | select FB_SYS_IMAGEBLIT | ||
| 2140 | select FB_SYS_FOPS | ||
| 2141 | select FB_DEFERRED_IO | ||
| 2142 | help | ||
| 2143 | This driver implements support for the E-Ink Broadsheet | ||
| 2144 | controller. The release name for this device was Epson S1D13521 | ||
| 2145 | and could also have been called by other names when coupled with | ||
| 2146 | a bridge adapter. | ||
| 2133 | 2147 | ||
| 2134 | source "drivers/video/omap/Kconfig" | 2148 | source "drivers/video/omap/Kconfig" |
| 2135 | 2149 | ||
diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 2a998ca6181d..bb265eca7d57 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile | |||
| @@ -106,6 +106,7 @@ obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o | |||
| 106 | obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o | 106 | obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o |
| 107 | obj-$(CONFIG_FB_MAXINE) += maxinefb.o | 107 | obj-$(CONFIG_FB_MAXINE) += maxinefb.o |
| 108 | obj-$(CONFIG_FB_METRONOME) += metronomefb.o | 108 | obj-$(CONFIG_FB_METRONOME) += metronomefb.o |
| 109 | obj-$(CONFIG_FB_BROADSHEET) += broadsheetfb.o | ||
| 109 | obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o | 110 | obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o |
| 110 | obj-$(CONFIG_FB_SH7760) += sh7760fb.o | 111 | obj-$(CONFIG_FB_SH7760) += sh7760fb.o |
| 111 | obj-$(CONFIG_FB_IMX) += imxfb.o | 112 | obj-$(CONFIG_FB_IMX) += imxfb.o |
| @@ -132,7 +133,7 @@ obj-$(CONFIG_FB_VGA16) += vga16fb.o | |||
| 132 | obj-$(CONFIG_FB_OF) += offb.o | 133 | obj-$(CONFIG_FB_OF) += offb.o |
| 133 | obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o | 134 | obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o |
| 134 | obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o | 135 | obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o |
| 135 | obj-$(CONFIG_FB_MX3) += mx3fb.o | 136 | obj-$(CONFIG_FB_MX3) += mx3fb.o |
| 136 | 137 | ||
| 137 | # the test framebuffer is last | 138 | # the test framebuffer is last |
| 138 | obj-$(CONFIG_FB_VIRTUAL) += vfb.o | 139 | obj-$(CONFIG_FB_VIRTUAL) += vfb.o |
diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c index 61c3d3f40fd1..6995fe1e86d4 100644 --- a/drivers/video/acornfb.c +++ b/drivers/video/acornfb.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #include <linux/fb.h> | 28 | #include <linux/fb.h> |
| 29 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/dma-mapping.h> | 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/io.h> | ||
| 31 | 32 | ||
| 32 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 33 | #include <asm/io.h> | ||
| 34 | #include <asm/irq.h> | 34 | #include <asm/irq.h> |
| 35 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
| 36 | #include <asm/pgtable.h> | 36 | #include <asm/pgtable.h> |
diff --git a/drivers/video/broadsheetfb.c b/drivers/video/broadsheetfb.c new file mode 100644 index 000000000000..509cb92e8731 --- /dev/null +++ b/drivers/video/broadsheetfb.c | |||
| @@ -0,0 +1,568 @@ | |||
| 1 | /* | ||
| 2 | * broadsheetfb.c -- FB driver for E-Ink Broadsheet controller | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008, Jaya Kumar | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | * | ||
| 10 | * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven. | ||
| 11 | * | ||
| 12 | * This driver is written to be used with the Broadsheet display controller. | ||
| 13 | * | ||
| 14 | * It is intended to be architecture independent. A board specific driver | ||
| 15 | * must be used to perform all the physical IO interactions. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/string.h> | ||
| 23 | #include <linux/mm.h> | ||
| 24 | #include <linux/slab.h> | ||
| 25 | #include <linux/vmalloc.h> | ||
| 26 | #include <linux/delay.h> | ||
| 27 | #include <linux/interrupt.h> | ||
| 28 | #include <linux/fb.h> | ||
| 29 | #include <linux/init.h> | ||
| 30 | #include <linux/platform_device.h> | ||
| 31 | #include <linux/list.h> | ||
| 32 | #include <linux/uaccess.h> | ||
| 33 | |||
| 34 | #include <video/broadsheetfb.h> | ||
| 35 | |||
| 36 | /* Display specific information */ | ||
| 37 | #define DPY_W 800 | ||
| 38 | #define DPY_H 600 | ||
| 39 | |||
| 40 | static struct fb_fix_screeninfo broadsheetfb_fix __devinitdata = { | ||
| 41 | .id = "broadsheetfb", | ||
| 42 | .type = FB_TYPE_PACKED_PIXELS, | ||
| 43 | .visual = FB_VISUAL_STATIC_PSEUDOCOLOR, | ||
| 44 | .xpanstep = 0, | ||
| 45 | .ypanstep = 0, | ||
| 46 | .ywrapstep = 0, | ||
| 47 | .line_length = DPY_W, | ||
| 48 | .accel = FB_ACCEL_NONE, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct fb_var_screeninfo broadsheetfb_var __devinitdata = { | ||
| 52 | .xres = DPY_W, | ||
| 53 | .yres = DPY_H, | ||
| 54 | .xres_virtual = DPY_W, | ||
| 55 | .yres_virtual = DPY_H, | ||
| 56 | .bits_per_pixel = 8, | ||
| 57 | .grayscale = 1, | ||
| 58 | .red = { 0, 4, 0 }, | ||
| 59 | .green = { 0, 4, 0 }, | ||
| 60 | .blue = { 0, 4, 0 }, | ||
| 61 | .transp = { 0, 0, 0 }, | ||
| 62 | }; | ||
| 63 | |||
| 64 | /* main broadsheetfb functions */ | ||
| 65 | static void broadsheet_issue_data(struct broadsheetfb_par *par, u16 data) | ||
| 66 | { | ||
| 67 | par->board->set_ctl(par, BS_WR, 0); | ||
| 68 | par->board->set_hdb(par, data); | ||
| 69 | par->board->set_ctl(par, BS_WR, 1); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void broadsheet_issue_cmd(struct broadsheetfb_par *par, u16 data) | ||
| 73 | { | ||
| 74 | par->board->set_ctl(par, BS_DC, 0); | ||
| 75 | broadsheet_issue_data(par, data); | ||
| 76 | } | ||
| 77 | |||
| 78 | static void broadsheet_send_command(struct broadsheetfb_par *par, u16 data) | ||
| 79 | { | ||
| 80 | par->board->wait_for_rdy(par); | ||
| 81 | |||
| 82 | par->board->set_ctl(par, BS_CS, 0); | ||
| 83 | broadsheet_issue_cmd(par, data); | ||
| 84 | par->board->set_ctl(par, BS_DC, 1); | ||
| 85 | par->board->set_ctl(par, BS_CS, 1); | ||
| 86 | } | ||
| 87 | |||
| 88 | static void broadsheet_send_cmdargs(struct broadsheetfb_par *par, u16 cmd, | ||
| 89 | int argc, u16 *argv) | ||
| 90 | { | ||
| 91 | int i; | ||
| 92 | |||
| 93 | par->board->wait_for_rdy(par); | ||
| 94 | |||
| 95 | par->board->set_ctl(par, BS_CS, 0); | ||
| 96 | broadsheet_issue_cmd(par, cmd); | ||
| 97 | par->board->set_ctl(par, BS_DC, 1); | ||
| 98 | |||
| 99 | for (i = 0; i < argc; i++) | ||
| 100 | broadsheet_issue_data(par, argv[i]); | ||
| 101 | par->board->set_ctl(par, BS_CS, 1); | ||
| 102 | } | ||
| 103 | |||
| 104 | static void broadsheet_burst_write(struct broadsheetfb_par *par, int size, | ||
| 105 | u16 *data) | ||
| 106 | { | ||
| 107 | int i; | ||
| 108 | u16 tmp; | ||
| 109 | |||
| 110 | par->board->set_ctl(par, BS_CS, 0); | ||
| 111 | par->board->set_ctl(par, BS_DC, 1); | ||
| 112 | |||
| 113 | for (i = 0; i < size; i++) { | ||
| 114 | par->board->set_ctl(par, BS_WR, 0); | ||
| 115 | tmp = (data[i] & 0x0F) << 4; | ||
| 116 | tmp |= (data[i] & 0x0F00) << 4; | ||
| 117 | par->board->set_hdb(par, tmp); | ||
| 118 | par->board->set_ctl(par, BS_WR, 1); | ||
| 119 | } | ||
| 120 | |||
| 121 | par->board->set_ctl(par, BS_CS, 1); | ||
| 122 | } | ||
| 123 | |||
| 124 | static u16 broadsheet_get_data(struct broadsheetfb_par *par) | ||
| 125 | { | ||
| 126 | u16 res; | ||
| 127 | /* wait for ready to go hi. (lo is busy) */ | ||
| 128 | par->board->wait_for_rdy(par); | ||
| 129 | |||
| 130 | /* cs lo, dc lo for cmd, we lo for each data, db as usual */ | ||
| 131 | par->board->set_ctl(par, BS_DC, 1); | ||
| 132 | par->board->set_ctl(par, BS_CS, 0); | ||
| 133 | par->board->set_ctl(par, BS_WR, 0); | ||
| 134 | |||
| 135 | res = par->board->get_hdb(par); | ||
| 136 | |||
| 137 | /* strobe wr */ | ||
| 138 | par->board->set_ctl(par, BS_WR, 1); | ||
| 139 | par->board->set_ctl(par, BS_CS, 1); | ||
| 140 | |||
| 141 | return res; | ||
| 142 | } | ||
| 143 | |||
| 144 | static void broadsheet_write_reg(struct broadsheetfb_par *par, u16 reg, | ||
| 145 | u16 data) | ||
| 146 | { | ||
| 147 | /* wait for ready to go hi. (lo is busy) */ | ||
| 148 | par->board->wait_for_rdy(par); | ||
| 149 | |||
| 150 | /* cs lo, dc lo for cmd, we lo for each data, db as usual */ | ||
| 151 | par->board->set_ctl(par, BS_CS, 0); | ||
| 152 | |||
| 153 | broadsheet_issue_cmd(par, BS_CMD_WR_REG); | ||
| 154 | |||
| 155 | par->board->set_ctl(par, BS_DC, 1); | ||
| 156 | |||
| 157 | broadsheet_issue_data(par, reg); | ||
| 158 | broadsheet_issue_data(par, data); | ||
| 159 | |||
| 160 | par->board->set_ctl(par, BS_CS, 1); | ||
| 161 | } | ||
| 162 | |||
| 163 | static u16 broadsheet_read_reg(struct broadsheetfb_par *par, u16 reg) | ||
| 164 | { | ||
| 165 | broadsheet_send_command(par, reg); | ||
| 166 | msleep(100); | ||
| 167 | return broadsheet_get_data(par); | ||
| 168 | } | ||
| 169 | |||
| 170 | static void __devinit broadsheet_init_display(struct broadsheetfb_par *par) | ||
| 171 | { | ||
| 172 | u16 args[5]; | ||
| 173 | |||
| 174 | args[0] = DPY_W; | ||
| 175 | args[1] = DPY_H; | ||
| 176 | args[2] = (100 | (1 << 8) | (1 << 9)); /* sdcfg */ | ||
| 177 | args[3] = 2; /* gdrv cfg */ | ||
| 178 | args[4] = (4 | (1 << 7)); /* lut index format */ | ||
| 179 | broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_CFG, 5, args); | ||
| 180 | |||
| 181 | /* did the controller really set it? */ | ||
| 182 | broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_CFG, 5, args); | ||
| 183 | |||
| 184 | args[0] = 4; /* fsync len */ | ||
| 185 | args[1] = (10 << 8) | 4; /* fend/fbegin len */ | ||
| 186 | args[2] = 10; /* line sync len */ | ||
| 187 | args[3] = (100 << 8) | 4; /* line end/begin len */ | ||
| 188 | args[4] = 6; /* pixel clock cfg */ | ||
| 189 | broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_TMG, 5, args); | ||
| 190 | |||
| 191 | /* setup waveform */ | ||
| 192 | args[0] = 0x886; | ||
| 193 | args[1] = 0; | ||
| 194 | broadsheet_send_cmdargs(par, BS_CMD_RD_WFM_INFO, 2, args); | ||
| 195 | |||
| 196 | broadsheet_send_command(par, BS_CMD_UPD_GDRV_CLR); | ||
| 197 | |||
| 198 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 199 | |||
| 200 | broadsheet_write_reg(par, 0x330, 0x84); | ||
| 201 | |||
| 202 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 203 | |||
| 204 | args[0] = (0x3 << 4); | ||
| 205 | broadsheet_send_cmdargs(par, BS_CMD_LD_IMG, 1, args); | ||
| 206 | |||
| 207 | args[0] = 0x154; | ||
| 208 | broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args); | ||
| 209 | |||
| 210 | broadsheet_burst_write(par, DPY_W*DPY_H/2, | ||
| 211 | (u16 *) par->info->screen_base); | ||
| 212 | |||
| 213 | broadsheet_send_command(par, BS_CMD_LD_IMG_END); | ||
| 214 | |||
| 215 | args[0] = 0x4300; | ||
| 216 | broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args); | ||
| 217 | |||
| 218 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 219 | |||
| 220 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND); | ||
| 221 | |||
| 222 | par->board->wait_for_rdy(par); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void __devinit broadsheet_init(struct broadsheetfb_par *par) | ||
| 226 | { | ||
| 227 | broadsheet_send_command(par, BS_CMD_INIT_SYS_RUN); | ||
| 228 | /* the controller needs a second */ | ||
| 229 | msleep(1000); | ||
| 230 | broadsheet_init_display(par); | ||
| 231 | } | ||
| 232 | |||
| 233 | static void broadsheetfb_dpy_update_pages(struct broadsheetfb_par *par, | ||
| 234 | u16 y1, u16 y2) | ||
| 235 | { | ||
| 236 | u16 args[5]; | ||
| 237 | unsigned char *buf = (unsigned char *)par->info->screen_base; | ||
| 238 | |||
| 239 | /* y1 must be a multiple of 4 so drop the lower bits */ | ||
| 240 | y1 &= 0xFFFC; | ||
| 241 | /* y2 must be a multiple of 4 , but - 1 so up the lower bits */ | ||
| 242 | y2 |= 0x0003; | ||
| 243 | |||
| 244 | args[0] = 0x3 << 4; | ||
| 245 | args[1] = 0; | ||
| 246 | args[2] = y1; | ||
| 247 | args[3] = cpu_to_le16(par->info->var.xres); | ||
| 248 | args[4] = y2; | ||
| 249 | broadsheet_send_cmdargs(par, BS_CMD_LD_IMG_AREA, 5, args); | ||
| 250 | |||
| 251 | args[0] = 0x154; | ||
| 252 | broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args); | ||
| 253 | |||
| 254 | buf += y1 * par->info->var.xres; | ||
| 255 | broadsheet_burst_write(par, ((1 + y2 - y1) * par->info->var.xres)/2, | ||
| 256 | (u16 *) buf); | ||
| 257 | |||
| 258 | broadsheet_send_command(par, BS_CMD_LD_IMG_END); | ||
| 259 | |||
| 260 | args[0] = 0x4300; | ||
| 261 | broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args); | ||
| 262 | |||
| 263 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 264 | |||
| 265 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND); | ||
| 266 | |||
| 267 | par->board->wait_for_rdy(par); | ||
| 268 | |||
| 269 | } | ||
| 270 | |||
| 271 | static void broadsheetfb_dpy_update(struct broadsheetfb_par *par) | ||
| 272 | { | ||
| 273 | u16 args[5]; | ||
| 274 | |||
| 275 | args[0] = 0x3 << 4; | ||
| 276 | broadsheet_send_cmdargs(par, BS_CMD_LD_IMG, 1, args); | ||
| 277 | |||
| 278 | args[0] = 0x154; | ||
| 279 | broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args); | ||
| 280 | broadsheet_burst_write(par, DPY_W*DPY_H/2, | ||
| 281 | (u16 *) par->info->screen_base); | ||
| 282 | |||
| 283 | broadsheet_send_command(par, BS_CMD_LD_IMG_END); | ||
| 284 | |||
| 285 | args[0] = 0x4300; | ||
| 286 | broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args); | ||
| 287 | |||
| 288 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 289 | |||
| 290 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND); | ||
| 291 | |||
| 292 | par->board->wait_for_rdy(par); | ||
| 293 | |||
| 294 | } | ||
| 295 | |||
| 296 | /* this is called back from the deferred io workqueue */ | ||
| 297 | static void broadsheetfb_dpy_deferred_io(struct fb_info *info, | ||
| 298 | struct list_head *pagelist) | ||
| 299 | { | ||
| 300 | u16 y1 = 0, h = 0; | ||
| 301 | int prev_index = -1; | ||
| 302 | struct page *cur; | ||
| 303 | struct fb_deferred_io *fbdefio = info->fbdefio; | ||
| 304 | int h_inc; | ||
| 305 | u16 yres = info->var.yres; | ||
| 306 | u16 xres = info->var.xres; | ||
| 307 | |||
| 308 | /* height increment is fixed per page */ | ||
| 309 | h_inc = DIV_ROUND_UP(PAGE_SIZE , xres); | ||
| 310 | |||
| 311 | /* walk the written page list and swizzle the data */ | ||
| 312 | list_for_each_entry(cur, &fbdefio->pagelist, lru) { | ||
| 313 | if (prev_index < 0) { | ||
| 314 | /* just starting so assign first page */ | ||
| 315 | y1 = (cur->index << PAGE_SHIFT) / xres; | ||
| 316 | h = h_inc; | ||
| 317 | } else if ((prev_index + 1) == cur->index) { | ||
| 318 | /* this page is consecutive so increase our height */ | ||
| 319 | h += h_inc; | ||
| 320 | } else { | ||
| 321 | /* page not consecutive, issue previous update first */ | ||
| 322 | broadsheetfb_dpy_update_pages(info->par, y1, y1 + h); | ||
| 323 | /* start over with our non consecutive page */ | ||
| 324 | y1 = (cur->index << PAGE_SHIFT) / xres; | ||
| 325 | h = h_inc; | ||
| 326 | } | ||
| 327 | prev_index = cur->index; | ||
| 328 | } | ||
| 329 | |||
| 330 | /* if we still have any pages to update we do so now */ | ||
| 331 | if (h >= yres) { | ||
| 332 | /* its a full screen update, just do it */ | ||
| 333 | broadsheetfb_dpy_update(info->par); | ||
| 334 | } else { | ||
| 335 | broadsheetfb_dpy_update_pages(info->par, y1, | ||
| 336 | min((u16) (y1 + h), yres)); | ||
| 337 | } | ||
| 338 | } | ||
| 339 | |||
| 340 | static void broadsheetfb_fillrect(struct fb_info *info, | ||
| 341 | const struct fb_fillrect *rect) | ||
| 342 | { | ||
| 343 | struct broadsheetfb_par *par = info->par; | ||
| 344 | |||
| 345 | sys_fillrect(info, rect); | ||
| 346 | |||
| 347 | broadsheetfb_dpy_update(par); | ||
| 348 | } | ||
| 349 | |||
| 350 | static void broadsheetfb_copyarea(struct fb_info *info, | ||
| 351 | const struct fb_copyarea *area) | ||
| 352 | { | ||
| 353 | struct broadsheetfb_par *par = info->par; | ||
| 354 | |||
| 355 | sys_copyarea(info, area); | ||
| 356 | |||
| 357 | broadsheetfb_dpy_update(par); | ||
| 358 | } | ||
| 359 | |||
| 360 | static void broadsheetfb_imageblit(struct fb_info *info, | ||
| 361 | const struct fb_image *image) | ||
| 362 | { | ||
| 363 | struct broadsheetfb_par *par = info->par; | ||
| 364 | |||
| 365 | sys_imageblit(info, image); | ||
| 366 | |||
| 367 | broadsheetfb_dpy_update(par); | ||
| 368 | } | ||
| 369 | |||
| 370 | /* | ||
| 371 | * this is the slow path from userspace. they can seek and write to | ||
| 372 | * the fb. it's inefficient to do anything less than a full screen draw | ||
| 373 | */ | ||
| 374 | static ssize_t broadsheetfb_write(struct fb_info *info, const char __user *buf, | ||
| 375 | size_t count, loff_t *ppos) | ||
| 376 | { | ||
| 377 | struct broadsheetfb_par *par = info->par; | ||
| 378 | unsigned long p = *ppos; | ||
| 379 | void *dst; | ||
| 380 | int err = 0; | ||
| 381 | unsigned long total_size; | ||
| 382 | |||
| 383 | if (info->state != FBINFO_STATE_RUNNING) | ||
| 384 | return -EPERM; | ||
| 385 | |||
| 386 | total_size = info->fix.smem_len; | ||
| 387 | |||
| 388 | if (p > total_size) | ||
| 389 | return -EFBIG; | ||
| 390 | |||
| 391 | if (count > total_size) { | ||
| 392 | err = -EFBIG; | ||
| 393 | count = total_size; | ||
| 394 | } | ||
| 395 | |||
| 396 | if (count + p > total_size) { | ||
| 397 | if (!err) | ||
| 398 | err = -ENOSPC; | ||
| 399 | |||
| 400 | count = total_size - p; | ||
| 401 | } | ||
| 402 | |||
| 403 | dst = (void *)(info->screen_base + p); | ||
| 404 | |||
| 405 | if (copy_from_user(dst, buf, count)) | ||
| 406 | err = -EFAULT; | ||
| 407 | |||
| 408 | if (!err) | ||
| 409 | *ppos += count; | ||
| 410 | |||
| 411 | broadsheetfb_dpy_update(par); | ||
| 412 | |||
| 413 | return (err) ? err : count; | ||
| 414 | } | ||
| 415 | |||
| 416 | static struct fb_ops broadsheetfb_ops = { | ||
| 417 | .owner = THIS_MODULE, | ||
| 418 | .fb_read = fb_sys_read, | ||
| 419 | .fb_write = broadsheetfb_write, | ||
| 420 | .fb_fillrect = broadsheetfb_fillrect, | ||
| 421 | .fb_copyarea = broadsheetfb_copyarea, | ||
| 422 | .fb_imageblit = broadsheetfb_imageblit, | ||
| 423 | }; | ||
| 424 | |||
| 425 | static struct fb_deferred_io broadsheetfb_defio = { | ||
| 426 | .delay = HZ/4, | ||
| 427 | .deferred_io = broadsheetfb_dpy_deferred_io, | ||
| 428 | }; | ||
| 429 | |||
| 430 | static int __devinit broadsheetfb_probe(struct platform_device *dev) | ||
| 431 | { | ||
| 432 | struct fb_info *info; | ||
| 433 | struct broadsheet_board *board; | ||
| 434 | int retval = -ENOMEM; | ||
| 435 | int videomemorysize; | ||
| 436 | unsigned char *videomemory; | ||
| 437 | struct broadsheetfb_par *par; | ||
| 438 | int i; | ||
| 439 | |||
| 440 | /* pick up board specific routines */ | ||
| 441 | board = dev->dev.platform_data; | ||
| 442 | if (!board) | ||
| 443 | return -EINVAL; | ||
| 444 | |||
| 445 | /* try to count device specific driver, if can't, platform recalls */ | ||
| 446 | if (!try_module_get(board->owner)) | ||
| 447 | return -ENODEV; | ||
| 448 | |||
| 449 | info = framebuffer_alloc(sizeof(struct broadsheetfb_par), &dev->dev); | ||
| 450 | if (!info) | ||
| 451 | goto err; | ||
| 452 | |||
| 453 | videomemorysize = (DPY_W*DPY_H); | ||
| 454 | videomemory = vmalloc(videomemorysize); | ||
| 455 | if (!videomemory) | ||
| 456 | goto err_fb_rel; | ||
| 457 | |||
| 458 | memset(videomemory, 0, videomemorysize); | ||
| 459 | |||
| 460 | info->screen_base = (char *)videomemory; | ||
| 461 | info->fbops = &broadsheetfb_ops; | ||
| 462 | |||
| 463 | info->var = broadsheetfb_var; | ||
| 464 | info->fix = broadsheetfb_fix; | ||
| 465 | info->fix.smem_len = videomemorysize; | ||
| 466 | par = info->par; | ||
| 467 | par->info = info; | ||
| 468 | par->board = board; | ||
| 469 | par->write_reg = broadsheet_write_reg; | ||
| 470 | par->read_reg = broadsheet_read_reg; | ||
| 471 | init_waitqueue_head(&par->waitq); | ||
| 472 | |||
| 473 | info->flags = FBINFO_FLAG_DEFAULT; | ||
| 474 | |||
| 475 | info->fbdefio = &broadsheetfb_defio; | ||
| 476 | fb_deferred_io_init(info); | ||
| 477 | |||
| 478 | retval = fb_alloc_cmap(&info->cmap, 16, 0); | ||
| 479 | if (retval < 0) { | ||
| 480 | dev_err(&dev->dev, "Failed to allocate colormap\n"); | ||
| 481 | goto err_vfree; | ||
| 482 | } | ||
| 483 | |||
| 484 | /* set cmap */ | ||
| 485 | for (i = 0; i < 16; i++) | ||
| 486 | info->cmap.red[i] = (((2*i)+1)*(0xFFFF))/32; | ||
| 487 | memcpy(info->cmap.green, info->cmap.red, sizeof(u16)*16); | ||
| 488 | memcpy(info->cmap.blue, info->cmap.red, sizeof(u16)*16); | ||
| 489 | |||
| 490 | retval = par->board->setup_irq(info); | ||
| 491 | if (retval < 0) | ||
| 492 | goto err_cmap; | ||
| 493 | |||
| 494 | /* this inits the dpy */ | ||
| 495 | retval = board->init(par); | ||
| 496 | if (retval < 0) | ||
| 497 | goto err_free_irq; | ||
| 498 | |||
| 499 | broadsheet_init(par); | ||
| 500 | |||
| 501 | retval = register_framebuffer(info); | ||
| 502 | if (retval < 0) | ||
| 503 | goto err_free_irq; | ||
| 504 | platform_set_drvdata(dev, info); | ||
| 505 | |||
| 506 | printk(KERN_INFO | ||
| 507 | "fb%d: Broadsheet frame buffer, using %dK of video memory\n", | ||
| 508 | info->node, videomemorysize >> 10); | ||
| 509 | |||
| 510 | |||
| 511 | return 0; | ||
| 512 | |||
| 513 | err_free_irq: | ||
| 514 | board->cleanup(par); | ||
| 515 | err_cmap: | ||
| 516 | fb_dealloc_cmap(&info->cmap); | ||
| 517 | err_vfree: | ||
| 518 | vfree(videomemory); | ||
| 519 | err_fb_rel: | ||
| 520 | framebuffer_release(info); | ||
| 521 | err: | ||
| 522 | module_put(board->owner); | ||
| 523 | return retval; | ||
| 524 | |||
| 525 | } | ||
| 526 | |||
| 527 | static int __devexit broadsheetfb_remove(struct platform_device *dev) | ||
| 528 | { | ||
| 529 | struct fb_info *info = platform_get_drvdata(dev); | ||
| 530 | |||
| 531 | if (info) { | ||
| 532 | struct broadsheetfb_par *par = info->par; | ||
| 533 | unregister_framebuffer(info); | ||
| 534 | fb_deferred_io_cleanup(info); | ||
| 535 | par->board->cleanup(par); | ||
| 536 | fb_dealloc_cmap(&info->cmap); | ||
| 537 | vfree((void *)info->screen_base); | ||
| 538 | module_put(par->board->owner); | ||
| 539 | framebuffer_release(info); | ||
| 540 | } | ||
| 541 | return 0; | ||
| 542 | } | ||
| 543 | |||
| 544 | static struct platform_driver broadsheetfb_driver = { | ||
| 545 | .probe = broadsheetfb_probe, | ||
| 546 | .remove = broadsheetfb_remove, | ||
| 547 | .driver = { | ||
| 548 | .owner = THIS_MODULE, | ||
| 549 | .name = "broadsheetfb", | ||
| 550 | }, | ||
| 551 | }; | ||
| 552 | |||
| 553 | static int __init broadsheetfb_init(void) | ||
| 554 | { | ||
| 555 | return platform_driver_register(&broadsheetfb_driver); | ||
| 556 | } | ||
| 557 | |||
| 558 | static void __exit broadsheetfb_exit(void) | ||
| 559 | { | ||
| 560 | platform_driver_unregister(&broadsheetfb_driver); | ||
| 561 | } | ||
| 562 | |||
| 563 | module_init(broadsheetfb_init); | ||
| 564 | module_exit(broadsheetfb_exit); | ||
| 565 | |||
| 566 | MODULE_DESCRIPTION("fbdev driver for Broadsheet controller"); | ||
| 567 | MODULE_AUTHOR("Jaya Kumar"); | ||
| 568 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c index 7a9e42e3a9a9..83c5cefc266c 100644 --- a/drivers/video/cyber2000fb.c +++ b/drivers/video/cyber2000fb.c | |||
| @@ -46,8 +46,8 @@ | |||
| 46 | #include <linux/fb.h> | 46 | #include <linux/fb.h> |
| 47 | #include <linux/pci.h> | 47 | #include <linux/pci.h> |
| 48 | #include <linux/init.h> | 48 | #include <linux/init.h> |
| 49 | #include <linux/io.h> | ||
| 49 | 50 | ||
| 50 | #include <asm/io.h> | ||
| 51 | #include <asm/pgtable.h> | 51 | #include <asm/pgtable.h> |
| 52 | #include <asm/system.h> | 52 | #include <asm/system.h> |
| 53 | 53 | ||
| @@ -1425,7 +1425,7 @@ static void cyberpro_common_resume(struct cfb_info *cfb) | |||
| 1425 | 1425 | ||
| 1426 | #ifdef CONFIG_ARCH_SHARK | 1426 | #ifdef CONFIG_ARCH_SHARK |
| 1427 | 1427 | ||
| 1428 | #include <mach/hardware.h> | 1428 | #include <mach/framebuffer.h> |
| 1429 | 1429 | ||
| 1430 | static int __devinit cyberpro_vl_probe(void) | 1430 | static int __devinit cyberpro_vl_probe(void) |
| 1431 | { | 1431 | { |
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index d58c68cd456e..15a0ee6d8e23 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | * linux-arm-kernel@lists.arm.linux.org.uk | 14 | * linux-arm-kernel@lists.arm.linux.org.uk |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | |||
| 18 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 19 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 20 | #include <linux/errno.h> | 19 | #include <linux/errno.h> |
| @@ -27,9 +26,11 @@ | |||
| 27 | #include <linux/init.h> | 26 | #include <linux/init.h> |
| 28 | #include <linux/ioport.h> | 27 | #include <linux/ioport.h> |
| 29 | #include <linux/cpufreq.h> | 28 | #include <linux/cpufreq.h> |
| 29 | #include <linux/clk.h> | ||
| 30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
| 31 | #include <linux/dma-mapping.h> | 31 | #include <linux/dma-mapping.h> |
| 32 | #include <linux/io.h> | 32 | #include <linux/io.h> |
| 33 | #include <linux/math64.h> | ||
| 33 | 34 | ||
| 34 | #include <mach/imxfb.h> | 35 | #include <mach/imxfb.h> |
| 35 | 36 | ||
| @@ -44,7 +45,12 @@ | |||
| 44 | 45 | ||
| 45 | #define LCDC_SIZE 0x04 | 46 | #define LCDC_SIZE 0x04 |
| 46 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | 47 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) |
| 48 | |||
| 49 | #ifdef CONFIG_ARCH_MX1 | ||
| 47 | #define SIZE_YMAX(y) ((y) & 0x1ff) | 50 | #define SIZE_YMAX(y) ((y) & 0x1ff) |
| 51 | #else | ||
| 52 | #define SIZE_YMAX(y) ((y) & 0x3ff) | ||
| 53 | #endif | ||
| 48 | 54 | ||
| 49 | #define LCDC_VPW 0x08 | 55 | #define LCDC_VPW 0x08 |
| 50 | #define VPW_VPW(x) ((x) & 0x3ff) | 56 | #define VPW_VPW(x) ((x) & 0x3ff) |
| @@ -54,7 +60,12 @@ | |||
| 54 | #define CPOS_CC0 (1<<30) | 60 | #define CPOS_CC0 (1<<30) |
| 55 | #define CPOS_OP (1<<28) | 61 | #define CPOS_OP (1<<28) |
| 56 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | 62 | #define CPOS_CXP(x) (((x) & 3ff) << 16) |
| 63 | |||
| 64 | #ifdef CONFIG_ARCH_MX1 | ||
| 57 | #define CPOS_CYP(y) ((y) & 0x1ff) | 65 | #define CPOS_CYP(y) ((y) & 0x1ff) |
| 66 | #else | ||
| 67 | #define CPOS_CYP(y) ((y) & 0x3ff) | ||
| 68 | #endif | ||
| 58 | 69 | ||
| 59 | #define LCDC_LCWHB 0x10 | 70 | #define LCDC_LCWHB 0x10 |
| 60 | #define LCWHB_BK_EN (1<<31) | 71 | #define LCWHB_BK_EN (1<<31) |
| @@ -63,9 +74,16 @@ | |||
| 63 | #define LCWHB_BD(x) ((x) & 0xff) | 74 | #define LCWHB_BD(x) ((x) & 0xff) |
| 64 | 75 | ||
| 65 | #define LCDC_LCHCC 0x14 | 76 | #define LCDC_LCHCC 0x14 |
| 77 | |||
| 78 | #ifdef CONFIG_ARCH_MX1 | ||
| 66 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) | 79 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) |
| 67 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) | 80 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) |
| 68 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) | 81 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) |
| 82 | #else | ||
| 83 | #define LCHCC_CUR_COL_R(r) (((r) & 0x3f) << 12) | ||
| 84 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 6) | ||
| 85 | #define LCHCC_CUR_COL_B(b) ((b) & 0x3f) | ||
| 86 | #endif | ||
| 69 | 87 | ||
| 70 | #define LCDC_PCR 0x18 | 88 | #define LCDC_PCR 0x18 |
| 71 | 89 | ||
| @@ -92,7 +110,13 @@ | |||
| 92 | /* bit fields in imxfb.h */ | 110 | /* bit fields in imxfb.h */ |
| 93 | 111 | ||
| 94 | #define LCDC_RMCR 0x34 | 112 | #define LCDC_RMCR 0x34 |
| 113 | |||
| 114 | #ifdef CONFIG_ARCH_MX1 | ||
| 95 | #define RMCR_LCDC_EN (1<<1) | 115 | #define RMCR_LCDC_EN (1<<1) |
| 116 | #else | ||
| 117 | #define RMCR_LCDC_EN 0 | ||
| 118 | #endif | ||
| 119 | |||
| 96 | #define RMCR_SELF_REF (1<<0) | 120 | #define RMCR_SELF_REF (1<<0) |
| 97 | 121 | ||
| 98 | #define LCDC_LCDICR 0x38 | 122 | #define LCDC_LCDICR 0x38 |
| @@ -119,6 +143,7 @@ struct imxfb_rgb { | |||
| 119 | struct imxfb_info { | 143 | struct imxfb_info { |
| 120 | struct platform_device *pdev; | 144 | struct platform_device *pdev; |
| 121 | void __iomem *regs; | 145 | void __iomem *regs; |
| 146 | struct clk *clk; | ||
| 122 | 147 | ||
| 123 | u_int max_bpp; | 148 | u_int max_bpp; |
| 124 | u_int max_xres; | 149 | u_int max_xres; |
| @@ -159,6 +184,17 @@ struct imxfb_info { | |||
| 159 | #define MIN_XRES 64 | 184 | #define MIN_XRES 64 |
| 160 | #define MIN_YRES 64 | 185 | #define MIN_YRES 64 |
| 161 | 186 | ||
| 187 | /* Actually this really is 18bit support, the lowest 2 bits of each colour | ||
| 188 | * are unused in hardware. We claim to have 24bit support to make software | ||
| 189 | * like X work, which does not support 18bit. | ||
| 190 | */ | ||
| 191 | static struct imxfb_rgb def_rgb_18 = { | ||
| 192 | .red = {.offset = 16, .length = 8,}, | ||
| 193 | .green = {.offset = 8, .length = 8,}, | ||
| 194 | .blue = {.offset = 0, .length = 8,}, | ||
| 195 | .transp = {.offset = 0, .length = 0,}, | ||
| 196 | }; | ||
| 197 | |||
| 162 | static struct imxfb_rgb def_rgb_16_tft = { | 198 | static struct imxfb_rgb def_rgb_16_tft = { |
| 163 | .red = {.offset = 11, .length = 5,}, | 199 | .red = {.offset = 11, .length = 5,}, |
| 164 | .green = {.offset = 5, .length = 6,}, | 200 | .green = {.offset = 5, .length = 6,}, |
| @@ -286,9 +322,12 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
| 286 | 322 | ||
| 287 | pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); | 323 | pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); |
| 288 | switch (var->bits_per_pixel) { | 324 | switch (var->bits_per_pixel) { |
| 325 | case 32: | ||
| 326 | rgb = &def_rgb_18; | ||
| 327 | break; | ||
| 289 | case 16: | 328 | case 16: |
| 290 | default: | 329 | default: |
| 291 | if (readl(fbi->regs + LCDC_PCR) & PCR_TFT) | 330 | if (fbi->pcr & PCR_TFT) |
| 292 | rgb = &def_rgb_16_tft; | 331 | rgb = &def_rgb_16_tft; |
| 293 | else | 332 | else |
| 294 | rgb = &def_rgb_16_stn; | 333 | rgb = &def_rgb_16_stn; |
| @@ -327,9 +366,7 @@ static int imxfb_set_par(struct fb_info *info) | |||
| 327 | struct imxfb_info *fbi = info->par; | 366 | struct imxfb_info *fbi = info->par; |
| 328 | struct fb_var_screeninfo *var = &info->var; | 367 | struct fb_var_screeninfo *var = &info->var; |
| 329 | 368 | ||
| 330 | pr_debug("set_par\n"); | 369 | if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32) |
| 331 | |||
| 332 | if (var->bits_per_pixel == 16) | ||
| 333 | info->fix.visual = FB_VISUAL_TRUECOLOR; | 370 | info->fix.visual = FB_VISUAL_TRUECOLOR; |
| 334 | else if (!fbi->cmap_static) | 371 | else if (!fbi->cmap_static) |
| 335 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | 372 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
| @@ -354,10 +391,6 @@ static void imxfb_enable_controller(struct imxfb_info *fbi) | |||
| 354 | { | 391 | { |
| 355 | pr_debug("Enabling LCD controller\n"); | 392 | pr_debug("Enabling LCD controller\n"); |
| 356 | 393 | ||
| 357 | /* initialize LCDC */ | ||
| 358 | writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN, | ||
| 359 | fbi->regs + LCDC_RMCR); /* just to be safe... */ | ||
| 360 | |||
| 361 | writel(fbi->screen_dma, fbi->regs + LCDC_SSA); | 394 | writel(fbi->screen_dma, fbi->regs + LCDC_SSA); |
| 362 | 395 | ||
| 363 | /* physical screen start address */ | 396 | /* physical screen start address */ |
| @@ -373,6 +406,8 @@ static void imxfb_enable_controller(struct imxfb_info *fbi) | |||
| 373 | 406 | ||
| 374 | writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR); | 407 | writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR); |
| 375 | 408 | ||
| 409 | clk_enable(fbi->clk); | ||
| 410 | |||
| 376 | if (fbi->backlight_power) | 411 | if (fbi->backlight_power) |
| 377 | fbi->backlight_power(1); | 412 | fbi->backlight_power(1); |
| 378 | if (fbi->lcd_power) | 413 | if (fbi->lcd_power) |
| @@ -388,6 +423,8 @@ static void imxfb_disable_controller(struct imxfb_info *fbi) | |||
| 388 | if (fbi->lcd_power) | 423 | if (fbi->lcd_power) |
| 389 | fbi->lcd_power(0); | 424 | fbi->lcd_power(0); |
| 390 | 425 | ||
| 426 | clk_disable(fbi->clk); | ||
| 427 | |||
| 391 | writel(0, fbi->regs + LCDC_RMCR); | 428 | writel(0, fbi->regs + LCDC_RMCR); |
| 392 | } | 429 | } |
| 393 | 430 | ||
| @@ -431,6 +468,9 @@ static struct fb_ops imxfb_ops = { | |||
| 431 | static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info) | 468 | static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info) |
| 432 | { | 469 | { |
| 433 | struct imxfb_info *fbi = info->par; | 470 | struct imxfb_info *fbi = info->par; |
| 471 | unsigned int pcr, lcd_clk; | ||
| 472 | unsigned long long tmp; | ||
| 473 | |||
| 434 | pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", | 474 | pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", |
| 435 | var->xres, var->hsync_len, | 475 | var->xres, var->hsync_len, |
| 436 | var->left_margin, var->right_margin); | 476 | var->left_margin, var->right_margin); |
| @@ -465,9 +505,9 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf | |||
| 465 | info->fix.id, var->lower_margin); | 505 | info->fix.id, var->lower_margin); |
| 466 | #endif | 506 | #endif |
| 467 | 507 | ||
| 468 | writel(HCR_H_WIDTH(var->hsync_len) | | 508 | writel(HCR_H_WIDTH(var->hsync_len - 1) | |
| 469 | HCR_H_WAIT_1(var->right_margin) | | 509 | HCR_H_WAIT_1(var->right_margin - 1) | |
| 470 | HCR_H_WAIT_2(var->left_margin), | 510 | HCR_H_WAIT_2(var->left_margin - 3), |
| 471 | fbi->regs + LCDC_HCR); | 511 | fbi->regs + LCDC_HCR); |
| 472 | 512 | ||
| 473 | writel(VCR_V_WIDTH(var->vsync_len) | | 513 | writel(VCR_V_WIDTH(var->vsync_len) | |
| @@ -477,7 +517,23 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf | |||
| 477 | 517 | ||
| 478 | writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres), | 518 | writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres), |
| 479 | fbi->regs + LCDC_SIZE); | 519 | fbi->regs + LCDC_SIZE); |
| 480 | writel(fbi->pcr, fbi->regs + LCDC_PCR); | 520 | |
| 521 | lcd_clk = clk_get_rate(fbi->clk); | ||
| 522 | tmp = var->pixclock * (unsigned long long)lcd_clk; | ||
| 523 | do_div(tmp, 1000000); | ||
| 524 | if (do_div(tmp, 1000000) > 500000) | ||
| 525 | tmp++; | ||
| 526 | pcr = (unsigned int)tmp; | ||
| 527 | if (--pcr > 0x3F) { | ||
| 528 | pcr = 0x3F; | ||
| 529 | printk(KERN_WARNING "Must limit pixel clock to %uHz\n", | ||
| 530 | lcd_clk / pcr); | ||
| 531 | } | ||
| 532 | |||
| 533 | /* add sync polarities */ | ||
| 534 | pcr |= fbi->pcr & ~0x3F; | ||
| 535 | |||
| 536 | writel(pcr, fbi->regs + LCDC_PCR); | ||
| 481 | writel(fbi->pwmr, fbi->regs + LCDC_PWMR); | 537 | writel(fbi->pwmr, fbi->regs + LCDC_PWMR); |
| 482 | writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); | 538 | writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); |
| 483 | writel(fbi->dmacr, fbi->regs + LCDC_DMACR); | 539 | writel(fbi->dmacr, fbi->regs + LCDC_DMACR); |
| @@ -619,6 +675,13 @@ static int __init imxfb_probe(struct platform_device *pdev) | |||
| 619 | goto failed_req; | 675 | goto failed_req; |
| 620 | } | 676 | } |
| 621 | 677 | ||
| 678 | fbi->clk = clk_get(&pdev->dev, NULL); | ||
| 679 | if (IS_ERR(fbi->clk)) { | ||
| 680 | ret = PTR_ERR(fbi->clk);; | ||
| 681 | dev_err(&pdev->dev, "unable to get clock: %d\n", ret); | ||
| 682 | goto failed_getclock; | ||
| 683 | } | ||
| 684 | |||
| 622 | fbi->regs = ioremap(res->start, resource_size(res)); | 685 | fbi->regs = ioremap(res->start, resource_size(res)); |
| 623 | if (fbi->regs == NULL) { | 686 | if (fbi->regs == NULL) { |
| 624 | printk(KERN_ERR"Cannot map frame buffer registers\n"); | 687 | printk(KERN_ERR"Cannot map frame buffer registers\n"); |
| @@ -650,6 +713,12 @@ static int __init imxfb_probe(struct platform_device *pdev) | |||
| 650 | info->fix.smem_start = fbi->screen_dma; | 713 | info->fix.smem_start = fbi->screen_dma; |
| 651 | } | 714 | } |
| 652 | 715 | ||
| 716 | if (pdata->init) { | ||
| 717 | ret = pdata->init(fbi->pdev); | ||
| 718 | if (ret) | ||
| 719 | goto failed_platform_init; | ||
| 720 | } | ||
| 721 | |||
| 653 | /* | 722 | /* |
| 654 | * This makes sure that our colour bitfield | 723 | * This makes sure that our colour bitfield |
| 655 | * descriptors are correctly initialised. | 724 | * descriptors are correctly initialised. |
| @@ -674,10 +743,15 @@ static int __init imxfb_probe(struct platform_device *pdev) | |||
| 674 | failed_register: | 743 | failed_register: |
| 675 | fb_dealloc_cmap(&info->cmap); | 744 | fb_dealloc_cmap(&info->cmap); |
| 676 | failed_cmap: | 745 | failed_cmap: |
| 746 | if (pdata->exit) | ||
| 747 | pdata->exit(fbi->pdev); | ||
| 748 | failed_platform_init: | ||
| 677 | if (!pdata->fixed_screen_cpu) | 749 | if (!pdata->fixed_screen_cpu) |
| 678 | dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, | 750 | dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, |
| 679 | fbi->map_dma); | 751 | fbi->map_dma); |
| 680 | failed_map: | 752 | failed_map: |
| 753 | clk_put(fbi->clk); | ||
| 754 | failed_getclock: | ||
| 681 | iounmap(fbi->regs); | 755 | iounmap(fbi->regs); |
| 682 | failed_ioremap: | 756 | failed_ioremap: |
| 683 | release_mem_region(res->start, res->end - res->start); | 757 | release_mem_region(res->start, res->end - res->start); |
| @@ -691,6 +765,7 @@ failed_init: | |||
| 691 | 765 | ||
| 692 | static int __devexit imxfb_remove(struct platform_device *pdev) | 766 | static int __devexit imxfb_remove(struct platform_device *pdev) |
| 693 | { | 767 | { |
| 768 | struct imx_fb_platform_data *pdata; | ||
| 694 | struct fb_info *info = platform_get_drvdata(pdev); | 769 | struct fb_info *info = platform_get_drvdata(pdev); |
| 695 | struct imxfb_info *fbi = info->par; | 770 | struct imxfb_info *fbi = info->par; |
| 696 | struct resource *res; | 771 | struct resource *res; |
| @@ -701,12 +776,19 @@ static int __devexit imxfb_remove(struct platform_device *pdev) | |||
| 701 | 776 | ||
| 702 | unregister_framebuffer(info); | 777 | unregister_framebuffer(info); |
| 703 | 778 | ||
| 779 | pdata = pdev->dev.platform_data; | ||
| 780 | if (pdata->exit) | ||
| 781 | pdata->exit(fbi->pdev); | ||
| 782 | |||
| 704 | fb_dealloc_cmap(&info->cmap); | 783 | fb_dealloc_cmap(&info->cmap); |
| 705 | kfree(info->pseudo_palette); | 784 | kfree(info->pseudo_palette); |
| 706 | framebuffer_release(info); | 785 | framebuffer_release(info); |
| 707 | 786 | ||
| 708 | iounmap(fbi->regs); | 787 | iounmap(fbi->regs); |
| 709 | release_mem_region(res->start, res->end - res->start + 1); | 788 | release_mem_region(res->start, res->end - res->start + 1); |
| 789 | clk_disable(fbi->clk); | ||
| 790 | clk_put(fbi->clk); | ||
| 791 | |||
| 710 | platform_set_drvdata(pdev, NULL); | 792 | platform_set_drvdata(pdev, NULL); |
| 711 | 793 | ||
| 712 | return 0; | 794 | return 0; |
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index 8a75d05f4334..fa1a512ce030 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c | |||
| @@ -34,240 +34,240 @@ | |||
| 34 | #include <asm/io.h> | 34 | #include <asm/io.h> |
| 35 | #include <asm/uaccess.h> | 35 | #include <asm/uaccess.h> |
| 36 | 36 | ||
| 37 | #define MX3FB_NAME "mx3_sdc_fb" | 37 | #define MX3FB_NAME "mx3_sdc_fb" |
| 38 | 38 | ||
| 39 | #define MX3FB_REG_OFFSET 0xB4 | 39 | #define MX3FB_REG_OFFSET 0xB4 |
| 40 | 40 | ||
| 41 | /* SDC Registers */ | 41 | /* SDC Registers */ |
| 42 | #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET) | 42 | #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET) |
| 43 | #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET) | 43 | #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET) |
| 44 | #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET) | 44 | #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET) |
| 45 | #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET) | 45 | #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET) |
| 46 | #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET) | 46 | #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET) |
| 47 | #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET) | 47 | #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET) |
| 48 | #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET) | 48 | #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET) |
| 49 | #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET) | 49 | #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET) |
| 50 | #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET) | 50 | #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET) |
| 51 | #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET) | 51 | #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET) |
| 52 | #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET) | 52 | #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET) |
| 53 | 53 | ||
| 54 | /* Register bits */ | 54 | /* Register bits */ |
| 55 | #define SDC_COM_TFT_COLOR 0x00000001UL | 55 | #define SDC_COM_TFT_COLOR 0x00000001UL |
| 56 | #define SDC_COM_FG_EN 0x00000010UL | 56 | #define SDC_COM_FG_EN 0x00000010UL |
| 57 | #define SDC_COM_GWSEL 0x00000020UL | 57 | #define SDC_COM_GWSEL 0x00000020UL |
| 58 | #define SDC_COM_GLB_A 0x00000040UL | 58 | #define SDC_COM_GLB_A 0x00000040UL |
| 59 | #define SDC_COM_KEY_COLOR_G 0x00000080UL | 59 | #define SDC_COM_KEY_COLOR_G 0x00000080UL |
| 60 | #define SDC_COM_BG_EN 0x00000200UL | 60 | #define SDC_COM_BG_EN 0x00000200UL |
| 61 | #define SDC_COM_SHARP 0x00001000UL | 61 | #define SDC_COM_SHARP 0x00001000UL |
| 62 | 62 | ||
| 63 | #define SDC_V_SYNC_WIDTH_L 0x00000001UL | 63 | #define SDC_V_SYNC_WIDTH_L 0x00000001UL |
| 64 | 64 | ||
| 65 | /* Display Interface registers */ | 65 | /* Display Interface registers */ |
| 66 | #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET) | 66 | #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET) |
| 67 | #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET) | 67 | #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET) |
| 68 | #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET) | 68 | #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET) |
| 69 | #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET) | 69 | #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET) |
| 70 | #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET) | 70 | #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET) |
| 71 | #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET) | 71 | #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET) |
| 72 | #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET) | 72 | #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET) |
| 73 | #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET) | 73 | #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET) |
| 74 | #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET) | 74 | #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET) |
| 75 | #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET) | 75 | #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET) |
| 76 | #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET) | 76 | #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET) |
| 77 | #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET) | 77 | #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET) |
| 78 | #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET) | 78 | #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET) |
| 79 | #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET) | 79 | #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET) |
| 80 | #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET) | 80 | #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET) |
| 81 | #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET) | 81 | #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET) |
| 82 | #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET) | 82 | #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET) |
| 83 | #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET) | 83 | #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET) |
| 84 | #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET) | 84 | #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET) |
| 85 | #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET) | 85 | #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET) |
| 86 | #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET) | 86 | #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET) |
| 87 | #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET) | 87 | #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET) |
| 88 | #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET) | 88 | #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET) |
| 89 | #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET) | 89 | #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET) |
| 90 | #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET) | 90 | #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET) |
| 91 | #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET) | 91 | #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET) |
| 92 | #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET) | 92 | #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET) |
| 93 | #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET) | 93 | #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET) |
| 94 | #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET) | 94 | #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET) |
| 95 | #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET) | 95 | #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET) |
| 96 | #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET) | 96 | #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET) |
| 97 | #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET) | 97 | #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET) |
| 98 | #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET) | 98 | #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET) |
| 99 | #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET) | 99 | #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET) |
| 100 | #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET) | 100 | #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET) |
| 101 | #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET) | 101 | #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET) |
| 102 | #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET) | 102 | #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET) |
| 103 | #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET) | 103 | #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET) |
| 104 | #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET) | 104 | #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET) |
| 105 | 105 | ||
| 106 | /* DI_DISP_SIG_POL bits */ | 106 | /* DI_DISP_SIG_POL bits */ |
| 107 | #define DI_D3_VSYNC_POL_SHIFT 28 | 107 | #define DI_D3_VSYNC_POL_SHIFT 28 |
| 108 | #define DI_D3_HSYNC_POL_SHIFT 27 | 108 | #define DI_D3_HSYNC_POL_SHIFT 27 |
| 109 | #define DI_D3_DRDY_SHARP_POL_SHIFT 26 | 109 | #define DI_D3_DRDY_SHARP_POL_SHIFT 26 |
| 110 | #define DI_D3_CLK_POL_SHIFT 25 | 110 | #define DI_D3_CLK_POL_SHIFT 25 |
| 111 | #define DI_D3_DATA_POL_SHIFT 24 | 111 | #define DI_D3_DATA_POL_SHIFT 24 |
| 112 | 112 | ||
| 113 | /* DI_DISP_IF_CONF bits */ | 113 | /* DI_DISP_IF_CONF bits */ |
| 114 | #define DI_D3_CLK_IDLE_SHIFT 26 | 114 | #define DI_D3_CLK_IDLE_SHIFT 26 |
| 115 | #define DI_D3_CLK_SEL_SHIFT 25 | 115 | #define DI_D3_CLK_SEL_SHIFT 25 |
| 116 | #define DI_D3_DATAMSK_SHIFT 24 | 116 | #define DI_D3_DATAMSK_SHIFT 24 |
| 117 | 117 | ||
| 118 | enum ipu_panel { | 118 | enum ipu_panel { |
| 119 | IPU_PANEL_SHARP_TFT, | 119 | IPU_PANEL_SHARP_TFT, |
| 120 | IPU_PANEL_TFT, | 120 | IPU_PANEL_TFT, |
| 121 | }; | 121 | }; |
| 122 | 122 | ||
| 123 | struct ipu_di_signal_cfg { | 123 | struct ipu_di_signal_cfg { |
| 124 | unsigned datamask_en:1; | 124 | unsigned datamask_en:1; |
| 125 | unsigned clksel_en:1; | 125 | unsigned clksel_en:1; |
| 126 | unsigned clkidle_en:1; | 126 | unsigned clkidle_en:1; |
| 127 | unsigned data_pol:1; /* true = inverted */ | 127 | unsigned data_pol:1; /* true = inverted */ |
| 128 | unsigned clk_pol:1; /* true = rising edge */ | 128 | unsigned clk_pol:1; /* true = rising edge */ |
| 129 | unsigned enable_pol:1; | 129 | unsigned enable_pol:1; |
| 130 | unsigned Hsync_pol:1; /* true = active high */ | 130 | unsigned Hsync_pol:1; /* true = active high */ |
| 131 | unsigned Vsync_pol:1; | 131 | unsigned Vsync_pol:1; |
| 132 | }; | 132 | }; |
| 133 | 133 | ||
| 134 | static const struct fb_videomode mx3fb_modedb[] = { | 134 | static const struct fb_videomode mx3fb_modedb[] = { |
| 135 | { | 135 | { |
| 136 | /* 240x320 @ 60 Hz */ | 136 | /* 240x320 @ 60 Hz */ |
| 137 | .name = "Sharp-QVGA", | 137 | .name = "Sharp-QVGA", |
| 138 | .refresh = 60, | 138 | .refresh = 60, |
| 139 | .xres = 240, | 139 | .xres = 240, |
| 140 | .yres = 320, | 140 | .yres = 320, |
| 141 | .pixclock = 185925, | 141 | .pixclock = 185925, |
| 142 | .left_margin = 9, | 142 | .left_margin = 9, |
| 143 | .right_margin = 16, | 143 | .right_margin = 16, |
| 144 | .upper_margin = 7, | 144 | .upper_margin = 7, |
| 145 | .lower_margin = 9, | 145 | .lower_margin = 9, |
| 146 | .hsync_len = 1, | 146 | .hsync_len = 1, |
| 147 | .vsync_len = 1, | 147 | .vsync_len = 1, |
| 148 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | | 148 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | |
| 149 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | | 149 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | |
| 150 | FB_SYNC_CLK_IDLE_EN, | 150 | FB_SYNC_CLK_IDLE_EN, |
| 151 | .vmode = FB_VMODE_NONINTERLACED, | 151 | .vmode = FB_VMODE_NONINTERLACED, |
| 152 | .flag = 0, | 152 | .flag = 0, |
| 153 | }, { | 153 | }, { |
| 154 | /* 240x33 @ 60 Hz */ | 154 | /* 240x33 @ 60 Hz */ |
| 155 | .name = "Sharp-CLI", | 155 | .name = "Sharp-CLI", |
| 156 | .refresh = 60, | 156 | .refresh = 60, |
| 157 | .xres = 240, | 157 | .xres = 240, |
| 158 | .yres = 33, | 158 | .yres = 33, |
| 159 | .pixclock = 185925, | 159 | .pixclock = 185925, |
| 160 | .left_margin = 9, | 160 | .left_margin = 9, |
| 161 | .right_margin = 16, | 161 | .right_margin = 16, |
| 162 | .upper_margin = 7, | 162 | .upper_margin = 7, |
| 163 | .lower_margin = 9 + 287, | 163 | .lower_margin = 9 + 287, |
| 164 | .hsync_len = 1, | 164 | .hsync_len = 1, |
| 165 | .vsync_len = 1, | 165 | .vsync_len = 1, |
| 166 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | | 166 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | |
| 167 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | | 167 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | |
| 168 | FB_SYNC_CLK_IDLE_EN, | 168 | FB_SYNC_CLK_IDLE_EN, |
| 169 | .vmode = FB_VMODE_NONINTERLACED, | 169 | .vmode = FB_VMODE_NONINTERLACED, |
| 170 | .flag = 0, | 170 | .flag = 0, |
| 171 | }, { | 171 | }, { |
| 172 | /* 640x480 @ 60 Hz */ | 172 | /* 640x480 @ 60 Hz */ |
| 173 | .name = "NEC-VGA", | 173 | .name = "NEC-VGA", |
| 174 | .refresh = 60, | 174 | .refresh = 60, |
| 175 | .xres = 640, | 175 | .xres = 640, |
| 176 | .yres = 480, | 176 | .yres = 480, |
| 177 | .pixclock = 38255, | 177 | .pixclock = 38255, |
| 178 | .left_margin = 144, | 178 | .left_margin = 144, |
| 179 | .right_margin = 0, | 179 | .right_margin = 0, |
| 180 | .upper_margin = 34, | 180 | .upper_margin = 34, |
| 181 | .lower_margin = 40, | 181 | .lower_margin = 40, |
| 182 | .hsync_len = 1, | 182 | .hsync_len = 1, |
| 183 | .vsync_len = 1, | 183 | .vsync_len = 1, |
| 184 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, | 184 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, |
| 185 | .vmode = FB_VMODE_NONINTERLACED, | 185 | .vmode = FB_VMODE_NONINTERLACED, |
| 186 | .flag = 0, | 186 | .flag = 0, |
| 187 | }, { | 187 | }, { |
| 188 | /* NTSC TV output */ | 188 | /* NTSC TV output */ |
| 189 | .name = "TV-NTSC", | 189 | .name = "TV-NTSC", |
| 190 | .refresh = 60, | 190 | .refresh = 60, |
| 191 | .xres = 640, | 191 | .xres = 640, |
| 192 | .yres = 480, | 192 | .yres = 480, |
| 193 | .pixclock = 37538, | 193 | .pixclock = 37538, |
| 194 | .left_margin = 38, | 194 | .left_margin = 38, |
| 195 | .right_margin = 858 - 640 - 38 - 3, | 195 | .right_margin = 858 - 640 - 38 - 3, |
| 196 | .upper_margin = 36, | 196 | .upper_margin = 36, |
| 197 | .lower_margin = 518 - 480 - 36 - 1, | 197 | .lower_margin = 518 - 480 - 36 - 1, |
| 198 | .hsync_len = 3, | 198 | .hsync_len = 3, |
| 199 | .vsync_len = 1, | 199 | .vsync_len = 1, |
| 200 | .sync = 0, | 200 | .sync = 0, |
| 201 | .vmode = FB_VMODE_NONINTERLACED, | 201 | .vmode = FB_VMODE_NONINTERLACED, |
| 202 | .flag = 0, | 202 | .flag = 0, |
| 203 | }, { | 203 | }, { |
| 204 | /* PAL TV output */ | 204 | /* PAL TV output */ |
| 205 | .name = "TV-PAL", | 205 | .name = "TV-PAL", |
| 206 | .refresh = 50, | 206 | .refresh = 50, |
| 207 | .xres = 640, | 207 | .xres = 640, |
| 208 | .yres = 480, | 208 | .yres = 480, |
| 209 | .pixclock = 37538, | 209 | .pixclock = 37538, |
| 210 | .left_margin = 38, | 210 | .left_margin = 38, |
| 211 | .right_margin = 960 - 640 - 38 - 32, | 211 | .right_margin = 960 - 640 - 38 - 32, |
| 212 | .upper_margin = 32, | 212 | .upper_margin = 32, |
| 213 | .lower_margin = 555 - 480 - 32 - 3, | 213 | .lower_margin = 555 - 480 - 32 - 3, |
| 214 | .hsync_len = 32, | 214 | .hsync_len = 32, |
| 215 | .vsync_len = 3, | 215 | .vsync_len = 3, |
| 216 | .sync = 0, | 216 | .sync = 0, |
| 217 | .vmode = FB_VMODE_NONINTERLACED, | 217 | .vmode = FB_VMODE_NONINTERLACED, |
| 218 | .flag = 0, | 218 | .flag = 0, |
| 219 | }, { | 219 | }, { |
| 220 | /* TV output VGA mode, 640x480 @ 65 Hz */ | 220 | /* TV output VGA mode, 640x480 @ 65 Hz */ |
| 221 | .name = "TV-VGA", | 221 | .name = "TV-VGA", |
| 222 | .refresh = 60, | 222 | .refresh = 60, |
| 223 | .xres = 640, | 223 | .xres = 640, |
| 224 | .yres = 480, | 224 | .yres = 480, |
| 225 | .pixclock = 40574, | 225 | .pixclock = 40574, |
| 226 | .left_margin = 35, | 226 | .left_margin = 35, |
| 227 | .right_margin = 45, | 227 | .right_margin = 45, |
| 228 | .upper_margin = 9, | 228 | .upper_margin = 9, |
| 229 | .lower_margin = 1, | 229 | .lower_margin = 1, |
| 230 | .hsync_len = 46, | 230 | .hsync_len = 46, |
| 231 | .vsync_len = 5, | 231 | .vsync_len = 5, |
| 232 | .sync = 0, | 232 | .sync = 0, |
| 233 | .vmode = FB_VMODE_NONINTERLACED, | 233 | .vmode = FB_VMODE_NONINTERLACED, |
| 234 | .flag = 0, | 234 | .flag = 0, |
| 235 | }, | 235 | }, |
| 236 | }; | 236 | }; |
| 237 | 237 | ||
| 238 | struct mx3fb_data { | 238 | struct mx3fb_data { |
| 239 | struct fb_info *fbi; | 239 | struct fb_info *fbi; |
| 240 | int backlight_level; | 240 | int backlight_level; |
| 241 | void __iomem *reg_base; | 241 | void __iomem *reg_base; |
| 242 | spinlock_t lock; | 242 | spinlock_t lock; |
| 243 | struct device *dev; | 243 | struct device *dev; |
| 244 | 244 | ||
| 245 | uint32_t h_start_width; | 245 | uint32_t h_start_width; |
| 246 | uint32_t v_start_width; | 246 | uint32_t v_start_width; |
| 247 | }; | 247 | }; |
| 248 | 248 | ||
| 249 | struct dma_chan_request { | 249 | struct dma_chan_request { |
| 250 | struct mx3fb_data *mx3fb; | 250 | struct mx3fb_data *mx3fb; |
| 251 | enum ipu_channel id; | 251 | enum ipu_channel id; |
| 252 | }; | 252 | }; |
| 253 | 253 | ||
| 254 | /* MX3 specific framebuffer information. */ | 254 | /* MX3 specific framebuffer information. */ |
| 255 | struct mx3fb_info { | 255 | struct mx3fb_info { |
| 256 | int blank; | 256 | int blank; |
| 257 | enum ipu_channel ipu_ch; | 257 | enum ipu_channel ipu_ch; |
| 258 | uint32_t cur_ipu_buf; | 258 | uint32_t cur_ipu_buf; |
| 259 | 259 | ||
| 260 | u32 pseudo_palette[16]; | 260 | u32 pseudo_palette[16]; |
| 261 | 261 | ||
| 262 | struct completion flip_cmpl; | 262 | struct completion flip_cmpl; |
| 263 | struct mutex mutex; /* Protects fb-ops */ | 263 | struct mutex mutex; /* Protects fb-ops */ |
| 264 | struct mx3fb_data *mx3fb; | 264 | struct mx3fb_data *mx3fb; |
| 265 | struct idmac_channel *idmac_channel; | 265 | struct idmac_channel *idmac_channel; |
| 266 | struct dma_async_tx_descriptor *txd; | 266 | struct dma_async_tx_descriptor *txd; |
| 267 | dma_cookie_t cookie; | 267 | dma_cookie_t cookie; |
| 268 | struct scatterlist sg[2]; | 268 | struct scatterlist sg[2]; |
| 269 | 269 | ||
| 270 | u32 sync; /* preserve var->sync flags */ | 270 | u32 sync; /* preserve var->sync flags */ |
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| 273 | static void mx3fb_dma_done(void *); | 273 | static void mx3fb_dma_done(void *); |
| @@ -278,389 +278,389 @@ static unsigned long default_bpp = 16; | |||
| 278 | 278 | ||
| 279 | static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg) | 279 | static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg) |
| 280 | { | 280 | { |
| 281 | return __raw_readl(mx3fb->reg_base + reg); | 281 | return __raw_readl(mx3fb->reg_base + reg); |
| 282 | } | 282 | } |
| 283 | 283 | ||
| 284 | static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg) | 284 | static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg) |
| 285 | { | 285 | { |
| 286 | __raw_writel(value, mx3fb->reg_base + reg); | 286 | __raw_writel(value, mx3fb->reg_base + reg); |
| 287 | } | 287 | } |
| 288 | 288 | ||
| 289 | static const uint32_t di_mappings[] = { | 289 | static const uint32_t di_mappings[] = { |
| 290 | 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */ | 290 | 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */ |
| 291 | 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */ | 291 | 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */ |
| 292 | 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */ | 292 | 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */ |
| 293 | 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */ | 293 | 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */ |
| 294 | }; | 294 | }; |
| 295 | 295 | ||
| 296 | static void sdc_fb_init(struct mx3fb_info *fbi) | 296 | static void sdc_fb_init(struct mx3fb_info *fbi) |
| 297 | { | 297 | { |
| 298 | struct mx3fb_data *mx3fb = fbi->mx3fb; | 298 | struct mx3fb_data *mx3fb = fbi->mx3fb; |
| 299 | uint32_t reg; | 299 | uint32_t reg; |
| 300 | 300 | ||
| 301 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 301 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 302 | 302 | ||
| 303 | mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF); | 303 | mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF); |
| 304 | } | 304 | } |
| 305 | 305 | ||
| 306 | /* Returns enabled flag before uninit */ | 306 | /* Returns enabled flag before uninit */ |
| 307 | static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi) | 307 | static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi) |
| 308 | { | 308 | { |
| 309 | struct mx3fb_data *mx3fb = fbi->mx3fb; | 309 | struct mx3fb_data *mx3fb = fbi->mx3fb; |
| 310 | uint32_t reg; | 310 | uint32_t reg; |
| 311 | 311 | ||
| 312 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 312 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 313 | 313 | ||
| 314 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF); | 314 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF); |
| 315 | 315 | ||
| 316 | return reg & SDC_COM_BG_EN; | 316 | return reg & SDC_COM_BG_EN; |
| 317 | } | 317 | } |
| 318 | 318 | ||
| 319 | static void sdc_enable_channel(struct mx3fb_info *mx3_fbi) | 319 | static void sdc_enable_channel(struct mx3fb_info *mx3_fbi) |
| 320 | { | 320 | { |
| 321 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 321 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 322 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; | 322 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; |
| 323 | struct dma_chan *dma_chan = &ichan->dma_chan; | 323 | struct dma_chan *dma_chan = &ichan->dma_chan; |
| 324 | unsigned long flags; | 324 | unsigned long flags; |
| 325 | dma_cookie_t cookie; | 325 | dma_cookie_t cookie; |
| 326 | 326 | ||
| 327 | dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi, | 327 | dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi, |
| 328 | to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg); | 328 | to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg); |
| 329 | 329 | ||
| 330 | /* This enables the channel */ | 330 | /* This enables the channel */ |
| 331 | if (mx3_fbi->cookie < 0) { | 331 | if (mx3_fbi->cookie < 0) { |
| 332 | mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan, | 332 | mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan, |
| 333 | &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); | 333 | &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); |
| 334 | if (!mx3_fbi->txd) { | 334 | if (!mx3_fbi->txd) { |
| 335 | dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n", | 335 | dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n", |
| 336 | dma_chan->chan_id); | 336 | dma_chan->chan_id); |
| 337 | return; | 337 | return; |
| 338 | } | 338 | } |
| 339 | 339 | ||
| 340 | mx3_fbi->txd->callback_param = mx3_fbi->txd; | 340 | mx3_fbi->txd->callback_param = mx3_fbi->txd; |
| 341 | mx3_fbi->txd->callback = mx3fb_dma_done; | 341 | mx3_fbi->txd->callback = mx3fb_dma_done; |
| 342 | 342 | ||
| 343 | cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd); | 343 | cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd); |
| 344 | dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__, | 344 | dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__, |
| 345 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); | 345 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); |
| 346 | } else { | 346 | } else { |
| 347 | if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) { | 347 | if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) { |
| 348 | dev_err(mx3fb->dev, "Cannot enable channel %d\n", | 348 | dev_err(mx3fb->dev, "Cannot enable channel %d\n", |
| 349 | dma_chan->chan_id); | 349 | dma_chan->chan_id); |
| 350 | return; | 350 | return; |
| 351 | } | 351 | } |
| 352 | 352 | ||
| 353 | /* Just re-activate the same buffer */ | 353 | /* Just re-activate the same buffer */ |
| 354 | dma_async_issue_pending(dma_chan); | 354 | dma_async_issue_pending(dma_chan); |
| 355 | cookie = mx3_fbi->cookie; | 355 | cookie = mx3_fbi->cookie; |
| 356 | dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__, | 356 | dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__, |
| 357 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); | 357 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); |
| 358 | } | 358 | } |
| 359 | 359 | ||
| 360 | if (cookie >= 0) { | 360 | if (cookie >= 0) { |
| 361 | spin_lock_irqsave(&mx3fb->lock, flags); | 361 | spin_lock_irqsave(&mx3fb->lock, flags); |
| 362 | sdc_fb_init(mx3_fbi); | 362 | sdc_fb_init(mx3_fbi); |
| 363 | mx3_fbi->cookie = cookie; | 363 | mx3_fbi->cookie = cookie; |
| 364 | spin_unlock_irqrestore(&mx3fb->lock, flags); | 364 | spin_unlock_irqrestore(&mx3fb->lock, flags); |
| 365 | } | 365 | } |
| 366 | 366 | ||
| 367 | /* | 367 | /* |
| 368 | * Attention! Without this msleep the channel keeps generating | 368 | * Attention! Without this msleep the channel keeps generating |
| 369 | * interrupts. Next sdc_set_brightness() is going to be called | 369 | * interrupts. Next sdc_set_brightness() is going to be called |
| 370 | * from mx3fb_blank(). | 370 | * from mx3fb_blank(). |
| 371 | */ | 371 | */ |
| 372 | msleep(2); | 372 | msleep(2); |
| 373 | } | 373 | } |
| 374 | 374 | ||
| 375 | static void sdc_disable_channel(struct mx3fb_info *mx3_fbi) | 375 | static void sdc_disable_channel(struct mx3fb_info *mx3_fbi) |
| 376 | { | 376 | { |
| 377 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 377 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 378 | uint32_t enabled; | 378 | uint32_t enabled; |
| 379 | unsigned long flags; | 379 | unsigned long flags; |
| 380 | 380 | ||
| 381 | spin_lock_irqsave(&mx3fb->lock, flags); | 381 | spin_lock_irqsave(&mx3fb->lock, flags); |
| 382 | 382 | ||
| 383 | enabled = sdc_fb_uninit(mx3_fbi); | 383 | enabled = sdc_fb_uninit(mx3_fbi); |
| 384 | 384 | ||
| 385 | spin_unlock_irqrestore(&mx3fb->lock, flags); | 385 | spin_unlock_irqrestore(&mx3fb->lock, flags); |
| 386 | 386 | ||
| 387 | mx3_fbi->txd->chan->device->device_terminate_all(mx3_fbi->txd->chan); | 387 | mx3_fbi->txd->chan->device->device_terminate_all(mx3_fbi->txd->chan); |
| 388 | mx3_fbi->txd = NULL; | 388 | mx3_fbi->txd = NULL; |
| 389 | mx3_fbi->cookie = -EINVAL; | 389 | mx3_fbi->cookie = -EINVAL; |
| 390 | } | 390 | } |
| 391 | 391 | ||
| 392 | /** | 392 | /** |
| 393 | * sdc_set_window_pos() - set window position of the respective plane. | 393 | * sdc_set_window_pos() - set window position of the respective plane. |
| 394 | * @mx3fb: mx3fb context. | 394 | * @mx3fb: mx3fb context. |
| 395 | * @channel: IPU DMAC channel ID. | 395 | * @channel: IPU DMAC channel ID. |
| 396 | * @x_pos: X coordinate relative to the top left corner to place window at. | 396 | * @x_pos: X coordinate relative to the top left corner to place window at. |
| 397 | * @y_pos: Y coordinate relative to the top left corner to place window at. | 397 | * @y_pos: Y coordinate relative to the top left corner to place window at. |
| 398 | * @return: 0 on success or negative error code on failure. | 398 | * @return: 0 on success or negative error code on failure. |
| 399 | */ | 399 | */ |
| 400 | static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel, | 400 | static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel, |
| 401 | int16_t x_pos, int16_t y_pos) | 401 | int16_t x_pos, int16_t y_pos) |
| 402 | { | 402 | { |
| 403 | x_pos += mx3fb->h_start_width; | 403 | x_pos += mx3fb->h_start_width; |
| 404 | y_pos += mx3fb->v_start_width; | 404 | y_pos += mx3fb->v_start_width; |
| 405 | 405 | ||
| 406 | if (channel != IDMAC_SDC_0) | 406 | if (channel != IDMAC_SDC_0) |
| 407 | return -EINVAL; | 407 | return -EINVAL; |
| 408 | 408 | ||
| 409 | mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS); | 409 | mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS); |
| 410 | return 0; | 410 | return 0; |
| 411 | } | 411 | } |
| 412 | 412 | ||
| 413 | /** | 413 | /** |
| 414 | * sdc_init_panel() - initialize a synchronous LCD panel. | 414 | * sdc_init_panel() - initialize a synchronous LCD panel. |
| 415 | * @mx3fb: mx3fb context. | 415 | * @mx3fb: mx3fb context. |
| 416 | * @panel: panel type. | 416 | * @panel: panel type. |
| 417 | * @pixel_clk: desired pixel clock frequency in Hz. | 417 | * @pixel_clk: desired pixel clock frequency in Hz. |
| 418 | * @width: width of panel in pixels. | 418 | * @width: width of panel in pixels. |
| 419 | * @height: height of panel in pixels. | 419 | * @height: height of panel in pixels. |
| 420 | * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. | 420 | * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. |
| 421 | * @h_start_width: number of pixel clocks between the HSYNC signal pulse | 421 | * @h_start_width: number of pixel clocks between the HSYNC signal pulse |
| 422 | * and the start of valid data. | 422 | * and the start of valid data. |
| 423 | * @h_sync_width: width of the HSYNC signal in units of pixel clocks. | 423 | * @h_sync_width: width of the HSYNC signal in units of pixel clocks. |
| 424 | * @h_end_width: number of pixel clocks between the end of valid data | 424 | * @h_end_width: number of pixel clocks between the end of valid data |
| 425 | * and the HSYNC signal for next line. | 425 | * and the HSYNC signal for next line. |
| 426 | * @v_start_width: number of lines between the VSYNC signal pulse and the | 426 | * @v_start_width: number of lines between the VSYNC signal pulse and the |
| 427 | * start of valid data. | 427 | * start of valid data. |
| 428 | * @v_sync_width: width of the VSYNC signal in units of lines | 428 | * @v_sync_width: width of the VSYNC signal in units of lines |
| 429 | * @v_end_width: number of lines between the end of valid data and the | 429 | * @v_end_width: number of lines between the end of valid data and the |
| 430 | * VSYNC signal for next frame. | 430 | * VSYNC signal for next frame. |
| 431 | * @sig: bitfield of signal polarities for LCD interface. | 431 | * @sig: bitfield of signal polarities for LCD interface. |
| 432 | * @return: 0 on success or negative error code on failure. | 432 | * @return: 0 on success or negative error code on failure. |
| 433 | */ | 433 | */ |
| 434 | static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel, | 434 | static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel, |
| 435 | uint32_t pixel_clk, | 435 | uint32_t pixel_clk, |
| 436 | uint16_t width, uint16_t height, | 436 | uint16_t width, uint16_t height, |
| 437 | enum pixel_fmt pixel_fmt, | 437 | enum pixel_fmt pixel_fmt, |
| 438 | uint16_t h_start_width, uint16_t h_sync_width, | 438 | uint16_t h_start_width, uint16_t h_sync_width, |
| 439 | uint16_t h_end_width, uint16_t v_start_width, | 439 | uint16_t h_end_width, uint16_t v_start_width, |
| 440 | uint16_t v_sync_width, uint16_t v_end_width, | 440 | uint16_t v_sync_width, uint16_t v_end_width, |
| 441 | struct ipu_di_signal_cfg sig) | 441 | struct ipu_di_signal_cfg sig) |
| 442 | { | 442 | { |
| 443 | unsigned long lock_flags; | 443 | unsigned long lock_flags; |
| 444 | uint32_t reg; | 444 | uint32_t reg; |
| 445 | uint32_t old_conf; | 445 | uint32_t old_conf; |
| 446 | uint32_t div; | 446 | uint32_t div; |
| 447 | struct clk *ipu_clk; | 447 | struct clk *ipu_clk; |
| 448 | 448 | ||
| 449 | dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height); | 449 | dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height); |
| 450 | 450 | ||
| 451 | if (v_sync_width == 0 || h_sync_width == 0) | 451 | if (v_sync_width == 0 || h_sync_width == 0) |
| 452 | return -EINVAL; | 452 | return -EINVAL; |
| 453 | 453 | ||
| 454 | /* Init panel size and blanking periods */ | 454 | /* Init panel size and blanking periods */ |
| 455 | reg = ((uint32_t) (h_sync_width - 1) << 26) | | 455 | reg = ((uint32_t) (h_sync_width - 1) << 26) | |
| 456 | ((uint32_t) (width + h_start_width + h_end_width - 1) << 16); | 456 | ((uint32_t) (width + h_start_width + h_end_width - 1) << 16); |
| 457 | mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF); | 457 | mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF); |
| 458 | 458 | ||
| 459 | #ifdef DEBUG | 459 | #ifdef DEBUG |
| 460 | printk(KERN_CONT " hor_conf %x,", reg); | 460 | printk(KERN_CONT " hor_conf %x,", reg); |
| 461 | #endif | 461 | #endif |
| 462 | 462 | ||
| 463 | reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | | 463 | reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | |
| 464 | ((uint32_t) (height + v_start_width + v_end_width - 1) << 16); | 464 | ((uint32_t) (height + v_start_width + v_end_width - 1) << 16); |
| 465 | mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF); | 465 | mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF); |
| 466 | 466 | ||
| 467 | #ifdef DEBUG | 467 | #ifdef DEBUG |
| 468 | printk(KERN_CONT " ver_conf %x\n", reg); | 468 | printk(KERN_CONT " ver_conf %x\n", reg); |
| 469 | #endif | 469 | #endif |
| 470 | 470 | ||
| 471 | mx3fb->h_start_width = h_start_width; | 471 | mx3fb->h_start_width = h_start_width; |
| 472 | mx3fb->v_start_width = v_start_width; | 472 | mx3fb->v_start_width = v_start_width; |
| 473 | 473 | ||
| 474 | switch (panel) { | 474 | switch (panel) { |
| 475 | case IPU_PANEL_SHARP_TFT: | 475 | case IPU_PANEL_SHARP_TFT: |
| 476 | mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1); | 476 | mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1); |
| 477 | mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2); | 477 | mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2); |
| 478 | mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); | 478 | mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); |
| 479 | break; | 479 | break; |
| 480 | case IPU_PANEL_TFT: | 480 | case IPU_PANEL_TFT: |
| 481 | mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF); | 481 | mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF); |
| 482 | break; | 482 | break; |
| 483 | default: | 483 | default: |
| 484 | return -EINVAL; | 484 | return -EINVAL; |
| 485 | } | 485 | } |
| 486 | 486 | ||
| 487 | /* Init clocking */ | 487 | /* Init clocking */ |
| 488 | 488 | ||
| 489 | /* | 489 | /* |
| 490 | * Calculate divider: fractional part is 4 bits so simply multiple by | 490 | * Calculate divider: fractional part is 4 bits so simply multiple by |
| 491 | * 24 to get fractional part, as long as we stay under ~250MHz and on | 491 | * 2^4 to get fractional part, as long as we stay under ~250MHz and on |
| 492 | * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz | 492 | * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz |
| 493 | */ | 493 | */ |
| 494 | dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk); | 494 | dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk); |
| 495 | 495 | ||
| 496 | ipu_clk = clk_get(mx3fb->dev, "ipu_clk"); | 496 | ipu_clk = clk_get(mx3fb->dev, NULL); |
| 497 | div = clk_get_rate(ipu_clk) * 16 / pixel_clk; | 497 | div = clk_get_rate(ipu_clk) * 16 / pixel_clk; |
| 498 | clk_put(ipu_clk); | 498 | clk_put(ipu_clk); |
| 499 | 499 | ||
| 500 | if (div < 0x40) { /* Divider less than 4 */ | 500 | if (div < 0x40) { /* Divider less than 4 */ |
| 501 | dev_dbg(mx3fb->dev, | 501 | dev_dbg(mx3fb->dev, |
| 502 | "InitPanel() - Pixel clock divider less than 4\n"); | 502 | "InitPanel() - Pixel clock divider less than 4\n"); |
| 503 | div = 0x40; | 503 | div = 0x40; |
| 504 | } | 504 | } |
| 505 | 505 | ||
| 506 | spin_lock_irqsave(&mx3fb->lock, lock_flags); | 506 | spin_lock_irqsave(&mx3fb->lock, lock_flags); |
| 507 | 507 | ||
| 508 | /* | 508 | /* |
| 509 | * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits | 509 | * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits |
| 510 | * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing | 510 | * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing |
| 511 | * debug. DISP3_IF_CLK_UP_WR is 0 | 511 | * debug. DISP3_IF_CLK_UP_WR is 0 |
| 512 | */ | 512 | */ |
| 513 | mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); | 513 | mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); |
| 514 | 514 | ||
| 515 | /* DI settings */ | 515 | /* DI settings */ |
| 516 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF; | 516 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF; |
| 517 | old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | | 517 | old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | |
| 518 | sig.clksel_en << DI_D3_CLK_SEL_SHIFT | | 518 | sig.clksel_en << DI_D3_CLK_SEL_SHIFT | |
| 519 | sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; | 519 | sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; |
| 520 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF); | 520 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF); |
| 521 | 521 | ||
| 522 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF; | 522 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF; |
| 523 | old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | | 523 | old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | |
| 524 | sig.clk_pol << DI_D3_CLK_POL_SHIFT | | 524 | sig.clk_pol << DI_D3_CLK_POL_SHIFT | |
| 525 | sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | | 525 | sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | |
| 526 | sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | | 526 | sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | |
| 527 | sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; | 527 | sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; |
| 528 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL); | 528 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL); |
| 529 | 529 | ||
| 530 | switch (pixel_fmt) { | 530 | switch (pixel_fmt) { |
| 531 | case IPU_PIX_FMT_RGB24: | 531 | case IPU_PIX_FMT_RGB24: |
| 532 | mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP); | 532 | mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP); |
| 533 | mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP); | 533 | mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP); |
| 534 | mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP); | 534 | mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP); |
| 535 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 535 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 536 | ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC); | 536 | ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC); |
| 537 | break; | 537 | break; |
| 538 | case IPU_PIX_FMT_RGB666: | 538 | case IPU_PIX_FMT_RGB666: |
| 539 | mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP); | 539 | mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP); |
| 540 | mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP); | 540 | mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP); |
| 541 | mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP); | 541 | mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP); |
| 542 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 542 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 543 | ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC); | 543 | ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC); |
| 544 | break; | 544 | break; |
| 545 | case IPU_PIX_FMT_BGR666: | 545 | case IPU_PIX_FMT_BGR666: |
| 546 | mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP); | 546 | mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP); |
| 547 | mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP); | 547 | mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP); |
| 548 | mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP); | 548 | mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP); |
| 549 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 549 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 550 | ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC); | 550 | ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC); |
| 551 | break; | 551 | break; |
| 552 | default: | 552 | default: |
| 553 | mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP); | 553 | mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP); |
| 554 | mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP); | 554 | mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP); |
| 555 | mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP); | 555 | mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP); |
| 556 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 556 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 557 | ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC); | 557 | ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC); |
| 558 | break; | 558 | break; |
| 559 | } | 559 | } |
| 560 | 560 | ||
| 561 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); | 561 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); |
| 562 | 562 | ||
| 563 | dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n", | 563 | dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n", |
| 564 | mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF)); | 564 | mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF)); |
| 565 | dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n", | 565 | dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n", |
| 566 | mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL)); | 566 | mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL)); |
| 567 | dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n", | 567 | dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n", |
| 568 | mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF)); | 568 | mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF)); |
| 569 | 569 | ||
| 570 | return 0; | 570 | return 0; |
| 571 | } | 571 | } |
| 572 | 572 | ||
| 573 | /** | 573 | /** |
| 574 | * sdc_set_color_key() - set the transparent color key for SDC graphic plane. | 574 | * sdc_set_color_key() - set the transparent color key for SDC graphic plane. |
| 575 | * @mx3fb: mx3fb context. | 575 | * @mx3fb: mx3fb context. |
| 576 | * @channel: IPU DMAC channel ID. | 576 | * @channel: IPU DMAC channel ID. |
| 577 | * @enable: boolean to enable or disable color keyl. | 577 | * @enable: boolean to enable or disable color keyl. |
| 578 | * @color_key: 24-bit RGB color to use as transparent color key. | 578 | * @color_key: 24-bit RGB color to use as transparent color key. |
| 579 | * @return: 0 on success or negative error code on failure. | 579 | * @return: 0 on success or negative error code on failure. |
| 580 | */ | 580 | */ |
| 581 | static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel, | 581 | static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel, |
| 582 | bool enable, uint32_t color_key) | 582 | bool enable, uint32_t color_key) |
| 583 | { | 583 | { |
| 584 | uint32_t reg, sdc_conf; | 584 | uint32_t reg, sdc_conf; |
| 585 | unsigned long lock_flags; | 585 | unsigned long lock_flags; |
| 586 | 586 | ||
| 587 | spin_lock_irqsave(&mx3fb->lock, lock_flags); | 587 | spin_lock_irqsave(&mx3fb->lock, lock_flags); |
| 588 | 588 | ||
| 589 | sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 589 | sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 590 | if (channel == IDMAC_SDC_0) | 590 | if (channel == IDMAC_SDC_0) |
| 591 | sdc_conf &= ~SDC_COM_GWSEL; | 591 | sdc_conf &= ~SDC_COM_GWSEL; |
| 592 | else | 592 | else |
| 593 | sdc_conf |= SDC_COM_GWSEL; | 593 | sdc_conf |= SDC_COM_GWSEL; |
| 594 | 594 | ||
| 595 | if (enable) { | 595 | if (enable) { |
| 596 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L; | 596 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L; |
| 597 | mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL), | 597 | mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL), |
| 598 | SDC_GW_CTRL); | 598 | SDC_GW_CTRL); |
| 599 | 599 | ||
| 600 | sdc_conf |= SDC_COM_KEY_COLOR_G; | 600 | sdc_conf |= SDC_COM_KEY_COLOR_G; |
| 601 | } else { | 601 | } else { |
| 602 | sdc_conf &= ~SDC_COM_KEY_COLOR_G; | 602 | sdc_conf &= ~SDC_COM_KEY_COLOR_G; |
| 603 | } | 603 | } |
| 604 | mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF); | 604 | mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF); |
| 605 | 605 | ||
| 606 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); | 606 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); |
| 607 | 607 | ||
| 608 | return 0; | 608 | return 0; |
| 609 | } | 609 | } |
| 610 | 610 | ||
| 611 | /** | 611 | /** |
| 612 | * sdc_set_global_alpha() - set global alpha blending modes. | 612 | * sdc_set_global_alpha() - set global alpha blending modes. |
| 613 | * @mx3fb: mx3fb context. | 613 | * @mx3fb: mx3fb context. |
| 614 | * @enable: boolean to enable or disable global alpha blending. If disabled, | 614 | * @enable: boolean to enable or disable global alpha blending. If disabled, |
| 615 | * per pixel blending is used. | 615 | * per pixel blending is used. |
| 616 | * @alpha: global alpha value. | 616 | * @alpha: global alpha value. |
| 617 | * @return: 0 on success or negative error code on failure. | 617 | * @return: 0 on success or negative error code on failure. |
| 618 | */ | 618 | */ |
| 619 | static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha) | 619 | static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha) |
| 620 | { | 620 | { |
| 621 | uint32_t reg; | 621 | uint32_t reg; |
| 622 | unsigned long lock_flags; | 622 | unsigned long lock_flags; |
| 623 | 623 | ||
| 624 | spin_lock_irqsave(&mx3fb->lock, lock_flags); | 624 | spin_lock_irqsave(&mx3fb->lock, lock_flags); |
| 625 | 625 | ||
| 626 | if (enable) { | 626 | if (enable) { |
| 627 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL; | 627 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL; |
| 628 | mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); | 628 | mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); |
| 629 | 629 | ||
| 630 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 630 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 631 | mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF); | 631 | mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF); |
| 632 | } else { | 632 | } else { |
| 633 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 633 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 634 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF); | 634 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF); |
| 635 | } | 635 | } |
| 636 | 636 | ||
| 637 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); | 637 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); |
| 638 | 638 | ||
| 639 | return 0; | 639 | return 0; |
| 640 | } | 640 | } |
| 641 | 641 | ||
| 642 | static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value) | 642 | static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value) |
| 643 | { | 643 | { |
| 644 | /* This might be board-specific */ | 644 | /* This might be board-specific */ |
| 645 | mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL); | 645 | mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL); |
| 646 | return; | 646 | return; |
| 647 | } | 647 | } |
| 648 | 648 | ||
| 649 | static uint32_t bpp_to_pixfmt(int bpp) | 649 | static uint32_t bpp_to_pixfmt(int bpp) |
| 650 | { | 650 | { |
| 651 | uint32_t pixfmt = 0; | 651 | uint32_t pixfmt = 0; |
| 652 | switch (bpp) { | 652 | switch (bpp) { |
| 653 | case 24: | 653 | case 24: |
| 654 | pixfmt = IPU_PIX_FMT_BGR24; | 654 | pixfmt = IPU_PIX_FMT_BGR24; |
| 655 | break; | 655 | break; |
| 656 | case 32: | 656 | case 32: |
| 657 | pixfmt = IPU_PIX_FMT_BGR32; | 657 | pixfmt = IPU_PIX_FMT_BGR32; |
| 658 | break; | 658 | break; |
| 659 | case 16: | 659 | case 16: |
| 660 | pixfmt = IPU_PIX_FMT_RGB565; | 660 | pixfmt = IPU_PIX_FMT_RGB565; |
| 661 | break; | 661 | break; |
| 662 | } | 662 | } |
| 663 | return pixfmt; | 663 | return pixfmt; |
| 664 | } | 664 | } |
| 665 | 665 | ||
| 666 | static int mx3fb_blank(int blank, struct fb_info *fbi); | 666 | static int mx3fb_blank(int blank, struct fb_info *fbi); |
| @@ -669,300 +669,300 @@ static int mx3fb_unmap_video_memory(struct fb_info *fbi); | |||
| 669 | 669 | ||
| 670 | /** | 670 | /** |
| 671 | * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings. | 671 | * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings. |
| 672 | * @info: framebuffer information pointer | 672 | * @info: framebuffer information pointer |
| 673 | * @return: 0 on success or negative error code on failure. | 673 | * @return: 0 on success or negative error code on failure. |
| 674 | */ | 674 | */ |
| 675 | static int mx3fb_set_fix(struct fb_info *fbi) | 675 | static int mx3fb_set_fix(struct fb_info *fbi) |
| 676 | { | 676 | { |
| 677 | struct fb_fix_screeninfo *fix = &fbi->fix; | 677 | struct fb_fix_screeninfo *fix = &fbi->fix; |
| 678 | struct fb_var_screeninfo *var = &fbi->var; | 678 | struct fb_var_screeninfo *var = &fbi->var; |
| 679 | 679 | ||
| 680 | strncpy(fix->id, "DISP3 BG", 8); | 680 | strncpy(fix->id, "DISP3 BG", 8); |
| 681 | 681 | ||
| 682 | fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; | 682 | fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; |
| 683 | 683 | ||
| 684 | fix->type = FB_TYPE_PACKED_PIXELS; | 684 | fix->type = FB_TYPE_PACKED_PIXELS; |
| 685 | fix->accel = FB_ACCEL_NONE; | 685 | fix->accel = FB_ACCEL_NONE; |
| 686 | fix->visual = FB_VISUAL_TRUECOLOR; | 686 | fix->visual = FB_VISUAL_TRUECOLOR; |
| 687 | fix->xpanstep = 1; | 687 | fix->xpanstep = 1; |
| 688 | fix->ypanstep = 1; | 688 | fix->ypanstep = 1; |
| 689 | 689 | ||
| 690 | return 0; | 690 | return 0; |
| 691 | } | 691 | } |
| 692 | 692 | ||
| 693 | static void mx3fb_dma_done(void *arg) | 693 | static void mx3fb_dma_done(void *arg) |
| 694 | { | 694 | { |
| 695 | struct idmac_tx_desc *tx_desc = to_tx_desc(arg); | 695 | struct idmac_tx_desc *tx_desc = to_tx_desc(arg); |
| 696 | struct dma_chan *chan = tx_desc->txd.chan; | 696 | struct dma_chan *chan = tx_desc->txd.chan; |
| 697 | struct idmac_channel *ichannel = to_idmac_chan(chan); | 697 | struct idmac_channel *ichannel = to_idmac_chan(chan); |
| 698 | struct mx3fb_data *mx3fb = ichannel->client; | 698 | struct mx3fb_data *mx3fb = ichannel->client; |
| 699 | struct mx3fb_info *mx3_fbi = mx3fb->fbi->par; | 699 | struct mx3fb_info *mx3_fbi = mx3fb->fbi->par; |
| 700 | 700 | ||
| 701 | dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq); | 701 | dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq); |
| 702 | 702 | ||
| 703 | /* We only need one interrupt, it will be re-enabled as needed */ | 703 | /* We only need one interrupt, it will be re-enabled as needed */ |
| 704 | disable_irq(ichannel->eof_irq); | 704 | disable_irq(ichannel->eof_irq); |
| 705 | 705 | ||
| 706 | complete(&mx3_fbi->flip_cmpl); | 706 | complete(&mx3_fbi->flip_cmpl); |
| 707 | } | 707 | } |
| 708 | 708 | ||
| 709 | /** | 709 | /** |
| 710 | * mx3fb_set_par() - set framebuffer parameters and change the operating mode. | 710 | * mx3fb_set_par() - set framebuffer parameters and change the operating mode. |
| 711 | * @fbi: framebuffer information pointer. | 711 | * @fbi: framebuffer information pointer. |
| 712 | * @return: 0 on success or negative error code on failure. | 712 | * @return: 0 on success or negative error code on failure. |
| 713 | */ | 713 | */ |
| 714 | static int mx3fb_set_par(struct fb_info *fbi) | 714 | static int mx3fb_set_par(struct fb_info *fbi) |
| 715 | { | 715 | { |
| 716 | u32 mem_len; | 716 | u32 mem_len; |
| 717 | struct ipu_di_signal_cfg sig_cfg; | 717 | struct ipu_di_signal_cfg sig_cfg; |
| 718 | enum ipu_panel mode = IPU_PANEL_TFT; | 718 | enum ipu_panel mode = IPU_PANEL_TFT; |
| 719 | struct mx3fb_info *mx3_fbi = fbi->par; | 719 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 720 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 720 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 721 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; | 721 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; |
| 722 | struct idmac_video_param *video = &ichan->params.video; | 722 | struct idmac_video_param *video = &ichan->params.video; |
| 723 | struct scatterlist *sg = mx3_fbi->sg; | 723 | struct scatterlist *sg = mx3_fbi->sg; |
| 724 | size_t screen_size; | 724 | size_t screen_size; |
| 725 | 725 | ||
| 726 | dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+'); | 726 | dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+'); |
| 727 | 727 | ||
| 728 | mutex_lock(&mx3_fbi->mutex); | 728 | mutex_lock(&mx3_fbi->mutex); |
| 729 | 729 | ||
| 730 | /* Total cleanup */ | 730 | /* Total cleanup */ |
| 731 | if (mx3_fbi->txd) | 731 | if (mx3_fbi->txd) |
| 732 | sdc_disable_channel(mx3_fbi); | 732 | sdc_disable_channel(mx3_fbi); |
| 733 | 733 | ||
| 734 | mx3fb_set_fix(fbi); | 734 | mx3fb_set_fix(fbi); |
| 735 | 735 | ||
| 736 | mem_len = fbi->var.yres_virtual * fbi->fix.line_length; | 736 | mem_len = fbi->var.yres_virtual * fbi->fix.line_length; |
| 737 | if (mem_len > fbi->fix.smem_len) { | 737 | if (mem_len > fbi->fix.smem_len) { |
| 738 | if (fbi->fix.smem_start) | 738 | if (fbi->fix.smem_start) |
| 739 | mx3fb_unmap_video_memory(fbi); | 739 | mx3fb_unmap_video_memory(fbi); |
| 740 | 740 | ||
| 741 | fbi->fix.smem_len = mem_len; | 741 | fbi->fix.smem_len = mem_len; |
| 742 | if (mx3fb_map_video_memory(fbi) < 0) { | 742 | if (mx3fb_map_video_memory(fbi) < 0) { |
| 743 | mutex_unlock(&mx3_fbi->mutex); | 743 | mutex_unlock(&mx3_fbi->mutex); |
| 744 | return -ENOMEM; | 744 | return -ENOMEM; |
| 745 | } | 745 | } |
| 746 | } | 746 | } |
| 747 | 747 | ||
| 748 | screen_size = fbi->fix.line_length * fbi->var.yres; | 748 | screen_size = fbi->fix.line_length * fbi->var.yres; |
| 749 | 749 | ||
| 750 | sg_init_table(&sg[0], 1); | 750 | sg_init_table(&sg[0], 1); |
| 751 | sg_init_table(&sg[1], 1); | 751 | sg_init_table(&sg[1], 1); |
| 752 | 752 | ||
| 753 | sg_dma_address(&sg[0]) = fbi->fix.smem_start; | 753 | sg_dma_address(&sg[0]) = fbi->fix.smem_start; |
| 754 | sg_set_page(&sg[0], virt_to_page(fbi->screen_base), | 754 | sg_set_page(&sg[0], virt_to_page(fbi->screen_base), |
| 755 | fbi->fix.smem_len, | 755 | fbi->fix.smem_len, |
| 756 | offset_in_page(fbi->screen_base)); | 756 | offset_in_page(fbi->screen_base)); |
| 757 | 757 | ||
| 758 | if (mx3_fbi->ipu_ch == IDMAC_SDC_0) { | 758 | if (mx3_fbi->ipu_ch == IDMAC_SDC_0) { |
| 759 | memset(&sig_cfg, 0, sizeof(sig_cfg)); | 759 | memset(&sig_cfg, 0, sizeof(sig_cfg)); |
| 760 | if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) | 760 | if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) |
| 761 | sig_cfg.Hsync_pol = true; | 761 | sig_cfg.Hsync_pol = true; |
| 762 | if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) | 762 | if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) |
| 763 | sig_cfg.Vsync_pol = true; | 763 | sig_cfg.Vsync_pol = true; |
| 764 | if (fbi->var.sync & FB_SYNC_CLK_INVERT) | 764 | if (fbi->var.sync & FB_SYNC_CLK_INVERT) |
| 765 | sig_cfg.clk_pol = true; | 765 | sig_cfg.clk_pol = true; |
| 766 | if (fbi->var.sync & FB_SYNC_DATA_INVERT) | 766 | if (fbi->var.sync & FB_SYNC_DATA_INVERT) |
| 767 | sig_cfg.data_pol = true; | 767 | sig_cfg.data_pol = true; |
| 768 | if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH) | 768 | if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH) |
| 769 | sig_cfg.enable_pol = true; | 769 | sig_cfg.enable_pol = true; |
| 770 | if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) | 770 | if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) |
| 771 | sig_cfg.clkidle_en = true; | 771 | sig_cfg.clkidle_en = true; |
| 772 | if (fbi->var.sync & FB_SYNC_CLK_SEL_EN) | 772 | if (fbi->var.sync & FB_SYNC_CLK_SEL_EN) |
| 773 | sig_cfg.clksel_en = true; | 773 | sig_cfg.clksel_en = true; |
| 774 | if (fbi->var.sync & FB_SYNC_SHARP_MODE) | 774 | if (fbi->var.sync & FB_SYNC_SHARP_MODE) |
| 775 | mode = IPU_PANEL_SHARP_TFT; | 775 | mode = IPU_PANEL_SHARP_TFT; |
| 776 | 776 | ||
| 777 | dev_dbg(fbi->device, "pixclock = %ul Hz\n", | 777 | dev_dbg(fbi->device, "pixclock = %ul Hz\n", |
| 778 | (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); | 778 | (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); |
| 779 | 779 | ||
| 780 | if (sdc_init_panel(mx3fb, mode, | 780 | if (sdc_init_panel(mx3fb, mode, |
| 781 | (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, | 781 | (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, |
| 782 | fbi->var.xres, fbi->var.yres, | 782 | fbi->var.xres, fbi->var.yres, |
| 783 | (fbi->var.sync & FB_SYNC_SWAP_RGB) ? | 783 | (fbi->var.sync & FB_SYNC_SWAP_RGB) ? |
| 784 | IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666, | 784 | IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666, |
| 785 | fbi->var.left_margin, | 785 | fbi->var.left_margin, |
| 786 | fbi->var.hsync_len, | 786 | fbi->var.hsync_len, |
| 787 | fbi->var.right_margin + | 787 | fbi->var.right_margin + |
| 788 | fbi->var.hsync_len, | 788 | fbi->var.hsync_len, |
| 789 | fbi->var.upper_margin, | 789 | fbi->var.upper_margin, |
| 790 | fbi->var.vsync_len, | 790 | fbi->var.vsync_len, |
| 791 | fbi->var.lower_margin + | 791 | fbi->var.lower_margin + |
| 792 | fbi->var.vsync_len, sig_cfg) != 0) { | 792 | fbi->var.vsync_len, sig_cfg) != 0) { |
| 793 | mutex_unlock(&mx3_fbi->mutex); | 793 | mutex_unlock(&mx3_fbi->mutex); |
| 794 | dev_err(fbi->device, | 794 | dev_err(fbi->device, |
| 795 | "mx3fb: Error initializing panel.\n"); | 795 | "mx3fb: Error initializing panel.\n"); |
| 796 | return -EINVAL; | 796 | return -EINVAL; |
| 797 | } | 797 | } |
| 798 | } | 798 | } |
| 799 | 799 | ||
| 800 | sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0); | 800 | sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0); |
| 801 | 801 | ||
| 802 | mx3_fbi->cur_ipu_buf = 0; | 802 | mx3_fbi->cur_ipu_buf = 0; |
| 803 | 803 | ||
| 804 | video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel); | 804 | video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel); |
| 805 | video->out_width = fbi->var.xres; | 805 | video->out_width = fbi->var.xres; |
| 806 | video->out_height = fbi->var.yres; | 806 | video->out_height = fbi->var.yres; |
| 807 | video->out_stride = fbi->var.xres_virtual; | 807 | video->out_stride = fbi->var.xres_virtual; |
| 808 | 808 | ||
| 809 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) | 809 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) |
| 810 | sdc_enable_channel(mx3_fbi); | 810 | sdc_enable_channel(mx3_fbi); |
| 811 | 811 | ||
| 812 | mutex_unlock(&mx3_fbi->mutex); | 812 | mutex_unlock(&mx3_fbi->mutex); |
| 813 | 813 | ||
| 814 | return 0; | 814 | return 0; |
| 815 | } | 815 | } |
| 816 | 816 | ||
| 817 | /** | 817 | /** |
| 818 | * mx3fb_check_var() - check and adjust framebuffer variable parameters. | 818 | * mx3fb_check_var() - check and adjust framebuffer variable parameters. |
| 819 | * @var: framebuffer variable parameters | 819 | * @var: framebuffer variable parameters |
| 820 | * @fbi: framebuffer information pointer | 820 | * @fbi: framebuffer information pointer |
| 821 | */ | 821 | */ |
| 822 | static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) | 822 | static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) |
| 823 | { | 823 | { |
| 824 | struct mx3fb_info *mx3_fbi = fbi->par; | 824 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 825 | u32 vtotal; | 825 | u32 vtotal; |
| 826 | u32 htotal; | 826 | u32 htotal; |
| 827 | 827 | ||
| 828 | dev_dbg(fbi->device, "%s\n", __func__); | 828 | dev_dbg(fbi->device, "%s\n", __func__); |
| 829 | 829 | ||
| 830 | if (var->xres_virtual < var->xres) | 830 | if (var->xres_virtual < var->xres) |
| 831 | var->xres_virtual = var->xres; | 831 | var->xres_virtual = var->xres; |
| 832 | if (var->yres_virtual < var->yres) | 832 | if (var->yres_virtual < var->yres) |
| 833 | var->yres_virtual = var->yres; | 833 | var->yres_virtual = var->yres; |
| 834 | 834 | ||
| 835 | if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && | 835 | if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && |
| 836 | (var->bits_per_pixel != 16)) | 836 | (var->bits_per_pixel != 16)) |
| 837 | var->bits_per_pixel = default_bpp; | 837 | var->bits_per_pixel = default_bpp; |
| 838 | 838 | ||
| 839 | switch (var->bits_per_pixel) { | 839 | switch (var->bits_per_pixel) { |
| 840 | case 16: | 840 | case 16: |
| 841 | var->red.length = 5; | 841 | var->red.length = 5; |
| 842 | var->red.offset = 11; | 842 | var->red.offset = 11; |
| 843 | var->red.msb_right = 0; | 843 | var->red.msb_right = 0; |
| 844 | 844 | ||
| 845 | var->green.length = 6; | 845 | var->green.length = 6; |
| 846 | var->green.offset = 5; | 846 | var->green.offset = 5; |
| 847 | var->green.msb_right = 0; | 847 | var->green.msb_right = 0; |
| 848 | 848 | ||
| 849 | var->blue.length = 5; | 849 | var->blue.length = 5; |
| 850 | var->blue.offset = 0; | 850 | var->blue.offset = 0; |
| 851 | var->blue.msb_right = 0; | 851 | var->blue.msb_right = 0; |
| 852 | 852 | ||
| 853 | var->transp.length = 0; | 853 | var->transp.length = 0; |
| 854 | var->transp.offset = 0; | 854 | var->transp.offset = 0; |
| 855 | var->transp.msb_right = 0; | 855 | var->transp.msb_right = 0; |
| 856 | break; | 856 | break; |
| 857 | case 24: | 857 | case 24: |
| 858 | var->red.length = 8; | 858 | var->red.length = 8; |
| 859 | var->red.offset = 16; | 859 | var->red.offset = 16; |
| 860 | var->red.msb_right = 0; | 860 | var->red.msb_right = 0; |
| 861 | 861 | ||
| 862 | var->green.length = 8; | 862 | var->green.length = 8; |
| 863 | var->green.offset = 8; | 863 | var->green.offset = 8; |
| 864 | var->green.msb_right = 0; | 864 | var->green.msb_right = 0; |
| 865 | 865 | ||
| 866 | var->blue.length = 8; | 866 | var->blue.length = 8; |
| 867 | var->blue.offset = 0; | 867 | var->blue.offset = 0; |
| 868 | var->blue.msb_right = 0; | 868 | var->blue.msb_right = 0; |
| 869 | 869 | ||
| 870 | var->transp.length = 0; | 870 | var->transp.length = 0; |
| 871 | var->transp.offset = 0; | 871 | var->transp.offset = 0; |
| 872 | var->transp.msb_right = 0; | 872 | var->transp.msb_right = 0; |
| 873 | break; | 873 | break; |
| 874 | case 32: | 874 | case 32: |
| 875 | var->red.length = 8; | 875 | var->red.length = 8; |
| 876 | var->red.offset = 16; | 876 | var->red.offset = 16; |
| 877 | var->red.msb_right = 0; | 877 | var->red.msb_right = 0; |
| 878 | 878 | ||
| 879 | var->green.length = 8; | 879 | var->green.length = 8; |
| 880 | var->green.offset = 8; | 880 | var->green.offset = 8; |
| 881 | var->green.msb_right = 0; | 881 | var->green.msb_right = 0; |
| 882 | 882 | ||
| 883 | var->blue.length = 8; | 883 | var->blue.length = 8; |
| 884 | var->blue.offset = 0; | 884 | var->blue.offset = 0; |
| 885 | var->blue.msb_right = 0; | 885 | var->blue.msb_right = 0; |
| 886 | 886 | ||
| 887 | var->transp.length = 8; | 887 | var->transp.length = 8; |
| 888 | var->transp.offset = 24; | 888 | var->transp.offset = 24; |
| 889 | var->transp.msb_right = 0; | 889 | var->transp.msb_right = 0; |
| 890 | break; | 890 | break; |
| 891 | } | 891 | } |
| 892 | 892 | ||
| 893 | if (var->pixclock < 1000) { | 893 | if (var->pixclock < 1000) { |
| 894 | htotal = var->xres + var->right_margin + var->hsync_len + | 894 | htotal = var->xres + var->right_margin + var->hsync_len + |
| 895 | var->left_margin; | 895 | var->left_margin; |
| 896 | vtotal = var->yres + var->lower_margin + var->vsync_len + | 896 | vtotal = var->yres + var->lower_margin + var->vsync_len + |
| 897 | var->upper_margin; | 897 | var->upper_margin; |
| 898 | var->pixclock = (vtotal * htotal * 6UL) / 100UL; | 898 | var->pixclock = (vtotal * htotal * 6UL) / 100UL; |
| 899 | var->pixclock = KHZ2PICOS(var->pixclock); | 899 | var->pixclock = KHZ2PICOS(var->pixclock); |
| 900 | dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n", | 900 | dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n", |
| 901 | var->pixclock); | 901 | var->pixclock); |
| 902 | } | 902 | } |
| 903 | 903 | ||
| 904 | var->height = -1; | 904 | var->height = -1; |
| 905 | var->width = -1; | 905 | var->width = -1; |
| 906 | var->grayscale = 0; | 906 | var->grayscale = 0; |
| 907 | 907 | ||
| 908 | /* Preserve sync flags */ | 908 | /* Preserve sync flags */ |
| 909 | var->sync |= mx3_fbi->sync; | 909 | var->sync |= mx3_fbi->sync; |
| 910 | mx3_fbi->sync |= var->sync; | 910 | mx3_fbi->sync |= var->sync; |
| 911 | 911 | ||
| 912 | return 0; | 912 | return 0; |
| 913 | } | 913 | } |
| 914 | 914 | ||
| 915 | static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf) | 915 | static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf) |
| 916 | { | 916 | { |
| 917 | chan &= 0xffff; | 917 | chan &= 0xffff; |
| 918 | chan >>= 16 - bf->length; | 918 | chan >>= 16 - bf->length; |
| 919 | return chan << bf->offset; | 919 | return chan << bf->offset; |
| 920 | } | 920 | } |
| 921 | 921 | ||
| 922 | static int mx3fb_setcolreg(unsigned int regno, unsigned int red, | 922 | static int mx3fb_setcolreg(unsigned int regno, unsigned int red, |
| 923 | unsigned int green, unsigned int blue, | 923 | unsigned int green, unsigned int blue, |
| 924 | unsigned int trans, struct fb_info *fbi) | 924 | unsigned int trans, struct fb_info *fbi) |
| 925 | { | 925 | { |
| 926 | struct mx3fb_info *mx3_fbi = fbi->par; | 926 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 927 | u32 val; | 927 | u32 val; |
| 928 | int ret = 1; | 928 | int ret = 1; |
| 929 | 929 | ||
| 930 | dev_dbg(fbi->device, "%s\n", __func__); | 930 | dev_dbg(fbi->device, "%s\n", __func__); |
| 931 | 931 | ||
| 932 | mutex_lock(&mx3_fbi->mutex); | 932 | mutex_lock(&mx3_fbi->mutex); |
| 933 | /* | 933 | /* |
| 934 | * If greyscale is true, then we convert the RGB value | 934 | * If greyscale is true, then we convert the RGB value |
| 935 | * to greyscale no matter what visual we are using. | 935 | * to greyscale no matter what visual we are using. |
| 936 | */ | 936 | */ |
| 937 | if (fbi->var.grayscale) | 937 | if (fbi->var.grayscale) |
| 938 | red = green = blue = (19595 * red + 38470 * green + | 938 | red = green = blue = (19595 * red + 38470 * green + |
| 939 | 7471 * blue) >> 16; | 939 | 7471 * blue) >> 16; |
| 940 | switch (fbi->fix.visual) { | 940 | switch (fbi->fix.visual) { |
| 941 | case FB_VISUAL_TRUECOLOR: | 941 | case FB_VISUAL_TRUECOLOR: |
| 942 | /* | 942 | /* |
| 943 | * 16-bit True Colour. We encode the RGB value | 943 | * 16-bit True Colour. We encode the RGB value |
| 944 | * according to the RGB bitfield information. | 944 | * according to the RGB bitfield information. |
| 945 | */ | 945 | */ |
| 946 | if (regno < 16) { | 946 | if (regno < 16) { |
| 947 | u32 *pal = fbi->pseudo_palette; | 947 | u32 *pal = fbi->pseudo_palette; |
| 948 | 948 | ||
| 949 | val = chan_to_field(red, &fbi->var.red); | 949 | val = chan_to_field(red, &fbi->var.red); |
| 950 | val |= chan_to_field(green, &fbi->var.green); | 950 | val |= chan_to_field(green, &fbi->var.green); |
| 951 | val |= chan_to_field(blue, &fbi->var.blue); | 951 | val |= chan_to_field(blue, &fbi->var.blue); |
| 952 | 952 | ||
| 953 | pal[regno] = val; | 953 | pal[regno] = val; |
| 954 | 954 | ||
| 955 | ret = 0; | 955 | ret = 0; |
| 956 | } | 956 | } |
| 957 | break; | 957 | break; |
| 958 | 958 | ||
| 959 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | 959 | case FB_VISUAL_STATIC_PSEUDOCOLOR: |
| 960 | case FB_VISUAL_PSEUDOCOLOR: | 960 | case FB_VISUAL_PSEUDOCOLOR: |
| 961 | break; | 961 | break; |
| 962 | } | 962 | } |
| 963 | mutex_unlock(&mx3_fbi->mutex); | 963 | mutex_unlock(&mx3_fbi->mutex); |
| 964 | 964 | ||
| 965 | return ret; | 965 | return ret; |
| 966 | } | 966 | } |
| 967 | 967 | ||
| 968 | /** | 968 | /** |
| @@ -970,152 +970,152 @@ static int mx3fb_setcolreg(unsigned int regno, unsigned int red, | |||
| 970 | */ | 970 | */ |
| 971 | static int mx3fb_blank(int blank, struct fb_info *fbi) | 971 | static int mx3fb_blank(int blank, struct fb_info *fbi) |
| 972 | { | 972 | { |
| 973 | struct mx3fb_info *mx3_fbi = fbi->par; | 973 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 974 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 974 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 975 | 975 | ||
| 976 | dev_dbg(fbi->device, "%s\n", __func__); | 976 | dev_dbg(fbi->device, "%s\n", __func__); |
| 977 | 977 | ||
| 978 | dev_dbg(fbi->device, "blank = %d\n", blank); | 978 | dev_dbg(fbi->device, "blank = %d\n", blank); |
| 979 | 979 | ||
| 980 | if (mx3_fbi->blank == blank) | 980 | if (mx3_fbi->blank == blank) |
| 981 | return 0; | 981 | return 0; |
| 982 | 982 | ||
| 983 | mutex_lock(&mx3_fbi->mutex); | 983 | mutex_lock(&mx3_fbi->mutex); |
| 984 | mx3_fbi->blank = blank; | 984 | mx3_fbi->blank = blank; |
| 985 | 985 | ||
| 986 | switch (blank) { | 986 | switch (blank) { |
| 987 | case FB_BLANK_POWERDOWN: | 987 | case FB_BLANK_POWERDOWN: |
| 988 | case FB_BLANK_VSYNC_SUSPEND: | 988 | case FB_BLANK_VSYNC_SUSPEND: |
| 989 | case FB_BLANK_HSYNC_SUSPEND: | 989 | case FB_BLANK_HSYNC_SUSPEND: |
| 990 | case FB_BLANK_NORMAL: | 990 | case FB_BLANK_NORMAL: |
| 991 | sdc_disable_channel(mx3_fbi); | 991 | sdc_disable_channel(mx3_fbi); |
| 992 | sdc_set_brightness(mx3fb, 0); | 992 | sdc_set_brightness(mx3fb, 0); |
| 993 | break; | 993 | break; |
| 994 | case FB_BLANK_UNBLANK: | 994 | case FB_BLANK_UNBLANK: |
| 995 | sdc_enable_channel(mx3_fbi); | 995 | sdc_enable_channel(mx3_fbi); |
| 996 | sdc_set_brightness(mx3fb, mx3fb->backlight_level); | 996 | sdc_set_brightness(mx3fb, mx3fb->backlight_level); |
| 997 | break; | 997 | break; |
| 998 | } | 998 | } |
| 999 | mutex_unlock(&mx3_fbi->mutex); | 999 | mutex_unlock(&mx3_fbi->mutex); |
| 1000 | 1000 | ||
| 1001 | return 0; | 1001 | return 0; |
| 1002 | } | 1002 | } |
| 1003 | 1003 | ||
| 1004 | /** | 1004 | /** |
| 1005 | * mx3fb_pan_display() - pan or wrap the display | 1005 | * mx3fb_pan_display() - pan or wrap the display |
| 1006 | * @var: variable screen buffer information. | 1006 | * @var: variable screen buffer information. |
| 1007 | * @info: framebuffer information pointer. | 1007 | * @info: framebuffer information pointer. |
| 1008 | * | 1008 | * |
| 1009 | * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag | 1009 | * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag |
| 1010 | */ | 1010 | */ |
| 1011 | static int mx3fb_pan_display(struct fb_var_screeninfo *var, | 1011 | static int mx3fb_pan_display(struct fb_var_screeninfo *var, |
| 1012 | struct fb_info *fbi) | 1012 | struct fb_info *fbi) |
| 1013 | { | 1013 | { |
| 1014 | struct mx3fb_info *mx3_fbi = fbi->par; | 1014 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 1015 | u32 y_bottom; | 1015 | u32 y_bottom; |
| 1016 | unsigned long base; | 1016 | unsigned long base; |
| 1017 | off_t offset; | 1017 | off_t offset; |
| 1018 | dma_cookie_t cookie; | 1018 | dma_cookie_t cookie; |
| 1019 | struct scatterlist *sg = mx3_fbi->sg; | 1019 | struct scatterlist *sg = mx3_fbi->sg; |
| 1020 | struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan; | 1020 | struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan; |
| 1021 | struct dma_async_tx_descriptor *txd; | 1021 | struct dma_async_tx_descriptor *txd; |
| 1022 | int ret; | 1022 | int ret; |
| 1023 | 1023 | ||
| 1024 | dev_dbg(fbi->device, "%s [%c]\n", __func__, | 1024 | dev_dbg(fbi->device, "%s [%c]\n", __func__, |
| 1025 | list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+'); | 1025 | list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+'); |
| 1026 | 1026 | ||
| 1027 | if (var->xoffset > 0) { | 1027 | if (var->xoffset > 0) { |
| 1028 | dev_dbg(fbi->device, "x panning not supported\n"); | 1028 | dev_dbg(fbi->device, "x panning not supported\n"); |
| 1029 | return -EINVAL; | 1029 | return -EINVAL; |
| 1030 | } | 1030 | } |
| 1031 | 1031 | ||
| 1032 | if (fbi->var.xoffset == var->xoffset && | 1032 | if (fbi->var.xoffset == var->xoffset && |
| 1033 | fbi->var.yoffset == var->yoffset) | 1033 | fbi->var.yoffset == var->yoffset) |
| 1034 | return 0; /* No change, do nothing */ | 1034 | return 0; /* No change, do nothing */ |
| 1035 | 1035 | ||
| 1036 | y_bottom = var->yoffset; | 1036 | y_bottom = var->yoffset; |
| 1037 | 1037 | ||
| 1038 | if (!(var->vmode & FB_VMODE_YWRAP)) | 1038 | if (!(var->vmode & FB_VMODE_YWRAP)) |
| 1039 | y_bottom += var->yres; | 1039 | y_bottom += var->yres; |
| 1040 | 1040 | ||
| 1041 | if (y_bottom > fbi->var.yres_virtual) | 1041 | if (y_bottom > fbi->var.yres_virtual) |
| 1042 | return -EINVAL; | 1042 | return -EINVAL; |
| 1043 | 1043 | ||
| 1044 | mutex_lock(&mx3_fbi->mutex); | 1044 | mutex_lock(&mx3_fbi->mutex); |
| 1045 | 1045 | ||
| 1046 | offset = (var->yoffset * var->xres_virtual + var->xoffset) * | 1046 | offset = (var->yoffset * var->xres_virtual + var->xoffset) * |
| 1047 | (var->bits_per_pixel / 8); | 1047 | (var->bits_per_pixel / 8); |
| 1048 | base = fbi->fix.smem_start + offset; | 1048 | base = fbi->fix.smem_start + offset; |
| 1049 | 1049 | ||
| 1050 | dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n", | 1050 | dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n", |
| 1051 | mx3_fbi->cur_ipu_buf, base); | 1051 | mx3_fbi->cur_ipu_buf, base); |
| 1052 | 1052 | ||
| 1053 | /* | 1053 | /* |
| 1054 | * We enable the End of Frame interrupt, which will free a tx-descriptor, | 1054 | * We enable the End of Frame interrupt, which will free a tx-descriptor, |
| 1055 | * which we will need for the next device_prep_slave_sg(). The | 1055 | * which we will need for the next device_prep_slave_sg(). The |
| 1056 | * IRQ-handler will disable the IRQ again. | 1056 | * IRQ-handler will disable the IRQ again. |
| 1057 | */ | 1057 | */ |
| 1058 | init_completion(&mx3_fbi->flip_cmpl); | 1058 | init_completion(&mx3_fbi->flip_cmpl); |
| 1059 | enable_irq(mx3_fbi->idmac_channel->eof_irq); | 1059 | enable_irq(mx3_fbi->idmac_channel->eof_irq); |
| 1060 | 1060 | ||
| 1061 | ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10); | 1061 | ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10); |
| 1062 | if (ret <= 0) { | 1062 | if (ret <= 0) { |
| 1063 | mutex_unlock(&mx3_fbi->mutex); | 1063 | mutex_unlock(&mx3_fbi->mutex); |
| 1064 | dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ? | 1064 | dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ? |
| 1065 | "user interrupt" : "timeout"); | 1065 | "user interrupt" : "timeout"); |
| 1066 | return ret ? : -ETIMEDOUT; | 1066 | return ret ? : -ETIMEDOUT; |
| 1067 | } | 1067 | } |
| 1068 | 1068 | ||
| 1069 | mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf; | 1069 | mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf; |
| 1070 | 1070 | ||
| 1071 | sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base; | 1071 | sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base; |
| 1072 | sg_set_page(&sg[mx3_fbi->cur_ipu_buf], | 1072 | sg_set_page(&sg[mx3_fbi->cur_ipu_buf], |
| 1073 | virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len, | 1073 | virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len, |
| 1074 | offset_in_page(fbi->screen_base + offset)); | 1074 | offset_in_page(fbi->screen_base + offset)); |
| 1075 | 1075 | ||
| 1076 | txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg + | 1076 | txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg + |
| 1077 | mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); | 1077 | mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); |
| 1078 | if (!txd) { | 1078 | if (!txd) { |
| 1079 | dev_err(fbi->device, | 1079 | dev_err(fbi->device, |
| 1080 | "Error preparing a DMA transaction descriptor.\n"); | 1080 | "Error preparing a DMA transaction descriptor.\n"); |
| 1081 | mutex_unlock(&mx3_fbi->mutex); | 1081 | mutex_unlock(&mx3_fbi->mutex); |
| 1082 | return -EIO; | 1082 | return -EIO; |
| 1083 | } | 1083 | } |
| 1084 | 1084 | ||
| 1085 | txd->callback_param = txd; | 1085 | txd->callback_param = txd; |
| 1086 | txd->callback = mx3fb_dma_done; | 1086 | txd->callback = mx3fb_dma_done; |
| 1087 | 1087 | ||
| 1088 | /* | 1088 | /* |
| 1089 | * Emulate original mx3fb behaviour: each new call to idmac_tx_submit() | 1089 | * Emulate original mx3fb behaviour: each new call to idmac_tx_submit() |
| 1090 | * should switch to another buffer | 1090 | * should switch to another buffer |
| 1091 | */ | 1091 | */ |
| 1092 | cookie = txd->tx_submit(txd); | 1092 | cookie = txd->tx_submit(txd); |
| 1093 | dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie); | 1093 | dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie); |
| 1094 | if (cookie < 0) { | 1094 | if (cookie < 0) { |
| 1095 | dev_err(fbi->device, | 1095 | dev_err(fbi->device, |
| 1096 | "Error updating SDC buf %d to address=0x%08lX\n", | 1096 | "Error updating SDC buf %d to address=0x%08lX\n", |
| 1097 | mx3_fbi->cur_ipu_buf, base); | 1097 | mx3_fbi->cur_ipu_buf, base); |
| 1098 | mutex_unlock(&mx3_fbi->mutex); | 1098 | mutex_unlock(&mx3_fbi->mutex); |
| 1099 | return -EIO; | 1099 | return -EIO; |
| 1100 | } | 1100 | } |
| 1101 | 1101 | ||
| 1102 | if (mx3_fbi->txd) | 1102 | if (mx3_fbi->txd) |
| 1103 | async_tx_ack(mx3_fbi->txd); | 1103 | async_tx_ack(mx3_fbi->txd); |
| 1104 | mx3_fbi->txd = txd; | 1104 | mx3_fbi->txd = txd; |
| 1105 | 1105 | ||
| 1106 | fbi->var.xoffset = var->xoffset; | 1106 | fbi->var.xoffset = var->xoffset; |
| 1107 | fbi->var.yoffset = var->yoffset; | 1107 | fbi->var.yoffset = var->yoffset; |
| 1108 | 1108 | ||
| 1109 | if (var->vmode & FB_VMODE_YWRAP) | 1109 | if (var->vmode & FB_VMODE_YWRAP) |
| 1110 | fbi->var.vmode |= FB_VMODE_YWRAP; | 1110 | fbi->var.vmode |= FB_VMODE_YWRAP; |
| 1111 | else | 1111 | else |
| 1112 | fbi->var.vmode &= ~FB_VMODE_YWRAP; | 1112 | fbi->var.vmode &= ~FB_VMODE_YWRAP; |
| 1113 | 1113 | ||
| 1114 | mutex_unlock(&mx3_fbi->mutex); | 1114 | mutex_unlock(&mx3_fbi->mutex); |
| 1115 | 1115 | ||
| 1116 | dev_dbg(fbi->device, "Update complete\n"); | 1116 | dev_dbg(fbi->device, "Update complete\n"); |
| 1117 | 1117 | ||
| 1118 | return 0; | 1118 | return 0; |
| 1119 | } | 1119 | } |
| 1120 | 1120 | ||
| 1121 | /* | 1121 | /* |
| @@ -1124,15 +1124,15 @@ static int mx3fb_pan_display(struct fb_var_screeninfo *var, | |||
| 1124 | * blitting, rectangle filling, copy regions and cursor definition. | 1124 | * blitting, rectangle filling, copy regions and cursor definition. |
| 1125 | */ | 1125 | */ |
| 1126 | static struct fb_ops mx3fb_ops = { | 1126 | static struct fb_ops mx3fb_ops = { |
| 1127 | .owner = THIS_MODULE, | 1127 | .owner = THIS_MODULE, |
| 1128 | .fb_set_par = mx3fb_set_par, | 1128 | .fb_set_par = mx3fb_set_par, |
| 1129 | .fb_check_var = mx3fb_check_var, | 1129 | .fb_check_var = mx3fb_check_var, |
| 1130 | .fb_setcolreg = mx3fb_setcolreg, | 1130 | .fb_setcolreg = mx3fb_setcolreg, |
| 1131 | .fb_pan_display = mx3fb_pan_display, | 1131 | .fb_pan_display = mx3fb_pan_display, |
| 1132 | .fb_fillrect = cfb_fillrect, | 1132 | .fb_fillrect = cfb_fillrect, |
| 1133 | .fb_copyarea = cfb_copyarea, | 1133 | .fb_copyarea = cfb_copyarea, |
| 1134 | .fb_imageblit = cfb_imageblit, | 1134 | .fb_imageblit = cfb_imageblit, |
| 1135 | .fb_blank = mx3fb_blank, | 1135 | .fb_blank = mx3fb_blank, |
| 1136 | }; | 1136 | }; |
| 1137 | 1137 | ||
| 1138 | #ifdef CONFIG_PM | 1138 | #ifdef CONFIG_PM |
| @@ -1146,19 +1146,19 @@ static struct fb_ops mx3fb_ops = { | |||
| 1146 | */ | 1146 | */ |
| 1147 | static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state) | 1147 | static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state) |
| 1148 | { | 1148 | { |
| 1149 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); | 1149 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); |
| 1150 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; | 1150 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; |
| 1151 | 1151 | ||
| 1152 | acquire_console_sem(); | 1152 | acquire_console_sem(); |
| 1153 | fb_set_suspend(drv_data->fbi, 1); | 1153 | fb_set_suspend(drv_data->fbi, 1); |
| 1154 | release_console_sem(); | 1154 | release_console_sem(); |
| 1155 | 1155 | ||
| 1156 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { | 1156 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { |
| 1157 | sdc_disable_channel(mx3_fbi); | 1157 | sdc_disable_channel(mx3_fbi); |
| 1158 | sdc_set_brightness(mx3fb, 0); | 1158 | sdc_set_brightness(mx3fb, 0); |
| 1159 | 1159 | ||
| 1160 | } | 1160 | } |
| 1161 | return 0; | 1161 | return 0; |
| 1162 | } | 1162 | } |
| 1163 | 1163 | ||
| 1164 | /* | 1164 | /* |
| @@ -1166,19 +1166,19 @@ static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state) | |||
| 1166 | */ | 1166 | */ |
| 1167 | static int mx3fb_resume(struct platform_device *pdev) | 1167 | static int mx3fb_resume(struct platform_device *pdev) |
| 1168 | { | 1168 | { |
| 1169 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); | 1169 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); |
| 1170 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; | 1170 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; |
| 1171 | 1171 | ||
| 1172 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { | 1172 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { |
| 1173 | sdc_enable_channel(mx3_fbi); | 1173 | sdc_enable_channel(mx3_fbi); |
| 1174 | sdc_set_brightness(mx3fb, drv_data->backlight_level); | 1174 | sdc_set_brightness(mx3fb, drv_data->backlight_level); |
| 1175 | } | 1175 | } |
| 1176 | 1176 | ||
| 1177 | acquire_console_sem(); | 1177 | acquire_console_sem(); |
| 1178 | fb_set_suspend(drv_data->fbi, 0); | 1178 | fb_set_suspend(drv_data->fbi, 0); |
| 1179 | release_console_sem(); | 1179 | release_console_sem(); |
| 1180 | 1180 | ||
| 1181 | return 0; | 1181 | return 0; |
| 1182 | } | 1182 | } |
| 1183 | #else | 1183 | #else |
| 1184 | #define mx3fb_suspend NULL | 1184 | #define mx3fb_suspend NULL |
| @@ -1191,8 +1191,8 @@ static int mx3fb_resume(struct platform_device *pdev) | |||
| 1191 | 1191 | ||
| 1192 | /** | 1192 | /** |
| 1193 | * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer. | 1193 | * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer. |
| 1194 | * @fbi: framebuffer information pointer | 1194 | * @fbi: framebuffer information pointer |
| 1195 | * @return: Error code indicating success or failure | 1195 | * @return: Error code indicating success or failure |
| 1196 | * | 1196 | * |
| 1197 | * This buffer is remapped into a non-cached, non-buffered, memory region to | 1197 | * This buffer is remapped into a non-cached, non-buffered, memory region to |
| 1198 | * allow palette and pixel writes to occur without flushing the cache. Once this | 1198 | * allow palette and pixel writes to occur without flushing the cache. Once this |
| @@ -1201,349 +1201,349 @@ static int mx3fb_resume(struct platform_device *pdev) | |||
| 1201 | */ | 1201 | */ |
| 1202 | static int mx3fb_map_video_memory(struct fb_info *fbi) | 1202 | static int mx3fb_map_video_memory(struct fb_info *fbi) |
| 1203 | { | 1203 | { |
| 1204 | int retval = 0; | 1204 | int retval = 0; |
| 1205 | dma_addr_t addr; | 1205 | dma_addr_t addr; |
| 1206 | 1206 | ||
| 1207 | fbi->screen_base = dma_alloc_writecombine(fbi->device, | 1207 | fbi->screen_base = dma_alloc_writecombine(fbi->device, |
| 1208 | fbi->fix.smem_len, | 1208 | fbi->fix.smem_len, |
| 1209 | &addr, GFP_DMA); | 1209 | &addr, GFP_DMA); |
| 1210 | 1210 | ||
| 1211 | if (!fbi->screen_base) { | 1211 | if (!fbi->screen_base) { |
| 1212 | dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n", | 1212 | dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n", |
| 1213 | fbi->fix.smem_len); | 1213 | fbi->fix.smem_len); |
| 1214 | retval = -EBUSY; | 1214 | retval = -EBUSY; |
| 1215 | goto err0; | 1215 | goto err0; |
| 1216 | } | 1216 | } |
| 1217 | 1217 | ||
| 1218 | fbi->fix.smem_start = addr; | 1218 | fbi->fix.smem_start = addr; |
| 1219 | 1219 | ||
| 1220 | dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n", | 1220 | dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n", |
| 1221 | (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len); | 1221 | (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len); |
| 1222 | 1222 | ||
| 1223 | fbi->screen_size = fbi->fix.smem_len; | 1223 | fbi->screen_size = fbi->fix.smem_len; |
| 1224 | 1224 | ||
| 1225 | /* Clear the screen */ | 1225 | /* Clear the screen */ |
| 1226 | memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); | 1226 | memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); |
| 1227 | 1227 | ||
| 1228 | return 0; | 1228 | return 0; |
| 1229 | 1229 | ||
| 1230 | err0: | 1230 | err0: |
| 1231 | fbi->fix.smem_len = 0; | 1231 | fbi->fix.smem_len = 0; |
| 1232 | fbi->fix.smem_start = 0; | 1232 | fbi->fix.smem_start = 0; |
| 1233 | fbi->screen_base = NULL; | 1233 | fbi->screen_base = NULL; |
| 1234 | return retval; | 1234 | return retval; |
| 1235 | } | 1235 | } |
| 1236 | 1236 | ||
| 1237 | /** | 1237 | /** |
| 1238 | * mx3fb_unmap_video_memory() - de-allocate frame buffer memory. | 1238 | * mx3fb_unmap_video_memory() - de-allocate frame buffer memory. |
| 1239 | * @fbi: framebuffer information pointer | 1239 | * @fbi: framebuffer information pointer |
| 1240 | * @return: error code indicating success or failure | 1240 | * @return: error code indicating success or failure |
| 1241 | */ | 1241 | */ |
| 1242 | static int mx3fb_unmap_video_memory(struct fb_info *fbi) | 1242 | static int mx3fb_unmap_video_memory(struct fb_info *fbi) |
| 1243 | { | 1243 | { |
| 1244 | dma_free_writecombine(fbi->device, fbi->fix.smem_len, | 1244 | dma_free_writecombine(fbi->device, fbi->fix.smem_len, |
| 1245 | fbi->screen_base, fbi->fix.smem_start); | 1245 | fbi->screen_base, fbi->fix.smem_start); |
| 1246 | 1246 | ||
| 1247 | fbi->screen_base = 0; | 1247 | fbi->screen_base = 0; |
| 1248 | fbi->fix.smem_start = 0; | 1248 | fbi->fix.smem_start = 0; |
| 1249 | fbi->fix.smem_len = 0; | 1249 | fbi->fix.smem_len = 0; |
| 1250 | return 0; | 1250 | return 0; |
| 1251 | } | 1251 | } |
| 1252 | 1252 | ||
| 1253 | /** | 1253 | /** |
| 1254 | * mx3fb_init_fbinfo() - initialize framebuffer information object. | 1254 | * mx3fb_init_fbinfo() - initialize framebuffer information object. |
| 1255 | * @return: initialized framebuffer structure. | 1255 | * @return: initialized framebuffer structure. |
| 1256 | */ | 1256 | */ |
| 1257 | static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops) | 1257 | static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops) |
| 1258 | { | 1258 | { |
| 1259 | struct fb_info *fbi; | 1259 | struct fb_info *fbi; |
| 1260 | struct mx3fb_info *mx3fbi; | 1260 | struct mx3fb_info *mx3fbi; |
| 1261 | int ret; | 1261 | int ret; |
| 1262 | 1262 | ||
| 1263 | /* Allocate sufficient memory for the fb structure */ | 1263 | /* Allocate sufficient memory for the fb structure */ |
| 1264 | fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev); | 1264 | fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev); |
| 1265 | if (!fbi) | 1265 | if (!fbi) |
| 1266 | return NULL; | 1266 | return NULL; |
| 1267 | 1267 | ||
| 1268 | mx3fbi = fbi->par; | 1268 | mx3fbi = fbi->par; |
| 1269 | mx3fbi->cookie = -EINVAL; | 1269 | mx3fbi->cookie = -EINVAL; |
| 1270 | mx3fbi->cur_ipu_buf = 0; | 1270 | mx3fbi->cur_ipu_buf = 0; |
| 1271 | 1271 | ||
| 1272 | fbi->var.activate = FB_ACTIVATE_NOW; | 1272 | fbi->var.activate = FB_ACTIVATE_NOW; |
| 1273 | 1273 | ||
| 1274 | fbi->fbops = ops; | 1274 | fbi->fbops = ops; |
| 1275 | fbi->flags = FBINFO_FLAG_DEFAULT; | 1275 | fbi->flags = FBINFO_FLAG_DEFAULT; |
| 1276 | fbi->pseudo_palette = mx3fbi->pseudo_palette; | 1276 | fbi->pseudo_palette = mx3fbi->pseudo_palette; |
| 1277 | 1277 | ||
| 1278 | mutex_init(&mx3fbi->mutex); | 1278 | mutex_init(&mx3fbi->mutex); |
| 1279 | 1279 | ||
| 1280 | /* Allocate colormap */ | 1280 | /* Allocate colormap */ |
| 1281 | ret = fb_alloc_cmap(&fbi->cmap, 16, 0); | 1281 | ret = fb_alloc_cmap(&fbi->cmap, 16, 0); |
| 1282 | if (ret < 0) { | 1282 | if (ret < 0) { |
| 1283 | framebuffer_release(fbi); | 1283 | framebuffer_release(fbi); |
| 1284 | return NULL; | 1284 | return NULL; |
| 1285 | } | 1285 | } |
| 1286 | 1286 | ||
| 1287 | return fbi; | 1287 | return fbi; |
| 1288 | } | 1288 | } |
| 1289 | 1289 | ||
| 1290 | static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan) | 1290 | static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan) |
| 1291 | { | 1291 | { |
| 1292 | struct device *dev = mx3fb->dev; | 1292 | struct device *dev = mx3fb->dev; |
| 1293 | struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data; | 1293 | struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data; |
| 1294 | const char *name = mx3fb_pdata->name; | 1294 | const char *name = mx3fb_pdata->name; |
| 1295 | unsigned int irq; | 1295 | unsigned int irq; |
| 1296 | struct fb_info *fbi; | 1296 | struct fb_info *fbi; |
| 1297 | struct mx3fb_info *mx3fbi; | 1297 | struct mx3fb_info *mx3fbi; |
| 1298 | const struct fb_videomode *mode; | 1298 | const struct fb_videomode *mode; |
| 1299 | int ret, num_modes; | 1299 | int ret, num_modes; |
| 1300 | 1300 | ||
| 1301 | ichan->client = mx3fb; | 1301 | ichan->client = mx3fb; |
| 1302 | irq = ichan->eof_irq; | 1302 | irq = ichan->eof_irq; |
| 1303 | 1303 | ||
| 1304 | if (ichan->dma_chan.chan_id != IDMAC_SDC_0) | 1304 | if (ichan->dma_chan.chan_id != IDMAC_SDC_0) |
| 1305 | return -EINVAL; | 1305 | return -EINVAL; |
| 1306 | 1306 | ||
| 1307 | fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops); | 1307 | fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops); |
| 1308 | if (!fbi) | 1308 | if (!fbi) |
| 1309 | return -ENOMEM; | 1309 | return -ENOMEM; |
| 1310 | 1310 | ||
| 1311 | if (!fb_mode) | 1311 | if (!fb_mode) |
| 1312 | fb_mode = name; | 1312 | fb_mode = name; |
| 1313 | 1313 | ||
| 1314 | if (!fb_mode) { | 1314 | if (!fb_mode) { |
| 1315 | ret = -EINVAL; | 1315 | ret = -EINVAL; |
| 1316 | goto emode; | 1316 | goto emode; |
| 1317 | } | 1317 | } |
| 1318 | 1318 | ||
| 1319 | if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) { | 1319 | if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) { |
| 1320 | mode = mx3fb_pdata->mode; | 1320 | mode = mx3fb_pdata->mode; |
| 1321 | num_modes = mx3fb_pdata->num_modes; | 1321 | num_modes = mx3fb_pdata->num_modes; |
| 1322 | } else { | 1322 | } else { |
| 1323 | mode = mx3fb_modedb; | 1323 | mode = mx3fb_modedb; |
| 1324 | num_modes = ARRAY_SIZE(mx3fb_modedb); | 1324 | num_modes = ARRAY_SIZE(mx3fb_modedb); |
| 1325 | } | 1325 | } |
| 1326 | 1326 | ||
| 1327 | if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode, | 1327 | if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode, |
| 1328 | num_modes, NULL, default_bpp)) { | 1328 | num_modes, NULL, default_bpp)) { |
| 1329 | ret = -EBUSY; | 1329 | ret = -EBUSY; |
| 1330 | goto emode; | 1330 | goto emode; |
| 1331 | } | 1331 | } |
| 1332 | 1332 | ||
| 1333 | fb_videomode_to_modelist(mode, num_modes, &fbi->modelist); | 1333 | fb_videomode_to_modelist(mode, num_modes, &fbi->modelist); |
| 1334 | 1334 | ||
| 1335 | /* Default Y virtual size is 2x panel size */ | 1335 | /* Default Y virtual size is 2x panel size */ |
| 1336 | fbi->var.yres_virtual = fbi->var.yres * 2; | 1336 | fbi->var.yres_virtual = fbi->var.yres * 2; |
| 1337 | 1337 | ||
| 1338 | mx3fb->fbi = fbi; | 1338 | mx3fb->fbi = fbi; |
| 1339 | 1339 | ||
| 1340 | /* set Display Interface clock period */ | 1340 | /* set Display Interface clock period */ |
| 1341 | mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER); | 1341 | mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER); |
| 1342 | /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ | 1342 | /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ |
| 1343 | 1343 | ||
| 1344 | sdc_set_brightness(mx3fb, 255); | 1344 | sdc_set_brightness(mx3fb, 255); |
| 1345 | sdc_set_global_alpha(mx3fb, true, 0xFF); | 1345 | sdc_set_global_alpha(mx3fb, true, 0xFF); |
| 1346 | sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0); | 1346 | sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0); |
| 1347 | 1347 | ||
| 1348 | mx3fbi = fbi->par; | 1348 | mx3fbi = fbi->par; |
| 1349 | mx3fbi->idmac_channel = ichan; | 1349 | mx3fbi->idmac_channel = ichan; |
| 1350 | mx3fbi->ipu_ch = ichan->dma_chan.chan_id; | 1350 | mx3fbi->ipu_ch = ichan->dma_chan.chan_id; |
| 1351 | mx3fbi->mx3fb = mx3fb; | 1351 | mx3fbi->mx3fb = mx3fb; |
| 1352 | mx3fbi->blank = FB_BLANK_NORMAL; | 1352 | mx3fbi->blank = FB_BLANK_NORMAL; |
| 1353 | 1353 | ||
| 1354 | init_completion(&mx3fbi->flip_cmpl); | 1354 | init_completion(&mx3fbi->flip_cmpl); |
| 1355 | disable_irq(ichan->eof_irq); | 1355 | disable_irq(ichan->eof_irq); |
| 1356 | dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq); | 1356 | dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq); |
| 1357 | ret = mx3fb_set_par(fbi); | 1357 | ret = mx3fb_set_par(fbi); |
| 1358 | if (ret < 0) | 1358 | if (ret < 0) |
| 1359 | goto esetpar; | 1359 | goto esetpar; |
| 1360 | 1360 | ||
| 1361 | mx3fb_blank(FB_BLANK_UNBLANK, fbi); | 1361 | mx3fb_blank(FB_BLANK_UNBLANK, fbi); |
| 1362 | 1362 | ||
| 1363 | dev_info(dev, "mx3fb: fb registered, using mode %s\n", fb_mode); | 1363 | dev_info(dev, "mx3fb: fb registered, using mode %s\n", fb_mode); |
| 1364 | 1364 | ||
| 1365 | ret = register_framebuffer(fbi); | 1365 | ret = register_framebuffer(fbi); |
| 1366 | if (ret < 0) | 1366 | if (ret < 0) |
| 1367 | goto erfb; | 1367 | goto erfb; |
| 1368 | 1368 | ||
| 1369 | return 0; | 1369 | return 0; |
| 1370 | 1370 | ||
| 1371 | erfb: | 1371 | erfb: |
| 1372 | esetpar: | 1372 | esetpar: |
| 1373 | emode: | 1373 | emode: |
| 1374 | fb_dealloc_cmap(&fbi->cmap); | 1374 | fb_dealloc_cmap(&fbi->cmap); |
| 1375 | framebuffer_release(fbi); | 1375 | framebuffer_release(fbi); |
| 1376 | 1376 | ||
| 1377 | return ret; | 1377 | return ret; |
| 1378 | } | 1378 | } |
| 1379 | 1379 | ||
| 1380 | static bool chan_filter(struct dma_chan *chan, void *arg) | 1380 | static bool chan_filter(struct dma_chan *chan, void *arg) |
| 1381 | { | 1381 | { |
| 1382 | struct dma_chan_request *rq = arg; | 1382 | struct dma_chan_request *rq = arg; |
| 1383 | struct device *dev; | 1383 | struct device *dev; |
| 1384 | struct mx3fb_platform_data *mx3fb_pdata; | 1384 | struct mx3fb_platform_data *mx3fb_pdata; |
| 1385 | 1385 | ||
| 1386 | if (!rq) | 1386 | if (!rq) |
| 1387 | return false; | 1387 | return false; |
| 1388 | 1388 | ||
| 1389 | dev = rq->mx3fb->dev; | 1389 | dev = rq->mx3fb->dev; |
| 1390 | mx3fb_pdata = dev->platform_data; | 1390 | mx3fb_pdata = dev->platform_data; |
| 1391 | 1391 | ||
| 1392 | return rq->id == chan->chan_id && | 1392 | return rq->id == chan->chan_id && |
| 1393 | mx3fb_pdata->dma_dev == chan->device->dev; | 1393 | mx3fb_pdata->dma_dev == chan->device->dev; |
| 1394 | } | 1394 | } |
| 1395 | 1395 | ||
| 1396 | static void release_fbi(struct fb_info *fbi) | 1396 | static void release_fbi(struct fb_info *fbi) |
| 1397 | { | 1397 | { |
| 1398 | mx3fb_unmap_video_memory(fbi); | 1398 | mx3fb_unmap_video_memory(fbi); |
| 1399 | 1399 | ||
| 1400 | fb_dealloc_cmap(&fbi->cmap); | 1400 | fb_dealloc_cmap(&fbi->cmap); |
| 1401 | 1401 | ||
| 1402 | unregister_framebuffer(fbi); | 1402 | unregister_framebuffer(fbi); |
| 1403 | framebuffer_release(fbi); | 1403 | framebuffer_release(fbi); |
| 1404 | } | 1404 | } |
| 1405 | 1405 | ||
| 1406 | static int mx3fb_probe(struct platform_device *pdev) | 1406 | static int mx3fb_probe(struct platform_device *pdev) |
| 1407 | { | 1407 | { |
| 1408 | struct device *dev = &pdev->dev; | 1408 | struct device *dev = &pdev->dev; |
| 1409 | int ret; | 1409 | int ret; |
| 1410 | struct resource *sdc_reg; | 1410 | struct resource *sdc_reg; |
| 1411 | struct mx3fb_data *mx3fb; | 1411 | struct mx3fb_data *mx3fb; |
| 1412 | dma_cap_mask_t mask; | 1412 | dma_cap_mask_t mask; |
| 1413 | struct dma_chan *chan; | 1413 | struct dma_chan *chan; |
| 1414 | struct dma_chan_request rq; | 1414 | struct dma_chan_request rq; |
| 1415 | 1415 | ||
| 1416 | /* | 1416 | /* |
| 1417 | * Display Interface (DI) and Synchronous Display Controller (SDC) | 1417 | * Display Interface (DI) and Synchronous Display Controller (SDC) |
| 1418 | * registers | 1418 | * registers |
| 1419 | */ | 1419 | */ |
| 1420 | sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1420 | sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1421 | if (!sdc_reg) | 1421 | if (!sdc_reg) |
| 1422 | return -EINVAL; | 1422 | return -EINVAL; |
| 1423 | 1423 | ||
| 1424 | mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL); | 1424 | mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL); |
| 1425 | if (!mx3fb) | 1425 | if (!mx3fb) |
| 1426 | return -ENOMEM; | 1426 | return -ENOMEM; |
| 1427 | 1427 | ||
| 1428 | spin_lock_init(&mx3fb->lock); | 1428 | spin_lock_init(&mx3fb->lock); |
| 1429 | 1429 | ||
| 1430 | mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg)); | 1430 | mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg)); |
| 1431 | if (!mx3fb->reg_base) { | 1431 | if (!mx3fb->reg_base) { |
| 1432 | ret = -ENOMEM; | 1432 | ret = -ENOMEM; |
| 1433 | goto eremap; | 1433 | goto eremap; |
| 1434 | } | 1434 | } |
| 1435 | 1435 | ||
| 1436 | pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end, | 1436 | pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end, |
| 1437 | mx3fb->reg_base); | 1437 | mx3fb->reg_base); |
| 1438 | 1438 | ||
| 1439 | /* IDMAC interface */ | 1439 | /* IDMAC interface */ |
| 1440 | dmaengine_get(); | 1440 | dmaengine_get(); |
| 1441 | 1441 | ||
| 1442 | mx3fb->dev = dev; | 1442 | mx3fb->dev = dev; |
| 1443 | platform_set_drvdata(pdev, mx3fb); | 1443 | platform_set_drvdata(pdev, mx3fb); |
| 1444 | 1444 | ||
| 1445 | rq.mx3fb = mx3fb; | 1445 | rq.mx3fb = mx3fb; |
| 1446 | 1446 | ||
| 1447 | dma_cap_zero(mask); | 1447 | dma_cap_zero(mask); |
| 1448 | dma_cap_set(DMA_SLAVE, mask); | 1448 | dma_cap_set(DMA_SLAVE, mask); |
| 1449 | dma_cap_set(DMA_PRIVATE, mask); | 1449 | dma_cap_set(DMA_PRIVATE, mask); |
| 1450 | rq.id = IDMAC_SDC_0; | 1450 | rq.id = IDMAC_SDC_0; |
| 1451 | chan = dma_request_channel(mask, chan_filter, &rq); | 1451 | chan = dma_request_channel(mask, chan_filter, &rq); |
| 1452 | if (!chan) { | 1452 | if (!chan) { |
| 1453 | ret = -EBUSY; | 1453 | ret = -EBUSY; |
| 1454 | goto ersdc0; | 1454 | goto ersdc0; |
| 1455 | } | 1455 | } |
| 1456 | 1456 | ||
| 1457 | ret = init_fb_chan(mx3fb, to_idmac_chan(chan)); | 1457 | ret = init_fb_chan(mx3fb, to_idmac_chan(chan)); |
| 1458 | if (ret < 0) | 1458 | if (ret < 0) |
| 1459 | goto eisdc0; | 1459 | goto eisdc0; |
| 1460 | 1460 | ||
| 1461 | mx3fb->backlight_level = 255; | 1461 | mx3fb->backlight_level = 255; |
| 1462 | 1462 | ||
| 1463 | return 0; | 1463 | return 0; |
| 1464 | 1464 | ||
| 1465 | eisdc0: | 1465 | eisdc0: |
| 1466 | dma_release_channel(chan); | 1466 | dma_release_channel(chan); |
| 1467 | ersdc0: | 1467 | ersdc0: |
| 1468 | dmaengine_put(); | 1468 | dmaengine_put(); |
| 1469 | iounmap(mx3fb->reg_base); | 1469 | iounmap(mx3fb->reg_base); |
| 1470 | eremap: | 1470 | eremap: |
| 1471 | kfree(mx3fb); | 1471 | kfree(mx3fb); |
| 1472 | dev_err(dev, "mx3fb: failed to register fb\n"); | 1472 | dev_err(dev, "mx3fb: failed to register fb\n"); |
| 1473 | return ret; | 1473 | return ret; |
| 1474 | } | 1474 | } |
| 1475 | 1475 | ||
| 1476 | static int mx3fb_remove(struct platform_device *dev) | 1476 | static int mx3fb_remove(struct platform_device *dev) |
| 1477 | { | 1477 | { |
| 1478 | struct mx3fb_data *mx3fb = platform_get_drvdata(dev); | 1478 | struct mx3fb_data *mx3fb = platform_get_drvdata(dev); |
| 1479 | struct fb_info *fbi = mx3fb->fbi; | 1479 | struct fb_info *fbi = mx3fb->fbi; |
| 1480 | struct mx3fb_info *mx3_fbi = fbi->par; | 1480 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 1481 | struct dma_chan *chan; | 1481 | struct dma_chan *chan; |
| 1482 | 1482 | ||
| 1483 | chan = &mx3_fbi->idmac_channel->dma_chan; | 1483 | chan = &mx3_fbi->idmac_channel->dma_chan; |
| 1484 | release_fbi(fbi); | 1484 | release_fbi(fbi); |
| 1485 | 1485 | ||
| 1486 | dma_release_channel(chan); | 1486 | dma_release_channel(chan); |
| 1487 | dmaengine_put(); | 1487 | dmaengine_put(); |
| 1488 | 1488 | ||
| 1489 | iounmap(mx3fb->reg_base); | 1489 | iounmap(mx3fb->reg_base); |
| 1490 | kfree(mx3fb); | 1490 | kfree(mx3fb); |
| 1491 | return 0; | 1491 | return 0; |
| 1492 | } | 1492 | } |
| 1493 | 1493 | ||
| 1494 | static struct platform_driver mx3fb_driver = { | 1494 | static struct platform_driver mx3fb_driver = { |
| 1495 | .driver = { | 1495 | .driver = { |
| 1496 | .name = MX3FB_NAME, | 1496 | .name = MX3FB_NAME, |
| 1497 | }, | 1497 | }, |
| 1498 | .probe = mx3fb_probe, | 1498 | .probe = mx3fb_probe, |
| 1499 | .remove = mx3fb_remove, | 1499 | .remove = mx3fb_remove, |
| 1500 | .suspend = mx3fb_suspend, | 1500 | .suspend = mx3fb_suspend, |
| 1501 | .resume = mx3fb_resume, | 1501 | .resume = mx3fb_resume, |
| 1502 | }; | 1502 | }; |
| 1503 | 1503 | ||
| 1504 | /* | 1504 | /* |
| 1505 | * Parse user specified options (`video=mx3fb:') | 1505 | * Parse user specified options (`video=mx3fb:') |
| 1506 | * example: | 1506 | * example: |
| 1507 | * video=mx3fb:bpp=16 | 1507 | * video=mx3fb:bpp=16 |
| 1508 | */ | 1508 | */ |
| 1509 | static int mx3fb_setup(void) | 1509 | static int mx3fb_setup(void) |
| 1510 | { | 1510 | { |
| 1511 | #ifndef MODULE | 1511 | #ifndef MODULE |
| 1512 | char *opt, *options = NULL; | 1512 | char *opt, *options = NULL; |
| 1513 | 1513 | ||
| 1514 | if (fb_get_options("mx3fb", &options)) | 1514 | if (fb_get_options("mx3fb", &options)) |
| 1515 | return -ENODEV; | 1515 | return -ENODEV; |
| 1516 | 1516 | ||
| 1517 | if (!options || !*options) | 1517 | if (!options || !*options) |
| 1518 | return 0; | 1518 | return 0; |
| 1519 | 1519 | ||
| 1520 | while ((opt = strsep(&options, ",")) != NULL) { | 1520 | while ((opt = strsep(&options, ",")) != NULL) { |
| 1521 | if (!*opt) | 1521 | if (!*opt) |
| 1522 | continue; | 1522 | continue; |
| 1523 | if (!strncmp(opt, "bpp=", 4)) | 1523 | if (!strncmp(opt, "bpp=", 4)) |
| 1524 | default_bpp = simple_strtoul(opt + 4, NULL, 0); | 1524 | default_bpp = simple_strtoul(opt + 4, NULL, 0); |
| 1525 | else | 1525 | else |
| 1526 | fb_mode = opt; | 1526 | fb_mode = opt; |
| 1527 | } | 1527 | } |
| 1528 | #endif | 1528 | #endif |
| 1529 | 1529 | ||
| 1530 | return 0; | 1530 | return 0; |
| 1531 | } | 1531 | } |
| 1532 | 1532 | ||
| 1533 | static int __init mx3fb_init(void) | 1533 | static int __init mx3fb_init(void) |
| 1534 | { | 1534 | { |
| 1535 | int ret = mx3fb_setup(); | 1535 | int ret = mx3fb_setup(); |
| 1536 | 1536 | ||
| 1537 | if (ret < 0) | 1537 | if (ret < 0) |
| 1538 | return ret; | 1538 | return ret; |
| 1539 | 1539 | ||
| 1540 | ret = platform_driver_register(&mx3fb_driver); | 1540 | ret = platform_driver_register(&mx3fb_driver); |
| 1541 | return ret; | 1541 | return ret; |
| 1542 | } | 1542 | } |
| 1543 | 1543 | ||
| 1544 | static void __exit mx3fb_exit(void) | 1544 | static void __exit mx3fb_exit(void) |
| 1545 | { | 1545 | { |
| 1546 | platform_driver_unregister(&mx3fb_driver); | 1546 | platform_driver_unregister(&mx3fb_driver); |
| 1547 | } | 1547 | } |
| 1548 | 1548 | ||
| 1549 | module_init(mx3fb_init); | 1549 | module_init(mx3fb_init); |
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 2552b9f325ee..84f63205c46d 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
| @@ -59,7 +59,6 @@ | |||
| 59 | #include <asm/io.h> | 59 | #include <asm/io.h> |
| 60 | #include <asm/irq.h> | 60 | #include <asm/irq.h> |
| 61 | #include <asm/div64.h> | 61 | #include <asm/div64.h> |
| 62 | #include <mach/pxa-regs.h> | ||
| 63 | #include <mach/bitfield.h> | 62 | #include <mach/bitfield.h> |
| 64 | #include <mach/pxafb.h> | 63 | #include <mach/pxafb.h> |
| 65 | 64 | ||
| @@ -883,10 +882,21 @@ static void __devinit init_pxafb_overlay(struct pxafb_info *fbi, | |||
| 883 | init_completion(&ofb->branch_done); | 882 | init_completion(&ofb->branch_done); |
| 884 | } | 883 | } |
| 885 | 884 | ||
| 885 | static inline int pxafb_overlay_supported(void) | ||
| 886 | { | ||
| 887 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) | ||
| 888 | return 1; | ||
| 889 | |||
| 890 | return 0; | ||
| 891 | } | ||
| 892 | |||
| 886 | static int __devinit pxafb_overlay_init(struct pxafb_info *fbi) | 893 | static int __devinit pxafb_overlay_init(struct pxafb_info *fbi) |
| 887 | { | 894 | { |
| 888 | int i, ret; | 895 | int i, ret; |
| 889 | 896 | ||
| 897 | if (!pxafb_overlay_supported()) | ||
| 898 | return 0; | ||
| 899 | |||
| 890 | for (i = 0; i < 2; i++) { | 900 | for (i = 0; i < 2; i++) { |
| 891 | init_pxafb_overlay(fbi, &fbi->overlay[i], i); | 901 | init_pxafb_overlay(fbi, &fbi->overlay[i], i); |
| 892 | ret = register_framebuffer(&fbi->overlay[i].fb); | 902 | ret = register_framebuffer(&fbi->overlay[i].fb); |
| @@ -909,6 +919,9 @@ static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi) | |||
| 909 | { | 919 | { |
| 910 | int i; | 920 | int i; |
| 911 | 921 | ||
| 922 | if (!pxafb_overlay_supported()) | ||
| 923 | return; | ||
| 924 | |||
| 912 | for (i = 0; i < 2; i++) | 925 | for (i = 0; i < 2; i++) |
| 913 | unregister_framebuffer(&fbi->overlay[i].fb); | 926 | unregister_framebuffer(&fbi->overlay[i].fb); |
| 914 | } | 927 | } |
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c index 79cf0b1976aa..b0b4513ba537 100644 --- a/drivers/video/s3c2410fb.c +++ b/drivers/video/s3c2410fb.c | |||
| @@ -1017,6 +1017,10 @@ static int s3c2410fb_resume(struct platform_device *dev) | |||
| 1017 | 1017 | ||
| 1018 | s3c2410fb_init_registers(fbinfo); | 1018 | s3c2410fb_init_registers(fbinfo); |
| 1019 | 1019 | ||
| 1020 | /* re-activate our display after resume */ | ||
| 1021 | s3c2410fb_activate_var(fbinfo); | ||
| 1022 | s3c2410fb_blank(FB_BLANK_UNBLANK, fbinfo); | ||
| 1023 | |||
| 1020 | return 0; | 1024 | return 0; |
| 1021 | } | 1025 | } |
| 1022 | 1026 | ||
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c index 076f946fa0f5..fad58cf9ef73 100644 --- a/drivers/video/sa1100fb.c +++ b/drivers/video/sa1100fb.c | |||
| @@ -176,9 +176,9 @@ | |||
| 176 | #include <linux/platform_device.h> | 176 | #include <linux/platform_device.h> |
| 177 | #include <linux/dma-mapping.h> | 177 | #include <linux/dma-mapping.h> |
| 178 | #include <linux/mutex.h> | 178 | #include <linux/mutex.h> |
| 179 | #include <linux/io.h> | ||
| 179 | 180 | ||
| 180 | #include <mach/hardware.h> | 181 | #include <mach/hardware.h> |
| 181 | #include <asm/io.h> | ||
| 182 | #include <asm/mach-types.h> | 182 | #include <asm/mach-types.h> |
| 183 | #include <mach/assabet.h> | 183 | #include <mach/assabet.h> |
| 184 | #include <mach/shannon.h> | 184 | #include <mach/shannon.h> |
| @@ -251,22 +251,6 @@ static struct sa1100fb_mach_info pal_info __initdata = { | |||
| 251 | #endif | 251 | #endif |
| 252 | #endif | 252 | #endif |
| 253 | 253 | ||
| 254 | #ifdef CONFIG_SA1100_H3800 | ||
| 255 | static struct sa1100fb_mach_info h3800_info __initdata = { | ||
| 256 | .pixclock = 174757, .bpp = 16, | ||
| 257 | .xres = 320, .yres = 240, | ||
| 258 | |||
| 259 | .hsync_len = 3, .vsync_len = 3, | ||
| 260 | .left_margin = 12, .upper_margin = 10, | ||
| 261 | .right_margin = 17, .lower_margin = 1, | ||
| 262 | |||
| 263 | .cmap_static = 1, | ||
| 264 | |||
| 265 | .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, | ||
| 266 | .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2), | ||
| 267 | }; | ||
| 268 | #endif | ||
| 269 | |||
| 270 | #ifdef CONFIG_SA1100_H3600 | 254 | #ifdef CONFIG_SA1100_H3600 |
| 271 | static struct sa1100fb_mach_info h3600_info __initdata = { | 255 | static struct sa1100fb_mach_info h3600_info __initdata = { |
| 272 | .pixclock = 174757, .bpp = 16, | 256 | .pixclock = 174757, .bpp = 16, |
| @@ -432,11 +416,6 @@ sa1100fb_get_machine_info(struct sa1100fb_info *fbi) | |||
| 432 | fbi->rgb[RGB_16] = &h3600_rgb_16; | 416 | fbi->rgb[RGB_16] = &h3600_rgb_16; |
| 433 | } | 417 | } |
| 434 | #endif | 418 | #endif |
| 435 | #ifdef CONFIG_SA1100_H3800 | ||
| 436 | if (machine_is_h3800()) { | ||
| 437 | inf = &h3800_info; | ||
| 438 | } | ||
| 439 | #endif | ||
| 440 | #ifdef CONFIG_SA1100_COLLIE | 419 | #ifdef CONFIG_SA1100_COLLIE |
| 441 | if (machine_is_collie()) { | 420 | if (machine_is_collie()) { |
| 442 | inf = &collie_info; | 421 | inf = &collie_info; |
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c index b9d74d0b353e..65244c02551b 100644 --- a/drivers/w1/masters/mxc_w1.c +++ b/drivers/w1/masters/mxc_w1.c | |||
| @@ -116,7 +116,7 @@ static int __init mxc_w1_probe(struct platform_device *pdev) | |||
| 116 | if (!mdev) | 116 | if (!mdev) |
| 117 | return -ENOMEM; | 117 | return -ENOMEM; |
| 118 | 118 | ||
| 119 | mdev->clk = clk_get(&pdev->dev, "owire_clk"); | 119 | mdev->clk = clk_get(&pdev->dev, "owire"); |
| 120 | if (!mdev->clk) { | 120 | if (!mdev->clk) { |
| 121 | err = -ENODEV; | 121 | err = -ENODEV; |
| 122 | goto failed_clk; | 122 | goto failed_clk; |
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index c973889110c8..a7e3b706b9d3 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c | |||
| @@ -590,8 +590,8 @@ static int __init omap_hdq_probe(struct platform_device *pdev) | |||
| 590 | } | 590 | } |
| 591 | 591 | ||
| 592 | /* get interface & functional clock objects */ | 592 | /* get interface & functional clock objects */ |
| 593 | hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick"); | 593 | hdq_data->hdq_ick = clk_get(&pdev->dev, "ick"); |
| 594 | hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck"); | 594 | hdq_data->hdq_fck = clk_get(&pdev->dev, "fck"); |
| 595 | 595 | ||
| 596 | if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) { | 596 | if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) { |
| 597 | dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n"); | 597 | dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n"); |
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 2f2ce7429f5b..aa5ad6e33f02 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c | |||
| @@ -60,9 +60,8 @@ struct omap_wdt_dev { | |||
| 60 | void __iomem *base; /* physical */ | 60 | void __iomem *base; /* physical */ |
| 61 | struct device *dev; | 61 | struct device *dev; |
| 62 | int omap_wdt_users; | 62 | int omap_wdt_users; |
| 63 | struct clk *armwdt_ck; | 63 | struct clk *ick; |
| 64 | struct clk *mpu_wdt_ick; | 64 | struct clk *fck; |
| 65 | struct clk *mpu_wdt_fck; | ||
| 66 | struct resource *mem; | 65 | struct resource *mem; |
| 67 | struct miscdevice omap_wdt_miscdev; | 66 | struct miscdevice omap_wdt_miscdev; |
| 68 | }; | 67 | }; |
| @@ -146,13 +145,8 @@ static int omap_wdt_open(struct inode *inode, struct file *file) | |||
| 146 | if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) | 145 | if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) |
| 147 | return -EBUSY; | 146 | return -EBUSY; |
| 148 | 147 | ||
| 149 | if (cpu_is_omap16xx()) | 148 | clk_enable(wdev->ick); /* Enable the interface clock */ |
| 150 | clk_enable(wdev->armwdt_ck); /* Enable the clock */ | 149 | clk_enable(wdev->fck); /* Enable the functional clock */ |
| 151 | |||
| 152 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
| 153 | clk_enable(wdev->mpu_wdt_ick); /* Enable the interface clock */ | ||
| 154 | clk_enable(wdev->mpu_wdt_fck); /* Enable the functional clock */ | ||
| 155 | } | ||
| 156 | 150 | ||
| 157 | /* initialize prescaler */ | 151 | /* initialize prescaler */ |
| 158 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | 152 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
| @@ -181,13 +175,8 @@ static int omap_wdt_release(struct inode *inode, struct file *file) | |||
| 181 | 175 | ||
| 182 | omap_wdt_disable(wdev); | 176 | omap_wdt_disable(wdev); |
| 183 | 177 | ||
| 184 | if (cpu_is_omap16xx()) | 178 | clk_disable(wdev->ick); |
| 185 | clk_disable(wdev->armwdt_ck); /* Disable the clock */ | 179 | clk_disable(wdev->fck); |
| 186 | |||
| 187 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
| 188 | clk_disable(wdev->mpu_wdt_ick); /* Disable the clock */ | ||
| 189 | clk_disable(wdev->mpu_wdt_fck); /* Disable the clock */ | ||
| 190 | } | ||
| 191 | #else | 180 | #else |
| 192 | printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); | 181 | printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); |
| 193 | #endif | 182 | #endif |
| @@ -303,44 +292,19 @@ static int __init omap_wdt_probe(struct platform_device *pdev) | |||
| 303 | wdev->omap_wdt_users = 0; | 292 | wdev->omap_wdt_users = 0; |
| 304 | wdev->mem = mem; | 293 | wdev->mem = mem; |
| 305 | 294 | ||
| 306 | if (cpu_is_omap16xx()) { | 295 | wdev->ick = clk_get(&pdev->dev, "ick"); |
| 307 | wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck"); | 296 | if (IS_ERR(wdev->ick)) { |
| 308 | if (IS_ERR(wdev->armwdt_ck)) { | 297 | ret = PTR_ERR(wdev->ick); |
| 309 | ret = PTR_ERR(wdev->armwdt_ck); | 298 | wdev->ick = NULL; |
| 310 | wdev->armwdt_ck = NULL; | 299 | goto err_clk; |
| 311 | goto err_clk; | ||
| 312 | } | ||
| 313 | } | 300 | } |
| 314 | 301 | wdev->fck = clk_get(&pdev->dev, "fck"); | |
| 315 | if (cpu_is_omap24xx()) { | 302 | if (IS_ERR(wdev->fck)) { |
| 316 | wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick"); | 303 | ret = PTR_ERR(wdev->fck); |
| 317 | if (IS_ERR(wdev->mpu_wdt_ick)) { | 304 | wdev->fck = NULL; |
| 318 | ret = PTR_ERR(wdev->mpu_wdt_ick); | 305 | goto err_clk; |
| 319 | wdev->mpu_wdt_ick = NULL; | ||
| 320 | goto err_clk; | ||
| 321 | } | ||
| 322 | wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck"); | ||
| 323 | if (IS_ERR(wdev->mpu_wdt_fck)) { | ||
| 324 | ret = PTR_ERR(wdev->mpu_wdt_fck); | ||
| 325 | wdev->mpu_wdt_fck = NULL; | ||
| 326 | goto err_clk; | ||
| 327 | } | ||
| 328 | } | 306 | } |
| 329 | 307 | ||
| 330 | if (cpu_is_omap34xx()) { | ||
| 331 | wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick"); | ||
| 332 | if (IS_ERR(wdev->mpu_wdt_ick)) { | ||
| 333 | ret = PTR_ERR(wdev->mpu_wdt_ick); | ||
| 334 | wdev->mpu_wdt_ick = NULL; | ||
| 335 | goto err_clk; | ||
| 336 | } | ||
| 337 | wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck"); | ||
| 338 | if (IS_ERR(wdev->mpu_wdt_fck)) { | ||
| 339 | ret = PTR_ERR(wdev->mpu_wdt_fck); | ||
| 340 | wdev->mpu_wdt_fck = NULL; | ||
| 341 | goto err_clk; | ||
| 342 | } | ||
| 343 | } | ||
| 344 | wdev->base = ioremap(res->start, res->end - res->start + 1); | 308 | wdev->base = ioremap(res->start, res->end - res->start + 1); |
| 345 | if (!wdev->base) { | 309 | if (!wdev->base) { |
| 346 | ret = -ENOMEM; | 310 | ret = -ENOMEM; |
| @@ -380,12 +344,10 @@ err_ioremap: | |||
| 380 | wdev->base = NULL; | 344 | wdev->base = NULL; |
| 381 | 345 | ||
| 382 | err_clk: | 346 | err_clk: |
| 383 | if (wdev->armwdt_ck) | 347 | if (wdev->ick) |
| 384 | clk_put(wdev->armwdt_ck); | 348 | clk_put(wdev->ick); |
| 385 | if (wdev->mpu_wdt_ick) | 349 | if (wdev->fck) |
| 386 | clk_put(wdev->mpu_wdt_ick); | 350 | clk_put(wdev->fck); |
| 387 | if (wdev->mpu_wdt_fck) | ||
| 388 | clk_put(wdev->mpu_wdt_fck); | ||
| 389 | kfree(wdev); | 351 | kfree(wdev); |
| 390 | 352 | ||
| 391 | err_kzalloc: | 353 | err_kzalloc: |
| @@ -417,20 +379,8 @@ static int omap_wdt_remove(struct platform_device *pdev) | |||
| 417 | release_mem_region(res->start, res->end - res->start + 1); | 379 | release_mem_region(res->start, res->end - res->start + 1); |
| 418 | platform_set_drvdata(pdev, NULL); | 380 | platform_set_drvdata(pdev, NULL); |
| 419 | 381 | ||
| 420 | if (wdev->armwdt_ck) { | 382 | clk_put(wdev->ick); |
| 421 | clk_put(wdev->armwdt_ck); | 383 | clk_put(wdev->fck); |
| 422 | wdev->armwdt_ck = NULL; | ||
| 423 | } | ||
| 424 | |||
| 425 | if (wdev->mpu_wdt_ick) { | ||
| 426 | clk_put(wdev->mpu_wdt_ick); | ||
| 427 | wdev->mpu_wdt_ick = NULL; | ||
| 428 | } | ||
| 429 | |||
| 430 | if (wdev->mpu_wdt_fck) { | ||
| 431 | clk_put(wdev->mpu_wdt_fck); | ||
| 432 | wdev->mpu_wdt_fck = NULL; | ||
| 433 | } | ||
| 434 | iounmap(wdev->base); | 384 | iounmap(wdev->base); |
| 435 | 385 | ||
| 436 | kfree(wdev); | 386 | kfree(wdev); |
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c index 5bd782f27837..ee1caae4d33b 100644 --- a/drivers/watchdog/sa1100_wdt.c +++ b/drivers/watchdog/sa1100_wdt.c | |||
| @@ -30,7 +30,7 @@ | |||
| 30 | #include <linux/timex.h> | 30 | #include <linux/timex.h> |
| 31 | 31 | ||
| 32 | #ifdef CONFIG_ARCH_PXA | 32 | #ifdef CONFIG_ARCH_PXA |
| 33 | #include <mach/pxa-regs.h> | 33 | #include <mach/regs-ost.h> |
| 34 | #endif | 34 | #endif |
| 35 | 35 | ||
| 36 | #include <mach/reset.h> | 36 | #include <mach/reset.h> |
diff --git a/include/linux/clk.h b/include/linux/clk.h index 778777316ea4..1db9bbf444a3 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h | |||
| @@ -125,4 +125,21 @@ int clk_set_parent(struct clk *clk, struct clk *parent); | |||
| 125 | */ | 125 | */ |
| 126 | struct clk *clk_get_parent(struct clk *clk); | 126 | struct clk *clk_get_parent(struct clk *clk); |
| 127 | 127 | ||
| 128 | /** | ||
| 129 | * clk_get_sys - get a clock based upon the device name | ||
| 130 | * @dev_id: device name | ||
| 131 | * @con_id: connection ID | ||
| 132 | * | ||
| 133 | * Returns a struct clk corresponding to the clock producer, or | ||
| 134 | * valid IS_ERR() condition containing errno. The implementation | ||
| 135 | * uses @dev_id and @con_id to determine the clock consumer, and | ||
| 136 | * thereby the clock producer. In contrast to clk_get() this function | ||
| 137 | * takes the device name instead of the device itself for identification. | ||
| 138 | * | ||
| 139 | * Drivers must assume that the clock source is not enabled. | ||
| 140 | * | ||
| 141 | * clk_get_sys should not be called from within interrupt context. | ||
| 142 | */ | ||
| 143 | struct clk *clk_get_sys(const char *dev_id, const char *con_id); | ||
| 144 | |||
| 128 | #endif | 145 | #endif |
diff --git a/include/video/broadsheetfb.h b/include/video/broadsheetfb.h new file mode 100644 index 000000000000..a758534c0272 --- /dev/null +++ b/include/video/broadsheetfb.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * broadsheetfb.h - definitions for the broadsheet framebuffer driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 by Jaya Kumar | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _LINUX_BROADSHEETFB_H_ | ||
| 13 | #define _LINUX_BROADSHEETFB_H_ | ||
| 14 | |||
| 15 | /* Broadsheet command defines */ | ||
| 16 | #define BS_CMD_INIT_SYS_RUN 0x06 | ||
| 17 | #define BS_CMD_INIT_DSPE_CFG 0x09 | ||
| 18 | #define BS_CMD_INIT_DSPE_TMG 0x0A | ||
| 19 | #define BS_CMD_INIT_ROTMODE 0x0B | ||
| 20 | #define BS_CMD_RD_REG 0x10 | ||
| 21 | #define BS_CMD_WR_REG 0x11 | ||
| 22 | #define BS_CMD_LD_IMG 0x20 | ||
| 23 | #define BS_CMD_LD_IMG_AREA 0x22 | ||
| 24 | #define BS_CMD_LD_IMG_END 0x23 | ||
| 25 | #define BS_CMD_WAIT_DSPE_TRG 0x28 | ||
| 26 | #define BS_CMD_WAIT_DSPE_FREND 0x29 | ||
| 27 | #define BS_CMD_RD_WFM_INFO 0x30 | ||
| 28 | #define BS_CMD_UPD_INIT 0x32 | ||
| 29 | #define BS_CMD_UPD_FULL 0x33 | ||
| 30 | #define BS_CMD_UPD_GDRV_CLR 0x37 | ||
| 31 | |||
| 32 | /* Broadsheet pin interface specific defines */ | ||
| 33 | #define BS_CS 0x01 | ||
| 34 | #define BS_DC 0x02 | ||
| 35 | #define BS_WR 0x03 | ||
| 36 | |||
| 37 | /* struct used by broadsheet. board specific stuff comes from *board */ | ||
| 38 | struct broadsheetfb_par { | ||
| 39 | struct fb_info *info; | ||
| 40 | struct broadsheet_board *board; | ||
| 41 | void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); | ||
| 42 | u16 (*read_reg)(struct broadsheetfb_par *, u16 reg); | ||
| 43 | wait_queue_head_t waitq; | ||
| 44 | }; | ||
| 45 | |||
| 46 | /* board specific routines */ | ||
| 47 | struct broadsheet_board { | ||
| 48 | struct module *owner; | ||
| 49 | int (*init)(struct broadsheetfb_par *); | ||
| 50 | int (*wait_for_rdy)(struct broadsheetfb_par *); | ||
| 51 | void (*set_ctl)(struct broadsheetfb_par *, unsigned char, u8); | ||
| 52 | void (*set_hdb)(struct broadsheetfb_par *, u16); | ||
| 53 | u16 (*get_hdb)(struct broadsheetfb_par *); | ||
| 54 | void (*cleanup)(struct broadsheetfb_par *); | ||
| 55 | int (*get_panel_type)(void); | ||
| 56 | int (*setup_irq)(struct fb_info *); | ||
| 57 | }; | ||
| 58 | |||
| 59 | #endif | ||
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 8fee0a13ac58..0626fa4856e6 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug | |||
| @@ -402,7 +402,7 @@ config LOCKDEP | |||
| 402 | bool | 402 | bool |
| 403 | depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT | 403 | depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT |
| 404 | select STACKTRACE | 404 | select STACKTRACE |
| 405 | select FRAME_POINTER if !X86 && !MIPS && !PPC | 405 | select FRAME_POINTER if !X86 && !MIPS && !PPC && !ARM_UNWIND |
| 406 | select KALLSYMS | 406 | select KALLSYMS |
| 407 | select KALLSYMS_ALL | 407 | select KALLSYMS_ALL |
| 408 | 408 | ||
diff --git a/mm/highmem.c b/mm/highmem.c index b36b83b920ff..910198037bf5 100644 --- a/mm/highmem.c +++ b/mm/highmem.c | |||
| @@ -67,6 +67,25 @@ pte_t * pkmap_page_table; | |||
| 67 | 67 | ||
| 68 | static DECLARE_WAIT_QUEUE_HEAD(pkmap_map_wait); | 68 | static DECLARE_WAIT_QUEUE_HEAD(pkmap_map_wait); |
| 69 | 69 | ||
| 70 | /* | ||
| 71 | * Most architectures have no use for kmap_high_get(), so let's abstract | ||
| 72 | * the disabling of IRQ out of the locking in that case to save on a | ||
| 73 | * potential useless overhead. | ||
| 74 | */ | ||
| 75 | #ifdef ARCH_NEEDS_KMAP_HIGH_GET | ||
| 76 | #define lock_kmap() spin_lock_irq(&kmap_lock) | ||
| 77 | #define unlock_kmap() spin_unlock_irq(&kmap_lock) | ||
| 78 | #define lock_kmap_any(flags) spin_lock_irqsave(&kmap_lock, flags) | ||
| 79 | #define unlock_kmap_any(flags) spin_unlock_irqrestore(&kmap_lock, flags) | ||
| 80 | #else | ||
| 81 | #define lock_kmap() spin_lock(&kmap_lock) | ||
| 82 | #define unlock_kmap() spin_unlock(&kmap_lock) | ||
| 83 | #define lock_kmap_any(flags) \ | ||
| 84 | do { spin_lock(&kmap_lock); (void)(flags); } while (0) | ||
| 85 | #define unlock_kmap_any(flags) \ | ||
| 86 | do { spin_unlock(&kmap_lock); (void)(flags); } while (0) | ||
| 87 | #endif | ||
| 88 | |||
| 70 | static void flush_all_zero_pkmaps(void) | 89 | static void flush_all_zero_pkmaps(void) |
| 71 | { | 90 | { |
| 72 | int i; | 91 | int i; |
| @@ -113,9 +132,9 @@ static void flush_all_zero_pkmaps(void) | |||
| 113 | */ | 132 | */ |
| 114 | void kmap_flush_unused(void) | 133 | void kmap_flush_unused(void) |
| 115 | { | 134 | { |
| 116 | spin_lock(&kmap_lock); | 135 | lock_kmap(); |
| 117 | flush_all_zero_pkmaps(); | 136 | flush_all_zero_pkmaps(); |
| 118 | spin_unlock(&kmap_lock); | 137 | unlock_kmap(); |
| 119 | } | 138 | } |
| 120 | 139 | ||
| 121 | static inline unsigned long map_new_virtual(struct page *page) | 140 | static inline unsigned long map_new_virtual(struct page *page) |
| @@ -145,10 +164,10 @@ start: | |||
| 145 | 164 | ||
| 146 | __set_current_state(TASK_UNINTERRUPTIBLE); | 165 | __set_current_state(TASK_UNINTERRUPTIBLE); |
| 147 | add_wait_queue(&pkmap_map_wait, &wait); | 166 | add_wait_queue(&pkmap_map_wait, &wait); |
| 148 | spin_unlock(&kmap_lock); | 167 | unlock_kmap(); |
| 149 | schedule(); | 168 | schedule(); |
| 150 | remove_wait_queue(&pkmap_map_wait, &wait); | 169 | remove_wait_queue(&pkmap_map_wait, &wait); |
| 151 | spin_lock(&kmap_lock); | 170 | lock_kmap(); |
| 152 | 171 | ||
| 153 | /* Somebody else might have mapped it while we slept */ | 172 | /* Somebody else might have mapped it while we slept */ |
| 154 | if (page_address(page)) | 173 | if (page_address(page)) |
| @@ -184,29 +203,59 @@ void *kmap_high(struct page *page) | |||
| 184 | * For highmem pages, we can't trust "virtual" until | 203 | * For highmem pages, we can't trust "virtual" until |
| 185 | * after we have the lock. | 204 | * after we have the lock. |
| 186 | */ | 205 | */ |
| 187 | spin_lock(&kmap_lock); | 206 | lock_kmap(); |
| 188 | vaddr = (unsigned long)page_address(page); | 207 | vaddr = (unsigned long)page_address(page); |
| 189 | if (!vaddr) | 208 | if (!vaddr) |
| 190 | vaddr = map_new_virtual(page); | 209 | vaddr = map_new_virtual(page); |
| 191 | pkmap_count[PKMAP_NR(vaddr)]++; | 210 | pkmap_count[PKMAP_NR(vaddr)]++; |
| 192 | BUG_ON(pkmap_count[PKMAP_NR(vaddr)] < 2); | 211 | BUG_ON(pkmap_count[PKMAP_NR(vaddr)] < 2); |
| 193 | spin_unlock(&kmap_lock); | 212 | unlock_kmap(); |
| 194 | return (void*) vaddr; | 213 | return (void*) vaddr; |
| 195 | } | 214 | } |
| 196 | 215 | ||
| 197 | EXPORT_SYMBOL(kmap_high); | 216 | EXPORT_SYMBOL(kmap_high); |
| 198 | 217 | ||
| 218 | #ifdef ARCH_NEEDS_KMAP_HIGH_GET | ||
| 219 | /** | ||
| 220 | * kmap_high_get - pin a highmem page into memory | ||
| 221 | * @page: &struct page to pin | ||
| 222 | * | ||
| 223 | * Returns the page's current virtual memory address, or NULL if no mapping | ||
| 224 | * exists. When and only when a non null address is returned then a | ||
| 225 | * matching call to kunmap_high() is necessary. | ||
| 226 | * | ||
| 227 | * This can be called from any context. | ||
| 228 | */ | ||
| 229 | void *kmap_high_get(struct page *page) | ||
| 230 | { | ||
| 231 | unsigned long vaddr, flags; | ||
| 232 | |||
| 233 | lock_kmap_any(flags); | ||
| 234 | vaddr = (unsigned long)page_address(page); | ||
| 235 | if (vaddr) { | ||
| 236 | BUG_ON(pkmap_count[PKMAP_NR(vaddr)] < 1); | ||
| 237 | pkmap_count[PKMAP_NR(vaddr)]++; | ||
| 238 | } | ||
| 239 | unlock_kmap_any(flags); | ||
| 240 | return (void*) vaddr; | ||
| 241 | } | ||
| 242 | #endif | ||
| 243 | |||
| 199 | /** | 244 | /** |
| 200 | * kunmap_high - map a highmem page into memory | 245 | * kunmap_high - map a highmem page into memory |
| 201 | * @page: &struct page to unmap | 246 | * @page: &struct page to unmap |
| 247 | * | ||
| 248 | * If ARCH_NEEDS_KMAP_HIGH_GET is not defined then this may be called | ||
| 249 | * only from user context. | ||
| 202 | */ | 250 | */ |
| 203 | void kunmap_high(struct page *page) | 251 | void kunmap_high(struct page *page) |
| 204 | { | 252 | { |
| 205 | unsigned long vaddr; | 253 | unsigned long vaddr; |
| 206 | unsigned long nr; | 254 | unsigned long nr; |
| 255 | unsigned long flags; | ||
| 207 | int need_wakeup; | 256 | int need_wakeup; |
| 208 | 257 | ||
| 209 | spin_lock(&kmap_lock); | 258 | lock_kmap_any(flags); |
| 210 | vaddr = (unsigned long)page_address(page); | 259 | vaddr = (unsigned long)page_address(page); |
| 211 | BUG_ON(!vaddr); | 260 | BUG_ON(!vaddr); |
| 212 | nr = PKMAP_NR(vaddr); | 261 | nr = PKMAP_NR(vaddr); |
| @@ -232,7 +281,7 @@ void kunmap_high(struct page *page) | |||
| 232 | */ | 281 | */ |
| 233 | need_wakeup = waitqueue_active(&pkmap_map_wait); | 282 | need_wakeup = waitqueue_active(&pkmap_map_wait); |
| 234 | } | 283 | } |
| 235 | spin_unlock(&kmap_lock); | 284 | unlock_kmap_any(flags); |
| 236 | 285 | ||
| 237 | /* do wake-up, if needed, race-free outside of the spin lock */ | 286 | /* do wake-up, if needed, race-free outside of the spin lock */ |
| 238 | if (need_wakeup) | 287 | if (need_wakeup) |
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c index 2e6355f4cbb9..7793d2a511ce 100644 --- a/sound/arm/pxa2xx-ac97-lib.c +++ b/sound/arm/pxa2xx-ac97-lib.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | #include <sound/pxa2xx-lib.h> | 21 | #include <sound/pxa2xx-lib.h> |
| 22 | 22 | ||
| 23 | #include <asm/irq.h> | 23 | #include <asm/irq.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/regs-ac97.h> | 24 | #include <mach/regs-ac97.h> |
| 26 | #include <mach/pxa2xx-gpio.h> | 25 | #include <mach/pxa2xx-gpio.h> |
| 27 | #include <mach/audio.h> | 26 | #include <mach/audio.h> |
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c index 7ed100c80a5f..c570ebd9d177 100644 --- a/sound/arm/pxa2xx-ac97.c +++ b/sound/arm/pxa2xx-ac97.c | |||
| @@ -20,8 +20,6 @@ | |||
| 20 | #include <sound/initval.h> | 20 | #include <sound/initval.h> |
| 21 | #include <sound/pxa2xx-lib.h> | 21 | #include <sound/pxa2xx-lib.h> |
| 22 | 22 | ||
| 23 | #include <mach/hardware.h> | ||
| 24 | #include <mach/pxa-regs.h> | ||
| 25 | #include <mach/regs-ac97.h> | 23 | #include <mach/regs-ac97.h> |
| 26 | #include <mach/audio.h> | 24 | #include <mach/audio.h> |
| 27 | 25 | ||
diff --git a/sound/arm/pxa2xx-pcm-lib.c b/sound/arm/pxa2xx-pcm-lib.c index 75a0d746fb60..108b643229ba 100644 --- a/sound/arm/pxa2xx-pcm-lib.c +++ b/sound/arm/pxa2xx-pcm-lib.c | |||
| @@ -12,8 +12,7 @@ | |||
| 12 | #include <sound/pcm_params.h> | 12 | #include <sound/pcm_params.h> |
| 13 | #include <sound/pxa2xx-lib.h> | 13 | #include <sound/pxa2xx-lib.h> |
| 14 | 14 | ||
| 15 | #include <asm/dma.h> | 15 | #include <mach/dma.h> |
| 16 | #include <mach/pxa-regs.h> | ||
| 17 | 16 | ||
| 18 | #include "pxa2xx-pcm.h" | 17 | #include "pxa2xx-pcm.h" |
| 19 | 18 | ||
diff --git a/sound/soc/pxa/corgi.c b/sound/soc/pxa/corgi.c index 02263e5d8f03..d5be2b30cda5 100644 --- a/sound/soc/pxa/corgi.c +++ b/sound/soc/pxa/corgi.c | |||
| @@ -26,8 +26,6 @@ | |||
| 26 | #include <sound/soc-dapm.h> | 26 | #include <sound/soc-dapm.h> |
| 27 | 27 | ||
| 28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/corgi.h> | 29 | #include <mach/corgi.h> |
| 32 | #include <mach/audio.h> | 30 | #include <mach/audio.h> |
| 33 | 31 | ||
diff --git a/sound/soc/pxa/em-x270.c b/sound/soc/pxa/em-x270.c index fe4a729ea648..949be9c2a01b 100644 --- a/sound/soc/pxa/em-x270.c +++ b/sound/soc/pxa/em-x270.c | |||
| @@ -29,8 +29,6 @@ | |||
| 29 | #include <sound/soc-dapm.h> | 29 | #include <sound/soc-dapm.h> |
| 30 | 30 | ||
| 31 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 32 | #include <mach/pxa-regs.h> | ||
| 33 | #include <mach/hardware.h> | ||
| 34 | #include <mach/audio.h> | 32 | #include <mach/audio.h> |
| 35 | 33 | ||
| 36 | #include "../codecs/wm9712.h" | 34 | #include "../codecs/wm9712.h" |
diff --git a/sound/soc/pxa/poodle.c b/sound/soc/pxa/poodle.c index ef7c6c8dc8f1..a51058f66747 100644 --- a/sound/soc/pxa/poodle.c +++ b/sound/soc/pxa/poodle.c | |||
| @@ -27,8 +27,6 @@ | |||
| 27 | 27 | ||
| 28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 29 | #include <asm/hardware/locomo.h> | 29 | #include <asm/hardware/locomo.h> |
| 30 | #include <mach/pxa-regs.h> | ||
| 31 | #include <mach/hardware.h> | ||
| 32 | #include <mach/poodle.h> | 30 | #include <mach/poodle.h> |
| 33 | #include <mach/audio.h> | 31 | #include <mach/audio.h> |
| 34 | 32 | ||
diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c index b0bf40973d5b..7acd3febf8b0 100644 --- a/sound/soc/pxa/pxa-ssp.c +++ b/sound/soc/pxa/pxa-ssp.c | |||
| @@ -30,7 +30,7 @@ | |||
| 30 | #include <sound/pxa2xx-lib.h> | 30 | #include <sound/pxa2xx-lib.h> |
| 31 | 31 | ||
| 32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 33 | #include <mach/pxa-regs.h> | 33 | #include <mach/dma.h> |
| 34 | #include <mach/regs-ssp.h> | 34 | #include <mach/regs-ssp.h> |
| 35 | #include <mach/audio.h> | 35 | #include <mach/audio.h> |
| 36 | #include <mach/ssp.h> | 36 | #include <mach/ssp.h> |
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c index 01c21c6cdbbc..d9c94d71fa61 100644 --- a/sound/soc/pxa/pxa2xx-ac97.c +++ b/sound/soc/pxa/pxa2xx-ac97.c | |||
| @@ -20,8 +20,8 @@ | |||
| 20 | #include <sound/pxa2xx-lib.h> | 20 | #include <sound/pxa2xx-lib.h> |
| 21 | 21 | ||
| 22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/regs-ac97.h> | 23 | #include <mach/regs-ac97.h> |
| 24 | #include <mach/dma.h> | ||
| 25 | 25 | ||
| 26 | #include "pxa2xx-pcm.h" | 26 | #include "pxa2xx-pcm.h" |
| 27 | #include "pxa2xx-ac97.h" | 27 | #include "pxa2xx-ac97.h" |
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c index e6c24408c5f9..2f4b6e489b78 100644 --- a/sound/soc/pxa/pxa2xx-i2s.c +++ b/sound/soc/pxa/pxa2xx-i2s.c | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | #include <sound/pxa2xx-lib.h> | 24 | #include <sound/pxa2xx-lib.h> |
| 25 | 25 | ||
| 26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 27 | #include <mach/pxa-regs.h> | 27 | #include <mach/dma.h> |
| 28 | #include <mach/audio.h> | 28 | #include <mach/audio.h> |
| 29 | 29 | ||
| 30 | #include "pxa2xx-pcm.h" | 30 | #include "pxa2xx-pcm.h" |
diff --git a/sound/soc/pxa/spitz.c b/sound/soc/pxa/spitz.c index 6ca9f53080c6..c4cd2acaacb4 100644 --- a/sound/soc/pxa/spitz.c +++ b/sound/soc/pxa/spitz.c | |||
| @@ -26,8 +26,6 @@ | |||
| 26 | #include <sound/soc-dapm.h> | 26 | #include <sound/soc-dapm.h> |
| 27 | 27 | ||
| 28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/spitz.h> | 29 | #include <mach/spitz.h> |
| 32 | #include "../codecs/wm8750.h" | 30 | #include "../codecs/wm8750.h" |
| 33 | #include "pxa2xx-pcm.h" | 31 | #include "pxa2xx-pcm.h" |
diff --git a/sound/soc/pxa/tosa.c b/sound/soc/pxa/tosa.c index fc781374b1bf..dbbd3e9d1637 100644 --- a/sound/soc/pxa/tosa.c +++ b/sound/soc/pxa/tosa.c | |||
| @@ -30,8 +30,6 @@ | |||
| 30 | 30 | ||
| 31 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 32 | #include <mach/tosa.h> | 32 | #include <mach/tosa.h> |
| 33 | #include <mach/pxa-regs.h> | ||
| 34 | #include <mach/hardware.h> | ||
| 35 | #include <mach/audio.h> | 33 | #include <mach/audio.h> |
| 36 | 34 | ||
| 37 | #include "../codecs/wm9712.h" | 35 | #include "../codecs/wm9712.h" |