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-rw-r--r--arch/arm/mach-mx3/clock.c959
1 files changed, 208 insertions, 751 deletions
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index b1746aae1f89..ca46f4801c3d 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -23,9 +23,13 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/io.h> 25#include <linux/io.h>
26
27#include <asm/clkdev.h>
28#include <asm/div64.h>
29
26#include <mach/clock.h> 30#include <mach/clock.h>
27#include <mach/hardware.h> 31#include <mach/hardware.h>
28#include <asm/div64.h> 32#include <mach/common.h>
29 33
30#include "crm_regs.h" 34#include "crm_regs.h"
31 35
@@ -64,17 +68,17 @@ static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
64} 68}
65 69
66static struct clk mcu_pll_clk; 70static struct clk mcu_pll_clk;
67static struct clk mcu_main_clk;
68static struct clk usb_pll_clk;
69static struct clk serial_pll_clk; 71static struct clk serial_pll_clk;
70static struct clk ipg_clk; 72static struct clk ipg_clk;
71static struct clk ckih_clk; 73static struct clk ckih_clk;
72static struct clk ahb_clk;
73 74
74static int _clk_enable(struct clk *clk) 75static int cgr_enable(struct clk *clk)
75{ 76{
76 u32 reg; 77 u32 reg;
77 78
79 if (!clk->enable_reg)
80 return 0;
81
78 reg = __raw_readl(clk->enable_reg); 82 reg = __raw_readl(clk->enable_reg);
79 reg |= 3 << clk->enable_shift; 83 reg |= 3 << clk->enable_shift;
80 __raw_writel(reg, clk->enable_reg); 84 __raw_writel(reg, clk->enable_reg);
@@ -82,133 +86,69 @@ static int _clk_enable(struct clk *clk)
82 return 0; 86 return 0;
83} 87}
84 88
85static void _clk_disable(struct clk *clk) 89static void cgr_disable(struct clk *clk)
86{ 90{
87 u32 reg; 91 u32 reg;
88 92
93 if (!clk->enable_reg)
94 return;
95
89 reg = __raw_readl(clk->enable_reg); 96 reg = __raw_readl(clk->enable_reg);
90 reg &= ~(3 << clk->enable_shift); 97 reg &= ~(3 << clk->enable_shift);
98
99 /* special case for EMI clock */
100 if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
101 reg |= (1 << clk->enable_shift);
102
91 __raw_writel(reg, clk->enable_reg); 103 __raw_writel(reg, clk->enable_reg);
92} 104}
93 105
94static void _clk_emi_disable(struct clk *clk) 106static unsigned long pll_ref_get_rate(void)
95{ 107{
96 u32 reg; 108 unsigned long ccmr;
109 unsigned int prcs;
97 110
98 reg = __raw_readl(clk->enable_reg); 111 ccmr = __raw_readl(MXC_CCM_CCMR);
99 reg &= ~(3 << clk->enable_shift); 112 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
100 reg |= (1 << clk->enable_shift); 113 if (prcs == 0x1)
101 __raw_writel(reg, clk->enable_reg); 114 return CKIL_CLK_FREQ * 1024;
115 else
116 return clk_get_rate(&ckih_clk);
102} 117}
103 118
104static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) 119static unsigned long usb_pll_get_rate(struct clk *clk)
105{ 120{
106 u32 reg; 121 unsigned long reg;
107 signed long pd = 1; /* Pre-divider */
108 signed long mfi; /* Multiplication Factor (Integer part) */
109 signed long mfn; /* Multiplication Factor (Integer part) */
110 signed long mfd; /* Multiplication Factor (Denominator Part) */
111 signed long tmp;
112 u32 ref_freq = clk_get_rate(clk->parent);
113 122
114 while (((ref_freq / pd) * 10) > rate) 123 reg = __raw_readl(MXC_CCM_UPCTL);
115 pd++;
116 124
117 if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) 125 return mxc_decode_pll(reg, pll_ref_get_rate());
118 return -EINVAL; 126}
119 127
120 /* the ref_freq/2 in the following is to round up */ 128static unsigned long serial_pll_get_rate(struct clk *clk)
121 mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; 129{
122 if (mfi < 5 || mfi > 15) 130 unsigned long reg;
123 return -EINVAL;
124 131
125 /* pick a mfd value that will work 132 reg = __raw_readl(MXC_CCM_SRPCTL);
126 * then solve for mfn */
127 mfd = ref_freq / 50000;
128
129 /*
130 * pll_freq * pd * mfd
131 * mfn = -------------------- - (mfi * mfd)
132 * 2 * ref_freq
133 */
134 /* the tmp/2 is for rounding */
135 tmp = ref_freq / 10000;
136 mfn =
137 ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
138 (mfi * mfd);
139
140 mfn = mfn & 0x3ff;
141 pd--;
142 mfd--;
143
144 /* Change the Pll value */
145 reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
146 (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
147 (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
148
149 if (clk == &mcu_pll_clk)
150 __raw_writel(reg, MXC_CCM_MPCTL);
151 else if (clk == &usb_pll_clk)
152 __raw_writel(reg, MXC_CCM_UPCTL);
153 else if (clk == &serial_pll_clk)
154 __raw_writel(reg, MXC_CCM_SRPCTL);
155 133
156 return 0; 134 return mxc_decode_pll(reg, pll_ref_get_rate());
157} 135}
158 136
159static unsigned long _clk_pll_get_rate(struct clk *clk) 137static unsigned long mcu_pll_get_rate(struct clk *clk)
160{ 138{
161 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
162 unsigned long reg, ccmr; 139 unsigned long reg, ccmr;
163 s64 temp;
164 unsigned int prcs;
165 140
166 ccmr = __raw_readl(MXC_CCM_CCMR); 141 ccmr = __raw_readl(MXC_CCM_CCMR);
167 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
168 if (prcs == 0x1)
169 ref_clk = CKIL_CLK_FREQ * 1024;
170 else
171 ref_clk = clk_get_rate(&ckih_clk);
172
173 if (clk == &mcu_pll_clk) {
174 if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
175 return ref_clk;
176 if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
177 return ref_clk;
178 reg = __raw_readl(MXC_CCM_MPCTL);
179 } else if (clk == &usb_pll_clk)
180 reg = __raw_readl(MXC_CCM_UPCTL);
181 else if (clk == &serial_pll_clk)
182 reg = __raw_readl(MXC_CCM_SRPCTL);
183 else {
184 BUG();
185 return 0;
186 }
187
188 pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
189 mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
190 mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
191 mfi = (mfi <= 5) ? 5 : mfi;
192 mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
193 142
194 if (mfn >= 0x200) { 143 if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
195 mfn |= 0xFFFFFE00; 144 return clk_get_rate(&ckih_clk);
196 mfn_abs = -mfn;
197 }
198
199 ref_clk *= 2;
200 ref_clk /= pdf + 1;
201 145
202 temp = (u64) ref_clk * mfn_abs; 146 reg = __raw_readl(MXC_CCM_MPCTL);
203 do_div(temp, mfd + 1);
204 if (mfn < 0)
205 temp = -temp;
206 temp = (ref_clk * mfi) + temp;
207 147
208 return temp; 148 return mxc_decode_pll(reg, pll_ref_get_rate());
209} 149}
210 150
211static int _clk_usb_pll_enable(struct clk *clk) 151static int usb_pll_enable(struct clk *clk)
212{ 152{
213 u32 reg; 153 u32 reg;
214 154
@@ -222,7 +162,7 @@ static int _clk_usb_pll_enable(struct clk *clk)
222 return 0; 162 return 0;
223} 163}
224 164
225static void _clk_usb_pll_disable(struct clk *clk) 165static void usb_pll_disable(struct clk *clk)
226{ 166{
227 u32 reg; 167 u32 reg;
228 168
@@ -231,7 +171,7 @@ static void _clk_usb_pll_disable(struct clk *clk)
231 __raw_writel(reg, MXC_CCM_CCMR); 171 __raw_writel(reg, MXC_CCM_CCMR);
232} 172}
233 173
234static int _clk_serial_pll_enable(struct clk *clk) 174static int serial_pll_enable(struct clk *clk)
235{ 175{
236 u32 reg; 176 u32 reg;
237 177
@@ -245,7 +185,7 @@ static int _clk_serial_pll_enable(struct clk *clk)
245 return 0; 185 return 0;
246} 186}
247 187
248static void _clk_serial_pll_disable(struct clk *clk) 188static void serial_pll_disable(struct clk *clk)
249{ 189{
250 u32 reg; 190 u32 reg;
251 191
@@ -258,7 +198,7 @@ static void _clk_serial_pll_disable(struct clk *clk)
258#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) 198#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
259#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) 199#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
260 200
261static unsigned long _clk_mcu_main_get_rate(struct clk *clk) 201static unsigned long mcu_main_get_rate(struct clk *clk)
262{ 202{
263 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); 203 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
264 204
@@ -268,7 +208,7 @@ static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
268 return clk_get_rate(&mcu_pll_clk); 208 return clk_get_rate(&mcu_pll_clk);
269} 209}
270 210
271static unsigned long _clk_hclk_get_rate(struct clk *clk) 211static unsigned long ahb_get_rate(struct clk *clk)
272{ 212{
273 unsigned long max_pdf; 213 unsigned long max_pdf;
274 214
@@ -277,7 +217,7 @@ static unsigned long _clk_hclk_get_rate(struct clk *clk)
277 return clk_get_rate(clk->parent) / (max_pdf + 1); 217 return clk_get_rate(clk->parent) / (max_pdf + 1);
278} 218}
279 219
280static unsigned long _clk_ipg_get_rate(struct clk *clk) 220static unsigned long ipg_get_rate(struct clk *clk)
281{ 221{
282 unsigned long ipg_pdf; 222 unsigned long ipg_pdf;
283 223
@@ -286,7 +226,7 @@ static unsigned long _clk_ipg_get_rate(struct clk *clk)
286 return clk_get_rate(clk->parent) / (ipg_pdf + 1); 226 return clk_get_rate(clk->parent) / (ipg_pdf + 1);
287} 227}
288 228
289static unsigned long _clk_nfc_get_rate(struct clk *clk) 229static unsigned long nfc_get_rate(struct clk *clk)
290{ 230{
291 unsigned long nfc_pdf; 231 unsigned long nfc_pdf;
292 232
@@ -295,7 +235,7 @@ static unsigned long _clk_nfc_get_rate(struct clk *clk)
295 return clk_get_rate(clk->parent) / (nfc_pdf + 1); 235 return clk_get_rate(clk->parent) / (nfc_pdf + 1);
296} 236}
297 237
298static unsigned long _clk_hsp_get_rate(struct clk *clk) 238static unsigned long hsp_get_rate(struct clk *clk)
299{ 239{
300 unsigned long hsp_pdf; 240 unsigned long hsp_pdf;
301 241
@@ -304,7 +244,7 @@ static unsigned long _clk_hsp_get_rate(struct clk *clk)
304 return clk_get_rate(clk->parent) / (hsp_pdf + 1); 244 return clk_get_rate(clk->parent) / (hsp_pdf + 1);
305} 245}
306 246
307static unsigned long _clk_usb_get_rate(struct clk *clk) 247static unsigned long usb_get_rate(struct clk *clk)
308{ 248{
309 unsigned long usb_pdf, usb_prepdf; 249 unsigned long usb_pdf, usb_prepdf;
310 250
@@ -315,7 +255,7 @@ static unsigned long _clk_usb_get_rate(struct clk *clk)
315 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); 255 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
316} 256}
317 257
318static unsigned long _clk_csi_get_rate(struct clk *clk) 258static unsigned long csi_get_rate(struct clk *clk)
319{ 259{
320 u32 reg, pre, post; 260 u32 reg, pre, post;
321 261
@@ -329,7 +269,7 @@ static unsigned long _clk_csi_get_rate(struct clk *clk)
329 return clk_get_rate(clk->parent) / (pre * post); 269 return clk_get_rate(clk->parent) / (pre * post);
330} 270}
331 271
332static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) 272static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
333{ 273{
334 u32 pre, post, parent = clk_get_rate(clk->parent); 274 u32 pre, post, parent = clk_get_rate(clk->parent);
335 u32 div = parent / rate; 275 u32 div = parent / rate;
@@ -342,7 +282,7 @@ static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
342 return parent / (pre * post); 282 return parent / (pre * post);
343} 283}
344 284
345static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) 285static int csi_set_rate(struct clk *clk, unsigned long rate)
346{ 286{
347 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); 287 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
348 288
@@ -363,16 +303,7 @@ static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
363 return 0; 303 return 0;
364} 304}
365 305
366static unsigned long _clk_per_get_rate(struct clk *clk) 306static unsigned long ssi1_get_rate(struct clk *clk)
367{
368 unsigned long per_pdf;
369
370 per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
371 MXC_CCM_PDR0_PER_PODF_OFFSET);
372 return clk_get_rate(clk->parent) / (per_pdf + 1);
373}
374
375static unsigned long _clk_ssi1_get_rate(struct clk *clk)
376{ 307{
377 unsigned long ssi1_pdf, ssi1_prepdf; 308 unsigned long ssi1_pdf, ssi1_prepdf;
378 309
@@ -383,7 +314,7 @@ static unsigned long _clk_ssi1_get_rate(struct clk *clk)
383 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); 314 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
384} 315}
385 316
386static unsigned long _clk_ssi2_get_rate(struct clk *clk) 317static unsigned long ssi2_get_rate(struct clk *clk)
387{ 318{
388 unsigned long ssi2_pdf, ssi2_prepdf; 319 unsigned long ssi2_pdf, ssi2_prepdf;
389 320
@@ -394,7 +325,7 @@ static unsigned long _clk_ssi2_get_rate(struct clk *clk)
394 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); 325 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
395} 326}
396 327
397static unsigned long _clk_firi_get_rate(struct clk *clk) 328static unsigned long firi_get_rate(struct clk *clk)
398{ 329{
399 unsigned long firi_pdf, firi_prepdf; 330 unsigned long firi_pdf, firi_prepdf;
400 331
@@ -405,7 +336,7 @@ static unsigned long _clk_firi_get_rate(struct clk *clk)
405 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); 336 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
406} 337}
407 338
408static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) 339static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
409{ 340{
410 u32 pre, post; 341 u32 pre, post;
411 u32 parent = clk_get_rate(clk->parent); 342 u32 parent = clk_get_rate(clk->parent);
@@ -420,7 +351,7 @@ static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
420 351
421} 352}
422 353
423static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) 354static int firi_set_rate(struct clk *clk, unsigned long rate)
424{ 355{
425 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); 356 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
426 357
@@ -441,12 +372,12 @@ static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
441 return 0; 372 return 0;
442} 373}
443 374
444static unsigned long _clk_mbx_get_rate(struct clk *clk) 375static unsigned long mbx_get_rate(struct clk *clk)
445{ 376{
446 return clk_get_rate(clk->parent) / 2; 377 return clk_get_rate(clk->parent) / 2;
447} 378}
448 379
449static unsigned long _clk_mstick1_get_rate(struct clk *clk) 380static unsigned long mstick1_get_rate(struct clk *clk)
450{ 381{
451 unsigned long msti_pdf; 382 unsigned long msti_pdf;
452 383
@@ -455,7 +386,7 @@ static unsigned long _clk_mstick1_get_rate(struct clk *clk)
455 return clk_get_rate(clk->parent) / (msti_pdf + 1); 386 return clk_get_rate(clk->parent) / (msti_pdf + 1);
456} 387}
457 388
458static unsigned long _clk_mstick2_get_rate(struct clk *clk) 389static unsigned long mstick2_get_rate(struct clk *clk)
459{ 390{
460 unsigned long msti_pdf; 391 unsigned long msti_pdf;
461 392
@@ -472,661 +403,185 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
472} 403}
473 404
474static struct clk ckih_clk = { 405static struct clk ckih_clk = {
475 .name = "ckih",
476 .get_rate = clk_ckih_get_rate, 406 .get_rate = clk_ckih_get_rate,
477}; 407};
478 408
479static unsigned long clk_ckil_get_rate(struct clk *clk)
480{
481 return CKIL_CLK_FREQ;
482}
483
484static struct clk ckil_clk = {
485 .name = "ckil",
486 .get_rate = clk_ckil_get_rate,
487};
488
489static struct clk mcu_pll_clk = { 409static struct clk mcu_pll_clk = {
490 .name = "mcu_pll",
491 .parent = &ckih_clk, 410 .parent = &ckih_clk,
492 .set_rate = _clk_pll_set_rate, 411 .get_rate = mcu_pll_get_rate,
493 .get_rate = _clk_pll_get_rate,
494}; 412};
495 413
496static struct clk mcu_main_clk = { 414static struct clk mcu_main_clk = {
497 .name = "mcu_main_clk",
498 .parent = &mcu_pll_clk, 415 .parent = &mcu_pll_clk,
499 .get_rate = _clk_mcu_main_get_rate, 416 .get_rate = mcu_main_get_rate,
500}; 417};
501 418
502static struct clk serial_pll_clk = { 419static struct clk serial_pll_clk = {
503 .name = "serial_pll",
504 .parent = &ckih_clk, 420 .parent = &ckih_clk,
505 .set_rate = _clk_pll_set_rate, 421 .get_rate = serial_pll_get_rate,
506 .get_rate = _clk_pll_get_rate, 422 .enable = serial_pll_enable,
507 .enable = _clk_serial_pll_enable, 423 .disable = serial_pll_disable,
508 .disable = _clk_serial_pll_disable,
509}; 424};
510 425
511static struct clk usb_pll_clk = { 426static struct clk usb_pll_clk = {
512 .name = "usb_pll",
513 .parent = &ckih_clk, 427 .parent = &ckih_clk,
514 .set_rate = _clk_pll_set_rate, 428 .get_rate = usb_pll_get_rate,
515 .get_rate = _clk_pll_get_rate, 429 .enable = usb_pll_enable,
516 .enable = _clk_usb_pll_enable, 430 .disable = usb_pll_disable,
517 .disable = _clk_usb_pll_disable,
518}; 431};
519 432
520static struct clk ahb_clk = { 433static struct clk ahb_clk = {
521 .name = "ahb_clk",
522 .parent = &mcu_main_clk, 434 .parent = &mcu_main_clk,
523 .get_rate = _clk_hclk_get_rate, 435 .get_rate = ahb_get_rate,
524}; 436};
525 437
526static struct clk per_clk = { 438#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
527 .name = "per_clk", 439 static struct clk name = { \
528 .parent = &usb_pll_clk, 440 .id = i, \
529 .get_rate = _clk_per_get_rate, 441 .enable_reg = er, \
530}; 442 .enable_shift = es, \
531 443 .get_rate = gr, \
532static struct clk perclk_clk = { 444 .enable = cgr_enable, \
533 .name = "perclk_clk", 445 .disable = cgr_disable, \
534 .parent = &ipg_clk, 446 .secondary = s, \
535}; 447 .parent = p, \
536 448 }
537static struct clk cspi_clk[] = {
538 {
539 .name = "cspi_clk",
540 .id = 0,
541 .parent = &ipg_clk,
542 .enable = _clk_enable,
543 .enable_reg = MXC_CCM_CGR2,
544 .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
545 .disable = _clk_disable,},
546 {
547 .name = "cspi_clk",
548 .id = 1,
549 .parent = &ipg_clk,
550 .enable = _clk_enable,
551 .enable_reg = MXC_CCM_CGR2,
552 .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
553 .disable = _clk_disable,},
554 {
555 .name = "cspi_clk",
556 .id = 2,
557 .parent = &ipg_clk,
558 .enable = _clk_enable,
559 .enable_reg = MXC_CCM_CGR0,
560 .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
561 .disable = _clk_disable,},
562};
563
564static struct clk ipg_clk = {
565 .name = "ipg_clk",
566 .parent = &ahb_clk,
567 .get_rate = _clk_ipg_get_rate,
568};
569
570static struct clk emi_clk = {
571 .name = "emi_clk",
572 .parent = &ahb_clk,
573 .enable = _clk_enable,
574 .enable_reg = MXC_CCM_CGR2,
575 .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
576 .disable = _clk_emi_disable,
577};
578
579static struct clk gpt_clk = {
580 .name = "gpt_clk",
581 .parent = &perclk_clk,
582 .enable = _clk_enable,
583 .enable_reg = MXC_CCM_CGR0,
584 .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
585 .disable = _clk_disable,
586};
587
588static struct clk pwm_clk = {
589 .name = "pwm_clk",
590 .parent = &perclk_clk,
591 .enable = _clk_enable,
592 .enable_reg = MXC_CCM_CGR0,
593 .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
594 .disable = _clk_disable,
595};
596
597static struct clk epit_clk[] = {
598 {
599 .name = "epit_clk",
600 .id = 0,
601 .parent = &perclk_clk,
602 .enable = _clk_enable,
603 .enable_reg = MXC_CCM_CGR0,
604 .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
605 .disable = _clk_disable,},
606 {
607 .name = "epit_clk",
608 .id = 1,
609 .parent = &perclk_clk,
610 .enable = _clk_enable,
611 .enable_reg = MXC_CCM_CGR0,
612 .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
613 .disable = _clk_disable,},
614};
615
616static struct clk nfc_clk = {
617 .name = "nfc_clk",
618 .parent = &ahb_clk,
619 .get_rate = _clk_nfc_get_rate,
620};
621
622static struct clk scc_clk = {
623 .name = "scc_clk",
624 .parent = &ipg_clk,
625};
626
627static struct clk ipu_clk = {
628 .name = "ipu_clk",
629 .parent = &mcu_main_clk,
630 .get_rate = _clk_hsp_get_rate,
631 .enable = _clk_enable,
632 .enable_reg = MXC_CCM_CGR1,
633 .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
634 .disable = _clk_disable,
635};
636
637static struct clk kpp_clk = {
638 .name = "kpp_clk",
639 .parent = &ipg_clk,
640 .enable = _clk_enable,
641 .enable_reg = MXC_CCM_CGR1,
642 .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
643 .disable = _clk_disable,
644};
645
646static struct clk wdog_clk = {
647 .name = "wdog_clk",
648 .parent = &ipg_clk,
649 .enable = _clk_enable,
650 .enable_reg = MXC_CCM_CGR1,
651 .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
652 .disable = _clk_disable,
653};
654static struct clk rtc_clk = {
655 .name = "rtc_clk",
656 .parent = &ipg_clk,
657 .enable = _clk_enable,
658 .enable_reg = MXC_CCM_CGR1,
659 .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
660 .disable = _clk_disable,
661};
662
663static struct clk usb_clk[] = {
664 {
665 .name = "usb_clk",
666 .parent = &usb_pll_clk,
667 .get_rate = _clk_usb_get_rate,},
668 {
669 .name = "usb_ahb_clk",
670 .parent = &ahb_clk,
671 .enable = _clk_enable,
672 .enable_reg = MXC_CCM_CGR1,
673 .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
674 .disable = _clk_disable,},
675};
676
677static struct clk csi_clk = {
678 .name = "csi_clk",
679 .parent = &serial_pll_clk,
680 .get_rate = _clk_csi_get_rate,
681 .round_rate = _clk_csi_round_rate,
682 .set_rate = _clk_csi_set_rate,
683 .enable = _clk_enable,
684 .enable_reg = MXC_CCM_CGR1,
685 .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
686 .disable = _clk_disable,
687};
688
689static struct clk uart_clk[] = {
690 {
691 .name = "uart_clk",
692 .id = 0,
693 .parent = &perclk_clk,
694 .enable = _clk_enable,
695 .enable_reg = MXC_CCM_CGR0,
696 .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
697 .disable = _clk_disable,},
698 {
699 .name = "uart_clk",
700 .id = 1,
701 .parent = &perclk_clk,
702 .enable = _clk_enable,
703 .enable_reg = MXC_CCM_CGR0,
704 .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
705 .disable = _clk_disable,},
706 {
707 .name = "uart_clk",
708 .id = 2,
709 .parent = &perclk_clk,
710 .enable = _clk_enable,
711 .enable_reg = MXC_CCM_CGR1,
712 .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
713 .disable = _clk_disable,},
714 {
715 .name = "uart_clk",
716 .id = 3,
717 .parent = &perclk_clk,
718 .enable = _clk_enable,
719 .enable_reg = MXC_CCM_CGR1,
720 .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
721 .disable = _clk_disable,},
722 {
723 .name = "uart_clk",
724 .id = 4,
725 .parent = &perclk_clk,
726 .enable = _clk_enable,
727 .enable_reg = MXC_CCM_CGR1,
728 .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
729 .disable = _clk_disable,},
730};
731
732static struct clk i2c_clk[] = {
733 {
734 .name = "i2c_clk",
735 .id = 0,
736 .parent = &perclk_clk,
737 .enable = _clk_enable,
738 .enable_reg = MXC_CCM_CGR0,
739 .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
740 .disable = _clk_disable,},
741 {
742 .name = "i2c_clk",
743 .id = 1,
744 .parent = &perclk_clk,
745 .enable = _clk_enable,
746 .enable_reg = MXC_CCM_CGR0,
747 .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
748 .disable = _clk_disable,},
749 {
750 .name = "i2c_clk",
751 .id = 2,
752 .parent = &perclk_clk,
753 .enable = _clk_enable,
754 .enable_reg = MXC_CCM_CGR0,
755 .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
756 .disable = _clk_disable,},
757};
758
759static struct clk owire_clk = {
760 .name = "owire_clk",
761 .parent = &perclk_clk,
762 .enable_reg = MXC_CCM_CGR1,
763 .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
764 .enable = _clk_enable,
765 .disable = _clk_disable,
766};
767
768static struct clk sdhc_clk[] = {
769 {
770 .name = "sdhc_clk",
771 .id = 0,
772 .parent = &perclk_clk,
773 .enable = _clk_enable,
774 .enable_reg = MXC_CCM_CGR0,
775 .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
776 .disable = _clk_disable,},
777 {
778 .name = "sdhc_clk",
779 .id = 1,
780 .parent = &perclk_clk,
781 .enable = _clk_enable,
782 .enable_reg = MXC_CCM_CGR0,
783 .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
784 .disable = _clk_disable,},
785};
786
787static struct clk ssi_clk[] = {
788 {
789 .name = "ssi_clk",
790 .parent = &serial_pll_clk,
791 .get_rate = _clk_ssi1_get_rate,
792 .enable = _clk_enable,
793 .enable_reg = MXC_CCM_CGR0,
794 .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
795 .disable = _clk_disable,},
796 {
797 .name = "ssi_clk",
798 .id = 1,
799 .parent = &serial_pll_clk,
800 .get_rate = _clk_ssi2_get_rate,
801 .enable = _clk_enable,
802 .enable_reg = MXC_CCM_CGR2,
803 .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
804 .disable = _clk_disable,},
805};
806
807static struct clk firi_clk = {
808 .name = "firi_clk",
809 .parent = &usb_pll_clk,
810 .round_rate = _clk_firi_round_rate,
811 .set_rate = _clk_firi_set_rate,
812 .get_rate = _clk_firi_get_rate,
813 .enable = _clk_enable,
814 .enable_reg = MXC_CCM_CGR2,
815 .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
816 .disable = _clk_disable,
817};
818
819static struct clk ata_clk = {
820 .name = "ata_clk",
821 .parent = &ipg_clk,
822 .enable = _clk_enable,
823 .enable_reg = MXC_CCM_CGR0,
824 .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
825 .disable = _clk_disable,
826};
827
828static struct clk mbx_clk = {
829 .name = "mbx_clk",
830 .parent = &ahb_clk,
831 .enable = _clk_enable,
832 .enable_reg = MXC_CCM_CGR2,
833 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
834 .get_rate = _clk_mbx_get_rate,
835};
836
837static struct clk vpu_clk = {
838 .name = "vpu_clk",
839 .parent = &ahb_clk,
840 .enable = _clk_enable,
841 .enable_reg = MXC_CCM_CGR2,
842 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
843 .get_rate = _clk_mbx_get_rate,
844};
845
846static struct clk rtic_clk = {
847 .name = "rtic_clk",
848 .parent = &ahb_clk,
849 .enable = _clk_enable,
850 .enable_reg = MXC_CCM_CGR2,
851 .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
852 .disable = _clk_disable,
853};
854
855static struct clk rng_clk = {
856 .name = "rng_clk",
857 .parent = &ipg_clk,
858 .enable = _clk_enable,
859 .enable_reg = MXC_CCM_CGR0,
860 .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
861 .disable = _clk_disable,
862};
863
864static struct clk sdma_clk[] = {
865 {
866 .name = "sdma_ahb_clk",
867 .parent = &ahb_clk,
868 .enable = _clk_enable,
869 .enable_reg = MXC_CCM_CGR0,
870 .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
871 .disable = _clk_disable,},
872 {
873 .name = "sdma_ipg_clk",
874 .parent = &ipg_clk,}
875};
876
877static struct clk mpeg4_clk = {
878 .name = "mpeg4_clk",
879 .parent = &ahb_clk,
880 .enable = _clk_enable,
881 .enable_reg = MXC_CCM_CGR1,
882 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
883 .disable = _clk_disable,
884};
885
886static struct clk vl2cc_clk = {
887 .name = "vl2cc_clk",
888 .parent = &ahb_clk,
889 .enable = _clk_enable,
890 .enable_reg = MXC_CCM_CGR1,
891 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
892 .disable = _clk_disable,
893};
894
895static struct clk mstick_clk[] = {
896 {
897 .name = "mstick_clk",
898 .id = 0,
899 .parent = &usb_pll_clk,
900 .get_rate = _clk_mstick1_get_rate,
901 .enable = _clk_enable,
902 .enable_reg = MXC_CCM_CGR1,
903 .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
904 .disable = _clk_disable,},
905 {
906 .name = "mstick_clk",
907 .id = 1,
908 .parent = &usb_pll_clk,
909 .get_rate = _clk_mstick2_get_rate,
910 .enable = _clk_enable,
911 .enable_reg = MXC_CCM_CGR1,
912 .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
913 .disable = _clk_disable,},
914};
915
916static struct clk iim_clk = {
917 .name = "iim_clk",
918 .parent = &ipg_clk,
919 .enable = _clk_enable,
920 .enable_reg = MXC_CCM_CGR0,
921 .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
922 .disable = _clk_disable,
923};
924
925static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
926{
927 u32 div, parent = clk_get_rate(clk->parent);
928
929 div = parent / rate;
930 if (parent % rate)
931 div++;
932
933 if (div > 8)
934 div = 16;
935 else if (div > 4)
936 div = 8;
937 else if (div > 2)
938 div = 4;
939
940 return parent / div;
941}
942
943static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
944{
945 u32 reg, div, parent = clk_get_rate(clk->parent);
946
947 div = parent / rate;
948
949 if (div == 16)
950 div = 4;
951 else if (div == 8)
952 div = 3;
953 else if (div == 4)
954 div = 2;
955 else if (div == 2)
956 div = 1;
957 else if (div == 1)
958 div = 0;
959 else
960 return -EINVAL;
961
962 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
963 reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
964 __raw_writel(reg, MXC_CCM_COSR);
965
966 return 0;
967}
968
969static unsigned long _clk_cko1_get_rate(struct clk *clk)
970{
971 u32 div;
972
973 div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
974 MXC_CCM_COSR_CLKOUTDIV_OFFSET;
975
976 return clk_get_rate(clk->parent) / (1 << div);
977}
978
979static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
980{
981 u32 reg;
982
983 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
984
985 if (parent == &mcu_main_clk)
986 reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
987 else if (parent == &ipg_clk)
988 reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
989 else if (parent == &usb_pll_clk)
990 reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
991 else if (parent == mcu_main_clk.parent)
992 reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
993 else if (parent == &ahb_clk)
994 reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
995 else if (parent == &serial_pll_clk)
996 reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
997 else if (parent == &ckih_clk)
998 reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
999 else if (parent == &emi_clk)
1000 reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
1001 else if (parent == &ipu_clk)
1002 reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
1003 else if (parent == &nfc_clk)
1004 reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
1005 else if (parent == &uart_clk[0])
1006 reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
1007 else
1008 return -EINVAL;
1009
1010 __raw_writel(reg, MXC_CCM_COSR);
1011
1012 return 0;
1013}
1014
1015static int _clk_cko1_enable(struct clk *clk)
1016{
1017 u32 reg;
1018
1019 reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
1020 __raw_writel(reg, MXC_CCM_COSR);
1021 449
1022 return 0; 450#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
1023} 451 static struct clk name = { \
452 .id = i, \
453 .enable_reg = er, \
454 .enable_shift = es, \
455 .get_rate = getsetround##_get_rate, \
456 .set_rate = getsetround##_set_rate, \
457 .round_rate = getsetround##_round_rate, \
458 .enable = cgr_enable, \
459 .disable = cgr_disable, \
460 .secondary = s, \
461 .parent = p, \
462 }
1024 463
1025static void _clk_cko1_disable(struct clk *clk) 464DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
465
466DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
467DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
468DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
469DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
470DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
471DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
472DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
473DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk);
474DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
475DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
476DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
477DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
478DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
479DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
480DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
481DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
482
483DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
484DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
485DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
486DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &ahb_clk);
487DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk);
488DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
489DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
490DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
491DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
492DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
493DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
494DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
495DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
496DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
497
498DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
499DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
500DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
501DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
502DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
503DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
504DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
505
506DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
507DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
508DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
509DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
510DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
511
512#define _REGISTER_CLOCK(d, n, c) \
513 { \
514 .dev_id = d, \
515 .con_id = n, \
516 .clk = &c, \
517 },
518
519static struct clk_lookup lookups[] __initdata = {
520 _REGISTER_CLOCK(NULL, "emi", emi_clk)
521 _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
522 _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
523 _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
524 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
525 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
526 _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
527 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
528 _REGISTER_CLOCK(NULL, "epit", epit1_clk)
529 _REGISTER_CLOCK(NULL, "epit", epit2_clk)
530 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
531 _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
532 _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
533 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
534 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
535 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
536 _REGISTER_CLOCK("mx3-camera.0", "csi", csi_clk)
537 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
538 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
539 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
540 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
541 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
542 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
543 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
544 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
545 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
546 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
547 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
548 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
549 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
550 _REGISTER_CLOCK(NULL, "firi", firi_clk)
551 _REGISTER_CLOCK(NULL, "ata", ata_clk)
552 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
553 _REGISTER_CLOCK(NULL, "rng", rng_clk)
554 _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1)
555 _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
556 _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
557 _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
558 _REGISTER_CLOCK(NULL, "scc", scc_clk)
559 _REGISTER_CLOCK(NULL, "iim", iim_clk)
560 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
561 _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
562};
563
564int __init mx31_clocks_init(unsigned long fref)
1026{ 565{
1027 u32 reg; 566 u32 reg;
567 int i;
1028 568
1029 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN; 569 mxc_set_cpu_type(MXC_CPU_MX31);
1030 __raw_writel(reg, MXC_CCM_COSR);
1031}
1032
1033static struct clk cko1_clk = {
1034 .name = "cko1_clk",
1035 .get_rate = _clk_cko1_get_rate,
1036 .set_rate = _clk_cko1_set_rate,
1037 .round_rate = _clk_cko1_round_rate,
1038 .set_parent = _clk_cko1_set_parent,
1039 .enable = _clk_cko1_enable,
1040 .disable = _clk_cko1_disable,
1041};
1042
1043static struct clk *mxc_clks[] = {
1044 &ckih_clk,
1045 &ckil_clk,
1046 &mcu_pll_clk,
1047 &usb_pll_clk,
1048 &serial_pll_clk,
1049 &mcu_main_clk,
1050 &ahb_clk,
1051 &per_clk,
1052 &perclk_clk,
1053 &cko1_clk,
1054 &emi_clk,
1055 &cspi_clk[0],
1056 &cspi_clk[1],
1057 &cspi_clk[2],
1058 &ipg_clk,
1059 &gpt_clk,
1060 &pwm_clk,
1061 &wdog_clk,
1062 &rtc_clk,
1063 &epit_clk[0],
1064 &epit_clk[1],
1065 &nfc_clk,
1066 &ipu_clk,
1067 &kpp_clk,
1068 &usb_clk[0],
1069 &usb_clk[1],
1070 &csi_clk,
1071 &uart_clk[0],
1072 &uart_clk[1],
1073 &uart_clk[2],
1074 &uart_clk[3],
1075 &uart_clk[4],
1076 &i2c_clk[0],
1077 &i2c_clk[1],
1078 &i2c_clk[2],
1079 &owire_clk,
1080 &sdhc_clk[0],
1081 &sdhc_clk[1],
1082 &ssi_clk[0],
1083 &ssi_clk[1],
1084 &firi_clk,
1085 &ata_clk,
1086 &rtic_clk,
1087 &rng_clk,
1088 &sdma_clk[0],
1089 &sdma_clk[1],
1090 &mstick_clk[0],
1091 &mstick_clk[1],
1092 &scc_clk,
1093 &iim_clk,
1094};
1095
1096int __init mxc_clocks_init(unsigned long fref)
1097{
1098 u32 reg;
1099 struct clk **clkp;
1100 570
1101 ckih_rate = fref; 571 ckih_rate = fref;
1102 572
1103 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) 573 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1104 clk_register(*clkp); 574 clkdev_add(&lookups[i]);
1105
1106 if (cpu_is_mx31()) {
1107 clk_register(&mpeg4_clk);
1108 clk_register(&mbx_clk);
1109 } else {
1110 clk_register(&vpu_clk);
1111 clk_register(&vl2cc_clk);
1112 }
1113 575
1114 /* Turn off all possible clocks */ 576 /* Turn off all possible clocks */
1115 __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0); 577 __raw_writel((3 << 4), MXC_CCM_CGR0);
1116 __raw_writel(0, MXC_CCM_CGR1); 578 __raw_writel(0, MXC_CCM_CGR1);
1117 579 __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
1118 __raw_writel(MXC_CCM_CGR2_EMI_MASK |
1119 MXC_CCM_CGR2_IPMUX1_MASK |
1120 MXC_CCM_CGR2_IPMUX2_MASK |
1121 MXC_CCM_CGR2_MXCCLKENSEL_MASK | /* for MX32 */
1122 MXC_CCM_CGR2_CHIKCAMPEN_MASK | /* for MX32 */
1123 MXC_CCM_CGR2_OVRVPUBUSY_MASK | /* for MX32 */
1124 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for 580 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
1125 MX32, but still required to be set */ 581 MX32, but still required to be set */
1126 MXC_CCM_CGR2); 582 MXC_CCM_CGR2);
1127 583
1128 clk_disable(&cko1_clk); 584 usb_pll_disable(&usb_pll_clk);
1129 clk_disable(&usb_pll_clk);
1130 585
1131 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); 586 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
1132 587
@@ -1143,6 +598,8 @@ int __init mxc_clocks_init(unsigned long fref)
1143 __raw_writel(reg, MXC_CCM_PMCR1); 598 __raw_writel(reg, MXC_CCM_PMCR1);
1144 } 599 }
1145 600
601 mxc_timer_init(&ipg_clk);
602
1146 return 0; 603 return 0;
1147} 604}
1148 605
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 03:31:23 -0500