aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s5pc100/clock.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-s5pc100/clock.c')
-rw-r--r--arch/arm/mach-s5pc100/clock.c130
1 files changed, 79 insertions, 51 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 9d644ece2604..69829ba9c01b 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = {
426 .enable = s5pc100_d0_2_ctrl, 426 .enable = s5pc100_d0_2_ctrl,
427 .ctrlbit = (1 << 1), 427 .ctrlbit = (1 << 1),
428 }, { 428 }, {
429 .name = "hsmmc",
430 .devname = "s3c-sdhci.2",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
433 .ctrlbit = (1 << 7),
434 }, {
435 .name = "hsmmc",
436 .devname = "s3c-sdhci.1",
437 .parent = &clk_div_d1_bus.clk,
438 .enable = s5pc100_d1_0_ctrl,
439 .ctrlbit = (1 << 6),
440 }, {
441 .name = "hsmmc",
442 .devname = "s3c-sdhci.0",
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
445 .ctrlbit = (1 << 5),
446 }, {
447 .name = "modemif", 429 .name = "modemif",
448 .parent = &clk_div_d1_bus.clk, 430 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl, 431 .enable = s5pc100_d1_0_ctrl,
@@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = {
711 }, 693 },
712}; 694};
713 695
696static struct clk clk_hsmmc2 = {
697 .name = "hsmmc",
698 .devname = "s3c-sdhci.2",
699 .parent = &clk_div_d1_bus.clk,
700 .enable = s5pc100_d1_0_ctrl,
701 .ctrlbit = (1 << 7),
702};
703
704static struct clk clk_hsmmc1 = {
705 .name = "hsmmc",
706 .devname = "s3c-sdhci.1",
707 .parent = &clk_div_d1_bus.clk,
708 .enable = s5pc100_d1_0_ctrl,
709 .ctrlbit = (1 << 6),
710};
711
712static struct clk clk_hsmmc0 = {
713 .name = "hsmmc",
714 .devname = "s3c-sdhci.0",
715 .parent = &clk_div_d1_bus.clk,
716 .enable = s5pc100_d1_0_ctrl,
717 .ctrlbit = (1 << 5),
718};
719
714static struct clk clk_vclk54m = { 720static struct clk clk_vclk54m = {
715 .name = "vclk_54m", 721 .name = "vclk_54m",
716 .rate = 54000000, 722 .rate = 54000000,
@@ -1014,39 +1020,6 @@ static struct clksrc_clk clksrcs[] = {
1014 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 1020 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1015 }, { 1021 }, {
1016 .clk = { 1022 .clk = {
1017 .name = "sclk_mmc",
1018 .devname = "s3c-sdhci.0",
1019 .ctrlbit = (1 << 12),
1020 .enable = s5pc100_sclk1_ctrl,
1021
1022 },
1023 .sources = &clk_src_mmc0,
1024 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1025 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1026 }, {
1027 .clk = {
1028 .name = "sclk_mmc",
1029 .devname = "s3c-sdhci.1",
1030 .ctrlbit = (1 << 13),
1031 .enable = s5pc100_sclk1_ctrl,
1032
1033 },
1034 .sources = &clk_src_mmc12,
1035 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1036 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1037 }, {
1038 .clk = {
1039 .name = "sclk_mmc",
1040 .devname = "s3c-sdhci.2",
1041 .ctrlbit = (1 << 14),
1042 .enable = s5pc100_sclk1_ctrl,
1043
1044 },
1045 .sources = &clk_src_mmc12,
1046 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1047 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1048 }, {
1049 .clk = {
1050 .name = "sclk_irda", 1023 .name = "sclk_irda",
1051 .ctrlbit = (1 << 10), 1024 .ctrlbit = (1 << 10),
1052 .enable = s5pc100_sclk0_ctrl, 1025 .enable = s5pc100_sclk0_ctrl,
@@ -1099,6 +1072,42 @@ static struct clksrc_clk clk_sclk_uart = {
1099 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, 1072 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1100}; 1073};
1101 1074
1075static struct clksrc_clk clk_sclk_mmc0 = {
1076 .clk = {
1077 .name = "sclk_mmc",
1078 .devname = "s3c-sdhci.0",
1079 .ctrlbit = (1 << 12),
1080 .enable = s5pc100_sclk1_ctrl,
1081 },
1082 .sources = &clk_src_mmc0,
1083 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1084 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1085};
1086
1087static struct clksrc_clk clk_sclk_mmc1 = {
1088 .clk = {
1089 .name = "sclk_mmc",
1090 .devname = "s3c-sdhci.1",
1091 .ctrlbit = (1 << 13),
1092 .enable = s5pc100_sclk1_ctrl,
1093 },
1094 .sources = &clk_src_mmc12,
1095 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1096 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1097};
1098
1099static struct clksrc_clk clk_sclk_mmc2 = {
1100 .clk = {
1101 .name = "sclk_mmc",
1102 .devname = "s3c-sdhci.2",
1103 .ctrlbit = (1 << 14),
1104 .enable = s5pc100_sclk1_ctrl,
1105 },
1106 .sources = &clk_src_mmc12,
1107 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1108 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1109};
1110
1102/* Clock initialisation code */ 1111/* Clock initialisation code */
1103static struct clksrc_clk *sysclks[] = { 1112static struct clksrc_clk *sysclks[] = {
1104 &clk_mout_apll, 1113 &clk_mout_apll,
@@ -1128,8 +1137,17 @@ static struct clksrc_clk *sysclks[] = {
1128 &clk_sclk_spdif, 1137 &clk_sclk_spdif,
1129}; 1138};
1130 1139
1140static struct clk *clk_cdev[] = {
1141 &clk_hsmmc0,
1142 &clk_hsmmc1,
1143 &clk_hsmmc2,
1144};
1145
1131static struct clksrc_clk *clksrc_cdev[] = { 1146static struct clksrc_clk *clksrc_cdev[] = {
1132 &clk_sclk_uart, 1147 &clk_sclk_uart,
1148 &clk_sclk_mmc0,
1149 &clk_sclk_mmc1,
1150 &clk_sclk_mmc2,
1133}; 1151};
1134 1152
1135void __init_or_cpufreq s5pc100_setup_clocks(void) 1153void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1274,6 +1292,12 @@ static struct clk *clks[] __initdata = {
1274static struct clk_lookup s5pc100_clk_lookup[] = { 1292static struct clk_lookup s5pc100_clk_lookup[] = {
1275 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 1293 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1276 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), 1294 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1295 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1296 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1297 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1298 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1299 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1300 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1277}; 1301};
1278 1302
1279void __init s5pc100_register_clocks(void) 1303void __init s5pc100_register_clocks(void)
@@ -1294,6 +1318,10 @@ void __init s5pc100_register_clocks(void)
1294 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1318 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1295 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); 1319 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1296 1320
1321 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1322 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1323 s3c_disable_clocks(clk_cdev[ptr], 1);
1324
1297 s3c24xx_register_clock(&dummy_apb_pclk); 1325 s3c24xx_register_clock(&dummy_apb_pclk);
1298 1326
1299 s3c_pwmclk_init(); 1327 s3c_pwmclk_init();