ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names

Add support for lookup of sdhci-s3c controller clocks using generic names
for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
[kgene.kim@samsung.com: fixed trailing whitespace]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 79 insertions, 51 deletions

diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 9d644ece2604..69829ba9c01b 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pc100_d0_2_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
                 .name           = "modemif",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_0_ctrl,
@@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = {
         },
 };
 
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 7),
+};
+
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 6),
+};
+
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 5),
+};
+
 static struct clk clk_vclk54m = {
         .name           = "vclk_54m",
         .rate           = 54000000,
@@ -1014,39 +1020,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
         }, {
                 .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 12),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_mmc0,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 13),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_mmc12,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 14),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_mmc12,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_irda",
                         .ctrlbit        = (1 << 10),
                         .enable         = s5pc100_sclk0_ctrl,
@@ -1099,6 +1072,42 @@ static struct clksrc_clk clk_sclk_uart = {
         .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 12),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc0,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 13),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc12,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 14),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc12,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+
 /* Clock initialisation code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
@@ -1128,8 +1137,17 @@ static struct clksrc_clk *sysclks[] = {
         &clk_sclk_spdif,
 };
 
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+};
+
 static struct clksrc_clk *clksrc_cdev[] = {
         &clk_sclk_uart,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
 };
 
 void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1274,6 +1292,12 @@ static struct clk *clks[] __initdata = {
 static struct clk_lookup s5pc100_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 };
 
 void __init s5pc100_register_clocks(void)
@@ -1294,6 +1318,10 @@ void __init s5pc100_register_clocks(void)
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
 
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
+
         s3c24xx_register_clock(&dummy_apb_pclk);
 
         s3c_pwmclk_init();