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-rw-r--r--arch/arm/mach-s3c64xx/Kconfig24
-rw-r--r--arch/arm/mach-s3c64xx/Makefile5
-rw-r--r--arch/arm/mach-s3c64xx/clock.c86
-rw-r--r--arch/arm/mach-s3c64xx/cpufreq.c270
-rw-r--r--arch/arm/mach-s3c64xx/dev-onenand1.c10
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pm-core.h19
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-fb.h21
-rw-r--r--arch/arm/mach-s3c64xx/irq.c12
-rw-r--r--arch/arm/mach-s3c64xx/mach-anw6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c774
-rw-r--r--arch/arm/mach-s3c64xx/mach-hmt.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-mini6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-ncp.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-real6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq5.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq7.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c43
-rw-r--r--arch/arm/mach-s3c64xx/setup-fb-24bpp.c1
20 files changed, 894 insertions, 397 deletions
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index e4177e22557b..f057b6ae4f90 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -142,6 +142,7 @@ config MACH_SMDK6410
142 select S3C_DEV_USB_HOST 142 select S3C_DEV_USB_HOST
143 select S3C_DEV_USB_HSOTG 143 select S3C_DEV_USB_HSOTG
144 select S3C_DEV_WDT 144 select S3C_DEV_WDT
145 select SAMSUNG_DEV_BACKLIGHT
145 select SAMSUNG_DEV_KEYPAD 146 select SAMSUNG_DEV_KEYPAD
146 select SAMSUNG_DEV_PWM 147 select SAMSUNG_DEV_PWM
147 select HAVE_S3C2410_WATCHDOG if WATCHDOG 148 select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -266,3 +267,26 @@ config MACH_SMARTQ7
266 select MACH_SMARTQ 267 select MACH_SMARTQ
267 help 268 help
268 Machine support for the SmartQ 7 269 Machine support for the SmartQ 7
270
271config MACH_WLF_CRAGG_6410
272 bool "Wolfson Cragganmore 6410"
273 select CPU_S3C6410
274 select S3C64XX_SETUP_SDHCI
275 select S3C64XX_SETUP_I2C1
276 select S3C64XX_SETUP_IDE
277 select S3C64XX_SETUP_FB_24BPP
278 select S3C64XX_SETUP_KEYPAD
279 select SAMSUNG_DEV_ADC
280 select SAMSUNG_DEV_KEYPAD
281 select S3C_DEV_USB_HOST
282 select S3C_DEV_USB_HSOTG
283 select S3C_DEV_HSMMC
284 select S3C_DEV_HSMMC1
285 select S3C_DEV_HSMMC2
286 select S3C_DEV_I2C1
287 select S3C_DEV_WDT
288 select S3C_DEV_RTC
289 select S3C64XX_DEV_SPI
290 select S3C24XX_GPIO_EXTRA128
291 help
292 Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 4657363f0674..61b4034a0c22 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -23,10 +23,6 @@ obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
23obj-y += irq.o 23obj-y += irq.o
24obj-y += irq-eint.o 24obj-y += irq-eint.o
25 25
26# CPU frequency scaling
27
28obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o
29
30# DMA support 26# DMA support
31 27
32obj-$(CONFIG_S3C64XX_DMA) += dma.o 28obj-$(CONFIG_S3C64XX_DMA) += dma.o
@@ -59,6 +55,7 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
59obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o 55obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
60obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o 56obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
61obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o 57obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
58obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
62 59
63# device support 60# device support
64 61
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fdfc4d5e37a1..8cf39e33579e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -39,7 +39,6 @@
39 39
40static struct clk clk_ext_xtal_mux = { 40static struct clk clk_ext_xtal_mux = {
41 .name = "ext_xtal", 41 .name = "ext_xtal",
42 .id = -1,
43}; 42};
44 43
45#define clk_fin_apll clk_ext_xtal_mux 44#define clk_fin_apll clk_ext_xtal_mux
@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
51 50
52struct clk clk_h2 = { 51struct clk clk_h2 = {
53 .name = "hclk2", 52 .name = "hclk2",
54 .id = -1,
55 .rate = 0, 53 .rate = 0,
56}; 54};
57 55
58struct clk clk_27m = { 56struct clk clk_27m = {
59 .name = "clk_27m", 57 .name = "clk_27m",
60 .id = -1,
61 .rate = 27000000, 58 .rate = 27000000,
62}; 59};
63 60
@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
83 80
84struct clk clk_48m = { 81struct clk clk_48m = {
85 .name = "clk_48m", 82 .name = "clk_48m",
86 .id = -1,
87 .rate = 48000000, 83 .rate = 48000000,
88 .enable = clk_48m_ctrl, 84 .enable = clk_48m_ctrl,
89}; 85};
90 86
91struct clk clk_xusbxti = { 87struct clk clk_xusbxti = {
92 .name = "xusbxti", 88 .name = "xusbxti",
93 .id = -1,
94 .rate = 48000000, 89 .rate = 48000000,
95}; 90};
96 91
@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
130static struct clk init_clocks_off[] = { 125static struct clk init_clocks_off[] = {
131 { 126 {
132 .name = "nand", 127 .name = "nand",
133 .id = -1,
134 .parent = &clk_h, 128 .parent = &clk_h,
135 }, { 129 }, {
136 .name = "rtc", 130 .name = "rtc",
137 .id = -1,
138 .parent = &clk_p, 131 .parent = &clk_p,
139 .enable = s3c64xx_pclk_ctrl, 132 .enable = s3c64xx_pclk_ctrl,
140 .ctrlbit = S3C_CLKCON_PCLK_RTC, 133 .ctrlbit = S3C_CLKCON_PCLK_RTC,
141 }, { 134 }, {
142 .name = "adc", 135 .name = "adc",
143 .id = -1,
144 .parent = &clk_p, 136 .parent = &clk_p,
145 .enable = s3c64xx_pclk_ctrl, 137 .enable = s3c64xx_pclk_ctrl,
146 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
147 }, { 139 }, {
148 .name = "i2c", 140 .name = "i2c",
149 .id = -1,
150 .parent = &clk_p, 141 .parent = &clk_p,
151 .enable = s3c64xx_pclk_ctrl, 142 .enable = s3c64xx_pclk_ctrl,
152 .ctrlbit = S3C_CLKCON_PCLK_IIC, 143 .ctrlbit = S3C_CLKCON_PCLK_IIC,
153 }, { 144 }, {
154 .name = "i2c", 145 .name = "i2c",
155 .id = 1, 146 .devname = "s3c2440-i2c.1",
156 .parent = &clk_p, 147 .parent = &clk_p,
157 .enable = s3c64xx_pclk_ctrl, 148 .enable = s3c64xx_pclk_ctrl,
158 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, 149 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
159 }, { 150 }, {
160 .name = "iis", 151 .name = "iis",
161 .id = 0, 152 .devname = "samsung-i2s.0",
162 .parent = &clk_p, 153 .parent = &clk_p,
163 .enable = s3c64xx_pclk_ctrl, 154 .enable = s3c64xx_pclk_ctrl,
164 .ctrlbit = S3C_CLKCON_PCLK_IIS0, 155 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
165 }, { 156 }, {
166 .name = "iis", 157 .name = "iis",
167 .id = 1, 158 .devname = "samsung-i2s.1",
168 .parent = &clk_p, 159 .parent = &clk_p,
169 .enable = s3c64xx_pclk_ctrl, 160 .enable = s3c64xx_pclk_ctrl,
170 .ctrlbit = S3C_CLKCON_PCLK_IIS1, 161 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
171 }, { 162 }, {
172#ifdef CONFIG_CPU_S3C6410 163#ifdef CONFIG_CPU_S3C6410
173 .name = "iis", 164 .name = "iis",
174 .id = -1, /* There's only one IISv4 port */
175 .parent = &clk_p, 165 .parent = &clk_p,
176 .enable = s3c64xx_pclk_ctrl, 166 .enable = s3c64xx_pclk_ctrl,
177 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, 167 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
178 }, { 168 }, {
179#endif 169#endif
180 .name = "keypad", 170 .name = "keypad",
181 .id = -1,
182 .parent = &clk_p, 171 .parent = &clk_p,
183 .enable = s3c64xx_pclk_ctrl, 172 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, 173 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
185 }, { 174 }, {
186 .name = "spi", 175 .name = "spi",
187 .id = 0, 176 .devname = "s3c64xx-spi.0",
188 .parent = &clk_p, 177 .parent = &clk_p,
189 .enable = s3c64xx_pclk_ctrl, 178 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI0, 179 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
191 }, { 180 }, {
192 .name = "spi", 181 .name = "spi",
193 .id = 1, 182 .devname = "s3c64xx-spi.1",
194 .parent = &clk_p, 183 .parent = &clk_p,
195 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
196 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
197 }, { 186 }, {
198 .name = "spi_48m", 187 .name = "spi_48m",
199 .id = 0, 188 .devname = "s3c64xx-spi.0",
200 .parent = &clk_48m, 189 .parent = &clk_48m,
201 .enable = s3c64xx_sclk_ctrl, 190 .enable = s3c64xx_sclk_ctrl,
202 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, 191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
203 }, { 192 }, {
204 .name = "spi_48m", 193 .name = "spi_48m",
205 .id = 1, 194 .devname = "s3c64xx-spi.1",
206 .parent = &clk_48m, 195 .parent = &clk_48m,
207 .enable = s3c64xx_sclk_ctrl, 196 .enable = s3c64xx_sclk_ctrl,
208 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, 197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
209 }, { 198 }, {
210 .name = "48m", 199 .name = "48m",
211 .id = 0, 200 .devname = "s3c-sdhci.0",
212 .parent = &clk_48m, 201 .parent = &clk_48m,
213 .enable = s3c64xx_sclk_ctrl, 202 .enable = s3c64xx_sclk_ctrl,
214 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, 203 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
215 }, { 204 }, {
216 .name = "48m", 205 .name = "48m",
217 .id = 1, 206 .devname = "s3c-sdhci.1",
218 .parent = &clk_48m, 207 .parent = &clk_48m,
219 .enable = s3c64xx_sclk_ctrl, 208 .enable = s3c64xx_sclk_ctrl,
220 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, 209 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
221 }, { 210 }, {
222 .name = "48m", 211 .name = "48m",
223 .id = 2, 212 .devname = "s3c-sdhci.2",
224 .parent = &clk_48m, 213 .parent = &clk_48m,
225 .enable = s3c64xx_sclk_ctrl, 214 .enable = s3c64xx_sclk_ctrl,
226 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, 215 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
227 }, { 216 }, {
228 .name = "dma0", 217 .name = "dma0",
229 .id = -1,
230 .parent = &clk_h, 218 .parent = &clk_h,
231 .enable = s3c64xx_hclk_ctrl, 219 .enable = s3c64xx_hclk_ctrl,
232 .ctrlbit = S3C_CLKCON_HCLK_DMA0, 220 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
233 }, { 221 }, {
234 .name = "dma1", 222 .name = "dma1",
235 .id = -1,
236 .parent = &clk_h, 223 .parent = &clk_h,
237 .enable = s3c64xx_hclk_ctrl, 224 .enable = s3c64xx_hclk_ctrl,
238 .ctrlbit = S3C_CLKCON_HCLK_DMA1, 225 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
242static struct clk init_clocks[] = { 229static struct clk init_clocks[] = {
243 { 230 {
244 .name = "lcd", 231 .name = "lcd",
245 .id = -1,
246 .parent = &clk_h, 232 .parent = &clk_h,
247 .enable = s3c64xx_hclk_ctrl, 233 .enable = s3c64xx_hclk_ctrl,
248 .ctrlbit = S3C_CLKCON_HCLK_LCD, 234 .ctrlbit = S3C_CLKCON_HCLK_LCD,
249 }, { 235 }, {
250 .name = "gpio", 236 .name = "gpio",
251 .id = -1,
252 .parent = &clk_p, 237 .parent = &clk_p,
253 .enable = s3c64xx_pclk_ctrl, 238 .enable = s3c64xx_pclk_ctrl,
254 .ctrlbit = S3C_CLKCON_PCLK_GPIO, 239 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
255 }, { 240 }, {
256 .name = "usb-host", 241 .name = "usb-host",
257 .id = -1,
258 .parent = &clk_h, 242 .parent = &clk_h,
259 .enable = s3c64xx_hclk_ctrl, 243 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 244 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
261 }, { 245 }, {
262 .name = "hsmmc", 246 .name = "hsmmc",
263 .id = 0, 247 .devname = "s3c-sdhci.0",
264 .parent = &clk_h, 248 .parent = &clk_h,
265 .enable = s3c64xx_hclk_ctrl, 249 .enable = s3c64xx_hclk_ctrl,
266 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, 250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
267 }, { 251 }, {
268 .name = "hsmmc", 252 .name = "hsmmc",
269 .id = 1, 253 .devname = "s3c-sdhci.1",
270 .parent = &clk_h, 254 .parent = &clk_h,
271 .enable = s3c64xx_hclk_ctrl, 255 .enable = s3c64xx_hclk_ctrl,
272 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, 256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
273 }, { 257 }, {
274 .name = "hsmmc", 258 .name = "hsmmc",
275 .id = 2, 259 .devname = "s3c-sdhci.2",
276 .parent = &clk_h, 260 .parent = &clk_h,
277 .enable = s3c64xx_hclk_ctrl, 261 .enable = s3c64xx_hclk_ctrl,
278 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, 262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
279 }, { 263 }, {
280 .name = "otg", 264 .name = "otg",
281 .id = -1,
282 .parent = &clk_h, 265 .parent = &clk_h,
283 .enable = s3c64xx_hclk_ctrl, 266 .enable = s3c64xx_hclk_ctrl,
284 .ctrlbit = S3C_CLKCON_HCLK_USB, 267 .ctrlbit = S3C_CLKCON_HCLK_USB,
285 }, { 268 }, {
286 .name = "timers", 269 .name = "timers",
287 .id = -1,
288 .parent = &clk_p, 270 .parent = &clk_p,
289 .enable = s3c64xx_pclk_ctrl, 271 .enable = s3c64xx_pclk_ctrl,
290 .ctrlbit = S3C_CLKCON_PCLK_PWM, 272 .ctrlbit = S3C_CLKCON_PCLK_PWM,
291 }, { 273 }, {
292 .name = "uart", 274 .name = "uart",
293 .id = 0, 275 .devname = "s3c6400-uart.0",
294 .parent = &clk_p, 276 .parent = &clk_p,
295 .enable = s3c64xx_pclk_ctrl, 277 .enable = s3c64xx_pclk_ctrl,
296 .ctrlbit = S3C_CLKCON_PCLK_UART0, 278 .ctrlbit = S3C_CLKCON_PCLK_UART0,
297 }, { 279 }, {
298 .name = "uart", 280 .name = "uart",
299 .id = 1, 281 .devname = "s3c6400-uart.1",
300 .parent = &clk_p, 282 .parent = &clk_p,
301 .enable = s3c64xx_pclk_ctrl, 283 .enable = s3c64xx_pclk_ctrl,
302 .ctrlbit = S3C_CLKCON_PCLK_UART1, 284 .ctrlbit = S3C_CLKCON_PCLK_UART1,
303 }, { 285 }, {
304 .name = "uart", 286 .name = "uart",
305 .id = 2, 287 .devname = "s3c6400-uart.2",
306 .parent = &clk_p, 288 .parent = &clk_p,
307 .enable = s3c64xx_pclk_ctrl, 289 .enable = s3c64xx_pclk_ctrl,
308 .ctrlbit = S3C_CLKCON_PCLK_UART2, 290 .ctrlbit = S3C_CLKCON_PCLK_UART2,
309 }, { 291 }, {
310 .name = "uart", 292 .name = "uart",
311 .id = 3, 293 .devname = "s3c6400-uart.3",
312 .parent = &clk_p, 294 .parent = &clk_p,
313 .enable = s3c64xx_pclk_ctrl, 295 .enable = s3c64xx_pclk_ctrl,
314 .ctrlbit = S3C_CLKCON_PCLK_UART3, 296 .ctrlbit = S3C_CLKCON_PCLK_UART3,
315 }, { 297 }, {
316 .name = "watchdog", 298 .name = "watchdog",
317 .id = -1,
318 .parent = &clk_p, 299 .parent = &clk_p,
319 .ctrlbit = S3C_CLKCON_PCLK_WDT, 300 .ctrlbit = S3C_CLKCON_PCLK_WDT,
320 }, { 301 }, {
321 .name = "ac97", 302 .name = "ac97",
322 .id = -1,
323 .parent = &clk_p, 303 .parent = &clk_p,
324 .ctrlbit = S3C_CLKCON_PCLK_AC97, 304 .ctrlbit = S3C_CLKCON_PCLK_AC97,
325 }, { 305 }, {
326 .name = "cfcon", 306 .name = "cfcon",
327 .id = -1,
328 .parent = &clk_h, 307 .parent = &clk_h,
329 .enable = s3c64xx_hclk_ctrl, 308 .enable = s3c64xx_hclk_ctrl,
330 .ctrlbit = S3C_CLKCON_HCLK_IHOST, 309 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
@@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
334 313
335static struct clk clk_fout_apll = { 314static struct clk clk_fout_apll = {
336 .name = "fout_apll", 315 .name = "fout_apll",
337 .id = -1,
338}; 316};
339 317
340static struct clk *clk_src_apll_list[] = { 318static struct clk *clk_src_apll_list[] = {
@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
350static struct clksrc_clk clk_mout_apll = { 328static struct clksrc_clk clk_mout_apll = {
351 .clk = { 329 .clk = {
352 .name = "mout_apll", 330 .name = "mout_apll",
353 .id = -1,
354 }, 331 },
355 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, 332 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
356 .sources = &clk_src_apll, 333 .sources = &clk_src_apll,
@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
369static struct clksrc_clk clk_mout_epll = { 346static struct clksrc_clk clk_mout_epll = {
370 .clk = { 347 .clk = {
371 .name = "mout_epll", 348 .name = "mout_epll",
372 .id = -1,
373 }, 349 },
374 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, 350 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
375 .sources = &clk_src_epll, 351 .sources = &clk_src_epll,
@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
388static struct clksrc_clk clk_mout_mpll = { 364static struct clksrc_clk clk_mout_mpll = {
389 .clk = { 365 .clk = {
390 .name = "mout_mpll", 366 .name = "mout_mpll",
391 .id = -1,
392 }, 367 },
393 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, 368 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
394 .sources = &clk_src_mpll, 369 .sources = &clk_src_mpll,
@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
446 421
447static struct clk clk_arm = { 422static struct clk clk_arm = {
448 .name = "armclk", 423 .name = "armclk",
449 .id = -1,
450 .parent = &clk_mout_apll.clk, 424 .parent = &clk_mout_apll.clk,
451 .ops = &(struct clk_ops) { 425 .ops = &(struct clk_ops) {
452 .get_rate = s3c64xx_clk_arm_get_rate, 426 .get_rate = s3c64xx_clk_arm_get_rate,
@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
473 447
474static struct clk clk_dout_mpll = { 448static struct clk clk_dout_mpll = {
475 .name = "dout_mpll", 449 .name = "dout_mpll",
476 .id = -1,
477 .parent = &clk_mout_mpll.clk, 450 .parent = &clk_mout_mpll.clk,
478 .ops = &clk_dout_ops, 451 .ops = &clk_dout_ops,
479}; 452};
@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
540 513
541static struct clk clk_iis_cd0 = { 514static struct clk clk_iis_cd0 = {
542 .name = "iis_cdclk0", 515 .name = "iis_cdclk0",
543 .id = -1,
544}; 516};
545 517
546static struct clk clk_iis_cd1 = { 518static struct clk clk_iis_cd1 = {
547 .name = "iis_cdclk1", 519 .name = "iis_cdclk1",
548 .id = -1,
549}; 520};
550 521
551static struct clk clk_iisv4_cd = { 522static struct clk clk_iisv4_cd = {
552 .name = "iis_cdclk_v4", 523 .name = "iis_cdclk_v4",
553 .id = -1,
554}; 524};
555 525
556static struct clk clk_pcm_cd = { 526static struct clk clk_pcm_cd = {
557 .name = "pcm_cdclk", 527 .name = "pcm_cdclk",
558 .id = -1,
559}; 528};
560 529
561static struct clk *clkset_audio0_list[] = { 530static struct clk *clkset_audio0_list[] = {
@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
610 { 579 {
611 .clk = { 580 .clk = {
612 .name = "mmc_bus", 581 .name = "mmc_bus",
613 .id = 0, 582 .devname = "s3c-sdhci.0",
614 .ctrlbit = S3C_CLKCON_SCLK_MMC0, 583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
615 .enable = s3c64xx_sclk_ctrl, 584 .enable = s3c64xx_sclk_ctrl,
616 }, 585 },
@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
620 }, { 589 }, {
621 .clk = { 590 .clk = {
622 .name = "mmc_bus", 591 .name = "mmc_bus",
623 .id = 1, 592 .devname = "s3c-sdhci.1",
624 .ctrlbit = S3C_CLKCON_SCLK_MMC1, 593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
625 .enable = s3c64xx_sclk_ctrl, 594 .enable = s3c64xx_sclk_ctrl,
626 }, 595 },
@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
630 }, { 599 }, {
631 .clk = { 600 .clk = {
632 .name = "mmc_bus", 601 .name = "mmc_bus",
633 .id = 2, 602 .devname = "s3c-sdhci.2",
634 .ctrlbit = S3C_CLKCON_SCLK_MMC2, 603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
635 .enable = s3c64xx_sclk_ctrl, 604 .enable = s3c64xx_sclk_ctrl,
636 }, 605 },
@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
640 }, { 609 }, {
641 .clk = { 610 .clk = {
642 .name = "usb-bus-host", 611 .name = "usb-bus-host",
643 .id = -1,
644 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 612 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
645 .enable = s3c64xx_sclk_ctrl, 613 .enable = s3c64xx_sclk_ctrl,
646 }, 614 },
@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
650 }, { 618 }, {
651 .clk = { 619 .clk = {
652 .name = "uclk1", 620 .name = "uclk1",
653 .id = -1,
654 .ctrlbit = S3C_CLKCON_SCLK_UART, 621 .ctrlbit = S3C_CLKCON_SCLK_UART,
655 .enable = s3c64xx_sclk_ctrl, 622 .enable = s3c64xx_sclk_ctrl,
656 }, 623 },
@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
661/* Where does UCLK0 come from? */ 628/* Where does UCLK0 come from? */
662 .clk = { 629 .clk = {
663 .name = "spi-bus", 630 .name = "spi-bus",
664 .id = 0, 631 .devname = "s3c64xx-spi.0",
665 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 632 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
666 .enable = s3c64xx_sclk_ctrl, 633 .enable = s3c64xx_sclk_ctrl,
667 }, 634 },
@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
671 }, { 638 }, {
672 .clk = { 639 .clk = {
673 .name = "spi-bus", 640 .name = "spi-bus",
674 .id = 1, 641 .devname = "s3c64xx-spi.1",
675 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
676 .enable = s3c64xx_sclk_ctrl, 642 .enable = s3c64xx_sclk_ctrl,
677 }, 643 },
678 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, 644 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
681 }, { 647 }, {
682 .clk = { 648 .clk = {
683 .name = "audio-bus", 649 .name = "audio-bus",
684 .id = 0, 650 .devname = "samsung-i2s.0",
685 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 651 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
686 .enable = s3c64xx_sclk_ctrl, 652 .enable = s3c64xx_sclk_ctrl,
687 }, 653 },
@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
691 }, { 657 }, {
692 .clk = { 658 .clk = {
693 .name = "audio-bus", 659 .name = "audio-bus",
694 .id = 1, 660 .devname = "samsung-i2s.1",
695 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, 661 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
696 .enable = s3c64xx_sclk_ctrl, 662 .enable = s3c64xx_sclk_ctrl,
697 }, 663 },
@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
701 }, { 667 }, {
702 .clk = { 668 .clk = {
703 .name = "audio-bus", 669 .name = "audio-bus",
704 .id = 2, 670 .devname = "samsung-i2s.2",
705 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, 671 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
706 .enable = s3c64xx_sclk_ctrl, 672 .enable = s3c64xx_sclk_ctrl,
707 }, 673 },
@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
711 }, { 677 }, {
712 .clk = { 678 .clk = {
713 .name = "irda-bus", 679 .name = "irda-bus",
714 .id = 0,
715 .ctrlbit = S3C_CLKCON_SCLK_IRDA, 680 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
716 .enable = s3c64xx_sclk_ctrl, 681 .enable = s3c64xx_sclk_ctrl,
717 }, 682 },
@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
721 }, { 686 }, {
722 .clk = { 687 .clk = {
723 .name = "camera", 688 .name = "camera",
724 .id = -1,
725 .ctrlbit = S3C_CLKCON_SCLK_CAM, 689 .ctrlbit = S3C_CLKCON_SCLK_CAM,
726 .enable = s3c64xx_sclk_ctrl, 690 .enable = s3c64xx_sclk_ctrl,
727 }, 691 },
diff --git a/arch/arm/mach-s3c64xx/cpufreq.c b/arch/arm/mach-s3c64xx/cpufreq.c
deleted file mode 100644
index 4375b97588b8..000000000000
--- a/arch/arm/mach-s3c64xx/cpufreq.c
+++ /dev/null
@@ -1,270 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/cpufreq.c
2 *
3 * Copyright 2009 Wolfson Microelectronics plc
4 *
5 * S3C64xx CPUfreq Support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/init.h>
15#include <linux/cpufreq.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/regulator/consumer.h>
19
20static struct clk *armclk;
21static struct regulator *vddarm;
22static unsigned long regulator_latency;
23
24#ifdef CONFIG_CPU_S3C6410
25struct s3c64xx_dvfs {
26 unsigned int vddarm_min;
27 unsigned int vddarm_max;
28};
29
30static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
31 [0] = { 1000000, 1150000 },
32 [1] = { 1050000, 1150000 },
33 [2] = { 1100000, 1150000 },
34 [3] = { 1200000, 1350000 },
35};
36
37static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
38 { 0, 66000 },
39 { 0, 133000 },
40 { 1, 222000 },
41 { 1, 266000 },
42 { 2, 333000 },
43 { 2, 400000 },
44 { 2, 532000 },
45 { 2, 533000 },
46 { 3, 667000 },
47 { 0, CPUFREQ_TABLE_END },
48};
49#endif
50
51static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
52{
53 if (policy->cpu != 0)
54 return -EINVAL;
55
56 return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
57}
58
59static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
60{
61 if (cpu != 0)
62 return 0;
63
64 return clk_get_rate(armclk) / 1000;
65}
66
67static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
68 unsigned int target_freq,
69 unsigned int relation)
70{
71 int ret;
72 unsigned int i;
73 struct cpufreq_freqs freqs;
74 struct s3c64xx_dvfs *dvfs;
75
76 ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
77 target_freq, relation, &i);
78 if (ret != 0)
79 return ret;
80
81 freqs.cpu = 0;
82 freqs.old = clk_get_rate(armclk) / 1000;
83 freqs.new = s3c64xx_freq_table[i].frequency;
84 freqs.flags = 0;
85 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
86
87 if (freqs.old == freqs.new)
88 return 0;
89
90 pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
91
92 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93
94#ifdef CONFIG_REGULATOR
95 if (vddarm && freqs.new > freqs.old) {
96 ret = regulator_set_voltage(vddarm,
97 dvfs->vddarm_min,
98 dvfs->vddarm_max);
99 if (ret != 0) {
100 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
101 freqs.new, ret);
102 goto err;
103 }
104 }
105#endif
106
107 ret = clk_set_rate(armclk, freqs.new * 1000);
108 if (ret < 0) {
109 pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
110 freqs.new, ret);
111 goto err;
112 }
113
114#ifdef CONFIG_REGULATOR
115 if (vddarm && freqs.new < freqs.old) {
116 ret = regulator_set_voltage(vddarm,
117 dvfs->vddarm_min,
118 dvfs->vddarm_max);
119 if (ret != 0) {
120 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
121 freqs.new, ret);
122 goto err_clk;
123 }
124 }
125#endif
126
127 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
128
129 pr_debug("cpufreq: Set actual frequency %lukHz\n",
130 clk_get_rate(armclk) / 1000);
131
132 return 0;
133
134err_clk:
135 if (clk_set_rate(armclk, freqs.old * 1000) < 0)
136 pr_err("Failed to restore original clock rate\n");
137err:
138 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
139
140 return ret;
141}
142
143#ifdef CONFIG_REGULATOR
144static void __init s3c64xx_cpufreq_config_regulator(void)
145{
146 int count, v, i, found;
147 struct cpufreq_frequency_table *freq;
148 struct s3c64xx_dvfs *dvfs;
149
150 count = regulator_count_voltages(vddarm);
151 if (count < 0) {
152 pr_err("cpufreq: Unable to check supported voltages\n");
153 }
154
155 freq = s3c64xx_freq_table;
156 while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
157 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
158 continue;
159
160 dvfs = &s3c64xx_dvfs_table[freq->index];
161 found = 0;
162
163 for (i = 0; i < count; i++) {
164 v = regulator_list_voltage(vddarm, i);
165 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
166 found = 1;
167 }
168
169 if (!found) {
170 pr_debug("cpufreq: %dkHz unsupported by regulator\n",
171 freq->frequency);
172 freq->frequency = CPUFREQ_ENTRY_INVALID;
173 }
174
175 freq++;
176 }
177
178 /* Guess based on having to do an I2C/SPI write; in future we
179 * will be able to query the regulator performance here. */
180 regulator_latency = 1 * 1000 * 1000;
181}
182#endif
183
184static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
185{
186 int ret;
187 struct cpufreq_frequency_table *freq;
188
189 if (policy->cpu != 0)
190 return -EINVAL;
191
192 if (s3c64xx_freq_table == NULL) {
193 pr_err("cpufreq: No frequency information for this CPU\n");
194 return -ENODEV;
195 }
196
197 armclk = clk_get(NULL, "armclk");
198 if (IS_ERR(armclk)) {
199 pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
200 PTR_ERR(armclk));
201 return PTR_ERR(armclk);
202 }
203
204#ifdef CONFIG_REGULATOR
205 vddarm = regulator_get(NULL, "vddarm");
206 if (IS_ERR(vddarm)) {
207 ret = PTR_ERR(vddarm);
208 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
209 pr_err("cpufreq: Only frequency scaling available\n");
210 vddarm = NULL;
211 } else {
212 s3c64xx_cpufreq_config_regulator();
213 }
214#endif
215
216 freq = s3c64xx_freq_table;
217 while (freq->frequency != CPUFREQ_TABLE_END) {
218 unsigned long r;
219
220 /* Check for frequencies we can generate */
221 r = clk_round_rate(armclk, freq->frequency * 1000);
222 r /= 1000;
223 if (r != freq->frequency) {
224 pr_debug("cpufreq: %dkHz unsupported by clock\n",
225 freq->frequency);
226 freq->frequency = CPUFREQ_ENTRY_INVALID;
227 }
228
229 /* If we have no regulator then assume startup
230 * frequency is the maximum we can support. */
231 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
232 freq->frequency = CPUFREQ_ENTRY_INVALID;
233
234 freq++;
235 }
236
237 policy->cur = clk_get_rate(armclk) / 1000;
238
239 /* Datasheet says PLL stabalisation time (if we were to use
240 * the PLLs, which we don't currently) is ~300us worst case,
241 * but add some fudge.
242 */
243 policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
244
245 ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
246 if (ret != 0) {
247 pr_err("cpufreq: Failed to configure frequency table: %d\n",
248 ret);
249 regulator_put(vddarm);
250 clk_put(armclk);
251 }
252
253 return ret;
254}
255
256static struct cpufreq_driver s3c64xx_cpufreq_driver = {
257 .owner = THIS_MODULE,
258 .flags = 0,
259 .verify = s3c64xx_cpufreq_verify_speed,
260 .target = s3c64xx_cpufreq_set_target,
261 .get = s3c64xx_cpufreq_get_speed,
262 .init = s3c64xx_cpufreq_driver_init,
263 .name = "s3c",
264};
265
266static int __init s3c64xx_cpufreq_init(void)
267{
268 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
269}
270module_init(s3c64xx_cpufreq_init);
diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c
index 92ffd5bac104..999f9e17a1e4 100644
--- a/arch/arm/mach-s3c64xx/dev-onenand1.c
+++ b/arch/arm/mach-s3c64xx/dev-onenand1.c
@@ -19,6 +19,8 @@
19#include <mach/irqs.h> 19#include <mach/irqs.h>
20#include <mach/map.h> 20#include <mach/map.h>
21 21
22#include <plat/devs.h>
23
22static struct resource s3c64xx_onenand1_resources[] = { 24static struct resource s3c64xx_onenand1_resources[] = {
23 [0] = { 25 [0] = {
24 .start = S3C64XX_PA_ONENAND1, 26 .start = S3C64XX_PA_ONENAND1,
@@ -46,10 +48,6 @@ struct platform_device s3c64xx_device_onenand1 = {
46 48
47void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) 49void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
48{ 50{
49 struct onenand_platform_data *pd; 51 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
50 52 &s3c64xx_device_onenand1);
51 pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
52 if (!pd)
53 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
54 s3c64xx_device_onenand1.dev.platform_data = pd;
55} 53}
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 8e2df26cf14a..c026f67a80de 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -198,7 +198,9 @@
198 * interrupt controllers). */ 198 * interrupt controllers). */
199#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) 199#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
200 200
201#ifdef CONFIG_SMDK6410_WM1190_EV1 201#ifdef CONFIG_MACH_WLF_CRAGG_6410
202#define IRQ_BOARD_NR 128
203#elif defined(CONFIG_SMDK6410_WM1190_EV1)
202#define IRQ_BOARD_NR 64 204#define IRQ_BOARD_NR 64
203#elif defined(CONFIG_SMDK6410_WM1192_EV1) 205#elif defined(CONFIG_SMDK6410_WM1192_EV1)
204#define IRQ_BOARD_NR 64 206#define IRQ_BOARD_NR 64
@@ -215,6 +217,7 @@
215/* Compatibility */ 217/* Compatibility */
216 218
217#define IRQ_ONENAND IRQ_ONENAND0 219#define IRQ_ONENAND IRQ_ONENAND0
220#define IRQ_I2S0 IRQ_S3C6410_IIS
218 221
219#endif /* __ASM_MACH_S3C64XX_IRQS_H */ 222#endif /* __ASM_MACH_S3C64XX_IRQS_H */
220 223
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 1e9f20f0bb7b..38659bebe4b1 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
53 * the IRQ wake controls depending on the CPU we are running on */ 53 * the IRQ wake controls depending on the CPU we are running on */
54 54
55#define s3c_irqwake_eintallow ((1 << 28) - 1) 55#define s3c_irqwake_eintallow ((1 << 28) - 1)
56#define s3c_irqwake_intallow (0) 56#define s3c_irqwake_intallow (~0)
57 57
58static inline void s3c_pm_arch_update_uart(void __iomem *regs, 58static inline void s3c_pm_arch_update_uart(void __iomem *regs,
59 struct pm_uart_save *save) 59 struct pm_uart_save *save)
@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
96 save->ucon = new_ucon; 96 save->ucon = new_ucon;
97 } 97 }
98} 98}
99
100static inline void s3c_pm_restored_gpios(void)
101{
102 /* ensure sleep mode has been cleared from the system */
103
104 __raw_writel(0, S3C64XX_SLPEN);
105}
106
107static inline void s3c_pm_saved_gpios(void)
108{
109 /* turn on the sleep mode and keep it there, as it seems that during
110 * suspend the xCON registers get re-set and thus you can end up with
111 * problems between going to sleep and resuming.
112 */
113
114 __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
115}
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
deleted file mode 100644
index a06ee0af9a4b..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2009 Samsung Electronics Co.
5 *
6 * Pawel Osciak <p.osciak@samsung.com>
7 * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
8 *
9 * Framebuffer register definitions for Samsung S3C64xx.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __ASM_ARCH_MACH_REGS_FB_H
17#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
18
19#include <plat/regs-fb-v4.h>
20
21#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 97660c8141ae..75d9a0e49193 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
48 }, 48 },
49}; 49};
50 50
51/* setup the sources the vic should advertise resume for, even though it
52 * is not doing the wake (set_irq_wake needs to be valid) */
53#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
54#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
55 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
56 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
57 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
58 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
51 59
52void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) 60void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
53{ 61{
54 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 62 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
55 63
56 /* initialise the pair of VICs */ 64 /* initialise the pair of VICs */
57 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); 65 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
58 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); 66 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
59 67
60 /* add the timer sub-irqs */ 68 /* add the timer sub-irqs */
61 s3c_init_vic_timer_irq(5, IRQ_TIMER0); 69 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index a53cf149476e..cb8864327ac4 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -35,7 +35,6 @@
35#include <asm/mach/irq.h> 35#include <asm/mach/irq.h>
36 36
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/regs-fb.h>
39#include <mach/map.h> 38#include <mach/map.h>
40 39
41#include <asm/irq.h> 40#include <asm/irq.h>
@@ -44,6 +43,7 @@
44#include <plat/regs-serial.h> 43#include <plat/regs-serial.h>
45#include <plat/iic.h> 44#include <plat/iic.h>
46#include <plat/fb.h> 45#include <plat/fb.h>
46#include <plat/regs-fb-v4.h>
47 47
48#include <mach/s3c6410.h> 48#include <mach/s3c6410.h>
49#include <plat/clock.h> 49#include <plat/clock.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
new file mode 100644
index 000000000000..9026249233ad
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -0,0 +1,774 @@
1/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * Copyright 2011 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/serial_core.h>
17#include <linux/platform_device.h>
18#include <linux/fb.h>
19#include <linux/io.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/regulator/machine.h>
24#include <linux/regulator/fixed.h>
25#include <linux/pwm_backlight.h>
26#include <linux/dm9000.h>
27#include <linux/gpio_keys.h>
28#include <linux/basic_mmio_gpio.h>
29#include <linux/spi/spi.h>
30
31#include <linux/i2c/pca953x.h>
32
33#include <video/platform_lcd.h>
34
35#include <linux/mfd/wm831x/core.h>
36#include <linux/mfd/wm831x/pdata.h>
37#include <linux/mfd/wm831x/irq.h>
38#include <linux/mfd/wm831x/gpio.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach-types.h>
42
43#include <mach/hardware.h>
44#include <mach/map.h>
45
46#include <mach/s3c6410.h>
47#include <mach/regs-sys.h>
48#include <mach/regs-gpio.h>
49#include <mach/regs-modem.h>
50
51#include <mach/regs-gpio-memport.h>
52
53#include <plat/regs-serial.h>
54#include <plat/regs-fb-v4.h>
55#include <plat/fb.h>
56#include <plat/sdhci.h>
57#include <plat/gpio-cfg.h>
58#include <plat/s3c64xx-spi.h>
59
60#include <plat/keypad.h>
61#include <plat/clock.h>
62#include <plat/devs.h>
63#include <plat/cpu.h>
64#include <plat/adc.h>
65#include <plat/iic.h>
66#include <plat/pm.h>
67
68#include <sound/wm8915.h>
69#include <sound/wm8962.h>
70#include <sound/wm9081.h>
71
72#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
73#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
74
75#define PCA935X_GPIO_BASE GPIO_BOARD_START
76#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
77#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
78
79/* serial port setup */
80
81#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
82#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
83#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
84
85static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
86 [0] = {
87 .hwport = 0,
88 .flags = 0,
89 .ucon = UCON,
90 .ulcon = ULCON,
91 .ufcon = UFCON,
92 },
93 [1] = {
94 .hwport = 1,
95 .flags = 0,
96 .ucon = UCON,
97 .ulcon = ULCON,
98 .ufcon = UFCON,
99 },
100 [2] = {
101 .hwport = 2,
102 .flags = 0,
103 .ucon = UCON,
104 .ulcon = ULCON,
105 .ufcon = UFCON,
106 },
107 [3] = {
108 .hwport = 3,
109 .flags = 0,
110 .ucon = UCON,
111 .ulcon = ULCON,
112 .ufcon = UFCON,
113 },
114};
115
116static struct platform_pwm_backlight_data crag6410_backlight_data = {
117 .pwm_id = 0,
118 .max_brightness = 1000,
119 .dft_brightness = 600,
120 .pwm_period_ns = 100000, /* about 1kHz */
121};
122
123static struct platform_device crag6410_backlight_device = {
124 .name = "pwm-backlight",
125 .id = -1,
126 .dev = {
127 .parent = &s3c_device_timer[0].dev,
128 .platform_data = &crag6410_backlight_data,
129 },
130};
131
132static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
133{
134 pr_debug("%s: setting power %d\n", __func__, power);
135
136 if (power) {
137 gpio_set_value(S3C64XX_GPB(0), 1);
138 msleep(1);
139 s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
140 } else {
141 gpio_direction_output(S3C64XX_GPF(14), 0);
142 gpio_set_value(S3C64XX_GPB(0), 0);
143 }
144}
145
146static struct platform_device crag6410_lcd_powerdev = {
147 .name = "platform-lcd",
148 .id = -1,
149 .dev.parent = &s3c_device_fb.dev,
150 .dev.platform_data = &(struct plat_lcd_data) {
151 .set_power = crag6410_lcd_power_set,
152 },
153};
154
155/* 640x480 URT */
156static struct s3c_fb_pd_win crag6410_fb_win0 = {
157 /* this is to ensure we use win0 */
158 .win_mode = {
159 .left_margin = 150,
160 .right_margin = 80,
161 .upper_margin = 40,
162 .lower_margin = 5,
163 .hsync_len = 40,
164 .vsync_len = 5,
165 .xres = 640,
166 .yres = 480,
167 },
168 .max_bpp = 32,
169 .default_bpp = 16,
170 .virtual_y = 480 * 2,
171 .virtual_x = 640,
172};
173
174/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
175static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
176 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
177 .win[0] = &crag6410_fb_win0,
178 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
179 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
180};
181
182/* 2x6 keypad */
183
184static uint32_t crag6410_keymap[] __initdata = {
185 /* KEY(row, col, keycode) */
186 KEY(0, 0, KEY_VOLUMEUP),
187 KEY(0, 1, KEY_HOME),
188 KEY(0, 2, KEY_VOLUMEDOWN),
189 KEY(0, 3, KEY_HELP),
190 KEY(0, 4, KEY_MENU),
191 KEY(0, 5, KEY_MEDIA),
192 KEY(1, 0, 232),
193 KEY(1, 1, KEY_DOWN),
194 KEY(1, 2, KEY_LEFT),
195 KEY(1, 3, KEY_UP),
196 KEY(1, 4, KEY_RIGHT),
197 KEY(1, 5, KEY_CAMERA),
198};
199
200static struct matrix_keymap_data crag6410_keymap_data __initdata = {
201 .keymap = crag6410_keymap,
202 .keymap_size = ARRAY_SIZE(crag6410_keymap),
203};
204
205static struct samsung_keypad_platdata crag6410_keypad_data __initdata = {
206 .keymap_data = &crag6410_keymap_data,
207 .rows = 2,
208 .cols = 6,
209};
210
211static struct gpio_keys_button crag6410_gpio_keys[] = {
212 [0] = {
213 .code = KEY_SUSPEND,
214 .gpio = S3C64XX_GPL(10), /* EINT 18 */
215 .type = EV_KEY,
216 .wakeup = 1,
217 .active_low = 1,
218 },
219 [1] = {
220 .code = SW_FRONT_PROXIMITY,
221 .gpio = S3C64XX_GPN(11), /* EINT 11 */
222 .type = EV_SW,
223 },
224};
225
226static struct gpio_keys_platform_data crag6410_gpio_keydata = {
227 .buttons = crag6410_gpio_keys,
228 .nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
229};
230
231static struct platform_device crag6410_gpio_keydev = {
232 .name = "gpio-keys",
233 .id = 0,
234 .dev.platform_data = &crag6410_gpio_keydata,
235};
236
237static struct resource crag6410_dm9k_resource[] = {
238 [0] = {
239 .start = S3C64XX_PA_XM0CSN5,
240 .end = S3C64XX_PA_XM0CSN5 + 1,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = S3C64XX_PA_XM0CSN5 + (1 << 8),
245 .end = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [2] = {
249 .start = S3C_EINT(17),
250 .end = S3C_EINT(17),
251 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
252 },
253};
254
255static struct dm9000_plat_data mini6410_dm9k_pdata = {
256 .flags = DM9000_PLATF_16BITONLY,
257};
258
259static struct platform_device crag6410_dm9k_device = {
260 .name = "dm9000",
261 .id = -1,
262 .num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
263 .resource = crag6410_dm9k_resource,
264 .dev.platform_data = &mini6410_dm9k_pdata,
265};
266
267static struct resource crag6410_mmgpio_resource[] = {
268 [0] = {
269 .start = S3C64XX_PA_XM0CSN4 + 1,
270 .end = S3C64XX_PA_XM0CSN4 + 1,
271 .flags = IORESOURCE_MEM,
272 },
273};
274
275static struct platform_device crag6410_mmgpio = {
276 .name = "basic-mmio-gpio",
277 .id = -1,
278 .resource = crag6410_mmgpio_resource,
279 .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
280 .dev.platform_data = &(struct bgpio_pdata) {
281 .base = -1,
282 },
283};
284
285static struct platform_device speyside_device = {
286 .name = "speyside",
287 .id = -1,
288};
289
290static struct platform_device speyside_wm8962_device = {
291 .name = "speyside-wm8962",
292 .id = -1,
293};
294
295static struct regulator_consumer_supply wallvdd_consumers[] = {
296 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
297 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
298};
299
300static struct regulator_init_data wallvdd_data = {
301 .constraints = {
302 .always_on = 1,
303 },
304 .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
305 .consumer_supplies = wallvdd_consumers,
306};
307
308static struct fixed_voltage_config wallvdd_pdata = {
309 .supply_name = "WALLVDD",
310 .microvolts = 5000000,
311 .init_data = &wallvdd_data,
312 .gpio = -EINVAL,
313};
314
315static struct platform_device wallvdd_device = {
316 .name = "reg-fixed-voltage",
317 .id = -1,
318 .dev = {
319 .platform_data = &wallvdd_pdata,
320 },
321};
322
323static struct platform_device *crag6410_devices[] __initdata = {
324 &s3c_device_hsmmc0,
325 &s3c_device_hsmmc1,
326 &s3c_device_hsmmc2,
327 &s3c_device_i2c0,
328 &s3c_device_i2c1,
329 &s3c_device_fb,
330 &s3c_device_ohci,
331 &s3c_device_usb_hsotg,
332 &s3c_device_adc,
333 &s3c_device_rtc,
334 &s3c_device_ts,
335 &s3c_device_timer[0],
336 &s3c64xx_device_iis0,
337 &s3c64xx_device_iis1,
338 &samsung_asoc_dma,
339 &samsung_device_keypad,
340 &crag6410_gpio_keydev,
341 &crag6410_dm9k_device,
342 &s3c64xx_device_spi0,
343 &crag6410_mmgpio,
344 &crag6410_lcd_powerdev,
345 &crag6410_backlight_device,
346 &speyside_device,
347 &speyside_wm8962_device,
348 &wallvdd_device,
349};
350
351static struct pca953x_platform_data crag6410_pca_data = {
352 .gpio_base = PCA935X_GPIO_BASE,
353 .irq_base = 0,
354};
355
356static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
357 REGULATOR_SUPPLY("vddarm", NULL),
358};
359
360static struct regulator_init_data vddarm __initdata = {
361 .constraints = {
362 .name = "VDDARM",
363 .min_uV = 1000000,
364 .max_uV = 1300000,
365 .always_on = 1,
366 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
367 },
368 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
369 .consumer_supplies = vddarm_consumers,
370 .supply_regulator = "WALLVDD",
371};
372
373static struct regulator_init_data vddint __initdata = {
374 .constraints = {
375 .name = "VDDINT",
376 .min_uV = 1000000,
377 .max_uV = 1200000,
378 .always_on = 1,
379 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
380 },
381};
382
383static struct regulator_init_data vddmem __initdata = {
384 .constraints = {
385 .name = "VDDMEM",
386 .always_on = 1,
387 },
388};
389
390static struct regulator_init_data vddsys __initdata = {
391 .constraints = {
392 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
393 .always_on = 1,
394 },
395};
396
397static struct regulator_consumer_supply vddmmc_consumers[] __initdata = {
398 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
399 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
400 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
401};
402
403static struct regulator_init_data vddmmc __initdata = {
404 .constraints = {
405 .name = "VDDMMC,UH",
406 .always_on = 1,
407 },
408 .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
409 .consumer_supplies = vddmmc_consumers,
410 .supply_regulator = "WALLVDD",
411};
412
413static struct regulator_init_data vddotgi __initdata = {
414 .constraints = {
415 .name = "VDDOTGi",
416 .always_on = 1,
417 },
418 .supply_regulator = "WALLVDD",
419};
420
421static struct regulator_init_data vddotg __initdata = {
422 .constraints = {
423 .name = "VDDOTG",
424 .always_on = 1,
425 },
426 .supply_regulator = "WALLVDD",
427};
428
429static struct regulator_init_data vddhi __initdata = {
430 .constraints = {
431 .name = "VDDHI",
432 .always_on = 1,
433 },
434 .supply_regulator = "WALLVDD",
435};
436
437static struct regulator_init_data vddadc __initdata = {
438 .constraints = {
439 .name = "VDDADC,VDDDAC",
440 .always_on = 1,
441 },
442 .supply_regulator = "WALLVDD",
443};
444
445static struct regulator_init_data vddmem0 __initdata = {
446 .constraints = {
447 .name = "VDDMEM0",
448 .always_on = 1,
449 },
450 .supply_regulator = "WALLVDD",
451};
452
453static struct regulator_init_data vddpll __initdata = {
454 .constraints = {
455 .name = "VDDPLL",
456 .always_on = 1,
457 },
458 .supply_regulator = "WALLVDD",
459};
460
461static struct regulator_init_data vddlcd __initdata = {
462 .constraints = {
463 .name = "VDDLCD",
464 .always_on = 1,
465 },
466 .supply_regulator = "WALLVDD",
467};
468
469static struct regulator_init_data vddalive __initdata = {
470 .constraints = {
471 .name = "VDDALIVE",
472 .always_on = 1,
473 },
474 .supply_regulator = "WALLVDD",
475};
476
477static struct wm831x_backup_pdata banff_backup_pdata __initdata = {
478 .charger_enable = 1,
479 .vlim = 2500, /* mV */
480 .ilim = 200, /* uA */
481};
482
483static struct wm831x_status_pdata banff_red_led __initdata = {
484 .name = "banff:red:",
485 .default_src = WM831X_STATUS_MANUAL,
486};
487
488static struct wm831x_status_pdata banff_green_led __initdata = {
489 .name = "banff:green:",
490 .default_src = WM831X_STATUS_MANUAL,
491};
492
493static struct wm831x_touch_pdata touch_pdata __initdata = {
494 .data_irq = S3C_EINT(26),
495 .pd_irq = S3C_EINT(27),
496};
497
498static struct wm831x_pdata crag_pmic_pdata __initdata = {
499 .wm831x_num = 1,
500 .irq_base = BANFF_PMIC_IRQ_BASE,
501 .gpio_base = GPIO_BOARD_START + 8,
502
503 .backup = &banff_backup_pdata,
504
505 .gpio_defaults = {
506 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
507 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
508 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
509 [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
510 },
511
512 .dcdc = {
513 &vddarm, /* DCDC1 */
514 &vddint, /* DCDC2 */
515 &vddmem, /* DCDC3 */
516 },
517
518 .ldo = {
519 &vddsys, /* LDO1 */
520 &vddmmc, /* LDO2 */
521 NULL, /* LDO3 */
522 &vddotgi, /* LDO4 */
523 &vddotg, /* LDO5 */
524 &vddhi, /* LDO6 */
525 &vddadc, /* LDO7 */
526 &vddmem0, /* LDO8 */
527 &vddpll, /* LDO9 */
528 &vddlcd, /* LDO10 */
529 &vddalive, /* LDO11 */
530 },
531
532 .status = {
533 &banff_green_led,
534 &banff_red_led,
535 },
536
537 .touch = &touch_pdata,
538};
539
540static struct i2c_board_info i2c_devs0[] __initdata = {
541 { I2C_BOARD_INFO("24c08", 0x50), },
542 { I2C_BOARD_INFO("tca6408", 0x20),
543 .platform_data = &crag6410_pca_data,
544 },
545 { I2C_BOARD_INFO("wm8312", 0x34),
546 .platform_data = &crag_pmic_pdata,
547 .irq = S3C_EINT(23),
548 },
549};
550
551static struct s3c2410_platform_i2c i2c0_pdata = {
552 .frequency = 400000,
553};
554
555static struct regulator_init_data pvdd_1v2 __initdata = {
556 .constraints = {
557 .name = "PVDD_1V2",
558 .always_on = 1,
559 },
560};
561
562static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
563 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
564 REGULATOR_SUPPLY("DBVDD", "1-001a"),
565 REGULATOR_SUPPLY("CPVDD", "1-001a"),
566 REGULATOR_SUPPLY("AVDD2", "1-001a"),
567 REGULATOR_SUPPLY("DCVDD", "1-001a"),
568 REGULATOR_SUPPLY("AVDD", "1-001a"),
569};
570
571static struct regulator_init_data pvdd_1v8 __initdata = {
572 .constraints = {
573 .name = "PVDD_1V8",
574 .always_on = 1,
575 },
576
577 .consumer_supplies = pvdd_1v8_consumers,
578 .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
579};
580
581static struct regulator_consumer_supply pvdd_3v3_consumers[] __initdata = {
582 REGULATOR_SUPPLY("MICVDD", "1-001a"),
583 REGULATOR_SUPPLY("AVDD1", "1-001a"),
584};
585
586static struct regulator_init_data pvdd_3v3 __initdata = {
587 .constraints = {
588 .name = "PVDD_3V3",
589 .always_on = 1,
590 },
591
592 .consumer_supplies = pvdd_3v3_consumers,
593 .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
594};
595
596static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
597 .wm831x_num = 2,
598 .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
599 .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
600
601 .gpio_defaults = {
602 /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
603 [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
604 [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
605 [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
606 },
607
608 .dcdc = {
609 &pvdd_1v2, /* DCDC1 */
610 &pvdd_1v8, /* DCDC2 */
611 &pvdd_3v3, /* DCDC3 */
612 },
613
614 .disable_touch = true,
615};
616
617static struct wm8915_retune_mobile_config wm8915_retune[] = {
618 {
619 .name = "Sub LPF",
620 .rate = 48000,
621 .regs = {
622 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
623 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
624 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
625 },
626 },
627 {
628 .name = "Sub HPF",
629 .rate = 48000,
630 .regs = {
631 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
632 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
633 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
634 },
635 },
636};
637
638static struct wm8915_pdata wm8915_pdata __initdata = {
639 .ldo_ena = S3C64XX_GPN(7),
640 .gpio_base = CODEC_GPIO_BASE,
641 .micdet_def = 1,
642 .inl_mode = WM8915_DIFFERRENTIAL_1,
643 .inr_mode = WM8915_DIFFERRENTIAL_1,
644
645 .irq_flags = IRQF_TRIGGER_RISING,
646
647 .gpio_default = {
648 0x8001, /* GPIO1 == ADCLRCLK1 */
649 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
650 0x0141, /* GPIO3 == HP_SEL */
651 0x0002, /* GPIO4 == IRQ */
652 0x020e, /* GPIO5 == CLKOUT */
653 },
654
655 .retune_mobile_cfgs = wm8915_retune,
656 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8915_retune),
657};
658
659static struct wm8962_pdata wm8962_pdata __initdata = {
660 .gpio_init = {
661 0,
662 WM8962_GPIO_FN_OPCLK,
663 WM8962_GPIO_FN_DMICCLK,
664 0,
665 0x8000 | WM8962_GPIO_FN_DMICDAT,
666 WM8962_GPIO_FN_IRQ, /* Open drain mode */
667 },
668 .irq_active_low = true,
669};
670
671static struct wm9081_pdata wm9081_pdata __initdata = {
672 .irq_high = false,
673 .irq_cmos = false,
674};
675
676static struct i2c_board_info i2c_devs1[] __initdata = {
677 { I2C_BOARD_INFO("wm8311", 0x34),
678 .irq = S3C_EINT(0),
679 .platform_data = &glenfarclas_pmic_pdata },
680
681 { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
682 { I2C_BOARD_INFO("wm8915", 0x1a),
683 .platform_data = &wm8915_pdata,
684 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
685 },
686 { I2C_BOARD_INFO("wm9081", 0x6c),
687 .platform_data = &wm9081_pdata, },
688 { I2C_BOARD_INFO("wm8962", 0x1a),
689 .platform_data = &wm8962_pdata,
690 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
691 },
692};
693
694static void __init crag6410_map_io(void)
695{
696 s3c64xx_init_io(NULL, 0);
697 s3c24xx_init_clocks(12000000);
698 s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
699
700 /* LCD type and Bypass set by bootloader */
701}
702
703static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
704 .max_width = 4,
705 .cd_type = S3C_SDHCI_CD_PERMANENT,
706};
707
708static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = {
709 .max_width = 4,
710 .cd_type = S3C_SDHCI_CD_GPIO,
711 .ext_cd_gpio = S3C64XX_GPF(11),
712};
713
714static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
715{
716 /* Set all the necessary GPG pins to special-function 2 */
717 s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
718
719 /* force card-detected for prototype 0 */
720 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
721}
722
723static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
724 .max_width = 4,
725 .cd_type = S3C_SDHCI_CD_INTERNAL,
726 .cfg_gpio = crag6410_cfg_sdhci0,
727};
728
729static void __init crag6410_machine_init(void)
730{
731 /* Open drain IRQs need pullups */
732 s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
733 s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
734
735 gpio_request(S3C64XX_GPB(0), "LCD power");
736 gpio_direction_output(S3C64XX_GPB(0), 0);
737
738 gpio_request(S3C64XX_GPF(14), "LCD PWM");
739 gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
740
741 gpio_request(S3C64XX_GPB(1), "SD power");
742 gpio_direction_output(S3C64XX_GPB(1), 0);
743
744 gpio_request(S3C64XX_GPF(10), "nRESETSEL");
745 gpio_direction_output(S3C64XX_GPF(10), 1);
746
747 s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
748 s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata);
749 s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
750
751 s3c_i2c0_set_platdata(&i2c0_pdata);
752 s3c_i2c1_set_platdata(NULL);
753 s3c_fb_set_platdata(&crag6410_lcd_pdata);
754
755 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
756 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
757
758 samsung_keypad_set_platdata(&crag6410_keypad_data);
759
760 platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
761
762 regulator_has_full_constraints();
763
764 s3c_pm_init();
765}
766
767MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
768 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
769 .boot_params = S3C64XX_PA_SDRAM + 0x100,
770 .init_irq = s3c6410_init_irq,
771 .map_io = crag6410_map_io,
772 .init_machine = crag6410_machine_init,
773 .timer = &s3c24xx_timer,
774MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index b2639582caca..b3d93cc8dde0 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -27,7 +27,6 @@
27#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/regs-fb.h>
31#include <mach/map.h> 30#include <mach/map.h>
32 31
33#include <asm/irq.h> 32#include <asm/irq.h>
@@ -42,6 +41,7 @@
42#include <plat/clock.h> 41#include <plat/clock.h>
43#include <plat/devs.h> 42#include <plat/devs.h>
44#include <plat/cpu.h> 43#include <plat/cpu.h>
44#include <plat/regs-fb-v4.h>
45 45
46#define UCON S3C2410_UCON_DEFAULT 46#define UCON S3C2410_UCON_DEFAULT
47#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) 47#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 89f35e02e883..527f49bd1b57 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -29,7 +29,6 @@
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30 30
31#include <mach/map.h> 31#include <mach/map.h>
32#include <mach/regs-fb.h>
33#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
34#include <mach/regs-modem.h> 33#include <mach/regs-modem.h>
35#include <mach/regs-srom.h> 34#include <mach/regs-srom.h>
@@ -42,6 +41,7 @@
42#include <plat/nand.h> 41#include <plat/nand.h>
43#include <plat/regs-serial.h> 42#include <plat/regs-serial.h>
44#include <plat/ts.h> 43#include <plat/ts.h>
44#include <plat/regs-fb-v4.h>
45 45
46#include <video/platform_lcd.h> 46#include <video/platform_lcd.h>
47 47
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index c4986498cd12..01c6857c5b63 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -30,7 +30,6 @@
30#include <asm/mach/irq.h> 30#include <asm/mach/irq.h>
31 31
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/regs-fb.h>
34#include <mach/map.h> 33#include <mach/map.h>
35 34
36#include <asm/irq.h> 35#include <asm/irq.h>
@@ -44,6 +43,7 @@
44#include <plat/clock.h> 43#include <plat/clock.h>
45#include <plat/devs.h> 44#include <plat/devs.h>
46#include <plat/cpu.h> 45#include <plat/cpu.h>
46#include <plat/regs-fb-v4.h>
47 47
48#define UCON S3C2410_UCON_DEFAULT 48#define UCON S3C2410_UCON_DEFAULT
49#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE 49#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 4957ab0a0d4a..95b04b1729e3 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -30,7 +30,6 @@
30#include <asm/mach/map.h> 30#include <asm/mach/map.h>
31 31
32#include <mach/map.h> 32#include <mach/map.h>
33#include <mach/regs-fb.h>
34#include <mach/regs-gpio.h> 33#include <mach/regs-gpio.h>
35#include <mach/regs-modem.h> 34#include <mach/regs-modem.h>
36#include <mach/regs-srom.h> 35#include <mach/regs-srom.h>
@@ -43,6 +42,7 @@
43#include <plat/nand.h> 42#include <plat/nand.h>
44#include <plat/regs-serial.h> 43#include <plat/regs-serial.h>
45#include <plat/ts.h> 44#include <plat/ts.h>
45#include <plat/regs-fb-v4.h>
46 46
47#include <video/platform_lcd.h> 47#include <video/platform_lcd.h>
48 48
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 3a3e5acde523..342e8dfddf8b 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -21,7 +21,6 @@
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22 22
23#include <mach/map.h> 23#include <mach/map.h>
24#include <mach/regs-fb.h>
25#include <mach/regs-gpio.h> 24#include <mach/regs-gpio.h>
26#include <mach/s3c6410.h> 25#include <mach/s3c6410.h>
27 26
@@ -29,6 +28,7 @@
29#include <plat/devs.h> 28#include <plat/devs.h>
30#include <plat/fb.h> 29#include <plat/fb.h>
31#include <plat/gpio-cfg.h> 30#include <plat/gpio-cfg.h>
31#include <plat/regs-fb-v4.h>
32 32
33#include "mach-smartq.h" 33#include "mach-smartq.h"
34 34
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index e65375877d53..57963977da8e 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -21,7 +21,6 @@
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22 22
23#include <mach/map.h> 23#include <mach/map.h>
24#include <mach/regs-fb.h>
25#include <mach/regs-gpio.h> 24#include <mach/regs-gpio.h>
26#include <mach/s3c6410.h> 25#include <mach/s3c6410.h>
27 26
@@ -29,6 +28,7 @@
29#include <plat/devs.h> 28#include <plat/devs.h>
30#include <plat/fb.h> 29#include <plat/fb.h>
31#include <plat/gpio-cfg.h> 30#include <plat/gpio-cfg.h>
31#include <plat/regs-fb-v4.h>
32 32
33#include "mach-smartq.h" 33#include "mach-smartq.h"
34 34
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 2c0353a80906..ecbea92bf83b 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -48,7 +48,6 @@
48#include <asm/mach/irq.h> 48#include <asm/mach/irq.h>
49 49
50#include <mach/hardware.h> 50#include <mach/hardware.h>
51#include <mach/regs-fb.h>
52#include <mach/map.h> 51#include <mach/map.h>
53 52
54#include <asm/irq.h> 53#include <asm/irq.h>
@@ -71,6 +70,8 @@
71#include <plat/adc.h> 70#include <plat/adc.h>
72#include <plat/ts.h> 71#include <plat/ts.h>
73#include <plat/keypad.h> 72#include <plat/keypad.h>
73#include <plat/backlight.h>
74#include <plat/regs-fb-v4.h>
74 75
75#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK 76#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
76#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 77#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -209,17 +210,9 @@ static struct platform_device smdk6410_smsc911x = {
209}; 210};
210 211
211#ifdef CONFIG_REGULATOR 212#ifdef CONFIG_REGULATOR
212static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = { 213static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = {
213 { 214 REGULATOR_SUPPLY("PVDD", "0-001b"),
214 /* WM8580 */ 215 REGULATOR_SUPPLY("AVDD", "0-001b"),
215 .supply = "PVDD",
216 .dev_name = "0-001b",
217 },
218 {
219 /* WM8580 */
220 .supply = "AVDD",
221 .dev_name = "0-001b",
222 },
223}; 216};
224 217
225static struct regulator_init_data smdk6410_b_pwr_5v_data = { 218static struct regulator_init_data smdk6410_b_pwr_5v_data = {
@@ -337,16 +330,12 @@ static struct platform_device *smdk6410_devices[] __initdata = {
337 &s3c_device_rtc, 330 &s3c_device_rtc,
338 &s3c_device_ts, 331 &s3c_device_ts,
339 &s3c_device_wdt, 332 &s3c_device_wdt,
340 &s3c_device_timer[1],
341 &smdk6410_backlight_device,
342}; 333};
343 334
344#ifdef CONFIG_REGULATOR 335#ifdef CONFIG_REGULATOR
345/* ARM core */ 336/* ARM core */
346static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = { 337static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
347 { 338 REGULATOR_SUPPLY("vddarm", NULL),
348 .supply = "vddarm",
349 }
350}; 339};
351 340
352/* VDDARM, BUCK1 on J5 */ 341/* VDDARM, BUCK1 on J5 */
@@ -484,11 +473,7 @@ static struct regulator_init_data wm8350_dcdc3_data = {
484 473
485/* USB, EXT, PCM, ADC/DAC, USB, MMC */ 474/* USB, EXT, PCM, ADC/DAC, USB, MMC */
486static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { 475static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
487 { 476 REGULATOR_SUPPLY("DVDD", "0-001b"),
488 /* WM8580 */
489 .supply = "DVDD",
490 .dev_name = "0-001b",
491 },
492}; 477};
493 478
494static struct regulator_init_data wm8350_dcdc4_data = { 479static struct regulator_init_data wm8350_dcdc4_data = {
@@ -599,7 +584,7 @@ static struct regulator_init_data wm1192_dcdc3 = {
599}; 584};
600 585
601static struct regulator_consumer_supply wm1192_ldo1_consumers[] = { 586static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
602 { .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */ 587 REGULATOR_SUPPLY("DVDD", "0-001b"), /* WM8580 */
603}; 588};
604 589
605static struct regulator_init_data wm1192_ldo1 = { 590static struct regulator_init_data wm1192_ldo1 = {
@@ -679,6 +664,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
679 .oversampling_shift = 2, 664 .oversampling_shift = 2,
680}; 665};
681 666
667/* LCD Backlight data */
668static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = {
669 .no = S3C64XX_GPF(15),
670 .func = S3C_GPIO_SFN(2),
671};
672
673static struct platform_pwm_backlight_data smdk6410_bl_data = {
674 .pwm_id = 1,
675};
676
682static void __init smdk6410_map_io(void) 677static void __init smdk6410_map_io(void)
683{ 678{
684 u32 tmp; 679 u32 tmp;
@@ -740,6 +735,8 @@ static void __init smdk6410_machine_init(void)
740 735
741 s3c_ide_set_platdata(&smdk6410_ide_pdata); 736 s3c_ide_set_platdata(&smdk6410_ide_pdata);
742 737
738 samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
739
743 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); 740 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
744} 741}
745 742
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
index 8f3091182f9c..83d2afb79e9f 100644
--- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
+++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
@@ -17,7 +17,6 @@
17#include <linux/fb.h> 17#include <linux/fb.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19 19
20#include <mach/regs-fb.h>
21#include <plat/fb.h> 20#include <plat/fb.h>
22#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
23 22
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 23:31:17 -0400