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-rw-r--r--arch/arm/mach-s3c64xx/clock.c86
1 files changed, 25 insertions, 61 deletions
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fdfc4d5e37a1..8cf39e33579e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -39,7 +39,6 @@
39 39
40static struct clk clk_ext_xtal_mux = { 40static struct clk clk_ext_xtal_mux = {
41 .name = "ext_xtal", 41 .name = "ext_xtal",
42 .id = -1,
43}; 42};
44 43
45#define clk_fin_apll clk_ext_xtal_mux 44#define clk_fin_apll clk_ext_xtal_mux
@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
51 50
52struct clk clk_h2 = { 51struct clk clk_h2 = {
53 .name = "hclk2", 52 .name = "hclk2",
54 .id = -1,
55 .rate = 0, 53 .rate = 0,
56}; 54};
57 55
58struct clk clk_27m = { 56struct clk clk_27m = {
59 .name = "clk_27m", 57 .name = "clk_27m",
60 .id = -1,
61 .rate = 27000000, 58 .rate = 27000000,
62}; 59};
63 60
@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
83 80
84struct clk clk_48m = { 81struct clk clk_48m = {
85 .name = "clk_48m", 82 .name = "clk_48m",
86 .id = -1,
87 .rate = 48000000, 83 .rate = 48000000,
88 .enable = clk_48m_ctrl, 84 .enable = clk_48m_ctrl,
89}; 85};
90 86
91struct clk clk_xusbxti = { 87struct clk clk_xusbxti = {
92 .name = "xusbxti", 88 .name = "xusbxti",
93 .id = -1,
94 .rate = 48000000, 89 .rate = 48000000,
95}; 90};
96 91
@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
130static struct clk init_clocks_off[] = { 125static struct clk init_clocks_off[] = {
131 { 126 {
132 .name = "nand", 127 .name = "nand",
133 .id = -1,
134 .parent = &clk_h, 128 .parent = &clk_h,
135 }, { 129 }, {
136 .name = "rtc", 130 .name = "rtc",
137 .id = -1,
138 .parent = &clk_p, 131 .parent = &clk_p,
139 .enable = s3c64xx_pclk_ctrl, 132 .enable = s3c64xx_pclk_ctrl,
140 .ctrlbit = S3C_CLKCON_PCLK_RTC, 133 .ctrlbit = S3C_CLKCON_PCLK_RTC,
141 }, { 134 }, {
142 .name = "adc", 135 .name = "adc",
143 .id = -1,
144 .parent = &clk_p, 136 .parent = &clk_p,
145 .enable = s3c64xx_pclk_ctrl, 137 .enable = s3c64xx_pclk_ctrl,
146 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
147 }, { 139 }, {
148 .name = "i2c", 140 .name = "i2c",
149 .id = -1,
150 .parent = &clk_p, 141 .parent = &clk_p,
151 .enable = s3c64xx_pclk_ctrl, 142 .enable = s3c64xx_pclk_ctrl,
152 .ctrlbit = S3C_CLKCON_PCLK_IIC, 143 .ctrlbit = S3C_CLKCON_PCLK_IIC,
153 }, { 144 }, {
154 .name = "i2c", 145 .name = "i2c",
155 .id = 1, 146 .devname = "s3c2440-i2c.1",
156 .parent = &clk_p, 147 .parent = &clk_p,
157 .enable = s3c64xx_pclk_ctrl, 148 .enable = s3c64xx_pclk_ctrl,
158 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1, 149 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
159 }, { 150 }, {
160 .name = "iis", 151 .name = "iis",
161 .id = 0, 152 .devname = "samsung-i2s.0",
162 .parent = &clk_p, 153 .parent = &clk_p,
163 .enable = s3c64xx_pclk_ctrl, 154 .enable = s3c64xx_pclk_ctrl,
164 .ctrlbit = S3C_CLKCON_PCLK_IIS0, 155 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
165 }, { 156 }, {
166 .name = "iis", 157 .name = "iis",
167 .id = 1, 158 .devname = "samsung-i2s.1",
168 .parent = &clk_p, 159 .parent = &clk_p,
169 .enable = s3c64xx_pclk_ctrl, 160 .enable = s3c64xx_pclk_ctrl,
170 .ctrlbit = S3C_CLKCON_PCLK_IIS1, 161 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
171 }, { 162 }, {
172#ifdef CONFIG_CPU_S3C6410 163#ifdef CONFIG_CPU_S3C6410
173 .name = "iis", 164 .name = "iis",
174 .id = -1, /* There's only one IISv4 port */
175 .parent = &clk_p, 165 .parent = &clk_p,
176 .enable = s3c64xx_pclk_ctrl, 166 .enable = s3c64xx_pclk_ctrl,
177 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, 167 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
178 }, { 168 }, {
179#endif 169#endif
180 .name = "keypad", 170 .name = "keypad",
181 .id = -1,
182 .parent = &clk_p, 171 .parent = &clk_p,
183 .enable = s3c64xx_pclk_ctrl, 172 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, 173 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
185 }, { 174 }, {
186 .name = "spi", 175 .name = "spi",
187 .id = 0, 176 .devname = "s3c64xx-spi.0",
188 .parent = &clk_p, 177 .parent = &clk_p,
189 .enable = s3c64xx_pclk_ctrl, 178 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI0, 179 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
191 }, { 180 }, {
192 .name = "spi", 181 .name = "spi",
193 .id = 1, 182 .devname = "s3c64xx-spi.1",
194 .parent = &clk_p, 183 .parent = &clk_p,
195 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
196 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
197 }, { 186 }, {
198 .name = "spi_48m", 187 .name = "spi_48m",
199 .id = 0, 188 .devname = "s3c64xx-spi.0",
200 .parent = &clk_48m, 189 .parent = &clk_48m,
201 .enable = s3c64xx_sclk_ctrl, 190 .enable = s3c64xx_sclk_ctrl,
202 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, 191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
203 }, { 192 }, {
204 .name = "spi_48m", 193 .name = "spi_48m",
205 .id = 1, 194 .devname = "s3c64xx-spi.1",
206 .parent = &clk_48m, 195 .parent = &clk_48m,
207 .enable = s3c64xx_sclk_ctrl, 196 .enable = s3c64xx_sclk_ctrl,
208 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, 197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
209 }, { 198 }, {
210 .name = "48m", 199 .name = "48m",
211 .id = 0, 200 .devname = "s3c-sdhci.0",
212 .parent = &clk_48m, 201 .parent = &clk_48m,
213 .enable = s3c64xx_sclk_ctrl, 202 .enable = s3c64xx_sclk_ctrl,
214 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, 203 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
215 }, { 204 }, {
216 .name = "48m", 205 .name = "48m",
217 .id = 1, 206 .devname = "s3c-sdhci.1",
218 .parent = &clk_48m, 207 .parent = &clk_48m,
219 .enable = s3c64xx_sclk_ctrl, 208 .enable = s3c64xx_sclk_ctrl,
220 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, 209 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
221 }, { 210 }, {
222 .name = "48m", 211 .name = "48m",
223 .id = 2, 212 .devname = "s3c-sdhci.2",
224 .parent = &clk_48m, 213 .parent = &clk_48m,
225 .enable = s3c64xx_sclk_ctrl, 214 .enable = s3c64xx_sclk_ctrl,
226 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, 215 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
227 }, { 216 }, {
228 .name = "dma0", 217 .name = "dma0",
229 .id = -1,
230 .parent = &clk_h, 218 .parent = &clk_h,
231 .enable = s3c64xx_hclk_ctrl, 219 .enable = s3c64xx_hclk_ctrl,
232 .ctrlbit = S3C_CLKCON_HCLK_DMA0, 220 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
233 }, { 221 }, {
234 .name = "dma1", 222 .name = "dma1",
235 .id = -1,
236 .parent = &clk_h, 223 .parent = &clk_h,
237 .enable = s3c64xx_hclk_ctrl, 224 .enable = s3c64xx_hclk_ctrl,
238 .ctrlbit = S3C_CLKCON_HCLK_DMA1, 225 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
242static struct clk init_clocks[] = { 229static struct clk init_clocks[] = {
243 { 230 {
244 .name = "lcd", 231 .name = "lcd",
245 .id = -1,
246 .parent = &clk_h, 232 .parent = &clk_h,
247 .enable = s3c64xx_hclk_ctrl, 233 .enable = s3c64xx_hclk_ctrl,
248 .ctrlbit = S3C_CLKCON_HCLK_LCD, 234 .ctrlbit = S3C_CLKCON_HCLK_LCD,
249 }, { 235 }, {
250 .name = "gpio", 236 .name = "gpio",
251 .id = -1,
252 .parent = &clk_p, 237 .parent = &clk_p,
253 .enable = s3c64xx_pclk_ctrl, 238 .enable = s3c64xx_pclk_ctrl,
254 .ctrlbit = S3C_CLKCON_PCLK_GPIO, 239 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
255 }, { 240 }, {
256 .name = "usb-host", 241 .name = "usb-host",
257 .id = -1,
258 .parent = &clk_h, 242 .parent = &clk_h,
259 .enable = s3c64xx_hclk_ctrl, 243 .enable = s3c64xx_hclk_ctrl,
260 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 244 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
261 }, { 245 }, {
262 .name = "hsmmc", 246 .name = "hsmmc",
263 .id = 0, 247 .devname = "s3c-sdhci.0",
264 .parent = &clk_h, 248 .parent = &clk_h,
265 .enable = s3c64xx_hclk_ctrl, 249 .enable = s3c64xx_hclk_ctrl,
266 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, 250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
267 }, { 251 }, {
268 .name = "hsmmc", 252 .name = "hsmmc",
269 .id = 1, 253 .devname = "s3c-sdhci.1",
270 .parent = &clk_h, 254 .parent = &clk_h,
271 .enable = s3c64xx_hclk_ctrl, 255 .enable = s3c64xx_hclk_ctrl,
272 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, 256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
273 }, { 257 }, {
274 .name = "hsmmc", 258 .name = "hsmmc",
275 .id = 2, 259 .devname = "s3c-sdhci.2",
276 .parent = &clk_h, 260 .parent = &clk_h,
277 .enable = s3c64xx_hclk_ctrl, 261 .enable = s3c64xx_hclk_ctrl,
278 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, 262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
279 }, { 263 }, {
280 .name = "otg", 264 .name = "otg",
281 .id = -1,
282 .parent = &clk_h, 265 .parent = &clk_h,
283 .enable = s3c64xx_hclk_ctrl, 266 .enable = s3c64xx_hclk_ctrl,
284 .ctrlbit = S3C_CLKCON_HCLK_USB, 267 .ctrlbit = S3C_CLKCON_HCLK_USB,
285 }, { 268 }, {
286 .name = "timers", 269 .name = "timers",
287 .id = -1,
288 .parent = &clk_p, 270 .parent = &clk_p,
289 .enable = s3c64xx_pclk_ctrl, 271 .enable = s3c64xx_pclk_ctrl,
290 .ctrlbit = S3C_CLKCON_PCLK_PWM, 272 .ctrlbit = S3C_CLKCON_PCLK_PWM,
291 }, { 273 }, {
292 .name = "uart", 274 .name = "uart",
293 .id = 0, 275 .devname = "s3c6400-uart.0",
294 .parent = &clk_p, 276 .parent = &clk_p,
295 .enable = s3c64xx_pclk_ctrl, 277 .enable = s3c64xx_pclk_ctrl,
296 .ctrlbit = S3C_CLKCON_PCLK_UART0, 278 .ctrlbit = S3C_CLKCON_PCLK_UART0,
297 }, { 279 }, {
298 .name = "uart", 280 .name = "uart",
299 .id = 1, 281 .devname = "s3c6400-uart.1",
300 .parent = &clk_p, 282 .parent = &clk_p,
301 .enable = s3c64xx_pclk_ctrl, 283 .enable = s3c64xx_pclk_ctrl,
302 .ctrlbit = S3C_CLKCON_PCLK_UART1, 284 .ctrlbit = S3C_CLKCON_PCLK_UART1,
303 }, { 285 }, {
304 .name = "uart", 286 .name = "uart",
305 .id = 2, 287 .devname = "s3c6400-uart.2",
306 .parent = &clk_p, 288 .parent = &clk_p,
307 .enable = s3c64xx_pclk_ctrl, 289 .enable = s3c64xx_pclk_ctrl,
308 .ctrlbit = S3C_CLKCON_PCLK_UART2, 290 .ctrlbit = S3C_CLKCON_PCLK_UART2,
309 }, { 291 }, {
310 .name = "uart", 292 .name = "uart",
311 .id = 3, 293 .devname = "s3c6400-uart.3",
312 .parent = &clk_p, 294 .parent = &clk_p,
313 .enable = s3c64xx_pclk_ctrl, 295 .enable = s3c64xx_pclk_ctrl,
314 .ctrlbit = S3C_CLKCON_PCLK_UART3, 296 .ctrlbit = S3C_CLKCON_PCLK_UART3,
315 }, { 297 }, {
316 .name = "watchdog", 298 .name = "watchdog",
317 .id = -1,
318 .parent = &clk_p, 299 .parent = &clk_p,
319 .ctrlbit = S3C_CLKCON_PCLK_WDT, 300 .ctrlbit = S3C_CLKCON_PCLK_WDT,
320 }, { 301 }, {
321 .name = "ac97", 302 .name = "ac97",
322 .id = -1,
323 .parent = &clk_p, 303 .parent = &clk_p,
324 .ctrlbit = S3C_CLKCON_PCLK_AC97, 304 .ctrlbit = S3C_CLKCON_PCLK_AC97,
325 }, { 305 }, {
326 .name = "cfcon", 306 .name = "cfcon",
327 .id = -1,
328 .parent = &clk_h, 307 .parent = &clk_h,
329 .enable = s3c64xx_hclk_ctrl, 308 .enable = s3c64xx_hclk_ctrl,
330 .ctrlbit = S3C_CLKCON_HCLK_IHOST, 309 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
@@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
334 313
335static struct clk clk_fout_apll = { 314static struct clk clk_fout_apll = {
336 .name = "fout_apll", 315 .name = "fout_apll",
337 .id = -1,
338}; 316};
339 317
340static struct clk *clk_src_apll_list[] = { 318static struct clk *clk_src_apll_list[] = {
@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
350static struct clksrc_clk clk_mout_apll = { 328static struct clksrc_clk clk_mout_apll = {
351 .clk = { 329 .clk = {
352 .name = "mout_apll", 330 .name = "mout_apll",
353 .id = -1,
354 }, 331 },
355 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, 332 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
356 .sources = &clk_src_apll, 333 .sources = &clk_src_apll,
@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
369static struct clksrc_clk clk_mout_epll = { 346static struct clksrc_clk clk_mout_epll = {
370 .clk = { 347 .clk = {
371 .name = "mout_epll", 348 .name = "mout_epll",
372 .id = -1,
373 }, 349 },
374 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, 350 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
375 .sources = &clk_src_epll, 351 .sources = &clk_src_epll,
@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
388static struct clksrc_clk clk_mout_mpll = { 364static struct clksrc_clk clk_mout_mpll = {
389 .clk = { 365 .clk = {
390 .name = "mout_mpll", 366 .name = "mout_mpll",
391 .id = -1,
392 }, 367 },
393 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, 368 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
394 .sources = &clk_src_mpll, 369 .sources = &clk_src_mpll,
@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
446 421
447static struct clk clk_arm = { 422static struct clk clk_arm = {
448 .name = "armclk", 423 .name = "armclk",
449 .id = -1,
450 .parent = &clk_mout_apll.clk, 424 .parent = &clk_mout_apll.clk,
451 .ops = &(struct clk_ops) { 425 .ops = &(struct clk_ops) {
452 .get_rate = s3c64xx_clk_arm_get_rate, 426 .get_rate = s3c64xx_clk_arm_get_rate,
@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
473 447
474static struct clk clk_dout_mpll = { 448static struct clk clk_dout_mpll = {
475 .name = "dout_mpll", 449 .name = "dout_mpll",
476 .id = -1,
477 .parent = &clk_mout_mpll.clk, 450 .parent = &clk_mout_mpll.clk,
478 .ops = &clk_dout_ops, 451 .ops = &clk_dout_ops,
479}; 452};
@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
540 513
541static struct clk clk_iis_cd0 = { 514static struct clk clk_iis_cd0 = {
542 .name = "iis_cdclk0", 515 .name = "iis_cdclk0",
543 .id = -1,
544}; 516};
545 517
546static struct clk clk_iis_cd1 = { 518static struct clk clk_iis_cd1 = {
547 .name = "iis_cdclk1", 519 .name = "iis_cdclk1",
548 .id = -1,
549}; 520};
550 521
551static struct clk clk_iisv4_cd = { 522static struct clk clk_iisv4_cd = {
552 .name = "iis_cdclk_v4", 523 .name = "iis_cdclk_v4",
553 .id = -1,
554}; 524};
555 525
556static struct clk clk_pcm_cd = { 526static struct clk clk_pcm_cd = {
557 .name = "pcm_cdclk", 527 .name = "pcm_cdclk",
558 .id = -1,
559}; 528};
560 529
561static struct clk *clkset_audio0_list[] = { 530static struct clk *clkset_audio0_list[] = {
@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
610 { 579 {
611 .clk = { 580 .clk = {
612 .name = "mmc_bus", 581 .name = "mmc_bus",
613 .id = 0, 582 .devname = "s3c-sdhci.0",
614 .ctrlbit = S3C_CLKCON_SCLK_MMC0, 583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
615 .enable = s3c64xx_sclk_ctrl, 584 .enable = s3c64xx_sclk_ctrl,
616 }, 585 },
@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
620 }, { 589 }, {
621 .clk = { 590 .clk = {
622 .name = "mmc_bus", 591 .name = "mmc_bus",
623 .id = 1, 592 .devname = "s3c-sdhci.1",
624 .ctrlbit = S3C_CLKCON_SCLK_MMC1, 593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
625 .enable = s3c64xx_sclk_ctrl, 594 .enable = s3c64xx_sclk_ctrl,
626 }, 595 },
@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
630 }, { 599 }, {
631 .clk = { 600 .clk = {
632 .name = "mmc_bus", 601 .name = "mmc_bus",
633 .id = 2, 602 .devname = "s3c-sdhci.2",
634 .ctrlbit = S3C_CLKCON_SCLK_MMC2, 603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
635 .enable = s3c64xx_sclk_ctrl, 604 .enable = s3c64xx_sclk_ctrl,
636 }, 605 },
@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
640 }, { 609 }, {
641 .clk = { 610 .clk = {
642 .name = "usb-bus-host", 611 .name = "usb-bus-host",
643 .id = -1,
644 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 612 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
645 .enable = s3c64xx_sclk_ctrl, 613 .enable = s3c64xx_sclk_ctrl,
646 }, 614 },
@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
650 }, { 618 }, {
651 .clk = { 619 .clk = {
652 .name = "uclk1", 620 .name = "uclk1",
653 .id = -1,
654 .ctrlbit = S3C_CLKCON_SCLK_UART, 621 .ctrlbit = S3C_CLKCON_SCLK_UART,
655 .enable = s3c64xx_sclk_ctrl, 622 .enable = s3c64xx_sclk_ctrl,
656 }, 623 },
@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
661/* Where does UCLK0 come from? */ 628/* Where does UCLK0 come from? */
662 .clk = { 629 .clk = {
663 .name = "spi-bus", 630 .name = "spi-bus",
664 .id = 0, 631 .devname = "s3c64xx-spi.0",
665 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 632 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
666 .enable = s3c64xx_sclk_ctrl, 633 .enable = s3c64xx_sclk_ctrl,
667 }, 634 },
@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
671 }, { 638 }, {
672 .clk = { 639 .clk = {
673 .name = "spi-bus", 640 .name = "spi-bus",
674 .id = 1, 641 .devname = "s3c64xx-spi.1",
675 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
676 .enable = s3c64xx_sclk_ctrl, 642 .enable = s3c64xx_sclk_ctrl,
677 }, 643 },
678 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, 644 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
681 }, { 647 }, {
682 .clk = { 648 .clk = {
683 .name = "audio-bus", 649 .name = "audio-bus",
684 .id = 0, 650 .devname = "samsung-i2s.0",
685 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 651 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
686 .enable = s3c64xx_sclk_ctrl, 652 .enable = s3c64xx_sclk_ctrl,
687 }, 653 },
@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
691 }, { 657 }, {
692 .clk = { 658 .clk = {
693 .name = "audio-bus", 659 .name = "audio-bus",
694 .id = 1, 660 .devname = "samsung-i2s.1",
695 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, 661 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
696 .enable = s3c64xx_sclk_ctrl, 662 .enable = s3c64xx_sclk_ctrl,
697 }, 663 },
@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
701 }, { 667 }, {
702 .clk = { 668 .clk = {
703 .name = "audio-bus", 669 .name = "audio-bus",
704 .id = 2, 670 .devname = "samsung-i2s.2",
705 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, 671 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
706 .enable = s3c64xx_sclk_ctrl, 672 .enable = s3c64xx_sclk_ctrl,
707 }, 673 },
@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
711 }, { 677 }, {
712 .clk = { 678 .clk = {
713 .name = "irda-bus", 679 .name = "irda-bus",
714 .id = 0,
715 .ctrlbit = S3C_CLKCON_SCLK_IRDA, 680 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
716 .enable = s3c64xx_sclk_ctrl, 681 .enable = s3c64xx_sclk_ctrl,
717 }, 682 },
@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
721 }, { 686 }, {
722 .clk = { 687 .clk = {
723 .name = "camera", 688 .name = "camera",
724 .id = -1,
725 .ctrlbit = S3C_CLKCON_SCLK_CAM, 689 .ctrlbit = S3C_CLKCON_SCLK_CAM,
726 .enable = s3c64xx_sclk_ctrl, 690 .enable = s3c64xx_sclk_ctrl,
727 }, 691 },
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 21:38:45 -0400