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Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 2172f6603848..ba6f9a0a43e9 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -84,6 +84,7 @@ static struct clk slimbus_clk = {
84 84
85static struct clk sys_32k_ck = { 85static struct clk sys_32k_ck = {
86 .name = "sys_32k_ck", 86 .name = "sys_32k_ck",
87 .clkdm_name = "prm_clkdm",
87 .rate = 32768, 88 .rate = 32768,
88 .ops = &clkops_null, 89 .ops = &clkops_null,
89}; 90};
@@ -512,6 +513,7 @@ static struct clk ddrphy_ck = {
512 .name = "ddrphy_ck", 513 .name = "ddrphy_ck",
513 .parent = &dpll_core_m2_ck, 514 .parent = &dpll_core_m2_ck,
514 .ops = &clkops_null, 515 .ops = &clkops_null,
516 .clkdm_name = "l3_emif_clkdm",
515 .fixed_div = 2, 517 .fixed_div = 2,
516 .recalc = &omap_fixed_divisor_recalc, 518 .recalc = &omap_fixed_divisor_recalc,
517}; 519};
@@ -769,6 +771,7 @@ static const struct clksel dpll_mpu_m2_div[] = {
769static struct clk dpll_mpu_m2_ck = { 771static struct clk dpll_mpu_m2_ck = {
770 .name = "dpll_mpu_m2_ck", 772 .name = "dpll_mpu_m2_ck",
771 .parent = &dpll_mpu_ck, 773 .parent = &dpll_mpu_ck,
774 .clkdm_name = "cm_clkdm",
772 .clksel = dpll_mpu_m2_div, 775 .clksel = dpll_mpu_m2_div,
773 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, 776 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
774 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 777 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
@@ -1149,6 +1152,7 @@ static const struct clksel l3_div_div[] = {
1149static struct clk l3_div_ck = { 1152static struct clk l3_div_ck = {
1150 .name = "l3_div_ck", 1153 .name = "l3_div_ck",
1151 .parent = &div_core_ck, 1154 .parent = &div_core_ck,
1155 .clkdm_name = "cm_clkdm",
1152 .clksel = l3_div_div, 1156 .clksel = l3_div_div,
1153 .clksel_reg = OMAP4430_CM_CLKSEL_CORE, 1157 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1154 .clksel_mask = OMAP4430_CLKSEL_L3_MASK, 1158 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
@@ -2824,6 +2828,7 @@ static const struct clksel trace_clk_div_div[] = {
2824static struct clk trace_clk_div_ck = { 2828static struct clk trace_clk_div_ck = {
2825 .name = "trace_clk_div_ck", 2829 .name = "trace_clk_div_ck",
2826 .parent = &pmd_trace_clk_mux_ck, 2830 .parent = &pmd_trace_clk_mux_ck,
2831 .clkdm_name = "emu_sys_clkdm",
2827 .clksel = trace_clk_div_div, 2832 .clksel = trace_clk_div_div,
2828 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, 2833 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2829 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, 2834 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
@@ -3412,9 +3417,12 @@ int __init omap4xxx_clk_init(void)
3412 if (cpu_is_omap443x()) { 3417 if (cpu_is_omap443x()) {
3413 cpu_mask = RATE_IN_4430; 3418 cpu_mask = RATE_IN_4430;
3414 cpu_clkflg = CK_443X; 3419 cpu_clkflg = CK_443X;
3415 } else if (cpu_is_omap446x()) { 3420 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
3416 cpu_mask = RATE_IN_4460 | RATE_IN_4430; 3421 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3417 cpu_clkflg = CK_446X | CK_443X; 3422 cpu_clkflg = CK_446X | CK_443X;
3423
3424 if (cpu_is_omap447x())
3425 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
3418 } else { 3426 } else {
3419 return 0; 3427 return 0;
3420 } 3428 }