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-rw-r--r--arch/arm/mach-integrator/Kconfig1
-rw-r--r--arch/arm/mach-integrator/Makefile2
-rw-r--r--arch/arm/mach-integrator/clock.c59
-rw-r--r--arch/arm/mach-integrator/common.h2
-rw-r--r--arch/arm/mach-integrator/core.c127
-rw-r--r--arch/arm/mach-integrator/cpu.c53
-rw-r--r--arch/arm/mach-integrator/impd1.c43
-rw-r--r--arch/arm/mach-integrator/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-integrator/include/mach/entry-macro.S1
-rw-r--r--arch/arm/mach-integrator/include/mach/hardware.h17
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h54
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c166
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c88
-rw-r--r--arch/arm/mach-integrator/leds.c1
-rw-r--r--arch/arm/mach-integrator/pci_v3.c7
15 files changed, 297 insertions, 331 deletions
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index df97d16390e3..27db275b367c 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -11,6 +11,7 @@ config ARCH_INTEGRATOR_AP
11config ARCH_INTEGRATOR_CP 11config ARCH_INTEGRATOR_CP
12 bool "Support Integrator/CP platform" 12 bool "Support Integrator/CP platform"
13 select ARCH_CINTEGRATOR 13 select ARCH_CINTEGRATOR
14 select ARM_TIMER_SP804
14 help 15 help
15 Include support for the ARM(R) Integrator CP platform. 16 Include support for the ARM(R) Integrator CP platform.
16 17
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 6a5ef8d30b10..ebeef966e1f5 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,7 +4,7 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := clock.o core.o lm.o 7obj-y := core.o lm.o
8obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o 8obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
9obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o 9obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
10 10
diff --git a/arch/arm/mach-integrator/clock.c b/arch/arm/mach-integrator/clock.c
deleted file mode 100644
index 989ecf5f5c46..000000000000
--- a/arch/arm/mach-integrator/clock.c
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * linux/arch/arm/mach-integrator/clock.c
3 *
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/clk.h>
15#include <linux/mutex.h>
16
17#include <asm/clkdev.h>
18#include <mach/clkdev.h>
19
20int clk_enable(struct clk *clk)
21{
22 return 0;
23}
24EXPORT_SYMBOL(clk_enable);
25
26void clk_disable(struct clk *clk)
27{
28}
29EXPORT_SYMBOL(clk_disable);
30
31unsigned long clk_get_rate(struct clk *clk)
32{
33 return clk->rate;
34}
35EXPORT_SYMBOL(clk_get_rate);
36
37long clk_round_rate(struct clk *clk, unsigned long rate)
38{
39 struct icst525_vco vco;
40 vco = icst525_khz_to_vco(clk->params, rate / 1000);
41 return icst525_khz(clk->params, vco) * 1000;
42}
43EXPORT_SYMBOL(clk_round_rate);
44
45int clk_set_rate(struct clk *clk, unsigned long rate)
46{
47 int ret = -EIO;
48
49 if (clk->setvco) {
50 struct icst525_vco vco;
51
52 vco = icst525_khz_to_vco(clk->params, rate / 1000);
53 clk->rate = icst525_khz(clk->params, vco) * 1000;
54 clk->setvco(clk, vco);
55 ret = 0;
56 }
57 return ret;
58}
59EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
deleted file mode 100644
index 609c49de3d47..000000000000
--- a/arch/arm/mach-integrator/common.h
+++ /dev/null
@@ -1,2 +0,0 @@
1extern void integrator_time_init(unsigned long, unsigned int);
2extern unsigned long integrator_gettimeoffset(void);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 8b390e36ba69..b02cfc06e0ae 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -24,15 +24,13 @@
24#include <asm/clkdev.h> 24#include <asm/clkdev.h>
25#include <mach/clkdev.h> 25#include <mach/clkdev.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/platform.h>
27#include <asm/irq.h> 28#include <asm/irq.h>
28#include <asm/hardware/arm_timer.h>
29#include <mach/cm.h> 29#include <mach/cm.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/leds.h> 31#include <asm/leds.h>
32#include <asm/mach/time.h> 32#include <asm/mach/time.h>
33 33
34#include "common.h"
35
36static struct amba_pl010_data integrator_uart_data; 34static struct amba_pl010_data integrator_uart_data;
37 35
38static struct amba_device rtc_device = { 36static struct amba_device rtc_device = {
@@ -163,8 +161,8 @@ arch_initcall(integrator_init);
163 * UART0 7 6 161 * UART0 7 6
164 * UART1 5 4 162 * UART1 5 4
165 */ 163 */
166#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET) 164#define SC_CTRLC IO_ADDRESS(INTEGRATOR_SC_CTRLC)
167#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET) 165#define SC_CTRLS IO_ADDRESS(INTEGRATOR_SC_CTRLS)
168 166
169static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl) 167static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
170{ 168{
@@ -196,7 +194,7 @@ static struct amba_pl010_data integrator_uart_data = {
196 .set_mctrl = integrator_uart_set_mctrl, 194 .set_mctrl = integrator_uart_set_mctrl,
197}; 195};
198 196
199#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET 197#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
200 198
201static DEFINE_SPINLOCK(cm_lock); 199static DEFINE_SPINLOCK(cm_lock);
202 200
@@ -217,120 +215,3 @@ void cm_control(u32 mask, u32 set)
217} 215}
218 216
219EXPORT_SYMBOL(cm_control); 217EXPORT_SYMBOL(cm_control);
220
221/*
222 * Where is the timer (VA)?
223 */
224#define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000)
225#define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100)
226#define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200)
227#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
228
229/*
230 * How long is the timer interval?
231 */
232#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
233#if TIMER_INTERVAL >= 0x100000
234#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
235#elif TIMER_INTERVAL >= 0x10000
236#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
237#else
238#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
239#endif
240
241static unsigned long timer_reload;
242
243/*
244 * Returns number of ms since last clock interrupt. Note that interrupts
245 * will have been disabled by do_gettimeoffset()
246 */
247unsigned long integrator_gettimeoffset(void)
248{
249 unsigned long ticks1, ticks2, status;
250
251 /*
252 * Get the current number of ticks. Note that there is a race
253 * condition between us reading the timer and checking for
254 * an interrupt. We get around this by ensuring that the
255 * counter has not reloaded between our two reads.
256 */
257 ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
258 do {
259 ticks1 = ticks2;
260 status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS);
261 ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
262 } while (ticks2 > ticks1);
263
264 /*
265 * Number of ticks since last interrupt.
266 */
267 ticks1 = timer_reload - ticks2;
268
269 /*
270 * Interrupt pending? If so, we've reloaded once already.
271 */
272 if (status & (1 << IRQ_TIMERINT1))
273 ticks1 += timer_reload;
274
275 /*
276 * Convert the ticks to usecs
277 */
278 return TICKS2USECS(ticks1);
279}
280
281/*
282 * IRQ handler for the timer
283 */
284static irqreturn_t
285integrator_timer_interrupt(int irq, void *dev_id)
286{
287 /*
288 * clear the interrupt
289 */
290 writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
291
292 timer_tick();
293
294 return IRQ_HANDLED;
295}
296
297static struct irqaction integrator_timer_irq = {
298 .name = "Integrator Timer Tick",
299 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
300 .handler = integrator_timer_interrupt,
301};
302
303/*
304 * Set up timer interrupt, and return the current time in seconds.
305 */
306void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
307{
308 unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
309
310 timer_reload = reload;
311 timer_ctrl |= ctrl;
312
313 if (timer_reload > 0x100000) {
314 timer_reload >>= 8;
315 timer_ctrl |= TIMER_CTRL_DIV256;
316 } else if (timer_reload > 0x010000) {
317 timer_reload >>= 4;
318 timer_ctrl |= TIMER_CTRL_DIV16;
319 }
320
321 /*
322 * Initialise to a known state (all timers off)
323 */
324 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
325 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
326 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
327
328 writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD);
329 writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE);
330 writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL);
331
332 /*
333 * Make irqs happen for the system timer
334 */
335 setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
336}
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index f77f20255045..a3fbcb3adc29 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -19,32 +19,39 @@
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/platform.h>
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
23#include <asm/hardware/icst525.h> 24#include <asm/hardware/icst.h>
24 25
25static struct cpufreq_driver integrator_driver; 26static struct cpufreq_driver integrator_driver;
26 27
27#define CM_ID (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_ID_OFFSET) 28#define CM_ID IO_ADDRESS(INTEGRATOR_HDR_ID)
28#define CM_OSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_OSC_OFFSET) 29#define CM_OSC IO_ADDRESS(INTEGRATOR_HDR_OSC)
29#define CM_STAT (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_STAT_OFFSET) 30#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT)
30#define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) 31#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
31 32
32static const struct icst525_params lclk_params = { 33static const struct icst_params lclk_params = {
33 .ref = 24000, 34 .ref = 24000000,
34 .vco_max = 320000, 35 .vco_max = ICST525_VCO_MAX_5V,
36 .vco_min = ICST525_VCO_MIN,
35 .vd_min = 8, 37 .vd_min = 8,
36 .vd_max = 132, 38 .vd_max = 132,
37 .rd_min = 24, 39 .rd_min = 24,
38 .rd_max = 24, 40 .rd_max = 24,
41 .s2div = icst525_s2div,
42 .idx2s = icst525_idx2s,
39}; 43};
40 44
41static const struct icst525_params cclk_params = { 45static const struct icst_params cclk_params = {
42 .ref = 24000, 46 .ref = 24000000,
43 .vco_max = 320000, 47 .vco_max = ICST525_VCO_MAX_5V,
48 .vco_min = ICST525_VCO_MIN,
44 .vd_min = 12, 49 .vd_min = 12,
45 .vd_max = 160, 50 .vd_max = 160,
46 .rd_min = 24, 51 .rd_min = 24,
47 .rd_max = 24, 52 .rd_max = 24,
53 .s2div = icst525_s2div,
54 .idx2s = icst525_idx2s,
48}; 55};
49 56
50/* 57/*
@@ -52,17 +59,17 @@ static const struct icst525_params cclk_params = {
52 */ 59 */
53static int integrator_verify_policy(struct cpufreq_policy *policy) 60static int integrator_verify_policy(struct cpufreq_policy *policy)
54{ 61{
55 struct icst525_vco vco; 62 struct icst_vco vco;
56 63
57 cpufreq_verify_within_limits(policy, 64 cpufreq_verify_within_limits(policy,
58 policy->cpuinfo.min_freq, 65 policy->cpuinfo.min_freq,
59 policy->cpuinfo.max_freq); 66 policy->cpuinfo.max_freq);
60 67
61 vco = icst525_khz_to_vco(&cclk_params, policy->max); 68 vco = icst_hz_to_vco(&cclk_params, policy->max * 1000);
62 policy->max = icst525_khz(&cclk_params, vco); 69 policy->max = icst_hz(&cclk_params, vco) / 1000;
63 70
64 vco = icst525_khz_to_vco(&cclk_params, policy->min); 71 vco = icst_hz_to_vco(&cclk_params, policy->min * 1000);
65 policy->min = icst525_khz(&cclk_params, vco); 72 policy->min = icst_hz(&cclk_params, vco) / 1000;
66 73
67 cpufreq_verify_within_limits(policy, 74 cpufreq_verify_within_limits(policy,
68 policy->cpuinfo.min_freq, 75 policy->cpuinfo.min_freq,
@@ -78,7 +85,7 @@ static int integrator_set_target(struct cpufreq_policy *policy,
78{ 85{
79 cpumask_t cpus_allowed; 86 cpumask_t cpus_allowed;
80 int cpu = policy->cpu; 87 int cpu = policy->cpu;
81 struct icst525_vco vco; 88 struct icst_vco vco;
82 struct cpufreq_freqs freqs; 89 struct cpufreq_freqs freqs;
83 u_int cm_osc; 90 u_int cm_osc;
84 91
@@ -104,17 +111,17 @@ static int integrator_set_target(struct cpufreq_policy *policy,
104 } 111 }
105 vco.v = cm_osc & 255; 112 vco.v = cm_osc & 255;
106 vco.r = 22; 113 vco.r = 22;
107 freqs.old = icst525_khz(&cclk_params, vco); 114 freqs.old = icst_hz(&cclk_params, vco) / 1000;
108 115
109 /* icst525_khz_to_vco rounds down -- so we need the next 116 /* icst_hz_to_vco rounds down -- so we need the next
110 * larger freq in case of CPUFREQ_RELATION_L. 117 * larger freq in case of CPUFREQ_RELATION_L.
111 */ 118 */
112 if (relation == CPUFREQ_RELATION_L) 119 if (relation == CPUFREQ_RELATION_L)
113 target_freq += 999; 120 target_freq += 999;
114 if (target_freq > policy->max) 121 if (target_freq > policy->max)
115 target_freq = policy->max; 122 target_freq = policy->max;
116 vco = icst525_khz_to_vco(&cclk_params, target_freq); 123 vco = icst_hz_to_vco(&cclk_params, target_freq * 1000);
117 freqs.new = icst525_khz(&cclk_params, vco); 124 freqs.new = icst_hz(&cclk_params, vco) / 1000;
118 125
119 freqs.cpu = policy->cpu; 126 freqs.cpu = policy->cpu;
120 127
@@ -154,7 +161,7 @@ static unsigned int integrator_get(unsigned int cpu)
154 cpumask_t cpus_allowed; 161 cpumask_t cpus_allowed;
155 unsigned int current_freq; 162 unsigned int current_freq;
156 u_int cm_osc; 163 u_int cm_osc;
157 struct icst525_vco vco; 164 struct icst_vco vco;
158 165
159 cpus_allowed = current->cpus_allowed; 166 cpus_allowed = current->cpus_allowed;
160 167
@@ -172,7 +179,7 @@ static unsigned int integrator_get(unsigned int cpu)
172 vco.v = cm_osc & 255; 179 vco.v = cm_osc & 255;
173 vco.r = 22; 180 vco.r = 22;
174 181
175 current_freq = icst525_khz(&cclk_params, vco); /* current freq */ 182 current_freq = icst_hz(&cclk_params, vco) / 1000; /* current freq */
176 183
177 set_cpus_allowed(current, cpus_allowed); 184 set_cpus_allowed(current, cpus_allowed);
178 185
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 41b10725cef7..fd684bf205e5 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -25,7 +25,7 @@
25 25
26#include <asm/clkdev.h> 26#include <asm/clkdev.h>
27#include <mach/clkdev.h> 27#include <mach/clkdev.h>
28#include <asm/hardware/icst525.h> 28#include <asm/hardware/icst.h>
29#include <mach/lm.h> 29#include <mach/lm.h>
30#include <mach/impd1.h> 30#include <mach/impd1.h>
31#include <asm/sizes.h> 31#include <asm/sizes.h>
@@ -41,32 +41,25 @@ struct impd1_module {
41 struct clk_lookup *clks[3]; 41 struct clk_lookup *clks[3];
42}; 42};
43 43
44static const struct icst525_params impd1_vco_params = { 44static const struct icst_params impd1_vco_params = {
45 .ref = 24000, /* 24 MHz */ 45 .ref = 24000000, /* 24 MHz */
46 .vco_max = 200000, /* 200 MHz */ 46 .vco_max = ICST525_VCO_MAX_3V,
47 .vco_min = ICST525_VCO_MIN,
47 .vd_min = 12, 48 .vd_min = 12,
48 .vd_max = 519, 49 .vd_max = 519,
49 .rd_min = 3, 50 .rd_min = 3,
50 .rd_max = 120, 51 .rd_max = 120,
52 .s2div = icst525_s2div,
53 .idx2s = icst525_idx2s,
51}; 54};
52 55
53static void impd1_setvco(struct clk *clk, struct icst525_vco vco) 56static void impd1_setvco(struct clk *clk, struct icst_vco vco)
54{ 57{
55 struct impd1_module *impd1 = clk->data; 58 struct impd1_module *impd1 = clk->data;
56 int vconr = clk - impd1->vcos; 59 u32 val = vco.v | (vco.r << 9) | (vco.s << 16);
57 u32 val;
58
59 val = vco.v | (vco.r << 9) | (vco.s << 16);
60 60
61 writel(0xa05f, impd1->base + IMPD1_LOCK); 61 writel(0xa05f, impd1->base + IMPD1_LOCK);
62 switch (vconr) { 62 writel(val, clk->vcoreg);
63 case 0:
64 writel(val, impd1->base + IMPD1_OSC1);
65 break;
66 case 1:
67 writel(val, impd1->base + IMPD1_OSC2);
68 break;
69 }
70 writel(0, impd1->base + IMPD1_LOCK); 63 writel(0, impd1->base + IMPD1_LOCK);
71 64
72#ifdef DEBUG 65#ifdef DEBUG
@@ -74,11 +67,17 @@ static void impd1_setvco(struct clk *clk, struct icst525_vco vco)
74 vco.r = (val >> 9) & 0x7f; 67 vco.r = (val >> 9) & 0x7f;
75 vco.s = (val >> 16) & 7; 68 vco.s = (val >> 16) & 7;
76 69
77 pr_debug("IM-PD1: VCO%d clock is %ld kHz\n", 70 pr_debug("IM-PD1: VCO%d clock is %ld Hz\n",
78 vconr, icst525_khz(&impd1_vco_params, vco)); 71 vconr, icst525_hz(&impd1_vco_params, vco));
79#endif 72#endif
80} 73}
81 74
75static const struct clk_ops impd1_clk_ops = {
76 .round = icst_clk_round,
77 .set = icst_clk_set,
78 .setvco = impd1_setvco,
79};
80
82void impd1_tweak_control(struct device *dev, u32 mask, u32 val) 81void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
83{ 82{
84 struct impd1_module *impd1 = dev_get_drvdata(dev); 83 struct impd1_module *impd1 = dev_get_drvdata(dev);
@@ -374,11 +373,13 @@ static int impd1_probe(struct lm_device *dev)
374 (unsigned long)dev->resource.start); 373 (unsigned long)dev->resource.start);
375 374
376 for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) { 375 for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) {
376 impd1->vcos[i].ops = &impd1_clk_ops,
377 impd1->vcos[i].owner = THIS_MODULE, 377 impd1->vcos[i].owner = THIS_MODULE,
378 impd1->vcos[i].params = &impd1_vco_params, 378 impd1->vcos[i].params = &impd1_vco_params,
379 impd1->vcos[i].data = impd1, 379 impd1->vcos[i].data = impd1;
380 impd1->vcos[i].setvco = impd1_setvco;
381 } 380 }
381 impd1->vcos[0].vcoreg = impd1->base + IMPD1_OSC1;
382 impd1->vcos[1].vcoreg = impd1->base + IMPD1_OSC2;
382 383
383 impd1->clks[0] = clkdev_alloc(&impd1->vcos[0], NULL, "lm%x:01000", 384 impd1->clks[0] = clkdev_alloc(&impd1->vcos[0], NULL, "lm%x:01000",
384 dev->id); 385 dev->id);
diff --git a/arch/arm/mach-integrator/include/mach/clkdev.h b/arch/arm/mach-integrator/include/mach/clkdev.h
index 9293e410832a..bfe07679faec 100644
--- a/arch/arm/mach-integrator/include/mach/clkdev.h
+++ b/arch/arm/mach-integrator/include/mach/clkdev.h
@@ -2,14 +2,15 @@
2#define __ASM_MACH_CLKDEV_H 2#define __ASM_MACH_CLKDEV_H
3 3
4#include <linux/module.h> 4#include <linux/module.h>
5#include <asm/hardware/icst525.h> 5#include <plat/clock.h>
6 6
7struct clk { 7struct clk {
8 unsigned long rate; 8 unsigned long rate;
9 const struct clk_ops *ops;
9 struct module *owner; 10 struct module *owner;
10 const struct icst525_params *params; 11 const struct icst_params *params;
12 void __iomem *vcoreg;
11 void *data; 13 void *data;
12 void (*setvco)(struct clk *, struct icst525_vco vco);
13}; 14};
14 15
15static inline int __clk_get(struct clk *clk) 16static inline int __clk_get(struct clk *clk)
diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S
index 7649c57acb53..3d029c9f3ef6 100644
--- a/arch/arm/mach-integrator/include/mach/entry-macro.S
+++ b/arch/arm/mach-integrator/include/mach/entry-macro.S
@@ -8,6 +8,7 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10#include <mach/hardware.h> 10#include <mach/hardware.h>
11#include <mach/platform.h>
11#include <mach/irqs.h> 12#include <mach/irqs.h>
12 13
13 .macro disable_fiq 14 .macro disable_fiq
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
index d795642fad22..8e26360ce9a3 100644
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ b/arch/arm/mach-integrator/include/mach/hardware.h
@@ -23,7 +23,6 @@
23#define __ASM_ARCH_HARDWARE_H 23#define __ASM_ARCH_HARDWARE_H
24 24
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26#include <mach/platform.h>
27 26
28/* 27/*
29 * Where in virtual memory the IO devices (timers, system controllers 28 * Where in virtual memory the IO devices (timers, system controllers
@@ -36,17 +35,19 @@
36#define PCIO_BASE PCI_IO_VADDR 35#define PCIO_BASE PCI_IO_VADDR
37#define PCIMEM_BASE PCI_MEMORY_VADDR 36#define PCIMEM_BASE PCI_MEMORY_VADDR
38 37
39#ifdef CONFIG_MMU
40/* macro to get at IO space when running virtually */
41#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE)
42#else
43#define IO_ADDRESS(x) (x)
44#endif
45
46#define pcibios_assign_all_busses() 1 38#define pcibios_assign_all_busses() 1
47 39
48#define PCIBIOS_MIN_IO 0x6000 40#define PCIBIOS_MIN_IO 0x6000
49#define PCIBIOS_MIN_MEM 0x00100000 41#define PCIBIOS_MIN_MEM 0x00100000
50 42
43/* macro to get at IO space when running virtually */
44#ifdef CONFIG_MMU
45#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
46#else
47#define IO_ADDRESS(x) (x)
48#endif
49
50#define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
51
51#endif 52#endif
52 53
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index e00a2624f269..5e6ea5cfea6e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -23,9 +23,6 @@
23 * 23 *
24 * Integrator address map 24 * Integrator address map
25 * 25 *
26 * NOTE: This is a multi-hosted header file for use with uHAL and
27 * supported debuggers.
28 *
29 * ***********************************************************************/ 26 * ***********************************************************************/
30 27
31#ifndef __address_h 28#ifndef __address_h
@@ -290,12 +287,14 @@
290#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) 287#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
291#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) 288#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
292 289
290#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
293 291
294#if defined(CONFIG_ARCH_INTEGRATOR_AP) 292#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
295#define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */ 293#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
296#elif defined(CONFIG_ARCH_INTEGRATOR_CP) 294#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
297#define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */ 295#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
298#endif 296#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
297#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
299 298
300/* ------------------------------------------------------------------------ 299/* ------------------------------------------------------------------------
301 * KMI keyboard/mouse definitions 300 * KMI keyboard/mouse definitions
@@ -328,20 +327,6 @@
328 */ 327 */
329#define PHYS_PCI_V3_BASE 0x62000000 328#define PHYS_PCI_V3_BASE 0x62000000
330 329
331#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
332
333/* 'export' these to UHAL */
334#define UHAL_PCI_IO PCI_IO_BASE
335#define UHAL_PCI_MEM PCI_MEM_BASE
336#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
337#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
338#define UHAL_PCI_MAX_SLOT 20
339
340/* ========================================================================
341 * Start of uHAL definitions
342 * ========================================================================
343 */
344
345/* ------------------------------------------------------------------------ 330/* ------------------------------------------------------------------------
346 * Integrator Interrupt Controllers 331 * Integrator Interrupt Controllers
347 * ------------------------------------------------------------------------ 332 * ------------------------------------------------------------------------
@@ -389,7 +374,7 @@
389 */ 374 */
390 375
391/* ------------------------------------------------------------------------ 376/* ------------------------------------------------------------------------
392 * LED's - The header LED is not accessible via the uHAL API 377 * LED's
393 * ------------------------------------------------------------------------ 378 * ------------------------------------------------------------------------
394 * 379 *
395 */ 380 */
@@ -402,34 +387,18 @@
402#define LED_BANK INTEGRATOR_DBG_LEDS 387#define LED_BANK INTEGRATOR_DBG_LEDS
403 388
404/* 389/*
405 * Memory definitions - run uHAL out of SSRAM.
406 *
407 */
408#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
409
410/*
411 * Clean base - dummy
412 *
413 */
414#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI
415
416/*
417 * Timer definitions 390 * Timer definitions
418 * 391 *
419 * Only use timer 1 & 2 392 * Only use timer 1 & 2
420 * (both run at 24MHz and will need the clock divider set to 16). 393 * (both run at 24MHz and will need the clock divider set to 16).
421 * 394 *
422 * Timer 0 runs at bus frequency and therefore could vary and currently 395 * Timer 0 runs at bus frequency
423 * uHAL can't handle that.
424 *
425 */ 396 */
426 397
427#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE 398#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
428#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) 399#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
429#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) 400#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
430 401
431#define MAX_TIMER 2
432#define MAX_PERIOD 699050
433#define TICKS_PER_uSEC 24 402#define TICKS_PER_uSEC 24
434 403
435/* 404/*
@@ -437,14 +406,9 @@
437 * 406 *
438 */ 407 */
439#define mSEC_1 1000 408#define mSEC_1 1000
440#define mSEC_5 (mSEC_1 * 5)
441#define mSEC_10 (mSEC_1 * 10) 409#define mSEC_10 (mSEC_1 * 10)
442#define mSEC_25 (mSEC_1 * 25)
443#define SEC_1 (mSEC_1 * 1000)
444 410
445#define INTEGRATOR_CSR_BASE 0x10000000 411#define INTEGRATOR_CSR_BASE 0x10000000
446#define INTEGRATOR_CSR_SIZE 0x10000000 412#define INTEGRATOR_CSR_SIZE 0x10000000
447 413
448#endif 414#endif
449
450/* END */
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 8138a7e24562..227cf4d05088 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -27,9 +27,14 @@
27#include <linux/sysdev.h> 27#include <linux/sysdev.h>
28#include <linux/amba/bus.h> 28#include <linux/amba/bus.h>
29#include <linux/amba/kmi.h> 29#include <linux/amba/kmi.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/interrupt.h>
30#include <linux/io.h> 33#include <linux/io.h>
31 34
32#include <mach/hardware.h> 35#include <mach/hardware.h>
36#include <mach/platform.h>
37#include <asm/hardware/arm_timer.h>
33#include <asm/irq.h> 38#include <asm/irq.h>
34#include <asm/setup.h> 39#include <asm/setup.h>
35#include <asm/param.h> /* HZ */ 40#include <asm/param.h> /* HZ */
@@ -43,8 +48,6 @@
43#include <asm/mach/map.h> 48#include <asm/mach/map.h>
44#include <asm/mach/time.h> 49#include <asm/mach/time.h>
45 50
46#include "common.h"
47
48/* 51/*
49 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx 52 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
50 * is the (PA >> 12). 53 * is the (PA >> 12).
@@ -55,7 +58,7 @@
55#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) 58#define VA_IC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
56#define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE) 59#define VA_SC_BASE IO_ADDRESS(INTEGRATOR_SC_BASE)
57#define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE) 60#define VA_EBI_BASE IO_ADDRESS(INTEGRATOR_EBI_BASE)
58#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET 61#define VA_CMIC_BASE IO_ADDRESS(INTEGRATOR_HDR_IC)
59 62
60/* 63/*
61 * Logical Physical 64 * Logical Physical
@@ -117,8 +120,8 @@ static struct map_desc ap_io_desc[] __initdata = {
117 .length = SZ_4K, 120 .length = SZ_4K,
118 .type = MT_DEVICE 121 .type = MT_DEVICE
119 }, { 122 }, {
120 .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), 123 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
121 .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), 124 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
122 .length = SZ_4K, 125 .length = SZ_4K,
123 .type = MT_DEVICE 126 .type = MT_DEVICE
124 }, { 127 }, {
@@ -334,14 +337,163 @@ static void __init ap_init(void)
334 } 337 }
335} 338}
336 339
340/*
341 * Where is the timer (VA)?
342 */
343#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
344#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
345#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
346
347/*
348 * How long is the timer interval?
349 */
350#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
351#if TIMER_INTERVAL >= 0x100000
352#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
353#elif TIMER_INTERVAL >= 0x10000
354#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
355#else
356#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
357#endif
358
359static unsigned long timer_reload;
360
361static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
362
363static cycle_t timersp_read(struct clocksource *cs)
364{
365 return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
366}
367
368static struct clocksource clocksource_timersp = {
369 .name = "timer2",
370 .rating = 200,
371 .read = timersp_read,
372 .mask = CLOCKSOURCE_MASK(16),
373 .shift = 16,
374 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
375};
376
377static void integrator_clocksource_init(u32 khz)
378{
379 struct clocksource *cs = &clocksource_timersp;
380 void __iomem *base = clksrc_base;
381 u32 ctrl = TIMER_CTRL_ENABLE;
382
383 if (khz >= 1500) {
384 khz /= 16;
385 ctrl = TIMER_CTRL_DIV16;
386 }
387
388 writel(ctrl, base + TIMER_CTRL);
389 writel(0xffff, base + TIMER_LOAD);
390
391 cs->mult = clocksource_khz2mult(khz, cs->shift);
392 clocksource_register(cs);
393}
394
395static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
396
397/*
398 * IRQ handler for the timer
399 */
400static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
401{
402 struct clock_event_device *evt = dev_id;
403
404 /* clear the interrupt */
405 writel(1, clkevt_base + TIMER_INTCLR);
406
407 evt->event_handler(evt);
408
409 return IRQ_HANDLED;
410}
411
412static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
413{
414 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
415
416 BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
417
418 if (mode == CLOCK_EVT_MODE_PERIODIC) {
419 writel(ctrl, clkevt_base + TIMER_CTRL);
420 writel(timer_reload, clkevt_base + TIMER_LOAD);
421 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
422 }
423
424 writel(ctrl, clkevt_base + TIMER_CTRL);
425}
426
427static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
428{
429 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
430
431 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
432 writel(next, clkevt_base + TIMER_LOAD);
433 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
434
435 return 0;
436}
437
438static struct clock_event_device integrator_clockevent = {
439 .name = "timer1",
440 .shift = 34,
441 .features = CLOCK_EVT_FEAT_PERIODIC,
442 .set_mode = clkevt_set_mode,
443 .set_next_event = clkevt_set_next_event,
444 .rating = 300,
445 .cpumask = cpu_all_mask,
446};
447
448static struct irqaction integrator_timer_irq = {
449 .name = "timer",
450 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
451 .handler = integrator_timer_interrupt,
452 .dev_id = &integrator_clockevent,
453};
454
455static void integrator_clockevent_init(u32 khz)
456{
457 struct clock_event_device *evt = &integrator_clockevent;
458 unsigned int ctrl = 0;
459
460 if (khz * 1000 > 0x100000 * HZ) {
461 khz /= 256;
462 ctrl |= TIMER_CTRL_DIV256;
463 } else if (khz * 1000 > 0x10000 * HZ) {
464 khz /= 16;
465 ctrl |= TIMER_CTRL_DIV16;
466 }
467
468 timer_reload = khz * 1000 / HZ;
469 writel(ctrl, clkevt_base + TIMER_CTRL);
470
471 evt->irq = IRQ_TIMERINT1;
472 evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
473 evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
474 evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
475
476 setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
477 clockevents_register_device(evt);
478}
479
480/*
481 * Set up timer(s).
482 */
337static void __init ap_init_timer(void) 483static void __init ap_init_timer(void)
338{ 484{
339 integrator_time_init(1000000 * TICKS_PER_uSEC / HZ, 0); 485 u32 khz = TICKS_PER_uSEC * 1000;
486
487 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
488 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
489 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
490
491 integrator_clocksource_init(khz);
492 integrator_clockevent_init(khz);
340} 493}
341 494
342static struct sys_timer ap_timer = { 495static struct sys_timer ap_timer = {
343 .init = ap_init_timer, 496 .init = ap_init_timer,
344 .offset = integrator_gettimeoffset,
345}; 497};
346 498
347MACHINE_START(INTEGRATOR, "ARM-Integrator") 499MACHINE_START(INTEGRATOR, "ARM-Integrator")
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 15e6cc5a352f..cde57b2b83b5 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -25,10 +25,12 @@
25#include <asm/clkdev.h> 25#include <asm/clkdev.h>
26#include <mach/clkdev.h> 26#include <mach/clkdev.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/platform.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
29#include <asm/setup.h> 30#include <asm/setup.h>
30#include <asm/mach-types.h> 31#include <asm/mach-types.h>
31#include <asm/hardware/icst525.h> 32#include <asm/hardware/arm_timer.h>
33#include <asm/hardware/icst.h>
32 34
33#include <mach/cm.h> 35#include <mach/cm.h>
34#include <mach/lm.h> 36#include <mach/lm.h>
@@ -39,24 +41,20 @@
39#include <asm/mach/map.h> 41#include <asm/mach/map.h>
40#include <asm/mach/time.h> 42#include <asm/mach/time.h>
41 43
42#include "common.h" 44#include <plat/timer-sp.h>
43
44#define INTCP_PA_MMC_BASE 0x1c000000
45#define INTCP_PA_AACI_BASE 0x1d000000
46 45
47#define INTCP_PA_FLASH_BASE 0x24000000 46#define INTCP_PA_FLASH_BASE 0x24000000
48#define INTCP_FLASH_SIZE SZ_32M 47#define INTCP_FLASH_SIZE SZ_32M
49 48
50#define INTCP_PA_CLCD_BASE 0xc0000000 49#define INTCP_PA_CLCD_BASE 0xc0000000
51 50
52#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40 51#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
53#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) 52#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
54#define INTCP_VA_SIC_BASE IO_ADDRESS(0xca000000) 53#define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
55 54
56#define INTCP_PA_ETH_BASE 0xc8000000
57#define INTCP_ETH_SIZE 0x10 55#define INTCP_ETH_SIZE 0x10
58 56
59#define INTCP_VA_CTRL_BASE IO_ADDRESS(0xcb000000) 57#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
60#define INTCP_FLASHPROG 0x04 58#define INTCP_FLASHPROG 0x04
61#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) 59#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
62#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) 60#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
@@ -71,7 +69,9 @@
71 * f1600000 16000000 UART 0 69 * f1600000 16000000 UART 0
72 * f1700000 17000000 UART 1 70 * f1700000 17000000 UART 1
73 * f1a00000 1a000000 Debug LEDs 71 * f1a00000 1a000000 Debug LEDs
74 * f1b00000 1b000000 GPIO 72 * fc900000 c9000000 GPIO
73 * fca00000 ca000000 SIC
74 * fcb00000 cb000000 CP system control
75 */ 75 */
76 76
77static struct map_desc intcp_io_desc[] __initdata = { 77static struct map_desc intcp_io_desc[] __initdata = {
@@ -116,18 +116,18 @@ static struct map_desc intcp_io_desc[] __initdata = {
116 .length = SZ_4K, 116 .length = SZ_4K,
117 .type = MT_DEVICE 117 .type = MT_DEVICE
118 }, { 118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), 119 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), 120 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
121 .length = SZ_4K, 121 .length = SZ_4K,
122 .type = MT_DEVICE 122 .type = MT_DEVICE
123 }, { 123 }, {
124 .virtual = IO_ADDRESS(0xca000000), 124 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
125 .pfn = __phys_to_pfn(0xca000000), 125 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
126 .length = SZ_4K, 126 .length = SZ_4K,
127 .type = MT_DEVICE 127 .type = MT_DEVICE
128 }, { 128 }, {
129 .virtual = IO_ADDRESS(0xcb000000), 129 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
130 .pfn = __phys_to_pfn(0xcb000000), 130 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
131 .length = SZ_4K, 131 .length = SZ_4K,
132 .type = MT_DEVICE 132 .type = MT_DEVICE
133 } 133 }
@@ -266,33 +266,43 @@ static void __init intcp_init_irq(void)
266/* 266/*
267 * Clock handling 267 * Clock handling
268 */ 268 */
269#define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) 269#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
270#define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c) 270#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
271 271
272static const struct icst525_params cp_auxvco_params = { 272static const struct icst_params cp_auxvco_params = {
273 .ref = 24000, 273 .ref = 24000000,
274 .vco_max = 320000, 274 .vco_max = ICST525_VCO_MAX_5V,
275 .vco_min = ICST525_VCO_MIN,
275 .vd_min = 8, 276 .vd_min = 8,
276 .vd_max = 263, 277 .vd_max = 263,
277 .rd_min = 3, 278 .rd_min = 3,
278 .rd_max = 65, 279 .rd_max = 65,
280 .s2div = icst525_s2div,
281 .idx2s = icst525_idx2s,
279}; 282};
280 283
281static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco) 284static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
282{ 285{
283 u32 val; 286 u32 val;
284 287
285 val = readl(CM_AUXOSC) & ~0x7ffff; 288 val = readl(clk->vcoreg) & ~0x7ffff;
286 val |= vco.v | (vco.r << 9) | (vco.s << 16); 289 val |= vco.v | (vco.r << 9) | (vco.s << 16);
287 290
288 writel(0xa05f, CM_LOCK); 291 writel(0xa05f, CM_LOCK);
289 writel(val, CM_AUXOSC); 292 writel(val, clk->vcoreg);
290 writel(0, CM_LOCK); 293 writel(0, CM_LOCK);
291} 294}
292 295
296static const struct clk_ops cp_auxclk_ops = {
297 .round = icst_clk_round,
298 .set = icst_clk_set,
299 .setvco = cp_auxvco_set,
300};
301
293static struct clk cp_auxclk = { 302static struct clk cp_auxclk = {
303 .ops = &cp_auxclk_ops,
294 .params = &cp_auxvco_params, 304 .params = &cp_auxvco_params,
295 .setvco = cp_auxvco_set, 305 .vcoreg = CM_AUXOSC,
296}; 306};
297 307
298static struct clk_lookup cp_lookups[] = { 308static struct clk_lookup cp_lookups[] = {
@@ -363,8 +373,8 @@ static struct platform_device intcp_flash_device = {
363 373
364static struct resource smc91x_resources[] = { 374static struct resource smc91x_resources[] = {
365 [0] = { 375 [0] = {
366 .start = INTCP_PA_ETH_BASE, 376 .start = INTEGRATOR_CP_ETH_BASE,
367 .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1, 377 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
368 .flags = IORESOURCE_MEM, 378 .flags = IORESOURCE_MEM,
369 }, 379 },
370 [1] = { 380 [1] = {
@@ -394,8 +404,8 @@ static struct platform_device *intcp_devs[] __initdata = {
394 */ 404 */
395static unsigned int mmc_status(struct device *dev) 405static unsigned int mmc_status(struct device *dev)
396{ 406{
397 unsigned int status = readl(IO_ADDRESS(0xca000000) + 4); 407 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
398 writel(8, IO_ADDRESS(0xcb000000) + 8); 408 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
399 409
400 return status & 8; 410 return status & 8;
401} 411}
@@ -413,8 +423,8 @@ static struct amba_device mmc_device = {
413 .platform_data = &mmc_data, 423 .platform_data = &mmc_data,
414 }, 424 },
415 .res = { 425 .res = {
416 .start = INTCP_PA_MMC_BASE, 426 .start = INTEGRATOR_CP_MMC_BASE,
417 .end = INTCP_PA_MMC_BASE + SZ_4K - 1, 427 .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
418 .flags = IORESOURCE_MEM, 428 .flags = IORESOURCE_MEM,
419 }, 429 },
420 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }, 430 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
@@ -426,8 +436,8 @@ static struct amba_device aaci_device = {
426 .init_name = "mb:1d", 436 .init_name = "mb:1d",
427 }, 437 },
428 .res = { 438 .res = {
429 .start = INTCP_PA_AACI_BASE, 439 .start = INTEGRATOR_CP_AACI_BASE,
430 .end = INTCP_PA_AACI_BASE + SZ_4K - 1, 440 .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
431 .flags = IORESOURCE_MEM, 441 .flags = IORESOURCE_MEM,
432 }, 442 },
433 .irq = { IRQ_CP_AACIINT, NO_IRQ }, 443 .irq = { IRQ_CP_AACIINT, NO_IRQ },
@@ -567,16 +577,22 @@ static void __init intcp_init(void)
567 } 577 }
568} 578}
569 579
570#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */ 580#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
581#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
582#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
571 583
572static void __init intcp_timer_init(void) 584static void __init intcp_timer_init(void)
573{ 585{
574 integrator_time_init(1000000 / HZ, TIMER_CTRL_IE); 586 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
587 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
588 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
589
590 sp804_clocksource_init(TIMER2_VA_BASE);
591 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
575} 592}
576 593
577static struct sys_timer cp_timer = { 594static struct sys_timer cp_timer = {
578 .init = intcp_timer_init, 595 .init = intcp_timer_init,
579 .offset = integrator_gettimeoffset,
580}; 596};
581 597
582MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") 598MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 8dcc823f4135..28be186adb89 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -27,6 +27,7 @@
27#include <linux/io.h> 27#include <linux/io.h>
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/platform.h>
30#include <asm/leds.h> 31#include <asm/leds.h>
31#include <asm/system.h> 32#include <asm/system.h>
32#include <asm/mach-types.h> 33#include <asm/mach-types.h>
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index ffbd349363af..9cef0590d5aa 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -29,6 +29,7 @@
29#include <linux/io.h> 29#include <linux/io.h>
30 30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <mach/platform.h>
32#include <asm/irq.h> 33#include <asm/irq.h>
33#include <asm/signal.h> 34#include <asm/signal.h>
34#include <asm/system.h> 35#include <asm/system.h>
@@ -389,9 +390,9 @@ static int __init pci_v3_setup_resources(struct resource **resource)
389 * means I can't get additional information on the reason for the pm2fb 390 * means I can't get additional information on the reason for the pm2fb
390 * problems. I suppose I'll just have to mind-meld with the machine. ;) 391 * problems. I suppose I'll just have to mind-meld with the machine. ;)
391 */ 392 */
392#define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET) 393#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
393#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20) 394#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
394#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24) 395#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
395 396
396static int 397static int
397v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 398v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 08:28:07 -0500