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-rw-r--r--arch/arm/mach-integrator/integrator_cp.c88
1 files changed, 52 insertions, 36 deletions
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 15e6cc5a352f..cde57b2b83b5 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -25,10 +25,12 @@
25#include <asm/clkdev.h> 25#include <asm/clkdev.h>
26#include <mach/clkdev.h> 26#include <mach/clkdev.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/platform.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
29#include <asm/setup.h> 30#include <asm/setup.h>
30#include <asm/mach-types.h> 31#include <asm/mach-types.h>
31#include <asm/hardware/icst525.h> 32#include <asm/hardware/arm_timer.h>
33#include <asm/hardware/icst.h>
32 34
33#include <mach/cm.h> 35#include <mach/cm.h>
34#include <mach/lm.h> 36#include <mach/lm.h>
@@ -39,24 +41,20 @@
39#include <asm/mach/map.h> 41#include <asm/mach/map.h>
40#include <asm/mach/time.h> 42#include <asm/mach/time.h>
41 43
42#include "common.h" 44#include <plat/timer-sp.h>
43
44#define INTCP_PA_MMC_BASE 0x1c000000
45#define INTCP_PA_AACI_BASE 0x1d000000
46 45
47#define INTCP_PA_FLASH_BASE 0x24000000 46#define INTCP_PA_FLASH_BASE 0x24000000
48#define INTCP_FLASH_SIZE SZ_32M 47#define INTCP_FLASH_SIZE SZ_32M
49 48
50#define INTCP_PA_CLCD_BASE 0xc0000000 49#define INTCP_PA_CLCD_BASE 0xc0000000
51 50
52#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40 51#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
53#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) 52#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
54#define INTCP_VA_SIC_BASE IO_ADDRESS(0xca000000) 53#define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
55 54
56#define INTCP_PA_ETH_BASE 0xc8000000
57#define INTCP_ETH_SIZE 0x10 55#define INTCP_ETH_SIZE 0x10
58 56
59#define INTCP_VA_CTRL_BASE IO_ADDRESS(0xcb000000) 57#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
60#define INTCP_FLASHPROG 0x04 58#define INTCP_FLASHPROG 0x04
61#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) 59#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
62#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) 60#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
@@ -71,7 +69,9 @@
71 * f1600000 16000000 UART 0 69 * f1600000 16000000 UART 0
72 * f1700000 17000000 UART 1 70 * f1700000 17000000 UART 1
73 * f1a00000 1a000000 Debug LEDs 71 * f1a00000 1a000000 Debug LEDs
74 * f1b00000 1b000000 GPIO 72 * fc900000 c9000000 GPIO
73 * fca00000 ca000000 SIC
74 * fcb00000 cb000000 CP system control
75 */ 75 */
76 76
77static struct map_desc intcp_io_desc[] __initdata = { 77static struct map_desc intcp_io_desc[] __initdata = {
@@ -116,18 +116,18 @@ static struct map_desc intcp_io_desc[] __initdata = {
116 .length = SZ_4K, 116 .length = SZ_4K,
117 .type = MT_DEVICE 117 .type = MT_DEVICE
118 }, { 118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), 119 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), 120 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
121 .length = SZ_4K, 121 .length = SZ_4K,
122 .type = MT_DEVICE 122 .type = MT_DEVICE
123 }, { 123 }, {
124 .virtual = IO_ADDRESS(0xca000000), 124 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
125 .pfn = __phys_to_pfn(0xca000000), 125 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
126 .length = SZ_4K, 126 .length = SZ_4K,
127 .type = MT_DEVICE 127 .type = MT_DEVICE
128 }, { 128 }, {
129 .virtual = IO_ADDRESS(0xcb000000), 129 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
130 .pfn = __phys_to_pfn(0xcb000000), 130 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
131 .length = SZ_4K, 131 .length = SZ_4K,
132 .type = MT_DEVICE 132 .type = MT_DEVICE
133 } 133 }
@@ -266,33 +266,43 @@ static void __init intcp_init_irq(void)
266/* 266/*
267 * Clock handling 267 * Clock handling
268 */ 268 */
269#define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) 269#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
270#define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c) 270#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
271 271
272static const struct icst525_params cp_auxvco_params = { 272static const struct icst_params cp_auxvco_params = {
273 .ref = 24000, 273 .ref = 24000000,
274 .vco_max = 320000, 274 .vco_max = ICST525_VCO_MAX_5V,
275 .vco_min = ICST525_VCO_MIN,
275 .vd_min = 8, 276 .vd_min = 8,
276 .vd_max = 263, 277 .vd_max = 263,
277 .rd_min = 3, 278 .rd_min = 3,
278 .rd_max = 65, 279 .rd_max = 65,
280 .s2div = icst525_s2div,
281 .idx2s = icst525_idx2s,
279}; 282};
280 283
281static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco) 284static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
282{ 285{
283 u32 val; 286 u32 val;
284 287
285 val = readl(CM_AUXOSC) & ~0x7ffff; 288 val = readl(clk->vcoreg) & ~0x7ffff;
286 val |= vco.v | (vco.r << 9) | (vco.s << 16); 289 val |= vco.v | (vco.r << 9) | (vco.s << 16);
287 290
288 writel(0xa05f, CM_LOCK); 291 writel(0xa05f, CM_LOCK);
289 writel(val, CM_AUXOSC); 292 writel(val, clk->vcoreg);
290 writel(0, CM_LOCK); 293 writel(0, CM_LOCK);
291} 294}
292 295
296static const struct clk_ops cp_auxclk_ops = {
297 .round = icst_clk_round,
298 .set = icst_clk_set,
299 .setvco = cp_auxvco_set,
300};
301
293static struct clk cp_auxclk = { 302static struct clk cp_auxclk = {
303 .ops = &cp_auxclk_ops,
294 .params = &cp_auxvco_params, 304 .params = &cp_auxvco_params,
295 .setvco = cp_auxvco_set, 305 .vcoreg = CM_AUXOSC,
296}; 306};
297 307
298static struct clk_lookup cp_lookups[] = { 308static struct clk_lookup cp_lookups[] = {
@@ -363,8 +373,8 @@ static struct platform_device intcp_flash_device = {
363 373
364static struct resource smc91x_resources[] = { 374static struct resource smc91x_resources[] = {
365 [0] = { 375 [0] = {
366 .start = INTCP_PA_ETH_BASE, 376 .start = INTEGRATOR_CP_ETH_BASE,
367 .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1, 377 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
368 .flags = IORESOURCE_MEM, 378 .flags = IORESOURCE_MEM,
369 }, 379 },
370 [1] = { 380 [1] = {
@@ -394,8 +404,8 @@ static struct platform_device *intcp_devs[] __initdata = {
394 */ 404 */
395static unsigned int mmc_status(struct device *dev) 405static unsigned int mmc_status(struct device *dev)
396{ 406{
397 unsigned int status = readl(IO_ADDRESS(0xca000000) + 4); 407 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
398 writel(8, IO_ADDRESS(0xcb000000) + 8); 408 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
399 409
400 return status & 8; 410 return status & 8;
401} 411}
@@ -413,8 +423,8 @@ static struct amba_device mmc_device = {
413 .platform_data = &mmc_data, 423 .platform_data = &mmc_data,
414 }, 424 },
415 .res = { 425 .res = {
416 .start = INTCP_PA_MMC_BASE, 426 .start = INTEGRATOR_CP_MMC_BASE,
417 .end = INTCP_PA_MMC_BASE + SZ_4K - 1, 427 .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
418 .flags = IORESOURCE_MEM, 428 .flags = IORESOURCE_MEM,
419 }, 429 },
420 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }, 430 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
@@ -426,8 +436,8 @@ static struct amba_device aaci_device = {
426 .init_name = "mb:1d", 436 .init_name = "mb:1d",
427 }, 437 },
428 .res = { 438 .res = {
429 .start = INTCP_PA_AACI_BASE, 439 .start = INTEGRATOR_CP_AACI_BASE,
430 .end = INTCP_PA_AACI_BASE + SZ_4K - 1, 440 .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
431 .flags = IORESOURCE_MEM, 441 .flags = IORESOURCE_MEM,
432 }, 442 },
433 .irq = { IRQ_CP_AACIINT, NO_IRQ }, 443 .irq = { IRQ_CP_AACIINT, NO_IRQ },
@@ -567,16 +577,22 @@ static void __init intcp_init(void)
567 } 577 }
568} 578}
569 579
570#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */ 580#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
581#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
582#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
571 583
572static void __init intcp_timer_init(void) 584static void __init intcp_timer_init(void)
573{ 585{
574 integrator_time_init(1000000 / HZ, TIMER_CTRL_IE); 586 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
587 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
588 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
589
590 sp804_clocksource_init(TIMER2_VA_BASE);
591 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
575} 592}
576 593
577static struct sys_timer cp_timer = { 594static struct sys_timer cp_timer = {
578 .init = intcp_timer_init, 595 .init = intcp_timer_init,
579 .offset = integrator_gettimeoffset,
580}; 596};
581 597
582MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") 598MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")