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Diffstat (limited to 'arch/arm/mach-imx/time.c')
-rw-r--r--arch/arm/mach-imx/time.c55
1 files changed, 37 insertions, 18 deletions
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bed081e58262..bf92e5a351c0 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -290,25 +290,20 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
290 return 0; 290 return 0;
291} 291}
292 292
293void __init mxc_timer_init(void __iomem *base, int irq) 293static void __init _mxc_timer_init(int irq,
294 struct clk *clk_per, struct clk *clk_ipg)
294{ 295{
295 uint32_t tctl_val; 296 uint32_t tctl_val;
296 struct clk *timer_clk;
297 struct clk *timer_ipg_clk;
298 297
299 timer_clk = clk_get_sys("imx-gpt.0", "per"); 298 if (IS_ERR(clk_per)) {
300 if (IS_ERR(timer_clk)) {
301 pr_err("i.MX timer: unable to get clk\n"); 299 pr_err("i.MX timer: unable to get clk\n");
302 return; 300 return;
303 } 301 }
304 302
305 timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg"); 303 if (!IS_ERR(clk_ipg))
306 if (!IS_ERR(timer_ipg_clk)) 304 clk_prepare_enable(clk_ipg);
307 clk_prepare_enable(timer_ipg_clk);
308
309 clk_prepare_enable(timer_clk);
310 305
311 timer_base = base; 306 clk_prepare_enable(clk_per);
312 307
313 /* 308 /*
314 * Initialise to a known state (all timers off, and timing reset) 309 * Initialise to a known state (all timers off, and timing reset)
@@ -325,21 +320,45 @@ void __init mxc_timer_init(void __iomem *base, int irq)
325 __raw_writel(tctl_val, timer_base + MXC_TCTL); 320 __raw_writel(tctl_val, timer_base + MXC_TCTL);
326 321
327 /* init and register the timer to the framework */ 322 /* init and register the timer to the framework */
328 mxc_clocksource_init(timer_clk); 323 mxc_clocksource_init(clk_per);
329 mxc_clockevent_init(timer_clk); 324 mxc_clockevent_init(clk_per);
330 325
331 /* Make irqs happen */ 326 /* Make irqs happen */
332 setup_irq(irq, &mxc_timer_irq); 327 setup_irq(irq, &mxc_timer_irq);
333} 328}
334 329
335void __init mxc_timer_init_dt(struct device_node *np) 330void __init mxc_timer_init(void __iomem *base, int irq)
336{ 331{
337 void __iomem *base; 332 struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
333 struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
334
335 timer_base = base;
336
337 _mxc_timer_init(irq, clk_per, clk_ipg);
338}
339
340static void __init mxc_timer_init_dt(struct device_node *np)
341{
342 struct clk *clk_per, *clk_ipg;
338 int irq; 343 int irq;
339 344
340 base = of_iomap(np, 0); 345 if (timer_base)
341 WARN_ON(!base); 346 return;
347
348 timer_base = of_iomap(np, 0);
349 WARN_ON(!timer_base);
342 irq = irq_of_parse_and_map(np, 0); 350 irq = irq_of_parse_and_map(np, 0);
343 351
344 mxc_timer_init(base, irq); 352 clk_per = of_clk_get_by_name(np, "per");
353 clk_ipg = of_clk_get_by_name(np, "ipg");
354
355 _mxc_timer_init(irq, clk_per, clk_ipg);
345} 356}
357CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
358CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
359CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
360CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
361CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
362CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
363CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
364CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);