Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...

1 files changed, 37 insertions, 18 deletions

diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index bed081e58262..bf92e5a351c0 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -290,25 +290,20 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxc_timer_init(void __iomem *base, int irq)
+static void __init _mxc_timer_init(int irq,
+                                   struct clk *clk_per, struct clk *clk_ipg)
 {
         uint32_t tctl_val;
-        struct clk *timer_clk;
-        struct clk *timer_ipg_clk;
 
-        timer_clk = clk_get_sys("imx-gpt.0", "per");
-        if (IS_ERR(timer_clk)) {
+        if (IS_ERR(clk_per)) {
                 pr_err("i.MX timer: unable to get clk\n");
                 return;
         }
 
-        timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
-        if (!IS_ERR(timer_ipg_clk))
-                clk_prepare_enable(timer_ipg_clk);
-
-        clk_prepare_enable(timer_clk);
+        if (!IS_ERR(clk_ipg))
+                clk_prepare_enable(clk_ipg);
 
-        timer_base = base;
+        clk_prepare_enable(clk_per);
 
         /*
          * Initialise to a known state (all timers off, and timing reset)
@@ -325,21 +320,45 @@ void __init mxc_timer_init(void __iomem *base, int irq)
         __raw_writel(tctl_val, timer_base + MXC_TCTL);
 
         /* init and register the timer to the framework */
-        mxc_clocksource_init(timer_clk);
-        mxc_clockevent_init(timer_clk);
+        mxc_clocksource_init(clk_per);
+        mxc_clockevent_init(clk_per);
 
         /* Make irqs happen */
         setup_irq(irq, &mxc_timer_irq);
 }
 
-void __init mxc_timer_init_dt(struct device_node *np)
+void __init mxc_timer_init(void __iomem *base, int irq)
 {
-        void __iomem *base;
+        struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
+        struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
+
+        timer_base = base;
+
+        _mxc_timer_init(irq, clk_per, clk_ipg);
+}
+
+static void __init mxc_timer_init_dt(struct device_node *np)
+{
+        struct clk *clk_per, *clk_ipg;
         int irq;
 
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
+        if (timer_base)
+                return;
+
+        timer_base = of_iomap(np, 0);
+        WARN_ON(!timer_base);
         irq = irq_of_parse_and_map(np, 0);
 
-        mxc_timer_init(base, irq);
+        clk_per = of_clk_get_by_name(np, "per");
+        clk_ipg = of_clk_get_by_name(np, "ipg");
+
+        _mxc_timer_init(irq, clk_per, clk_ipg);
 }
+CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
+CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);